1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
526 unsigned writeback
: 1; /* Operand has trailing ! */
527 unsigned preind
: 1; /* Preindexed address. */
528 unsigned postind
: 1; /* Postindexed address. */
529 unsigned negative
: 1; /* Index register was negated. */
530 unsigned shifted
: 1; /* Shift applied to operation. */
531 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
532 } operands
[ARM_IT_MAX_OPERANDS
];
535 static struct arm_it inst
;
537 #define NUM_FLOAT_VALS 8
539 const char * fp_const
[] =
541 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
544 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
554 #define CP_T_X 0x00008000
555 #define CP_T_Y 0x00400000
557 #define CONDS_BIT 0x00100000
558 #define LOAD_BIT 0x00100000
560 #define DOUBLE_LOAD_FLAG 0x00000001
564 const char * template_name
;
568 #define COND_ALWAYS 0xE
572 const char * template_name
;
576 struct asm_barrier_opt
578 const char * template_name
;
580 const arm_feature_set arch
;
583 /* The bit that distinguishes CPSR and SPSR. */
584 #define SPSR_BIT (1 << 22)
586 /* The individual PSR flag bits. */
587 #define PSR_c (1 << 16)
588 #define PSR_x (1 << 17)
589 #define PSR_s (1 << 18)
590 #define PSR_f (1 << 19)
595 bfd_reloc_code_real_type reloc
;
600 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
601 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
606 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
609 /* Bits for DEFINED field in neon_typed_alias. */
610 #define NTA_HASTYPE 1
611 #define NTA_HASINDEX 2
613 struct neon_typed_alias
615 unsigned char defined
;
617 struct neon_type_el eltype
;
620 /* ARM register categories. This includes coprocessor numbers and various
621 architecture extensions' registers. Each entry should have an error message
622 in reg_expected_msgs below. */
651 /* Structure for a hash table entry for a register.
652 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
653 information which states whether a vector type or index is specified (for a
654 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
660 unsigned char builtin
;
661 struct neon_typed_alias
* neon
;
664 /* Diagnostics used when we don't get a register of the expected type. */
665 const char * const reg_expected_msgs
[] =
667 [REG_TYPE_RN
] = N_("ARM register expected"),
668 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
669 [REG_TYPE_CN
] = N_("co-processor register expected"),
670 [REG_TYPE_FN
] = N_("FPA register expected"),
671 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
672 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
673 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
674 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
675 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
676 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
677 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
679 [REG_TYPE_VFC
] = N_("VFP system register expected"),
680 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
681 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
682 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
683 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
684 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
685 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
686 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
687 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
688 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
689 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
690 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
691 [REG_TYPE_RNB
] = N_("")
694 /* Some well known registers that we refer to directly elsewhere. */
700 /* ARM instructions take 4bytes in the object file, Thumb instructions
706 /* Basic string to match. */
707 const char * template_name
;
709 /* Parameters to instruction. */
710 unsigned int operands
[8];
712 /* Conditional tag - see opcode_lookup. */
713 unsigned int tag
: 4;
715 /* Basic instruction code. */
718 /* Thumb-format instruction code. */
721 /* Which architecture variant provides this instruction. */
722 const arm_feature_set
* avariant
;
723 const arm_feature_set
* tvariant
;
725 /* Function to call to encode instruction in ARM format. */
726 void (* aencode
) (void);
728 /* Function to call to encode instruction in Thumb format. */
729 void (* tencode
) (void);
731 /* Indicates whether this instruction may be vector predicated. */
732 unsigned int mayBeVecPred
: 1;
735 /* Defines for various bits that we will want to toggle. */
736 #define INST_IMMEDIATE 0x02000000
737 #define OFFSET_REG 0x02000000
738 #define HWOFFSET_IMM 0x00400000
739 #define SHIFT_BY_REG 0x00000010
740 #define PRE_INDEX 0x01000000
741 #define INDEX_UP 0x00800000
742 #define WRITE_BACK 0x00200000
743 #define LDM_TYPE_2_OR_3 0x00400000
744 #define CPSI_MMOD 0x00020000
746 #define LITERAL_MASK 0xf000f000
747 #define OPCODE_MASK 0xfe1fffff
748 #define V4_STR_BIT 0x00000020
749 #define VLDR_VMOV_SAME 0x0040f000
751 #define T2_SUBS_PC_LR 0xf3de8f00
753 #define DATA_OP_SHIFT 21
754 #define SBIT_SHIFT 20
756 #define T2_OPCODE_MASK 0xfe1fffff
757 #define T2_DATA_OP_SHIFT 21
758 #define T2_SBIT_SHIFT 20
760 #define A_COND_MASK 0xf0000000
761 #define A_PUSH_POP_OP_MASK 0x0fff0000
763 /* Opcodes for pushing/poping registers to/from the stack. */
764 #define A1_OPCODE_PUSH 0x092d0000
765 #define A2_OPCODE_PUSH 0x052d0004
766 #define A2_OPCODE_POP 0x049d0004
768 /* Codes to distinguish the arithmetic instructions. */
779 #define OPCODE_CMP 10
780 #define OPCODE_CMN 11
781 #define OPCODE_ORR 12
782 #define OPCODE_MOV 13
783 #define OPCODE_BIC 14
784 #define OPCODE_MVN 15
786 #define T2_OPCODE_AND 0
787 #define T2_OPCODE_BIC 1
788 #define T2_OPCODE_ORR 2
789 #define T2_OPCODE_ORN 3
790 #define T2_OPCODE_EOR 4
791 #define T2_OPCODE_ADD 8
792 #define T2_OPCODE_ADC 10
793 #define T2_OPCODE_SBC 11
794 #define T2_OPCODE_SUB 13
795 #define T2_OPCODE_RSB 14
797 #define T_OPCODE_MUL 0x4340
798 #define T_OPCODE_TST 0x4200
799 #define T_OPCODE_CMN 0x42c0
800 #define T_OPCODE_NEG 0x4240
801 #define T_OPCODE_MVN 0x43c0
803 #define T_OPCODE_ADD_R3 0x1800
804 #define T_OPCODE_SUB_R3 0x1a00
805 #define T_OPCODE_ADD_HI 0x4400
806 #define T_OPCODE_ADD_ST 0xb000
807 #define T_OPCODE_SUB_ST 0xb080
808 #define T_OPCODE_ADD_SP 0xa800
809 #define T_OPCODE_ADD_PC 0xa000
810 #define T_OPCODE_ADD_I8 0x3000
811 #define T_OPCODE_SUB_I8 0x3800
812 #define T_OPCODE_ADD_I3 0x1c00
813 #define T_OPCODE_SUB_I3 0x1e00
815 #define T_OPCODE_ASR_R 0x4100
816 #define T_OPCODE_LSL_R 0x4080
817 #define T_OPCODE_LSR_R 0x40c0
818 #define T_OPCODE_ROR_R 0x41c0
819 #define T_OPCODE_ASR_I 0x1000
820 #define T_OPCODE_LSL_I 0x0000
821 #define T_OPCODE_LSR_I 0x0800
823 #define T_OPCODE_MOV_I8 0x2000
824 #define T_OPCODE_CMP_I8 0x2800
825 #define T_OPCODE_CMP_LR 0x4280
826 #define T_OPCODE_MOV_HR 0x4600
827 #define T_OPCODE_CMP_HR 0x4500
829 #define T_OPCODE_LDR_PC 0x4800
830 #define T_OPCODE_LDR_SP 0x9800
831 #define T_OPCODE_STR_SP 0x9000
832 #define T_OPCODE_LDR_IW 0x6800
833 #define T_OPCODE_STR_IW 0x6000
834 #define T_OPCODE_LDR_IH 0x8800
835 #define T_OPCODE_STR_IH 0x8000
836 #define T_OPCODE_LDR_IB 0x7800
837 #define T_OPCODE_STR_IB 0x7000
838 #define T_OPCODE_LDR_RW 0x5800
839 #define T_OPCODE_STR_RW 0x5000
840 #define T_OPCODE_LDR_RH 0x5a00
841 #define T_OPCODE_STR_RH 0x5200
842 #define T_OPCODE_LDR_RB 0x5c00
843 #define T_OPCODE_STR_RB 0x5400
845 #define T_OPCODE_PUSH 0xb400
846 #define T_OPCODE_POP 0xbc00
848 #define T_OPCODE_BRANCH 0xe000
850 #define THUMB_SIZE 2 /* Size of thumb instruction. */
851 #define THUMB_PP_PC_LR 0x0100
852 #define THUMB_LOAD_BIT 0x0800
853 #define THUMB2_LOAD_BIT 0x00100000
855 #define BAD_SYNTAX _("syntax error")
856 #define BAD_ARGS _("bad arguments to instruction")
857 #define BAD_SP _("r13 not allowed here")
858 #define BAD_PC _("r15 not allowed here")
859 #define BAD_ODD _("Odd register not allowed here")
860 #define BAD_EVEN _("Even register not allowed here")
861 #define BAD_COND _("instruction cannot be conditional")
862 #define BAD_OVERLAP _("registers may not be the same")
863 #define BAD_HIREG _("lo register required")
864 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
865 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
866 #define BAD_BRANCH _("branch must be last instruction in IT block")
867 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
868 #define BAD_NOT_IT _("instruction not allowed in IT block")
869 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
870 #define BAD_FPU _("selected FPU does not support instruction")
871 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
872 #define BAD_OUT_VPT \
873 _("vector predicated instruction should be in VPT/VPST block")
874 #define BAD_IT_COND _("incorrect condition in IT block")
875 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
876 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
877 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
878 #define BAD_PC_ADDRESSING \
879 _("cannot use register index with PC-relative addressing")
880 #define BAD_PC_WRITEBACK \
881 _("cannot use writeback with PC-relative addressing")
882 #define BAD_RANGE _("branch out of range")
883 #define BAD_FP16 _("selected processor does not support fp16 instruction")
884 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
885 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
886 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
888 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
890 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
892 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
894 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
895 #define BAD_MVE_AUTO \
896 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
897 " use a valid -march or -mcpu option.")
898 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
899 "and source operands makes instruction UNPREDICTABLE")
900 #define BAD_EL_TYPE _("bad element type for instruction")
902 static struct hash_control
* arm_ops_hsh
;
903 static struct hash_control
* arm_cond_hsh
;
904 static struct hash_control
* arm_vcond_hsh
;
905 static struct hash_control
* arm_shift_hsh
;
906 static struct hash_control
* arm_psr_hsh
;
907 static struct hash_control
* arm_v7m_psr_hsh
;
908 static struct hash_control
* arm_reg_hsh
;
909 static struct hash_control
* arm_reloc_hsh
;
910 static struct hash_control
* arm_barrier_opt_hsh
;
912 /* Stuff needed to resolve the label ambiguity
921 symbolS
* last_label_seen
;
922 static int label_is_thumb_function_name
= FALSE
;
924 /* Literal pool structure. Held on a per-section
925 and per-sub-section basis. */
927 #define MAX_LITERAL_POOL_SIZE 1024
928 typedef struct literal_pool
930 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
931 unsigned int next_free_entry
;
937 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
939 struct literal_pool
* next
;
940 unsigned int alignment
;
943 /* Pointer to a linked list of literal pools. */
944 literal_pool
* list_of_pools
= NULL
;
946 typedef enum asmfunc_states
949 WAITING_ASMFUNC_NAME
,
953 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
956 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
958 static struct current_pred now_pred
;
962 now_pred_compatible (int cond
)
964 return (cond
& ~1) == (now_pred
.cc
& ~1);
968 conditional_insn (void)
970 return inst
.cond
!= COND_ALWAYS
;
973 static int in_pred_block (void);
975 static int handle_pred_state (void);
977 static void force_automatic_it_block_close (void);
979 static void it_fsm_post_encode (void);
981 #define set_pred_insn_type(type) \
984 inst.pred_insn_type = type; \
985 if (handle_pred_state () == FAIL) \
990 #define set_pred_insn_type_nonvoid(type, failret) \
993 inst.pred_insn_type = type; \
994 if (handle_pred_state () == FAIL) \
999 #define set_pred_insn_type_last() \
1002 if (inst.cond == COND_ALWAYS) \
1003 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1005 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1011 /* This array holds the chars that always start a comment. If the
1012 pre-processor is disabled, these aren't very useful. */
1013 char arm_comment_chars
[] = "@";
1015 /* This array holds the chars that only start a comment at the beginning of
1016 a line. If the line seems to have the form '# 123 filename'
1017 .line and .file directives will appear in the pre-processed output. */
1018 /* Note that input_file.c hand checks for '#' at the beginning of the
1019 first line of the input file. This is because the compiler outputs
1020 #NO_APP at the beginning of its output. */
1021 /* Also note that comments like this one will always work. */
1022 const char line_comment_chars
[] = "#";
1024 char arm_line_separator_chars
[] = ";";
1026 /* Chars that can be used to separate mant
1027 from exp in floating point numbers. */
1028 const char EXP_CHARS
[] = "eE";
1030 /* Chars that mean this number is a floating point constant. */
1031 /* As in 0f12.456 */
1032 /* or 0d1.2345e12 */
1034 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1036 /* Prefix characters that indicate the start of an immediate
1038 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1040 /* Separator character handling. */
1042 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1045 skip_past_char (char ** str
, char c
)
1047 /* PR gas/14987: Allow for whitespace before the expected character. */
1048 skip_whitespace (*str
);
1059 #define skip_past_comma(str) skip_past_char (str, ',')
1061 /* Arithmetic expressions (possibly involving symbols). */
1063 /* Return TRUE if anything in the expression is a bignum. */
1066 walk_no_bignums (symbolS
* sp
)
1068 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1071 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1073 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1074 || (symbol_get_value_expression (sp
)->X_op_symbol
1075 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1081 static bfd_boolean in_my_get_expression
= FALSE
;
1083 /* Third argument to my_get_expression. */
1084 #define GE_NO_PREFIX 0
1085 #define GE_IMM_PREFIX 1
1086 #define GE_OPT_PREFIX 2
1087 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1088 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1089 #define GE_OPT_PREFIX_BIG 3
1092 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1096 /* In unified syntax, all prefixes are optional. */
1098 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1101 switch (prefix_mode
)
1103 case GE_NO_PREFIX
: break;
1105 if (!is_immediate_prefix (**str
))
1107 inst
.error
= _("immediate expression requires a # prefix");
1113 case GE_OPT_PREFIX_BIG
:
1114 if (is_immediate_prefix (**str
))
1121 memset (ep
, 0, sizeof (expressionS
));
1123 save_in
= input_line_pointer
;
1124 input_line_pointer
= *str
;
1125 in_my_get_expression
= TRUE
;
1127 in_my_get_expression
= FALSE
;
1129 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1131 /* We found a bad or missing expression in md_operand(). */
1132 *str
= input_line_pointer
;
1133 input_line_pointer
= save_in
;
1134 if (inst
.error
== NULL
)
1135 inst
.error
= (ep
->X_op
== O_absent
1136 ? _("missing expression") :_("bad expression"));
1140 /* Get rid of any bignums now, so that we don't generate an error for which
1141 we can't establish a line number later on. Big numbers are never valid
1142 in instructions, which is where this routine is always called. */
1143 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1144 && (ep
->X_op
== O_big
1145 || (ep
->X_add_symbol
1146 && (walk_no_bignums (ep
->X_add_symbol
)
1148 && walk_no_bignums (ep
->X_op_symbol
))))))
1150 inst
.error
= _("invalid constant");
1151 *str
= input_line_pointer
;
1152 input_line_pointer
= save_in
;
1156 *str
= input_line_pointer
;
1157 input_line_pointer
= save_in
;
1161 /* Turn a string in input_line_pointer into a floating point constant
1162 of type TYPE, and store the appropriate bytes in *LITP. The number
1163 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1164 returned, or NULL on OK.
1166 Note that fp constants aren't represent in the normal way on the ARM.
1167 In big endian mode, things are as expected. However, in little endian
1168 mode fp constants are big-endian word-wise, and little-endian byte-wise
1169 within the words. For example, (double) 1.1 in big endian mode is
1170 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1171 the byte sequence 99 99 f1 3f 9a 99 99 99.
1173 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1176 md_atof (int type
, char * litP
, int * sizeP
)
1179 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1211 return _("Unrecognized or unsupported floating point constant");
1214 t
= atof_ieee (input_line_pointer
, type
, words
);
1216 input_line_pointer
= t
;
1217 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1219 if (target_big_endian
)
1221 for (i
= 0; i
< prec
; i
++)
1223 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1224 litP
+= sizeof (LITTLENUM_TYPE
);
1229 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1230 for (i
= prec
- 1; i
>= 0; i
--)
1232 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1233 litP
+= sizeof (LITTLENUM_TYPE
);
1236 /* For a 4 byte float the order of elements in `words' is 1 0.
1237 For an 8 byte float the order is 1 0 3 2. */
1238 for (i
= 0; i
< prec
; i
+= 2)
1240 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1241 sizeof (LITTLENUM_TYPE
));
1242 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1243 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1244 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1251 /* We handle all bad expressions here, so that we can report the faulty
1252 instruction in the error message. */
1255 md_operand (expressionS
* exp
)
1257 if (in_my_get_expression
)
1258 exp
->X_op
= O_illegal
;
1261 /* Immediate values. */
1264 /* Generic immediate-value read function for use in directives.
1265 Accepts anything that 'expression' can fold to a constant.
1266 *val receives the number. */
1269 immediate_for_directive (int *val
)
1272 exp
.X_op
= O_illegal
;
1274 if (is_immediate_prefix (*input_line_pointer
))
1276 input_line_pointer
++;
1280 if (exp
.X_op
!= O_constant
)
1282 as_bad (_("expected #constant"));
1283 ignore_rest_of_line ();
1286 *val
= exp
.X_add_number
;
1291 /* Register parsing. */
1293 /* Generic register parser. CCP points to what should be the
1294 beginning of a register name. If it is indeed a valid register
1295 name, advance CCP over it and return the reg_entry structure;
1296 otherwise return NULL. Does not issue diagnostics. */
1298 static struct reg_entry
*
1299 arm_reg_parse_multi (char **ccp
)
1303 struct reg_entry
*reg
;
1305 skip_whitespace (start
);
1307 #ifdef REGISTER_PREFIX
1308 if (*start
!= REGISTER_PREFIX
)
1312 #ifdef OPTIONAL_REGISTER_PREFIX
1313 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1318 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1323 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1325 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1335 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1336 enum arm_reg_type type
)
1338 /* Alternative syntaxes are accepted for a few register classes. */
1345 /* Generic coprocessor register names are allowed for these. */
1346 if (reg
&& reg
->type
== REG_TYPE_CN
)
1351 /* For backward compatibility, a bare number is valid here. */
1353 unsigned long processor
= strtoul (start
, ccp
, 10);
1354 if (*ccp
!= start
&& processor
<= 15)
1359 case REG_TYPE_MMXWC
:
1360 /* WC includes WCG. ??? I'm not sure this is true for all
1361 instructions that take WC registers. */
1362 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1373 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1374 return value is the register number or FAIL. */
1377 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1380 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1383 /* Do not allow a scalar (reg+index) to parse as a register. */
1384 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1387 if (reg
&& reg
->type
== type
)
1390 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1397 /* Parse a Neon type specifier. *STR should point at the leading '.'
1398 character. Does no verification at this stage that the type fits the opcode
1405 Can all be legally parsed by this function.
1407 Fills in neon_type struct pointer with parsed information, and updates STR
1408 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1409 type, FAIL if not. */
1412 parse_neon_type (struct neon_type
*type
, char **str
)
1419 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1421 enum neon_el_type thistype
= NT_untyped
;
1422 unsigned thissize
= -1u;
1429 /* Just a size without an explicit type. */
1433 switch (TOLOWER (*ptr
))
1435 case 'i': thistype
= NT_integer
; break;
1436 case 'f': thistype
= NT_float
; break;
1437 case 'p': thistype
= NT_poly
; break;
1438 case 's': thistype
= NT_signed
; break;
1439 case 'u': thistype
= NT_unsigned
; break;
1441 thistype
= NT_float
;
1446 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1452 /* .f is an abbreviation for .f32. */
1453 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1458 thissize
= strtoul (ptr
, &ptr
, 10);
1460 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1463 as_bad (_("bad size %d in type specifier"), thissize
);
1471 type
->el
[type
->elems
].type
= thistype
;
1472 type
->el
[type
->elems
].size
= thissize
;
1477 /* Empty/missing type is not a successful parse. */
1478 if (type
->elems
== 0)
1486 /* Errors may be set multiple times during parsing or bit encoding
1487 (particularly in the Neon bits), but usually the earliest error which is set
1488 will be the most meaningful. Avoid overwriting it with later (cascading)
1489 errors by calling this function. */
1492 first_error (const char *err
)
1498 /* Parse a single type, e.g. ".s32", leading period included. */
1500 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1503 struct neon_type optype
;
1507 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1509 if (optype
.elems
== 1)
1510 *vectype
= optype
.el
[0];
1513 first_error (_("only one type should be specified for operand"));
1519 first_error (_("vector type expected"));
1531 /* Special meanings for indices (which have a range of 0-7), which will fit into
1534 #define NEON_ALL_LANES 15
1535 #define NEON_INTERLEAVE_LANES 14
1537 /* Record a use of the given feature. */
1539 record_feature_use (const arm_feature_set
*feature
)
1542 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1544 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1547 /* If the given feature available in the selected CPU, mark it as used.
1548 Returns TRUE iff feature is available. */
1550 mark_feature_used (const arm_feature_set
*feature
)
1553 /* Do not support the use of MVE only instructions when in auto-detection or
1555 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1556 && ARM_CPU_IS_ANY (cpu_variant
))
1558 first_error (BAD_MVE_AUTO
);
1561 /* Ensure the option is valid on the current architecture. */
1562 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1565 /* Add the appropriate architecture feature for the barrier option used.
1567 record_feature_use (feature
);
1572 /* Parse either a register or a scalar, with an optional type. Return the
1573 register number, and optionally fill in the actual type of the register
1574 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1575 type/index information in *TYPEINFO. */
1578 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1579 enum arm_reg_type
*rtype
,
1580 struct neon_typed_alias
*typeinfo
)
1583 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1584 struct neon_typed_alias atype
;
1585 struct neon_type_el parsetype
;
1589 atype
.eltype
.type
= NT_invtype
;
1590 atype
.eltype
.size
= -1;
1592 /* Try alternate syntax for some types of register. Note these are mutually
1593 exclusive with the Neon syntax extensions. */
1596 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1604 /* Undo polymorphism when a set of register types may be accepted. */
1605 if ((type
== REG_TYPE_NDQ
1606 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1607 || (type
== REG_TYPE_VFSD
1608 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1609 || (type
== REG_TYPE_NSDQ
1610 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1611 || reg
->type
== REG_TYPE_NQ
))
1612 || (type
== REG_TYPE_NSD
1613 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1614 || (type
== REG_TYPE_MMXWC
1615 && (reg
->type
== REG_TYPE_MMXWCG
)))
1616 type
= (enum arm_reg_type
) reg
->type
;
1618 if (type
== REG_TYPE_MQ
)
1620 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1623 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1626 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1628 first_error (_("expected MVE register [q0..q7]"));
1633 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1634 && (type
== REG_TYPE_NQ
))
1638 if (type
!= reg
->type
)
1644 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1646 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1648 first_error (_("can't redefine type for operand"));
1651 atype
.defined
|= NTA_HASTYPE
;
1652 atype
.eltype
= parsetype
;
1655 if (skip_past_char (&str
, '[') == SUCCESS
)
1657 if (type
!= REG_TYPE_VFD
1658 && !(type
== REG_TYPE_VFS
1659 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1660 && !(type
== REG_TYPE_NQ
1661 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1663 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1664 first_error (_("only D and Q registers may be indexed"));
1666 first_error (_("only D registers may be indexed"));
1670 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1672 first_error (_("can't change index for operand"));
1676 atype
.defined
|= NTA_HASINDEX
;
1678 if (skip_past_char (&str
, ']') == SUCCESS
)
1679 atype
.index
= NEON_ALL_LANES
;
1684 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1686 if (exp
.X_op
!= O_constant
)
1688 first_error (_("constant expression required"));
1692 if (skip_past_char (&str
, ']') == FAIL
)
1695 atype
.index
= exp
.X_add_number
;
1710 /* Like arm_reg_parse, but also allow the following extra features:
1711 - If RTYPE is non-zero, return the (possibly restricted) type of the
1712 register (e.g. Neon double or quad reg when either has been requested).
1713 - If this is a Neon vector type with additional type information, fill
1714 in the struct pointed to by VECTYPE (if non-NULL).
1715 This function will fault on encountering a scalar. */
1718 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1719 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1721 struct neon_typed_alias atype
;
1723 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1728 /* Do not allow regname(... to parse as a register. */
1732 /* Do not allow a scalar (reg+index) to parse as a register. */
1733 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1735 first_error (_("register operand expected, but got scalar"));
1740 *vectype
= atype
.eltype
;
1747 #define NEON_SCALAR_REG(X) ((X) >> 4)
1748 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1750 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1751 have enough information to be able to do a good job bounds-checking. So, we
1752 just do easy checks here, and do further checks later. */
1755 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1756 arm_reg_type reg_type
)
1760 struct neon_typed_alias atype
;
1763 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1781 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1784 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1786 first_error (_("scalar must have an index"));
1789 else if (atype
.index
>= reg_size
/ elsize
)
1791 first_error (_("scalar index out of range"));
1796 *type
= atype
.eltype
;
1800 return reg
* 16 + atype
.index
;
1803 /* Types of registers in a list. */
1816 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1819 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1825 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1827 /* We come back here if we get ranges concatenated by '+' or '|'. */
1830 skip_whitespace (str
);
1843 const char apsr_str
[] = "apsr";
1844 int apsr_str_len
= strlen (apsr_str
);
1846 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1847 if (etype
== REGLIST_CLRM
)
1849 if (reg
== REG_SP
|| reg
== REG_PC
)
1851 else if (reg
== FAIL
1852 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1853 && !ISALPHA (*(str
+ apsr_str_len
)))
1856 str
+= apsr_str_len
;
1861 first_error (_("r0-r12, lr or APSR expected"));
1865 else /* etype == REGLIST_RN. */
1869 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1880 first_error (_("bad range in register list"));
1884 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1886 if (range
& (1 << i
))
1888 (_("Warning: duplicated register (r%d) in register list"),
1896 if (range
& (1 << reg
))
1897 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1899 else if (reg
<= cur_reg
)
1900 as_tsktsk (_("Warning: register range not in ascending order"));
1905 while (skip_past_comma (&str
) != FAIL
1906 || (in_range
= 1, *str
++ == '-'));
1909 if (skip_past_char (&str
, '}') == FAIL
)
1911 first_error (_("missing `}'"));
1915 else if (etype
== REGLIST_RN
)
1919 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1922 if (exp
.X_op
== O_constant
)
1924 if (exp
.X_add_number
1925 != (exp
.X_add_number
& 0x0000ffff))
1927 inst
.error
= _("invalid register mask");
1931 if ((range
& exp
.X_add_number
) != 0)
1933 int regno
= range
& exp
.X_add_number
;
1936 regno
= (1 << regno
) - 1;
1938 (_("Warning: duplicated register (r%d) in register list"),
1942 range
|= exp
.X_add_number
;
1946 if (inst
.relocs
[0].type
!= 0)
1948 inst
.error
= _("expression too complex");
1952 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1953 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1954 inst
.relocs
[0].pc_rel
= 0;
1958 if (*str
== '|' || *str
== '+')
1964 while (another_range
);
1970 /* Parse a VFP register list. If the string is invalid return FAIL.
1971 Otherwise return the number of registers, and set PBASE to the first
1972 register. Parses registers of type ETYPE.
1973 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1974 - Q registers can be used to specify pairs of D registers
1975 - { } can be omitted from around a singleton register list
1976 FIXME: This is not implemented, as it would require backtracking in
1979 This could be done (the meaning isn't really ambiguous), but doesn't
1980 fit in well with the current parsing framework.
1981 - 32 D registers may be used (also true for VFPv3).
1982 FIXME: Types are ignored in these register lists, which is probably a
1986 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1987 bfd_boolean
*partial_match
)
1992 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1996 unsigned long mask
= 0;
1998 bfd_boolean vpr_seen
= FALSE
;
1999 bfd_boolean expect_vpr
=
2000 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2002 if (skip_past_char (&str
, '{') == FAIL
)
2004 inst
.error
= _("expecting {");
2011 case REGLIST_VFP_S_VPR
:
2012 regtype
= REG_TYPE_VFS
;
2017 case REGLIST_VFP_D_VPR
:
2018 regtype
= REG_TYPE_VFD
;
2021 case REGLIST_NEON_D
:
2022 regtype
= REG_TYPE_NDQ
;
2029 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2031 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2032 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2036 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2039 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2046 base_reg
= max_regs
;
2047 *partial_match
= FALSE
;
2051 int setmask
= 1, addregs
= 1;
2052 const char vpr_str
[] = "vpr";
2053 int vpr_str_len
= strlen (vpr_str
);
2055 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2059 if (new_base
== FAIL
2060 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2061 && !ISALPHA (*(str
+ vpr_str_len
))
2067 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2071 first_error (_("VPR expected last"));
2074 else if (new_base
== FAIL
)
2076 if (regtype
== REG_TYPE_VFS
)
2077 first_error (_("VFP single precision register or VPR "
2079 else /* regtype == REG_TYPE_VFD. */
2080 first_error (_("VFP/Neon double precision register or VPR "
2085 else if (new_base
== FAIL
)
2087 first_error (_(reg_expected_msgs
[regtype
]));
2091 *partial_match
= TRUE
;
2095 if (new_base
>= max_regs
)
2097 first_error (_("register out of range in list"));
2101 /* Note: a value of 2 * n is returned for the register Q<n>. */
2102 if (regtype
== REG_TYPE_NQ
)
2108 if (new_base
< base_reg
)
2109 base_reg
= new_base
;
2111 if (mask
& (setmask
<< new_base
))
2113 first_error (_("invalid register list"));
2117 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2119 as_tsktsk (_("register list not in ascending order"));
2123 mask
|= setmask
<< new_base
;
2126 if (*str
== '-') /* We have the start of a range expression */
2132 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2135 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2139 if (high_range
>= max_regs
)
2141 first_error (_("register out of range in list"));
2145 if (regtype
== REG_TYPE_NQ
)
2146 high_range
= high_range
+ 1;
2148 if (high_range
<= new_base
)
2150 inst
.error
= _("register range not in ascending order");
2154 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2156 if (mask
& (setmask
<< new_base
))
2158 inst
.error
= _("invalid register list");
2162 mask
|= setmask
<< new_base
;
2167 while (skip_past_comma (&str
) != FAIL
);
2171 /* Sanity check -- should have raised a parse error above. */
2172 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2177 if (expect_vpr
&& !vpr_seen
)
2179 first_error (_("VPR expected last"));
2183 /* Final test -- the registers must be consecutive. */
2185 for (i
= 0; i
< count
; i
++)
2187 if ((mask
& (1u << i
)) == 0)
2189 inst
.error
= _("non-contiguous register range");
2199 /* True if two alias types are the same. */
2202 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2210 if (a
->defined
!= b
->defined
)
2213 if ((a
->defined
& NTA_HASTYPE
) != 0
2214 && (a
->eltype
.type
!= b
->eltype
.type
2215 || a
->eltype
.size
!= b
->eltype
.size
))
2218 if ((a
->defined
& NTA_HASINDEX
) != 0
2219 && (a
->index
!= b
->index
))
2225 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2226 The base register is put in *PBASE.
2227 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2229 The register stride (minus one) is put in bit 4 of the return value.
2230 Bits [6:5] encode the list length (minus one).
2231 The type of the list elements is put in *ELTYPE, if non-NULL. */
2233 #define NEON_LANE(X) ((X) & 0xf)
2234 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2235 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2238 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2240 struct neon_type_el
*eltype
)
2247 int leading_brace
= 0;
2248 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2249 const char *const incr_error
= mve
? _("register stride must be 1") :
2250 _("register stride must be 1 or 2");
2251 const char *const type_error
= _("mismatched element/structure types in list");
2252 struct neon_typed_alias firsttype
;
2253 firsttype
.defined
= 0;
2254 firsttype
.eltype
.type
= NT_invtype
;
2255 firsttype
.eltype
.size
= -1;
2256 firsttype
.index
= -1;
2258 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2263 struct neon_typed_alias atype
;
2265 rtype
= REG_TYPE_MQ
;
2266 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2270 first_error (_(reg_expected_msgs
[rtype
]));
2277 if (rtype
== REG_TYPE_NQ
)
2283 else if (reg_incr
== -1)
2285 reg_incr
= getreg
- base_reg
;
2286 if (reg_incr
< 1 || reg_incr
> 2)
2288 first_error (_(incr_error
));
2292 else if (getreg
!= base_reg
+ reg_incr
* count
)
2294 first_error (_(incr_error
));
2298 if (! neon_alias_types_same (&atype
, &firsttype
))
2300 first_error (_(type_error
));
2304 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2308 struct neon_typed_alias htype
;
2309 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2311 lane
= NEON_INTERLEAVE_LANES
;
2312 else if (lane
!= NEON_INTERLEAVE_LANES
)
2314 first_error (_(type_error
));
2319 else if (reg_incr
!= 1)
2321 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2325 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2328 first_error (_(reg_expected_msgs
[rtype
]));
2331 if (! neon_alias_types_same (&htype
, &firsttype
))
2333 first_error (_(type_error
));
2336 count
+= hireg
+ dregs
- getreg
;
2340 /* If we're using Q registers, we can't use [] or [n] syntax. */
2341 if (rtype
== REG_TYPE_NQ
)
2347 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2351 else if (lane
!= atype
.index
)
2353 first_error (_(type_error
));
2357 else if (lane
== -1)
2358 lane
= NEON_INTERLEAVE_LANES
;
2359 else if (lane
!= NEON_INTERLEAVE_LANES
)
2361 first_error (_(type_error
));
2366 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2368 /* No lane set by [x]. We must be interleaving structures. */
2370 lane
= NEON_INTERLEAVE_LANES
;
2373 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2374 || (count
> 1 && reg_incr
== -1))
2376 first_error (_("error parsing element/structure list"));
2380 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2382 first_error (_("expected }"));
2390 *eltype
= firsttype
.eltype
;
2395 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2398 /* Parse an explicit relocation suffix on an expression. This is
2399 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2400 arm_reloc_hsh contains no entries, so this function can only
2401 succeed if there is no () after the word. Returns -1 on error,
2402 BFD_RELOC_UNUSED if there wasn't any suffix. */
2405 parse_reloc (char **str
)
2407 struct reloc_entry
*r
;
2411 return BFD_RELOC_UNUSED
;
2416 while (*q
&& *q
!= ')' && *q
!= ',')
2421 if ((r
= (struct reloc_entry
*)
2422 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2429 /* Directives: register aliases. */
2431 static struct reg_entry
*
2432 insert_reg_alias (char *str
, unsigned number
, int type
)
2434 struct reg_entry
*new_reg
;
2437 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2439 if (new_reg
->builtin
)
2440 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2442 /* Only warn about a redefinition if it's not defined as the
2444 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2445 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2450 name
= xstrdup (str
);
2451 new_reg
= XNEW (struct reg_entry
);
2453 new_reg
->name
= name
;
2454 new_reg
->number
= number
;
2455 new_reg
->type
= type
;
2456 new_reg
->builtin
= FALSE
;
2457 new_reg
->neon
= NULL
;
2459 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2466 insert_neon_reg_alias (char *str
, int number
, int type
,
2467 struct neon_typed_alias
*atype
)
2469 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2473 first_error (_("attempt to redefine typed alias"));
2479 reg
->neon
= XNEW (struct neon_typed_alias
);
2480 *reg
->neon
= *atype
;
2484 /* Look for the .req directive. This is of the form:
2486 new_register_name .req existing_register_name
2488 If we find one, or if it looks sufficiently like one that we want to
2489 handle any error here, return TRUE. Otherwise return FALSE. */
2492 create_register_alias (char * newname
, char *p
)
2494 struct reg_entry
*old
;
2495 char *oldname
, *nbuf
;
2498 /* The input scrubber ensures that whitespace after the mnemonic is
2499 collapsed to single spaces. */
2501 if (strncmp (oldname
, " .req ", 6) != 0)
2505 if (*oldname
== '\0')
2508 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2511 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2515 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2516 the desired alias name, and p points to its end. If not, then
2517 the desired alias name is in the global original_case_string. */
2518 #ifdef TC_CASE_SENSITIVE
2521 newname
= original_case_string
;
2522 nlen
= strlen (newname
);
2525 nbuf
= xmemdup0 (newname
, nlen
);
2527 /* Create aliases under the new name as stated; an all-lowercase
2528 version of the new name; and an all-uppercase version of the new
2530 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2532 for (p
= nbuf
; *p
; p
++)
2535 if (strncmp (nbuf
, newname
, nlen
))
2537 /* If this attempt to create an additional alias fails, do not bother
2538 trying to create the all-lower case alias. We will fail and issue
2539 a second, duplicate error message. This situation arises when the
2540 programmer does something like:
2543 The second .req creates the "Foo" alias but then fails to create
2544 the artificial FOO alias because it has already been created by the
2546 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2553 for (p
= nbuf
; *p
; p
++)
2556 if (strncmp (nbuf
, newname
, nlen
))
2557 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2564 /* Create a Neon typed/indexed register alias using directives, e.g.:
2569 These typed registers can be used instead of the types specified after the
2570 Neon mnemonic, so long as all operands given have types. Types can also be
2571 specified directly, e.g.:
2572 vadd d0.s32, d1.s32, d2.s32 */
2575 create_neon_reg_alias (char *newname
, char *p
)
2577 enum arm_reg_type basetype
;
2578 struct reg_entry
*basereg
;
2579 struct reg_entry mybasereg
;
2580 struct neon_type ntype
;
2581 struct neon_typed_alias typeinfo
;
2582 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2585 typeinfo
.defined
= 0;
2586 typeinfo
.eltype
.type
= NT_invtype
;
2587 typeinfo
.eltype
.size
= -1;
2588 typeinfo
.index
= -1;
2592 if (strncmp (p
, " .dn ", 5) == 0)
2593 basetype
= REG_TYPE_VFD
;
2594 else if (strncmp (p
, " .qn ", 5) == 0)
2595 basetype
= REG_TYPE_NQ
;
2604 basereg
= arm_reg_parse_multi (&p
);
2606 if (basereg
&& basereg
->type
!= basetype
)
2608 as_bad (_("bad type for register"));
2612 if (basereg
== NULL
)
2615 /* Try parsing as an integer. */
2616 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2617 if (exp
.X_op
!= O_constant
)
2619 as_bad (_("expression must be constant"));
2622 basereg
= &mybasereg
;
2623 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2629 typeinfo
= *basereg
->neon
;
2631 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2633 /* We got a type. */
2634 if (typeinfo
.defined
& NTA_HASTYPE
)
2636 as_bad (_("can't redefine the type of a register alias"));
2640 typeinfo
.defined
|= NTA_HASTYPE
;
2641 if (ntype
.elems
!= 1)
2643 as_bad (_("you must specify a single type only"));
2646 typeinfo
.eltype
= ntype
.el
[0];
2649 if (skip_past_char (&p
, '[') == SUCCESS
)
2652 /* We got a scalar index. */
2654 if (typeinfo
.defined
& NTA_HASINDEX
)
2656 as_bad (_("can't redefine the index of a scalar alias"));
2660 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2662 if (exp
.X_op
!= O_constant
)
2664 as_bad (_("scalar index must be constant"));
2668 typeinfo
.defined
|= NTA_HASINDEX
;
2669 typeinfo
.index
= exp
.X_add_number
;
2671 if (skip_past_char (&p
, ']') == FAIL
)
2673 as_bad (_("expecting ]"));
2678 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2679 the desired alias name, and p points to its end. If not, then
2680 the desired alias name is in the global original_case_string. */
2681 #ifdef TC_CASE_SENSITIVE
2682 namelen
= nameend
- newname
;
2684 newname
= original_case_string
;
2685 namelen
= strlen (newname
);
2688 namebuf
= xmemdup0 (newname
, namelen
);
2690 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2691 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2693 /* Insert name in all uppercase. */
2694 for (p
= namebuf
; *p
; p
++)
2697 if (strncmp (namebuf
, newname
, namelen
))
2698 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2699 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2701 /* Insert name in all lowercase. */
2702 for (p
= namebuf
; *p
; p
++)
2705 if (strncmp (namebuf
, newname
, namelen
))
2706 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2707 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2713 /* Should never be called, as .req goes between the alias and the
2714 register name, not at the beginning of the line. */
2717 s_req (int a ATTRIBUTE_UNUSED
)
2719 as_bad (_("invalid syntax for .req directive"));
2723 s_dn (int a ATTRIBUTE_UNUSED
)
2725 as_bad (_("invalid syntax for .dn directive"));
2729 s_qn (int a ATTRIBUTE_UNUSED
)
2731 as_bad (_("invalid syntax for .qn directive"));
2734 /* The .unreq directive deletes an alias which was previously defined
2735 by .req. For example:
2741 s_unreq (int a ATTRIBUTE_UNUSED
)
2746 name
= input_line_pointer
;
2748 while (*input_line_pointer
!= 0
2749 && *input_line_pointer
!= ' '
2750 && *input_line_pointer
!= '\n')
2751 ++input_line_pointer
;
2753 saved_char
= *input_line_pointer
;
2754 *input_line_pointer
= 0;
2757 as_bad (_("invalid syntax for .unreq directive"));
2760 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2764 as_bad (_("unknown register alias '%s'"), name
);
2765 else if (reg
->builtin
)
2766 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2773 hash_delete (arm_reg_hsh
, name
, FALSE
);
2774 free ((char *) reg
->name
);
2779 /* Also locate the all upper case and all lower case versions.
2780 Do not complain if we cannot find one or the other as it
2781 was probably deleted above. */
2783 nbuf
= strdup (name
);
2784 for (p
= nbuf
; *p
; p
++)
2786 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2789 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2790 free ((char *) reg
->name
);
2796 for (p
= nbuf
; *p
; p
++)
2798 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2801 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2802 free ((char *) reg
->name
);
2812 *input_line_pointer
= saved_char
;
2813 demand_empty_rest_of_line ();
2816 /* Directives: Instruction set selection. */
2819 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2820 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2821 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2822 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2824 /* Create a new mapping symbol for the transition to STATE. */
2827 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2830 const char * symname
;
2837 type
= BSF_NO_FLAGS
;
2841 type
= BSF_NO_FLAGS
;
2845 type
= BSF_NO_FLAGS
;
2851 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2852 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2857 THUMB_SET_FUNC (symbolP
, 0);
2858 ARM_SET_THUMB (symbolP
, 0);
2859 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2863 THUMB_SET_FUNC (symbolP
, 1);
2864 ARM_SET_THUMB (symbolP
, 1);
2865 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2873 /* Save the mapping symbols for future reference. Also check that
2874 we do not place two mapping symbols at the same offset within a
2875 frag. We'll handle overlap between frags in
2876 check_mapping_symbols.
2878 If .fill or other data filling directive generates zero sized data,
2879 the mapping symbol for the following code will have the same value
2880 as the one generated for the data filling directive. In this case,
2881 we replace the old symbol with the new one at the same address. */
2884 if (frag
->tc_frag_data
.first_map
!= NULL
)
2886 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2887 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2889 frag
->tc_frag_data
.first_map
= symbolP
;
2891 if (frag
->tc_frag_data
.last_map
!= NULL
)
2893 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2894 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2895 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2897 frag
->tc_frag_data
.last_map
= symbolP
;
2900 /* We must sometimes convert a region marked as code to data during
2901 code alignment, if an odd number of bytes have to be padded. The
2902 code mapping symbol is pushed to an aligned address. */
2905 insert_data_mapping_symbol (enum mstate state
,
2906 valueT value
, fragS
*frag
, offsetT bytes
)
2908 /* If there was already a mapping symbol, remove it. */
2909 if (frag
->tc_frag_data
.last_map
!= NULL
2910 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2912 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2916 know (frag
->tc_frag_data
.first_map
== symp
);
2917 frag
->tc_frag_data
.first_map
= NULL
;
2919 frag
->tc_frag_data
.last_map
= NULL
;
2920 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2923 make_mapping_symbol (MAP_DATA
, value
, frag
);
2924 make_mapping_symbol (state
, value
+ bytes
, frag
);
2927 static void mapping_state_2 (enum mstate state
, int max_chars
);
2929 /* Set the mapping state to STATE. Only call this when about to
2930 emit some STATE bytes to the file. */
2932 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2934 mapping_state (enum mstate state
)
2936 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2938 if (mapstate
== state
)
2939 /* The mapping symbol has already been emitted.
2940 There is nothing else to do. */
2943 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2945 All ARM instructions require 4-byte alignment.
2946 (Almost) all Thumb instructions require 2-byte alignment.
2948 When emitting instructions into any section, mark the section
2951 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2952 but themselves require 2-byte alignment; this applies to some
2953 PC- relative forms. However, these cases will involve implicit
2954 literal pool generation or an explicit .align >=2, both of
2955 which will cause the section to me marked with sufficient
2956 alignment. Thus, we don't handle those cases here. */
2957 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2959 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2960 /* This case will be evaluated later. */
2963 mapping_state_2 (state
, 0);
2966 /* Same as mapping_state, but MAX_CHARS bytes have already been
2967 allocated. Put the mapping symbol that far back. */
2970 mapping_state_2 (enum mstate state
, int max_chars
)
2972 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2974 if (!SEG_NORMAL (now_seg
))
2977 if (mapstate
== state
)
2978 /* The mapping symbol has already been emitted.
2979 There is nothing else to do. */
2982 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2983 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2985 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2986 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2989 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2992 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2993 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2997 #define mapping_state(x) ((void)0)
2998 #define mapping_state_2(x, y) ((void)0)
3001 /* Find the real, Thumb encoded start of a Thumb function. */
3005 find_real_start (symbolS
* symbolP
)
3008 const char * name
= S_GET_NAME (symbolP
);
3009 symbolS
* new_target
;
3011 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3012 #define STUB_NAME ".real_start_of"
3017 /* The compiler may generate BL instructions to local labels because
3018 it needs to perform a branch to a far away location. These labels
3019 do not have a corresponding ".real_start_of" label. We check
3020 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3021 the ".real_start_of" convention for nonlocal branches. */
3022 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3025 real_start
= concat (STUB_NAME
, name
, NULL
);
3026 new_target
= symbol_find (real_start
);
3029 if (new_target
== NULL
)
3031 as_warn (_("Failed to find real start of function: %s\n"), name
);
3032 new_target
= symbolP
;
3040 opcode_select (int width
)
3047 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3048 as_bad (_("selected processor does not support THUMB opcodes"));
3051 /* No need to force the alignment, since we will have been
3052 coming from ARM mode, which is word-aligned. */
3053 record_alignment (now_seg
, 1);
3060 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3061 as_bad (_("selected processor does not support ARM opcodes"));
3066 frag_align (2, 0, 0);
3068 record_alignment (now_seg
, 1);
3073 as_bad (_("invalid instruction size selected (%d)"), width
);
3078 s_arm (int ignore ATTRIBUTE_UNUSED
)
3081 demand_empty_rest_of_line ();
3085 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3088 demand_empty_rest_of_line ();
3092 s_code (int unused ATTRIBUTE_UNUSED
)
3096 temp
= get_absolute_expression ();
3101 opcode_select (temp
);
3105 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3110 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3112 /* If we are not already in thumb mode go into it, EVEN if
3113 the target processor does not support thumb instructions.
3114 This is used by gcc/config/arm/lib1funcs.asm for example
3115 to compile interworking support functions even if the
3116 target processor should not support interworking. */
3120 record_alignment (now_seg
, 1);
3123 demand_empty_rest_of_line ();
3127 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3131 /* The following label is the name/address of the start of a Thumb function.
3132 We need to know this for the interworking support. */
3133 label_is_thumb_function_name
= TRUE
;
3136 /* Perform a .set directive, but also mark the alias as
3137 being a thumb function. */
3140 s_thumb_set (int equiv
)
3142 /* XXX the following is a duplicate of the code for s_set() in read.c
3143 We cannot just call that code as we need to get at the symbol that
3150 /* Especial apologies for the random logic:
3151 This just grew, and could be parsed much more simply!
3153 delim
= get_symbol_name (& name
);
3154 end_name
= input_line_pointer
;
3155 (void) restore_line_pointer (delim
);
3157 if (*input_line_pointer
!= ',')
3160 as_bad (_("expected comma after name \"%s\""), name
);
3162 ignore_rest_of_line ();
3166 input_line_pointer
++;
3169 if (name
[0] == '.' && name
[1] == '\0')
3171 /* XXX - this should not happen to .thumb_set. */
3175 if ((symbolP
= symbol_find (name
)) == NULL
3176 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3179 /* When doing symbol listings, play games with dummy fragments living
3180 outside the normal fragment chain to record the file and line info
3182 if (listing
& LISTING_SYMBOLS
)
3184 extern struct list_info_struct
* listing_tail
;
3185 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3187 memset (dummy_frag
, 0, sizeof (fragS
));
3188 dummy_frag
->fr_type
= rs_fill
;
3189 dummy_frag
->line
= listing_tail
;
3190 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3191 dummy_frag
->fr_symbol
= symbolP
;
3195 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3198 /* "set" symbols are local unless otherwise specified. */
3199 SF_SET_LOCAL (symbolP
);
3200 #endif /* OBJ_COFF */
3201 } /* Make a new symbol. */
3203 symbol_table_insert (symbolP
);
3208 && S_IS_DEFINED (symbolP
)
3209 && S_GET_SEGMENT (symbolP
) != reg_section
)
3210 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3212 pseudo_set (symbolP
);
3214 demand_empty_rest_of_line ();
3216 /* XXX Now we come to the Thumb specific bit of code. */
3218 THUMB_SET_FUNC (symbolP
, 1);
3219 ARM_SET_THUMB (symbolP
, 1);
3220 #if defined OBJ_ELF || defined OBJ_COFF
3221 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3225 /* Directives: Mode selection. */
3227 /* .syntax [unified|divided] - choose the new unified syntax
3228 (same for Arm and Thumb encoding, modulo slight differences in what
3229 can be represented) or the old divergent syntax for each mode. */
3231 s_syntax (int unused ATTRIBUTE_UNUSED
)
3235 delim
= get_symbol_name (& name
);
3237 if (!strcasecmp (name
, "unified"))
3238 unified_syntax
= TRUE
;
3239 else if (!strcasecmp (name
, "divided"))
3240 unified_syntax
= FALSE
;
3243 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3246 (void) restore_line_pointer (delim
);
3247 demand_empty_rest_of_line ();
3250 /* Directives: sectioning and alignment. */
3253 s_bss (int ignore ATTRIBUTE_UNUSED
)
3255 /* We don't support putting frags in the BSS segment, we fake it by
3256 marking in_bss, then looking at s_skip for clues. */
3257 subseg_set (bss_section
, 0);
3258 demand_empty_rest_of_line ();
3260 #ifdef md_elf_section_change_hook
3261 md_elf_section_change_hook ();
3266 s_even (int ignore ATTRIBUTE_UNUSED
)
3268 /* Never make frag if expect extra pass. */
3270 frag_align (1, 0, 0);
3272 record_alignment (now_seg
, 1);
3274 demand_empty_rest_of_line ();
3277 /* Directives: CodeComposer Studio. */
3279 /* .ref (for CodeComposer Studio syntax only). */
3281 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3283 if (codecomposer_syntax
)
3284 ignore_rest_of_line ();
3286 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3289 /* If name is not NULL, then it is used for marking the beginning of a
3290 function, whereas if it is NULL then it means the function end. */
3292 asmfunc_debug (const char * name
)
3294 static const char * last_name
= NULL
;
3298 gas_assert (last_name
== NULL
);
3301 if (debug_type
== DEBUG_STABS
)
3302 stabs_generate_asm_func (name
, name
);
3306 gas_assert (last_name
!= NULL
);
3308 if (debug_type
== DEBUG_STABS
)
3309 stabs_generate_asm_endfunc (last_name
, last_name
);
3316 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3318 if (codecomposer_syntax
)
3320 switch (asmfunc_state
)
3322 case OUTSIDE_ASMFUNC
:
3323 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3326 case WAITING_ASMFUNC_NAME
:
3327 as_bad (_(".asmfunc repeated."));
3330 case WAITING_ENDASMFUNC
:
3331 as_bad (_(".asmfunc without function."));
3334 demand_empty_rest_of_line ();
3337 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3341 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3343 if (codecomposer_syntax
)
3345 switch (asmfunc_state
)
3347 case OUTSIDE_ASMFUNC
:
3348 as_bad (_(".endasmfunc without a .asmfunc."));
3351 case WAITING_ASMFUNC_NAME
:
3352 as_bad (_(".endasmfunc without function."));
3355 case WAITING_ENDASMFUNC
:
3356 asmfunc_state
= OUTSIDE_ASMFUNC
;
3357 asmfunc_debug (NULL
);
3360 demand_empty_rest_of_line ();
3363 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3367 s_ccs_def (int name
)
3369 if (codecomposer_syntax
)
3372 as_bad (_(".def pseudo-op only available with -mccs flag."));
3375 /* Directives: Literal pools. */
3377 static literal_pool
*
3378 find_literal_pool (void)
3380 literal_pool
* pool
;
3382 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3384 if (pool
->section
== now_seg
3385 && pool
->sub_section
== now_subseg
)
3392 static literal_pool
*
3393 find_or_make_literal_pool (void)
3395 /* Next literal pool ID number. */
3396 static unsigned int latest_pool_num
= 1;
3397 literal_pool
* pool
;
3399 pool
= find_literal_pool ();
3403 /* Create a new pool. */
3404 pool
= XNEW (literal_pool
);
3408 pool
->next_free_entry
= 0;
3409 pool
->section
= now_seg
;
3410 pool
->sub_section
= now_subseg
;
3411 pool
->next
= list_of_pools
;
3412 pool
->symbol
= NULL
;
3413 pool
->alignment
= 2;
3415 /* Add it to the list. */
3416 list_of_pools
= pool
;
3419 /* New pools, and emptied pools, will have a NULL symbol. */
3420 if (pool
->symbol
== NULL
)
3422 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3423 (valueT
) 0, &zero_address_frag
);
3424 pool
->id
= latest_pool_num
++;
3431 /* Add the literal in the global 'inst'
3432 structure to the relevant literal pool. */
3435 add_to_lit_pool (unsigned int nbytes
)
3437 #define PADDING_SLOT 0x1
3438 #define LIT_ENTRY_SIZE_MASK 0xFF
3439 literal_pool
* pool
;
3440 unsigned int entry
, pool_size
= 0;
3441 bfd_boolean padding_slot_p
= FALSE
;
3447 imm1
= inst
.operands
[1].imm
;
3448 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3449 : inst
.relocs
[0].exp
.X_unsigned
? 0
3450 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3451 if (target_big_endian
)
3454 imm2
= inst
.operands
[1].imm
;
3458 pool
= find_or_make_literal_pool ();
3460 /* Check if this literal value is already in the pool. */
3461 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3465 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3466 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3467 && (pool
->literals
[entry
].X_add_number
3468 == inst
.relocs
[0].exp
.X_add_number
)
3469 && (pool
->literals
[entry
].X_md
== nbytes
)
3470 && (pool
->literals
[entry
].X_unsigned
3471 == inst
.relocs
[0].exp
.X_unsigned
))
3474 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3475 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3476 && (pool
->literals
[entry
].X_add_number
3477 == inst
.relocs
[0].exp
.X_add_number
)
3478 && (pool
->literals
[entry
].X_add_symbol
3479 == inst
.relocs
[0].exp
.X_add_symbol
)
3480 && (pool
->literals
[entry
].X_op_symbol
3481 == inst
.relocs
[0].exp
.X_op_symbol
)
3482 && (pool
->literals
[entry
].X_md
== nbytes
))
3485 else if ((nbytes
== 8)
3486 && !(pool_size
& 0x7)
3487 && ((entry
+ 1) != pool
->next_free_entry
)
3488 && (pool
->literals
[entry
].X_op
== O_constant
)
3489 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3490 && (pool
->literals
[entry
].X_unsigned
3491 == inst
.relocs
[0].exp
.X_unsigned
)
3492 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3493 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3494 && (pool
->literals
[entry
+ 1].X_unsigned
3495 == inst
.relocs
[0].exp
.X_unsigned
))
3498 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3499 if (padding_slot_p
&& (nbytes
== 4))
3505 /* Do we need to create a new entry? */
3506 if (entry
== pool
->next_free_entry
)
3508 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3510 inst
.error
= _("literal pool overflow");
3516 /* For 8-byte entries, we align to an 8-byte boundary,
3517 and split it into two 4-byte entries, because on 32-bit
3518 host, 8-byte constants are treated as big num, thus
3519 saved in "generic_bignum" which will be overwritten
3520 by later assignments.
3522 We also need to make sure there is enough space for
3525 We also check to make sure the literal operand is a
3527 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3528 || inst
.relocs
[0].exp
.X_op
== O_big
))
3530 inst
.error
= _("invalid type for literal pool");
3533 else if (pool_size
& 0x7)
3535 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3537 inst
.error
= _("literal pool overflow");
3541 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3542 pool
->literals
[entry
].X_op
= O_constant
;
3543 pool
->literals
[entry
].X_add_number
= 0;
3544 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3545 pool
->next_free_entry
+= 1;
3548 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3550 inst
.error
= _("literal pool overflow");
3554 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3555 pool
->literals
[entry
].X_op
= O_constant
;
3556 pool
->literals
[entry
].X_add_number
= imm1
;
3557 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3558 pool
->literals
[entry
++].X_md
= 4;
3559 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3560 pool
->literals
[entry
].X_op
= O_constant
;
3561 pool
->literals
[entry
].X_add_number
= imm2
;
3562 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3563 pool
->literals
[entry
].X_md
= 4;
3564 pool
->alignment
= 3;
3565 pool
->next_free_entry
+= 1;
3569 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3570 pool
->literals
[entry
].X_md
= 4;
3574 /* PR ld/12974: Record the location of the first source line to reference
3575 this entry in the literal pool. If it turns out during linking that the
3576 symbol does not exist we will be able to give an accurate line number for
3577 the (first use of the) missing reference. */
3578 if (debug_type
== DEBUG_DWARF2
)
3579 dwarf2_where (pool
->locs
+ entry
);
3581 pool
->next_free_entry
+= 1;
3583 else if (padding_slot_p
)
3585 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3586 pool
->literals
[entry
].X_md
= nbytes
;
3589 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3590 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3591 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3597 tc_start_label_without_colon (void)
3599 bfd_boolean ret
= TRUE
;
3601 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3603 const char *label
= input_line_pointer
;
3605 while (!is_end_of_line
[(int) label
[-1]])
3610 as_bad (_("Invalid label '%s'"), label
);
3614 asmfunc_debug (label
);
3616 asmfunc_state
= WAITING_ENDASMFUNC
;
3622 /* Can't use symbol_new here, so have to create a symbol and then at
3623 a later date assign it a value. That's what these functions do. */
3626 symbol_locate (symbolS
* symbolP
,
3627 const char * name
, /* It is copied, the caller can modify. */
3628 segT segment
, /* Segment identifier (SEG_<something>). */
3629 valueT valu
, /* Symbol value. */
3630 fragS
* frag
) /* Associated fragment. */
3633 char * preserved_copy_of_name
;
3635 name_length
= strlen (name
) + 1; /* +1 for \0. */
3636 obstack_grow (¬es
, name
, name_length
);
3637 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3639 #ifdef tc_canonicalize_symbol_name
3640 preserved_copy_of_name
=
3641 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3644 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3646 S_SET_SEGMENT (symbolP
, segment
);
3647 S_SET_VALUE (symbolP
, valu
);
3648 symbol_clear_list_pointers (symbolP
);
3650 symbol_set_frag (symbolP
, frag
);
3652 /* Link to end of symbol chain. */
3654 extern int symbol_table_frozen
;
3656 if (symbol_table_frozen
)
3660 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3662 obj_symbol_new_hook (symbolP
);
3664 #ifdef tc_symbol_new_hook
3665 tc_symbol_new_hook (symbolP
);
3669 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3670 #endif /* DEBUG_SYMS */
3674 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3677 literal_pool
* pool
;
3680 pool
= find_literal_pool ();
3682 || pool
->symbol
== NULL
3683 || pool
->next_free_entry
== 0)
3686 /* Align pool as you have word accesses.
3687 Only make a frag if we have to. */
3689 frag_align (pool
->alignment
, 0, 0);
3691 record_alignment (now_seg
, 2);
3694 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3695 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3697 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3699 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3700 (valueT
) frag_now_fix (), frag_now
);
3701 symbol_table_insert (pool
->symbol
);
3703 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3705 #if defined OBJ_COFF || defined OBJ_ELF
3706 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3709 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3712 if (debug_type
== DEBUG_DWARF2
)
3713 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3715 /* First output the expression in the instruction to the pool. */
3716 emit_expr (&(pool
->literals
[entry
]),
3717 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3720 /* Mark the pool as empty. */
3721 pool
->next_free_entry
= 0;
3722 pool
->symbol
= NULL
;
3726 /* Forward declarations for functions below, in the MD interface
3728 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3729 static valueT
create_unwind_entry (int);
3730 static void start_unwind_section (const segT
, int);
3731 static void add_unwind_opcode (valueT
, int);
3732 static void flush_pending_unwind (void);
3734 /* Directives: Data. */
3737 s_arm_elf_cons (int nbytes
)
3741 #ifdef md_flush_pending_output
3742 md_flush_pending_output ();
3745 if (is_it_end_of_statement ())
3747 demand_empty_rest_of_line ();
3751 #ifdef md_cons_align
3752 md_cons_align (nbytes
);
3755 mapping_state (MAP_DATA
);
3759 char *base
= input_line_pointer
;
3763 if (exp
.X_op
!= O_symbol
)
3764 emit_expr (&exp
, (unsigned int) nbytes
);
3767 char *before_reloc
= input_line_pointer
;
3768 reloc
= parse_reloc (&input_line_pointer
);
3771 as_bad (_("unrecognized relocation suffix"));
3772 ignore_rest_of_line ();
3775 else if (reloc
== BFD_RELOC_UNUSED
)
3776 emit_expr (&exp
, (unsigned int) nbytes
);
3779 reloc_howto_type
*howto
= (reloc_howto_type
*)
3780 bfd_reloc_type_lookup (stdoutput
,
3781 (bfd_reloc_code_real_type
) reloc
);
3782 int size
= bfd_get_reloc_size (howto
);
3784 if (reloc
== BFD_RELOC_ARM_PLT32
)
3786 as_bad (_("(plt) is only valid on branch targets"));
3787 reloc
= BFD_RELOC_UNUSED
;
3792 as_bad (ngettext ("%s relocations do not fit in %d byte",
3793 "%s relocations do not fit in %d bytes",
3795 howto
->name
, nbytes
);
3798 /* We've parsed an expression stopping at O_symbol.
3799 But there may be more expression left now that we
3800 have parsed the relocation marker. Parse it again.
3801 XXX Surely there is a cleaner way to do this. */
3802 char *p
= input_line_pointer
;
3804 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3806 memcpy (save_buf
, base
, input_line_pointer
- base
);
3807 memmove (base
+ (input_line_pointer
- before_reloc
),
3808 base
, before_reloc
- base
);
3810 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3812 memcpy (base
, save_buf
, p
- base
);
3814 offset
= nbytes
- size
;
3815 p
= frag_more (nbytes
);
3816 memset (p
, 0, nbytes
);
3817 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3818 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3824 while (*input_line_pointer
++ == ',');
3826 /* Put terminator back into stream. */
3827 input_line_pointer
--;
3828 demand_empty_rest_of_line ();
3831 /* Emit an expression containing a 32-bit thumb instruction.
3832 Implementation based on put_thumb32_insn. */
3835 emit_thumb32_expr (expressionS
* exp
)
3837 expressionS exp_high
= *exp
;
3839 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3840 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3841 exp
->X_add_number
&= 0xffff;
3842 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3845 /* Guess the instruction size based on the opcode. */
3848 thumb_insn_size (int opcode
)
3850 if ((unsigned int) opcode
< 0xe800u
)
3852 else if ((unsigned int) opcode
>= 0xe8000000u
)
3859 emit_insn (expressionS
*exp
, int nbytes
)
3863 if (exp
->X_op
== O_constant
)
3868 size
= thumb_insn_size (exp
->X_add_number
);
3872 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3874 as_bad (_(".inst.n operand too big. "\
3875 "Use .inst.w instead"));
3880 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3881 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3883 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3885 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3886 emit_thumb32_expr (exp
);
3888 emit_expr (exp
, (unsigned int) size
);
3890 it_fsm_post_encode ();
3894 as_bad (_("cannot determine Thumb instruction size. " \
3895 "Use .inst.n/.inst.w instead"));
3898 as_bad (_("constant expression required"));
3903 /* Like s_arm_elf_cons but do not use md_cons_align and
3904 set the mapping state to MAP_ARM/MAP_THUMB. */
3907 s_arm_elf_inst (int nbytes
)
3909 if (is_it_end_of_statement ())
3911 demand_empty_rest_of_line ();
3915 /* Calling mapping_state () here will not change ARM/THUMB,
3916 but will ensure not to be in DATA state. */
3919 mapping_state (MAP_THUMB
);
3924 as_bad (_("width suffixes are invalid in ARM mode"));
3925 ignore_rest_of_line ();
3931 mapping_state (MAP_ARM
);
3940 if (! emit_insn (& exp
, nbytes
))
3942 ignore_rest_of_line ();
3946 while (*input_line_pointer
++ == ',');
3948 /* Put terminator back into stream. */
3949 input_line_pointer
--;
3950 demand_empty_rest_of_line ();
3953 /* Parse a .rel31 directive. */
3956 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3963 if (*input_line_pointer
== '1')
3964 highbit
= 0x80000000;
3965 else if (*input_line_pointer
!= '0')
3966 as_bad (_("expected 0 or 1"));
3968 input_line_pointer
++;
3969 if (*input_line_pointer
!= ',')
3970 as_bad (_("missing comma"));
3971 input_line_pointer
++;
3973 #ifdef md_flush_pending_output
3974 md_flush_pending_output ();
3977 #ifdef md_cons_align
3981 mapping_state (MAP_DATA
);
3986 md_number_to_chars (p
, highbit
, 4);
3987 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3988 BFD_RELOC_ARM_PREL31
);
3990 demand_empty_rest_of_line ();
3993 /* Directives: AEABI stack-unwind tables. */
3995 /* Parse an unwind_fnstart directive. Simply records the current location. */
3998 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4000 demand_empty_rest_of_line ();
4001 if (unwind
.proc_start
)
4003 as_bad (_("duplicate .fnstart directive"));
4007 /* Mark the start of the function. */
4008 unwind
.proc_start
= expr_build_dot ();
4010 /* Reset the rest of the unwind info. */
4011 unwind
.opcode_count
= 0;
4012 unwind
.table_entry
= NULL
;
4013 unwind
.personality_routine
= NULL
;
4014 unwind
.personality_index
= -1;
4015 unwind
.frame_size
= 0;
4016 unwind
.fp_offset
= 0;
4017 unwind
.fp_reg
= REG_SP
;
4019 unwind
.sp_restored
= 0;
4023 /* Parse a handlerdata directive. Creates the exception handling table entry
4024 for the function. */
4027 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4029 demand_empty_rest_of_line ();
4030 if (!unwind
.proc_start
)
4031 as_bad (MISSING_FNSTART
);
4033 if (unwind
.table_entry
)
4034 as_bad (_("duplicate .handlerdata directive"));
4036 create_unwind_entry (1);
4039 /* Parse an unwind_fnend directive. Generates the index table entry. */
4042 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4047 unsigned int marked_pr_dependency
;
4049 demand_empty_rest_of_line ();
4051 if (!unwind
.proc_start
)
4053 as_bad (_(".fnend directive without .fnstart"));
4057 /* Add eh table entry. */
4058 if (unwind
.table_entry
== NULL
)
4059 val
= create_unwind_entry (0);
4063 /* Add index table entry. This is two words. */
4064 start_unwind_section (unwind
.saved_seg
, 1);
4065 frag_align (2, 0, 0);
4066 record_alignment (now_seg
, 2);
4068 ptr
= frag_more (8);
4070 where
= frag_now_fix () - 8;
4072 /* Self relative offset of the function start. */
4073 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4074 BFD_RELOC_ARM_PREL31
);
4076 /* Indicate dependency on EHABI-defined personality routines to the
4077 linker, if it hasn't been done already. */
4078 marked_pr_dependency
4079 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4080 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4081 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4083 static const char *const name
[] =
4085 "__aeabi_unwind_cpp_pr0",
4086 "__aeabi_unwind_cpp_pr1",
4087 "__aeabi_unwind_cpp_pr2"
4089 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4090 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4091 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4092 |= 1 << unwind
.personality_index
;
4096 /* Inline exception table entry. */
4097 md_number_to_chars (ptr
+ 4, val
, 4);
4099 /* Self relative offset of the table entry. */
4100 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4101 BFD_RELOC_ARM_PREL31
);
4103 /* Restore the original section. */
4104 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4106 unwind
.proc_start
= NULL
;
4110 /* Parse an unwind_cantunwind directive. */
4113 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4115 demand_empty_rest_of_line ();
4116 if (!unwind
.proc_start
)
4117 as_bad (MISSING_FNSTART
);
4119 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4120 as_bad (_("personality routine specified for cantunwind frame"));
4122 unwind
.personality_index
= -2;
4126 /* Parse a personalityindex directive. */
4129 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4133 if (!unwind
.proc_start
)
4134 as_bad (MISSING_FNSTART
);
4136 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4137 as_bad (_("duplicate .personalityindex directive"));
4141 if (exp
.X_op
!= O_constant
4142 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4144 as_bad (_("bad personality routine number"));
4145 ignore_rest_of_line ();
4149 unwind
.personality_index
= exp
.X_add_number
;
4151 demand_empty_rest_of_line ();
4155 /* Parse a personality directive. */
4158 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4162 if (!unwind
.proc_start
)
4163 as_bad (MISSING_FNSTART
);
4165 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4166 as_bad (_("duplicate .personality directive"));
4168 c
= get_symbol_name (& name
);
4169 p
= input_line_pointer
;
4171 ++ input_line_pointer
;
4172 unwind
.personality_routine
= symbol_find_or_make (name
);
4174 demand_empty_rest_of_line ();
4178 /* Parse a directive saving core registers. */
4181 s_arm_unwind_save_core (void)
4187 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4190 as_bad (_("expected register list"));
4191 ignore_rest_of_line ();
4195 demand_empty_rest_of_line ();
4197 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4198 into .unwind_save {..., sp...}. We aren't bothered about the value of
4199 ip because it is clobbered by calls. */
4200 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4201 && (range
& 0x3000) == 0x1000)
4203 unwind
.opcode_count
--;
4204 unwind
.sp_restored
= 0;
4205 range
= (range
| 0x2000) & ~0x1000;
4206 unwind
.pending_offset
= 0;
4212 /* See if we can use the short opcodes. These pop a block of up to 8
4213 registers starting with r4, plus maybe r14. */
4214 for (n
= 0; n
< 8; n
++)
4216 /* Break at the first non-saved register. */
4217 if ((range
& (1 << (n
+ 4))) == 0)
4220 /* See if there are any other bits set. */
4221 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4223 /* Use the long form. */
4224 op
= 0x8000 | ((range
>> 4) & 0xfff);
4225 add_unwind_opcode (op
, 2);
4229 /* Use the short form. */
4231 op
= 0xa8; /* Pop r14. */
4233 op
= 0xa0; /* Do not pop r14. */
4235 add_unwind_opcode (op
, 1);
4242 op
= 0xb100 | (range
& 0xf);
4243 add_unwind_opcode (op
, 2);
4246 /* Record the number of bytes pushed. */
4247 for (n
= 0; n
< 16; n
++)
4249 if (range
& (1 << n
))
4250 unwind
.frame_size
+= 4;
4255 /* Parse a directive saving FPA registers. */
4258 s_arm_unwind_save_fpa (int reg
)
4264 /* Get Number of registers to transfer. */
4265 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4268 exp
.X_op
= O_illegal
;
4270 if (exp
.X_op
!= O_constant
)
4272 as_bad (_("expected , <constant>"));
4273 ignore_rest_of_line ();
4277 num_regs
= exp
.X_add_number
;
4279 if (num_regs
< 1 || num_regs
> 4)
4281 as_bad (_("number of registers must be in the range [1:4]"));
4282 ignore_rest_of_line ();
4286 demand_empty_rest_of_line ();
4291 op
= 0xb4 | (num_regs
- 1);
4292 add_unwind_opcode (op
, 1);
4297 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4298 add_unwind_opcode (op
, 2);
4300 unwind
.frame_size
+= num_regs
* 12;
4304 /* Parse a directive saving VFP registers for ARMv6 and above. */
4307 s_arm_unwind_save_vfp_armv6 (void)
4312 int num_vfpv3_regs
= 0;
4313 int num_regs_below_16
;
4314 bfd_boolean partial_match
;
4316 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4320 as_bad (_("expected register list"));
4321 ignore_rest_of_line ();
4325 demand_empty_rest_of_line ();
4327 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4328 than FSTMX/FLDMX-style ones). */
4330 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4332 num_vfpv3_regs
= count
;
4333 else if (start
+ count
> 16)
4334 num_vfpv3_regs
= start
+ count
- 16;
4336 if (num_vfpv3_regs
> 0)
4338 int start_offset
= start
> 16 ? start
- 16 : 0;
4339 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4340 add_unwind_opcode (op
, 2);
4343 /* Generate opcode for registers numbered in the range 0 .. 15. */
4344 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4345 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4346 if (num_regs_below_16
> 0)
4348 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4349 add_unwind_opcode (op
, 2);
4352 unwind
.frame_size
+= count
* 8;
4356 /* Parse a directive saving VFP registers for pre-ARMv6. */
4359 s_arm_unwind_save_vfp (void)
4364 bfd_boolean partial_match
;
4366 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4370 as_bad (_("expected register list"));
4371 ignore_rest_of_line ();
4375 demand_empty_rest_of_line ();
4380 op
= 0xb8 | (count
- 1);
4381 add_unwind_opcode (op
, 1);
4386 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4387 add_unwind_opcode (op
, 2);
4389 unwind
.frame_size
+= count
* 8 + 4;
4393 /* Parse a directive saving iWMMXt data registers. */
4396 s_arm_unwind_save_mmxwr (void)
4404 if (*input_line_pointer
== '{')
4405 input_line_pointer
++;
4409 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4413 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4418 as_tsktsk (_("register list not in ascending order"));
4421 if (*input_line_pointer
== '-')
4423 input_line_pointer
++;
4424 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4427 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4430 else if (reg
>= hi_reg
)
4432 as_bad (_("bad register range"));
4435 for (; reg
< hi_reg
; reg
++)
4439 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4441 skip_past_char (&input_line_pointer
, '}');
4443 demand_empty_rest_of_line ();
4445 /* Generate any deferred opcodes because we're going to be looking at
4447 flush_pending_unwind ();
4449 for (i
= 0; i
< 16; i
++)
4451 if (mask
& (1 << i
))
4452 unwind
.frame_size
+= 8;
4455 /* Attempt to combine with a previous opcode. We do this because gcc
4456 likes to output separate unwind directives for a single block of
4458 if (unwind
.opcode_count
> 0)
4460 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4461 if ((i
& 0xf8) == 0xc0)
4464 /* Only merge if the blocks are contiguous. */
4467 if ((mask
& 0xfe00) == (1 << 9))
4469 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4470 unwind
.opcode_count
--;
4473 else if (i
== 6 && unwind
.opcode_count
>= 2)
4475 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4479 op
= 0xffff << (reg
- 1);
4481 && ((mask
& op
) == (1u << (reg
- 1))))
4483 op
= (1 << (reg
+ i
+ 1)) - 1;
4484 op
&= ~((1 << reg
) - 1);
4486 unwind
.opcode_count
-= 2;
4493 /* We want to generate opcodes in the order the registers have been
4494 saved, ie. descending order. */
4495 for (reg
= 15; reg
>= -1; reg
--)
4497 /* Save registers in blocks. */
4499 || !(mask
& (1 << reg
)))
4501 /* We found an unsaved reg. Generate opcodes to save the
4508 op
= 0xc0 | (hi_reg
- 10);
4509 add_unwind_opcode (op
, 1);
4514 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4515 add_unwind_opcode (op
, 2);
4524 ignore_rest_of_line ();
4528 s_arm_unwind_save_mmxwcg (void)
4535 if (*input_line_pointer
== '{')
4536 input_line_pointer
++;
4538 skip_whitespace (input_line_pointer
);
4542 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4546 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4552 as_tsktsk (_("register list not in ascending order"));
4555 if (*input_line_pointer
== '-')
4557 input_line_pointer
++;
4558 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4561 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4564 else if (reg
>= hi_reg
)
4566 as_bad (_("bad register range"));
4569 for (; reg
< hi_reg
; reg
++)
4573 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4575 skip_past_char (&input_line_pointer
, '}');
4577 demand_empty_rest_of_line ();
4579 /* Generate any deferred opcodes because we're going to be looking at
4581 flush_pending_unwind ();
4583 for (reg
= 0; reg
< 16; reg
++)
4585 if (mask
& (1 << reg
))
4586 unwind
.frame_size
+= 4;
4589 add_unwind_opcode (op
, 2);
4592 ignore_rest_of_line ();
4596 /* Parse an unwind_save directive.
4597 If the argument is non-zero, this is a .vsave directive. */
4600 s_arm_unwind_save (int arch_v6
)
4603 struct reg_entry
*reg
;
4604 bfd_boolean had_brace
= FALSE
;
4606 if (!unwind
.proc_start
)
4607 as_bad (MISSING_FNSTART
);
4609 /* Figure out what sort of save we have. */
4610 peek
= input_line_pointer
;
4618 reg
= arm_reg_parse_multi (&peek
);
4622 as_bad (_("register expected"));
4623 ignore_rest_of_line ();
4632 as_bad (_("FPA .unwind_save does not take a register list"));
4633 ignore_rest_of_line ();
4636 input_line_pointer
= peek
;
4637 s_arm_unwind_save_fpa (reg
->number
);
4641 s_arm_unwind_save_core ();
4646 s_arm_unwind_save_vfp_armv6 ();
4648 s_arm_unwind_save_vfp ();
4651 case REG_TYPE_MMXWR
:
4652 s_arm_unwind_save_mmxwr ();
4655 case REG_TYPE_MMXWCG
:
4656 s_arm_unwind_save_mmxwcg ();
4660 as_bad (_(".unwind_save does not support this kind of register"));
4661 ignore_rest_of_line ();
4666 /* Parse an unwind_movsp directive. */
4669 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4675 if (!unwind
.proc_start
)
4676 as_bad (MISSING_FNSTART
);
4678 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4681 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4682 ignore_rest_of_line ();
4686 /* Optional constant. */
4687 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4689 if (immediate_for_directive (&offset
) == FAIL
)
4695 demand_empty_rest_of_line ();
4697 if (reg
== REG_SP
|| reg
== REG_PC
)
4699 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4703 if (unwind
.fp_reg
!= REG_SP
)
4704 as_bad (_("unexpected .unwind_movsp directive"));
4706 /* Generate opcode to restore the value. */
4708 add_unwind_opcode (op
, 1);
4710 /* Record the information for later. */
4711 unwind
.fp_reg
= reg
;
4712 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4713 unwind
.sp_restored
= 1;
4716 /* Parse an unwind_pad directive. */
4719 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4723 if (!unwind
.proc_start
)
4724 as_bad (MISSING_FNSTART
);
4726 if (immediate_for_directive (&offset
) == FAIL
)
4731 as_bad (_("stack increment must be multiple of 4"));
4732 ignore_rest_of_line ();
4736 /* Don't generate any opcodes, just record the details for later. */
4737 unwind
.frame_size
+= offset
;
4738 unwind
.pending_offset
+= offset
;
4740 demand_empty_rest_of_line ();
4743 /* Parse an unwind_setfp directive. */
4746 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4752 if (!unwind
.proc_start
)
4753 as_bad (MISSING_FNSTART
);
4755 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4756 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4759 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4761 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4763 as_bad (_("expected <reg>, <reg>"));
4764 ignore_rest_of_line ();
4768 /* Optional constant. */
4769 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4771 if (immediate_for_directive (&offset
) == FAIL
)
4777 demand_empty_rest_of_line ();
4779 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4781 as_bad (_("register must be either sp or set by a previous"
4782 "unwind_movsp directive"));
4786 /* Don't generate any opcodes, just record the information for later. */
4787 unwind
.fp_reg
= fp_reg
;
4789 if (sp_reg
== REG_SP
)
4790 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4792 unwind
.fp_offset
-= offset
;
4795 /* Parse an unwind_raw directive. */
4798 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4801 /* This is an arbitrary limit. */
4802 unsigned char op
[16];
4805 if (!unwind
.proc_start
)
4806 as_bad (MISSING_FNSTART
);
4809 if (exp
.X_op
== O_constant
4810 && skip_past_comma (&input_line_pointer
) != FAIL
)
4812 unwind
.frame_size
+= exp
.X_add_number
;
4816 exp
.X_op
= O_illegal
;
4818 if (exp
.X_op
!= O_constant
)
4820 as_bad (_("expected <offset>, <opcode>"));
4821 ignore_rest_of_line ();
4827 /* Parse the opcode. */
4832 as_bad (_("unwind opcode too long"));
4833 ignore_rest_of_line ();
4835 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4837 as_bad (_("invalid unwind opcode"));
4838 ignore_rest_of_line ();
4841 op
[count
++] = exp
.X_add_number
;
4843 /* Parse the next byte. */
4844 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4850 /* Add the opcode bytes in reverse order. */
4852 add_unwind_opcode (op
[count
], 1);
4854 demand_empty_rest_of_line ();
4858 /* Parse a .eabi_attribute directive. */
4861 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4863 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4865 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4866 attributes_set_explicitly
[tag
] = 1;
4869 /* Emit a tls fix for the symbol. */
4872 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4876 #ifdef md_flush_pending_output
4877 md_flush_pending_output ();
4880 #ifdef md_cons_align
4884 /* Since we're just labelling the code, there's no need to define a
4887 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4888 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4889 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4890 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4892 #endif /* OBJ_ELF */
4894 static void s_arm_arch (int);
4895 static void s_arm_object_arch (int);
4896 static void s_arm_cpu (int);
4897 static void s_arm_fpu (int);
4898 static void s_arm_arch_extension (int);
4903 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4910 if (exp
.X_op
== O_symbol
)
4911 exp
.X_op
= O_secrel
;
4913 emit_expr (&exp
, 4);
4915 while (*input_line_pointer
++ == ',');
4917 input_line_pointer
--;
4918 demand_empty_rest_of_line ();
4922 /* This table describes all the machine specific pseudo-ops the assembler
4923 has to support. The fields are:
4924 pseudo-op name without dot
4925 function to call to execute this pseudo-op
4926 Integer arg to pass to the function. */
4928 const pseudo_typeS md_pseudo_table
[] =
4930 /* Never called because '.req' does not start a line. */
4931 { "req", s_req
, 0 },
4932 /* Following two are likewise never called. */
4935 { "unreq", s_unreq
, 0 },
4936 { "bss", s_bss
, 0 },
4937 { "align", s_align_ptwo
, 2 },
4938 { "arm", s_arm
, 0 },
4939 { "thumb", s_thumb
, 0 },
4940 { "code", s_code
, 0 },
4941 { "force_thumb", s_force_thumb
, 0 },
4942 { "thumb_func", s_thumb_func
, 0 },
4943 { "thumb_set", s_thumb_set
, 0 },
4944 { "even", s_even
, 0 },
4945 { "ltorg", s_ltorg
, 0 },
4946 { "pool", s_ltorg
, 0 },
4947 { "syntax", s_syntax
, 0 },
4948 { "cpu", s_arm_cpu
, 0 },
4949 { "arch", s_arm_arch
, 0 },
4950 { "object_arch", s_arm_object_arch
, 0 },
4951 { "fpu", s_arm_fpu
, 0 },
4952 { "arch_extension", s_arm_arch_extension
, 0 },
4954 { "word", s_arm_elf_cons
, 4 },
4955 { "long", s_arm_elf_cons
, 4 },
4956 { "inst.n", s_arm_elf_inst
, 2 },
4957 { "inst.w", s_arm_elf_inst
, 4 },
4958 { "inst", s_arm_elf_inst
, 0 },
4959 { "rel31", s_arm_rel31
, 0 },
4960 { "fnstart", s_arm_unwind_fnstart
, 0 },
4961 { "fnend", s_arm_unwind_fnend
, 0 },
4962 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4963 { "personality", s_arm_unwind_personality
, 0 },
4964 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4965 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4966 { "save", s_arm_unwind_save
, 0 },
4967 { "vsave", s_arm_unwind_save
, 1 },
4968 { "movsp", s_arm_unwind_movsp
, 0 },
4969 { "pad", s_arm_unwind_pad
, 0 },
4970 { "setfp", s_arm_unwind_setfp
, 0 },
4971 { "unwind_raw", s_arm_unwind_raw
, 0 },
4972 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4973 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4977 /* These are used for dwarf. */
4981 /* These are used for dwarf2. */
4982 { "file", dwarf2_directive_file
, 0 },
4983 { "loc", dwarf2_directive_loc
, 0 },
4984 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4986 { "extend", float_cons
, 'x' },
4987 { "ldouble", float_cons
, 'x' },
4988 { "packed", float_cons
, 'p' },
4990 {"secrel32", pe_directive_secrel
, 0},
4993 /* These are for compatibility with CodeComposer Studio. */
4994 {"ref", s_ccs_ref
, 0},
4995 {"def", s_ccs_def
, 0},
4996 {"asmfunc", s_ccs_asmfunc
, 0},
4997 {"endasmfunc", s_ccs_endasmfunc
, 0},
5002 /* Parser functions used exclusively in instruction operands. */
5004 /* Generic immediate-value read function for use in insn parsing.
5005 STR points to the beginning of the immediate (the leading #);
5006 VAL receives the value; if the value is outside [MIN, MAX]
5007 issue an error. PREFIX_OPT is true if the immediate prefix is
5011 parse_immediate (char **str
, int *val
, int min
, int max
,
5012 bfd_boolean prefix_opt
)
5016 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5017 if (exp
.X_op
!= O_constant
)
5019 inst
.error
= _("constant expression required");
5023 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5025 inst
.error
= _("immediate value out of range");
5029 *val
= exp
.X_add_number
;
5033 /* Less-generic immediate-value read function with the possibility of loading a
5034 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5035 instructions. Puts the result directly in inst.operands[i]. */
5038 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5039 bfd_boolean allow_symbol_p
)
5042 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5045 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5047 if (exp_p
->X_op
== O_constant
)
5049 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5050 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5051 O_constant. We have to be careful not to break compilation for
5052 32-bit X_add_number, though. */
5053 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5055 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5056 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5058 inst
.operands
[i
].regisimm
= 1;
5061 else if (exp_p
->X_op
== O_big
5062 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5064 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5066 /* Bignums have their least significant bits in
5067 generic_bignum[0]. Make sure we put 32 bits in imm and
5068 32 bits in reg, in a (hopefully) portable way. */
5069 gas_assert (parts
!= 0);
5071 /* Make sure that the number is not too big.
5072 PR 11972: Bignums can now be sign-extended to the
5073 size of a .octa so check that the out of range bits
5074 are all zero or all one. */
5075 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5077 LITTLENUM_TYPE m
= -1;
5079 if (generic_bignum
[parts
* 2] != 0
5080 && generic_bignum
[parts
* 2] != m
)
5083 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5084 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5088 inst
.operands
[i
].imm
= 0;
5089 for (j
= 0; j
< parts
; j
++, idx
++)
5090 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5091 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5092 inst
.operands
[i
].reg
= 0;
5093 for (j
= 0; j
< parts
; j
++, idx
++)
5094 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5095 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5096 inst
.operands
[i
].regisimm
= 1;
5098 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5106 /* Returns the pseudo-register number of an FPA immediate constant,
5107 or FAIL if there isn't a valid constant here. */
5110 parse_fpa_immediate (char ** str
)
5112 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5118 /* First try and match exact strings, this is to guarantee
5119 that some formats will work even for cross assembly. */
5121 for (i
= 0; fp_const
[i
]; i
++)
5123 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5127 *str
+= strlen (fp_const
[i
]);
5128 if (is_end_of_line
[(unsigned char) **str
])
5134 /* Just because we didn't get a match doesn't mean that the constant
5135 isn't valid, just that it is in a format that we don't
5136 automatically recognize. Try parsing it with the standard
5137 expression routines. */
5139 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5141 /* Look for a raw floating point number. */
5142 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5143 && is_end_of_line
[(unsigned char) *save_in
])
5145 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5147 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5149 if (words
[j
] != fp_values
[i
][j
])
5153 if (j
== MAX_LITTLENUMS
)
5161 /* Try and parse a more complex expression, this will probably fail
5162 unless the code uses a floating point prefix (eg "0f"). */
5163 save_in
= input_line_pointer
;
5164 input_line_pointer
= *str
;
5165 if (expression (&exp
) == absolute_section
5166 && exp
.X_op
== O_big
5167 && exp
.X_add_number
< 0)
5169 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5171 #define X_PRECISION 5
5172 #define E_PRECISION 15L
5173 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5175 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5177 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5179 if (words
[j
] != fp_values
[i
][j
])
5183 if (j
== MAX_LITTLENUMS
)
5185 *str
= input_line_pointer
;
5186 input_line_pointer
= save_in
;
5193 *str
= input_line_pointer
;
5194 input_line_pointer
= save_in
;
5195 inst
.error
= _("invalid FPA immediate expression");
5199 /* Returns 1 if a number has "quarter-precision" float format
5200 0baBbbbbbc defgh000 00000000 00000000. */
5203 is_quarter_float (unsigned imm
)
5205 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5206 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5210 /* Detect the presence of a floating point or integer zero constant,
5214 parse_ifimm_zero (char **in
)
5218 if (!is_immediate_prefix (**in
))
5220 /* In unified syntax, all prefixes are optional. */
5221 if (!unified_syntax
)
5227 /* Accept #0x0 as a synonym for #0. */
5228 if (strncmp (*in
, "0x", 2) == 0)
5231 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5236 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5237 &generic_floating_point_number
);
5240 && generic_floating_point_number
.sign
== '+'
5241 && (generic_floating_point_number
.low
5242 > generic_floating_point_number
.leader
))
5248 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5249 0baBbbbbbc defgh000 00000000 00000000.
5250 The zero and minus-zero cases need special handling, since they can't be
5251 encoded in the "quarter-precision" float format, but can nonetheless be
5252 loaded as integer constants. */
5255 parse_qfloat_immediate (char **ccp
, int *immed
)
5259 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5260 int found_fpchar
= 0;
5262 skip_past_char (&str
, '#');
5264 /* We must not accidentally parse an integer as a floating-point number. Make
5265 sure that the value we parse is not an integer by checking for special
5266 characters '.' or 'e'.
5267 FIXME: This is a horrible hack, but doing better is tricky because type
5268 information isn't in a very usable state at parse time. */
5270 skip_whitespace (fpnum
);
5272 if (strncmp (fpnum
, "0x", 2) == 0)
5276 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5277 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5287 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5289 unsigned fpword
= 0;
5292 /* Our FP word must be 32 bits (single-precision FP). */
5293 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5295 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5299 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5312 /* Shift operands. */
5315 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5318 struct asm_shift_name
5321 enum shift_kind kind
;
5324 /* Third argument to parse_shift. */
5325 enum parse_shift_mode
5327 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5328 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5329 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5330 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5331 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5332 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5335 /* Parse a <shift> specifier on an ARM data processing instruction.
5336 This has three forms:
5338 (LSL|LSR|ASL|ASR|ROR) Rs
5339 (LSL|LSR|ASL|ASR|ROR) #imm
5342 Note that ASL is assimilated to LSL in the instruction encoding, and
5343 RRX to ROR #0 (which cannot be written as such). */
5346 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5348 const struct asm_shift_name
*shift_name
;
5349 enum shift_kind shift
;
5354 for (p
= *str
; ISALPHA (*p
); p
++)
5359 inst
.error
= _("shift expression expected");
5363 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5366 if (shift_name
== NULL
)
5368 inst
.error
= _("shift expression expected");
5372 shift
= shift_name
->kind
;
5376 case NO_SHIFT_RESTRICT
:
5377 case SHIFT_IMMEDIATE
:
5378 if (shift
== SHIFT_UXTW
)
5380 inst
.error
= _("'UXTW' not allowed here");
5385 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5386 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5388 inst
.error
= _("'LSL' or 'ASR' required");
5393 case SHIFT_LSL_IMMEDIATE
:
5394 if (shift
!= SHIFT_LSL
)
5396 inst
.error
= _("'LSL' required");
5401 case SHIFT_ASR_IMMEDIATE
:
5402 if (shift
!= SHIFT_ASR
)
5404 inst
.error
= _("'ASR' required");
5408 case SHIFT_UXTW_IMMEDIATE
:
5409 if (shift
!= SHIFT_UXTW
)
5411 inst
.error
= _("'UXTW' required");
5419 if (shift
!= SHIFT_RRX
)
5421 /* Whitespace can appear here if the next thing is a bare digit. */
5422 skip_whitespace (p
);
5424 if (mode
== NO_SHIFT_RESTRICT
5425 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5427 inst
.operands
[i
].imm
= reg
;
5428 inst
.operands
[i
].immisreg
= 1;
5430 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5433 inst
.operands
[i
].shift_kind
= shift
;
5434 inst
.operands
[i
].shifted
= 1;
5439 /* Parse a <shifter_operand> for an ARM data processing instruction:
5442 #<immediate>, <rotate>
5446 where <shift> is defined by parse_shift above, and <rotate> is a
5447 multiple of 2 between 0 and 30. Validation of immediate operands
5448 is deferred to md_apply_fix. */
5451 parse_shifter_operand (char **str
, int i
)
5456 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5458 inst
.operands
[i
].reg
= value
;
5459 inst
.operands
[i
].isreg
= 1;
5461 /* parse_shift will override this if appropriate */
5462 inst
.relocs
[0].exp
.X_op
= O_constant
;
5463 inst
.relocs
[0].exp
.X_add_number
= 0;
5465 if (skip_past_comma (str
) == FAIL
)
5468 /* Shift operation on register. */
5469 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5472 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5475 if (skip_past_comma (str
) == SUCCESS
)
5477 /* #x, y -- ie explicit rotation by Y. */
5478 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5481 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5483 inst
.error
= _("constant expression expected");
5487 value
= exp
.X_add_number
;
5488 if (value
< 0 || value
> 30 || value
% 2 != 0)
5490 inst
.error
= _("invalid rotation");
5493 if (inst
.relocs
[0].exp
.X_add_number
< 0
5494 || inst
.relocs
[0].exp
.X_add_number
> 255)
5496 inst
.error
= _("invalid constant");
5500 /* Encode as specified. */
5501 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5505 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5506 inst
.relocs
[0].pc_rel
= 0;
5510 /* Group relocation information. Each entry in the table contains the
5511 textual name of the relocation as may appear in assembler source
5512 and must end with a colon.
5513 Along with this textual name are the relocation codes to be used if
5514 the corresponding instruction is an ALU instruction (ADD or SUB only),
5515 an LDR, an LDRS, or an LDC. */
5517 struct group_reloc_table_entry
5528 /* Varieties of non-ALU group relocation. */
5536 static struct group_reloc_table_entry group_reloc_table
[] =
5537 { /* Program counter relative: */
5539 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5544 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5545 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5546 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5547 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5549 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5554 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5555 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5556 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5557 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5559 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5560 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5561 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5562 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5563 /* Section base relative */
5565 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5570 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5571 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5572 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5573 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5575 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5580 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5581 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5582 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5583 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5585 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5586 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5587 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5588 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5589 /* Absolute thumb alu relocations. */
5591 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5596 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5601 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5606 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5611 /* Given the address of a pointer pointing to the textual name of a group
5612 relocation as may appear in assembler source, attempt to find its details
5613 in group_reloc_table. The pointer will be updated to the character after
5614 the trailing colon. On failure, FAIL will be returned; SUCCESS
5615 otherwise. On success, *entry will be updated to point at the relevant
5616 group_reloc_table entry. */
5619 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5622 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5624 int length
= strlen (group_reloc_table
[i
].name
);
5626 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5627 && (*str
)[length
] == ':')
5629 *out
= &group_reloc_table
[i
];
5630 *str
+= (length
+ 1);
5638 /* Parse a <shifter_operand> for an ARM data processing instruction
5639 (as for parse_shifter_operand) where group relocations are allowed:
5642 #<immediate>, <rotate>
5643 #:<group_reloc>:<expression>
5647 where <group_reloc> is one of the strings defined in group_reloc_table.
5648 The hashes are optional.
5650 Everything else is as for parse_shifter_operand. */
5652 static parse_operand_result
5653 parse_shifter_operand_group_reloc (char **str
, int i
)
5655 /* Determine if we have the sequence of characters #: or just :
5656 coming next. If we do, then we check for a group relocation.
5657 If we don't, punt the whole lot to parse_shifter_operand. */
5659 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5660 || (*str
)[0] == ':')
5662 struct group_reloc_table_entry
*entry
;
5664 if ((*str
)[0] == '#')
5669 /* Try to parse a group relocation. Anything else is an error. */
5670 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5672 inst
.error
= _("unknown group relocation");
5673 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5676 /* We now have the group relocation table entry corresponding to
5677 the name in the assembler source. Next, we parse the expression. */
5678 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5679 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5681 /* Record the relocation type (always the ALU variant here). */
5682 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5683 gas_assert (inst
.relocs
[0].type
!= 0);
5685 return PARSE_OPERAND_SUCCESS
;
5688 return parse_shifter_operand (str
, i
) == SUCCESS
5689 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5691 /* Never reached. */
5694 /* Parse a Neon alignment expression. Information is written to
5695 inst.operands[i]. We assume the initial ':' has been skipped.
5697 align .imm = align << 8, .immisalign=1, .preind=0 */
5698 static parse_operand_result
5699 parse_neon_alignment (char **str
, int i
)
5704 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5706 if (exp
.X_op
!= O_constant
)
5708 inst
.error
= _("alignment must be constant");
5709 return PARSE_OPERAND_FAIL
;
5712 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5713 inst
.operands
[i
].immisalign
= 1;
5714 /* Alignments are not pre-indexes. */
5715 inst
.operands
[i
].preind
= 0;
5718 return PARSE_OPERAND_SUCCESS
;
5721 /* Parse all forms of an ARM address expression. Information is written
5722 to inst.operands[i] and/or inst.relocs[0].
5724 Preindexed addressing (.preind=1):
5726 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5727 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5728 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5729 .shift_kind=shift .relocs[0].exp=shift_imm
5731 These three may have a trailing ! which causes .writeback to be set also.
5733 Postindexed addressing (.postind=1, .writeback=1):
5735 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5736 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5737 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5738 .shift_kind=shift .relocs[0].exp=shift_imm
5740 Unindexed addressing (.preind=0, .postind=0):
5742 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5746 [Rn]{!} shorthand for [Rn,#0]{!}
5747 =immediate .isreg=0 .relocs[0].exp=immediate
5748 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5750 It is the caller's responsibility to check for addressing modes not
5751 supported by the instruction, and to set inst.relocs[0].type. */
5753 static parse_operand_result
5754 parse_address_main (char **str
, int i
, int group_relocations
,
5755 group_reloc_type group_type
)
5760 if (skip_past_char (&p
, '[') == FAIL
)
5762 if (skip_past_char (&p
, '=') == FAIL
)
5764 /* Bare address - translate to PC-relative offset. */
5765 inst
.relocs
[0].pc_rel
= 1;
5766 inst
.operands
[i
].reg
= REG_PC
;
5767 inst
.operands
[i
].isreg
= 1;
5768 inst
.operands
[i
].preind
= 1;
5770 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5771 return PARSE_OPERAND_FAIL
;
5773 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5774 /*allow_symbol_p=*/TRUE
))
5775 return PARSE_OPERAND_FAIL
;
5778 return PARSE_OPERAND_SUCCESS
;
5781 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5782 skip_whitespace (p
);
5784 if (group_type
== GROUP_MVE
)
5786 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5787 struct neon_type_el et
;
5788 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5790 inst
.operands
[i
].isquad
= 1;
5792 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5794 inst
.error
= BAD_ADDR_MODE
;
5795 return PARSE_OPERAND_FAIL
;
5798 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5800 if (group_type
== GROUP_MVE
)
5801 inst
.error
= BAD_ADDR_MODE
;
5803 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5804 return PARSE_OPERAND_FAIL
;
5806 inst
.operands
[i
].reg
= reg
;
5807 inst
.operands
[i
].isreg
= 1;
5809 if (skip_past_comma (&p
) == SUCCESS
)
5811 inst
.operands
[i
].preind
= 1;
5814 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5816 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5817 struct neon_type_el et
;
5818 if (group_type
== GROUP_MVE
5819 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5821 inst
.operands
[i
].immisreg
= 2;
5822 inst
.operands
[i
].imm
= reg
;
5824 if (skip_past_comma (&p
) == SUCCESS
)
5826 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5828 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5829 inst
.relocs
[0].exp
.X_add_number
= 0;
5832 return PARSE_OPERAND_FAIL
;
5835 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5837 inst
.operands
[i
].imm
= reg
;
5838 inst
.operands
[i
].immisreg
= 1;
5840 if (skip_past_comma (&p
) == SUCCESS
)
5841 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5842 return PARSE_OPERAND_FAIL
;
5844 else if (skip_past_char (&p
, ':') == SUCCESS
)
5846 /* FIXME: '@' should be used here, but it's filtered out by generic
5847 code before we get to see it here. This may be subject to
5849 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5851 if (result
!= PARSE_OPERAND_SUCCESS
)
5856 if (inst
.operands
[i
].negative
)
5858 inst
.operands
[i
].negative
= 0;
5862 if (group_relocations
5863 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5865 struct group_reloc_table_entry
*entry
;
5867 /* Skip over the #: or : sequence. */
5873 /* Try to parse a group relocation. Anything else is an
5875 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5877 inst
.error
= _("unknown group relocation");
5878 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5881 /* We now have the group relocation table entry corresponding to
5882 the name in the assembler source. Next, we parse the
5884 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5885 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5887 /* Record the relocation type. */
5892 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5897 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5902 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5909 if (inst
.relocs
[0].type
== 0)
5911 inst
.error
= _("this group relocation is not allowed on this instruction");
5912 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5919 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5920 return PARSE_OPERAND_FAIL
;
5921 /* If the offset is 0, find out if it's a +0 or -0. */
5922 if (inst
.relocs
[0].exp
.X_op
== O_constant
5923 && inst
.relocs
[0].exp
.X_add_number
== 0)
5925 skip_whitespace (q
);
5929 skip_whitespace (q
);
5932 inst
.operands
[i
].negative
= 1;
5937 else if (skip_past_char (&p
, ':') == SUCCESS
)
5939 /* FIXME: '@' should be used here, but it's filtered out by generic code
5940 before we get to see it here. This may be subject to change. */
5941 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5943 if (result
!= PARSE_OPERAND_SUCCESS
)
5947 if (skip_past_char (&p
, ']') == FAIL
)
5949 inst
.error
= _("']' expected");
5950 return PARSE_OPERAND_FAIL
;
5953 if (skip_past_char (&p
, '!') == SUCCESS
)
5954 inst
.operands
[i
].writeback
= 1;
5956 else if (skip_past_comma (&p
) == SUCCESS
)
5958 if (skip_past_char (&p
, '{') == SUCCESS
)
5960 /* [Rn], {expr} - unindexed, with option */
5961 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5962 0, 255, TRUE
) == FAIL
)
5963 return PARSE_OPERAND_FAIL
;
5965 if (skip_past_char (&p
, '}') == FAIL
)
5967 inst
.error
= _("'}' expected at end of 'option' field");
5968 return PARSE_OPERAND_FAIL
;
5970 if (inst
.operands
[i
].preind
)
5972 inst
.error
= _("cannot combine index with option");
5973 return PARSE_OPERAND_FAIL
;
5976 return PARSE_OPERAND_SUCCESS
;
5980 inst
.operands
[i
].postind
= 1;
5981 inst
.operands
[i
].writeback
= 1;
5983 if (inst
.operands
[i
].preind
)
5985 inst
.error
= _("cannot combine pre- and post-indexing");
5986 return PARSE_OPERAND_FAIL
;
5990 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5992 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5993 struct neon_type_el et
;
5994 if (group_type
== GROUP_MVE
5995 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5997 inst
.operands
[i
].immisreg
= 2;
5998 inst
.operands
[i
].imm
= reg
;
6000 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6002 /* We might be using the immediate for alignment already. If we
6003 are, OR the register number into the low-order bits. */
6004 if (inst
.operands
[i
].immisalign
)
6005 inst
.operands
[i
].imm
|= reg
;
6007 inst
.operands
[i
].imm
= reg
;
6008 inst
.operands
[i
].immisreg
= 1;
6010 if (skip_past_comma (&p
) == SUCCESS
)
6011 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6012 return PARSE_OPERAND_FAIL
;
6018 if (inst
.operands
[i
].negative
)
6020 inst
.operands
[i
].negative
= 0;
6023 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6024 return PARSE_OPERAND_FAIL
;
6025 /* If the offset is 0, find out if it's a +0 or -0. */
6026 if (inst
.relocs
[0].exp
.X_op
== O_constant
6027 && inst
.relocs
[0].exp
.X_add_number
== 0)
6029 skip_whitespace (q
);
6033 skip_whitespace (q
);
6036 inst
.operands
[i
].negative
= 1;
6042 /* If at this point neither .preind nor .postind is set, we have a
6043 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6044 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6046 inst
.operands
[i
].preind
= 1;
6047 inst
.relocs
[0].exp
.X_op
= O_constant
;
6048 inst
.relocs
[0].exp
.X_add_number
= 0;
6051 return PARSE_OPERAND_SUCCESS
;
6055 parse_address (char **str
, int i
)
6057 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6061 static parse_operand_result
6062 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6064 return parse_address_main (str
, i
, 1, type
);
6067 /* Parse an operand for a MOVW or MOVT instruction. */
6069 parse_half (char **str
)
6074 skip_past_char (&p
, '#');
6075 if (strncasecmp (p
, ":lower16:", 9) == 0)
6076 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6077 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6078 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6080 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6083 skip_whitespace (p
);
6086 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6089 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6091 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6093 inst
.error
= _("constant expression expected");
6096 if (inst
.relocs
[0].exp
.X_add_number
< 0
6097 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6099 inst
.error
= _("immediate value out of range");
6107 /* Miscellaneous. */
6109 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6110 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6112 parse_psr (char **str
, bfd_boolean lhs
)
6115 unsigned long psr_field
;
6116 const struct asm_psr
*psr
;
6118 bfd_boolean is_apsr
= FALSE
;
6119 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6121 /* PR gas/12698: If the user has specified -march=all then m_profile will
6122 be TRUE, but we want to ignore it in this case as we are building for any
6123 CPU type, including non-m variants. */
6124 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6127 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6128 feature for ease of use and backwards compatibility. */
6130 if (strncasecmp (p
, "SPSR", 4) == 0)
6133 goto unsupported_psr
;
6135 psr_field
= SPSR_BIT
;
6137 else if (strncasecmp (p
, "CPSR", 4) == 0)
6140 goto unsupported_psr
;
6144 else if (strncasecmp (p
, "APSR", 4) == 0)
6146 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6147 and ARMv7-R architecture CPUs. */
6156 while (ISALNUM (*p
) || *p
== '_');
6158 if (strncasecmp (start
, "iapsr", 5) == 0
6159 || strncasecmp (start
, "eapsr", 5) == 0
6160 || strncasecmp (start
, "xpsr", 4) == 0
6161 || strncasecmp (start
, "psr", 3) == 0)
6162 p
= start
+ strcspn (start
, "rR") + 1;
6164 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6170 /* If APSR is being written, a bitfield may be specified. Note that
6171 APSR itself is handled above. */
6172 if (psr
->field
<= 3)
6174 psr_field
= psr
->field
;
6180 /* M-profile MSR instructions have the mask field set to "10", except
6181 *PSR variants which modify APSR, which may use a different mask (and
6182 have been handled already). Do that by setting the PSR_f field
6184 return psr
->field
| (lhs
? PSR_f
: 0);
6187 goto unsupported_psr
;
6193 /* A suffix follows. */
6199 while (ISALNUM (*p
) || *p
== '_');
6203 /* APSR uses a notation for bits, rather than fields. */
6204 unsigned int nzcvq_bits
= 0;
6205 unsigned int g_bit
= 0;
6208 for (bit
= start
; bit
!= p
; bit
++)
6210 switch (TOLOWER (*bit
))
6213 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6217 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6221 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6225 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6229 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6233 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6237 inst
.error
= _("unexpected bit specified after APSR");
6242 if (nzcvq_bits
== 0x1f)
6247 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6249 inst
.error
= _("selected processor does not "
6250 "support DSP extension");
6257 if ((nzcvq_bits
& 0x20) != 0
6258 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6259 || (g_bit
& 0x2) != 0)
6261 inst
.error
= _("bad bitmask specified after APSR");
6267 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6272 psr_field
|= psr
->field
;
6278 goto error
; /* Garbage after "[CS]PSR". */
6280 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6281 is deprecated, but allow it anyway. */
6285 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6288 else if (!m_profile
)
6289 /* These bits are never right for M-profile devices: don't set them
6290 (only code paths which read/write APSR reach here). */
6291 psr_field
|= (PSR_c
| PSR_f
);
6297 inst
.error
= _("selected processor does not support requested special "
6298 "purpose register");
6302 inst
.error
= _("flag for {c}psr instruction expected");
6307 parse_sys_vldr_vstr (char **str
)
6316 {"FPSCR", 0x1, 0x0},
6317 {"FPSCR_nzcvqc", 0x2, 0x0},
6320 {"FPCXTNS", 0x6, 0x1},
6321 {"FPCXTS", 0x7, 0x1}
6323 char *op_end
= strchr (*str
, ',');
6324 size_t op_strlen
= op_end
- *str
;
6326 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6328 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6330 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6339 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6340 value suitable for splatting into the AIF field of the instruction. */
6343 parse_cps_flags (char **str
)
6352 case '\0': case ',':
6355 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6356 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6357 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6360 inst
.error
= _("unrecognized CPS flag");
6365 if (saw_a_flag
== 0)
6367 inst
.error
= _("missing CPS flags");
6375 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6376 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6379 parse_endian_specifier (char **str
)
6384 if (strncasecmp (s
, "BE", 2))
6386 else if (strncasecmp (s
, "LE", 2))
6390 inst
.error
= _("valid endian specifiers are be or le");
6394 if (ISALNUM (s
[2]) || s
[2] == '_')
6396 inst
.error
= _("valid endian specifiers are be or le");
6401 return little_endian
;
6404 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6405 value suitable for poking into the rotate field of an sxt or sxta
6406 instruction, or FAIL on error. */
6409 parse_ror (char **str
)
6414 if (strncasecmp (s
, "ROR", 3) == 0)
6418 inst
.error
= _("missing rotation field after comma");
6422 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6427 case 0: *str
= s
; return 0x0;
6428 case 8: *str
= s
; return 0x1;
6429 case 16: *str
= s
; return 0x2;
6430 case 24: *str
= s
; return 0x3;
6433 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6438 /* Parse a conditional code (from conds[] below). The value returned is in the
6439 range 0 .. 14, or FAIL. */
6441 parse_cond (char **str
)
6444 const struct asm_cond
*c
;
6446 /* Condition codes are always 2 characters, so matching up to
6447 3 characters is sufficient. */
6452 while (ISALPHA (*q
) && n
< 3)
6454 cond
[n
] = TOLOWER (*q
);
6459 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6462 inst
.error
= _("condition required");
6470 /* Parse an option for a barrier instruction. Returns the encoding for the
6473 parse_barrier (char **str
)
6476 const struct asm_barrier_opt
*o
;
6479 while (ISALPHA (*q
))
6482 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6487 if (!mark_feature_used (&o
->arch
))
6494 /* Parse the operands of a table branch instruction. Similar to a memory
6497 parse_tb (char **str
)
6502 if (skip_past_char (&p
, '[') == FAIL
)
6504 inst
.error
= _("'[' expected");
6508 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6510 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6513 inst
.operands
[0].reg
= reg
;
6515 if (skip_past_comma (&p
) == FAIL
)
6517 inst
.error
= _("',' expected");
6521 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6523 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6526 inst
.operands
[0].imm
= reg
;
6528 if (skip_past_comma (&p
) == SUCCESS
)
6530 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6532 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6534 inst
.error
= _("invalid shift");
6537 inst
.operands
[0].shifted
= 1;
6540 if (skip_past_char (&p
, ']') == FAIL
)
6542 inst
.error
= _("']' expected");
6549 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6550 information on the types the operands can take and how they are encoded.
6551 Up to four operands may be read; this function handles setting the
6552 ".present" field for each read operand itself.
6553 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6554 else returns FAIL. */
6557 parse_neon_mov (char **str
, int *which_operand
)
6559 int i
= *which_operand
, val
;
6560 enum arm_reg_type rtype
;
6562 struct neon_type_el optype
;
6564 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6566 /* Cases 17 or 19. */
6567 inst
.operands
[i
].reg
= val
;
6568 inst
.operands
[i
].isvec
= 1;
6569 inst
.operands
[i
].isscalar
= 2;
6570 inst
.operands
[i
].vectype
= optype
;
6571 inst
.operands
[i
++].present
= 1;
6573 if (skip_past_comma (&ptr
) == FAIL
)
6576 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6578 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6579 inst
.operands
[i
].reg
= val
;
6580 inst
.operands
[i
].isreg
= 1;
6581 inst
.operands
[i
].present
= 1;
6583 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6585 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6586 inst
.operands
[i
].reg
= val
;
6587 inst
.operands
[i
].isvec
= 1;
6588 inst
.operands
[i
].isscalar
= 2;
6589 inst
.operands
[i
].vectype
= optype
;
6590 inst
.operands
[i
++].present
= 1;
6592 if (skip_past_comma (&ptr
) == FAIL
)
6595 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6598 inst
.operands
[i
].reg
= val
;
6599 inst
.operands
[i
].isreg
= 1;
6600 inst
.operands
[i
++].present
= 1;
6602 if (skip_past_comma (&ptr
) == FAIL
)
6605 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6608 inst
.operands
[i
].reg
= val
;
6609 inst
.operands
[i
].isreg
= 1;
6610 inst
.operands
[i
].present
= 1;
6614 first_error (_("expected ARM or MVE vector register"));
6618 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6620 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6621 inst
.operands
[i
].reg
= val
;
6622 inst
.operands
[i
].isscalar
= 1;
6623 inst
.operands
[i
].vectype
= optype
;
6624 inst
.operands
[i
++].present
= 1;
6626 if (skip_past_comma (&ptr
) == FAIL
)
6629 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6632 inst
.operands
[i
].reg
= val
;
6633 inst
.operands
[i
].isreg
= 1;
6634 inst
.operands
[i
].present
= 1;
6636 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6638 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6641 /* Cases 0, 1, 2, 3, 5 (D only). */
6642 if (skip_past_comma (&ptr
) == FAIL
)
6645 inst
.operands
[i
].reg
= val
;
6646 inst
.operands
[i
].isreg
= 1;
6647 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6648 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6649 inst
.operands
[i
].isvec
= 1;
6650 inst
.operands
[i
].vectype
= optype
;
6651 inst
.operands
[i
++].present
= 1;
6653 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6655 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6656 Case 13: VMOV <Sd>, <Rm> */
6657 inst
.operands
[i
].reg
= val
;
6658 inst
.operands
[i
].isreg
= 1;
6659 inst
.operands
[i
].present
= 1;
6661 if (rtype
== REG_TYPE_NQ
)
6663 first_error (_("can't use Neon quad register here"));
6666 else if (rtype
!= REG_TYPE_VFS
)
6669 if (skip_past_comma (&ptr
) == FAIL
)
6671 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6673 inst
.operands
[i
].reg
= val
;
6674 inst
.operands
[i
].isreg
= 1;
6675 inst
.operands
[i
].present
= 1;
6678 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6681 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6682 Case 1: VMOV<c><q> <Dd>, <Dm>
6683 Case 8: VMOV.F32 <Sd>, <Sm>
6684 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6686 inst
.operands
[i
].reg
= val
;
6687 inst
.operands
[i
].isreg
= 1;
6688 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6689 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6690 inst
.operands
[i
].isvec
= 1;
6691 inst
.operands
[i
].vectype
= optype
;
6692 inst
.operands
[i
].present
= 1;
6694 if (skip_past_comma (&ptr
) == SUCCESS
)
6699 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6702 inst
.operands
[i
].reg
= val
;
6703 inst
.operands
[i
].isreg
= 1;
6704 inst
.operands
[i
++].present
= 1;
6706 if (skip_past_comma (&ptr
) == FAIL
)
6709 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6712 inst
.operands
[i
].reg
= val
;
6713 inst
.operands
[i
].isreg
= 1;
6714 inst
.operands
[i
].present
= 1;
6717 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6718 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6719 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6720 Case 10: VMOV.F32 <Sd>, #<imm>
6721 Case 11: VMOV.F64 <Dd>, #<imm> */
6722 inst
.operands
[i
].immisfloat
= 1;
6723 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6725 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6726 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6730 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6734 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6736 /* Cases 6, 7, 16, 18. */
6737 inst
.operands
[i
].reg
= val
;
6738 inst
.operands
[i
].isreg
= 1;
6739 inst
.operands
[i
++].present
= 1;
6741 if (skip_past_comma (&ptr
) == FAIL
)
6744 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6746 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6747 inst
.operands
[i
].reg
= val
;
6748 inst
.operands
[i
].isscalar
= 2;
6749 inst
.operands
[i
].present
= 1;
6750 inst
.operands
[i
].vectype
= optype
;
6752 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6754 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6755 inst
.operands
[i
].reg
= val
;
6756 inst
.operands
[i
].isscalar
= 1;
6757 inst
.operands
[i
].present
= 1;
6758 inst
.operands
[i
].vectype
= optype
;
6760 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6762 inst
.operands
[i
].reg
= val
;
6763 inst
.operands
[i
].isreg
= 1;
6764 inst
.operands
[i
++].present
= 1;
6766 if (skip_past_comma (&ptr
) == FAIL
)
6769 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6772 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6774 inst
.operands
[i
].reg
= val
;
6775 inst
.operands
[i
].isreg
= 1;
6776 inst
.operands
[i
].isvec
= 1;
6777 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6778 inst
.operands
[i
].vectype
= optype
;
6779 inst
.operands
[i
].present
= 1;
6781 if (rtype
== REG_TYPE_VFS
)
6785 if (skip_past_comma (&ptr
) == FAIL
)
6787 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6790 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6793 inst
.operands
[i
].reg
= val
;
6794 inst
.operands
[i
].isreg
= 1;
6795 inst
.operands
[i
].isvec
= 1;
6796 inst
.operands
[i
].issingle
= 1;
6797 inst
.operands
[i
].vectype
= optype
;
6798 inst
.operands
[i
].present
= 1;
6803 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6806 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6807 inst
.operands
[i
].reg
= val
;
6808 inst
.operands
[i
].isvec
= 1;
6809 inst
.operands
[i
].isscalar
= 2;
6810 inst
.operands
[i
].vectype
= optype
;
6811 inst
.operands
[i
++].present
= 1;
6813 if (skip_past_comma (&ptr
) == FAIL
)
6816 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6819 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6822 inst
.operands
[i
].reg
= val
;
6823 inst
.operands
[i
].isvec
= 1;
6824 inst
.operands
[i
].isscalar
= 2;
6825 inst
.operands
[i
].vectype
= optype
;
6826 inst
.operands
[i
].present
= 1;
6830 first_error (_("VFP single, double or MVE vector register"
6836 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6840 inst
.operands
[i
].reg
= val
;
6841 inst
.operands
[i
].isreg
= 1;
6842 inst
.operands
[i
].isvec
= 1;
6843 inst
.operands
[i
].issingle
= 1;
6844 inst
.operands
[i
].vectype
= optype
;
6845 inst
.operands
[i
].present
= 1;
6850 first_error (_("parse error"));
6854 /* Successfully parsed the operands. Update args. */
6860 first_error (_("expected comma"));
6864 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6868 /* Use this macro when the operand constraints are different
6869 for ARM and THUMB (e.g. ldrd). */
6870 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6871 ((arm_operand) | ((thumb_operand) << 16))
6873 /* Matcher codes for parse_operands. */
6874 enum operand_parse_code
6876 OP_stop
, /* end of line */
6878 OP_RR
, /* ARM register */
6879 OP_RRnpc
, /* ARM register, not r15 */
6880 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6881 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6882 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6883 optional trailing ! */
6884 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6885 OP_RCP
, /* Coprocessor number */
6886 OP_RCN
, /* Coprocessor register */
6887 OP_RF
, /* FPA register */
6888 OP_RVS
, /* VFP single precision register */
6889 OP_RVD
, /* VFP double precision register (0..15) */
6890 OP_RND
, /* Neon double precision register (0..31) */
6891 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6892 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6894 OP_RNQ
, /* Neon quad precision register */
6895 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6896 OP_RVSD
, /* VFP single or double precision register */
6897 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6898 OP_RNSD
, /* Neon single or double precision register */
6899 OP_RNDQ
, /* Neon double or quad precision register */
6900 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6901 OP_RNSDQ
, /* Neon single, double or quad precision register */
6902 OP_RNSC
, /* Neon scalar D[X] */
6903 OP_RVC
, /* VFP control register */
6904 OP_RMF
, /* Maverick F register */
6905 OP_RMD
, /* Maverick D register */
6906 OP_RMFX
, /* Maverick FX register */
6907 OP_RMDX
, /* Maverick DX register */
6908 OP_RMAX
, /* Maverick AX register */
6909 OP_RMDS
, /* Maverick DSPSC register */
6910 OP_RIWR
, /* iWMMXt wR register */
6911 OP_RIWC
, /* iWMMXt wC register */
6912 OP_RIWG
, /* iWMMXt wCG register */
6913 OP_RXA
, /* XScale accumulator register */
6915 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6917 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6919 OP_RMQ
, /* MVE vector register. */
6921 /* New operands for Armv8.1-M Mainline. */
6922 OP_LR
, /* ARM LR register */
6923 OP_RRe
, /* ARM register, only even numbered. */
6924 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6925 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6927 OP_REGLST
, /* ARM register list */
6928 OP_CLRMLST
, /* CLRM register list */
6929 OP_VRSLST
, /* VFP single-precision register list */
6930 OP_VRDLST
, /* VFP double-precision register list */
6931 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6932 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6933 OP_NSTRLST
, /* Neon element/structure list */
6934 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6935 OP_MSTRLST2
, /* MVE vector list with two elements. */
6936 OP_MSTRLST4
, /* MVE vector list with four elements. */
6938 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6939 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6940 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6941 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6942 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6943 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6944 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6946 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6947 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6948 OP_VMOV
, /* Neon VMOV operands. */
6949 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6950 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6951 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6952 OP_VLDR
, /* VLDR operand. */
6954 OP_I0
, /* immediate zero */
6955 OP_I7
, /* immediate value 0 .. 7 */
6956 OP_I15
, /* 0 .. 15 */
6957 OP_I16
, /* 1 .. 16 */
6958 OP_I16z
, /* 0 .. 16 */
6959 OP_I31
, /* 0 .. 31 */
6960 OP_I31w
, /* 0 .. 31, optional trailing ! */
6961 OP_I32
, /* 1 .. 32 */
6962 OP_I32z
, /* 0 .. 32 */
6963 OP_I63
, /* 0 .. 63 */
6964 OP_I63s
, /* -64 .. 63 */
6965 OP_I64
, /* 1 .. 64 */
6966 OP_I64z
, /* 0 .. 64 */
6967 OP_I255
, /* 0 .. 255 */
6969 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6970 OP_I7b
, /* 0 .. 7 */
6971 OP_I15b
, /* 0 .. 15 */
6972 OP_I31b
, /* 0 .. 31 */
6974 OP_SH
, /* shifter operand */
6975 OP_SHG
, /* shifter operand with possible group relocation */
6976 OP_ADDR
, /* Memory address expression (any mode) */
6977 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
6978 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6979 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6980 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6981 OP_EXP
, /* arbitrary expression */
6982 OP_EXPi
, /* same, with optional immediate prefix */
6983 OP_EXPr
, /* same, with optional relocation suffix */
6984 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
6985 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6986 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6987 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6989 OP_CPSF
, /* CPS flags */
6990 OP_ENDI
, /* Endianness specifier */
6991 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6992 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6993 OP_COND
, /* conditional code */
6994 OP_TB
, /* Table branch. */
6996 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6998 OP_RRnpc_I0
, /* ARM register or literal 0 */
6999 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7000 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7001 OP_RF_IF
, /* FPA register or immediate */
7002 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7003 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7005 /* Optional operands. */
7006 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7007 OP_oI31b
, /* 0 .. 31 */
7008 OP_oI32b
, /* 1 .. 32 */
7009 OP_oI32z
, /* 0 .. 32 */
7010 OP_oIffffb
, /* 0 .. 65535 */
7011 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7013 OP_oRR
, /* ARM register */
7014 OP_oLR
, /* ARM LR register */
7015 OP_oRRnpc
, /* ARM register, not the PC */
7016 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7017 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7018 OP_oRND
, /* Optional Neon double precision register */
7019 OP_oRNQ
, /* Optional Neon quad precision register */
7020 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7021 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7022 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7023 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7025 OP_oSHll
, /* LSL immediate */
7026 OP_oSHar
, /* ASR immediate */
7027 OP_oSHllar
, /* LSL or ASR immediate */
7028 OP_oROR
, /* ROR 0/8/16/24 */
7029 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7031 /* Some pre-defined mixed (ARM/THUMB) operands. */
7032 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7033 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7034 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7036 OP_FIRST_OPTIONAL
= OP_oI7b
7039 /* Generic instruction operand parser. This does no encoding and no
7040 semantic validation; it merely squirrels values away in the inst
7041 structure. Returns SUCCESS or FAIL depending on whether the
7042 specified grammar matched. */
7044 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7046 unsigned const int *upat
= pattern
;
7047 char *backtrack_pos
= 0;
7048 const char *backtrack_error
= 0;
7049 int i
, val
= 0, backtrack_index
= 0;
7050 enum arm_reg_type rtype
;
7051 parse_operand_result result
;
7052 unsigned int op_parse_code
;
7053 bfd_boolean partial_match
;
7055 #define po_char_or_fail(chr) \
7058 if (skip_past_char (&str, chr) == FAIL) \
7063 #define po_reg_or_fail(regtype) \
7066 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7067 & inst.operands[i].vectype); \
7070 first_error (_(reg_expected_msgs[regtype])); \
7073 inst.operands[i].reg = val; \
7074 inst.operands[i].isreg = 1; \
7075 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7076 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7077 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7078 || rtype == REG_TYPE_VFD \
7079 || rtype == REG_TYPE_NQ); \
7083 #define po_reg_or_goto(regtype, label) \
7086 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7087 & inst.operands[i].vectype); \
7091 inst.operands[i].reg = val; \
7092 inst.operands[i].isreg = 1; \
7093 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7094 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7095 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7096 || rtype == REG_TYPE_VFD \
7097 || rtype == REG_TYPE_NQ); \
7101 #define po_imm_or_fail(min, max, popt) \
7104 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7106 inst.operands[i].imm = val; \
7110 #define po_scalar_or_goto(elsz, label, reg_type) \
7113 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7117 inst.operands[i].reg = val; \
7118 inst.operands[i].isscalar = 1; \
7122 #define po_misc_or_fail(expr) \
7130 #define po_misc_or_fail_no_backtrack(expr) \
7134 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7135 backtrack_pos = 0; \
7136 if (result != PARSE_OPERAND_SUCCESS) \
7141 #define po_barrier_or_imm(str) \
7144 val = parse_barrier (&str); \
7145 if (val == FAIL && ! ISALPHA (*str)) \
7148 /* ISB can only take SY as an option. */ \
7149 || ((inst.instruction & 0xf0) == 0x60 \
7152 inst.error = _("invalid barrier type"); \
7153 backtrack_pos = 0; \
7159 skip_whitespace (str
);
7161 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7163 op_parse_code
= upat
[i
];
7164 if (op_parse_code
>= 1<<16)
7165 op_parse_code
= thumb
? (op_parse_code
>> 16)
7166 : (op_parse_code
& ((1<<16)-1));
7168 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7170 /* Remember where we are in case we need to backtrack. */
7171 backtrack_pos
= str
;
7172 backtrack_error
= inst
.error
;
7173 backtrack_index
= i
;
7176 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7177 po_char_or_fail (',');
7179 switch (op_parse_code
)
7191 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7192 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7193 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7194 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7195 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7196 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7199 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7203 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7206 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7208 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7210 /* Also accept generic coprocessor regs for unknown registers. */
7212 po_reg_or_fail (REG_TYPE_CN
);
7214 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7215 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7216 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7217 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7218 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7219 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7220 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7221 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7222 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7223 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7226 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7229 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7230 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7233 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7237 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7239 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7242 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7244 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7246 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7251 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7254 po_reg_or_fail (REG_TYPE_NSDQ
);
7258 po_reg_or_fail (REG_TYPE_MQ
);
7260 /* Neon scalar. Using an element size of 8 means that some invalid
7261 scalars are accepted here, so deal with those in later code. */
7262 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7266 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7269 po_imm_or_fail (0, 0, TRUE
);
7274 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7279 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7282 if (parse_ifimm_zero (&str
))
7283 inst
.operands
[i
].imm
= 0;
7287 = _("only floating point zero is allowed as immediate value");
7295 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7298 po_reg_or_fail (REG_TYPE_RN
);
7302 case OP_RNSDQ_RNSC_MQ
:
7303 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7308 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7312 po_reg_or_fail (REG_TYPE_NSDQ
);
7319 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7322 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7325 po_reg_or_fail (REG_TYPE_NSD
);
7331 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7334 po_reg_or_fail (REG_TYPE_NDQ
);
7340 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7343 po_reg_or_fail (REG_TYPE_VFD
);
7348 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7349 not careful then bad things might happen. */
7350 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7355 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7358 /* There's a possibility of getting a 64-bit immediate here, so
7359 we need special handling. */
7360 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7363 inst
.error
= _("immediate value is out of range");
7371 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7374 po_imm_or_fail (0, 63, TRUE
);
7379 po_char_or_fail ('[');
7380 po_reg_or_fail (REG_TYPE_RN
);
7381 po_char_or_fail (']');
7387 po_reg_or_fail (REG_TYPE_RN
);
7388 if (skip_past_char (&str
, '!') == SUCCESS
)
7389 inst
.operands
[i
].writeback
= 1;
7393 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7394 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7395 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7396 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7397 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7398 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7399 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7400 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7401 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7402 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7403 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7404 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7406 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7408 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7409 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7411 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7412 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7413 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7414 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7416 /* Immediate variants */
7418 po_char_or_fail ('{');
7419 po_imm_or_fail (0, 255, TRUE
);
7420 po_char_or_fail ('}');
7424 /* The expression parser chokes on a trailing !, so we have
7425 to find it first and zap it. */
7428 while (*s
&& *s
!= ',')
7433 inst
.operands
[i
].writeback
= 1;
7435 po_imm_or_fail (0, 31, TRUE
);
7443 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7448 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7453 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7455 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7457 val
= parse_reloc (&str
);
7460 inst
.error
= _("unrecognized relocation suffix");
7463 else if (val
!= BFD_RELOC_UNUSED
)
7465 inst
.operands
[i
].imm
= val
;
7466 inst
.operands
[i
].hasreloc
= 1;
7472 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7474 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7476 inst
.operands
[i
].hasreloc
= 1;
7478 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7480 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7481 inst
.operands
[i
].hasreloc
= 0;
7485 /* Operand for MOVW or MOVT. */
7487 po_misc_or_fail (parse_half (&str
));
7490 /* Register or expression. */
7491 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7492 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7494 /* Register or immediate. */
7495 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7496 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7498 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7500 if (!is_immediate_prefix (*str
))
7503 val
= parse_fpa_immediate (&str
);
7506 /* FPA immediates are encoded as registers 8-15.
7507 parse_fpa_immediate has already applied the offset. */
7508 inst
.operands
[i
].reg
= val
;
7509 inst
.operands
[i
].isreg
= 1;
7512 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7513 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7515 /* Two kinds of register. */
7518 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7520 || (rege
->type
!= REG_TYPE_MMXWR
7521 && rege
->type
!= REG_TYPE_MMXWC
7522 && rege
->type
!= REG_TYPE_MMXWCG
))
7524 inst
.error
= _("iWMMXt data or control register expected");
7527 inst
.operands
[i
].reg
= rege
->number
;
7528 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7534 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7536 || (rege
->type
!= REG_TYPE_MMXWC
7537 && rege
->type
!= REG_TYPE_MMXWCG
))
7539 inst
.error
= _("iWMMXt control register expected");
7542 inst
.operands
[i
].reg
= rege
->number
;
7543 inst
.operands
[i
].isreg
= 1;
7548 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7549 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7550 case OP_oROR
: val
= parse_ror (&str
); break;
7551 case OP_COND
: val
= parse_cond (&str
); break;
7552 case OP_oBARRIER_I15
:
7553 po_barrier_or_imm (str
); break;
7555 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7561 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7562 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7564 inst
.error
= _("Banked registers are not available with this "
7570 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7574 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7577 val
= parse_sys_vldr_vstr (&str
);
7581 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7584 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7586 if (strncasecmp (str
, "APSR_", 5) == 0)
7593 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7594 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7595 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7596 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7597 default: found
= 16;
7601 inst
.operands
[i
].isvec
= 1;
7602 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7603 inst
.operands
[i
].reg
= REG_PC
;
7610 po_misc_or_fail (parse_tb (&str
));
7613 /* Register lists. */
7615 val
= parse_reg_list (&str
, REGLIST_RN
);
7618 inst
.operands
[i
].writeback
= 1;
7624 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7628 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7633 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7638 /* Allow Q registers too. */
7639 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7640 REGLIST_NEON_D
, &partial_match
);
7644 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7645 REGLIST_VFP_S
, &partial_match
);
7646 inst
.operands
[i
].issingle
= 1;
7651 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7652 REGLIST_VFP_D_VPR
, &partial_match
);
7653 if (val
== FAIL
&& !partial_match
)
7656 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7657 REGLIST_VFP_S_VPR
, &partial_match
);
7658 inst
.operands
[i
].issingle
= 1;
7663 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7664 REGLIST_NEON_D
, &partial_match
);
7669 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7670 1, &inst
.operands
[i
].vectype
);
7671 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7675 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7676 0, &inst
.operands
[i
].vectype
);
7679 /* Addressing modes */
7681 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7685 po_misc_or_fail (parse_address (&str
, i
));
7689 po_misc_or_fail_no_backtrack (
7690 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7694 po_misc_or_fail_no_backtrack (
7695 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7699 po_misc_or_fail_no_backtrack (
7700 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7704 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7708 po_misc_or_fail_no_backtrack (
7709 parse_shifter_operand_group_reloc (&str
, i
));
7713 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7717 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7721 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7725 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7728 /* Various value-based sanity checks and shared operations. We
7729 do not signal immediate failures for the register constraints;
7730 this allows a syntax error to take precedence. */
7731 switch (op_parse_code
)
7739 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7740 inst
.error
= BAD_PC
;
7745 if (inst
.operands
[i
].isreg
)
7747 if (inst
.operands
[i
].reg
== REG_PC
)
7748 inst
.error
= BAD_PC
;
7749 else if (inst
.operands
[i
].reg
== REG_SP
7750 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7751 relaxed since ARMv8-A. */
7752 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7755 inst
.error
= BAD_SP
;
7761 if (inst
.operands
[i
].isreg
7762 && inst
.operands
[i
].reg
== REG_PC
7763 && (inst
.operands
[i
].writeback
|| thumb
))
7764 inst
.error
= BAD_PC
;
7768 if (inst
.operands
[i
].isreg
)
7777 case OP_oBARRIER_I15
:
7790 inst
.operands
[i
].imm
= val
;
7795 if (inst
.operands
[i
].reg
!= REG_LR
)
7796 inst
.error
= _("operand must be LR register");
7800 if (inst
.operands
[i
].isreg
7801 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7802 inst
.error
= BAD_ODD
;
7806 if (inst
.operands
[i
].isreg
)
7808 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7809 inst
.error
= BAD_EVEN
;
7810 else if (inst
.operands
[i
].reg
== REG_SP
)
7811 as_tsktsk (MVE_BAD_SP
);
7812 else if (inst
.operands
[i
].reg
== REG_PC
)
7813 inst
.error
= BAD_PC
;
7821 /* If we get here, this operand was successfully parsed. */
7822 inst
.operands
[i
].present
= 1;
7826 inst
.error
= BAD_ARGS
;
7831 /* The parse routine should already have set inst.error, but set a
7832 default here just in case. */
7834 inst
.error
= BAD_SYNTAX
;
7838 /* Do not backtrack over a trailing optional argument that
7839 absorbed some text. We will only fail again, with the
7840 'garbage following instruction' error message, which is
7841 probably less helpful than the current one. */
7842 if (backtrack_index
== i
&& backtrack_pos
!= str
7843 && upat
[i
+1] == OP_stop
)
7846 inst
.error
= BAD_SYNTAX
;
7850 /* Try again, skipping the optional argument at backtrack_pos. */
7851 str
= backtrack_pos
;
7852 inst
.error
= backtrack_error
;
7853 inst
.operands
[backtrack_index
].present
= 0;
7854 i
= backtrack_index
;
7858 /* Check that we have parsed all the arguments. */
7859 if (*str
!= '\0' && !inst
.error
)
7860 inst
.error
= _("garbage following instruction");
7862 return inst
.error
? FAIL
: SUCCESS
;
7865 #undef po_char_or_fail
7866 #undef po_reg_or_fail
7867 #undef po_reg_or_goto
7868 #undef po_imm_or_fail
7869 #undef po_scalar_or_fail
7870 #undef po_barrier_or_imm
7872 /* Shorthand macro for instruction encoding functions issuing errors. */
7873 #define constraint(expr, err) \
7884 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7885 instructions are unpredictable if these registers are used. This
7886 is the BadReg predicate in ARM's Thumb-2 documentation.
7888 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7889 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7890 #define reject_bad_reg(reg) \
7892 if (reg == REG_PC) \
7894 inst.error = BAD_PC; \
7897 else if (reg == REG_SP \
7898 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7900 inst.error = BAD_SP; \
7905 /* If REG is R13 (the stack pointer), warn that its use is
7907 #define warn_deprecated_sp(reg) \
7909 if (warn_on_deprecated && reg == REG_SP) \
7910 as_tsktsk (_("use of r13 is deprecated")); \
7913 /* Functions for operand encoding. ARM, then Thumb. */
7915 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7917 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7919 The only binary encoding difference is the Coprocessor number. Coprocessor
7920 9 is used for half-precision calculations or conversions. The format of the
7921 instruction is the same as the equivalent Coprocessor 10 instruction that
7922 exists for Single-Precision operation. */
7925 do_scalar_fp16_v82_encode (void)
7927 if (inst
.cond
< COND_ALWAYS
)
7928 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7929 " the behaviour is UNPREDICTABLE"));
7930 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7933 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7934 mark_feature_used (&arm_ext_fp16
);
7937 /* If VAL can be encoded in the immediate field of an ARM instruction,
7938 return the encoded form. Otherwise, return FAIL. */
7941 encode_arm_immediate (unsigned int val
)
7948 for (i
= 2; i
< 32; i
+= 2)
7949 if ((a
= rotate_left (val
, i
)) <= 0xff)
7950 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7955 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7956 return the encoded form. Otherwise, return FAIL. */
7958 encode_thumb32_immediate (unsigned int val
)
7965 for (i
= 1; i
<= 24; i
++)
7968 if ((val
& ~(0xff << i
)) == 0)
7969 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7973 if (val
== ((a
<< 16) | a
))
7975 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7979 if (val
== ((a
<< 16) | a
))
7980 return 0x200 | (a
>> 8);
7984 /* Encode a VFP SP or DP register number into inst.instruction. */
7987 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7989 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7992 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7995 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7998 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8003 first_error (_("D register out of range for selected VFP version"));
8011 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8015 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8019 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8023 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8027 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8031 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8039 /* Encode a <shift> in an ARM-format instruction. The immediate,
8040 if any, is handled by md_apply_fix. */
8042 encode_arm_shift (int i
)
8044 /* register-shifted register. */
8045 if (inst
.operands
[i
].immisreg
)
8048 for (op_index
= 0; op_index
<= i
; ++op_index
)
8050 /* Check the operand only when it's presented. In pre-UAL syntax,
8051 if the destination register is the same as the first operand, two
8052 register form of the instruction can be used. */
8053 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8054 && inst
.operands
[op_index
].reg
== REG_PC
)
8055 as_warn (UNPRED_REG ("r15"));
8058 if (inst
.operands
[i
].imm
== REG_PC
)
8059 as_warn (UNPRED_REG ("r15"));
8062 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8063 inst
.instruction
|= SHIFT_ROR
<< 5;
8066 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8067 if (inst
.operands
[i
].immisreg
)
8069 inst
.instruction
|= SHIFT_BY_REG
;
8070 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8073 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8078 encode_arm_shifter_operand (int i
)
8080 if (inst
.operands
[i
].isreg
)
8082 inst
.instruction
|= inst
.operands
[i
].reg
;
8083 encode_arm_shift (i
);
8087 inst
.instruction
|= INST_IMMEDIATE
;
8088 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8089 inst
.instruction
|= inst
.operands
[i
].imm
;
8093 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8095 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8098 Generate an error if the operand is not a register. */
8099 constraint (!inst
.operands
[i
].isreg
,
8100 _("Instruction does not support =N addresses"));
8102 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8104 if (inst
.operands
[i
].preind
)
8108 inst
.error
= _("instruction does not accept preindexed addressing");
8111 inst
.instruction
|= PRE_INDEX
;
8112 if (inst
.operands
[i
].writeback
)
8113 inst
.instruction
|= WRITE_BACK
;
8116 else if (inst
.operands
[i
].postind
)
8118 gas_assert (inst
.operands
[i
].writeback
);
8120 inst
.instruction
|= WRITE_BACK
;
8122 else /* unindexed - only for coprocessor */
8124 inst
.error
= _("instruction does not accept unindexed addressing");
8128 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8129 && (((inst
.instruction
& 0x000f0000) >> 16)
8130 == ((inst
.instruction
& 0x0000f000) >> 12)))
8131 as_warn ((inst
.instruction
& LOAD_BIT
)
8132 ? _("destination register same as write-back base")
8133 : _("source register same as write-back base"));
8136 /* inst.operands[i] was set up by parse_address. Encode it into an
8137 ARM-format mode 2 load or store instruction. If is_t is true,
8138 reject forms that cannot be used with a T instruction (i.e. not
8141 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8143 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8145 encode_arm_addr_mode_common (i
, is_t
);
8147 if (inst
.operands
[i
].immisreg
)
8149 constraint ((inst
.operands
[i
].imm
== REG_PC
8150 || (is_pc
&& inst
.operands
[i
].writeback
)),
8152 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8153 inst
.instruction
|= inst
.operands
[i
].imm
;
8154 if (!inst
.operands
[i
].negative
)
8155 inst
.instruction
|= INDEX_UP
;
8156 if (inst
.operands
[i
].shifted
)
8158 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8159 inst
.instruction
|= SHIFT_ROR
<< 5;
8162 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8163 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8167 else /* immediate offset in inst.relocs[0] */
8169 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8171 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8173 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8174 cannot use PC in addressing.
8175 PC cannot be used in writeback addressing, either. */
8176 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8179 /* Use of PC in str is deprecated for ARMv7. */
8180 if (warn_on_deprecated
8182 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8183 as_tsktsk (_("use of PC in this instruction is deprecated"));
8186 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8188 /* Prefer + for zero encoded value. */
8189 if (!inst
.operands
[i
].negative
)
8190 inst
.instruction
|= INDEX_UP
;
8191 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8196 /* inst.operands[i] was set up by parse_address. Encode it into an
8197 ARM-format mode 3 load or store instruction. Reject forms that
8198 cannot be used with such instructions. If is_t is true, reject
8199 forms that cannot be used with a T instruction (i.e. not
8202 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8204 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8206 inst
.error
= _("instruction does not accept scaled register index");
8210 encode_arm_addr_mode_common (i
, is_t
);
8212 if (inst
.operands
[i
].immisreg
)
8214 constraint ((inst
.operands
[i
].imm
== REG_PC
8215 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8217 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8219 inst
.instruction
|= inst
.operands
[i
].imm
;
8220 if (!inst
.operands
[i
].negative
)
8221 inst
.instruction
|= INDEX_UP
;
8223 else /* immediate offset in inst.relocs[0] */
8225 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8226 && inst
.operands
[i
].writeback
),
8228 inst
.instruction
|= HWOFFSET_IMM
;
8229 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8231 /* Prefer + for zero encoded value. */
8232 if (!inst
.operands
[i
].negative
)
8233 inst
.instruction
|= INDEX_UP
;
8235 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8240 /* Write immediate bits [7:0] to the following locations:
8242 |28/24|23 19|18 16|15 4|3 0|
8243 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8245 This function is used by VMOV/VMVN/VORR/VBIC. */
8248 neon_write_immbits (unsigned immbits
)
8250 inst
.instruction
|= immbits
& 0xf;
8251 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8252 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8255 /* Invert low-order SIZE bits of XHI:XLO. */
8258 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8260 unsigned immlo
= xlo
? *xlo
: 0;
8261 unsigned immhi
= xhi
? *xhi
: 0;
8266 immlo
= (~immlo
) & 0xff;
8270 immlo
= (~immlo
) & 0xffff;
8274 immhi
= (~immhi
) & 0xffffffff;
8278 immlo
= (~immlo
) & 0xffffffff;
8292 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8296 neon_bits_same_in_bytes (unsigned imm
)
8298 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8299 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8300 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8301 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8304 /* For immediate of above form, return 0bABCD. */
8307 neon_squash_bits (unsigned imm
)
8309 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8310 | ((imm
& 0x01000000) >> 21);
8313 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8316 neon_qfloat_bits (unsigned imm
)
8318 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8321 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8322 the instruction. *OP is passed as the initial value of the op field, and
8323 may be set to a different value depending on the constant (i.e.
8324 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8325 MVN). If the immediate looks like a repeated pattern then also
8326 try smaller element sizes. */
8329 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8330 unsigned *immbits
, int *op
, int size
,
8331 enum neon_el_type type
)
8333 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8335 if (type
== NT_float
&& !float_p
)
8338 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8340 if (size
!= 32 || *op
== 1)
8342 *immbits
= neon_qfloat_bits (immlo
);
8348 if (neon_bits_same_in_bytes (immhi
)
8349 && neon_bits_same_in_bytes (immlo
))
8353 *immbits
= (neon_squash_bits (immhi
) << 4)
8354 | neon_squash_bits (immlo
);
8365 if (immlo
== (immlo
& 0x000000ff))
8370 else if (immlo
== (immlo
& 0x0000ff00))
8372 *immbits
= immlo
>> 8;
8375 else if (immlo
== (immlo
& 0x00ff0000))
8377 *immbits
= immlo
>> 16;
8380 else if (immlo
== (immlo
& 0xff000000))
8382 *immbits
= immlo
>> 24;
8385 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8387 *immbits
= (immlo
>> 8) & 0xff;
8390 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8392 *immbits
= (immlo
>> 16) & 0xff;
8396 if ((immlo
& 0xffff) != (immlo
>> 16))
8403 if (immlo
== (immlo
& 0x000000ff))
8408 else if (immlo
== (immlo
& 0x0000ff00))
8410 *immbits
= immlo
>> 8;
8414 if ((immlo
& 0xff) != (immlo
>> 8))
8419 if (immlo
== (immlo
& 0x000000ff))
8421 /* Don't allow MVN with 8-bit immediate. */
8431 #if defined BFD_HOST_64_BIT
8432 /* Returns TRUE if double precision value V may be cast
8433 to single precision without loss of accuracy. */
8436 is_double_a_single (bfd_int64_t v
)
8438 int exp
= (int)((v
>> 52) & 0x7FF);
8439 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8441 return (exp
== 0 || exp
== 0x7FF
8442 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8443 && (mantissa
& 0x1FFFFFFFl
) == 0;
8446 /* Returns a double precision value casted to single precision
8447 (ignoring the least significant bits in exponent and mantissa). */
8450 double_to_single (bfd_int64_t v
)
8452 int sign
= (int) ((v
>> 63) & 1l);
8453 int exp
= (int) ((v
>> 52) & 0x7FF);
8454 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8460 exp
= exp
- 1023 + 127;
8469 /* No denormalized numbers. */
8475 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8477 #endif /* BFD_HOST_64_BIT */
8486 static void do_vfp_nsyn_opcode (const char *);
8488 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8489 Determine whether it can be performed with a move instruction; if
8490 it can, convert inst.instruction to that move instruction and
8491 return TRUE; if it can't, convert inst.instruction to a literal-pool
8492 load and return FALSE. If this is not a valid thing to do in the
8493 current context, set inst.error and return TRUE.
8495 inst.operands[i] describes the destination register. */
8498 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8501 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8502 bfd_boolean arm_p
= (t
== CONST_ARM
);
8505 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8509 if ((inst
.instruction
& tbit
) == 0)
8511 inst
.error
= _("invalid pseudo operation");
8515 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8516 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8517 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8519 inst
.error
= _("constant expression expected");
8523 if (inst
.relocs
[0].exp
.X_op
== O_constant
8524 || inst
.relocs
[0].exp
.X_op
== O_big
)
8526 #if defined BFD_HOST_64_BIT
8531 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8533 LITTLENUM_TYPE w
[X_PRECISION
];
8536 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8538 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8540 /* FIXME: Should we check words w[2..5] ? */
8545 #if defined BFD_HOST_64_BIT
8547 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8548 << LITTLENUM_NUMBER_OF_BITS
)
8549 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8550 << LITTLENUM_NUMBER_OF_BITS
)
8551 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8552 << LITTLENUM_NUMBER_OF_BITS
)
8553 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8555 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8556 | (l
[0] & LITTLENUM_MASK
);
8560 v
= inst
.relocs
[0].exp
.X_add_number
;
8562 if (!inst
.operands
[i
].issingle
)
8566 /* LDR should not use lead in a flag-setting instruction being
8567 chosen so we do not check whether movs can be used. */
8569 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8570 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8571 && inst
.operands
[i
].reg
!= 13
8572 && inst
.operands
[i
].reg
!= 15)
8574 /* Check if on thumb2 it can be done with a mov.w, mvn or
8575 movw instruction. */
8576 unsigned int newimm
;
8577 bfd_boolean isNegated
;
8579 newimm
= encode_thumb32_immediate (v
);
8580 if (newimm
!= (unsigned int) FAIL
)
8584 newimm
= encode_thumb32_immediate (~v
);
8585 if (newimm
!= (unsigned int) FAIL
)
8589 /* The number can be loaded with a mov.w or mvn
8591 if (newimm
!= (unsigned int) FAIL
8592 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8594 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8595 | (inst
.operands
[i
].reg
<< 8));
8596 /* Change to MOVN. */
8597 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8598 inst
.instruction
|= (newimm
& 0x800) << 15;
8599 inst
.instruction
|= (newimm
& 0x700) << 4;
8600 inst
.instruction
|= (newimm
& 0x0ff);
8603 /* The number can be loaded with a movw instruction. */
8604 else if ((v
& ~0xFFFF) == 0
8605 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8607 int imm
= v
& 0xFFFF;
8609 inst
.instruction
= 0xf2400000; /* MOVW. */
8610 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8611 inst
.instruction
|= (imm
& 0xf000) << 4;
8612 inst
.instruction
|= (imm
& 0x0800) << 15;
8613 inst
.instruction
|= (imm
& 0x0700) << 4;
8614 inst
.instruction
|= (imm
& 0x00ff);
8621 int value
= encode_arm_immediate (v
);
8625 /* This can be done with a mov instruction. */
8626 inst
.instruction
&= LITERAL_MASK
;
8627 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8628 inst
.instruction
|= value
& 0xfff;
8632 value
= encode_arm_immediate (~ v
);
8635 /* This can be done with a mvn instruction. */
8636 inst
.instruction
&= LITERAL_MASK
;
8637 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8638 inst
.instruction
|= value
& 0xfff;
8642 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8645 unsigned immbits
= 0;
8646 unsigned immlo
= inst
.operands
[1].imm
;
8647 unsigned immhi
= inst
.operands
[1].regisimm
8648 ? inst
.operands
[1].reg
8649 : inst
.relocs
[0].exp
.X_unsigned
8651 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8652 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8653 &op
, 64, NT_invtype
);
8657 neon_invert_size (&immlo
, &immhi
, 64);
8659 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8660 &op
, 64, NT_invtype
);
8665 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8671 /* Fill other bits in vmov encoding for both thumb and arm. */
8673 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8675 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8676 neon_write_immbits (immbits
);
8684 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8685 if (inst
.operands
[i
].issingle
8686 && is_quarter_float (inst
.operands
[1].imm
)
8687 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8689 inst
.operands
[1].imm
=
8690 neon_qfloat_bits (v
);
8691 do_vfp_nsyn_opcode ("fconsts");
8695 /* If our host does not support a 64-bit type then we cannot perform
8696 the following optimization. This mean that there will be a
8697 discrepancy between the output produced by an assembler built for
8698 a 32-bit-only host and the output produced from a 64-bit host, but
8699 this cannot be helped. */
8700 #if defined BFD_HOST_64_BIT
8701 else if (!inst
.operands
[1].issingle
8702 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8704 if (is_double_a_single (v
)
8705 && is_quarter_float (double_to_single (v
)))
8707 inst
.operands
[1].imm
=
8708 neon_qfloat_bits (double_to_single (v
));
8709 do_vfp_nsyn_opcode ("fconstd");
8717 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8718 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8721 inst
.operands
[1].reg
= REG_PC
;
8722 inst
.operands
[1].isreg
= 1;
8723 inst
.operands
[1].preind
= 1;
8724 inst
.relocs
[0].pc_rel
= 1;
8725 inst
.relocs
[0].type
= (thumb_p
8726 ? BFD_RELOC_ARM_THUMB_OFFSET
8728 ? BFD_RELOC_ARM_HWLITERAL
8729 : BFD_RELOC_ARM_LITERAL
));
8733 /* inst.operands[i] was set up by parse_address. Encode it into an
8734 ARM-format instruction. Reject all forms which cannot be encoded
8735 into a coprocessor load/store instruction. If wb_ok is false,
8736 reject use of writeback; if unind_ok is false, reject use of
8737 unindexed addressing. If reloc_override is not 0, use it instead
8738 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8739 (in which case it is preserved). */
8742 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8744 if (!inst
.operands
[i
].isreg
)
8747 if (! inst
.operands
[0].isvec
)
8749 inst
.error
= _("invalid co-processor operand");
8752 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8756 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8758 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8760 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8762 gas_assert (!inst
.operands
[i
].writeback
);
8765 inst
.error
= _("instruction does not support unindexed addressing");
8768 inst
.instruction
|= inst
.operands
[i
].imm
;
8769 inst
.instruction
|= INDEX_UP
;
8773 if (inst
.operands
[i
].preind
)
8774 inst
.instruction
|= PRE_INDEX
;
8776 if (inst
.operands
[i
].writeback
)
8778 if (inst
.operands
[i
].reg
== REG_PC
)
8780 inst
.error
= _("pc may not be used with write-back");
8785 inst
.error
= _("instruction does not support writeback");
8788 inst
.instruction
|= WRITE_BACK
;
8792 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8793 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8794 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8795 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8798 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8800 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8803 /* Prefer + for zero encoded value. */
8804 if (!inst
.operands
[i
].negative
)
8805 inst
.instruction
|= INDEX_UP
;
8810 /* Functions for instruction encoding, sorted by sub-architecture.
8811 First some generics; their names are taken from the conventional
8812 bit positions for register arguments in ARM format instructions. */
8822 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8828 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8834 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8835 inst
.instruction
|= inst
.operands
[1].reg
;
8841 inst
.instruction
|= inst
.operands
[0].reg
;
8842 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8848 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8849 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8855 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8856 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8862 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8863 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8867 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8869 if (ARM_CPU_IS_ANY (cpu_variant
))
8871 as_tsktsk ("%s", msg
);
8874 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8886 unsigned Rn
= inst
.operands
[2].reg
;
8887 /* Enforce restrictions on SWP instruction. */
8888 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8890 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8891 _("Rn must not overlap other operands"));
8893 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8895 if (!check_obsolete (&arm_ext_v8
,
8896 _("swp{b} use is obsoleted for ARMv8 and later"))
8897 && warn_on_deprecated
8898 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8899 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8902 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8903 inst
.instruction
|= inst
.operands
[1].reg
;
8904 inst
.instruction
|= Rn
<< 16;
8910 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8911 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8912 inst
.instruction
|= inst
.operands
[2].reg
;
8918 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8919 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
8920 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
8921 || inst
.relocs
[0].exp
.X_add_number
!= 0),
8923 inst
.instruction
|= inst
.operands
[0].reg
;
8924 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8925 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8931 inst
.instruction
|= inst
.operands
[0].imm
;
8937 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8938 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8941 /* ARM instructions, in alphabetical order by function name (except
8942 that wrapper functions appear immediately after the function they
8945 /* This is a pseudo-op of the form "adr rd, label" to be converted
8946 into a relative address of the form "add rd, pc, #label-.-8". */
8951 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8953 /* Frag hacking will turn this into a sub instruction if the offset turns
8954 out to be negative. */
8955 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
8956 inst
.relocs
[0].pc_rel
= 1;
8957 inst
.relocs
[0].exp
.X_add_number
-= 8;
8959 if (support_interwork
8960 && inst
.relocs
[0].exp
.X_op
== O_symbol
8961 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
8962 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
8963 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
8964 inst
.relocs
[0].exp
.X_add_number
|= 1;
8967 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8968 into a relative address of the form:
8969 add rd, pc, #low(label-.-8)"
8970 add rd, rd, #high(label-.-8)" */
8975 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8977 /* Frag hacking will turn this into a sub instruction if the offset turns
8978 out to be negative. */
8979 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8980 inst
.relocs
[0].pc_rel
= 1;
8981 inst
.size
= INSN_SIZE
* 2;
8982 inst
.relocs
[0].exp
.X_add_number
-= 8;
8984 if (support_interwork
8985 && inst
.relocs
[0].exp
.X_op
== O_symbol
8986 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
8987 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
8988 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
8989 inst
.relocs
[0].exp
.X_add_number
|= 1;
8995 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8996 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8998 if (!inst
.operands
[1].present
)
8999 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9000 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9001 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9002 encode_arm_shifter_operand (2);
9008 if (inst
.operands
[0].present
)
9009 inst
.instruction
|= inst
.operands
[0].imm
;
9011 inst
.instruction
|= 0xf;
9017 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9018 constraint (msb
> 32, _("bit-field extends past end of register"));
9019 /* The instruction encoding stores the LSB and MSB,
9020 not the LSB and width. */
9021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9022 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9023 inst
.instruction
|= (msb
- 1) << 16;
9031 /* #0 in second position is alternative syntax for bfc, which is
9032 the same instruction but with REG_PC in the Rm field. */
9033 if (!inst
.operands
[1].isreg
)
9034 inst
.operands
[1].reg
= REG_PC
;
9036 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9037 constraint (msb
> 32, _("bit-field extends past end of register"));
9038 /* The instruction encoding stores the LSB and MSB,
9039 not the LSB and width. */
9040 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9041 inst
.instruction
|= inst
.operands
[1].reg
;
9042 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9043 inst
.instruction
|= (msb
- 1) << 16;
9049 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9050 _("bit-field extends past end of register"));
9051 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9052 inst
.instruction
|= inst
.operands
[1].reg
;
9053 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9054 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9057 /* ARM V5 breakpoint instruction (argument parse)
9058 BKPT <16 bit unsigned immediate>
9059 Instruction is not conditional.
9060 The bit pattern given in insns[] has the COND_ALWAYS condition,
9061 and it is an error if the caller tried to override that. */
9066 /* Top 12 of 16 bits to bits 19:8. */
9067 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9069 /* Bottom 4 of 16 bits to bits 3:0. */
9070 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9074 encode_branch (int default_reloc
)
9076 if (inst
.operands
[0].hasreloc
)
9078 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9079 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9080 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9081 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9082 ? BFD_RELOC_ARM_PLT32
9083 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9086 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9087 inst
.relocs
[0].pc_rel
= 1;
9094 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9095 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9098 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9105 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9107 if (inst
.cond
== COND_ALWAYS
)
9108 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9110 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9114 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9117 /* ARM V5 branch-link-exchange instruction (argument parse)
9118 BLX <target_addr> ie BLX(1)
9119 BLX{<condition>} <Rm> ie BLX(2)
9120 Unfortunately, there are two different opcodes for this mnemonic.
9121 So, the insns[].value is not used, and the code here zaps values
9122 into inst.instruction.
9123 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9128 if (inst
.operands
[0].isreg
)
9130 /* Arg is a register; the opcode provided by insns[] is correct.
9131 It is not illegal to do "blx pc", just useless. */
9132 if (inst
.operands
[0].reg
== REG_PC
)
9133 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9135 inst
.instruction
|= inst
.operands
[0].reg
;
9139 /* Arg is an address; this instruction cannot be executed
9140 conditionally, and the opcode must be adjusted.
9141 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9142 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9143 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9144 inst
.instruction
= 0xfa000000;
9145 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9152 bfd_boolean want_reloc
;
9154 if (inst
.operands
[0].reg
== REG_PC
)
9155 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9157 inst
.instruction
|= inst
.operands
[0].reg
;
9158 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9159 it is for ARMv4t or earlier. */
9160 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9161 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9162 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9166 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9171 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9175 /* ARM v5TEJ. Jump to Jazelle code. */
9180 if (inst
.operands
[0].reg
== REG_PC
)
9181 as_tsktsk (_("use of r15 in bxj is not really useful"));
9183 inst
.instruction
|= inst
.operands
[0].reg
;
9186 /* Co-processor data operation:
9187 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9188 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9192 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9193 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9194 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9195 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9196 inst
.instruction
|= inst
.operands
[4].reg
;
9197 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9203 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9204 encode_arm_shifter_operand (1);
9207 /* Transfer between coprocessor and ARM registers.
9208 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9213 No special properties. */
9215 struct deprecated_coproc_regs_s
9222 arm_feature_set deprecated
;
9223 arm_feature_set obsoleted
;
9224 const char *dep_msg
;
9225 const char *obs_msg
;
9228 #define DEPR_ACCESS_V8 \
9229 N_("This coprocessor register access is deprecated in ARMv8")
9231 /* Table of all deprecated coprocessor registers. */
9232 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9234 {15, 0, 7, 10, 5, /* CP15DMB. */
9235 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9236 DEPR_ACCESS_V8
, NULL
},
9237 {15, 0, 7, 10, 4, /* CP15DSB. */
9238 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9239 DEPR_ACCESS_V8
, NULL
},
9240 {15, 0, 7, 5, 4, /* CP15ISB. */
9241 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9242 DEPR_ACCESS_V8
, NULL
},
9243 {14, 6, 1, 0, 0, /* TEEHBR. */
9244 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9245 DEPR_ACCESS_V8
, NULL
},
9246 {14, 6, 0, 0, 0, /* TEECR. */
9247 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9248 DEPR_ACCESS_V8
, NULL
},
9251 #undef DEPR_ACCESS_V8
9253 static const size_t deprecated_coproc_reg_count
=
9254 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9262 Rd
= inst
.operands
[2].reg
;
9265 if (inst
.instruction
== 0xee000010
9266 || inst
.instruction
== 0xfe000010)
9268 reject_bad_reg (Rd
);
9269 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9271 constraint (Rd
== REG_SP
, BAD_SP
);
9276 if (inst
.instruction
== 0xe000010)
9277 constraint (Rd
== REG_PC
, BAD_PC
);
9280 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9282 const struct deprecated_coproc_regs_s
*r
=
9283 deprecated_coproc_regs
+ i
;
9285 if (inst
.operands
[0].reg
== r
->cp
9286 && inst
.operands
[1].imm
== r
->opc1
9287 && inst
.operands
[3].reg
== r
->crn
9288 && inst
.operands
[4].reg
== r
->crm
9289 && inst
.operands
[5].imm
== r
->opc2
)
9291 if (! ARM_CPU_IS_ANY (cpu_variant
)
9292 && warn_on_deprecated
9293 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9294 as_tsktsk ("%s", r
->dep_msg
);
9298 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9299 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9300 inst
.instruction
|= Rd
<< 12;
9301 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9302 inst
.instruction
|= inst
.operands
[4].reg
;
9303 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9306 /* Transfer between coprocessor register and pair of ARM registers.
9307 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9312 Two XScale instructions are special cases of these:
9314 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9315 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9317 Result unpredictable if Rd or Rn is R15. */
9324 Rd
= inst
.operands
[2].reg
;
9325 Rn
= inst
.operands
[3].reg
;
9329 reject_bad_reg (Rd
);
9330 reject_bad_reg (Rn
);
9334 constraint (Rd
== REG_PC
, BAD_PC
);
9335 constraint (Rn
== REG_PC
, BAD_PC
);
9338 /* Only check the MRRC{2} variants. */
9339 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9341 /* If Rd == Rn, error that the operation is
9342 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9343 constraint (Rd
== Rn
, BAD_OVERLAP
);
9346 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9347 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9348 inst
.instruction
|= Rd
<< 12;
9349 inst
.instruction
|= Rn
<< 16;
9350 inst
.instruction
|= inst
.operands
[4].reg
;
9356 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9357 if (inst
.operands
[1].present
)
9359 inst
.instruction
|= CPSI_MMOD
;
9360 inst
.instruction
|= inst
.operands
[1].imm
;
9367 inst
.instruction
|= inst
.operands
[0].imm
;
9373 unsigned Rd
, Rn
, Rm
;
9375 Rd
= inst
.operands
[0].reg
;
9376 Rn
= (inst
.operands
[1].present
9377 ? inst
.operands
[1].reg
: Rd
);
9378 Rm
= inst
.operands
[2].reg
;
9380 constraint ((Rd
== REG_PC
), BAD_PC
);
9381 constraint ((Rn
== REG_PC
), BAD_PC
);
9382 constraint ((Rm
== REG_PC
), BAD_PC
);
9384 inst
.instruction
|= Rd
<< 16;
9385 inst
.instruction
|= Rn
<< 0;
9386 inst
.instruction
|= Rm
<< 8;
9392 /* There is no IT instruction in ARM mode. We
9393 process it to do the validation as if in
9394 thumb mode, just in case the code gets
9395 assembled for thumb using the unified syntax. */
9400 set_pred_insn_type (IT_INSN
);
9401 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9402 now_pred
.cc
= inst
.operands
[0].imm
;
9406 /* If there is only one register in the register list,
9407 then return its register number. Otherwise return -1. */
9409 only_one_reg_in_list (int range
)
9411 int i
= ffs (range
) - 1;
9412 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9416 encode_ldmstm(int from_push_pop_mnem
)
9418 int base_reg
= inst
.operands
[0].reg
;
9419 int range
= inst
.operands
[1].imm
;
9422 inst
.instruction
|= base_reg
<< 16;
9423 inst
.instruction
|= range
;
9425 if (inst
.operands
[1].writeback
)
9426 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9428 if (inst
.operands
[0].writeback
)
9430 inst
.instruction
|= WRITE_BACK
;
9431 /* Check for unpredictable uses of writeback. */
9432 if (inst
.instruction
& LOAD_BIT
)
9434 /* Not allowed in LDM type 2. */
9435 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9436 && ((range
& (1 << REG_PC
)) == 0))
9437 as_warn (_("writeback of base register is UNPREDICTABLE"));
9438 /* Only allowed if base reg not in list for other types. */
9439 else if (range
& (1 << base_reg
))
9440 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9444 /* Not allowed for type 2. */
9445 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9446 as_warn (_("writeback of base register is UNPREDICTABLE"));
9447 /* Only allowed if base reg not in list, or first in list. */
9448 else if ((range
& (1 << base_reg
))
9449 && (range
& ((1 << base_reg
) - 1)))
9450 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9454 /* If PUSH/POP has only one register, then use the A2 encoding. */
9455 one_reg
= only_one_reg_in_list (range
);
9456 if (from_push_pop_mnem
&& one_reg
>= 0)
9458 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9460 if (is_push
&& one_reg
== 13 /* SP */)
9461 /* PR 22483: The A2 encoding cannot be used when
9462 pushing the stack pointer as this is UNPREDICTABLE. */
9465 inst
.instruction
&= A_COND_MASK
;
9466 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9467 inst
.instruction
|= one_reg
<< 12;
9474 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9477 /* ARMv5TE load-consecutive (argument parse)
9486 constraint (inst
.operands
[0].reg
% 2 != 0,
9487 _("first transfer register must be even"));
9488 constraint (inst
.operands
[1].present
9489 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9490 _("can only transfer two consecutive registers"));
9491 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9492 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9494 if (!inst
.operands
[1].present
)
9495 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9497 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9498 register and the first register written; we have to diagnose
9499 overlap between the base and the second register written here. */
9501 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9502 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9503 as_warn (_("base register written back, and overlaps "
9504 "second transfer register"));
9506 if (!(inst
.instruction
& V4_STR_BIT
))
9508 /* For an index-register load, the index register must not overlap the
9509 destination (even if not write-back). */
9510 if (inst
.operands
[2].immisreg
9511 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9512 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9513 as_warn (_("index register overlaps transfer register"));
9515 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9516 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9522 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9523 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9524 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9525 || inst
.operands
[1].negative
9526 /* This can arise if the programmer has written
9528 or if they have mistakenly used a register name as the last
9531 It is very difficult to distinguish between these two cases
9532 because "rX" might actually be a label. ie the register
9533 name has been occluded by a symbol of the same name. So we
9534 just generate a general 'bad addressing mode' type error
9535 message and leave it up to the programmer to discover the
9536 true cause and fix their mistake. */
9537 || (inst
.operands
[1].reg
== REG_PC
),
9540 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9541 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9542 _("offset must be zero in ARM encoding"));
9544 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9546 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9547 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9548 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9554 constraint (inst
.operands
[0].reg
% 2 != 0,
9555 _("even register required"));
9556 constraint (inst
.operands
[1].present
9557 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9558 _("can only load two consecutive registers"));
9559 /* If op 1 were present and equal to PC, this function wouldn't
9560 have been called in the first place. */
9561 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9563 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9564 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9567 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9568 which is not a multiple of four is UNPREDICTABLE. */
9570 check_ldr_r15_aligned (void)
9572 constraint (!(inst
.operands
[1].immisreg
)
9573 && (inst
.operands
[0].reg
== REG_PC
9574 && inst
.operands
[1].reg
== REG_PC
9575 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9576 _("ldr to register 15 must be 4-byte aligned"));
9582 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9583 if (!inst
.operands
[1].isreg
)
9584 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9586 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9587 check_ldr_r15_aligned ();
9593 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9595 if (inst
.operands
[1].preind
)
9597 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9598 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9599 _("this instruction requires a post-indexed address"));
9601 inst
.operands
[1].preind
= 0;
9602 inst
.operands
[1].postind
= 1;
9603 inst
.operands
[1].writeback
= 1;
9605 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9606 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9609 /* Halfword and signed-byte load/store operations. */
9614 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9615 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9616 if (!inst
.operands
[1].isreg
)
9617 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9619 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9625 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9627 if (inst
.operands
[1].preind
)
9629 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9630 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9631 _("this instruction requires a post-indexed address"));
9633 inst
.operands
[1].preind
= 0;
9634 inst
.operands
[1].postind
= 1;
9635 inst
.operands
[1].writeback
= 1;
9637 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9638 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9641 /* Co-processor register load/store.
9642 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9646 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9647 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9648 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9654 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9655 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9656 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9657 && !(inst
.instruction
& 0x00400000))
9658 as_tsktsk (_("Rd and Rm should be different in mla"));
9660 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9661 inst
.instruction
|= inst
.operands
[1].reg
;
9662 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9663 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9669 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9670 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9672 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9673 encode_arm_shifter_operand (1);
9676 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9683 top
= (inst
.instruction
& 0x00400000) != 0;
9684 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9685 _(":lower16: not allowed in this instruction"));
9686 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9687 _(":upper16: not allowed in this instruction"));
9688 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9689 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9691 imm
= inst
.relocs
[0].exp
.X_add_number
;
9692 /* The value is in two pieces: 0:11, 16:19. */
9693 inst
.instruction
|= (imm
& 0x00000fff);
9694 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9699 do_vfp_nsyn_mrs (void)
9701 if (inst
.operands
[0].isvec
)
9703 if (inst
.operands
[1].reg
!= 1)
9704 first_error (_("operand 1 must be FPSCR"));
9705 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9706 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9707 do_vfp_nsyn_opcode ("fmstat");
9709 else if (inst
.operands
[1].isvec
)
9710 do_vfp_nsyn_opcode ("fmrx");
9718 do_vfp_nsyn_msr (void)
9720 if (inst
.operands
[0].isvec
)
9721 do_vfp_nsyn_opcode ("fmxr");
9731 unsigned Rt
= inst
.operands
[0].reg
;
9733 if (thumb_mode
&& Rt
== REG_SP
)
9735 inst
.error
= BAD_SP
;
9739 /* MVFR2 is only valid at ARMv8-A. */
9740 if (inst
.operands
[1].reg
== 5)
9741 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9744 /* APSR_ sets isvec. All other refs to PC are illegal. */
9745 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9747 inst
.error
= BAD_PC
;
9751 /* If we get through parsing the register name, we just insert the number
9752 generated into the instruction without further validation. */
9753 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9754 inst
.instruction
|= (Rt
<< 12);
9760 unsigned Rt
= inst
.operands
[1].reg
;
9763 reject_bad_reg (Rt
);
9764 else if (Rt
== REG_PC
)
9766 inst
.error
= BAD_PC
;
9770 /* MVFR2 is only valid for ARMv8-A. */
9771 if (inst
.operands
[0].reg
== 5)
9772 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9775 /* If we get through parsing the register name, we just insert the number
9776 generated into the instruction without further validation. */
9777 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9778 inst
.instruction
|= (Rt
<< 12);
9786 if (do_vfp_nsyn_mrs () == SUCCESS
)
9789 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9790 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9792 if (inst
.operands
[1].isreg
)
9794 br
= inst
.operands
[1].reg
;
9795 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9796 as_bad (_("bad register for mrs"));
9800 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9801 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9803 _("'APSR', 'CPSR' or 'SPSR' expected"));
9804 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9807 inst
.instruction
|= br
;
9810 /* Two possible forms:
9811 "{C|S}PSR_<field>, Rm",
9812 "{C|S}PSR_f, #expression". */
9817 if (do_vfp_nsyn_msr () == SUCCESS
)
9820 inst
.instruction
|= inst
.operands
[0].imm
;
9821 if (inst
.operands
[1].isreg
)
9822 inst
.instruction
|= inst
.operands
[1].reg
;
9825 inst
.instruction
|= INST_IMMEDIATE
;
9826 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9827 inst
.relocs
[0].pc_rel
= 0;
9834 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9836 if (!inst
.operands
[2].present
)
9837 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9838 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9839 inst
.instruction
|= inst
.operands
[1].reg
;
9840 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9842 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9843 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9844 as_tsktsk (_("Rd and Rm should be different in mul"));
9847 /* Long Multiply Parser
9848 UMULL RdLo, RdHi, Rm, Rs
9849 SMULL RdLo, RdHi, Rm, Rs
9850 UMLAL RdLo, RdHi, Rm, Rs
9851 SMLAL RdLo, RdHi, Rm, Rs. */
9856 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9857 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9858 inst
.instruction
|= inst
.operands
[2].reg
;
9859 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9861 /* rdhi and rdlo must be different. */
9862 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9863 as_tsktsk (_("rdhi and rdlo must be different"));
9865 /* rdhi, rdlo and rm must all be different before armv6. */
9866 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9867 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9868 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9869 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9875 if (inst
.operands
[0].present
9876 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9878 /* Architectural NOP hints are CPSR sets with no bits selected. */
9879 inst
.instruction
&= 0xf0000000;
9880 inst
.instruction
|= 0x0320f000;
9881 if (inst
.operands
[0].present
)
9882 inst
.instruction
|= inst
.operands
[0].imm
;
9886 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9887 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9888 Condition defaults to COND_ALWAYS.
9889 Error if Rd, Rn or Rm are R15. */
9894 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9895 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9896 inst
.instruction
|= inst
.operands
[2].reg
;
9897 if (inst
.operands
[3].present
)
9898 encode_arm_shift (3);
9901 /* ARM V6 PKHTB (Argument Parse). */
9906 if (!inst
.operands
[3].present
)
9908 /* If the shift specifier is omitted, turn the instruction
9909 into pkhbt rd, rm, rn. */
9910 inst
.instruction
&= 0xfff00010;
9911 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9912 inst
.instruction
|= inst
.operands
[1].reg
;
9913 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9917 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9918 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9919 inst
.instruction
|= inst
.operands
[2].reg
;
9920 encode_arm_shift (3);
9924 /* ARMv5TE: Preload-Cache
9925 MP Extensions: Preload for write
9929 Syntactically, like LDR with B=1, W=0, L=1. */
9934 constraint (!inst
.operands
[0].isreg
,
9935 _("'[' expected after PLD mnemonic"));
9936 constraint (inst
.operands
[0].postind
,
9937 _("post-indexed expression used in preload instruction"));
9938 constraint (inst
.operands
[0].writeback
,
9939 _("writeback used in preload instruction"));
9940 constraint (!inst
.operands
[0].preind
,
9941 _("unindexed addressing used in preload instruction"));
9942 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9945 /* ARMv7: PLI <addr_mode> */
9949 constraint (!inst
.operands
[0].isreg
,
9950 _("'[' expected after PLI mnemonic"));
9951 constraint (inst
.operands
[0].postind
,
9952 _("post-indexed expression used in preload instruction"));
9953 constraint (inst
.operands
[0].writeback
,
9954 _("writeback used in preload instruction"));
9955 constraint (!inst
.operands
[0].preind
,
9956 _("unindexed addressing used in preload instruction"));
9957 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9958 inst
.instruction
&= ~PRE_INDEX
;
9964 constraint (inst
.operands
[0].writeback
,
9965 _("push/pop do not support {reglist}^"));
9966 inst
.operands
[1] = inst
.operands
[0];
9967 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9968 inst
.operands
[0].isreg
= 1;
9969 inst
.operands
[0].writeback
= 1;
9970 inst
.operands
[0].reg
= REG_SP
;
9971 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9974 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9975 word at the specified address and the following word
9977 Unconditionally executed.
9978 Error if Rn is R15. */
9983 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9984 if (inst
.operands
[0].writeback
)
9985 inst
.instruction
|= WRITE_BACK
;
9988 /* ARM V6 ssat (argument parse). */
9993 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9994 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9995 inst
.instruction
|= inst
.operands
[2].reg
;
9997 if (inst
.operands
[3].present
)
9998 encode_arm_shift (3);
10001 /* ARM V6 usat (argument parse). */
10006 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10007 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10008 inst
.instruction
|= inst
.operands
[2].reg
;
10010 if (inst
.operands
[3].present
)
10011 encode_arm_shift (3);
10014 /* ARM V6 ssat16 (argument parse). */
10019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10020 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10021 inst
.instruction
|= inst
.operands
[2].reg
;
10027 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10028 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10029 inst
.instruction
|= inst
.operands
[2].reg
;
10032 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10033 preserving the other bits.
10035 setend <endian_specifier>, where <endian_specifier> is either
10041 if (warn_on_deprecated
10042 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10043 as_tsktsk (_("setend use is deprecated for ARMv8"));
10045 if (inst
.operands
[0].imm
)
10046 inst
.instruction
|= 0x200;
10052 unsigned int Rm
= (inst
.operands
[1].present
10053 ? inst
.operands
[1].reg
10054 : inst
.operands
[0].reg
);
10056 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10057 inst
.instruction
|= Rm
;
10058 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10060 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10061 inst
.instruction
|= SHIFT_BY_REG
;
10062 /* PR 12854: Error on extraneous shifts. */
10063 constraint (inst
.operands
[2].shifted
,
10064 _("extraneous shift as part of operand to shift insn"));
10067 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10073 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10074 inst
.relocs
[0].pc_rel
= 0;
10080 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10081 inst
.relocs
[0].pc_rel
= 0;
10087 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10088 inst
.relocs
[0].pc_rel
= 0;
10094 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10095 _("selected processor does not support SETPAN instruction"));
10097 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10103 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10104 _("selected processor does not support SETPAN instruction"));
10106 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10109 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10110 SMLAxy{cond} Rd,Rm,Rs,Rn
10111 SMLAWy{cond} Rd,Rm,Rs,Rn
10112 Error if any register is R15. */
10117 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10118 inst
.instruction
|= inst
.operands
[1].reg
;
10119 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10120 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10123 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10124 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10125 Error if any register is R15.
10126 Warning if Rdlo == Rdhi. */
10131 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10132 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10133 inst
.instruction
|= inst
.operands
[2].reg
;
10134 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10136 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10137 as_tsktsk (_("rdhi and rdlo must be different"));
10140 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10141 SMULxy{cond} Rd,Rm,Rs
10142 Error if any register is R15. */
10147 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10148 inst
.instruction
|= inst
.operands
[1].reg
;
10149 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10152 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10153 the same for both ARM and Thumb-2. */
10160 if (inst
.operands
[0].present
)
10162 reg
= inst
.operands
[0].reg
;
10163 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10168 inst
.instruction
|= reg
<< 16;
10169 inst
.instruction
|= inst
.operands
[1].imm
;
10170 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10171 inst
.instruction
|= WRITE_BACK
;
10174 /* ARM V6 strex (argument parse). */
10179 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10180 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10181 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10182 || inst
.operands
[2].negative
10183 /* See comment in do_ldrex(). */
10184 || (inst
.operands
[2].reg
== REG_PC
),
10187 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10188 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10190 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10191 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10192 _("offset must be zero in ARM encoding"));
10194 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10195 inst
.instruction
|= inst
.operands
[1].reg
;
10196 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10197 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10201 do_t_strexbh (void)
10203 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10204 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10205 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10206 || inst
.operands
[2].negative
,
10209 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10210 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10218 constraint (inst
.operands
[1].reg
% 2 != 0,
10219 _("even register required"));
10220 constraint (inst
.operands
[2].present
10221 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10222 _("can only store two consecutive registers"));
10223 /* If op 2 were present and equal to PC, this function wouldn't
10224 have been called in the first place. */
10225 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10227 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10228 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10229 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10232 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10233 inst
.instruction
|= inst
.operands
[1].reg
;
10234 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10241 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10242 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10250 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10251 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10256 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10257 extends it to 32-bits, and adds the result to a value in another
10258 register. You can specify a rotation by 0, 8, 16, or 24 bits
10259 before extracting the 16-bit value.
10260 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10261 Condition defaults to COND_ALWAYS.
10262 Error if any register uses R15. */
10267 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10268 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10269 inst
.instruction
|= inst
.operands
[2].reg
;
10270 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10275 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10276 Condition defaults to COND_ALWAYS.
10277 Error if any register uses R15. */
10282 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10283 inst
.instruction
|= inst
.operands
[1].reg
;
10284 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10287 /* VFP instructions. In a logical order: SP variant first, monad
10288 before dyad, arithmetic then move then load/store. */
10291 do_vfp_sp_monadic (void)
10293 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10294 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10297 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10298 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10302 do_vfp_sp_dyadic (void)
10304 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10305 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10306 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10310 do_vfp_sp_compare_z (void)
10312 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10316 do_vfp_dp_sp_cvt (void)
10318 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10319 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10323 do_vfp_sp_dp_cvt (void)
10325 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10326 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10330 do_vfp_reg_from_sp (void)
10332 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10333 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10336 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10337 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10341 do_vfp_reg2_from_sp2 (void)
10343 constraint (inst
.operands
[2].imm
!= 2,
10344 _("only two consecutive VFP SP registers allowed here"));
10345 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10346 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10347 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10351 do_vfp_sp_from_reg (void)
10353 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10354 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10357 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10358 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10362 do_vfp_sp2_from_reg2 (void)
10364 constraint (inst
.operands
[0].imm
!= 2,
10365 _("only two consecutive VFP SP registers allowed here"));
10366 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10367 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10368 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10372 do_vfp_sp_ldst (void)
10374 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10375 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10379 do_vfp_dp_ldst (void)
10381 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10382 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10387 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10389 if (inst
.operands
[0].writeback
)
10390 inst
.instruction
|= WRITE_BACK
;
10392 constraint (ldstm_type
!= VFP_LDSTMIA
,
10393 _("this addressing mode requires base-register writeback"));
10394 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10395 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10396 inst
.instruction
|= inst
.operands
[1].imm
;
10400 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10404 if (inst
.operands
[0].writeback
)
10405 inst
.instruction
|= WRITE_BACK
;
10407 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10408 _("this addressing mode requires base-register writeback"));
10410 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10411 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10413 count
= inst
.operands
[1].imm
<< 1;
10414 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10417 inst
.instruction
|= count
;
10421 do_vfp_sp_ldstmia (void)
10423 vfp_sp_ldstm (VFP_LDSTMIA
);
10427 do_vfp_sp_ldstmdb (void)
10429 vfp_sp_ldstm (VFP_LDSTMDB
);
10433 do_vfp_dp_ldstmia (void)
10435 vfp_dp_ldstm (VFP_LDSTMIA
);
10439 do_vfp_dp_ldstmdb (void)
10441 vfp_dp_ldstm (VFP_LDSTMDB
);
10445 do_vfp_xp_ldstmia (void)
10447 vfp_dp_ldstm (VFP_LDSTMIAX
);
10451 do_vfp_xp_ldstmdb (void)
10453 vfp_dp_ldstm (VFP_LDSTMDBX
);
10457 do_vfp_dp_rd_rm (void)
10459 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10460 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10463 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10464 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10468 do_vfp_dp_rn_rd (void)
10470 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10471 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10475 do_vfp_dp_rd_rn (void)
10477 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10478 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10482 do_vfp_dp_rd_rn_rm (void)
10484 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10485 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10488 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10489 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10490 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10494 do_vfp_dp_rd (void)
10496 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10500 do_vfp_dp_rm_rd_rn (void)
10502 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10503 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10506 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10507 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10508 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10511 /* VFPv3 instructions. */
10513 do_vfp_sp_const (void)
10515 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10516 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10517 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10521 do_vfp_dp_const (void)
10523 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10524 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10525 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10529 vfp_conv (int srcsize
)
10531 int immbits
= srcsize
- inst
.operands
[1].imm
;
10533 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10535 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10536 i.e. immbits must be in range 0 - 16. */
10537 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10540 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10542 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10543 i.e. immbits must be in range 0 - 31. */
10544 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10548 inst
.instruction
|= (immbits
& 1) << 5;
10549 inst
.instruction
|= (immbits
>> 1);
10553 do_vfp_sp_conv_16 (void)
10555 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10560 do_vfp_dp_conv_16 (void)
10562 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10567 do_vfp_sp_conv_32 (void)
10569 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10574 do_vfp_dp_conv_32 (void)
10576 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10580 /* FPA instructions. Also in a logical order. */
10585 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10586 inst
.instruction
|= inst
.operands
[1].reg
;
10590 do_fpa_ldmstm (void)
10592 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10593 switch (inst
.operands
[1].imm
)
10595 case 1: inst
.instruction
|= CP_T_X
; break;
10596 case 2: inst
.instruction
|= CP_T_Y
; break;
10597 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10602 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10604 /* The instruction specified "ea" or "fd", so we can only accept
10605 [Rn]{!}. The instruction does not really support stacking or
10606 unstacking, so we have to emulate these by setting appropriate
10607 bits and offsets. */
10608 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10609 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10610 _("this instruction does not support indexing"));
10612 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10613 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10615 if (!(inst
.instruction
& INDEX_UP
))
10616 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10618 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10620 inst
.operands
[2].preind
= 0;
10621 inst
.operands
[2].postind
= 1;
10625 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10628 /* iWMMXt instructions: strictly in alphabetical order. */
10631 do_iwmmxt_tandorc (void)
10633 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10637 do_iwmmxt_textrc (void)
10639 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10640 inst
.instruction
|= inst
.operands
[1].imm
;
10644 do_iwmmxt_textrm (void)
10646 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10647 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10648 inst
.instruction
|= inst
.operands
[2].imm
;
10652 do_iwmmxt_tinsr (void)
10654 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10655 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10656 inst
.instruction
|= inst
.operands
[2].imm
;
10660 do_iwmmxt_tmia (void)
10662 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10663 inst
.instruction
|= inst
.operands
[1].reg
;
10664 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10668 do_iwmmxt_waligni (void)
10670 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10671 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10672 inst
.instruction
|= inst
.operands
[2].reg
;
10673 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10677 do_iwmmxt_wmerge (void)
10679 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10680 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10681 inst
.instruction
|= inst
.operands
[2].reg
;
10682 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10686 do_iwmmxt_wmov (void)
10688 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10689 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10690 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10691 inst
.instruction
|= inst
.operands
[1].reg
;
10695 do_iwmmxt_wldstbh (void)
10698 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10700 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10702 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10703 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10707 do_iwmmxt_wldstw (void)
10709 /* RIWR_RIWC clears .isreg for a control register. */
10710 if (!inst
.operands
[0].isreg
)
10712 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10713 inst
.instruction
|= 0xf0000000;
10716 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10717 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10721 do_iwmmxt_wldstd (void)
10723 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10724 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10725 && inst
.operands
[1].immisreg
)
10727 inst
.instruction
&= ~0x1a000ff;
10728 inst
.instruction
|= (0xfU
<< 28);
10729 if (inst
.operands
[1].preind
)
10730 inst
.instruction
|= PRE_INDEX
;
10731 if (!inst
.operands
[1].negative
)
10732 inst
.instruction
|= INDEX_UP
;
10733 if (inst
.operands
[1].writeback
)
10734 inst
.instruction
|= WRITE_BACK
;
10735 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10736 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10737 inst
.instruction
|= inst
.operands
[1].imm
;
10740 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10744 do_iwmmxt_wshufh (void)
10746 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10747 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10748 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10749 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10753 do_iwmmxt_wzero (void)
10755 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10756 inst
.instruction
|= inst
.operands
[0].reg
;
10757 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10758 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10762 do_iwmmxt_wrwrwr_or_imm5 (void)
10764 if (inst
.operands
[2].isreg
)
10767 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10768 _("immediate operand requires iWMMXt2"));
10770 if (inst
.operands
[2].imm
== 0)
10772 switch ((inst
.instruction
>> 20) & 0xf)
10778 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10779 inst
.operands
[2].imm
= 16;
10780 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10786 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10787 inst
.operands
[2].imm
= 32;
10788 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10795 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10797 wrn
= (inst
.instruction
>> 16) & 0xf;
10798 inst
.instruction
&= 0xff0fff0f;
10799 inst
.instruction
|= wrn
;
10800 /* Bail out here; the instruction is now assembled. */
10805 /* Map 32 -> 0, etc. */
10806 inst
.operands
[2].imm
&= 0x1f;
10807 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10811 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10812 operations first, then control, shift, and load/store. */
10814 /* Insns like "foo X,Y,Z". */
10817 do_mav_triple (void)
10819 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10820 inst
.instruction
|= inst
.operands
[1].reg
;
10821 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10824 /* Insns like "foo W,X,Y,Z".
10825 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10830 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10831 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10832 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10833 inst
.instruction
|= inst
.operands
[3].reg
;
10836 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10838 do_mav_dspsc (void)
10840 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10843 /* Maverick shift immediate instructions.
10844 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10845 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10848 do_mav_shift (void)
10850 int imm
= inst
.operands
[2].imm
;
10852 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10853 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10855 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10856 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10857 Bit 4 should be 0. */
10858 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10860 inst
.instruction
|= imm
;
10863 /* XScale instructions. Also sorted arithmetic before move. */
10865 /* Xscale multiply-accumulate (argument parse)
10868 MIAxycc acc0,Rm,Rs. */
10873 inst
.instruction
|= inst
.operands
[1].reg
;
10874 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10877 /* Xscale move-accumulator-register (argument parse)
10879 MARcc acc0,RdLo,RdHi. */
10884 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10885 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10888 /* Xscale move-register-accumulator (argument parse)
10890 MRAcc RdLo,RdHi,acc0. */
10895 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10896 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10897 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10900 /* Encoding functions relevant only to Thumb. */
10902 /* inst.operands[i] is a shifted-register operand; encode
10903 it into inst.instruction in the format used by Thumb32. */
10906 encode_thumb32_shifted_operand (int i
)
10908 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10909 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10911 constraint (inst
.operands
[i
].immisreg
,
10912 _("shift by register not allowed in thumb mode"));
10913 inst
.instruction
|= inst
.operands
[i
].reg
;
10914 if (shift
== SHIFT_RRX
)
10915 inst
.instruction
|= SHIFT_ROR
<< 4;
10918 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10919 _("expression too complex"));
10921 constraint (value
> 32
10922 || (value
== 32 && (shift
== SHIFT_LSL
10923 || shift
== SHIFT_ROR
)),
10924 _("shift expression is too large"));
10928 else if (value
== 32)
10931 inst
.instruction
|= shift
<< 4;
10932 inst
.instruction
|= (value
& 0x1c) << 10;
10933 inst
.instruction
|= (value
& 0x03) << 6;
10938 /* inst.operands[i] was set up by parse_address. Encode it into a
10939 Thumb32 format load or store instruction. Reject forms that cannot
10940 be used with such instructions. If is_t is true, reject forms that
10941 cannot be used with a T instruction; if is_d is true, reject forms
10942 that cannot be used with a D instruction. If it is a store insn,
10943 reject PC in Rn. */
10946 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10948 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10950 constraint (!inst
.operands
[i
].isreg
,
10951 _("Instruction does not support =N addresses"));
10953 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10954 if (inst
.operands
[i
].immisreg
)
10956 constraint (is_pc
, BAD_PC_ADDRESSING
);
10957 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10958 constraint (inst
.operands
[i
].negative
,
10959 _("Thumb does not support negative register indexing"));
10960 constraint (inst
.operands
[i
].postind
,
10961 _("Thumb does not support register post-indexing"));
10962 constraint (inst
.operands
[i
].writeback
,
10963 _("Thumb does not support register indexing with writeback"));
10964 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10965 _("Thumb supports only LSL in shifted register indexing"));
10967 inst
.instruction
|= inst
.operands
[i
].imm
;
10968 if (inst
.operands
[i
].shifted
)
10970 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10971 _("expression too complex"));
10972 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
10973 || inst
.relocs
[0].exp
.X_add_number
> 3,
10974 _("shift out of range"));
10975 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10977 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10979 else if (inst
.operands
[i
].preind
)
10981 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10982 constraint (is_t
&& inst
.operands
[i
].writeback
,
10983 _("cannot use writeback with this instruction"));
10984 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10985 BAD_PC_ADDRESSING
);
10989 inst
.instruction
|= 0x01000000;
10990 if (inst
.operands
[i
].writeback
)
10991 inst
.instruction
|= 0x00200000;
10995 inst
.instruction
|= 0x00000c00;
10996 if (inst
.operands
[i
].writeback
)
10997 inst
.instruction
|= 0x00000100;
10999 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11001 else if (inst
.operands
[i
].postind
)
11003 gas_assert (inst
.operands
[i
].writeback
);
11004 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11005 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11008 inst
.instruction
|= 0x00200000;
11010 inst
.instruction
|= 0x00000900;
11011 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11013 else /* unindexed - only for coprocessor */
11014 inst
.error
= _("instruction does not accept unindexed addressing");
11017 /* Table of Thumb instructions which exist in both 16- and 32-bit
11018 encodings (the latter only in post-V6T2 cores). The index is the
11019 value used in the insns table below. When there is more than one
11020 possible 16-bit encoding for the instruction, this table always
11022 Also contains several pseudo-instructions used during relaxation. */
11023 #define T16_32_TAB \
11024 X(_adc, 4140, eb400000), \
11025 X(_adcs, 4140, eb500000), \
11026 X(_add, 1c00, eb000000), \
11027 X(_adds, 1c00, eb100000), \
11028 X(_addi, 0000, f1000000), \
11029 X(_addis, 0000, f1100000), \
11030 X(_add_pc,000f, f20f0000), \
11031 X(_add_sp,000d, f10d0000), \
11032 X(_adr, 000f, f20f0000), \
11033 X(_and, 4000, ea000000), \
11034 X(_ands, 4000, ea100000), \
11035 X(_asr, 1000, fa40f000), \
11036 X(_asrs, 1000, fa50f000), \
11037 X(_b, e000, f000b000), \
11038 X(_bcond, d000, f0008000), \
11039 X(_bf, 0000, f040e001), \
11040 X(_bfcsel,0000, f000e001), \
11041 X(_bfx, 0000, f060e001), \
11042 X(_bfl, 0000, f000c001), \
11043 X(_bflx, 0000, f070e001), \
11044 X(_bic, 4380, ea200000), \
11045 X(_bics, 4380, ea300000), \
11046 X(_cmn, 42c0, eb100f00), \
11047 X(_cmp, 2800, ebb00f00), \
11048 X(_cpsie, b660, f3af8400), \
11049 X(_cpsid, b670, f3af8600), \
11050 X(_cpy, 4600, ea4f0000), \
11051 X(_dec_sp,80dd, f1ad0d00), \
11052 X(_dls, 0000, f040e001), \
11053 X(_eor, 4040, ea800000), \
11054 X(_eors, 4040, ea900000), \
11055 X(_inc_sp,00dd, f10d0d00), \
11056 X(_ldmia, c800, e8900000), \
11057 X(_ldr, 6800, f8500000), \
11058 X(_ldrb, 7800, f8100000), \
11059 X(_ldrh, 8800, f8300000), \
11060 X(_ldrsb, 5600, f9100000), \
11061 X(_ldrsh, 5e00, f9300000), \
11062 X(_ldr_pc,4800, f85f0000), \
11063 X(_ldr_pc2,4800, f85f0000), \
11064 X(_ldr_sp,9800, f85d0000), \
11065 X(_le, 0000, f00fc001), \
11066 X(_lsl, 0000, fa00f000), \
11067 X(_lsls, 0000, fa10f000), \
11068 X(_lsr, 0800, fa20f000), \
11069 X(_lsrs, 0800, fa30f000), \
11070 X(_mov, 2000, ea4f0000), \
11071 X(_movs, 2000, ea5f0000), \
11072 X(_mul, 4340, fb00f000), \
11073 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11074 X(_mvn, 43c0, ea6f0000), \
11075 X(_mvns, 43c0, ea7f0000), \
11076 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11077 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11078 X(_orr, 4300, ea400000), \
11079 X(_orrs, 4300, ea500000), \
11080 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11081 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11082 X(_rev, ba00, fa90f080), \
11083 X(_rev16, ba40, fa90f090), \
11084 X(_revsh, bac0, fa90f0b0), \
11085 X(_ror, 41c0, fa60f000), \
11086 X(_rors, 41c0, fa70f000), \
11087 X(_sbc, 4180, eb600000), \
11088 X(_sbcs, 4180, eb700000), \
11089 X(_stmia, c000, e8800000), \
11090 X(_str, 6000, f8400000), \
11091 X(_strb, 7000, f8000000), \
11092 X(_strh, 8000, f8200000), \
11093 X(_str_sp,9000, f84d0000), \
11094 X(_sub, 1e00, eba00000), \
11095 X(_subs, 1e00, ebb00000), \
11096 X(_subi, 8000, f1a00000), \
11097 X(_subis, 8000, f1b00000), \
11098 X(_sxtb, b240, fa4ff080), \
11099 X(_sxth, b200, fa0ff080), \
11100 X(_tst, 4200, ea100f00), \
11101 X(_uxtb, b2c0, fa5ff080), \
11102 X(_uxth, b280, fa1ff080), \
11103 X(_nop, bf00, f3af8000), \
11104 X(_yield, bf10, f3af8001), \
11105 X(_wfe, bf20, f3af8002), \
11106 X(_wfi, bf30, f3af8003), \
11107 X(_wls, 0000, f040c001), \
11108 X(_sev, bf40, f3af8004), \
11109 X(_sevl, bf50, f3af8005), \
11110 X(_udf, de00, f7f0a000)
11112 /* To catch errors in encoding functions, the codes are all offset by
11113 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11114 as 16-bit instructions. */
11115 #define X(a,b,c) T_MNEM##a
11116 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11119 #define X(a,b,c) 0x##b
11120 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11121 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11124 #define X(a,b,c) 0x##c
11125 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11126 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11127 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11131 /* Thumb instruction encoders, in alphabetical order. */
11133 /* ADDW or SUBW. */
11136 do_t_add_sub_w (void)
11140 Rd
= inst
.operands
[0].reg
;
11141 Rn
= inst
.operands
[1].reg
;
11143 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11144 is the SP-{plus,minus}-immediate form of the instruction. */
11146 constraint (Rd
== REG_PC
, BAD_PC
);
11148 reject_bad_reg (Rd
);
11150 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11151 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11154 /* Parse an add or subtract instruction. We get here with inst.instruction
11155 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11158 do_t_add_sub (void)
11162 Rd
= inst
.operands
[0].reg
;
11163 Rs
= (inst
.operands
[1].present
11164 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11165 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11168 set_pred_insn_type_last ();
11170 if (unified_syntax
)
11173 bfd_boolean narrow
;
11176 flags
= (inst
.instruction
== T_MNEM_adds
11177 || inst
.instruction
== T_MNEM_subs
);
11179 narrow
= !in_pred_block ();
11181 narrow
= in_pred_block ();
11182 if (!inst
.operands
[2].isreg
)
11186 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11187 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11189 add
= (inst
.instruction
== T_MNEM_add
11190 || inst
.instruction
== T_MNEM_adds
);
11192 if (inst
.size_req
!= 4)
11194 /* Attempt to use a narrow opcode, with relaxation if
11196 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11197 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11198 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11199 opcode
= T_MNEM_add_sp
;
11200 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11201 opcode
= T_MNEM_add_pc
;
11202 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11205 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11207 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11211 inst
.instruction
= THUMB_OP16(opcode
);
11212 inst
.instruction
|= (Rd
<< 4) | Rs
;
11213 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11214 || (inst
.relocs
[0].type
11215 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11217 if (inst
.size_req
== 2)
11218 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11220 inst
.relax
= opcode
;
11224 constraint (inst
.size_req
== 2, BAD_HIREG
);
11226 if (inst
.size_req
== 4
11227 || (inst
.size_req
!= 2 && !opcode
))
11229 constraint ((inst
.relocs
[0].type
11230 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11231 && (inst
.relocs
[0].type
11232 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11233 THUMB1_RELOC_ONLY
);
11236 constraint (add
, BAD_PC
);
11237 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11238 _("only SUBS PC, LR, #const allowed"));
11239 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11240 _("expression too complex"));
11241 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11242 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11243 _("immediate value out of range"));
11244 inst
.instruction
= T2_SUBS_PC_LR
11245 | inst
.relocs
[0].exp
.X_add_number
;
11246 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11249 else if (Rs
== REG_PC
)
11251 /* Always use addw/subw. */
11252 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11253 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11257 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11258 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11261 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11263 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11265 inst
.instruction
|= Rd
<< 8;
11266 inst
.instruction
|= Rs
<< 16;
11271 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11272 unsigned int shift
= inst
.operands
[2].shift_kind
;
11274 Rn
= inst
.operands
[2].reg
;
11275 /* See if we can do this with a 16-bit instruction. */
11276 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11278 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11283 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11284 || inst
.instruction
== T_MNEM_add
)
11286 : T_OPCODE_SUB_R3
);
11287 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11291 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11293 /* Thumb-1 cores (except v6-M) require at least one high
11294 register in a narrow non flag setting add. */
11295 if (Rd
> 7 || Rn
> 7
11296 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11297 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11304 inst
.instruction
= T_OPCODE_ADD_HI
;
11305 inst
.instruction
|= (Rd
& 8) << 4;
11306 inst
.instruction
|= (Rd
& 7);
11307 inst
.instruction
|= Rn
<< 3;
11313 constraint (Rd
== REG_PC
, BAD_PC
);
11314 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11315 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11316 constraint (Rs
== REG_PC
, BAD_PC
);
11317 reject_bad_reg (Rn
);
11319 /* If we get here, it can't be done in 16 bits. */
11320 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11321 _("shift must be constant"));
11322 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11323 inst
.instruction
|= Rd
<< 8;
11324 inst
.instruction
|= Rs
<< 16;
11325 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11326 _("shift value over 3 not allowed in thumb mode"));
11327 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11328 _("only LSL shift allowed in thumb mode"));
11329 encode_thumb32_shifted_operand (2);
11334 constraint (inst
.instruction
== T_MNEM_adds
11335 || inst
.instruction
== T_MNEM_subs
,
11338 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11340 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11341 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11344 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11345 ? 0x0000 : 0x8000);
11346 inst
.instruction
|= (Rd
<< 4) | Rs
;
11347 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11351 Rn
= inst
.operands
[2].reg
;
11352 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11354 /* We now have Rd, Rs, and Rn set to registers. */
11355 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11357 /* Can't do this for SUB. */
11358 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11359 inst
.instruction
= T_OPCODE_ADD_HI
;
11360 inst
.instruction
|= (Rd
& 8) << 4;
11361 inst
.instruction
|= (Rd
& 7);
11363 inst
.instruction
|= Rn
<< 3;
11365 inst
.instruction
|= Rs
<< 3;
11367 constraint (1, _("dest must overlap one source register"));
11371 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11372 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11373 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11383 Rd
= inst
.operands
[0].reg
;
11384 reject_bad_reg (Rd
);
11386 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11388 /* Defer to section relaxation. */
11389 inst
.relax
= inst
.instruction
;
11390 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11391 inst
.instruction
|= Rd
<< 4;
11393 else if (unified_syntax
&& inst
.size_req
!= 2)
11395 /* Generate a 32-bit opcode. */
11396 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11397 inst
.instruction
|= Rd
<< 8;
11398 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11399 inst
.relocs
[0].pc_rel
= 1;
11403 /* Generate a 16-bit opcode. */
11404 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11405 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11406 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11407 inst
.relocs
[0].pc_rel
= 1;
11408 inst
.instruction
|= Rd
<< 4;
11411 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11412 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11413 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11414 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11415 inst
.relocs
[0].exp
.X_add_number
+= 1;
11418 /* Arithmetic instructions for which there is just one 16-bit
11419 instruction encoding, and it allows only two low registers.
11420 For maximal compatibility with ARM syntax, we allow three register
11421 operands even when Thumb-32 instructions are not available, as long
11422 as the first two are identical. For instance, both "sbc r0,r1" and
11423 "sbc r0,r0,r1" are allowed. */
11429 Rd
= inst
.operands
[0].reg
;
11430 Rs
= (inst
.operands
[1].present
11431 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11432 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11433 Rn
= inst
.operands
[2].reg
;
11435 reject_bad_reg (Rd
);
11436 reject_bad_reg (Rs
);
11437 if (inst
.operands
[2].isreg
)
11438 reject_bad_reg (Rn
);
11440 if (unified_syntax
)
11442 if (!inst
.operands
[2].isreg
)
11444 /* For an immediate, we always generate a 32-bit opcode;
11445 section relaxation will shrink it later if possible. */
11446 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11447 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11448 inst
.instruction
|= Rd
<< 8;
11449 inst
.instruction
|= Rs
<< 16;
11450 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11454 bfd_boolean narrow
;
11456 /* See if we can do this with a 16-bit instruction. */
11457 if (THUMB_SETS_FLAGS (inst
.instruction
))
11458 narrow
= !in_pred_block ();
11460 narrow
= in_pred_block ();
11462 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11464 if (inst
.operands
[2].shifted
)
11466 if (inst
.size_req
== 4)
11472 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11473 inst
.instruction
|= Rd
;
11474 inst
.instruction
|= Rn
<< 3;
11478 /* If we get here, it can't be done in 16 bits. */
11479 constraint (inst
.operands
[2].shifted
11480 && inst
.operands
[2].immisreg
,
11481 _("shift must be constant"));
11482 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11483 inst
.instruction
|= Rd
<< 8;
11484 inst
.instruction
|= Rs
<< 16;
11485 encode_thumb32_shifted_operand (2);
11490 /* On its face this is a lie - the instruction does set the
11491 flags. However, the only supported mnemonic in this mode
11492 says it doesn't. */
11493 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11495 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11496 _("unshifted register required"));
11497 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11498 constraint (Rd
!= Rs
,
11499 _("dest and source1 must be the same register"));
11501 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11502 inst
.instruction
|= Rd
;
11503 inst
.instruction
|= Rn
<< 3;
11507 /* Similarly, but for instructions where the arithmetic operation is
11508 commutative, so we can allow either of them to be different from
11509 the destination operand in a 16-bit instruction. For instance, all
11510 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11517 Rd
= inst
.operands
[0].reg
;
11518 Rs
= (inst
.operands
[1].present
11519 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11520 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11521 Rn
= inst
.operands
[2].reg
;
11523 reject_bad_reg (Rd
);
11524 reject_bad_reg (Rs
);
11525 if (inst
.operands
[2].isreg
)
11526 reject_bad_reg (Rn
);
11528 if (unified_syntax
)
11530 if (!inst
.operands
[2].isreg
)
11532 /* For an immediate, we always generate a 32-bit opcode;
11533 section relaxation will shrink it later if possible. */
11534 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11535 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11536 inst
.instruction
|= Rd
<< 8;
11537 inst
.instruction
|= Rs
<< 16;
11538 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11542 bfd_boolean narrow
;
11544 /* See if we can do this with a 16-bit instruction. */
11545 if (THUMB_SETS_FLAGS (inst
.instruction
))
11546 narrow
= !in_pred_block ();
11548 narrow
= in_pred_block ();
11550 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11552 if (inst
.operands
[2].shifted
)
11554 if (inst
.size_req
== 4)
11561 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11562 inst
.instruction
|= Rd
;
11563 inst
.instruction
|= Rn
<< 3;
11568 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11569 inst
.instruction
|= Rd
;
11570 inst
.instruction
|= Rs
<< 3;
11575 /* If we get here, it can't be done in 16 bits. */
11576 constraint (inst
.operands
[2].shifted
11577 && inst
.operands
[2].immisreg
,
11578 _("shift must be constant"));
11579 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11580 inst
.instruction
|= Rd
<< 8;
11581 inst
.instruction
|= Rs
<< 16;
11582 encode_thumb32_shifted_operand (2);
11587 /* On its face this is a lie - the instruction does set the
11588 flags. However, the only supported mnemonic in this mode
11589 says it doesn't. */
11590 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11592 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11593 _("unshifted register required"));
11594 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11596 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11597 inst
.instruction
|= Rd
;
11600 inst
.instruction
|= Rn
<< 3;
11602 inst
.instruction
|= Rs
<< 3;
11604 constraint (1, _("dest must overlap one source register"));
11612 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11613 constraint (msb
> 32, _("bit-field extends past end of register"));
11614 /* The instruction encoding stores the LSB and MSB,
11615 not the LSB and width. */
11616 Rd
= inst
.operands
[0].reg
;
11617 reject_bad_reg (Rd
);
11618 inst
.instruction
|= Rd
<< 8;
11619 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11620 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11621 inst
.instruction
|= msb
- 1;
11630 Rd
= inst
.operands
[0].reg
;
11631 reject_bad_reg (Rd
);
11633 /* #0 in second position is alternative syntax for bfc, which is
11634 the same instruction but with REG_PC in the Rm field. */
11635 if (!inst
.operands
[1].isreg
)
11639 Rn
= inst
.operands
[1].reg
;
11640 reject_bad_reg (Rn
);
11643 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11644 constraint (msb
> 32, _("bit-field extends past end of register"));
11645 /* The instruction encoding stores the LSB and MSB,
11646 not the LSB and width. */
11647 inst
.instruction
|= Rd
<< 8;
11648 inst
.instruction
|= Rn
<< 16;
11649 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11650 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11651 inst
.instruction
|= msb
- 1;
11659 Rd
= inst
.operands
[0].reg
;
11660 Rn
= inst
.operands
[1].reg
;
11662 reject_bad_reg (Rd
);
11663 reject_bad_reg (Rn
);
11665 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11666 _("bit-field extends past end of register"));
11667 inst
.instruction
|= Rd
<< 8;
11668 inst
.instruction
|= Rn
<< 16;
11669 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11670 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11671 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11674 /* ARM V5 Thumb BLX (argument parse)
11675 BLX <target_addr> which is BLX(1)
11676 BLX <Rm> which is BLX(2)
11677 Unfortunately, there are two different opcodes for this mnemonic.
11678 So, the insns[].value is not used, and the code here zaps values
11679 into inst.instruction.
11681 ??? How to take advantage of the additional two bits of displacement
11682 available in Thumb32 mode? Need new relocation? */
11687 set_pred_insn_type_last ();
11689 if (inst
.operands
[0].isreg
)
11691 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11692 /* We have a register, so this is BLX(2). */
11693 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11697 /* No register. This must be BLX(1). */
11698 inst
.instruction
= 0xf000e800;
11699 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11708 bfd_reloc_code_real_type reloc
;
11711 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11713 if (in_pred_block ())
11715 /* Conditional branches inside IT blocks are encoded as unconditional
11717 cond
= COND_ALWAYS
;
11722 if (cond
!= COND_ALWAYS
)
11723 opcode
= T_MNEM_bcond
;
11725 opcode
= inst
.instruction
;
11728 && (inst
.size_req
== 4
11729 || (inst
.size_req
!= 2
11730 && (inst
.operands
[0].hasreloc
11731 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11733 inst
.instruction
= THUMB_OP32(opcode
);
11734 if (cond
== COND_ALWAYS
)
11735 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11738 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11739 _("selected architecture does not support "
11740 "wide conditional branch instruction"));
11742 gas_assert (cond
!= 0xF);
11743 inst
.instruction
|= cond
<< 22;
11744 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11749 inst
.instruction
= THUMB_OP16(opcode
);
11750 if (cond
== COND_ALWAYS
)
11751 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11754 inst
.instruction
|= cond
<< 8;
11755 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11757 /* Allow section relaxation. */
11758 if (unified_syntax
&& inst
.size_req
!= 2)
11759 inst
.relax
= opcode
;
11761 inst
.relocs
[0].type
= reloc
;
11762 inst
.relocs
[0].pc_rel
= 1;
11765 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11766 between the two is the maximum immediate allowed - which is passed in
11769 do_t_bkpt_hlt1 (int range
)
11771 constraint (inst
.cond
!= COND_ALWAYS
,
11772 _("instruction is always unconditional"));
11773 if (inst
.operands
[0].present
)
11775 constraint (inst
.operands
[0].imm
> range
,
11776 _("immediate value out of range"));
11777 inst
.instruction
|= inst
.operands
[0].imm
;
11780 set_pred_insn_type (NEUTRAL_IT_INSN
);
11786 do_t_bkpt_hlt1 (63);
11792 do_t_bkpt_hlt1 (255);
11796 do_t_branch23 (void)
11798 set_pred_insn_type_last ();
11799 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11801 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11802 this file. We used to simply ignore the PLT reloc type here --
11803 the branch encoding is now needed to deal with TLSCALL relocs.
11804 So if we see a PLT reloc now, put it back to how it used to be to
11805 keep the preexisting behaviour. */
11806 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11807 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11809 #if defined(OBJ_COFF)
11810 /* If the destination of the branch is a defined symbol which does not have
11811 the THUMB_FUNC attribute, then we must be calling a function which has
11812 the (interfacearm) attribute. We look for the Thumb entry point to that
11813 function and change the branch to refer to that function instead. */
11814 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11815 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11816 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11817 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11818 inst
.relocs
[0].exp
.X_add_symbol
11819 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11826 set_pred_insn_type_last ();
11827 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11828 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11829 should cause the alignment to be checked once it is known. This is
11830 because BX PC only works if the instruction is word aligned. */
11838 set_pred_insn_type_last ();
11839 Rm
= inst
.operands
[0].reg
;
11840 reject_bad_reg (Rm
);
11841 inst
.instruction
|= Rm
<< 16;
11850 Rd
= inst
.operands
[0].reg
;
11851 Rm
= inst
.operands
[1].reg
;
11853 reject_bad_reg (Rd
);
11854 reject_bad_reg (Rm
);
11856 inst
.instruction
|= Rd
<< 8;
11857 inst
.instruction
|= Rm
<< 16;
11858 inst
.instruction
|= Rm
;
11864 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11870 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11871 inst
.instruction
|= inst
.operands
[0].imm
;
11877 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11879 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11880 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11882 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11883 inst
.instruction
= 0xf3af8000;
11884 inst
.instruction
|= imod
<< 9;
11885 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11886 if (inst
.operands
[1].present
)
11887 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11891 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11892 && (inst
.operands
[0].imm
& 4),
11893 _("selected processor does not support 'A' form "
11894 "of this instruction"));
11895 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11896 _("Thumb does not support the 2-argument "
11897 "form of this instruction"));
11898 inst
.instruction
|= inst
.operands
[0].imm
;
11902 /* THUMB CPY instruction (argument parse). */
11907 if (inst
.size_req
== 4)
11909 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11910 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11911 inst
.instruction
|= inst
.operands
[1].reg
;
11915 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11916 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11917 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11924 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11925 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11926 inst
.instruction
|= inst
.operands
[0].reg
;
11927 inst
.relocs
[0].pc_rel
= 1;
11928 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11934 inst
.instruction
|= inst
.operands
[0].imm
;
11940 unsigned Rd
, Rn
, Rm
;
11942 Rd
= inst
.operands
[0].reg
;
11943 Rn
= (inst
.operands
[1].present
11944 ? inst
.operands
[1].reg
: Rd
);
11945 Rm
= inst
.operands
[2].reg
;
11947 reject_bad_reg (Rd
);
11948 reject_bad_reg (Rn
);
11949 reject_bad_reg (Rm
);
11951 inst
.instruction
|= Rd
<< 8;
11952 inst
.instruction
|= Rn
<< 16;
11953 inst
.instruction
|= Rm
;
11959 if (unified_syntax
&& inst
.size_req
== 4)
11960 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11962 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11968 unsigned int cond
= inst
.operands
[0].imm
;
11970 set_pred_insn_type (IT_INSN
);
11971 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
11972 now_pred
.cc
= cond
;
11973 now_pred
.warn_deprecated
= FALSE
;
11974 now_pred
.type
= SCALAR_PRED
;
11976 /* If the condition is a negative condition, invert the mask. */
11977 if ((cond
& 0x1) == 0x0)
11979 unsigned int mask
= inst
.instruction
& 0x000f;
11981 if ((mask
& 0x7) == 0)
11983 /* No conversion needed. */
11984 now_pred
.block_length
= 1;
11986 else if ((mask
& 0x3) == 0)
11989 now_pred
.block_length
= 2;
11991 else if ((mask
& 0x1) == 0)
11994 now_pred
.block_length
= 3;
11999 now_pred
.block_length
= 4;
12002 inst
.instruction
&= 0xfff0;
12003 inst
.instruction
|= mask
;
12006 inst
.instruction
|= cond
<< 4;
12012 /* We are dealing with a vector predicated block. */
12013 set_pred_insn_type (VPT_INSN
);
12015 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
12016 | ((inst
.instruction
& 0xe000) >> 13);
12017 now_pred
.warn_deprecated
= FALSE
;
12018 now_pred
.type
= VECTOR_PRED
;
12021 /* Helper function used for both push/pop and ldm/stm. */
12023 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12024 bfd_boolean writeback
)
12026 bfd_boolean load
, store
;
12028 gas_assert (base
!= -1 || !do_io
);
12029 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12030 store
= do_io
&& !load
;
12032 if (mask
& (1 << 13))
12033 inst
.error
= _("SP not allowed in register list");
12035 if (do_io
&& (mask
& (1 << base
)) != 0
12037 inst
.error
= _("having the base register in the register list when "
12038 "using write back is UNPREDICTABLE");
12042 if (mask
& (1 << 15))
12044 if (mask
& (1 << 14))
12045 inst
.error
= _("LR and PC should not both be in register list");
12047 set_pred_insn_type_last ();
12052 if (mask
& (1 << 15))
12053 inst
.error
= _("PC not allowed in register list");
12056 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12058 /* Single register transfers implemented as str/ldr. */
12061 if (inst
.instruction
& (1 << 23))
12062 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12064 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12068 if (inst
.instruction
& (1 << 23))
12069 inst
.instruction
= 0x00800000; /* ia -> [base] */
12071 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12074 inst
.instruction
|= 0xf8400000;
12076 inst
.instruction
|= 0x00100000;
12078 mask
= ffs (mask
) - 1;
12081 else if (writeback
)
12082 inst
.instruction
|= WRITE_BACK
;
12084 inst
.instruction
|= mask
;
12086 inst
.instruction
|= base
<< 16;
12092 /* This really doesn't seem worth it. */
12093 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12094 _("expression too complex"));
12095 constraint (inst
.operands
[1].writeback
,
12096 _("Thumb load/store multiple does not support {reglist}^"));
12098 if (unified_syntax
)
12100 bfd_boolean narrow
;
12104 /* See if we can use a 16-bit instruction. */
12105 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12106 && inst
.size_req
!= 4
12107 && !(inst
.operands
[1].imm
& ~0xff))
12109 mask
= 1 << inst
.operands
[0].reg
;
12111 if (inst
.operands
[0].reg
<= 7)
12113 if (inst
.instruction
== T_MNEM_stmia
12114 ? inst
.operands
[0].writeback
12115 : (inst
.operands
[0].writeback
12116 == !(inst
.operands
[1].imm
& mask
)))
12118 if (inst
.instruction
== T_MNEM_stmia
12119 && (inst
.operands
[1].imm
& mask
)
12120 && (inst
.operands
[1].imm
& (mask
- 1)))
12121 as_warn (_("value stored for r%d is UNKNOWN"),
12122 inst
.operands
[0].reg
);
12124 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12125 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12126 inst
.instruction
|= inst
.operands
[1].imm
;
12129 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12131 /* This means 1 register in reg list one of 3 situations:
12132 1. Instruction is stmia, but without writeback.
12133 2. lmdia without writeback, but with Rn not in
12135 3. ldmia with writeback, but with Rn in reglist.
12136 Case 3 is UNPREDICTABLE behaviour, so we handle
12137 case 1 and 2 which can be converted into a 16-bit
12138 str or ldr. The SP cases are handled below. */
12139 unsigned long opcode
;
12140 /* First, record an error for Case 3. */
12141 if (inst
.operands
[1].imm
& mask
12142 && inst
.operands
[0].writeback
)
12144 _("having the base register in the register list when "
12145 "using write back is UNPREDICTABLE");
12147 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12149 inst
.instruction
= THUMB_OP16 (opcode
);
12150 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12151 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12155 else if (inst
.operands
[0] .reg
== REG_SP
)
12157 if (inst
.operands
[0].writeback
)
12160 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12161 ? T_MNEM_push
: T_MNEM_pop
);
12162 inst
.instruction
|= inst
.operands
[1].imm
;
12165 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12168 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12169 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12170 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12178 if (inst
.instruction
< 0xffff)
12179 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12181 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12182 inst
.operands
[1].imm
,
12183 inst
.operands
[0].writeback
);
12188 constraint (inst
.operands
[0].reg
> 7
12189 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12190 constraint (inst
.instruction
!= T_MNEM_ldmia
12191 && inst
.instruction
!= T_MNEM_stmia
,
12192 _("Thumb-2 instruction only valid in unified syntax"));
12193 if (inst
.instruction
== T_MNEM_stmia
)
12195 if (!inst
.operands
[0].writeback
)
12196 as_warn (_("this instruction will write back the base register"));
12197 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12198 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12199 as_warn (_("value stored for r%d is UNKNOWN"),
12200 inst
.operands
[0].reg
);
12204 if (!inst
.operands
[0].writeback
12205 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12206 as_warn (_("this instruction will write back the base register"));
12207 else if (inst
.operands
[0].writeback
12208 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12209 as_warn (_("this instruction will not write back the base register"));
12212 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12213 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12214 inst
.instruction
|= inst
.operands
[1].imm
;
12221 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12222 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12223 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12224 || inst
.operands
[1].negative
,
12227 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12229 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12230 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12231 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12237 if (!inst
.operands
[1].present
)
12239 constraint (inst
.operands
[0].reg
== REG_LR
,
12240 _("r14 not allowed as first register "
12241 "when second register is omitted"));
12242 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12244 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12247 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12248 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12249 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12255 unsigned long opcode
;
12258 if (inst
.operands
[0].isreg
12259 && !inst
.operands
[0].preind
12260 && inst
.operands
[0].reg
== REG_PC
)
12261 set_pred_insn_type_last ();
12263 opcode
= inst
.instruction
;
12264 if (unified_syntax
)
12266 if (!inst
.operands
[1].isreg
)
12268 if (opcode
<= 0xffff)
12269 inst
.instruction
= THUMB_OP32 (opcode
);
12270 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12273 if (inst
.operands
[1].isreg
12274 && !inst
.operands
[1].writeback
12275 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12276 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12277 && opcode
<= 0xffff
12278 && inst
.size_req
!= 4)
12280 /* Insn may have a 16-bit form. */
12281 Rn
= inst
.operands
[1].reg
;
12282 if (inst
.operands
[1].immisreg
)
12284 inst
.instruction
= THUMB_OP16 (opcode
);
12286 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12288 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12289 reject_bad_reg (inst
.operands
[1].imm
);
12291 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12292 && opcode
!= T_MNEM_ldrsb
)
12293 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12294 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12301 if (inst
.relocs
[0].pc_rel
)
12302 opcode
= T_MNEM_ldr_pc2
;
12304 opcode
= T_MNEM_ldr_pc
;
12308 if (opcode
== T_MNEM_ldr
)
12309 opcode
= T_MNEM_ldr_sp
;
12311 opcode
= T_MNEM_str_sp
;
12313 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12317 inst
.instruction
= inst
.operands
[0].reg
;
12318 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12320 inst
.instruction
|= THUMB_OP16 (opcode
);
12321 if (inst
.size_req
== 2)
12322 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12324 inst
.relax
= opcode
;
12328 /* Definitely a 32-bit variant. */
12330 /* Warning for Erratum 752419. */
12331 if (opcode
== T_MNEM_ldr
12332 && inst
.operands
[0].reg
== REG_SP
12333 && inst
.operands
[1].writeback
== 1
12334 && !inst
.operands
[1].immisreg
)
12336 if (no_cpu_selected ()
12337 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12338 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12339 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12340 as_warn (_("This instruction may be unpredictable "
12341 "if executed on M-profile cores "
12342 "with interrupts enabled."));
12345 /* Do some validations regarding addressing modes. */
12346 if (inst
.operands
[1].immisreg
)
12347 reject_bad_reg (inst
.operands
[1].imm
);
12349 constraint (inst
.operands
[1].writeback
== 1
12350 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12353 inst
.instruction
= THUMB_OP32 (opcode
);
12354 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12355 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12356 check_ldr_r15_aligned ();
12360 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12362 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12364 /* Only [Rn,Rm] is acceptable. */
12365 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12366 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12367 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12368 || inst
.operands
[1].negative
,
12369 _("Thumb does not support this addressing mode"));
12370 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12374 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12375 if (!inst
.operands
[1].isreg
)
12376 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12379 constraint (!inst
.operands
[1].preind
12380 || inst
.operands
[1].shifted
12381 || inst
.operands
[1].writeback
,
12382 _("Thumb does not support this addressing mode"));
12383 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12385 constraint (inst
.instruction
& 0x0600,
12386 _("byte or halfword not valid for base register"));
12387 constraint (inst
.operands
[1].reg
== REG_PC
12388 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12389 _("r15 based store not allowed"));
12390 constraint (inst
.operands
[1].immisreg
,
12391 _("invalid base register for register offset"));
12393 if (inst
.operands
[1].reg
== REG_PC
)
12394 inst
.instruction
= T_OPCODE_LDR_PC
;
12395 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12396 inst
.instruction
= T_OPCODE_LDR_SP
;
12398 inst
.instruction
= T_OPCODE_STR_SP
;
12400 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12401 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12405 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12406 if (!inst
.operands
[1].immisreg
)
12408 /* Immediate offset. */
12409 inst
.instruction
|= inst
.operands
[0].reg
;
12410 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12411 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12415 /* Register offset. */
12416 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12417 constraint (inst
.operands
[1].negative
,
12418 _("Thumb does not support this addressing mode"));
12421 switch (inst
.instruction
)
12423 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12424 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12425 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12426 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12427 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12428 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12429 case 0x5600 /* ldrsb */:
12430 case 0x5e00 /* ldrsh */: break;
12434 inst
.instruction
|= inst
.operands
[0].reg
;
12435 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12436 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12442 if (!inst
.operands
[1].present
)
12444 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12445 constraint (inst
.operands
[0].reg
== REG_LR
,
12446 _("r14 not allowed here"));
12447 constraint (inst
.operands
[0].reg
== REG_R12
,
12448 _("r12 not allowed here"));
12451 if (inst
.operands
[2].writeback
12452 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12453 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12454 as_warn (_("base register written back, and overlaps "
12455 "one of transfer registers"));
12457 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12458 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12459 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12465 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12466 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12472 unsigned Rd
, Rn
, Rm
, Ra
;
12474 Rd
= inst
.operands
[0].reg
;
12475 Rn
= inst
.operands
[1].reg
;
12476 Rm
= inst
.operands
[2].reg
;
12477 Ra
= inst
.operands
[3].reg
;
12479 reject_bad_reg (Rd
);
12480 reject_bad_reg (Rn
);
12481 reject_bad_reg (Rm
);
12482 reject_bad_reg (Ra
);
12484 inst
.instruction
|= Rd
<< 8;
12485 inst
.instruction
|= Rn
<< 16;
12486 inst
.instruction
|= Rm
;
12487 inst
.instruction
|= Ra
<< 12;
12493 unsigned RdLo
, RdHi
, Rn
, Rm
;
12495 RdLo
= inst
.operands
[0].reg
;
12496 RdHi
= inst
.operands
[1].reg
;
12497 Rn
= inst
.operands
[2].reg
;
12498 Rm
= inst
.operands
[3].reg
;
12500 reject_bad_reg (RdLo
);
12501 reject_bad_reg (RdHi
);
12502 reject_bad_reg (Rn
);
12503 reject_bad_reg (Rm
);
12505 inst
.instruction
|= RdLo
<< 12;
12506 inst
.instruction
|= RdHi
<< 8;
12507 inst
.instruction
|= Rn
<< 16;
12508 inst
.instruction
|= Rm
;
12512 do_t_mov_cmp (void)
12516 Rn
= inst
.operands
[0].reg
;
12517 Rm
= inst
.operands
[1].reg
;
12520 set_pred_insn_type_last ();
12522 if (unified_syntax
)
12524 int r0off
= (inst
.instruction
== T_MNEM_mov
12525 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12526 unsigned long opcode
;
12527 bfd_boolean narrow
;
12528 bfd_boolean low_regs
;
12530 low_regs
= (Rn
<= 7 && Rm
<= 7);
12531 opcode
= inst
.instruction
;
12532 if (in_pred_block ())
12533 narrow
= opcode
!= T_MNEM_movs
;
12535 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12536 if (inst
.size_req
== 4
12537 || inst
.operands
[1].shifted
)
12540 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12541 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12542 && !inst
.operands
[1].shifted
12546 inst
.instruction
= T2_SUBS_PC_LR
;
12550 if (opcode
== T_MNEM_cmp
)
12552 constraint (Rn
== REG_PC
, BAD_PC
);
12555 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12557 warn_deprecated_sp (Rm
);
12558 /* R15 was documented as a valid choice for Rm in ARMv6,
12559 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12560 tools reject R15, so we do too. */
12561 constraint (Rm
== REG_PC
, BAD_PC
);
12564 reject_bad_reg (Rm
);
12566 else if (opcode
== T_MNEM_mov
12567 || opcode
== T_MNEM_movs
)
12569 if (inst
.operands
[1].isreg
)
12571 if (opcode
== T_MNEM_movs
)
12573 reject_bad_reg (Rn
);
12574 reject_bad_reg (Rm
);
12578 /* This is mov.n. */
12579 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12580 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12582 as_tsktsk (_("Use of r%u as a source register is "
12583 "deprecated when r%u is the destination "
12584 "register."), Rm
, Rn
);
12589 /* This is mov.w. */
12590 constraint (Rn
== REG_PC
, BAD_PC
);
12591 constraint (Rm
== REG_PC
, BAD_PC
);
12592 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12593 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12597 reject_bad_reg (Rn
);
12600 if (!inst
.operands
[1].isreg
)
12602 /* Immediate operand. */
12603 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12605 if (low_regs
&& narrow
)
12607 inst
.instruction
= THUMB_OP16 (opcode
);
12608 inst
.instruction
|= Rn
<< 8;
12609 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12610 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12612 if (inst
.size_req
== 2)
12613 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12615 inst
.relax
= opcode
;
12620 constraint ((inst
.relocs
[0].type
12621 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12622 && (inst
.relocs
[0].type
12623 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12624 THUMB1_RELOC_ONLY
);
12626 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12627 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12628 inst
.instruction
|= Rn
<< r0off
;
12629 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12632 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12633 && (inst
.instruction
== T_MNEM_mov
12634 || inst
.instruction
== T_MNEM_movs
))
12636 /* Register shifts are encoded as separate shift instructions. */
12637 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12639 if (in_pred_block ())
12644 if (inst
.size_req
== 4)
12647 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12653 switch (inst
.operands
[1].shift_kind
)
12656 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12659 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12662 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12665 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12671 inst
.instruction
= opcode
;
12674 inst
.instruction
|= Rn
;
12675 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12680 inst
.instruction
|= CONDS_BIT
;
12682 inst
.instruction
|= Rn
<< 8;
12683 inst
.instruction
|= Rm
<< 16;
12684 inst
.instruction
|= inst
.operands
[1].imm
;
12689 /* Some mov with immediate shift have narrow variants.
12690 Register shifts are handled above. */
12691 if (low_regs
&& inst
.operands
[1].shifted
12692 && (inst
.instruction
== T_MNEM_mov
12693 || inst
.instruction
== T_MNEM_movs
))
12695 if (in_pred_block ())
12696 narrow
= (inst
.instruction
== T_MNEM_mov
);
12698 narrow
= (inst
.instruction
== T_MNEM_movs
);
12703 switch (inst
.operands
[1].shift_kind
)
12705 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12706 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12707 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12708 default: narrow
= FALSE
; break;
12714 inst
.instruction
|= Rn
;
12715 inst
.instruction
|= Rm
<< 3;
12716 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12720 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12721 inst
.instruction
|= Rn
<< r0off
;
12722 encode_thumb32_shifted_operand (1);
12726 switch (inst
.instruction
)
12729 /* In v4t or v5t a move of two lowregs produces unpredictable
12730 results. Don't allow this. */
12733 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12734 "MOV Rd, Rs with two low registers is not "
12735 "permitted on this architecture");
12736 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12740 inst
.instruction
= T_OPCODE_MOV_HR
;
12741 inst
.instruction
|= (Rn
& 0x8) << 4;
12742 inst
.instruction
|= (Rn
& 0x7);
12743 inst
.instruction
|= Rm
<< 3;
12747 /* We know we have low registers at this point.
12748 Generate LSLS Rd, Rs, #0. */
12749 inst
.instruction
= T_OPCODE_LSL_I
;
12750 inst
.instruction
|= Rn
;
12751 inst
.instruction
|= Rm
<< 3;
12757 inst
.instruction
= T_OPCODE_CMP_LR
;
12758 inst
.instruction
|= Rn
;
12759 inst
.instruction
|= Rm
<< 3;
12763 inst
.instruction
= T_OPCODE_CMP_HR
;
12764 inst
.instruction
|= (Rn
& 0x8) << 4;
12765 inst
.instruction
|= (Rn
& 0x7);
12766 inst
.instruction
|= Rm
<< 3;
12773 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12775 /* PR 10443: Do not silently ignore shifted operands. */
12776 constraint (inst
.operands
[1].shifted
,
12777 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12779 if (inst
.operands
[1].isreg
)
12781 if (Rn
< 8 && Rm
< 8)
12783 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12784 since a MOV instruction produces unpredictable results. */
12785 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12786 inst
.instruction
= T_OPCODE_ADD_I3
;
12788 inst
.instruction
= T_OPCODE_CMP_LR
;
12790 inst
.instruction
|= Rn
;
12791 inst
.instruction
|= Rm
<< 3;
12795 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12796 inst
.instruction
= T_OPCODE_MOV_HR
;
12798 inst
.instruction
= T_OPCODE_CMP_HR
;
12804 constraint (Rn
> 7,
12805 _("only lo regs allowed with immediate"));
12806 inst
.instruction
|= Rn
<< 8;
12807 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12818 top
= (inst
.instruction
& 0x00800000) != 0;
12819 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12821 constraint (top
, _(":lower16: not allowed in this instruction"));
12822 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12824 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12826 constraint (!top
, _(":upper16: not allowed in this instruction"));
12827 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12830 Rd
= inst
.operands
[0].reg
;
12831 reject_bad_reg (Rd
);
12833 inst
.instruction
|= Rd
<< 8;
12834 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12836 imm
= inst
.relocs
[0].exp
.X_add_number
;
12837 inst
.instruction
|= (imm
& 0xf000) << 4;
12838 inst
.instruction
|= (imm
& 0x0800) << 15;
12839 inst
.instruction
|= (imm
& 0x0700) << 4;
12840 inst
.instruction
|= (imm
& 0x00ff);
12845 do_t_mvn_tst (void)
12849 Rn
= inst
.operands
[0].reg
;
12850 Rm
= inst
.operands
[1].reg
;
12852 if (inst
.instruction
== T_MNEM_cmp
12853 || inst
.instruction
== T_MNEM_cmn
)
12854 constraint (Rn
== REG_PC
, BAD_PC
);
12856 reject_bad_reg (Rn
);
12857 reject_bad_reg (Rm
);
12859 if (unified_syntax
)
12861 int r0off
= (inst
.instruction
== T_MNEM_mvn
12862 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12863 bfd_boolean narrow
;
12865 if (inst
.size_req
== 4
12866 || inst
.instruction
> 0xffff
12867 || inst
.operands
[1].shifted
12868 || Rn
> 7 || Rm
> 7)
12870 else if (inst
.instruction
== T_MNEM_cmn
12871 || inst
.instruction
== T_MNEM_tst
)
12873 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12874 narrow
= !in_pred_block ();
12876 narrow
= in_pred_block ();
12878 if (!inst
.operands
[1].isreg
)
12880 /* For an immediate, we always generate a 32-bit opcode;
12881 section relaxation will shrink it later if possible. */
12882 if (inst
.instruction
< 0xffff)
12883 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12884 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12885 inst
.instruction
|= Rn
<< r0off
;
12886 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12890 /* See if we can do this with a 16-bit instruction. */
12893 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12894 inst
.instruction
|= Rn
;
12895 inst
.instruction
|= Rm
<< 3;
12899 constraint (inst
.operands
[1].shifted
12900 && inst
.operands
[1].immisreg
,
12901 _("shift must be constant"));
12902 if (inst
.instruction
< 0xffff)
12903 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12904 inst
.instruction
|= Rn
<< r0off
;
12905 encode_thumb32_shifted_operand (1);
12911 constraint (inst
.instruction
> 0xffff
12912 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12913 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12914 _("unshifted register required"));
12915 constraint (Rn
> 7 || Rm
> 7,
12918 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12919 inst
.instruction
|= Rn
;
12920 inst
.instruction
|= Rm
<< 3;
12929 if (do_vfp_nsyn_mrs () == SUCCESS
)
12932 Rd
= inst
.operands
[0].reg
;
12933 reject_bad_reg (Rd
);
12934 inst
.instruction
|= Rd
<< 8;
12936 if (inst
.operands
[1].isreg
)
12938 unsigned br
= inst
.operands
[1].reg
;
12939 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12940 as_bad (_("bad register for mrs"));
12942 inst
.instruction
|= br
& (0xf << 16);
12943 inst
.instruction
|= (br
& 0x300) >> 4;
12944 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12948 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12950 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12952 /* PR gas/12698: The constraint is only applied for m_profile.
12953 If the user has specified -march=all, we want to ignore it as
12954 we are building for any CPU type, including non-m variants. */
12955 bfd_boolean m_profile
=
12956 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12957 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12958 "not support requested special purpose register"));
12961 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12963 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12964 _("'APSR', 'CPSR' or 'SPSR' expected"));
12966 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12967 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12968 inst
.instruction
|= 0xf0000;
12978 if (do_vfp_nsyn_msr () == SUCCESS
)
12981 constraint (!inst
.operands
[1].isreg
,
12982 _("Thumb encoding does not support an immediate here"));
12984 if (inst
.operands
[0].isreg
)
12985 flags
= (int)(inst
.operands
[0].reg
);
12987 flags
= inst
.operands
[0].imm
;
12989 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12991 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12993 /* PR gas/12698: The constraint is only applied for m_profile.
12994 If the user has specified -march=all, we want to ignore it as
12995 we are building for any CPU type, including non-m variants. */
12996 bfd_boolean m_profile
=
12997 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12998 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12999 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13000 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13001 && bits
!= PSR_f
)) && m_profile
,
13002 _("selected processor does not support requested special "
13003 "purpose register"));
13006 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13007 "requested special purpose register"));
13009 Rn
= inst
.operands
[1].reg
;
13010 reject_bad_reg (Rn
);
13012 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13013 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13014 inst
.instruction
|= (flags
& 0x300) >> 4;
13015 inst
.instruction
|= (flags
& 0xff);
13016 inst
.instruction
|= Rn
<< 16;
13022 bfd_boolean narrow
;
13023 unsigned Rd
, Rn
, Rm
;
13025 if (!inst
.operands
[2].present
)
13026 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13028 Rd
= inst
.operands
[0].reg
;
13029 Rn
= inst
.operands
[1].reg
;
13030 Rm
= inst
.operands
[2].reg
;
13032 if (unified_syntax
)
13034 if (inst
.size_req
== 4
13040 else if (inst
.instruction
== T_MNEM_muls
)
13041 narrow
= !in_pred_block ();
13043 narrow
= in_pred_block ();
13047 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13048 constraint (Rn
> 7 || Rm
> 7,
13055 /* 16-bit MULS/Conditional MUL. */
13056 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13057 inst
.instruction
|= Rd
;
13060 inst
.instruction
|= Rm
<< 3;
13062 inst
.instruction
|= Rn
<< 3;
13064 constraint (1, _("dest must overlap one source register"));
13068 constraint (inst
.instruction
!= T_MNEM_mul
,
13069 _("Thumb-2 MUL must not set flags"));
13071 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13072 inst
.instruction
|= Rd
<< 8;
13073 inst
.instruction
|= Rn
<< 16;
13074 inst
.instruction
|= Rm
<< 0;
13076 reject_bad_reg (Rd
);
13077 reject_bad_reg (Rn
);
13078 reject_bad_reg (Rm
);
13085 unsigned RdLo
, RdHi
, Rn
, Rm
;
13087 RdLo
= inst
.operands
[0].reg
;
13088 RdHi
= inst
.operands
[1].reg
;
13089 Rn
= inst
.operands
[2].reg
;
13090 Rm
= inst
.operands
[3].reg
;
13092 reject_bad_reg (RdLo
);
13093 reject_bad_reg (RdHi
);
13094 reject_bad_reg (Rn
);
13095 reject_bad_reg (Rm
);
13097 inst
.instruction
|= RdLo
<< 12;
13098 inst
.instruction
|= RdHi
<< 8;
13099 inst
.instruction
|= Rn
<< 16;
13100 inst
.instruction
|= Rm
;
13103 as_tsktsk (_("rdhi and rdlo must be different"));
13109 set_pred_insn_type (NEUTRAL_IT_INSN
);
13111 if (unified_syntax
)
13113 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13115 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13116 inst
.instruction
|= inst
.operands
[0].imm
;
13120 /* PR9722: Check for Thumb2 availability before
13121 generating a thumb2 nop instruction. */
13122 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13124 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13125 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13128 inst
.instruction
= 0x46c0;
13133 constraint (inst
.operands
[0].present
,
13134 _("Thumb does not support NOP with hints"));
13135 inst
.instruction
= 0x46c0;
13142 if (unified_syntax
)
13144 bfd_boolean narrow
;
13146 if (THUMB_SETS_FLAGS (inst
.instruction
))
13147 narrow
= !in_pred_block ();
13149 narrow
= in_pred_block ();
13150 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13152 if (inst
.size_req
== 4)
13157 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13158 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13159 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13163 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13164 inst
.instruction
|= inst
.operands
[0].reg
;
13165 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13170 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13172 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13174 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13175 inst
.instruction
|= inst
.operands
[0].reg
;
13176 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13185 Rd
= inst
.operands
[0].reg
;
13186 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13188 reject_bad_reg (Rd
);
13189 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13190 reject_bad_reg (Rn
);
13192 inst
.instruction
|= Rd
<< 8;
13193 inst
.instruction
|= Rn
<< 16;
13195 if (!inst
.operands
[2].isreg
)
13197 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13198 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13204 Rm
= inst
.operands
[2].reg
;
13205 reject_bad_reg (Rm
);
13207 constraint (inst
.operands
[2].shifted
13208 && inst
.operands
[2].immisreg
,
13209 _("shift must be constant"));
13210 encode_thumb32_shifted_operand (2);
13217 unsigned Rd
, Rn
, Rm
;
13219 Rd
= inst
.operands
[0].reg
;
13220 Rn
= inst
.operands
[1].reg
;
13221 Rm
= inst
.operands
[2].reg
;
13223 reject_bad_reg (Rd
);
13224 reject_bad_reg (Rn
);
13225 reject_bad_reg (Rm
);
13227 inst
.instruction
|= Rd
<< 8;
13228 inst
.instruction
|= Rn
<< 16;
13229 inst
.instruction
|= Rm
;
13230 if (inst
.operands
[3].present
)
13232 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13233 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13234 _("expression too complex"));
13235 inst
.instruction
|= (val
& 0x1c) << 10;
13236 inst
.instruction
|= (val
& 0x03) << 6;
13243 if (!inst
.operands
[3].present
)
13247 inst
.instruction
&= ~0x00000020;
13249 /* PR 10168. Swap the Rm and Rn registers. */
13250 Rtmp
= inst
.operands
[1].reg
;
13251 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13252 inst
.operands
[2].reg
= Rtmp
;
13260 if (inst
.operands
[0].immisreg
)
13261 reject_bad_reg (inst
.operands
[0].imm
);
13263 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13267 do_t_push_pop (void)
13271 constraint (inst
.operands
[0].writeback
,
13272 _("push/pop do not support {reglist}^"));
13273 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13274 _("expression too complex"));
13276 mask
= inst
.operands
[0].imm
;
13277 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13278 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13279 else if (inst
.size_req
!= 4
13280 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13281 ? REG_LR
: REG_PC
)))
13283 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13284 inst
.instruction
|= THUMB_PP_PC_LR
;
13285 inst
.instruction
|= mask
& 0xff;
13287 else if (unified_syntax
)
13289 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13290 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13294 inst
.error
= _("invalid register list to push/pop instruction");
13302 if (unified_syntax
)
13303 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13306 inst
.error
= _("invalid register list to push/pop instruction");
13312 do_t_vscclrm (void)
13314 if (inst
.operands
[0].issingle
)
13316 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13317 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13318 inst
.instruction
|= inst
.operands
[0].imm
;
13322 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13323 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13324 inst
.instruction
|= 1 << 8;
13325 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13334 Rd
= inst
.operands
[0].reg
;
13335 Rm
= inst
.operands
[1].reg
;
13337 reject_bad_reg (Rd
);
13338 reject_bad_reg (Rm
);
13340 inst
.instruction
|= Rd
<< 8;
13341 inst
.instruction
|= Rm
<< 16;
13342 inst
.instruction
|= Rm
;
13350 Rd
= inst
.operands
[0].reg
;
13351 Rm
= inst
.operands
[1].reg
;
13353 reject_bad_reg (Rd
);
13354 reject_bad_reg (Rm
);
13356 if (Rd
<= 7 && Rm
<= 7
13357 && inst
.size_req
!= 4)
13359 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13360 inst
.instruction
|= Rd
;
13361 inst
.instruction
|= Rm
<< 3;
13363 else if (unified_syntax
)
13365 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13366 inst
.instruction
|= Rd
<< 8;
13367 inst
.instruction
|= Rm
<< 16;
13368 inst
.instruction
|= Rm
;
13371 inst
.error
= BAD_HIREG
;
13379 Rd
= inst
.operands
[0].reg
;
13380 Rm
= inst
.operands
[1].reg
;
13382 reject_bad_reg (Rd
);
13383 reject_bad_reg (Rm
);
13385 inst
.instruction
|= Rd
<< 8;
13386 inst
.instruction
|= Rm
;
13394 Rd
= inst
.operands
[0].reg
;
13395 Rs
= (inst
.operands
[1].present
13396 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13397 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13399 reject_bad_reg (Rd
);
13400 reject_bad_reg (Rs
);
13401 if (inst
.operands
[2].isreg
)
13402 reject_bad_reg (inst
.operands
[2].reg
);
13404 inst
.instruction
|= Rd
<< 8;
13405 inst
.instruction
|= Rs
<< 16;
13406 if (!inst
.operands
[2].isreg
)
13408 bfd_boolean narrow
;
13410 if ((inst
.instruction
& 0x00100000) != 0)
13411 narrow
= !in_pred_block ();
13413 narrow
= in_pred_block ();
13415 if (Rd
> 7 || Rs
> 7)
13418 if (inst
.size_req
== 4 || !unified_syntax
)
13421 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13422 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13425 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13426 relaxation, but it doesn't seem worth the hassle. */
13429 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13430 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13431 inst
.instruction
|= Rs
<< 3;
13432 inst
.instruction
|= Rd
;
13436 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13437 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13441 encode_thumb32_shifted_operand (2);
13447 if (warn_on_deprecated
13448 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13449 as_tsktsk (_("setend use is deprecated for ARMv8"));
13451 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13452 if (inst
.operands
[0].imm
)
13453 inst
.instruction
|= 0x8;
13459 if (!inst
.operands
[1].present
)
13460 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13462 if (unified_syntax
)
13464 bfd_boolean narrow
;
13467 switch (inst
.instruction
)
13470 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13472 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13474 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13476 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13480 if (THUMB_SETS_FLAGS (inst
.instruction
))
13481 narrow
= !in_pred_block ();
13483 narrow
= in_pred_block ();
13484 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13486 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13488 if (inst
.operands
[2].isreg
13489 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13490 || inst
.operands
[2].reg
> 7))
13492 if (inst
.size_req
== 4)
13495 reject_bad_reg (inst
.operands
[0].reg
);
13496 reject_bad_reg (inst
.operands
[1].reg
);
13500 if (inst
.operands
[2].isreg
)
13502 reject_bad_reg (inst
.operands
[2].reg
);
13503 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13504 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13505 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13506 inst
.instruction
|= inst
.operands
[2].reg
;
13508 /* PR 12854: Error on extraneous shifts. */
13509 constraint (inst
.operands
[2].shifted
,
13510 _("extraneous shift as part of operand to shift insn"));
13514 inst
.operands
[1].shifted
= 1;
13515 inst
.operands
[1].shift_kind
= shift_kind
;
13516 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13517 ? T_MNEM_movs
: T_MNEM_mov
);
13518 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13519 encode_thumb32_shifted_operand (1);
13520 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13521 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13526 if (inst
.operands
[2].isreg
)
13528 switch (shift_kind
)
13530 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13531 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13532 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13533 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13537 inst
.instruction
|= inst
.operands
[0].reg
;
13538 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13540 /* PR 12854: Error on extraneous shifts. */
13541 constraint (inst
.operands
[2].shifted
,
13542 _("extraneous shift as part of operand to shift insn"));
13546 switch (shift_kind
)
13548 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13549 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13550 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13553 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13554 inst
.instruction
|= inst
.operands
[0].reg
;
13555 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13561 constraint (inst
.operands
[0].reg
> 7
13562 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13563 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13565 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13567 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13568 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13569 _("source1 and dest must be same register"));
13571 switch (inst
.instruction
)
13573 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13574 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13575 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13576 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13580 inst
.instruction
|= inst
.operands
[0].reg
;
13581 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13583 /* PR 12854: Error on extraneous shifts. */
13584 constraint (inst
.operands
[2].shifted
,
13585 _("extraneous shift as part of operand to shift insn"));
13589 switch (inst
.instruction
)
13591 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13592 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13593 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13594 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13597 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13598 inst
.instruction
|= inst
.operands
[0].reg
;
13599 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13607 unsigned Rd
, Rn
, Rm
;
13609 Rd
= inst
.operands
[0].reg
;
13610 Rn
= inst
.operands
[1].reg
;
13611 Rm
= inst
.operands
[2].reg
;
13613 reject_bad_reg (Rd
);
13614 reject_bad_reg (Rn
);
13615 reject_bad_reg (Rm
);
13617 inst
.instruction
|= Rd
<< 8;
13618 inst
.instruction
|= Rn
<< 16;
13619 inst
.instruction
|= Rm
;
13625 unsigned Rd
, Rn
, Rm
;
13627 Rd
= inst
.operands
[0].reg
;
13628 Rm
= inst
.operands
[1].reg
;
13629 Rn
= inst
.operands
[2].reg
;
13631 reject_bad_reg (Rd
);
13632 reject_bad_reg (Rn
);
13633 reject_bad_reg (Rm
);
13635 inst
.instruction
|= Rd
<< 8;
13636 inst
.instruction
|= Rn
<< 16;
13637 inst
.instruction
|= Rm
;
13643 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13644 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13645 _("SMC is not permitted on this architecture"));
13646 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13647 _("expression too complex"));
13648 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13649 inst
.instruction
|= (value
& 0xf000) >> 12;
13650 inst
.instruction
|= (value
& 0x0ff0);
13651 inst
.instruction
|= (value
& 0x000f) << 16;
13652 /* PR gas/15623: SMC instructions must be last in an IT block. */
13653 set_pred_insn_type_last ();
13659 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13661 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13662 inst
.instruction
|= (value
& 0x0fff);
13663 inst
.instruction
|= (value
& 0xf000) << 4;
13667 do_t_ssat_usat (int bias
)
13671 Rd
= inst
.operands
[0].reg
;
13672 Rn
= inst
.operands
[2].reg
;
13674 reject_bad_reg (Rd
);
13675 reject_bad_reg (Rn
);
13677 inst
.instruction
|= Rd
<< 8;
13678 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13679 inst
.instruction
|= Rn
<< 16;
13681 if (inst
.operands
[3].present
)
13683 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13685 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13687 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13688 _("expression too complex"));
13690 if (shift_amount
!= 0)
13692 constraint (shift_amount
> 31,
13693 _("shift expression is too large"));
13695 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13696 inst
.instruction
|= 0x00200000; /* sh bit. */
13698 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13699 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13707 do_t_ssat_usat (1);
13715 Rd
= inst
.operands
[0].reg
;
13716 Rn
= inst
.operands
[2].reg
;
13718 reject_bad_reg (Rd
);
13719 reject_bad_reg (Rn
);
13721 inst
.instruction
|= Rd
<< 8;
13722 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13723 inst
.instruction
|= Rn
<< 16;
13729 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13730 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13731 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13732 || inst
.operands
[2].negative
,
13735 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13737 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13738 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13739 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13740 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13746 if (!inst
.operands
[2].present
)
13747 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13749 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13750 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13751 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13754 inst
.instruction
|= inst
.operands
[0].reg
;
13755 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13756 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13757 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13763 unsigned Rd
, Rn
, Rm
;
13765 Rd
= inst
.operands
[0].reg
;
13766 Rn
= inst
.operands
[1].reg
;
13767 Rm
= inst
.operands
[2].reg
;
13769 reject_bad_reg (Rd
);
13770 reject_bad_reg (Rn
);
13771 reject_bad_reg (Rm
);
13773 inst
.instruction
|= Rd
<< 8;
13774 inst
.instruction
|= Rn
<< 16;
13775 inst
.instruction
|= Rm
;
13776 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13784 Rd
= inst
.operands
[0].reg
;
13785 Rm
= inst
.operands
[1].reg
;
13787 reject_bad_reg (Rd
);
13788 reject_bad_reg (Rm
);
13790 if (inst
.instruction
<= 0xffff
13791 && inst
.size_req
!= 4
13792 && Rd
<= 7 && Rm
<= 7
13793 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13795 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13796 inst
.instruction
|= Rd
;
13797 inst
.instruction
|= Rm
<< 3;
13799 else if (unified_syntax
)
13801 if (inst
.instruction
<= 0xffff)
13802 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13803 inst
.instruction
|= Rd
<< 8;
13804 inst
.instruction
|= Rm
;
13805 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13809 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13810 _("Thumb encoding does not support rotation"));
13811 constraint (1, BAD_HIREG
);
13818 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13827 half
= (inst
.instruction
& 0x10) != 0;
13828 set_pred_insn_type_last ();
13829 constraint (inst
.operands
[0].immisreg
,
13830 _("instruction requires register index"));
13832 Rn
= inst
.operands
[0].reg
;
13833 Rm
= inst
.operands
[0].imm
;
13835 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13836 constraint (Rn
== REG_SP
, BAD_SP
);
13837 reject_bad_reg (Rm
);
13839 constraint (!half
&& inst
.operands
[0].shifted
,
13840 _("instruction does not allow shifted index"));
13841 inst
.instruction
|= (Rn
<< 16) | Rm
;
13847 if (!inst
.operands
[0].present
)
13848 inst
.operands
[0].imm
= 0;
13850 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13852 constraint (inst
.size_req
== 2,
13853 _("immediate value out of range"));
13854 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13855 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13856 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13860 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13861 inst
.instruction
|= inst
.operands
[0].imm
;
13864 set_pred_insn_type (NEUTRAL_IT_INSN
);
13871 do_t_ssat_usat (0);
13879 Rd
= inst
.operands
[0].reg
;
13880 Rn
= inst
.operands
[2].reg
;
13882 reject_bad_reg (Rd
);
13883 reject_bad_reg (Rn
);
13885 inst
.instruction
|= Rd
<< 8;
13886 inst
.instruction
|= inst
.operands
[1].imm
;
13887 inst
.instruction
|= Rn
<< 16;
13890 /* Checking the range of the branch offset (VAL) with NBITS bits
13891 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13893 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13895 gas_assert (nbits
> 0 && nbits
<= 32);
13898 int cmp
= (1 << (nbits
- 1));
13899 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13904 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13910 /* For branches in Armv8.1-M Mainline. */
13912 do_t_branch_future (void)
13914 unsigned long insn
= inst
.instruction
;
13916 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13917 if (inst
.operands
[0].hasreloc
== 0)
13919 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13920 as_bad (BAD_BRANCH_OFF
);
13922 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
13926 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
13927 inst
.relocs
[0].pc_rel
= 1;
13933 if (inst
.operands
[1].hasreloc
== 0)
13935 int val
= inst
.operands
[1].imm
;
13936 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
13937 as_bad (BAD_BRANCH_OFF
);
13939 int immA
= (val
& 0x0001f000) >> 12;
13940 int immB
= (val
& 0x00000ffc) >> 2;
13941 int immC
= (val
& 0x00000002) >> 1;
13942 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13946 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
13947 inst
.relocs
[1].pc_rel
= 1;
13952 if (inst
.operands
[1].hasreloc
== 0)
13954 int val
= inst
.operands
[1].imm
;
13955 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
13956 as_bad (BAD_BRANCH_OFF
);
13958 int immA
= (val
& 0x0007f000) >> 12;
13959 int immB
= (val
& 0x00000ffc) >> 2;
13960 int immC
= (val
& 0x00000002) >> 1;
13961 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13965 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
13966 inst
.relocs
[1].pc_rel
= 1;
13970 case T_MNEM_bfcsel
:
13972 if (inst
.operands
[1].hasreloc
== 0)
13974 int val
= inst
.operands
[1].imm
;
13975 int immA
= (val
& 0x00001000) >> 12;
13976 int immB
= (val
& 0x00000ffc) >> 2;
13977 int immC
= (val
& 0x00000002) >> 1;
13978 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13982 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
13983 inst
.relocs
[1].pc_rel
= 1;
13987 if (inst
.operands
[2].hasreloc
== 0)
13989 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
13990 int val2
= inst
.operands
[2].imm
;
13991 int val0
= inst
.operands
[0].imm
& 0x1f;
13992 int diff
= val2
- val0
;
13994 inst
.instruction
|= 1 << 17; /* T bit. */
13995 else if (diff
!= 2)
13996 as_bad (_("out of range label-relative fixup value"));
14000 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14001 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14002 inst
.relocs
[2].pc_rel
= 1;
14006 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14007 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14012 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14019 /* Helper function for do_t_loloop to handle relocations. */
14021 v8_1_loop_reloc (int is_le
)
14023 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14025 int value
= inst
.relocs
[0].exp
.X_add_number
;
14026 value
= (is_le
) ? -value
: value
;
14028 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14029 as_bad (BAD_BRANCH_OFF
);
14033 immh
= (value
& 0x00000ffc) >> 2;
14034 imml
= (value
& 0x00000002) >> 1;
14036 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14040 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14041 inst
.relocs
[0].pc_rel
= 1;
14045 /* To handle the Scalar Low Overhead Loop instructions
14046 in Armv8.1-M Mainline. */
14050 unsigned long insn
= inst
.instruction
;
14052 set_pred_insn_type (OUTSIDE_PRED_INSN
);
14053 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14059 if (!inst
.operands
[0].present
)
14060 inst
.instruction
|= 1 << 21;
14062 v8_1_loop_reloc (TRUE
);
14066 v8_1_loop_reloc (FALSE
);
14067 /* Fall through. */
14069 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
14070 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
14077 /* MVE instruction encoder helpers. */
14078 #define M_MNEM_vabav 0xee800f01
14079 #define M_MNEM_vmladav 0xeef00e00
14080 #define M_MNEM_vmladava 0xeef00e20
14081 #define M_MNEM_vmladavx 0xeef01e00
14082 #define M_MNEM_vmladavax 0xeef01e20
14083 #define M_MNEM_vmlsdav 0xeef00e01
14084 #define M_MNEM_vmlsdava 0xeef00e21
14085 #define M_MNEM_vmlsdavx 0xeef01e01
14086 #define M_MNEM_vmlsdavax 0xeef01e21
14087 #define M_MNEM_vmullt 0xee011e00
14088 #define M_MNEM_vmullb 0xee010e00
14089 #define M_MNEM_vst20 0xfc801e00
14090 #define M_MNEM_vst21 0xfc801e20
14091 #define M_MNEM_vst40 0xfc801e01
14092 #define M_MNEM_vst41 0xfc801e21
14093 #define M_MNEM_vst42 0xfc801e41
14094 #define M_MNEM_vst43 0xfc801e61
14095 #define M_MNEM_vld20 0xfc901e00
14096 #define M_MNEM_vld21 0xfc901e20
14097 #define M_MNEM_vld40 0xfc901e01
14098 #define M_MNEM_vld41 0xfc901e21
14099 #define M_MNEM_vld42 0xfc901e41
14100 #define M_MNEM_vld43 0xfc901e61
14101 #define M_MNEM_vstrb 0xec000e00
14102 #define M_MNEM_vstrh 0xec000e10
14103 #define M_MNEM_vstrw 0xec000e40
14104 #define M_MNEM_vstrd 0xec000e50
14105 #define M_MNEM_vldrb 0xec100e00
14106 #define M_MNEM_vldrh 0xec100e10
14107 #define M_MNEM_vldrw 0xec100e40
14108 #define M_MNEM_vldrd 0xec100e50
14109 #define M_MNEM_vmovlt 0xeea01f40
14110 #define M_MNEM_vmovlb 0xeea00f40
14111 #define M_MNEM_vmovnt 0xfe311e81
14112 #define M_MNEM_vmovnb 0xfe310e81
14114 /* Neon instruction encoder helpers. */
14116 /* Encodings for the different types for various Neon opcodes. */
14118 /* An "invalid" code for the following tables. */
14121 struct neon_tab_entry
14124 unsigned float_or_poly
;
14125 unsigned scalar_or_imm
;
14128 /* Map overloaded Neon opcodes to their respective encodings. */
14129 #define NEON_ENC_TAB \
14130 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14131 X(vabdl, 0x0800700, N_INV, N_INV), \
14132 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14133 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14134 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14135 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14136 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14137 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14138 X(vaddl, 0x0800000, N_INV, N_INV), \
14139 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14140 X(vsubl, 0x0800200, N_INV, N_INV), \
14141 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14142 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14143 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14144 /* Register variants of the following two instructions are encoded as
14145 vcge / vcgt with the operands reversed. */ \
14146 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14147 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14148 X(vfma, N_INV, 0x0000c10, N_INV), \
14149 X(vfms, N_INV, 0x0200c10, N_INV), \
14150 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14151 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14152 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14153 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14154 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14155 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14156 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14157 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14158 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14159 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14160 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14161 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14162 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14163 X(vshl, 0x0000400, N_INV, 0x0800510), \
14164 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14165 X(vand, 0x0000110, N_INV, 0x0800030), \
14166 X(vbic, 0x0100110, N_INV, 0x0800030), \
14167 X(veor, 0x1000110, N_INV, N_INV), \
14168 X(vorn, 0x0300110, N_INV, 0x0800010), \
14169 X(vorr, 0x0200110, N_INV, 0x0800010), \
14170 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14171 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14172 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14173 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14174 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14175 X(vst1, 0x0000000, 0x0800000, N_INV), \
14176 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14177 X(vst2, 0x0000100, 0x0800100, N_INV), \
14178 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14179 X(vst3, 0x0000200, 0x0800200, N_INV), \
14180 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14181 X(vst4, 0x0000300, 0x0800300, N_INV), \
14182 X(vmovn, 0x1b20200, N_INV, N_INV), \
14183 X(vtrn, 0x1b20080, N_INV, N_INV), \
14184 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14185 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14186 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14187 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14188 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14189 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14190 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14191 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14192 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14193 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14194 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14195 X(vseleq, 0xe000a00, N_INV, N_INV), \
14196 X(vselvs, 0xe100a00, N_INV, N_INV), \
14197 X(vselge, 0xe200a00, N_INV, N_INV), \
14198 X(vselgt, 0xe300a00, N_INV, N_INV), \
14199 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14200 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14201 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14202 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14203 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14204 X(aes, 0x3b00300, N_INV, N_INV), \
14205 X(sha3op, 0x2000c00, N_INV, N_INV), \
14206 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14207 X(sha2op, 0x3ba0380, N_INV, N_INV)
14211 #define X(OPC,I,F,S) N_MNEM_##OPC
14216 static const struct neon_tab_entry neon_enc_tab
[] =
14218 #define X(OPC,I,F,S) { (I), (F), (S) }
14223 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14224 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14225 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14226 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14227 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14228 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14229 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14230 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14231 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14232 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14233 #define NEON_ENC_SINGLE_(X) \
14234 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14235 #define NEON_ENC_DOUBLE_(X) \
14236 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14237 #define NEON_ENC_FPV8_(X) \
14238 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14240 #define NEON_ENCODE(type, inst) \
14243 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14244 inst.is_neon = 1; \
14248 #define check_neon_suffixes \
14251 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14253 as_bad (_("invalid neon suffix for non neon instruction")); \
14259 /* Define shapes for instruction operands. The following mnemonic characters
14260 are used in this table:
14262 F - VFP S<n> register
14263 D - Neon D<n> register
14264 Q - Neon Q<n> register
14268 L - D<n> register list
14270 This table is used to generate various data:
14271 - enumerations of the form NS_DDR to be used as arguments to
14273 - a table classifying shapes into single, double, quad, mixed.
14274 - a table used to drive neon_select_shape. */
14276 #define NEON_SHAPE_DEF \
14277 X(4, (R, R, S, S), QUAD), \
14278 X(4, (S, S, R, R), QUAD), \
14279 X(3, (R, Q, Q), QUAD), \
14280 X(3, (D, D, D), DOUBLE), \
14281 X(3, (Q, Q, Q), QUAD), \
14282 X(3, (D, D, I), DOUBLE), \
14283 X(3, (Q, Q, I), QUAD), \
14284 X(3, (D, D, S), DOUBLE), \
14285 X(3, (Q, Q, S), QUAD), \
14286 X(3, (Q, Q, R), QUAD), \
14287 X(2, (D, D), DOUBLE), \
14288 X(2, (Q, Q), QUAD), \
14289 X(2, (D, S), DOUBLE), \
14290 X(2, (Q, S), QUAD), \
14291 X(2, (D, R), DOUBLE), \
14292 X(2, (Q, R), QUAD), \
14293 X(2, (D, I), DOUBLE), \
14294 X(2, (Q, I), QUAD), \
14295 X(3, (D, L, D), DOUBLE), \
14296 X(2, (D, Q), MIXED), \
14297 X(2, (Q, D), MIXED), \
14298 X(3, (D, Q, I), MIXED), \
14299 X(3, (Q, D, I), MIXED), \
14300 X(3, (Q, D, D), MIXED), \
14301 X(3, (D, Q, Q), MIXED), \
14302 X(3, (Q, Q, D), MIXED), \
14303 X(3, (Q, D, S), MIXED), \
14304 X(3, (D, Q, S), MIXED), \
14305 X(4, (D, D, D, I), DOUBLE), \
14306 X(4, (Q, Q, Q, I), QUAD), \
14307 X(4, (D, D, S, I), DOUBLE), \
14308 X(4, (Q, Q, S, I), QUAD), \
14309 X(2, (F, F), SINGLE), \
14310 X(3, (F, F, F), SINGLE), \
14311 X(2, (F, I), SINGLE), \
14312 X(2, (F, D), MIXED), \
14313 X(2, (D, F), MIXED), \
14314 X(3, (F, F, I), MIXED), \
14315 X(4, (R, R, F, F), SINGLE), \
14316 X(4, (F, F, R, R), SINGLE), \
14317 X(3, (D, R, R), DOUBLE), \
14318 X(3, (R, R, D), DOUBLE), \
14319 X(2, (S, R), SINGLE), \
14320 X(2, (R, S), SINGLE), \
14321 X(2, (F, R), SINGLE), \
14322 X(2, (R, F), SINGLE), \
14323 /* Half float shape supported so far. */\
14324 X (2, (H, D), MIXED), \
14325 X (2, (D, H), MIXED), \
14326 X (2, (H, F), MIXED), \
14327 X (2, (F, H), MIXED), \
14328 X (2, (H, H), HALF), \
14329 X (2, (H, R), HALF), \
14330 X (2, (R, H), HALF), \
14331 X (2, (H, I), HALF), \
14332 X (3, (H, H, H), HALF), \
14333 X (3, (H, F, I), MIXED), \
14334 X (3, (F, H, I), MIXED), \
14335 X (3, (D, H, H), MIXED), \
14336 X (3, (D, H, S), MIXED)
14338 #define S2(A,B) NS_##A##B
14339 #define S3(A,B,C) NS_##A##B##C
14340 #define S4(A,B,C,D) NS_##A##B##C##D
14342 #define X(N, L, C) S##N L
14355 enum neon_shape_class
14364 #define X(N, L, C) SC_##C
14366 static enum neon_shape_class neon_shape_class
[] =
14385 /* Register widths of above. */
14386 static unsigned neon_shape_el_size
[] =
14398 struct neon_shape_info
14401 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14404 #define S2(A,B) { SE_##A, SE_##B }
14405 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14406 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14408 #define X(N, L, C) { N, S##N L }
14410 static struct neon_shape_info neon_shape_tab
[] =
14420 /* Bit masks used in type checking given instructions.
14421 'N_EQK' means the type must be the same as (or based on in some way) the key
14422 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14423 set, various other bits can be set as well in order to modify the meaning of
14424 the type constraint. */
14426 enum neon_type_mask
14450 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14451 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14452 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14453 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14454 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14455 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14456 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14457 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14458 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14459 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14460 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14462 N_MAX_NONSPECIAL
= N_P64
14465 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14467 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14468 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14469 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14470 #define N_S_32 (N_S8 | N_S16 | N_S32)
14471 #define N_F_16_32 (N_F16 | N_F32)
14472 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14473 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14474 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14475 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14476 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14477 #define N_F_MVE (N_F16 | N_F32)
14478 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14480 /* Pass this as the first type argument to neon_check_type to ignore types
14482 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14484 /* Select a "shape" for the current instruction (describing register types or
14485 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14486 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14487 function of operand parsing, so this function doesn't need to be called.
14488 Shapes should be listed in order of decreasing length. */
14490 static enum neon_shape
14491 neon_select_shape (enum neon_shape shape
, ...)
14494 enum neon_shape first_shape
= shape
;
14496 /* Fix missing optional operands. FIXME: we don't know at this point how
14497 many arguments we should have, so this makes the assumption that we have
14498 > 1. This is true of all current Neon opcodes, I think, but may not be
14499 true in the future. */
14500 if (!inst
.operands
[1].present
)
14501 inst
.operands
[1] = inst
.operands
[0];
14503 va_start (ap
, shape
);
14505 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14510 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14512 if (!inst
.operands
[j
].present
)
14518 switch (neon_shape_tab
[shape
].el
[j
])
14520 /* If a .f16, .16, .u16, .s16 type specifier is given over
14521 a VFP single precision register operand, it's essentially
14522 means only half of the register is used.
14524 If the type specifier is given after the mnemonics, the
14525 information is stored in inst.vectype. If the type specifier
14526 is given after register operand, the information is stored
14527 in inst.operands[].vectype.
14529 When there is only one type specifier, and all the register
14530 operands are the same type of hardware register, the type
14531 specifier applies to all register operands.
14533 If no type specifier is given, the shape is inferred from
14534 operand information.
14537 vadd.f16 s0, s1, s2: NS_HHH
14538 vabs.f16 s0, s1: NS_HH
14539 vmov.f16 s0, r1: NS_HR
14540 vmov.f16 r0, s1: NS_RH
14541 vcvt.f16 r0, s1: NS_RH
14542 vcvt.f16.s32 s2, s2, #29: NS_HFI
14543 vcvt.f16.s32 s2, s2: NS_HF
14546 if (!(inst
.operands
[j
].isreg
14547 && inst
.operands
[j
].isvec
14548 && inst
.operands
[j
].issingle
14549 && !inst
.operands
[j
].isquad
14550 && ((inst
.vectype
.elems
== 1
14551 && inst
.vectype
.el
[0].size
== 16)
14552 || (inst
.vectype
.elems
> 1
14553 && inst
.vectype
.el
[j
].size
== 16)
14554 || (inst
.vectype
.elems
== 0
14555 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14556 && inst
.operands
[j
].vectype
.size
== 16))))
14561 if (!(inst
.operands
[j
].isreg
14562 && inst
.operands
[j
].isvec
14563 && inst
.operands
[j
].issingle
14564 && !inst
.operands
[j
].isquad
14565 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14566 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14567 || (inst
.vectype
.elems
== 0
14568 && (inst
.operands
[j
].vectype
.size
== 32
14569 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14574 if (!(inst
.operands
[j
].isreg
14575 && inst
.operands
[j
].isvec
14576 && !inst
.operands
[j
].isquad
14577 && !inst
.operands
[j
].issingle
))
14582 if (!(inst
.operands
[j
].isreg
14583 && !inst
.operands
[j
].isvec
))
14588 if (!(inst
.operands
[j
].isreg
14589 && inst
.operands
[j
].isvec
14590 && inst
.operands
[j
].isquad
14591 && !inst
.operands
[j
].issingle
))
14596 if (!(!inst
.operands
[j
].isreg
14597 && !inst
.operands
[j
].isscalar
))
14602 if (!(!inst
.operands
[j
].isreg
14603 && inst
.operands
[j
].isscalar
))
14613 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14614 /* We've matched all the entries in the shape table, and we don't
14615 have any left over operands which have not been matched. */
14621 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14622 first_error (_("invalid instruction shape"));
14627 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14628 means the Q bit should be set). */
14631 neon_quad (enum neon_shape shape
)
14633 return neon_shape_class
[shape
] == SC_QUAD
;
14637 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14640 /* Allow modification to be made to types which are constrained to be
14641 based on the key element, based on bits set alongside N_EQK. */
14642 if ((typebits
& N_EQK
) != 0)
14644 if ((typebits
& N_HLF
) != 0)
14646 else if ((typebits
& N_DBL
) != 0)
14648 if ((typebits
& N_SGN
) != 0)
14649 *g_type
= NT_signed
;
14650 else if ((typebits
& N_UNS
) != 0)
14651 *g_type
= NT_unsigned
;
14652 else if ((typebits
& N_INT
) != 0)
14653 *g_type
= NT_integer
;
14654 else if ((typebits
& N_FLT
) != 0)
14655 *g_type
= NT_float
;
14656 else if ((typebits
& N_SIZ
) != 0)
14657 *g_type
= NT_untyped
;
14661 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14662 operand type, i.e. the single type specified in a Neon instruction when it
14663 is the only one given. */
14665 static struct neon_type_el
14666 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14668 struct neon_type_el dest
= *key
;
14670 gas_assert ((thisarg
& N_EQK
) != 0);
14672 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14677 /* Convert Neon type and size into compact bitmask representation. */
14679 static enum neon_type_mask
14680 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14687 case 8: return N_8
;
14688 case 16: return N_16
;
14689 case 32: return N_32
;
14690 case 64: return N_64
;
14698 case 8: return N_I8
;
14699 case 16: return N_I16
;
14700 case 32: return N_I32
;
14701 case 64: return N_I64
;
14709 case 16: return N_F16
;
14710 case 32: return N_F32
;
14711 case 64: return N_F64
;
14719 case 8: return N_P8
;
14720 case 16: return N_P16
;
14721 case 64: return N_P64
;
14729 case 8: return N_S8
;
14730 case 16: return N_S16
;
14731 case 32: return N_S32
;
14732 case 64: return N_S64
;
14740 case 8: return N_U8
;
14741 case 16: return N_U16
;
14742 case 32: return N_U32
;
14743 case 64: return N_U64
;
14754 /* Convert compact Neon bitmask type representation to a type and size. Only
14755 handles the case where a single bit is set in the mask. */
14758 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14759 enum neon_type_mask mask
)
14761 if ((mask
& N_EQK
) != 0)
14764 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14766 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14768 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14770 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14775 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14777 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14778 *type
= NT_unsigned
;
14779 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14780 *type
= NT_integer
;
14781 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14782 *type
= NT_untyped
;
14783 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14785 else if ((mask
& (N_F_ALL
)) != 0)
14793 /* Modify a bitmask of allowed types. This is only needed for type
14797 modify_types_allowed (unsigned allowed
, unsigned mods
)
14800 enum neon_el_type type
;
14806 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14808 if (el_type_of_type_chk (&type
, &size
,
14809 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14811 neon_modify_type_size (mods
, &type
, &size
);
14812 destmask
|= type_chk_of_el_type (type
, size
);
14819 /* Check type and return type classification.
14820 The manual states (paraphrase): If one datatype is given, it indicates the
14822 - the second operand, if there is one
14823 - the operand, if there is no second operand
14824 - the result, if there are no operands.
14825 This isn't quite good enough though, so we use a concept of a "key" datatype
14826 which is set on a per-instruction basis, which is the one which matters when
14827 only one data type is written.
14828 Note: this function has side-effects (e.g. filling in missing operands). All
14829 Neon instructions should call it before performing bit encoding. */
14831 static struct neon_type_el
14832 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14835 unsigned i
, pass
, key_el
= 0;
14836 unsigned types
[NEON_MAX_TYPE_ELS
];
14837 enum neon_el_type k_type
= NT_invtype
;
14838 unsigned k_size
= -1u;
14839 struct neon_type_el badtype
= {NT_invtype
, -1};
14840 unsigned key_allowed
= 0;
14842 /* Optional registers in Neon instructions are always (not) in operand 1.
14843 Fill in the missing operand here, if it was omitted. */
14844 if (els
> 1 && !inst
.operands
[1].present
)
14845 inst
.operands
[1] = inst
.operands
[0];
14847 /* Suck up all the varargs. */
14849 for (i
= 0; i
< els
; i
++)
14851 unsigned thisarg
= va_arg (ap
, unsigned);
14852 if (thisarg
== N_IGNORE_TYPE
)
14857 types
[i
] = thisarg
;
14858 if ((thisarg
& N_KEY
) != 0)
14863 if (inst
.vectype
.elems
> 0)
14864 for (i
= 0; i
< els
; i
++)
14865 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14867 first_error (_("types specified in both the mnemonic and operands"));
14871 /* Duplicate inst.vectype elements here as necessary.
14872 FIXME: No idea if this is exactly the same as the ARM assembler,
14873 particularly when an insn takes one register and one non-register
14875 if (inst
.vectype
.elems
== 1 && els
> 1)
14878 inst
.vectype
.elems
= els
;
14879 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14880 for (j
= 0; j
< els
; j
++)
14882 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14885 else if (inst
.vectype
.elems
== 0 && els
> 0)
14888 /* No types were given after the mnemonic, so look for types specified
14889 after each operand. We allow some flexibility here; as long as the
14890 "key" operand has a type, we can infer the others. */
14891 for (j
= 0; j
< els
; j
++)
14892 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14893 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14895 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14897 for (j
= 0; j
< els
; j
++)
14898 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14899 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14904 first_error (_("operand types can't be inferred"));
14908 else if (inst
.vectype
.elems
!= els
)
14910 first_error (_("type specifier has the wrong number of parts"));
14914 for (pass
= 0; pass
< 2; pass
++)
14916 for (i
= 0; i
< els
; i
++)
14918 unsigned thisarg
= types
[i
];
14919 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14920 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14921 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14922 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14924 /* Decay more-specific signed & unsigned types to sign-insensitive
14925 integer types if sign-specific variants are unavailable. */
14926 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14927 && (types_allowed
& N_SU_ALL
) == 0)
14928 g_type
= NT_integer
;
14930 /* If only untyped args are allowed, decay any more specific types to
14931 them. Some instructions only care about signs for some element
14932 sizes, so handle that properly. */
14933 if (((types_allowed
& N_UNT
) == 0)
14934 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14935 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14936 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14937 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14938 g_type
= NT_untyped
;
14942 if ((thisarg
& N_KEY
) != 0)
14946 key_allowed
= thisarg
& ~N_KEY
;
14948 /* Check architecture constraint on FP16 extension. */
14950 && k_type
== NT_float
14951 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14953 inst
.error
= _(BAD_FP16
);
14960 if ((thisarg
& N_VFP
) != 0)
14962 enum neon_shape_el regshape
;
14963 unsigned regwidth
, match
;
14965 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14968 first_error (_("invalid instruction shape"));
14971 regshape
= neon_shape_tab
[ns
].el
[i
];
14972 regwidth
= neon_shape_el_size
[regshape
];
14974 /* In VFP mode, operands must match register widths. If we
14975 have a key operand, use its width, else use the width of
14976 the current operand. */
14982 /* FP16 will use a single precision register. */
14983 if (regwidth
== 32 && match
== 16)
14985 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14989 inst
.error
= _(BAD_FP16
);
14994 if (regwidth
!= match
)
14996 first_error (_("operand size must match register width"));
15001 if ((thisarg
& N_EQK
) == 0)
15003 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15005 if ((given_type
& types_allowed
) == 0)
15007 first_error (BAD_SIMD_TYPE
);
15013 enum neon_el_type mod_k_type
= k_type
;
15014 unsigned mod_k_size
= k_size
;
15015 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15016 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15018 first_error (_("inconsistent types in Neon instruction"));
15026 return inst
.vectype
.el
[key_el
];
15029 /* Neon-style VFP instruction forwarding. */
15031 /* Thumb VFP instructions have 0xE in the condition field. */
15034 do_vfp_cond_or_thumb (void)
15039 inst
.instruction
|= 0xe0000000;
15041 inst
.instruction
|= inst
.cond
<< 28;
15044 /* Look up and encode a simple mnemonic, for use as a helper function for the
15045 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15046 etc. It is assumed that operand parsing has already been done, and that the
15047 operands are in the form expected by the given opcode (this isn't necessarily
15048 the same as the form in which they were parsed, hence some massaging must
15049 take place before this function is called).
15050 Checks current arch version against that in the looked-up opcode. */
15053 do_vfp_nsyn_opcode (const char *opname
)
15055 const struct asm_opcode
*opcode
;
15057 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15062 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15063 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15070 inst
.instruction
= opcode
->tvalue
;
15071 opcode
->tencode ();
15075 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15076 opcode
->aencode ();
15081 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15083 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15085 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15088 do_vfp_nsyn_opcode ("fadds");
15090 do_vfp_nsyn_opcode ("fsubs");
15092 /* ARMv8.2 fp16 instruction. */
15094 do_scalar_fp16_v82_encode ();
15099 do_vfp_nsyn_opcode ("faddd");
15101 do_vfp_nsyn_opcode ("fsubd");
15105 /* Check operand types to see if this is a VFP instruction, and if so call
15109 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15111 enum neon_shape rs
;
15112 struct neon_type_el et
;
15117 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15118 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15122 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15123 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15124 N_F_ALL
| N_KEY
| N_VFP
);
15131 if (et
.type
!= NT_invtype
)
15142 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15144 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15146 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15149 do_vfp_nsyn_opcode ("fmacs");
15151 do_vfp_nsyn_opcode ("fnmacs");
15153 /* ARMv8.2 fp16 instruction. */
15155 do_scalar_fp16_v82_encode ();
15160 do_vfp_nsyn_opcode ("fmacd");
15162 do_vfp_nsyn_opcode ("fnmacd");
15167 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15169 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15171 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15174 do_vfp_nsyn_opcode ("ffmas");
15176 do_vfp_nsyn_opcode ("ffnmas");
15178 /* ARMv8.2 fp16 instruction. */
15180 do_scalar_fp16_v82_encode ();
15185 do_vfp_nsyn_opcode ("ffmad");
15187 do_vfp_nsyn_opcode ("ffnmad");
15192 do_vfp_nsyn_mul (enum neon_shape rs
)
15194 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15196 do_vfp_nsyn_opcode ("fmuls");
15198 /* ARMv8.2 fp16 instruction. */
15200 do_scalar_fp16_v82_encode ();
15203 do_vfp_nsyn_opcode ("fmuld");
15207 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15209 int is_neg
= (inst
.instruction
& 0x80) != 0;
15210 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15212 if (rs
== NS_FF
|| rs
== NS_HH
)
15215 do_vfp_nsyn_opcode ("fnegs");
15217 do_vfp_nsyn_opcode ("fabss");
15219 /* ARMv8.2 fp16 instruction. */
15221 do_scalar_fp16_v82_encode ();
15226 do_vfp_nsyn_opcode ("fnegd");
15228 do_vfp_nsyn_opcode ("fabsd");
15232 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15233 insns belong to Neon, and are handled elsewhere. */
15236 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15238 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15242 do_vfp_nsyn_opcode ("fldmdbs");
15244 do_vfp_nsyn_opcode ("fldmias");
15249 do_vfp_nsyn_opcode ("fstmdbs");
15251 do_vfp_nsyn_opcode ("fstmias");
15256 do_vfp_nsyn_sqrt (void)
15258 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15259 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15261 if (rs
== NS_FF
|| rs
== NS_HH
)
15263 do_vfp_nsyn_opcode ("fsqrts");
15265 /* ARMv8.2 fp16 instruction. */
15267 do_scalar_fp16_v82_encode ();
15270 do_vfp_nsyn_opcode ("fsqrtd");
15274 do_vfp_nsyn_div (void)
15276 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15277 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15278 N_F_ALL
| N_KEY
| N_VFP
);
15280 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15282 do_vfp_nsyn_opcode ("fdivs");
15284 /* ARMv8.2 fp16 instruction. */
15286 do_scalar_fp16_v82_encode ();
15289 do_vfp_nsyn_opcode ("fdivd");
15293 do_vfp_nsyn_nmul (void)
15295 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15296 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15297 N_F_ALL
| N_KEY
| N_VFP
);
15299 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15301 NEON_ENCODE (SINGLE
, inst
);
15302 do_vfp_sp_dyadic ();
15304 /* ARMv8.2 fp16 instruction. */
15306 do_scalar_fp16_v82_encode ();
15310 NEON_ENCODE (DOUBLE
, inst
);
15311 do_vfp_dp_rd_rn_rm ();
15313 do_vfp_cond_or_thumb ();
15318 do_vfp_nsyn_cmp (void)
15320 enum neon_shape rs
;
15321 if (inst
.operands
[1].isreg
)
15323 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15324 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15326 if (rs
== NS_FF
|| rs
== NS_HH
)
15328 NEON_ENCODE (SINGLE
, inst
);
15329 do_vfp_sp_monadic ();
15333 NEON_ENCODE (DOUBLE
, inst
);
15334 do_vfp_dp_rd_rm ();
15339 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
15340 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
15342 switch (inst
.instruction
& 0x0fffffff)
15345 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
15348 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
15354 if (rs
== NS_FI
|| rs
== NS_HI
)
15356 NEON_ENCODE (SINGLE
, inst
);
15357 do_vfp_sp_compare_z ();
15361 NEON_ENCODE (DOUBLE
, inst
);
15365 do_vfp_cond_or_thumb ();
15367 /* ARMv8.2 fp16 instruction. */
15368 if (rs
== NS_HI
|| rs
== NS_HH
)
15369 do_scalar_fp16_v82_encode ();
15373 nsyn_insert_sp (void)
15375 inst
.operands
[1] = inst
.operands
[0];
15376 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
15377 inst
.operands
[0].reg
= REG_SP
;
15378 inst
.operands
[0].isreg
= 1;
15379 inst
.operands
[0].writeback
= 1;
15380 inst
.operands
[0].present
= 1;
15384 do_vfp_nsyn_push (void)
15388 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15389 _("register list must contain at least 1 and at most 16 "
15392 if (inst
.operands
[1].issingle
)
15393 do_vfp_nsyn_opcode ("fstmdbs");
15395 do_vfp_nsyn_opcode ("fstmdbd");
15399 do_vfp_nsyn_pop (void)
15403 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15404 _("register list must contain at least 1 and at most 16 "
15407 if (inst
.operands
[1].issingle
)
15408 do_vfp_nsyn_opcode ("fldmias");
15410 do_vfp_nsyn_opcode ("fldmiad");
15413 /* Fix up Neon data-processing instructions, ORing in the correct bits for
15414 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
15417 neon_dp_fixup (struct arm_it
* insn
)
15419 unsigned int i
= insn
->instruction
;
15424 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
15435 insn
->instruction
= i
;
15438 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15442 neon_logbits (unsigned x
)
15444 return ffs (x
) - 4;
15447 #define LOW4(R) ((R) & 0xf)
15448 #define HI1(R) (((R) >> 4) & 1)
15451 mve_encode_qqr (int size
, int fp
)
15453 if (inst
.operands
[2].reg
== REG_SP
)
15454 as_tsktsk (MVE_BAD_SP
);
15455 else if (inst
.operands
[2].reg
== REG_PC
)
15456 as_tsktsk (MVE_BAD_PC
);
15461 if (((unsigned)inst
.instruction
) == 0xd00)
15462 inst
.instruction
= 0xee300f40;
15464 else if (((unsigned)inst
.instruction
) == 0x200d00)
15465 inst
.instruction
= 0xee301f40;
15467 /* Setting size which is 1 for F16 and 0 for F32. */
15468 inst
.instruction
|= (size
== 16) << 28;
15473 if (((unsigned)inst
.instruction
) == 0x800)
15474 inst
.instruction
= 0xee010f40;
15476 else if (((unsigned)inst
.instruction
) == 0x1000800)
15477 inst
.instruction
= 0xee011f40;
15478 /* Setting bits for size. */
15479 inst
.instruction
|= neon_logbits (size
) << 20;
15481 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15482 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15483 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15484 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15485 inst
.instruction
|= inst
.operands
[2].reg
;
15490 mve_encode_rqq (unsigned bit28
, unsigned size
)
15492 inst
.instruction
|= bit28
<< 28;
15493 inst
.instruction
|= neon_logbits (size
) << 20;
15494 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15495 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15496 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15497 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15498 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15503 mve_encode_qqq (int ubit
, int size
)
15506 inst
.instruction
|= (ubit
!= 0) << 28;
15507 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15508 inst
.instruction
|= neon_logbits (size
) << 20;
15509 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15510 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15511 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15512 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15513 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15519 /* Encode insns with bit pattern:
15521 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15522 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
15524 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
15525 different meaning for some instruction. */
15528 neon_three_same (int isquad
, int ubit
, int size
)
15530 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15531 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15532 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15533 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15534 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15535 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15536 inst
.instruction
|= (isquad
!= 0) << 6;
15537 inst
.instruction
|= (ubit
!= 0) << 24;
15539 inst
.instruction
|= neon_logbits (size
) << 20;
15541 neon_dp_fixup (&inst
);
15544 /* Encode instructions of the form:
15546 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
15547 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
15549 Don't write size if SIZE == -1. */
15552 neon_two_same (int qbit
, int ubit
, int size
)
15554 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15555 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15556 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15557 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15558 inst
.instruction
|= (qbit
!= 0) << 6;
15559 inst
.instruction
|= (ubit
!= 0) << 24;
15562 inst
.instruction
|= neon_logbits (size
) << 18;
15564 neon_dp_fixup (&inst
);
15567 /* Neon instruction encoders, in approximate order of appearance. */
15570 do_neon_dyadic_i_su (void)
15572 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15573 struct neon_type_el et
= neon_check_type (3, rs
,
15574 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
15575 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15579 do_neon_dyadic_i64_su (void)
15581 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15582 struct neon_type_el et
= neon_check_type (3, rs
,
15583 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
15584 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15588 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
15591 unsigned size
= et
.size
>> 3;
15592 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15593 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15594 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15595 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15596 inst
.instruction
|= (isquad
!= 0) << 6;
15597 inst
.instruction
|= immbits
<< 16;
15598 inst
.instruction
|= (size
>> 3) << 7;
15599 inst
.instruction
|= (size
& 0x7) << 19;
15601 inst
.instruction
|= (uval
!= 0) << 24;
15603 neon_dp_fixup (&inst
);
15607 do_neon_shl_imm (void)
15609 if (!inst
.operands
[2].isreg
)
15611 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15612 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
15613 int imm
= inst
.operands
[2].imm
;
15615 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15616 _("immediate out of range for shift"));
15617 NEON_ENCODE (IMMED
, inst
);
15618 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15622 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15623 struct neon_type_el et
= neon_check_type (3, rs
,
15624 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
15627 /* VSHL/VQSHL 3-register variants have syntax such as:
15629 whereas other 3-register operations encoded by neon_three_same have
15632 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
15634 tmp
= inst
.operands
[2].reg
;
15635 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15636 inst
.operands
[1].reg
= tmp
;
15637 NEON_ENCODE (INTEGER
, inst
);
15638 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15643 do_neon_qshl_imm (void)
15645 if (!inst
.operands
[2].isreg
)
15647 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15648 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15649 int imm
= inst
.operands
[2].imm
;
15651 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15652 _("immediate out of range for shift"));
15653 NEON_ENCODE (IMMED
, inst
);
15654 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
15658 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15659 struct neon_type_el et
= neon_check_type (3, rs
,
15660 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
15663 /* See note in do_neon_shl_imm. */
15664 tmp
= inst
.operands
[2].reg
;
15665 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15666 inst
.operands
[1].reg
= tmp
;
15667 NEON_ENCODE (INTEGER
, inst
);
15668 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15673 do_neon_rshl (void)
15675 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15676 struct neon_type_el et
= neon_check_type (3, rs
,
15677 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
15680 tmp
= inst
.operands
[2].reg
;
15681 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15682 inst
.operands
[1].reg
= tmp
;
15683 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15687 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
15689 /* Handle .I8 pseudo-instructions. */
15692 /* Unfortunately, this will make everything apart from zero out-of-range.
15693 FIXME is this the intended semantics? There doesn't seem much point in
15694 accepting .I8 if so. */
15695 immediate
|= immediate
<< 8;
15701 if (immediate
== (immediate
& 0x000000ff))
15703 *immbits
= immediate
;
15706 else if (immediate
== (immediate
& 0x0000ff00))
15708 *immbits
= immediate
>> 8;
15711 else if (immediate
== (immediate
& 0x00ff0000))
15713 *immbits
= immediate
>> 16;
15716 else if (immediate
== (immediate
& 0xff000000))
15718 *immbits
= immediate
>> 24;
15721 if ((immediate
& 0xffff) != (immediate
>> 16))
15722 goto bad_immediate
;
15723 immediate
&= 0xffff;
15726 if (immediate
== (immediate
& 0x000000ff))
15728 *immbits
= immediate
;
15731 else if (immediate
== (immediate
& 0x0000ff00))
15733 *immbits
= immediate
>> 8;
15738 first_error (_("immediate value out of range"));
15743 do_neon_logic (void)
15745 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
15747 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15748 neon_check_type (3, rs
, N_IGNORE_TYPE
);
15749 /* U bit and size field were set as part of the bitmask. */
15750 NEON_ENCODE (INTEGER
, inst
);
15751 neon_three_same (neon_quad (rs
), 0, -1);
15755 const int three_ops_form
= (inst
.operands
[2].present
15756 && !inst
.operands
[2].isreg
);
15757 const int immoperand
= (three_ops_form
? 2 : 1);
15758 enum neon_shape rs
= (three_ops_form
15759 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
15760 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
15761 struct neon_type_el et
= neon_check_type (2, rs
,
15762 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15763 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
15767 if (et
.type
== NT_invtype
)
15770 if (three_ops_form
)
15771 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15772 _("first and second operands shall be the same register"));
15774 NEON_ENCODE (IMMED
, inst
);
15776 immbits
= inst
.operands
[immoperand
].imm
;
15779 /* .i64 is a pseudo-op, so the immediate must be a repeating
15781 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
15782 inst
.operands
[immoperand
].reg
: 0))
15784 /* Set immbits to an invalid constant. */
15785 immbits
= 0xdeadbeef;
15792 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15796 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15800 /* Pseudo-instruction for VBIC. */
15801 neon_invert_size (&immbits
, 0, et
.size
);
15802 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15806 /* Pseudo-instruction for VORR. */
15807 neon_invert_size (&immbits
, 0, et
.size
);
15808 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15818 inst
.instruction
|= neon_quad (rs
) << 6;
15819 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15820 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15821 inst
.instruction
|= cmode
<< 8;
15822 neon_write_immbits (immbits
);
15824 neon_dp_fixup (&inst
);
15829 do_neon_bitfield (void)
15831 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15832 neon_check_type (3, rs
, N_IGNORE_TYPE
);
15833 neon_three_same (neon_quad (rs
), 0, -1);
15837 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
15840 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
15841 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
15843 if (et
.type
== NT_float
)
15845 NEON_ENCODE (FLOAT
, inst
);
15847 mve_encode_qqr (et
.size
, 1);
15849 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15853 NEON_ENCODE (INTEGER
, inst
);
15855 mve_encode_qqr (et
.size
, 0);
15857 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
15863 do_neon_dyadic_if_su_d (void)
15865 /* This version only allow D registers, but that constraint is enforced during
15866 operand parsing so we don't need to do anything extra here. */
15867 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
15871 do_neon_dyadic_if_i_d (void)
15873 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15874 affected if we specify unsigned args. */
15875 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15878 enum vfp_or_neon_is_neon_bits
15881 NEON_CHECK_ARCH
= 2,
15882 NEON_CHECK_ARCH8
= 4
15885 /* Call this function if an instruction which may have belonged to the VFP or
15886 Neon instruction sets, but turned out to be a Neon instruction (due to the
15887 operand types involved, etc.). We have to check and/or fix-up a couple of
15890 - Make sure the user hasn't attempted to make a Neon instruction
15892 - Alter the value in the condition code field if necessary.
15893 - Make sure that the arch supports Neon instructions.
15895 Which of these operations take place depends on bits from enum
15896 vfp_or_neon_is_neon_bits.
15898 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
15899 current instruction's condition is COND_ALWAYS, the condition field is
15900 changed to inst.uncond_value. This is necessary because instructions shared
15901 between VFP and Neon may be conditional for the VFP variants only, and the
15902 unconditional Neon version must have, e.g., 0xF in the condition field. */
15905 vfp_or_neon_is_neon (unsigned check
)
15907 /* Conditions are always legal in Thumb mode (IT blocks). */
15908 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
15910 if (inst
.cond
!= COND_ALWAYS
)
15912 first_error (_(BAD_COND
));
15915 if (inst
.uncond_value
!= -1)
15916 inst
.instruction
|= inst
.uncond_value
<< 28;
15920 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
15921 || ((check
& NEON_CHECK_ARCH8
)
15922 && !mark_feature_used (&fpu_neon_ext_armv8
)))
15924 first_error (_(BAD_FPU
));
15932 check_simd_pred_availability (int fp
, unsigned check
)
15934 if (inst
.cond
> COND_ALWAYS
)
15936 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
15938 inst
.error
= BAD_FPU
;
15941 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15943 else if (inst
.cond
< COND_ALWAYS
)
15945 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
15946 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15947 else if (vfp_or_neon_is_neon (check
) == FAIL
)
15952 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
15953 && vfp_or_neon_is_neon (check
) == FAIL
)
15956 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
15957 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15963 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
15965 constraint (size
< 32, BAD_ADDR_MODE
);
15966 constraint (size
!= elsize
, BAD_EL_TYPE
);
15967 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
15968 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
15969 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
15970 _("destination register and offset register may not be the"
15973 int imm
= inst
.relocs
[0].exp
.X_add_number
;
15980 constraint ((imm
% (size
/ 8) != 0)
15981 || imm
> (0x7f << neon_logbits (size
)),
15982 (size
== 32) ? _("immediate must be a multiple of 4 in the"
15983 " range of +/-[0,508]")
15984 : _("immediate must be a multiple of 8 in the"
15985 " range of +/-[0,1016]"));
15986 inst
.instruction
|= 0x11 << 24;
15987 inst
.instruction
|= add
<< 23;
15988 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15989 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
15990 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15991 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15992 inst
.instruction
|= 1 << 12;
15993 inst
.instruction
|= (size
== 64) << 8;
15994 inst
.instruction
&= 0xffffff00;
15995 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15996 inst
.instruction
|= imm
>> neon_logbits (size
);
16000 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
16002 unsigned os
= inst
.operands
[1].imm
>> 5;
16003 constraint (os
!= 0 && size
== 8,
16004 _("can not shift offsets when accessing less than half-word"));
16005 constraint (os
&& os
!= neon_logbits (size
),
16006 _("shift immediate must be 1, 2 or 3 for half-word, word"
16007 " or double-word accesses respectively"));
16008 if (inst
.operands
[1].reg
== REG_PC
)
16009 as_tsktsk (MVE_BAD_PC
);
16014 constraint (elsize
>= 64, BAD_EL_TYPE
);
16017 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16021 constraint (elsize
!= size
, BAD_EL_TYPE
);
16026 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
16030 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
16031 _("destination register and offset register may not be"
16033 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
16035 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
16036 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
16037 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
16041 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
16044 inst
.instruction
|= 1 << 23;
16045 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16046 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16047 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16048 inst
.instruction
|= neon_logbits (elsize
) << 7;
16049 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
16050 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
16051 inst
.instruction
|= !!os
;
16055 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
16057 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
16059 constraint (size
>= 64, BAD_ADDR_MODE
);
16063 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16066 constraint (elsize
!= size
, BAD_EL_TYPE
);
16073 constraint (elsize
!= size
&& type
!= NT_unsigned
16074 && type
!= NT_signed
, BAD_EL_TYPE
);
16078 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
16081 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16089 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
16094 constraint (1, _("immediate must be in the range of +/-[0,127]"));
16097 constraint (1, _("immediate must be a multiple of 2 in the"
16098 " range of +/-[0,254]"));
16101 constraint (1, _("immediate must be a multiple of 4 in the"
16102 " range of +/-[0,508]"));
16107 if (size
!= elsize
)
16109 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
16110 constraint (inst
.operands
[0].reg
> 14,
16111 _("MVE vector register in the range [Q0..Q7] expected"));
16112 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
16113 inst
.instruction
|= (size
== 16) << 19;
16114 inst
.instruction
|= neon_logbits (elsize
) << 7;
16118 if (inst
.operands
[1].reg
== REG_PC
)
16119 as_tsktsk (MVE_BAD_PC
);
16120 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16121 as_tsktsk (MVE_BAD_SP
);
16122 inst
.instruction
|= 1 << 12;
16123 inst
.instruction
|= neon_logbits (size
) << 7;
16125 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
16126 inst
.instruction
|= add
<< 23;
16127 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16128 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16129 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16130 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16131 inst
.instruction
&= 0xffffff80;
16132 inst
.instruction
|= imm
>> neon_logbits (size
);
16137 do_mve_vstr_vldr (void)
16142 if (inst
.cond
> COND_ALWAYS
)
16143 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16145 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16147 switch (inst
.instruction
)
16154 /* fall through. */
16160 /* fall through. */
16166 /* fall through. */
16172 /* fall through. */
16177 unsigned elsize
= inst
.vectype
.el
[0].size
;
16179 if (inst
.operands
[1].isquad
)
16181 /* We are dealing with [Q, imm]{!} cases. */
16182 do_mve_vstr_vldr_QI (size
, elsize
, load
);
16186 if (inst
.operands
[1].immisreg
== 2)
16188 /* We are dealing with [R, Q, {UXTW #os}] cases. */
16189 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
16191 else if (!inst
.operands
[1].immisreg
)
16193 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
16194 do_mve_vstr_vldr_RI (size
, elsize
, load
);
16197 constraint (1, BAD_ADDR_MODE
);
16204 do_mve_vst_vld (void)
16206 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16209 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
16210 || inst
.relocs
[0].exp
.X_add_number
!= 0
16211 || inst
.operands
[1].immisreg
!= 0,
16213 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
16214 if (inst
.operands
[1].reg
== REG_PC
)
16215 as_tsktsk (MVE_BAD_PC
);
16216 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16217 as_tsktsk (MVE_BAD_SP
);
16220 /* These instructions are one of the "exceptions" mentioned in
16221 handle_pred_state. They are MVE instructions that are not VPT compatible
16222 and do not accept a VPT code, thus appending such a code is a syntax
16224 if (inst
.cond
> COND_ALWAYS
)
16225 first_error (BAD_SYNTAX
);
16226 /* If we append a scalar condition code we can set this to
16227 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
16228 else if (inst
.cond
< COND_ALWAYS
)
16229 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16231 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
16233 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16234 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16235 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16236 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16237 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
16242 do_neon_dyadic_if_su (void)
16244 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16245 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16248 if (check_simd_pred_availability (et
.type
== NT_float
,
16249 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16252 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16256 do_neon_addsub_if_i (void)
16258 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
16259 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
16262 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16263 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
16264 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
16266 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
16267 /* If we are parsing Q registers and the element types match MVE, which NEON
16268 also supports, then we must check whether this is an instruction that can
16269 be used by both MVE/NEON. This distinction can be made based on whether
16270 they are predicated or not. */
16271 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
16273 if (check_simd_pred_availability (et
.type
== NT_float
,
16274 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16279 /* If they are either in a D register or are using an unsupported. */
16281 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16285 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16286 affected if we specify unsigned args. */
16287 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
16290 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
16292 V<op> A,B (A is operand 0, B is operand 2)
16297 so handle that case specially. */
16300 neon_exchange_operands (void)
16302 if (inst
.operands
[1].present
)
16304 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
16306 /* Swap operands[1] and operands[2]. */
16307 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
16308 inst
.operands
[1] = inst
.operands
[2];
16309 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
16314 inst
.operands
[1] = inst
.operands
[2];
16315 inst
.operands
[2] = inst
.operands
[0];
16320 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
16322 if (inst
.operands
[2].isreg
)
16325 neon_exchange_operands ();
16326 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
16330 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16331 struct neon_type_el et
= neon_check_type (2, rs
,
16332 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
16334 NEON_ENCODE (IMMED
, inst
);
16335 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16336 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16337 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16338 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16339 inst
.instruction
|= neon_quad (rs
) << 6;
16340 inst
.instruction
|= (et
.type
== NT_float
) << 10;
16341 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16343 neon_dp_fixup (&inst
);
16350 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
16354 do_neon_cmp_inv (void)
16356 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
16362 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
16365 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
16366 scalars, which are encoded in 5 bits, M : Rm.
16367 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
16368 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
16371 Dot Product instructions are similar to multiply instructions except elsize
16372 should always be 32.
16374 This function translates SCALAR, which is GAS's internal encoding of indexed
16375 scalar register, to raw encoding. There is also register and index range
16376 check based on ELSIZE. */
16379 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
16381 unsigned regno
= NEON_SCALAR_REG (scalar
);
16382 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16387 if (regno
> 7 || elno
> 3)
16389 return regno
| (elno
<< 3);
16392 if (regno
> 15 || elno
> 1)
16394 return regno
| (elno
<< 4);
16398 first_error (_("scalar out of range for multiply instruction"));
16404 /* Encode multiply / multiply-accumulate scalar instructions. */
16407 neon_mul_mac (struct neon_type_el et
, int ubit
)
16411 /* Give a more helpful error message if we have an invalid type. */
16412 if (et
.type
== NT_invtype
)
16415 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
16416 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16417 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16418 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16419 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16420 inst
.instruction
|= LOW4 (scalar
);
16421 inst
.instruction
|= HI1 (scalar
) << 5;
16422 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16423 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16424 inst
.instruction
|= (ubit
!= 0) << 24;
16426 neon_dp_fixup (&inst
);
16430 do_neon_mac_maybe_scalar (void)
16432 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
16435 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16438 if (inst
.operands
[2].isscalar
)
16440 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
16441 struct neon_type_el et
= neon_check_type (3, rs
,
16442 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
16443 NEON_ENCODE (SCALAR
, inst
);
16444 neon_mul_mac (et
, neon_quad (rs
));
16448 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16449 affected if we specify unsigned args. */
16450 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16455 do_neon_fmac (void)
16457 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
16460 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16463 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16469 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16470 struct neon_type_el et
= neon_check_type (3, rs
,
16471 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16472 neon_three_same (neon_quad (rs
), 0, et
.size
);
16475 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
16476 same types as the MAC equivalents. The polynomial type for this instruction
16477 is encoded the same as the integer type. */
16482 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
16485 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16488 if (inst
.operands
[2].isscalar
)
16489 do_neon_mac_maybe_scalar ();
16491 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
16495 do_neon_qdmulh (void)
16497 if (inst
.operands
[2].isscalar
)
16499 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
16500 struct neon_type_el et
= neon_check_type (3, rs
,
16501 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16502 NEON_ENCODE (SCALAR
, inst
);
16503 neon_mul_mac (et
, neon_quad (rs
));
16507 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16508 struct neon_type_el et
= neon_check_type (3, rs
,
16509 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16510 NEON_ENCODE (INTEGER
, inst
);
16511 /* The U bit (rounding) comes from bit mask. */
16512 neon_three_same (neon_quad (rs
), 0, et
.size
);
16517 do_mve_vmull (void)
16520 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
16521 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
16522 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
16523 && inst
.cond
== COND_ALWAYS
16524 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
16529 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16530 N_SUF_32
| N_F64
| N_P8
16531 | N_P16
| N_I_MVE
| N_KEY
);
16532 if (((et
.type
== NT_poly
) && et
.size
== 8
16533 && ARM_CPU_IS_ANY (cpu_variant
))
16534 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
16541 constraint (rs
!= NS_QQQ
, BAD_FPU
);
16542 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16543 N_SU_32
| N_P8
| N_P16
| N_KEY
);
16545 /* We are dealing with MVE's vmullt. */
16547 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16548 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16549 as_tsktsk (BAD_MVE_SRCDEST
);
16551 if (inst
.cond
> COND_ALWAYS
)
16552 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16554 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16556 if (et
.type
== NT_poly
)
16557 mve_encode_qqq (neon_logbits (et
.size
), 64);
16559 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
16564 inst
.instruction
= N_MNEM_vmul
;
16567 inst
.pred_insn_type
= INSIDE_IT_INSN
;
16572 do_mve_vabav (void)
16574 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
16579 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16582 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
16583 | N_S16
| N_S32
| N_U8
| N_U16
16586 if (inst
.cond
> COND_ALWAYS
)
16587 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16589 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16591 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
16595 do_mve_vmladav (void)
16597 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
16598 struct neon_type_el et
= neon_check_type (3, rs
,
16599 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16601 if (et
.type
== NT_unsigned
16602 && (inst
.instruction
== M_MNEM_vmladavx
16603 || inst
.instruction
== M_MNEM_vmladavax
16604 || inst
.instruction
== M_MNEM_vmlsdav
16605 || inst
.instruction
== M_MNEM_vmlsdava
16606 || inst
.instruction
== M_MNEM_vmlsdavx
16607 || inst
.instruction
== M_MNEM_vmlsdavax
))
16608 first_error (BAD_SIMD_TYPE
);
16610 constraint (inst
.operands
[2].reg
> 14,
16611 _("MVE vector register in the range [Q0..Q7] expected"));
16613 if (inst
.cond
> COND_ALWAYS
)
16614 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16616 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16618 if (inst
.instruction
== M_MNEM_vmlsdav
16619 || inst
.instruction
== M_MNEM_vmlsdava
16620 || inst
.instruction
== M_MNEM_vmlsdavx
16621 || inst
.instruction
== M_MNEM_vmlsdavax
)
16622 inst
.instruction
|= (et
.size
== 8) << 28;
16624 inst
.instruction
|= (et
.size
== 8) << 8;
16626 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
16627 inst
.instruction
|= (et
.size
== 32) << 16;
16631 do_neon_qrdmlah (void)
16633 /* Check we're on the correct architecture. */
16634 if (!mark_feature_used (&fpu_neon_ext_armv8
))
16636 _("instruction form not available on this architecture.");
16637 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
16639 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
16640 record_feature_use (&fpu_neon_ext_v8_1
);
16643 if (inst
.operands
[2].isscalar
)
16645 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
16646 struct neon_type_el et
= neon_check_type (3, rs
,
16647 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16648 NEON_ENCODE (SCALAR
, inst
);
16649 neon_mul_mac (et
, neon_quad (rs
));
16653 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16654 struct neon_type_el et
= neon_check_type (3, rs
,
16655 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16656 NEON_ENCODE (INTEGER
, inst
);
16657 /* The U bit (rounding) comes from bit mask. */
16658 neon_three_same (neon_quad (rs
), 0, et
.size
);
16663 do_neon_fcmp_absolute (void)
16665 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16666 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16667 N_F_16_32
| N_KEY
);
16668 /* Size field comes from bit mask. */
16669 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
16673 do_neon_fcmp_absolute_inv (void)
16675 neon_exchange_operands ();
16676 do_neon_fcmp_absolute ();
16680 do_neon_step (void)
16682 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16683 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16684 N_F_16_32
| N_KEY
);
16685 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
16689 do_neon_abs_neg (void)
16691 enum neon_shape rs
;
16692 struct neon_type_el et
;
16694 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
16697 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16698 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
16700 if (check_simd_pred_availability (et
.type
== NT_float
,
16701 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16704 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16705 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16706 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16707 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16708 inst
.instruction
|= neon_quad (rs
) << 6;
16709 inst
.instruction
|= (et
.type
== NT_float
) << 10;
16710 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16712 neon_dp_fixup (&inst
);
16718 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16719 struct neon_type_el et
= neon_check_type (2, rs
,
16720 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16721 int imm
= inst
.operands
[2].imm
;
16722 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16723 _("immediate out of range for insert"));
16724 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16730 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16731 struct neon_type_el et
= neon_check_type (2, rs
,
16732 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16733 int imm
= inst
.operands
[2].imm
;
16734 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16735 _("immediate out of range for insert"));
16736 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
16740 do_neon_qshlu_imm (void)
16742 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16743 struct neon_type_el et
= neon_check_type (2, rs
,
16744 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
16745 int imm
= inst
.operands
[2].imm
;
16746 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16747 _("immediate out of range for shift"));
16748 /* Only encodes the 'U present' variant of the instruction.
16749 In this case, signed types have OP (bit 8) set to 0.
16750 Unsigned types have OP set to 1. */
16751 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
16752 /* The rest of the bits are the same as other immediate shifts. */
16753 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16757 do_neon_qmovn (void)
16759 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
16760 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
16761 /* Saturating move where operands can be signed or unsigned, and the
16762 destination has the same signedness. */
16763 NEON_ENCODE (INTEGER
, inst
);
16764 if (et
.type
== NT_unsigned
)
16765 inst
.instruction
|= 0xc0;
16767 inst
.instruction
|= 0x80;
16768 neon_two_same (0, 1, et
.size
/ 2);
16772 do_neon_qmovun (void)
16774 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
16775 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
16776 /* Saturating move with unsigned results. Operands must be signed. */
16777 NEON_ENCODE (INTEGER
, inst
);
16778 neon_two_same (0, 1, et
.size
/ 2);
16782 do_neon_rshift_sat_narrow (void)
16784 /* FIXME: Types for narrowing. If operands are signed, results can be signed
16785 or unsigned. If operands are unsigned, results must also be unsigned. */
16786 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
16787 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
16788 int imm
= inst
.operands
[2].imm
;
16789 /* This gets the bounds check, size encoding and immediate bits calculation
16793 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
16794 VQMOVN.I<size> <Dd>, <Qm>. */
16797 inst
.operands
[2].present
= 0;
16798 inst
.instruction
= N_MNEM_vqmovn
;
16803 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16804 _("immediate out of range"));
16805 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
16809 do_neon_rshift_sat_narrow_u (void)
16811 /* FIXME: Types for narrowing. If operands are signed, results can be signed
16812 or unsigned. If operands are unsigned, results must also be unsigned. */
16813 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
16814 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
16815 int imm
= inst
.operands
[2].imm
;
16816 /* This gets the bounds check, size encoding and immediate bits calculation
16820 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
16821 VQMOVUN.I<size> <Dd>, <Qm>. */
16824 inst
.operands
[2].present
= 0;
16825 inst
.instruction
= N_MNEM_vqmovun
;
16830 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16831 _("immediate out of range"));
16832 /* FIXME: The manual is kind of unclear about what value U should have in
16833 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
16835 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
16839 do_neon_movn (void)
16841 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
16842 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
16843 NEON_ENCODE (INTEGER
, inst
);
16844 neon_two_same (0, 1, et
.size
/ 2);
16848 do_neon_rshift_narrow (void)
16850 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
16851 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
16852 int imm
= inst
.operands
[2].imm
;
16853 /* This gets the bounds check, size encoding and immediate bits calculation
16857 /* If immediate is zero then we are a pseudo-instruction for
16858 VMOVN.I<size> <Dd>, <Qm> */
16861 inst
.operands
[2].present
= 0;
16862 inst
.instruction
= N_MNEM_vmovn
;
16867 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16868 _("immediate out of range for narrowing operation"));
16869 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
16873 do_neon_shll (void)
16875 /* FIXME: Type checking when lengthening. */
16876 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
16877 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
16878 unsigned imm
= inst
.operands
[2].imm
;
16880 if (imm
== et
.size
)
16882 /* Maximum shift variant. */
16883 NEON_ENCODE (INTEGER
, inst
);
16884 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16885 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16886 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16887 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16888 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16890 neon_dp_fixup (&inst
);
16894 /* A more-specific type check for non-max versions. */
16895 et
= neon_check_type (2, NS_QDI
,
16896 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16897 NEON_ENCODE (IMMED
, inst
);
16898 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
16902 /* Check the various types for the VCVT instruction, and return which version
16903 the current instruction is. */
16905 #define CVT_FLAVOUR_VAR \
16906 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
16907 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
16908 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
16909 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
16910 /* Half-precision conversions. */ \
16911 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
16912 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
16913 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
16914 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
16915 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
16916 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
16917 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
16918 Compared with single/double precision variants, only the co-processor \
16919 field is different, so the encoding flow is reused here. */ \
16920 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
16921 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
16922 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
16923 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
16924 /* VFP instructions. */ \
16925 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
16926 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
16927 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
16928 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
16929 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
16930 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
16931 /* VFP instructions with bitshift. */ \
16932 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
16933 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
16934 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
16935 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
16936 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
16937 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
16938 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
16939 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
16941 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
16942 neon_cvt_flavour_##C,
16944 /* The different types of conversions we can do. */
16945 enum neon_cvt_flavour
16948 neon_cvt_flavour_invalid
,
16949 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
16954 static enum neon_cvt_flavour
16955 get_neon_cvt_flavour (enum neon_shape rs
)
16957 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
16958 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
16959 if (et.type != NT_invtype) \
16961 inst.error = NULL; \
16962 return (neon_cvt_flavour_##C); \
16965 struct neon_type_el et
;
16966 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
16967 || rs
== NS_FF
) ? N_VFP
: 0;
16968 /* The instruction versions which take an immediate take one register
16969 argument, which is extended to the width of the full register. Thus the
16970 "source" and "destination" registers must have the same width. Hack that
16971 here by making the size equal to the key (wider, in this case) operand. */
16972 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
16976 return neon_cvt_flavour_invalid
;
16991 /* Neon-syntax VFP conversions. */
16994 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
16996 const char *opname
= 0;
16998 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
16999 || rs
== NS_FHI
|| rs
== NS_HFI
)
17001 /* Conversions with immediate bitshift. */
17002 const char *enc
[] =
17004 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
17010 if (flavour
< (int) ARRAY_SIZE (enc
))
17012 opname
= enc
[flavour
];
17013 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17014 _("operands 0 and 1 must be the same register"));
17015 inst
.operands
[1] = inst
.operands
[2];
17016 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
17021 /* Conversions without bitshift. */
17022 const char *enc
[] =
17024 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
17030 if (flavour
< (int) ARRAY_SIZE (enc
))
17031 opname
= enc
[flavour
];
17035 do_vfp_nsyn_opcode (opname
);
17037 /* ARMv8.2 fp16 VCVT instruction. */
17038 if (flavour
== neon_cvt_flavour_s32_f16
17039 || flavour
== neon_cvt_flavour_u32_f16
17040 || flavour
== neon_cvt_flavour_f16_u32
17041 || flavour
== neon_cvt_flavour_f16_s32
)
17042 do_scalar_fp16_v82_encode ();
17046 do_vfp_nsyn_cvtz (void)
17048 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
17049 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17050 const char *enc
[] =
17052 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
17058 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
17059 do_vfp_nsyn_opcode (enc
[flavour
]);
17063 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
17064 enum neon_cvt_mode mode
)
17069 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17070 D register operands. */
17071 if (flavour
== neon_cvt_flavour_s32_f64
17072 || flavour
== neon_cvt_flavour_u32_f64
)
17073 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17076 if (flavour
== neon_cvt_flavour_s32_f16
17077 || flavour
== neon_cvt_flavour_u32_f16
)
17078 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
17081 set_pred_insn_type (OUTSIDE_PRED_INSN
);
17085 case neon_cvt_flavour_s32_f64
:
17089 case neon_cvt_flavour_s32_f32
:
17093 case neon_cvt_flavour_s32_f16
:
17097 case neon_cvt_flavour_u32_f64
:
17101 case neon_cvt_flavour_u32_f32
:
17105 case neon_cvt_flavour_u32_f16
:
17110 first_error (_("invalid instruction shape"));
17116 case neon_cvt_mode_a
: rm
= 0; break;
17117 case neon_cvt_mode_n
: rm
= 1; break;
17118 case neon_cvt_mode_p
: rm
= 2; break;
17119 case neon_cvt_mode_m
: rm
= 3; break;
17120 default: first_error (_("invalid rounding mode")); return;
17123 NEON_ENCODE (FPV8
, inst
);
17124 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
17125 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
17126 inst
.instruction
|= sz
<< 8;
17128 /* ARMv8.2 fp16 VCVT instruction. */
17129 if (flavour
== neon_cvt_flavour_s32_f16
17130 ||flavour
== neon_cvt_flavour_u32_f16
)
17131 do_scalar_fp16_v82_encode ();
17132 inst
.instruction
|= op
<< 7;
17133 inst
.instruction
|= rm
<< 16;
17134 inst
.instruction
|= 0xf0000000;
17135 inst
.is_neon
= TRUE
;
17139 do_neon_cvt_1 (enum neon_cvt_mode mode
)
17141 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
17142 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
17143 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
17145 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17147 if (flavour
== neon_cvt_flavour_invalid
)
17150 /* PR11109: Handle round-to-zero for VCVT conversions. */
17151 if (mode
== neon_cvt_mode_z
17152 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
17153 && (flavour
== neon_cvt_flavour_s16_f16
17154 || flavour
== neon_cvt_flavour_u16_f16
17155 || flavour
== neon_cvt_flavour_s32_f32
17156 || flavour
== neon_cvt_flavour_u32_f32
17157 || flavour
== neon_cvt_flavour_s32_f64
17158 || flavour
== neon_cvt_flavour_u32_f64
)
17159 && (rs
== NS_FD
|| rs
== NS_FF
))
17161 do_vfp_nsyn_cvtz ();
17165 /* ARMv8.2 fp16 VCVT conversions. */
17166 if (mode
== neon_cvt_mode_z
17167 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
17168 && (flavour
== neon_cvt_flavour_s32_f16
17169 || flavour
== neon_cvt_flavour_u32_f16
)
17172 do_vfp_nsyn_cvtz ();
17173 do_scalar_fp16_v82_encode ();
17177 /* VFP rather than Neon conversions. */
17178 if (flavour
>= neon_cvt_flavour_first_fp
)
17180 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
17181 do_vfp_nsyn_cvt (rs
, flavour
);
17183 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
17191 if (mode
== neon_cvt_mode_z
17192 && (flavour
== neon_cvt_flavour_f16_s16
17193 || flavour
== neon_cvt_flavour_f16_u16
17194 || flavour
== neon_cvt_flavour_s16_f16
17195 || flavour
== neon_cvt_flavour_u16_f16
17196 || flavour
== neon_cvt_flavour_f32_u32
17197 || flavour
== neon_cvt_flavour_f32_s32
17198 || flavour
== neon_cvt_flavour_s32_f32
17199 || flavour
== neon_cvt_flavour_u32_f32
))
17201 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17204 else if (mode
== neon_cvt_mode_n
)
17206 /* We are dealing with vcvt with the 'ne' condition. */
17208 inst
.instruction
= N_MNEM_vcvt
;
17209 do_neon_cvt_1 (neon_cvt_mode_z
);
17212 /* fall through. */
17216 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
17217 0x0000100, 0x1000100, 0x0, 0x1000000};
17219 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17220 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17223 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17225 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
17226 _("immediate value out of range"));
17229 case neon_cvt_flavour_f16_s16
:
17230 case neon_cvt_flavour_f16_u16
:
17231 case neon_cvt_flavour_s16_f16
:
17232 case neon_cvt_flavour_u16_f16
:
17233 constraint (inst
.operands
[2].imm
> 16,
17234 _("immediate value out of range"));
17236 case neon_cvt_flavour_f32_u32
:
17237 case neon_cvt_flavour_f32_s32
:
17238 case neon_cvt_flavour_s32_f32
:
17239 case neon_cvt_flavour_u32_f32
:
17240 constraint (inst
.operands
[2].imm
> 32,
17241 _("immediate value out of range"));
17244 inst
.error
= BAD_FPU
;
17249 /* Fixed-point conversion with #0 immediate is encoded as an
17250 integer conversion. */
17251 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
17253 NEON_ENCODE (IMMED
, inst
);
17254 if (flavour
!= neon_cvt_flavour_invalid
)
17255 inst
.instruction
|= enctab
[flavour
];
17256 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17257 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17258 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17259 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17260 inst
.instruction
|= neon_quad (rs
) << 6;
17261 inst
.instruction
|= 1 << 21;
17262 if (flavour
< neon_cvt_flavour_s16_f16
)
17264 inst
.instruction
|= 1 << 21;
17265 immbits
= 32 - inst
.operands
[2].imm
;
17266 inst
.instruction
|= immbits
<< 16;
17270 inst
.instruction
|= 3 << 20;
17271 immbits
= 16 - inst
.operands
[2].imm
;
17272 inst
.instruction
|= immbits
<< 16;
17273 inst
.instruction
&= ~(1 << 9);
17276 neon_dp_fixup (&inst
);
17281 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17282 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
17283 && (flavour
== neon_cvt_flavour_s16_f16
17284 || flavour
== neon_cvt_flavour_u16_f16
17285 || flavour
== neon_cvt_flavour_s32_f32
17286 || flavour
== neon_cvt_flavour_u32_f32
))
17288 if (check_simd_pred_availability (1,
17289 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
17292 else if (mode
== neon_cvt_mode_z
17293 && (flavour
== neon_cvt_flavour_f16_s16
17294 || flavour
== neon_cvt_flavour_f16_u16
17295 || flavour
== neon_cvt_flavour_s16_f16
17296 || flavour
== neon_cvt_flavour_u16_f16
17297 || flavour
== neon_cvt_flavour_f32_u32
17298 || flavour
== neon_cvt_flavour_f32_s32
17299 || flavour
== neon_cvt_flavour_s32_f32
17300 || flavour
== neon_cvt_flavour_u32_f32
))
17302 if (check_simd_pred_availability (1,
17303 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17306 /* fall through. */
17308 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
17311 NEON_ENCODE (FLOAT
, inst
);
17312 if (check_simd_pred_availability (1,
17313 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
17316 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17317 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17318 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17319 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17320 inst
.instruction
|= neon_quad (rs
) << 6;
17321 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
17322 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
17323 inst
.instruction
|= mode
<< 8;
17324 if (flavour
== neon_cvt_flavour_u16_f16
17325 || flavour
== neon_cvt_flavour_s16_f16
)
17326 /* Mask off the original size bits and reencode them. */
17327 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
17330 inst
.instruction
|= 0xfc000000;
17332 inst
.instruction
|= 0xf0000000;
17338 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
17339 0x100, 0x180, 0x0, 0x080};
17341 NEON_ENCODE (INTEGER
, inst
);
17343 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17345 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17349 if (flavour
!= neon_cvt_flavour_invalid
)
17350 inst
.instruction
|= enctab
[flavour
];
17352 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17353 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17354 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17355 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17356 inst
.instruction
|= neon_quad (rs
) << 6;
17357 if (flavour
>= neon_cvt_flavour_s16_f16
17358 && flavour
<= neon_cvt_flavour_f16_u16
)
17359 /* Half precision. */
17360 inst
.instruction
|= 1 << 18;
17362 inst
.instruction
|= 2 << 18;
17364 neon_dp_fixup (&inst
);
17369 /* Half-precision conversions for Advanced SIMD -- neon. */
17372 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17376 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
17378 as_bad (_("operand size must match register width"));
17383 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
17385 as_bad (_("operand size must match register width"));
17390 inst
.instruction
= 0x3b60600;
17392 inst
.instruction
= 0x3b60700;
17394 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17395 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17396 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17397 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17398 neon_dp_fixup (&inst
);
17402 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
17403 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
17404 do_vfp_nsyn_cvt (rs
, flavour
);
17406 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
17411 do_neon_cvtr (void)
17413 do_neon_cvt_1 (neon_cvt_mode_x
);
17419 do_neon_cvt_1 (neon_cvt_mode_z
);
17423 do_neon_cvta (void)
17425 do_neon_cvt_1 (neon_cvt_mode_a
);
17429 do_neon_cvtn (void)
17431 do_neon_cvt_1 (neon_cvt_mode_n
);
17435 do_neon_cvtp (void)
17437 do_neon_cvt_1 (neon_cvt_mode_p
);
17441 do_neon_cvtm (void)
17443 do_neon_cvt_1 (neon_cvt_mode_m
);
17447 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
17450 mark_feature_used (&fpu_vfp_ext_armv8
);
17452 encode_arm_vfp_reg (inst
.operands
[0].reg
,
17453 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
17454 encode_arm_vfp_reg (inst
.operands
[1].reg
,
17455 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
17456 inst
.instruction
|= to
? 0x10000 : 0;
17457 inst
.instruction
|= t
? 0x80 : 0;
17458 inst
.instruction
|= is_double
? 0x100 : 0;
17459 do_vfp_cond_or_thumb ();
17463 do_neon_cvttb_1 (bfd_boolean t
)
17465 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
17466 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
17470 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
17472 int single_to_half
= 0;
17473 if (check_simd_pred_availability (1, NEON_CHECK_ARCH
))
17476 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17478 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17479 && (flavour
== neon_cvt_flavour_u16_f16
17480 || flavour
== neon_cvt_flavour_s16_f16
17481 || flavour
== neon_cvt_flavour_f16_s16
17482 || flavour
== neon_cvt_flavour_f16_u16
17483 || flavour
== neon_cvt_flavour_u32_f32
17484 || flavour
== neon_cvt_flavour_s32_f32
17485 || flavour
== neon_cvt_flavour_f32_s32
17486 || flavour
== neon_cvt_flavour_f32_u32
))
17489 inst
.instruction
= N_MNEM_vcvt
;
17490 set_pred_insn_type (INSIDE_VPT_INSN
);
17491 do_neon_cvt_1 (neon_cvt_mode_z
);
17494 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
17495 single_to_half
= 1;
17496 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
17498 first_error (BAD_FPU
);
17502 inst
.instruction
= 0xee3f0e01;
17503 inst
.instruction
|= single_to_half
<< 28;
17504 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17505 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
17506 inst
.instruction
|= t
<< 12;
17507 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17508 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
17511 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
17514 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
17516 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
17519 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
17521 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
17523 /* The VCVTB and VCVTT instructions with D-register operands
17524 don't work for SP only targets. */
17525 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17529 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
17531 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
17533 /* The VCVTB and VCVTT instructions with D-register operands
17534 don't work for SP only targets. */
17535 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17539 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
17546 do_neon_cvtb (void)
17548 do_neon_cvttb_1 (FALSE
);
17553 do_neon_cvtt (void)
17555 do_neon_cvttb_1 (TRUE
);
17559 neon_move_immediate (void)
17561 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
17562 struct neon_type_el et
= neon_check_type (2, rs
,
17563 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
17564 unsigned immlo
, immhi
= 0, immbits
;
17565 int op
, cmode
, float_p
;
17567 constraint (et
.type
== NT_invtype
,
17568 _("operand size must be specified for immediate VMOV"));
17570 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
17571 op
= (inst
.instruction
& (1 << 5)) != 0;
17573 immlo
= inst
.operands
[1].imm
;
17574 if (inst
.operands
[1].regisimm
)
17575 immhi
= inst
.operands
[1].reg
;
17577 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
17578 _("immediate has bits set outside the operand size"));
17580 float_p
= inst
.operands
[1].immisfloat
;
17582 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
17583 et
.size
, et
.type
)) == FAIL
)
17585 /* Invert relevant bits only. */
17586 neon_invert_size (&immlo
, &immhi
, et
.size
);
17587 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
17588 with one or the other; those cases are caught by
17589 neon_cmode_for_move_imm. */
17591 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
17592 &op
, et
.size
, et
.type
)) == FAIL
)
17594 first_error (_("immediate out of range"));
17599 inst
.instruction
&= ~(1 << 5);
17600 inst
.instruction
|= op
<< 5;
17602 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17603 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17604 inst
.instruction
|= neon_quad (rs
) << 6;
17605 inst
.instruction
|= cmode
<< 8;
17607 neon_write_immbits (immbits
);
17613 if (inst
.operands
[1].isreg
)
17615 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17617 NEON_ENCODE (INTEGER
, inst
);
17618 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17619 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17620 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17621 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17622 inst
.instruction
|= neon_quad (rs
) << 6;
17626 NEON_ENCODE (IMMED
, inst
);
17627 neon_move_immediate ();
17630 neon_dp_fixup (&inst
);
17633 /* Encode instructions of form:
17635 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
17636 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
17639 neon_mixed_length (struct neon_type_el et
, unsigned size
)
17641 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17642 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17643 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17644 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17645 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
17646 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
17647 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
17648 inst
.instruction
|= neon_logbits (size
) << 20;
17650 neon_dp_fixup (&inst
);
17654 do_neon_dyadic_long (void)
17656 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17659 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
17662 NEON_ENCODE (INTEGER
, inst
);
17663 /* FIXME: Type checking for lengthening op. */
17664 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
17665 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
17666 neon_mixed_length (et
, et
.size
);
17668 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17669 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
17671 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
17672 in an IT block with le/lt conditions. */
17674 if (inst
.cond
== 0xf)
17676 else if (inst
.cond
== 0x10)
17679 inst
.pred_insn_type
= INSIDE_IT_INSN
;
17681 if (inst
.instruction
== N_MNEM_vaddl
)
17683 inst
.instruction
= N_MNEM_vadd
;
17684 do_neon_addsub_if_i ();
17686 else if (inst
.instruction
== N_MNEM_vsubl
)
17688 inst
.instruction
= N_MNEM_vsub
;
17689 do_neon_addsub_if_i ();
17691 else if (inst
.instruction
== N_MNEM_vabdl
)
17693 inst
.instruction
= N_MNEM_vabd
;
17694 do_neon_dyadic_if_su ();
17698 first_error (BAD_FPU
);
17702 do_neon_abal (void)
17704 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
17705 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
17706 neon_mixed_length (et
, et
.size
);
17710 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
17712 if (inst
.operands
[2].isscalar
)
17714 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
17715 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
17716 NEON_ENCODE (SCALAR
, inst
);
17717 neon_mul_mac (et
, et
.type
== NT_unsigned
);
17721 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
17722 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
17723 NEON_ENCODE (INTEGER
, inst
);
17724 neon_mixed_length (et
, et
.size
);
17729 do_neon_mac_maybe_scalar_long (void)
17731 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
17734 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
17735 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
17738 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
17740 unsigned regno
= NEON_SCALAR_REG (scalar
);
17741 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17745 if (regno
> 7 || elno
> 3)
17748 return ((regno
& 0x7)
17749 | ((elno
& 0x1) << 3)
17750 | (((elno
>> 1) & 0x1) << 5));
17754 if (regno
> 15 || elno
> 1)
17757 return (((regno
& 0x1) << 5)
17758 | ((regno
>> 1) & 0x7)
17759 | ((elno
& 0x1) << 3));
17763 first_error (_("scalar out of range for multiply instruction"));
17768 do_neon_fmac_maybe_scalar_long (int subtype
)
17770 enum neon_shape rs
;
17772 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
17773 field (bits[21:20]) has different meaning. For scalar index variant, it's
17774 used to differentiate add and subtract, otherwise it's with fixed value
17778 if (inst
.cond
!= COND_ALWAYS
)
17779 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
17780 "behaviour is UNPREDICTABLE"));
17782 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
17785 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17788 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
17789 be a scalar index register. */
17790 if (inst
.operands
[2].isscalar
)
17792 high8
= 0xfe000000;
17795 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
17799 high8
= 0xfc000000;
17802 inst
.instruction
|= (0x1 << 23);
17803 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
17806 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
17808 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
17809 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
17810 so we simply pass -1 as size. */
17811 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
17812 neon_three_same (quad_p
, 0, size
);
17814 /* Undo neon_dp_fixup. Redo the high eight bits. */
17815 inst
.instruction
&= 0x00ffffff;
17816 inst
.instruction
|= high8
;
17818 #define LOW1(R) ((R) & 0x1)
17819 #define HI4(R) (((R) >> 1) & 0xf)
17820 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
17821 whether the instruction is in Q form and whether Vm is a scalar indexed
17823 if (inst
.operands
[2].isscalar
)
17826 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
17827 inst
.instruction
&= 0xffffffd0;
17828 inst
.instruction
|= rm
;
17832 /* Redo Rn as well. */
17833 inst
.instruction
&= 0xfff0ff7f;
17834 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
17835 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
17840 /* Redo Rn and Rm. */
17841 inst
.instruction
&= 0xfff0ff50;
17842 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
17843 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
17844 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
17845 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
17850 do_neon_vfmal (void)
17852 return do_neon_fmac_maybe_scalar_long (0);
17856 do_neon_vfmsl (void)
17858 return do_neon_fmac_maybe_scalar_long (1);
17862 do_neon_dyadic_wide (void)
17864 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
17865 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
17866 neon_mixed_length (et
, et
.size
);
17870 do_neon_dyadic_narrow (void)
17872 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
17873 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
17874 /* Operand sign is unimportant, and the U bit is part of the opcode,
17875 so force the operand type to integer. */
17876 et
.type
= NT_integer
;
17877 neon_mixed_length (et
, et
.size
/ 2);
17881 do_neon_mul_sat_scalar_long (void)
17883 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
17887 do_neon_vmull (void)
17889 if (inst
.operands
[2].isscalar
)
17890 do_neon_mac_maybe_scalar_long ();
17893 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
17894 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
17896 if (et
.type
== NT_poly
)
17897 NEON_ENCODE (POLY
, inst
);
17899 NEON_ENCODE (INTEGER
, inst
);
17901 /* For polynomial encoding the U bit must be zero, and the size must
17902 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
17903 obviously, as 0b10). */
17906 /* Check we're on the correct architecture. */
17907 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
17909 _("Instruction form not available on this architecture.");
17914 neon_mixed_length (et
, et
.size
);
17921 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17922 struct neon_type_el et
= neon_check_type (3, rs
,
17923 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
17924 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
17926 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
17927 _("shift out of range"));
17928 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17929 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17930 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17931 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17932 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
17933 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
17934 inst
.instruction
|= neon_quad (rs
) << 6;
17935 inst
.instruction
|= imm
<< 8;
17937 neon_dp_fixup (&inst
);
17943 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17944 struct neon_type_el et
= neon_check_type (2, rs
,
17945 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17946 unsigned op
= (inst
.instruction
>> 7) & 3;
17947 /* N (width of reversed regions) is encoded as part of the bitmask. We
17948 extract it here to check the elements to be reversed are smaller.
17949 Otherwise we'd get a reserved instruction. */
17950 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
17951 gas_assert (elsize
!= 0);
17952 constraint (et
.size
>= elsize
,
17953 _("elements must be smaller than reversal region"));
17954 neon_two_same (neon_quad (rs
), 1, et
.size
);
17960 if (inst
.operands
[1].isscalar
)
17962 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
17963 struct neon_type_el et
= neon_check_type (2, rs
,
17964 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17965 unsigned sizebits
= et
.size
>> 3;
17966 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
17967 int logsize
= neon_logbits (et
.size
);
17968 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
17970 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
17973 NEON_ENCODE (SCALAR
, inst
);
17974 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17975 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17976 inst
.instruction
|= LOW4 (dm
);
17977 inst
.instruction
|= HI1 (dm
) << 5;
17978 inst
.instruction
|= neon_quad (rs
) << 6;
17979 inst
.instruction
|= x
<< 17;
17980 inst
.instruction
|= sizebits
<< 16;
17982 neon_dp_fixup (&inst
);
17986 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
17987 struct neon_type_el et
= neon_check_type (2, rs
,
17988 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
17989 /* Duplicate ARM register to lanes of vector. */
17990 NEON_ENCODE (ARMREG
, inst
);
17993 case 8: inst
.instruction
|= 0x400000; break;
17994 case 16: inst
.instruction
|= 0x000020; break;
17995 case 32: inst
.instruction
|= 0x000000; break;
17998 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
17999 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
18000 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
18001 inst
.instruction
|= neon_quad (rs
) << 21;
18002 /* The encoding for this instruction is identical for the ARM and Thumb
18003 variants, except for the condition field. */
18004 do_vfp_cond_or_thumb ();
18009 do_mve_mov (int toQ
)
18011 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18013 if (inst
.cond
> COND_ALWAYS
)
18014 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
18016 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
18025 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
18026 _("Index one must be [2,3] and index two must be two less than"
18028 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
18029 _("General purpose registers may not be the same"));
18030 constraint (inst
.operands
[Rt
].reg
== REG_SP
18031 || inst
.operands
[Rt2
].reg
== REG_SP
,
18033 constraint (inst
.operands
[Rt
].reg
== REG_PC
18034 || inst
.operands
[Rt2
].reg
== REG_PC
,
18037 inst
.instruction
= 0xec000f00;
18038 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
18039 inst
.instruction
|= !!toQ
<< 20;
18040 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
18041 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
18042 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
18043 inst
.instruction
|= inst
.operands
[Rt
].reg
;
18049 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18052 if (inst
.cond
> COND_ALWAYS
)
18053 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18055 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18057 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
18060 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18061 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
18062 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18063 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18064 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18069 /* VMOV has particularly many variations. It can be one of:
18070 0. VMOV<c><q> <Qd>, <Qm>
18071 1. VMOV<c><q> <Dd>, <Dm>
18072 (Register operations, which are VORR with Rm = Rn.)
18073 2. VMOV<c><q>.<dt> <Qd>, #<imm>
18074 3. VMOV<c><q>.<dt> <Dd>, #<imm>
18076 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
18077 (ARM register to scalar.)
18078 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
18079 (Two ARM registers to vector.)
18080 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
18081 (Scalar to ARM register.)
18082 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
18083 (Vector to two ARM registers.)
18084 8. VMOV.F32 <Sd>, <Sm>
18085 9. VMOV.F64 <Dd>, <Dm>
18086 (VFP register moves.)
18087 10. VMOV.F32 <Sd>, #imm
18088 11. VMOV.F64 <Dd>, #imm
18089 (VFP float immediate load.)
18090 12. VMOV <Rd>, <Sm>
18091 (VFP single to ARM reg.)
18092 13. VMOV <Sd>, <Rm>
18093 (ARM reg to VFP single.)
18094 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
18095 (Two ARM regs to two VFP singles.)
18096 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
18097 (Two VFP singles to two ARM regs.)
18098 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
18099 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
18100 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
18101 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
18103 These cases can be disambiguated using neon_select_shape, except cases 1/9
18104 and 3/11 which depend on the operand type too.
18106 All the encoded bits are hardcoded by this function.
18108 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
18109 Cases 5, 7 may be used with VFPv2 and above.
18111 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
18112 can specify a type where it doesn't make sense to, and is ignored). */
18117 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
18118 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
18119 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
18120 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
18122 struct neon_type_el et
;
18123 const char *ldconst
= 0;
18127 case NS_DD
: /* case 1/9. */
18128 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
18129 /* It is not an error here if no type is given. */
18131 if (et
.type
== NT_float
&& et
.size
== 64)
18133 do_vfp_nsyn_opcode ("fcpyd");
18136 /* fall through. */
18138 case NS_QQ
: /* case 0/1. */
18140 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18142 /* The architecture manual I have doesn't explicitly state which
18143 value the U bit should have for register->register moves, but
18144 the equivalent VORR instruction has U = 0, so do that. */
18145 inst
.instruction
= 0x0200110;
18146 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18147 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18148 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18149 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18150 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18151 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18152 inst
.instruction
|= neon_quad (rs
) << 6;
18154 neon_dp_fixup (&inst
);
18158 case NS_DI
: /* case 3/11. */
18159 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
18161 if (et
.type
== NT_float
&& et
.size
== 64)
18163 /* case 11 (fconstd). */
18164 ldconst
= "fconstd";
18165 goto encode_fconstd
;
18167 /* fall through. */
18169 case NS_QI
: /* case 2/3. */
18170 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18172 inst
.instruction
= 0x0800010;
18173 neon_move_immediate ();
18174 neon_dp_fixup (&inst
);
18177 case NS_SR
: /* case 4. */
18179 unsigned bcdebits
= 0;
18181 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
18182 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
18184 /* .<size> is optional here, defaulting to .32. */
18185 if (inst
.vectype
.elems
== 0
18186 && inst
.operands
[0].vectype
.type
== NT_invtype
18187 && inst
.operands
[1].vectype
.type
== NT_invtype
)
18189 inst
.vectype
.el
[0].type
= NT_untyped
;
18190 inst
.vectype
.el
[0].size
= 32;
18191 inst
.vectype
.elems
= 1;
18194 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
18195 logsize
= neon_logbits (et
.size
);
18199 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18200 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
18205 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
18206 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18210 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18212 if (inst
.operands
[1].reg
== REG_SP
)
18213 as_tsktsk (MVE_BAD_SP
);
18214 else if (inst
.operands
[1].reg
== REG_PC
)
18215 as_tsktsk (MVE_BAD_PC
);
18217 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
18219 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
18220 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
18225 case 8: bcdebits
= 0x8; break;
18226 case 16: bcdebits
= 0x1; break;
18227 case 32: bcdebits
= 0x0; break;
18231 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
18233 inst
.instruction
= 0xe000b10;
18234 do_vfp_cond_or_thumb ();
18235 inst
.instruction
|= LOW4 (dn
) << 16;
18236 inst
.instruction
|= HI1 (dn
) << 7;
18237 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
18238 inst
.instruction
|= (bcdebits
& 3) << 5;
18239 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
18240 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
18244 case NS_DRR
: /* case 5 (fmdrr). */
18245 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18246 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18249 inst
.instruction
= 0xc400b10;
18250 do_vfp_cond_or_thumb ();
18251 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
18252 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
18253 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
18254 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
18257 case NS_RS
: /* case 6. */
18260 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
18261 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
18262 unsigned abcdebits
= 0;
18264 /* .<dt> is optional here, defaulting to .32. */
18265 if (inst
.vectype
.elems
== 0
18266 && inst
.operands
[0].vectype
.type
== NT_invtype
18267 && inst
.operands
[1].vectype
.type
== NT_invtype
)
18269 inst
.vectype
.el
[0].type
= NT_untyped
;
18270 inst
.vectype
.el
[0].size
= 32;
18271 inst
.vectype
.elems
= 1;
18274 et
= neon_check_type (2, NS_NULL
,
18275 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
18276 logsize
= neon_logbits (et
.size
);
18280 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18281 && vfp_or_neon_is_neon (NEON_CHECK_CC
18282 | NEON_CHECK_ARCH
) == FAIL
)
18287 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
18288 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18292 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18294 if (inst
.operands
[0].reg
== REG_SP
)
18295 as_tsktsk (MVE_BAD_SP
);
18296 else if (inst
.operands
[0].reg
== REG_PC
)
18297 as_tsktsk (MVE_BAD_PC
);
18300 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
18302 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
18303 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
18307 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
18308 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
18309 case 32: abcdebits
= 0x00; break;
18313 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
18314 inst
.instruction
= 0xe100b10;
18315 do_vfp_cond_or_thumb ();
18316 inst
.instruction
|= LOW4 (dn
) << 16;
18317 inst
.instruction
|= HI1 (dn
) << 7;
18318 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
18319 inst
.instruction
|= (abcdebits
& 3) << 5;
18320 inst
.instruction
|= (abcdebits
>> 2) << 21;
18321 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
18325 case NS_RRD
: /* case 7 (fmrrd). */
18326 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18327 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18330 inst
.instruction
= 0xc500b10;
18331 do_vfp_cond_or_thumb ();
18332 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
18333 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
18334 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18335 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18338 case NS_FF
: /* case 8 (fcpys). */
18339 do_vfp_nsyn_opcode ("fcpys");
18343 case NS_FI
: /* case 10 (fconsts). */
18344 ldconst
= "fconsts";
18346 if (!inst
.operands
[1].immisfloat
)
18349 /* Immediate has to fit in 8 bits so float is enough. */
18350 float imm
= (float) inst
.operands
[1].imm
;
18351 memcpy (&new_imm
, &imm
, sizeof (float));
18352 /* But the assembly may have been written to provide an integer
18353 bit pattern that equates to a float, so check that the
18354 conversion has worked. */
18355 if (is_quarter_float (new_imm
))
18357 if (is_quarter_float (inst
.operands
[1].imm
))
18358 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
18360 inst
.operands
[1].imm
= new_imm
;
18361 inst
.operands
[1].immisfloat
= 1;
18365 if (is_quarter_float (inst
.operands
[1].imm
))
18367 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
18368 do_vfp_nsyn_opcode (ldconst
);
18370 /* ARMv8.2 fp16 vmov.f16 instruction. */
18372 do_scalar_fp16_v82_encode ();
18375 first_error (_("immediate out of range"));
18379 case NS_RF
: /* case 12 (fmrs). */
18380 do_vfp_nsyn_opcode ("fmrs");
18381 /* ARMv8.2 fp16 vmov.f16 instruction. */
18383 do_scalar_fp16_v82_encode ();
18387 case NS_FR
: /* case 13 (fmsr). */
18388 do_vfp_nsyn_opcode ("fmsr");
18389 /* ARMv8.2 fp16 vmov.f16 instruction. */
18391 do_scalar_fp16_v82_encode ();
18401 /* The encoders for the fmrrs and fmsrr instructions expect three operands
18402 (one of which is a list), but we have parsed four. Do some fiddling to
18403 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
18405 case NS_RRFF
: /* case 14 (fmrrs). */
18406 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18407 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18409 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
18410 _("VFP registers must be adjacent"));
18411 inst
.operands
[2].imm
= 2;
18412 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
18413 do_vfp_nsyn_opcode ("fmrrs");
18416 case NS_FFRR
: /* case 15 (fmsrr). */
18417 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18418 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18420 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
18421 _("VFP registers must be adjacent"));
18422 inst
.operands
[1] = inst
.operands
[2];
18423 inst
.operands
[2] = inst
.operands
[3];
18424 inst
.operands
[0].imm
= 2;
18425 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
18426 do_vfp_nsyn_opcode ("fmsrr");
18430 /* neon_select_shape has determined that the instruction
18431 shape is wrong and has already set the error message. */
18442 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
18443 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
18444 && !inst
.operands
[2].present
))
18446 inst
.instruction
= 0;
18449 set_pred_insn_type (INSIDE_IT_INSN
);
18454 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18457 if (inst
.cond
!= COND_ALWAYS
)
18458 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18460 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
18461 | N_S16
| N_U16
| N_KEY
);
18463 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
18464 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18465 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
18466 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18467 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18468 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18473 do_neon_rshift_round_imm (void)
18475 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18476 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
18477 int imm
= inst
.operands
[2].imm
;
18479 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
18482 inst
.operands
[2].present
= 0;
18487 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18488 _("immediate out of range for shift"));
18489 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
18494 do_neon_movhf (void)
18496 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
18497 constraint (rs
!= NS_HH
, _("invalid suffix"));
18499 if (inst
.cond
!= COND_ALWAYS
)
18503 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
18504 " the behaviour is UNPREDICTABLE"));
18508 inst
.error
= BAD_COND
;
18513 do_vfp_sp_monadic ();
18516 inst
.instruction
|= 0xf0000000;
18520 do_neon_movl (void)
18522 struct neon_type_el et
= neon_check_type (2, NS_QD
,
18523 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18524 unsigned sizebits
= et
.size
>> 3;
18525 inst
.instruction
|= sizebits
<< 19;
18526 neon_two_same (0, et
.type
== NT_unsigned
, -1);
18532 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18533 struct neon_type_el et
= neon_check_type (2, rs
,
18534 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18535 NEON_ENCODE (INTEGER
, inst
);
18536 neon_two_same (neon_quad (rs
), 1, et
.size
);
18540 do_neon_zip_uzp (void)
18542 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18543 struct neon_type_el et
= neon_check_type (2, rs
,
18544 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18545 if (rs
== NS_DD
&& et
.size
== 32)
18547 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
18548 inst
.instruction
= N_MNEM_vtrn
;
18552 neon_two_same (neon_quad (rs
), 1, et
.size
);
18556 do_neon_sat_abs_neg (void)
18558 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18559 struct neon_type_el et
= neon_check_type (2, rs
,
18560 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18561 neon_two_same (neon_quad (rs
), 1, et
.size
);
18565 do_neon_pair_long (void)
18567 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18568 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18569 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
18570 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
18571 neon_two_same (neon_quad (rs
), 1, et
.size
);
18575 do_neon_recip_est (void)
18577 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18578 struct neon_type_el et
= neon_check_type (2, rs
,
18579 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
18580 inst
.instruction
|= (et
.type
== NT_float
) << 8;
18581 neon_two_same (neon_quad (rs
), 1, et
.size
);
18587 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18588 struct neon_type_el et
= neon_check_type (2, rs
,
18589 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18590 neon_two_same (neon_quad (rs
), 1, et
.size
);
18596 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18597 struct neon_type_el et
= neon_check_type (2, rs
,
18598 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
18599 neon_two_same (neon_quad (rs
), 1, et
.size
);
18605 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18606 struct neon_type_el et
= neon_check_type (2, rs
,
18607 N_EQK
| N_INT
, N_8
| N_KEY
);
18608 neon_two_same (neon_quad (rs
), 1, et
.size
);
18614 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18615 neon_two_same (neon_quad (rs
), 1, -1);
18619 do_neon_tbl_tbx (void)
18621 unsigned listlenbits
;
18622 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
18624 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
18626 first_error (_("bad list length for table lookup"));
18630 listlenbits
= inst
.operands
[1].imm
- 1;
18631 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18632 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18633 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18634 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18635 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18636 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18637 inst
.instruction
|= listlenbits
<< 8;
18639 neon_dp_fixup (&inst
);
18643 do_neon_ldm_stm (void)
18645 /* P, U and L bits are part of bitmask. */
18646 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
18647 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
18649 if (inst
.operands
[1].issingle
)
18651 do_vfp_nsyn_ldm_stm (is_dbmode
);
18655 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
18656 _("writeback (!) must be used for VLDMDB and VSTMDB"));
18658 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
18659 _("register list must contain at least 1 and at most 16 "
18662 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
18663 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
18664 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
18665 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
18667 inst
.instruction
|= offsetbits
;
18669 do_vfp_cond_or_thumb ();
18673 do_neon_ldr_str (void)
18675 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
18677 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
18678 And is UNPREDICTABLE in thumb mode. */
18680 && inst
.operands
[1].reg
== REG_PC
18681 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
18684 inst
.error
= _("Use of PC here is UNPREDICTABLE");
18685 else if (warn_on_deprecated
)
18686 as_tsktsk (_("Use of PC here is deprecated"));
18689 if (inst
.operands
[0].issingle
)
18692 do_vfp_nsyn_opcode ("flds");
18694 do_vfp_nsyn_opcode ("fsts");
18696 /* ARMv8.2 vldr.16/vstr.16 instruction. */
18697 if (inst
.vectype
.el
[0].size
== 16)
18698 do_scalar_fp16_v82_encode ();
18703 do_vfp_nsyn_opcode ("fldd");
18705 do_vfp_nsyn_opcode ("fstd");
18710 do_t_vldr_vstr_sysreg (void)
18712 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
18713 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
18715 /* Use of PC is UNPREDICTABLE. */
18716 if (inst
.operands
[1].reg
== REG_PC
)
18717 inst
.error
= _("Use of PC here is UNPREDICTABLE");
18719 if (inst
.operands
[1].immisreg
)
18720 inst
.error
= _("instruction does not accept register index");
18722 if (!inst
.operands
[1].isreg
)
18723 inst
.error
= _("instruction does not accept PC-relative addressing");
18725 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
18726 inst
.error
= _("immediate value out of range");
18728 inst
.instruction
= 0xec000f80;
18730 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
18731 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
18732 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
18733 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
18737 do_vldr_vstr (void)
18739 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
18741 /* VLDR/VSTR (System Register). */
18744 if (!mark_feature_used (&arm_ext_v8_1m_main
))
18745 as_bad (_("Instruction not permitted on this architecture"));
18747 do_t_vldr_vstr_sysreg ();
18752 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
18753 as_bad (_("Instruction not permitted on this architecture"));
18754 do_neon_ldr_str ();
18758 /* "interleave" version also handles non-interleaving register VLD1/VST1
18762 do_neon_ld_st_interleave (void)
18764 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
18765 N_8
| N_16
| N_32
| N_64
);
18766 unsigned alignbits
= 0;
18768 /* The bits in this table go:
18769 0: register stride of one (0) or two (1)
18770 1,2: register list length, minus one (1, 2, 3, 4).
18771 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
18772 We use -1 for invalid entries. */
18773 const int typetable
[] =
18775 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
18776 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
18777 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
18778 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
18782 if (et
.type
== NT_invtype
)
18785 if (inst
.operands
[1].immisalign
)
18786 switch (inst
.operands
[1].imm
>> 8)
18788 case 64: alignbits
= 1; break;
18790 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
18791 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
18792 goto bad_alignment
;
18796 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
18797 goto bad_alignment
;
18802 first_error (_("bad alignment"));
18806 inst
.instruction
|= alignbits
<< 4;
18807 inst
.instruction
|= neon_logbits (et
.size
) << 6;
18809 /* Bits [4:6] of the immediate in a list specifier encode register stride
18810 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
18811 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
18812 up the right value for "type" in a table based on this value and the given
18813 list style, then stick it back. */
18814 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
18815 | (((inst
.instruction
>> 8) & 3) << 3);
18817 typebits
= typetable
[idx
];
18819 constraint (typebits
== -1, _("bad list type for instruction"));
18820 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
18823 inst
.instruction
&= ~0xf00;
18824 inst
.instruction
|= typebits
<< 8;
18827 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
18828 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
18829 otherwise. The variable arguments are a list of pairs of legal (size, align)
18830 values, terminated with -1. */
18833 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
18836 int result
= FAIL
, thissize
, thisalign
;
18838 if (!inst
.operands
[1].immisalign
)
18844 va_start (ap
, do_alignment
);
18848 thissize
= va_arg (ap
, int);
18849 if (thissize
== -1)
18851 thisalign
= va_arg (ap
, int);
18853 if (size
== thissize
&& align
== thisalign
)
18856 while (result
!= SUCCESS
);
18860 if (result
== SUCCESS
)
18863 first_error (_("unsupported alignment for instruction"));
18869 do_neon_ld_st_lane (void)
18871 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
18872 int align_good
, do_alignment
= 0;
18873 int logsize
= neon_logbits (et
.size
);
18874 int align
= inst
.operands
[1].imm
>> 8;
18875 int n
= (inst
.instruction
>> 8) & 3;
18876 int max_el
= 64 / et
.size
;
18878 if (et
.type
== NT_invtype
)
18881 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
18882 _("bad list length"));
18883 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
18884 _("scalar index out of range"));
18885 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
18887 _("stride of 2 unavailable when element size is 8"));
18891 case 0: /* VLD1 / VST1. */
18892 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
18894 if (align_good
== FAIL
)
18898 unsigned alignbits
= 0;
18901 case 16: alignbits
= 0x1; break;
18902 case 32: alignbits
= 0x3; break;
18905 inst
.instruction
|= alignbits
<< 4;
18909 case 1: /* VLD2 / VST2. */
18910 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
18911 16, 32, 32, 64, -1);
18912 if (align_good
== FAIL
)
18915 inst
.instruction
|= 1 << 4;
18918 case 2: /* VLD3 / VST3. */
18919 constraint (inst
.operands
[1].immisalign
,
18920 _("can't use alignment with this instruction"));
18923 case 3: /* VLD4 / VST4. */
18924 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
18925 16, 64, 32, 64, 32, 128, -1);
18926 if (align_good
== FAIL
)
18930 unsigned alignbits
= 0;
18933 case 8: alignbits
= 0x1; break;
18934 case 16: alignbits
= 0x1; break;
18935 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
18938 inst
.instruction
|= alignbits
<< 4;
18945 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
18946 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
18947 inst
.instruction
|= 1 << (4 + logsize
);
18949 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
18950 inst
.instruction
|= logsize
<< 10;
18953 /* Encode single n-element structure to all lanes VLD<n> instructions. */
18956 do_neon_ld_dup (void)
18958 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
18959 int align_good
, do_alignment
= 0;
18961 if (et
.type
== NT_invtype
)
18964 switch ((inst
.instruction
>> 8) & 3)
18966 case 0: /* VLD1. */
18967 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
18968 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
18969 &do_alignment
, 16, 16, 32, 32, -1);
18970 if (align_good
== FAIL
)
18972 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
18975 case 2: inst
.instruction
|= 1 << 5; break;
18976 default: first_error (_("bad list length")); return;
18978 inst
.instruction
|= neon_logbits (et
.size
) << 6;
18981 case 1: /* VLD2. */
18982 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
18983 &do_alignment
, 8, 16, 16, 32, 32, 64,
18985 if (align_good
== FAIL
)
18987 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
18988 _("bad list length"));
18989 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
18990 inst
.instruction
|= 1 << 5;
18991 inst
.instruction
|= neon_logbits (et
.size
) << 6;
18994 case 2: /* VLD3. */
18995 constraint (inst
.operands
[1].immisalign
,
18996 _("can't use alignment with this instruction"));
18997 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
18998 _("bad list length"));
18999 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19000 inst
.instruction
|= 1 << 5;
19001 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19004 case 3: /* VLD4. */
19006 int align
= inst
.operands
[1].imm
>> 8;
19007 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
19008 16, 64, 32, 64, 32, 128, -1);
19009 if (align_good
== FAIL
)
19011 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
19012 _("bad list length"));
19013 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19014 inst
.instruction
|= 1 << 5;
19015 if (et
.size
== 32 && align
== 128)
19016 inst
.instruction
|= 0x3 << 6;
19018 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19025 inst
.instruction
|= do_alignment
<< 4;
19028 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
19029 apart from bits [11:4]. */
19032 do_neon_ldx_stx (void)
19034 if (inst
.operands
[1].isreg
)
19035 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
19037 switch (NEON_LANE (inst
.operands
[0].imm
))
19039 case NEON_INTERLEAVE_LANES
:
19040 NEON_ENCODE (INTERLV
, inst
);
19041 do_neon_ld_st_interleave ();
19044 case NEON_ALL_LANES
:
19045 NEON_ENCODE (DUP
, inst
);
19046 if (inst
.instruction
== N_INV
)
19048 first_error ("only loads support such operands");
19055 NEON_ENCODE (LANE
, inst
);
19056 do_neon_ld_st_lane ();
19059 /* L bit comes from bit mask. */
19060 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19061 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19062 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19064 if (inst
.operands
[1].postind
)
19066 int postreg
= inst
.operands
[1].imm
& 0xf;
19067 constraint (!inst
.operands
[1].immisreg
,
19068 _("post-index must be a register"));
19069 constraint (postreg
== 0xd || postreg
== 0xf,
19070 _("bad register for post-index"));
19071 inst
.instruction
|= postreg
;
19075 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
19076 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
19077 || inst
.relocs
[0].exp
.X_add_number
!= 0,
19080 if (inst
.operands
[1].writeback
)
19082 inst
.instruction
|= 0xd;
19085 inst
.instruction
|= 0xf;
19089 inst
.instruction
|= 0xf9000000;
19091 inst
.instruction
|= 0xf4000000;
19096 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
19098 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19099 D register operands. */
19100 if (neon_shape_class
[rs
] == SC_DOUBLE
)
19101 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19104 NEON_ENCODE (FPV8
, inst
);
19106 if (rs
== NS_FFF
|| rs
== NS_HHH
)
19108 do_vfp_sp_dyadic ();
19110 /* ARMv8.2 fp16 instruction. */
19112 do_scalar_fp16_v82_encode ();
19115 do_vfp_dp_rd_rn_rm ();
19118 inst
.instruction
|= 0x100;
19120 inst
.instruction
|= 0xf0000000;
19126 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19128 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
19129 first_error (_("invalid instruction shape"));
19135 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19137 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
19140 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
19143 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
19147 do_vrint_1 (enum neon_cvt_mode mode
)
19149 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
19150 struct neon_type_el et
;
19155 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19156 D register operands. */
19157 if (neon_shape_class
[rs
] == SC_DOUBLE
)
19158 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19161 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
19163 if (et
.type
!= NT_invtype
)
19165 /* VFP encodings. */
19166 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19167 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
19168 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19170 NEON_ENCODE (FPV8
, inst
);
19171 if (rs
== NS_FF
|| rs
== NS_HH
)
19172 do_vfp_sp_monadic ();
19174 do_vfp_dp_rd_rm ();
19178 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
19179 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
19180 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
19181 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
19182 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
19183 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
19184 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
19188 inst
.instruction
|= (rs
== NS_DD
) << 8;
19189 do_vfp_cond_or_thumb ();
19191 /* ARMv8.2 fp16 vrint instruction. */
19193 do_scalar_fp16_v82_encode ();
19197 /* Neon encodings (or something broken...). */
19199 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
19201 if (et
.type
== NT_invtype
)
19204 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19205 NEON_ENCODE (FLOAT
, inst
);
19207 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
19210 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19211 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19212 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19213 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19214 inst
.instruction
|= neon_quad (rs
) << 6;
19215 /* Mask off the original size bits and reencode them. */
19216 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
19217 | neon_logbits (et
.size
) << 18);
19221 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
19222 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
19223 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
19224 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
19225 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
19226 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
19227 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
19232 inst
.instruction
|= 0xfc000000;
19234 inst
.instruction
|= 0xf0000000;
19241 do_vrint_1 (neon_cvt_mode_x
);
19247 do_vrint_1 (neon_cvt_mode_z
);
19253 do_vrint_1 (neon_cvt_mode_r
);
19259 do_vrint_1 (neon_cvt_mode_a
);
19265 do_vrint_1 (neon_cvt_mode_n
);
19271 do_vrint_1 (neon_cvt_mode_p
);
19277 do_vrint_1 (neon_cvt_mode_m
);
19281 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
19283 unsigned regno
= NEON_SCALAR_REG (opnd
);
19284 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
19286 if (elsize
== 16 && elno
< 2 && regno
< 16)
19287 return regno
| (elno
<< 4);
19288 else if (elsize
== 32 && elno
== 0)
19291 first_error (_("scalar out of range"));
19298 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19300 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
19301 _("expression too complex"));
19302 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
19303 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
19304 _("immediate out of range"));
19306 if (inst
.operands
[2].isscalar
)
19308 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
19309 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
19310 N_KEY
| N_F16
| N_F32
).size
;
19311 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
19313 inst
.instruction
= 0xfe000800;
19314 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19315 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19316 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19317 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19318 inst
.instruction
|= LOW4 (m
);
19319 inst
.instruction
|= HI1 (m
) << 5;
19320 inst
.instruction
|= neon_quad (rs
) << 6;
19321 inst
.instruction
|= rot
<< 20;
19322 inst
.instruction
|= (size
== 32) << 23;
19326 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19327 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
19328 N_KEY
| N_F16
| N_F32
).size
;
19329 neon_three_same (neon_quad (rs
), 0, -1);
19330 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
19331 inst
.instruction
|= 0xfc200800;
19332 inst
.instruction
|= rot
<< 23;
19333 inst
.instruction
|= (size
== 32) << 20;
19340 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19342 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
19343 _("expression too complex"));
19344 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
19345 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
19346 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19347 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
19348 N_KEY
| N_F16
| N_F32
).size
;
19349 neon_three_same (neon_quad (rs
), 0, -1);
19350 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
19351 inst
.instruction
|= 0xfc800800;
19352 inst
.instruction
|= (rot
== 270) << 24;
19353 inst
.instruction
|= (size
== 32) << 20;
19356 /* Dot Product instructions encoding support. */
19359 do_neon_dotproduct (int unsigned_p
)
19361 enum neon_shape rs
;
19362 unsigned scalar_oprd2
= 0;
19365 if (inst
.cond
!= COND_ALWAYS
)
19366 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
19367 "is UNPREDICTABLE"));
19369 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19372 /* Dot Product instructions are in three-same D/Q register format or the third
19373 operand can be a scalar index register. */
19374 if (inst
.operands
[2].isscalar
)
19376 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
19377 high8
= 0xfe000000;
19378 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
19382 high8
= 0xfc000000;
19383 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
19387 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
19389 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
19391 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
19392 Product instruction, so we pass 0 as the "ubit" parameter. And the
19393 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
19394 neon_three_same (neon_quad (rs
), 0, 32);
19396 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
19397 different NEON three-same encoding. */
19398 inst
.instruction
&= 0x00ffffff;
19399 inst
.instruction
|= high8
;
19400 /* Encode 'U' bit which indicates signedness. */
19401 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
19402 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
19403 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
19404 the instruction encoding. */
19405 if (inst
.operands
[2].isscalar
)
19407 inst
.instruction
&= 0xffffffd0;
19408 inst
.instruction
|= LOW4 (scalar_oprd2
);
19409 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
19413 /* Dot Product instructions for signed integer. */
19416 do_neon_dotproduct_s (void)
19418 return do_neon_dotproduct (0);
19421 /* Dot Product instructions for unsigned integer. */
19424 do_neon_dotproduct_u (void)
19426 return do_neon_dotproduct (1);
19429 /* Crypto v1 instructions. */
19431 do_crypto_2op_1 (unsigned elttype
, int op
)
19433 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19435 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
19441 NEON_ENCODE (INTEGER
, inst
);
19442 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19443 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19444 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19445 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19447 inst
.instruction
|= op
<< 6;
19450 inst
.instruction
|= 0xfc000000;
19452 inst
.instruction
|= 0xf0000000;
19456 do_crypto_3op_1 (int u
, int op
)
19458 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19460 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
19461 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
19466 NEON_ENCODE (INTEGER
, inst
);
19467 neon_three_same (1, u
, 8 << op
);
19473 do_crypto_2op_1 (N_8
, 0);
19479 do_crypto_2op_1 (N_8
, 1);
19485 do_crypto_2op_1 (N_8
, 2);
19491 do_crypto_2op_1 (N_8
, 3);
19497 do_crypto_3op_1 (0, 0);
19503 do_crypto_3op_1 (0, 1);
19509 do_crypto_3op_1 (0, 2);
19515 do_crypto_3op_1 (0, 3);
19521 do_crypto_3op_1 (1, 0);
19527 do_crypto_3op_1 (1, 1);
19531 do_sha256su1 (void)
19533 do_crypto_3op_1 (1, 2);
19539 do_crypto_2op_1 (N_32
, -1);
19545 do_crypto_2op_1 (N_32
, 0);
19549 do_sha256su0 (void)
19551 do_crypto_2op_1 (N_32
, 1);
19555 do_crc32_1 (unsigned int poly
, unsigned int sz
)
19557 unsigned int Rd
= inst
.operands
[0].reg
;
19558 unsigned int Rn
= inst
.operands
[1].reg
;
19559 unsigned int Rm
= inst
.operands
[2].reg
;
19561 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19562 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
19563 inst
.instruction
|= LOW4 (Rn
) << 16;
19564 inst
.instruction
|= LOW4 (Rm
);
19565 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
19566 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
19568 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
19569 as_warn (UNPRED_REG ("r15"));
19611 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19613 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
19614 do_vfp_sp_dp_cvt ();
19615 do_vfp_cond_or_thumb ();
19619 /* Overall per-instruction processing. */
19621 /* We need to be able to fix up arbitrary expressions in some statements.
19622 This is so that we can handle symbols that are an arbitrary distance from
19623 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
19624 which returns part of an address in a form which will be valid for
19625 a data instruction. We do this by pushing the expression into a symbol
19626 in the expr_section, and creating a fix for that. */
19629 fix_new_arm (fragS
* frag
,
19643 /* Create an absolute valued symbol, so we have something to
19644 refer to in the object file. Unfortunately for us, gas's
19645 generic expression parsing will already have folded out
19646 any use of .set foo/.type foo %function that may have
19647 been used to set type information of the target location,
19648 that's being specified symbolically. We have to presume
19649 the user knows what they are doing. */
19653 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
19655 symbol
= symbol_find_or_make (name
);
19656 S_SET_SEGMENT (symbol
, absolute_section
);
19657 symbol_set_frag (symbol
, &zero_address_frag
);
19658 S_SET_VALUE (symbol
, exp
->X_add_number
);
19659 exp
->X_op
= O_symbol
;
19660 exp
->X_add_symbol
= symbol
;
19661 exp
->X_add_number
= 0;
19667 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
19668 (enum bfd_reloc_code_real
) reloc
);
19672 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
19673 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
19677 /* Mark whether the fix is to a THUMB instruction, or an ARM
19679 new_fix
->tc_fix_data
= thumb_mode
;
19682 /* Create a frg for an instruction requiring relaxation. */
19684 output_relax_insn (void)
19690 /* The size of the instruction is unknown, so tie the debug info to the
19691 start of the instruction. */
19692 dwarf2_emit_insn (0);
19694 switch (inst
.relocs
[0].exp
.X_op
)
19697 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
19698 offset
= inst
.relocs
[0].exp
.X_add_number
;
19702 offset
= inst
.relocs
[0].exp
.X_add_number
;
19705 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
19709 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
19710 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
19711 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
19714 /* Write a 32-bit thumb instruction to buf. */
19716 put_thumb32_insn (char * buf
, unsigned long insn
)
19718 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
19719 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
19723 output_inst (const char * str
)
19729 as_bad ("%s -- `%s'", inst
.error
, str
);
19734 output_relax_insn ();
19737 if (inst
.size
== 0)
19740 to
= frag_more (inst
.size
);
19741 /* PR 9814: Record the thumb mode into the current frag so that we know
19742 what type of NOP padding to use, if necessary. We override any previous
19743 setting so that if the mode has changed then the NOPS that we use will
19744 match the encoding of the last instruction in the frag. */
19745 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19747 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
19749 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
19750 put_thumb32_insn (to
, inst
.instruction
);
19752 else if (inst
.size
> INSN_SIZE
)
19754 gas_assert (inst
.size
== (2 * INSN_SIZE
));
19755 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
19756 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
19759 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
19762 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
19764 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
19765 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
19766 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
19767 inst
.relocs
[r
].type
);
19770 dwarf2_emit_insn (inst
.size
);
19774 output_it_inst (int cond
, int mask
, char * to
)
19776 unsigned long instruction
= 0xbf00;
19779 instruction
|= mask
;
19780 instruction
|= cond
<< 4;
19784 to
= frag_more (2);
19786 dwarf2_emit_insn (2);
19790 md_number_to_chars (to
, instruction
, 2);
19795 /* Tag values used in struct asm_opcode's tag field. */
19798 OT_unconditional
, /* Instruction cannot be conditionalized.
19799 The ARM condition field is still 0xE. */
19800 OT_unconditionalF
, /* Instruction cannot be conditionalized
19801 and carries 0xF in its ARM condition field. */
19802 OT_csuffix
, /* Instruction takes a conditional suffix. */
19803 OT_csuffixF
, /* Some forms of the instruction take a scalar
19804 conditional suffix, others place 0xF where the
19805 condition field would be, others take a vector
19806 conditional suffix. */
19807 OT_cinfix3
, /* Instruction takes a conditional infix,
19808 beginning at character index 3. (In
19809 unified mode, it becomes a suffix.) */
19810 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
19811 tsts, cmps, cmns, and teqs. */
19812 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
19813 character index 3, even in unified mode. Used for
19814 legacy instructions where suffix and infix forms
19815 may be ambiguous. */
19816 OT_csuf_or_in3
, /* Instruction takes either a conditional
19817 suffix or an infix at character index 3. */
19818 OT_odd_infix_unc
, /* This is the unconditional variant of an
19819 instruction that takes a conditional infix
19820 at an unusual position. In unified mode,
19821 this variant will accept a suffix. */
19822 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
19823 are the conditional variants of instructions that
19824 take conditional infixes in unusual positions.
19825 The infix appears at character index
19826 (tag - OT_odd_infix_0). These are not accepted
19827 in unified mode. */
19830 /* Subroutine of md_assemble, responsible for looking up the primary
19831 opcode from the mnemonic the user wrote. STR points to the
19832 beginning of the mnemonic.
19834 This is not simply a hash table lookup, because of conditional
19835 variants. Most instructions have conditional variants, which are
19836 expressed with a _conditional affix_ to the mnemonic. If we were
19837 to encode each conditional variant as a literal string in the opcode
19838 table, it would have approximately 20,000 entries.
19840 Most mnemonics take this affix as a suffix, and in unified syntax,
19841 'most' is upgraded to 'all'. However, in the divided syntax, some
19842 instructions take the affix as an infix, notably the s-variants of
19843 the arithmetic instructions. Of those instructions, all but six
19844 have the infix appear after the third character of the mnemonic.
19846 Accordingly, the algorithm for looking up primary opcodes given
19849 1. Look up the identifier in the opcode table.
19850 If we find a match, go to step U.
19852 2. Look up the last two characters of the identifier in the
19853 conditions table. If we find a match, look up the first N-2
19854 characters of the identifier in the opcode table. If we
19855 find a match, go to step CE.
19857 3. Look up the fourth and fifth characters of the identifier in
19858 the conditions table. If we find a match, extract those
19859 characters from the identifier, and look up the remaining
19860 characters in the opcode table. If we find a match, go
19865 U. Examine the tag field of the opcode structure, in case this is
19866 one of the six instructions with its conditional infix in an
19867 unusual place. If it is, the tag tells us where to find the
19868 infix; look it up in the conditions table and set inst.cond
19869 accordingly. Otherwise, this is an unconditional instruction.
19870 Again set inst.cond accordingly. Return the opcode structure.
19872 CE. Examine the tag field to make sure this is an instruction that
19873 should receive a conditional suffix. If it is not, fail.
19874 Otherwise, set inst.cond from the suffix we already looked up,
19875 and return the opcode structure.
19877 CM. Examine the tag field to make sure this is an instruction that
19878 should receive a conditional infix after the third character.
19879 If it is not, fail. Otherwise, undo the edits to the current
19880 line of input and proceed as for case CE. */
19882 static const struct asm_opcode
*
19883 opcode_lookup (char **str
)
19887 const struct asm_opcode
*opcode
;
19888 const struct asm_cond
*cond
;
19891 /* Scan up to the end of the mnemonic, which must end in white space,
19892 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
19893 for (base
= end
= *str
; *end
!= '\0'; end
++)
19894 if (*end
== ' ' || *end
== '.')
19900 /* Handle a possible width suffix and/or Neon type suffix. */
19905 /* The .w and .n suffixes are only valid if the unified syntax is in
19907 if (unified_syntax
&& end
[1] == 'w')
19909 else if (unified_syntax
&& end
[1] == 'n')
19914 inst
.vectype
.elems
= 0;
19916 *str
= end
+ offset
;
19918 if (end
[offset
] == '.')
19920 /* See if we have a Neon type suffix (possible in either unified or
19921 non-unified ARM syntax mode). */
19922 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
19925 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
19931 /* Look for unaffixed or special-case affixed mnemonic. */
19932 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
19937 if (opcode
->tag
< OT_odd_infix_0
)
19939 inst
.cond
= COND_ALWAYS
;
19943 if (warn_on_deprecated
&& unified_syntax
)
19944 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
19945 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
19946 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
19949 inst
.cond
= cond
->value
;
19952 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19954 /* Cannot have a conditional suffix on a mnemonic of less than a character.
19956 if (end
- base
< 2)
19959 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
19960 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
19962 /* If this opcode can not be vector predicated then don't accept it with a
19963 vector predication code. */
19964 if (opcode
&& !opcode
->mayBeVecPred
)
19967 if (!opcode
|| !cond
)
19969 /* Cannot have a conditional suffix on a mnemonic of less than two
19971 if (end
- base
< 3)
19974 /* Look for suffixed mnemonic. */
19976 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
19977 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
19981 if (opcode
&& cond
)
19984 switch (opcode
->tag
)
19986 case OT_cinfix3_legacy
:
19987 /* Ignore conditional suffixes matched on infix only mnemonics. */
19991 case OT_cinfix3_deprecated
:
19992 case OT_odd_infix_unc
:
19993 if (!unified_syntax
)
19995 /* Fall through. */
19999 case OT_csuf_or_in3
:
20000 inst
.cond
= cond
->value
;
20003 case OT_unconditional
:
20004 case OT_unconditionalF
:
20006 inst
.cond
= cond
->value
;
20009 /* Delayed diagnostic. */
20010 inst
.error
= BAD_COND
;
20011 inst
.cond
= COND_ALWAYS
;
20020 /* Cannot have a usual-position infix on a mnemonic of less than
20021 six characters (five would be a suffix). */
20022 if (end
- base
< 6)
20025 /* Look for infixed mnemonic in the usual position. */
20027 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20031 memcpy (save
, affix
, 2);
20032 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
20033 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20035 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
20036 memcpy (affix
, save
, 2);
20039 && (opcode
->tag
== OT_cinfix3
20040 || opcode
->tag
== OT_cinfix3_deprecated
20041 || opcode
->tag
== OT_csuf_or_in3
20042 || opcode
->tag
== OT_cinfix3_legacy
))
20045 if (warn_on_deprecated
&& unified_syntax
20046 && (opcode
->tag
== OT_cinfix3
20047 || opcode
->tag
== OT_cinfix3_deprecated
))
20048 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20050 inst
.cond
= cond
->value
;
20057 /* This function generates an initial IT instruction, leaving its block
20058 virtually open for the new instructions. Eventually,
20059 the mask will be updated by now_pred_add_mask () each time
20060 a new instruction needs to be included in the IT block.
20061 Finally, the block is closed with close_automatic_it_block ().
20062 The block closure can be requested either from md_assemble (),
20063 a tencode (), or due to a label hook. */
20066 new_automatic_it_block (int cond
)
20068 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
20069 now_pred
.mask
= 0x18;
20070 now_pred
.cc
= cond
;
20071 now_pred
.block_length
= 1;
20072 mapping_state (MAP_THUMB
);
20073 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
20074 now_pred
.warn_deprecated
= FALSE
;
20075 now_pred
.insn_cond
= TRUE
;
20078 /* Close an automatic IT block.
20079 See comments in new_automatic_it_block (). */
20082 close_automatic_it_block (void)
20084 now_pred
.mask
= 0x10;
20085 now_pred
.block_length
= 0;
20088 /* Update the mask of the current automatically-generated IT
20089 instruction. See comments in new_automatic_it_block (). */
20092 now_pred_add_mask (int cond
)
20094 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
20095 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
20096 | ((bitvalue) << (nbit)))
20097 const int resulting_bit
= (cond
& 1);
20099 now_pred
.mask
&= 0xf;
20100 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
20102 (5 - now_pred
.block_length
));
20103 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
20105 ((5 - now_pred
.block_length
) - 1));
20106 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
20109 #undef SET_BIT_VALUE
20112 /* The IT blocks handling machinery is accessed through the these functions:
20113 it_fsm_pre_encode () from md_assemble ()
20114 set_pred_insn_type () optional, from the tencode functions
20115 set_pred_insn_type_last () ditto
20116 in_pred_block () ditto
20117 it_fsm_post_encode () from md_assemble ()
20118 force_automatic_it_block_close () from label handling functions
20121 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
20122 initializing the IT insn type with a generic initial value depending
20123 on the inst.condition.
20124 2) During the tencode function, two things may happen:
20125 a) The tencode function overrides the IT insn type by
20126 calling either set_pred_insn_type (type) or
20127 set_pred_insn_type_last ().
20128 b) The tencode function queries the IT block state by
20129 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
20131 Both set_pred_insn_type and in_pred_block run the internal FSM state
20132 handling function (handle_pred_state), because: a) setting the IT insn
20133 type may incur in an invalid state (exiting the function),
20134 and b) querying the state requires the FSM to be updated.
20135 Specifically we want to avoid creating an IT block for conditional
20136 branches, so it_fsm_pre_encode is actually a guess and we can't
20137 determine whether an IT block is required until the tencode () routine
20138 has decided what type of instruction this actually it.
20139 Because of this, if set_pred_insn_type and in_pred_block have to be
20140 used, set_pred_insn_type has to be called first.
20142 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
20143 that determines the insn IT type depending on the inst.cond code.
20144 When a tencode () routine encodes an instruction that can be
20145 either outside an IT block, or, in the case of being inside, has to be
20146 the last one, set_pred_insn_type_last () will determine the proper
20147 IT instruction type based on the inst.cond code. Otherwise,
20148 set_pred_insn_type can be called for overriding that logic or
20149 for covering other cases.
20151 Calling handle_pred_state () may not transition the IT block state to
20152 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
20153 still queried. Instead, if the FSM determines that the state should
20154 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
20155 after the tencode () function: that's what it_fsm_post_encode () does.
20157 Since in_pred_block () calls the state handling function to get an
20158 updated state, an error may occur (due to invalid insns combination).
20159 In that case, inst.error is set.
20160 Therefore, inst.error has to be checked after the execution of
20161 the tencode () routine.
20163 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
20164 any pending state change (if any) that didn't take place in
20165 handle_pred_state () as explained above. */
20168 it_fsm_pre_encode (void)
20170 if (inst
.cond
!= COND_ALWAYS
)
20171 inst
.pred_insn_type
= INSIDE_IT_INSN
;
20173 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
20175 now_pred
.state_handled
= 0;
20178 /* IT state FSM handling function. */
20179 /* MVE instructions and non-MVE instructions are handled differently because of
20180 the introduction of VPT blocks.
20181 Specifications say that any non-MVE instruction inside a VPT block is
20182 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
20183 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
20184 few exceptions we have MVE_UNPREDICABLE_INSN.
20185 The error messages provided depending on the different combinations possible
20186 are described in the cases below:
20187 For 'most' MVE instructions:
20188 1) In an IT block, with an IT code: syntax error
20189 2) In an IT block, with a VPT code: error: must be in a VPT block
20190 3) In an IT block, with no code: warning: UNPREDICTABLE
20191 4) In a VPT block, with an IT code: syntax error
20192 5) In a VPT block, with a VPT code: OK!
20193 6) In a VPT block, with no code: error: missing code
20194 7) Outside a pred block, with an IT code: error: syntax error
20195 8) Outside a pred block, with a VPT code: error: should be in a VPT block
20196 9) Outside a pred block, with no code: OK!
20197 For non-MVE instructions:
20198 10) In an IT block, with an IT code: OK!
20199 11) In an IT block, with a VPT code: syntax error
20200 12) In an IT block, with no code: error: missing code
20201 13) In a VPT block, with an IT code: error: should be in an IT block
20202 14) In a VPT block, with a VPT code: syntax error
20203 15) In a VPT block, with no code: UNPREDICTABLE
20204 16) Outside a pred block, with an IT code: error: should be in an IT block
20205 17) Outside a pred block, with a VPT code: syntax error
20206 18) Outside a pred block, with no code: OK!
20211 handle_pred_state (void)
20213 now_pred
.state_handled
= 1;
20214 now_pred
.insn_cond
= FALSE
;
20216 switch (now_pred
.state
)
20218 case OUTSIDE_PRED_BLOCK
:
20219 switch (inst
.pred_insn_type
)
20221 case MVE_UNPREDICABLE_INSN
:
20222 case MVE_OUTSIDE_PRED_INSN
:
20223 if (inst
.cond
< COND_ALWAYS
)
20225 /* Case 7: Outside a pred block, with an IT code: error: syntax
20227 inst
.error
= BAD_SYNTAX
;
20230 /* Case 9: Outside a pred block, with no code: OK! */
20232 case OUTSIDE_PRED_INSN
:
20233 if (inst
.cond
> COND_ALWAYS
)
20235 /* Case 17: Outside a pred block, with a VPT code: syntax error.
20237 inst
.error
= BAD_SYNTAX
;
20240 /* Case 18: Outside a pred block, with no code: OK! */
20243 case INSIDE_VPT_INSN
:
20244 /* Case 8: Outside a pred block, with a VPT code: error: should be in
20246 inst
.error
= BAD_OUT_VPT
;
20249 case INSIDE_IT_INSN
:
20250 case INSIDE_IT_LAST_INSN
:
20251 if (inst
.cond
< COND_ALWAYS
)
20253 /* Case 16: Outside a pred block, with an IT code: error: should
20254 be in an IT block. */
20255 if (thumb_mode
== 0)
20258 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
20259 as_tsktsk (_("Warning: conditional outside an IT block"\
20264 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
20265 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
20267 /* Automatically generate the IT instruction. */
20268 new_automatic_it_block (inst
.cond
);
20269 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
20270 close_automatic_it_block ();
20274 inst
.error
= BAD_OUT_IT
;
20280 else if (inst
.cond
> COND_ALWAYS
)
20282 /* Case 17: Outside a pred block, with a VPT code: syntax error.
20284 inst
.error
= BAD_SYNTAX
;
20289 case IF_INSIDE_IT_LAST_INSN
:
20290 case NEUTRAL_IT_INSN
:
20294 if (inst
.cond
!= COND_ALWAYS
)
20295 first_error (BAD_SYNTAX
);
20296 now_pred
.state
= MANUAL_PRED_BLOCK
;
20297 now_pred
.block_length
= 0;
20298 now_pred
.type
= VECTOR_PRED
;
20302 now_pred
.state
= MANUAL_PRED_BLOCK
;
20303 now_pred
.block_length
= 0;
20304 now_pred
.type
= SCALAR_PRED
;
20309 case AUTOMATIC_PRED_BLOCK
:
20310 /* Three things may happen now:
20311 a) We should increment current it block size;
20312 b) We should close current it block (closing insn or 4 insns);
20313 c) We should close current it block and start a new one (due
20314 to incompatible conditions or
20315 4 insns-length block reached). */
20317 switch (inst
.pred_insn_type
)
20319 case INSIDE_VPT_INSN
:
20321 case MVE_UNPREDICABLE_INSN
:
20322 case MVE_OUTSIDE_PRED_INSN
:
20324 case OUTSIDE_PRED_INSN
:
20325 /* The closure of the block shall happen immediately,
20326 so any in_pred_block () call reports the block as closed. */
20327 force_automatic_it_block_close ();
20330 case INSIDE_IT_INSN
:
20331 case INSIDE_IT_LAST_INSN
:
20332 case IF_INSIDE_IT_LAST_INSN
:
20333 now_pred
.block_length
++;
20335 if (now_pred
.block_length
> 4
20336 || !now_pred_compatible (inst
.cond
))
20338 force_automatic_it_block_close ();
20339 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
20340 new_automatic_it_block (inst
.cond
);
20344 now_pred
.insn_cond
= TRUE
;
20345 now_pred_add_mask (inst
.cond
);
20348 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
20349 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
20350 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
20351 close_automatic_it_block ();
20354 case NEUTRAL_IT_INSN
:
20355 now_pred
.block_length
++;
20356 now_pred
.insn_cond
= TRUE
;
20358 if (now_pred
.block_length
> 4)
20359 force_automatic_it_block_close ();
20361 now_pred_add_mask (now_pred
.cc
& 1);
20365 close_automatic_it_block ();
20366 now_pred
.state
= MANUAL_PRED_BLOCK
;
20371 case MANUAL_PRED_BLOCK
:
20374 if (now_pred
.type
== SCALAR_PRED
)
20376 /* Check conditional suffixes. */
20377 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
20378 now_pred
.mask
<<= 1;
20379 now_pred
.mask
&= 0x1f;
20380 is_last
= (now_pred
.mask
== 0x10);
20384 now_pred
.cc
^= (now_pred
.mask
>> 4);
20385 cond
= now_pred
.cc
+ 0xf;
20386 now_pred
.mask
<<= 1;
20387 now_pred
.mask
&= 0x1f;
20388 is_last
= now_pred
.mask
== 0x10;
20390 now_pred
.insn_cond
= TRUE
;
20392 switch (inst
.pred_insn_type
)
20394 case OUTSIDE_PRED_INSN
:
20395 if (now_pred
.type
== SCALAR_PRED
)
20397 if (inst
.cond
== COND_ALWAYS
)
20399 /* Case 12: In an IT block, with no code: error: missing
20401 inst
.error
= BAD_NOT_IT
;
20404 else if (inst
.cond
> COND_ALWAYS
)
20406 /* Case 11: In an IT block, with a VPT code: syntax error.
20408 inst
.error
= BAD_SYNTAX
;
20411 else if (thumb_mode
)
20413 /* This is for some special cases where a non-MVE
20414 instruction is not allowed in an IT block, such as cbz,
20415 but are put into one with a condition code.
20416 You could argue this should be a syntax error, but we
20417 gave the 'not allowed in IT block' diagnostic in the
20418 past so we will keep doing so. */
20419 inst
.error
= BAD_NOT_IT
;
20426 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
20427 as_tsktsk (MVE_NOT_VPT
);
20430 case MVE_OUTSIDE_PRED_INSN
:
20431 if (now_pred
.type
== SCALAR_PRED
)
20433 if (inst
.cond
== COND_ALWAYS
)
20435 /* Case 3: In an IT block, with no code: warning:
20437 as_tsktsk (MVE_NOT_IT
);
20440 else if (inst
.cond
< COND_ALWAYS
)
20442 /* Case 1: In an IT block, with an IT code: syntax error.
20444 inst
.error
= BAD_SYNTAX
;
20452 if (inst
.cond
< COND_ALWAYS
)
20454 /* Case 4: In a VPT block, with an IT code: syntax error.
20456 inst
.error
= BAD_SYNTAX
;
20459 else if (inst
.cond
== COND_ALWAYS
)
20461 /* Case 6: In a VPT block, with no code: error: missing
20463 inst
.error
= BAD_NOT_VPT
;
20471 case MVE_UNPREDICABLE_INSN
:
20472 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
20474 case INSIDE_IT_INSN
:
20475 if (inst
.cond
> COND_ALWAYS
)
20477 /* Case 11: In an IT block, with a VPT code: syntax error. */
20478 /* Case 14: In a VPT block, with a VPT code: syntax error. */
20479 inst
.error
= BAD_SYNTAX
;
20482 else if (now_pred
.type
== SCALAR_PRED
)
20484 /* Case 10: In an IT block, with an IT code: OK! */
20485 if (cond
!= inst
.cond
)
20487 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
20494 /* Case 13: In a VPT block, with an IT code: error: should be
20496 inst
.error
= BAD_OUT_IT
;
20501 case INSIDE_VPT_INSN
:
20502 if (now_pred
.type
== SCALAR_PRED
)
20504 /* Case 2: In an IT block, with a VPT code: error: must be in a
20506 inst
.error
= BAD_OUT_VPT
;
20509 /* Case 5: In a VPT block, with a VPT code: OK! */
20510 else if (cond
!= inst
.cond
)
20512 inst
.error
= BAD_VPT_COND
;
20516 case INSIDE_IT_LAST_INSN
:
20517 case IF_INSIDE_IT_LAST_INSN
:
20518 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
20520 /* Case 4: In a VPT block, with an IT code: syntax error. */
20521 /* Case 11: In an IT block, with a VPT code: syntax error. */
20522 inst
.error
= BAD_SYNTAX
;
20525 else if (cond
!= inst
.cond
)
20527 inst
.error
= BAD_IT_COND
;
20532 inst
.error
= BAD_BRANCH
;
20537 case NEUTRAL_IT_INSN
:
20538 /* The BKPT instruction is unconditional even in a IT or VPT
20543 if (now_pred
.type
== SCALAR_PRED
)
20545 inst
.error
= BAD_IT_IT
;
20548 /* fall through. */
20550 if (inst
.cond
== COND_ALWAYS
)
20552 /* Executing a VPT/VPST instruction inside an IT block or a
20553 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
20555 if (now_pred
.type
== SCALAR_PRED
)
20556 as_tsktsk (MVE_NOT_IT
);
20558 as_tsktsk (MVE_NOT_VPT
);
20563 /* VPT/VPST do not accept condition codes. */
20564 inst
.error
= BAD_SYNTAX
;
20575 struct depr_insn_mask
20577 unsigned long pattern
;
20578 unsigned long mask
;
20579 const char* description
;
20582 /* List of 16-bit instruction patterns deprecated in an IT block in
20584 static const struct depr_insn_mask depr_it_insns
[] = {
20585 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
20586 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
20587 { 0xa000, 0xb800, N_("ADR") },
20588 { 0x4800, 0xf800, N_("Literal loads") },
20589 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
20590 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
20591 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
20592 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
20593 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
20598 it_fsm_post_encode (void)
20602 if (!now_pred
.state_handled
)
20603 handle_pred_state ();
20605 if (now_pred
.insn_cond
20606 && !now_pred
.warn_deprecated
20607 && warn_on_deprecated
20608 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
20609 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
20611 if (inst
.instruction
>= 0x10000)
20613 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
20614 "performance deprecated in ARMv8-A and ARMv8-R"));
20615 now_pred
.warn_deprecated
= TRUE
;
20619 const struct depr_insn_mask
*p
= depr_it_insns
;
20621 while (p
->mask
!= 0)
20623 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
20625 as_tsktsk (_("IT blocks containing 16-bit Thumb "
20626 "instructions of the following class are "
20627 "performance deprecated in ARMv8-A and "
20628 "ARMv8-R: %s"), p
->description
);
20629 now_pred
.warn_deprecated
= TRUE
;
20637 if (now_pred
.block_length
> 1)
20639 as_tsktsk (_("IT blocks containing more than one conditional "
20640 "instruction are performance deprecated in ARMv8-A and "
20642 now_pred
.warn_deprecated
= TRUE
;
20646 is_last
= (now_pred
.mask
== 0x10);
20649 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
20655 force_automatic_it_block_close (void)
20657 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
20659 close_automatic_it_block ();
20660 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
20666 in_pred_block (void)
20668 if (!now_pred
.state_handled
)
20669 handle_pred_state ();
20671 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
20674 /* Whether OPCODE only has T32 encoding. Since this function is only used by
20675 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
20676 here, hence the "known" in the function name. */
20679 known_t32_only_insn (const struct asm_opcode
*opcode
)
20681 /* Original Thumb-1 wide instruction. */
20682 if (opcode
->tencode
== do_t_blx
20683 || opcode
->tencode
== do_t_branch23
20684 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
20685 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
20688 /* Wide-only instruction added to ARMv8-M Baseline. */
20689 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
20690 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
20691 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
20692 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
20698 /* Whether wide instruction variant can be used if available for a valid OPCODE
20702 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
20704 if (known_t32_only_insn (opcode
))
20707 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
20708 of variant T3 of B.W is checked in do_t_branch. */
20709 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
20710 && opcode
->tencode
== do_t_branch
)
20713 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
20714 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
20715 && opcode
->tencode
== do_t_mov_cmp
20716 /* Make sure CMP instruction is not affected. */
20717 && opcode
->aencode
== do_mov
)
20720 /* Wide instruction variants of all instructions with narrow *and* wide
20721 variants become available with ARMv6t2. Other opcodes are either
20722 narrow-only or wide-only and are thus available if OPCODE is valid. */
20723 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
20726 /* OPCODE with narrow only instruction variant or wide variant not
20732 md_assemble (char *str
)
20735 const struct asm_opcode
* opcode
;
20737 /* Align the previous label if needed. */
20738 if (last_label_seen
!= NULL
)
20740 symbol_set_frag (last_label_seen
, frag_now
);
20741 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
20742 S_SET_SEGMENT (last_label_seen
, now_seg
);
20745 memset (&inst
, '\0', sizeof (inst
));
20747 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
20748 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
20750 opcode
= opcode_lookup (&p
);
20753 /* It wasn't an instruction, but it might be a register alias of
20754 the form alias .req reg, or a Neon .dn/.qn directive. */
20755 if (! create_register_alias (str
, p
)
20756 && ! create_neon_reg_alias (str
, p
))
20757 as_bad (_("bad instruction `%s'"), str
);
20762 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
20763 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
20765 /* The value which unconditional instructions should have in place of the
20766 condition field. */
20767 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
20771 arm_feature_set variant
;
20773 variant
= cpu_variant
;
20774 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
20775 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
20776 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
20777 /* Check that this instruction is supported for this CPU. */
20778 if (!opcode
->tvariant
20779 || (thumb_mode
== 1
20780 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
20782 if (opcode
->tencode
== do_t_swi
)
20783 as_bad (_("SVC is not permitted on this architecture"));
20785 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
20788 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
20789 && opcode
->tencode
!= do_t_branch
)
20791 as_bad (_("Thumb does not support conditional execution"));
20795 /* Two things are addressed here:
20796 1) Implicit require narrow instructions on Thumb-1.
20797 This avoids relaxation accidentally introducing Thumb-2
20799 2) Reject wide instructions in non Thumb-2 cores.
20801 Only instructions with narrow and wide variants need to be handled
20802 but selecting all non wide-only instructions is easier. */
20803 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
20804 && !t32_insn_ok (variant
, opcode
))
20806 if (inst
.size_req
== 0)
20808 else if (inst
.size_req
== 4)
20810 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
20811 as_bad (_("selected processor does not support 32bit wide "
20812 "variant of instruction `%s'"), str
);
20814 as_bad (_("selected processor does not support `%s' in "
20815 "Thumb-2 mode"), str
);
20820 inst
.instruction
= opcode
->tvalue
;
20822 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
20824 /* Prepare the pred_insn_type for those encodings that don't set
20826 it_fsm_pre_encode ();
20828 opcode
->tencode ();
20830 it_fsm_post_encode ();
20833 if (!(inst
.error
|| inst
.relax
))
20835 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
20836 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
20837 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
20839 as_bad (_("cannot honor width suffix -- `%s'"), str
);
20844 /* Something has gone badly wrong if we try to relax a fixed size
20846 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
20848 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
20849 *opcode
->tvariant
);
20850 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
20851 set those bits when Thumb-2 32-bit instructions are seen. The impact
20852 of relaxable instructions will be considered later after we finish all
20854 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
20855 variant
= arm_arch_none
;
20857 variant
= cpu_variant
;
20858 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
20859 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
20862 check_neon_suffixes
;
20866 mapping_state (MAP_THUMB
);
20869 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
20873 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
20874 is_bx
= (opcode
->aencode
== do_bx
);
20876 /* Check that this instruction is supported for this CPU. */
20877 if (!(is_bx
&& fix_v4bx
)
20878 && !(opcode
->avariant
&&
20879 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
20881 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
20886 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
20890 inst
.instruction
= opcode
->avalue
;
20891 if (opcode
->tag
== OT_unconditionalF
)
20892 inst
.instruction
|= 0xFU
<< 28;
20894 inst
.instruction
|= inst
.cond
<< 28;
20895 inst
.size
= INSN_SIZE
;
20896 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
20898 it_fsm_pre_encode ();
20899 opcode
->aencode ();
20900 it_fsm_post_encode ();
20902 /* Arm mode bx is marked as both v4T and v5 because it's still required
20903 on a hypothetical non-thumb v5 core. */
20905 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
20907 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
20908 *opcode
->avariant
);
20910 check_neon_suffixes
;
20914 mapping_state (MAP_ARM
);
20919 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
20927 check_pred_blocks_finished (void)
20932 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
20933 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
20934 == MANUAL_PRED_BLOCK
)
20936 if (now_pred
.type
== SCALAR_PRED
)
20937 as_warn (_("section '%s' finished with an open IT block."),
20940 as_warn (_("section '%s' finished with an open VPT/VPST block."),
20944 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
20946 if (now_pred
.type
== SCALAR_PRED
)
20947 as_warn (_("file finished with an open IT block."));
20949 as_warn (_("file finished with an open VPT/VPST block."));
20954 /* Various frobbings of labels and their addresses. */
20957 arm_start_line_hook (void)
20959 last_label_seen
= NULL
;
20963 arm_frob_label (symbolS
* sym
)
20965 last_label_seen
= sym
;
20967 ARM_SET_THUMB (sym
, thumb_mode
);
20969 #if defined OBJ_COFF || defined OBJ_ELF
20970 ARM_SET_INTERWORK (sym
, support_interwork
);
20973 force_automatic_it_block_close ();
20975 /* Note - do not allow local symbols (.Lxxx) to be labelled
20976 as Thumb functions. This is because these labels, whilst
20977 they exist inside Thumb code, are not the entry points for
20978 possible ARM->Thumb calls. Also, these labels can be used
20979 as part of a computed goto or switch statement. eg gcc
20980 can generate code that looks like this:
20982 ldr r2, [pc, .Laaa]
20992 The first instruction loads the address of the jump table.
20993 The second instruction converts a table index into a byte offset.
20994 The third instruction gets the jump address out of the table.
20995 The fourth instruction performs the jump.
20997 If the address stored at .Laaa is that of a symbol which has the
20998 Thumb_Func bit set, then the linker will arrange for this address
20999 to have the bottom bit set, which in turn would mean that the
21000 address computation performed by the third instruction would end
21001 up with the bottom bit set. Since the ARM is capable of unaligned
21002 word loads, the instruction would then load the incorrect address
21003 out of the jump table, and chaos would ensue. */
21004 if (label_is_thumb_function_name
21005 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
21006 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
21008 /* When the address of a Thumb function is taken the bottom
21009 bit of that address should be set. This will allow
21010 interworking between Arm and Thumb functions to work
21013 THUMB_SET_FUNC (sym
, 1);
21015 label_is_thumb_function_name
= FALSE
;
21018 dwarf2_emit_label (sym
);
21022 arm_data_in_code (void)
21024 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
21026 *input_line_pointer
= '/';
21027 input_line_pointer
+= 5;
21028 *input_line_pointer
= 0;
21036 arm_canonicalize_symbol_name (char * name
)
21040 if (thumb_mode
&& (len
= strlen (name
)) > 5
21041 && streq (name
+ len
- 5, "/data"))
21042 *(name
+ len
- 5) = 0;
21047 /* Table of all register names defined by default. The user can
21048 define additional names with .req. Note that all register names
21049 should appear in both upper and lowercase variants. Some registers
21050 also have mixed-case names. */
21052 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
21053 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
21054 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
21055 #define REGSET(p,t) \
21056 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
21057 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
21058 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
21059 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
21060 #define REGSETH(p,t) \
21061 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
21062 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
21063 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
21064 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
21065 #define REGSET2(p,t) \
21066 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
21067 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
21068 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
21069 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
21070 #define SPLRBANK(base,bank,t) \
21071 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
21072 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
21073 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
21074 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
21075 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
21076 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
21078 static const struct reg_entry reg_names
[] =
21080 /* ARM integer registers. */
21081 REGSET(r
, RN
), REGSET(R
, RN
),
21083 /* ATPCS synonyms. */
21084 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
21085 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
21086 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
21088 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
21089 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
21090 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
21092 /* Well-known aliases. */
21093 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
21094 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
21096 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
21097 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
21099 /* Coprocessor numbers. */
21100 REGSET(p
, CP
), REGSET(P
, CP
),
21102 /* Coprocessor register numbers. The "cr" variants are for backward
21104 REGSET(c
, CN
), REGSET(C
, CN
),
21105 REGSET(cr
, CN
), REGSET(CR
, CN
),
21107 /* ARM banked registers. */
21108 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
21109 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
21110 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
21111 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
21112 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
21113 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
21114 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
21116 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
21117 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
21118 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
21119 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
21120 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
21121 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
21122 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
21123 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
21125 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
21126 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
21127 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
21128 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
21129 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
21130 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
21131 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
21132 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
21133 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
21135 /* FPA registers. */
21136 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
21137 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
21139 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
21140 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
21142 /* VFP SP registers. */
21143 REGSET(s
,VFS
), REGSET(S
,VFS
),
21144 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
21146 /* VFP DP Registers. */
21147 REGSET(d
,VFD
), REGSET(D
,VFD
),
21148 /* Extra Neon DP registers. */
21149 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
21151 /* Neon QP registers. */
21152 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
21154 /* VFP control registers. */
21155 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
21156 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
21157 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
21158 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
21159 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
21160 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
21161 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
21163 /* Maverick DSP coprocessor registers. */
21164 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
21165 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
21167 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
21168 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
21169 REGDEF(dspsc
,0,DSPSC
),
21171 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
21172 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
21173 REGDEF(DSPSC
,0,DSPSC
),
21175 /* iWMMXt data registers - p0, c0-15. */
21176 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
21178 /* iWMMXt control registers - p1, c0-3. */
21179 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
21180 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
21181 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
21182 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
21184 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
21185 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
21186 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
21187 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
21188 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
21190 /* XScale accumulator registers. */
21191 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
21197 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
21198 within psr_required_here. */
21199 static const struct asm_psr psrs
[] =
21201 /* Backward compatibility notation. Note that "all" is no longer
21202 truly all possible PSR bits. */
21203 {"all", PSR_c
| PSR_f
},
21207 /* Individual flags. */
21213 /* Combinations of flags. */
21214 {"fs", PSR_f
| PSR_s
},
21215 {"fx", PSR_f
| PSR_x
},
21216 {"fc", PSR_f
| PSR_c
},
21217 {"sf", PSR_s
| PSR_f
},
21218 {"sx", PSR_s
| PSR_x
},
21219 {"sc", PSR_s
| PSR_c
},
21220 {"xf", PSR_x
| PSR_f
},
21221 {"xs", PSR_x
| PSR_s
},
21222 {"xc", PSR_x
| PSR_c
},
21223 {"cf", PSR_c
| PSR_f
},
21224 {"cs", PSR_c
| PSR_s
},
21225 {"cx", PSR_c
| PSR_x
},
21226 {"fsx", PSR_f
| PSR_s
| PSR_x
},
21227 {"fsc", PSR_f
| PSR_s
| PSR_c
},
21228 {"fxs", PSR_f
| PSR_x
| PSR_s
},
21229 {"fxc", PSR_f
| PSR_x
| PSR_c
},
21230 {"fcs", PSR_f
| PSR_c
| PSR_s
},
21231 {"fcx", PSR_f
| PSR_c
| PSR_x
},
21232 {"sfx", PSR_s
| PSR_f
| PSR_x
},
21233 {"sfc", PSR_s
| PSR_f
| PSR_c
},
21234 {"sxf", PSR_s
| PSR_x
| PSR_f
},
21235 {"sxc", PSR_s
| PSR_x
| PSR_c
},
21236 {"scf", PSR_s
| PSR_c
| PSR_f
},
21237 {"scx", PSR_s
| PSR_c
| PSR_x
},
21238 {"xfs", PSR_x
| PSR_f
| PSR_s
},
21239 {"xfc", PSR_x
| PSR_f
| PSR_c
},
21240 {"xsf", PSR_x
| PSR_s
| PSR_f
},
21241 {"xsc", PSR_x
| PSR_s
| PSR_c
},
21242 {"xcf", PSR_x
| PSR_c
| PSR_f
},
21243 {"xcs", PSR_x
| PSR_c
| PSR_s
},
21244 {"cfs", PSR_c
| PSR_f
| PSR_s
},
21245 {"cfx", PSR_c
| PSR_f
| PSR_x
},
21246 {"csf", PSR_c
| PSR_s
| PSR_f
},
21247 {"csx", PSR_c
| PSR_s
| PSR_x
},
21248 {"cxf", PSR_c
| PSR_x
| PSR_f
},
21249 {"cxs", PSR_c
| PSR_x
| PSR_s
},
21250 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
21251 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
21252 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
21253 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
21254 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
21255 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
21256 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
21257 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
21258 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
21259 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
21260 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
21261 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
21262 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
21263 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
21264 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
21265 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
21266 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
21267 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
21268 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
21269 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
21270 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
21271 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
21272 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
21273 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
21276 /* Table of V7M psr names. */
21277 static const struct asm_psr v7m_psrs
[] =
21279 {"apsr", 0x0 }, {"APSR", 0x0 },
21280 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
21281 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
21282 {"psr", 0x3 }, {"PSR", 0x3 },
21283 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
21284 {"ipsr", 0x5 }, {"IPSR", 0x5 },
21285 {"epsr", 0x6 }, {"EPSR", 0x6 },
21286 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
21287 {"msp", 0x8 }, {"MSP", 0x8 },
21288 {"psp", 0x9 }, {"PSP", 0x9 },
21289 {"msplim", 0xa }, {"MSPLIM", 0xa },
21290 {"psplim", 0xb }, {"PSPLIM", 0xb },
21291 {"primask", 0x10}, {"PRIMASK", 0x10},
21292 {"basepri", 0x11}, {"BASEPRI", 0x11},
21293 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
21294 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
21295 {"control", 0x14}, {"CONTROL", 0x14},
21296 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
21297 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
21298 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
21299 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
21300 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
21301 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
21302 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
21303 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
21304 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
21307 /* Table of all shift-in-operand names. */
21308 static const struct asm_shift_name shift_names
[] =
21310 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
21311 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
21312 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
21313 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
21314 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
21315 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
21316 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
21319 /* Table of all explicit relocation names. */
21321 static struct reloc_entry reloc_names
[] =
21323 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
21324 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
21325 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
21326 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
21327 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
21328 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
21329 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
21330 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
21331 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
21332 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
21333 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
21334 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
21335 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
21336 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
21337 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
21338 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
21339 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
21340 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
21341 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
21342 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
21343 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
21344 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
21345 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
21346 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
21347 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
21348 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
21349 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
21353 /* Table of all conditional affixes. */
21354 static const struct asm_cond conds
[] =
21358 {"cs", 0x2}, {"hs", 0x2},
21359 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
21372 static const struct asm_cond vconds
[] =
21378 #define UL_BARRIER(L,U,CODE,FEAT) \
21379 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
21380 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
21382 static struct asm_barrier_opt barrier_opt_names
[] =
21384 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
21385 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
21386 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
21387 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
21388 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
21389 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
21390 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
21391 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
21392 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
21393 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
21394 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
21395 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
21396 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
21397 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
21398 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
21399 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
21404 /* Table of ARM-format instructions. */
21406 /* Macros for gluing together operand strings. N.B. In all cases
21407 other than OPS0, the trailing OP_stop comes from default
21408 zero-initialization of the unspecified elements of the array. */
21409 #define OPS0() { OP_stop, }
21410 #define OPS1(a) { OP_##a, }
21411 #define OPS2(a,b) { OP_##a,OP_##b, }
21412 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
21413 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
21414 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
21415 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
21417 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
21418 This is useful when mixing operands for ARM and THUMB, i.e. using the
21419 MIX_ARM_THUMB_OPERANDS macro.
21420 In order to use these macros, prefix the number of operands with _
21422 #define OPS_1(a) { a, }
21423 #define OPS_2(a,b) { a,b, }
21424 #define OPS_3(a,b,c) { a,b,c, }
21425 #define OPS_4(a,b,c,d) { a,b,c,d, }
21426 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
21427 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
21429 /* These macros abstract out the exact format of the mnemonic table and
21430 save some repeated characters. */
21432 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
21433 #define TxCE(mnem, op, top, nops, ops, ae, te) \
21434 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
21435 THUMB_VARIANT, do_##ae, do_##te, 0 }
21437 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
21438 a T_MNEM_xyz enumerator. */
21439 #define TCE(mnem, aop, top, nops, ops, ae, te) \
21440 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
21441 #define tCE(mnem, aop, top, nops, ops, ae, te) \
21442 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
21444 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
21445 infix after the third character. */
21446 #define TxC3(mnem, op, top, nops, ops, ae, te) \
21447 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
21448 THUMB_VARIANT, do_##ae, do_##te, 0 }
21449 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
21450 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
21451 THUMB_VARIANT, do_##ae, do_##te, 0 }
21452 #define TC3(mnem, aop, top, nops, ops, ae, te) \
21453 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
21454 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
21455 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
21456 #define tC3(mnem, aop, top, nops, ops, ae, te) \
21457 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
21458 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
21459 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
21461 /* Mnemonic that cannot be conditionalized. The ARM condition-code
21462 field is still 0xE. Many of the Thumb variants can be executed
21463 conditionally, so this is checked separately. */
21464 #define TUE(mnem, op, top, nops, ops, ae, te) \
21465 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
21466 THUMB_VARIANT, do_##ae, do_##te, 0 }
21468 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
21469 Used by mnemonics that have very minimal differences in the encoding for
21470 ARM and Thumb variants and can be handled in a common function. */
21471 #define TUEc(mnem, op, top, nops, ops, en) \
21472 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
21473 THUMB_VARIANT, do_##en, do_##en, 0 }
21475 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
21476 condition code field. */
21477 #define TUF(mnem, op, top, nops, ops, ae, te) \
21478 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
21479 THUMB_VARIANT, do_##ae, do_##te, 0 }
21481 /* ARM-only variants of all the above. */
21482 #define CE(mnem, op, nops, ops, ae) \
21483 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21485 #define C3(mnem, op, nops, ops, ae) \
21486 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21488 /* Thumb-only variants of TCE and TUE. */
21489 #define ToC(mnem, top, nops, ops, te) \
21490 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
21493 #define ToU(mnem, top, nops, ops, te) \
21494 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
21497 /* T_MNEM_xyz enumerator variants of ToC. */
21498 #define toC(mnem, top, nops, ops, te) \
21499 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
21502 /* T_MNEM_xyz enumerator variants of ToU. */
21503 #define toU(mnem, top, nops, ops, te) \
21504 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
21507 /* Legacy mnemonics that always have conditional infix after the third
21509 #define CL(mnem, op, nops, ops, ae) \
21510 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
21511 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21513 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
21514 #define cCE(mnem, op, nops, ops, ae) \
21515 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
21517 /* mov instructions that are shared between coprocessor and MVE. */
21518 #define mcCE(mnem, op, nops, ops, ae) \
21519 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
21521 /* Legacy coprocessor instructions where conditional infix and conditional
21522 suffix are ambiguous. For consistency this includes all FPA instructions,
21523 not just the potentially ambiguous ones. */
21524 #define cCL(mnem, op, nops, ops, ae) \
21525 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
21526 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
21528 /* Coprocessor, takes either a suffix or a position-3 infix
21529 (for an FPA corner case). */
21530 #define C3E(mnem, op, nops, ops, ae) \
21531 { mnem, OPS##nops ops, OT_csuf_or_in3, \
21532 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
21534 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
21535 { m1 #m2 m3, OPS##nops ops, \
21536 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
21537 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21539 #define CM(m1, m2, op, nops, ops, ae) \
21540 xCM_ (m1, , m2, op, nops, ops, ae), \
21541 xCM_ (m1, eq, m2, op, nops, ops, ae), \
21542 xCM_ (m1, ne, m2, op, nops, ops, ae), \
21543 xCM_ (m1, cs, m2, op, nops, ops, ae), \
21544 xCM_ (m1, hs, m2, op, nops, ops, ae), \
21545 xCM_ (m1, cc, m2, op, nops, ops, ae), \
21546 xCM_ (m1, ul, m2, op, nops, ops, ae), \
21547 xCM_ (m1, lo, m2, op, nops, ops, ae), \
21548 xCM_ (m1, mi, m2, op, nops, ops, ae), \
21549 xCM_ (m1, pl, m2, op, nops, ops, ae), \
21550 xCM_ (m1, vs, m2, op, nops, ops, ae), \
21551 xCM_ (m1, vc, m2, op, nops, ops, ae), \
21552 xCM_ (m1, hi, m2, op, nops, ops, ae), \
21553 xCM_ (m1, ls, m2, op, nops, ops, ae), \
21554 xCM_ (m1, ge, m2, op, nops, ops, ae), \
21555 xCM_ (m1, lt, m2, op, nops, ops, ae), \
21556 xCM_ (m1, gt, m2, op, nops, ops, ae), \
21557 xCM_ (m1, le, m2, op, nops, ops, ae), \
21558 xCM_ (m1, al, m2, op, nops, ops, ae)
21560 #define UE(mnem, op, nops, ops, ae) \
21561 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21563 #define UF(mnem, op, nops, ops, ae) \
21564 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21566 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
21567 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
21568 use the same encoding function for each. */
21569 #define NUF(mnem, op, nops, ops, enc) \
21570 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
21571 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
21573 /* Neon data processing, version which indirects through neon_enc_tab for
21574 the various overloaded versions of opcodes. */
21575 #define nUF(mnem, op, nops, ops, enc) \
21576 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
21577 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
21579 /* Neon insn with conditional suffix for the ARM version, non-overloaded
21581 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
21582 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
21583 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
21585 #define NCE(mnem, op, nops, ops, enc) \
21586 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
21588 #define NCEF(mnem, op, nops, ops, enc) \
21589 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
21591 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
21592 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
21593 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
21594 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
21596 #define nCE(mnem, op, nops, ops, enc) \
21597 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
21599 #define nCEF(mnem, op, nops, ops, enc) \
21600 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
21603 #define mCEF(mnem, op, nops, ops, enc) \
21604 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
21605 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
21608 /* nCEF but for MVE predicated instructions. */
21609 #define mnCEF(mnem, op, nops, ops, enc) \
21610 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
21612 /* nCE but for MVE predicated instructions. */
21613 #define mnCE(mnem, op, nops, ops, enc) \
21614 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
21616 /* NUF but for potentially MVE predicated instructions. */
21617 #define MNUF(mnem, op, nops, ops, enc) \
21618 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
21619 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
21621 /* nUF but for potentially MVE predicated instructions. */
21622 #define mnUF(mnem, op, nops, ops, enc) \
21623 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
21624 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
21626 /* ToC but for potentially MVE predicated instructions. */
21627 #define mToC(mnem, top, nops, ops, te) \
21628 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
21631 /* NCE but for MVE predicated instructions. */
21632 #define MNCE(mnem, op, nops, ops, enc) \
21633 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
21635 /* NCEF but for MVE predicated instructions. */
21636 #define MNCEF(mnem, op, nops, ops, enc) \
21637 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
21640 static const struct asm_opcode insns
[] =
21642 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
21643 #define THUMB_VARIANT & arm_ext_v4t
21644 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21645 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21646 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21647 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21648 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
21649 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
21650 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
21651 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
21652 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21653 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21654 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
21655 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
21656 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21657 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21658 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
21659 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
21661 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
21662 for setting PSR flag bits. They are obsolete in V6 and do not
21663 have Thumb equivalents. */
21664 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
21665 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
21666 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
21667 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
21668 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
21669 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
21670 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
21671 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
21672 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
21674 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
21675 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
21676 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
21677 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
21679 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
21680 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
21681 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
21683 OP_ADDRGLDR
),ldst
, t_ldst
),
21684 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
21686 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21687 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21688 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21689 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21690 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21691 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21693 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
21694 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
21697 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
21698 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
21699 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
21700 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
21702 /* Thumb-compatibility pseudo ops. */
21703 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21704 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21705 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21706 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21707 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21708 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21709 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21710 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21711 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
21712 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
21713 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
21714 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
21716 /* These may simplify to neg. */
21717 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
21718 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
21720 #undef THUMB_VARIANT
21721 #define THUMB_VARIANT & arm_ext_os
21723 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
21724 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
21726 #undef THUMB_VARIANT
21727 #define THUMB_VARIANT & arm_ext_v6
21729 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
21731 /* V1 instructions with no Thumb analogue prior to V6T2. */
21732 #undef THUMB_VARIANT
21733 #define THUMB_VARIANT & arm_ext_v6t2
21735 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
21736 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
21737 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
21739 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
21740 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
21741 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
21742 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
21744 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21745 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21747 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21748 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21750 /* V1 instructions with no Thumb analogue at all. */
21751 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
21752 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
21754 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
21755 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
21756 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
21757 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
21758 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
21759 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
21760 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
21761 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
21764 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
21765 #undef THUMB_VARIANT
21766 #define THUMB_VARIANT & arm_ext_v4t
21768 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
21769 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
21771 #undef THUMB_VARIANT
21772 #define THUMB_VARIANT & arm_ext_v6t2
21774 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
21775 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
21777 /* Generic coprocessor instructions. */
21778 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
21779 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
21780 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
21781 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
21782 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
21783 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
21784 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
21787 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
21789 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
21790 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
21793 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
21794 #undef THUMB_VARIANT
21795 #define THUMB_VARIANT & arm_ext_msr
21797 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
21798 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
21801 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
21802 #undef THUMB_VARIANT
21803 #define THUMB_VARIANT & arm_ext_v6t2
21805 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
21806 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
21807 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
21808 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
21809 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
21810 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
21811 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
21812 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
21815 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
21816 #undef THUMB_VARIANT
21817 #define THUMB_VARIANT & arm_ext_v4t
21819 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
21820 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
21821 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
21822 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
21823 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
21824 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
21827 #define ARM_VARIANT & arm_ext_v4t_5
21829 /* ARM Architecture 4T. */
21830 /* Note: bx (and blx) are required on V5, even if the processor does
21831 not support Thumb. */
21832 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
21835 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
21836 #undef THUMB_VARIANT
21837 #define THUMB_VARIANT & arm_ext_v5t
21839 /* Note: blx has 2 variants; the .value coded here is for
21840 BLX(2). Only this variant has conditional execution. */
21841 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
21842 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
21844 #undef THUMB_VARIANT
21845 #define THUMB_VARIANT & arm_ext_v6t2
21847 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
21848 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
21849 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
21850 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
21851 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
21852 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
21853 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
21854 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
21857 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
21858 #undef THUMB_VARIANT
21859 #define THUMB_VARIANT & arm_ext_v5exp
21861 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
21862 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
21863 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
21864 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
21866 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
21867 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
21869 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
21870 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
21871 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
21872 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
21874 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
21875 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
21876 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
21877 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
21879 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
21880 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
21882 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
21883 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
21884 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
21885 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
21888 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
21889 #undef THUMB_VARIANT
21890 #define THUMB_VARIANT & arm_ext_v6t2
21892 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
21893 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
21895 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
21896 ADDRGLDRS
), ldrd
, t_ldstd
),
21898 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
21899 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
21902 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
21904 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
21907 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
21908 #undef THUMB_VARIANT
21909 #define THUMB_VARIANT & arm_ext_v6
21911 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
21912 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
21913 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
21914 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
21915 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
21916 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
21917 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
21918 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
21919 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
21920 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
21922 #undef THUMB_VARIANT
21923 #define THUMB_VARIANT & arm_ext_v6t2_v8m
21925 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
21926 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
21928 #undef THUMB_VARIANT
21929 #define THUMB_VARIANT & arm_ext_v6t2
21931 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
21932 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
21934 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
21935 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
21937 /* ARM V6 not included in V7M. */
21938 #undef THUMB_VARIANT
21939 #define THUMB_VARIANT & arm_ext_v6_notm
21940 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
21941 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
21942 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
21943 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
21944 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
21945 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
21946 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
21947 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
21948 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
21949 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
21950 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
21951 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
21952 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
21953 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
21954 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
21955 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
21956 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
21957 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
21958 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
21960 /* ARM V6 not included in V7M (eg. integer SIMD). */
21961 #undef THUMB_VARIANT
21962 #define THUMB_VARIANT & arm_ext_v6_dsp
21963 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
21964 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
21965 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21966 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21967 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21968 /* Old name for QASX. */
21969 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21970 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21971 /* Old name for QSAX. */
21972 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21973 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21974 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21975 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21976 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21977 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21978 /* Old name for SASX. */
21979 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21980 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21981 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21982 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21983 /* Old name for SHASX. */
21984 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21985 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21986 /* Old name for SHSAX. */
21987 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21988 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21989 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21990 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21991 /* Old name for SSAX. */
21992 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21993 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21994 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21995 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21996 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21997 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21998 /* Old name for UASX. */
21999 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22000 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22001 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22002 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22003 /* Old name for UHASX. */
22004 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22005 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22006 /* Old name for UHSAX. */
22007 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22008 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22009 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22010 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22011 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22012 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22013 /* Old name for UQASX. */
22014 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22015 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22016 /* Old name for UQSAX. */
22017 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22018 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22019 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22020 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22021 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22022 /* Old name for USAX. */
22023 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22024 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22025 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22026 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22027 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22028 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22029 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22030 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22031 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22032 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22033 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22034 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22035 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22036 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22037 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22038 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22039 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22040 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22041 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22042 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22043 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22044 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22045 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22046 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22047 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22048 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22049 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22050 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22051 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22052 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
22053 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
22054 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22055 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22056 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
22059 #define ARM_VARIANT & arm_ext_v6k_v6t2
22060 #undef THUMB_VARIANT
22061 #define THUMB_VARIANT & arm_ext_v6k_v6t2
22063 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
22064 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
22065 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
22066 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
22068 #undef THUMB_VARIANT
22069 #define THUMB_VARIANT & arm_ext_v6_notm
22070 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
22072 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
22073 RRnpcb
), strexd
, t_strexd
),
22075 #undef THUMB_VARIANT
22076 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22077 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
22079 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
22081 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22083 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22085 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
22088 #define ARM_VARIANT & arm_ext_sec
22089 #undef THUMB_VARIANT
22090 #define THUMB_VARIANT & arm_ext_sec
22092 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
22095 #define ARM_VARIANT & arm_ext_virt
22096 #undef THUMB_VARIANT
22097 #define THUMB_VARIANT & arm_ext_virt
22099 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
22100 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
22103 #define ARM_VARIANT & arm_ext_pan
22104 #undef THUMB_VARIANT
22105 #define THUMB_VARIANT & arm_ext_pan
22107 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
22110 #define ARM_VARIANT & arm_ext_v6t2
22111 #undef THUMB_VARIANT
22112 #define THUMB_VARIANT & arm_ext_v6t2
22114 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
22115 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
22116 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
22117 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
22119 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
22120 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
22122 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22123 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22124 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22125 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22128 #define ARM_VARIANT & arm_ext_v3
22129 #undef THUMB_VARIANT
22130 #define THUMB_VARIANT & arm_ext_v6t2
22132 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
22133 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
22134 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
22137 #define ARM_VARIANT & arm_ext_v6t2
22138 #undef THUMB_VARIANT
22139 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22140 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
22141 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
22143 /* Thumb-only instructions. */
22145 #define ARM_VARIANT NULL
22146 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
22147 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
22149 /* ARM does not really have an IT instruction, so always allow it.
22150 The opcode is copied from Thumb in order to allow warnings in
22151 -mimplicit-it=[never | arm] modes. */
22153 #define ARM_VARIANT & arm_ext_v1
22154 #undef THUMB_VARIANT
22155 #define THUMB_VARIANT & arm_ext_v6t2
22157 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
22158 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
22159 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
22160 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
22161 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
22162 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
22163 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
22164 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
22165 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
22166 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
22167 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
22168 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
22169 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
22170 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
22171 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
22172 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
22173 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
22174 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
22176 /* Thumb2 only instructions. */
22178 #define ARM_VARIANT NULL
22180 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
22181 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
22182 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
22183 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
22184 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
22185 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
22187 /* Hardware division instructions. */
22189 #define ARM_VARIANT & arm_ext_adiv
22190 #undef THUMB_VARIANT
22191 #define THUMB_VARIANT & arm_ext_div
22193 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
22194 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
22196 /* ARM V6M/V7 instructions. */
22198 #define ARM_VARIANT & arm_ext_barrier
22199 #undef THUMB_VARIANT
22200 #define THUMB_VARIANT & arm_ext_barrier
22202 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
22203 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
22204 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
22206 /* ARM V7 instructions. */
22208 #define ARM_VARIANT & arm_ext_v7
22209 #undef THUMB_VARIANT
22210 #define THUMB_VARIANT & arm_ext_v7
22212 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
22213 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
22216 #define ARM_VARIANT & arm_ext_mp
22217 #undef THUMB_VARIANT
22218 #define THUMB_VARIANT & arm_ext_mp
22220 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
22222 /* AArchv8 instructions. */
22224 #define ARM_VARIANT & arm_ext_v8
22226 /* Instructions shared between armv8-a and armv8-m. */
22227 #undef THUMB_VARIANT
22228 #define THUMB_VARIANT & arm_ext_atomics
22230 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22231 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22232 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22233 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
22234 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
22235 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
22236 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22237 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
22238 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22239 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
22241 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
22243 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
22245 #undef THUMB_VARIANT
22246 #define THUMB_VARIANT & arm_ext_v8
22248 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
22249 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
22251 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
22254 /* Defined in V8 but is in undefined encoding space for earlier
22255 architectures. However earlier architectures are required to treat
22256 this instuction as a semihosting trap as well. Hence while not explicitly
22257 defined as such, it is in fact correct to define the instruction for all
22259 #undef THUMB_VARIANT
22260 #define THUMB_VARIANT & arm_ext_v1
22262 #define ARM_VARIANT & arm_ext_v1
22263 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
22265 /* ARMv8 T32 only. */
22267 #define ARM_VARIANT NULL
22268 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
22269 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
22270 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
22272 /* FP for ARMv8. */
22274 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
22275 #undef THUMB_VARIANT
22276 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
22278 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22279 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22280 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22281 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22282 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
22283 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
22284 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
22285 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
22286 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
22287 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
22288 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
22289 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
22290 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
22292 /* Crypto v1 extensions. */
22294 #define ARM_VARIANT & fpu_crypto_ext_armv8
22295 #undef THUMB_VARIANT
22296 #define THUMB_VARIANT & fpu_crypto_ext_armv8
22298 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
22299 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
22300 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
22301 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
22302 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
22303 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
22304 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
22305 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
22306 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
22307 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
22308 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
22309 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
22310 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
22311 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
22314 #define ARM_VARIANT & crc_ext_armv8
22315 #undef THUMB_VARIANT
22316 #define THUMB_VARIANT & crc_ext_armv8
22317 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
22318 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
22319 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
22320 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
22321 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
22322 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
22324 /* ARMv8.2 RAS extension. */
22326 #define ARM_VARIANT & arm_ext_ras
22327 #undef THUMB_VARIANT
22328 #define THUMB_VARIANT & arm_ext_ras
22329 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
22332 #define ARM_VARIANT & arm_ext_v8_3
22333 #undef THUMB_VARIANT
22334 #define THUMB_VARIANT & arm_ext_v8_3
22335 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
22336 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
22337 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
22340 #define ARM_VARIANT & fpu_neon_ext_dotprod
22341 #undef THUMB_VARIANT
22342 #define THUMB_VARIANT & fpu_neon_ext_dotprod
22343 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
22344 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
22347 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
22348 #undef THUMB_VARIANT
22349 #define THUMB_VARIANT NULL
22351 cCE("wfs", e200110
, 1, (RR
), rd
),
22352 cCE("rfs", e300110
, 1, (RR
), rd
),
22353 cCE("wfc", e400110
, 1, (RR
), rd
),
22354 cCE("rfc", e500110
, 1, (RR
), rd
),
22356 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22357 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22358 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22359 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22361 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22362 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22363 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22364 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22366 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
22367 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
22368 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
22369 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
22370 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
22371 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
22372 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
22373 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
22374 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
22375 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
22376 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
22377 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
22379 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
22380 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
22381 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
22382 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
22383 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
22384 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
22385 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
22386 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
22387 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
22388 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
22389 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
22390 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
22392 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
22393 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
22394 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
22395 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
22396 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
22397 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
22398 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
22399 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
22400 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
22401 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
22402 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
22403 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
22405 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
22406 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
22407 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
22408 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
22409 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
22410 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
22411 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
22412 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
22413 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
22414 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
22415 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
22416 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
22418 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
22419 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
22420 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
22421 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
22422 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
22423 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
22424 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
22425 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
22426 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
22427 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
22428 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
22429 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
22431 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
22432 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
22433 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
22434 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
22435 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
22436 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
22437 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
22438 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
22439 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
22440 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
22441 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
22442 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
22444 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
22445 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
22446 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
22447 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
22448 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
22449 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
22450 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
22451 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
22452 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
22453 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
22454 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
22455 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
22457 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
22458 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
22459 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
22460 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
22461 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
22462 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
22463 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
22464 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
22465 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
22466 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
22467 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
22468 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
22470 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
22471 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
22472 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
22473 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
22474 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
22475 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
22476 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
22477 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
22478 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
22479 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
22480 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
22481 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
22483 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
22484 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
22485 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
22486 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
22487 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
22488 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
22489 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
22490 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
22491 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
22492 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
22493 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
22494 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
22496 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
22497 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
22498 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
22499 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
22500 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
22501 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
22502 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
22503 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
22504 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
22505 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
22506 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
22507 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
22509 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
22510 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
22511 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
22512 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
22513 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
22514 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
22515 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
22516 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
22517 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
22518 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
22519 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
22520 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
22522 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
22523 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
22524 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
22525 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
22526 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
22527 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
22528 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
22529 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
22530 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
22531 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
22532 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
22533 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
22535 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
22536 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
22537 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
22538 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
22539 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
22540 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
22541 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
22542 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
22543 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
22544 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
22545 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
22546 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
22548 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
22549 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
22550 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
22551 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
22552 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
22553 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
22554 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
22555 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
22556 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
22557 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
22558 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
22559 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
22561 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
22562 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
22563 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
22564 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
22565 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
22566 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
22567 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
22568 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
22569 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
22570 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
22571 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
22572 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
22574 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22575 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22576 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22577 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22578 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22579 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22580 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22581 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22582 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22583 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22584 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22585 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22587 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22588 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22589 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22590 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22591 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22592 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22593 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22594 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22595 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22596 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22597 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22598 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22600 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22601 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22602 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22603 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22604 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22605 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22606 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22607 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22608 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22609 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22610 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22611 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22613 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22614 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22615 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22616 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22617 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22618 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22619 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22620 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22621 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22622 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22623 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22624 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22626 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22627 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22628 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22629 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22630 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22631 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22632 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22633 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22634 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22635 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22636 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22637 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22639 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22640 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22641 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22642 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22643 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22644 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22645 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22646 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22647 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22648 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22649 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22650 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22652 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22653 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22654 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22655 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22656 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22657 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22658 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22659 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22660 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22661 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22662 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22663 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22665 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22666 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22667 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22668 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22669 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22670 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22671 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22672 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22673 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22674 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22675 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22676 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22678 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22679 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22680 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22681 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22682 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22683 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22684 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22685 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22686 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22687 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22688 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22689 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22691 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22692 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22693 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22694 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22695 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22696 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22697 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22698 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22699 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22700 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22701 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22702 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22704 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22705 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22706 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22707 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22708 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22709 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22710 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22711 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22712 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22713 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22714 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22715 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22717 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22718 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22719 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22720 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22721 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22722 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22723 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22724 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22725 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22726 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22727 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22728 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22730 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22731 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22732 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22733 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22734 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22735 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22736 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22737 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22738 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22739 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22740 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22741 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22743 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
22744 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
22745 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
22746 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
22748 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
22749 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
22750 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
22751 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
22752 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
22753 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
22754 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
22755 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
22756 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
22757 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
22758 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
22759 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
22761 /* The implementation of the FIX instruction is broken on some
22762 assemblers, in that it accepts a precision specifier as well as a
22763 rounding specifier, despite the fact that this is meaningless.
22764 To be more compatible, we accept it as well, though of course it
22765 does not set any bits. */
22766 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
22767 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
22768 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
22769 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
22770 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
22771 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
22772 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
22773 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
22774 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
22775 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
22776 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
22777 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
22778 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
22780 /* Instructions that were new with the real FPA, call them V2. */
22782 #define ARM_VARIANT & fpu_fpa_ext_v2
22784 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
22785 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
22786 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
22787 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
22788 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
22789 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
22792 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
22794 /* Moves and type conversions. */
22795 cCE("fmstat", ef1fa10
, 0, (), noargs
),
22796 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
22797 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
22798 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
22799 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
22800 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
22801 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
22802 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
22803 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
22804 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
22805 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
22807 /* Memory operations. */
22808 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
22809 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
22810 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
22811 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
22812 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
22813 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
22814 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
22815 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
22816 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
22817 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
22818 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
22819 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
22820 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
22821 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
22822 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
22823 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
22824 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
22825 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
22827 /* Monadic operations. */
22828 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
22829 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
22830 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
22832 /* Dyadic operations. */
22833 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
22834 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
22835 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
22836 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
22837 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
22838 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
22839 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
22840 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
22841 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
22844 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
22845 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
22846 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
22847 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
22849 /* Double precision load/store are still present on single precision
22850 implementations. */
22851 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
22852 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
22853 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
22854 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
22855 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
22856 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
22857 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
22858 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
22859 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
22860 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
22863 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
22865 /* Moves and type conversions. */
22866 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
22867 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
22868 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
22869 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
22870 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
22871 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
22872 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
22873 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
22874 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
22875 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
22876 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
22877 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
22879 /* Monadic operations. */
22880 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
22881 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
22882 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
22884 /* Dyadic operations. */
22885 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
22886 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
22887 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
22888 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
22889 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
22890 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
22891 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
22892 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
22893 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
22896 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
22897 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
22898 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
22899 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
22901 /* Instructions which may belong to either the Neon or VFP instruction sets.
22902 Individual encoder functions perform additional architecture checks. */
22904 #define ARM_VARIANT & fpu_vfp_ext_v1xd
22905 #undef THUMB_VARIANT
22906 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
22908 /* These mnemonics are unique to VFP. */
22909 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
22910 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
22911 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
22912 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
22913 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
22914 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
22915 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
22916 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
22917 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
22918 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
22920 /* Mnemonics shared by Neon and VFP. */
22921 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
22922 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
22923 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
22925 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
22926 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
22927 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
22928 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
22929 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
22930 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
22932 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
22933 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
22934 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
22935 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
22938 /* NOTE: All VMOV encoding is special-cased! */
22939 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
22941 #undef THUMB_VARIANT
22942 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
22943 by different feature bits. Since we are setting the Thumb guard, we can
22944 require Thumb-1 which makes it a nop guard and set the right feature bit in
22945 do_vldr_vstr (). */
22946 #define THUMB_VARIANT & arm_ext_v4t
22947 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
22948 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
22951 #define ARM_VARIANT & arm_ext_fp16
22952 #undef THUMB_VARIANT
22953 #define THUMB_VARIANT & arm_ext_fp16
22954 /* New instructions added from v8.2, allowing the extraction and insertion of
22955 the upper 16 bits of a 32-bit vector register. */
22956 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
22957 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
22959 /* New backported fma/fms instructions optional in v8.2. */
22960 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
22961 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
22963 #undef THUMB_VARIANT
22964 #define THUMB_VARIANT & fpu_neon_ext_v1
22966 #define ARM_VARIANT & fpu_neon_ext_v1
22968 /* Data processing with three registers of the same length. */
22969 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
22970 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
22971 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
22972 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
22973 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
22974 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
22975 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
22976 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
22977 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
22978 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
22979 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
22980 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
22981 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
22982 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
22983 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
22984 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
22985 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
22986 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
22987 /* If not immediate, fall back to neon_dyadic_i64_su.
22988 shl_imm should accept I8 I16 I32 I64,
22989 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
22990 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
22991 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
22992 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
22993 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
22994 /* Logic ops, types optional & ignored. */
22995 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
22996 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
22997 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
22998 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
22999 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
23000 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23001 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
23002 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23003 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
23004 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
23005 /* Bitfield ops, untyped. */
23006 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23007 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23008 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23009 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23010 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23011 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23012 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
23013 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23014 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
23015 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23016 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
23017 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23018 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
23019 back to neon_dyadic_if_su. */
23020 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
23021 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
23022 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
23023 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
23024 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
23025 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
23026 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
23027 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
23028 /* Comparison. Type I8 I16 I32 F32. */
23029 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
23030 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
23031 /* As above, D registers only. */
23032 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
23033 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
23034 /* Int and float variants, signedness unimportant. */
23035 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
23036 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
23037 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
23038 /* Add/sub take types I8 I16 I32 I64 F32. */
23039 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
23040 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
23041 /* vtst takes sizes 8, 16, 32. */
23042 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
23043 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
23044 /* VMUL takes I8 I16 I32 F32 P8. */
23045 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
23046 /* VQD{R}MULH takes S16 S32. */
23047 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
23048 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
23049 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
23050 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
23051 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
23052 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
23053 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
23054 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
23055 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
23056 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
23057 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
23058 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
23059 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
23060 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
23061 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
23062 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
23063 /* ARM v8.1 extension. */
23064 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
23065 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
23066 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
23067 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
23069 /* Two address, int/float. Types S8 S16 S32 F32. */
23070 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
23071 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
23073 /* Data processing with two registers and a shift amount. */
23074 /* Right shifts, and variants with rounding.
23075 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
23076 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
23077 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
23078 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
23079 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
23080 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
23081 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
23082 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
23083 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
23084 /* Shift and insert. Sizes accepted 8 16 32 64. */
23085 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
23086 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
23087 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
23088 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
23089 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
23090 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
23091 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
23092 /* Right shift immediate, saturating & narrowing, with rounding variants.
23093 Types accepted S16 S32 S64 U16 U32 U64. */
23094 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
23095 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
23096 /* As above, unsigned. Types accepted S16 S32 S64. */
23097 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
23098 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
23099 /* Right shift narrowing. Types accepted I16 I32 I64. */
23100 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
23101 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
23102 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
23103 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
23104 /* CVT with optional immediate for fixed-point variant. */
23105 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
23107 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
23108 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
23110 /* Data processing, three registers of different lengths. */
23111 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
23112 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
23113 /* If not scalar, fall back to neon_dyadic_long.
23114 Vector types as above, scalar types S16 S32 U16 U32. */
23115 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
23116 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
23117 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
23118 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
23119 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
23120 /* Dyadic, narrowing insns. Types I16 I32 I64. */
23121 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23122 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23123 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23124 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23125 /* Saturating doubling multiplies. Types S16 S32. */
23126 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23127 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23128 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23129 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
23130 S16 S32 U16 U32. */
23131 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
23133 /* Extract. Size 8. */
23134 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
23135 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
23137 /* Two registers, miscellaneous. */
23138 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
23139 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
23140 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
23141 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
23142 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
23143 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
23144 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
23145 /* Vector replicate. Sizes 8 16 32. */
23146 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
23147 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
23148 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
23149 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
23150 /* VMOVN. Types I16 I32 I64. */
23151 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
23152 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
23153 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
23154 /* VQMOVUN. Types S16 S32 S64. */
23155 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
23156 /* VZIP / VUZP. Sizes 8 16 32. */
23157 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
23158 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
23159 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
23160 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
23161 /* VQABS / VQNEG. Types S8 S16 S32. */
23162 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
23163 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
23164 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
23165 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
23166 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
23167 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
23168 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
23169 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
23170 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
23171 /* Reciprocal estimates. Types U32 F16 F32. */
23172 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
23173 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
23174 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
23175 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
23176 /* VCLS. Types S8 S16 S32. */
23177 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
23178 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
23179 /* VCLZ. Types I8 I16 I32. */
23180 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
23181 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
23182 /* VCNT. Size 8. */
23183 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
23184 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
23185 /* Two address, untyped. */
23186 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
23187 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
23188 /* VTRN. Sizes 8 16 32. */
23189 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
23190 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
23192 /* Table lookup. Size 8. */
23193 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
23194 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
23196 #undef THUMB_VARIANT
23197 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
23199 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
23201 /* Neon element/structure load/store. */
23202 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23203 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23204 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23205 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23206 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23207 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23208 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23209 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23211 #undef THUMB_VARIANT
23212 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
23214 #define ARM_VARIANT & fpu_vfp_ext_v3xd
23215 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
23216 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23217 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23218 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23219 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23220 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23221 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23222 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23223 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23225 #undef THUMB_VARIANT
23226 #define THUMB_VARIANT & fpu_vfp_ext_v3
23228 #define ARM_VARIANT & fpu_vfp_ext_v3
23230 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
23231 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23232 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23233 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23234 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23235 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23236 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23237 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23238 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23241 #define ARM_VARIANT & fpu_vfp_ext_fma
23242 #undef THUMB_VARIANT
23243 #define THUMB_VARIANT & fpu_vfp_ext_fma
23244 /* Mnemonics shared by Neon and VFP. These are included in the
23245 VFP FMA variant; NEON and VFP FMA always includes the NEON
23246 FMA instructions. */
23247 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
23248 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
23249 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
23250 the v form should always be used. */
23251 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23252 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23253 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23254 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23255 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23256 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23258 #undef THUMB_VARIANT
23260 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
23262 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23263 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23264 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23265 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23266 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23267 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23268 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
23269 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
23272 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
23274 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
23275 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
23276 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
23277 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
23278 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
23279 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
23280 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
23281 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
23282 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
23283 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23284 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23285 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23286 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23287 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23288 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23289 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
23290 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
23291 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
23292 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
23293 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
23294 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23295 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23296 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23297 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23298 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23299 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23300 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
23301 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
23302 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
23303 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
23304 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
23305 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
23306 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
23307 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
23308 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23309 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23310 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23311 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23312 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23313 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23314 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23315 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23316 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23317 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23318 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23319 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23320 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
23321 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23322 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23323 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23324 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23325 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23326 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23327 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23328 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23329 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23330 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23331 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23332 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23333 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23334 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23335 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23336 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23337 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23338 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23339 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23340 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23341 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23342 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
23343 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
23344 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23345 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23346 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23347 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23348 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23349 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23350 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23351 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23352 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23353 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23354 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23355 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23356 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23357 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23358 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23359 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23360 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23361 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23362 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
23363 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23364 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23365 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23366 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23367 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23368 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23369 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23370 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23371 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23372 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23373 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23374 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23375 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23376 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23377 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23378 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23379 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23380 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23381 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23382 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23383 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23384 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
23385 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23386 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23387 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23388 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23389 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23390 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23391 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23392 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23393 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23394 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23395 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23396 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23397 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23398 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23399 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23400 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23401 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23402 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23403 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23404 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23405 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
23406 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
23407 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23408 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23409 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23410 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23411 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23412 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23413 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23414 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23415 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23416 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23417 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23418 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23419 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23420 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23421 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23422 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23423 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23424 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23425 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23426 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23427 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23428 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23429 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23430 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23431 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23432 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23433 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23434 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23435 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
23438 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
23440 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
23441 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
23442 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
23443 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23444 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23445 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23446 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23447 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23448 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23449 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23450 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23451 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23452 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23453 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23454 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23455 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23456 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23457 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23458 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23459 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23460 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
23461 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23462 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23463 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23464 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23465 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23466 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23467 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23468 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23469 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23470 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23471 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23472 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23473 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23474 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23475 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23476 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23477 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23478 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23479 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23480 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23481 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23482 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23483 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23484 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23485 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23486 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23487 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23488 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23489 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23490 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23491 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23492 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23493 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23494 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23495 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23496 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23499 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
23501 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
23502 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
23503 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
23504 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
23505 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
23506 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
23507 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
23508 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
23509 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
23510 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
23511 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
23512 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
23513 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
23514 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
23515 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
23516 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
23517 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
23518 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
23519 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
23520 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
23521 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
23522 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
23523 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
23524 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
23525 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
23526 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
23527 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
23528 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
23529 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
23530 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
23531 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
23532 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
23533 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
23534 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
23535 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
23536 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
23537 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
23538 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
23539 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
23540 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
23541 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
23542 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
23543 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
23544 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
23545 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
23546 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
23547 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
23548 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
23549 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
23550 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
23551 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
23552 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
23553 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
23554 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
23555 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
23556 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
23557 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
23558 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
23559 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
23560 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
23561 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
23562 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
23563 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
23564 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
23565 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23566 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
23567 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23568 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
23569 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23570 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
23571 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23572 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23573 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
23574 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
23575 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
23576 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
23578 /* ARMv8.5-A instructions. */
23580 #define ARM_VARIANT & arm_ext_sb
23581 #undef THUMB_VARIANT
23582 #define THUMB_VARIANT & arm_ext_sb
23583 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
23586 #define ARM_VARIANT & arm_ext_predres
23587 #undef THUMB_VARIANT
23588 #define THUMB_VARIANT & arm_ext_predres
23589 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
23590 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
23591 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
23593 /* ARMv8-M instructions. */
23595 #define ARM_VARIANT NULL
23596 #undef THUMB_VARIANT
23597 #define THUMB_VARIANT & arm_ext_v8m
23598 ToU("sg", e97fe97f
, 0, (), noargs
),
23599 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
23600 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
23601 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
23602 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
23603 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
23604 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
23606 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
23607 instructions behave as nop if no VFP is present. */
23608 #undef THUMB_VARIANT
23609 #define THUMB_VARIANT & arm_ext_v8m_main
23610 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
23611 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
23613 /* Armv8.1-M Mainline instructions. */
23614 #undef THUMB_VARIANT
23615 #define THUMB_VARIANT & arm_ext_v8_1m_main
23616 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
23617 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
23618 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
23619 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
23620 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
23622 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
23623 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
23624 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
23626 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
23627 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
23629 #undef THUMB_VARIANT
23630 #define THUMB_VARIANT & mve_ext
23631 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
23632 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
23633 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
23634 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
23635 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
23636 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
23637 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
23638 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
23639 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
23640 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
23641 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
23642 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
23643 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
23644 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
23645 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
23647 /* MVE and MVE FP only. */
23648 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
23649 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
23650 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23651 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23652 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23653 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23654 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23655 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23656 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23657 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23658 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23659 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23661 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
23662 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
23663 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23664 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23665 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23666 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23667 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
23668 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
23669 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23670 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23671 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23672 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23673 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23674 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23675 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23676 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23677 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23678 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23679 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23680 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23682 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
23683 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
23686 #define ARM_VARIANT & fpu_vfp_ext_v1
23687 #undef THUMB_VARIANT
23688 #define THUMB_VARIANT & arm_ext_v6t2
23690 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23693 #define ARM_VARIANT & fpu_vfp_ext_v1xd
23695 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
23696 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
23697 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
23698 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23700 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
23701 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
23702 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
23704 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
23705 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
23707 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
23708 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
23711 #define ARM_VARIANT & fpu_vfp_ext_v2
23713 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
23714 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
23715 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
23716 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
23719 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
23720 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
23721 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
23722 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
23723 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
23726 #define ARM_VARIANT & fpu_neon_ext_v1
23727 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
23728 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
23729 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
23730 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
23733 #undef THUMB_VARIANT
23765 /* MD interface: bits in the object file. */
23767 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
23768 for use in the a.out file, and stores them in the array pointed to by buf.
23769 This knows about the endian-ness of the target machine and does
23770 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
23771 2 (short) and 4 (long) Floating numbers are put out as a series of
23772 LITTLENUMS (shorts, here at least). */
23775 md_number_to_chars (char * buf
, valueT val
, int n
)
23777 if (target_big_endian
)
23778 number_to_chars_bigendian (buf
, val
, n
);
23780 number_to_chars_littleendian (buf
, val
, n
);
23784 md_chars_to_number (char * buf
, int n
)
23787 unsigned char * where
= (unsigned char *) buf
;
23789 if (target_big_endian
)
23794 result
|= (*where
++ & 255);
23802 result
|= (where
[n
] & 255);
23809 /* MD interface: Sections. */
23811 /* Calculate the maximum variable size (i.e., excluding fr_fix)
23812 that an rs_machine_dependent frag may reach. */
23815 arm_frag_max_var (fragS
*fragp
)
23817 /* We only use rs_machine_dependent for variable-size Thumb instructions,
23818 which are either THUMB_SIZE (2) or INSN_SIZE (4).
23820 Note that we generate relaxable instructions even for cases that don't
23821 really need it, like an immediate that's a trivial constant. So we're
23822 overestimating the instruction size for some of those cases. Rather
23823 than putting more intelligence here, it would probably be better to
23824 avoid generating a relaxation frag in the first place when it can be
23825 determined up front that a short instruction will suffice. */
23827 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
23831 /* Estimate the size of a frag before relaxing. Assume everything fits in
23835 md_estimate_size_before_relax (fragS
* fragp
,
23836 segT segtype ATTRIBUTE_UNUSED
)
23842 /* Convert a machine dependent frag. */
23845 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
23847 unsigned long insn
;
23848 unsigned long old_op
;
23856 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
23858 old_op
= bfd_get_16(abfd
, buf
);
23859 if (fragp
->fr_symbol
)
23861 exp
.X_op
= O_symbol
;
23862 exp
.X_add_symbol
= fragp
->fr_symbol
;
23866 exp
.X_op
= O_constant
;
23868 exp
.X_add_number
= fragp
->fr_offset
;
23869 opcode
= fragp
->fr_subtype
;
23872 case T_MNEM_ldr_pc
:
23873 case T_MNEM_ldr_pc2
:
23874 case T_MNEM_ldr_sp
:
23875 case T_MNEM_str_sp
:
23882 if (fragp
->fr_var
== 4)
23884 insn
= THUMB_OP32 (opcode
);
23885 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
23887 insn
|= (old_op
& 0x700) << 4;
23891 insn
|= (old_op
& 7) << 12;
23892 insn
|= (old_op
& 0x38) << 13;
23894 insn
|= 0x00000c00;
23895 put_thumb32_insn (buf
, insn
);
23896 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
23900 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
23902 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
23905 if (fragp
->fr_var
== 4)
23907 insn
= THUMB_OP32 (opcode
);
23908 insn
|= (old_op
& 0xf0) << 4;
23909 put_thumb32_insn (buf
, insn
);
23910 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
23914 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
23915 exp
.X_add_number
-= 4;
23923 if (fragp
->fr_var
== 4)
23925 int r0off
= (opcode
== T_MNEM_mov
23926 || opcode
== T_MNEM_movs
) ? 0 : 8;
23927 insn
= THUMB_OP32 (opcode
);
23928 insn
= (insn
& 0xe1ffffff) | 0x10000000;
23929 insn
|= (old_op
& 0x700) << r0off
;
23930 put_thumb32_insn (buf
, insn
);
23931 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
23935 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
23940 if (fragp
->fr_var
== 4)
23942 insn
= THUMB_OP32(opcode
);
23943 put_thumb32_insn (buf
, insn
);
23944 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
23947 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
23951 if (fragp
->fr_var
== 4)
23953 insn
= THUMB_OP32(opcode
);
23954 insn
|= (old_op
& 0xf00) << 14;
23955 put_thumb32_insn (buf
, insn
);
23956 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
23959 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
23962 case T_MNEM_add_sp
:
23963 case T_MNEM_add_pc
:
23964 case T_MNEM_inc_sp
:
23965 case T_MNEM_dec_sp
:
23966 if (fragp
->fr_var
== 4)
23968 /* ??? Choose between add and addw. */
23969 insn
= THUMB_OP32 (opcode
);
23970 insn
|= (old_op
& 0xf0) << 4;
23971 put_thumb32_insn (buf
, insn
);
23972 if (opcode
== T_MNEM_add_pc
)
23973 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
23975 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
23978 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
23986 if (fragp
->fr_var
== 4)
23988 insn
= THUMB_OP32 (opcode
);
23989 insn
|= (old_op
& 0xf0) << 4;
23990 insn
|= (old_op
& 0xf) << 16;
23991 put_thumb32_insn (buf
, insn
);
23992 if (insn
& (1 << 20))
23993 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
23995 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
23998 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24004 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
24005 (enum bfd_reloc_code_real
) reloc_type
);
24006 fixp
->fx_file
= fragp
->fr_file
;
24007 fixp
->fx_line
= fragp
->fr_line
;
24008 fragp
->fr_fix
+= fragp
->fr_var
;
24010 /* Set whether we use thumb-2 ISA based on final relaxation results. */
24011 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
24012 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
24013 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
24016 /* Return the size of a relaxable immediate operand instruction.
24017 SHIFT and SIZE specify the form of the allowable immediate. */
24019 relax_immediate (fragS
*fragp
, int size
, int shift
)
24025 /* ??? Should be able to do better than this. */
24026 if (fragp
->fr_symbol
)
24029 low
= (1 << shift
) - 1;
24030 mask
= (1 << (shift
+ size
)) - (1 << shift
);
24031 offset
= fragp
->fr_offset
;
24032 /* Force misaligned offsets to 32-bit variant. */
24035 if (offset
& ~mask
)
24040 /* Get the address of a symbol during relaxation. */
24042 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
24048 sym
= fragp
->fr_symbol
;
24049 sym_frag
= symbol_get_frag (sym
);
24050 know (S_GET_SEGMENT (sym
) != absolute_section
24051 || sym_frag
== &zero_address_frag
);
24052 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
24054 /* If frag has yet to be reached on this pass, assume it will
24055 move by STRETCH just as we did. If this is not so, it will
24056 be because some frag between grows, and that will force
24060 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
24064 /* Adjust stretch for any alignment frag. Note that if have
24065 been expanding the earlier code, the symbol may be
24066 defined in what appears to be an earlier frag. FIXME:
24067 This doesn't handle the fr_subtype field, which specifies
24068 a maximum number of bytes to skip when doing an
24070 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
24072 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
24075 stretch
= - ((- stretch
)
24076 & ~ ((1 << (int) f
->fr_offset
) - 1));
24078 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
24090 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
24093 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
24098 /* Assume worst case for symbols not known to be in the same section. */
24099 if (fragp
->fr_symbol
== NULL
24100 || !S_IS_DEFINED (fragp
->fr_symbol
)
24101 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
24102 || S_IS_WEAK (fragp
->fr_symbol
))
24105 val
= relaxed_symbol_addr (fragp
, stretch
);
24106 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
24107 addr
= (addr
+ 4) & ~3;
24108 /* Force misaligned targets to 32-bit variant. */
24112 if (val
< 0 || val
> 1020)
24117 /* Return the size of a relaxable add/sub immediate instruction. */
24119 relax_addsub (fragS
*fragp
, asection
*sec
)
24124 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
24125 op
= bfd_get_16(sec
->owner
, buf
);
24126 if ((op
& 0xf) == ((op
>> 4) & 0xf))
24127 return relax_immediate (fragp
, 8, 0);
24129 return relax_immediate (fragp
, 3, 0);
24132 /* Return TRUE iff the definition of symbol S could be pre-empted
24133 (overridden) at link or load time. */
24135 symbol_preemptible (symbolS
*s
)
24137 /* Weak symbols can always be pre-empted. */
24141 /* Non-global symbols cannot be pre-empted. */
24142 if (! S_IS_EXTERNAL (s
))
24146 /* In ELF, a global symbol can be marked protected, or private. In that
24147 case it can't be pre-empted (other definitions in the same link unit
24148 would violate the ODR). */
24149 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
24153 /* Other global symbols might be pre-empted. */
24157 /* Return the size of a relaxable branch instruction. BITS is the
24158 size of the offset field in the narrow instruction. */
24161 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
24167 /* Assume worst case for symbols not known to be in the same section. */
24168 if (!S_IS_DEFINED (fragp
->fr_symbol
)
24169 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
24170 || S_IS_WEAK (fragp
->fr_symbol
))
24174 /* A branch to a function in ARM state will require interworking. */
24175 if (S_IS_DEFINED (fragp
->fr_symbol
)
24176 && ARM_IS_FUNC (fragp
->fr_symbol
))
24180 if (symbol_preemptible (fragp
->fr_symbol
))
24183 val
= relaxed_symbol_addr (fragp
, stretch
);
24184 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
24187 /* Offset is a signed value *2 */
24189 if (val
>= limit
|| val
< -limit
)
24195 /* Relax a machine dependent frag. This returns the amount by which
24196 the current size of the frag should change. */
24199 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
24204 oldsize
= fragp
->fr_var
;
24205 switch (fragp
->fr_subtype
)
24207 case T_MNEM_ldr_pc2
:
24208 newsize
= relax_adr (fragp
, sec
, stretch
);
24210 case T_MNEM_ldr_pc
:
24211 case T_MNEM_ldr_sp
:
24212 case T_MNEM_str_sp
:
24213 newsize
= relax_immediate (fragp
, 8, 2);
24217 newsize
= relax_immediate (fragp
, 5, 2);
24221 newsize
= relax_immediate (fragp
, 5, 1);
24225 newsize
= relax_immediate (fragp
, 5, 0);
24228 newsize
= relax_adr (fragp
, sec
, stretch
);
24234 newsize
= relax_immediate (fragp
, 8, 0);
24237 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
24240 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
24242 case T_MNEM_add_sp
:
24243 case T_MNEM_add_pc
:
24244 newsize
= relax_immediate (fragp
, 8, 2);
24246 case T_MNEM_inc_sp
:
24247 case T_MNEM_dec_sp
:
24248 newsize
= relax_immediate (fragp
, 7, 2);
24254 newsize
= relax_addsub (fragp
, sec
);
24260 fragp
->fr_var
= newsize
;
24261 /* Freeze wide instructions that are at or before the same location as
24262 in the previous pass. This avoids infinite loops.
24263 Don't freeze them unconditionally because targets may be artificially
24264 misaligned by the expansion of preceding frags. */
24265 if (stretch
<= 0 && newsize
> 2)
24267 md_convert_frag (sec
->owner
, sec
, fragp
);
24271 return newsize
- oldsize
;
24274 /* Round up a section size to the appropriate boundary. */
24277 md_section_align (segT segment ATTRIBUTE_UNUSED
,
24283 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
24284 of an rs_align_code fragment. */
24287 arm_handle_align (fragS
* fragP
)
24289 static unsigned char const arm_noop
[2][2][4] =
24292 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
24293 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
24296 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
24297 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
24300 static unsigned char const thumb_noop
[2][2][2] =
24303 {0xc0, 0x46}, /* LE */
24304 {0x46, 0xc0}, /* BE */
24307 {0x00, 0xbf}, /* LE */
24308 {0xbf, 0x00} /* BE */
24311 static unsigned char const wide_thumb_noop
[2][4] =
24312 { /* Wide Thumb-2 */
24313 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
24314 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
24317 unsigned bytes
, fix
, noop_size
;
24319 const unsigned char * noop
;
24320 const unsigned char *narrow_noop
= NULL
;
24325 if (fragP
->fr_type
!= rs_align_code
)
24328 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
24329 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
24332 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
24333 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
24335 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
24337 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
24339 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
24340 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
24342 narrow_noop
= thumb_noop
[1][target_big_endian
];
24343 noop
= wide_thumb_noop
[target_big_endian
];
24346 noop
= thumb_noop
[0][target_big_endian
];
24354 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
24355 ? selected_cpu
: arm_arch_none
,
24357 [target_big_endian
];
24364 fragP
->fr_var
= noop_size
;
24366 if (bytes
& (noop_size
- 1))
24368 fix
= bytes
& (noop_size
- 1);
24370 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
24372 memset (p
, 0, fix
);
24379 if (bytes
& noop_size
)
24381 /* Insert a narrow noop. */
24382 memcpy (p
, narrow_noop
, noop_size
);
24384 bytes
-= noop_size
;
24388 /* Use wide noops for the remainder */
24392 while (bytes
>= noop_size
)
24394 memcpy (p
, noop
, noop_size
);
24396 bytes
-= noop_size
;
24400 fragP
->fr_fix
+= fix
;
24403 /* Called from md_do_align. Used to create an alignment
24404 frag in a code section. */
24407 arm_frag_align_code (int n
, int max
)
24411 /* We assume that there will never be a requirement
24412 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
24413 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
24418 _("alignments greater than %d bytes not supported in .text sections."),
24419 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
24420 as_fatal ("%s", err_msg
);
24423 p
= frag_var (rs_align_code
,
24424 MAX_MEM_FOR_RS_ALIGN_CODE
,
24426 (relax_substateT
) max
,
24433 /* Perform target specific initialisation of a frag.
24434 Note - despite the name this initialisation is not done when the frag
24435 is created, but only when its type is assigned. A frag can be created
24436 and used a long time before its type is set, so beware of assuming that
24437 this initialisation is performed first. */
24441 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
24443 /* Record whether this frag is in an ARM or a THUMB area. */
24444 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
24447 #else /* OBJ_ELF is defined. */
24449 arm_init_frag (fragS
* fragP
, int max_chars
)
24451 bfd_boolean frag_thumb_mode
;
24453 /* If the current ARM vs THUMB mode has not already
24454 been recorded into this frag then do so now. */
24455 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
24456 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
24458 /* PR 21809: Do not set a mapping state for debug sections
24459 - it just confuses other tools. */
24460 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
24463 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
24465 /* Record a mapping symbol for alignment frags. We will delete this
24466 later if the alignment ends up empty. */
24467 switch (fragP
->fr_type
)
24470 case rs_align_test
:
24472 mapping_state_2 (MAP_DATA
, max_chars
);
24474 case rs_align_code
:
24475 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
24482 /* When we change sections we need to issue a new mapping symbol. */
24485 arm_elf_change_section (void)
24487 /* Link an unlinked unwind index table section to the .text section. */
24488 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
24489 && elf_linked_to_section (now_seg
) == NULL
)
24490 elf_linked_to_section (now_seg
) = text_section
;
24494 arm_elf_section_type (const char * str
, size_t len
)
24496 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
24497 return SHT_ARM_EXIDX
;
24502 /* Code to deal with unwinding tables. */
24504 static void add_unwind_adjustsp (offsetT
);
24506 /* Generate any deferred unwind frame offset. */
24509 flush_pending_unwind (void)
24513 offset
= unwind
.pending_offset
;
24514 unwind
.pending_offset
= 0;
24516 add_unwind_adjustsp (offset
);
24519 /* Add an opcode to this list for this function. Two-byte opcodes should
24520 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
24524 add_unwind_opcode (valueT op
, int length
)
24526 /* Add any deferred stack adjustment. */
24527 if (unwind
.pending_offset
)
24528 flush_pending_unwind ();
24530 unwind
.sp_restored
= 0;
24532 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
24534 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
24535 if (unwind
.opcodes
)
24536 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
24537 unwind
.opcode_alloc
);
24539 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
24544 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
24546 unwind
.opcode_count
++;
24550 /* Add unwind opcodes to adjust the stack pointer. */
24553 add_unwind_adjustsp (offsetT offset
)
24557 if (offset
> 0x200)
24559 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
24564 /* Long form: 0xb2, uleb128. */
24565 /* This might not fit in a word so add the individual bytes,
24566 remembering the list is built in reverse order. */
24567 o
= (valueT
) ((offset
- 0x204) >> 2);
24569 add_unwind_opcode (0, 1);
24571 /* Calculate the uleb128 encoding of the offset. */
24575 bytes
[n
] = o
& 0x7f;
24581 /* Add the insn. */
24583 add_unwind_opcode (bytes
[n
- 1], 1);
24584 add_unwind_opcode (0xb2, 1);
24586 else if (offset
> 0x100)
24588 /* Two short opcodes. */
24589 add_unwind_opcode (0x3f, 1);
24590 op
= (offset
- 0x104) >> 2;
24591 add_unwind_opcode (op
, 1);
24593 else if (offset
> 0)
24595 /* Short opcode. */
24596 op
= (offset
- 4) >> 2;
24597 add_unwind_opcode (op
, 1);
24599 else if (offset
< 0)
24602 while (offset
> 0x100)
24604 add_unwind_opcode (0x7f, 1);
24607 op
= ((offset
- 4) >> 2) | 0x40;
24608 add_unwind_opcode (op
, 1);
24612 /* Finish the list of unwind opcodes for this function. */
24615 finish_unwind_opcodes (void)
24619 if (unwind
.fp_used
)
24621 /* Adjust sp as necessary. */
24622 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
24623 flush_pending_unwind ();
24625 /* After restoring sp from the frame pointer. */
24626 op
= 0x90 | unwind
.fp_reg
;
24627 add_unwind_opcode (op
, 1);
24630 flush_pending_unwind ();
24634 /* Start an exception table entry. If idx is nonzero this is an index table
24638 start_unwind_section (const segT text_seg
, int idx
)
24640 const char * text_name
;
24641 const char * prefix
;
24642 const char * prefix_once
;
24643 const char * group_name
;
24651 prefix
= ELF_STRING_ARM_unwind
;
24652 prefix_once
= ELF_STRING_ARM_unwind_once
;
24653 type
= SHT_ARM_EXIDX
;
24657 prefix
= ELF_STRING_ARM_unwind_info
;
24658 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
24659 type
= SHT_PROGBITS
;
24662 text_name
= segment_name (text_seg
);
24663 if (streq (text_name
, ".text"))
24666 if (strncmp (text_name
, ".gnu.linkonce.t.",
24667 strlen (".gnu.linkonce.t.")) == 0)
24669 prefix
= prefix_once
;
24670 text_name
+= strlen (".gnu.linkonce.t.");
24673 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
24679 /* Handle COMDAT group. */
24680 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
24682 group_name
= elf_group_name (text_seg
);
24683 if (group_name
== NULL
)
24685 as_bad (_("Group section `%s' has no group signature"),
24686 segment_name (text_seg
));
24687 ignore_rest_of_line ();
24690 flags
|= SHF_GROUP
;
24694 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
24697 /* Set the section link for index tables. */
24699 elf_linked_to_section (now_seg
) = text_seg
;
24703 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
24704 personality routine data. Returns zero, or the index table value for
24705 an inline entry. */
24708 create_unwind_entry (int have_data
)
24713 /* The current word of data. */
24715 /* The number of bytes left in this word. */
24718 finish_unwind_opcodes ();
24720 /* Remember the current text section. */
24721 unwind
.saved_seg
= now_seg
;
24722 unwind
.saved_subseg
= now_subseg
;
24724 start_unwind_section (now_seg
, 0);
24726 if (unwind
.personality_routine
== NULL
)
24728 if (unwind
.personality_index
== -2)
24731 as_bad (_("handlerdata in cantunwind frame"));
24732 return 1; /* EXIDX_CANTUNWIND. */
24735 /* Use a default personality routine if none is specified. */
24736 if (unwind
.personality_index
== -1)
24738 if (unwind
.opcode_count
> 3)
24739 unwind
.personality_index
= 1;
24741 unwind
.personality_index
= 0;
24744 /* Space for the personality routine entry. */
24745 if (unwind
.personality_index
== 0)
24747 if (unwind
.opcode_count
> 3)
24748 as_bad (_("too many unwind opcodes for personality routine 0"));
24752 /* All the data is inline in the index table. */
24755 while (unwind
.opcode_count
> 0)
24757 unwind
.opcode_count
--;
24758 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
24762 /* Pad with "finish" opcodes. */
24764 data
= (data
<< 8) | 0xb0;
24771 /* We get two opcodes "free" in the first word. */
24772 size
= unwind
.opcode_count
- 2;
24776 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
24777 if (unwind
.personality_index
!= -1)
24779 as_bad (_("attempt to recreate an unwind entry"));
24783 /* An extra byte is required for the opcode count. */
24784 size
= unwind
.opcode_count
+ 1;
24787 size
= (size
+ 3) >> 2;
24789 as_bad (_("too many unwind opcodes"));
24791 frag_align (2, 0, 0);
24792 record_alignment (now_seg
, 2);
24793 unwind
.table_entry
= expr_build_dot ();
24795 /* Allocate the table entry. */
24796 ptr
= frag_more ((size
<< 2) + 4);
24797 /* PR 13449: Zero the table entries in case some of them are not used. */
24798 memset (ptr
, 0, (size
<< 2) + 4);
24799 where
= frag_now_fix () - ((size
<< 2) + 4);
24801 switch (unwind
.personality_index
)
24804 /* ??? Should this be a PLT generating relocation? */
24805 /* Custom personality routine. */
24806 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
24807 BFD_RELOC_ARM_PREL31
);
24812 /* Set the first byte to the number of additional words. */
24813 data
= size
> 0 ? size
- 1 : 0;
24817 /* ABI defined personality routines. */
24819 /* Three opcodes bytes are packed into the first word. */
24826 /* The size and first two opcode bytes go in the first word. */
24827 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
24832 /* Should never happen. */
24836 /* Pack the opcodes into words (MSB first), reversing the list at the same
24838 while (unwind
.opcode_count
> 0)
24842 md_number_to_chars (ptr
, data
, 4);
24847 unwind
.opcode_count
--;
24849 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
24852 /* Finish off the last word. */
24855 /* Pad with "finish" opcodes. */
24857 data
= (data
<< 8) | 0xb0;
24859 md_number_to_chars (ptr
, data
, 4);
24864 /* Add an empty descriptor if there is no user-specified data. */
24865 ptr
= frag_more (4);
24866 md_number_to_chars (ptr
, 0, 4);
24873 /* Initialize the DWARF-2 unwind information for this procedure. */
24876 tc_arm_frame_initial_instructions (void)
24878 cfi_add_CFA_def_cfa (REG_SP
, 0);
24880 #endif /* OBJ_ELF */
24882 /* Convert REGNAME to a DWARF-2 register number. */
24885 tc_arm_regname_to_dw2regnum (char *regname
)
24887 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
24891 /* PR 16694: Allow VFP registers as well. */
24892 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
24896 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
24905 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
24909 exp
.X_op
= O_secrel
;
24910 exp
.X_add_symbol
= symbol
;
24911 exp
.X_add_number
= 0;
24912 emit_expr (&exp
, size
);
24916 /* MD interface: Symbol and relocation handling. */
24918 /* Return the address within the segment that a PC-relative fixup is
24919 relative to. For ARM, PC-relative fixups applied to instructions
24920 are generally relative to the location of the fixup plus 8 bytes.
24921 Thumb branches are offset by 4, and Thumb loads relative to PC
24922 require special handling. */
24925 md_pcrel_from_section (fixS
* fixP
, segT seg
)
24927 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24929 /* If this is pc-relative and we are going to emit a relocation
24930 then we just want to put out any pipeline compensation that the linker
24931 will need. Otherwise we want to use the calculated base.
24932 For WinCE we skip the bias for externals as well, since this
24933 is how the MS ARM-CE assembler behaves and we want to be compatible. */
24935 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
24936 || (arm_force_relocation (fixP
)
24938 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
24944 switch (fixP
->fx_r_type
)
24946 /* PC relative addressing on the Thumb is slightly odd as the
24947 bottom two bits of the PC are forced to zero for the
24948 calculation. This happens *after* application of the
24949 pipeline offset. However, Thumb adrl already adjusts for
24950 this, so we need not do it again. */
24951 case BFD_RELOC_ARM_THUMB_ADD
:
24954 case BFD_RELOC_ARM_THUMB_OFFSET
:
24955 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
24956 case BFD_RELOC_ARM_T32_ADD_PC12
:
24957 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
24958 return (base
+ 4) & ~3;
24960 /* Thumb branches are simply offset by +4. */
24961 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
24962 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24963 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24964 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24965 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24966 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24967 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
24968 case BFD_RELOC_ARM_THUMB_BF17
:
24969 case BFD_RELOC_ARM_THUMB_BF19
:
24970 case BFD_RELOC_ARM_THUMB_BF13
:
24971 case BFD_RELOC_ARM_THUMB_LOOP12
:
24974 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24976 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24977 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24978 && ARM_IS_FUNC (fixP
->fx_addsy
)
24979 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
24980 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24983 /* BLX is like branches above, but forces the low two bits of PC to
24985 case BFD_RELOC_THUMB_PCREL_BLX
:
24987 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24988 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24989 && THUMB_IS_FUNC (fixP
->fx_addsy
)
24990 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
24991 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24992 return (base
+ 4) & ~3;
24994 /* ARM mode branches are offset by +8. However, the Windows CE
24995 loader expects the relocation not to take this into account. */
24996 case BFD_RELOC_ARM_PCREL_BLX
:
24998 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24999 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25000 && ARM_IS_FUNC (fixP
->fx_addsy
)
25001 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25002 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25005 case BFD_RELOC_ARM_PCREL_CALL
:
25007 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25008 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25009 && THUMB_IS_FUNC (fixP
->fx_addsy
)
25010 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25011 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25014 case BFD_RELOC_ARM_PCREL_BRANCH
:
25015 case BFD_RELOC_ARM_PCREL_JUMP
:
25016 case BFD_RELOC_ARM_PLT32
:
25018 /* When handling fixups immediately, because we have already
25019 discovered the value of a symbol, or the address of the frag involved
25020 we must account for the offset by +8, as the OS loader will never see the reloc.
25021 see fixup_segment() in write.c
25022 The S_IS_EXTERNAL test handles the case of global symbols.
25023 Those need the calculated base, not just the pipe compensation the linker will need. */
25025 && fixP
->fx_addsy
!= NULL
25026 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25027 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
25035 /* ARM mode loads relative to PC are also offset by +8. Unlike
25036 branches, the Windows CE loader *does* expect the relocation
25037 to take this into account. */
25038 case BFD_RELOC_ARM_OFFSET_IMM
:
25039 case BFD_RELOC_ARM_OFFSET_IMM8
:
25040 case BFD_RELOC_ARM_HWLITERAL
:
25041 case BFD_RELOC_ARM_LITERAL
:
25042 case BFD_RELOC_ARM_CP_OFF_IMM
:
25046 /* Other PC-relative relocations are un-offset. */
25052 static bfd_boolean flag_warn_syms
= TRUE
;
25055 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
25057 /* PR 18347 - Warn if the user attempts to create a symbol with the same
25058 name as an ARM instruction. Whilst strictly speaking it is allowed, it
25059 does mean that the resulting code might be very confusing to the reader.
25060 Also this warning can be triggered if the user omits an operand before
25061 an immediate address, eg:
25065 GAS treats this as an assignment of the value of the symbol foo to a
25066 symbol LDR, and so (without this code) it will not issue any kind of
25067 warning or error message.
25069 Note - ARM instructions are case-insensitive but the strings in the hash
25070 table are all stored in lower case, so we must first ensure that name is
25072 if (flag_warn_syms
&& arm_ops_hsh
)
25074 char * nbuf
= strdup (name
);
25077 for (p
= nbuf
; *p
; p
++)
25079 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
25081 static struct hash_control
* already_warned
= NULL
;
25083 if (already_warned
== NULL
)
25084 already_warned
= hash_new ();
25085 /* Only warn about the symbol once. To keep the code
25086 simple we let hash_insert do the lookup for us. */
25087 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
25088 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
25097 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
25098 Otherwise we have no need to default values of symbols. */
25101 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
25104 if (name
[0] == '_' && name
[1] == 'G'
25105 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
25109 if (symbol_find (name
))
25110 as_bad (_("GOT already in the symbol table"));
25112 GOT_symbol
= symbol_new (name
, undefined_section
,
25113 (valueT
) 0, & zero_address_frag
);
25123 /* Subroutine of md_apply_fix. Check to see if an immediate can be
25124 computed as two separate immediate values, added together. We
25125 already know that this value cannot be computed by just one ARM
25128 static unsigned int
25129 validate_immediate_twopart (unsigned int val
,
25130 unsigned int * highpart
)
25135 for (i
= 0; i
< 32; i
+= 2)
25136 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
25142 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
25144 else if (a
& 0xff0000)
25146 if (a
& 0xff000000)
25148 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
25152 gas_assert (a
& 0xff000000);
25153 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
25156 return (a
& 0xff) | (i
<< 7);
25163 validate_offset_imm (unsigned int val
, int hwse
)
25165 if ((hwse
&& val
> 255) || val
> 4095)
25170 /* Subroutine of md_apply_fix. Do those data_ops which can take a
25171 negative immediate constant by altering the instruction. A bit of
25176 by inverting the second operand, and
25179 by negating the second operand. */
25182 negate_data_op (unsigned long * instruction
,
25183 unsigned long value
)
25186 unsigned long negated
, inverted
;
25188 negated
= encode_arm_immediate (-value
);
25189 inverted
= encode_arm_immediate (~value
);
25191 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
25194 /* First negates. */
25195 case OPCODE_SUB
: /* ADD <-> SUB */
25196 new_inst
= OPCODE_ADD
;
25201 new_inst
= OPCODE_SUB
;
25205 case OPCODE_CMP
: /* CMP <-> CMN */
25206 new_inst
= OPCODE_CMN
;
25211 new_inst
= OPCODE_CMP
;
25215 /* Now Inverted ops. */
25216 case OPCODE_MOV
: /* MOV <-> MVN */
25217 new_inst
= OPCODE_MVN
;
25222 new_inst
= OPCODE_MOV
;
25226 case OPCODE_AND
: /* AND <-> BIC */
25227 new_inst
= OPCODE_BIC
;
25232 new_inst
= OPCODE_AND
;
25236 case OPCODE_ADC
: /* ADC <-> SBC */
25237 new_inst
= OPCODE_SBC
;
25242 new_inst
= OPCODE_ADC
;
25246 /* We cannot do anything. */
25251 if (value
== (unsigned) FAIL
)
25254 *instruction
&= OPCODE_MASK
;
25255 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
25259 /* Like negate_data_op, but for Thumb-2. */
25261 static unsigned int
25262 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
25266 unsigned int negated
, inverted
;
25268 negated
= encode_thumb32_immediate (-value
);
25269 inverted
= encode_thumb32_immediate (~value
);
25271 rd
= (*instruction
>> 8) & 0xf;
25272 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
25275 /* ADD <-> SUB. Includes CMP <-> CMN. */
25276 case T2_OPCODE_SUB
:
25277 new_inst
= T2_OPCODE_ADD
;
25281 case T2_OPCODE_ADD
:
25282 new_inst
= T2_OPCODE_SUB
;
25286 /* ORR <-> ORN. Includes MOV <-> MVN. */
25287 case T2_OPCODE_ORR
:
25288 new_inst
= T2_OPCODE_ORN
;
25292 case T2_OPCODE_ORN
:
25293 new_inst
= T2_OPCODE_ORR
;
25297 /* AND <-> BIC. TST has no inverted equivalent. */
25298 case T2_OPCODE_AND
:
25299 new_inst
= T2_OPCODE_BIC
;
25306 case T2_OPCODE_BIC
:
25307 new_inst
= T2_OPCODE_AND
;
25312 case T2_OPCODE_ADC
:
25313 new_inst
= T2_OPCODE_SBC
;
25317 case T2_OPCODE_SBC
:
25318 new_inst
= T2_OPCODE_ADC
;
25322 /* We cannot do anything. */
25327 if (value
== (unsigned int)FAIL
)
25330 *instruction
&= T2_OPCODE_MASK
;
25331 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
25335 /* Read a 32-bit thumb instruction from buf. */
25337 static unsigned long
25338 get_thumb32_insn (char * buf
)
25340 unsigned long insn
;
25341 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
25342 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25347 /* We usually want to set the low bit on the address of thumb function
25348 symbols. In particular .word foo - . should have the low bit set.
25349 Generic code tries to fold the difference of two symbols to
25350 a constant. Prevent this and force a relocation when the first symbols
25351 is a thumb function. */
25354 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
25356 if (op
== O_subtract
25357 && l
->X_op
== O_symbol
25358 && r
->X_op
== O_symbol
25359 && THUMB_IS_FUNC (l
->X_add_symbol
))
25361 l
->X_op
= O_subtract
;
25362 l
->X_op_symbol
= r
->X_add_symbol
;
25363 l
->X_add_number
-= r
->X_add_number
;
25367 /* Process as normal. */
25371 /* Encode Thumb2 unconditional branches and calls. The encoding
25372 for the 2 are identical for the immediate values. */
25375 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
25377 #define T2I1I2MASK ((1 << 13) | (1 << 11))
25380 addressT S
, I1
, I2
, lo
, hi
;
25382 S
= (value
>> 24) & 0x01;
25383 I1
= (value
>> 23) & 0x01;
25384 I2
= (value
>> 22) & 0x01;
25385 hi
= (value
>> 12) & 0x3ff;
25386 lo
= (value
>> 1) & 0x7ff;
25387 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25388 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25389 newval
|= (S
<< 10) | hi
;
25390 newval2
&= ~T2I1I2MASK
;
25391 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
25392 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25393 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25397 md_apply_fix (fixS
* fixP
,
25401 offsetT value
= * valP
;
25403 unsigned int newimm
;
25404 unsigned long temp
;
25406 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
25408 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
25410 /* Note whether this will delete the relocation. */
25412 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
25415 /* On a 64-bit host, silently truncate 'value' to 32 bits for
25416 consistency with the behaviour on 32-bit hosts. Remember value
25418 value
&= 0xffffffff;
25419 value
^= 0x80000000;
25420 value
-= 0x80000000;
25423 fixP
->fx_addnumber
= value
;
25425 /* Same treatment for fixP->fx_offset. */
25426 fixP
->fx_offset
&= 0xffffffff;
25427 fixP
->fx_offset
^= 0x80000000;
25428 fixP
->fx_offset
-= 0x80000000;
25430 switch (fixP
->fx_r_type
)
25432 case BFD_RELOC_NONE
:
25433 /* This will need to go in the object file. */
25437 case BFD_RELOC_ARM_IMMEDIATE
:
25438 /* We claim that this fixup has been processed here,
25439 even if in fact we generate an error because we do
25440 not have a reloc for it, so tc_gen_reloc will reject it. */
25443 if (fixP
->fx_addsy
)
25445 const char *msg
= 0;
25447 if (! S_IS_DEFINED (fixP
->fx_addsy
))
25448 msg
= _("undefined symbol %s used as an immediate value");
25449 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
25450 msg
= _("symbol %s is in a different section");
25451 else if (S_IS_WEAK (fixP
->fx_addsy
))
25452 msg
= _("symbol %s is weak and may be overridden later");
25456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25457 msg
, S_GET_NAME (fixP
->fx_addsy
));
25462 temp
= md_chars_to_number (buf
, INSN_SIZE
);
25464 /* If the offset is negative, we should use encoding A2 for ADR. */
25465 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
25466 newimm
= negate_data_op (&temp
, value
);
25469 newimm
= encode_arm_immediate (value
);
25471 /* If the instruction will fail, see if we can fix things up by
25472 changing the opcode. */
25473 if (newimm
== (unsigned int) FAIL
)
25474 newimm
= negate_data_op (&temp
, value
);
25475 /* MOV accepts both ARM modified immediate (A1 encoding) and
25476 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
25477 When disassembling, MOV is preferred when there is no encoding
25479 if (newimm
== (unsigned int) FAIL
25480 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
25481 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
25482 && !((temp
>> SBIT_SHIFT
) & 0x1)
25483 && value
>= 0 && value
<= 0xffff)
25485 /* Clear bits[23:20] to change encoding from A1 to A2. */
25486 temp
&= 0xff0fffff;
25487 /* Encoding high 4bits imm. Code below will encode the remaining
25489 temp
|= (value
& 0x0000f000) << 4;
25490 newimm
= value
& 0x00000fff;
25494 if (newimm
== (unsigned int) FAIL
)
25496 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25497 _("invalid constant (%lx) after fixup"),
25498 (unsigned long) value
);
25502 newimm
|= (temp
& 0xfffff000);
25503 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
25506 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
25508 unsigned int highpart
= 0;
25509 unsigned int newinsn
= 0xe1a00000; /* nop. */
25511 if (fixP
->fx_addsy
)
25513 const char *msg
= 0;
25515 if (! S_IS_DEFINED (fixP
->fx_addsy
))
25516 msg
= _("undefined symbol %s used as an immediate value");
25517 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
25518 msg
= _("symbol %s is in a different section");
25519 else if (S_IS_WEAK (fixP
->fx_addsy
))
25520 msg
= _("symbol %s is weak and may be overridden later");
25524 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25525 msg
, S_GET_NAME (fixP
->fx_addsy
));
25530 newimm
= encode_arm_immediate (value
);
25531 temp
= md_chars_to_number (buf
, INSN_SIZE
);
25533 /* If the instruction will fail, see if we can fix things up by
25534 changing the opcode. */
25535 if (newimm
== (unsigned int) FAIL
25536 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
25538 /* No ? OK - try using two ADD instructions to generate
25540 newimm
= validate_immediate_twopart (value
, & highpart
);
25542 /* Yes - then make sure that the second instruction is
25544 if (newimm
!= (unsigned int) FAIL
)
25546 /* Still No ? Try using a negated value. */
25547 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
25548 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
25549 /* Otherwise - give up. */
25552 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25553 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
25558 /* Replace the first operand in the 2nd instruction (which
25559 is the PC) with the destination register. We have
25560 already added in the PC in the first instruction and we
25561 do not want to do it again. */
25562 newinsn
&= ~ 0xf0000;
25563 newinsn
|= ((newinsn
& 0x0f000) << 4);
25566 newimm
|= (temp
& 0xfffff000);
25567 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
25569 highpart
|= (newinsn
& 0xfffff000);
25570 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
25574 case BFD_RELOC_ARM_OFFSET_IMM
:
25575 if (!fixP
->fx_done
&& seg
->use_rela_p
)
25577 /* Fall through. */
25579 case BFD_RELOC_ARM_LITERAL
:
25585 if (validate_offset_imm (value
, 0) == FAIL
)
25587 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
25588 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25589 _("invalid literal constant: pool needs to be closer"));
25591 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25592 _("bad immediate value for offset (%ld)"),
25597 newval
= md_chars_to_number (buf
, INSN_SIZE
);
25599 newval
&= 0xfffff000;
25602 newval
&= 0xff7ff000;
25603 newval
|= value
| (sign
? INDEX_UP
: 0);
25605 md_number_to_chars (buf
, newval
, INSN_SIZE
);
25608 case BFD_RELOC_ARM_OFFSET_IMM8
:
25609 case BFD_RELOC_ARM_HWLITERAL
:
25615 if (validate_offset_imm (value
, 1) == FAIL
)
25617 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
25618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25619 _("invalid literal constant: pool needs to be closer"));
25621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25622 _("bad immediate value for 8-bit offset (%ld)"),
25627 newval
= md_chars_to_number (buf
, INSN_SIZE
);
25629 newval
&= 0xfffff0f0;
25632 newval
&= 0xff7ff0f0;
25633 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
25635 md_number_to_chars (buf
, newval
, INSN_SIZE
);
25638 case BFD_RELOC_ARM_T32_OFFSET_U8
:
25639 if (value
< 0 || value
> 1020 || value
% 4 != 0)
25640 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25641 _("bad immediate value for offset (%ld)"), (long) value
);
25644 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
25646 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
25649 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
25650 /* This is a complicated relocation used for all varieties of Thumb32
25651 load/store instruction with immediate offset:
25653 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
25654 *4, optional writeback(W)
25655 (doubleword load/store)
25657 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
25658 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
25659 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
25660 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
25661 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
25663 Uppercase letters indicate bits that are already encoded at
25664 this point. Lowercase letters are our problem. For the
25665 second block of instructions, the secondary opcode nybble
25666 (bits 8..11) is present, and bit 23 is zero, even if this is
25667 a PC-relative operation. */
25668 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25670 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
25672 if ((newval
& 0xf0000000) == 0xe0000000)
25674 /* Doubleword load/store: 8-bit offset, scaled by 4. */
25676 newval
|= (1 << 23);
25679 if (value
% 4 != 0)
25681 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25682 _("offset not a multiple of 4"));
25688 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25689 _("offset out of range"));
25694 else if ((newval
& 0x000f0000) == 0x000f0000)
25696 /* PC-relative, 12-bit offset. */
25698 newval
|= (1 << 23);
25703 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25704 _("offset out of range"));
25709 else if ((newval
& 0x00000100) == 0x00000100)
25711 /* Writeback: 8-bit, +/- offset. */
25713 newval
|= (1 << 9);
25718 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25719 _("offset out of range"));
25724 else if ((newval
& 0x00000f00) == 0x00000e00)
25726 /* T-instruction: positive 8-bit offset. */
25727 if (value
< 0 || value
> 0xff)
25729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25730 _("offset out of range"));
25738 /* Positive 12-bit or negative 8-bit offset. */
25742 newval
|= (1 << 23);
25752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25753 _("offset out of range"));
25760 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
25761 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
25764 case BFD_RELOC_ARM_SHIFT_IMM
:
25765 newval
= md_chars_to_number (buf
, INSN_SIZE
);
25766 if (((unsigned long) value
) > 32
25768 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
25770 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25771 _("shift expression is too large"));
25776 /* Shifts of zero must be done as lsl. */
25778 else if (value
== 32)
25780 newval
&= 0xfffff07f;
25781 newval
|= (value
& 0x1f) << 7;
25782 md_number_to_chars (buf
, newval
, INSN_SIZE
);
25785 case BFD_RELOC_ARM_T32_IMMEDIATE
:
25786 case BFD_RELOC_ARM_T32_ADD_IMM
:
25787 case BFD_RELOC_ARM_T32_IMM12
:
25788 case BFD_RELOC_ARM_T32_ADD_PC12
:
25789 /* We claim that this fixup has been processed here,
25790 even if in fact we generate an error because we do
25791 not have a reloc for it, so tc_gen_reloc will reject it. */
25795 && ! S_IS_DEFINED (fixP
->fx_addsy
))
25797 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25798 _("undefined symbol %s used as an immediate value"),
25799 S_GET_NAME (fixP
->fx_addsy
));
25803 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25805 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
25808 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
25809 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
25810 Thumb2 modified immediate encoding (T2). */
25811 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
25812 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
25814 newimm
= encode_thumb32_immediate (value
);
25815 if (newimm
== (unsigned int) FAIL
)
25816 newimm
= thumb32_negate_data_op (&newval
, value
);
25818 if (newimm
== (unsigned int) FAIL
)
25820 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
25822 /* Turn add/sum into addw/subw. */
25823 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
25824 newval
= (newval
& 0xfeffffff) | 0x02000000;
25825 /* No flat 12-bit imm encoding for addsw/subsw. */
25826 if ((newval
& 0x00100000) == 0)
25828 /* 12 bit immediate for addw/subw. */
25832 newval
^= 0x00a00000;
25835 newimm
= (unsigned int) FAIL
;
25842 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
25843 UINT16 (T3 encoding), MOVW only accepts UINT16. When
25844 disassembling, MOV is preferred when there is no encoding
25846 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
25847 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
25848 but with the Rn field [19:16] set to 1111. */
25849 && (((newval
>> 16) & 0xf) == 0xf)
25850 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
25851 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
25852 && value
>= 0 && value
<= 0xffff)
25854 /* Toggle bit[25] to change encoding from T2 to T3. */
25856 /* Clear bits[19:16]. */
25857 newval
&= 0xfff0ffff;
25858 /* Encoding high 4bits imm. Code below will encode the
25859 remaining low 12bits. */
25860 newval
|= (value
& 0x0000f000) << 4;
25861 newimm
= value
& 0x00000fff;
25866 if (newimm
== (unsigned int)FAIL
)
25868 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25869 _("invalid constant (%lx) after fixup"),
25870 (unsigned long) value
);
25874 newval
|= (newimm
& 0x800) << 15;
25875 newval
|= (newimm
& 0x700) << 4;
25876 newval
|= (newimm
& 0x0ff);
25878 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
25879 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
25882 case BFD_RELOC_ARM_SMC
:
25883 if (((unsigned long) value
) > 0xffff)
25884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25885 _("invalid smc expression"));
25886 newval
= md_chars_to_number (buf
, INSN_SIZE
);
25887 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
25888 md_number_to_chars (buf
, newval
, INSN_SIZE
);
25891 case BFD_RELOC_ARM_HVC
:
25892 if (((unsigned long) value
) > 0xffff)
25893 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25894 _("invalid hvc expression"));
25895 newval
= md_chars_to_number (buf
, INSN_SIZE
);
25896 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
25897 md_number_to_chars (buf
, newval
, INSN_SIZE
);
25900 case BFD_RELOC_ARM_SWI
:
25901 if (fixP
->tc_fix_data
!= 0)
25903 if (((unsigned long) value
) > 0xff)
25904 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25905 _("invalid swi expression"));
25906 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25908 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25912 if (((unsigned long) value
) > 0x00ffffff)
25913 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25914 _("invalid swi expression"));
25915 newval
= md_chars_to_number (buf
, INSN_SIZE
);
25917 md_number_to_chars (buf
, newval
, INSN_SIZE
);
25921 case BFD_RELOC_ARM_MULTI
:
25922 if (((unsigned long) value
) > 0xffff)
25923 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25924 _("invalid expression in load/store multiple"));
25925 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
25926 md_number_to_chars (buf
, newval
, INSN_SIZE
);
25930 case BFD_RELOC_ARM_PCREL_CALL
:
25932 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25934 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25935 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25936 && THUMB_IS_FUNC (fixP
->fx_addsy
))
25937 /* Flip the bl to blx. This is a simple flip
25938 bit here because we generate PCREL_CALL for
25939 unconditional bls. */
25941 newval
= md_chars_to_number (buf
, INSN_SIZE
);
25942 newval
= newval
| 0x10000000;
25943 md_number_to_chars (buf
, newval
, INSN_SIZE
);
25949 goto arm_branch_common
;
25951 case BFD_RELOC_ARM_PCREL_JUMP
:
25952 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25954 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25955 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25956 && THUMB_IS_FUNC (fixP
->fx_addsy
))
25958 /* This would map to a bl<cond>, b<cond>,
25959 b<always> to a Thumb function. We
25960 need to force a relocation for this particular
25962 newval
= md_chars_to_number (buf
, INSN_SIZE
);
25965 /* Fall through. */
25967 case BFD_RELOC_ARM_PLT32
:
25969 case BFD_RELOC_ARM_PCREL_BRANCH
:
25971 goto arm_branch_common
;
25973 case BFD_RELOC_ARM_PCREL_BLX
:
25976 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25978 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25979 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25980 && ARM_IS_FUNC (fixP
->fx_addsy
))
25982 /* Flip the blx to a bl and warn. */
25983 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
25984 newval
= 0xeb000000;
25985 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
25986 _("blx to '%s' an ARM ISA state function changed to bl"),
25988 md_number_to_chars (buf
, newval
, INSN_SIZE
);
25994 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
25995 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
25999 /* We are going to store value (shifted right by two) in the
26000 instruction, in a 24 bit, signed field. Bits 26 through 32 either
26001 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
26004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26005 _("misaligned branch destination"));
26006 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
26007 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
26008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26010 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26012 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26013 newval
|= (value
>> 2) & 0x00ffffff;
26014 /* Set the H bit on BLX instructions. */
26018 newval
|= 0x01000000;
26020 newval
&= ~0x01000000;
26022 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26026 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
26027 /* CBZ can only branch forward. */
26029 /* Attempts to use CBZ to branch to the next instruction
26030 (which, strictly speaking, are prohibited) will be turned into
26033 FIXME: It may be better to remove the instruction completely and
26034 perform relaxation. */
26037 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26038 newval
= 0xbf00; /* NOP encoding T1 */
26039 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26046 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26048 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26049 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
26050 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26055 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
26056 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
26057 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26059 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26061 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26062 newval
|= (value
& 0x1ff) >> 1;
26063 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26067 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
26068 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
26069 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26071 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26073 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26074 newval
|= (value
& 0xfff) >> 1;
26075 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26079 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26081 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26082 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26083 && ARM_IS_FUNC (fixP
->fx_addsy
)
26084 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26086 /* Force a relocation for a branch 20 bits wide. */
26089 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
26090 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26091 _("conditional branch out of range"));
26093 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26096 addressT S
, J1
, J2
, lo
, hi
;
26098 S
= (value
& 0x00100000) >> 20;
26099 J2
= (value
& 0x00080000) >> 19;
26100 J1
= (value
& 0x00040000) >> 18;
26101 hi
= (value
& 0x0003f000) >> 12;
26102 lo
= (value
& 0x00000ffe) >> 1;
26104 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26105 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26106 newval
|= (S
<< 10) | hi
;
26107 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
26108 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26109 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
26113 case BFD_RELOC_THUMB_PCREL_BLX
:
26114 /* If there is a blx from a thumb state function to
26115 another thumb function flip this to a bl and warn
26119 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26120 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26121 && THUMB_IS_FUNC (fixP
->fx_addsy
))
26123 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
26124 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
26125 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
26127 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26128 newval
= newval
| 0x1000;
26129 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
26130 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
26135 goto thumb_bl_common
;
26137 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26138 /* A bl from Thumb state ISA to an internal ARM state function
26139 is converted to a blx. */
26141 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26142 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26143 && ARM_IS_FUNC (fixP
->fx_addsy
)
26144 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26146 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26147 newval
= newval
& ~0x1000;
26148 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
26149 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
26155 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
26156 /* For a BLX instruction, make sure that the relocation is rounded up
26157 to a word boundary. This follows the semantics of the instruction
26158 which specifies that bit 1 of the target address will come from bit
26159 1 of the base address. */
26160 value
= (value
+ 3) & ~ 3;
26163 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
26164 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
26165 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
26168 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
26170 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
26171 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26172 else if ((value
& ~0x1ffffff)
26173 && ((value
& ~0x1ffffff) != ~0x1ffffff))
26174 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26175 _("Thumb2 branch out of range"));
26178 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26179 encode_thumb2_b_bl_offset (buf
, value
);
26183 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26184 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
26185 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26187 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26188 encode_thumb2_b_bl_offset (buf
, value
);
26193 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26198 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26199 md_number_to_chars (buf
, value
, 2);
26203 case BFD_RELOC_ARM_TLS_CALL
:
26204 case BFD_RELOC_ARM_THM_TLS_CALL
:
26205 case BFD_RELOC_ARM_TLS_DESCSEQ
:
26206 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
26207 case BFD_RELOC_ARM_TLS_GOTDESC
:
26208 case BFD_RELOC_ARM_TLS_GD32
:
26209 case BFD_RELOC_ARM_TLS_LE32
:
26210 case BFD_RELOC_ARM_TLS_IE32
:
26211 case BFD_RELOC_ARM_TLS_LDM32
:
26212 case BFD_RELOC_ARM_TLS_LDO32
:
26213 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
26216 /* Same handling as above, but with the arm_fdpic guard. */
26217 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
26218 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
26219 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
26222 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
26226 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26227 _("Relocation supported only in FDPIC mode"));
26231 case BFD_RELOC_ARM_GOT32
:
26232 case BFD_RELOC_ARM_GOTOFF
:
26235 case BFD_RELOC_ARM_GOT_PREL
:
26236 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26237 md_number_to_chars (buf
, value
, 4);
26240 case BFD_RELOC_ARM_TARGET2
:
26241 /* TARGET2 is not partial-inplace, so we need to write the
26242 addend here for REL targets, because it won't be written out
26243 during reloc processing later. */
26244 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26245 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
26248 /* Relocations for FDPIC. */
26249 case BFD_RELOC_ARM_GOTFUNCDESC
:
26250 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
26251 case BFD_RELOC_ARM_FUNCDESC
:
26254 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26255 md_number_to_chars (buf
, 0, 4);
26259 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26260 _("Relocation supported only in FDPIC mode"));
26265 case BFD_RELOC_RVA
:
26267 case BFD_RELOC_ARM_TARGET1
:
26268 case BFD_RELOC_ARM_ROSEGREL32
:
26269 case BFD_RELOC_ARM_SBREL32
:
26270 case BFD_RELOC_32_PCREL
:
26272 case BFD_RELOC_32_SECREL
:
26274 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26276 /* For WinCE we only do this for pcrel fixups. */
26277 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
26279 md_number_to_chars (buf
, value
, 4);
26283 case BFD_RELOC_ARM_PREL31
:
26284 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26286 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
26287 if ((value
^ (value
>> 1)) & 0x40000000)
26289 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26290 _("rel31 relocation overflow"));
26292 newval
|= value
& 0x7fffffff;
26293 md_number_to_chars (buf
, newval
, 4);
26298 case BFD_RELOC_ARM_CP_OFF_IMM
:
26299 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26300 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
26301 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
26302 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26304 newval
= get_thumb32_insn (buf
);
26305 if ((newval
& 0x0f200f00) == 0x0d000900)
26307 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
26308 has permitted values that are multiples of 2, in the range 0
26310 if (value
< -510 || value
> 510 || (value
& 1))
26311 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26312 _("co-processor offset out of range"));
26314 else if ((newval
& 0xfe001f80) == 0xec000f80)
26316 if (value
< -511 || value
> 512 || (value
& 3))
26317 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26318 _("co-processor offset out of range"));
26320 else if (value
< -1023 || value
> 1023 || (value
& 3))
26321 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26322 _("co-processor offset out of range"));
26327 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
26328 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
26329 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26331 newval
= get_thumb32_insn (buf
);
26334 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
26335 newval
&= 0xffffff80;
26337 newval
&= 0xffffff00;
26341 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
26342 newval
&= 0xff7fff80;
26344 newval
&= 0xff7fff00;
26345 if ((newval
& 0x0f200f00) == 0x0d000900)
26347 /* This is a fp16 vstr/vldr.
26349 It requires the immediate offset in the instruction is shifted
26350 left by 1 to be a half-word offset.
26352 Here, left shift by 1 first, and later right shift by 2
26353 should get the right offset. */
26356 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
26358 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
26359 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
26360 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26362 put_thumb32_insn (buf
, newval
);
26365 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
26366 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
26367 if (value
< -255 || value
> 255)
26368 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26369 _("co-processor offset out of range"));
26371 goto cp_off_common
;
26373 case BFD_RELOC_ARM_THUMB_OFFSET
:
26374 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26375 /* Exactly what ranges, and where the offset is inserted depends
26376 on the type of instruction, we can establish this from the
26378 switch (newval
>> 12)
26380 case 4: /* PC load. */
26381 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
26382 forced to zero for these loads; md_pcrel_from has already
26383 compensated for this. */
26385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26386 _("invalid offset, target not word aligned (0x%08lX)"),
26387 (((unsigned long) fixP
->fx_frag
->fr_address
26388 + (unsigned long) fixP
->fx_where
) & ~3)
26389 + (unsigned long) value
);
26391 if (value
& ~0x3fc)
26392 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26393 _("invalid offset, value too big (0x%08lX)"),
26396 newval
|= value
>> 2;
26399 case 9: /* SP load/store. */
26400 if (value
& ~0x3fc)
26401 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26402 _("invalid offset, value too big (0x%08lX)"),
26404 newval
|= value
>> 2;
26407 case 6: /* Word load/store. */
26409 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26410 _("invalid offset, value too big (0x%08lX)"),
26412 newval
|= value
<< 4; /* 6 - 2. */
26415 case 7: /* Byte load/store. */
26417 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26418 _("invalid offset, value too big (0x%08lX)"),
26420 newval
|= value
<< 6;
26423 case 8: /* Halfword load/store. */
26425 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26426 _("invalid offset, value too big (0x%08lX)"),
26428 newval
|= value
<< 5; /* 6 - 1. */
26432 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26433 "Unable to process relocation for thumb opcode: %lx",
26434 (unsigned long) newval
);
26437 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26440 case BFD_RELOC_ARM_THUMB_ADD
:
26441 /* This is a complicated relocation, since we use it for all of
26442 the following immediate relocations:
26446 9bit ADD/SUB SP word-aligned
26447 10bit ADD PC/SP word-aligned
26449 The type of instruction being processed is encoded in the
26456 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26458 int rd
= (newval
>> 4) & 0xf;
26459 int rs
= newval
& 0xf;
26460 int subtract
= !!(newval
& 0x8000);
26462 /* Check for HI regs, only very restricted cases allowed:
26463 Adjusting SP, and using PC or SP to get an address. */
26464 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
26465 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
26466 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26467 _("invalid Hi register with immediate"));
26469 /* If value is negative, choose the opposite instruction. */
26473 subtract
= !subtract
;
26475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26476 _("immediate value out of range"));
26481 if (value
& ~0x1fc)
26482 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26483 _("invalid immediate for stack address calculation"));
26484 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
26485 newval
|= value
>> 2;
26487 else if (rs
== REG_PC
|| rs
== REG_SP
)
26489 /* PR gas/18541. If the addition is for a defined symbol
26490 within range of an ADR instruction then accept it. */
26493 && fixP
->fx_addsy
!= NULL
)
26497 if (! S_IS_DEFINED (fixP
->fx_addsy
)
26498 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
26499 || S_IS_WEAK (fixP
->fx_addsy
))
26501 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26502 _("address calculation needs a strongly defined nearby symbol"));
26506 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26508 /* Round up to the next 4-byte boundary. */
26513 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
26517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26518 _("symbol too far away"));
26528 if (subtract
|| value
& ~0x3fc)
26529 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26530 _("invalid immediate for address calculation (value = 0x%08lX)"),
26531 (unsigned long) (subtract
? - value
: value
));
26532 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
26534 newval
|= value
>> 2;
26539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26540 _("immediate value out of range"));
26541 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
26542 newval
|= (rd
<< 8) | value
;
26547 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26548 _("immediate value out of range"));
26549 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
26550 newval
|= rd
| (rs
<< 3) | (value
<< 6);
26553 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26556 case BFD_RELOC_ARM_THUMB_IMM
:
26557 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26558 if (value
< 0 || value
> 255)
26559 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26560 _("invalid immediate: %ld is out of range"),
26563 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26566 case BFD_RELOC_ARM_THUMB_SHIFT
:
26567 /* 5bit shift value (0..32). LSL cannot take 32. */
26568 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
26569 temp
= newval
& 0xf800;
26570 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
26571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26572 _("invalid shift value: %ld"), (long) value
);
26573 /* Shifts of zero must be encoded as LSL. */
26575 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
26576 /* Shifts of 32 are encoded as zero. */
26577 else if (value
== 32)
26579 newval
|= value
<< 6;
26580 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26583 case BFD_RELOC_VTABLE_INHERIT
:
26584 case BFD_RELOC_VTABLE_ENTRY
:
26588 case BFD_RELOC_ARM_MOVW
:
26589 case BFD_RELOC_ARM_MOVT
:
26590 case BFD_RELOC_ARM_THUMB_MOVW
:
26591 case BFD_RELOC_ARM_THUMB_MOVT
:
26592 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26594 /* REL format relocations are limited to a 16-bit addend. */
26595 if (!fixP
->fx_done
)
26597 if (value
< -0x8000 || value
> 0x7fff)
26598 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26599 _("offset out of range"));
26601 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
26602 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
26607 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
26608 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
26610 newval
= get_thumb32_insn (buf
);
26611 newval
&= 0xfbf08f00;
26612 newval
|= (value
& 0xf000) << 4;
26613 newval
|= (value
& 0x0800) << 15;
26614 newval
|= (value
& 0x0700) << 4;
26615 newval
|= (value
& 0x00ff);
26616 put_thumb32_insn (buf
, newval
);
26620 newval
= md_chars_to_number (buf
, 4);
26621 newval
&= 0xfff0f000;
26622 newval
|= value
& 0x0fff;
26623 newval
|= (value
& 0xf000) << 4;
26624 md_number_to_chars (buf
, newval
, 4);
26629 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
26630 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
26631 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
26632 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
26633 gas_assert (!fixP
->fx_done
);
26636 bfd_boolean is_mov
;
26637 bfd_vma encoded_addend
= value
;
26639 /* Check that addend can be encoded in instruction. */
26640 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
26641 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26642 _("the offset 0x%08lX is not representable"),
26643 (unsigned long) encoded_addend
);
26645 /* Extract the instruction. */
26646 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
26647 is_mov
= (insn
& 0xf800) == 0x2000;
26652 if (!seg
->use_rela_p
)
26653 insn
|= encoded_addend
;
26659 /* Extract the instruction. */
26660 /* Encoding is the following
26665 /* The following conditions must be true :
26670 rd
= (insn
>> 4) & 0xf;
26672 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
26673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26674 _("Unable to process relocation for thumb opcode: %lx"),
26675 (unsigned long) insn
);
26677 /* Encode as ADD immediate8 thumb 1 code. */
26678 insn
= 0x3000 | (rd
<< 8);
26680 /* Place the encoded addend into the first 8 bits of the
26682 if (!seg
->use_rela_p
)
26683 insn
|= encoded_addend
;
26686 /* Update the instruction. */
26687 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
26691 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
26692 case BFD_RELOC_ARM_ALU_PC_G0
:
26693 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
26694 case BFD_RELOC_ARM_ALU_PC_G1
:
26695 case BFD_RELOC_ARM_ALU_PC_G2
:
26696 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
26697 case BFD_RELOC_ARM_ALU_SB_G0
:
26698 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
26699 case BFD_RELOC_ARM_ALU_SB_G1
:
26700 case BFD_RELOC_ARM_ALU_SB_G2
:
26701 gas_assert (!fixP
->fx_done
);
26702 if (!seg
->use_rela_p
)
26705 bfd_vma encoded_addend
;
26706 bfd_vma addend_abs
= llabs (value
);
26708 /* Check that the absolute value of the addend can be
26709 expressed as an 8-bit constant plus a rotation. */
26710 encoded_addend
= encode_arm_immediate (addend_abs
);
26711 if (encoded_addend
== (unsigned int) FAIL
)
26712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26713 _("the offset 0x%08lX is not representable"),
26714 (unsigned long) addend_abs
);
26716 /* Extract the instruction. */
26717 insn
= md_chars_to_number (buf
, INSN_SIZE
);
26719 /* If the addend is positive, use an ADD instruction.
26720 Otherwise use a SUB. Take care not to destroy the S bit. */
26721 insn
&= 0xff1fffff;
26727 /* Place the encoded addend into the first 12 bits of the
26729 insn
&= 0xfffff000;
26730 insn
|= encoded_addend
;
26732 /* Update the instruction. */
26733 md_number_to_chars (buf
, insn
, INSN_SIZE
);
26737 case BFD_RELOC_ARM_LDR_PC_G0
:
26738 case BFD_RELOC_ARM_LDR_PC_G1
:
26739 case BFD_RELOC_ARM_LDR_PC_G2
:
26740 case BFD_RELOC_ARM_LDR_SB_G0
:
26741 case BFD_RELOC_ARM_LDR_SB_G1
:
26742 case BFD_RELOC_ARM_LDR_SB_G2
:
26743 gas_assert (!fixP
->fx_done
);
26744 if (!seg
->use_rela_p
)
26747 bfd_vma addend_abs
= llabs (value
);
26749 /* Check that the absolute value of the addend can be
26750 encoded in 12 bits. */
26751 if (addend_abs
>= 0x1000)
26752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26753 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
26754 (unsigned long) addend_abs
);
26756 /* Extract the instruction. */
26757 insn
= md_chars_to_number (buf
, INSN_SIZE
);
26759 /* If the addend is negative, clear bit 23 of the instruction.
26760 Otherwise set it. */
26762 insn
&= ~(1 << 23);
26766 /* Place the absolute value of the addend into the first 12 bits
26767 of the instruction. */
26768 insn
&= 0xfffff000;
26769 insn
|= addend_abs
;
26771 /* Update the instruction. */
26772 md_number_to_chars (buf
, insn
, INSN_SIZE
);
26776 case BFD_RELOC_ARM_LDRS_PC_G0
:
26777 case BFD_RELOC_ARM_LDRS_PC_G1
:
26778 case BFD_RELOC_ARM_LDRS_PC_G2
:
26779 case BFD_RELOC_ARM_LDRS_SB_G0
:
26780 case BFD_RELOC_ARM_LDRS_SB_G1
:
26781 case BFD_RELOC_ARM_LDRS_SB_G2
:
26782 gas_assert (!fixP
->fx_done
);
26783 if (!seg
->use_rela_p
)
26786 bfd_vma addend_abs
= llabs (value
);
26788 /* Check that the absolute value of the addend can be
26789 encoded in 8 bits. */
26790 if (addend_abs
>= 0x100)
26791 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26792 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
26793 (unsigned long) addend_abs
);
26795 /* Extract the instruction. */
26796 insn
= md_chars_to_number (buf
, INSN_SIZE
);
26798 /* If the addend is negative, clear bit 23 of the instruction.
26799 Otherwise set it. */
26801 insn
&= ~(1 << 23);
26805 /* Place the first four bits of the absolute value of the addend
26806 into the first 4 bits of the instruction, and the remaining
26807 four into bits 8 .. 11. */
26808 insn
&= 0xfffff0f0;
26809 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
26811 /* Update the instruction. */
26812 md_number_to_chars (buf
, insn
, INSN_SIZE
);
26816 case BFD_RELOC_ARM_LDC_PC_G0
:
26817 case BFD_RELOC_ARM_LDC_PC_G1
:
26818 case BFD_RELOC_ARM_LDC_PC_G2
:
26819 case BFD_RELOC_ARM_LDC_SB_G0
:
26820 case BFD_RELOC_ARM_LDC_SB_G1
:
26821 case BFD_RELOC_ARM_LDC_SB_G2
:
26822 gas_assert (!fixP
->fx_done
);
26823 if (!seg
->use_rela_p
)
26826 bfd_vma addend_abs
= llabs (value
);
26828 /* Check that the absolute value of the addend is a multiple of
26829 four and, when divided by four, fits in 8 bits. */
26830 if (addend_abs
& 0x3)
26831 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26832 _("bad offset 0x%08lX (must be word-aligned)"),
26833 (unsigned long) addend_abs
);
26835 if ((addend_abs
>> 2) > 0xff)
26836 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26837 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
26838 (unsigned long) addend_abs
);
26840 /* Extract the instruction. */
26841 insn
= md_chars_to_number (buf
, INSN_SIZE
);
26843 /* If the addend is negative, clear bit 23 of the instruction.
26844 Otherwise set it. */
26846 insn
&= ~(1 << 23);
26850 /* Place the addend (divided by four) into the first eight
26851 bits of the instruction. */
26852 insn
&= 0xfffffff0;
26853 insn
|= addend_abs
>> 2;
26855 /* Update the instruction. */
26856 md_number_to_chars (buf
, insn
, INSN_SIZE
);
26860 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26862 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26863 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26864 && ARM_IS_FUNC (fixP
->fx_addsy
)
26865 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
26867 /* Force a relocation for a branch 5 bits wide. */
26870 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
26871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26874 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26876 addressT boff
= value
>> 1;
26878 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26879 newval
|= (boff
<< 7);
26880 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26884 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
26886 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26887 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26888 && ARM_IS_FUNC (fixP
->fx_addsy
)
26889 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
26893 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
26894 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26895 _("branch out of range"));
26897 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26899 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26901 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
26902 addressT diff
= value
- boff
;
26906 newval
|= 1 << 1; /* T bit. */
26908 else if (diff
!= 2)
26910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26911 _("out of range label-relative fixup value"));
26913 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26917 case BFD_RELOC_ARM_THUMB_BF17
:
26919 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26920 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26921 && ARM_IS_FUNC (fixP
->fx_addsy
)
26922 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
26924 /* Force a relocation for a branch 17 bits wide. */
26928 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
26929 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26932 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26935 addressT immA
, immB
, immC
;
26937 immA
= (value
& 0x0001f000) >> 12;
26938 immB
= (value
& 0x00000ffc) >> 2;
26939 immC
= (value
& 0x00000002) >> 1;
26941 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26942 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26944 newval2
|= (immC
<< 11) | (immB
<< 1);
26945 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26946 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
26950 case BFD_RELOC_ARM_THUMB_BF19
:
26952 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26953 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26954 && ARM_IS_FUNC (fixP
->fx_addsy
)
26955 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
26957 /* Force a relocation for a branch 19 bits wide. */
26961 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
26962 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26965 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26968 addressT immA
, immB
, immC
;
26970 immA
= (value
& 0x0007f000) >> 12;
26971 immB
= (value
& 0x00000ffc) >> 2;
26972 immC
= (value
& 0x00000002) >> 1;
26974 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26975 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26977 newval2
|= (immC
<< 11) | (immB
<< 1);
26978 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26979 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
26983 case BFD_RELOC_ARM_THUMB_BF13
:
26985 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26986 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26987 && ARM_IS_FUNC (fixP
->fx_addsy
)
26988 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
26990 /* Force a relocation for a branch 13 bits wide. */
26994 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
26995 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26998 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27001 addressT immA
, immB
, immC
;
27003 immA
= (value
& 0x00001000) >> 12;
27004 immB
= (value
& 0x00000ffc) >> 2;
27005 immC
= (value
& 0x00000002) >> 1;
27007 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27008 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27010 newval2
|= (immC
<< 11) | (immB
<< 1);
27011 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27012 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27016 case BFD_RELOC_ARM_THUMB_LOOP12
:
27018 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27019 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27020 && ARM_IS_FUNC (fixP
->fx_addsy
)
27021 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27023 /* Force a relocation for a branch 12 bits wide. */
27027 bfd_vma insn
= get_thumb32_insn (buf
);
27028 /* le lr, <label> or le <label> */
27029 if (((insn
& 0xffffffff) == 0xf00fc001)
27030 || ((insn
& 0xffffffff) == 0xf02fc001))
27033 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
27034 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27036 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27038 addressT imml
, immh
;
27040 immh
= (value
& 0x00000ffc) >> 2;
27041 imml
= (value
& 0x00000002) >> 1;
27043 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27044 newval
|= (imml
<< 11) | (immh
<< 1);
27045 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
27049 case BFD_RELOC_ARM_V4BX
:
27050 /* This will need to go in the object file. */
27054 case BFD_RELOC_UNUSED
:
27056 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27057 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
27061 /* Translate internal representation of relocation info to BFD target
27065 tc_gen_reloc (asection
*section
, fixS
*fixp
)
27068 bfd_reloc_code_real_type code
;
27070 reloc
= XNEW (arelent
);
27072 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
27073 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
27074 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
27076 if (fixp
->fx_pcrel
)
27078 if (section
->use_rela_p
)
27079 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
27081 fixp
->fx_offset
= reloc
->address
;
27083 reloc
->addend
= fixp
->fx_offset
;
27085 switch (fixp
->fx_r_type
)
27088 if (fixp
->fx_pcrel
)
27090 code
= BFD_RELOC_8_PCREL
;
27093 /* Fall through. */
27096 if (fixp
->fx_pcrel
)
27098 code
= BFD_RELOC_16_PCREL
;
27101 /* Fall through. */
27104 if (fixp
->fx_pcrel
)
27106 code
= BFD_RELOC_32_PCREL
;
27109 /* Fall through. */
27111 case BFD_RELOC_ARM_MOVW
:
27112 if (fixp
->fx_pcrel
)
27114 code
= BFD_RELOC_ARM_MOVW_PCREL
;
27117 /* Fall through. */
27119 case BFD_RELOC_ARM_MOVT
:
27120 if (fixp
->fx_pcrel
)
27122 code
= BFD_RELOC_ARM_MOVT_PCREL
;
27125 /* Fall through. */
27127 case BFD_RELOC_ARM_THUMB_MOVW
:
27128 if (fixp
->fx_pcrel
)
27130 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
27133 /* Fall through. */
27135 case BFD_RELOC_ARM_THUMB_MOVT
:
27136 if (fixp
->fx_pcrel
)
27138 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
27141 /* Fall through. */
27143 case BFD_RELOC_NONE
:
27144 case BFD_RELOC_ARM_PCREL_BRANCH
:
27145 case BFD_RELOC_ARM_PCREL_BLX
:
27146 case BFD_RELOC_RVA
:
27147 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27148 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27149 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27150 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27151 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27152 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27153 case BFD_RELOC_VTABLE_ENTRY
:
27154 case BFD_RELOC_VTABLE_INHERIT
:
27156 case BFD_RELOC_32_SECREL
:
27158 code
= fixp
->fx_r_type
;
27161 case BFD_RELOC_THUMB_PCREL_BLX
:
27163 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27164 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27167 code
= BFD_RELOC_THUMB_PCREL_BLX
;
27170 case BFD_RELOC_ARM_LITERAL
:
27171 case BFD_RELOC_ARM_HWLITERAL
:
27172 /* If this is called then the a literal has
27173 been referenced across a section boundary. */
27174 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27175 _("literal referenced across section boundary"));
27179 case BFD_RELOC_ARM_TLS_CALL
:
27180 case BFD_RELOC_ARM_THM_TLS_CALL
:
27181 case BFD_RELOC_ARM_TLS_DESCSEQ
:
27182 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
27183 case BFD_RELOC_ARM_GOT32
:
27184 case BFD_RELOC_ARM_GOTOFF
:
27185 case BFD_RELOC_ARM_GOT_PREL
:
27186 case BFD_RELOC_ARM_PLT32
:
27187 case BFD_RELOC_ARM_TARGET1
:
27188 case BFD_RELOC_ARM_ROSEGREL32
:
27189 case BFD_RELOC_ARM_SBREL32
:
27190 case BFD_RELOC_ARM_PREL31
:
27191 case BFD_RELOC_ARM_TARGET2
:
27192 case BFD_RELOC_ARM_TLS_LDO32
:
27193 case BFD_RELOC_ARM_PCREL_CALL
:
27194 case BFD_RELOC_ARM_PCREL_JUMP
:
27195 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
27196 case BFD_RELOC_ARM_ALU_PC_G0
:
27197 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
27198 case BFD_RELOC_ARM_ALU_PC_G1
:
27199 case BFD_RELOC_ARM_ALU_PC_G2
:
27200 case BFD_RELOC_ARM_LDR_PC_G0
:
27201 case BFD_RELOC_ARM_LDR_PC_G1
:
27202 case BFD_RELOC_ARM_LDR_PC_G2
:
27203 case BFD_RELOC_ARM_LDRS_PC_G0
:
27204 case BFD_RELOC_ARM_LDRS_PC_G1
:
27205 case BFD_RELOC_ARM_LDRS_PC_G2
:
27206 case BFD_RELOC_ARM_LDC_PC_G0
:
27207 case BFD_RELOC_ARM_LDC_PC_G1
:
27208 case BFD_RELOC_ARM_LDC_PC_G2
:
27209 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
27210 case BFD_RELOC_ARM_ALU_SB_G0
:
27211 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
27212 case BFD_RELOC_ARM_ALU_SB_G1
:
27213 case BFD_RELOC_ARM_ALU_SB_G2
:
27214 case BFD_RELOC_ARM_LDR_SB_G0
:
27215 case BFD_RELOC_ARM_LDR_SB_G1
:
27216 case BFD_RELOC_ARM_LDR_SB_G2
:
27217 case BFD_RELOC_ARM_LDRS_SB_G0
:
27218 case BFD_RELOC_ARM_LDRS_SB_G1
:
27219 case BFD_RELOC_ARM_LDRS_SB_G2
:
27220 case BFD_RELOC_ARM_LDC_SB_G0
:
27221 case BFD_RELOC_ARM_LDC_SB_G1
:
27222 case BFD_RELOC_ARM_LDC_SB_G2
:
27223 case BFD_RELOC_ARM_V4BX
:
27224 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
27225 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
27226 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
27227 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
27228 case BFD_RELOC_ARM_GOTFUNCDESC
:
27229 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
27230 case BFD_RELOC_ARM_FUNCDESC
:
27231 case BFD_RELOC_ARM_THUMB_BF17
:
27232 case BFD_RELOC_ARM_THUMB_BF19
:
27233 case BFD_RELOC_ARM_THUMB_BF13
:
27234 code
= fixp
->fx_r_type
;
27237 case BFD_RELOC_ARM_TLS_GOTDESC
:
27238 case BFD_RELOC_ARM_TLS_GD32
:
27239 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
27240 case BFD_RELOC_ARM_TLS_LE32
:
27241 case BFD_RELOC_ARM_TLS_IE32
:
27242 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
27243 case BFD_RELOC_ARM_TLS_LDM32
:
27244 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
27245 /* BFD will include the symbol's address in the addend.
27246 But we don't want that, so subtract it out again here. */
27247 if (!S_IS_COMMON (fixp
->fx_addsy
))
27248 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
27249 code
= fixp
->fx_r_type
;
27253 case BFD_RELOC_ARM_IMMEDIATE
:
27254 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27255 _("internal relocation (type: IMMEDIATE) not fixed up"));
27258 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27259 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27260 _("ADRL used for a symbol not defined in the same file"));
27263 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27264 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27265 case BFD_RELOC_ARM_THUMB_LOOP12
:
27266 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27267 _("%s used for a symbol not defined in the same file"),
27268 bfd_get_reloc_code_name (fixp
->fx_r_type
));
27271 case BFD_RELOC_ARM_OFFSET_IMM
:
27272 if (section
->use_rela_p
)
27274 code
= fixp
->fx_r_type
;
27278 if (fixp
->fx_addsy
!= NULL
27279 && !S_IS_DEFINED (fixp
->fx_addsy
)
27280 && S_IS_LOCAL (fixp
->fx_addsy
))
27282 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27283 _("undefined local label `%s'"),
27284 S_GET_NAME (fixp
->fx_addsy
));
27288 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27289 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
27296 switch (fixp
->fx_r_type
)
27298 case BFD_RELOC_NONE
: type
= "NONE"; break;
27299 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
27300 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
27301 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
27302 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
27303 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
27304 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
27305 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
27306 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
27307 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
27308 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
27309 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
27310 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
27311 default: type
= _("<unknown>"); break;
27313 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27314 _("cannot represent %s relocation in this object file format"),
27321 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
27323 && fixp
->fx_addsy
== GOT_symbol
)
27325 code
= BFD_RELOC_ARM_GOTPC
;
27326 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
27330 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
27332 if (reloc
->howto
== NULL
)
27334 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27335 _("cannot represent %s relocation in this object file format"),
27336 bfd_get_reloc_code_name (code
));
27340 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
27341 vtable entry to be used in the relocation's section offset. */
27342 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
27343 reloc
->address
= fixp
->fx_offset
;
27348 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
27351 cons_fix_new_arm (fragS
* frag
,
27355 bfd_reloc_code_real_type reloc
)
27360 FIXME: @@ Should look at CPU word size. */
27364 reloc
= BFD_RELOC_8
;
27367 reloc
= BFD_RELOC_16
;
27371 reloc
= BFD_RELOC_32
;
27374 reloc
= BFD_RELOC_64
;
27379 if (exp
->X_op
== O_secrel
)
27381 exp
->X_op
= O_symbol
;
27382 reloc
= BFD_RELOC_32_SECREL
;
27386 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
27389 #if defined (OBJ_COFF)
27391 arm_validate_fix (fixS
* fixP
)
27393 /* If the destination of the branch is a defined symbol which does not have
27394 the THUMB_FUNC attribute, then we must be calling a function which has
27395 the (interfacearm) attribute. We look for the Thumb entry point to that
27396 function and change the branch to refer to that function instead. */
27397 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
27398 && fixP
->fx_addsy
!= NULL
27399 && S_IS_DEFINED (fixP
->fx_addsy
)
27400 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
27402 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
27409 arm_force_relocation (struct fix
* fixp
)
27411 #if defined (OBJ_COFF) && defined (TE_PE)
27412 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
27416 /* In case we have a call or a branch to a function in ARM ISA mode from
27417 a thumb function or vice-versa force the relocation. These relocations
27418 are cleared off for some cores that might have blx and simple transformations
27422 switch (fixp
->fx_r_type
)
27424 case BFD_RELOC_ARM_PCREL_JUMP
:
27425 case BFD_RELOC_ARM_PCREL_CALL
:
27426 case BFD_RELOC_THUMB_PCREL_BLX
:
27427 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
27431 case BFD_RELOC_ARM_PCREL_BLX
:
27432 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27433 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27434 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27435 if (ARM_IS_FUNC (fixp
->fx_addsy
))
27444 /* Resolve these relocations even if the symbol is extern or weak.
27445 Technically this is probably wrong due to symbol preemption.
27446 In practice these relocations do not have enough range to be useful
27447 at dynamic link time, and some code (e.g. in the Linux kernel)
27448 expects these references to be resolved. */
27449 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
27450 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
27451 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
27452 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
27453 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27454 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
27455 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
27456 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
27457 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27458 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
27459 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
27460 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
27461 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
27462 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
27465 /* Always leave these relocations for the linker. */
27466 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
27467 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
27468 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
27471 /* Always generate relocations against function symbols. */
27472 if (fixp
->fx_r_type
== BFD_RELOC_32
27474 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
27477 return generic_force_reloc (fixp
);
27480 #if defined (OBJ_ELF) || defined (OBJ_COFF)
27481 /* Relocations against function names must be left unadjusted,
27482 so that the linker can use this information to generate interworking
27483 stubs. The MIPS version of this function
27484 also prevents relocations that are mips-16 specific, but I do not
27485 know why it does this.
27488 There is one other problem that ought to be addressed here, but
27489 which currently is not: Taking the address of a label (rather
27490 than a function) and then later jumping to that address. Such
27491 addresses also ought to have their bottom bit set (assuming that
27492 they reside in Thumb code), but at the moment they will not. */
27495 arm_fix_adjustable (fixS
* fixP
)
27497 if (fixP
->fx_addsy
== NULL
)
27500 /* Preserve relocations against symbols with function type. */
27501 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
27504 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
27505 && fixP
->fx_subsy
== NULL
)
27508 /* We need the symbol name for the VTABLE entries. */
27509 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
27510 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
27513 /* Don't allow symbols to be discarded on GOT related relocs. */
27514 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
27515 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
27516 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
27517 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
27518 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
27519 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
27520 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
27521 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
27522 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
27523 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
27524 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
27525 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
27526 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
27527 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
27528 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
27529 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
27530 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
27533 /* Similarly for group relocations. */
27534 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
27535 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
27536 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
27539 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
27540 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
27541 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
27542 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
27543 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
27544 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
27545 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
27546 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
27547 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
27550 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
27551 offsets, so keep these symbols. */
27552 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
27553 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
27558 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
27562 elf32_arm_target_format (void)
27565 return (target_big_endian
27566 ? "elf32-bigarm-symbian"
27567 : "elf32-littlearm-symbian");
27568 #elif defined (TE_VXWORKS)
27569 return (target_big_endian
27570 ? "elf32-bigarm-vxworks"
27571 : "elf32-littlearm-vxworks");
27572 #elif defined (TE_NACL)
27573 return (target_big_endian
27574 ? "elf32-bigarm-nacl"
27575 : "elf32-littlearm-nacl");
27579 if (target_big_endian
)
27580 return "elf32-bigarm-fdpic";
27582 return "elf32-littlearm-fdpic";
27586 if (target_big_endian
)
27587 return "elf32-bigarm";
27589 return "elf32-littlearm";
27595 armelf_frob_symbol (symbolS
* symp
,
27598 elf_frob_symbol (symp
, puntp
);
27602 /* MD interface: Finalization. */
27607 literal_pool
* pool
;
27609 /* Ensure that all the predication blocks are properly closed. */
27610 check_pred_blocks_finished ();
27612 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
27614 /* Put it at the end of the relevant section. */
27615 subseg_set (pool
->section
, pool
->sub_section
);
27617 arm_elf_change_section ();
27624 /* Remove any excess mapping symbols generated for alignment frags in
27625 SEC. We may have created a mapping symbol before a zero byte
27626 alignment; remove it if there's a mapping symbol after the
27629 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
27630 void *dummy ATTRIBUTE_UNUSED
)
27632 segment_info_type
*seginfo
= seg_info (sec
);
27635 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
27638 for (fragp
= seginfo
->frchainP
->frch_root
;
27640 fragp
= fragp
->fr_next
)
27642 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
27643 fragS
*next
= fragp
->fr_next
;
27645 /* Variable-sized frags have been converted to fixed size by
27646 this point. But if this was variable-sized to start with,
27647 there will be a fixed-size frag after it. So don't handle
27649 if (sym
== NULL
|| next
== NULL
)
27652 if (S_GET_VALUE (sym
) < next
->fr_address
)
27653 /* Not at the end of this frag. */
27655 know (S_GET_VALUE (sym
) == next
->fr_address
);
27659 if (next
->tc_frag_data
.first_map
!= NULL
)
27661 /* Next frag starts with a mapping symbol. Discard this
27663 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
27667 if (next
->fr_next
== NULL
)
27669 /* This mapping symbol is at the end of the section. Discard
27671 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
27672 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
27676 /* As long as we have empty frags without any mapping symbols,
27678 /* If the next frag is non-empty and does not start with a
27679 mapping symbol, then this mapping symbol is required. */
27680 if (next
->fr_address
!= next
->fr_next
->fr_address
)
27683 next
= next
->fr_next
;
27685 while (next
!= NULL
);
27690 /* Adjust the symbol table. This marks Thumb symbols as distinct from
27694 arm_adjust_symtab (void)
27699 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
27701 if (ARM_IS_THUMB (sym
))
27703 if (THUMB_IS_FUNC (sym
))
27705 /* Mark the symbol as a Thumb function. */
27706 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
27707 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
27708 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
27710 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
27711 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
27713 as_bad (_("%s: unexpected function type: %d"),
27714 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
27716 else switch (S_GET_STORAGE_CLASS (sym
))
27719 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
27722 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
27725 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
27733 if (ARM_IS_INTERWORK (sym
))
27734 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
27741 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
27743 if (ARM_IS_THUMB (sym
))
27745 elf_symbol_type
* elf_sym
;
27747 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
27748 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
27750 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
27751 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
27753 /* If it's a .thumb_func, declare it as so,
27754 otherwise tag label as .code 16. */
27755 if (THUMB_IS_FUNC (sym
))
27756 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
27757 ST_BRANCH_TO_THUMB
);
27758 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
27759 elf_sym
->internal_elf_sym
.st_info
=
27760 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
27765 /* Remove any overlapping mapping symbols generated by alignment frags. */
27766 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
27767 /* Now do generic ELF adjustments. */
27768 elf_adjust_symtab ();
27772 /* MD interface: Initialization. */
27775 set_constant_flonums (void)
27779 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
27780 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
27784 /* Auto-select Thumb mode if it's the only available instruction set for the
27785 given architecture. */
27788 autoselect_thumb_from_cpu_variant (void)
27790 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
27791 opcode_select (16);
27800 if ( (arm_ops_hsh
= hash_new ()) == NULL
27801 || (arm_cond_hsh
= hash_new ()) == NULL
27802 || (arm_vcond_hsh
= hash_new ()) == NULL
27803 || (arm_shift_hsh
= hash_new ()) == NULL
27804 || (arm_psr_hsh
= hash_new ()) == NULL
27805 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
27806 || (arm_reg_hsh
= hash_new ()) == NULL
27807 || (arm_reloc_hsh
= hash_new ()) == NULL
27808 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
27809 as_fatal (_("virtual memory exhausted"));
27811 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
27812 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
27813 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
27814 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
27815 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
27816 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
27817 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
27818 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
27819 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
27820 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
27821 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
27822 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
27823 (void *) (v7m_psrs
+ i
));
27824 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
27825 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
27827 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
27829 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
27830 (void *) (barrier_opt_names
+ i
));
27832 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
27834 struct reloc_entry
* entry
= reloc_names
+ i
;
27836 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
27837 /* This makes encode_branch() use the EABI versions of this relocation. */
27838 entry
->reloc
= BFD_RELOC_UNUSED
;
27840 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
27844 set_constant_flonums ();
27846 /* Set the cpu variant based on the command-line options. We prefer
27847 -mcpu= over -march= if both are set (as for GCC); and we prefer
27848 -mfpu= over any other way of setting the floating point unit.
27849 Use of legacy options with new options are faulted. */
27852 if (mcpu_cpu_opt
|| march_cpu_opt
)
27853 as_bad (_("use of old and new-style options to set CPU type"));
27855 selected_arch
= *legacy_cpu
;
27857 else if (mcpu_cpu_opt
)
27859 selected_arch
= *mcpu_cpu_opt
;
27860 selected_ext
= *mcpu_ext_opt
;
27862 else if (march_cpu_opt
)
27864 selected_arch
= *march_cpu_opt
;
27865 selected_ext
= *march_ext_opt
;
27867 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
27872 as_bad (_("use of old and new-style options to set FPU type"));
27874 selected_fpu
= *legacy_fpu
;
27877 selected_fpu
= *mfpu_opt
;
27880 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
27881 || defined (TE_NetBSD) || defined (TE_VXWORKS))
27882 /* Some environments specify a default FPU. If they don't, infer it
27883 from the processor. */
27885 selected_fpu
= *mcpu_fpu_opt
;
27886 else if (march_fpu_opt
)
27887 selected_fpu
= *march_fpu_opt
;
27889 selected_fpu
= fpu_default
;
27893 if (ARM_FEATURE_ZERO (selected_fpu
))
27895 if (!no_cpu_selected ())
27896 selected_fpu
= fpu_default
;
27898 selected_fpu
= fpu_arch_fpa
;
27902 if (ARM_FEATURE_ZERO (selected_arch
))
27904 selected_arch
= cpu_default
;
27905 selected_cpu
= selected_arch
;
27907 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27909 /* Autodection of feature mode: allow all features in cpu_variant but leave
27910 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
27911 after all instruction have been processed and we can decide what CPU
27912 should be selected. */
27913 if (ARM_FEATURE_ZERO (selected_arch
))
27914 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
27916 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27919 autoselect_thumb_from_cpu_variant ();
27921 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
27923 #if defined OBJ_COFF || defined OBJ_ELF
27925 unsigned int flags
= 0;
27927 #if defined OBJ_ELF
27928 flags
= meabi_flags
;
27930 switch (meabi_flags
)
27932 case EF_ARM_EABI_UNKNOWN
:
27934 /* Set the flags in the private structure. */
27935 if (uses_apcs_26
) flags
|= F_APCS26
;
27936 if (support_interwork
) flags
|= F_INTERWORK
;
27937 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
27938 if (pic_code
) flags
|= F_PIC
;
27939 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
27940 flags
|= F_SOFT_FLOAT
;
27942 switch (mfloat_abi_opt
)
27944 case ARM_FLOAT_ABI_SOFT
:
27945 case ARM_FLOAT_ABI_SOFTFP
:
27946 flags
|= F_SOFT_FLOAT
;
27949 case ARM_FLOAT_ABI_HARD
:
27950 if (flags
& F_SOFT_FLOAT
)
27951 as_bad (_("hard-float conflicts with specified fpu"));
27955 /* Using pure-endian doubles (even if soft-float). */
27956 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
27957 flags
|= F_VFP_FLOAT
;
27959 #if defined OBJ_ELF
27960 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
27961 flags
|= EF_ARM_MAVERICK_FLOAT
;
27964 case EF_ARM_EABI_VER4
:
27965 case EF_ARM_EABI_VER5
:
27966 /* No additional flags to set. */
27973 bfd_set_private_flags (stdoutput
, flags
);
27975 /* We have run out flags in the COFF header to encode the
27976 status of ATPCS support, so instead we create a dummy,
27977 empty, debug section called .arm.atpcs. */
27982 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
27986 bfd_set_section_flags
27987 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
27988 bfd_set_section_size (stdoutput
, sec
, 0);
27989 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
27995 /* Record the CPU type as well. */
27996 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
27997 mach
= bfd_mach_arm_iWMMXt2
;
27998 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
27999 mach
= bfd_mach_arm_iWMMXt
;
28000 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
28001 mach
= bfd_mach_arm_XScale
;
28002 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
28003 mach
= bfd_mach_arm_ep9312
;
28004 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
28005 mach
= bfd_mach_arm_5TE
;
28006 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
28008 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
28009 mach
= bfd_mach_arm_5T
;
28011 mach
= bfd_mach_arm_5
;
28013 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
28015 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
28016 mach
= bfd_mach_arm_4T
;
28018 mach
= bfd_mach_arm_4
;
28020 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
28021 mach
= bfd_mach_arm_3M
;
28022 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
28023 mach
= bfd_mach_arm_3
;
28024 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
28025 mach
= bfd_mach_arm_2a
;
28026 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
28027 mach
= bfd_mach_arm_2
;
28029 mach
= bfd_mach_arm_unknown
;
28031 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
28034 /* Command line processing. */
28037 Invocation line includes a switch not recognized by the base assembler.
28038 See if it's a processor-specific option.
28040 This routine is somewhat complicated by the need for backwards
28041 compatibility (since older releases of gcc can't be changed).
28042 The new options try to make the interface as compatible as
28045 New options (supported) are:
28047 -mcpu=<cpu name> Assemble for selected processor
28048 -march=<architecture name> Assemble for selected architecture
28049 -mfpu=<fpu architecture> Assemble for selected FPU.
28050 -EB/-mbig-endian Big-endian
28051 -EL/-mlittle-endian Little-endian
28052 -k Generate PIC code
28053 -mthumb Start in Thumb mode
28054 -mthumb-interwork Code supports ARM/Thumb interworking
28056 -m[no-]warn-deprecated Warn about deprecated features
28057 -m[no-]warn-syms Warn when symbols match instructions
28059 For now we will also provide support for:
28061 -mapcs-32 32-bit Program counter
28062 -mapcs-26 26-bit Program counter
28063 -macps-float Floats passed in FP registers
28064 -mapcs-reentrant Reentrant code
28066 (sometime these will probably be replaced with -mapcs=<list of options>
28067 and -matpcs=<list of options>)
28069 The remaining options are only supported for back-wards compatibility.
28070 Cpu variants, the arm part is optional:
28071 -m[arm]1 Currently not supported.
28072 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
28073 -m[arm]3 Arm 3 processor
28074 -m[arm]6[xx], Arm 6 processors
28075 -m[arm]7[xx][t][[d]m] Arm 7 processors
28076 -m[arm]8[10] Arm 8 processors
28077 -m[arm]9[20][tdmi] Arm 9 processors
28078 -mstrongarm[110[0]] StrongARM processors
28079 -mxscale XScale processors
28080 -m[arm]v[2345[t[e]]] Arm architectures
28081 -mall All (except the ARM1)
28083 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
28084 -mfpe-old (No float load/store multiples)
28085 -mvfpxd VFP Single precision
28087 -mno-fpu Disable all floating point instructions
28089 The following CPU names are recognized:
28090 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
28091 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
28092 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
28093 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
28094 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
28095 arm10t arm10e, arm1020t, arm1020e, arm10200e,
28096 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
28100 const char * md_shortopts
= "m:k";
28102 #ifdef ARM_BI_ENDIAN
28103 #define OPTION_EB (OPTION_MD_BASE + 0)
28104 #define OPTION_EL (OPTION_MD_BASE + 1)
28106 #if TARGET_BYTES_BIG_ENDIAN
28107 #define OPTION_EB (OPTION_MD_BASE + 0)
28109 #define OPTION_EL (OPTION_MD_BASE + 1)
28112 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
28113 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
28115 struct option md_longopts
[] =
28118 {"EB", no_argument
, NULL
, OPTION_EB
},
28121 {"EL", no_argument
, NULL
, OPTION_EL
},
28123 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
28125 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
28127 {NULL
, no_argument
, NULL
, 0}
28130 size_t md_longopts_size
= sizeof (md_longopts
);
28132 struct arm_option_table
28134 const char * option
; /* Option name to match. */
28135 const char * help
; /* Help information. */
28136 int * var
; /* Variable to change. */
28137 int value
; /* What to change it to. */
28138 const char * deprecated
; /* If non-null, print this message. */
28141 struct arm_option_table arm_opts
[] =
28143 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
28144 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
28145 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
28146 &support_interwork
, 1, NULL
},
28147 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
28148 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
28149 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
28151 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
28152 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
28153 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
28154 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
28157 /* These are recognized by the assembler, but have no affect on code. */
28158 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
28159 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
28161 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
28162 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
28163 &warn_on_deprecated
, 0, NULL
},
28164 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
28165 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
28166 {NULL
, NULL
, NULL
, 0, NULL
}
28169 struct arm_legacy_option_table
28171 const char * option
; /* Option name to match. */
28172 const arm_feature_set
** var
; /* Variable to change. */
28173 const arm_feature_set value
; /* What to change it to. */
28174 const char * deprecated
; /* If non-null, print this message. */
28177 const struct arm_legacy_option_table arm_legacy_opts
[] =
28179 /* DON'T add any new processors to this list -- we want the whole list
28180 to go away... Add them to the processors table instead. */
28181 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
28182 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
28183 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
28184 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
28185 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
28186 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
28187 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
28188 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
28189 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
28190 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
28191 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
28192 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
28193 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
28194 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
28195 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
28196 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
28197 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
28198 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
28199 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
28200 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
28201 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
28202 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
28203 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
28204 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
28205 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
28206 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
28207 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
28208 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
28209 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
28210 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
28211 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
28212 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
28213 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
28214 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
28215 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
28216 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
28217 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
28218 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
28219 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
28220 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
28221 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
28222 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
28223 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
28224 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
28225 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
28226 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
28227 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28228 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28229 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28230 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28231 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
28232 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
28233 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
28234 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
28235 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
28236 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
28237 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
28238 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
28239 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
28240 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
28241 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
28242 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
28243 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
28244 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
28245 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
28246 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
28247 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
28248 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
28249 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
28250 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
28251 N_("use -mcpu=strongarm110")},
28252 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
28253 N_("use -mcpu=strongarm1100")},
28254 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
28255 N_("use -mcpu=strongarm1110")},
28256 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
28257 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
28258 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
28260 /* Architecture variants -- don't add any more to this list either. */
28261 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
28262 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
28263 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
28264 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
28265 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
28266 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
28267 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
28268 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
28269 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
28270 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
28271 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
28272 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
28273 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
28274 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
28275 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
28276 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
28277 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
28278 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
28280 /* Floating point variants -- don't add any more to this list either. */
28281 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
28282 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
28283 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
28284 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
28285 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
28287 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
28290 struct arm_cpu_option_table
28294 const arm_feature_set value
;
28295 const arm_feature_set ext
;
28296 /* For some CPUs we assume an FPU unless the user explicitly sets
28298 const arm_feature_set default_fpu
;
28299 /* The canonical name of the CPU, or NULL to use NAME converted to upper
28301 const char * canonical_name
;
28304 /* This list should, at a minimum, contain all the cpu names
28305 recognized by GCC. */
28306 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
28308 static const struct arm_cpu_option_table arm_cpus
[] =
28310 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
28313 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
28316 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
28319 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
28322 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
28325 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
28328 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
28331 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
28334 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
28337 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
28340 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
28343 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
28346 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
28349 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
28352 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
28355 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
28358 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
28361 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
28364 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
28367 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
28370 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
28373 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
28376 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
28379 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
28382 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
28385 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
28388 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
28391 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
28394 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
28397 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
28400 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
28403 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
28406 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
28409 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
28412 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
28415 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
28418 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
28421 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
28424 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
28427 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
28430 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
28433 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
28436 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
28439 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
28442 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
28445 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
28449 /* For V5 or later processors we default to using VFP; but the user
28450 should really set the FPU type explicitly. */
28451 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
28454 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
28457 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
28460 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
28463 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
28466 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
28469 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
28472 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
28475 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
28478 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
28481 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
28484 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
28487 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
28490 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
28493 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
28496 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
28499 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
28502 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
28505 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
28508 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
28511 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
28514 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
28517 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
28520 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
28523 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
28526 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
28529 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
28532 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
28535 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
28538 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
28541 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
28544 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
28547 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
28550 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
28553 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
28556 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
28559 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
28560 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
28562 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
28564 FPU_ARCH_NEON_VFP_V4
),
28565 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
28566 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
28567 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
28568 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
28569 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
28570 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
28571 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
28573 FPU_ARCH_NEON_VFP_V4
),
28574 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
28576 FPU_ARCH_NEON_VFP_V4
),
28577 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
28579 FPU_ARCH_NEON_VFP_V4
),
28580 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
28581 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28582 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28583 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
28584 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28585 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28586 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
28587 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28588 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28589 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
28590 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28591 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28592 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
28593 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28594 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28595 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
28596 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28597 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28598 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
28599 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28600 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28601 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
28602 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28603 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28604 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
28605 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28606 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28607 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
28608 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28609 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28610 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
28613 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
28615 FPU_ARCH_VFP_V3D16
),
28616 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
28617 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
28619 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
28620 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
28621 FPU_ARCH_VFP_V3D16
),
28622 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
28623 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
28624 FPU_ARCH_VFP_V3D16
),
28625 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
28626 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28627 FPU_ARCH_NEON_VFP_ARMV8
),
28628 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
28629 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
28631 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
28634 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
28637 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
28640 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
28643 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
28646 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
28649 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
28652 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
28653 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28654 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28655 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
28656 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28657 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28658 /* ??? XSCALE is really an architecture. */
28659 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
28663 /* ??? iwmmxt is not a processor. */
28664 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
28667 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
28670 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
28675 ARM_CPU_OPT ("ep9312", "ARM920T",
28676 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
28677 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
28679 /* Marvell processors. */
28680 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
28681 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
28682 FPU_ARCH_VFP_V3D16
),
28683 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
28684 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
28685 FPU_ARCH_NEON_VFP_V4
),
28687 /* APM X-Gene family. */
28688 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
28690 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28691 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
28692 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28693 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28695 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
28699 struct arm_ext_table
28703 const arm_feature_set merge
;
28704 const arm_feature_set clear
;
28707 struct arm_arch_option_table
28711 const arm_feature_set value
;
28712 const arm_feature_set default_fpu
;
28713 const struct arm_ext_table
* ext_table
;
28716 /* Used to add support for +E and +noE extension. */
28717 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
28718 /* Used to add support for a +E extension. */
28719 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
28720 /* Used to add support for a +noE extension. */
28721 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
28723 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
28724 ~0 & ~FPU_ENDIAN_PURE)
28726 static const struct arm_ext_table armv5te_ext_table
[] =
28728 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
28729 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28732 static const struct arm_ext_table armv7_ext_table
[] =
28734 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
28735 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28738 static const struct arm_ext_table armv7ve_ext_table
[] =
28740 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
28741 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
28742 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
28743 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
28744 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
28745 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
28746 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
28748 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
28749 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
28751 /* Aliases for +simd. */
28752 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
28754 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
28755 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
28756 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
28758 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28761 static const struct arm_ext_table armv7a_ext_table
[] =
28763 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
28764 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
28765 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
28766 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
28767 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
28768 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
28769 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
28771 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
28772 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
28774 /* Aliases for +simd. */
28775 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
28776 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
28778 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
28779 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
28781 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
28782 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
28783 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28786 static const struct arm_ext_table armv7r_ext_table
[] =
28788 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
28789 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
28790 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
28791 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
28792 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
28793 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
28794 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
28795 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
28796 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28799 static const struct arm_ext_table armv7em_ext_table
[] =
28801 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
28802 /* Alias for +fp, used to be known as fpv4-sp-d16. */
28803 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
28804 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
28805 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
28806 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
28807 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28810 static const struct arm_ext_table armv8a_ext_table
[] =
28812 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
28813 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
28814 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
28815 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
28817 /* Armv8-a does not allow an FP implementation without SIMD, so the user
28818 should use the +simd option to turn on FP. */
28819 ARM_REMOVE ("fp", ALL_FP
),
28820 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
28821 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
28822 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28826 static const struct arm_ext_table armv81a_ext_table
[] =
28828 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
28829 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
28830 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
28832 /* Armv8-a does not allow an FP implementation without SIMD, so the user
28833 should use the +simd option to turn on FP. */
28834 ARM_REMOVE ("fp", ALL_FP
),
28835 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
28836 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
28837 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28840 static const struct arm_ext_table armv82a_ext_table
[] =
28842 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
28843 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
28844 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
28845 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
28846 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
28847 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
28849 /* Armv8-a does not allow an FP implementation without SIMD, so the user
28850 should use the +simd option to turn on FP. */
28851 ARM_REMOVE ("fp", ALL_FP
),
28852 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
28853 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
28854 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28857 static const struct arm_ext_table armv84a_ext_table
[] =
28859 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
28860 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
28861 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
28862 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
28864 /* Armv8-a does not allow an FP implementation without SIMD, so the user
28865 should use the +simd option to turn on FP. */
28866 ARM_REMOVE ("fp", ALL_FP
),
28867 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
28868 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
28869 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28872 static const struct arm_ext_table armv85a_ext_table
[] =
28874 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
28875 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
28876 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
28877 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
28879 /* Armv8-a does not allow an FP implementation without SIMD, so the user
28880 should use the +simd option to turn on FP. */
28881 ARM_REMOVE ("fp", ALL_FP
),
28882 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28885 static const struct arm_ext_table armv8m_main_ext_table
[] =
28887 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
28888 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
28889 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
28890 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
28891 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28894 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
28896 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
28897 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
28899 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
28900 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
28903 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
28904 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
28905 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
28906 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
28908 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
28909 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
28910 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
28911 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28914 static const struct arm_ext_table armv8r_ext_table
[] =
28916 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
28917 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
28918 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
28919 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
28920 ARM_REMOVE ("fp", ALL_FP
),
28921 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
28922 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28925 /* This list should, at a minimum, contain all the architecture names
28926 recognized by GCC. */
28927 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
28928 #define ARM_ARCH_OPT2(N, V, DF, ext) \
28929 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
28931 static const struct arm_arch_option_table arm_archs
[] =
28933 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
28934 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
28935 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
28936 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
28937 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
28938 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
28939 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
28940 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
28941 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
28942 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
28943 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
28944 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
28945 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
28946 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
28947 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
28948 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
28949 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
28950 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
28951 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
28952 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
28953 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
28954 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
28955 kept to preserve existing behaviour. */
28956 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
28957 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
28958 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
28959 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
28960 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
28961 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
28962 kept to preserve existing behaviour. */
28963 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
28964 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
28965 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
28966 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
28967 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
28968 /* The official spelling of the ARMv7 profile variants is the dashed form.
28969 Accept the non-dashed form for compatibility with old toolchains. */
28970 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
28971 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
28972 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
28973 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
28974 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
28975 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
28976 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
28977 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
28978 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
28979 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
28981 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
28983 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
28984 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
28985 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
28986 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
28987 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
28988 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
28989 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
28990 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
28991 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
28992 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
28993 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
28995 #undef ARM_ARCH_OPT
28997 /* ISA extensions in the co-processor and main instruction set space. */
28999 struct arm_option_extension_value_table
29003 const arm_feature_set merge_value
;
29004 const arm_feature_set clear_value
;
29005 /* List of architectures for which an extension is available. ARM_ARCH_NONE
29006 indicates that an extension is available for all architectures while
29007 ARM_ANY marks an empty entry. */
29008 const arm_feature_set allowed_archs
[2];
29011 /* The following table must be in alphabetical order with a NULL last entry. */
29013 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
29014 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
29016 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
29017 use the context sensitive approach using arm_ext_table's. */
29018 static const struct arm_option_extension_value_table arm_extensions
[] =
29020 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29021 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29022 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29023 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
29024 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29025 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
29026 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
29028 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29029 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29030 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
29031 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
29032 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29033 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29034 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29036 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
29037 | ARM_EXT2_FP16_FML
),
29038 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
29039 | ARM_EXT2_FP16_FML
),
29041 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29042 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29043 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
29044 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
29045 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
29046 Thumb divide instruction. Due to this having the same name as the
29047 previous entry, this will be ignored when doing command-line parsing and
29048 only considered by build attribute selection code. */
29049 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
29050 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
29051 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
29052 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
29053 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
29054 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
29055 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
29056 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
29057 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
29058 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
29059 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
29060 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
29061 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
29062 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
29063 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
29064 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
29065 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
29066 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
29067 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29068 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
29069 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
29071 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
29072 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
29073 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29074 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
29075 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
29076 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29077 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
29078 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
29080 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
29081 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
29082 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
29083 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
29084 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
29085 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
29086 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29087 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
29089 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
29090 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
29091 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
29092 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
29093 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
29097 /* ISA floating-point and Advanced SIMD extensions. */
29098 struct arm_option_fpu_value_table
29101 const arm_feature_set value
;
29104 /* This list should, at a minimum, contain all the fpu names
29105 recognized by GCC. */
29106 static const struct arm_option_fpu_value_table arm_fpus
[] =
29108 {"softfpa", FPU_NONE
},
29109 {"fpe", FPU_ARCH_FPE
},
29110 {"fpe2", FPU_ARCH_FPE
},
29111 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
29112 {"fpa", FPU_ARCH_FPA
},
29113 {"fpa10", FPU_ARCH_FPA
},
29114 {"fpa11", FPU_ARCH_FPA
},
29115 {"arm7500fe", FPU_ARCH_FPA
},
29116 {"softvfp", FPU_ARCH_VFP
},
29117 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
29118 {"vfp", FPU_ARCH_VFP_V2
},
29119 {"vfp9", FPU_ARCH_VFP_V2
},
29120 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
29121 {"vfp10", FPU_ARCH_VFP_V2
},
29122 {"vfp10-r0", FPU_ARCH_VFP_V1
},
29123 {"vfpxd", FPU_ARCH_VFP_V1xD
},
29124 {"vfpv2", FPU_ARCH_VFP_V2
},
29125 {"vfpv3", FPU_ARCH_VFP_V3
},
29126 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
29127 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
29128 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
29129 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
29130 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
29131 {"arm1020t", FPU_ARCH_VFP_V1
},
29132 {"arm1020e", FPU_ARCH_VFP_V2
},
29133 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
29134 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
29135 {"maverick", FPU_ARCH_MAVERICK
},
29136 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
29137 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
29138 {"neon-fp16", FPU_ARCH_NEON_FP16
},
29139 {"vfpv4", FPU_ARCH_VFP_V4
},
29140 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
29141 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
29142 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
29143 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
29144 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
29145 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
29146 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
29147 {"crypto-neon-fp-armv8",
29148 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
29149 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
29150 {"crypto-neon-fp-armv8.1",
29151 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
29152 {NULL
, ARM_ARCH_NONE
}
29155 struct arm_option_value_table
29161 static const struct arm_option_value_table arm_float_abis
[] =
29163 {"hard", ARM_FLOAT_ABI_HARD
},
29164 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
29165 {"soft", ARM_FLOAT_ABI_SOFT
},
29170 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
29171 static const struct arm_option_value_table arm_eabis
[] =
29173 {"gnu", EF_ARM_EABI_UNKNOWN
},
29174 {"4", EF_ARM_EABI_VER4
},
29175 {"5", EF_ARM_EABI_VER5
},
29180 struct arm_long_option_table
29182 const char * option
; /* Substring to match. */
29183 const char * help
; /* Help information. */
29184 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
29185 const char * deprecated
; /* If non-null, print this message. */
29189 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
29190 arm_feature_set
*ext_set
,
29191 const struct arm_ext_table
*ext_table
)
29193 /* We insist on extensions being specified in alphabetical order, and with
29194 extensions being added before being removed. We achieve this by having
29195 the global ARM_EXTENSIONS table in alphabetical order, and using the
29196 ADDING_VALUE variable to indicate whether we are adding an extension (1)
29197 or removing it (0) and only allowing it to change in the order
29199 const struct arm_option_extension_value_table
* opt
= NULL
;
29200 const arm_feature_set arm_any
= ARM_ANY
;
29201 int adding_value
= -1;
29203 while (str
!= NULL
&& *str
!= 0)
29210 as_bad (_("invalid architectural extension"));
29215 ext
= strchr (str
, '+');
29220 len
= strlen (str
);
29222 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
29224 if (adding_value
!= 0)
29227 opt
= arm_extensions
;
29235 if (adding_value
== -1)
29238 opt
= arm_extensions
;
29240 else if (adding_value
!= 1)
29242 as_bad (_("must specify extensions to add before specifying "
29243 "those to remove"));
29250 as_bad (_("missing architectural extension"));
29254 gas_assert (adding_value
!= -1);
29255 gas_assert (opt
!= NULL
);
29257 if (ext_table
!= NULL
)
29259 const struct arm_ext_table
* ext_opt
= ext_table
;
29260 bfd_boolean found
= FALSE
;
29261 for (; ext_opt
->name
!= NULL
; ext_opt
++)
29262 if (ext_opt
->name_len
== len
29263 && strncmp (ext_opt
->name
, str
, len
) == 0)
29267 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
29268 /* TODO: Option not supported. When we remove the
29269 legacy table this case should error out. */
29272 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
29276 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
29277 /* TODO: Option not supported. When we remove the
29278 legacy table this case should error out. */
29280 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
29292 /* Scan over the options table trying to find an exact match. */
29293 for (; opt
->name
!= NULL
; opt
++)
29294 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29296 int i
, nb_allowed_archs
=
29297 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
29298 /* Check we can apply the extension to this architecture. */
29299 for (i
= 0; i
< nb_allowed_archs
; i
++)
29302 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
29304 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
29307 if (i
== nb_allowed_archs
)
29309 as_bad (_("extension does not apply to the base architecture"));
29313 /* Add or remove the extension. */
29315 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
29317 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
29319 /* Allowing Thumb division instructions for ARMv7 in autodetection
29320 rely on this break so that duplicate extensions (extensions
29321 with the same name as a previous extension in the list) are not
29322 considered for command-line parsing. */
29326 if (opt
->name
== NULL
)
29328 /* Did we fail to find an extension because it wasn't specified in
29329 alphabetical order, or because it does not exist? */
29331 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
29332 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29335 if (opt
->name
== NULL
)
29336 as_bad (_("unknown architectural extension `%s'"), str
);
29338 as_bad (_("architectural extensions must be specified in "
29339 "alphabetical order"));
29345 /* We should skip the extension we've just matched the next time
29357 arm_parse_cpu (const char *str
)
29359 const struct arm_cpu_option_table
*opt
;
29360 const char *ext
= strchr (str
, '+');
29366 len
= strlen (str
);
29370 as_bad (_("missing cpu name `%s'"), str
);
29374 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
29375 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29377 mcpu_cpu_opt
= &opt
->value
;
29378 if (mcpu_ext_opt
== NULL
)
29379 mcpu_ext_opt
= XNEW (arm_feature_set
);
29380 *mcpu_ext_opt
= opt
->ext
;
29381 mcpu_fpu_opt
= &opt
->default_fpu
;
29382 if (opt
->canonical_name
)
29384 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
29385 strcpy (selected_cpu_name
, opt
->canonical_name
);
29391 if (len
>= sizeof selected_cpu_name
)
29392 len
= (sizeof selected_cpu_name
) - 1;
29394 for (i
= 0; i
< len
; i
++)
29395 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
29396 selected_cpu_name
[i
] = 0;
29400 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
29405 as_bad (_("unknown cpu `%s'"), str
);
29410 arm_parse_arch (const char *str
)
29412 const struct arm_arch_option_table
*opt
;
29413 const char *ext
= strchr (str
, '+');
29419 len
= strlen (str
);
29423 as_bad (_("missing architecture name `%s'"), str
);
29427 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
29428 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29430 march_cpu_opt
= &opt
->value
;
29431 if (march_ext_opt
== NULL
)
29432 march_ext_opt
= XNEW (arm_feature_set
);
29433 *march_ext_opt
= arm_arch_none
;
29434 march_fpu_opt
= &opt
->default_fpu
;
29435 strcpy (selected_cpu_name
, opt
->name
);
29438 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
29444 as_bad (_("unknown architecture `%s'\n"), str
);
29449 arm_parse_fpu (const char * str
)
29451 const struct arm_option_fpu_value_table
* opt
;
29453 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
29454 if (streq (opt
->name
, str
))
29456 mfpu_opt
= &opt
->value
;
29460 as_bad (_("unknown floating point format `%s'\n"), str
);
29465 arm_parse_float_abi (const char * str
)
29467 const struct arm_option_value_table
* opt
;
29469 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
29470 if (streq (opt
->name
, str
))
29472 mfloat_abi_opt
= opt
->value
;
29476 as_bad (_("unknown floating point abi `%s'\n"), str
);
29482 arm_parse_eabi (const char * str
)
29484 const struct arm_option_value_table
*opt
;
29486 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
29487 if (streq (opt
->name
, str
))
29489 meabi_flags
= opt
->value
;
29492 as_bad (_("unknown EABI `%s'\n"), str
);
29498 arm_parse_it_mode (const char * str
)
29500 bfd_boolean ret
= TRUE
;
29502 if (streq ("arm", str
))
29503 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
29504 else if (streq ("thumb", str
))
29505 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
29506 else if (streq ("always", str
))
29507 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
29508 else if (streq ("never", str
))
29509 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
29512 as_bad (_("unknown implicit IT mode `%s', should be "\
29513 "arm, thumb, always, or never."), str
);
29521 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
29523 codecomposer_syntax
= TRUE
;
29524 arm_comment_chars
[0] = ';';
29525 arm_line_separator_chars
[0] = 0;
29529 struct arm_long_option_table arm_long_opts
[] =
29531 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
29532 arm_parse_cpu
, NULL
},
29533 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
29534 arm_parse_arch
, NULL
},
29535 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
29536 arm_parse_fpu
, NULL
},
29537 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
29538 arm_parse_float_abi
, NULL
},
29540 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
29541 arm_parse_eabi
, NULL
},
29543 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
29544 arm_parse_it_mode
, NULL
},
29545 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
29546 arm_ccs_mode
, NULL
},
29547 {NULL
, NULL
, 0, NULL
}
29551 md_parse_option (int c
, const char * arg
)
29553 struct arm_option_table
*opt
;
29554 const struct arm_legacy_option_table
*fopt
;
29555 struct arm_long_option_table
*lopt
;
29561 target_big_endian
= 1;
29567 target_big_endian
= 0;
29571 case OPTION_FIX_V4BX
:
29579 #endif /* OBJ_ELF */
29582 /* Listing option. Just ignore these, we don't support additional
29587 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
29589 if (c
== opt
->option
[0]
29590 && ((arg
== NULL
&& opt
->option
[1] == 0)
29591 || streq (arg
, opt
->option
+ 1)))
29593 /* If the option is deprecated, tell the user. */
29594 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
29595 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
29596 arg
? arg
: "", _(opt
->deprecated
));
29598 if (opt
->var
!= NULL
)
29599 *opt
->var
= opt
->value
;
29605 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
29607 if (c
== fopt
->option
[0]
29608 && ((arg
== NULL
&& fopt
->option
[1] == 0)
29609 || streq (arg
, fopt
->option
+ 1)))
29611 /* If the option is deprecated, tell the user. */
29612 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
29613 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
29614 arg
? arg
: "", _(fopt
->deprecated
));
29616 if (fopt
->var
!= NULL
)
29617 *fopt
->var
= &fopt
->value
;
29623 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
29625 /* These options are expected to have an argument. */
29626 if (c
== lopt
->option
[0]
29628 && strncmp (arg
, lopt
->option
+ 1,
29629 strlen (lopt
->option
+ 1)) == 0)
29631 /* If the option is deprecated, tell the user. */
29632 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
29633 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
29634 _(lopt
->deprecated
));
29636 /* Call the sup-option parser. */
29637 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
29648 md_show_usage (FILE * fp
)
29650 struct arm_option_table
*opt
;
29651 struct arm_long_option_table
*lopt
;
29653 fprintf (fp
, _(" ARM-specific assembler options:\n"));
29655 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
29656 if (opt
->help
!= NULL
)
29657 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
29659 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
29660 if (lopt
->help
!= NULL
)
29661 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
29665 -EB assemble code for a big-endian cpu\n"));
29670 -EL assemble code for a little-endian cpu\n"));
29674 --fix-v4bx Allow BX in ARMv4 code\n"));
29678 --fdpic generate an FDPIC object file\n"));
29679 #endif /* OBJ_ELF */
29687 arm_feature_set flags
;
29688 } cpu_arch_ver_table
;
29690 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
29691 chronologically for architectures, with an exception for ARMv6-M and
29692 ARMv6S-M due to legacy reasons. No new architecture should have a
29693 special case. This allows for build attribute selection results to be
29694 stable when new architectures are added. */
29695 static const cpu_arch_ver_table cpu_arch_ver
[] =
29697 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
29698 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
29699 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
29700 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
29701 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
29702 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
29703 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
29704 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
29705 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
29706 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
29707 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
29708 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
29709 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
29710 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
29711 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
29712 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
29713 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
29714 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
29715 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
29716 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
29717 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
29718 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
29719 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
29720 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
29722 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
29723 always selected build attributes to match those of ARMv6-M
29724 (resp. ARMv6S-M). However, due to these architectures being a strict
29725 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
29726 would be selected when fully respecting chronology of architectures.
29727 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
29728 move them before ARMv7 architectures. */
29729 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
29730 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
29732 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
29733 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
29734 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
29735 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
29736 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
29737 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
29738 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
29739 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
29740 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
29741 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
29742 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
29743 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
29744 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
29745 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
29746 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
29747 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
29748 {-1, ARM_ARCH_NONE
}
29751 /* Set an attribute if it has not already been set by the user. */
29754 aeabi_set_attribute_int (int tag
, int value
)
29757 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
29758 || !attributes_set_explicitly
[tag
])
29759 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
29763 aeabi_set_attribute_string (int tag
, const char *value
)
29766 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
29767 || !attributes_set_explicitly
[tag
])
29768 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
29771 /* Return whether features in the *NEEDED feature set are available via
29772 extensions for the architecture whose feature set is *ARCH_FSET. */
29775 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
29776 const arm_feature_set
*needed
)
29778 int i
, nb_allowed_archs
;
29779 arm_feature_set ext_fset
;
29780 const struct arm_option_extension_value_table
*opt
;
29782 ext_fset
= arm_arch_none
;
29783 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
29785 /* Extension does not provide any feature we need. */
29786 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
29790 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
29791 for (i
= 0; i
< nb_allowed_archs
; i
++)
29794 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
29797 /* Extension is available, add it. */
29798 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
29799 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
29803 /* Can we enable all features in *needed? */
29804 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
29807 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
29808 a given architecture feature set *ARCH_EXT_FSET including extension feature
29809 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
29810 - if true, check for an exact match of the architecture modulo extensions;
29811 - otherwise, select build attribute value of the first superset
29812 architecture released so that results remains stable when new architectures
29814 For -march/-mcpu=all the build attribute value of the most featureful
29815 architecture is returned. Tag_CPU_arch_profile result is returned in
29819 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
29820 const arm_feature_set
*ext_fset
,
29821 char *profile
, int exact_match
)
29823 arm_feature_set arch_fset
;
29824 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
29826 /* Select most featureful architecture with all its extensions if building
29827 for -march=all as the feature sets used to set build attributes. */
29828 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
29830 /* Force revisiting of decision for each new architecture. */
29831 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
29833 return TAG_CPU_ARCH_V8
;
29836 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
29838 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
29840 arm_feature_set known_arch_fset
;
29842 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
29845 /* Base architecture match user-specified architecture and
29846 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
29847 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
29852 /* Base architecture match user-specified architecture only
29853 (eg. ARMv6-M in the same case as above). Record it in case we
29854 find a match with above condition. */
29855 else if (p_ver_ret
== NULL
29856 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
29862 /* Architecture has all features wanted. */
29863 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
29865 arm_feature_set added_fset
;
29867 /* Compute features added by this architecture over the one
29868 recorded in p_ver_ret. */
29869 if (p_ver_ret
!= NULL
)
29870 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
29872 /* First architecture that match incl. with extensions, or the
29873 only difference in features over the recorded match is
29874 features that were optional and are now mandatory. */
29875 if (p_ver_ret
== NULL
29876 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
29882 else if (p_ver_ret
== NULL
)
29884 arm_feature_set needed_ext_fset
;
29886 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
29888 /* Architecture has all features needed when using some
29889 extensions. Record it and continue searching in case there
29890 exist an architecture providing all needed features without
29891 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
29893 if (have_ext_for_needed_feat_p (&known_arch_fset
,
29900 if (p_ver_ret
== NULL
)
29904 /* Tag_CPU_arch_profile. */
29905 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
29906 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
29907 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
29908 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
29910 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
29912 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
29916 return p_ver_ret
->val
;
29919 /* Set the public EABI object attributes. */
29922 aeabi_set_public_attributes (void)
29924 char profile
= '\0';
29927 int fp16_optional
= 0;
29928 int skip_exact_match
= 0;
29929 arm_feature_set flags
, flags_arch
, flags_ext
;
29931 /* Autodetection mode, choose the architecture based the instructions
29933 if (no_cpu_selected ())
29935 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
29937 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
29938 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
29940 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
29941 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
29943 /* Code run during relaxation relies on selected_cpu being set. */
29944 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
29945 flags_ext
= arm_arch_none
;
29946 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
29947 selected_ext
= flags_ext
;
29948 selected_cpu
= flags
;
29950 /* Otherwise, choose the architecture based on the capabilities of the
29954 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
29955 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
29956 flags_ext
= selected_ext
;
29957 flags
= selected_cpu
;
29959 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
29961 /* Allow the user to override the reported architecture. */
29962 if (!ARM_FEATURE_ZERO (selected_object_arch
))
29964 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
29965 flags_ext
= arm_arch_none
;
29968 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
29970 /* When this function is run again after relaxation has happened there is no
29971 way to determine whether an architecture or CPU was specified by the user:
29972 - selected_cpu is set above for relaxation to work;
29973 - march_cpu_opt is not set if only -mcpu or .cpu is used;
29974 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
29975 Therefore, if not in -march=all case we first try an exact match and fall
29976 back to autodetection. */
29977 if (!skip_exact_match
)
29978 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
29980 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
29982 as_bad (_("no architecture contains all the instructions used\n"));
29984 /* Tag_CPU_name. */
29985 if (selected_cpu_name
[0])
29989 q
= selected_cpu_name
;
29990 if (strncmp (q
, "armv", 4) == 0)
29995 for (i
= 0; q
[i
]; i
++)
29996 q
[i
] = TOUPPER (q
[i
]);
29998 aeabi_set_attribute_string (Tag_CPU_name
, q
);
30001 /* Tag_CPU_arch. */
30002 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
30004 /* Tag_CPU_arch_profile. */
30005 if (profile
!= '\0')
30006 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
30008 /* Tag_DSP_extension. */
30009 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
30010 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
30012 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
30013 /* Tag_ARM_ISA_use. */
30014 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
30015 || ARM_FEATURE_ZERO (flags_arch
))
30016 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
30018 /* Tag_THUMB_ISA_use. */
30019 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
30020 || ARM_FEATURE_ZERO (flags_arch
))
30024 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
30025 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
30027 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
30031 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
30034 /* Tag_VFP_arch. */
30035 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
30036 aeabi_set_attribute_int (Tag_VFP_arch
,
30037 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
30039 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
30040 aeabi_set_attribute_int (Tag_VFP_arch
,
30041 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
30043 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
30046 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
30048 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
30050 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
30053 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
30054 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
30055 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
30056 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
30057 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
30059 /* Tag_ABI_HardFP_use. */
30060 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
30061 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
30062 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
30064 /* Tag_WMMX_arch. */
30065 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
30066 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
30067 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
30068 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
30070 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
30071 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
30072 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
30073 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
30074 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
30075 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
30077 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
30079 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
30083 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
30088 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
30089 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
30090 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
30091 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
30093 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
30094 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
30095 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
30099 We set Tag_DIV_use to two when integer divide instructions have been used
30100 in ARM state, or when Thumb integer divide instructions have been used,
30101 but we have no architecture profile set, nor have we any ARM instructions.
30103 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
30104 by the base architecture.
30106 For new architectures we will have to check these tests. */
30107 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
30108 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
30109 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
30110 aeabi_set_attribute_int (Tag_DIV_use
, 0);
30111 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
30112 || (profile
== '\0'
30113 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
30114 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
30115 aeabi_set_attribute_int (Tag_DIV_use
, 2);
30117 /* Tag_MP_extension_use. */
30118 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
30119 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
30121 /* Tag Virtualization_use. */
30122 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
30124 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
30127 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
30130 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
30131 finished and free extension feature bits which will not be used anymore. */
30134 arm_md_post_relax (void)
30136 aeabi_set_public_attributes ();
30137 XDELETE (mcpu_ext_opt
);
30138 mcpu_ext_opt
= NULL
;
30139 XDELETE (march_ext_opt
);
30140 march_ext_opt
= NULL
;
30143 /* Add the default contents for the .ARM.attributes section. */
30148 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30151 aeabi_set_public_attributes ();
30153 #endif /* OBJ_ELF */
30155 /* Parse a .cpu directive. */
30158 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
30160 const struct arm_cpu_option_table
*opt
;
30164 name
= input_line_pointer
;
30165 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30166 input_line_pointer
++;
30167 saved_char
= *input_line_pointer
;
30168 *input_line_pointer
= 0;
30170 /* Skip the first "all" entry. */
30171 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
30172 if (streq (opt
->name
, name
))
30174 selected_arch
= opt
->value
;
30175 selected_ext
= opt
->ext
;
30176 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30177 if (opt
->canonical_name
)
30178 strcpy (selected_cpu_name
, opt
->canonical_name
);
30182 for (i
= 0; opt
->name
[i
]; i
++)
30183 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
30185 selected_cpu_name
[i
] = 0;
30187 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30189 *input_line_pointer
= saved_char
;
30190 demand_empty_rest_of_line ();
30193 as_bad (_("unknown cpu `%s'"), name
);
30194 *input_line_pointer
= saved_char
;
30195 ignore_rest_of_line ();
30198 /* Parse a .arch directive. */
30201 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
30203 const struct arm_arch_option_table
*opt
;
30207 name
= input_line_pointer
;
30208 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30209 input_line_pointer
++;
30210 saved_char
= *input_line_pointer
;
30211 *input_line_pointer
= 0;
30213 /* Skip the first "all" entry. */
30214 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
30215 if (streq (opt
->name
, name
))
30217 selected_arch
= opt
->value
;
30218 selected_ext
= arm_arch_none
;
30219 selected_cpu
= selected_arch
;
30220 strcpy (selected_cpu_name
, opt
->name
);
30221 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30222 *input_line_pointer
= saved_char
;
30223 demand_empty_rest_of_line ();
30227 as_bad (_("unknown architecture `%s'\n"), name
);
30228 *input_line_pointer
= saved_char
;
30229 ignore_rest_of_line ();
30232 /* Parse a .object_arch directive. */
30235 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
30237 const struct arm_arch_option_table
*opt
;
30241 name
= input_line_pointer
;
30242 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30243 input_line_pointer
++;
30244 saved_char
= *input_line_pointer
;
30245 *input_line_pointer
= 0;
30247 /* Skip the first "all" entry. */
30248 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
30249 if (streq (opt
->name
, name
))
30251 selected_object_arch
= opt
->value
;
30252 *input_line_pointer
= saved_char
;
30253 demand_empty_rest_of_line ();
30257 as_bad (_("unknown architecture `%s'\n"), name
);
30258 *input_line_pointer
= saved_char
;
30259 ignore_rest_of_line ();
30262 /* Parse a .arch_extension directive. */
30265 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
30267 const struct arm_option_extension_value_table
*opt
;
30270 int adding_value
= 1;
30272 name
= input_line_pointer
;
30273 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30274 input_line_pointer
++;
30275 saved_char
= *input_line_pointer
;
30276 *input_line_pointer
= 0;
30278 if (strlen (name
) >= 2
30279 && strncmp (name
, "no", 2) == 0)
30285 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30286 if (streq (opt
->name
, name
))
30288 int i
, nb_allowed_archs
=
30289 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
30290 for (i
= 0; i
< nb_allowed_archs
; i
++)
30293 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
30295 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
30299 if (i
== nb_allowed_archs
)
30301 as_bad (_("architectural extension `%s' is not allowed for the "
30302 "current base architecture"), name
);
30307 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
30310 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
30312 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30313 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30314 *input_line_pointer
= saved_char
;
30315 demand_empty_rest_of_line ();
30316 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
30317 on this return so that duplicate extensions (extensions with the
30318 same name as a previous extension in the list) are not considered
30319 for command-line parsing. */
30323 if (opt
->name
== NULL
)
30324 as_bad (_("unknown architecture extension `%s'\n"), name
);
30326 *input_line_pointer
= saved_char
;
30327 ignore_rest_of_line ();
30330 /* Parse a .fpu directive. */
30333 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
30335 const struct arm_option_fpu_value_table
*opt
;
30339 name
= input_line_pointer
;
30340 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30341 input_line_pointer
++;
30342 saved_char
= *input_line_pointer
;
30343 *input_line_pointer
= 0;
30345 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
30346 if (streq (opt
->name
, name
))
30348 selected_fpu
= opt
->value
;
30349 #ifndef CPU_DEFAULT
30350 if (no_cpu_selected ())
30351 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30354 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30355 *input_line_pointer
= saved_char
;
30356 demand_empty_rest_of_line ();
30360 as_bad (_("unknown floating point format `%s'\n"), name
);
30361 *input_line_pointer
= saved_char
;
30362 ignore_rest_of_line ();
30365 /* Copy symbol information. */
30368 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
30370 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
30374 /* Given a symbolic attribute NAME, return the proper integer value.
30375 Returns -1 if the attribute is not known. */
30378 arm_convert_symbolic_attribute (const char *name
)
30380 static const struct
30385 attribute_table
[] =
30387 /* When you modify this table you should
30388 also modify the list in doc/c-arm.texi. */
30389 #define T(tag) {#tag, tag}
30390 T (Tag_CPU_raw_name
),
30393 T (Tag_CPU_arch_profile
),
30394 T (Tag_ARM_ISA_use
),
30395 T (Tag_THUMB_ISA_use
),
30399 T (Tag_Advanced_SIMD_arch
),
30400 T (Tag_PCS_config
),
30401 T (Tag_ABI_PCS_R9_use
),
30402 T (Tag_ABI_PCS_RW_data
),
30403 T (Tag_ABI_PCS_RO_data
),
30404 T (Tag_ABI_PCS_GOT_use
),
30405 T (Tag_ABI_PCS_wchar_t
),
30406 T (Tag_ABI_FP_rounding
),
30407 T (Tag_ABI_FP_denormal
),
30408 T (Tag_ABI_FP_exceptions
),
30409 T (Tag_ABI_FP_user_exceptions
),
30410 T (Tag_ABI_FP_number_model
),
30411 T (Tag_ABI_align_needed
),
30412 T (Tag_ABI_align8_needed
),
30413 T (Tag_ABI_align_preserved
),
30414 T (Tag_ABI_align8_preserved
),
30415 T (Tag_ABI_enum_size
),
30416 T (Tag_ABI_HardFP_use
),
30417 T (Tag_ABI_VFP_args
),
30418 T (Tag_ABI_WMMX_args
),
30419 T (Tag_ABI_optimization_goals
),
30420 T (Tag_ABI_FP_optimization_goals
),
30421 T (Tag_compatibility
),
30422 T (Tag_CPU_unaligned_access
),
30423 T (Tag_FP_HP_extension
),
30424 T (Tag_VFP_HP_extension
),
30425 T (Tag_ABI_FP_16bit_format
),
30426 T (Tag_MPextension_use
),
30428 T (Tag_nodefaults
),
30429 T (Tag_also_compatible_with
),
30430 T (Tag_conformance
),
30432 T (Tag_Virtualization_use
),
30433 T (Tag_DSP_extension
),
30435 /* We deliberately do not include Tag_MPextension_use_legacy. */
30443 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
30444 if (streq (name
, attribute_table
[i
].name
))
30445 return attribute_table
[i
].tag
;
30450 /* Apply sym value for relocations only in the case that they are for
30451 local symbols in the same segment as the fixup and you have the
30452 respective architectural feature for blx and simple switches. */
30455 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
30458 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
30459 /* PR 17444: If the local symbol is in a different section then a reloc
30460 will always be generated for it, so applying the symbol value now
30461 will result in a double offset being stored in the relocation. */
30462 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
30463 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
30465 switch (fixP
->fx_r_type
)
30467 case BFD_RELOC_ARM_PCREL_BLX
:
30468 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30469 if (ARM_IS_FUNC (fixP
->fx_addsy
))
30473 case BFD_RELOC_ARM_PCREL_CALL
:
30474 case BFD_RELOC_THUMB_PCREL_BLX
:
30475 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
30486 #endif /* OBJ_ELF */