1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
39 #include "dw2gencfi.h"
42 #include "dwarf2dbg.h"
45 /* Must be at least the size of the largest unwind opcode (currently two). */
46 #define ARM_OPCODE_CHUNK_SIZE 8
48 /* This structure holds the unwinding state. */
53 symbolS
* table_entry
;
54 symbolS
* personality_routine
;
55 int personality_index
;
56 /* The segment containing the function. */
59 /* Opcodes generated from this function. */
60 unsigned char * opcodes
;
63 /* The number of bytes pushed to the stack. */
65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
68 offsetT pending_offset
;
69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
70 hold the reg+offset to use when restoring sp from a frame pointer. */
73 /* Nonzero if an unwind_setfp directive has been seen. */
75 /* Nonzero if the last opcode restores sp from fp_reg. */
76 unsigned sp_restored
:1;
79 /* Whether --fdpic was given. */
84 /* Results from operand parsing worker functions. */
88 PARSE_OPERAND_SUCCESS
,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91 } parse_operand_result
;
100 /* Types of processor to assemble for. */
102 /* The code that was here used to select a default CPU depending on compiler
103 pre-defines which were only present when doing native builds, thus
104 changing gas' default behaviour depending upon the build host.
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
110 /* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112 static bfd_boolean
out_of_range_p (offsetT value
, offsetT bits
)
114 gas_assert (bits
< (offsetT
)(sizeof (value
) * 8));
115 return (value
& ~((1 << bits
)-1))
116 && ((value
& ~((1 << bits
)-1)) != ~((1 << bits
)-1));
121 # define FPU_DEFAULT FPU_ARCH_FPA
122 # elif defined (TE_NetBSD)
124 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
126 /* Legacy a.out format. */
127 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
129 # elif defined (TE_VXWORKS)
130 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
132 /* For backwards compatibility, default to FPA. */
133 # define FPU_DEFAULT FPU_ARCH_FPA
135 #endif /* ifndef FPU_DEFAULT */
137 #define streq(a, b) (strcmp (a, b) == 0)
139 /* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
142 static arm_feature_set cpu_variant
;
143 /* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
145 static arm_feature_set arm_arch_used
;
146 static arm_feature_set thumb_arch_used
;
148 /* Flags stored in private area of BFD structure. */
149 static int uses_apcs_26
= FALSE
;
150 static int atpcs
= FALSE
;
151 static int support_interwork
= FALSE
;
152 static int uses_apcs_float
= FALSE
;
153 static int pic_code
= FALSE
;
154 static int fix_v4bx
= FALSE
;
155 /* Warn on using deprecated features. */
156 static int warn_on_deprecated
= TRUE
;
158 /* Understand CodeComposer Studio assembly syntax. */
159 bfd_boolean codecomposer_syntax
= FALSE
;
161 /* Variables that we set while parsing command-line options. Once all
162 options have been read we re-process these values to set the real
165 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
166 instead of -mcpu=arm1). */
167 static const arm_feature_set
*legacy_cpu
= NULL
;
168 static const arm_feature_set
*legacy_fpu
= NULL
;
170 /* CPU, extension and FPU feature bits selected by -mcpu. */
171 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
172 static arm_feature_set
*mcpu_ext_opt
= NULL
;
173 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
175 /* CPU, extension and FPU feature bits selected by -march. */
176 static const arm_feature_set
*march_cpu_opt
= NULL
;
177 static arm_feature_set
*march_ext_opt
= NULL
;
178 static const arm_feature_set
*march_fpu_opt
= NULL
;
180 /* Feature bits selected by -mfpu. */
181 static const arm_feature_set
*mfpu_opt
= NULL
;
183 /* Constants for known architecture features. */
184 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
185 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
186 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
187 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
188 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
189 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
190 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
192 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
194 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
197 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
200 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
201 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
202 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
203 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
204 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
205 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
206 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
207 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
208 static const arm_feature_set arm_ext_v4t_5
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
210 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
211 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
212 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
213 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
214 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
215 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
216 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
217 /* Only for compatability of hint instructions. */
218 static const arm_feature_set arm_ext_v6k_v6t2
=
219 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
220 static const arm_feature_set arm_ext_v6_notm
=
221 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
222 static const arm_feature_set arm_ext_v6_dsp
=
223 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
224 static const arm_feature_set arm_ext_barrier
=
225 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
226 static const arm_feature_set arm_ext_msr
=
227 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
228 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
229 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
230 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
231 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
233 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
235 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
236 static const arm_feature_set arm_ext_m
=
237 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
238 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
239 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
240 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
241 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
242 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
243 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
244 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
245 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
246 static const arm_feature_set arm_ext_v8m_main
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
248 static const arm_feature_set arm_ext_v8_1m_main
=
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
250 /* Instructions in ARMv8-M only found in M profile architectures. */
251 static const arm_feature_set arm_ext_v8m_m_only
=
252 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
253 static const arm_feature_set arm_ext_v6t2_v8m
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
255 /* Instructions shared between ARMv8-A and ARMv8-M. */
256 static const arm_feature_set arm_ext_atomics
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
259 /* DSP instructions Tag_DSP_extension refers to. */
260 static const arm_feature_set arm_ext_dsp
=
261 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
263 static const arm_feature_set arm_ext_ras
=
264 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
265 /* FP16 instructions. */
266 static const arm_feature_set arm_ext_fp16
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
268 static const arm_feature_set arm_ext_fp16_fml
=
269 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
270 static const arm_feature_set arm_ext_v8_2
=
271 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
272 static const arm_feature_set arm_ext_v8_3
=
273 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
274 static const arm_feature_set arm_ext_sb
=
275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
276 static const arm_feature_set arm_ext_predres
=
277 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
278 static const arm_feature_set arm_ext_bf16
=
279 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
);
280 static const arm_feature_set arm_ext_i8mm
=
281 ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
);
283 static const arm_feature_set arm_arch_any
= ARM_ANY
;
285 static const arm_feature_set fpu_any
= FPU_ANY
;
287 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
288 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
289 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
291 static const arm_feature_set arm_cext_iwmmxt2
=
292 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
293 static const arm_feature_set arm_cext_iwmmxt
=
294 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
295 static const arm_feature_set arm_cext_xscale
=
296 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
297 static const arm_feature_set arm_cext_maverick
=
298 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
299 static const arm_feature_set fpu_fpa_ext_v1
=
300 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
301 static const arm_feature_set fpu_fpa_ext_v2
=
302 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
303 static const arm_feature_set fpu_vfp_ext_v1xd
=
304 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
305 static const arm_feature_set fpu_vfp_ext_v1
=
306 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
307 static const arm_feature_set fpu_vfp_ext_v2
=
308 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
309 static const arm_feature_set fpu_vfp_ext_v3xd
=
310 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
311 static const arm_feature_set fpu_vfp_ext_v3
=
312 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
313 static const arm_feature_set fpu_vfp_ext_d32
=
314 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
315 static const arm_feature_set fpu_neon_ext_v1
=
316 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
317 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
318 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
319 static const arm_feature_set mve_ext
=
320 ARM_FEATURE_COPROC (FPU_MVE
);
321 static const arm_feature_set mve_fp_ext
=
322 ARM_FEATURE_COPROC (FPU_MVE_FP
);
324 static const arm_feature_set fpu_vfp_fp16
=
325 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
326 static const arm_feature_set fpu_neon_ext_fma
=
327 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
329 static const arm_feature_set fpu_vfp_ext_fma
=
330 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
331 static const arm_feature_set fpu_vfp_ext_armv8
=
332 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
333 static const arm_feature_set fpu_vfp_ext_armv8xd
=
334 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
335 static const arm_feature_set fpu_neon_ext_armv8
=
336 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
337 static const arm_feature_set fpu_crypto_ext_armv8
=
338 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
339 static const arm_feature_set crc_ext_armv8
=
340 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
341 static const arm_feature_set fpu_neon_ext_v8_1
=
342 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
343 static const arm_feature_set fpu_neon_ext_dotprod
=
344 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
346 static int mfloat_abi_opt
= -1;
347 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
349 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
350 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
352 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
353 /* Feature bits selected by the last -mcpu/-march or by the combination of the
354 last .cpu/.arch directive .arch_extension directives since that
356 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
357 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
358 static arm_feature_set selected_fpu
= FPU_NONE
;
359 /* Feature bits selected by the last .object_arch directive. */
360 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
361 /* Must be long enough to hold any of the names in arm_cpus. */
362 static const struct arm_ext_table
* selected_ctx_ext_table
= NULL
;
363 static char selected_cpu_name
[20];
365 extern FLONUM_TYPE generic_floating_point_number
;
367 /* Return if no cpu was selected on command-line. */
369 no_cpu_selected (void)
371 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
376 static int meabi_flags
= EABI_DEFAULT
;
378 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
381 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
386 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
391 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
392 symbolS
* GOT_symbol
;
395 /* 0: assemble for ARM,
396 1: assemble for Thumb,
397 2: assemble for Thumb even though target CPU does not support thumb
399 static int thumb_mode
= 0;
400 /* A value distinct from the possible values for thumb_mode that we
401 can use to record whether thumb_mode has been copied into the
402 tc_frag_data field of a frag. */
403 #define MODE_RECORDED (1 << 4)
405 /* Specifies the intrinsic IT insn behavior mode. */
406 enum implicit_it_mode
408 IMPLICIT_IT_MODE_NEVER
= 0x00,
409 IMPLICIT_IT_MODE_ARM
= 0x01,
410 IMPLICIT_IT_MODE_THUMB
= 0x02,
411 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
413 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
415 /* If unified_syntax is true, we are processing the new unified
416 ARM/Thumb syntax. Important differences from the old ARM mode:
418 - Immediate operands do not require a # prefix.
419 - Conditional affixes always appear at the end of the
420 instruction. (For backward compatibility, those instructions
421 that formerly had them in the middle, continue to accept them
423 - The IT instruction may appear, and if it does is validated
424 against subsequent conditional affixes. It does not generate
427 Important differences from the old Thumb mode:
429 - Immediate operands do not require a # prefix.
430 - Most of the V6T2 instructions are only available in unified mode.
431 - The .N and .W suffixes are recognized and honored (it is an error
432 if they cannot be honored).
433 - All instructions set the flags if and only if they have an 's' affix.
434 - Conditional affixes may be used. They are validated against
435 preceding IT instructions. Unlike ARM mode, you cannot use a
436 conditional affix except in the scope of an IT instruction. */
438 static bfd_boolean unified_syntax
= FALSE
;
440 /* An immediate operand can start with #, and ld*, st*, pld operands
441 can contain [ and ]. We need to tell APP not to elide whitespace
442 before a [, which can appear as the first operand for pld.
443 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
444 const char arm_symbol_chars
[] = "#[]{}";
460 enum neon_el_type type
;
464 #define NEON_MAX_TYPE_ELS 4
468 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
472 enum pred_instruction_type
478 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
479 if inside, should be the last one. */
480 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
481 i.e. BKPT and NOP. */
482 IT_INSN
, /* The IT insn has been parsed. */
483 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
484 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
485 a predication code. */
486 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
489 /* The maximum number of operands we need. */
490 #define ARM_IT_MAX_OPERANDS 6
491 #define ARM_IT_MAX_RELOCS 3
496 unsigned long instruction
;
500 /* "uncond_value" is set to the value in place of the conditional field in
501 unconditional versions of the instruction, or -1 if nothing is
504 struct neon_type vectype
;
505 /* This does not indicate an actual NEON instruction, only that
506 the mnemonic accepts neon-style type suffixes. */
508 /* Set to the opcode if the instruction needs relaxation.
509 Zero if the instruction is not relaxed. */
513 bfd_reloc_code_real_type type
;
516 } relocs
[ARM_IT_MAX_RELOCS
];
518 enum pred_instruction_type pred_insn_type
;
524 struct neon_type_el vectype
;
525 unsigned present
: 1; /* Operand present. */
526 unsigned isreg
: 1; /* Operand was a register. */
527 unsigned immisreg
: 2; /* .imm field is a second register.
528 0: imm, 1: gpr, 2: MVE Q-register. */
529 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
533 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
534 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
535 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
536 instructions. This allows us to disambiguate ARM <-> vector insns. */
537 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
538 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
539 unsigned isquad
: 1; /* Operand is SIMD quad register. */
540 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
541 unsigned iszr
: 1; /* Operand is ZR register. */
542 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
543 unsigned writeback
: 1; /* Operand has trailing ! */
544 unsigned preind
: 1; /* Preindexed address. */
545 unsigned postind
: 1; /* Postindexed address. */
546 unsigned negative
: 1; /* Index register was negated. */
547 unsigned shifted
: 1; /* Shift applied to operation. */
548 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
549 } operands
[ARM_IT_MAX_OPERANDS
];
552 static struct arm_it inst
;
554 #define NUM_FLOAT_VALS 8
556 const char * fp_const
[] =
558 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
561 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
571 #define CP_T_X 0x00008000
572 #define CP_T_Y 0x00400000
574 #define CONDS_BIT 0x00100000
575 #define LOAD_BIT 0x00100000
577 #define DOUBLE_LOAD_FLAG 0x00000001
581 const char * template_name
;
585 #define COND_ALWAYS 0xE
589 const char * template_name
;
593 struct asm_barrier_opt
595 const char * template_name
;
597 const arm_feature_set arch
;
600 /* The bit that distinguishes CPSR and SPSR. */
601 #define SPSR_BIT (1 << 22)
603 /* The individual PSR flag bits. */
604 #define PSR_c (1 << 16)
605 #define PSR_x (1 << 17)
606 #define PSR_s (1 << 18)
607 #define PSR_f (1 << 19)
612 bfd_reloc_code_real_type reloc
;
617 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
618 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
623 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
626 /* Bits for DEFINED field in neon_typed_alias. */
627 #define NTA_HASTYPE 1
628 #define NTA_HASINDEX 2
630 struct neon_typed_alias
632 unsigned char defined
;
634 struct neon_type_el eltype
;
637 /* ARM register categories. This includes coprocessor numbers and various
638 architecture extensions' registers. Each entry should have an error message
639 in reg_expected_msgs below. */
669 /* Structure for a hash table entry for a register.
670 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
671 information which states whether a vector type or index is specified (for a
672 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
678 unsigned char builtin
;
679 struct neon_typed_alias
* neon
;
682 /* Diagnostics used when we don't get a register of the expected type. */
683 const char * const reg_expected_msgs
[] =
685 [REG_TYPE_RN
] = N_("ARM register expected"),
686 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
687 [REG_TYPE_CN
] = N_("co-processor register expected"),
688 [REG_TYPE_FN
] = N_("FPA register expected"),
689 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
690 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
691 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
692 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
693 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
694 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
695 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
697 [REG_TYPE_VFC
] = N_("VFP system register expected"),
698 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
699 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
700 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
701 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
702 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
703 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
704 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
705 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
706 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
707 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
708 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
709 [REG_TYPE_RNB
] = N_("")
712 /* Some well known registers that we refer to directly elsewhere. */
718 /* ARM instructions take 4bytes in the object file, Thumb instructions
724 /* Basic string to match. */
725 const char * template_name
;
727 /* Parameters to instruction. */
728 unsigned int operands
[8];
730 /* Conditional tag - see opcode_lookup. */
731 unsigned int tag
: 4;
733 /* Basic instruction code. */
736 /* Thumb-format instruction code. */
739 /* Which architecture variant provides this instruction. */
740 const arm_feature_set
* avariant
;
741 const arm_feature_set
* tvariant
;
743 /* Function to call to encode instruction in ARM format. */
744 void (* aencode
) (void);
746 /* Function to call to encode instruction in Thumb format. */
747 void (* tencode
) (void);
749 /* Indicates whether this instruction may be vector predicated. */
750 unsigned int mayBeVecPred
: 1;
753 /* Defines for various bits that we will want to toggle. */
754 #define INST_IMMEDIATE 0x02000000
755 #define OFFSET_REG 0x02000000
756 #define HWOFFSET_IMM 0x00400000
757 #define SHIFT_BY_REG 0x00000010
758 #define PRE_INDEX 0x01000000
759 #define INDEX_UP 0x00800000
760 #define WRITE_BACK 0x00200000
761 #define LDM_TYPE_2_OR_3 0x00400000
762 #define CPSI_MMOD 0x00020000
764 #define LITERAL_MASK 0xf000f000
765 #define OPCODE_MASK 0xfe1fffff
766 #define V4_STR_BIT 0x00000020
767 #define VLDR_VMOV_SAME 0x0040f000
769 #define T2_SUBS_PC_LR 0xf3de8f00
771 #define DATA_OP_SHIFT 21
772 #define SBIT_SHIFT 20
774 #define T2_OPCODE_MASK 0xfe1fffff
775 #define T2_DATA_OP_SHIFT 21
776 #define T2_SBIT_SHIFT 20
778 #define A_COND_MASK 0xf0000000
779 #define A_PUSH_POP_OP_MASK 0x0fff0000
781 /* Opcodes for pushing/poping registers to/from the stack. */
782 #define A1_OPCODE_PUSH 0x092d0000
783 #define A2_OPCODE_PUSH 0x052d0004
784 #define A2_OPCODE_POP 0x049d0004
786 /* Codes to distinguish the arithmetic instructions. */
797 #define OPCODE_CMP 10
798 #define OPCODE_CMN 11
799 #define OPCODE_ORR 12
800 #define OPCODE_MOV 13
801 #define OPCODE_BIC 14
802 #define OPCODE_MVN 15
804 #define T2_OPCODE_AND 0
805 #define T2_OPCODE_BIC 1
806 #define T2_OPCODE_ORR 2
807 #define T2_OPCODE_ORN 3
808 #define T2_OPCODE_EOR 4
809 #define T2_OPCODE_ADD 8
810 #define T2_OPCODE_ADC 10
811 #define T2_OPCODE_SBC 11
812 #define T2_OPCODE_SUB 13
813 #define T2_OPCODE_RSB 14
815 #define T_OPCODE_MUL 0x4340
816 #define T_OPCODE_TST 0x4200
817 #define T_OPCODE_CMN 0x42c0
818 #define T_OPCODE_NEG 0x4240
819 #define T_OPCODE_MVN 0x43c0
821 #define T_OPCODE_ADD_R3 0x1800
822 #define T_OPCODE_SUB_R3 0x1a00
823 #define T_OPCODE_ADD_HI 0x4400
824 #define T_OPCODE_ADD_ST 0xb000
825 #define T_OPCODE_SUB_ST 0xb080
826 #define T_OPCODE_ADD_SP 0xa800
827 #define T_OPCODE_ADD_PC 0xa000
828 #define T_OPCODE_ADD_I8 0x3000
829 #define T_OPCODE_SUB_I8 0x3800
830 #define T_OPCODE_ADD_I3 0x1c00
831 #define T_OPCODE_SUB_I3 0x1e00
833 #define T_OPCODE_ASR_R 0x4100
834 #define T_OPCODE_LSL_R 0x4080
835 #define T_OPCODE_LSR_R 0x40c0
836 #define T_OPCODE_ROR_R 0x41c0
837 #define T_OPCODE_ASR_I 0x1000
838 #define T_OPCODE_LSL_I 0x0000
839 #define T_OPCODE_LSR_I 0x0800
841 #define T_OPCODE_MOV_I8 0x2000
842 #define T_OPCODE_CMP_I8 0x2800
843 #define T_OPCODE_CMP_LR 0x4280
844 #define T_OPCODE_MOV_HR 0x4600
845 #define T_OPCODE_CMP_HR 0x4500
847 #define T_OPCODE_LDR_PC 0x4800
848 #define T_OPCODE_LDR_SP 0x9800
849 #define T_OPCODE_STR_SP 0x9000
850 #define T_OPCODE_LDR_IW 0x6800
851 #define T_OPCODE_STR_IW 0x6000
852 #define T_OPCODE_LDR_IH 0x8800
853 #define T_OPCODE_STR_IH 0x8000
854 #define T_OPCODE_LDR_IB 0x7800
855 #define T_OPCODE_STR_IB 0x7000
856 #define T_OPCODE_LDR_RW 0x5800
857 #define T_OPCODE_STR_RW 0x5000
858 #define T_OPCODE_LDR_RH 0x5a00
859 #define T_OPCODE_STR_RH 0x5200
860 #define T_OPCODE_LDR_RB 0x5c00
861 #define T_OPCODE_STR_RB 0x5400
863 #define T_OPCODE_PUSH 0xb400
864 #define T_OPCODE_POP 0xbc00
866 #define T_OPCODE_BRANCH 0xe000
868 #define THUMB_SIZE 2 /* Size of thumb instruction. */
869 #define THUMB_PP_PC_LR 0x0100
870 #define THUMB_LOAD_BIT 0x0800
871 #define THUMB2_LOAD_BIT 0x00100000
873 #define BAD_SYNTAX _("syntax error")
874 #define BAD_ARGS _("bad arguments to instruction")
875 #define BAD_SP _("r13 not allowed here")
876 #define BAD_PC _("r15 not allowed here")
877 #define BAD_ODD _("Odd register not allowed here")
878 #define BAD_EVEN _("Even register not allowed here")
879 #define BAD_COND _("instruction cannot be conditional")
880 #define BAD_OVERLAP _("registers may not be the same")
881 #define BAD_HIREG _("lo register required")
882 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
883 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
884 #define BAD_BRANCH _("branch must be last instruction in IT block")
885 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
886 #define BAD_NOT_IT _("instruction not allowed in IT block")
887 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
888 #define BAD_FPU _("selected FPU does not support instruction")
889 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
890 #define BAD_OUT_VPT \
891 _("vector predicated instruction should be in VPT/VPST block")
892 #define BAD_IT_COND _("incorrect condition in IT block")
893 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
894 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
895 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
896 #define BAD_PC_ADDRESSING \
897 _("cannot use register index with PC-relative addressing")
898 #define BAD_PC_WRITEBACK \
899 _("cannot use writeback with PC-relative addressing")
900 #define BAD_RANGE _("branch out of range")
901 #define BAD_FP16 _("selected processor does not support fp16 instruction")
902 #define BAD_BF16 _("selected processor does not support bf16 instruction")
903 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
904 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
905 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
907 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
909 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
911 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
913 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
914 #define BAD_MVE_AUTO \
915 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
916 " use a valid -march or -mcpu option.")
917 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
918 "and source operands makes instruction UNPREDICTABLE")
919 #define BAD_EL_TYPE _("bad element type for instruction")
920 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
922 static struct hash_control
* arm_ops_hsh
;
923 static struct hash_control
* arm_cond_hsh
;
924 static struct hash_control
* arm_vcond_hsh
;
925 static struct hash_control
* arm_shift_hsh
;
926 static struct hash_control
* arm_psr_hsh
;
927 static struct hash_control
* arm_v7m_psr_hsh
;
928 static struct hash_control
* arm_reg_hsh
;
929 static struct hash_control
* arm_reloc_hsh
;
930 static struct hash_control
* arm_barrier_opt_hsh
;
932 /* Stuff needed to resolve the label ambiguity
941 symbolS
* last_label_seen
;
942 static int label_is_thumb_function_name
= FALSE
;
944 /* Literal pool structure. Held on a per-section
945 and per-sub-section basis. */
947 #define MAX_LITERAL_POOL_SIZE 1024
948 typedef struct literal_pool
950 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
951 unsigned int next_free_entry
;
957 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
959 struct literal_pool
* next
;
960 unsigned int alignment
;
963 /* Pointer to a linked list of literal pools. */
964 literal_pool
* list_of_pools
= NULL
;
966 typedef enum asmfunc_states
969 WAITING_ASMFUNC_NAME
,
973 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
976 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
978 static struct current_pred now_pred
;
982 now_pred_compatible (int cond
)
984 return (cond
& ~1) == (now_pred
.cc
& ~1);
988 conditional_insn (void)
990 return inst
.cond
!= COND_ALWAYS
;
993 static int in_pred_block (void);
995 static int handle_pred_state (void);
997 static void force_automatic_it_block_close (void);
999 static void it_fsm_post_encode (void);
1001 #define set_pred_insn_type(type) \
1004 inst.pred_insn_type = type; \
1005 if (handle_pred_state () == FAIL) \
1010 #define set_pred_insn_type_nonvoid(type, failret) \
1013 inst.pred_insn_type = type; \
1014 if (handle_pred_state () == FAIL) \
1019 #define set_pred_insn_type_last() \
1022 if (inst.cond == COND_ALWAYS) \
1023 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1025 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1029 /* Toggle value[pos]. */
1030 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1034 /* This array holds the chars that always start a comment. If the
1035 pre-processor is disabled, these aren't very useful. */
1036 char arm_comment_chars
[] = "@";
1038 /* This array holds the chars that only start a comment at the beginning of
1039 a line. If the line seems to have the form '# 123 filename'
1040 .line and .file directives will appear in the pre-processed output. */
1041 /* Note that input_file.c hand checks for '#' at the beginning of the
1042 first line of the input file. This is because the compiler outputs
1043 #NO_APP at the beginning of its output. */
1044 /* Also note that comments like this one will always work. */
1045 const char line_comment_chars
[] = "#";
1047 char arm_line_separator_chars
[] = ";";
1049 /* Chars that can be used to separate mant
1050 from exp in floating point numbers. */
1051 const char EXP_CHARS
[] = "eE";
1053 /* Chars that mean this number is a floating point constant. */
1054 /* As in 0f12.456 */
1055 /* or 0d1.2345e12 */
1057 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1059 /* Prefix characters that indicate the start of an immediate
1061 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1063 /* Separator character handling. */
1065 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1067 enum fp_16bit_format
1069 ARM_FP16_FORMAT_IEEE
= 0x1,
1070 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1071 ARM_FP16_FORMAT_DEFAULT
= 0x3
1074 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1078 skip_past_char (char ** str
, char c
)
1080 /* PR gas/14987: Allow for whitespace before the expected character. */
1081 skip_whitespace (*str
);
1092 #define skip_past_comma(str) skip_past_char (str, ',')
1094 /* Arithmetic expressions (possibly involving symbols). */
1096 /* Return TRUE if anything in the expression is a bignum. */
1099 walk_no_bignums (symbolS
* sp
)
1101 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1104 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1106 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1107 || (symbol_get_value_expression (sp
)->X_op_symbol
1108 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1114 static bfd_boolean in_my_get_expression
= FALSE
;
1116 /* Third argument to my_get_expression. */
1117 #define GE_NO_PREFIX 0
1118 #define GE_IMM_PREFIX 1
1119 #define GE_OPT_PREFIX 2
1120 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1121 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1122 #define GE_OPT_PREFIX_BIG 3
1125 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1129 /* In unified syntax, all prefixes are optional. */
1131 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1134 switch (prefix_mode
)
1136 case GE_NO_PREFIX
: break;
1138 if (!is_immediate_prefix (**str
))
1140 inst
.error
= _("immediate expression requires a # prefix");
1146 case GE_OPT_PREFIX_BIG
:
1147 if (is_immediate_prefix (**str
))
1154 memset (ep
, 0, sizeof (expressionS
));
1156 save_in
= input_line_pointer
;
1157 input_line_pointer
= *str
;
1158 in_my_get_expression
= TRUE
;
1160 in_my_get_expression
= FALSE
;
1162 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1164 /* We found a bad or missing expression in md_operand(). */
1165 *str
= input_line_pointer
;
1166 input_line_pointer
= save_in
;
1167 if (inst
.error
== NULL
)
1168 inst
.error
= (ep
->X_op
== O_absent
1169 ? _("missing expression") :_("bad expression"));
1173 /* Get rid of any bignums now, so that we don't generate an error for which
1174 we can't establish a line number later on. Big numbers are never valid
1175 in instructions, which is where this routine is always called. */
1176 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1177 && (ep
->X_op
== O_big
1178 || (ep
->X_add_symbol
1179 && (walk_no_bignums (ep
->X_add_symbol
)
1181 && walk_no_bignums (ep
->X_op_symbol
))))))
1183 inst
.error
= _("invalid constant");
1184 *str
= input_line_pointer
;
1185 input_line_pointer
= save_in
;
1189 *str
= input_line_pointer
;
1190 input_line_pointer
= save_in
;
1194 /* Turn a string in input_line_pointer into a floating point constant
1195 of type TYPE, and store the appropriate bytes in *LITP. The number
1196 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1197 returned, or NULL on OK.
1199 Note that fp constants aren't represent in the normal way on the ARM.
1200 In big endian mode, things are as expected. However, in little endian
1201 mode fp constants are big-endian word-wise, and little-endian byte-wise
1202 within the words. For example, (double) 1.1 in big endian mode is
1203 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1204 the byte sequence 99 99 f1 3f 9a 99 99 99.
1206 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1209 md_atof (int type
, char * litP
, int * sizeP
)
1212 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1223 /* If this is a bfloat16, then parse it slightly differently, as it
1224 does not follow the IEEE specification for floating point numbers
1228 FLONUM_TYPE generic_float
;
1230 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
1233 input_line_pointer
= t
;
1235 return _("invalid floating point number");
1237 switch (generic_float
.sign
)
1250 /* bfloat16 has two types of NaN - quiet and signalling.
1251 Quiet NaN has bit[6] == 1 && faction != 0, whereas
1252 signalling NaN's have bit[0] == 0 && fraction != 0.
1253 Chosen this specific encoding as it is the same form
1254 as used by other IEEE 754 encodings in GAS. */
1265 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
1295 return _("Unrecognized or unsupported floating point constant");
1298 t
= atof_ieee (input_line_pointer
, type
, words
);
1300 input_line_pointer
= t
;
1301 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1303 if (target_big_endian
|| prec
== 1)
1304 for (i
= 0; i
< prec
; i
++)
1306 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1307 litP
+= sizeof (LITTLENUM_TYPE
);
1309 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1310 for (i
= prec
- 1; i
>= 0; i
--)
1312 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1313 litP
+= sizeof (LITTLENUM_TYPE
);
1316 /* For a 4 byte float the order of elements in `words' is 1 0.
1317 For an 8 byte float the order is 1 0 3 2. */
1318 for (i
= 0; i
< prec
; i
+= 2)
1320 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1321 sizeof (LITTLENUM_TYPE
));
1322 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1323 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1324 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1330 /* We handle all bad expressions here, so that we can report the faulty
1331 instruction in the error message. */
1334 md_operand (expressionS
* exp
)
1336 if (in_my_get_expression
)
1337 exp
->X_op
= O_illegal
;
1340 /* Immediate values. */
1343 /* Generic immediate-value read function for use in directives.
1344 Accepts anything that 'expression' can fold to a constant.
1345 *val receives the number. */
1348 immediate_for_directive (int *val
)
1351 exp
.X_op
= O_illegal
;
1353 if (is_immediate_prefix (*input_line_pointer
))
1355 input_line_pointer
++;
1359 if (exp
.X_op
!= O_constant
)
1361 as_bad (_("expected #constant"));
1362 ignore_rest_of_line ();
1365 *val
= exp
.X_add_number
;
1370 /* Register parsing. */
1372 /* Generic register parser. CCP points to what should be the
1373 beginning of a register name. If it is indeed a valid register
1374 name, advance CCP over it and return the reg_entry structure;
1375 otherwise return NULL. Does not issue diagnostics. */
1377 static struct reg_entry
*
1378 arm_reg_parse_multi (char **ccp
)
1382 struct reg_entry
*reg
;
1384 skip_whitespace (start
);
1386 #ifdef REGISTER_PREFIX
1387 if (*start
!= REGISTER_PREFIX
)
1391 #ifdef OPTIONAL_REGISTER_PREFIX
1392 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1397 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1402 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1404 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1414 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1415 enum arm_reg_type type
)
1417 /* Alternative syntaxes are accepted for a few register classes. */
1424 /* Generic coprocessor register names are allowed for these. */
1425 if (reg
&& reg
->type
== REG_TYPE_CN
)
1430 /* For backward compatibility, a bare number is valid here. */
1432 unsigned long processor
= strtoul (start
, ccp
, 10);
1433 if (*ccp
!= start
&& processor
<= 15)
1438 case REG_TYPE_MMXWC
:
1439 /* WC includes WCG. ??? I'm not sure this is true for all
1440 instructions that take WC registers. */
1441 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1452 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1453 return value is the register number or FAIL. */
1456 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1459 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1462 /* Do not allow a scalar (reg+index) to parse as a register. */
1463 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1466 if (reg
&& reg
->type
== type
)
1469 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1476 /* Parse a Neon type specifier. *STR should point at the leading '.'
1477 character. Does no verification at this stage that the type fits the opcode
1484 Can all be legally parsed by this function.
1486 Fills in neon_type struct pointer with parsed information, and updates STR
1487 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1488 type, FAIL if not. */
1491 parse_neon_type (struct neon_type
*type
, char **str
)
1498 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1500 enum neon_el_type thistype
= NT_untyped
;
1501 unsigned thissize
= -1u;
1508 /* Just a size without an explicit type. */
1512 switch (TOLOWER (*ptr
))
1514 case 'i': thistype
= NT_integer
; break;
1515 case 'f': thistype
= NT_float
; break;
1516 case 'p': thistype
= NT_poly
; break;
1517 case 's': thistype
= NT_signed
; break;
1518 case 'u': thistype
= NT_unsigned
; break;
1520 thistype
= NT_float
;
1525 thistype
= NT_bfloat
;
1526 switch (TOLOWER (*(++ptr
)))
1530 thissize
= strtoul (ptr
, &ptr
, 10);
1533 as_bad (_("bad size %d in type specifier"), thissize
);
1537 case '0': case '1': case '2': case '3': case '4':
1538 case '5': case '6': case '7': case '8': case '9':
1540 as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1547 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1553 /* .f is an abbreviation for .f32. */
1554 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1559 thissize
= strtoul (ptr
, &ptr
, 10);
1561 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1564 as_bad (_("bad size %d in type specifier"), thissize
);
1572 type
->el
[type
->elems
].type
= thistype
;
1573 type
->el
[type
->elems
].size
= thissize
;
1578 /* Empty/missing type is not a successful parse. */
1579 if (type
->elems
== 0)
1587 /* Errors may be set multiple times during parsing or bit encoding
1588 (particularly in the Neon bits), but usually the earliest error which is set
1589 will be the most meaningful. Avoid overwriting it with later (cascading)
1590 errors by calling this function. */
1593 first_error (const char *err
)
1599 /* Parse a single type, e.g. ".s32", leading period included. */
1601 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1604 struct neon_type optype
;
1608 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1610 if (optype
.elems
== 1)
1611 *vectype
= optype
.el
[0];
1614 first_error (_("only one type should be specified for operand"));
1620 first_error (_("vector type expected"));
1632 /* Special meanings for indices (which have a range of 0-7), which will fit into
1635 #define NEON_ALL_LANES 15
1636 #define NEON_INTERLEAVE_LANES 14
1638 /* Record a use of the given feature. */
1640 record_feature_use (const arm_feature_set
*feature
)
1643 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1645 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1648 /* If the given feature available in the selected CPU, mark it as used.
1649 Returns TRUE iff feature is available. */
1651 mark_feature_used (const arm_feature_set
*feature
)
1654 /* Do not support the use of MVE only instructions when in auto-detection or
1656 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1657 && ARM_CPU_IS_ANY (cpu_variant
))
1659 first_error (BAD_MVE_AUTO
);
1662 /* Ensure the option is valid on the current architecture. */
1663 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1666 /* Add the appropriate architecture feature for the barrier option used.
1668 record_feature_use (feature
);
1673 /* Parse either a register or a scalar, with an optional type. Return the
1674 register number, and optionally fill in the actual type of the register
1675 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1676 type/index information in *TYPEINFO. */
1679 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1680 enum arm_reg_type
*rtype
,
1681 struct neon_typed_alias
*typeinfo
)
1684 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1685 struct neon_typed_alias atype
;
1686 struct neon_type_el parsetype
;
1690 atype
.eltype
.type
= NT_invtype
;
1691 atype
.eltype
.size
= -1;
1693 /* Try alternate syntax for some types of register. Note these are mutually
1694 exclusive with the Neon syntax extensions. */
1697 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1705 /* Undo polymorphism when a set of register types may be accepted. */
1706 if ((type
== REG_TYPE_NDQ
1707 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1708 || (type
== REG_TYPE_VFSD
1709 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1710 || (type
== REG_TYPE_NSDQ
1711 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1712 || reg
->type
== REG_TYPE_NQ
))
1713 || (type
== REG_TYPE_NSD
1714 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1715 || (type
== REG_TYPE_MMXWC
1716 && (reg
->type
== REG_TYPE_MMXWCG
)))
1717 type
= (enum arm_reg_type
) reg
->type
;
1719 if (type
== REG_TYPE_MQ
)
1721 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1724 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1727 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1729 first_error (_("expected MVE register [q0..q7]"));
1734 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1735 && (type
== REG_TYPE_NQ
))
1739 if (type
!= reg
->type
)
1745 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1747 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1749 first_error (_("can't redefine type for operand"));
1752 atype
.defined
|= NTA_HASTYPE
;
1753 atype
.eltype
= parsetype
;
1756 if (skip_past_char (&str
, '[') == SUCCESS
)
1758 if (type
!= REG_TYPE_VFD
1759 && !(type
== REG_TYPE_VFS
1760 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1761 && !(type
== REG_TYPE_NQ
1762 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1764 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1765 first_error (_("only D and Q registers may be indexed"));
1767 first_error (_("only D registers may be indexed"));
1771 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1773 first_error (_("can't change index for operand"));
1777 atype
.defined
|= NTA_HASINDEX
;
1779 if (skip_past_char (&str
, ']') == SUCCESS
)
1780 atype
.index
= NEON_ALL_LANES
;
1785 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1787 if (exp
.X_op
!= O_constant
)
1789 first_error (_("constant expression required"));
1793 if (skip_past_char (&str
, ']') == FAIL
)
1796 atype
.index
= exp
.X_add_number
;
1811 /* Like arm_reg_parse, but also allow the following extra features:
1812 - If RTYPE is non-zero, return the (possibly restricted) type of the
1813 register (e.g. Neon double or quad reg when either has been requested).
1814 - If this is a Neon vector type with additional type information, fill
1815 in the struct pointed to by VECTYPE (if non-NULL).
1816 This function will fault on encountering a scalar. */
1819 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1820 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1822 struct neon_typed_alias atype
;
1824 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1829 /* Do not allow regname(... to parse as a register. */
1833 /* Do not allow a scalar (reg+index) to parse as a register. */
1834 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1836 first_error (_("register operand expected, but got scalar"));
1841 *vectype
= atype
.eltype
;
1848 #define NEON_SCALAR_REG(X) ((X) >> 4)
1849 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1851 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1852 have enough information to be able to do a good job bounds-checking. So, we
1853 just do easy checks here, and do further checks later. */
1856 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1857 arm_reg_type reg_type
)
1861 struct neon_typed_alias atype
;
1864 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1882 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1885 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1887 first_error (_("scalar must have an index"));
1890 else if (atype
.index
>= reg_size
/ elsize
)
1892 first_error (_("scalar index out of range"));
1897 *type
= atype
.eltype
;
1901 return reg
* 16 + atype
.index
;
1904 /* Types of registers in a list. */
1917 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1920 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1926 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1928 /* We come back here if we get ranges concatenated by '+' or '|'. */
1931 skip_whitespace (str
);
1944 const char apsr_str
[] = "apsr";
1945 int apsr_str_len
= strlen (apsr_str
);
1947 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1948 if (etype
== REGLIST_CLRM
)
1950 if (reg
== REG_SP
|| reg
== REG_PC
)
1952 else if (reg
== FAIL
1953 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1954 && !ISALPHA (*(str
+ apsr_str_len
)))
1957 str
+= apsr_str_len
;
1962 first_error (_("r0-r12, lr or APSR expected"));
1966 else /* etype == REGLIST_RN. */
1970 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1981 first_error (_("bad range in register list"));
1985 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1987 if (range
& (1 << i
))
1989 (_("Warning: duplicated register (r%d) in register list"),
1997 if (range
& (1 << reg
))
1998 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
2000 else if (reg
<= cur_reg
)
2001 as_tsktsk (_("Warning: register range not in ascending order"));
2006 while (skip_past_comma (&str
) != FAIL
2007 || (in_range
= 1, *str
++ == '-'));
2010 if (skip_past_char (&str
, '}') == FAIL
)
2012 first_error (_("missing `}'"));
2016 else if (etype
== REGLIST_RN
)
2020 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
2023 if (exp
.X_op
== O_constant
)
2025 if (exp
.X_add_number
2026 != (exp
.X_add_number
& 0x0000ffff))
2028 inst
.error
= _("invalid register mask");
2032 if ((range
& exp
.X_add_number
) != 0)
2034 int regno
= range
& exp
.X_add_number
;
2037 regno
= (1 << regno
) - 1;
2039 (_("Warning: duplicated register (r%d) in register list"),
2043 range
|= exp
.X_add_number
;
2047 if (inst
.relocs
[0].type
!= 0)
2049 inst
.error
= _("expression too complex");
2053 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
2054 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
2055 inst
.relocs
[0].pc_rel
= 0;
2059 if (*str
== '|' || *str
== '+')
2065 while (another_range
);
2071 /* Parse a VFP register list. If the string is invalid return FAIL.
2072 Otherwise return the number of registers, and set PBASE to the first
2073 register. Parses registers of type ETYPE.
2074 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2075 - Q registers can be used to specify pairs of D registers
2076 - { } can be omitted from around a singleton register list
2077 FIXME: This is not implemented, as it would require backtracking in
2080 This could be done (the meaning isn't really ambiguous), but doesn't
2081 fit in well with the current parsing framework.
2082 - 32 D registers may be used (also true for VFPv3).
2083 FIXME: Types are ignored in these register lists, which is probably a
2087 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2088 bfd_boolean
*partial_match
)
2093 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2097 unsigned long mask
= 0;
2099 bfd_boolean vpr_seen
= FALSE
;
2100 bfd_boolean expect_vpr
=
2101 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2103 if (skip_past_char (&str
, '{') == FAIL
)
2105 inst
.error
= _("expecting {");
2112 case REGLIST_VFP_S_VPR
:
2113 regtype
= REG_TYPE_VFS
;
2118 case REGLIST_VFP_D_VPR
:
2119 regtype
= REG_TYPE_VFD
;
2122 case REGLIST_NEON_D
:
2123 regtype
= REG_TYPE_NDQ
;
2130 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2132 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2133 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2137 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2140 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2147 base_reg
= max_regs
;
2148 *partial_match
= FALSE
;
2152 int setmask
= 1, addregs
= 1;
2153 const char vpr_str
[] = "vpr";
2154 int vpr_str_len
= strlen (vpr_str
);
2156 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2160 if (new_base
== FAIL
2161 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2162 && !ISALPHA (*(str
+ vpr_str_len
))
2168 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2172 first_error (_("VPR expected last"));
2175 else if (new_base
== FAIL
)
2177 if (regtype
== REG_TYPE_VFS
)
2178 first_error (_("VFP single precision register or VPR "
2180 else /* regtype == REG_TYPE_VFD. */
2181 first_error (_("VFP/Neon double precision register or VPR "
2186 else if (new_base
== FAIL
)
2188 first_error (_(reg_expected_msgs
[regtype
]));
2192 *partial_match
= TRUE
;
2196 if (new_base
>= max_regs
)
2198 first_error (_("register out of range in list"));
2202 /* Note: a value of 2 * n is returned for the register Q<n>. */
2203 if (regtype
== REG_TYPE_NQ
)
2209 if (new_base
< base_reg
)
2210 base_reg
= new_base
;
2212 if (mask
& (setmask
<< new_base
))
2214 first_error (_("invalid register list"));
2218 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2220 as_tsktsk (_("register list not in ascending order"));
2224 mask
|= setmask
<< new_base
;
2227 if (*str
== '-') /* We have the start of a range expression */
2233 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2236 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2240 if (high_range
>= max_regs
)
2242 first_error (_("register out of range in list"));
2246 if (regtype
== REG_TYPE_NQ
)
2247 high_range
= high_range
+ 1;
2249 if (high_range
<= new_base
)
2251 inst
.error
= _("register range not in ascending order");
2255 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2257 if (mask
& (setmask
<< new_base
))
2259 inst
.error
= _("invalid register list");
2263 mask
|= setmask
<< new_base
;
2268 while (skip_past_comma (&str
) != FAIL
);
2272 /* Sanity check -- should have raised a parse error above. */
2273 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2278 if (expect_vpr
&& !vpr_seen
)
2280 first_error (_("VPR expected last"));
2284 /* Final test -- the registers must be consecutive. */
2286 for (i
= 0; i
< count
; i
++)
2288 if ((mask
& (1u << i
)) == 0)
2290 inst
.error
= _("non-contiguous register range");
2300 /* True if two alias types are the same. */
2303 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2311 if (a
->defined
!= b
->defined
)
2314 if ((a
->defined
& NTA_HASTYPE
) != 0
2315 && (a
->eltype
.type
!= b
->eltype
.type
2316 || a
->eltype
.size
!= b
->eltype
.size
))
2319 if ((a
->defined
& NTA_HASINDEX
) != 0
2320 && (a
->index
!= b
->index
))
2326 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2327 The base register is put in *PBASE.
2328 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2330 The register stride (minus one) is put in bit 4 of the return value.
2331 Bits [6:5] encode the list length (minus one).
2332 The type of the list elements is put in *ELTYPE, if non-NULL. */
2334 #define NEON_LANE(X) ((X) & 0xf)
2335 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2336 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2339 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2341 struct neon_type_el
*eltype
)
2348 int leading_brace
= 0;
2349 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2350 const char *const incr_error
= mve
? _("register stride must be 1") :
2351 _("register stride must be 1 or 2");
2352 const char *const type_error
= _("mismatched element/structure types in list");
2353 struct neon_typed_alias firsttype
;
2354 firsttype
.defined
= 0;
2355 firsttype
.eltype
.type
= NT_invtype
;
2356 firsttype
.eltype
.size
= -1;
2357 firsttype
.index
= -1;
2359 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2364 struct neon_typed_alias atype
;
2366 rtype
= REG_TYPE_MQ
;
2367 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2371 first_error (_(reg_expected_msgs
[rtype
]));
2378 if (rtype
== REG_TYPE_NQ
)
2384 else if (reg_incr
== -1)
2386 reg_incr
= getreg
- base_reg
;
2387 if (reg_incr
< 1 || reg_incr
> 2)
2389 first_error (_(incr_error
));
2393 else if (getreg
!= base_reg
+ reg_incr
* count
)
2395 first_error (_(incr_error
));
2399 if (! neon_alias_types_same (&atype
, &firsttype
))
2401 first_error (_(type_error
));
2405 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2409 struct neon_typed_alias htype
;
2410 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2412 lane
= NEON_INTERLEAVE_LANES
;
2413 else if (lane
!= NEON_INTERLEAVE_LANES
)
2415 first_error (_(type_error
));
2420 else if (reg_incr
!= 1)
2422 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2426 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2429 first_error (_(reg_expected_msgs
[rtype
]));
2432 if (! neon_alias_types_same (&htype
, &firsttype
))
2434 first_error (_(type_error
));
2437 count
+= hireg
+ dregs
- getreg
;
2441 /* If we're using Q registers, we can't use [] or [n] syntax. */
2442 if (rtype
== REG_TYPE_NQ
)
2448 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2452 else if (lane
!= atype
.index
)
2454 first_error (_(type_error
));
2458 else if (lane
== -1)
2459 lane
= NEON_INTERLEAVE_LANES
;
2460 else if (lane
!= NEON_INTERLEAVE_LANES
)
2462 first_error (_(type_error
));
2467 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2469 /* No lane set by [x]. We must be interleaving structures. */
2471 lane
= NEON_INTERLEAVE_LANES
;
2474 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2475 || (count
> 1 && reg_incr
== -1))
2477 first_error (_("error parsing element/structure list"));
2481 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2483 first_error (_("expected }"));
2491 *eltype
= firsttype
.eltype
;
2496 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2499 /* Parse an explicit relocation suffix on an expression. This is
2500 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2501 arm_reloc_hsh contains no entries, so this function can only
2502 succeed if there is no () after the word. Returns -1 on error,
2503 BFD_RELOC_UNUSED if there wasn't any suffix. */
2506 parse_reloc (char **str
)
2508 struct reloc_entry
*r
;
2512 return BFD_RELOC_UNUSED
;
2517 while (*q
&& *q
!= ')' && *q
!= ',')
2522 if ((r
= (struct reloc_entry
*)
2523 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2530 /* Directives: register aliases. */
2532 static struct reg_entry
*
2533 insert_reg_alias (char *str
, unsigned number
, int type
)
2535 struct reg_entry
*new_reg
;
2538 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2540 if (new_reg
->builtin
)
2541 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2543 /* Only warn about a redefinition if it's not defined as the
2545 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2546 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2551 name
= xstrdup (str
);
2552 new_reg
= XNEW (struct reg_entry
);
2554 new_reg
->name
= name
;
2555 new_reg
->number
= number
;
2556 new_reg
->type
= type
;
2557 new_reg
->builtin
= FALSE
;
2558 new_reg
->neon
= NULL
;
2560 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2567 insert_neon_reg_alias (char *str
, int number
, int type
,
2568 struct neon_typed_alias
*atype
)
2570 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2574 first_error (_("attempt to redefine typed alias"));
2580 reg
->neon
= XNEW (struct neon_typed_alias
);
2581 *reg
->neon
= *atype
;
2585 /* Look for the .req directive. This is of the form:
2587 new_register_name .req existing_register_name
2589 If we find one, or if it looks sufficiently like one that we want to
2590 handle any error here, return TRUE. Otherwise return FALSE. */
2593 create_register_alias (char * newname
, char *p
)
2595 struct reg_entry
*old
;
2596 char *oldname
, *nbuf
;
2599 /* The input scrubber ensures that whitespace after the mnemonic is
2600 collapsed to single spaces. */
2602 if (strncmp (oldname
, " .req ", 6) != 0)
2606 if (*oldname
== '\0')
2609 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2612 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2616 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2617 the desired alias name, and p points to its end. If not, then
2618 the desired alias name is in the global original_case_string. */
2619 #ifdef TC_CASE_SENSITIVE
2622 newname
= original_case_string
;
2623 nlen
= strlen (newname
);
2626 nbuf
= xmemdup0 (newname
, nlen
);
2628 /* Create aliases under the new name as stated; an all-lowercase
2629 version of the new name; and an all-uppercase version of the new
2631 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2633 for (p
= nbuf
; *p
; p
++)
2636 if (strncmp (nbuf
, newname
, nlen
))
2638 /* If this attempt to create an additional alias fails, do not bother
2639 trying to create the all-lower case alias. We will fail and issue
2640 a second, duplicate error message. This situation arises when the
2641 programmer does something like:
2644 The second .req creates the "Foo" alias but then fails to create
2645 the artificial FOO alias because it has already been created by the
2647 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2654 for (p
= nbuf
; *p
; p
++)
2657 if (strncmp (nbuf
, newname
, nlen
))
2658 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2665 /* Create a Neon typed/indexed register alias using directives, e.g.:
2670 These typed registers can be used instead of the types specified after the
2671 Neon mnemonic, so long as all operands given have types. Types can also be
2672 specified directly, e.g.:
2673 vadd d0.s32, d1.s32, d2.s32 */
2676 create_neon_reg_alias (char *newname
, char *p
)
2678 enum arm_reg_type basetype
;
2679 struct reg_entry
*basereg
;
2680 struct reg_entry mybasereg
;
2681 struct neon_type ntype
;
2682 struct neon_typed_alias typeinfo
;
2683 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2686 typeinfo
.defined
= 0;
2687 typeinfo
.eltype
.type
= NT_invtype
;
2688 typeinfo
.eltype
.size
= -1;
2689 typeinfo
.index
= -1;
2693 if (strncmp (p
, " .dn ", 5) == 0)
2694 basetype
= REG_TYPE_VFD
;
2695 else if (strncmp (p
, " .qn ", 5) == 0)
2696 basetype
= REG_TYPE_NQ
;
2705 basereg
= arm_reg_parse_multi (&p
);
2707 if (basereg
&& basereg
->type
!= basetype
)
2709 as_bad (_("bad type for register"));
2713 if (basereg
== NULL
)
2716 /* Try parsing as an integer. */
2717 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2718 if (exp
.X_op
!= O_constant
)
2720 as_bad (_("expression must be constant"));
2723 basereg
= &mybasereg
;
2724 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2730 typeinfo
= *basereg
->neon
;
2732 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2734 /* We got a type. */
2735 if (typeinfo
.defined
& NTA_HASTYPE
)
2737 as_bad (_("can't redefine the type of a register alias"));
2741 typeinfo
.defined
|= NTA_HASTYPE
;
2742 if (ntype
.elems
!= 1)
2744 as_bad (_("you must specify a single type only"));
2747 typeinfo
.eltype
= ntype
.el
[0];
2750 if (skip_past_char (&p
, '[') == SUCCESS
)
2753 /* We got a scalar index. */
2755 if (typeinfo
.defined
& NTA_HASINDEX
)
2757 as_bad (_("can't redefine the index of a scalar alias"));
2761 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2763 if (exp
.X_op
!= O_constant
)
2765 as_bad (_("scalar index must be constant"));
2769 typeinfo
.defined
|= NTA_HASINDEX
;
2770 typeinfo
.index
= exp
.X_add_number
;
2772 if (skip_past_char (&p
, ']') == FAIL
)
2774 as_bad (_("expecting ]"));
2779 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2780 the desired alias name, and p points to its end. If not, then
2781 the desired alias name is in the global original_case_string. */
2782 #ifdef TC_CASE_SENSITIVE
2783 namelen
= nameend
- newname
;
2785 newname
= original_case_string
;
2786 namelen
= strlen (newname
);
2789 namebuf
= xmemdup0 (newname
, namelen
);
2791 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2792 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2794 /* Insert name in all uppercase. */
2795 for (p
= namebuf
; *p
; p
++)
2798 if (strncmp (namebuf
, newname
, namelen
))
2799 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2800 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2802 /* Insert name in all lowercase. */
2803 for (p
= namebuf
; *p
; p
++)
2806 if (strncmp (namebuf
, newname
, namelen
))
2807 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2808 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2814 /* Should never be called, as .req goes between the alias and the
2815 register name, not at the beginning of the line. */
2818 s_req (int a ATTRIBUTE_UNUSED
)
2820 as_bad (_("invalid syntax for .req directive"));
2824 s_dn (int a ATTRIBUTE_UNUSED
)
2826 as_bad (_("invalid syntax for .dn directive"));
2830 s_qn (int a ATTRIBUTE_UNUSED
)
2832 as_bad (_("invalid syntax for .qn directive"));
2835 /* The .unreq directive deletes an alias which was previously defined
2836 by .req. For example:
2842 s_unreq (int a ATTRIBUTE_UNUSED
)
2847 name
= input_line_pointer
;
2849 while (*input_line_pointer
!= 0
2850 && *input_line_pointer
!= ' '
2851 && *input_line_pointer
!= '\n')
2852 ++input_line_pointer
;
2854 saved_char
= *input_line_pointer
;
2855 *input_line_pointer
= 0;
2858 as_bad (_("invalid syntax for .unreq directive"));
2861 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2865 as_bad (_("unknown register alias '%s'"), name
);
2866 else if (reg
->builtin
)
2867 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2874 hash_delete (arm_reg_hsh
, name
, FALSE
);
2875 free ((char *) reg
->name
);
2880 /* Also locate the all upper case and all lower case versions.
2881 Do not complain if we cannot find one or the other as it
2882 was probably deleted above. */
2884 nbuf
= strdup (name
);
2885 for (p
= nbuf
; *p
; p
++)
2887 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2890 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2891 free ((char *) reg
->name
);
2897 for (p
= nbuf
; *p
; p
++)
2899 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2902 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2903 free ((char *) reg
->name
);
2913 *input_line_pointer
= saved_char
;
2914 demand_empty_rest_of_line ();
2917 /* Directives: Instruction set selection. */
2920 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2921 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2922 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2923 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2925 /* Create a new mapping symbol for the transition to STATE. */
2928 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2931 const char * symname
;
2938 type
= BSF_NO_FLAGS
;
2942 type
= BSF_NO_FLAGS
;
2946 type
= BSF_NO_FLAGS
;
2952 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2953 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2958 THUMB_SET_FUNC (symbolP
, 0);
2959 ARM_SET_THUMB (symbolP
, 0);
2960 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2964 THUMB_SET_FUNC (symbolP
, 1);
2965 ARM_SET_THUMB (symbolP
, 1);
2966 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2974 /* Save the mapping symbols for future reference. Also check that
2975 we do not place two mapping symbols at the same offset within a
2976 frag. We'll handle overlap between frags in
2977 check_mapping_symbols.
2979 If .fill or other data filling directive generates zero sized data,
2980 the mapping symbol for the following code will have the same value
2981 as the one generated for the data filling directive. In this case,
2982 we replace the old symbol with the new one at the same address. */
2985 if (frag
->tc_frag_data
.first_map
!= NULL
)
2987 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2988 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2990 frag
->tc_frag_data
.first_map
= symbolP
;
2992 if (frag
->tc_frag_data
.last_map
!= NULL
)
2994 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2995 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2996 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2998 frag
->tc_frag_data
.last_map
= symbolP
;
3001 /* We must sometimes convert a region marked as code to data during
3002 code alignment, if an odd number of bytes have to be padded. The
3003 code mapping symbol is pushed to an aligned address. */
3006 insert_data_mapping_symbol (enum mstate state
,
3007 valueT value
, fragS
*frag
, offsetT bytes
)
3009 /* If there was already a mapping symbol, remove it. */
3010 if (frag
->tc_frag_data
.last_map
!= NULL
3011 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
3013 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
3017 know (frag
->tc_frag_data
.first_map
== symp
);
3018 frag
->tc_frag_data
.first_map
= NULL
;
3020 frag
->tc_frag_data
.last_map
= NULL
;
3021 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
3024 make_mapping_symbol (MAP_DATA
, value
, frag
);
3025 make_mapping_symbol (state
, value
+ bytes
, frag
);
3028 static void mapping_state_2 (enum mstate state
, int max_chars
);
3030 /* Set the mapping state to STATE. Only call this when about to
3031 emit some STATE bytes to the file. */
3033 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
3035 mapping_state (enum mstate state
)
3037 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3039 if (mapstate
== state
)
3040 /* The mapping symbol has already been emitted.
3041 There is nothing else to do. */
3044 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
3046 All ARM instructions require 4-byte alignment.
3047 (Almost) all Thumb instructions require 2-byte alignment.
3049 When emitting instructions into any section, mark the section
3052 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3053 but themselves require 2-byte alignment; this applies to some
3054 PC- relative forms. However, these cases will involve implicit
3055 literal pool generation or an explicit .align >=2, both of
3056 which will cause the section to me marked with sufficient
3057 alignment. Thus, we don't handle those cases here. */
3058 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
3060 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
3061 /* This case will be evaluated later. */
3064 mapping_state_2 (state
, 0);
3067 /* Same as mapping_state, but MAX_CHARS bytes have already been
3068 allocated. Put the mapping symbol that far back. */
3071 mapping_state_2 (enum mstate state
, int max_chars
)
3073 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3075 if (!SEG_NORMAL (now_seg
))
3078 if (mapstate
== state
)
3079 /* The mapping symbol has already been emitted.
3080 There is nothing else to do. */
3083 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
3084 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3086 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3087 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3090 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3093 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3094 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3098 #define mapping_state(x) ((void)0)
3099 #define mapping_state_2(x, y) ((void)0)
3102 /* Find the real, Thumb encoded start of a Thumb function. */
3106 find_real_start (symbolS
* symbolP
)
3109 const char * name
= S_GET_NAME (symbolP
);
3110 symbolS
* new_target
;
3112 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3113 #define STUB_NAME ".real_start_of"
3118 /* The compiler may generate BL instructions to local labels because
3119 it needs to perform a branch to a far away location. These labels
3120 do not have a corresponding ".real_start_of" label. We check
3121 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3122 the ".real_start_of" convention for nonlocal branches. */
3123 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3126 real_start
= concat (STUB_NAME
, name
, NULL
);
3127 new_target
= symbol_find (real_start
);
3130 if (new_target
== NULL
)
3132 as_warn (_("Failed to find real start of function: %s\n"), name
);
3133 new_target
= symbolP
;
3141 opcode_select (int width
)
3148 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3149 as_bad (_("selected processor does not support THUMB opcodes"));
3152 /* No need to force the alignment, since we will have been
3153 coming from ARM mode, which is word-aligned. */
3154 record_alignment (now_seg
, 1);
3161 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3162 as_bad (_("selected processor does not support ARM opcodes"));
3167 frag_align (2, 0, 0);
3169 record_alignment (now_seg
, 1);
3174 as_bad (_("invalid instruction size selected (%d)"), width
);
3179 s_arm (int ignore ATTRIBUTE_UNUSED
)
3182 demand_empty_rest_of_line ();
3186 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3189 demand_empty_rest_of_line ();
3193 s_code (int unused ATTRIBUTE_UNUSED
)
3197 temp
= get_absolute_expression ();
3202 opcode_select (temp
);
3206 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3211 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3213 /* If we are not already in thumb mode go into it, EVEN if
3214 the target processor does not support thumb instructions.
3215 This is used by gcc/config/arm/lib1funcs.asm for example
3216 to compile interworking support functions even if the
3217 target processor should not support interworking. */
3221 record_alignment (now_seg
, 1);
3224 demand_empty_rest_of_line ();
3228 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3232 /* The following label is the name/address of the start of a Thumb function.
3233 We need to know this for the interworking support. */
3234 label_is_thumb_function_name
= TRUE
;
3237 /* Perform a .set directive, but also mark the alias as
3238 being a thumb function. */
3241 s_thumb_set (int equiv
)
3243 /* XXX the following is a duplicate of the code for s_set() in read.c
3244 We cannot just call that code as we need to get at the symbol that
3251 /* Especial apologies for the random logic:
3252 This just grew, and could be parsed much more simply!
3254 delim
= get_symbol_name (& name
);
3255 end_name
= input_line_pointer
;
3256 (void) restore_line_pointer (delim
);
3258 if (*input_line_pointer
!= ',')
3261 as_bad (_("expected comma after name \"%s\""), name
);
3263 ignore_rest_of_line ();
3267 input_line_pointer
++;
3270 if (name
[0] == '.' && name
[1] == '\0')
3272 /* XXX - this should not happen to .thumb_set. */
3276 if ((symbolP
= symbol_find (name
)) == NULL
3277 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3280 /* When doing symbol listings, play games with dummy fragments living
3281 outside the normal fragment chain to record the file and line info
3283 if (listing
& LISTING_SYMBOLS
)
3285 extern struct list_info_struct
* listing_tail
;
3286 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3288 memset (dummy_frag
, 0, sizeof (fragS
));
3289 dummy_frag
->fr_type
= rs_fill
;
3290 dummy_frag
->line
= listing_tail
;
3291 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3292 dummy_frag
->fr_symbol
= symbolP
;
3296 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3299 /* "set" symbols are local unless otherwise specified. */
3300 SF_SET_LOCAL (symbolP
);
3301 #endif /* OBJ_COFF */
3302 } /* Make a new symbol. */
3304 symbol_table_insert (symbolP
);
3309 && S_IS_DEFINED (symbolP
)
3310 && S_GET_SEGMENT (symbolP
) != reg_section
)
3311 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3313 pseudo_set (symbolP
);
3315 demand_empty_rest_of_line ();
3317 /* XXX Now we come to the Thumb specific bit of code. */
3319 THUMB_SET_FUNC (symbolP
, 1);
3320 ARM_SET_THUMB (symbolP
, 1);
3321 #if defined OBJ_ELF || defined OBJ_COFF
3322 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3326 /* Directives: Mode selection. */
3328 /* .syntax [unified|divided] - choose the new unified syntax
3329 (same for Arm and Thumb encoding, modulo slight differences in what
3330 can be represented) or the old divergent syntax for each mode. */
3332 s_syntax (int unused ATTRIBUTE_UNUSED
)
3336 delim
= get_symbol_name (& name
);
3338 if (!strcasecmp (name
, "unified"))
3339 unified_syntax
= TRUE
;
3340 else if (!strcasecmp (name
, "divided"))
3341 unified_syntax
= FALSE
;
3344 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3347 (void) restore_line_pointer (delim
);
3348 demand_empty_rest_of_line ();
3351 /* Directives: sectioning and alignment. */
3354 s_bss (int ignore ATTRIBUTE_UNUSED
)
3356 /* We don't support putting frags in the BSS segment, we fake it by
3357 marking in_bss, then looking at s_skip for clues. */
3358 subseg_set (bss_section
, 0);
3359 demand_empty_rest_of_line ();
3361 #ifdef md_elf_section_change_hook
3362 md_elf_section_change_hook ();
3367 s_even (int ignore ATTRIBUTE_UNUSED
)
3369 /* Never make frag if expect extra pass. */
3371 frag_align (1, 0, 0);
3373 record_alignment (now_seg
, 1);
3375 demand_empty_rest_of_line ();
3378 /* Directives: CodeComposer Studio. */
3380 /* .ref (for CodeComposer Studio syntax only). */
3382 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3384 if (codecomposer_syntax
)
3385 ignore_rest_of_line ();
3387 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3390 /* If name is not NULL, then it is used for marking the beginning of a
3391 function, whereas if it is NULL then it means the function end. */
3393 asmfunc_debug (const char * name
)
3395 static const char * last_name
= NULL
;
3399 gas_assert (last_name
== NULL
);
3402 if (debug_type
== DEBUG_STABS
)
3403 stabs_generate_asm_func (name
, name
);
3407 gas_assert (last_name
!= NULL
);
3409 if (debug_type
== DEBUG_STABS
)
3410 stabs_generate_asm_endfunc (last_name
, last_name
);
3417 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3419 if (codecomposer_syntax
)
3421 switch (asmfunc_state
)
3423 case OUTSIDE_ASMFUNC
:
3424 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3427 case WAITING_ASMFUNC_NAME
:
3428 as_bad (_(".asmfunc repeated."));
3431 case WAITING_ENDASMFUNC
:
3432 as_bad (_(".asmfunc without function."));
3435 demand_empty_rest_of_line ();
3438 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3442 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3444 if (codecomposer_syntax
)
3446 switch (asmfunc_state
)
3448 case OUTSIDE_ASMFUNC
:
3449 as_bad (_(".endasmfunc without a .asmfunc."));
3452 case WAITING_ASMFUNC_NAME
:
3453 as_bad (_(".endasmfunc without function."));
3456 case WAITING_ENDASMFUNC
:
3457 asmfunc_state
= OUTSIDE_ASMFUNC
;
3458 asmfunc_debug (NULL
);
3461 demand_empty_rest_of_line ();
3464 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3468 s_ccs_def (int name
)
3470 if (codecomposer_syntax
)
3473 as_bad (_(".def pseudo-op only available with -mccs flag."));
3476 /* Directives: Literal pools. */
3478 static literal_pool
*
3479 find_literal_pool (void)
3481 literal_pool
* pool
;
3483 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3485 if (pool
->section
== now_seg
3486 && pool
->sub_section
== now_subseg
)
3493 static literal_pool
*
3494 find_or_make_literal_pool (void)
3496 /* Next literal pool ID number. */
3497 static unsigned int latest_pool_num
= 1;
3498 literal_pool
* pool
;
3500 pool
= find_literal_pool ();
3504 /* Create a new pool. */
3505 pool
= XNEW (literal_pool
);
3509 pool
->next_free_entry
= 0;
3510 pool
->section
= now_seg
;
3511 pool
->sub_section
= now_subseg
;
3512 pool
->next
= list_of_pools
;
3513 pool
->symbol
= NULL
;
3514 pool
->alignment
= 2;
3516 /* Add it to the list. */
3517 list_of_pools
= pool
;
3520 /* New pools, and emptied pools, will have a NULL symbol. */
3521 if (pool
->symbol
== NULL
)
3523 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3524 (valueT
) 0, &zero_address_frag
);
3525 pool
->id
= latest_pool_num
++;
3532 /* Add the literal in the global 'inst'
3533 structure to the relevant literal pool. */
3536 add_to_lit_pool (unsigned int nbytes
)
3538 #define PADDING_SLOT 0x1
3539 #define LIT_ENTRY_SIZE_MASK 0xFF
3540 literal_pool
* pool
;
3541 unsigned int entry
, pool_size
= 0;
3542 bfd_boolean padding_slot_p
= FALSE
;
3548 imm1
= inst
.operands
[1].imm
;
3549 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3550 : inst
.relocs
[0].exp
.X_unsigned
? 0
3551 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3552 if (target_big_endian
)
3555 imm2
= inst
.operands
[1].imm
;
3559 pool
= find_or_make_literal_pool ();
3561 /* Check if this literal value is already in the pool. */
3562 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3566 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3567 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3568 && (pool
->literals
[entry
].X_add_number
3569 == inst
.relocs
[0].exp
.X_add_number
)
3570 && (pool
->literals
[entry
].X_md
== nbytes
)
3571 && (pool
->literals
[entry
].X_unsigned
3572 == inst
.relocs
[0].exp
.X_unsigned
))
3575 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3576 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3577 && (pool
->literals
[entry
].X_add_number
3578 == inst
.relocs
[0].exp
.X_add_number
)
3579 && (pool
->literals
[entry
].X_add_symbol
3580 == inst
.relocs
[0].exp
.X_add_symbol
)
3581 && (pool
->literals
[entry
].X_op_symbol
3582 == inst
.relocs
[0].exp
.X_op_symbol
)
3583 && (pool
->literals
[entry
].X_md
== nbytes
))
3586 else if ((nbytes
== 8)
3587 && !(pool_size
& 0x7)
3588 && ((entry
+ 1) != pool
->next_free_entry
)
3589 && (pool
->literals
[entry
].X_op
== O_constant
)
3590 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3591 && (pool
->literals
[entry
].X_unsigned
3592 == inst
.relocs
[0].exp
.X_unsigned
)
3593 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3594 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3595 && (pool
->literals
[entry
+ 1].X_unsigned
3596 == inst
.relocs
[0].exp
.X_unsigned
))
3599 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3600 if (padding_slot_p
&& (nbytes
== 4))
3606 /* Do we need to create a new entry? */
3607 if (entry
== pool
->next_free_entry
)
3609 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3611 inst
.error
= _("literal pool overflow");
3617 /* For 8-byte entries, we align to an 8-byte boundary,
3618 and split it into two 4-byte entries, because on 32-bit
3619 host, 8-byte constants are treated as big num, thus
3620 saved in "generic_bignum" which will be overwritten
3621 by later assignments.
3623 We also need to make sure there is enough space for
3626 We also check to make sure the literal operand is a
3628 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3629 || inst
.relocs
[0].exp
.X_op
== O_big
))
3631 inst
.error
= _("invalid type for literal pool");
3634 else if (pool_size
& 0x7)
3636 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3638 inst
.error
= _("literal pool overflow");
3642 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3643 pool
->literals
[entry
].X_op
= O_constant
;
3644 pool
->literals
[entry
].X_add_number
= 0;
3645 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3646 pool
->next_free_entry
+= 1;
3649 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3651 inst
.error
= _("literal pool overflow");
3655 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3656 pool
->literals
[entry
].X_op
= O_constant
;
3657 pool
->literals
[entry
].X_add_number
= imm1
;
3658 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3659 pool
->literals
[entry
++].X_md
= 4;
3660 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3661 pool
->literals
[entry
].X_op
= O_constant
;
3662 pool
->literals
[entry
].X_add_number
= imm2
;
3663 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3664 pool
->literals
[entry
].X_md
= 4;
3665 pool
->alignment
= 3;
3666 pool
->next_free_entry
+= 1;
3670 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3671 pool
->literals
[entry
].X_md
= 4;
3675 /* PR ld/12974: Record the location of the first source line to reference
3676 this entry in the literal pool. If it turns out during linking that the
3677 symbol does not exist we will be able to give an accurate line number for
3678 the (first use of the) missing reference. */
3679 if (debug_type
== DEBUG_DWARF2
)
3680 dwarf2_where (pool
->locs
+ entry
);
3682 pool
->next_free_entry
+= 1;
3684 else if (padding_slot_p
)
3686 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3687 pool
->literals
[entry
].X_md
= nbytes
;
3690 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3691 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3692 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3698 tc_start_label_without_colon (void)
3700 bfd_boolean ret
= TRUE
;
3702 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3704 const char *label
= input_line_pointer
;
3706 while (!is_end_of_line
[(int) label
[-1]])
3711 as_bad (_("Invalid label '%s'"), label
);
3715 asmfunc_debug (label
);
3717 asmfunc_state
= WAITING_ENDASMFUNC
;
3723 /* Can't use symbol_new here, so have to create a symbol and then at
3724 a later date assign it a value. That's what these functions do. */
3727 symbol_locate (symbolS
* symbolP
,
3728 const char * name
, /* It is copied, the caller can modify. */
3729 segT segment
, /* Segment identifier (SEG_<something>). */
3730 valueT valu
, /* Symbol value. */
3731 fragS
* frag
) /* Associated fragment. */
3734 char * preserved_copy_of_name
;
3736 name_length
= strlen (name
) + 1; /* +1 for \0. */
3737 obstack_grow (¬es
, name
, name_length
);
3738 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3740 #ifdef tc_canonicalize_symbol_name
3741 preserved_copy_of_name
=
3742 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3745 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3747 S_SET_SEGMENT (symbolP
, segment
);
3748 S_SET_VALUE (symbolP
, valu
);
3749 symbol_clear_list_pointers (symbolP
);
3751 symbol_set_frag (symbolP
, frag
);
3753 /* Link to end of symbol chain. */
3755 extern int symbol_table_frozen
;
3757 if (symbol_table_frozen
)
3761 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3763 obj_symbol_new_hook (symbolP
);
3765 #ifdef tc_symbol_new_hook
3766 tc_symbol_new_hook (symbolP
);
3770 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3771 #endif /* DEBUG_SYMS */
3775 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3778 literal_pool
* pool
;
3781 pool
= find_literal_pool ();
3783 || pool
->symbol
== NULL
3784 || pool
->next_free_entry
== 0)
3787 /* Align pool as you have word accesses.
3788 Only make a frag if we have to. */
3790 frag_align (pool
->alignment
, 0, 0);
3792 record_alignment (now_seg
, 2);
3795 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3796 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3798 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3800 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3801 (valueT
) frag_now_fix (), frag_now
);
3802 symbol_table_insert (pool
->symbol
);
3804 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3806 #if defined OBJ_COFF || defined OBJ_ELF
3807 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3810 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3813 if (debug_type
== DEBUG_DWARF2
)
3814 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3816 /* First output the expression in the instruction to the pool. */
3817 emit_expr (&(pool
->literals
[entry
]),
3818 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3821 /* Mark the pool as empty. */
3822 pool
->next_free_entry
= 0;
3823 pool
->symbol
= NULL
;
3827 /* Forward declarations for functions below, in the MD interface
3829 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3830 static valueT
create_unwind_entry (int);
3831 static void start_unwind_section (const segT
, int);
3832 static void add_unwind_opcode (valueT
, int);
3833 static void flush_pending_unwind (void);
3835 /* Directives: Data. */
3838 s_arm_elf_cons (int nbytes
)
3842 #ifdef md_flush_pending_output
3843 md_flush_pending_output ();
3846 if (is_it_end_of_statement ())
3848 demand_empty_rest_of_line ();
3852 #ifdef md_cons_align
3853 md_cons_align (nbytes
);
3856 mapping_state (MAP_DATA
);
3860 char *base
= input_line_pointer
;
3864 if (exp
.X_op
!= O_symbol
)
3865 emit_expr (&exp
, (unsigned int) nbytes
);
3868 char *before_reloc
= input_line_pointer
;
3869 reloc
= parse_reloc (&input_line_pointer
);
3872 as_bad (_("unrecognized relocation suffix"));
3873 ignore_rest_of_line ();
3876 else if (reloc
== BFD_RELOC_UNUSED
)
3877 emit_expr (&exp
, (unsigned int) nbytes
);
3880 reloc_howto_type
*howto
= (reloc_howto_type
*)
3881 bfd_reloc_type_lookup (stdoutput
,
3882 (bfd_reloc_code_real_type
) reloc
);
3883 int size
= bfd_get_reloc_size (howto
);
3885 if (reloc
== BFD_RELOC_ARM_PLT32
)
3887 as_bad (_("(plt) is only valid on branch targets"));
3888 reloc
= BFD_RELOC_UNUSED
;
3893 as_bad (ngettext ("%s relocations do not fit in %d byte",
3894 "%s relocations do not fit in %d bytes",
3896 howto
->name
, nbytes
);
3899 /* We've parsed an expression stopping at O_symbol.
3900 But there may be more expression left now that we
3901 have parsed the relocation marker. Parse it again.
3902 XXX Surely there is a cleaner way to do this. */
3903 char *p
= input_line_pointer
;
3905 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3907 memcpy (save_buf
, base
, input_line_pointer
- base
);
3908 memmove (base
+ (input_line_pointer
- before_reloc
),
3909 base
, before_reloc
- base
);
3911 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3913 memcpy (base
, save_buf
, p
- base
);
3915 offset
= nbytes
- size
;
3916 p
= frag_more (nbytes
);
3917 memset (p
, 0, nbytes
);
3918 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3919 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3925 while (*input_line_pointer
++ == ',');
3927 /* Put terminator back into stream. */
3928 input_line_pointer
--;
3929 demand_empty_rest_of_line ();
3932 /* Emit an expression containing a 32-bit thumb instruction.
3933 Implementation based on put_thumb32_insn. */
3936 emit_thumb32_expr (expressionS
* exp
)
3938 expressionS exp_high
= *exp
;
3940 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3941 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3942 exp
->X_add_number
&= 0xffff;
3943 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3946 /* Guess the instruction size based on the opcode. */
3949 thumb_insn_size (int opcode
)
3951 if ((unsigned int) opcode
< 0xe800u
)
3953 else if ((unsigned int) opcode
>= 0xe8000000u
)
3960 emit_insn (expressionS
*exp
, int nbytes
)
3964 if (exp
->X_op
== O_constant
)
3969 size
= thumb_insn_size (exp
->X_add_number
);
3973 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3975 as_bad (_(".inst.n operand too big. "\
3976 "Use .inst.w instead"));
3981 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3982 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3984 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3986 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3987 emit_thumb32_expr (exp
);
3989 emit_expr (exp
, (unsigned int) size
);
3991 it_fsm_post_encode ();
3995 as_bad (_("cannot determine Thumb instruction size. " \
3996 "Use .inst.n/.inst.w instead"));
3999 as_bad (_("constant expression required"));
4004 /* Like s_arm_elf_cons but do not use md_cons_align and
4005 set the mapping state to MAP_ARM/MAP_THUMB. */
4008 s_arm_elf_inst (int nbytes
)
4010 if (is_it_end_of_statement ())
4012 demand_empty_rest_of_line ();
4016 /* Calling mapping_state () here will not change ARM/THUMB,
4017 but will ensure not to be in DATA state. */
4020 mapping_state (MAP_THUMB
);
4025 as_bad (_("width suffixes are invalid in ARM mode"));
4026 ignore_rest_of_line ();
4032 mapping_state (MAP_ARM
);
4041 if (! emit_insn (& exp
, nbytes
))
4043 ignore_rest_of_line ();
4047 while (*input_line_pointer
++ == ',');
4049 /* Put terminator back into stream. */
4050 input_line_pointer
--;
4051 demand_empty_rest_of_line ();
4054 /* Parse a .rel31 directive. */
4057 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
4064 if (*input_line_pointer
== '1')
4065 highbit
= 0x80000000;
4066 else if (*input_line_pointer
!= '0')
4067 as_bad (_("expected 0 or 1"));
4069 input_line_pointer
++;
4070 if (*input_line_pointer
!= ',')
4071 as_bad (_("missing comma"));
4072 input_line_pointer
++;
4074 #ifdef md_flush_pending_output
4075 md_flush_pending_output ();
4078 #ifdef md_cons_align
4082 mapping_state (MAP_DATA
);
4087 md_number_to_chars (p
, highbit
, 4);
4088 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4089 BFD_RELOC_ARM_PREL31
);
4091 demand_empty_rest_of_line ();
4094 /* Directives: AEABI stack-unwind tables. */
4096 /* Parse an unwind_fnstart directive. Simply records the current location. */
4099 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4101 demand_empty_rest_of_line ();
4102 if (unwind
.proc_start
)
4104 as_bad (_("duplicate .fnstart directive"));
4108 /* Mark the start of the function. */
4109 unwind
.proc_start
= expr_build_dot ();
4111 /* Reset the rest of the unwind info. */
4112 unwind
.opcode_count
= 0;
4113 unwind
.table_entry
= NULL
;
4114 unwind
.personality_routine
= NULL
;
4115 unwind
.personality_index
= -1;
4116 unwind
.frame_size
= 0;
4117 unwind
.fp_offset
= 0;
4118 unwind
.fp_reg
= REG_SP
;
4120 unwind
.sp_restored
= 0;
4124 /* Parse a handlerdata directive. Creates the exception handling table entry
4125 for the function. */
4128 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4130 demand_empty_rest_of_line ();
4131 if (!unwind
.proc_start
)
4132 as_bad (MISSING_FNSTART
);
4134 if (unwind
.table_entry
)
4135 as_bad (_("duplicate .handlerdata directive"));
4137 create_unwind_entry (1);
4140 /* Parse an unwind_fnend directive. Generates the index table entry. */
4143 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4148 unsigned int marked_pr_dependency
;
4150 demand_empty_rest_of_line ();
4152 if (!unwind
.proc_start
)
4154 as_bad (_(".fnend directive without .fnstart"));
4158 /* Add eh table entry. */
4159 if (unwind
.table_entry
== NULL
)
4160 val
= create_unwind_entry (0);
4164 /* Add index table entry. This is two words. */
4165 start_unwind_section (unwind
.saved_seg
, 1);
4166 frag_align (2, 0, 0);
4167 record_alignment (now_seg
, 2);
4169 ptr
= frag_more (8);
4171 where
= frag_now_fix () - 8;
4173 /* Self relative offset of the function start. */
4174 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4175 BFD_RELOC_ARM_PREL31
);
4177 /* Indicate dependency on EHABI-defined personality routines to the
4178 linker, if it hasn't been done already. */
4179 marked_pr_dependency
4180 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4181 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4182 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4184 static const char *const name
[] =
4186 "__aeabi_unwind_cpp_pr0",
4187 "__aeabi_unwind_cpp_pr1",
4188 "__aeabi_unwind_cpp_pr2"
4190 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4191 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4192 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4193 |= 1 << unwind
.personality_index
;
4197 /* Inline exception table entry. */
4198 md_number_to_chars (ptr
+ 4, val
, 4);
4200 /* Self relative offset of the table entry. */
4201 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4202 BFD_RELOC_ARM_PREL31
);
4204 /* Restore the original section. */
4205 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4207 unwind
.proc_start
= NULL
;
4211 /* Parse an unwind_cantunwind directive. */
4214 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4216 demand_empty_rest_of_line ();
4217 if (!unwind
.proc_start
)
4218 as_bad (MISSING_FNSTART
);
4220 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4221 as_bad (_("personality routine specified for cantunwind frame"));
4223 unwind
.personality_index
= -2;
4227 /* Parse a personalityindex directive. */
4230 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4234 if (!unwind
.proc_start
)
4235 as_bad (MISSING_FNSTART
);
4237 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4238 as_bad (_("duplicate .personalityindex directive"));
4242 if (exp
.X_op
!= O_constant
4243 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4245 as_bad (_("bad personality routine number"));
4246 ignore_rest_of_line ();
4250 unwind
.personality_index
= exp
.X_add_number
;
4252 demand_empty_rest_of_line ();
4256 /* Parse a personality directive. */
4259 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4263 if (!unwind
.proc_start
)
4264 as_bad (MISSING_FNSTART
);
4266 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4267 as_bad (_("duplicate .personality directive"));
4269 c
= get_symbol_name (& name
);
4270 p
= input_line_pointer
;
4272 ++ input_line_pointer
;
4273 unwind
.personality_routine
= symbol_find_or_make (name
);
4275 demand_empty_rest_of_line ();
4279 /* Parse a directive saving core registers. */
4282 s_arm_unwind_save_core (void)
4288 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4291 as_bad (_("expected register list"));
4292 ignore_rest_of_line ();
4296 demand_empty_rest_of_line ();
4298 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4299 into .unwind_save {..., sp...}. We aren't bothered about the value of
4300 ip because it is clobbered by calls. */
4301 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4302 && (range
& 0x3000) == 0x1000)
4304 unwind
.opcode_count
--;
4305 unwind
.sp_restored
= 0;
4306 range
= (range
| 0x2000) & ~0x1000;
4307 unwind
.pending_offset
= 0;
4313 /* See if we can use the short opcodes. These pop a block of up to 8
4314 registers starting with r4, plus maybe r14. */
4315 for (n
= 0; n
< 8; n
++)
4317 /* Break at the first non-saved register. */
4318 if ((range
& (1 << (n
+ 4))) == 0)
4321 /* See if there are any other bits set. */
4322 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4324 /* Use the long form. */
4325 op
= 0x8000 | ((range
>> 4) & 0xfff);
4326 add_unwind_opcode (op
, 2);
4330 /* Use the short form. */
4332 op
= 0xa8; /* Pop r14. */
4334 op
= 0xa0; /* Do not pop r14. */
4336 add_unwind_opcode (op
, 1);
4343 op
= 0xb100 | (range
& 0xf);
4344 add_unwind_opcode (op
, 2);
4347 /* Record the number of bytes pushed. */
4348 for (n
= 0; n
< 16; n
++)
4350 if (range
& (1 << n
))
4351 unwind
.frame_size
+= 4;
4356 /* Parse a directive saving FPA registers. */
4359 s_arm_unwind_save_fpa (int reg
)
4365 /* Get Number of registers to transfer. */
4366 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4369 exp
.X_op
= O_illegal
;
4371 if (exp
.X_op
!= O_constant
)
4373 as_bad (_("expected , <constant>"));
4374 ignore_rest_of_line ();
4378 num_regs
= exp
.X_add_number
;
4380 if (num_regs
< 1 || num_regs
> 4)
4382 as_bad (_("number of registers must be in the range [1:4]"));
4383 ignore_rest_of_line ();
4387 demand_empty_rest_of_line ();
4392 op
= 0xb4 | (num_regs
- 1);
4393 add_unwind_opcode (op
, 1);
4398 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4399 add_unwind_opcode (op
, 2);
4401 unwind
.frame_size
+= num_regs
* 12;
4405 /* Parse a directive saving VFP registers for ARMv6 and above. */
4408 s_arm_unwind_save_vfp_armv6 (void)
4413 int num_vfpv3_regs
= 0;
4414 int num_regs_below_16
;
4415 bfd_boolean partial_match
;
4417 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4421 as_bad (_("expected register list"));
4422 ignore_rest_of_line ();
4426 demand_empty_rest_of_line ();
4428 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4429 than FSTMX/FLDMX-style ones). */
4431 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4433 num_vfpv3_regs
= count
;
4434 else if (start
+ count
> 16)
4435 num_vfpv3_regs
= start
+ count
- 16;
4437 if (num_vfpv3_regs
> 0)
4439 int start_offset
= start
> 16 ? start
- 16 : 0;
4440 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4441 add_unwind_opcode (op
, 2);
4444 /* Generate opcode for registers numbered in the range 0 .. 15. */
4445 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4446 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4447 if (num_regs_below_16
> 0)
4449 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4450 add_unwind_opcode (op
, 2);
4453 unwind
.frame_size
+= count
* 8;
4457 /* Parse a directive saving VFP registers for pre-ARMv6. */
4460 s_arm_unwind_save_vfp (void)
4465 bfd_boolean partial_match
;
4467 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4471 as_bad (_("expected register list"));
4472 ignore_rest_of_line ();
4476 demand_empty_rest_of_line ();
4481 op
= 0xb8 | (count
- 1);
4482 add_unwind_opcode (op
, 1);
4487 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4488 add_unwind_opcode (op
, 2);
4490 unwind
.frame_size
+= count
* 8 + 4;
4494 /* Parse a directive saving iWMMXt data registers. */
4497 s_arm_unwind_save_mmxwr (void)
4505 if (*input_line_pointer
== '{')
4506 input_line_pointer
++;
4510 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4514 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4519 as_tsktsk (_("register list not in ascending order"));
4522 if (*input_line_pointer
== '-')
4524 input_line_pointer
++;
4525 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4528 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4531 else if (reg
>= hi_reg
)
4533 as_bad (_("bad register range"));
4536 for (; reg
< hi_reg
; reg
++)
4540 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4542 skip_past_char (&input_line_pointer
, '}');
4544 demand_empty_rest_of_line ();
4546 /* Generate any deferred opcodes because we're going to be looking at
4548 flush_pending_unwind ();
4550 for (i
= 0; i
< 16; i
++)
4552 if (mask
& (1 << i
))
4553 unwind
.frame_size
+= 8;
4556 /* Attempt to combine with a previous opcode. We do this because gcc
4557 likes to output separate unwind directives for a single block of
4559 if (unwind
.opcode_count
> 0)
4561 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4562 if ((i
& 0xf8) == 0xc0)
4565 /* Only merge if the blocks are contiguous. */
4568 if ((mask
& 0xfe00) == (1 << 9))
4570 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4571 unwind
.opcode_count
--;
4574 else if (i
== 6 && unwind
.opcode_count
>= 2)
4576 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4580 op
= 0xffff << (reg
- 1);
4582 && ((mask
& op
) == (1u << (reg
- 1))))
4584 op
= (1 << (reg
+ i
+ 1)) - 1;
4585 op
&= ~((1 << reg
) - 1);
4587 unwind
.opcode_count
-= 2;
4594 /* We want to generate opcodes in the order the registers have been
4595 saved, ie. descending order. */
4596 for (reg
= 15; reg
>= -1; reg
--)
4598 /* Save registers in blocks. */
4600 || !(mask
& (1 << reg
)))
4602 /* We found an unsaved reg. Generate opcodes to save the
4609 op
= 0xc0 | (hi_reg
- 10);
4610 add_unwind_opcode (op
, 1);
4615 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4616 add_unwind_opcode (op
, 2);
4625 ignore_rest_of_line ();
4629 s_arm_unwind_save_mmxwcg (void)
4636 if (*input_line_pointer
== '{')
4637 input_line_pointer
++;
4639 skip_whitespace (input_line_pointer
);
4643 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4647 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4653 as_tsktsk (_("register list not in ascending order"));
4656 if (*input_line_pointer
== '-')
4658 input_line_pointer
++;
4659 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4662 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4665 else if (reg
>= hi_reg
)
4667 as_bad (_("bad register range"));
4670 for (; reg
< hi_reg
; reg
++)
4674 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4676 skip_past_char (&input_line_pointer
, '}');
4678 demand_empty_rest_of_line ();
4680 /* Generate any deferred opcodes because we're going to be looking at
4682 flush_pending_unwind ();
4684 for (reg
= 0; reg
< 16; reg
++)
4686 if (mask
& (1 << reg
))
4687 unwind
.frame_size
+= 4;
4690 add_unwind_opcode (op
, 2);
4693 ignore_rest_of_line ();
4697 /* Parse an unwind_save directive.
4698 If the argument is non-zero, this is a .vsave directive. */
4701 s_arm_unwind_save (int arch_v6
)
4704 struct reg_entry
*reg
;
4705 bfd_boolean had_brace
= FALSE
;
4707 if (!unwind
.proc_start
)
4708 as_bad (MISSING_FNSTART
);
4710 /* Figure out what sort of save we have. */
4711 peek
= input_line_pointer
;
4719 reg
= arm_reg_parse_multi (&peek
);
4723 as_bad (_("register expected"));
4724 ignore_rest_of_line ();
4733 as_bad (_("FPA .unwind_save does not take a register list"));
4734 ignore_rest_of_line ();
4737 input_line_pointer
= peek
;
4738 s_arm_unwind_save_fpa (reg
->number
);
4742 s_arm_unwind_save_core ();
4747 s_arm_unwind_save_vfp_armv6 ();
4749 s_arm_unwind_save_vfp ();
4752 case REG_TYPE_MMXWR
:
4753 s_arm_unwind_save_mmxwr ();
4756 case REG_TYPE_MMXWCG
:
4757 s_arm_unwind_save_mmxwcg ();
4761 as_bad (_(".unwind_save does not support this kind of register"));
4762 ignore_rest_of_line ();
4767 /* Parse an unwind_movsp directive. */
4770 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4776 if (!unwind
.proc_start
)
4777 as_bad (MISSING_FNSTART
);
4779 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4782 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4783 ignore_rest_of_line ();
4787 /* Optional constant. */
4788 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4790 if (immediate_for_directive (&offset
) == FAIL
)
4796 demand_empty_rest_of_line ();
4798 if (reg
== REG_SP
|| reg
== REG_PC
)
4800 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4804 if (unwind
.fp_reg
!= REG_SP
)
4805 as_bad (_("unexpected .unwind_movsp directive"));
4807 /* Generate opcode to restore the value. */
4809 add_unwind_opcode (op
, 1);
4811 /* Record the information for later. */
4812 unwind
.fp_reg
= reg
;
4813 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4814 unwind
.sp_restored
= 1;
4817 /* Parse an unwind_pad directive. */
4820 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4824 if (!unwind
.proc_start
)
4825 as_bad (MISSING_FNSTART
);
4827 if (immediate_for_directive (&offset
) == FAIL
)
4832 as_bad (_("stack increment must be multiple of 4"));
4833 ignore_rest_of_line ();
4837 /* Don't generate any opcodes, just record the details for later. */
4838 unwind
.frame_size
+= offset
;
4839 unwind
.pending_offset
+= offset
;
4841 demand_empty_rest_of_line ();
4844 /* Parse an unwind_setfp directive. */
4847 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4853 if (!unwind
.proc_start
)
4854 as_bad (MISSING_FNSTART
);
4856 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4857 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4860 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4862 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4864 as_bad (_("expected <reg>, <reg>"));
4865 ignore_rest_of_line ();
4869 /* Optional constant. */
4870 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4872 if (immediate_for_directive (&offset
) == FAIL
)
4878 demand_empty_rest_of_line ();
4880 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4882 as_bad (_("register must be either sp or set by a previous"
4883 "unwind_movsp directive"));
4887 /* Don't generate any opcodes, just record the information for later. */
4888 unwind
.fp_reg
= fp_reg
;
4890 if (sp_reg
== REG_SP
)
4891 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4893 unwind
.fp_offset
-= offset
;
4896 /* Parse an unwind_raw directive. */
4899 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4902 /* This is an arbitrary limit. */
4903 unsigned char op
[16];
4906 if (!unwind
.proc_start
)
4907 as_bad (MISSING_FNSTART
);
4910 if (exp
.X_op
== O_constant
4911 && skip_past_comma (&input_line_pointer
) != FAIL
)
4913 unwind
.frame_size
+= exp
.X_add_number
;
4917 exp
.X_op
= O_illegal
;
4919 if (exp
.X_op
!= O_constant
)
4921 as_bad (_("expected <offset>, <opcode>"));
4922 ignore_rest_of_line ();
4928 /* Parse the opcode. */
4933 as_bad (_("unwind opcode too long"));
4934 ignore_rest_of_line ();
4936 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4938 as_bad (_("invalid unwind opcode"));
4939 ignore_rest_of_line ();
4942 op
[count
++] = exp
.X_add_number
;
4944 /* Parse the next byte. */
4945 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4951 /* Add the opcode bytes in reverse order. */
4953 add_unwind_opcode (op
[count
], 1);
4955 demand_empty_rest_of_line ();
4959 /* Parse a .eabi_attribute directive. */
4962 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4964 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4966 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4967 attributes_set_explicitly
[tag
] = 1;
4970 /* Emit a tls fix for the symbol. */
4973 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4977 #ifdef md_flush_pending_output
4978 md_flush_pending_output ();
4981 #ifdef md_cons_align
4985 /* Since we're just labelling the code, there's no need to define a
4988 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4989 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4990 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4991 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4993 #endif /* OBJ_ELF */
4995 static void s_arm_arch (int);
4996 static void s_arm_object_arch (int);
4997 static void s_arm_cpu (int);
4998 static void s_arm_fpu (int);
4999 static void s_arm_arch_extension (int);
5004 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
5011 if (exp
.X_op
== O_symbol
)
5012 exp
.X_op
= O_secrel
;
5014 emit_expr (&exp
, 4);
5016 while (*input_line_pointer
++ == ',');
5018 input_line_pointer
--;
5019 demand_empty_rest_of_line ();
5024 arm_is_largest_exponent_ok (int precision
)
5026 /* precision == 1 ensures that this will only return
5027 true for 16 bit floats. */
5028 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
5032 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
5036 enum fp_16bit_format new_format
;
5038 new_format
= ARM_FP16_FORMAT_DEFAULT
;
5040 name
= input_line_pointer
;
5041 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
5042 input_line_pointer
++;
5044 saved_char
= *input_line_pointer
;
5045 *input_line_pointer
= 0;
5047 if (strcasecmp (name
, "ieee") == 0)
5048 new_format
= ARM_FP16_FORMAT_IEEE
;
5049 else if (strcasecmp (name
, "alternative") == 0)
5050 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
5053 as_bad (_("unrecognised float16 format \"%s\""), name
);
5057 /* Only set fp16_format if it is still the default (aka not already
5059 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
5060 fp16_format
= new_format
;
5063 if (new_format
!= fp16_format
)
5064 as_warn (_("float16 format cannot be set more than once, ignoring."));
5068 *input_line_pointer
= saved_char
;
5069 ignore_rest_of_line ();
5072 /* This table describes all the machine specific pseudo-ops the assembler
5073 has to support. The fields are:
5074 pseudo-op name without dot
5075 function to call to execute this pseudo-op
5076 Integer arg to pass to the function. */
5078 const pseudo_typeS md_pseudo_table
[] =
5080 /* Never called because '.req' does not start a line. */
5081 { "req", s_req
, 0 },
5082 /* Following two are likewise never called. */
5085 { "unreq", s_unreq
, 0 },
5086 { "bss", s_bss
, 0 },
5087 { "align", s_align_ptwo
, 2 },
5088 { "arm", s_arm
, 0 },
5089 { "thumb", s_thumb
, 0 },
5090 { "code", s_code
, 0 },
5091 { "force_thumb", s_force_thumb
, 0 },
5092 { "thumb_func", s_thumb_func
, 0 },
5093 { "thumb_set", s_thumb_set
, 0 },
5094 { "even", s_even
, 0 },
5095 { "ltorg", s_ltorg
, 0 },
5096 { "pool", s_ltorg
, 0 },
5097 { "syntax", s_syntax
, 0 },
5098 { "cpu", s_arm_cpu
, 0 },
5099 { "arch", s_arm_arch
, 0 },
5100 { "object_arch", s_arm_object_arch
, 0 },
5101 { "fpu", s_arm_fpu
, 0 },
5102 { "arch_extension", s_arm_arch_extension
, 0 },
5104 { "word", s_arm_elf_cons
, 4 },
5105 { "long", s_arm_elf_cons
, 4 },
5106 { "inst.n", s_arm_elf_inst
, 2 },
5107 { "inst.w", s_arm_elf_inst
, 4 },
5108 { "inst", s_arm_elf_inst
, 0 },
5109 { "rel31", s_arm_rel31
, 0 },
5110 { "fnstart", s_arm_unwind_fnstart
, 0 },
5111 { "fnend", s_arm_unwind_fnend
, 0 },
5112 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5113 { "personality", s_arm_unwind_personality
, 0 },
5114 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5115 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5116 { "save", s_arm_unwind_save
, 0 },
5117 { "vsave", s_arm_unwind_save
, 1 },
5118 { "movsp", s_arm_unwind_movsp
, 0 },
5119 { "pad", s_arm_unwind_pad
, 0 },
5120 { "setfp", s_arm_unwind_setfp
, 0 },
5121 { "unwind_raw", s_arm_unwind_raw
, 0 },
5122 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5123 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5127 /* These are used for dwarf. */
5131 /* These are used for dwarf2. */
5132 { "file", dwarf2_directive_file
, 0 },
5133 { "loc", dwarf2_directive_loc
, 0 },
5134 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5136 { "extend", float_cons
, 'x' },
5137 { "ldouble", float_cons
, 'x' },
5138 { "packed", float_cons
, 'p' },
5139 { "bfloat16", float_cons
, 'b' },
5141 {"secrel32", pe_directive_secrel
, 0},
5144 /* These are for compatibility with CodeComposer Studio. */
5145 {"ref", s_ccs_ref
, 0},
5146 {"def", s_ccs_def
, 0},
5147 {"asmfunc", s_ccs_asmfunc
, 0},
5148 {"endasmfunc", s_ccs_endasmfunc
, 0},
5150 {"float16", float_cons
, 'h' },
5151 {"float16_format", set_fp16_format
, 0 },
5156 /* Parser functions used exclusively in instruction operands. */
5158 /* Generic immediate-value read function for use in insn parsing.
5159 STR points to the beginning of the immediate (the leading #);
5160 VAL receives the value; if the value is outside [MIN, MAX]
5161 issue an error. PREFIX_OPT is true if the immediate prefix is
5165 parse_immediate (char **str
, int *val
, int min
, int max
,
5166 bfd_boolean prefix_opt
)
5170 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5171 if (exp
.X_op
!= O_constant
)
5173 inst
.error
= _("constant expression required");
5177 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5179 inst
.error
= _("immediate value out of range");
5183 *val
= exp
.X_add_number
;
5187 /* Less-generic immediate-value read function with the possibility of loading a
5188 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5189 instructions. Puts the result directly in inst.operands[i]. */
5192 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5193 bfd_boolean allow_symbol_p
)
5196 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5199 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5201 if (exp_p
->X_op
== O_constant
)
5203 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5204 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5205 O_constant. We have to be careful not to break compilation for
5206 32-bit X_add_number, though. */
5207 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5209 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5210 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5212 inst
.operands
[i
].regisimm
= 1;
5215 else if (exp_p
->X_op
== O_big
5216 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5218 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5220 /* Bignums have their least significant bits in
5221 generic_bignum[0]. Make sure we put 32 bits in imm and
5222 32 bits in reg, in a (hopefully) portable way. */
5223 gas_assert (parts
!= 0);
5225 /* Make sure that the number is not too big.
5226 PR 11972: Bignums can now be sign-extended to the
5227 size of a .octa so check that the out of range bits
5228 are all zero or all one. */
5229 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5231 LITTLENUM_TYPE m
= -1;
5233 if (generic_bignum
[parts
* 2] != 0
5234 && generic_bignum
[parts
* 2] != m
)
5237 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5238 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5242 inst
.operands
[i
].imm
= 0;
5243 for (j
= 0; j
< parts
; j
++, idx
++)
5244 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5245 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5246 inst
.operands
[i
].reg
= 0;
5247 for (j
= 0; j
< parts
; j
++, idx
++)
5248 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5249 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5250 inst
.operands
[i
].regisimm
= 1;
5252 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5260 /* Returns the pseudo-register number of an FPA immediate constant,
5261 or FAIL if there isn't a valid constant here. */
5264 parse_fpa_immediate (char ** str
)
5266 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5272 /* First try and match exact strings, this is to guarantee
5273 that some formats will work even for cross assembly. */
5275 for (i
= 0; fp_const
[i
]; i
++)
5277 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5281 *str
+= strlen (fp_const
[i
]);
5282 if (is_end_of_line
[(unsigned char) **str
])
5288 /* Just because we didn't get a match doesn't mean that the constant
5289 isn't valid, just that it is in a format that we don't
5290 automatically recognize. Try parsing it with the standard
5291 expression routines. */
5293 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5295 /* Look for a raw floating point number. */
5296 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5297 && is_end_of_line
[(unsigned char) *save_in
])
5299 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5301 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5303 if (words
[j
] != fp_values
[i
][j
])
5307 if (j
== MAX_LITTLENUMS
)
5315 /* Try and parse a more complex expression, this will probably fail
5316 unless the code uses a floating point prefix (eg "0f"). */
5317 save_in
= input_line_pointer
;
5318 input_line_pointer
= *str
;
5319 if (expression (&exp
) == absolute_section
5320 && exp
.X_op
== O_big
5321 && exp
.X_add_number
< 0)
5323 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5325 #define X_PRECISION 5
5326 #define E_PRECISION 15L
5327 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5329 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5331 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5333 if (words
[j
] != fp_values
[i
][j
])
5337 if (j
== MAX_LITTLENUMS
)
5339 *str
= input_line_pointer
;
5340 input_line_pointer
= save_in
;
5347 *str
= input_line_pointer
;
5348 input_line_pointer
= save_in
;
5349 inst
.error
= _("invalid FPA immediate expression");
5353 /* Returns 1 if a number has "quarter-precision" float format
5354 0baBbbbbbc defgh000 00000000 00000000. */
5357 is_quarter_float (unsigned imm
)
5359 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5360 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5364 /* Detect the presence of a floating point or integer zero constant,
5368 parse_ifimm_zero (char **in
)
5372 if (!is_immediate_prefix (**in
))
5374 /* In unified syntax, all prefixes are optional. */
5375 if (!unified_syntax
)
5381 /* Accept #0x0 as a synonym for #0. */
5382 if (strncmp (*in
, "0x", 2) == 0)
5385 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5390 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5391 &generic_floating_point_number
);
5394 && generic_floating_point_number
.sign
== '+'
5395 && (generic_floating_point_number
.low
5396 > generic_floating_point_number
.leader
))
5402 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5403 0baBbbbbbc defgh000 00000000 00000000.
5404 The zero and minus-zero cases need special handling, since they can't be
5405 encoded in the "quarter-precision" float format, but can nonetheless be
5406 loaded as integer constants. */
5409 parse_qfloat_immediate (char **ccp
, int *immed
)
5413 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5414 int found_fpchar
= 0;
5416 skip_past_char (&str
, '#');
5418 /* We must not accidentally parse an integer as a floating-point number. Make
5419 sure that the value we parse is not an integer by checking for special
5420 characters '.' or 'e'.
5421 FIXME: This is a horrible hack, but doing better is tricky because type
5422 information isn't in a very usable state at parse time. */
5424 skip_whitespace (fpnum
);
5426 if (strncmp (fpnum
, "0x", 2) == 0)
5430 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5431 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5441 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5443 unsigned fpword
= 0;
5446 /* Our FP word must be 32 bits (single-precision FP). */
5447 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5449 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5453 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5466 /* Shift operands. */
5469 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5472 struct asm_shift_name
5475 enum shift_kind kind
;
5478 /* Third argument to parse_shift. */
5479 enum parse_shift_mode
5481 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5482 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5483 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5484 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5485 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5486 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5489 /* Parse a <shift> specifier on an ARM data processing instruction.
5490 This has three forms:
5492 (LSL|LSR|ASL|ASR|ROR) Rs
5493 (LSL|LSR|ASL|ASR|ROR) #imm
5496 Note that ASL is assimilated to LSL in the instruction encoding, and
5497 RRX to ROR #0 (which cannot be written as such). */
5500 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5502 const struct asm_shift_name
*shift_name
;
5503 enum shift_kind shift
;
5508 for (p
= *str
; ISALPHA (*p
); p
++)
5513 inst
.error
= _("shift expression expected");
5517 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5520 if (shift_name
== NULL
)
5522 inst
.error
= _("shift expression expected");
5526 shift
= shift_name
->kind
;
5530 case NO_SHIFT_RESTRICT
:
5531 case SHIFT_IMMEDIATE
:
5532 if (shift
== SHIFT_UXTW
)
5534 inst
.error
= _("'UXTW' not allowed here");
5539 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5540 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5542 inst
.error
= _("'LSL' or 'ASR' required");
5547 case SHIFT_LSL_IMMEDIATE
:
5548 if (shift
!= SHIFT_LSL
)
5550 inst
.error
= _("'LSL' required");
5555 case SHIFT_ASR_IMMEDIATE
:
5556 if (shift
!= SHIFT_ASR
)
5558 inst
.error
= _("'ASR' required");
5562 case SHIFT_UXTW_IMMEDIATE
:
5563 if (shift
!= SHIFT_UXTW
)
5565 inst
.error
= _("'UXTW' required");
5573 if (shift
!= SHIFT_RRX
)
5575 /* Whitespace can appear here if the next thing is a bare digit. */
5576 skip_whitespace (p
);
5578 if (mode
== NO_SHIFT_RESTRICT
5579 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5581 inst
.operands
[i
].imm
= reg
;
5582 inst
.operands
[i
].immisreg
= 1;
5584 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5587 inst
.operands
[i
].shift_kind
= shift
;
5588 inst
.operands
[i
].shifted
= 1;
5593 /* Parse a <shifter_operand> for an ARM data processing instruction:
5596 #<immediate>, <rotate>
5600 where <shift> is defined by parse_shift above, and <rotate> is a
5601 multiple of 2 between 0 and 30. Validation of immediate operands
5602 is deferred to md_apply_fix. */
5605 parse_shifter_operand (char **str
, int i
)
5610 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5612 inst
.operands
[i
].reg
= value
;
5613 inst
.operands
[i
].isreg
= 1;
5615 /* parse_shift will override this if appropriate */
5616 inst
.relocs
[0].exp
.X_op
= O_constant
;
5617 inst
.relocs
[0].exp
.X_add_number
= 0;
5619 if (skip_past_comma (str
) == FAIL
)
5622 /* Shift operation on register. */
5623 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5626 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5629 if (skip_past_comma (str
) == SUCCESS
)
5631 /* #x, y -- ie explicit rotation by Y. */
5632 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5635 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5637 inst
.error
= _("constant expression expected");
5641 value
= exp
.X_add_number
;
5642 if (value
< 0 || value
> 30 || value
% 2 != 0)
5644 inst
.error
= _("invalid rotation");
5647 if (inst
.relocs
[0].exp
.X_add_number
< 0
5648 || inst
.relocs
[0].exp
.X_add_number
> 255)
5650 inst
.error
= _("invalid constant");
5654 /* Encode as specified. */
5655 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5659 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5660 inst
.relocs
[0].pc_rel
= 0;
5664 /* Group relocation information. Each entry in the table contains the
5665 textual name of the relocation as may appear in assembler source
5666 and must end with a colon.
5667 Along with this textual name are the relocation codes to be used if
5668 the corresponding instruction is an ALU instruction (ADD or SUB only),
5669 an LDR, an LDRS, or an LDC. */
5671 struct group_reloc_table_entry
5682 /* Varieties of non-ALU group relocation. */
5690 static struct group_reloc_table_entry group_reloc_table
[] =
5691 { /* Program counter relative: */
5693 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5698 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5699 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5700 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5701 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5703 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5708 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5709 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5710 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5711 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5713 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5714 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5715 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5716 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5717 /* Section base relative */
5719 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5724 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5725 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5726 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5727 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5729 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5734 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5735 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5736 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5737 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5739 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5740 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5741 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5742 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5743 /* Absolute thumb alu relocations. */
5745 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5750 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5755 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5760 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5765 /* Given the address of a pointer pointing to the textual name of a group
5766 relocation as may appear in assembler source, attempt to find its details
5767 in group_reloc_table. The pointer will be updated to the character after
5768 the trailing colon. On failure, FAIL will be returned; SUCCESS
5769 otherwise. On success, *entry will be updated to point at the relevant
5770 group_reloc_table entry. */
5773 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5776 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5778 int length
= strlen (group_reloc_table
[i
].name
);
5780 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5781 && (*str
)[length
] == ':')
5783 *out
= &group_reloc_table
[i
];
5784 *str
+= (length
+ 1);
5792 /* Parse a <shifter_operand> for an ARM data processing instruction
5793 (as for parse_shifter_operand) where group relocations are allowed:
5796 #<immediate>, <rotate>
5797 #:<group_reloc>:<expression>
5801 where <group_reloc> is one of the strings defined in group_reloc_table.
5802 The hashes are optional.
5804 Everything else is as for parse_shifter_operand. */
5806 static parse_operand_result
5807 parse_shifter_operand_group_reloc (char **str
, int i
)
5809 /* Determine if we have the sequence of characters #: or just :
5810 coming next. If we do, then we check for a group relocation.
5811 If we don't, punt the whole lot to parse_shifter_operand. */
5813 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5814 || (*str
)[0] == ':')
5816 struct group_reloc_table_entry
*entry
;
5818 if ((*str
)[0] == '#')
5823 /* Try to parse a group relocation. Anything else is an error. */
5824 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5826 inst
.error
= _("unknown group relocation");
5827 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5830 /* We now have the group relocation table entry corresponding to
5831 the name in the assembler source. Next, we parse the expression. */
5832 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5833 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5835 /* Record the relocation type (always the ALU variant here). */
5836 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5837 gas_assert (inst
.relocs
[0].type
!= 0);
5839 return PARSE_OPERAND_SUCCESS
;
5842 return parse_shifter_operand (str
, i
) == SUCCESS
5843 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5845 /* Never reached. */
5848 /* Parse a Neon alignment expression. Information is written to
5849 inst.operands[i]. We assume the initial ':' has been skipped.
5851 align .imm = align << 8, .immisalign=1, .preind=0 */
5852 static parse_operand_result
5853 parse_neon_alignment (char **str
, int i
)
5858 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5860 if (exp
.X_op
!= O_constant
)
5862 inst
.error
= _("alignment must be constant");
5863 return PARSE_OPERAND_FAIL
;
5866 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5867 inst
.operands
[i
].immisalign
= 1;
5868 /* Alignments are not pre-indexes. */
5869 inst
.operands
[i
].preind
= 0;
5872 return PARSE_OPERAND_SUCCESS
;
5875 /* Parse all forms of an ARM address expression. Information is written
5876 to inst.operands[i] and/or inst.relocs[0].
5878 Preindexed addressing (.preind=1):
5880 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5881 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5882 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5883 .shift_kind=shift .relocs[0].exp=shift_imm
5885 These three may have a trailing ! which causes .writeback to be set also.
5887 Postindexed addressing (.postind=1, .writeback=1):
5889 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5890 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5891 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5892 .shift_kind=shift .relocs[0].exp=shift_imm
5894 Unindexed addressing (.preind=0, .postind=0):
5896 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5900 [Rn]{!} shorthand for [Rn,#0]{!}
5901 =immediate .isreg=0 .relocs[0].exp=immediate
5902 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5904 It is the caller's responsibility to check for addressing modes not
5905 supported by the instruction, and to set inst.relocs[0].type. */
5907 static parse_operand_result
5908 parse_address_main (char **str
, int i
, int group_relocations
,
5909 group_reloc_type group_type
)
5914 if (skip_past_char (&p
, '[') == FAIL
)
5916 if (skip_past_char (&p
, '=') == FAIL
)
5918 /* Bare address - translate to PC-relative offset. */
5919 inst
.relocs
[0].pc_rel
= 1;
5920 inst
.operands
[i
].reg
= REG_PC
;
5921 inst
.operands
[i
].isreg
= 1;
5922 inst
.operands
[i
].preind
= 1;
5924 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5925 return PARSE_OPERAND_FAIL
;
5927 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5928 /*allow_symbol_p=*/TRUE
))
5929 return PARSE_OPERAND_FAIL
;
5932 return PARSE_OPERAND_SUCCESS
;
5935 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5936 skip_whitespace (p
);
5938 if (group_type
== GROUP_MVE
)
5940 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5941 struct neon_type_el et
;
5942 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5944 inst
.operands
[i
].isquad
= 1;
5946 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5948 inst
.error
= BAD_ADDR_MODE
;
5949 return PARSE_OPERAND_FAIL
;
5952 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5954 if (group_type
== GROUP_MVE
)
5955 inst
.error
= BAD_ADDR_MODE
;
5957 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5958 return PARSE_OPERAND_FAIL
;
5960 inst
.operands
[i
].reg
= reg
;
5961 inst
.operands
[i
].isreg
= 1;
5963 if (skip_past_comma (&p
) == SUCCESS
)
5965 inst
.operands
[i
].preind
= 1;
5968 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5970 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5971 struct neon_type_el et
;
5972 if (group_type
== GROUP_MVE
5973 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5975 inst
.operands
[i
].immisreg
= 2;
5976 inst
.operands
[i
].imm
= reg
;
5978 if (skip_past_comma (&p
) == SUCCESS
)
5980 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5982 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5983 inst
.relocs
[0].exp
.X_add_number
= 0;
5986 return PARSE_OPERAND_FAIL
;
5989 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5991 inst
.operands
[i
].imm
= reg
;
5992 inst
.operands
[i
].immisreg
= 1;
5994 if (skip_past_comma (&p
) == SUCCESS
)
5995 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5996 return PARSE_OPERAND_FAIL
;
5998 else if (skip_past_char (&p
, ':') == SUCCESS
)
6000 /* FIXME: '@' should be used here, but it's filtered out by generic
6001 code before we get to see it here. This may be subject to
6003 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6005 if (result
!= PARSE_OPERAND_SUCCESS
)
6010 if (inst
.operands
[i
].negative
)
6012 inst
.operands
[i
].negative
= 0;
6016 if (group_relocations
6017 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
6019 struct group_reloc_table_entry
*entry
;
6021 /* Skip over the #: or : sequence. */
6027 /* Try to parse a group relocation. Anything else is an
6029 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
6031 inst
.error
= _("unknown group relocation");
6032 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6035 /* We now have the group relocation table entry corresponding to
6036 the name in the assembler source. Next, we parse the
6038 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6039 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6041 /* Record the relocation type. */
6046 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
6051 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
6056 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
6063 if (inst
.relocs
[0].type
== 0)
6065 inst
.error
= _("this group relocation is not allowed on this instruction");
6066 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6073 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6074 return PARSE_OPERAND_FAIL
;
6075 /* If the offset is 0, find out if it's a +0 or -0. */
6076 if (inst
.relocs
[0].exp
.X_op
== O_constant
6077 && inst
.relocs
[0].exp
.X_add_number
== 0)
6079 skip_whitespace (q
);
6083 skip_whitespace (q
);
6086 inst
.operands
[i
].negative
= 1;
6091 else if (skip_past_char (&p
, ':') == SUCCESS
)
6093 /* FIXME: '@' should be used here, but it's filtered out by generic code
6094 before we get to see it here. This may be subject to change. */
6095 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6097 if (result
!= PARSE_OPERAND_SUCCESS
)
6101 if (skip_past_char (&p
, ']') == FAIL
)
6103 inst
.error
= _("']' expected");
6104 return PARSE_OPERAND_FAIL
;
6107 if (skip_past_char (&p
, '!') == SUCCESS
)
6108 inst
.operands
[i
].writeback
= 1;
6110 else if (skip_past_comma (&p
) == SUCCESS
)
6112 if (skip_past_char (&p
, '{') == SUCCESS
)
6114 /* [Rn], {expr} - unindexed, with option */
6115 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6116 0, 255, TRUE
) == FAIL
)
6117 return PARSE_OPERAND_FAIL
;
6119 if (skip_past_char (&p
, '}') == FAIL
)
6121 inst
.error
= _("'}' expected at end of 'option' field");
6122 return PARSE_OPERAND_FAIL
;
6124 if (inst
.operands
[i
].preind
)
6126 inst
.error
= _("cannot combine index with option");
6127 return PARSE_OPERAND_FAIL
;
6130 return PARSE_OPERAND_SUCCESS
;
6134 inst
.operands
[i
].postind
= 1;
6135 inst
.operands
[i
].writeback
= 1;
6137 if (inst
.operands
[i
].preind
)
6139 inst
.error
= _("cannot combine pre- and post-indexing");
6140 return PARSE_OPERAND_FAIL
;
6144 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6146 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6147 struct neon_type_el et
;
6148 if (group_type
== GROUP_MVE
6149 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6151 inst
.operands
[i
].immisreg
= 2;
6152 inst
.operands
[i
].imm
= reg
;
6154 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6156 /* We might be using the immediate for alignment already. If we
6157 are, OR the register number into the low-order bits. */
6158 if (inst
.operands
[i
].immisalign
)
6159 inst
.operands
[i
].imm
|= reg
;
6161 inst
.operands
[i
].imm
= reg
;
6162 inst
.operands
[i
].immisreg
= 1;
6164 if (skip_past_comma (&p
) == SUCCESS
)
6165 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6166 return PARSE_OPERAND_FAIL
;
6172 if (inst
.operands
[i
].negative
)
6174 inst
.operands
[i
].negative
= 0;
6177 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6178 return PARSE_OPERAND_FAIL
;
6179 /* If the offset is 0, find out if it's a +0 or -0. */
6180 if (inst
.relocs
[0].exp
.X_op
== O_constant
6181 && inst
.relocs
[0].exp
.X_add_number
== 0)
6183 skip_whitespace (q
);
6187 skip_whitespace (q
);
6190 inst
.operands
[i
].negative
= 1;
6196 /* If at this point neither .preind nor .postind is set, we have a
6197 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6198 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6200 inst
.operands
[i
].preind
= 1;
6201 inst
.relocs
[0].exp
.X_op
= O_constant
;
6202 inst
.relocs
[0].exp
.X_add_number
= 0;
6205 return PARSE_OPERAND_SUCCESS
;
6209 parse_address (char **str
, int i
)
6211 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6215 static parse_operand_result
6216 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6218 return parse_address_main (str
, i
, 1, type
);
6221 /* Parse an operand for a MOVW or MOVT instruction. */
6223 parse_half (char **str
)
6228 skip_past_char (&p
, '#');
6229 if (strncasecmp (p
, ":lower16:", 9) == 0)
6230 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6231 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6232 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6234 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6237 skip_whitespace (p
);
6240 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6243 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6245 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6247 inst
.error
= _("constant expression expected");
6250 if (inst
.relocs
[0].exp
.X_add_number
< 0
6251 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6253 inst
.error
= _("immediate value out of range");
6261 /* Miscellaneous. */
6263 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6264 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6266 parse_psr (char **str
, bfd_boolean lhs
)
6269 unsigned long psr_field
;
6270 const struct asm_psr
*psr
;
6272 bfd_boolean is_apsr
= FALSE
;
6273 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6275 /* PR gas/12698: If the user has specified -march=all then m_profile will
6276 be TRUE, but we want to ignore it in this case as we are building for any
6277 CPU type, including non-m variants. */
6278 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6281 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6282 feature for ease of use and backwards compatibility. */
6284 if (strncasecmp (p
, "SPSR", 4) == 0)
6287 goto unsupported_psr
;
6289 psr_field
= SPSR_BIT
;
6291 else if (strncasecmp (p
, "CPSR", 4) == 0)
6294 goto unsupported_psr
;
6298 else if (strncasecmp (p
, "APSR", 4) == 0)
6300 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6301 and ARMv7-R architecture CPUs. */
6310 while (ISALNUM (*p
) || *p
== '_');
6312 if (strncasecmp (start
, "iapsr", 5) == 0
6313 || strncasecmp (start
, "eapsr", 5) == 0
6314 || strncasecmp (start
, "xpsr", 4) == 0
6315 || strncasecmp (start
, "psr", 3) == 0)
6316 p
= start
+ strcspn (start
, "rR") + 1;
6318 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6324 /* If APSR is being written, a bitfield may be specified. Note that
6325 APSR itself is handled above. */
6326 if (psr
->field
<= 3)
6328 psr_field
= psr
->field
;
6334 /* M-profile MSR instructions have the mask field set to "10", except
6335 *PSR variants which modify APSR, which may use a different mask (and
6336 have been handled already). Do that by setting the PSR_f field
6338 return psr
->field
| (lhs
? PSR_f
: 0);
6341 goto unsupported_psr
;
6347 /* A suffix follows. */
6353 while (ISALNUM (*p
) || *p
== '_');
6357 /* APSR uses a notation for bits, rather than fields. */
6358 unsigned int nzcvq_bits
= 0;
6359 unsigned int g_bit
= 0;
6362 for (bit
= start
; bit
!= p
; bit
++)
6364 switch (TOLOWER (*bit
))
6367 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6371 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6375 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6379 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6383 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6387 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6391 inst
.error
= _("unexpected bit specified after APSR");
6396 if (nzcvq_bits
== 0x1f)
6401 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6403 inst
.error
= _("selected processor does not "
6404 "support DSP extension");
6411 if ((nzcvq_bits
& 0x20) != 0
6412 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6413 || (g_bit
& 0x2) != 0)
6415 inst
.error
= _("bad bitmask specified after APSR");
6421 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6426 psr_field
|= psr
->field
;
6432 goto error
; /* Garbage after "[CS]PSR". */
6434 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6435 is deprecated, but allow it anyway. */
6439 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6442 else if (!m_profile
)
6443 /* These bits are never right for M-profile devices: don't set them
6444 (only code paths which read/write APSR reach here). */
6445 psr_field
|= (PSR_c
| PSR_f
);
6451 inst
.error
= _("selected processor does not support requested special "
6452 "purpose register");
6456 inst
.error
= _("flag for {c}psr instruction expected");
6461 parse_sys_vldr_vstr (char **str
)
6470 {"FPSCR", 0x1, 0x0},
6471 {"FPSCR_nzcvqc", 0x2, 0x0},
6474 {"FPCXTNS", 0x6, 0x1},
6475 {"FPCXTS", 0x7, 0x1}
6477 char *op_end
= strchr (*str
, ',');
6478 size_t op_strlen
= op_end
- *str
;
6480 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6482 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6484 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6493 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6494 value suitable for splatting into the AIF field of the instruction. */
6497 parse_cps_flags (char **str
)
6506 case '\0': case ',':
6509 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6510 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6511 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6514 inst
.error
= _("unrecognized CPS flag");
6519 if (saw_a_flag
== 0)
6521 inst
.error
= _("missing CPS flags");
6529 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6530 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6533 parse_endian_specifier (char **str
)
6538 if (strncasecmp (s
, "BE", 2))
6540 else if (strncasecmp (s
, "LE", 2))
6544 inst
.error
= _("valid endian specifiers are be or le");
6548 if (ISALNUM (s
[2]) || s
[2] == '_')
6550 inst
.error
= _("valid endian specifiers are be or le");
6555 return little_endian
;
6558 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6559 value suitable for poking into the rotate field of an sxt or sxta
6560 instruction, or FAIL on error. */
6563 parse_ror (char **str
)
6568 if (strncasecmp (s
, "ROR", 3) == 0)
6572 inst
.error
= _("missing rotation field after comma");
6576 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6581 case 0: *str
= s
; return 0x0;
6582 case 8: *str
= s
; return 0x1;
6583 case 16: *str
= s
; return 0x2;
6584 case 24: *str
= s
; return 0x3;
6587 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6592 /* Parse a conditional code (from conds[] below). The value returned is in the
6593 range 0 .. 14, or FAIL. */
6595 parse_cond (char **str
)
6598 const struct asm_cond
*c
;
6600 /* Condition codes are always 2 characters, so matching up to
6601 3 characters is sufficient. */
6606 while (ISALPHA (*q
) && n
< 3)
6608 cond
[n
] = TOLOWER (*q
);
6613 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6616 inst
.error
= _("condition required");
6624 /* Parse an option for a barrier instruction. Returns the encoding for the
6627 parse_barrier (char **str
)
6630 const struct asm_barrier_opt
*o
;
6633 while (ISALPHA (*q
))
6636 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6641 if (!mark_feature_used (&o
->arch
))
6648 /* Parse the operands of a table branch instruction. Similar to a memory
6651 parse_tb (char **str
)
6656 if (skip_past_char (&p
, '[') == FAIL
)
6658 inst
.error
= _("'[' expected");
6662 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6664 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6667 inst
.operands
[0].reg
= reg
;
6669 if (skip_past_comma (&p
) == FAIL
)
6671 inst
.error
= _("',' expected");
6675 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6677 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6680 inst
.operands
[0].imm
= reg
;
6682 if (skip_past_comma (&p
) == SUCCESS
)
6684 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6686 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6688 inst
.error
= _("invalid shift");
6691 inst
.operands
[0].shifted
= 1;
6694 if (skip_past_char (&p
, ']') == FAIL
)
6696 inst
.error
= _("']' expected");
6703 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6704 information on the types the operands can take and how they are encoded.
6705 Up to four operands may be read; this function handles setting the
6706 ".present" field for each read operand itself.
6707 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6708 else returns FAIL. */
6711 parse_neon_mov (char **str
, int *which_operand
)
6713 int i
= *which_operand
, val
;
6714 enum arm_reg_type rtype
;
6716 struct neon_type_el optype
;
6718 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6720 /* Cases 17 or 19. */
6721 inst
.operands
[i
].reg
= val
;
6722 inst
.operands
[i
].isvec
= 1;
6723 inst
.operands
[i
].isscalar
= 2;
6724 inst
.operands
[i
].vectype
= optype
;
6725 inst
.operands
[i
++].present
= 1;
6727 if (skip_past_comma (&ptr
) == FAIL
)
6730 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6732 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6733 inst
.operands
[i
].reg
= val
;
6734 inst
.operands
[i
].isreg
= 1;
6735 inst
.operands
[i
].present
= 1;
6737 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6739 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6740 inst
.operands
[i
].reg
= val
;
6741 inst
.operands
[i
].isvec
= 1;
6742 inst
.operands
[i
].isscalar
= 2;
6743 inst
.operands
[i
].vectype
= optype
;
6744 inst
.operands
[i
++].present
= 1;
6746 if (skip_past_comma (&ptr
) == FAIL
)
6749 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6752 inst
.operands
[i
].reg
= val
;
6753 inst
.operands
[i
].isreg
= 1;
6754 inst
.operands
[i
++].present
= 1;
6756 if (skip_past_comma (&ptr
) == FAIL
)
6759 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6762 inst
.operands
[i
].reg
= val
;
6763 inst
.operands
[i
].isreg
= 1;
6764 inst
.operands
[i
].present
= 1;
6768 first_error (_("expected ARM or MVE vector register"));
6772 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6774 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6775 inst
.operands
[i
].reg
= val
;
6776 inst
.operands
[i
].isscalar
= 1;
6777 inst
.operands
[i
].vectype
= optype
;
6778 inst
.operands
[i
++].present
= 1;
6780 if (skip_past_comma (&ptr
) == FAIL
)
6783 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6786 inst
.operands
[i
].reg
= val
;
6787 inst
.operands
[i
].isreg
= 1;
6788 inst
.operands
[i
].present
= 1;
6790 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6792 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6795 /* Cases 0, 1, 2, 3, 5 (D only). */
6796 if (skip_past_comma (&ptr
) == FAIL
)
6799 inst
.operands
[i
].reg
= val
;
6800 inst
.operands
[i
].isreg
= 1;
6801 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6802 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6803 inst
.operands
[i
].isvec
= 1;
6804 inst
.operands
[i
].vectype
= optype
;
6805 inst
.operands
[i
++].present
= 1;
6807 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6809 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6810 Case 13: VMOV <Sd>, <Rm> */
6811 inst
.operands
[i
].reg
= val
;
6812 inst
.operands
[i
].isreg
= 1;
6813 inst
.operands
[i
].present
= 1;
6815 if (rtype
== REG_TYPE_NQ
)
6817 first_error (_("can't use Neon quad register here"));
6820 else if (rtype
!= REG_TYPE_VFS
)
6823 if (skip_past_comma (&ptr
) == FAIL
)
6825 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6827 inst
.operands
[i
].reg
= val
;
6828 inst
.operands
[i
].isreg
= 1;
6829 inst
.operands
[i
].present
= 1;
6832 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6834 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6837 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6838 Case 1: VMOV<c><q> <Dd>, <Dm>
6839 Case 8: VMOV.F32 <Sd>, <Sm>
6840 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6842 inst
.operands
[i
].reg
= val
;
6843 inst
.operands
[i
].isreg
= 1;
6844 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6845 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6846 inst
.operands
[i
].isvec
= 1;
6847 inst
.operands
[i
].vectype
= optype
;
6848 inst
.operands
[i
].present
= 1;
6850 if (skip_past_comma (&ptr
) == SUCCESS
)
6855 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6858 inst
.operands
[i
].reg
= val
;
6859 inst
.operands
[i
].isreg
= 1;
6860 inst
.operands
[i
++].present
= 1;
6862 if (skip_past_comma (&ptr
) == FAIL
)
6865 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6868 inst
.operands
[i
].reg
= val
;
6869 inst
.operands
[i
].isreg
= 1;
6870 inst
.operands
[i
].present
= 1;
6873 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6874 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6875 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6876 Case 10: VMOV.F32 <Sd>, #<imm>
6877 Case 11: VMOV.F64 <Dd>, #<imm> */
6878 inst
.operands
[i
].immisfloat
= 1;
6879 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6881 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6882 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6886 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6890 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6892 /* Cases 6, 7, 16, 18. */
6893 inst
.operands
[i
].reg
= val
;
6894 inst
.operands
[i
].isreg
= 1;
6895 inst
.operands
[i
++].present
= 1;
6897 if (skip_past_comma (&ptr
) == FAIL
)
6900 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6902 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6903 inst
.operands
[i
].reg
= val
;
6904 inst
.operands
[i
].isscalar
= 2;
6905 inst
.operands
[i
].present
= 1;
6906 inst
.operands
[i
].vectype
= optype
;
6908 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6910 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6911 inst
.operands
[i
].reg
= val
;
6912 inst
.operands
[i
].isscalar
= 1;
6913 inst
.operands
[i
].present
= 1;
6914 inst
.operands
[i
].vectype
= optype
;
6916 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6918 inst
.operands
[i
].reg
= val
;
6919 inst
.operands
[i
].isreg
= 1;
6920 inst
.operands
[i
++].present
= 1;
6922 if (skip_past_comma (&ptr
) == FAIL
)
6925 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6928 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6930 inst
.operands
[i
].reg
= val
;
6931 inst
.operands
[i
].isreg
= 1;
6932 inst
.operands
[i
].isvec
= 1;
6933 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6934 inst
.operands
[i
].vectype
= optype
;
6935 inst
.operands
[i
].present
= 1;
6937 if (rtype
== REG_TYPE_VFS
)
6941 if (skip_past_comma (&ptr
) == FAIL
)
6943 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6946 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6949 inst
.operands
[i
].reg
= val
;
6950 inst
.operands
[i
].isreg
= 1;
6951 inst
.operands
[i
].isvec
= 1;
6952 inst
.operands
[i
].issingle
= 1;
6953 inst
.operands
[i
].vectype
= optype
;
6954 inst
.operands
[i
].present
= 1;
6959 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6962 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6963 inst
.operands
[i
].reg
= val
;
6964 inst
.operands
[i
].isvec
= 1;
6965 inst
.operands
[i
].isscalar
= 2;
6966 inst
.operands
[i
].vectype
= optype
;
6967 inst
.operands
[i
++].present
= 1;
6969 if (skip_past_comma (&ptr
) == FAIL
)
6972 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6975 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6978 inst
.operands
[i
].reg
= val
;
6979 inst
.operands
[i
].isvec
= 1;
6980 inst
.operands
[i
].isscalar
= 2;
6981 inst
.operands
[i
].vectype
= optype
;
6982 inst
.operands
[i
].present
= 1;
6986 first_error (_("VFP single, double or MVE vector register"
6992 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6996 inst
.operands
[i
].reg
= val
;
6997 inst
.operands
[i
].isreg
= 1;
6998 inst
.operands
[i
].isvec
= 1;
6999 inst
.operands
[i
].issingle
= 1;
7000 inst
.operands
[i
].vectype
= optype
;
7001 inst
.operands
[i
].present
= 1;
7006 first_error (_("parse error"));
7010 /* Successfully parsed the operands. Update args. */
7016 first_error (_("expected comma"));
7020 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
7024 /* Use this macro when the operand constraints are different
7025 for ARM and THUMB (e.g. ldrd). */
7026 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
7027 ((arm_operand) | ((thumb_operand) << 16))
7029 /* Matcher codes for parse_operands. */
7030 enum operand_parse_code
7032 OP_stop
, /* end of line */
7034 OP_RR
, /* ARM register */
7035 OP_RRnpc
, /* ARM register, not r15 */
7036 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
7037 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
7038 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
7039 optional trailing ! */
7040 OP_RRw
, /* ARM register, not r15, optional trailing ! */
7041 OP_RCP
, /* Coprocessor number */
7042 OP_RCN
, /* Coprocessor register */
7043 OP_RF
, /* FPA register */
7044 OP_RVS
, /* VFP single precision register */
7045 OP_RVD
, /* VFP double precision register (0..15) */
7046 OP_RND
, /* Neon double precision register (0..31) */
7047 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
7048 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
7050 OP_RNQ
, /* Neon quad precision register */
7051 OP_RNQMQ
, /* Neon quad or MVE vector register. */
7052 OP_RVSD
, /* VFP single or double precision register */
7053 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
7054 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
7055 OP_RNSD
, /* Neon single or double precision register */
7056 OP_RNDQ
, /* Neon double or quad precision register */
7057 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
7058 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
7059 OP_RNSDQ
, /* Neon single, double or quad precision register */
7060 OP_RNSC
, /* Neon scalar D[X] */
7061 OP_RVC
, /* VFP control register */
7062 OP_RMF
, /* Maverick F register */
7063 OP_RMD
, /* Maverick D register */
7064 OP_RMFX
, /* Maverick FX register */
7065 OP_RMDX
, /* Maverick DX register */
7066 OP_RMAX
, /* Maverick AX register */
7067 OP_RMDS
, /* Maverick DSPSC register */
7068 OP_RIWR
, /* iWMMXt wR register */
7069 OP_RIWC
, /* iWMMXt wC register */
7070 OP_RIWG
, /* iWMMXt wCG register */
7071 OP_RXA
, /* XScale accumulator register */
7073 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
7075 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
7077 OP_RMQ
, /* MVE vector register. */
7078 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
7079 OP_RMQRR
, /* MVE vector or ARM register. */
7081 /* New operands for Armv8.1-M Mainline. */
7082 OP_LR
, /* ARM LR register */
7083 OP_RRe
, /* ARM register, only even numbered. */
7084 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
7085 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7086 OP_RR_ZR
, /* ARM register or ZR but no PC */
7088 OP_REGLST
, /* ARM register list */
7089 OP_CLRMLST
, /* CLRM register list */
7090 OP_VRSLST
, /* VFP single-precision register list */
7091 OP_VRDLST
, /* VFP double-precision register list */
7092 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7093 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7094 OP_NSTRLST
, /* Neon element/structure list */
7095 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7096 OP_MSTRLST2
, /* MVE vector list with two elements. */
7097 OP_MSTRLST4
, /* MVE vector list with four elements. */
7099 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7100 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7101 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7102 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7104 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7105 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7106 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7107 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7109 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7110 scalar, or ARM register. */
7111 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7112 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7113 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7115 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7116 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7117 OP_VMOV
, /* Neon VMOV operands. */
7118 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7119 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7121 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7122 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7124 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7125 OP_VLDR
, /* VLDR operand. */
7127 OP_I0
, /* immediate zero */
7128 OP_I7
, /* immediate value 0 .. 7 */
7129 OP_I15
, /* 0 .. 15 */
7130 OP_I16
, /* 1 .. 16 */
7131 OP_I16z
, /* 0 .. 16 */
7132 OP_I31
, /* 0 .. 31 */
7133 OP_I31w
, /* 0 .. 31, optional trailing ! */
7134 OP_I32
, /* 1 .. 32 */
7135 OP_I32z
, /* 0 .. 32 */
7136 OP_I48_I64
, /* 48 or 64 */
7137 OP_I63
, /* 0 .. 63 */
7138 OP_I63s
, /* -64 .. 63 */
7139 OP_I64
, /* 1 .. 64 */
7140 OP_I64z
, /* 0 .. 64 */
7141 OP_I255
, /* 0 .. 255 */
7143 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7144 OP_I7b
, /* 0 .. 7 */
7145 OP_I15b
, /* 0 .. 15 */
7146 OP_I31b
, /* 0 .. 31 */
7148 OP_SH
, /* shifter operand */
7149 OP_SHG
, /* shifter operand with possible group relocation */
7150 OP_ADDR
, /* Memory address expression (any mode) */
7151 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7152 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7153 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7154 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7155 OP_EXP
, /* arbitrary expression */
7156 OP_EXPi
, /* same, with optional immediate prefix */
7157 OP_EXPr
, /* same, with optional relocation suffix */
7158 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7159 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7160 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7161 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7163 OP_CPSF
, /* CPS flags */
7164 OP_ENDI
, /* Endianness specifier */
7165 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7166 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7167 OP_COND
, /* conditional code */
7168 OP_TB
, /* Table branch. */
7170 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7172 OP_RRnpc_I0
, /* ARM register or literal 0 */
7173 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7174 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7175 OP_RF_IF
, /* FPA register or immediate */
7176 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7177 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7179 /* Optional operands. */
7180 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7181 OP_oI31b
, /* 0 .. 31 */
7182 OP_oI32b
, /* 1 .. 32 */
7183 OP_oI32z
, /* 0 .. 32 */
7184 OP_oIffffb
, /* 0 .. 65535 */
7185 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7187 OP_oRR
, /* ARM register */
7188 OP_oLR
, /* ARM LR register */
7189 OP_oRRnpc
, /* ARM register, not the PC */
7190 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7191 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7192 OP_oRND
, /* Optional Neon double precision register */
7193 OP_oRNQ
, /* Optional Neon quad precision register */
7194 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7195 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7196 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7197 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7199 OP_oSHll
, /* LSL immediate */
7200 OP_oSHar
, /* ASR immediate */
7201 OP_oSHllar
, /* LSL or ASR immediate */
7202 OP_oROR
, /* ROR 0/8/16/24 */
7203 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7205 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7207 /* Some pre-defined mixed (ARM/THUMB) operands. */
7208 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7209 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7210 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7212 OP_FIRST_OPTIONAL
= OP_oI7b
7215 /* Generic instruction operand parser. This does no encoding and no
7216 semantic validation; it merely squirrels values away in the inst
7217 structure. Returns SUCCESS or FAIL depending on whether the
7218 specified grammar matched. */
7220 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7222 unsigned const int *upat
= pattern
;
7223 char *backtrack_pos
= 0;
7224 const char *backtrack_error
= 0;
7225 int i
, val
= 0, backtrack_index
= 0;
7226 enum arm_reg_type rtype
;
7227 parse_operand_result result
;
7228 unsigned int op_parse_code
;
7229 bfd_boolean partial_match
;
7231 #define po_char_or_fail(chr) \
7234 if (skip_past_char (&str, chr) == FAIL) \
7239 #define po_reg_or_fail(regtype) \
7242 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7243 & inst.operands[i].vectype); \
7246 first_error (_(reg_expected_msgs[regtype])); \
7249 inst.operands[i].reg = val; \
7250 inst.operands[i].isreg = 1; \
7251 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7252 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7253 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7254 || rtype == REG_TYPE_VFD \
7255 || rtype == REG_TYPE_NQ); \
7256 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7260 #define po_reg_or_goto(regtype, label) \
7263 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7264 & inst.operands[i].vectype); \
7268 inst.operands[i].reg = val; \
7269 inst.operands[i].isreg = 1; \
7270 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7271 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7272 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7273 || rtype == REG_TYPE_VFD \
7274 || rtype == REG_TYPE_NQ); \
7275 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7279 #define po_imm_or_fail(min, max, popt) \
7282 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7284 inst.operands[i].imm = val; \
7288 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7292 my_get_expression (&exp, &str, popt); \
7293 if (exp.X_op != O_constant) \
7295 inst.error = _("constant expression required"); \
7298 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7300 inst.error = _("immediate value 48 or 64 expected"); \
7303 inst.operands[i].imm = exp.X_add_number; \
7307 #define po_scalar_or_goto(elsz, label, reg_type) \
7310 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7314 inst.operands[i].reg = val; \
7315 inst.operands[i].isscalar = 1; \
7319 #define po_misc_or_fail(expr) \
7327 #define po_misc_or_fail_no_backtrack(expr) \
7331 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7332 backtrack_pos = 0; \
7333 if (result != PARSE_OPERAND_SUCCESS) \
7338 #define po_barrier_or_imm(str) \
7341 val = parse_barrier (&str); \
7342 if (val == FAIL && ! ISALPHA (*str)) \
7345 /* ISB can only take SY as an option. */ \
7346 || ((inst.instruction & 0xf0) == 0x60 \
7349 inst.error = _("invalid barrier type"); \
7350 backtrack_pos = 0; \
7356 skip_whitespace (str
);
7358 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7360 op_parse_code
= upat
[i
];
7361 if (op_parse_code
>= 1<<16)
7362 op_parse_code
= thumb
? (op_parse_code
>> 16)
7363 : (op_parse_code
& ((1<<16)-1));
7365 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7367 /* Remember where we are in case we need to backtrack. */
7368 backtrack_pos
= str
;
7369 backtrack_error
= inst
.error
;
7370 backtrack_index
= i
;
7373 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7374 po_char_or_fail (',');
7376 switch (op_parse_code
)
7388 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7389 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7390 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7391 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7392 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7393 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7396 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7400 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7403 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7405 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7407 /* Also accept generic coprocessor regs for unknown registers. */
7409 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7411 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7412 existing register with a value of 0, this seems like the
7413 best way to parse P0. */
7415 if (strncasecmp (str
, "P0", 2) == 0)
7418 inst
.operands
[i
].isreg
= 1;
7419 inst
.operands
[i
].reg
= 13;
7424 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7425 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7426 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7427 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7428 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7429 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7430 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7431 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7432 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7433 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7436 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7439 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7440 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7442 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7447 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7451 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7453 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7456 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7458 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7461 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7463 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7468 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7471 po_reg_or_fail (REG_TYPE_NSDQ
);
7475 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7479 po_reg_or_fail (REG_TYPE_MQ
);
7481 /* Neon scalar. Using an element size of 8 means that some invalid
7482 scalars are accepted here, so deal with those in later code. */
7483 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7487 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7490 po_imm_or_fail (0, 0, TRUE
);
7495 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7499 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7504 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7507 if (parse_ifimm_zero (&str
))
7508 inst
.operands
[i
].imm
= 0;
7512 = _("only floating point zero is allowed as immediate value");
7520 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7523 po_reg_or_fail (REG_TYPE_RN
);
7527 case OP_RNSDQ_RNSC_MQ_RR
:
7528 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7531 case OP_RNSDQ_RNSC_MQ
:
7532 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7537 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7541 po_reg_or_fail (REG_TYPE_NSDQ
);
7548 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7551 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7554 po_reg_or_fail (REG_TYPE_NSD
);
7558 case OP_RNDQMQ_RNSC_RR
:
7559 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7562 case OP_RNDQ_RNSC_RR
:
7563 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7565 case OP_RNDQMQ_RNSC
:
7566 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7571 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7574 po_reg_or_fail (REG_TYPE_NDQ
);
7580 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7583 po_reg_or_fail (REG_TYPE_VFD
);
7588 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7589 not careful then bad things might happen. */
7590 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7593 case OP_RNDQMQ_Ibig
:
7594 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7599 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7602 /* There's a possibility of getting a 64-bit immediate here, so
7603 we need special handling. */
7604 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7607 inst
.error
= _("immediate value is out of range");
7613 case OP_RNDQMQ_I63b_RR
:
7614 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7617 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7622 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7625 po_imm_or_fail (0, 63, TRUE
);
7630 po_char_or_fail ('[');
7631 po_reg_or_fail (REG_TYPE_RN
);
7632 po_char_or_fail (']');
7638 po_reg_or_fail (REG_TYPE_RN
);
7639 if (skip_past_char (&str
, '!') == SUCCESS
)
7640 inst
.operands
[i
].writeback
= 1;
7644 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7645 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7646 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7647 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7648 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7649 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7650 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7651 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7652 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7653 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7654 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7655 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7656 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7658 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7660 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7661 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7663 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7664 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7665 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7666 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7668 /* Immediate variants */
7670 po_char_or_fail ('{');
7671 po_imm_or_fail (0, 255, TRUE
);
7672 po_char_or_fail ('}');
7676 /* The expression parser chokes on a trailing !, so we have
7677 to find it first and zap it. */
7680 while (*s
&& *s
!= ',')
7685 inst
.operands
[i
].writeback
= 1;
7687 po_imm_or_fail (0, 31, TRUE
);
7695 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7700 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7705 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7707 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7709 val
= parse_reloc (&str
);
7712 inst
.error
= _("unrecognized relocation suffix");
7715 else if (val
!= BFD_RELOC_UNUSED
)
7717 inst
.operands
[i
].imm
= val
;
7718 inst
.operands
[i
].hasreloc
= 1;
7724 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7726 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7728 inst
.operands
[i
].hasreloc
= 1;
7730 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7732 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7733 inst
.operands
[i
].hasreloc
= 0;
7737 /* Operand for MOVW or MOVT. */
7739 po_misc_or_fail (parse_half (&str
));
7742 /* Register or expression. */
7743 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7744 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7746 /* Register or immediate. */
7747 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7748 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7750 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7751 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7753 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7755 if (!is_immediate_prefix (*str
))
7758 val
= parse_fpa_immediate (&str
);
7761 /* FPA immediates are encoded as registers 8-15.
7762 parse_fpa_immediate has already applied the offset. */
7763 inst
.operands
[i
].reg
= val
;
7764 inst
.operands
[i
].isreg
= 1;
7767 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7768 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7770 /* Two kinds of register. */
7773 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7775 || (rege
->type
!= REG_TYPE_MMXWR
7776 && rege
->type
!= REG_TYPE_MMXWC
7777 && rege
->type
!= REG_TYPE_MMXWCG
))
7779 inst
.error
= _("iWMMXt data or control register expected");
7782 inst
.operands
[i
].reg
= rege
->number
;
7783 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7789 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7791 || (rege
->type
!= REG_TYPE_MMXWC
7792 && rege
->type
!= REG_TYPE_MMXWCG
))
7794 inst
.error
= _("iWMMXt control register expected");
7797 inst
.operands
[i
].reg
= rege
->number
;
7798 inst
.operands
[i
].isreg
= 1;
7803 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7804 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7805 case OP_oROR
: val
= parse_ror (&str
); break;
7807 case OP_COND
: val
= parse_cond (&str
); break;
7808 case OP_oBARRIER_I15
:
7809 po_barrier_or_imm (str
); break;
7811 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7817 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7818 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7820 inst
.error
= _("Banked registers are not available with this "
7826 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7830 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7833 val
= parse_sys_vldr_vstr (&str
);
7837 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7840 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7842 if (strncasecmp (str
, "APSR_", 5) == 0)
7849 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7850 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7851 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7852 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7853 default: found
= 16;
7857 inst
.operands
[i
].isvec
= 1;
7858 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7859 inst
.operands
[i
].reg
= REG_PC
;
7866 po_misc_or_fail (parse_tb (&str
));
7869 /* Register lists. */
7871 val
= parse_reg_list (&str
, REGLIST_RN
);
7874 inst
.operands
[i
].writeback
= 1;
7880 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7884 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7889 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7894 /* Allow Q registers too. */
7895 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7896 REGLIST_NEON_D
, &partial_match
);
7900 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7901 REGLIST_VFP_S
, &partial_match
);
7902 inst
.operands
[i
].issingle
= 1;
7907 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7908 REGLIST_VFP_D_VPR
, &partial_match
);
7909 if (val
== FAIL
&& !partial_match
)
7912 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7913 REGLIST_VFP_S_VPR
, &partial_match
);
7914 inst
.operands
[i
].issingle
= 1;
7919 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7920 REGLIST_NEON_D
, &partial_match
);
7925 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7926 1, &inst
.operands
[i
].vectype
);
7927 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7931 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7932 0, &inst
.operands
[i
].vectype
);
7935 /* Addressing modes */
7937 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7941 po_misc_or_fail (parse_address (&str
, i
));
7945 po_misc_or_fail_no_backtrack (
7946 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7950 po_misc_or_fail_no_backtrack (
7951 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7955 po_misc_or_fail_no_backtrack (
7956 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7960 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7964 po_misc_or_fail_no_backtrack (
7965 parse_shifter_operand_group_reloc (&str
, i
));
7969 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7973 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7977 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7982 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7987 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7990 po_reg_or_fail (REG_TYPE_ZR
);
7994 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7997 /* Various value-based sanity checks and shared operations. We
7998 do not signal immediate failures for the register constraints;
7999 this allows a syntax error to take precedence. */
8000 switch (op_parse_code
)
8008 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
8009 inst
.error
= BAD_PC
;
8014 case OP_RRnpcsp_I32
:
8015 if (inst
.operands
[i
].isreg
)
8017 if (inst
.operands
[i
].reg
== REG_PC
)
8018 inst
.error
= BAD_PC
;
8019 else if (inst
.operands
[i
].reg
== REG_SP
8020 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
8021 relaxed since ARMv8-A. */
8022 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8025 inst
.error
= BAD_SP
;
8031 if (inst
.operands
[i
].isreg
8032 && inst
.operands
[i
].reg
== REG_PC
8033 && (inst
.operands
[i
].writeback
|| thumb
))
8034 inst
.error
= BAD_PC
;
8039 if (inst
.operands
[i
].isreg
)
8049 case OP_oBARRIER_I15
:
8062 inst
.operands
[i
].imm
= val
;
8067 if (inst
.operands
[i
].reg
!= REG_LR
)
8068 inst
.error
= _("operand must be LR register");
8074 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
8075 inst
.error
= BAD_PC
;
8079 if (inst
.operands
[i
].isreg
8080 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
8081 inst
.error
= BAD_ODD
;
8085 if (inst
.operands
[i
].isreg
)
8087 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8088 inst
.error
= BAD_EVEN
;
8089 else if (inst
.operands
[i
].reg
== REG_SP
)
8090 as_tsktsk (MVE_BAD_SP
);
8091 else if (inst
.operands
[i
].reg
== REG_PC
)
8092 inst
.error
= BAD_PC
;
8100 /* If we get here, this operand was successfully parsed. */
8101 inst
.operands
[i
].present
= 1;
8105 inst
.error
= BAD_ARGS
;
8110 /* The parse routine should already have set inst.error, but set a
8111 default here just in case. */
8113 inst
.error
= BAD_SYNTAX
;
8117 /* Do not backtrack over a trailing optional argument that
8118 absorbed some text. We will only fail again, with the
8119 'garbage following instruction' error message, which is
8120 probably less helpful than the current one. */
8121 if (backtrack_index
== i
&& backtrack_pos
!= str
8122 && upat
[i
+1] == OP_stop
)
8125 inst
.error
= BAD_SYNTAX
;
8129 /* Try again, skipping the optional argument at backtrack_pos. */
8130 str
= backtrack_pos
;
8131 inst
.error
= backtrack_error
;
8132 inst
.operands
[backtrack_index
].present
= 0;
8133 i
= backtrack_index
;
8137 /* Check that we have parsed all the arguments. */
8138 if (*str
!= '\0' && !inst
.error
)
8139 inst
.error
= _("garbage following instruction");
8141 return inst
.error
? FAIL
: SUCCESS
;
8144 #undef po_char_or_fail
8145 #undef po_reg_or_fail
8146 #undef po_reg_or_goto
8147 #undef po_imm_or_fail
8148 #undef po_scalar_or_fail
8149 #undef po_barrier_or_imm
8151 /* Shorthand macro for instruction encoding functions issuing errors. */
8152 #define constraint(expr, err) \
8163 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8164 instructions are unpredictable if these registers are used. This
8165 is the BadReg predicate in ARM's Thumb-2 documentation.
8167 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8168 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8169 #define reject_bad_reg(reg) \
8171 if (reg == REG_PC) \
8173 inst.error = BAD_PC; \
8176 else if (reg == REG_SP \
8177 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8179 inst.error = BAD_SP; \
8184 /* If REG is R13 (the stack pointer), warn that its use is
8186 #define warn_deprecated_sp(reg) \
8188 if (warn_on_deprecated && reg == REG_SP) \
8189 as_tsktsk (_("use of r13 is deprecated")); \
8192 /* Functions for operand encoding. ARM, then Thumb. */
8194 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8196 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8198 The only binary encoding difference is the Coprocessor number. Coprocessor
8199 9 is used for half-precision calculations or conversions. The format of the
8200 instruction is the same as the equivalent Coprocessor 10 instruction that
8201 exists for Single-Precision operation. */
8204 do_scalar_fp16_v82_encode (void)
8206 if (inst
.cond
< COND_ALWAYS
)
8207 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8208 " the behaviour is UNPREDICTABLE"));
8209 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8212 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8213 mark_feature_used (&arm_ext_fp16
);
8216 /* If VAL can be encoded in the immediate field of an ARM instruction,
8217 return the encoded form. Otherwise, return FAIL. */
8220 encode_arm_immediate (unsigned int val
)
8227 for (i
= 2; i
< 32; i
+= 2)
8228 if ((a
= rotate_left (val
, i
)) <= 0xff)
8229 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8234 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8235 return the encoded form. Otherwise, return FAIL. */
8237 encode_thumb32_immediate (unsigned int val
)
8244 for (i
= 1; i
<= 24; i
++)
8247 if ((val
& ~(0xff << i
)) == 0)
8248 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8252 if (val
== ((a
<< 16) | a
))
8254 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8258 if (val
== ((a
<< 16) | a
))
8259 return 0x200 | (a
>> 8);
8263 /* Encode a VFP SP or DP register number into inst.instruction. */
8266 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8268 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8271 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8274 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8277 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8282 first_error (_("D register out of range for selected VFP version"));
8290 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8294 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8298 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8302 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8306 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8310 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8318 /* Encode a <shift> in an ARM-format instruction. The immediate,
8319 if any, is handled by md_apply_fix. */
8321 encode_arm_shift (int i
)
8323 /* register-shifted register. */
8324 if (inst
.operands
[i
].immisreg
)
8327 for (op_index
= 0; op_index
<= i
; ++op_index
)
8329 /* Check the operand only when it's presented. In pre-UAL syntax,
8330 if the destination register is the same as the first operand, two
8331 register form of the instruction can be used. */
8332 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8333 && inst
.operands
[op_index
].reg
== REG_PC
)
8334 as_warn (UNPRED_REG ("r15"));
8337 if (inst
.operands
[i
].imm
== REG_PC
)
8338 as_warn (UNPRED_REG ("r15"));
8341 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8342 inst
.instruction
|= SHIFT_ROR
<< 5;
8345 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8346 if (inst
.operands
[i
].immisreg
)
8348 inst
.instruction
|= SHIFT_BY_REG
;
8349 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8352 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8357 encode_arm_shifter_operand (int i
)
8359 if (inst
.operands
[i
].isreg
)
8361 inst
.instruction
|= inst
.operands
[i
].reg
;
8362 encode_arm_shift (i
);
8366 inst
.instruction
|= INST_IMMEDIATE
;
8367 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8368 inst
.instruction
|= inst
.operands
[i
].imm
;
8372 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8374 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8377 Generate an error if the operand is not a register. */
8378 constraint (!inst
.operands
[i
].isreg
,
8379 _("Instruction does not support =N addresses"));
8381 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8383 if (inst
.operands
[i
].preind
)
8387 inst
.error
= _("instruction does not accept preindexed addressing");
8390 inst
.instruction
|= PRE_INDEX
;
8391 if (inst
.operands
[i
].writeback
)
8392 inst
.instruction
|= WRITE_BACK
;
8395 else if (inst
.operands
[i
].postind
)
8397 gas_assert (inst
.operands
[i
].writeback
);
8399 inst
.instruction
|= WRITE_BACK
;
8401 else /* unindexed - only for coprocessor */
8403 inst
.error
= _("instruction does not accept unindexed addressing");
8407 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8408 && (((inst
.instruction
& 0x000f0000) >> 16)
8409 == ((inst
.instruction
& 0x0000f000) >> 12)))
8410 as_warn ((inst
.instruction
& LOAD_BIT
)
8411 ? _("destination register same as write-back base")
8412 : _("source register same as write-back base"));
8415 /* inst.operands[i] was set up by parse_address. Encode it into an
8416 ARM-format mode 2 load or store instruction. If is_t is true,
8417 reject forms that cannot be used with a T instruction (i.e. not
8420 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8422 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8424 encode_arm_addr_mode_common (i
, is_t
);
8426 if (inst
.operands
[i
].immisreg
)
8428 constraint ((inst
.operands
[i
].imm
== REG_PC
8429 || (is_pc
&& inst
.operands
[i
].writeback
)),
8431 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8432 inst
.instruction
|= inst
.operands
[i
].imm
;
8433 if (!inst
.operands
[i
].negative
)
8434 inst
.instruction
|= INDEX_UP
;
8435 if (inst
.operands
[i
].shifted
)
8437 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8438 inst
.instruction
|= SHIFT_ROR
<< 5;
8441 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8442 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8446 else /* immediate offset in inst.relocs[0] */
8448 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8450 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8452 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8453 cannot use PC in addressing.
8454 PC cannot be used in writeback addressing, either. */
8455 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8458 /* Use of PC in str is deprecated for ARMv7. */
8459 if (warn_on_deprecated
8461 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8462 as_tsktsk (_("use of PC in this instruction is deprecated"));
8465 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8467 /* Prefer + for zero encoded value. */
8468 if (!inst
.operands
[i
].negative
)
8469 inst
.instruction
|= INDEX_UP
;
8470 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8475 /* inst.operands[i] was set up by parse_address. Encode it into an
8476 ARM-format mode 3 load or store instruction. Reject forms that
8477 cannot be used with such instructions. If is_t is true, reject
8478 forms that cannot be used with a T instruction (i.e. not
8481 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8483 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8485 inst
.error
= _("instruction does not accept scaled register index");
8489 encode_arm_addr_mode_common (i
, is_t
);
8491 if (inst
.operands
[i
].immisreg
)
8493 constraint ((inst
.operands
[i
].imm
== REG_PC
8494 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8496 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8498 inst
.instruction
|= inst
.operands
[i
].imm
;
8499 if (!inst
.operands
[i
].negative
)
8500 inst
.instruction
|= INDEX_UP
;
8502 else /* immediate offset in inst.relocs[0] */
8504 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8505 && inst
.operands
[i
].writeback
),
8507 inst
.instruction
|= HWOFFSET_IMM
;
8508 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8510 /* Prefer + for zero encoded value. */
8511 if (!inst
.operands
[i
].negative
)
8512 inst
.instruction
|= INDEX_UP
;
8514 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8519 /* Write immediate bits [7:0] to the following locations:
8521 |28/24|23 19|18 16|15 4|3 0|
8522 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8524 This function is used by VMOV/VMVN/VORR/VBIC. */
8527 neon_write_immbits (unsigned immbits
)
8529 inst
.instruction
|= immbits
& 0xf;
8530 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8531 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8534 /* Invert low-order SIZE bits of XHI:XLO. */
8537 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8539 unsigned immlo
= xlo
? *xlo
: 0;
8540 unsigned immhi
= xhi
? *xhi
: 0;
8545 immlo
= (~immlo
) & 0xff;
8549 immlo
= (~immlo
) & 0xffff;
8553 immhi
= (~immhi
) & 0xffffffff;
8557 immlo
= (~immlo
) & 0xffffffff;
8571 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8575 neon_bits_same_in_bytes (unsigned imm
)
8577 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8578 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8579 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8580 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8583 /* For immediate of above form, return 0bABCD. */
8586 neon_squash_bits (unsigned imm
)
8588 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8589 | ((imm
& 0x01000000) >> 21);
8592 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8595 neon_qfloat_bits (unsigned imm
)
8597 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8600 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8601 the instruction. *OP is passed as the initial value of the op field, and
8602 may be set to a different value depending on the constant (i.e.
8603 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8604 MVN). If the immediate looks like a repeated pattern then also
8605 try smaller element sizes. */
8608 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8609 unsigned *immbits
, int *op
, int size
,
8610 enum neon_el_type type
)
8612 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8614 if (type
== NT_float
&& !float_p
)
8617 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8619 if (size
!= 32 || *op
== 1)
8621 *immbits
= neon_qfloat_bits (immlo
);
8627 if (neon_bits_same_in_bytes (immhi
)
8628 && neon_bits_same_in_bytes (immlo
))
8632 *immbits
= (neon_squash_bits (immhi
) << 4)
8633 | neon_squash_bits (immlo
);
8644 if (immlo
== (immlo
& 0x000000ff))
8649 else if (immlo
== (immlo
& 0x0000ff00))
8651 *immbits
= immlo
>> 8;
8654 else if (immlo
== (immlo
& 0x00ff0000))
8656 *immbits
= immlo
>> 16;
8659 else if (immlo
== (immlo
& 0xff000000))
8661 *immbits
= immlo
>> 24;
8664 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8666 *immbits
= (immlo
>> 8) & 0xff;
8669 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8671 *immbits
= (immlo
>> 16) & 0xff;
8675 if ((immlo
& 0xffff) != (immlo
>> 16))
8682 if (immlo
== (immlo
& 0x000000ff))
8687 else if (immlo
== (immlo
& 0x0000ff00))
8689 *immbits
= immlo
>> 8;
8693 if ((immlo
& 0xff) != (immlo
>> 8))
8698 if (immlo
== (immlo
& 0x000000ff))
8700 /* Don't allow MVN with 8-bit immediate. */
8710 #if defined BFD_HOST_64_BIT
8711 /* Returns TRUE if double precision value V may be cast
8712 to single precision without loss of accuracy. */
8715 is_double_a_single (bfd_int64_t v
)
8717 int exp
= (int)((v
>> 52) & 0x7FF);
8718 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8720 return (exp
== 0 || exp
== 0x7FF
8721 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8722 && (mantissa
& 0x1FFFFFFFl
) == 0;
8725 /* Returns a double precision value casted to single precision
8726 (ignoring the least significant bits in exponent and mantissa). */
8729 double_to_single (bfd_int64_t v
)
8731 int sign
= (int) ((v
>> 63) & 1l);
8732 int exp
= (int) ((v
>> 52) & 0x7FF);
8733 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8739 exp
= exp
- 1023 + 127;
8748 /* No denormalized numbers. */
8754 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8756 #endif /* BFD_HOST_64_BIT */
8765 static void do_vfp_nsyn_opcode (const char *);
8767 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8768 Determine whether it can be performed with a move instruction; if
8769 it can, convert inst.instruction to that move instruction and
8770 return TRUE; if it can't, convert inst.instruction to a literal-pool
8771 load and return FALSE. If this is not a valid thing to do in the
8772 current context, set inst.error and return TRUE.
8774 inst.operands[i] describes the destination register. */
8777 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8780 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8781 bfd_boolean arm_p
= (t
== CONST_ARM
);
8784 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8788 if ((inst
.instruction
& tbit
) == 0)
8790 inst
.error
= _("invalid pseudo operation");
8794 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8795 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8796 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8798 inst
.error
= _("constant expression expected");
8802 if (inst
.relocs
[0].exp
.X_op
== O_constant
8803 || inst
.relocs
[0].exp
.X_op
== O_big
)
8805 #if defined BFD_HOST_64_BIT
8810 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8812 LITTLENUM_TYPE w
[X_PRECISION
];
8815 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8817 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8819 /* FIXME: Should we check words w[2..5] ? */
8824 #if defined BFD_HOST_64_BIT
8826 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8827 << LITTLENUM_NUMBER_OF_BITS
)
8828 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8829 << LITTLENUM_NUMBER_OF_BITS
)
8830 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8831 << LITTLENUM_NUMBER_OF_BITS
)
8832 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8834 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8835 | (l
[0] & LITTLENUM_MASK
);
8839 v
= inst
.relocs
[0].exp
.X_add_number
;
8841 if (!inst
.operands
[i
].issingle
)
8845 /* LDR should not use lead in a flag-setting instruction being
8846 chosen so we do not check whether movs can be used. */
8848 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8849 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8850 && inst
.operands
[i
].reg
!= 13
8851 && inst
.operands
[i
].reg
!= 15)
8853 /* Check if on thumb2 it can be done with a mov.w, mvn or
8854 movw instruction. */
8855 unsigned int newimm
;
8856 bfd_boolean isNegated
;
8858 newimm
= encode_thumb32_immediate (v
);
8859 if (newimm
!= (unsigned int) FAIL
)
8863 newimm
= encode_thumb32_immediate (~v
);
8864 if (newimm
!= (unsigned int) FAIL
)
8868 /* The number can be loaded with a mov.w or mvn
8870 if (newimm
!= (unsigned int) FAIL
8871 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8873 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8874 | (inst
.operands
[i
].reg
<< 8));
8875 /* Change to MOVN. */
8876 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8877 inst
.instruction
|= (newimm
& 0x800) << 15;
8878 inst
.instruction
|= (newimm
& 0x700) << 4;
8879 inst
.instruction
|= (newimm
& 0x0ff);
8882 /* The number can be loaded with a movw instruction. */
8883 else if ((v
& ~0xFFFF) == 0
8884 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8886 int imm
= v
& 0xFFFF;
8888 inst
.instruction
= 0xf2400000; /* MOVW. */
8889 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8890 inst
.instruction
|= (imm
& 0xf000) << 4;
8891 inst
.instruction
|= (imm
& 0x0800) << 15;
8892 inst
.instruction
|= (imm
& 0x0700) << 4;
8893 inst
.instruction
|= (imm
& 0x00ff);
8894 /* In case this replacement is being done on Armv8-M
8895 Baseline we need to make sure to disable the
8896 instruction size check, as otherwise GAS will reject
8897 the use of this T32 instruction. */
8905 int value
= encode_arm_immediate (v
);
8909 /* This can be done with a mov instruction. */
8910 inst
.instruction
&= LITERAL_MASK
;
8911 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8912 inst
.instruction
|= value
& 0xfff;
8916 value
= encode_arm_immediate (~ v
);
8919 /* This can be done with a mvn instruction. */
8920 inst
.instruction
&= LITERAL_MASK
;
8921 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8922 inst
.instruction
|= value
& 0xfff;
8926 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8929 unsigned immbits
= 0;
8930 unsigned immlo
= inst
.operands
[1].imm
;
8931 unsigned immhi
= inst
.operands
[1].regisimm
8932 ? inst
.operands
[1].reg
8933 : inst
.relocs
[0].exp
.X_unsigned
8935 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8936 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8937 &op
, 64, NT_invtype
);
8941 neon_invert_size (&immlo
, &immhi
, 64);
8943 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8944 &op
, 64, NT_invtype
);
8949 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8955 /* Fill other bits in vmov encoding for both thumb and arm. */
8957 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8959 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8960 neon_write_immbits (immbits
);
8968 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8969 if (inst
.operands
[i
].issingle
8970 && is_quarter_float (inst
.operands
[1].imm
)
8971 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8973 inst
.operands
[1].imm
=
8974 neon_qfloat_bits (v
);
8975 do_vfp_nsyn_opcode ("fconsts");
8979 /* If our host does not support a 64-bit type then we cannot perform
8980 the following optimization. This mean that there will be a
8981 discrepancy between the output produced by an assembler built for
8982 a 32-bit-only host and the output produced from a 64-bit host, but
8983 this cannot be helped. */
8984 #if defined BFD_HOST_64_BIT
8985 else if (!inst
.operands
[1].issingle
8986 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8988 if (is_double_a_single (v
)
8989 && is_quarter_float (double_to_single (v
)))
8991 inst
.operands
[1].imm
=
8992 neon_qfloat_bits (double_to_single (v
));
8993 do_vfp_nsyn_opcode ("fconstd");
9001 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
9002 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
9005 inst
.operands
[1].reg
= REG_PC
;
9006 inst
.operands
[1].isreg
= 1;
9007 inst
.operands
[1].preind
= 1;
9008 inst
.relocs
[0].pc_rel
= 1;
9009 inst
.relocs
[0].type
= (thumb_p
9010 ? BFD_RELOC_ARM_THUMB_OFFSET
9012 ? BFD_RELOC_ARM_HWLITERAL
9013 : BFD_RELOC_ARM_LITERAL
));
9017 /* inst.operands[i] was set up by parse_address. Encode it into an
9018 ARM-format instruction. Reject all forms which cannot be encoded
9019 into a coprocessor load/store instruction. If wb_ok is false,
9020 reject use of writeback; if unind_ok is false, reject use of
9021 unindexed addressing. If reloc_override is not 0, use it instead
9022 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
9023 (in which case it is preserved). */
9026 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
9028 if (!inst
.operands
[i
].isreg
)
9031 if (! inst
.operands
[0].isvec
)
9033 inst
.error
= _("invalid co-processor operand");
9036 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
9040 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9042 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
9044 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
9046 gas_assert (!inst
.operands
[i
].writeback
);
9049 inst
.error
= _("instruction does not support unindexed addressing");
9052 inst
.instruction
|= inst
.operands
[i
].imm
;
9053 inst
.instruction
|= INDEX_UP
;
9057 if (inst
.operands
[i
].preind
)
9058 inst
.instruction
|= PRE_INDEX
;
9060 if (inst
.operands
[i
].writeback
)
9062 if (inst
.operands
[i
].reg
== REG_PC
)
9064 inst
.error
= _("pc may not be used with write-back");
9069 inst
.error
= _("instruction does not support writeback");
9072 inst
.instruction
|= WRITE_BACK
;
9076 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
9077 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
9078 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
9079 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
9082 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
9084 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9087 /* Prefer + for zero encoded value. */
9088 if (!inst
.operands
[i
].negative
)
9089 inst
.instruction
|= INDEX_UP
;
9094 /* Functions for instruction encoding, sorted by sub-architecture.
9095 First some generics; their names are taken from the conventional
9096 bit positions for register arguments in ARM format instructions. */
9106 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9112 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9118 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9119 inst
.instruction
|= inst
.operands
[1].reg
;
9125 inst
.instruction
|= inst
.operands
[0].reg
;
9126 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9132 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9133 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9139 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9140 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9146 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9147 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9151 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9153 if (ARM_CPU_IS_ANY (cpu_variant
))
9155 as_tsktsk ("%s", msg
);
9158 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9170 unsigned Rn
= inst
.operands
[2].reg
;
9171 /* Enforce restrictions on SWP instruction. */
9172 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9174 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9175 _("Rn must not overlap other operands"));
9177 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9179 if (!check_obsolete (&arm_ext_v8
,
9180 _("swp{b} use is obsoleted for ARMv8 and later"))
9181 && warn_on_deprecated
9182 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9183 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9186 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9187 inst
.instruction
|= inst
.operands
[1].reg
;
9188 inst
.instruction
|= Rn
<< 16;
9194 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9195 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9196 inst
.instruction
|= inst
.operands
[2].reg
;
9202 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9203 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9204 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9205 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9207 inst
.instruction
|= inst
.operands
[0].reg
;
9208 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9209 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9215 inst
.instruction
|= inst
.operands
[0].imm
;
9221 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9222 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9225 /* ARM instructions, in alphabetical order by function name (except
9226 that wrapper functions appear immediately after the function they
9229 /* This is a pseudo-op of the form "adr rd, label" to be converted
9230 into a relative address of the form "add rd, pc, #label-.-8". */
9235 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9237 /* Frag hacking will turn this into a sub instruction if the offset turns
9238 out to be negative. */
9239 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9240 inst
.relocs
[0].pc_rel
= 1;
9241 inst
.relocs
[0].exp
.X_add_number
-= 8;
9243 if (support_interwork
9244 && inst
.relocs
[0].exp
.X_op
== O_symbol
9245 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9246 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9247 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9248 inst
.relocs
[0].exp
.X_add_number
|= 1;
9251 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9252 into a relative address of the form:
9253 add rd, pc, #low(label-.-8)"
9254 add rd, rd, #high(label-.-8)" */
9259 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9261 /* Frag hacking will turn this into a sub instruction if the offset turns
9262 out to be negative. */
9263 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9264 inst
.relocs
[0].pc_rel
= 1;
9265 inst
.size
= INSN_SIZE
* 2;
9266 inst
.relocs
[0].exp
.X_add_number
-= 8;
9268 if (support_interwork
9269 && inst
.relocs
[0].exp
.X_op
== O_symbol
9270 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9271 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9272 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9273 inst
.relocs
[0].exp
.X_add_number
|= 1;
9279 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9280 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9282 if (!inst
.operands
[1].present
)
9283 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9284 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9285 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9286 encode_arm_shifter_operand (2);
9292 if (inst
.operands
[0].present
)
9293 inst
.instruction
|= inst
.operands
[0].imm
;
9295 inst
.instruction
|= 0xf;
9301 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9302 constraint (msb
> 32, _("bit-field extends past end of register"));
9303 /* The instruction encoding stores the LSB and MSB,
9304 not the LSB and width. */
9305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9306 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9307 inst
.instruction
|= (msb
- 1) << 16;
9315 /* #0 in second position is alternative syntax for bfc, which is
9316 the same instruction but with REG_PC in the Rm field. */
9317 if (!inst
.operands
[1].isreg
)
9318 inst
.operands
[1].reg
= REG_PC
;
9320 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9321 constraint (msb
> 32, _("bit-field extends past end of register"));
9322 /* The instruction encoding stores the LSB and MSB,
9323 not the LSB and width. */
9324 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9325 inst
.instruction
|= inst
.operands
[1].reg
;
9326 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9327 inst
.instruction
|= (msb
- 1) << 16;
9333 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9334 _("bit-field extends past end of register"));
9335 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9336 inst
.instruction
|= inst
.operands
[1].reg
;
9337 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9338 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9341 /* ARM V5 breakpoint instruction (argument parse)
9342 BKPT <16 bit unsigned immediate>
9343 Instruction is not conditional.
9344 The bit pattern given in insns[] has the COND_ALWAYS condition,
9345 and it is an error if the caller tried to override that. */
9350 /* Top 12 of 16 bits to bits 19:8. */
9351 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9353 /* Bottom 4 of 16 bits to bits 3:0. */
9354 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9358 encode_branch (int default_reloc
)
9360 if (inst
.operands
[0].hasreloc
)
9362 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9363 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9364 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9365 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9366 ? BFD_RELOC_ARM_PLT32
9367 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9370 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9371 inst
.relocs
[0].pc_rel
= 1;
9378 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9379 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9382 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9389 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9391 if (inst
.cond
== COND_ALWAYS
)
9392 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9394 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9398 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9401 /* ARM V5 branch-link-exchange instruction (argument parse)
9402 BLX <target_addr> ie BLX(1)
9403 BLX{<condition>} <Rm> ie BLX(2)
9404 Unfortunately, there are two different opcodes for this mnemonic.
9405 So, the insns[].value is not used, and the code here zaps values
9406 into inst.instruction.
9407 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9412 if (inst
.operands
[0].isreg
)
9414 /* Arg is a register; the opcode provided by insns[] is correct.
9415 It is not illegal to do "blx pc", just useless. */
9416 if (inst
.operands
[0].reg
== REG_PC
)
9417 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9419 inst
.instruction
|= inst
.operands
[0].reg
;
9423 /* Arg is an address; this instruction cannot be executed
9424 conditionally, and the opcode must be adjusted.
9425 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9426 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9427 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9428 inst
.instruction
= 0xfa000000;
9429 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9436 bfd_boolean want_reloc
;
9438 if (inst
.operands
[0].reg
== REG_PC
)
9439 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9441 inst
.instruction
|= inst
.operands
[0].reg
;
9442 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9443 it is for ARMv4t or earlier. */
9444 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9445 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9446 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9450 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9455 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9459 /* ARM v5TEJ. Jump to Jazelle code. */
9464 if (inst
.operands
[0].reg
== REG_PC
)
9465 as_tsktsk (_("use of r15 in bxj is not really useful"));
9467 inst
.instruction
|= inst
.operands
[0].reg
;
9470 /* Co-processor data operation:
9471 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9472 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9476 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9477 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9478 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9479 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9480 inst
.instruction
|= inst
.operands
[4].reg
;
9481 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9487 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9488 encode_arm_shifter_operand (1);
9491 /* Transfer between coprocessor and ARM registers.
9492 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9497 No special properties. */
9499 struct deprecated_coproc_regs_s
9506 arm_feature_set deprecated
;
9507 arm_feature_set obsoleted
;
9508 const char *dep_msg
;
9509 const char *obs_msg
;
9512 #define DEPR_ACCESS_V8 \
9513 N_("This coprocessor register access is deprecated in ARMv8")
9515 /* Table of all deprecated coprocessor registers. */
9516 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9518 {15, 0, 7, 10, 5, /* CP15DMB. */
9519 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9520 DEPR_ACCESS_V8
, NULL
},
9521 {15, 0, 7, 10, 4, /* CP15DSB. */
9522 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9523 DEPR_ACCESS_V8
, NULL
},
9524 {15, 0, 7, 5, 4, /* CP15ISB. */
9525 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9526 DEPR_ACCESS_V8
, NULL
},
9527 {14, 6, 1, 0, 0, /* TEEHBR. */
9528 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9529 DEPR_ACCESS_V8
, NULL
},
9530 {14, 6, 0, 0, 0, /* TEECR. */
9531 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9532 DEPR_ACCESS_V8
, NULL
},
9535 #undef DEPR_ACCESS_V8
9537 static const size_t deprecated_coproc_reg_count
=
9538 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9546 Rd
= inst
.operands
[2].reg
;
9549 if (inst
.instruction
== 0xee000010
9550 || inst
.instruction
== 0xfe000010)
9552 reject_bad_reg (Rd
);
9553 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9555 constraint (Rd
== REG_SP
, BAD_SP
);
9560 if (inst
.instruction
== 0xe000010)
9561 constraint (Rd
== REG_PC
, BAD_PC
);
9564 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9566 const struct deprecated_coproc_regs_s
*r
=
9567 deprecated_coproc_regs
+ i
;
9569 if (inst
.operands
[0].reg
== r
->cp
9570 && inst
.operands
[1].imm
== r
->opc1
9571 && inst
.operands
[3].reg
== r
->crn
9572 && inst
.operands
[4].reg
== r
->crm
9573 && inst
.operands
[5].imm
== r
->opc2
)
9575 if (! ARM_CPU_IS_ANY (cpu_variant
)
9576 && warn_on_deprecated
9577 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9578 as_tsktsk ("%s", r
->dep_msg
);
9582 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9583 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9584 inst
.instruction
|= Rd
<< 12;
9585 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9586 inst
.instruction
|= inst
.operands
[4].reg
;
9587 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9590 /* Transfer between coprocessor register and pair of ARM registers.
9591 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9596 Two XScale instructions are special cases of these:
9598 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9599 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9601 Result unpredictable if Rd or Rn is R15. */
9608 Rd
= inst
.operands
[2].reg
;
9609 Rn
= inst
.operands
[3].reg
;
9613 reject_bad_reg (Rd
);
9614 reject_bad_reg (Rn
);
9618 constraint (Rd
== REG_PC
, BAD_PC
);
9619 constraint (Rn
== REG_PC
, BAD_PC
);
9622 /* Only check the MRRC{2} variants. */
9623 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9625 /* If Rd == Rn, error that the operation is
9626 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9627 constraint (Rd
== Rn
, BAD_OVERLAP
);
9630 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9631 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9632 inst
.instruction
|= Rd
<< 12;
9633 inst
.instruction
|= Rn
<< 16;
9634 inst
.instruction
|= inst
.operands
[4].reg
;
9640 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9641 if (inst
.operands
[1].present
)
9643 inst
.instruction
|= CPSI_MMOD
;
9644 inst
.instruction
|= inst
.operands
[1].imm
;
9651 inst
.instruction
|= inst
.operands
[0].imm
;
9657 unsigned Rd
, Rn
, Rm
;
9659 Rd
= inst
.operands
[0].reg
;
9660 Rn
= (inst
.operands
[1].present
9661 ? inst
.operands
[1].reg
: Rd
);
9662 Rm
= inst
.operands
[2].reg
;
9664 constraint ((Rd
== REG_PC
), BAD_PC
);
9665 constraint ((Rn
== REG_PC
), BAD_PC
);
9666 constraint ((Rm
== REG_PC
), BAD_PC
);
9668 inst
.instruction
|= Rd
<< 16;
9669 inst
.instruction
|= Rn
<< 0;
9670 inst
.instruction
|= Rm
<< 8;
9676 /* There is no IT instruction in ARM mode. We
9677 process it to do the validation as if in
9678 thumb mode, just in case the code gets
9679 assembled for thumb using the unified syntax. */
9684 set_pred_insn_type (IT_INSN
);
9685 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9686 now_pred
.cc
= inst
.operands
[0].imm
;
9690 /* If there is only one register in the register list,
9691 then return its register number. Otherwise return -1. */
9693 only_one_reg_in_list (int range
)
9695 int i
= ffs (range
) - 1;
9696 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9700 encode_ldmstm(int from_push_pop_mnem
)
9702 int base_reg
= inst
.operands
[0].reg
;
9703 int range
= inst
.operands
[1].imm
;
9706 inst
.instruction
|= base_reg
<< 16;
9707 inst
.instruction
|= range
;
9709 if (inst
.operands
[1].writeback
)
9710 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9712 if (inst
.operands
[0].writeback
)
9714 inst
.instruction
|= WRITE_BACK
;
9715 /* Check for unpredictable uses of writeback. */
9716 if (inst
.instruction
& LOAD_BIT
)
9718 /* Not allowed in LDM type 2. */
9719 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9720 && ((range
& (1 << REG_PC
)) == 0))
9721 as_warn (_("writeback of base register is UNPREDICTABLE"));
9722 /* Only allowed if base reg not in list for other types. */
9723 else if (range
& (1 << base_reg
))
9724 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9728 /* Not allowed for type 2. */
9729 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9730 as_warn (_("writeback of base register is UNPREDICTABLE"));
9731 /* Only allowed if base reg not in list, or first in list. */
9732 else if ((range
& (1 << base_reg
))
9733 && (range
& ((1 << base_reg
) - 1)))
9734 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9738 /* If PUSH/POP has only one register, then use the A2 encoding. */
9739 one_reg
= only_one_reg_in_list (range
);
9740 if (from_push_pop_mnem
&& one_reg
>= 0)
9742 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9744 if (is_push
&& one_reg
== 13 /* SP */)
9745 /* PR 22483: The A2 encoding cannot be used when
9746 pushing the stack pointer as this is UNPREDICTABLE. */
9749 inst
.instruction
&= A_COND_MASK
;
9750 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9751 inst
.instruction
|= one_reg
<< 12;
9758 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9761 /* ARMv5TE load-consecutive (argument parse)
9770 constraint (inst
.operands
[0].reg
% 2 != 0,
9771 _("first transfer register must be even"));
9772 constraint (inst
.operands
[1].present
9773 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9774 _("can only transfer two consecutive registers"));
9775 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9776 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9778 if (!inst
.operands
[1].present
)
9779 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9781 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9782 register and the first register written; we have to diagnose
9783 overlap between the base and the second register written here. */
9785 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9786 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9787 as_warn (_("base register written back, and overlaps "
9788 "second transfer register"));
9790 if (!(inst
.instruction
& V4_STR_BIT
))
9792 /* For an index-register load, the index register must not overlap the
9793 destination (even if not write-back). */
9794 if (inst
.operands
[2].immisreg
9795 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9796 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9797 as_warn (_("index register overlaps transfer register"));
9799 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9800 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9806 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9807 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9808 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9809 || inst
.operands
[1].negative
9810 /* This can arise if the programmer has written
9812 or if they have mistakenly used a register name as the last
9815 It is very difficult to distinguish between these two cases
9816 because "rX" might actually be a label. ie the register
9817 name has been occluded by a symbol of the same name. So we
9818 just generate a general 'bad addressing mode' type error
9819 message and leave it up to the programmer to discover the
9820 true cause and fix their mistake. */
9821 || (inst
.operands
[1].reg
== REG_PC
),
9824 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9825 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9826 _("offset must be zero in ARM encoding"));
9828 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9830 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9831 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9832 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9838 constraint (inst
.operands
[0].reg
% 2 != 0,
9839 _("even register required"));
9840 constraint (inst
.operands
[1].present
9841 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9842 _("can only load two consecutive registers"));
9843 /* If op 1 were present and equal to PC, this function wouldn't
9844 have been called in the first place. */
9845 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9847 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9848 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9851 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9852 which is not a multiple of four is UNPREDICTABLE. */
9854 check_ldr_r15_aligned (void)
9856 constraint (!(inst
.operands
[1].immisreg
)
9857 && (inst
.operands
[0].reg
== REG_PC
9858 && inst
.operands
[1].reg
== REG_PC
9859 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9860 _("ldr to register 15 must be 4-byte aligned"));
9866 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9867 if (!inst
.operands
[1].isreg
)
9868 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9870 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9871 check_ldr_r15_aligned ();
9877 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9879 if (inst
.operands
[1].preind
)
9881 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9882 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9883 _("this instruction requires a post-indexed address"));
9885 inst
.operands
[1].preind
= 0;
9886 inst
.operands
[1].postind
= 1;
9887 inst
.operands
[1].writeback
= 1;
9889 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9890 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9893 /* Halfword and signed-byte load/store operations. */
9898 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9899 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9900 if (!inst
.operands
[1].isreg
)
9901 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9903 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9909 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9911 if (inst
.operands
[1].preind
)
9913 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9914 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9915 _("this instruction requires a post-indexed address"));
9917 inst
.operands
[1].preind
= 0;
9918 inst
.operands
[1].postind
= 1;
9919 inst
.operands
[1].writeback
= 1;
9921 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9922 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9925 /* Co-processor register load/store.
9926 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9930 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9931 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9932 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9938 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9939 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9940 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9941 && !(inst
.instruction
& 0x00400000))
9942 as_tsktsk (_("Rd and Rm should be different in mla"));
9944 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9945 inst
.instruction
|= inst
.operands
[1].reg
;
9946 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9947 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9953 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9954 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9956 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9957 encode_arm_shifter_operand (1);
9960 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9967 top
= (inst
.instruction
& 0x00400000) != 0;
9968 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9969 _(":lower16: not allowed in this instruction"));
9970 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9971 _(":upper16: not allowed in this instruction"));
9972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9973 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9975 imm
= inst
.relocs
[0].exp
.X_add_number
;
9976 /* The value is in two pieces: 0:11, 16:19. */
9977 inst
.instruction
|= (imm
& 0x00000fff);
9978 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9983 do_vfp_nsyn_mrs (void)
9985 if (inst
.operands
[0].isvec
)
9987 if (inst
.operands
[1].reg
!= 1)
9988 first_error (_("operand 1 must be FPSCR"));
9989 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9990 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9991 do_vfp_nsyn_opcode ("fmstat");
9993 else if (inst
.operands
[1].isvec
)
9994 do_vfp_nsyn_opcode ("fmrx");
10002 do_vfp_nsyn_msr (void)
10004 if (inst
.operands
[0].isvec
)
10005 do_vfp_nsyn_opcode ("fmxr");
10015 unsigned Rt
= inst
.operands
[0].reg
;
10017 if (thumb_mode
&& Rt
== REG_SP
)
10019 inst
.error
= BAD_SP
;
10023 switch (inst
.operands
[1].reg
)
10025 /* MVFR2 is only valid for Armv8-A. */
10027 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10031 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10032 case 1: /* fpscr. */
10033 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10034 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10038 case 14: /* fpcxt_ns. */
10039 case 15: /* fpcxt_s. */
10040 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10041 _("selected processor does not support instruction"));
10044 case 2: /* fpscr_nzcvqc. */
10045 case 12: /* vpr. */
10047 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10048 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10049 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10050 _("selected processor does not support instruction"));
10051 if (inst
.operands
[0].reg
!= 2
10052 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10053 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10060 /* APSR_ sets isvec. All other refs to PC are illegal. */
10061 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
10063 inst
.error
= BAD_PC
;
10067 /* If we get through parsing the register name, we just insert the number
10068 generated into the instruction without further validation. */
10069 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
10070 inst
.instruction
|= (Rt
<< 12);
10076 unsigned Rt
= inst
.operands
[1].reg
;
10079 reject_bad_reg (Rt
);
10080 else if (Rt
== REG_PC
)
10082 inst
.error
= BAD_PC
;
10086 switch (inst
.operands
[0].reg
)
10088 /* MVFR2 is only valid for Armv8-A. */
10090 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10094 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10095 case 1: /* fpcr. */
10096 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10097 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10101 case 14: /* fpcxt_ns. */
10102 case 15: /* fpcxt_s. */
10103 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10104 _("selected processor does not support instruction"));
10107 case 2: /* fpscr_nzcvqc. */
10108 case 12: /* vpr. */
10110 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10111 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10112 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10113 _("selected processor does not support instruction"));
10114 if (inst
.operands
[0].reg
!= 2
10115 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10116 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10123 /* If we get through parsing the register name, we just insert the number
10124 generated into the instruction without further validation. */
10125 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10126 inst
.instruction
|= (Rt
<< 12);
10134 if (do_vfp_nsyn_mrs () == SUCCESS
)
10137 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10138 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10140 if (inst
.operands
[1].isreg
)
10142 br
= inst
.operands
[1].reg
;
10143 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10144 as_bad (_("bad register for mrs"));
10148 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10149 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10151 _("'APSR', 'CPSR' or 'SPSR' expected"));
10152 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10155 inst
.instruction
|= br
;
10158 /* Two possible forms:
10159 "{C|S}PSR_<field>, Rm",
10160 "{C|S}PSR_f, #expression". */
10165 if (do_vfp_nsyn_msr () == SUCCESS
)
10168 inst
.instruction
|= inst
.operands
[0].imm
;
10169 if (inst
.operands
[1].isreg
)
10170 inst
.instruction
|= inst
.operands
[1].reg
;
10173 inst
.instruction
|= INST_IMMEDIATE
;
10174 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10175 inst
.relocs
[0].pc_rel
= 0;
10182 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10184 if (!inst
.operands
[2].present
)
10185 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10186 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10187 inst
.instruction
|= inst
.operands
[1].reg
;
10188 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10190 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10191 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10192 as_tsktsk (_("Rd and Rm should be different in mul"));
10195 /* Long Multiply Parser
10196 UMULL RdLo, RdHi, Rm, Rs
10197 SMULL RdLo, RdHi, Rm, Rs
10198 UMLAL RdLo, RdHi, Rm, Rs
10199 SMLAL RdLo, RdHi, Rm, Rs. */
10204 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10205 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10206 inst
.instruction
|= inst
.operands
[2].reg
;
10207 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10209 /* rdhi and rdlo must be different. */
10210 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10211 as_tsktsk (_("rdhi and rdlo must be different"));
10213 /* rdhi, rdlo and rm must all be different before armv6. */
10214 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10215 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10216 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10217 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10223 if (inst
.operands
[0].present
10224 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10226 /* Architectural NOP hints are CPSR sets with no bits selected. */
10227 inst
.instruction
&= 0xf0000000;
10228 inst
.instruction
|= 0x0320f000;
10229 if (inst
.operands
[0].present
)
10230 inst
.instruction
|= inst
.operands
[0].imm
;
10234 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10235 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10236 Condition defaults to COND_ALWAYS.
10237 Error if Rd, Rn or Rm are R15. */
10242 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10243 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10244 inst
.instruction
|= inst
.operands
[2].reg
;
10245 if (inst
.operands
[3].present
)
10246 encode_arm_shift (3);
10249 /* ARM V6 PKHTB (Argument Parse). */
10254 if (!inst
.operands
[3].present
)
10256 /* If the shift specifier is omitted, turn the instruction
10257 into pkhbt rd, rm, rn. */
10258 inst
.instruction
&= 0xfff00010;
10259 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10260 inst
.instruction
|= inst
.operands
[1].reg
;
10261 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10265 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10266 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10267 inst
.instruction
|= inst
.operands
[2].reg
;
10268 encode_arm_shift (3);
10272 /* ARMv5TE: Preload-Cache
10273 MP Extensions: Preload for write
10277 Syntactically, like LDR with B=1, W=0, L=1. */
10282 constraint (!inst
.operands
[0].isreg
,
10283 _("'[' expected after PLD mnemonic"));
10284 constraint (inst
.operands
[0].postind
,
10285 _("post-indexed expression used in preload instruction"));
10286 constraint (inst
.operands
[0].writeback
,
10287 _("writeback used in preload instruction"));
10288 constraint (!inst
.operands
[0].preind
,
10289 _("unindexed addressing used in preload instruction"));
10290 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10293 /* ARMv7: PLI <addr_mode> */
10297 constraint (!inst
.operands
[0].isreg
,
10298 _("'[' expected after PLI mnemonic"));
10299 constraint (inst
.operands
[0].postind
,
10300 _("post-indexed expression used in preload instruction"));
10301 constraint (inst
.operands
[0].writeback
,
10302 _("writeback used in preload instruction"));
10303 constraint (!inst
.operands
[0].preind
,
10304 _("unindexed addressing used in preload instruction"));
10305 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10306 inst
.instruction
&= ~PRE_INDEX
;
10312 constraint (inst
.operands
[0].writeback
,
10313 _("push/pop do not support {reglist}^"));
10314 inst
.operands
[1] = inst
.operands
[0];
10315 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10316 inst
.operands
[0].isreg
= 1;
10317 inst
.operands
[0].writeback
= 1;
10318 inst
.operands
[0].reg
= REG_SP
;
10319 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10322 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10323 word at the specified address and the following word
10325 Unconditionally executed.
10326 Error if Rn is R15. */
10331 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10332 if (inst
.operands
[0].writeback
)
10333 inst
.instruction
|= WRITE_BACK
;
10336 /* ARM V6 ssat (argument parse). */
10341 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10342 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10343 inst
.instruction
|= inst
.operands
[2].reg
;
10345 if (inst
.operands
[3].present
)
10346 encode_arm_shift (3);
10349 /* ARM V6 usat (argument parse). */
10354 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10355 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10356 inst
.instruction
|= inst
.operands
[2].reg
;
10358 if (inst
.operands
[3].present
)
10359 encode_arm_shift (3);
10362 /* ARM V6 ssat16 (argument parse). */
10367 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10368 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10369 inst
.instruction
|= inst
.operands
[2].reg
;
10375 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10376 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10377 inst
.instruction
|= inst
.operands
[2].reg
;
10380 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10381 preserving the other bits.
10383 setend <endian_specifier>, where <endian_specifier> is either
10389 if (warn_on_deprecated
10390 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10391 as_tsktsk (_("setend use is deprecated for ARMv8"));
10393 if (inst
.operands
[0].imm
)
10394 inst
.instruction
|= 0x200;
10400 unsigned int Rm
= (inst
.operands
[1].present
10401 ? inst
.operands
[1].reg
10402 : inst
.operands
[0].reg
);
10404 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10405 inst
.instruction
|= Rm
;
10406 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10408 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10409 inst
.instruction
|= SHIFT_BY_REG
;
10410 /* PR 12854: Error on extraneous shifts. */
10411 constraint (inst
.operands
[2].shifted
,
10412 _("extraneous shift as part of operand to shift insn"));
10415 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10421 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10422 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10424 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10425 inst
.relocs
[0].pc_rel
= 0;
10431 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10432 inst
.relocs
[0].pc_rel
= 0;
10438 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10439 inst
.relocs
[0].pc_rel
= 0;
10445 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10446 _("selected processor does not support SETPAN instruction"));
10448 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10454 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10455 _("selected processor does not support SETPAN instruction"));
10457 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10460 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10461 SMLAxy{cond} Rd,Rm,Rs,Rn
10462 SMLAWy{cond} Rd,Rm,Rs,Rn
10463 Error if any register is R15. */
10468 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10469 inst
.instruction
|= inst
.operands
[1].reg
;
10470 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10471 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10474 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10475 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10476 Error if any register is R15.
10477 Warning if Rdlo == Rdhi. */
10482 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10483 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10484 inst
.instruction
|= inst
.operands
[2].reg
;
10485 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10487 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10488 as_tsktsk (_("rdhi and rdlo must be different"));
10491 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10492 SMULxy{cond} Rd,Rm,Rs
10493 Error if any register is R15. */
10498 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10499 inst
.instruction
|= inst
.operands
[1].reg
;
10500 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10503 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10504 the same for both ARM and Thumb-2. */
10511 if (inst
.operands
[0].present
)
10513 reg
= inst
.operands
[0].reg
;
10514 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10519 inst
.instruction
|= reg
<< 16;
10520 inst
.instruction
|= inst
.operands
[1].imm
;
10521 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10522 inst
.instruction
|= WRITE_BACK
;
10525 /* ARM V6 strex (argument parse). */
10530 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10531 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10532 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10533 || inst
.operands
[2].negative
10534 /* See comment in do_ldrex(). */
10535 || (inst
.operands
[2].reg
== REG_PC
),
10538 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10539 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10541 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10542 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10543 _("offset must be zero in ARM encoding"));
10545 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10546 inst
.instruction
|= inst
.operands
[1].reg
;
10547 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10548 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10552 do_t_strexbh (void)
10554 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10555 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10556 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10557 || inst
.operands
[2].negative
,
10560 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10561 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10569 constraint (inst
.operands
[1].reg
% 2 != 0,
10570 _("even register required"));
10571 constraint (inst
.operands
[2].present
10572 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10573 _("can only store two consecutive registers"));
10574 /* If op 2 were present and equal to PC, this function wouldn't
10575 have been called in the first place. */
10576 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10578 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10579 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10580 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10583 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10584 inst
.instruction
|= inst
.operands
[1].reg
;
10585 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10592 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10593 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10601 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10602 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10607 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10608 extends it to 32-bits, and adds the result to a value in another
10609 register. You can specify a rotation by 0, 8, 16, or 24 bits
10610 before extracting the 16-bit value.
10611 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10612 Condition defaults to COND_ALWAYS.
10613 Error if any register uses R15. */
10618 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10619 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10620 inst
.instruction
|= inst
.operands
[2].reg
;
10621 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10626 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10627 Condition defaults to COND_ALWAYS.
10628 Error if any register uses R15. */
10633 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10634 inst
.instruction
|= inst
.operands
[1].reg
;
10635 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10638 /* VFP instructions. In a logical order: SP variant first, monad
10639 before dyad, arithmetic then move then load/store. */
10642 do_vfp_sp_monadic (void)
10644 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10645 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10648 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10649 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10653 do_vfp_sp_dyadic (void)
10655 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10656 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10657 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10661 do_vfp_sp_compare_z (void)
10663 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10667 do_vfp_dp_sp_cvt (void)
10669 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10670 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10674 do_vfp_sp_dp_cvt (void)
10676 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10677 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10681 do_vfp_reg_from_sp (void)
10683 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10684 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10687 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10688 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10692 do_vfp_reg2_from_sp2 (void)
10694 constraint (inst
.operands
[2].imm
!= 2,
10695 _("only two consecutive VFP SP registers allowed here"));
10696 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10697 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10698 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10702 do_vfp_sp_from_reg (void)
10704 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10705 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10708 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10709 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10713 do_vfp_sp2_from_reg2 (void)
10715 constraint (inst
.operands
[0].imm
!= 2,
10716 _("only two consecutive VFP SP registers allowed here"));
10717 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10718 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10719 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10723 do_vfp_sp_ldst (void)
10725 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10726 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10730 do_vfp_dp_ldst (void)
10732 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10733 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10738 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10740 if (inst
.operands
[0].writeback
)
10741 inst
.instruction
|= WRITE_BACK
;
10743 constraint (ldstm_type
!= VFP_LDSTMIA
,
10744 _("this addressing mode requires base-register writeback"));
10745 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10746 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10747 inst
.instruction
|= inst
.operands
[1].imm
;
10751 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10755 if (inst
.operands
[0].writeback
)
10756 inst
.instruction
|= WRITE_BACK
;
10758 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10759 _("this addressing mode requires base-register writeback"));
10761 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10762 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10764 count
= inst
.operands
[1].imm
<< 1;
10765 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10768 inst
.instruction
|= count
;
10772 do_vfp_sp_ldstmia (void)
10774 vfp_sp_ldstm (VFP_LDSTMIA
);
10778 do_vfp_sp_ldstmdb (void)
10780 vfp_sp_ldstm (VFP_LDSTMDB
);
10784 do_vfp_dp_ldstmia (void)
10786 vfp_dp_ldstm (VFP_LDSTMIA
);
10790 do_vfp_dp_ldstmdb (void)
10792 vfp_dp_ldstm (VFP_LDSTMDB
);
10796 do_vfp_xp_ldstmia (void)
10798 vfp_dp_ldstm (VFP_LDSTMIAX
);
10802 do_vfp_xp_ldstmdb (void)
10804 vfp_dp_ldstm (VFP_LDSTMDBX
);
10808 do_vfp_dp_rd_rm (void)
10810 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10811 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10814 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10815 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10819 do_vfp_dp_rn_rd (void)
10821 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10822 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10826 do_vfp_dp_rd_rn (void)
10828 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10829 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10833 do_vfp_dp_rd_rn_rm (void)
10835 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10836 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10839 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10840 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10841 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10845 do_vfp_dp_rd (void)
10847 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10851 do_vfp_dp_rm_rd_rn (void)
10853 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10854 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10857 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10858 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10859 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10862 /* VFPv3 instructions. */
10864 do_vfp_sp_const (void)
10866 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10867 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10868 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10872 do_vfp_dp_const (void)
10874 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10875 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10876 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10880 vfp_conv (int srcsize
)
10882 int immbits
= srcsize
- inst
.operands
[1].imm
;
10884 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10886 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10887 i.e. immbits must be in range 0 - 16. */
10888 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10891 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10893 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10894 i.e. immbits must be in range 0 - 31. */
10895 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10899 inst
.instruction
|= (immbits
& 1) << 5;
10900 inst
.instruction
|= (immbits
>> 1);
10904 do_vfp_sp_conv_16 (void)
10906 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10911 do_vfp_dp_conv_16 (void)
10913 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10918 do_vfp_sp_conv_32 (void)
10920 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10925 do_vfp_dp_conv_32 (void)
10927 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10931 /* FPA instructions. Also in a logical order. */
10936 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10937 inst
.instruction
|= inst
.operands
[1].reg
;
10941 do_fpa_ldmstm (void)
10943 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10944 switch (inst
.operands
[1].imm
)
10946 case 1: inst
.instruction
|= CP_T_X
; break;
10947 case 2: inst
.instruction
|= CP_T_Y
; break;
10948 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10953 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10955 /* The instruction specified "ea" or "fd", so we can only accept
10956 [Rn]{!}. The instruction does not really support stacking or
10957 unstacking, so we have to emulate these by setting appropriate
10958 bits and offsets. */
10959 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10960 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10961 _("this instruction does not support indexing"));
10963 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10964 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10966 if (!(inst
.instruction
& INDEX_UP
))
10967 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10969 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10971 inst
.operands
[2].preind
= 0;
10972 inst
.operands
[2].postind
= 1;
10976 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10979 /* iWMMXt instructions: strictly in alphabetical order. */
10982 do_iwmmxt_tandorc (void)
10984 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10988 do_iwmmxt_textrc (void)
10990 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10991 inst
.instruction
|= inst
.operands
[1].imm
;
10995 do_iwmmxt_textrm (void)
10997 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10998 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10999 inst
.instruction
|= inst
.operands
[2].imm
;
11003 do_iwmmxt_tinsr (void)
11005 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11006 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11007 inst
.instruction
|= inst
.operands
[2].imm
;
11011 do_iwmmxt_tmia (void)
11013 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11014 inst
.instruction
|= inst
.operands
[1].reg
;
11015 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11019 do_iwmmxt_waligni (void)
11021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11022 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11023 inst
.instruction
|= inst
.operands
[2].reg
;
11024 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
11028 do_iwmmxt_wmerge (void)
11030 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11031 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11032 inst
.instruction
|= inst
.operands
[2].reg
;
11033 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
11037 do_iwmmxt_wmov (void)
11039 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
11040 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11041 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11042 inst
.instruction
|= inst
.operands
[1].reg
;
11046 do_iwmmxt_wldstbh (void)
11049 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11051 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
11053 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
11054 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
11058 do_iwmmxt_wldstw (void)
11060 /* RIWR_RIWC clears .isreg for a control register. */
11061 if (!inst
.operands
[0].isreg
)
11063 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
11064 inst
.instruction
|= 0xf0000000;
11067 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11068 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
11072 do_iwmmxt_wldstd (void)
11074 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11075 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
11076 && inst
.operands
[1].immisreg
)
11078 inst
.instruction
&= ~0x1a000ff;
11079 inst
.instruction
|= (0xfU
<< 28);
11080 if (inst
.operands
[1].preind
)
11081 inst
.instruction
|= PRE_INDEX
;
11082 if (!inst
.operands
[1].negative
)
11083 inst
.instruction
|= INDEX_UP
;
11084 if (inst
.operands
[1].writeback
)
11085 inst
.instruction
|= WRITE_BACK
;
11086 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11087 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11088 inst
.instruction
|= inst
.operands
[1].imm
;
11091 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11095 do_iwmmxt_wshufh (void)
11097 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11098 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11099 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11100 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11104 do_iwmmxt_wzero (void)
11106 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11107 inst
.instruction
|= inst
.operands
[0].reg
;
11108 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11109 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11113 do_iwmmxt_wrwrwr_or_imm5 (void)
11115 if (inst
.operands
[2].isreg
)
11118 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11119 _("immediate operand requires iWMMXt2"));
11121 if (inst
.operands
[2].imm
== 0)
11123 switch ((inst
.instruction
>> 20) & 0xf)
11129 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11130 inst
.operands
[2].imm
= 16;
11131 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11137 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11138 inst
.operands
[2].imm
= 32;
11139 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11146 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11148 wrn
= (inst
.instruction
>> 16) & 0xf;
11149 inst
.instruction
&= 0xff0fff0f;
11150 inst
.instruction
|= wrn
;
11151 /* Bail out here; the instruction is now assembled. */
11156 /* Map 32 -> 0, etc. */
11157 inst
.operands
[2].imm
&= 0x1f;
11158 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11162 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11163 operations first, then control, shift, and load/store. */
11165 /* Insns like "foo X,Y,Z". */
11168 do_mav_triple (void)
11170 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11171 inst
.instruction
|= inst
.operands
[1].reg
;
11172 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11175 /* Insns like "foo W,X,Y,Z".
11176 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11181 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11182 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11183 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11184 inst
.instruction
|= inst
.operands
[3].reg
;
11187 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11189 do_mav_dspsc (void)
11191 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11194 /* Maverick shift immediate instructions.
11195 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11196 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11199 do_mav_shift (void)
11201 int imm
= inst
.operands
[2].imm
;
11203 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11204 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11206 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11207 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11208 Bit 4 should be 0. */
11209 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11211 inst
.instruction
|= imm
;
11214 /* XScale instructions. Also sorted arithmetic before move. */
11216 /* Xscale multiply-accumulate (argument parse)
11219 MIAxycc acc0,Rm,Rs. */
11224 inst
.instruction
|= inst
.operands
[1].reg
;
11225 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11228 /* Xscale move-accumulator-register (argument parse)
11230 MARcc acc0,RdLo,RdHi. */
11235 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11236 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11239 /* Xscale move-register-accumulator (argument parse)
11241 MRAcc RdLo,RdHi,acc0. */
11246 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11247 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11248 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11251 /* Encoding functions relevant only to Thumb. */
11253 /* inst.operands[i] is a shifted-register operand; encode
11254 it into inst.instruction in the format used by Thumb32. */
11257 encode_thumb32_shifted_operand (int i
)
11259 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11260 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11262 constraint (inst
.operands
[i
].immisreg
,
11263 _("shift by register not allowed in thumb mode"));
11264 inst
.instruction
|= inst
.operands
[i
].reg
;
11265 if (shift
== SHIFT_RRX
)
11266 inst
.instruction
|= SHIFT_ROR
<< 4;
11269 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11270 _("expression too complex"));
11272 constraint (value
> 32
11273 || (value
== 32 && (shift
== SHIFT_LSL
11274 || shift
== SHIFT_ROR
)),
11275 _("shift expression is too large"));
11279 else if (value
== 32)
11282 inst
.instruction
|= shift
<< 4;
11283 inst
.instruction
|= (value
& 0x1c) << 10;
11284 inst
.instruction
|= (value
& 0x03) << 6;
11289 /* inst.operands[i] was set up by parse_address. Encode it into a
11290 Thumb32 format load or store instruction. Reject forms that cannot
11291 be used with such instructions. If is_t is true, reject forms that
11292 cannot be used with a T instruction; if is_d is true, reject forms
11293 that cannot be used with a D instruction. If it is a store insn,
11294 reject PC in Rn. */
11297 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11299 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11301 constraint (!inst
.operands
[i
].isreg
,
11302 _("Instruction does not support =N addresses"));
11304 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11305 if (inst
.operands
[i
].immisreg
)
11307 constraint (is_pc
, BAD_PC_ADDRESSING
);
11308 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11309 constraint (inst
.operands
[i
].negative
,
11310 _("Thumb does not support negative register indexing"));
11311 constraint (inst
.operands
[i
].postind
,
11312 _("Thumb does not support register post-indexing"));
11313 constraint (inst
.operands
[i
].writeback
,
11314 _("Thumb does not support register indexing with writeback"));
11315 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11316 _("Thumb supports only LSL in shifted register indexing"));
11318 inst
.instruction
|= inst
.operands
[i
].imm
;
11319 if (inst
.operands
[i
].shifted
)
11321 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11322 _("expression too complex"));
11323 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11324 || inst
.relocs
[0].exp
.X_add_number
> 3,
11325 _("shift out of range"));
11326 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11328 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11330 else if (inst
.operands
[i
].preind
)
11332 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11333 constraint (is_t
&& inst
.operands
[i
].writeback
,
11334 _("cannot use writeback with this instruction"));
11335 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11336 BAD_PC_ADDRESSING
);
11340 inst
.instruction
|= 0x01000000;
11341 if (inst
.operands
[i
].writeback
)
11342 inst
.instruction
|= 0x00200000;
11346 inst
.instruction
|= 0x00000c00;
11347 if (inst
.operands
[i
].writeback
)
11348 inst
.instruction
|= 0x00000100;
11350 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11352 else if (inst
.operands
[i
].postind
)
11354 gas_assert (inst
.operands
[i
].writeback
);
11355 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11356 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11359 inst
.instruction
|= 0x00200000;
11361 inst
.instruction
|= 0x00000900;
11362 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11364 else /* unindexed - only for coprocessor */
11365 inst
.error
= _("instruction does not accept unindexed addressing");
11368 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11369 encodings (the latter only in post-V6T2 cores). The index is the
11370 value used in the insns table below. When there is more than one
11371 possible 16-bit encoding for the instruction, this table always
11373 Also contains several pseudo-instructions used during relaxation. */
11374 #define T16_32_TAB \
11375 X(_adc, 4140, eb400000), \
11376 X(_adcs, 4140, eb500000), \
11377 X(_add, 1c00, eb000000), \
11378 X(_adds, 1c00, eb100000), \
11379 X(_addi, 0000, f1000000), \
11380 X(_addis, 0000, f1100000), \
11381 X(_add_pc,000f, f20f0000), \
11382 X(_add_sp,000d, f10d0000), \
11383 X(_adr, 000f, f20f0000), \
11384 X(_and, 4000, ea000000), \
11385 X(_ands, 4000, ea100000), \
11386 X(_asr, 1000, fa40f000), \
11387 X(_asrs, 1000, fa50f000), \
11388 X(_b, e000, f000b000), \
11389 X(_bcond, d000, f0008000), \
11390 X(_bf, 0000, f040e001), \
11391 X(_bfcsel,0000, f000e001), \
11392 X(_bfx, 0000, f060e001), \
11393 X(_bfl, 0000, f000c001), \
11394 X(_bflx, 0000, f070e001), \
11395 X(_bic, 4380, ea200000), \
11396 X(_bics, 4380, ea300000), \
11397 X(_cinc, 0000, ea509000), \
11398 X(_cinv, 0000, ea50a000), \
11399 X(_cmn, 42c0, eb100f00), \
11400 X(_cmp, 2800, ebb00f00), \
11401 X(_cneg, 0000, ea50b000), \
11402 X(_cpsie, b660, f3af8400), \
11403 X(_cpsid, b670, f3af8600), \
11404 X(_cpy, 4600, ea4f0000), \
11405 X(_csel, 0000, ea508000), \
11406 X(_cset, 0000, ea5f900f), \
11407 X(_csetm, 0000, ea5fa00f), \
11408 X(_csinc, 0000, ea509000), \
11409 X(_csinv, 0000, ea50a000), \
11410 X(_csneg, 0000, ea50b000), \
11411 X(_dec_sp,80dd, f1ad0d00), \
11412 X(_dls, 0000, f040e001), \
11413 X(_dlstp, 0000, f000e001), \
11414 X(_eor, 4040, ea800000), \
11415 X(_eors, 4040, ea900000), \
11416 X(_inc_sp,00dd, f10d0d00), \
11417 X(_lctp, 0000, f00fe001), \
11418 X(_ldmia, c800, e8900000), \
11419 X(_ldr, 6800, f8500000), \
11420 X(_ldrb, 7800, f8100000), \
11421 X(_ldrh, 8800, f8300000), \
11422 X(_ldrsb, 5600, f9100000), \
11423 X(_ldrsh, 5e00, f9300000), \
11424 X(_ldr_pc,4800, f85f0000), \
11425 X(_ldr_pc2,4800, f85f0000), \
11426 X(_ldr_sp,9800, f85d0000), \
11427 X(_le, 0000, f00fc001), \
11428 X(_letp, 0000, f01fc001), \
11429 X(_lsl, 0000, fa00f000), \
11430 X(_lsls, 0000, fa10f000), \
11431 X(_lsr, 0800, fa20f000), \
11432 X(_lsrs, 0800, fa30f000), \
11433 X(_mov, 2000, ea4f0000), \
11434 X(_movs, 2000, ea5f0000), \
11435 X(_mul, 4340, fb00f000), \
11436 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11437 X(_mvn, 43c0, ea6f0000), \
11438 X(_mvns, 43c0, ea7f0000), \
11439 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11440 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11441 X(_orr, 4300, ea400000), \
11442 X(_orrs, 4300, ea500000), \
11443 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11444 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11445 X(_rev, ba00, fa90f080), \
11446 X(_rev16, ba40, fa90f090), \
11447 X(_revsh, bac0, fa90f0b0), \
11448 X(_ror, 41c0, fa60f000), \
11449 X(_rors, 41c0, fa70f000), \
11450 X(_sbc, 4180, eb600000), \
11451 X(_sbcs, 4180, eb700000), \
11452 X(_stmia, c000, e8800000), \
11453 X(_str, 6000, f8400000), \
11454 X(_strb, 7000, f8000000), \
11455 X(_strh, 8000, f8200000), \
11456 X(_str_sp,9000, f84d0000), \
11457 X(_sub, 1e00, eba00000), \
11458 X(_subs, 1e00, ebb00000), \
11459 X(_subi, 8000, f1a00000), \
11460 X(_subis, 8000, f1b00000), \
11461 X(_sxtb, b240, fa4ff080), \
11462 X(_sxth, b200, fa0ff080), \
11463 X(_tst, 4200, ea100f00), \
11464 X(_uxtb, b2c0, fa5ff080), \
11465 X(_uxth, b280, fa1ff080), \
11466 X(_nop, bf00, f3af8000), \
11467 X(_yield, bf10, f3af8001), \
11468 X(_wfe, bf20, f3af8002), \
11469 X(_wfi, bf30, f3af8003), \
11470 X(_wls, 0000, f040c001), \
11471 X(_wlstp, 0000, f000c001), \
11472 X(_sev, bf40, f3af8004), \
11473 X(_sevl, bf50, f3af8005), \
11474 X(_udf, de00, f7f0a000)
11476 /* To catch errors in encoding functions, the codes are all offset by
11477 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11478 as 16-bit instructions. */
11479 #define X(a,b,c) T_MNEM##a
11480 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11483 #define X(a,b,c) 0x##b
11484 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11485 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11488 #define X(a,b,c) 0x##c
11489 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11490 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11491 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11495 /* Thumb instruction encoders, in alphabetical order. */
11497 /* ADDW or SUBW. */
11500 do_t_add_sub_w (void)
11504 Rd
= inst
.operands
[0].reg
;
11505 Rn
= inst
.operands
[1].reg
;
11507 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11508 is the SP-{plus,minus}-immediate form of the instruction. */
11510 constraint (Rd
== REG_PC
, BAD_PC
);
11512 reject_bad_reg (Rd
);
11514 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11515 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11518 /* Parse an add or subtract instruction. We get here with inst.instruction
11519 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11522 do_t_add_sub (void)
11526 Rd
= inst
.operands
[0].reg
;
11527 Rs
= (inst
.operands
[1].present
11528 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11529 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11532 set_pred_insn_type_last ();
11534 if (unified_syntax
)
11537 bfd_boolean narrow
;
11540 flags
= (inst
.instruction
== T_MNEM_adds
11541 || inst
.instruction
== T_MNEM_subs
);
11543 narrow
= !in_pred_block ();
11545 narrow
= in_pred_block ();
11546 if (!inst
.operands
[2].isreg
)
11550 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11551 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11553 add
= (inst
.instruction
== T_MNEM_add
11554 || inst
.instruction
== T_MNEM_adds
);
11556 if (inst
.size_req
!= 4)
11558 /* Attempt to use a narrow opcode, with relaxation if
11560 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11561 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11562 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11563 opcode
= T_MNEM_add_sp
;
11564 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11565 opcode
= T_MNEM_add_pc
;
11566 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11569 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11571 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11575 inst
.instruction
= THUMB_OP16(opcode
);
11576 inst
.instruction
|= (Rd
<< 4) | Rs
;
11577 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11578 || (inst
.relocs
[0].type
11579 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11581 if (inst
.size_req
== 2)
11582 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11584 inst
.relax
= opcode
;
11588 constraint (inst
.size_req
== 2, BAD_HIREG
);
11590 if (inst
.size_req
== 4
11591 || (inst
.size_req
!= 2 && !opcode
))
11593 constraint ((inst
.relocs
[0].type
11594 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11595 && (inst
.relocs
[0].type
11596 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11597 THUMB1_RELOC_ONLY
);
11600 constraint (add
, BAD_PC
);
11601 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11602 _("only SUBS PC, LR, #const allowed"));
11603 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11604 _("expression too complex"));
11605 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11606 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11607 _("immediate value out of range"));
11608 inst
.instruction
= T2_SUBS_PC_LR
11609 | inst
.relocs
[0].exp
.X_add_number
;
11610 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11613 else if (Rs
== REG_PC
)
11615 /* Always use addw/subw. */
11616 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11617 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11621 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11622 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11625 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11627 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11629 inst
.instruction
|= Rd
<< 8;
11630 inst
.instruction
|= Rs
<< 16;
11635 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11636 unsigned int shift
= inst
.operands
[2].shift_kind
;
11638 Rn
= inst
.operands
[2].reg
;
11639 /* See if we can do this with a 16-bit instruction. */
11640 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11642 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11647 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11648 || inst
.instruction
== T_MNEM_add
)
11650 : T_OPCODE_SUB_R3
);
11651 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11655 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11657 /* Thumb-1 cores (except v6-M) require at least one high
11658 register in a narrow non flag setting add. */
11659 if (Rd
> 7 || Rn
> 7
11660 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11661 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11668 inst
.instruction
= T_OPCODE_ADD_HI
;
11669 inst
.instruction
|= (Rd
& 8) << 4;
11670 inst
.instruction
|= (Rd
& 7);
11671 inst
.instruction
|= Rn
<< 3;
11677 constraint (Rd
== REG_PC
, BAD_PC
);
11678 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11679 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11680 constraint (Rs
== REG_PC
, BAD_PC
);
11681 reject_bad_reg (Rn
);
11683 /* If we get here, it can't be done in 16 bits. */
11684 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11685 _("shift must be constant"));
11686 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11687 inst
.instruction
|= Rd
<< 8;
11688 inst
.instruction
|= Rs
<< 16;
11689 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11690 _("shift value over 3 not allowed in thumb mode"));
11691 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11692 _("only LSL shift allowed in thumb mode"));
11693 encode_thumb32_shifted_operand (2);
11698 constraint (inst
.instruction
== T_MNEM_adds
11699 || inst
.instruction
== T_MNEM_subs
,
11702 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11704 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11705 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11708 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11709 ? 0x0000 : 0x8000);
11710 inst
.instruction
|= (Rd
<< 4) | Rs
;
11711 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11715 Rn
= inst
.operands
[2].reg
;
11716 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11718 /* We now have Rd, Rs, and Rn set to registers. */
11719 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11721 /* Can't do this for SUB. */
11722 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11723 inst
.instruction
= T_OPCODE_ADD_HI
;
11724 inst
.instruction
|= (Rd
& 8) << 4;
11725 inst
.instruction
|= (Rd
& 7);
11727 inst
.instruction
|= Rn
<< 3;
11729 inst
.instruction
|= Rs
<< 3;
11731 constraint (1, _("dest must overlap one source register"));
11735 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11736 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11737 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11747 Rd
= inst
.operands
[0].reg
;
11748 reject_bad_reg (Rd
);
11750 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11752 /* Defer to section relaxation. */
11753 inst
.relax
= inst
.instruction
;
11754 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11755 inst
.instruction
|= Rd
<< 4;
11757 else if (unified_syntax
&& inst
.size_req
!= 2)
11759 /* Generate a 32-bit opcode. */
11760 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11761 inst
.instruction
|= Rd
<< 8;
11762 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11763 inst
.relocs
[0].pc_rel
= 1;
11767 /* Generate a 16-bit opcode. */
11768 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11769 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11770 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11771 inst
.relocs
[0].pc_rel
= 1;
11772 inst
.instruction
|= Rd
<< 4;
11775 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11776 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11777 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11778 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11779 inst
.relocs
[0].exp
.X_add_number
+= 1;
11782 /* Arithmetic instructions for which there is just one 16-bit
11783 instruction encoding, and it allows only two low registers.
11784 For maximal compatibility with ARM syntax, we allow three register
11785 operands even when Thumb-32 instructions are not available, as long
11786 as the first two are identical. For instance, both "sbc r0,r1" and
11787 "sbc r0,r0,r1" are allowed. */
11793 Rd
= inst
.operands
[0].reg
;
11794 Rs
= (inst
.operands
[1].present
11795 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11796 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11797 Rn
= inst
.operands
[2].reg
;
11799 reject_bad_reg (Rd
);
11800 reject_bad_reg (Rs
);
11801 if (inst
.operands
[2].isreg
)
11802 reject_bad_reg (Rn
);
11804 if (unified_syntax
)
11806 if (!inst
.operands
[2].isreg
)
11808 /* For an immediate, we always generate a 32-bit opcode;
11809 section relaxation will shrink it later if possible. */
11810 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11811 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11812 inst
.instruction
|= Rd
<< 8;
11813 inst
.instruction
|= Rs
<< 16;
11814 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11818 bfd_boolean narrow
;
11820 /* See if we can do this with a 16-bit instruction. */
11821 if (THUMB_SETS_FLAGS (inst
.instruction
))
11822 narrow
= !in_pred_block ();
11824 narrow
= in_pred_block ();
11826 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11828 if (inst
.operands
[2].shifted
)
11830 if (inst
.size_req
== 4)
11836 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11837 inst
.instruction
|= Rd
;
11838 inst
.instruction
|= Rn
<< 3;
11842 /* If we get here, it can't be done in 16 bits. */
11843 constraint (inst
.operands
[2].shifted
11844 && inst
.operands
[2].immisreg
,
11845 _("shift must be constant"));
11846 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11847 inst
.instruction
|= Rd
<< 8;
11848 inst
.instruction
|= Rs
<< 16;
11849 encode_thumb32_shifted_operand (2);
11854 /* On its face this is a lie - the instruction does set the
11855 flags. However, the only supported mnemonic in this mode
11856 says it doesn't. */
11857 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11859 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11860 _("unshifted register required"));
11861 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11862 constraint (Rd
!= Rs
,
11863 _("dest and source1 must be the same register"));
11865 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11866 inst
.instruction
|= Rd
;
11867 inst
.instruction
|= Rn
<< 3;
11871 /* Similarly, but for instructions where the arithmetic operation is
11872 commutative, so we can allow either of them to be different from
11873 the destination operand in a 16-bit instruction. For instance, all
11874 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11881 Rd
= inst
.operands
[0].reg
;
11882 Rs
= (inst
.operands
[1].present
11883 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11884 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11885 Rn
= inst
.operands
[2].reg
;
11887 reject_bad_reg (Rd
);
11888 reject_bad_reg (Rs
);
11889 if (inst
.operands
[2].isreg
)
11890 reject_bad_reg (Rn
);
11892 if (unified_syntax
)
11894 if (!inst
.operands
[2].isreg
)
11896 /* For an immediate, we always generate a 32-bit opcode;
11897 section relaxation will shrink it later if possible. */
11898 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11899 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11900 inst
.instruction
|= Rd
<< 8;
11901 inst
.instruction
|= Rs
<< 16;
11902 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11906 bfd_boolean narrow
;
11908 /* See if we can do this with a 16-bit instruction. */
11909 if (THUMB_SETS_FLAGS (inst
.instruction
))
11910 narrow
= !in_pred_block ();
11912 narrow
= in_pred_block ();
11914 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11916 if (inst
.operands
[2].shifted
)
11918 if (inst
.size_req
== 4)
11925 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11926 inst
.instruction
|= Rd
;
11927 inst
.instruction
|= Rn
<< 3;
11932 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11933 inst
.instruction
|= Rd
;
11934 inst
.instruction
|= Rs
<< 3;
11939 /* If we get here, it can't be done in 16 bits. */
11940 constraint (inst
.operands
[2].shifted
11941 && inst
.operands
[2].immisreg
,
11942 _("shift must be constant"));
11943 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11944 inst
.instruction
|= Rd
<< 8;
11945 inst
.instruction
|= Rs
<< 16;
11946 encode_thumb32_shifted_operand (2);
11951 /* On its face this is a lie - the instruction does set the
11952 flags. However, the only supported mnemonic in this mode
11953 says it doesn't. */
11954 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11956 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11957 _("unshifted register required"));
11958 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11960 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11961 inst
.instruction
|= Rd
;
11964 inst
.instruction
|= Rn
<< 3;
11966 inst
.instruction
|= Rs
<< 3;
11968 constraint (1, _("dest must overlap one source register"));
11976 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11977 constraint (msb
> 32, _("bit-field extends past end of register"));
11978 /* The instruction encoding stores the LSB and MSB,
11979 not the LSB and width. */
11980 Rd
= inst
.operands
[0].reg
;
11981 reject_bad_reg (Rd
);
11982 inst
.instruction
|= Rd
<< 8;
11983 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11984 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11985 inst
.instruction
|= msb
- 1;
11994 Rd
= inst
.operands
[0].reg
;
11995 reject_bad_reg (Rd
);
11997 /* #0 in second position is alternative syntax for bfc, which is
11998 the same instruction but with REG_PC in the Rm field. */
11999 if (!inst
.operands
[1].isreg
)
12003 Rn
= inst
.operands
[1].reg
;
12004 reject_bad_reg (Rn
);
12007 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
12008 constraint (msb
> 32, _("bit-field extends past end of register"));
12009 /* The instruction encoding stores the LSB and MSB,
12010 not the LSB and width. */
12011 inst
.instruction
|= Rd
<< 8;
12012 inst
.instruction
|= Rn
<< 16;
12013 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12014 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12015 inst
.instruction
|= msb
- 1;
12023 Rd
= inst
.operands
[0].reg
;
12024 Rn
= inst
.operands
[1].reg
;
12026 reject_bad_reg (Rd
);
12027 reject_bad_reg (Rn
);
12029 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
12030 _("bit-field extends past end of register"));
12031 inst
.instruction
|= Rd
<< 8;
12032 inst
.instruction
|= Rn
<< 16;
12033 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12034 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12035 inst
.instruction
|= inst
.operands
[3].imm
- 1;
12038 /* ARM V5 Thumb BLX (argument parse)
12039 BLX <target_addr> which is BLX(1)
12040 BLX <Rm> which is BLX(2)
12041 Unfortunately, there are two different opcodes for this mnemonic.
12042 So, the insns[].value is not used, and the code here zaps values
12043 into inst.instruction.
12045 ??? How to take advantage of the additional two bits of displacement
12046 available in Thumb32 mode? Need new relocation? */
12051 set_pred_insn_type_last ();
12053 if (inst
.operands
[0].isreg
)
12055 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
12056 /* We have a register, so this is BLX(2). */
12057 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12061 /* No register. This must be BLX(1). */
12062 inst
.instruction
= 0xf000e800;
12063 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
12072 bfd_reloc_code_real_type reloc
;
12075 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
12077 if (in_pred_block ())
12079 /* Conditional branches inside IT blocks are encoded as unconditional
12081 cond
= COND_ALWAYS
;
12086 if (cond
!= COND_ALWAYS
)
12087 opcode
= T_MNEM_bcond
;
12089 opcode
= inst
.instruction
;
12092 && (inst
.size_req
== 4
12093 || (inst
.size_req
!= 2
12094 && (inst
.operands
[0].hasreloc
12095 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12097 inst
.instruction
= THUMB_OP32(opcode
);
12098 if (cond
== COND_ALWAYS
)
12099 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12102 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12103 _("selected architecture does not support "
12104 "wide conditional branch instruction"));
12106 gas_assert (cond
!= 0xF);
12107 inst
.instruction
|= cond
<< 22;
12108 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12113 inst
.instruction
= THUMB_OP16(opcode
);
12114 if (cond
== COND_ALWAYS
)
12115 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12118 inst
.instruction
|= cond
<< 8;
12119 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12121 /* Allow section relaxation. */
12122 if (unified_syntax
&& inst
.size_req
!= 2)
12123 inst
.relax
= opcode
;
12125 inst
.relocs
[0].type
= reloc
;
12126 inst
.relocs
[0].pc_rel
= 1;
12129 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12130 between the two is the maximum immediate allowed - which is passed in
12133 do_t_bkpt_hlt1 (int range
)
12135 constraint (inst
.cond
!= COND_ALWAYS
,
12136 _("instruction is always unconditional"));
12137 if (inst
.operands
[0].present
)
12139 constraint (inst
.operands
[0].imm
> range
,
12140 _("immediate value out of range"));
12141 inst
.instruction
|= inst
.operands
[0].imm
;
12144 set_pred_insn_type (NEUTRAL_IT_INSN
);
12150 do_t_bkpt_hlt1 (63);
12156 do_t_bkpt_hlt1 (255);
12160 do_t_branch23 (void)
12162 set_pred_insn_type_last ();
12163 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12165 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12166 this file. We used to simply ignore the PLT reloc type here --
12167 the branch encoding is now needed to deal with TLSCALL relocs.
12168 So if we see a PLT reloc now, put it back to how it used to be to
12169 keep the preexisting behaviour. */
12170 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12171 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12173 #if defined(OBJ_COFF)
12174 /* If the destination of the branch is a defined symbol which does not have
12175 the THUMB_FUNC attribute, then we must be calling a function which has
12176 the (interfacearm) attribute. We look for the Thumb entry point to that
12177 function and change the branch to refer to that function instead. */
12178 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12179 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12180 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12181 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12182 inst
.relocs
[0].exp
.X_add_symbol
12183 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12190 set_pred_insn_type_last ();
12191 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12192 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12193 should cause the alignment to be checked once it is known. This is
12194 because BX PC only works if the instruction is word aligned. */
12202 set_pred_insn_type_last ();
12203 Rm
= inst
.operands
[0].reg
;
12204 reject_bad_reg (Rm
);
12205 inst
.instruction
|= Rm
<< 16;
12214 Rd
= inst
.operands
[0].reg
;
12215 Rm
= inst
.operands
[1].reg
;
12217 reject_bad_reg (Rd
);
12218 reject_bad_reg (Rm
);
12220 inst
.instruction
|= Rd
<< 8;
12221 inst
.instruction
|= Rm
<< 16;
12222 inst
.instruction
|= Rm
;
12225 /* For the Armv8.1-M conditional instructions. */
12229 unsigned Rd
, Rn
, Rm
;
12232 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12234 Rd
= inst
.operands
[0].reg
;
12235 switch (inst
.instruction
)
12241 Rn
= inst
.operands
[1].reg
;
12242 Rm
= inst
.operands
[2].reg
;
12243 cond
= inst
.operands
[3].imm
;
12244 constraint (Rn
== REG_SP
, BAD_SP
);
12245 constraint (Rm
== REG_SP
, BAD_SP
);
12251 Rn
= inst
.operands
[1].reg
;
12252 cond
= inst
.operands
[2].imm
;
12253 /* Invert the last bit to invert the cond. */
12254 cond
= TOGGLE_BIT (cond
, 0);
12255 constraint (Rn
== REG_SP
, BAD_SP
);
12261 cond
= inst
.operands
[1].imm
;
12262 /* Invert the last bit to invert the cond. */
12263 cond
= TOGGLE_BIT (cond
, 0);
12271 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12272 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12273 inst
.instruction
|= Rd
<< 8;
12274 inst
.instruction
|= Rn
<< 16;
12275 inst
.instruction
|= Rm
;
12276 inst
.instruction
|= cond
<< 4;
12282 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12288 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12289 inst
.instruction
|= inst
.operands
[0].imm
;
12295 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12297 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12298 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12300 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12301 inst
.instruction
= 0xf3af8000;
12302 inst
.instruction
|= imod
<< 9;
12303 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12304 if (inst
.operands
[1].present
)
12305 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12309 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12310 && (inst
.operands
[0].imm
& 4),
12311 _("selected processor does not support 'A' form "
12312 "of this instruction"));
12313 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12314 _("Thumb does not support the 2-argument "
12315 "form of this instruction"));
12316 inst
.instruction
|= inst
.operands
[0].imm
;
12320 /* THUMB CPY instruction (argument parse). */
12325 if (inst
.size_req
== 4)
12327 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12328 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12329 inst
.instruction
|= inst
.operands
[1].reg
;
12333 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12334 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12335 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12342 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12343 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12344 inst
.instruction
|= inst
.operands
[0].reg
;
12345 inst
.relocs
[0].pc_rel
= 1;
12346 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12352 inst
.instruction
|= inst
.operands
[0].imm
;
12358 unsigned Rd
, Rn
, Rm
;
12360 Rd
= inst
.operands
[0].reg
;
12361 Rn
= (inst
.operands
[1].present
12362 ? inst
.operands
[1].reg
: Rd
);
12363 Rm
= inst
.operands
[2].reg
;
12365 reject_bad_reg (Rd
);
12366 reject_bad_reg (Rn
);
12367 reject_bad_reg (Rm
);
12369 inst
.instruction
|= Rd
<< 8;
12370 inst
.instruction
|= Rn
<< 16;
12371 inst
.instruction
|= Rm
;
12377 if (unified_syntax
&& inst
.size_req
== 4)
12378 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12380 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12386 unsigned int cond
= inst
.operands
[0].imm
;
12388 set_pred_insn_type (IT_INSN
);
12389 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12390 now_pred
.cc
= cond
;
12391 now_pred
.warn_deprecated
= FALSE
;
12392 now_pred
.type
= SCALAR_PRED
;
12394 /* If the condition is a negative condition, invert the mask. */
12395 if ((cond
& 0x1) == 0x0)
12397 unsigned int mask
= inst
.instruction
& 0x000f;
12399 if ((mask
& 0x7) == 0)
12401 /* No conversion needed. */
12402 now_pred
.block_length
= 1;
12404 else if ((mask
& 0x3) == 0)
12407 now_pred
.block_length
= 2;
12409 else if ((mask
& 0x1) == 0)
12412 now_pred
.block_length
= 3;
12417 now_pred
.block_length
= 4;
12420 inst
.instruction
&= 0xfff0;
12421 inst
.instruction
|= mask
;
12424 inst
.instruction
|= cond
<< 4;
12427 /* Helper function used for both push/pop and ldm/stm. */
12429 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12430 bfd_boolean writeback
)
12432 bfd_boolean load
, store
;
12434 gas_assert (base
!= -1 || !do_io
);
12435 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12436 store
= do_io
&& !load
;
12438 if (mask
& (1 << 13))
12439 inst
.error
= _("SP not allowed in register list");
12441 if (do_io
&& (mask
& (1 << base
)) != 0
12443 inst
.error
= _("having the base register in the register list when "
12444 "using write back is UNPREDICTABLE");
12448 if (mask
& (1 << 15))
12450 if (mask
& (1 << 14))
12451 inst
.error
= _("LR and PC should not both be in register list");
12453 set_pred_insn_type_last ();
12458 if (mask
& (1 << 15))
12459 inst
.error
= _("PC not allowed in register list");
12462 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12464 /* Single register transfers implemented as str/ldr. */
12467 if (inst
.instruction
& (1 << 23))
12468 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12470 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12474 if (inst
.instruction
& (1 << 23))
12475 inst
.instruction
= 0x00800000; /* ia -> [base] */
12477 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12480 inst
.instruction
|= 0xf8400000;
12482 inst
.instruction
|= 0x00100000;
12484 mask
= ffs (mask
) - 1;
12487 else if (writeback
)
12488 inst
.instruction
|= WRITE_BACK
;
12490 inst
.instruction
|= mask
;
12492 inst
.instruction
|= base
<< 16;
12498 /* This really doesn't seem worth it. */
12499 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12500 _("expression too complex"));
12501 constraint (inst
.operands
[1].writeback
,
12502 _("Thumb load/store multiple does not support {reglist}^"));
12504 if (unified_syntax
)
12506 bfd_boolean narrow
;
12510 /* See if we can use a 16-bit instruction. */
12511 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12512 && inst
.size_req
!= 4
12513 && !(inst
.operands
[1].imm
& ~0xff))
12515 mask
= 1 << inst
.operands
[0].reg
;
12517 if (inst
.operands
[0].reg
<= 7)
12519 if (inst
.instruction
== T_MNEM_stmia
12520 ? inst
.operands
[0].writeback
12521 : (inst
.operands
[0].writeback
12522 == !(inst
.operands
[1].imm
& mask
)))
12524 if (inst
.instruction
== T_MNEM_stmia
12525 && (inst
.operands
[1].imm
& mask
)
12526 && (inst
.operands
[1].imm
& (mask
- 1)))
12527 as_warn (_("value stored for r%d is UNKNOWN"),
12528 inst
.operands
[0].reg
);
12530 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12531 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12532 inst
.instruction
|= inst
.operands
[1].imm
;
12535 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12537 /* This means 1 register in reg list one of 3 situations:
12538 1. Instruction is stmia, but without writeback.
12539 2. lmdia without writeback, but with Rn not in
12541 3. ldmia with writeback, but with Rn in reglist.
12542 Case 3 is UNPREDICTABLE behaviour, so we handle
12543 case 1 and 2 which can be converted into a 16-bit
12544 str or ldr. The SP cases are handled below. */
12545 unsigned long opcode
;
12546 /* First, record an error for Case 3. */
12547 if (inst
.operands
[1].imm
& mask
12548 && inst
.operands
[0].writeback
)
12550 _("having the base register in the register list when "
12551 "using write back is UNPREDICTABLE");
12553 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12555 inst
.instruction
= THUMB_OP16 (opcode
);
12556 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12557 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12561 else if (inst
.operands
[0] .reg
== REG_SP
)
12563 if (inst
.operands
[0].writeback
)
12566 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12567 ? T_MNEM_push
: T_MNEM_pop
);
12568 inst
.instruction
|= inst
.operands
[1].imm
;
12571 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12574 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12575 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12576 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12584 if (inst
.instruction
< 0xffff)
12585 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12587 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12588 inst
.operands
[1].imm
,
12589 inst
.operands
[0].writeback
);
12594 constraint (inst
.operands
[0].reg
> 7
12595 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12596 constraint (inst
.instruction
!= T_MNEM_ldmia
12597 && inst
.instruction
!= T_MNEM_stmia
,
12598 _("Thumb-2 instruction only valid in unified syntax"));
12599 if (inst
.instruction
== T_MNEM_stmia
)
12601 if (!inst
.operands
[0].writeback
)
12602 as_warn (_("this instruction will write back the base register"));
12603 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12604 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12605 as_warn (_("value stored for r%d is UNKNOWN"),
12606 inst
.operands
[0].reg
);
12610 if (!inst
.operands
[0].writeback
12611 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12612 as_warn (_("this instruction will write back the base register"));
12613 else if (inst
.operands
[0].writeback
12614 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12615 as_warn (_("this instruction will not write back the base register"));
12618 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12619 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12620 inst
.instruction
|= inst
.operands
[1].imm
;
12627 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12628 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12629 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12630 || inst
.operands
[1].negative
,
12633 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12635 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12636 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12637 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12643 if (!inst
.operands
[1].present
)
12645 constraint (inst
.operands
[0].reg
== REG_LR
,
12646 _("r14 not allowed as first register "
12647 "when second register is omitted"));
12648 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12650 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12653 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12654 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12655 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12661 unsigned long opcode
;
12664 if (inst
.operands
[0].isreg
12665 && !inst
.operands
[0].preind
12666 && inst
.operands
[0].reg
== REG_PC
)
12667 set_pred_insn_type_last ();
12669 opcode
= inst
.instruction
;
12670 if (unified_syntax
)
12672 if (!inst
.operands
[1].isreg
)
12674 if (opcode
<= 0xffff)
12675 inst
.instruction
= THUMB_OP32 (opcode
);
12676 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12679 if (inst
.operands
[1].isreg
12680 && !inst
.operands
[1].writeback
12681 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12682 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12683 && opcode
<= 0xffff
12684 && inst
.size_req
!= 4)
12686 /* Insn may have a 16-bit form. */
12687 Rn
= inst
.operands
[1].reg
;
12688 if (inst
.operands
[1].immisreg
)
12690 inst
.instruction
= THUMB_OP16 (opcode
);
12692 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12694 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12695 reject_bad_reg (inst
.operands
[1].imm
);
12697 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12698 && opcode
!= T_MNEM_ldrsb
)
12699 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12700 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12707 if (inst
.relocs
[0].pc_rel
)
12708 opcode
= T_MNEM_ldr_pc2
;
12710 opcode
= T_MNEM_ldr_pc
;
12714 if (opcode
== T_MNEM_ldr
)
12715 opcode
= T_MNEM_ldr_sp
;
12717 opcode
= T_MNEM_str_sp
;
12719 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12723 inst
.instruction
= inst
.operands
[0].reg
;
12724 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12726 inst
.instruction
|= THUMB_OP16 (opcode
);
12727 if (inst
.size_req
== 2)
12728 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12730 inst
.relax
= opcode
;
12734 /* Definitely a 32-bit variant. */
12736 /* Warning for Erratum 752419. */
12737 if (opcode
== T_MNEM_ldr
12738 && inst
.operands
[0].reg
== REG_SP
12739 && inst
.operands
[1].writeback
== 1
12740 && !inst
.operands
[1].immisreg
)
12742 if (no_cpu_selected ()
12743 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12744 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12745 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12746 as_warn (_("This instruction may be unpredictable "
12747 "if executed on M-profile cores "
12748 "with interrupts enabled."));
12751 /* Do some validations regarding addressing modes. */
12752 if (inst
.operands
[1].immisreg
)
12753 reject_bad_reg (inst
.operands
[1].imm
);
12755 constraint (inst
.operands
[1].writeback
== 1
12756 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12759 inst
.instruction
= THUMB_OP32 (opcode
);
12760 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12761 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12762 check_ldr_r15_aligned ();
12766 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12768 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12770 /* Only [Rn,Rm] is acceptable. */
12771 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12772 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12773 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12774 || inst
.operands
[1].negative
,
12775 _("Thumb does not support this addressing mode"));
12776 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12780 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12781 if (!inst
.operands
[1].isreg
)
12782 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12785 constraint (!inst
.operands
[1].preind
12786 || inst
.operands
[1].shifted
12787 || inst
.operands
[1].writeback
,
12788 _("Thumb does not support this addressing mode"));
12789 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12791 constraint (inst
.instruction
& 0x0600,
12792 _("byte or halfword not valid for base register"));
12793 constraint (inst
.operands
[1].reg
== REG_PC
12794 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12795 _("r15 based store not allowed"));
12796 constraint (inst
.operands
[1].immisreg
,
12797 _("invalid base register for register offset"));
12799 if (inst
.operands
[1].reg
== REG_PC
)
12800 inst
.instruction
= T_OPCODE_LDR_PC
;
12801 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12802 inst
.instruction
= T_OPCODE_LDR_SP
;
12804 inst
.instruction
= T_OPCODE_STR_SP
;
12806 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12807 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12811 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12812 if (!inst
.operands
[1].immisreg
)
12814 /* Immediate offset. */
12815 inst
.instruction
|= inst
.operands
[0].reg
;
12816 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12817 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12821 /* Register offset. */
12822 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12823 constraint (inst
.operands
[1].negative
,
12824 _("Thumb does not support this addressing mode"));
12827 switch (inst
.instruction
)
12829 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12830 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12831 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12832 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12833 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12834 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12835 case 0x5600 /* ldrsb */:
12836 case 0x5e00 /* ldrsh */: break;
12840 inst
.instruction
|= inst
.operands
[0].reg
;
12841 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12842 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12848 if (!inst
.operands
[1].present
)
12850 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12851 constraint (inst
.operands
[0].reg
== REG_LR
,
12852 _("r14 not allowed here"));
12853 constraint (inst
.operands
[0].reg
== REG_R12
,
12854 _("r12 not allowed here"));
12857 if (inst
.operands
[2].writeback
12858 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12859 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12860 as_warn (_("base register written back, and overlaps "
12861 "one of transfer registers"));
12863 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12864 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12865 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12871 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12872 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12878 unsigned Rd
, Rn
, Rm
, Ra
;
12880 Rd
= inst
.operands
[0].reg
;
12881 Rn
= inst
.operands
[1].reg
;
12882 Rm
= inst
.operands
[2].reg
;
12883 Ra
= inst
.operands
[3].reg
;
12885 reject_bad_reg (Rd
);
12886 reject_bad_reg (Rn
);
12887 reject_bad_reg (Rm
);
12888 reject_bad_reg (Ra
);
12890 inst
.instruction
|= Rd
<< 8;
12891 inst
.instruction
|= Rn
<< 16;
12892 inst
.instruction
|= Rm
;
12893 inst
.instruction
|= Ra
<< 12;
12899 unsigned RdLo
, RdHi
, Rn
, Rm
;
12901 RdLo
= inst
.operands
[0].reg
;
12902 RdHi
= inst
.operands
[1].reg
;
12903 Rn
= inst
.operands
[2].reg
;
12904 Rm
= inst
.operands
[3].reg
;
12906 reject_bad_reg (RdLo
);
12907 reject_bad_reg (RdHi
);
12908 reject_bad_reg (Rn
);
12909 reject_bad_reg (Rm
);
12911 inst
.instruction
|= RdLo
<< 12;
12912 inst
.instruction
|= RdHi
<< 8;
12913 inst
.instruction
|= Rn
<< 16;
12914 inst
.instruction
|= Rm
;
12918 do_t_mov_cmp (void)
12922 Rn
= inst
.operands
[0].reg
;
12923 Rm
= inst
.operands
[1].reg
;
12926 set_pred_insn_type_last ();
12928 if (unified_syntax
)
12930 int r0off
= (inst
.instruction
== T_MNEM_mov
12931 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12932 unsigned long opcode
;
12933 bfd_boolean narrow
;
12934 bfd_boolean low_regs
;
12936 low_regs
= (Rn
<= 7 && Rm
<= 7);
12937 opcode
= inst
.instruction
;
12938 if (in_pred_block ())
12939 narrow
= opcode
!= T_MNEM_movs
;
12941 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12942 if (inst
.size_req
== 4
12943 || inst
.operands
[1].shifted
)
12946 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12947 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12948 && !inst
.operands
[1].shifted
12952 inst
.instruction
= T2_SUBS_PC_LR
;
12956 if (opcode
== T_MNEM_cmp
)
12958 constraint (Rn
== REG_PC
, BAD_PC
);
12961 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12963 warn_deprecated_sp (Rm
);
12964 /* R15 was documented as a valid choice for Rm in ARMv6,
12965 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12966 tools reject R15, so we do too. */
12967 constraint (Rm
== REG_PC
, BAD_PC
);
12970 reject_bad_reg (Rm
);
12972 else if (opcode
== T_MNEM_mov
12973 || opcode
== T_MNEM_movs
)
12975 if (inst
.operands
[1].isreg
)
12977 if (opcode
== T_MNEM_movs
)
12979 reject_bad_reg (Rn
);
12980 reject_bad_reg (Rm
);
12984 /* This is mov.n. */
12985 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12986 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12988 as_tsktsk (_("Use of r%u as a source register is "
12989 "deprecated when r%u is the destination "
12990 "register."), Rm
, Rn
);
12995 /* This is mov.w. */
12996 constraint (Rn
== REG_PC
, BAD_PC
);
12997 constraint (Rm
== REG_PC
, BAD_PC
);
12998 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12999 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
13003 reject_bad_reg (Rn
);
13006 if (!inst
.operands
[1].isreg
)
13008 /* Immediate operand. */
13009 if (!in_pred_block () && opcode
== T_MNEM_mov
)
13011 if (low_regs
&& narrow
)
13013 inst
.instruction
= THUMB_OP16 (opcode
);
13014 inst
.instruction
|= Rn
<< 8;
13015 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
13016 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
13018 if (inst
.size_req
== 2)
13019 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13021 inst
.relax
= opcode
;
13026 constraint ((inst
.relocs
[0].type
13027 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
13028 && (inst
.relocs
[0].type
13029 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
13030 THUMB1_RELOC_ONLY
);
13032 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13033 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13034 inst
.instruction
|= Rn
<< r0off
;
13035 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13038 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
13039 && (inst
.instruction
== T_MNEM_mov
13040 || inst
.instruction
== T_MNEM_movs
))
13042 /* Register shifts are encoded as separate shift instructions. */
13043 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
13045 if (in_pred_block ())
13050 if (inst
.size_req
== 4)
13053 if (!low_regs
|| inst
.operands
[1].imm
> 7)
13059 switch (inst
.operands
[1].shift_kind
)
13062 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
13065 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
13068 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
13071 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
13077 inst
.instruction
= opcode
;
13080 inst
.instruction
|= Rn
;
13081 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13086 inst
.instruction
|= CONDS_BIT
;
13088 inst
.instruction
|= Rn
<< 8;
13089 inst
.instruction
|= Rm
<< 16;
13090 inst
.instruction
|= inst
.operands
[1].imm
;
13095 /* Some mov with immediate shift have narrow variants.
13096 Register shifts are handled above. */
13097 if (low_regs
&& inst
.operands
[1].shifted
13098 && (inst
.instruction
== T_MNEM_mov
13099 || inst
.instruction
== T_MNEM_movs
))
13101 if (in_pred_block ())
13102 narrow
= (inst
.instruction
== T_MNEM_mov
);
13104 narrow
= (inst
.instruction
== T_MNEM_movs
);
13109 switch (inst
.operands
[1].shift_kind
)
13111 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13112 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13113 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13114 default: narrow
= FALSE
; break;
13120 inst
.instruction
|= Rn
;
13121 inst
.instruction
|= Rm
<< 3;
13122 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13126 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13127 inst
.instruction
|= Rn
<< r0off
;
13128 encode_thumb32_shifted_operand (1);
13132 switch (inst
.instruction
)
13135 /* In v4t or v5t a move of two lowregs produces unpredictable
13136 results. Don't allow this. */
13139 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13140 "MOV Rd, Rs with two low registers is not "
13141 "permitted on this architecture");
13142 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13146 inst
.instruction
= T_OPCODE_MOV_HR
;
13147 inst
.instruction
|= (Rn
& 0x8) << 4;
13148 inst
.instruction
|= (Rn
& 0x7);
13149 inst
.instruction
|= Rm
<< 3;
13153 /* We know we have low registers at this point.
13154 Generate LSLS Rd, Rs, #0. */
13155 inst
.instruction
= T_OPCODE_LSL_I
;
13156 inst
.instruction
|= Rn
;
13157 inst
.instruction
|= Rm
<< 3;
13163 inst
.instruction
= T_OPCODE_CMP_LR
;
13164 inst
.instruction
|= Rn
;
13165 inst
.instruction
|= Rm
<< 3;
13169 inst
.instruction
= T_OPCODE_CMP_HR
;
13170 inst
.instruction
|= (Rn
& 0x8) << 4;
13171 inst
.instruction
|= (Rn
& 0x7);
13172 inst
.instruction
|= Rm
<< 3;
13179 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13181 /* PR 10443: Do not silently ignore shifted operands. */
13182 constraint (inst
.operands
[1].shifted
,
13183 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13185 if (inst
.operands
[1].isreg
)
13187 if (Rn
< 8 && Rm
< 8)
13189 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13190 since a MOV instruction produces unpredictable results. */
13191 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13192 inst
.instruction
= T_OPCODE_ADD_I3
;
13194 inst
.instruction
= T_OPCODE_CMP_LR
;
13196 inst
.instruction
|= Rn
;
13197 inst
.instruction
|= Rm
<< 3;
13201 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13202 inst
.instruction
= T_OPCODE_MOV_HR
;
13204 inst
.instruction
= T_OPCODE_CMP_HR
;
13210 constraint (Rn
> 7,
13211 _("only lo regs allowed with immediate"));
13212 inst
.instruction
|= Rn
<< 8;
13213 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13224 top
= (inst
.instruction
& 0x00800000) != 0;
13225 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13227 constraint (top
, _(":lower16: not allowed in this instruction"));
13228 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13230 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13232 constraint (!top
, _(":upper16: not allowed in this instruction"));
13233 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13236 Rd
= inst
.operands
[0].reg
;
13237 reject_bad_reg (Rd
);
13239 inst
.instruction
|= Rd
<< 8;
13240 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13242 imm
= inst
.relocs
[0].exp
.X_add_number
;
13243 inst
.instruction
|= (imm
& 0xf000) << 4;
13244 inst
.instruction
|= (imm
& 0x0800) << 15;
13245 inst
.instruction
|= (imm
& 0x0700) << 4;
13246 inst
.instruction
|= (imm
& 0x00ff);
13251 do_t_mvn_tst (void)
13255 Rn
= inst
.operands
[0].reg
;
13256 Rm
= inst
.operands
[1].reg
;
13258 if (inst
.instruction
== T_MNEM_cmp
13259 || inst
.instruction
== T_MNEM_cmn
)
13260 constraint (Rn
== REG_PC
, BAD_PC
);
13262 reject_bad_reg (Rn
);
13263 reject_bad_reg (Rm
);
13265 if (unified_syntax
)
13267 int r0off
= (inst
.instruction
== T_MNEM_mvn
13268 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13269 bfd_boolean narrow
;
13271 if (inst
.size_req
== 4
13272 || inst
.instruction
> 0xffff
13273 || inst
.operands
[1].shifted
13274 || Rn
> 7 || Rm
> 7)
13276 else if (inst
.instruction
== T_MNEM_cmn
13277 || inst
.instruction
== T_MNEM_tst
)
13279 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13280 narrow
= !in_pred_block ();
13282 narrow
= in_pred_block ();
13284 if (!inst
.operands
[1].isreg
)
13286 /* For an immediate, we always generate a 32-bit opcode;
13287 section relaxation will shrink it later if possible. */
13288 if (inst
.instruction
< 0xffff)
13289 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13290 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13291 inst
.instruction
|= Rn
<< r0off
;
13292 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13296 /* See if we can do this with a 16-bit instruction. */
13299 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13300 inst
.instruction
|= Rn
;
13301 inst
.instruction
|= Rm
<< 3;
13305 constraint (inst
.operands
[1].shifted
13306 && inst
.operands
[1].immisreg
,
13307 _("shift must be constant"));
13308 if (inst
.instruction
< 0xffff)
13309 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13310 inst
.instruction
|= Rn
<< r0off
;
13311 encode_thumb32_shifted_operand (1);
13317 constraint (inst
.instruction
> 0xffff
13318 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13319 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13320 _("unshifted register required"));
13321 constraint (Rn
> 7 || Rm
> 7,
13324 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13325 inst
.instruction
|= Rn
;
13326 inst
.instruction
|= Rm
<< 3;
13335 if (do_vfp_nsyn_mrs () == SUCCESS
)
13338 Rd
= inst
.operands
[0].reg
;
13339 reject_bad_reg (Rd
);
13340 inst
.instruction
|= Rd
<< 8;
13342 if (inst
.operands
[1].isreg
)
13344 unsigned br
= inst
.operands
[1].reg
;
13345 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13346 as_bad (_("bad register for mrs"));
13348 inst
.instruction
|= br
& (0xf << 16);
13349 inst
.instruction
|= (br
& 0x300) >> 4;
13350 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13354 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13356 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13358 /* PR gas/12698: The constraint is only applied for m_profile.
13359 If the user has specified -march=all, we want to ignore it as
13360 we are building for any CPU type, including non-m variants. */
13361 bfd_boolean m_profile
=
13362 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13363 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13364 "not support requested special purpose register"));
13367 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13369 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13370 _("'APSR', 'CPSR' or 'SPSR' expected"));
13372 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13373 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13374 inst
.instruction
|= 0xf0000;
13384 if (do_vfp_nsyn_msr () == SUCCESS
)
13387 constraint (!inst
.operands
[1].isreg
,
13388 _("Thumb encoding does not support an immediate here"));
13390 if (inst
.operands
[0].isreg
)
13391 flags
= (int)(inst
.operands
[0].reg
);
13393 flags
= inst
.operands
[0].imm
;
13395 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13397 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13399 /* PR gas/12698: The constraint is only applied for m_profile.
13400 If the user has specified -march=all, we want to ignore it as
13401 we are building for any CPU type, including non-m variants. */
13402 bfd_boolean m_profile
=
13403 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13404 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13405 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13406 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13407 && bits
!= PSR_f
)) && m_profile
,
13408 _("selected processor does not support requested special "
13409 "purpose register"));
13412 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13413 "requested special purpose register"));
13415 Rn
= inst
.operands
[1].reg
;
13416 reject_bad_reg (Rn
);
13418 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13419 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13420 inst
.instruction
|= (flags
& 0x300) >> 4;
13421 inst
.instruction
|= (flags
& 0xff);
13422 inst
.instruction
|= Rn
<< 16;
13428 bfd_boolean narrow
;
13429 unsigned Rd
, Rn
, Rm
;
13431 if (!inst
.operands
[2].present
)
13432 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13434 Rd
= inst
.operands
[0].reg
;
13435 Rn
= inst
.operands
[1].reg
;
13436 Rm
= inst
.operands
[2].reg
;
13438 if (unified_syntax
)
13440 if (inst
.size_req
== 4
13446 else if (inst
.instruction
== T_MNEM_muls
)
13447 narrow
= !in_pred_block ();
13449 narrow
= in_pred_block ();
13453 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13454 constraint (Rn
> 7 || Rm
> 7,
13461 /* 16-bit MULS/Conditional MUL. */
13462 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13463 inst
.instruction
|= Rd
;
13466 inst
.instruction
|= Rm
<< 3;
13468 inst
.instruction
|= Rn
<< 3;
13470 constraint (1, _("dest must overlap one source register"));
13474 constraint (inst
.instruction
!= T_MNEM_mul
,
13475 _("Thumb-2 MUL must not set flags"));
13477 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13478 inst
.instruction
|= Rd
<< 8;
13479 inst
.instruction
|= Rn
<< 16;
13480 inst
.instruction
|= Rm
<< 0;
13482 reject_bad_reg (Rd
);
13483 reject_bad_reg (Rn
);
13484 reject_bad_reg (Rm
);
13491 unsigned RdLo
, RdHi
, Rn
, Rm
;
13493 RdLo
= inst
.operands
[0].reg
;
13494 RdHi
= inst
.operands
[1].reg
;
13495 Rn
= inst
.operands
[2].reg
;
13496 Rm
= inst
.operands
[3].reg
;
13498 reject_bad_reg (RdLo
);
13499 reject_bad_reg (RdHi
);
13500 reject_bad_reg (Rn
);
13501 reject_bad_reg (Rm
);
13503 inst
.instruction
|= RdLo
<< 12;
13504 inst
.instruction
|= RdHi
<< 8;
13505 inst
.instruction
|= Rn
<< 16;
13506 inst
.instruction
|= Rm
;
13509 as_tsktsk (_("rdhi and rdlo must be different"));
13515 set_pred_insn_type (NEUTRAL_IT_INSN
);
13517 if (unified_syntax
)
13519 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13521 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13522 inst
.instruction
|= inst
.operands
[0].imm
;
13526 /* PR9722: Check for Thumb2 availability before
13527 generating a thumb2 nop instruction. */
13528 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13530 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13531 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13534 inst
.instruction
= 0x46c0;
13539 constraint (inst
.operands
[0].present
,
13540 _("Thumb does not support NOP with hints"));
13541 inst
.instruction
= 0x46c0;
13548 if (unified_syntax
)
13550 bfd_boolean narrow
;
13552 if (THUMB_SETS_FLAGS (inst
.instruction
))
13553 narrow
= !in_pred_block ();
13555 narrow
= in_pred_block ();
13556 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13558 if (inst
.size_req
== 4)
13563 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13564 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13565 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13569 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13570 inst
.instruction
|= inst
.operands
[0].reg
;
13571 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13576 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13578 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13580 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13581 inst
.instruction
|= inst
.operands
[0].reg
;
13582 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13591 Rd
= inst
.operands
[0].reg
;
13592 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13594 reject_bad_reg (Rd
);
13595 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13596 reject_bad_reg (Rn
);
13598 inst
.instruction
|= Rd
<< 8;
13599 inst
.instruction
|= Rn
<< 16;
13601 if (!inst
.operands
[2].isreg
)
13603 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13604 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13610 Rm
= inst
.operands
[2].reg
;
13611 reject_bad_reg (Rm
);
13613 constraint (inst
.operands
[2].shifted
13614 && inst
.operands
[2].immisreg
,
13615 _("shift must be constant"));
13616 encode_thumb32_shifted_operand (2);
13623 unsigned Rd
, Rn
, Rm
;
13625 Rd
= inst
.operands
[0].reg
;
13626 Rn
= inst
.operands
[1].reg
;
13627 Rm
= inst
.operands
[2].reg
;
13629 reject_bad_reg (Rd
);
13630 reject_bad_reg (Rn
);
13631 reject_bad_reg (Rm
);
13633 inst
.instruction
|= Rd
<< 8;
13634 inst
.instruction
|= Rn
<< 16;
13635 inst
.instruction
|= Rm
;
13636 if (inst
.operands
[3].present
)
13638 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13639 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13640 _("expression too complex"));
13641 inst
.instruction
|= (val
& 0x1c) << 10;
13642 inst
.instruction
|= (val
& 0x03) << 6;
13649 if (!inst
.operands
[3].present
)
13653 inst
.instruction
&= ~0x00000020;
13655 /* PR 10168. Swap the Rm and Rn registers. */
13656 Rtmp
= inst
.operands
[1].reg
;
13657 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13658 inst
.operands
[2].reg
= Rtmp
;
13666 if (inst
.operands
[0].immisreg
)
13667 reject_bad_reg (inst
.operands
[0].imm
);
13669 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13673 do_t_push_pop (void)
13677 constraint (inst
.operands
[0].writeback
,
13678 _("push/pop do not support {reglist}^"));
13679 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13680 _("expression too complex"));
13682 mask
= inst
.operands
[0].imm
;
13683 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13684 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13685 else if (inst
.size_req
!= 4
13686 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13687 ? REG_LR
: REG_PC
)))
13689 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13690 inst
.instruction
|= THUMB_PP_PC_LR
;
13691 inst
.instruction
|= mask
& 0xff;
13693 else if (unified_syntax
)
13695 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13696 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13700 inst
.error
= _("invalid register list to push/pop instruction");
13708 if (unified_syntax
)
13709 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13712 inst
.error
= _("invalid register list to push/pop instruction");
13718 do_t_vscclrm (void)
13720 if (inst
.operands
[0].issingle
)
13722 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13723 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13724 inst
.instruction
|= inst
.operands
[0].imm
;
13728 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13729 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13730 inst
.instruction
|= 1 << 8;
13731 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13740 Rd
= inst
.operands
[0].reg
;
13741 Rm
= inst
.operands
[1].reg
;
13743 reject_bad_reg (Rd
);
13744 reject_bad_reg (Rm
);
13746 inst
.instruction
|= Rd
<< 8;
13747 inst
.instruction
|= Rm
<< 16;
13748 inst
.instruction
|= Rm
;
13756 Rd
= inst
.operands
[0].reg
;
13757 Rm
= inst
.operands
[1].reg
;
13759 reject_bad_reg (Rd
);
13760 reject_bad_reg (Rm
);
13762 if (Rd
<= 7 && Rm
<= 7
13763 && inst
.size_req
!= 4)
13765 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13766 inst
.instruction
|= Rd
;
13767 inst
.instruction
|= Rm
<< 3;
13769 else if (unified_syntax
)
13771 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13772 inst
.instruction
|= Rd
<< 8;
13773 inst
.instruction
|= Rm
<< 16;
13774 inst
.instruction
|= Rm
;
13777 inst
.error
= BAD_HIREG
;
13785 Rd
= inst
.operands
[0].reg
;
13786 Rm
= inst
.operands
[1].reg
;
13788 reject_bad_reg (Rd
);
13789 reject_bad_reg (Rm
);
13791 inst
.instruction
|= Rd
<< 8;
13792 inst
.instruction
|= Rm
;
13800 Rd
= inst
.operands
[0].reg
;
13801 Rs
= (inst
.operands
[1].present
13802 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13803 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13805 reject_bad_reg (Rd
);
13806 reject_bad_reg (Rs
);
13807 if (inst
.operands
[2].isreg
)
13808 reject_bad_reg (inst
.operands
[2].reg
);
13810 inst
.instruction
|= Rd
<< 8;
13811 inst
.instruction
|= Rs
<< 16;
13812 if (!inst
.operands
[2].isreg
)
13814 bfd_boolean narrow
;
13816 if ((inst
.instruction
& 0x00100000) != 0)
13817 narrow
= !in_pred_block ();
13819 narrow
= in_pred_block ();
13821 if (Rd
> 7 || Rs
> 7)
13824 if (inst
.size_req
== 4 || !unified_syntax
)
13827 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13828 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13831 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13832 relaxation, but it doesn't seem worth the hassle. */
13835 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13836 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13837 inst
.instruction
|= Rs
<< 3;
13838 inst
.instruction
|= Rd
;
13842 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13843 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13847 encode_thumb32_shifted_operand (2);
13853 if (warn_on_deprecated
13854 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13855 as_tsktsk (_("setend use is deprecated for ARMv8"));
13857 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13858 if (inst
.operands
[0].imm
)
13859 inst
.instruction
|= 0x8;
13865 if (!inst
.operands
[1].present
)
13866 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13868 if (unified_syntax
)
13870 bfd_boolean narrow
;
13873 switch (inst
.instruction
)
13876 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13878 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13880 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13882 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13886 if (THUMB_SETS_FLAGS (inst
.instruction
))
13887 narrow
= !in_pred_block ();
13889 narrow
= in_pred_block ();
13890 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13892 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13894 if (inst
.operands
[2].isreg
13895 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13896 || inst
.operands
[2].reg
> 7))
13898 if (inst
.size_req
== 4)
13901 reject_bad_reg (inst
.operands
[0].reg
);
13902 reject_bad_reg (inst
.operands
[1].reg
);
13906 if (inst
.operands
[2].isreg
)
13908 reject_bad_reg (inst
.operands
[2].reg
);
13909 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13910 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13911 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13912 inst
.instruction
|= inst
.operands
[2].reg
;
13914 /* PR 12854: Error on extraneous shifts. */
13915 constraint (inst
.operands
[2].shifted
,
13916 _("extraneous shift as part of operand to shift insn"));
13920 inst
.operands
[1].shifted
= 1;
13921 inst
.operands
[1].shift_kind
= shift_kind
;
13922 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13923 ? T_MNEM_movs
: T_MNEM_mov
);
13924 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13925 encode_thumb32_shifted_operand (1);
13926 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13927 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13932 if (inst
.operands
[2].isreg
)
13934 switch (shift_kind
)
13936 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13937 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13938 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13939 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13943 inst
.instruction
|= inst
.operands
[0].reg
;
13944 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13946 /* PR 12854: Error on extraneous shifts. */
13947 constraint (inst
.operands
[2].shifted
,
13948 _("extraneous shift as part of operand to shift insn"));
13952 switch (shift_kind
)
13954 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13955 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13956 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13959 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13960 inst
.instruction
|= inst
.operands
[0].reg
;
13961 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13967 constraint (inst
.operands
[0].reg
> 7
13968 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13969 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13971 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13973 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13974 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13975 _("source1 and dest must be same register"));
13977 switch (inst
.instruction
)
13979 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13980 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13981 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13982 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13986 inst
.instruction
|= inst
.operands
[0].reg
;
13987 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13989 /* PR 12854: Error on extraneous shifts. */
13990 constraint (inst
.operands
[2].shifted
,
13991 _("extraneous shift as part of operand to shift insn"));
13995 switch (inst
.instruction
)
13997 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13998 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13999 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14000 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
14003 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14004 inst
.instruction
|= inst
.operands
[0].reg
;
14005 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14013 unsigned Rd
, Rn
, Rm
;
14015 Rd
= inst
.operands
[0].reg
;
14016 Rn
= inst
.operands
[1].reg
;
14017 Rm
= inst
.operands
[2].reg
;
14019 reject_bad_reg (Rd
);
14020 reject_bad_reg (Rn
);
14021 reject_bad_reg (Rm
);
14023 inst
.instruction
|= Rd
<< 8;
14024 inst
.instruction
|= Rn
<< 16;
14025 inst
.instruction
|= Rm
;
14031 unsigned Rd
, Rn
, Rm
;
14033 Rd
= inst
.operands
[0].reg
;
14034 Rm
= inst
.operands
[1].reg
;
14035 Rn
= inst
.operands
[2].reg
;
14037 reject_bad_reg (Rd
);
14038 reject_bad_reg (Rn
);
14039 reject_bad_reg (Rm
);
14041 inst
.instruction
|= Rd
<< 8;
14042 inst
.instruction
|= Rn
<< 16;
14043 inst
.instruction
|= Rm
;
14049 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14050 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
14051 _("SMC is not permitted on this architecture"));
14052 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14053 _("expression too complex"));
14054 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
14056 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14057 inst
.instruction
|= (value
& 0x000f) << 16;
14059 /* PR gas/15623: SMC instructions must be last in an IT block. */
14060 set_pred_insn_type_last ();
14066 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14068 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14069 inst
.instruction
|= (value
& 0x0fff);
14070 inst
.instruction
|= (value
& 0xf000) << 4;
14074 do_t_ssat_usat (int bias
)
14078 Rd
= inst
.operands
[0].reg
;
14079 Rn
= inst
.operands
[2].reg
;
14081 reject_bad_reg (Rd
);
14082 reject_bad_reg (Rn
);
14084 inst
.instruction
|= Rd
<< 8;
14085 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14086 inst
.instruction
|= Rn
<< 16;
14088 if (inst
.operands
[3].present
)
14090 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14092 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14094 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14095 _("expression too complex"));
14097 if (shift_amount
!= 0)
14099 constraint (shift_amount
> 31,
14100 _("shift expression is too large"));
14102 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14103 inst
.instruction
|= 0x00200000; /* sh bit. */
14105 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14106 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14114 do_t_ssat_usat (1);
14122 Rd
= inst
.operands
[0].reg
;
14123 Rn
= inst
.operands
[2].reg
;
14125 reject_bad_reg (Rd
);
14126 reject_bad_reg (Rn
);
14128 inst
.instruction
|= Rd
<< 8;
14129 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14130 inst
.instruction
|= Rn
<< 16;
14136 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14137 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14138 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14139 || inst
.operands
[2].negative
,
14142 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14144 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14145 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14146 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14147 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14153 if (!inst
.operands
[2].present
)
14154 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14156 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14157 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14158 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14161 inst
.instruction
|= inst
.operands
[0].reg
;
14162 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14163 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14164 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14170 unsigned Rd
, Rn
, Rm
;
14172 Rd
= inst
.operands
[0].reg
;
14173 Rn
= inst
.operands
[1].reg
;
14174 Rm
= inst
.operands
[2].reg
;
14176 reject_bad_reg (Rd
);
14177 reject_bad_reg (Rn
);
14178 reject_bad_reg (Rm
);
14180 inst
.instruction
|= Rd
<< 8;
14181 inst
.instruction
|= Rn
<< 16;
14182 inst
.instruction
|= Rm
;
14183 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14191 Rd
= inst
.operands
[0].reg
;
14192 Rm
= inst
.operands
[1].reg
;
14194 reject_bad_reg (Rd
);
14195 reject_bad_reg (Rm
);
14197 if (inst
.instruction
<= 0xffff
14198 && inst
.size_req
!= 4
14199 && Rd
<= 7 && Rm
<= 7
14200 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14202 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14203 inst
.instruction
|= Rd
;
14204 inst
.instruction
|= Rm
<< 3;
14206 else if (unified_syntax
)
14208 if (inst
.instruction
<= 0xffff)
14209 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14210 inst
.instruction
|= Rd
<< 8;
14211 inst
.instruction
|= Rm
;
14212 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14216 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14217 _("Thumb encoding does not support rotation"));
14218 constraint (1, BAD_HIREG
);
14225 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14234 half
= (inst
.instruction
& 0x10) != 0;
14235 set_pred_insn_type_last ();
14236 constraint (inst
.operands
[0].immisreg
,
14237 _("instruction requires register index"));
14239 Rn
= inst
.operands
[0].reg
;
14240 Rm
= inst
.operands
[0].imm
;
14242 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14243 constraint (Rn
== REG_SP
, BAD_SP
);
14244 reject_bad_reg (Rm
);
14246 constraint (!half
&& inst
.operands
[0].shifted
,
14247 _("instruction does not allow shifted index"));
14248 inst
.instruction
|= (Rn
<< 16) | Rm
;
14254 if (!inst
.operands
[0].present
)
14255 inst
.operands
[0].imm
= 0;
14257 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14259 constraint (inst
.size_req
== 2,
14260 _("immediate value out of range"));
14261 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14262 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14263 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14267 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14268 inst
.instruction
|= inst
.operands
[0].imm
;
14271 set_pred_insn_type (NEUTRAL_IT_INSN
);
14278 do_t_ssat_usat (0);
14286 Rd
= inst
.operands
[0].reg
;
14287 Rn
= inst
.operands
[2].reg
;
14289 reject_bad_reg (Rd
);
14290 reject_bad_reg (Rn
);
14292 inst
.instruction
|= Rd
<< 8;
14293 inst
.instruction
|= inst
.operands
[1].imm
;
14294 inst
.instruction
|= Rn
<< 16;
14297 /* Checking the range of the branch offset (VAL) with NBITS bits
14298 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14300 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14302 gas_assert (nbits
> 0 && nbits
<= 32);
14305 int cmp
= (1 << (nbits
- 1));
14306 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14311 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14317 /* For branches in Armv8.1-M Mainline. */
14319 do_t_branch_future (void)
14321 unsigned long insn
= inst
.instruction
;
14323 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14324 if (inst
.operands
[0].hasreloc
== 0)
14326 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14327 as_bad (BAD_BRANCH_OFF
);
14329 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14333 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14334 inst
.relocs
[0].pc_rel
= 1;
14340 if (inst
.operands
[1].hasreloc
== 0)
14342 int val
= inst
.operands
[1].imm
;
14343 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14344 as_bad (BAD_BRANCH_OFF
);
14346 int immA
= (val
& 0x0001f000) >> 12;
14347 int immB
= (val
& 0x00000ffc) >> 2;
14348 int immC
= (val
& 0x00000002) >> 1;
14349 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14353 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14354 inst
.relocs
[1].pc_rel
= 1;
14359 if (inst
.operands
[1].hasreloc
== 0)
14361 int val
= inst
.operands
[1].imm
;
14362 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14363 as_bad (BAD_BRANCH_OFF
);
14365 int immA
= (val
& 0x0007f000) >> 12;
14366 int immB
= (val
& 0x00000ffc) >> 2;
14367 int immC
= (val
& 0x00000002) >> 1;
14368 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14372 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14373 inst
.relocs
[1].pc_rel
= 1;
14377 case T_MNEM_bfcsel
:
14379 if (inst
.operands
[1].hasreloc
== 0)
14381 int val
= inst
.operands
[1].imm
;
14382 int immA
= (val
& 0x00001000) >> 12;
14383 int immB
= (val
& 0x00000ffc) >> 2;
14384 int immC
= (val
& 0x00000002) >> 1;
14385 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14389 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14390 inst
.relocs
[1].pc_rel
= 1;
14394 if (inst
.operands
[2].hasreloc
== 0)
14396 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14397 int val2
= inst
.operands
[2].imm
;
14398 int val0
= inst
.operands
[0].imm
& 0x1f;
14399 int diff
= val2
- val0
;
14401 inst
.instruction
|= 1 << 17; /* T bit. */
14402 else if (diff
!= 2)
14403 as_bad (_("out of range label-relative fixup value"));
14407 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14408 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14409 inst
.relocs
[2].pc_rel
= 1;
14413 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14414 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14419 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14426 /* Helper function for do_t_loloop to handle relocations. */
14428 v8_1_loop_reloc (int is_le
)
14430 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14432 int value
= inst
.relocs
[0].exp
.X_add_number
;
14433 value
= (is_le
) ? -value
: value
;
14435 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14436 as_bad (BAD_BRANCH_OFF
);
14440 immh
= (value
& 0x00000ffc) >> 2;
14441 imml
= (value
& 0x00000002) >> 1;
14443 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14447 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14448 inst
.relocs
[0].pc_rel
= 1;
14452 /* For shifts with four operands in MVE. */
14454 do_mve_scalar_shift1 (void)
14456 unsigned int value
= inst
.operands
[2].imm
;
14458 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14459 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14461 /* Setting the bit for saturation. */
14462 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14464 /* Assuming Rm is already checked not to be 11x1. */
14465 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14466 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14467 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14470 /* For shifts in MVE. */
14472 do_mve_scalar_shift (void)
14474 if (!inst
.operands
[2].present
)
14476 inst
.operands
[2] = inst
.operands
[1];
14477 inst
.operands
[1].reg
= 0xf;
14480 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14481 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14483 if (inst
.operands
[2].isreg
)
14485 /* Assuming Rm is already checked not to be 11x1. */
14486 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14487 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14488 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14492 /* Assuming imm is already checked as [1,32]. */
14493 unsigned int value
= inst
.operands
[2].imm
;
14494 inst
.instruction
|= (value
& 0x1c) << 10;
14495 inst
.instruction
|= (value
& 0x03) << 6;
14496 /* Change last 4 bits from 0xd to 0xf. */
14497 inst
.instruction
|= 0x2;
14501 /* MVE instruction encoder helpers. */
14502 #define M_MNEM_vabav 0xee800f01
14503 #define M_MNEM_vmladav 0xeef00e00
14504 #define M_MNEM_vmladava 0xeef00e20
14505 #define M_MNEM_vmladavx 0xeef01e00
14506 #define M_MNEM_vmladavax 0xeef01e20
14507 #define M_MNEM_vmlsdav 0xeef00e01
14508 #define M_MNEM_vmlsdava 0xeef00e21
14509 #define M_MNEM_vmlsdavx 0xeef01e01
14510 #define M_MNEM_vmlsdavax 0xeef01e21
14511 #define M_MNEM_vmullt 0xee011e00
14512 #define M_MNEM_vmullb 0xee010e00
14513 #define M_MNEM_vctp 0xf000e801
14514 #define M_MNEM_vst20 0xfc801e00
14515 #define M_MNEM_vst21 0xfc801e20
14516 #define M_MNEM_vst40 0xfc801e01
14517 #define M_MNEM_vst41 0xfc801e21
14518 #define M_MNEM_vst42 0xfc801e41
14519 #define M_MNEM_vst43 0xfc801e61
14520 #define M_MNEM_vld20 0xfc901e00
14521 #define M_MNEM_vld21 0xfc901e20
14522 #define M_MNEM_vld40 0xfc901e01
14523 #define M_MNEM_vld41 0xfc901e21
14524 #define M_MNEM_vld42 0xfc901e41
14525 #define M_MNEM_vld43 0xfc901e61
14526 #define M_MNEM_vstrb 0xec000e00
14527 #define M_MNEM_vstrh 0xec000e10
14528 #define M_MNEM_vstrw 0xec000e40
14529 #define M_MNEM_vstrd 0xec000e50
14530 #define M_MNEM_vldrb 0xec100e00
14531 #define M_MNEM_vldrh 0xec100e10
14532 #define M_MNEM_vldrw 0xec100e40
14533 #define M_MNEM_vldrd 0xec100e50
14534 #define M_MNEM_vmovlt 0xeea01f40
14535 #define M_MNEM_vmovlb 0xeea00f40
14536 #define M_MNEM_vmovnt 0xfe311e81
14537 #define M_MNEM_vmovnb 0xfe310e81
14538 #define M_MNEM_vadc 0xee300f00
14539 #define M_MNEM_vadci 0xee301f00
14540 #define M_MNEM_vbrsr 0xfe011e60
14541 #define M_MNEM_vaddlv 0xee890f00
14542 #define M_MNEM_vaddlva 0xee890f20
14543 #define M_MNEM_vaddv 0xeef10f00
14544 #define M_MNEM_vaddva 0xeef10f20
14545 #define M_MNEM_vddup 0xee011f6e
14546 #define M_MNEM_vdwdup 0xee011f60
14547 #define M_MNEM_vidup 0xee010f6e
14548 #define M_MNEM_viwdup 0xee010f60
14549 #define M_MNEM_vmaxv 0xeee20f00
14550 #define M_MNEM_vmaxav 0xeee00f00
14551 #define M_MNEM_vminv 0xeee20f80
14552 #define M_MNEM_vminav 0xeee00f80
14553 #define M_MNEM_vmlaldav 0xee800e00
14554 #define M_MNEM_vmlaldava 0xee800e20
14555 #define M_MNEM_vmlaldavx 0xee801e00
14556 #define M_MNEM_vmlaldavax 0xee801e20
14557 #define M_MNEM_vmlsldav 0xee800e01
14558 #define M_MNEM_vmlsldava 0xee800e21
14559 #define M_MNEM_vmlsldavx 0xee801e01
14560 #define M_MNEM_vmlsldavax 0xee801e21
14561 #define M_MNEM_vrmlaldavhx 0xee801f00
14562 #define M_MNEM_vrmlaldavhax 0xee801f20
14563 #define M_MNEM_vrmlsldavh 0xfe800e01
14564 #define M_MNEM_vrmlsldavha 0xfe800e21
14565 #define M_MNEM_vrmlsldavhx 0xfe801e01
14566 #define M_MNEM_vrmlsldavhax 0xfe801e21
14567 #define M_MNEM_vqmovnt 0xee331e01
14568 #define M_MNEM_vqmovnb 0xee330e01
14569 #define M_MNEM_vqmovunt 0xee311e81
14570 #define M_MNEM_vqmovunb 0xee310e81
14571 #define M_MNEM_vshrnt 0xee801fc1
14572 #define M_MNEM_vshrnb 0xee800fc1
14573 #define M_MNEM_vrshrnt 0xfe801fc1
14574 #define M_MNEM_vqshrnt 0xee801f40
14575 #define M_MNEM_vqshrnb 0xee800f40
14576 #define M_MNEM_vqshrunt 0xee801fc0
14577 #define M_MNEM_vqshrunb 0xee800fc0
14578 #define M_MNEM_vrshrnb 0xfe800fc1
14579 #define M_MNEM_vqrshrnt 0xee801f41
14580 #define M_MNEM_vqrshrnb 0xee800f41
14581 #define M_MNEM_vqrshrunt 0xfe801fc0
14582 #define M_MNEM_vqrshrunb 0xfe800fc0
14584 /* Bfloat16 instruction encoder helpers. */
14585 #define B_MNEM_vfmat 0xfc300850
14586 #define B_MNEM_vfmab 0xfc300810
14588 /* Neon instruction encoder helpers. */
14590 /* Encodings for the different types for various Neon opcodes. */
14592 /* An "invalid" code for the following tables. */
14595 struct neon_tab_entry
14598 unsigned float_or_poly
;
14599 unsigned scalar_or_imm
;
14602 /* Map overloaded Neon opcodes to their respective encodings. */
14603 #define NEON_ENC_TAB \
14604 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14605 X(vabdl, 0x0800700, N_INV, N_INV), \
14606 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14607 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14608 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14609 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14610 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14611 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14612 X(vaddl, 0x0800000, N_INV, N_INV), \
14613 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14614 X(vsubl, 0x0800200, N_INV, N_INV), \
14615 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14616 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14617 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14618 /* Register variants of the following two instructions are encoded as
14619 vcge / vcgt with the operands reversed. */ \
14620 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14621 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14622 X(vfma, N_INV, 0x0000c10, N_INV), \
14623 X(vfms, N_INV, 0x0200c10, N_INV), \
14624 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14625 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14626 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14627 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14628 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14629 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14630 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14631 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14632 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14633 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14634 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14635 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14636 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14637 X(vshl, 0x0000400, N_INV, 0x0800510), \
14638 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14639 X(vand, 0x0000110, N_INV, 0x0800030), \
14640 X(vbic, 0x0100110, N_INV, 0x0800030), \
14641 X(veor, 0x1000110, N_INV, N_INV), \
14642 X(vorn, 0x0300110, N_INV, 0x0800010), \
14643 X(vorr, 0x0200110, N_INV, 0x0800010), \
14644 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14645 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14646 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14647 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14648 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14649 X(vst1, 0x0000000, 0x0800000, N_INV), \
14650 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14651 X(vst2, 0x0000100, 0x0800100, N_INV), \
14652 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14653 X(vst3, 0x0000200, 0x0800200, N_INV), \
14654 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14655 X(vst4, 0x0000300, 0x0800300, N_INV), \
14656 X(vmovn, 0x1b20200, N_INV, N_INV), \
14657 X(vtrn, 0x1b20080, N_INV, N_INV), \
14658 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14659 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14660 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14661 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14662 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14663 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14664 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14665 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14666 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14667 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14668 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14669 X(vseleq, 0xe000a00, N_INV, N_INV), \
14670 X(vselvs, 0xe100a00, N_INV, N_INV), \
14671 X(vselge, 0xe200a00, N_INV, N_INV), \
14672 X(vselgt, 0xe300a00, N_INV, N_INV), \
14673 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14674 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14675 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14676 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14677 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14678 X(aes, 0x3b00300, N_INV, N_INV), \
14679 X(sha3op, 0x2000c00, N_INV, N_INV), \
14680 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14681 X(sha2op, 0x3ba0380, N_INV, N_INV)
14685 #define X(OPC,I,F,S) N_MNEM_##OPC
14690 static const struct neon_tab_entry neon_enc_tab
[] =
14692 #define X(OPC,I,F,S) { (I), (F), (S) }
14697 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14698 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14699 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14700 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14701 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14702 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14703 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14704 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14705 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14706 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14707 #define NEON_ENC_SINGLE_(X) \
14708 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14709 #define NEON_ENC_DOUBLE_(X) \
14710 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14711 #define NEON_ENC_FPV8_(X) \
14712 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14714 #define NEON_ENCODE(type, inst) \
14717 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14718 inst.is_neon = 1; \
14722 #define check_neon_suffixes \
14725 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14727 as_bad (_("invalid neon suffix for non neon instruction")); \
14733 /* Define shapes for instruction operands. The following mnemonic characters
14734 are used in this table:
14736 F - VFP S<n> register
14737 D - Neon D<n> register
14738 Q - Neon Q<n> register
14742 L - D<n> register list
14744 This table is used to generate various data:
14745 - enumerations of the form NS_DDR to be used as arguments to
14747 - a table classifying shapes into single, double, quad, mixed.
14748 - a table used to drive neon_select_shape. */
14750 #define NEON_SHAPE_DEF \
14751 X(4, (R, R, Q, Q), QUAD), \
14752 X(4, (Q, R, R, I), QUAD), \
14753 X(4, (R, R, S, S), QUAD), \
14754 X(4, (S, S, R, R), QUAD), \
14755 X(3, (Q, R, I), QUAD), \
14756 X(3, (I, Q, Q), QUAD), \
14757 X(3, (I, Q, R), QUAD), \
14758 X(3, (R, Q, Q), QUAD), \
14759 X(3, (D, D, D), DOUBLE), \
14760 X(3, (Q, Q, Q), QUAD), \
14761 X(3, (D, D, I), DOUBLE), \
14762 X(3, (Q, Q, I), QUAD), \
14763 X(3, (D, D, S), DOUBLE), \
14764 X(3, (Q, Q, S), QUAD), \
14765 X(3, (Q, Q, R), QUAD), \
14766 X(3, (R, R, Q), QUAD), \
14767 X(2, (R, Q), QUAD), \
14768 X(2, (D, D), DOUBLE), \
14769 X(2, (Q, Q), QUAD), \
14770 X(2, (D, S), DOUBLE), \
14771 X(2, (Q, S), QUAD), \
14772 X(2, (D, R), DOUBLE), \
14773 X(2, (Q, R), QUAD), \
14774 X(2, (D, I), DOUBLE), \
14775 X(2, (Q, I), QUAD), \
14776 X(3, (D, L, D), DOUBLE), \
14777 X(2, (D, Q), MIXED), \
14778 X(2, (Q, D), MIXED), \
14779 X(3, (D, Q, I), MIXED), \
14780 X(3, (Q, D, I), MIXED), \
14781 X(3, (Q, D, D), MIXED), \
14782 X(3, (D, Q, Q), MIXED), \
14783 X(3, (Q, Q, D), MIXED), \
14784 X(3, (Q, D, S), MIXED), \
14785 X(3, (D, Q, S), MIXED), \
14786 X(4, (D, D, D, I), DOUBLE), \
14787 X(4, (Q, Q, Q, I), QUAD), \
14788 X(4, (D, D, S, I), DOUBLE), \
14789 X(4, (Q, Q, S, I), QUAD), \
14790 X(2, (F, F), SINGLE), \
14791 X(3, (F, F, F), SINGLE), \
14792 X(2, (F, I), SINGLE), \
14793 X(2, (F, D), MIXED), \
14794 X(2, (D, F), MIXED), \
14795 X(3, (F, F, I), MIXED), \
14796 X(4, (R, R, F, F), SINGLE), \
14797 X(4, (F, F, R, R), SINGLE), \
14798 X(3, (D, R, R), DOUBLE), \
14799 X(3, (R, R, D), DOUBLE), \
14800 X(2, (S, R), SINGLE), \
14801 X(2, (R, S), SINGLE), \
14802 X(2, (F, R), SINGLE), \
14803 X(2, (R, F), SINGLE), \
14804 /* Used for MVE tail predicated loop instructions. */\
14805 X(2, (R, R), QUAD), \
14806 /* Half float shape supported so far. */\
14807 X (2, (H, D), MIXED), \
14808 X (2, (D, H), MIXED), \
14809 X (2, (H, F), MIXED), \
14810 X (2, (F, H), MIXED), \
14811 X (2, (H, H), HALF), \
14812 X (2, (H, R), HALF), \
14813 X (2, (R, H), HALF), \
14814 X (2, (H, I), HALF), \
14815 X (3, (H, H, H), HALF), \
14816 X (3, (H, F, I), MIXED), \
14817 X (3, (F, H, I), MIXED), \
14818 X (3, (D, H, H), MIXED), \
14819 X (3, (D, H, S), MIXED)
14821 #define S2(A,B) NS_##A##B
14822 #define S3(A,B,C) NS_##A##B##C
14823 #define S4(A,B,C,D) NS_##A##B##C##D
14825 #define X(N, L, C) S##N L
14838 enum neon_shape_class
14847 #define X(N, L, C) SC_##C
14849 static enum neon_shape_class neon_shape_class
[] =
14868 /* Register widths of above. */
14869 static unsigned neon_shape_el_size
[] =
14881 struct neon_shape_info
14884 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14887 #define S2(A,B) { SE_##A, SE_##B }
14888 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14889 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14891 #define X(N, L, C) { N, S##N L }
14893 static struct neon_shape_info neon_shape_tab
[] =
14903 /* Bit masks used in type checking given instructions.
14904 'N_EQK' means the type must be the same as (or based on in some way) the key
14905 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14906 set, various other bits can be set as well in order to modify the meaning of
14907 the type constraint. */
14909 enum neon_type_mask
14933 N_BF16
= 0x0400000,
14934 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14935 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14936 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14937 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14938 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14939 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14940 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14941 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14942 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14943 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14944 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14946 N_MAX_NONSPECIAL
= N_P64
14949 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14951 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14952 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14953 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14954 #define N_S_32 (N_S8 | N_S16 | N_S32)
14955 #define N_F_16_32 (N_F16 | N_F32)
14956 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14957 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14958 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14959 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14960 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14961 #define N_F_MVE (N_F16 | N_F32)
14962 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14964 /* Pass this as the first type argument to neon_check_type to ignore types
14966 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14968 /* Select a "shape" for the current instruction (describing register types or
14969 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14970 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14971 function of operand parsing, so this function doesn't need to be called.
14972 Shapes should be listed in order of decreasing length. */
14974 static enum neon_shape
14975 neon_select_shape (enum neon_shape shape
, ...)
14978 enum neon_shape first_shape
= shape
;
14980 /* Fix missing optional operands. FIXME: we don't know at this point how
14981 many arguments we should have, so this makes the assumption that we have
14982 > 1. This is true of all current Neon opcodes, I think, but may not be
14983 true in the future. */
14984 if (!inst
.operands
[1].present
)
14985 inst
.operands
[1] = inst
.operands
[0];
14987 va_start (ap
, shape
);
14989 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14994 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14996 if (!inst
.operands
[j
].present
)
15002 switch (neon_shape_tab
[shape
].el
[j
])
15004 /* If a .f16, .16, .u16, .s16 type specifier is given over
15005 a VFP single precision register operand, it's essentially
15006 means only half of the register is used.
15008 If the type specifier is given after the mnemonics, the
15009 information is stored in inst.vectype. If the type specifier
15010 is given after register operand, the information is stored
15011 in inst.operands[].vectype.
15013 When there is only one type specifier, and all the register
15014 operands are the same type of hardware register, the type
15015 specifier applies to all register operands.
15017 If no type specifier is given, the shape is inferred from
15018 operand information.
15021 vadd.f16 s0, s1, s2: NS_HHH
15022 vabs.f16 s0, s1: NS_HH
15023 vmov.f16 s0, r1: NS_HR
15024 vmov.f16 r0, s1: NS_RH
15025 vcvt.f16 r0, s1: NS_RH
15026 vcvt.f16.s32 s2, s2, #29: NS_HFI
15027 vcvt.f16.s32 s2, s2: NS_HF
15030 if (!(inst
.operands
[j
].isreg
15031 && inst
.operands
[j
].isvec
15032 && inst
.operands
[j
].issingle
15033 && !inst
.operands
[j
].isquad
15034 && ((inst
.vectype
.elems
== 1
15035 && inst
.vectype
.el
[0].size
== 16)
15036 || (inst
.vectype
.elems
> 1
15037 && inst
.vectype
.el
[j
].size
== 16)
15038 || (inst
.vectype
.elems
== 0
15039 && inst
.operands
[j
].vectype
.type
!= NT_invtype
15040 && inst
.operands
[j
].vectype
.size
== 16))))
15045 if (!(inst
.operands
[j
].isreg
15046 && inst
.operands
[j
].isvec
15047 && inst
.operands
[j
].issingle
15048 && !inst
.operands
[j
].isquad
15049 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
15050 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
15051 || (inst
.vectype
.elems
== 0
15052 && (inst
.operands
[j
].vectype
.size
== 32
15053 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
15058 if (!(inst
.operands
[j
].isreg
15059 && inst
.operands
[j
].isvec
15060 && !inst
.operands
[j
].isquad
15061 && !inst
.operands
[j
].issingle
))
15066 if (!(inst
.operands
[j
].isreg
15067 && !inst
.operands
[j
].isvec
))
15072 if (!(inst
.operands
[j
].isreg
15073 && inst
.operands
[j
].isvec
15074 && inst
.operands
[j
].isquad
15075 && !inst
.operands
[j
].issingle
))
15080 if (!(!inst
.operands
[j
].isreg
15081 && !inst
.operands
[j
].isscalar
))
15086 if (!(!inst
.operands
[j
].isreg
15087 && inst
.operands
[j
].isscalar
))
15097 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15098 /* We've matched all the entries in the shape table, and we don't
15099 have any left over operands which have not been matched. */
15105 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15106 first_error (_("invalid instruction shape"));
15111 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15112 means the Q bit should be set). */
15115 neon_quad (enum neon_shape shape
)
15117 return neon_shape_class
[shape
] == SC_QUAD
;
15121 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15124 /* Allow modification to be made to types which are constrained to be
15125 based on the key element, based on bits set alongside N_EQK. */
15126 if ((typebits
& N_EQK
) != 0)
15128 if ((typebits
& N_HLF
) != 0)
15130 else if ((typebits
& N_DBL
) != 0)
15132 if ((typebits
& N_SGN
) != 0)
15133 *g_type
= NT_signed
;
15134 else if ((typebits
& N_UNS
) != 0)
15135 *g_type
= NT_unsigned
;
15136 else if ((typebits
& N_INT
) != 0)
15137 *g_type
= NT_integer
;
15138 else if ((typebits
& N_FLT
) != 0)
15139 *g_type
= NT_float
;
15140 else if ((typebits
& N_SIZ
) != 0)
15141 *g_type
= NT_untyped
;
15145 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15146 operand type, i.e. the single type specified in a Neon instruction when it
15147 is the only one given. */
15149 static struct neon_type_el
15150 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15152 struct neon_type_el dest
= *key
;
15154 gas_assert ((thisarg
& N_EQK
) != 0);
15156 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15161 /* Convert Neon type and size into compact bitmask representation. */
15163 static enum neon_type_mask
15164 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15171 case 8: return N_8
;
15172 case 16: return N_16
;
15173 case 32: return N_32
;
15174 case 64: return N_64
;
15182 case 8: return N_I8
;
15183 case 16: return N_I16
;
15184 case 32: return N_I32
;
15185 case 64: return N_I64
;
15193 case 16: return N_F16
;
15194 case 32: return N_F32
;
15195 case 64: return N_F64
;
15203 case 8: return N_P8
;
15204 case 16: return N_P16
;
15205 case 64: return N_P64
;
15213 case 8: return N_S8
;
15214 case 16: return N_S16
;
15215 case 32: return N_S32
;
15216 case 64: return N_S64
;
15224 case 8: return N_U8
;
15225 case 16: return N_U16
;
15226 case 32: return N_U32
;
15227 case 64: return N_U64
;
15233 if (size
== 16) return N_BF16
;
15242 /* Convert compact Neon bitmask type representation to a type and size. Only
15243 handles the case where a single bit is set in the mask. */
15246 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15247 enum neon_type_mask mask
)
15249 if ((mask
& N_EQK
) != 0)
15252 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15254 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
| N_BF16
))
15257 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15259 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15264 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15266 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15267 *type
= NT_unsigned
;
15268 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15269 *type
= NT_integer
;
15270 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15271 *type
= NT_untyped
;
15272 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15274 else if ((mask
& (N_F_ALL
)) != 0)
15276 else if ((mask
& (N_BF16
)) != 0)
15284 /* Modify a bitmask of allowed types. This is only needed for type
15288 modify_types_allowed (unsigned allowed
, unsigned mods
)
15291 enum neon_el_type type
;
15297 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15299 if (el_type_of_type_chk (&type
, &size
,
15300 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15302 neon_modify_type_size (mods
, &type
, &size
);
15303 destmask
|= type_chk_of_el_type (type
, size
);
15310 /* Check type and return type classification.
15311 The manual states (paraphrase): If one datatype is given, it indicates the
15313 - the second operand, if there is one
15314 - the operand, if there is no second operand
15315 - the result, if there are no operands.
15316 This isn't quite good enough though, so we use a concept of a "key" datatype
15317 which is set on a per-instruction basis, which is the one which matters when
15318 only one data type is written.
15319 Note: this function has side-effects (e.g. filling in missing operands). All
15320 Neon instructions should call it before performing bit encoding. */
15322 static struct neon_type_el
15323 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15326 unsigned i
, pass
, key_el
= 0;
15327 unsigned types
[NEON_MAX_TYPE_ELS
];
15328 enum neon_el_type k_type
= NT_invtype
;
15329 unsigned k_size
= -1u;
15330 struct neon_type_el badtype
= {NT_invtype
, -1};
15331 unsigned key_allowed
= 0;
15333 /* Optional registers in Neon instructions are always (not) in operand 1.
15334 Fill in the missing operand here, if it was omitted. */
15335 if (els
> 1 && !inst
.operands
[1].present
)
15336 inst
.operands
[1] = inst
.operands
[0];
15338 /* Suck up all the varargs. */
15340 for (i
= 0; i
< els
; i
++)
15342 unsigned thisarg
= va_arg (ap
, unsigned);
15343 if (thisarg
== N_IGNORE_TYPE
)
15348 types
[i
] = thisarg
;
15349 if ((thisarg
& N_KEY
) != 0)
15354 if (inst
.vectype
.elems
> 0)
15355 for (i
= 0; i
< els
; i
++)
15356 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15358 first_error (_("types specified in both the mnemonic and operands"));
15362 /* Duplicate inst.vectype elements here as necessary.
15363 FIXME: No idea if this is exactly the same as the ARM assembler,
15364 particularly when an insn takes one register and one non-register
15366 if (inst
.vectype
.elems
== 1 && els
> 1)
15369 inst
.vectype
.elems
= els
;
15370 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15371 for (j
= 0; j
< els
; j
++)
15373 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15376 else if (inst
.vectype
.elems
== 0 && els
> 0)
15379 /* No types were given after the mnemonic, so look for types specified
15380 after each operand. We allow some flexibility here; as long as the
15381 "key" operand has a type, we can infer the others. */
15382 for (j
= 0; j
< els
; j
++)
15383 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15384 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15386 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15388 for (j
= 0; j
< els
; j
++)
15389 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15390 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15395 first_error (_("operand types can't be inferred"));
15399 else if (inst
.vectype
.elems
!= els
)
15401 first_error (_("type specifier has the wrong number of parts"));
15405 for (pass
= 0; pass
< 2; pass
++)
15407 for (i
= 0; i
< els
; i
++)
15409 unsigned thisarg
= types
[i
];
15410 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15411 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15412 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15413 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15415 /* Decay more-specific signed & unsigned types to sign-insensitive
15416 integer types if sign-specific variants are unavailable. */
15417 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15418 && (types_allowed
& N_SU_ALL
) == 0)
15419 g_type
= NT_integer
;
15421 /* If only untyped args are allowed, decay any more specific types to
15422 them. Some instructions only care about signs for some element
15423 sizes, so handle that properly. */
15424 if (((types_allowed
& N_UNT
) == 0)
15425 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15426 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15427 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15428 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15429 g_type
= NT_untyped
;
15433 if ((thisarg
& N_KEY
) != 0)
15437 key_allowed
= thisarg
& ~N_KEY
;
15439 /* Check architecture constraint on FP16 extension. */
15441 && k_type
== NT_float
15442 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15444 inst
.error
= _(BAD_FP16
);
15451 if ((thisarg
& N_VFP
) != 0)
15453 enum neon_shape_el regshape
;
15454 unsigned regwidth
, match
;
15456 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15459 first_error (_("invalid instruction shape"));
15462 regshape
= neon_shape_tab
[ns
].el
[i
];
15463 regwidth
= neon_shape_el_size
[regshape
];
15465 /* In VFP mode, operands must match register widths. If we
15466 have a key operand, use its width, else use the width of
15467 the current operand. */
15473 /* FP16 will use a single precision register. */
15474 if (regwidth
== 32 && match
== 16)
15476 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15480 inst
.error
= _(BAD_FP16
);
15485 if (regwidth
!= match
)
15487 first_error (_("operand size must match register width"));
15492 if ((thisarg
& N_EQK
) == 0)
15494 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15496 if ((given_type
& types_allowed
) == 0)
15498 first_error (BAD_SIMD_TYPE
);
15504 enum neon_el_type mod_k_type
= k_type
;
15505 unsigned mod_k_size
= k_size
;
15506 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15507 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15509 first_error (_("inconsistent types in Neon instruction"));
15517 return inst
.vectype
.el
[key_el
];
15520 /* Neon-style VFP instruction forwarding. */
15522 /* Thumb VFP instructions have 0xE in the condition field. */
15525 do_vfp_cond_or_thumb (void)
15530 inst
.instruction
|= 0xe0000000;
15532 inst
.instruction
|= inst
.cond
<< 28;
15535 /* Look up and encode a simple mnemonic, for use as a helper function for the
15536 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15537 etc. It is assumed that operand parsing has already been done, and that the
15538 operands are in the form expected by the given opcode (this isn't necessarily
15539 the same as the form in which they were parsed, hence some massaging must
15540 take place before this function is called).
15541 Checks current arch version against that in the looked-up opcode. */
15544 do_vfp_nsyn_opcode (const char *opname
)
15546 const struct asm_opcode
*opcode
;
15548 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15553 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15554 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15561 inst
.instruction
= opcode
->tvalue
;
15562 opcode
->tencode ();
15566 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15567 opcode
->aencode ();
15572 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15574 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15576 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15579 do_vfp_nsyn_opcode ("fadds");
15581 do_vfp_nsyn_opcode ("fsubs");
15583 /* ARMv8.2 fp16 instruction. */
15585 do_scalar_fp16_v82_encode ();
15590 do_vfp_nsyn_opcode ("faddd");
15592 do_vfp_nsyn_opcode ("fsubd");
15596 /* Check operand types to see if this is a VFP instruction, and if so call
15600 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15602 enum neon_shape rs
;
15603 struct neon_type_el et
;
15608 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15609 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15613 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15614 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15615 N_F_ALL
| N_KEY
| N_VFP
);
15622 if (et
.type
!= NT_invtype
)
15633 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15635 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15637 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15640 do_vfp_nsyn_opcode ("fmacs");
15642 do_vfp_nsyn_opcode ("fnmacs");
15644 /* ARMv8.2 fp16 instruction. */
15646 do_scalar_fp16_v82_encode ();
15651 do_vfp_nsyn_opcode ("fmacd");
15653 do_vfp_nsyn_opcode ("fnmacd");
15658 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15660 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15662 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15665 do_vfp_nsyn_opcode ("ffmas");
15667 do_vfp_nsyn_opcode ("ffnmas");
15669 /* ARMv8.2 fp16 instruction. */
15671 do_scalar_fp16_v82_encode ();
15676 do_vfp_nsyn_opcode ("ffmad");
15678 do_vfp_nsyn_opcode ("ffnmad");
15683 do_vfp_nsyn_mul (enum neon_shape rs
)
15685 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15687 do_vfp_nsyn_opcode ("fmuls");
15689 /* ARMv8.2 fp16 instruction. */
15691 do_scalar_fp16_v82_encode ();
15694 do_vfp_nsyn_opcode ("fmuld");
15698 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15700 int is_neg
= (inst
.instruction
& 0x80) != 0;
15701 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15703 if (rs
== NS_FF
|| rs
== NS_HH
)
15706 do_vfp_nsyn_opcode ("fnegs");
15708 do_vfp_nsyn_opcode ("fabss");
15710 /* ARMv8.2 fp16 instruction. */
15712 do_scalar_fp16_v82_encode ();
15717 do_vfp_nsyn_opcode ("fnegd");
15719 do_vfp_nsyn_opcode ("fabsd");
15723 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15724 insns belong to Neon, and are handled elsewhere. */
15727 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15729 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15733 do_vfp_nsyn_opcode ("fldmdbs");
15735 do_vfp_nsyn_opcode ("fldmias");
15740 do_vfp_nsyn_opcode ("fstmdbs");
15742 do_vfp_nsyn_opcode ("fstmias");
15747 do_vfp_nsyn_sqrt (void)
15749 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15750 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15752 if (rs
== NS_FF
|| rs
== NS_HH
)
15754 do_vfp_nsyn_opcode ("fsqrts");
15756 /* ARMv8.2 fp16 instruction. */
15758 do_scalar_fp16_v82_encode ();
15761 do_vfp_nsyn_opcode ("fsqrtd");
15765 do_vfp_nsyn_div (void)
15767 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15768 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15769 N_F_ALL
| N_KEY
| N_VFP
);
15771 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15773 do_vfp_nsyn_opcode ("fdivs");
15775 /* ARMv8.2 fp16 instruction. */
15777 do_scalar_fp16_v82_encode ();
15780 do_vfp_nsyn_opcode ("fdivd");
15784 do_vfp_nsyn_nmul (void)
15786 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15787 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15788 N_F_ALL
| N_KEY
| N_VFP
);
15790 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15792 NEON_ENCODE (SINGLE
, inst
);
15793 do_vfp_sp_dyadic ();
15795 /* ARMv8.2 fp16 instruction. */
15797 do_scalar_fp16_v82_encode ();
15801 NEON_ENCODE (DOUBLE
, inst
);
15802 do_vfp_dp_rd_rn_rm ();
15804 do_vfp_cond_or_thumb ();
15808 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15812 neon_logbits (unsigned x
)
15814 return ffs (x
) - 4;
15817 #define LOW4(R) ((R) & 0xf)
15818 #define HI1(R) (((R) >> 4) & 1)
15821 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15826 first_error (BAD_EL_TYPE
);
15829 switch (inst
.operands
[0].imm
)
15832 first_error (_("invalid condition"));
15854 /* only accept eq and ne. */
15855 if (inst
.operands
[0].imm
> 1)
15857 first_error (_("invalid condition"));
15860 return inst
.operands
[0].imm
;
15862 if (inst
.operands
[0].imm
== 0x2)
15864 else if (inst
.operands
[0].imm
== 0x8)
15868 first_error (_("invalid condition"));
15872 switch (inst
.operands
[0].imm
)
15875 first_error (_("invalid condition"));
15891 /* Should be unreachable. */
15895 /* For VCTP (create vector tail predicate) in MVE. */
15900 unsigned size
= 0x0;
15902 if (inst
.cond
> COND_ALWAYS
)
15903 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15905 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15907 /* This is a typical MVE instruction which has no type but have size 8, 16,
15908 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15909 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15910 if ((inst
.operands
[0].present
) && (inst
.vectype
.el
[0].type
== NT_untyped
))
15911 dt
= inst
.vectype
.el
[0].size
;
15913 /* Setting this does not indicate an actual NEON instruction, but only
15914 indicates that the mnemonic accepts neon-style type suffixes. */
15928 first_error (_("Type is not allowed for this instruction"));
15930 inst
.instruction
|= size
<< 20;
15931 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15937 /* We are dealing with a vector predicated block. */
15938 if (inst
.operands
[0].present
)
15940 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15941 struct neon_type_el et
15942 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15945 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15947 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15949 if (et
.type
== NT_invtype
)
15952 if (et
.type
== NT_float
)
15954 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15956 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15957 inst
.instruction
|= (et
.size
== 16) << 28;
15958 inst
.instruction
|= 0x3 << 20;
15962 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15964 inst
.instruction
|= 1 << 28;
15965 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15968 if (inst
.operands
[2].isquad
)
15970 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15971 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15972 inst
.instruction
|= (fcond
& 0x2) >> 1;
15976 if (inst
.operands
[2].reg
== REG_SP
)
15977 as_tsktsk (MVE_BAD_SP
);
15978 inst
.instruction
|= 1 << 6;
15979 inst
.instruction
|= (fcond
& 0x2) << 4;
15980 inst
.instruction
|= inst
.operands
[2].reg
;
15982 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15983 inst
.instruction
|= (fcond
& 0x4) << 10;
15984 inst
.instruction
|= (fcond
& 0x1) << 7;
15987 set_pred_insn_type (VPT_INSN
);
15989 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15990 | ((inst
.instruction
& 0xe000) >> 13);
15991 now_pred
.warn_deprecated
= FALSE
;
15992 now_pred
.type
= VECTOR_PRED
;
15999 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
16000 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
16001 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
16002 if (!inst
.operands
[2].present
)
16003 first_error (_("MVE vector or ARM register expected"));
16004 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16006 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
16007 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
16008 && inst
.operands
[1].isquad
)
16010 inst
.instruction
= N_MNEM_vcmp
;
16014 if (inst
.cond
> COND_ALWAYS
)
16015 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16017 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16019 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16020 struct neon_type_el et
16021 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16024 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
16025 && !inst
.operands
[2].iszr
, BAD_PC
);
16027 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16029 inst
.instruction
= 0xee010f00;
16030 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16031 inst
.instruction
|= (fcond
& 0x4) << 10;
16032 inst
.instruction
|= (fcond
& 0x1) << 7;
16033 if (et
.type
== NT_float
)
16035 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16037 inst
.instruction
|= (et
.size
== 16) << 28;
16038 inst
.instruction
|= 0x3 << 20;
16042 inst
.instruction
|= 1 << 28;
16043 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16045 if (inst
.operands
[2].isquad
)
16047 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16048 inst
.instruction
|= (fcond
& 0x2) >> 1;
16049 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16053 if (inst
.operands
[2].reg
== REG_SP
)
16054 as_tsktsk (MVE_BAD_SP
);
16055 inst
.instruction
|= 1 << 6;
16056 inst
.instruction
|= (fcond
& 0x2) << 4;
16057 inst
.instruction
|= inst
.operands
[2].reg
;
16065 do_mve_vmaxa_vmina (void)
16067 if (inst
.cond
> COND_ALWAYS
)
16068 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16070 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16072 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16073 struct neon_type_el et
16074 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
16076 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16077 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16078 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16079 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16080 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16085 do_mve_vfmas (void)
16087 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16088 struct neon_type_el et
16089 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
16091 if (inst
.cond
> COND_ALWAYS
)
16092 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16094 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16096 if (inst
.operands
[2].reg
== REG_SP
)
16097 as_tsktsk (MVE_BAD_SP
);
16098 else if (inst
.operands
[2].reg
== REG_PC
)
16099 as_tsktsk (MVE_BAD_PC
);
16101 inst
.instruction
|= (et
.size
== 16) << 28;
16102 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16103 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16104 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16105 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16106 inst
.instruction
|= inst
.operands
[2].reg
;
16111 do_mve_viddup (void)
16113 if (inst
.cond
> COND_ALWAYS
)
16114 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16116 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16118 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
16119 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
16120 _("immediate must be either 1, 2, 4 or 8"));
16122 enum neon_shape rs
;
16123 struct neon_type_el et
;
16125 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
16127 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
16128 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
16133 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
16134 if (inst
.operands
[2].reg
== REG_SP
)
16135 as_tsktsk (MVE_BAD_SP
);
16136 else if (inst
.operands
[2].reg
== REG_PC
)
16137 first_error (BAD_PC
);
16139 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16140 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16141 Rm
= inst
.operands
[2].reg
>> 1;
16143 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16144 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16145 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16146 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16147 inst
.instruction
|= (imm
> 2) << 7;
16148 inst
.instruction
|= Rm
<< 1;
16149 inst
.instruction
|= (imm
== 2 || imm
== 8);
16154 do_mve_vmlas (void)
16156 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16157 struct neon_type_el et
16158 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16160 if (inst
.operands
[2].reg
== REG_PC
)
16161 as_tsktsk (MVE_BAD_PC
);
16162 else if (inst
.operands
[2].reg
== REG_SP
)
16163 as_tsktsk (MVE_BAD_SP
);
16165 if (inst
.cond
> COND_ALWAYS
)
16166 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16168 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16170 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16171 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16172 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16173 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16174 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16175 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16176 inst
.instruction
|= inst
.operands
[2].reg
;
16181 do_mve_vshll (void)
16183 struct neon_type_el et
16184 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16186 if (inst
.cond
> COND_ALWAYS
)
16187 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16189 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16191 int imm
= inst
.operands
[2].imm
;
16192 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16193 _("immediate value out of range"));
16195 if ((unsigned)imm
== et
.size
)
16197 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16198 inst
.instruction
|= 0x110001;
16202 inst
.instruction
|= (et
.size
+ imm
) << 16;
16203 inst
.instruction
|= 0x800140;
16206 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16207 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16208 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16209 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16210 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16215 do_mve_vshlc (void)
16217 if (inst
.cond
> COND_ALWAYS
)
16218 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16220 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16222 if (inst
.operands
[1].reg
== REG_PC
)
16223 as_tsktsk (MVE_BAD_PC
);
16224 else if (inst
.operands
[1].reg
== REG_SP
)
16225 as_tsktsk (MVE_BAD_SP
);
16227 int imm
= inst
.operands
[2].imm
;
16228 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16230 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16231 inst
.instruction
|= (imm
& 0x1f) << 16;
16232 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16233 inst
.instruction
|= inst
.operands
[1].reg
;
16238 do_mve_vshrn (void)
16241 switch (inst
.instruction
)
16243 case M_MNEM_vshrnt
:
16244 case M_MNEM_vshrnb
:
16245 case M_MNEM_vrshrnt
:
16246 case M_MNEM_vrshrnb
:
16247 types
= N_I16
| N_I32
;
16249 case M_MNEM_vqshrnt
:
16250 case M_MNEM_vqshrnb
:
16251 case M_MNEM_vqrshrnt
:
16252 case M_MNEM_vqrshrnb
:
16253 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16255 case M_MNEM_vqshrunt
:
16256 case M_MNEM_vqshrunb
:
16257 case M_MNEM_vqrshrunt
:
16258 case M_MNEM_vqrshrunb
:
16259 types
= N_S16
| N_S32
;
16265 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16267 if (inst
.cond
> COND_ALWAYS
)
16268 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16270 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16272 unsigned Qd
= inst
.operands
[0].reg
;
16273 unsigned Qm
= inst
.operands
[1].reg
;
16274 unsigned imm
= inst
.operands
[2].imm
;
16275 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16277 ? _("immediate operand expected in the range [1,8]")
16278 : _("immediate operand expected in the range [1,16]"));
16280 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16281 inst
.instruction
|= HI1 (Qd
) << 22;
16282 inst
.instruction
|= (et
.size
- imm
) << 16;
16283 inst
.instruction
|= LOW4 (Qd
) << 12;
16284 inst
.instruction
|= HI1 (Qm
) << 5;
16285 inst
.instruction
|= LOW4 (Qm
);
16290 do_mve_vqmovn (void)
16292 struct neon_type_el et
;
16293 if (inst
.instruction
== M_MNEM_vqmovnt
16294 || inst
.instruction
== M_MNEM_vqmovnb
)
16295 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16296 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16298 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16300 if (inst
.cond
> COND_ALWAYS
)
16301 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16303 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16305 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16306 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16307 inst
.instruction
|= (et
.size
== 32) << 18;
16308 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16309 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16310 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16315 do_mve_vpsel (void)
16317 neon_select_shape (NS_QQQ
, NS_NULL
);
16319 if (inst
.cond
> COND_ALWAYS
)
16320 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16322 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16324 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16325 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16326 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16327 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16328 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16329 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16334 do_mve_vpnot (void)
16336 if (inst
.cond
> COND_ALWAYS
)
16337 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16339 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16343 do_mve_vmaxnma_vminnma (void)
16345 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16346 struct neon_type_el et
16347 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16349 if (inst
.cond
> COND_ALWAYS
)
16350 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16352 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16354 inst
.instruction
|= (et
.size
== 16) << 28;
16355 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16356 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16357 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16358 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16363 do_mve_vcmul (void)
16365 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16366 struct neon_type_el et
16367 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16369 if (inst
.cond
> COND_ALWAYS
)
16370 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16372 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16374 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16375 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16376 _("immediate out of range"));
16378 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16379 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16380 as_tsktsk (BAD_MVE_SRCDEST
);
16382 inst
.instruction
|= (et
.size
== 32) << 28;
16383 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16384 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16385 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16386 inst
.instruction
|= (rot
> 90) << 12;
16387 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16388 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16389 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16390 inst
.instruction
|= (rot
== 90 || rot
== 270);
16394 /* To handle the Low Overhead Loop instructions
16395 in Armv8.1-M Mainline and MVE. */
16399 unsigned long insn
= inst
.instruction
;
16401 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16403 if (insn
== T_MNEM_lctp
)
16406 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16408 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16410 struct neon_type_el et
16411 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16412 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16419 constraint (!inst
.operands
[0].present
,
16421 /* fall through. */
16424 if (!inst
.operands
[0].present
)
16425 inst
.instruction
|= 1 << 21;
16427 v8_1_loop_reloc (TRUE
);
16432 v8_1_loop_reloc (FALSE
);
16433 /* fall through. */
16436 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16438 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16439 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16440 else if (inst
.operands
[1].reg
== REG_PC
)
16441 as_tsktsk (MVE_BAD_PC
);
16442 if (inst
.operands
[1].reg
== REG_SP
)
16443 as_tsktsk (MVE_BAD_SP
);
16445 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16455 do_vfp_nsyn_cmp (void)
16457 enum neon_shape rs
;
16458 if (!inst
.operands
[0].isreg
)
16465 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16466 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16470 if (inst
.operands
[1].isreg
)
16472 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16473 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16475 if (rs
== NS_FF
|| rs
== NS_HH
)
16477 NEON_ENCODE (SINGLE
, inst
);
16478 do_vfp_sp_monadic ();
16482 NEON_ENCODE (DOUBLE
, inst
);
16483 do_vfp_dp_rd_rm ();
16488 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16489 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16491 switch (inst
.instruction
& 0x0fffffff)
16494 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16497 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16503 if (rs
== NS_FI
|| rs
== NS_HI
)
16505 NEON_ENCODE (SINGLE
, inst
);
16506 do_vfp_sp_compare_z ();
16510 NEON_ENCODE (DOUBLE
, inst
);
16514 do_vfp_cond_or_thumb ();
16516 /* ARMv8.2 fp16 instruction. */
16517 if (rs
== NS_HI
|| rs
== NS_HH
)
16518 do_scalar_fp16_v82_encode ();
16522 nsyn_insert_sp (void)
16524 inst
.operands
[1] = inst
.operands
[0];
16525 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16526 inst
.operands
[0].reg
= REG_SP
;
16527 inst
.operands
[0].isreg
= 1;
16528 inst
.operands
[0].writeback
= 1;
16529 inst
.operands
[0].present
= 1;
16533 do_vfp_nsyn_push (void)
16537 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16538 _("register list must contain at least 1 and at most 16 "
16541 if (inst
.operands
[1].issingle
)
16542 do_vfp_nsyn_opcode ("fstmdbs");
16544 do_vfp_nsyn_opcode ("fstmdbd");
16548 do_vfp_nsyn_pop (void)
16552 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16553 _("register list must contain at least 1 and at most 16 "
16556 if (inst
.operands
[1].issingle
)
16557 do_vfp_nsyn_opcode ("fldmias");
16559 do_vfp_nsyn_opcode ("fldmiad");
16562 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16563 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16566 neon_dp_fixup (struct arm_it
* insn
)
16568 unsigned int i
= insn
->instruction
;
16573 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16584 insn
->instruction
= i
;
16588 mve_encode_qqr (int size
, int U
, int fp
)
16590 if (inst
.operands
[2].reg
== REG_SP
)
16591 as_tsktsk (MVE_BAD_SP
);
16592 else if (inst
.operands
[2].reg
== REG_PC
)
16593 as_tsktsk (MVE_BAD_PC
);
16598 if (((unsigned)inst
.instruction
) == 0xd00)
16599 inst
.instruction
= 0xee300f40;
16601 else if (((unsigned)inst
.instruction
) == 0x200d00)
16602 inst
.instruction
= 0xee301f40;
16604 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16605 inst
.instruction
= 0xee310e60;
16607 /* Setting size which is 1 for F16 and 0 for F32. */
16608 inst
.instruction
|= (size
== 16) << 28;
16613 if (((unsigned)inst
.instruction
) == 0x800)
16614 inst
.instruction
= 0xee010f40;
16616 else if (((unsigned)inst
.instruction
) == 0x1000800)
16617 inst
.instruction
= 0xee011f40;
16619 else if (((unsigned)inst
.instruction
) == 0)
16620 inst
.instruction
= 0xee000f40;
16622 else if (((unsigned)inst
.instruction
) == 0x200)
16623 inst
.instruction
= 0xee001f40;
16625 else if (((unsigned)inst
.instruction
) == 0x900)
16626 inst
.instruction
= 0xee010e40;
16628 else if (((unsigned)inst
.instruction
) == 0x910)
16629 inst
.instruction
= 0xee011e60;
16631 else if (((unsigned)inst
.instruction
) == 0x10)
16632 inst
.instruction
= 0xee000f60;
16634 else if (((unsigned)inst
.instruction
) == 0x210)
16635 inst
.instruction
= 0xee001f60;
16637 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16638 inst
.instruction
= 0xee000e40;
16640 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16641 inst
.instruction
= 0xee010e60;
16643 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16644 inst
.instruction
= 0xfe010e60;
16647 inst
.instruction
|= U
<< 28;
16649 /* Setting bits for size. */
16650 inst
.instruction
|= neon_logbits (size
) << 20;
16652 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16653 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16654 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16655 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16656 inst
.instruction
|= inst
.operands
[2].reg
;
16661 mve_encode_rqq (unsigned bit28
, unsigned size
)
16663 inst
.instruction
|= bit28
<< 28;
16664 inst
.instruction
|= neon_logbits (size
) << 20;
16665 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16666 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16667 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16668 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16669 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16674 mve_encode_qqq (int ubit
, int size
)
16677 inst
.instruction
|= (ubit
!= 0) << 28;
16678 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16679 inst
.instruction
|= neon_logbits (size
) << 20;
16680 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16681 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16682 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16683 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16684 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16690 mve_encode_rq (unsigned bit28
, unsigned size
)
16692 inst
.instruction
|= bit28
<< 28;
16693 inst
.instruction
|= neon_logbits (size
) << 18;
16694 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16695 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16700 mve_encode_rrqq (unsigned U
, unsigned size
)
16702 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16704 inst
.instruction
|= U
<< 28;
16705 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16706 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16707 inst
.instruction
|= (size
== 32) << 16;
16708 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16709 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16710 inst
.instruction
|= inst
.operands
[3].reg
;
16714 /* Helper function for neon_three_same handling the operands. */
16716 neon_three_args (int isquad
)
16718 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16719 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16720 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16721 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16722 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16723 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16724 inst
.instruction
|= (isquad
!= 0) << 6;
16728 /* Encode insns with bit pattern:
16730 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16731 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16733 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16734 different meaning for some instruction. */
16737 neon_three_same (int isquad
, int ubit
, int size
)
16739 neon_three_args (isquad
);
16740 inst
.instruction
|= (ubit
!= 0) << 24;
16742 inst
.instruction
|= neon_logbits (size
) << 20;
16744 neon_dp_fixup (&inst
);
16747 /* Encode instructions of the form:
16749 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16750 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16752 Don't write size if SIZE == -1. */
16755 neon_two_same (int qbit
, int ubit
, int size
)
16757 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16758 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16759 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16760 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16761 inst
.instruction
|= (qbit
!= 0) << 6;
16762 inst
.instruction
|= (ubit
!= 0) << 24;
16765 inst
.instruction
|= neon_logbits (size
) << 18;
16767 neon_dp_fixup (&inst
);
16770 enum vfp_or_neon_is_neon_bits
16773 NEON_CHECK_ARCH
= 2,
16774 NEON_CHECK_ARCH8
= 4
16777 /* Call this function if an instruction which may have belonged to the VFP or
16778 Neon instruction sets, but turned out to be a Neon instruction (due to the
16779 operand types involved, etc.). We have to check and/or fix-up a couple of
16782 - Make sure the user hasn't attempted to make a Neon instruction
16784 - Alter the value in the condition code field if necessary.
16785 - Make sure that the arch supports Neon instructions.
16787 Which of these operations take place depends on bits from enum
16788 vfp_or_neon_is_neon_bits.
16790 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16791 current instruction's condition is COND_ALWAYS, the condition field is
16792 changed to inst.uncond_value. This is necessary because instructions shared
16793 between VFP and Neon may be conditional for the VFP variants only, and the
16794 unconditional Neon version must have, e.g., 0xF in the condition field. */
16797 vfp_or_neon_is_neon (unsigned check
)
16799 /* Conditions are always legal in Thumb mode (IT blocks). */
16800 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16802 if (inst
.cond
!= COND_ALWAYS
)
16804 first_error (_(BAD_COND
));
16807 if (inst
.uncond_value
!= -1)
16808 inst
.instruction
|= inst
.uncond_value
<< 28;
16812 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16813 || ((check
& NEON_CHECK_ARCH8
)
16814 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16816 first_error (_(BAD_FPU
));
16824 /* Return TRUE if the SIMD instruction is available for the current
16825 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16826 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16827 vfp_or_neon_is_neon for the NEON specific checks. */
16830 check_simd_pred_availability (int fp
, unsigned check
)
16832 if (inst
.cond
> COND_ALWAYS
)
16834 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16836 inst
.error
= BAD_FPU
;
16839 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16841 else if (inst
.cond
< COND_ALWAYS
)
16843 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16844 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16845 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16850 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16851 && vfp_or_neon_is_neon (check
) == FAIL
)
16854 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16855 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16860 /* Neon instruction encoders, in approximate order of appearance. */
16863 do_neon_dyadic_i_su (void)
16865 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16868 enum neon_shape rs
;
16869 struct neon_type_el et
;
16870 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16871 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16873 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16875 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16879 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16881 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16885 do_neon_dyadic_i64_su (void)
16887 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16889 enum neon_shape rs
;
16890 struct neon_type_el et
;
16891 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16893 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16894 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16898 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16899 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16902 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16904 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16908 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16911 unsigned size
= et
.size
>> 3;
16912 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16913 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16914 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16915 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16916 inst
.instruction
|= (isquad
!= 0) << 6;
16917 inst
.instruction
|= immbits
<< 16;
16918 inst
.instruction
|= (size
>> 3) << 7;
16919 inst
.instruction
|= (size
& 0x7) << 19;
16921 inst
.instruction
|= (uval
!= 0) << 24;
16923 neon_dp_fixup (&inst
);
16929 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16932 if (!inst
.operands
[2].isreg
)
16934 enum neon_shape rs
;
16935 struct neon_type_el et
;
16936 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16938 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16939 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16943 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16944 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16946 int imm
= inst
.operands
[2].imm
;
16948 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16949 _("immediate out of range for shift"));
16950 NEON_ENCODE (IMMED
, inst
);
16951 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16955 enum neon_shape rs
;
16956 struct neon_type_el et
;
16957 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16959 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16960 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16964 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16965 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16971 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16972 _("invalid instruction shape"));
16973 if (inst
.operands
[2].reg
== REG_SP
)
16974 as_tsktsk (MVE_BAD_SP
);
16975 else if (inst
.operands
[2].reg
== REG_PC
)
16976 as_tsktsk (MVE_BAD_PC
);
16978 inst
.instruction
= 0xee311e60;
16979 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16980 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16981 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16982 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16983 inst
.instruction
|= inst
.operands
[2].reg
;
16990 /* VSHL/VQSHL 3-register variants have syntax such as:
16992 whereas other 3-register operations encoded by neon_three_same have
16995 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16996 operands[2].reg here. */
16997 tmp
= inst
.operands
[2].reg
;
16998 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16999 inst
.operands
[1].reg
= tmp
;
17000 NEON_ENCODE (INTEGER
, inst
);
17001 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17007 do_neon_qshl (void)
17009 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17012 if (!inst
.operands
[2].isreg
)
17014 enum neon_shape rs
;
17015 struct neon_type_el et
;
17016 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17018 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
17019 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
17023 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17024 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
17026 int imm
= inst
.operands
[2].imm
;
17028 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17029 _("immediate out of range for shift"));
17030 NEON_ENCODE (IMMED
, inst
);
17031 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
17035 enum neon_shape rs
;
17036 struct neon_type_el et
;
17038 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17040 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17041 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
17045 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17046 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17051 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17052 _("invalid instruction shape"));
17053 if (inst
.operands
[2].reg
== REG_SP
)
17054 as_tsktsk (MVE_BAD_SP
);
17055 else if (inst
.operands
[2].reg
== REG_PC
)
17056 as_tsktsk (MVE_BAD_PC
);
17058 inst
.instruction
= 0xee311ee0;
17059 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17060 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17061 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17062 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17063 inst
.instruction
|= inst
.operands
[2].reg
;
17070 /* See note in do_neon_shl. */
17071 tmp
= inst
.operands
[2].reg
;
17072 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17073 inst
.operands
[1].reg
= tmp
;
17074 NEON_ENCODE (INTEGER
, inst
);
17075 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17081 do_neon_rshl (void)
17083 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17086 enum neon_shape rs
;
17087 struct neon_type_el et
;
17088 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17090 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17091 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17095 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17096 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
17103 if (inst
.operands
[2].reg
== REG_PC
)
17104 as_tsktsk (MVE_BAD_PC
);
17105 else if (inst
.operands
[2].reg
== REG_SP
)
17106 as_tsktsk (MVE_BAD_SP
);
17108 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17109 _("invalid instruction shape"));
17111 if (inst
.instruction
== 0x0000510)
17112 /* We are dealing with vqrshl. */
17113 inst
.instruction
= 0xee331ee0;
17115 /* We are dealing with vrshl. */
17116 inst
.instruction
= 0xee331e60;
17118 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17119 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17120 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17121 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17122 inst
.instruction
|= inst
.operands
[2].reg
;
17127 tmp
= inst
.operands
[2].reg
;
17128 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17129 inst
.operands
[1].reg
= tmp
;
17130 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17135 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
17137 /* Handle .I8 pseudo-instructions. */
17140 /* Unfortunately, this will make everything apart from zero out-of-range.
17141 FIXME is this the intended semantics? There doesn't seem much point in
17142 accepting .I8 if so. */
17143 immediate
|= immediate
<< 8;
17149 if (immediate
== (immediate
& 0x000000ff))
17151 *immbits
= immediate
;
17154 else if (immediate
== (immediate
& 0x0000ff00))
17156 *immbits
= immediate
>> 8;
17159 else if (immediate
== (immediate
& 0x00ff0000))
17161 *immbits
= immediate
>> 16;
17164 else if (immediate
== (immediate
& 0xff000000))
17166 *immbits
= immediate
>> 24;
17169 if ((immediate
& 0xffff) != (immediate
>> 16))
17170 goto bad_immediate
;
17171 immediate
&= 0xffff;
17174 if (immediate
== (immediate
& 0x000000ff))
17176 *immbits
= immediate
;
17179 else if (immediate
== (immediate
& 0x0000ff00))
17181 *immbits
= immediate
>> 8;
17186 first_error (_("immediate value out of range"));
17191 do_neon_logic (void)
17193 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17195 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17197 && !check_simd_pred_availability (FALSE
,
17198 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17200 else if (rs
!= NS_QQQ
17201 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17202 first_error (BAD_FPU
);
17204 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17205 /* U bit and size field were set as part of the bitmask. */
17206 NEON_ENCODE (INTEGER
, inst
);
17207 neon_three_same (neon_quad (rs
), 0, -1);
17211 const int three_ops_form
= (inst
.operands
[2].present
17212 && !inst
.operands
[2].isreg
);
17213 const int immoperand
= (three_ops_form
? 2 : 1);
17214 enum neon_shape rs
= (three_ops_form
17215 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17216 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17217 /* Because neon_select_shape makes the second operand a copy of the first
17218 if the second operand is not present. */
17220 && !check_simd_pred_availability (FALSE
,
17221 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17223 else if (rs
!= NS_QQI
17224 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17225 first_error (BAD_FPU
);
17227 struct neon_type_el et
;
17228 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17229 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17231 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17234 if (et
.type
== NT_invtype
)
17236 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17241 if (three_ops_form
)
17242 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17243 _("first and second operands shall be the same register"));
17245 NEON_ENCODE (IMMED
, inst
);
17247 immbits
= inst
.operands
[immoperand
].imm
;
17250 /* .i64 is a pseudo-op, so the immediate must be a repeating
17252 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17253 inst
.operands
[immoperand
].reg
: 0))
17255 /* Set immbits to an invalid constant. */
17256 immbits
= 0xdeadbeef;
17263 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17267 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17271 /* Pseudo-instruction for VBIC. */
17272 neon_invert_size (&immbits
, 0, et
.size
);
17273 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17277 /* Pseudo-instruction for VORR. */
17278 neon_invert_size (&immbits
, 0, et
.size
);
17279 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17289 inst
.instruction
|= neon_quad (rs
) << 6;
17290 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17291 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17292 inst
.instruction
|= cmode
<< 8;
17293 neon_write_immbits (immbits
);
17295 neon_dp_fixup (&inst
);
17300 do_neon_bitfield (void)
17302 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17303 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17304 neon_three_same (neon_quad (rs
), 0, -1);
17308 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17311 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17312 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17314 if (et
.type
== NT_float
)
17316 NEON_ENCODE (FLOAT
, inst
);
17318 mve_encode_qqr (et
.size
, 0, 1);
17320 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17324 NEON_ENCODE (INTEGER
, inst
);
17326 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17328 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17334 do_neon_dyadic_if_su_d (void)
17336 /* This version only allow D registers, but that constraint is enforced during
17337 operand parsing so we don't need to do anything extra here. */
17338 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17342 do_neon_dyadic_if_i_d (void)
17344 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17345 affected if we specify unsigned args. */
17346 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17350 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17352 constraint (size
< 32, BAD_ADDR_MODE
);
17353 constraint (size
!= elsize
, BAD_EL_TYPE
);
17354 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17355 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17356 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17357 _("destination register and offset register may not be the"
17360 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17367 constraint ((imm
% (size
/ 8) != 0)
17368 || imm
> (0x7f << neon_logbits (size
)),
17369 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17370 " range of +/-[0,508]")
17371 : _("immediate must be a multiple of 8 in the"
17372 " range of +/-[0,1016]"));
17373 inst
.instruction
|= 0x11 << 24;
17374 inst
.instruction
|= add
<< 23;
17375 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17376 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17377 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17378 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17379 inst
.instruction
|= 1 << 12;
17380 inst
.instruction
|= (size
== 64) << 8;
17381 inst
.instruction
&= 0xffffff00;
17382 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17383 inst
.instruction
|= imm
>> neon_logbits (size
);
17387 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17389 unsigned os
= inst
.operands
[1].imm
>> 5;
17390 unsigned type
= inst
.vectype
.el
[0].type
;
17391 constraint (os
!= 0 && size
== 8,
17392 _("can not shift offsets when accessing less than half-word"));
17393 constraint (os
&& os
!= neon_logbits (size
),
17394 _("shift immediate must be 1, 2 or 3 for half-word, word"
17395 " or double-word accesses respectively"));
17396 if (inst
.operands
[1].reg
== REG_PC
)
17397 as_tsktsk (MVE_BAD_PC
);
17402 constraint (elsize
>= 64, BAD_EL_TYPE
);
17405 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17409 constraint (elsize
!= size
, BAD_EL_TYPE
);
17414 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17418 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17419 _("destination register and offset register may not be"
17421 constraint (size
== elsize
&& type
== NT_signed
, BAD_EL_TYPE
);
17422 constraint (size
!= elsize
&& type
!= NT_unsigned
&& type
!= NT_signed
,
17424 inst
.instruction
|= ((size
== elsize
) || (type
== NT_unsigned
)) << 28;
17428 constraint (type
!= NT_untyped
, BAD_EL_TYPE
);
17431 inst
.instruction
|= 1 << 23;
17432 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17433 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17434 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17435 inst
.instruction
|= neon_logbits (elsize
) << 7;
17436 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17437 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17438 inst
.instruction
|= !!os
;
17442 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17444 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17446 constraint (size
>= 64, BAD_ADDR_MODE
);
17450 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17453 constraint (elsize
!= size
, BAD_EL_TYPE
);
17460 constraint (elsize
!= size
&& type
!= NT_unsigned
17461 && type
!= NT_signed
, BAD_EL_TYPE
);
17465 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17468 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17476 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17481 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17484 constraint (1, _("immediate must be a multiple of 2 in the"
17485 " range of +/-[0,254]"));
17488 constraint (1, _("immediate must be a multiple of 4 in the"
17489 " range of +/-[0,508]"));
17494 if (size
!= elsize
)
17496 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17497 constraint (inst
.operands
[0].reg
> 14,
17498 _("MVE vector register in the range [Q0..Q7] expected"));
17499 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17500 inst
.instruction
|= (size
== 16) << 19;
17501 inst
.instruction
|= neon_logbits (elsize
) << 7;
17505 if (inst
.operands
[1].reg
== REG_PC
)
17506 as_tsktsk (MVE_BAD_PC
);
17507 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17508 as_tsktsk (MVE_BAD_SP
);
17509 inst
.instruction
|= 1 << 12;
17510 inst
.instruction
|= neon_logbits (size
) << 7;
17512 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17513 inst
.instruction
|= add
<< 23;
17514 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17515 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17516 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17517 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17518 inst
.instruction
&= 0xffffff80;
17519 inst
.instruction
|= imm
>> neon_logbits (size
);
17524 do_mve_vstr_vldr (void)
17529 if (inst
.cond
> COND_ALWAYS
)
17530 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17532 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17534 switch (inst
.instruction
)
17541 /* fall through. */
17547 /* fall through. */
17553 /* fall through. */
17559 /* fall through. */
17564 unsigned elsize
= inst
.vectype
.el
[0].size
;
17566 if (inst
.operands
[1].isquad
)
17568 /* We are dealing with [Q, imm]{!} cases. */
17569 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17573 if (inst
.operands
[1].immisreg
== 2)
17575 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17576 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17578 else if (!inst
.operands
[1].immisreg
)
17580 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17581 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17584 constraint (1, BAD_ADDR_MODE
);
17591 do_mve_vst_vld (void)
17593 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17596 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17597 || inst
.relocs
[0].exp
.X_add_number
!= 0
17598 || inst
.operands
[1].immisreg
!= 0,
17600 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17601 if (inst
.operands
[1].reg
== REG_PC
)
17602 as_tsktsk (MVE_BAD_PC
);
17603 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17604 as_tsktsk (MVE_BAD_SP
);
17607 /* These instructions are one of the "exceptions" mentioned in
17608 handle_pred_state. They are MVE instructions that are not VPT compatible
17609 and do not accept a VPT code, thus appending such a code is a syntax
17611 if (inst
.cond
> COND_ALWAYS
)
17612 first_error (BAD_SYNTAX
);
17613 /* If we append a scalar condition code we can set this to
17614 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17615 else if (inst
.cond
< COND_ALWAYS
)
17616 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17618 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17620 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17621 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17622 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17623 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17624 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17629 do_mve_vaddlv (void)
17631 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17632 struct neon_type_el et
17633 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17635 if (et
.type
== NT_invtype
)
17636 first_error (BAD_EL_TYPE
);
17638 if (inst
.cond
> COND_ALWAYS
)
17639 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17641 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17643 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17645 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17646 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17647 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17648 inst
.instruction
|= inst
.operands
[2].reg
;
17653 do_neon_dyadic_if_su (void)
17655 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17656 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17659 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17660 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17661 && et
.type
== NT_float
17662 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17664 if (!check_simd_pred_availability (et
.type
== NT_float
,
17665 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17668 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17672 do_neon_addsub_if_i (void)
17674 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17675 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17678 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17679 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17680 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17682 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17683 /* If we are parsing Q registers and the element types match MVE, which NEON
17684 also supports, then we must check whether this is an instruction that can
17685 be used by both MVE/NEON. This distinction can be made based on whether
17686 they are predicated or not. */
17687 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17689 if (!check_simd_pred_availability (et
.type
== NT_float
,
17690 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17695 /* If they are either in a D register or are using an unsupported. */
17697 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17701 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17702 affected if we specify unsigned args. */
17703 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17706 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17708 V<op> A,B (A is operand 0, B is operand 2)
17713 so handle that case specially. */
17716 neon_exchange_operands (void)
17718 if (inst
.operands
[1].present
)
17720 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17722 /* Swap operands[1] and operands[2]. */
17723 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17724 inst
.operands
[1] = inst
.operands
[2];
17725 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17730 inst
.operands
[1] = inst
.operands
[2];
17731 inst
.operands
[2] = inst
.operands
[0];
17736 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17738 if (inst
.operands
[2].isreg
)
17741 neon_exchange_operands ();
17742 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17746 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17747 struct neon_type_el et
= neon_check_type (2, rs
,
17748 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17750 NEON_ENCODE (IMMED
, inst
);
17751 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17752 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17753 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17754 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17755 inst
.instruction
|= neon_quad (rs
) << 6;
17756 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17757 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17759 neon_dp_fixup (&inst
);
17766 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17770 do_neon_cmp_inv (void)
17772 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17778 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17781 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17782 scalars, which are encoded in 5 bits, M : Rm.
17783 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17784 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17787 Dot Product instructions are similar to multiply instructions except elsize
17788 should always be 32.
17790 This function translates SCALAR, which is GAS's internal encoding of indexed
17791 scalar register, to raw encoding. There is also register and index range
17792 check based on ELSIZE. */
17795 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17797 unsigned regno
= NEON_SCALAR_REG (scalar
);
17798 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17803 if (regno
> 7 || elno
> 3)
17805 return regno
| (elno
<< 3);
17808 if (regno
> 15 || elno
> 1)
17810 return regno
| (elno
<< 4);
17814 first_error (_("scalar out of range for multiply instruction"));
17820 /* Encode multiply / multiply-accumulate scalar instructions. */
17823 neon_mul_mac (struct neon_type_el et
, int ubit
)
17827 /* Give a more helpful error message if we have an invalid type. */
17828 if (et
.type
== NT_invtype
)
17831 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17832 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17833 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17834 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17835 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17836 inst
.instruction
|= LOW4 (scalar
);
17837 inst
.instruction
|= HI1 (scalar
) << 5;
17838 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17839 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17840 inst
.instruction
|= (ubit
!= 0) << 24;
17842 neon_dp_fixup (&inst
);
17846 do_neon_mac_maybe_scalar (void)
17848 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17851 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17854 if (inst
.operands
[2].isscalar
)
17856 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17857 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17858 struct neon_type_el et
= neon_check_type (3, rs
,
17859 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17860 NEON_ENCODE (SCALAR
, inst
);
17861 neon_mul_mac (et
, neon_quad (rs
));
17863 else if (!inst
.operands
[2].isvec
)
17865 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17867 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17868 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17870 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17874 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17875 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17876 affected if we specify unsigned args. */
17877 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17882 do_bfloat_vfma (void)
17884 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
17885 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
17886 enum neon_shape rs
;
17889 if (inst
.instruction
!= B_MNEM_vfmab
)
17892 inst
.instruction
= B_MNEM_vfmat
;
17895 if (inst
.operands
[2].isscalar
)
17897 rs
= neon_select_shape (NS_QQS
, NS_NULL
);
17898 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17900 inst
.instruction
|= (1 << 25);
17901 int index
= inst
.operands
[2].reg
& 0xf;
17902 constraint (!(index
< 4), _("index must be in the range 0 to 3"));
17903 inst
.operands
[2].reg
>>= 4;
17904 constraint (!(inst
.operands
[2].reg
< 8),
17905 _("indexed register must be less than 8"));
17906 neon_three_args (t_bit
);
17907 inst
.instruction
|= ((index
& 1) << 3);
17908 inst
.instruction
|= ((index
& 2) << 4);
17912 rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17913 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17914 neon_three_args (t_bit
);
17920 do_neon_fmac (void)
17922 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17923 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17926 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17929 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17931 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17932 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17938 if (inst
.operands
[2].reg
== REG_SP
)
17939 as_tsktsk (MVE_BAD_SP
);
17940 else if (inst
.operands
[2].reg
== REG_PC
)
17941 as_tsktsk (MVE_BAD_PC
);
17943 inst
.instruction
= 0xee310e40;
17944 inst
.instruction
|= (et
.size
== 16) << 28;
17945 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17946 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17947 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17948 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17949 inst
.instruction
|= inst
.operands
[2].reg
;
17956 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17959 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17965 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_bf16
) &&
17966 inst
.cond
== COND_ALWAYS
)
17968 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17969 inst
.instruction
= N_MNEM_vfma
;
17970 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17972 return do_neon_fmac();
17983 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17984 struct neon_type_el et
= neon_check_type (3, rs
,
17985 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17986 neon_three_same (neon_quad (rs
), 0, et
.size
);
17989 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17990 same types as the MAC equivalents. The polynomial type for this instruction
17991 is encoded the same as the integer type. */
17996 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17999 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18002 if (inst
.operands
[2].isscalar
)
18004 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18005 do_neon_mac_maybe_scalar ();
18009 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18011 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18012 struct neon_type_el et
18013 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
18014 if (et
.type
== NT_float
)
18015 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
18018 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
18022 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
18023 neon_dyadic_misc (NT_poly
,
18024 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
18030 do_neon_qdmulh (void)
18032 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18035 if (inst
.operands
[2].isscalar
)
18037 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18038 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18039 struct neon_type_el et
= neon_check_type (3, rs
,
18040 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18041 NEON_ENCODE (SCALAR
, inst
);
18042 neon_mul_mac (et
, neon_quad (rs
));
18046 enum neon_shape rs
;
18047 struct neon_type_el et
;
18048 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18050 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18051 et
= neon_check_type (3, rs
,
18052 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18056 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18057 et
= neon_check_type (3, rs
,
18058 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18061 NEON_ENCODE (INTEGER
, inst
);
18063 mve_encode_qqr (et
.size
, 0, 0);
18065 /* The U bit (rounding) comes from bit mask. */
18066 neon_three_same (neon_quad (rs
), 0, et
.size
);
18071 do_mve_vaddv (void)
18073 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18074 struct neon_type_el et
18075 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18077 if (et
.type
== NT_invtype
)
18078 first_error (BAD_EL_TYPE
);
18080 if (inst
.cond
> COND_ALWAYS
)
18081 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18083 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18085 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
18087 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18091 do_mve_vhcadd (void)
18093 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
18094 struct neon_type_el et
18095 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18097 if (inst
.cond
> COND_ALWAYS
)
18098 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18100 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18102 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
18103 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
18105 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
18106 as_tsktsk (_("Warning: 32-bit element size and same first and third "
18107 "operand makes instruction UNPREDICTABLE"));
18109 mve_encode_qqq (0, et
.size
);
18110 inst
.instruction
|= (rot
== 270) << 12;
18115 do_mve_vqdmull (void)
18117 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
18118 struct neon_type_el et
18119 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18122 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18123 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
18124 as_tsktsk (BAD_MVE_SRCDEST
);
18126 if (inst
.cond
> COND_ALWAYS
)
18127 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18129 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18133 mve_encode_qqq (et
.size
== 32, 64);
18134 inst
.instruction
|= 1;
18138 mve_encode_qqr (64, et
.size
== 32, 0);
18139 inst
.instruction
|= 0x3 << 5;
18146 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18147 struct neon_type_el et
18148 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
18150 if (et
.type
== NT_invtype
)
18151 first_error (BAD_EL_TYPE
);
18153 if (inst
.cond
> COND_ALWAYS
)
18154 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18156 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18158 mve_encode_qqq (0, 64);
18162 do_mve_vbrsr (void)
18164 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18165 struct neon_type_el et
18166 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18168 if (inst
.cond
> COND_ALWAYS
)
18169 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18171 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18173 mve_encode_qqr (et
.size
, 0, 0);
18179 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
18181 if (inst
.cond
> COND_ALWAYS
)
18182 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18184 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18186 mve_encode_qqq (1, 64);
18190 do_mve_vmulh (void)
18192 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18193 struct neon_type_el et
18194 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18196 if (inst
.cond
> COND_ALWAYS
)
18197 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18199 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18201 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18205 do_mve_vqdmlah (void)
18207 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18208 struct neon_type_el et
18209 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18211 if (inst
.cond
> COND_ALWAYS
)
18212 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18214 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18216 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18220 do_mve_vqdmladh (void)
18222 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18223 struct neon_type_el et
18224 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18226 if (inst
.cond
> COND_ALWAYS
)
18227 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18229 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18231 mve_encode_qqq (0, et
.size
);
18236 do_mve_vmull (void)
18239 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18240 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18241 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18242 && inst
.cond
== COND_ALWAYS
18243 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18248 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18249 N_SUF_32
| N_F64
| N_P8
18250 | N_P16
| N_I_MVE
| N_KEY
);
18251 if (((et
.type
== NT_poly
) && et
.size
== 8
18252 && ARM_CPU_IS_ANY (cpu_variant
))
18253 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
18260 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18261 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18262 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18264 /* We are dealing with MVE's vmullt. */
18266 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18267 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18268 as_tsktsk (BAD_MVE_SRCDEST
);
18270 if (inst
.cond
> COND_ALWAYS
)
18271 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18273 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18275 if (et
.type
== NT_poly
)
18276 mve_encode_qqq (neon_logbits (et
.size
), 64);
18278 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18283 inst
.instruction
= N_MNEM_vmul
;
18286 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18291 do_mve_vabav (void)
18293 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18298 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18301 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18302 | N_S16
| N_S32
| N_U8
| N_U16
18305 if (inst
.cond
> COND_ALWAYS
)
18306 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18308 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18310 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18314 do_mve_vmladav (void)
18316 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18317 struct neon_type_el et
= neon_check_type (3, rs
,
18318 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18320 if (et
.type
== NT_unsigned
18321 && (inst
.instruction
== M_MNEM_vmladavx
18322 || inst
.instruction
== M_MNEM_vmladavax
18323 || inst
.instruction
== M_MNEM_vmlsdav
18324 || inst
.instruction
== M_MNEM_vmlsdava
18325 || inst
.instruction
== M_MNEM_vmlsdavx
18326 || inst
.instruction
== M_MNEM_vmlsdavax
))
18327 first_error (BAD_SIMD_TYPE
);
18329 constraint (inst
.operands
[2].reg
> 14,
18330 _("MVE vector register in the range [Q0..Q7] expected"));
18332 if (inst
.cond
> COND_ALWAYS
)
18333 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18335 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18337 if (inst
.instruction
== M_MNEM_vmlsdav
18338 || inst
.instruction
== M_MNEM_vmlsdava
18339 || inst
.instruction
== M_MNEM_vmlsdavx
18340 || inst
.instruction
== M_MNEM_vmlsdavax
)
18341 inst
.instruction
|= (et
.size
== 8) << 28;
18343 inst
.instruction
|= (et
.size
== 8) << 8;
18345 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18346 inst
.instruction
|= (et
.size
== 32) << 16;
18350 do_mve_vmlaldav (void)
18352 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18353 struct neon_type_el et
18354 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18355 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18357 if (et
.type
== NT_unsigned
18358 && (inst
.instruction
== M_MNEM_vmlsldav
18359 || inst
.instruction
== M_MNEM_vmlsldava
18360 || inst
.instruction
== M_MNEM_vmlsldavx
18361 || inst
.instruction
== M_MNEM_vmlsldavax
))
18362 first_error (BAD_SIMD_TYPE
);
18364 if (inst
.cond
> COND_ALWAYS
)
18365 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18367 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18369 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18373 do_mve_vrmlaldavh (void)
18375 struct neon_type_el et
;
18376 if (inst
.instruction
== M_MNEM_vrmlsldavh
18377 || inst
.instruction
== M_MNEM_vrmlsldavha
18378 || inst
.instruction
== M_MNEM_vrmlsldavhx
18379 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18381 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18382 if (inst
.operands
[1].reg
== REG_SP
)
18383 as_tsktsk (MVE_BAD_SP
);
18387 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18388 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18389 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18391 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18392 N_U32
| N_S32
| N_KEY
);
18393 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18394 with vmax/min instructions, making the use of SP in assembly really
18395 nonsensical, so instead of issuing a warning like we do for other uses
18396 of SP for the odd register operand we error out. */
18397 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18400 /* Make sure we still check the second operand is an odd one and that PC is
18401 disallowed. This because we are parsing for any GPR operand, to be able
18402 to distinguish between giving a warning or an error for SP as described
18404 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18405 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18407 if (inst
.cond
> COND_ALWAYS
)
18408 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18410 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18412 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18417 do_mve_vmaxnmv (void)
18419 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18420 struct neon_type_el et
18421 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18423 if (inst
.cond
> COND_ALWAYS
)
18424 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18426 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18428 if (inst
.operands
[0].reg
== REG_SP
)
18429 as_tsktsk (MVE_BAD_SP
);
18430 else if (inst
.operands
[0].reg
== REG_PC
)
18431 as_tsktsk (MVE_BAD_PC
);
18433 mve_encode_rq (et
.size
== 16, 64);
18437 do_mve_vmaxv (void)
18439 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18440 struct neon_type_el et
;
18442 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18443 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18445 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18447 if (inst
.cond
> COND_ALWAYS
)
18448 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18450 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18452 if (inst
.operands
[0].reg
== REG_SP
)
18453 as_tsktsk (MVE_BAD_SP
);
18454 else if (inst
.operands
[0].reg
== REG_PC
)
18455 as_tsktsk (MVE_BAD_PC
);
18457 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18462 do_neon_qrdmlah (void)
18464 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18466 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18468 /* Check we're on the correct architecture. */
18469 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18471 = _("instruction form not available on this architecture.");
18472 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18474 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18475 record_feature_use (&fpu_neon_ext_v8_1
);
18477 if (inst
.operands
[2].isscalar
)
18479 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18480 struct neon_type_el et
= neon_check_type (3, rs
,
18481 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18482 NEON_ENCODE (SCALAR
, inst
);
18483 neon_mul_mac (et
, neon_quad (rs
));
18487 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18488 struct neon_type_el et
= neon_check_type (3, rs
,
18489 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18490 NEON_ENCODE (INTEGER
, inst
);
18491 /* The U bit (rounding) comes from bit mask. */
18492 neon_three_same (neon_quad (rs
), 0, et
.size
);
18497 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18498 struct neon_type_el et
18499 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18501 NEON_ENCODE (INTEGER
, inst
);
18502 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18507 do_neon_fcmp_absolute (void)
18509 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18510 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18511 N_F_16_32
| N_KEY
);
18512 /* Size field comes from bit mask. */
18513 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18517 do_neon_fcmp_absolute_inv (void)
18519 neon_exchange_operands ();
18520 do_neon_fcmp_absolute ();
18524 do_neon_step (void)
18526 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18527 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18528 N_F_16_32
| N_KEY
);
18529 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18533 do_neon_abs_neg (void)
18535 enum neon_shape rs
;
18536 struct neon_type_el et
;
18538 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18541 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18542 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18544 if (!check_simd_pred_availability (et
.type
== NT_float
,
18545 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18548 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18549 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18550 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18551 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18552 inst
.instruction
|= neon_quad (rs
) << 6;
18553 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18554 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18556 neon_dp_fixup (&inst
);
18562 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18565 enum neon_shape rs
;
18566 struct neon_type_el et
;
18567 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18569 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18570 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18574 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18575 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18579 int imm
= inst
.operands
[2].imm
;
18580 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18581 _("immediate out of range for insert"));
18582 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18588 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18591 enum neon_shape rs
;
18592 struct neon_type_el et
;
18593 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18595 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18596 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18600 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18601 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18604 int imm
= inst
.operands
[2].imm
;
18605 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18606 _("immediate out of range for insert"));
18607 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18611 do_neon_qshlu_imm (void)
18613 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18616 enum neon_shape rs
;
18617 struct neon_type_el et
;
18618 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18620 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18621 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18625 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18626 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18627 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18630 int imm
= inst
.operands
[2].imm
;
18631 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18632 _("immediate out of range for shift"));
18633 /* Only encodes the 'U present' variant of the instruction.
18634 In this case, signed types have OP (bit 8) set to 0.
18635 Unsigned types have OP set to 1. */
18636 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18637 /* The rest of the bits are the same as other immediate shifts. */
18638 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18642 do_neon_qmovn (void)
18644 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18645 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18646 /* Saturating move where operands can be signed or unsigned, and the
18647 destination has the same signedness. */
18648 NEON_ENCODE (INTEGER
, inst
);
18649 if (et
.type
== NT_unsigned
)
18650 inst
.instruction
|= 0xc0;
18652 inst
.instruction
|= 0x80;
18653 neon_two_same (0, 1, et
.size
/ 2);
18657 do_neon_qmovun (void)
18659 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18660 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18661 /* Saturating move with unsigned results. Operands must be signed. */
18662 NEON_ENCODE (INTEGER
, inst
);
18663 neon_two_same (0, 1, et
.size
/ 2);
18667 do_neon_rshift_sat_narrow (void)
18669 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18670 or unsigned. If operands are unsigned, results must also be unsigned. */
18671 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18672 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18673 int imm
= inst
.operands
[2].imm
;
18674 /* This gets the bounds check, size encoding and immediate bits calculation
18678 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18679 VQMOVN.I<size> <Dd>, <Qm>. */
18682 inst
.operands
[2].present
= 0;
18683 inst
.instruction
= N_MNEM_vqmovn
;
18688 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18689 _("immediate out of range"));
18690 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18694 do_neon_rshift_sat_narrow_u (void)
18696 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18697 or unsigned. If operands are unsigned, results must also be unsigned. */
18698 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18699 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18700 int imm
= inst
.operands
[2].imm
;
18701 /* This gets the bounds check, size encoding and immediate bits calculation
18705 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18706 VQMOVUN.I<size> <Dd>, <Qm>. */
18709 inst
.operands
[2].present
= 0;
18710 inst
.instruction
= N_MNEM_vqmovun
;
18715 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18716 _("immediate out of range"));
18717 /* FIXME: The manual is kind of unclear about what value U should have in
18718 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18720 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18724 do_neon_movn (void)
18726 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18727 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18728 NEON_ENCODE (INTEGER
, inst
);
18729 neon_two_same (0, 1, et
.size
/ 2);
18733 do_neon_rshift_narrow (void)
18735 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18736 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18737 int imm
= inst
.operands
[2].imm
;
18738 /* This gets the bounds check, size encoding and immediate bits calculation
18742 /* If immediate is zero then we are a pseudo-instruction for
18743 VMOVN.I<size> <Dd>, <Qm> */
18746 inst
.operands
[2].present
= 0;
18747 inst
.instruction
= N_MNEM_vmovn
;
18752 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18753 _("immediate out of range for narrowing operation"));
18754 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18758 do_neon_shll (void)
18760 /* FIXME: Type checking when lengthening. */
18761 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18762 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18763 unsigned imm
= inst
.operands
[2].imm
;
18765 if (imm
== et
.size
)
18767 /* Maximum shift variant. */
18768 NEON_ENCODE (INTEGER
, inst
);
18769 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18770 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18771 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18772 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18773 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18775 neon_dp_fixup (&inst
);
18779 /* A more-specific type check for non-max versions. */
18780 et
= neon_check_type (2, NS_QDI
,
18781 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18782 NEON_ENCODE (IMMED
, inst
);
18783 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18787 /* Check the various types for the VCVT instruction, and return which version
18788 the current instruction is. */
18790 #define CVT_FLAVOUR_VAR \
18791 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18792 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18793 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18794 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18795 /* Half-precision conversions. */ \
18796 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18797 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18798 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18799 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18800 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18801 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18802 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18803 Compared with single/double precision variants, only the co-processor \
18804 field is different, so the encoding flow is reused here. */ \
18805 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18806 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18807 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18808 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18809 CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg, NULL, NULL, NULL) \
18810 /* VFP instructions. */ \
18811 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18812 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18813 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18814 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18815 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18816 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18817 /* VFP instructions with bitshift. */ \
18818 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18819 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18820 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18821 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18822 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18823 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18824 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18825 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18827 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18828 neon_cvt_flavour_##C,
18830 /* The different types of conversions we can do. */
18831 enum neon_cvt_flavour
18834 neon_cvt_flavour_invalid
,
18835 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18840 static enum neon_cvt_flavour
18841 get_neon_cvt_flavour (enum neon_shape rs
)
18843 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18844 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18845 if (et.type != NT_invtype) \
18847 inst.error = NULL; \
18848 return (neon_cvt_flavour_##C); \
18851 struct neon_type_el et
;
18852 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18853 || rs
== NS_FF
) ? N_VFP
: 0;
18854 /* The instruction versions which take an immediate take one register
18855 argument, which is extended to the width of the full register. Thus the
18856 "source" and "destination" registers must have the same width. Hack that
18857 here by making the size equal to the key (wider, in this case) operand. */
18858 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18862 return neon_cvt_flavour_invalid
;
18877 /* Neon-syntax VFP conversions. */
18880 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18882 const char *opname
= 0;
18884 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18885 || rs
== NS_FHI
|| rs
== NS_HFI
)
18887 /* Conversions with immediate bitshift. */
18888 const char *enc
[] =
18890 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18896 if (flavour
< (int) ARRAY_SIZE (enc
))
18898 opname
= enc
[flavour
];
18899 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18900 _("operands 0 and 1 must be the same register"));
18901 inst
.operands
[1] = inst
.operands
[2];
18902 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18907 /* Conversions without bitshift. */
18908 const char *enc
[] =
18910 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18916 if (flavour
< (int) ARRAY_SIZE (enc
))
18917 opname
= enc
[flavour
];
18921 do_vfp_nsyn_opcode (opname
);
18923 /* ARMv8.2 fp16 VCVT instruction. */
18924 if (flavour
== neon_cvt_flavour_s32_f16
18925 || flavour
== neon_cvt_flavour_u32_f16
18926 || flavour
== neon_cvt_flavour_f16_u32
18927 || flavour
== neon_cvt_flavour_f16_s32
)
18928 do_scalar_fp16_v82_encode ();
18932 do_vfp_nsyn_cvtz (void)
18934 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18935 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18936 const char *enc
[] =
18938 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18944 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18945 do_vfp_nsyn_opcode (enc
[flavour
]);
18949 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18950 enum neon_cvt_mode mode
)
18955 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18956 D register operands. */
18957 if (flavour
== neon_cvt_flavour_s32_f64
18958 || flavour
== neon_cvt_flavour_u32_f64
)
18959 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18962 if (flavour
== neon_cvt_flavour_s32_f16
18963 || flavour
== neon_cvt_flavour_u32_f16
)
18964 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18967 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18971 case neon_cvt_flavour_s32_f64
:
18975 case neon_cvt_flavour_s32_f32
:
18979 case neon_cvt_flavour_s32_f16
:
18983 case neon_cvt_flavour_u32_f64
:
18987 case neon_cvt_flavour_u32_f32
:
18991 case neon_cvt_flavour_u32_f16
:
18996 first_error (_("invalid instruction shape"));
19002 case neon_cvt_mode_a
: rm
= 0; break;
19003 case neon_cvt_mode_n
: rm
= 1; break;
19004 case neon_cvt_mode_p
: rm
= 2; break;
19005 case neon_cvt_mode_m
: rm
= 3; break;
19006 default: first_error (_("invalid rounding mode")); return;
19009 NEON_ENCODE (FPV8
, inst
);
19010 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
19011 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
19012 inst
.instruction
|= sz
<< 8;
19014 /* ARMv8.2 fp16 VCVT instruction. */
19015 if (flavour
== neon_cvt_flavour_s32_f16
19016 ||flavour
== neon_cvt_flavour_u32_f16
)
19017 do_scalar_fp16_v82_encode ();
19018 inst
.instruction
|= op
<< 7;
19019 inst
.instruction
|= rm
<< 16;
19020 inst
.instruction
|= 0xf0000000;
19021 inst
.is_neon
= TRUE
;
19025 do_neon_cvt_1 (enum neon_cvt_mode mode
)
19027 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
19028 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
19029 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
19031 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19033 if (flavour
== neon_cvt_flavour_invalid
)
19036 /* PR11109: Handle round-to-zero for VCVT conversions. */
19037 if (mode
== neon_cvt_mode_z
19038 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
19039 && (flavour
== neon_cvt_flavour_s16_f16
19040 || flavour
== neon_cvt_flavour_u16_f16
19041 || flavour
== neon_cvt_flavour_s32_f32
19042 || flavour
== neon_cvt_flavour_u32_f32
19043 || flavour
== neon_cvt_flavour_s32_f64
19044 || flavour
== neon_cvt_flavour_u32_f64
)
19045 && (rs
== NS_FD
|| rs
== NS_FF
))
19047 do_vfp_nsyn_cvtz ();
19051 /* ARMv8.2 fp16 VCVT conversions. */
19052 if (mode
== neon_cvt_mode_z
19053 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
19054 && (flavour
== neon_cvt_flavour_s32_f16
19055 || flavour
== neon_cvt_flavour_u32_f16
)
19058 do_vfp_nsyn_cvtz ();
19059 do_scalar_fp16_v82_encode ();
19063 /* VFP rather than Neon conversions. */
19064 if (flavour
>= neon_cvt_flavour_first_fp
)
19066 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19067 do_vfp_nsyn_cvt (rs
, flavour
);
19069 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19077 if (mode
== neon_cvt_mode_z
19078 && (flavour
== neon_cvt_flavour_f16_s16
19079 || flavour
== neon_cvt_flavour_f16_u16
19080 || flavour
== neon_cvt_flavour_s16_f16
19081 || flavour
== neon_cvt_flavour_u16_f16
19082 || flavour
== neon_cvt_flavour_f32_u32
19083 || flavour
== neon_cvt_flavour_f32_s32
19084 || flavour
== neon_cvt_flavour_s32_f32
19085 || flavour
== neon_cvt_flavour_u32_f32
))
19087 if (!check_simd_pred_availability (TRUE
,
19088 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19091 else if (mode
== neon_cvt_mode_n
)
19093 /* We are dealing with vcvt with the 'ne' condition. */
19095 inst
.instruction
= N_MNEM_vcvt
;
19096 do_neon_cvt_1 (neon_cvt_mode_z
);
19099 /* fall through. */
19103 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19104 0x0000100, 0x1000100, 0x0, 0x1000000};
19106 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19107 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19110 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19112 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
19113 _("immediate value out of range"));
19116 case neon_cvt_flavour_f16_s16
:
19117 case neon_cvt_flavour_f16_u16
:
19118 case neon_cvt_flavour_s16_f16
:
19119 case neon_cvt_flavour_u16_f16
:
19120 constraint (inst
.operands
[2].imm
> 16,
19121 _("immediate value out of range"));
19123 case neon_cvt_flavour_f32_u32
:
19124 case neon_cvt_flavour_f32_s32
:
19125 case neon_cvt_flavour_s32_f32
:
19126 case neon_cvt_flavour_u32_f32
:
19127 constraint (inst
.operands
[2].imm
> 32,
19128 _("immediate value out of range"));
19131 inst
.error
= BAD_FPU
;
19136 /* Fixed-point conversion with #0 immediate is encoded as an
19137 integer conversion. */
19138 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
19140 NEON_ENCODE (IMMED
, inst
);
19141 if (flavour
!= neon_cvt_flavour_invalid
)
19142 inst
.instruction
|= enctab
[flavour
];
19143 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19144 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19145 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19146 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19147 inst
.instruction
|= neon_quad (rs
) << 6;
19148 inst
.instruction
|= 1 << 21;
19149 if (flavour
< neon_cvt_flavour_s16_f16
)
19151 inst
.instruction
|= 1 << 21;
19152 immbits
= 32 - inst
.operands
[2].imm
;
19153 inst
.instruction
|= immbits
<< 16;
19157 inst
.instruction
|= 3 << 20;
19158 immbits
= 16 - inst
.operands
[2].imm
;
19159 inst
.instruction
|= immbits
<< 16;
19160 inst
.instruction
&= ~(1 << 9);
19163 neon_dp_fixup (&inst
);
19168 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19169 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
19170 && (flavour
== neon_cvt_flavour_s16_f16
19171 || flavour
== neon_cvt_flavour_u16_f16
19172 || flavour
== neon_cvt_flavour_s32_f32
19173 || flavour
== neon_cvt_flavour_u32_f32
))
19175 if (!check_simd_pred_availability (TRUE
,
19176 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19179 else if (mode
== neon_cvt_mode_z
19180 && (flavour
== neon_cvt_flavour_f16_s16
19181 || flavour
== neon_cvt_flavour_f16_u16
19182 || flavour
== neon_cvt_flavour_s16_f16
19183 || flavour
== neon_cvt_flavour_u16_f16
19184 || flavour
== neon_cvt_flavour_f32_u32
19185 || flavour
== neon_cvt_flavour_f32_s32
19186 || flavour
== neon_cvt_flavour_s32_f32
19187 || flavour
== neon_cvt_flavour_u32_f32
))
19189 if (!check_simd_pred_availability (TRUE
,
19190 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19193 /* fall through. */
19195 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
19198 NEON_ENCODE (FLOAT
, inst
);
19199 if (!check_simd_pred_availability (TRUE
,
19200 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19203 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19204 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19205 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19206 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19207 inst
.instruction
|= neon_quad (rs
) << 6;
19208 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19209 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19210 inst
.instruction
|= mode
<< 8;
19211 if (flavour
== neon_cvt_flavour_u16_f16
19212 || flavour
== neon_cvt_flavour_s16_f16
)
19213 /* Mask off the original size bits and reencode them. */
19214 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19217 inst
.instruction
|= 0xfc000000;
19219 inst
.instruction
|= 0xf0000000;
19225 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19226 0x100, 0x180, 0x0, 0x080};
19228 NEON_ENCODE (INTEGER
, inst
);
19230 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19232 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19236 if (flavour
!= neon_cvt_flavour_invalid
)
19237 inst
.instruction
|= enctab
[flavour
];
19239 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19240 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19241 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19242 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19243 inst
.instruction
|= neon_quad (rs
) << 6;
19244 if (flavour
>= neon_cvt_flavour_s16_f16
19245 && flavour
<= neon_cvt_flavour_f16_u16
)
19246 /* Half precision. */
19247 inst
.instruction
|= 1 << 18;
19249 inst
.instruction
|= 2 << 18;
19251 neon_dp_fixup (&inst
);
19256 /* Half-precision conversions for Advanced SIMD -- neon. */
19259 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19263 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19265 as_bad (_("operand size must match register width"));
19270 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19272 as_bad (_("operand size must match register width"));
19278 if (flavour
== neon_cvt_flavour_bf16_f32
)
19280 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8
) == FAIL
)
19282 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19283 /* VCVT.bf16.f32. */
19284 inst
.instruction
= 0x11b60640;
19287 /* VCVT.f16.f32. */
19288 inst
.instruction
= 0x3b60600;
19291 /* VCVT.f32.f16. */
19292 inst
.instruction
= 0x3b60700;
19294 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19295 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19296 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19297 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19298 neon_dp_fixup (&inst
);
19302 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19303 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19304 do_vfp_nsyn_cvt (rs
, flavour
);
19306 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19311 do_neon_cvtr (void)
19313 do_neon_cvt_1 (neon_cvt_mode_x
);
19319 do_neon_cvt_1 (neon_cvt_mode_z
);
19323 do_neon_cvta (void)
19325 do_neon_cvt_1 (neon_cvt_mode_a
);
19329 do_neon_cvtn (void)
19331 do_neon_cvt_1 (neon_cvt_mode_n
);
19335 do_neon_cvtp (void)
19337 do_neon_cvt_1 (neon_cvt_mode_p
);
19341 do_neon_cvtm (void)
19343 do_neon_cvt_1 (neon_cvt_mode_m
);
19347 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19350 mark_feature_used (&fpu_vfp_ext_armv8
);
19352 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19353 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19354 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19355 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19356 inst
.instruction
|= to
? 0x10000 : 0;
19357 inst
.instruction
|= t
? 0x80 : 0;
19358 inst
.instruction
|= is_double
? 0x100 : 0;
19359 do_vfp_cond_or_thumb ();
19363 do_neon_cvttb_1 (bfd_boolean t
)
19365 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19366 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19370 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19372 int single_to_half
= 0;
19373 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19376 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19378 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19379 && (flavour
== neon_cvt_flavour_u16_f16
19380 || flavour
== neon_cvt_flavour_s16_f16
19381 || flavour
== neon_cvt_flavour_f16_s16
19382 || flavour
== neon_cvt_flavour_f16_u16
19383 || flavour
== neon_cvt_flavour_u32_f32
19384 || flavour
== neon_cvt_flavour_s32_f32
19385 || flavour
== neon_cvt_flavour_f32_s32
19386 || flavour
== neon_cvt_flavour_f32_u32
))
19389 inst
.instruction
= N_MNEM_vcvt
;
19390 set_pred_insn_type (INSIDE_VPT_INSN
);
19391 do_neon_cvt_1 (neon_cvt_mode_z
);
19394 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19395 single_to_half
= 1;
19396 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19398 first_error (BAD_FPU
);
19402 inst
.instruction
= 0xee3f0e01;
19403 inst
.instruction
|= single_to_half
<< 28;
19404 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19405 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19406 inst
.instruction
|= t
<< 12;
19407 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19408 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19411 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19414 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19416 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19419 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19421 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19423 /* The VCVTB and VCVTT instructions with D-register operands
19424 don't work for SP only targets. */
19425 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19429 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19431 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19433 /* The VCVTB and VCVTT instructions with D-register operands
19434 don't work for SP only targets. */
19435 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19439 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19441 else if (neon_check_type (2, rs
, N_BF16
| N_VFP
, N_F32
).type
!= NT_invtype
)
19443 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19445 inst
.instruction
|= (1 << 8);
19446 inst
.instruction
&= ~(1 << 9);
19447 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19454 do_neon_cvtb (void)
19456 do_neon_cvttb_1 (FALSE
);
19461 do_neon_cvtt (void)
19463 do_neon_cvttb_1 (TRUE
);
19467 neon_move_immediate (void)
19469 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19470 struct neon_type_el et
= neon_check_type (2, rs
,
19471 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19472 unsigned immlo
, immhi
= 0, immbits
;
19473 int op
, cmode
, float_p
;
19475 constraint (et
.type
== NT_invtype
,
19476 _("operand size must be specified for immediate VMOV"));
19478 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19479 op
= (inst
.instruction
& (1 << 5)) != 0;
19481 immlo
= inst
.operands
[1].imm
;
19482 if (inst
.operands
[1].regisimm
)
19483 immhi
= inst
.operands
[1].reg
;
19485 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19486 _("immediate has bits set outside the operand size"));
19488 float_p
= inst
.operands
[1].immisfloat
;
19490 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19491 et
.size
, et
.type
)) == FAIL
)
19493 /* Invert relevant bits only. */
19494 neon_invert_size (&immlo
, &immhi
, et
.size
);
19495 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19496 with one or the other; those cases are caught by
19497 neon_cmode_for_move_imm. */
19499 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19500 &op
, et
.size
, et
.type
)) == FAIL
)
19502 first_error (_("immediate out of range"));
19507 inst
.instruction
&= ~(1 << 5);
19508 inst
.instruction
|= op
<< 5;
19510 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19511 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19512 inst
.instruction
|= neon_quad (rs
) << 6;
19513 inst
.instruction
|= cmode
<< 8;
19515 neon_write_immbits (immbits
);
19521 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19524 if (inst
.operands
[1].isreg
)
19526 enum neon_shape rs
;
19527 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19528 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19530 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19532 NEON_ENCODE (INTEGER
, inst
);
19533 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19534 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19535 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19536 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19537 inst
.instruction
|= neon_quad (rs
) << 6;
19541 NEON_ENCODE (IMMED
, inst
);
19542 neon_move_immediate ();
19545 neon_dp_fixup (&inst
);
19547 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19549 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19550 constraint ((inst
.instruction
& 0xd00) == 0xd00,
19551 _("immediate value out of range"));
19555 /* Encode instructions of form:
19557 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19558 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19561 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19563 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19564 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19565 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19566 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19567 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19568 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19569 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19570 inst
.instruction
|= neon_logbits (size
) << 20;
19572 neon_dp_fixup (&inst
);
19576 do_neon_dyadic_long (void)
19578 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19581 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19584 NEON_ENCODE (INTEGER
, inst
);
19585 /* FIXME: Type checking for lengthening op. */
19586 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19587 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19588 neon_mixed_length (et
, et
.size
);
19590 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19591 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19593 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19594 in an IT block with le/lt conditions. */
19596 if (inst
.cond
== 0xf)
19598 else if (inst
.cond
== 0x10)
19601 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19603 if (inst
.instruction
== N_MNEM_vaddl
)
19605 inst
.instruction
= N_MNEM_vadd
;
19606 do_neon_addsub_if_i ();
19608 else if (inst
.instruction
== N_MNEM_vsubl
)
19610 inst
.instruction
= N_MNEM_vsub
;
19611 do_neon_addsub_if_i ();
19613 else if (inst
.instruction
== N_MNEM_vabdl
)
19615 inst
.instruction
= N_MNEM_vabd
;
19616 do_neon_dyadic_if_su ();
19620 first_error (BAD_FPU
);
19624 do_neon_abal (void)
19626 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19627 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19628 neon_mixed_length (et
, et
.size
);
19632 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19634 if (inst
.operands
[2].isscalar
)
19636 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19637 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19638 NEON_ENCODE (SCALAR
, inst
);
19639 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19643 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19644 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19645 NEON_ENCODE (INTEGER
, inst
);
19646 neon_mixed_length (et
, et
.size
);
19651 do_neon_mac_maybe_scalar_long (void)
19653 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19656 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19657 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19660 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19662 unsigned regno
= NEON_SCALAR_REG (scalar
);
19663 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19667 if (regno
> 7 || elno
> 3)
19670 return ((regno
& 0x7)
19671 | ((elno
& 0x1) << 3)
19672 | (((elno
>> 1) & 0x1) << 5));
19676 if (regno
> 15 || elno
> 1)
19679 return (((regno
& 0x1) << 5)
19680 | ((regno
>> 1) & 0x7)
19681 | ((elno
& 0x1) << 3));
19685 first_error (_("scalar out of range for multiply instruction"));
19690 do_neon_fmac_maybe_scalar_long (int subtype
)
19692 enum neon_shape rs
;
19694 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19695 field (bits[21:20]) has different meaning. For scalar index variant, it's
19696 used to differentiate add and subtract, otherwise it's with fixed value
19700 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19701 be a scalar index register. */
19702 if (inst
.operands
[2].isscalar
)
19704 high8
= 0xfe000000;
19707 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19711 high8
= 0xfc000000;
19714 inst
.instruction
|= (0x1 << 23);
19715 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19719 if (inst
.cond
!= COND_ALWAYS
)
19720 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19721 "behaviour is UNPREDICTABLE"));
19723 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19726 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19729 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19730 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19731 so we simply pass -1 as size. */
19732 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19733 neon_three_same (quad_p
, 0, size
);
19735 /* Undo neon_dp_fixup. Redo the high eight bits. */
19736 inst
.instruction
&= 0x00ffffff;
19737 inst
.instruction
|= high8
;
19739 #define LOW1(R) ((R) & 0x1)
19740 #define HI4(R) (((R) >> 1) & 0xf)
19741 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19742 whether the instruction is in Q form and whether Vm is a scalar indexed
19744 if (inst
.operands
[2].isscalar
)
19747 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19748 inst
.instruction
&= 0xffffffd0;
19749 inst
.instruction
|= rm
;
19753 /* Redo Rn as well. */
19754 inst
.instruction
&= 0xfff0ff7f;
19755 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19756 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19761 /* Redo Rn and Rm. */
19762 inst
.instruction
&= 0xfff0ff50;
19763 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19764 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19765 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19766 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19771 do_neon_vfmal (void)
19773 return do_neon_fmac_maybe_scalar_long (0);
19777 do_neon_vfmsl (void)
19779 return do_neon_fmac_maybe_scalar_long (1);
19783 do_neon_dyadic_wide (void)
19785 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19786 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19787 neon_mixed_length (et
, et
.size
);
19791 do_neon_dyadic_narrow (void)
19793 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19794 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19795 /* Operand sign is unimportant, and the U bit is part of the opcode,
19796 so force the operand type to integer. */
19797 et
.type
= NT_integer
;
19798 neon_mixed_length (et
, et
.size
/ 2);
19802 do_neon_mul_sat_scalar_long (void)
19804 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19808 do_neon_vmull (void)
19810 if (inst
.operands
[2].isscalar
)
19811 do_neon_mac_maybe_scalar_long ();
19814 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19815 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19817 if (et
.type
== NT_poly
)
19818 NEON_ENCODE (POLY
, inst
);
19820 NEON_ENCODE (INTEGER
, inst
);
19822 /* For polynomial encoding the U bit must be zero, and the size must
19823 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19824 obviously, as 0b10). */
19827 /* Check we're on the correct architecture. */
19828 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19830 _("Instruction form not available on this architecture.");
19835 neon_mixed_length (et
, et
.size
);
19842 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19843 struct neon_type_el et
= neon_check_type (3, rs
,
19844 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19845 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19847 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19848 _("shift out of range"));
19849 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19850 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19851 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19852 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19853 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19854 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19855 inst
.instruction
|= neon_quad (rs
) << 6;
19856 inst
.instruction
|= imm
<< 8;
19858 neon_dp_fixup (&inst
);
19864 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19867 enum neon_shape rs
;
19868 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19869 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19871 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19873 struct neon_type_el et
= neon_check_type (2, rs
,
19874 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19876 unsigned op
= (inst
.instruction
>> 7) & 3;
19877 /* N (width of reversed regions) is encoded as part of the bitmask. We
19878 extract it here to check the elements to be reversed are smaller.
19879 Otherwise we'd get a reserved instruction. */
19880 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19882 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19883 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19884 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19885 " operands makes instruction UNPREDICTABLE"));
19887 gas_assert (elsize
!= 0);
19888 constraint (et
.size
>= elsize
,
19889 _("elements must be smaller than reversal region"));
19890 neon_two_same (neon_quad (rs
), 1, et
.size
);
19896 if (inst
.operands
[1].isscalar
)
19898 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19900 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19901 struct neon_type_el et
= neon_check_type (2, rs
,
19902 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19903 unsigned sizebits
= et
.size
>> 3;
19904 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19905 int logsize
= neon_logbits (et
.size
);
19906 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19908 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19911 NEON_ENCODE (SCALAR
, inst
);
19912 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19913 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19914 inst
.instruction
|= LOW4 (dm
);
19915 inst
.instruction
|= HI1 (dm
) << 5;
19916 inst
.instruction
|= neon_quad (rs
) << 6;
19917 inst
.instruction
|= x
<< 17;
19918 inst
.instruction
|= sizebits
<< 16;
19920 neon_dp_fixup (&inst
);
19924 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19925 struct neon_type_el et
= neon_check_type (2, rs
,
19926 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19929 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19933 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19936 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19938 if (inst
.operands
[1].reg
== REG_SP
)
19939 as_tsktsk (MVE_BAD_SP
);
19940 else if (inst
.operands
[1].reg
== REG_PC
)
19941 as_tsktsk (MVE_BAD_PC
);
19944 /* Duplicate ARM register to lanes of vector. */
19945 NEON_ENCODE (ARMREG
, inst
);
19948 case 8: inst
.instruction
|= 0x400000; break;
19949 case 16: inst
.instruction
|= 0x000020; break;
19950 case 32: inst
.instruction
|= 0x000000; break;
19953 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19954 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19955 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19956 inst
.instruction
|= neon_quad (rs
) << 21;
19957 /* The encoding for this instruction is identical for the ARM and Thumb
19958 variants, except for the condition field. */
19959 do_vfp_cond_or_thumb ();
19964 do_mve_mov (int toQ
)
19966 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19968 if (inst
.cond
> COND_ALWAYS
)
19969 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19971 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19980 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19981 _("Index one must be [2,3] and index two must be two less than"
19983 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19984 _("General purpose registers may not be the same"));
19985 constraint (inst
.operands
[Rt
].reg
== REG_SP
19986 || inst
.operands
[Rt2
].reg
== REG_SP
,
19988 constraint (inst
.operands
[Rt
].reg
== REG_PC
19989 || inst
.operands
[Rt2
].reg
== REG_PC
,
19992 inst
.instruction
= 0xec000f00;
19993 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19994 inst
.instruction
|= !!toQ
<< 20;
19995 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19996 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19997 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19998 inst
.instruction
|= inst
.operands
[Rt
].reg
;
20004 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20007 if (inst
.cond
> COND_ALWAYS
)
20008 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20010 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
20012 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
20015 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20016 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
20017 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20018 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20019 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20024 /* VMOV has particularly many variations. It can be one of:
20025 0. VMOV<c><q> <Qd>, <Qm>
20026 1. VMOV<c><q> <Dd>, <Dm>
20027 (Register operations, which are VORR with Rm = Rn.)
20028 2. VMOV<c><q>.<dt> <Qd>, #<imm>
20029 3. VMOV<c><q>.<dt> <Dd>, #<imm>
20031 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
20032 (ARM register to scalar.)
20033 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
20034 (Two ARM registers to vector.)
20035 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
20036 (Scalar to ARM register.)
20037 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
20038 (Vector to two ARM registers.)
20039 8. VMOV.F32 <Sd>, <Sm>
20040 9. VMOV.F64 <Dd>, <Dm>
20041 (VFP register moves.)
20042 10. VMOV.F32 <Sd>, #imm
20043 11. VMOV.F64 <Dd>, #imm
20044 (VFP float immediate load.)
20045 12. VMOV <Rd>, <Sm>
20046 (VFP single to ARM reg.)
20047 13. VMOV <Sd>, <Rm>
20048 (ARM reg to VFP single.)
20049 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20050 (Two ARM regs to two VFP singles.)
20051 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20052 (Two VFP singles to two ARM regs.)
20053 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20054 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20055 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20056 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
20058 These cases can be disambiguated using neon_select_shape, except cases 1/9
20059 and 3/11 which depend on the operand type too.
20061 All the encoded bits are hardcoded by this function.
20063 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20064 Cases 5, 7 may be used with VFPv2 and above.
20066 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
20067 can specify a type where it doesn't make sense to, and is ignored). */
20072 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
20073 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
20074 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
20075 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
20077 struct neon_type_el et
;
20078 const char *ldconst
= 0;
20082 case NS_DD
: /* case 1/9. */
20083 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20084 /* It is not an error here if no type is given. */
20087 /* In MVE we interpret the following instructions as same, so ignoring
20088 the following type (float) and size (64) checks.
20089 a: VMOV<c><q> <Dd>, <Dm>
20090 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
20091 if ((et
.type
== NT_float
&& et
.size
== 64)
20092 || (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
20094 do_vfp_nsyn_opcode ("fcpyd");
20097 /* fall through. */
20099 case NS_QQ
: /* case 0/1. */
20101 if (!check_simd_pred_availability (FALSE
,
20102 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20104 /* The architecture manual I have doesn't explicitly state which
20105 value the U bit should have for register->register moves, but
20106 the equivalent VORR instruction has U = 0, so do that. */
20107 inst
.instruction
= 0x0200110;
20108 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20109 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20110 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20111 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20112 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20113 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20114 inst
.instruction
|= neon_quad (rs
) << 6;
20116 neon_dp_fixup (&inst
);
20120 case NS_DI
: /* case 3/11. */
20121 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20123 if (et
.type
== NT_float
&& et
.size
== 64)
20125 /* case 11 (fconstd). */
20126 ldconst
= "fconstd";
20127 goto encode_fconstd
;
20129 /* fall through. */
20131 case NS_QI
: /* case 2/3. */
20132 if (!check_simd_pred_availability (FALSE
,
20133 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20135 inst
.instruction
= 0x0800010;
20136 neon_move_immediate ();
20137 neon_dp_fixup (&inst
);
20140 case NS_SR
: /* case 4. */
20142 unsigned bcdebits
= 0;
20144 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
20145 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
20147 /* .<size> is optional here, defaulting to .32. */
20148 if (inst
.vectype
.elems
== 0
20149 && inst
.operands
[0].vectype
.type
== NT_invtype
20150 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20152 inst
.vectype
.el
[0].type
= NT_untyped
;
20153 inst
.vectype
.el
[0].size
= 32;
20154 inst
.vectype
.elems
= 1;
20157 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
20158 logsize
= neon_logbits (et
.size
);
20162 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20163 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
20168 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20169 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20173 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20175 if (inst
.operands
[1].reg
== REG_SP
)
20176 as_tsktsk (MVE_BAD_SP
);
20177 else if (inst
.operands
[1].reg
== REG_PC
)
20178 as_tsktsk (MVE_BAD_PC
);
20180 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
20182 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20183 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20188 case 8: bcdebits
= 0x8; break;
20189 case 16: bcdebits
= 0x1; break;
20190 case 32: bcdebits
= 0x0; break;
20194 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20196 inst
.instruction
= 0xe000b10;
20197 do_vfp_cond_or_thumb ();
20198 inst
.instruction
|= LOW4 (dn
) << 16;
20199 inst
.instruction
|= HI1 (dn
) << 7;
20200 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20201 inst
.instruction
|= (bcdebits
& 3) << 5;
20202 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
20203 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20207 case NS_DRR
: /* case 5 (fmdrr). */
20208 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20209 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20212 inst
.instruction
= 0xc400b10;
20213 do_vfp_cond_or_thumb ();
20214 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
20215 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
20216 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20217 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
20220 case NS_RS
: /* case 6. */
20223 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
20224 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
20225 unsigned abcdebits
= 0;
20227 /* .<dt> is optional here, defaulting to .32. */
20228 if (inst
.vectype
.elems
== 0
20229 && inst
.operands
[0].vectype
.type
== NT_invtype
20230 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20232 inst
.vectype
.el
[0].type
= NT_untyped
;
20233 inst
.vectype
.el
[0].size
= 32;
20234 inst
.vectype
.elems
= 1;
20237 et
= neon_check_type (2, NS_NULL
,
20238 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20239 logsize
= neon_logbits (et
.size
);
20243 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20244 && vfp_or_neon_is_neon (NEON_CHECK_CC
20245 | NEON_CHECK_ARCH
) == FAIL
)
20250 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20251 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20255 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20257 if (inst
.operands
[0].reg
== REG_SP
)
20258 as_tsktsk (MVE_BAD_SP
);
20259 else if (inst
.operands
[0].reg
== REG_PC
)
20260 as_tsktsk (MVE_BAD_PC
);
20263 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20265 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20266 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20270 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20271 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20272 case 32: abcdebits
= 0x00; break;
20276 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20277 inst
.instruction
= 0xe100b10;
20278 do_vfp_cond_or_thumb ();
20279 inst
.instruction
|= LOW4 (dn
) << 16;
20280 inst
.instruction
|= HI1 (dn
) << 7;
20281 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20282 inst
.instruction
|= (abcdebits
& 3) << 5;
20283 inst
.instruction
|= (abcdebits
>> 2) << 21;
20284 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20288 case NS_RRD
: /* case 7 (fmrrd). */
20289 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20290 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20293 inst
.instruction
= 0xc500b10;
20294 do_vfp_cond_or_thumb ();
20295 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20296 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20297 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20298 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20301 case NS_FF
: /* case 8 (fcpys). */
20302 do_vfp_nsyn_opcode ("fcpys");
20306 case NS_FI
: /* case 10 (fconsts). */
20307 ldconst
= "fconsts";
20309 if (!inst
.operands
[1].immisfloat
)
20312 /* Immediate has to fit in 8 bits so float is enough. */
20313 float imm
= (float) inst
.operands
[1].imm
;
20314 memcpy (&new_imm
, &imm
, sizeof (float));
20315 /* But the assembly may have been written to provide an integer
20316 bit pattern that equates to a float, so check that the
20317 conversion has worked. */
20318 if (is_quarter_float (new_imm
))
20320 if (is_quarter_float (inst
.operands
[1].imm
))
20321 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20323 inst
.operands
[1].imm
= new_imm
;
20324 inst
.operands
[1].immisfloat
= 1;
20328 if (is_quarter_float (inst
.operands
[1].imm
))
20330 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20331 do_vfp_nsyn_opcode (ldconst
);
20333 /* ARMv8.2 fp16 vmov.f16 instruction. */
20335 do_scalar_fp16_v82_encode ();
20338 first_error (_("immediate out of range"));
20342 case NS_RF
: /* case 12 (fmrs). */
20343 do_vfp_nsyn_opcode ("fmrs");
20344 /* ARMv8.2 fp16 vmov.f16 instruction. */
20346 do_scalar_fp16_v82_encode ();
20350 case NS_FR
: /* case 13 (fmsr). */
20351 do_vfp_nsyn_opcode ("fmsr");
20352 /* ARMv8.2 fp16 vmov.f16 instruction. */
20354 do_scalar_fp16_v82_encode ();
20364 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20365 (one of which is a list), but we have parsed four. Do some fiddling to
20366 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20368 case NS_RRFF
: /* case 14 (fmrrs). */
20369 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20370 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20372 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20373 _("VFP registers must be adjacent"));
20374 inst
.operands
[2].imm
= 2;
20375 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20376 do_vfp_nsyn_opcode ("fmrrs");
20379 case NS_FFRR
: /* case 15 (fmsrr). */
20380 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20381 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20383 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20384 _("VFP registers must be adjacent"));
20385 inst
.operands
[1] = inst
.operands
[2];
20386 inst
.operands
[2] = inst
.operands
[3];
20387 inst
.operands
[0].imm
= 2;
20388 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20389 do_vfp_nsyn_opcode ("fmsrr");
20393 /* neon_select_shape has determined that the instruction
20394 shape is wrong and has already set the error message. */
20405 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20406 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20407 && !inst
.operands
[2].present
))
20409 inst
.instruction
= 0;
20412 set_pred_insn_type (INSIDE_IT_INSN
);
20417 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20420 if (inst
.cond
!= COND_ALWAYS
)
20421 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20423 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20424 | N_S16
| N_U16
| N_KEY
);
20426 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20427 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20428 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20429 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20430 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20431 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20436 do_neon_rshift_round_imm (void)
20438 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20441 enum neon_shape rs
;
20442 struct neon_type_el et
;
20444 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20446 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20447 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20451 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20452 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20454 int imm
= inst
.operands
[2].imm
;
20456 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20459 inst
.operands
[2].present
= 0;
20464 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20465 _("immediate out of range for shift"));
20466 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20471 do_neon_movhf (void)
20473 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20474 constraint (rs
!= NS_HH
, _("invalid suffix"));
20476 if (inst
.cond
!= COND_ALWAYS
)
20480 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20481 " the behaviour is UNPREDICTABLE"));
20485 inst
.error
= BAD_COND
;
20490 do_vfp_sp_monadic ();
20493 inst
.instruction
|= 0xf0000000;
20497 do_neon_movl (void)
20499 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20500 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20501 unsigned sizebits
= et
.size
>> 3;
20502 inst
.instruction
|= sizebits
<< 19;
20503 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20509 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20510 struct neon_type_el et
= neon_check_type (2, rs
,
20511 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20512 NEON_ENCODE (INTEGER
, inst
);
20513 neon_two_same (neon_quad (rs
), 1, et
.size
);
20517 do_neon_zip_uzp (void)
20519 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20520 struct neon_type_el et
= neon_check_type (2, rs
,
20521 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20522 if (rs
== NS_DD
&& et
.size
== 32)
20524 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20525 inst
.instruction
= N_MNEM_vtrn
;
20529 neon_two_same (neon_quad (rs
), 1, et
.size
);
20533 do_neon_sat_abs_neg (void)
20535 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20538 enum neon_shape rs
;
20539 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20540 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20542 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20543 struct neon_type_el et
= neon_check_type (2, rs
,
20544 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20545 neon_two_same (neon_quad (rs
), 1, et
.size
);
20549 do_neon_pair_long (void)
20551 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20552 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20553 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20554 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20555 neon_two_same (neon_quad (rs
), 1, et
.size
);
20559 do_neon_recip_est (void)
20561 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20562 struct neon_type_el et
= neon_check_type (2, rs
,
20563 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20564 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20565 neon_two_same (neon_quad (rs
), 1, et
.size
);
20571 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20574 enum neon_shape rs
;
20575 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20576 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20578 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20580 struct neon_type_el et
= neon_check_type (2, rs
,
20581 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20582 neon_two_same (neon_quad (rs
), 1, et
.size
);
20588 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20591 enum neon_shape rs
;
20592 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20593 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20595 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20597 struct neon_type_el et
= neon_check_type (2, rs
,
20598 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20599 neon_two_same (neon_quad (rs
), 1, et
.size
);
20605 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20606 struct neon_type_el et
= neon_check_type (2, rs
,
20607 N_EQK
| N_INT
, N_8
| N_KEY
);
20608 neon_two_same (neon_quad (rs
), 1, et
.size
);
20614 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20615 neon_two_same (neon_quad (rs
), 1, -1);
20619 do_neon_tbl_tbx (void)
20621 unsigned listlenbits
;
20622 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20624 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20626 first_error (_("bad list length for table lookup"));
20630 listlenbits
= inst
.operands
[1].imm
- 1;
20631 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20632 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20633 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20634 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20635 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20636 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20637 inst
.instruction
|= listlenbits
<< 8;
20639 neon_dp_fixup (&inst
);
20643 do_neon_ldm_stm (void)
20645 /* P, U and L bits are part of bitmask. */
20646 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20647 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20649 if (inst
.operands
[1].issingle
)
20651 do_vfp_nsyn_ldm_stm (is_dbmode
);
20655 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20656 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20658 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20659 _("register list must contain at least 1 and at most 16 "
20662 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20663 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20664 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20665 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20667 inst
.instruction
|= offsetbits
;
20669 do_vfp_cond_or_thumb ();
20673 do_neon_ldr_str (void)
20675 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20677 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20678 And is UNPREDICTABLE in thumb mode. */
20680 && inst
.operands
[1].reg
== REG_PC
20681 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20684 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20685 else if (warn_on_deprecated
)
20686 as_tsktsk (_("Use of PC here is deprecated"));
20689 if (inst
.operands
[0].issingle
)
20692 do_vfp_nsyn_opcode ("flds");
20694 do_vfp_nsyn_opcode ("fsts");
20696 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20697 if (inst
.vectype
.el
[0].size
== 16)
20698 do_scalar_fp16_v82_encode ();
20703 do_vfp_nsyn_opcode ("fldd");
20705 do_vfp_nsyn_opcode ("fstd");
20710 do_t_vldr_vstr_sysreg (void)
20712 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20713 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20715 /* Use of PC is UNPREDICTABLE. */
20716 if (inst
.operands
[1].reg
== REG_PC
)
20717 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20719 if (inst
.operands
[1].immisreg
)
20720 inst
.error
= _("instruction does not accept register index");
20722 if (!inst
.operands
[1].isreg
)
20723 inst
.error
= _("instruction does not accept PC-relative addressing");
20725 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20726 inst
.error
= _("immediate value out of range");
20728 inst
.instruction
= 0xec000f80;
20730 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20731 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20732 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20733 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20737 do_vldr_vstr (void)
20739 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20741 /* VLDR/VSTR (System Register). */
20744 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20745 as_bad (_("Instruction not permitted on this architecture"));
20747 do_t_vldr_vstr_sysreg ();
20752 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20753 as_bad (_("Instruction not permitted on this architecture"));
20754 do_neon_ldr_str ();
20758 /* "interleave" version also handles non-interleaving register VLD1/VST1
20762 do_neon_ld_st_interleave (void)
20764 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20765 N_8
| N_16
| N_32
| N_64
);
20766 unsigned alignbits
= 0;
20768 /* The bits in this table go:
20769 0: register stride of one (0) or two (1)
20770 1,2: register list length, minus one (1, 2, 3, 4).
20771 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20772 We use -1 for invalid entries. */
20773 const int typetable
[] =
20775 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20776 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20777 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20778 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20782 if (et
.type
== NT_invtype
)
20785 if (inst
.operands
[1].immisalign
)
20786 switch (inst
.operands
[1].imm
>> 8)
20788 case 64: alignbits
= 1; break;
20790 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20791 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20792 goto bad_alignment
;
20796 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20797 goto bad_alignment
;
20802 first_error (_("bad alignment"));
20806 inst
.instruction
|= alignbits
<< 4;
20807 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20809 /* Bits [4:6] of the immediate in a list specifier encode register stride
20810 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20811 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20812 up the right value for "type" in a table based on this value and the given
20813 list style, then stick it back. */
20814 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20815 | (((inst
.instruction
>> 8) & 3) << 3);
20817 typebits
= typetable
[idx
];
20819 constraint (typebits
== -1, _("bad list type for instruction"));
20820 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20823 inst
.instruction
&= ~0xf00;
20824 inst
.instruction
|= typebits
<< 8;
20827 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20828 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20829 otherwise. The variable arguments are a list of pairs of legal (size, align)
20830 values, terminated with -1. */
20833 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20836 int result
= FAIL
, thissize
, thisalign
;
20838 if (!inst
.operands
[1].immisalign
)
20844 va_start (ap
, do_alignment
);
20848 thissize
= va_arg (ap
, int);
20849 if (thissize
== -1)
20851 thisalign
= va_arg (ap
, int);
20853 if (size
== thissize
&& align
== thisalign
)
20856 while (result
!= SUCCESS
);
20860 if (result
== SUCCESS
)
20863 first_error (_("unsupported alignment for instruction"));
20869 do_neon_ld_st_lane (void)
20871 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20872 int align_good
, do_alignment
= 0;
20873 int logsize
= neon_logbits (et
.size
);
20874 int align
= inst
.operands
[1].imm
>> 8;
20875 int n
= (inst
.instruction
>> 8) & 3;
20876 int max_el
= 64 / et
.size
;
20878 if (et
.type
== NT_invtype
)
20881 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20882 _("bad list length"));
20883 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20884 _("scalar index out of range"));
20885 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20887 _("stride of 2 unavailable when element size is 8"));
20891 case 0: /* VLD1 / VST1. */
20892 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20894 if (align_good
== FAIL
)
20898 unsigned alignbits
= 0;
20901 case 16: alignbits
= 0x1; break;
20902 case 32: alignbits
= 0x3; break;
20905 inst
.instruction
|= alignbits
<< 4;
20909 case 1: /* VLD2 / VST2. */
20910 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20911 16, 32, 32, 64, -1);
20912 if (align_good
== FAIL
)
20915 inst
.instruction
|= 1 << 4;
20918 case 2: /* VLD3 / VST3. */
20919 constraint (inst
.operands
[1].immisalign
,
20920 _("can't use alignment with this instruction"));
20923 case 3: /* VLD4 / VST4. */
20924 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20925 16, 64, 32, 64, 32, 128, -1);
20926 if (align_good
== FAIL
)
20930 unsigned alignbits
= 0;
20933 case 8: alignbits
= 0x1; break;
20934 case 16: alignbits
= 0x1; break;
20935 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20938 inst
.instruction
|= alignbits
<< 4;
20945 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20946 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20947 inst
.instruction
|= 1 << (4 + logsize
);
20949 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20950 inst
.instruction
|= logsize
<< 10;
20953 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20956 do_neon_ld_dup (void)
20958 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20959 int align_good
, do_alignment
= 0;
20961 if (et
.type
== NT_invtype
)
20964 switch ((inst
.instruction
>> 8) & 3)
20966 case 0: /* VLD1. */
20967 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20968 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20969 &do_alignment
, 16, 16, 32, 32, -1);
20970 if (align_good
== FAIL
)
20972 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20975 case 2: inst
.instruction
|= 1 << 5; break;
20976 default: first_error (_("bad list length")); return;
20978 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20981 case 1: /* VLD2. */
20982 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20983 &do_alignment
, 8, 16, 16, 32, 32, 64,
20985 if (align_good
== FAIL
)
20987 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20988 _("bad list length"));
20989 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20990 inst
.instruction
|= 1 << 5;
20991 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20994 case 2: /* VLD3. */
20995 constraint (inst
.operands
[1].immisalign
,
20996 _("can't use alignment with this instruction"));
20997 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20998 _("bad list length"));
20999 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21000 inst
.instruction
|= 1 << 5;
21001 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21004 case 3: /* VLD4. */
21006 int align
= inst
.operands
[1].imm
>> 8;
21007 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
21008 16, 64, 32, 64, 32, 128, -1);
21009 if (align_good
== FAIL
)
21011 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
21012 _("bad list length"));
21013 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21014 inst
.instruction
|= 1 << 5;
21015 if (et
.size
== 32 && align
== 128)
21016 inst
.instruction
|= 0x3 << 6;
21018 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21025 inst
.instruction
|= do_alignment
<< 4;
21028 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
21029 apart from bits [11:4]. */
21032 do_neon_ldx_stx (void)
21034 if (inst
.operands
[1].isreg
)
21035 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
21037 switch (NEON_LANE (inst
.operands
[0].imm
))
21039 case NEON_INTERLEAVE_LANES
:
21040 NEON_ENCODE (INTERLV
, inst
);
21041 do_neon_ld_st_interleave ();
21044 case NEON_ALL_LANES
:
21045 NEON_ENCODE (DUP
, inst
);
21046 if (inst
.instruction
== N_INV
)
21048 first_error ("only loads support such operands");
21055 NEON_ENCODE (LANE
, inst
);
21056 do_neon_ld_st_lane ();
21059 /* L bit comes from bit mask. */
21060 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21061 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21062 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
21064 if (inst
.operands
[1].postind
)
21066 int postreg
= inst
.operands
[1].imm
& 0xf;
21067 constraint (!inst
.operands
[1].immisreg
,
21068 _("post-index must be a register"));
21069 constraint (postreg
== 0xd || postreg
== 0xf,
21070 _("bad register for post-index"));
21071 inst
.instruction
|= postreg
;
21075 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
21076 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
21077 || inst
.relocs
[0].exp
.X_add_number
!= 0,
21080 if (inst
.operands
[1].writeback
)
21082 inst
.instruction
|= 0xd;
21085 inst
.instruction
|= 0xf;
21089 inst
.instruction
|= 0xf9000000;
21091 inst
.instruction
|= 0xf4000000;
21096 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
21098 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21099 D register operands. */
21100 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21101 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21104 NEON_ENCODE (FPV8
, inst
);
21106 if (rs
== NS_FFF
|| rs
== NS_HHH
)
21108 do_vfp_sp_dyadic ();
21110 /* ARMv8.2 fp16 instruction. */
21112 do_scalar_fp16_v82_encode ();
21115 do_vfp_dp_rd_rn_rm ();
21118 inst
.instruction
|= 0x100;
21120 inst
.instruction
|= 0xf0000000;
21126 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21128 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
21129 first_error (_("invalid instruction shape"));
21135 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21136 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21138 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
21141 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21144 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
21148 do_vrint_1 (enum neon_cvt_mode mode
)
21150 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
21151 struct neon_type_el et
;
21156 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21157 D register operands. */
21158 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21159 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21162 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
21164 if (et
.type
!= NT_invtype
)
21166 /* VFP encodings. */
21167 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
21168 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
21169 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21171 NEON_ENCODE (FPV8
, inst
);
21172 if (rs
== NS_FF
|| rs
== NS_HH
)
21173 do_vfp_sp_monadic ();
21175 do_vfp_dp_rd_rm ();
21179 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
21180 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
21181 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
21182 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
21183 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
21184 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
21185 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
21189 inst
.instruction
|= (rs
== NS_DD
) << 8;
21190 do_vfp_cond_or_thumb ();
21192 /* ARMv8.2 fp16 vrint instruction. */
21194 do_scalar_fp16_v82_encode ();
21198 /* Neon encodings (or something broken...). */
21200 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
21202 if (et
.type
== NT_invtype
)
21205 if (!check_simd_pred_availability (TRUE
,
21206 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21209 NEON_ENCODE (FLOAT
, inst
);
21211 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21212 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21213 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21214 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21215 inst
.instruction
|= neon_quad (rs
) << 6;
21216 /* Mask off the original size bits and reencode them. */
21217 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
21218 | neon_logbits (et
.size
) << 18);
21222 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
21223 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
21224 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
21225 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
21226 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
21227 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
21228 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21233 inst
.instruction
|= 0xfc000000;
21235 inst
.instruction
|= 0xf0000000;
21242 do_vrint_1 (neon_cvt_mode_x
);
21248 do_vrint_1 (neon_cvt_mode_z
);
21254 do_vrint_1 (neon_cvt_mode_r
);
21260 do_vrint_1 (neon_cvt_mode_a
);
21266 do_vrint_1 (neon_cvt_mode_n
);
21272 do_vrint_1 (neon_cvt_mode_p
);
21278 do_vrint_1 (neon_cvt_mode_m
);
21282 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21284 unsigned regno
= NEON_SCALAR_REG (opnd
);
21285 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21287 if (elsize
== 16 && elno
< 2 && regno
< 16)
21288 return regno
| (elno
<< 4);
21289 else if (elsize
== 32 && elno
== 0)
21292 first_error (_("scalar out of range"));
21299 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21300 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21301 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21302 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21303 _("expression too complex"));
21304 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21305 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21306 _("immediate out of range"));
21309 if (!check_simd_pred_availability (TRUE
,
21310 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21313 if (inst
.operands
[2].isscalar
)
21315 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21316 first_error (_("invalid instruction shape"));
21317 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21318 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21319 N_KEY
| N_F16
| N_F32
).size
;
21320 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21322 inst
.instruction
= 0xfe000800;
21323 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21324 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21325 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21326 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21327 inst
.instruction
|= LOW4 (m
);
21328 inst
.instruction
|= HI1 (m
) << 5;
21329 inst
.instruction
|= neon_quad (rs
) << 6;
21330 inst
.instruction
|= rot
<< 20;
21331 inst
.instruction
|= (size
== 32) << 23;
21335 enum neon_shape rs
;
21336 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21337 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21339 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21341 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21342 N_KEY
| N_F16
| N_F32
).size
;
21343 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21344 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21345 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21346 as_tsktsk (BAD_MVE_SRCDEST
);
21348 neon_three_same (neon_quad (rs
), 0, -1);
21349 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21350 inst
.instruction
|= 0xfc200800;
21351 inst
.instruction
|= rot
<< 23;
21352 inst
.instruction
|= (size
== 32) << 20;
21359 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21360 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21361 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21362 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21363 _("expression too complex"));
21365 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21366 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21367 enum neon_shape rs
;
21368 struct neon_type_el et
;
21369 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21371 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21372 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21376 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21377 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21379 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21380 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21381 "operand makes instruction UNPREDICTABLE"));
21384 if (et
.type
== NT_invtype
)
21387 if (!check_simd_pred_availability (et
.type
== NT_float
,
21388 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21391 if (et
.type
== NT_float
)
21393 neon_three_same (neon_quad (rs
), 0, -1);
21394 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21395 inst
.instruction
|= 0xfc800800;
21396 inst
.instruction
|= (rot
== 270) << 24;
21397 inst
.instruction
|= (et
.size
== 32) << 20;
21401 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21402 inst
.instruction
= 0xfe000f00;
21403 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21404 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21405 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21406 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21407 inst
.instruction
|= (rot
== 270) << 12;
21408 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21409 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21410 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21415 /* Dot Product instructions encoding support. */
21418 do_neon_dotproduct (int unsigned_p
)
21420 enum neon_shape rs
;
21421 unsigned scalar_oprd2
= 0;
21424 if (inst
.cond
!= COND_ALWAYS
)
21425 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21426 "is UNPREDICTABLE"));
21428 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21431 /* Dot Product instructions are in three-same D/Q register format or the third
21432 operand can be a scalar index register. */
21433 if (inst
.operands
[2].isscalar
)
21435 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21436 high8
= 0xfe000000;
21437 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21441 high8
= 0xfc000000;
21442 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21446 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21448 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21450 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21451 Product instruction, so we pass 0 as the "ubit" parameter. And the
21452 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21453 neon_three_same (neon_quad (rs
), 0, 32);
21455 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21456 different NEON three-same encoding. */
21457 inst
.instruction
&= 0x00ffffff;
21458 inst
.instruction
|= high8
;
21459 /* Encode 'U' bit which indicates signedness. */
21460 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21461 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21462 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21463 the instruction encoding. */
21464 if (inst
.operands
[2].isscalar
)
21466 inst
.instruction
&= 0xffffffd0;
21467 inst
.instruction
|= LOW4 (scalar_oprd2
);
21468 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21472 /* Dot Product instructions for signed integer. */
21475 do_neon_dotproduct_s (void)
21477 return do_neon_dotproduct (0);
21480 /* Dot Product instructions for unsigned integer. */
21483 do_neon_dotproduct_u (void)
21485 return do_neon_dotproduct (1);
21491 enum neon_shape rs
;
21492 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21493 if (inst
.operands
[2].isscalar
)
21495 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21496 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21498 inst
.instruction
|= (1 << 25);
21499 int index
= inst
.operands
[2].reg
& 0xf;
21500 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21501 inst
.operands
[2].reg
>>= 4;
21502 constraint (!(inst
.operands
[2].reg
< 16),
21503 _("indexed register must be less than 16"));
21504 neon_three_args (rs
== NS_QQS
);
21505 inst
.instruction
|= (index
<< 5);
21509 inst
.instruction
|= (1 << 21);
21510 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21511 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21512 neon_three_args (rs
== NS_QQQ
);
21519 enum neon_shape rs
;
21520 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21521 if (inst
.operands
[2].isscalar
)
21523 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21524 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21526 inst
.instruction
|= (1 << 25);
21527 int index
= inst
.operands
[2].reg
& 0xf;
21528 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21529 inst
.operands
[2].reg
>>= 4;
21530 constraint (!(inst
.operands
[2].reg
< 16),
21531 _("indexed register must be less than 16"));
21532 neon_three_args (rs
== NS_QQS
);
21533 inst
.instruction
|= (index
<< 5);
21540 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21541 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21543 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21545 neon_three_args (1);
21552 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21553 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21555 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21557 neon_three_args (1);
21561 /* Crypto v1 instructions. */
21563 do_crypto_2op_1 (unsigned elttype
, int op
)
21565 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21567 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
21573 NEON_ENCODE (INTEGER
, inst
);
21574 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21575 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21576 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21577 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21579 inst
.instruction
|= op
<< 6;
21582 inst
.instruction
|= 0xfc000000;
21584 inst
.instruction
|= 0xf0000000;
21588 do_crypto_3op_1 (int u
, int op
)
21590 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21592 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
21593 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
21598 NEON_ENCODE (INTEGER
, inst
);
21599 neon_three_same (1, u
, 8 << op
);
21605 do_crypto_2op_1 (N_8
, 0);
21611 do_crypto_2op_1 (N_8
, 1);
21617 do_crypto_2op_1 (N_8
, 2);
21623 do_crypto_2op_1 (N_8
, 3);
21629 do_crypto_3op_1 (0, 0);
21635 do_crypto_3op_1 (0, 1);
21641 do_crypto_3op_1 (0, 2);
21647 do_crypto_3op_1 (0, 3);
21653 do_crypto_3op_1 (1, 0);
21659 do_crypto_3op_1 (1, 1);
21663 do_sha256su1 (void)
21665 do_crypto_3op_1 (1, 2);
21671 do_crypto_2op_1 (N_32
, -1);
21677 do_crypto_2op_1 (N_32
, 0);
21681 do_sha256su0 (void)
21683 do_crypto_2op_1 (N_32
, 1);
21687 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21689 unsigned int Rd
= inst
.operands
[0].reg
;
21690 unsigned int Rn
= inst
.operands
[1].reg
;
21691 unsigned int Rm
= inst
.operands
[2].reg
;
21693 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21694 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21695 inst
.instruction
|= LOW4 (Rn
) << 16;
21696 inst
.instruction
|= LOW4 (Rm
);
21697 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21698 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21700 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21701 as_warn (UNPRED_REG ("r15"));
21743 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21745 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21746 do_vfp_sp_dp_cvt ();
21747 do_vfp_cond_or_thumb ();
21753 enum neon_shape rs
;
21754 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
21755 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21756 if (inst
.operands
[2].isscalar
)
21758 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21759 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
21761 inst
.instruction
|= (1 << 25);
21762 int index
= inst
.operands
[2].reg
& 0xf;
21763 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21764 inst
.operands
[2].reg
>>= 4;
21765 constraint (!(inst
.operands
[2].reg
< 16),
21766 _("indexed register must be less than 16"));
21767 neon_three_args (rs
== NS_QQS
);
21768 inst
.instruction
|= (index
<< 5);
21772 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21773 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
21774 neon_three_args (rs
== NS_QQQ
);
21781 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21782 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
21784 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
21785 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21787 neon_three_args (1);
21791 /* Overall per-instruction processing. */
21793 /* We need to be able to fix up arbitrary expressions in some statements.
21794 This is so that we can handle symbols that are an arbitrary distance from
21795 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21796 which returns part of an address in a form which will be valid for
21797 a data instruction. We do this by pushing the expression into a symbol
21798 in the expr_section, and creating a fix for that. */
21801 fix_new_arm (fragS
* frag
,
21815 /* Create an absolute valued symbol, so we have something to
21816 refer to in the object file. Unfortunately for us, gas's
21817 generic expression parsing will already have folded out
21818 any use of .set foo/.type foo %function that may have
21819 been used to set type information of the target location,
21820 that's being specified symbolically. We have to presume
21821 the user knows what they are doing. */
21825 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21827 symbol
= symbol_find_or_make (name
);
21828 S_SET_SEGMENT (symbol
, absolute_section
);
21829 symbol_set_frag (symbol
, &zero_address_frag
);
21830 S_SET_VALUE (symbol
, exp
->X_add_number
);
21831 exp
->X_op
= O_symbol
;
21832 exp
->X_add_symbol
= symbol
;
21833 exp
->X_add_number
= 0;
21839 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21840 (enum bfd_reloc_code_real
) reloc
);
21844 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21845 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21849 /* Mark whether the fix is to a THUMB instruction, or an ARM
21851 new_fix
->tc_fix_data
= thumb_mode
;
21854 /* Create a frg for an instruction requiring relaxation. */
21856 output_relax_insn (void)
21862 /* The size of the instruction is unknown, so tie the debug info to the
21863 start of the instruction. */
21864 dwarf2_emit_insn (0);
21866 switch (inst
.relocs
[0].exp
.X_op
)
21869 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21870 offset
= inst
.relocs
[0].exp
.X_add_number
;
21874 offset
= inst
.relocs
[0].exp
.X_add_number
;
21877 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21881 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21882 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21883 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21886 /* Write a 32-bit thumb instruction to buf. */
21888 put_thumb32_insn (char * buf
, unsigned long insn
)
21890 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21891 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21895 output_inst (const char * str
)
21901 as_bad ("%s -- `%s'", inst
.error
, str
);
21906 output_relax_insn ();
21909 if (inst
.size
== 0)
21912 to
= frag_more (inst
.size
);
21913 /* PR 9814: Record the thumb mode into the current frag so that we know
21914 what type of NOP padding to use, if necessary. We override any previous
21915 setting so that if the mode has changed then the NOPS that we use will
21916 match the encoding of the last instruction in the frag. */
21917 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21919 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21921 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21922 put_thumb32_insn (to
, inst
.instruction
);
21924 else if (inst
.size
> INSN_SIZE
)
21926 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21927 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21928 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21931 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21934 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21936 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21937 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21938 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21939 inst
.relocs
[r
].type
);
21942 dwarf2_emit_insn (inst
.size
);
21946 output_it_inst (int cond
, int mask
, char * to
)
21948 unsigned long instruction
= 0xbf00;
21951 instruction
|= mask
;
21952 instruction
|= cond
<< 4;
21956 to
= frag_more (2);
21958 dwarf2_emit_insn (2);
21962 md_number_to_chars (to
, instruction
, 2);
21967 /* Tag values used in struct asm_opcode's tag field. */
21970 OT_unconditional
, /* Instruction cannot be conditionalized.
21971 The ARM condition field is still 0xE. */
21972 OT_unconditionalF
, /* Instruction cannot be conditionalized
21973 and carries 0xF in its ARM condition field. */
21974 OT_csuffix
, /* Instruction takes a conditional suffix. */
21975 OT_csuffixF
, /* Some forms of the instruction take a scalar
21976 conditional suffix, others place 0xF where the
21977 condition field would be, others take a vector
21978 conditional suffix. */
21979 OT_cinfix3
, /* Instruction takes a conditional infix,
21980 beginning at character index 3. (In
21981 unified mode, it becomes a suffix.) */
21982 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21983 tsts, cmps, cmns, and teqs. */
21984 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21985 character index 3, even in unified mode. Used for
21986 legacy instructions where suffix and infix forms
21987 may be ambiguous. */
21988 OT_csuf_or_in3
, /* Instruction takes either a conditional
21989 suffix or an infix at character index 3. */
21990 OT_odd_infix_unc
, /* This is the unconditional variant of an
21991 instruction that takes a conditional infix
21992 at an unusual position. In unified mode,
21993 this variant will accept a suffix. */
21994 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21995 are the conditional variants of instructions that
21996 take conditional infixes in unusual positions.
21997 The infix appears at character index
21998 (tag - OT_odd_infix_0). These are not accepted
21999 in unified mode. */
22002 /* Subroutine of md_assemble, responsible for looking up the primary
22003 opcode from the mnemonic the user wrote. STR points to the
22004 beginning of the mnemonic.
22006 This is not simply a hash table lookup, because of conditional
22007 variants. Most instructions have conditional variants, which are
22008 expressed with a _conditional affix_ to the mnemonic. If we were
22009 to encode each conditional variant as a literal string in the opcode
22010 table, it would have approximately 20,000 entries.
22012 Most mnemonics take this affix as a suffix, and in unified syntax,
22013 'most' is upgraded to 'all'. However, in the divided syntax, some
22014 instructions take the affix as an infix, notably the s-variants of
22015 the arithmetic instructions. Of those instructions, all but six
22016 have the infix appear after the third character of the mnemonic.
22018 Accordingly, the algorithm for looking up primary opcodes given
22021 1. Look up the identifier in the opcode table.
22022 If we find a match, go to step U.
22024 2. Look up the last two characters of the identifier in the
22025 conditions table. If we find a match, look up the first N-2
22026 characters of the identifier in the opcode table. If we
22027 find a match, go to step CE.
22029 3. Look up the fourth and fifth characters of the identifier in
22030 the conditions table. If we find a match, extract those
22031 characters from the identifier, and look up the remaining
22032 characters in the opcode table. If we find a match, go
22037 U. Examine the tag field of the opcode structure, in case this is
22038 one of the six instructions with its conditional infix in an
22039 unusual place. If it is, the tag tells us where to find the
22040 infix; look it up in the conditions table and set inst.cond
22041 accordingly. Otherwise, this is an unconditional instruction.
22042 Again set inst.cond accordingly. Return the opcode structure.
22044 CE. Examine the tag field to make sure this is an instruction that
22045 should receive a conditional suffix. If it is not, fail.
22046 Otherwise, set inst.cond from the suffix we already looked up,
22047 and return the opcode structure.
22049 CM. Examine the tag field to make sure this is an instruction that
22050 should receive a conditional infix after the third character.
22051 If it is not, fail. Otherwise, undo the edits to the current
22052 line of input and proceed as for case CE. */
22054 static const struct asm_opcode
*
22055 opcode_lookup (char **str
)
22059 const struct asm_opcode
*opcode
;
22060 const struct asm_cond
*cond
;
22063 /* Scan up to the end of the mnemonic, which must end in white space,
22064 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
22065 for (base
= end
= *str
; *end
!= '\0'; end
++)
22066 if (*end
== ' ' || *end
== '.')
22072 /* Handle a possible width suffix and/or Neon type suffix. */
22077 /* The .w and .n suffixes are only valid if the unified syntax is in
22079 if (unified_syntax
&& end
[1] == 'w')
22081 else if (unified_syntax
&& end
[1] == 'n')
22086 inst
.vectype
.elems
= 0;
22088 *str
= end
+ offset
;
22090 if (end
[offset
] == '.')
22092 /* See if we have a Neon type suffix (possible in either unified or
22093 non-unified ARM syntax mode). */
22094 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
22097 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
22103 /* Look for unaffixed or special-case affixed mnemonic. */
22104 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22109 if (opcode
->tag
< OT_odd_infix_0
)
22111 inst
.cond
= COND_ALWAYS
;
22115 if (warn_on_deprecated
&& unified_syntax
)
22116 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22117 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
22118 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22121 inst
.cond
= cond
->value
;
22124 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
22126 /* Cannot have a conditional suffix on a mnemonic of less than a character.
22128 if (end
- base
< 2)
22131 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
22132 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22134 /* If this opcode can not be vector predicated then don't accept it with a
22135 vector predication code. */
22136 if (opcode
&& !opcode
->mayBeVecPred
)
22139 if (!opcode
|| !cond
)
22141 /* Cannot have a conditional suffix on a mnemonic of less than two
22143 if (end
- base
< 3)
22146 /* Look for suffixed mnemonic. */
22148 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22149 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22153 if (opcode
&& cond
)
22156 switch (opcode
->tag
)
22158 case OT_cinfix3_legacy
:
22159 /* Ignore conditional suffixes matched on infix only mnemonics. */
22163 case OT_cinfix3_deprecated
:
22164 case OT_odd_infix_unc
:
22165 if (!unified_syntax
)
22167 /* Fall through. */
22171 case OT_csuf_or_in3
:
22172 inst
.cond
= cond
->value
;
22175 case OT_unconditional
:
22176 case OT_unconditionalF
:
22178 inst
.cond
= cond
->value
;
22181 /* Delayed diagnostic. */
22182 inst
.error
= BAD_COND
;
22183 inst
.cond
= COND_ALWAYS
;
22192 /* Cannot have a usual-position infix on a mnemonic of less than
22193 six characters (five would be a suffix). */
22194 if (end
- base
< 6)
22197 /* Look for infixed mnemonic in the usual position. */
22199 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22203 memcpy (save
, affix
, 2);
22204 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
22205 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22207 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
22208 memcpy (affix
, save
, 2);
22211 && (opcode
->tag
== OT_cinfix3
22212 || opcode
->tag
== OT_cinfix3_deprecated
22213 || opcode
->tag
== OT_csuf_or_in3
22214 || opcode
->tag
== OT_cinfix3_legacy
))
22217 if (warn_on_deprecated
&& unified_syntax
22218 && (opcode
->tag
== OT_cinfix3
22219 || opcode
->tag
== OT_cinfix3_deprecated
))
22220 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22222 inst
.cond
= cond
->value
;
22229 /* This function generates an initial IT instruction, leaving its block
22230 virtually open for the new instructions. Eventually,
22231 the mask will be updated by now_pred_add_mask () each time
22232 a new instruction needs to be included in the IT block.
22233 Finally, the block is closed with close_automatic_it_block ().
22234 The block closure can be requested either from md_assemble (),
22235 a tencode (), or due to a label hook. */
22238 new_automatic_it_block (int cond
)
22240 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
22241 now_pred
.mask
= 0x18;
22242 now_pred
.cc
= cond
;
22243 now_pred
.block_length
= 1;
22244 mapping_state (MAP_THUMB
);
22245 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
22246 now_pred
.warn_deprecated
= FALSE
;
22247 now_pred
.insn_cond
= TRUE
;
22250 /* Close an automatic IT block.
22251 See comments in new_automatic_it_block (). */
22254 close_automatic_it_block (void)
22256 now_pred
.mask
= 0x10;
22257 now_pred
.block_length
= 0;
22260 /* Update the mask of the current automatically-generated IT
22261 instruction. See comments in new_automatic_it_block (). */
22264 now_pred_add_mask (int cond
)
22266 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
22267 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
22268 | ((bitvalue) << (nbit)))
22269 const int resulting_bit
= (cond
& 1);
22271 now_pred
.mask
&= 0xf;
22272 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22274 (5 - now_pred
.block_length
));
22275 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22277 ((5 - now_pred
.block_length
) - 1));
22278 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
22281 #undef SET_BIT_VALUE
22284 /* The IT blocks handling machinery is accessed through the these functions:
22285 it_fsm_pre_encode () from md_assemble ()
22286 set_pred_insn_type () optional, from the tencode functions
22287 set_pred_insn_type_last () ditto
22288 in_pred_block () ditto
22289 it_fsm_post_encode () from md_assemble ()
22290 force_automatic_it_block_close () from label handling functions
22293 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22294 initializing the IT insn type with a generic initial value depending
22295 on the inst.condition.
22296 2) During the tencode function, two things may happen:
22297 a) The tencode function overrides the IT insn type by
22298 calling either set_pred_insn_type (type) or
22299 set_pred_insn_type_last ().
22300 b) The tencode function queries the IT block state by
22301 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22303 Both set_pred_insn_type and in_pred_block run the internal FSM state
22304 handling function (handle_pred_state), because: a) setting the IT insn
22305 type may incur in an invalid state (exiting the function),
22306 and b) querying the state requires the FSM to be updated.
22307 Specifically we want to avoid creating an IT block for conditional
22308 branches, so it_fsm_pre_encode is actually a guess and we can't
22309 determine whether an IT block is required until the tencode () routine
22310 has decided what type of instruction this actually it.
22311 Because of this, if set_pred_insn_type and in_pred_block have to be
22312 used, set_pred_insn_type has to be called first.
22314 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22315 that determines the insn IT type depending on the inst.cond code.
22316 When a tencode () routine encodes an instruction that can be
22317 either outside an IT block, or, in the case of being inside, has to be
22318 the last one, set_pred_insn_type_last () will determine the proper
22319 IT instruction type based on the inst.cond code. Otherwise,
22320 set_pred_insn_type can be called for overriding that logic or
22321 for covering other cases.
22323 Calling handle_pred_state () may not transition the IT block state to
22324 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22325 still queried. Instead, if the FSM determines that the state should
22326 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22327 after the tencode () function: that's what it_fsm_post_encode () does.
22329 Since in_pred_block () calls the state handling function to get an
22330 updated state, an error may occur (due to invalid insns combination).
22331 In that case, inst.error is set.
22332 Therefore, inst.error has to be checked after the execution of
22333 the tencode () routine.
22335 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22336 any pending state change (if any) that didn't take place in
22337 handle_pred_state () as explained above. */
22340 it_fsm_pre_encode (void)
22342 if (inst
.cond
!= COND_ALWAYS
)
22343 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22345 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22347 now_pred
.state_handled
= 0;
22350 /* IT state FSM handling function. */
22351 /* MVE instructions and non-MVE instructions are handled differently because of
22352 the introduction of VPT blocks.
22353 Specifications say that any non-MVE instruction inside a VPT block is
22354 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22355 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22356 few exceptions we have MVE_UNPREDICABLE_INSN.
22357 The error messages provided depending on the different combinations possible
22358 are described in the cases below:
22359 For 'most' MVE instructions:
22360 1) In an IT block, with an IT code: syntax error
22361 2) In an IT block, with a VPT code: error: must be in a VPT block
22362 3) In an IT block, with no code: warning: UNPREDICTABLE
22363 4) In a VPT block, with an IT code: syntax error
22364 5) In a VPT block, with a VPT code: OK!
22365 6) In a VPT block, with no code: error: missing code
22366 7) Outside a pred block, with an IT code: error: syntax error
22367 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22368 9) Outside a pred block, with no code: OK!
22369 For non-MVE instructions:
22370 10) In an IT block, with an IT code: OK!
22371 11) In an IT block, with a VPT code: syntax error
22372 12) In an IT block, with no code: error: missing code
22373 13) In a VPT block, with an IT code: error: should be in an IT block
22374 14) In a VPT block, with a VPT code: syntax error
22375 15) In a VPT block, with no code: UNPREDICTABLE
22376 16) Outside a pred block, with an IT code: error: should be in an IT block
22377 17) Outside a pred block, with a VPT code: syntax error
22378 18) Outside a pred block, with no code: OK!
22383 handle_pred_state (void)
22385 now_pred
.state_handled
= 1;
22386 now_pred
.insn_cond
= FALSE
;
22388 switch (now_pred
.state
)
22390 case OUTSIDE_PRED_BLOCK
:
22391 switch (inst
.pred_insn_type
)
22393 case MVE_UNPREDICABLE_INSN
:
22394 case MVE_OUTSIDE_PRED_INSN
:
22395 if (inst
.cond
< COND_ALWAYS
)
22397 /* Case 7: Outside a pred block, with an IT code: error: syntax
22399 inst
.error
= BAD_SYNTAX
;
22402 /* Case 9: Outside a pred block, with no code: OK! */
22404 case OUTSIDE_PRED_INSN
:
22405 if (inst
.cond
> COND_ALWAYS
)
22407 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22409 inst
.error
= BAD_SYNTAX
;
22412 /* Case 18: Outside a pred block, with no code: OK! */
22415 case INSIDE_VPT_INSN
:
22416 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22418 inst
.error
= BAD_OUT_VPT
;
22421 case INSIDE_IT_INSN
:
22422 case INSIDE_IT_LAST_INSN
:
22423 if (inst
.cond
< COND_ALWAYS
)
22425 /* Case 16: Outside a pred block, with an IT code: error: should
22426 be in an IT block. */
22427 if (thumb_mode
== 0)
22430 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22431 as_tsktsk (_("Warning: conditional outside an IT block"\
22436 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22437 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22439 /* Automatically generate the IT instruction. */
22440 new_automatic_it_block (inst
.cond
);
22441 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22442 close_automatic_it_block ();
22446 inst
.error
= BAD_OUT_IT
;
22452 else if (inst
.cond
> COND_ALWAYS
)
22454 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22456 inst
.error
= BAD_SYNTAX
;
22461 case IF_INSIDE_IT_LAST_INSN
:
22462 case NEUTRAL_IT_INSN
:
22466 if (inst
.cond
!= COND_ALWAYS
)
22467 first_error (BAD_SYNTAX
);
22468 now_pred
.state
= MANUAL_PRED_BLOCK
;
22469 now_pred
.block_length
= 0;
22470 now_pred
.type
= VECTOR_PRED
;
22474 now_pred
.state
= MANUAL_PRED_BLOCK
;
22475 now_pred
.block_length
= 0;
22476 now_pred
.type
= SCALAR_PRED
;
22481 case AUTOMATIC_PRED_BLOCK
:
22482 /* Three things may happen now:
22483 a) We should increment current it block size;
22484 b) We should close current it block (closing insn or 4 insns);
22485 c) We should close current it block and start a new one (due
22486 to incompatible conditions or
22487 4 insns-length block reached). */
22489 switch (inst
.pred_insn_type
)
22491 case INSIDE_VPT_INSN
:
22493 case MVE_UNPREDICABLE_INSN
:
22494 case MVE_OUTSIDE_PRED_INSN
:
22496 case OUTSIDE_PRED_INSN
:
22497 /* The closure of the block shall happen immediately,
22498 so any in_pred_block () call reports the block as closed. */
22499 force_automatic_it_block_close ();
22502 case INSIDE_IT_INSN
:
22503 case INSIDE_IT_LAST_INSN
:
22504 case IF_INSIDE_IT_LAST_INSN
:
22505 now_pred
.block_length
++;
22507 if (now_pred
.block_length
> 4
22508 || !now_pred_compatible (inst
.cond
))
22510 force_automatic_it_block_close ();
22511 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
22512 new_automatic_it_block (inst
.cond
);
22516 now_pred
.insn_cond
= TRUE
;
22517 now_pred_add_mask (inst
.cond
);
22520 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
22521 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
22522 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
22523 close_automatic_it_block ();
22526 case NEUTRAL_IT_INSN
:
22527 now_pred
.block_length
++;
22528 now_pred
.insn_cond
= TRUE
;
22530 if (now_pred
.block_length
> 4)
22531 force_automatic_it_block_close ();
22533 now_pred_add_mask (now_pred
.cc
& 1);
22537 close_automatic_it_block ();
22538 now_pred
.state
= MANUAL_PRED_BLOCK
;
22543 case MANUAL_PRED_BLOCK
:
22546 if (now_pred
.type
== SCALAR_PRED
)
22548 /* Check conditional suffixes. */
22549 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
22550 now_pred
.mask
<<= 1;
22551 now_pred
.mask
&= 0x1f;
22552 is_last
= (now_pred
.mask
== 0x10);
22556 now_pred
.cc
^= (now_pred
.mask
>> 4);
22557 cond
= now_pred
.cc
+ 0xf;
22558 now_pred
.mask
<<= 1;
22559 now_pred
.mask
&= 0x1f;
22560 is_last
= now_pred
.mask
== 0x10;
22562 now_pred
.insn_cond
= TRUE
;
22564 switch (inst
.pred_insn_type
)
22566 case OUTSIDE_PRED_INSN
:
22567 if (now_pred
.type
== SCALAR_PRED
)
22569 if (inst
.cond
== COND_ALWAYS
)
22571 /* Case 12: In an IT block, with no code: error: missing
22573 inst
.error
= BAD_NOT_IT
;
22576 else if (inst
.cond
> COND_ALWAYS
)
22578 /* Case 11: In an IT block, with a VPT code: syntax error.
22580 inst
.error
= BAD_SYNTAX
;
22583 else if (thumb_mode
)
22585 /* This is for some special cases where a non-MVE
22586 instruction is not allowed in an IT block, such as cbz,
22587 but are put into one with a condition code.
22588 You could argue this should be a syntax error, but we
22589 gave the 'not allowed in IT block' diagnostic in the
22590 past so we will keep doing so. */
22591 inst
.error
= BAD_NOT_IT
;
22598 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22599 as_tsktsk (MVE_NOT_VPT
);
22602 case MVE_OUTSIDE_PRED_INSN
:
22603 if (now_pred
.type
== SCALAR_PRED
)
22605 if (inst
.cond
== COND_ALWAYS
)
22607 /* Case 3: In an IT block, with no code: warning:
22609 as_tsktsk (MVE_NOT_IT
);
22612 else if (inst
.cond
< COND_ALWAYS
)
22614 /* Case 1: In an IT block, with an IT code: syntax error.
22616 inst
.error
= BAD_SYNTAX
;
22624 if (inst
.cond
< COND_ALWAYS
)
22626 /* Case 4: In a VPT block, with an IT code: syntax error.
22628 inst
.error
= BAD_SYNTAX
;
22631 else if (inst
.cond
== COND_ALWAYS
)
22633 /* Case 6: In a VPT block, with no code: error: missing
22635 inst
.error
= BAD_NOT_VPT
;
22643 case MVE_UNPREDICABLE_INSN
:
22644 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
22646 case INSIDE_IT_INSN
:
22647 if (inst
.cond
> COND_ALWAYS
)
22649 /* Case 11: In an IT block, with a VPT code: syntax error. */
22650 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22651 inst
.error
= BAD_SYNTAX
;
22654 else if (now_pred
.type
== SCALAR_PRED
)
22656 /* Case 10: In an IT block, with an IT code: OK! */
22657 if (cond
!= inst
.cond
)
22659 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
22666 /* Case 13: In a VPT block, with an IT code: error: should be
22668 inst
.error
= BAD_OUT_IT
;
22673 case INSIDE_VPT_INSN
:
22674 if (now_pred
.type
== SCALAR_PRED
)
22676 /* Case 2: In an IT block, with a VPT code: error: must be in a
22678 inst
.error
= BAD_OUT_VPT
;
22681 /* Case 5: In a VPT block, with a VPT code: OK! */
22682 else if (cond
!= inst
.cond
)
22684 inst
.error
= BAD_VPT_COND
;
22688 case INSIDE_IT_LAST_INSN
:
22689 case IF_INSIDE_IT_LAST_INSN
:
22690 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22692 /* Case 4: In a VPT block, with an IT code: syntax error. */
22693 /* Case 11: In an IT block, with a VPT code: syntax error. */
22694 inst
.error
= BAD_SYNTAX
;
22697 else if (cond
!= inst
.cond
)
22699 inst
.error
= BAD_IT_COND
;
22704 inst
.error
= BAD_BRANCH
;
22709 case NEUTRAL_IT_INSN
:
22710 /* The BKPT instruction is unconditional even in a IT or VPT
22715 if (now_pred
.type
== SCALAR_PRED
)
22717 inst
.error
= BAD_IT_IT
;
22720 /* fall through. */
22722 if (inst
.cond
== COND_ALWAYS
)
22724 /* Executing a VPT/VPST instruction inside an IT block or a
22725 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22727 if (now_pred
.type
== SCALAR_PRED
)
22728 as_tsktsk (MVE_NOT_IT
);
22730 as_tsktsk (MVE_NOT_VPT
);
22735 /* VPT/VPST do not accept condition codes. */
22736 inst
.error
= BAD_SYNTAX
;
22747 struct depr_insn_mask
22749 unsigned long pattern
;
22750 unsigned long mask
;
22751 const char* description
;
22754 /* List of 16-bit instruction patterns deprecated in an IT block in
22756 static const struct depr_insn_mask depr_it_insns
[] = {
22757 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22758 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22759 { 0xa000, 0xb800, N_("ADR") },
22760 { 0x4800, 0xf800, N_("Literal loads") },
22761 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22762 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22763 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22764 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22765 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22770 it_fsm_post_encode (void)
22774 if (!now_pred
.state_handled
)
22775 handle_pred_state ();
22777 if (now_pred
.insn_cond
22778 && !now_pred
.warn_deprecated
22779 && warn_on_deprecated
22780 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22781 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22783 if (inst
.instruction
>= 0x10000)
22785 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22786 "performance deprecated in ARMv8-A and ARMv8-R"));
22787 now_pred
.warn_deprecated
= TRUE
;
22791 const struct depr_insn_mask
*p
= depr_it_insns
;
22793 while (p
->mask
!= 0)
22795 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22797 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22798 "instructions of the following class are "
22799 "performance deprecated in ARMv8-A and "
22800 "ARMv8-R: %s"), p
->description
);
22801 now_pred
.warn_deprecated
= TRUE
;
22809 if (now_pred
.block_length
> 1)
22811 as_tsktsk (_("IT blocks containing more than one conditional "
22812 "instruction are performance deprecated in ARMv8-A and "
22814 now_pred
.warn_deprecated
= TRUE
;
22818 is_last
= (now_pred
.mask
== 0x10);
22821 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22827 force_automatic_it_block_close (void)
22829 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22831 close_automatic_it_block ();
22832 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22838 in_pred_block (void)
22840 if (!now_pred
.state_handled
)
22841 handle_pred_state ();
22843 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22846 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22847 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22848 here, hence the "known" in the function name. */
22851 known_t32_only_insn (const struct asm_opcode
*opcode
)
22853 /* Original Thumb-1 wide instruction. */
22854 if (opcode
->tencode
== do_t_blx
22855 || opcode
->tencode
== do_t_branch23
22856 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22857 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22860 /* Wide-only instruction added to ARMv8-M Baseline. */
22861 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22862 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22863 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22864 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22870 /* Whether wide instruction variant can be used if available for a valid OPCODE
22874 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22876 if (known_t32_only_insn (opcode
))
22879 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22880 of variant T3 of B.W is checked in do_t_branch. */
22881 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22882 && opcode
->tencode
== do_t_branch
)
22885 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22886 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22887 && opcode
->tencode
== do_t_mov_cmp
22888 /* Make sure CMP instruction is not affected. */
22889 && opcode
->aencode
== do_mov
)
22892 /* Wide instruction variants of all instructions with narrow *and* wide
22893 variants become available with ARMv6t2. Other opcodes are either
22894 narrow-only or wide-only and are thus available if OPCODE is valid. */
22895 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22898 /* OPCODE with narrow only instruction variant or wide variant not
22904 md_assemble (char *str
)
22907 const struct asm_opcode
* opcode
;
22909 /* Align the previous label if needed. */
22910 if (last_label_seen
!= NULL
)
22912 symbol_set_frag (last_label_seen
, frag_now
);
22913 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22914 S_SET_SEGMENT (last_label_seen
, now_seg
);
22917 memset (&inst
, '\0', sizeof (inst
));
22919 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22920 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22922 opcode
= opcode_lookup (&p
);
22925 /* It wasn't an instruction, but it might be a register alias of
22926 the form alias .req reg, or a Neon .dn/.qn directive. */
22927 if (! create_register_alias (str
, p
)
22928 && ! create_neon_reg_alias (str
, p
))
22929 as_bad (_("bad instruction `%s'"), str
);
22934 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22935 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22937 /* The value which unconditional instructions should have in place of the
22938 condition field. */
22939 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22943 arm_feature_set variant
;
22945 variant
= cpu_variant
;
22946 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22947 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22948 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22949 /* Check that this instruction is supported for this CPU. */
22950 if (!opcode
->tvariant
22951 || (thumb_mode
== 1
22952 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22954 if (opcode
->tencode
== do_t_swi
)
22955 as_bad (_("SVC is not permitted on this architecture"));
22957 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22960 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22961 && opcode
->tencode
!= do_t_branch
)
22963 as_bad (_("Thumb does not support conditional execution"));
22967 /* Two things are addressed here:
22968 1) Implicit require narrow instructions on Thumb-1.
22969 This avoids relaxation accidentally introducing Thumb-2
22971 2) Reject wide instructions in non Thumb-2 cores.
22973 Only instructions with narrow and wide variants need to be handled
22974 but selecting all non wide-only instructions is easier. */
22975 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22976 && !t32_insn_ok (variant
, opcode
))
22978 if (inst
.size_req
== 0)
22980 else if (inst
.size_req
== 4)
22982 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22983 as_bad (_("selected processor does not support 32bit wide "
22984 "variant of instruction `%s'"), str
);
22986 as_bad (_("selected processor does not support `%s' in "
22987 "Thumb-2 mode"), str
);
22992 inst
.instruction
= opcode
->tvalue
;
22994 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22996 /* Prepare the pred_insn_type for those encodings that don't set
22998 it_fsm_pre_encode ();
23000 opcode
->tencode ();
23002 it_fsm_post_encode ();
23005 if (!(inst
.error
|| inst
.relax
))
23007 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
23008 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
23009 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
23011 as_bad (_("cannot honor width suffix -- `%s'"), str
);
23016 /* Something has gone badly wrong if we try to relax a fixed size
23018 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
23020 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23021 *opcode
->tvariant
);
23022 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
23023 set those bits when Thumb-2 32-bit instructions are seen. The impact
23024 of relaxable instructions will be considered later after we finish all
23026 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
23027 variant
= arm_arch_none
;
23029 variant
= cpu_variant
;
23030 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
23031 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23034 check_neon_suffixes
;
23038 mapping_state (MAP_THUMB
);
23041 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23045 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23046 is_bx
= (opcode
->aencode
== do_bx
);
23048 /* Check that this instruction is supported for this CPU. */
23049 if (!(is_bx
&& fix_v4bx
)
23050 && !(opcode
->avariant
&&
23051 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
23053 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
23058 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
23062 inst
.instruction
= opcode
->avalue
;
23063 if (opcode
->tag
== OT_unconditionalF
)
23064 inst
.instruction
|= 0xFU
<< 28;
23066 inst
.instruction
|= inst
.cond
<< 28;
23067 inst
.size
= INSN_SIZE
;
23068 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
23070 it_fsm_pre_encode ();
23071 opcode
->aencode ();
23072 it_fsm_post_encode ();
23074 /* Arm mode bx is marked as both v4T and v5 because it's still required
23075 on a hypothetical non-thumb v5 core. */
23077 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
23079 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
23080 *opcode
->avariant
);
23082 check_neon_suffixes
;
23086 mapping_state (MAP_ARM
);
23091 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
23099 check_pred_blocks_finished (void)
23104 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
23105 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
23106 == MANUAL_PRED_BLOCK
)
23108 if (now_pred
.type
== SCALAR_PRED
)
23109 as_warn (_("section '%s' finished with an open IT block."),
23112 as_warn (_("section '%s' finished with an open VPT/VPST block."),
23116 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
23118 if (now_pred
.type
== SCALAR_PRED
)
23119 as_warn (_("file finished with an open IT block."));
23121 as_warn (_("file finished with an open VPT/VPST block."));
23126 /* Various frobbings of labels and their addresses. */
23129 arm_start_line_hook (void)
23131 last_label_seen
= NULL
;
23135 arm_frob_label (symbolS
* sym
)
23137 last_label_seen
= sym
;
23139 ARM_SET_THUMB (sym
, thumb_mode
);
23141 #if defined OBJ_COFF || defined OBJ_ELF
23142 ARM_SET_INTERWORK (sym
, support_interwork
);
23145 force_automatic_it_block_close ();
23147 /* Note - do not allow local symbols (.Lxxx) to be labelled
23148 as Thumb functions. This is because these labels, whilst
23149 they exist inside Thumb code, are not the entry points for
23150 possible ARM->Thumb calls. Also, these labels can be used
23151 as part of a computed goto or switch statement. eg gcc
23152 can generate code that looks like this:
23154 ldr r2, [pc, .Laaa]
23164 The first instruction loads the address of the jump table.
23165 The second instruction converts a table index into a byte offset.
23166 The third instruction gets the jump address out of the table.
23167 The fourth instruction performs the jump.
23169 If the address stored at .Laaa is that of a symbol which has the
23170 Thumb_Func bit set, then the linker will arrange for this address
23171 to have the bottom bit set, which in turn would mean that the
23172 address computation performed by the third instruction would end
23173 up with the bottom bit set. Since the ARM is capable of unaligned
23174 word loads, the instruction would then load the incorrect address
23175 out of the jump table, and chaos would ensue. */
23176 if (label_is_thumb_function_name
23177 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
23178 && (bfd_section_flags (now_seg
) & SEC_CODE
) != 0)
23180 /* When the address of a Thumb function is taken the bottom
23181 bit of that address should be set. This will allow
23182 interworking between Arm and Thumb functions to work
23185 THUMB_SET_FUNC (sym
, 1);
23187 label_is_thumb_function_name
= FALSE
;
23190 dwarf2_emit_label (sym
);
23194 arm_data_in_code (void)
23196 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
23198 *input_line_pointer
= '/';
23199 input_line_pointer
+= 5;
23200 *input_line_pointer
= 0;
23208 arm_canonicalize_symbol_name (char * name
)
23212 if (thumb_mode
&& (len
= strlen (name
)) > 5
23213 && streq (name
+ len
- 5, "/data"))
23214 *(name
+ len
- 5) = 0;
23219 /* Table of all register names defined by default. The user can
23220 define additional names with .req. Note that all register names
23221 should appear in both upper and lowercase variants. Some registers
23222 also have mixed-case names. */
23224 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
23225 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
23226 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
23227 #define REGSET(p,t) \
23228 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23229 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23230 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23231 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
23232 #define REGSETH(p,t) \
23233 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23234 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23235 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23236 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23237 #define REGSET2(p,t) \
23238 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23239 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23240 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23241 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
23242 #define SPLRBANK(base,bank,t) \
23243 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23244 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23245 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23246 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23247 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23248 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
23250 static const struct reg_entry reg_names
[] =
23252 /* ARM integer registers. */
23253 REGSET(r
, RN
), REGSET(R
, RN
),
23255 /* ATPCS synonyms. */
23256 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
23257 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
23258 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
23260 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
23261 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
23262 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
23264 /* Well-known aliases. */
23265 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
23266 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
23268 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
23269 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
23271 /* Defining the new Zero register from ARMv8.1-M. */
23275 /* Coprocessor numbers. */
23276 REGSET(p
, CP
), REGSET(P
, CP
),
23278 /* Coprocessor register numbers. The "cr" variants are for backward
23280 REGSET(c
, CN
), REGSET(C
, CN
),
23281 REGSET(cr
, CN
), REGSET(CR
, CN
),
23283 /* ARM banked registers. */
23284 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
23285 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
23286 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
23287 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
23288 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
23289 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
23290 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
23292 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
23293 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
23294 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
23295 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
23296 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
23297 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
23298 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
23299 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
23301 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
23302 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
23303 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
23304 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
23305 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
23306 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
23307 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
23308 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23309 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23311 /* FPA registers. */
23312 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
23313 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
23315 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
23316 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
23318 /* VFP SP registers. */
23319 REGSET(s
,VFS
), REGSET(S
,VFS
),
23320 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
23322 /* VFP DP Registers. */
23323 REGSET(d
,VFD
), REGSET(D
,VFD
),
23324 /* Extra Neon DP registers. */
23325 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
23327 /* Neon QP registers. */
23328 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
23330 /* VFP control registers. */
23331 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
23332 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
23333 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
23334 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
23335 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
23336 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
23337 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
23338 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
23339 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
23340 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
23341 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23343 /* Maverick DSP coprocessor registers. */
23344 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23345 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23347 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23348 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23349 REGDEF(dspsc
,0,DSPSC
),
23351 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23352 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23353 REGDEF(DSPSC
,0,DSPSC
),
23355 /* iWMMXt data registers - p0, c0-15. */
23356 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23358 /* iWMMXt control registers - p1, c0-3. */
23359 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23360 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23361 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23362 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23364 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23365 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23366 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23367 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23368 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23370 /* XScale accumulator registers. */
23371 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23377 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23378 within psr_required_here. */
23379 static const struct asm_psr psrs
[] =
23381 /* Backward compatibility notation. Note that "all" is no longer
23382 truly all possible PSR bits. */
23383 {"all", PSR_c
| PSR_f
},
23387 /* Individual flags. */
23393 /* Combinations of flags. */
23394 {"fs", PSR_f
| PSR_s
},
23395 {"fx", PSR_f
| PSR_x
},
23396 {"fc", PSR_f
| PSR_c
},
23397 {"sf", PSR_s
| PSR_f
},
23398 {"sx", PSR_s
| PSR_x
},
23399 {"sc", PSR_s
| PSR_c
},
23400 {"xf", PSR_x
| PSR_f
},
23401 {"xs", PSR_x
| PSR_s
},
23402 {"xc", PSR_x
| PSR_c
},
23403 {"cf", PSR_c
| PSR_f
},
23404 {"cs", PSR_c
| PSR_s
},
23405 {"cx", PSR_c
| PSR_x
},
23406 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23407 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23408 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23409 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23410 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23411 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23412 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23413 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23414 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23415 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23416 {"scf", PSR_s
| PSR_c
| PSR_f
},
23417 {"scx", PSR_s
| PSR_c
| PSR_x
},
23418 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23419 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23420 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23421 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23422 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23423 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23424 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23425 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23426 {"csf", PSR_c
| PSR_s
| PSR_f
},
23427 {"csx", PSR_c
| PSR_s
| PSR_x
},
23428 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23429 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23430 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23431 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23432 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23433 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23434 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23435 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23436 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23437 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23438 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23439 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23440 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23441 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23442 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23443 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23444 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23445 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23446 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23447 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23448 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23449 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23450 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23451 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23452 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23453 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23456 /* Table of V7M psr names. */
23457 static const struct asm_psr v7m_psrs
[] =
23459 {"apsr", 0x0 }, {"APSR", 0x0 },
23460 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23461 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23462 {"psr", 0x3 }, {"PSR", 0x3 },
23463 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23464 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23465 {"epsr", 0x6 }, {"EPSR", 0x6 },
23466 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23467 {"msp", 0x8 }, {"MSP", 0x8 },
23468 {"psp", 0x9 }, {"PSP", 0x9 },
23469 {"msplim", 0xa }, {"MSPLIM", 0xa },
23470 {"psplim", 0xb }, {"PSPLIM", 0xb },
23471 {"primask", 0x10}, {"PRIMASK", 0x10},
23472 {"basepri", 0x11}, {"BASEPRI", 0x11},
23473 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23474 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23475 {"control", 0x14}, {"CONTROL", 0x14},
23476 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23477 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23478 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
23479 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
23480 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
23481 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
23482 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
23483 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
23484 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
23487 /* Table of all shift-in-operand names. */
23488 static const struct asm_shift_name shift_names
[] =
23490 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
23491 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
23492 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
23493 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
23494 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
23495 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
23496 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
23499 /* Table of all explicit relocation names. */
23501 static struct reloc_entry reloc_names
[] =
23503 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
23504 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
23505 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
23506 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
23507 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
23508 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
23509 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
23510 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
23511 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
23512 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
23513 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
23514 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
23515 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
23516 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
23517 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
23518 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
23519 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
23520 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
23521 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
23522 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
23523 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23524 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23525 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
23526 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
23527 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
23528 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
23529 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
23533 /* Table of all conditional affixes. */
23534 static const struct asm_cond conds
[] =
23538 {"cs", 0x2}, {"hs", 0x2},
23539 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
23552 static const struct asm_cond vconds
[] =
23558 #define UL_BARRIER(L,U,CODE,FEAT) \
23559 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
23560 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
23562 static struct asm_barrier_opt barrier_opt_names
[] =
23564 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
23565 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
23566 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
23567 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
23568 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
23569 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
23570 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
23571 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
23572 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
23573 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
23574 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
23575 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
23576 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
23577 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
23578 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
23579 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
23584 /* Table of ARM-format instructions. */
23586 /* Macros for gluing together operand strings. N.B. In all cases
23587 other than OPS0, the trailing OP_stop comes from default
23588 zero-initialization of the unspecified elements of the array. */
23589 #define OPS0() { OP_stop, }
23590 #define OPS1(a) { OP_##a, }
23591 #define OPS2(a,b) { OP_##a,OP_##b, }
23592 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
23593 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
23594 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
23595 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23597 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23598 This is useful when mixing operands for ARM and THUMB, i.e. using the
23599 MIX_ARM_THUMB_OPERANDS macro.
23600 In order to use these macros, prefix the number of operands with _
23602 #define OPS_1(a) { a, }
23603 #define OPS_2(a,b) { a,b, }
23604 #define OPS_3(a,b,c) { a,b,c, }
23605 #define OPS_4(a,b,c,d) { a,b,c,d, }
23606 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23607 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23609 /* These macros abstract out the exact format of the mnemonic table and
23610 save some repeated characters. */
23612 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23613 #define TxCE(mnem, op, top, nops, ops, ae, te) \
23614 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
23615 THUMB_VARIANT, do_##ae, do_##te, 0 }
23617 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23618 a T_MNEM_xyz enumerator. */
23619 #define TCE(mnem, aop, top, nops, ops, ae, te) \
23620 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
23621 #define tCE(mnem, aop, top, nops, ops, ae, te) \
23622 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23624 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23625 infix after the third character. */
23626 #define TxC3(mnem, op, top, nops, ops, ae, te) \
23627 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
23628 THUMB_VARIANT, do_##ae, do_##te, 0 }
23629 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
23630 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
23631 THUMB_VARIANT, do_##ae, do_##te, 0 }
23632 #define TC3(mnem, aop, top, nops, ops, ae, te) \
23633 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
23634 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
23635 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
23636 #define tC3(mnem, aop, top, nops, ops, ae, te) \
23637 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23638 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
23639 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23641 /* Mnemonic that cannot be conditionalized. The ARM condition-code
23642 field is still 0xE. Many of the Thumb variants can be executed
23643 conditionally, so this is checked separately. */
23644 #define TUE(mnem, op, top, nops, ops, ae, te) \
23645 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23646 THUMB_VARIANT, do_##ae, do_##te, 0 }
23648 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23649 Used by mnemonics that have very minimal differences in the encoding for
23650 ARM and Thumb variants and can be handled in a common function. */
23651 #define TUEc(mnem, op, top, nops, ops, en) \
23652 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23653 THUMB_VARIANT, do_##en, do_##en, 0 }
23655 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23656 condition code field. */
23657 #define TUF(mnem, op, top, nops, ops, ae, te) \
23658 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
23659 THUMB_VARIANT, do_##ae, do_##te, 0 }
23661 /* ARM-only variants of all the above. */
23662 #define CE(mnem, op, nops, ops, ae) \
23663 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23665 #define C3(mnem, op, nops, ops, ae) \
23666 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23668 /* Thumb-only variants of TCE and TUE. */
23669 #define ToC(mnem, top, nops, ops, te) \
23670 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23673 #define ToU(mnem, top, nops, ops, te) \
23674 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
23677 /* T_MNEM_xyz enumerator variants of ToC. */
23678 #define toC(mnem, top, nops, ops, te) \
23679 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23682 /* T_MNEM_xyz enumerator variants of ToU. */
23683 #define toU(mnem, top, nops, ops, te) \
23684 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23687 /* Legacy mnemonics that always have conditional infix after the third
23689 #define CL(mnem, op, nops, ops, ae) \
23690 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23691 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23693 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23694 #define cCE(mnem, op, nops, ops, ae) \
23695 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23697 /* mov instructions that are shared between coprocessor and MVE. */
23698 #define mcCE(mnem, op, nops, ops, ae) \
23699 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23701 /* Legacy coprocessor instructions where conditional infix and conditional
23702 suffix are ambiguous. For consistency this includes all FPA instructions,
23703 not just the potentially ambiguous ones. */
23704 #define cCL(mnem, op, nops, ops, ae) \
23705 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23706 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23708 /* Coprocessor, takes either a suffix or a position-3 infix
23709 (for an FPA corner case). */
23710 #define C3E(mnem, op, nops, ops, ae) \
23711 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23712 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23714 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23715 { m1 #m2 m3, OPS##nops ops, \
23716 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23717 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23719 #define CM(m1, m2, op, nops, ops, ae) \
23720 xCM_ (m1, , m2, op, nops, ops, ae), \
23721 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23722 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23723 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23724 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23725 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23726 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23727 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23728 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23729 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23730 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23731 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23732 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23733 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23734 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23735 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23736 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23737 xCM_ (m1, le, m2, op, nops, ops, ae), \
23738 xCM_ (m1, al, m2, op, nops, ops, ae)
23740 #define UE(mnem, op, nops, ops, ae) \
23741 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23743 #define UF(mnem, op, nops, ops, ae) \
23744 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23746 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23747 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23748 use the same encoding function for each. */
23749 #define NUF(mnem, op, nops, ops, enc) \
23750 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23751 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23753 /* Neon data processing, version which indirects through neon_enc_tab for
23754 the various overloaded versions of opcodes. */
23755 #define nUF(mnem, op, nops, ops, enc) \
23756 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23757 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23759 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23761 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23762 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23763 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23765 #define NCE(mnem, op, nops, ops, enc) \
23766 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23768 #define NCEF(mnem, op, nops, ops, enc) \
23769 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23771 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23772 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23773 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23774 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23776 #define nCE(mnem, op, nops, ops, enc) \
23777 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23779 #define nCEF(mnem, op, nops, ops, enc) \
23780 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23783 #define mCEF(mnem, op, nops, ops, enc) \
23784 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23785 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23788 /* nCEF but for MVE predicated instructions. */
23789 #define mnCEF(mnem, op, nops, ops, enc) \
23790 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23792 /* nCE but for MVE predicated instructions. */
23793 #define mnCE(mnem, op, nops, ops, enc) \
23794 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23796 /* NUF but for potentially MVE predicated instructions. */
23797 #define MNUF(mnem, op, nops, ops, enc) \
23798 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23799 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23801 /* nUF but for potentially MVE predicated instructions. */
23802 #define mnUF(mnem, op, nops, ops, enc) \
23803 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23804 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23806 /* ToC but for potentially MVE predicated instructions. */
23807 #define mToC(mnem, top, nops, ops, te) \
23808 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23811 /* NCE but for MVE predicated instructions. */
23812 #define MNCE(mnem, op, nops, ops, enc) \
23813 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23815 /* NCEF but for MVE predicated instructions. */
23816 #define MNCEF(mnem, op, nops, ops, enc) \
23817 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23820 static const struct asm_opcode insns
[] =
23822 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23823 #define THUMB_VARIANT & arm_ext_v4t
23824 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23825 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23826 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23827 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23828 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23829 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23830 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23831 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23832 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23833 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23834 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23835 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23836 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23837 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23838 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23839 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23841 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23842 for setting PSR flag bits. They are obsolete in V6 and do not
23843 have Thumb equivalents. */
23844 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23845 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23846 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23847 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23848 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23849 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23850 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23851 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23852 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23854 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23855 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23856 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23857 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23859 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23860 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23861 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23863 OP_ADDRGLDR
),ldst
, t_ldst
),
23864 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23866 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23867 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23868 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23869 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23870 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23871 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23873 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23874 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23877 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23878 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23879 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23880 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23882 /* Thumb-compatibility pseudo ops. */
23883 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23884 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23885 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23886 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23887 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23888 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23889 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23890 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23891 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23892 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23893 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23894 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23896 /* These may simplify to neg. */
23897 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23898 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23900 #undef THUMB_VARIANT
23901 #define THUMB_VARIANT & arm_ext_os
23903 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23904 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23906 #undef THUMB_VARIANT
23907 #define THUMB_VARIANT & arm_ext_v6
23909 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23911 /* V1 instructions with no Thumb analogue prior to V6T2. */
23912 #undef THUMB_VARIANT
23913 #define THUMB_VARIANT & arm_ext_v6t2
23915 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23916 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23917 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23919 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23920 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23921 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23922 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23924 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23925 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23927 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23928 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23930 /* V1 instructions with no Thumb analogue at all. */
23931 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23932 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23934 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23935 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23936 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23937 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23938 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23939 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23940 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23941 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23944 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23945 #undef THUMB_VARIANT
23946 #define THUMB_VARIANT & arm_ext_v4t
23948 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23949 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23951 #undef THUMB_VARIANT
23952 #define THUMB_VARIANT & arm_ext_v6t2
23954 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23955 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23957 /* Generic coprocessor instructions. */
23958 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23959 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23960 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23961 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23962 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23963 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23964 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23967 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23969 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23970 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23973 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23974 #undef THUMB_VARIANT
23975 #define THUMB_VARIANT & arm_ext_msr
23977 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23978 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23981 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23982 #undef THUMB_VARIANT
23983 #define THUMB_VARIANT & arm_ext_v6t2
23985 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23986 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23987 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23988 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23989 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23990 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23991 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23992 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23995 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23996 #undef THUMB_VARIANT
23997 #define THUMB_VARIANT & arm_ext_v4t
23999 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24000 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24001 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24002 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24003 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24004 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24007 #define ARM_VARIANT & arm_ext_v4t_5
24009 /* ARM Architecture 4T. */
24010 /* Note: bx (and blx) are required on V5, even if the processor does
24011 not support Thumb. */
24012 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
24015 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
24016 #undef THUMB_VARIANT
24017 #define THUMB_VARIANT & arm_ext_v5t
24019 /* Note: blx has 2 variants; the .value coded here is for
24020 BLX(2). Only this variant has conditional execution. */
24021 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
24022 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
24024 #undef THUMB_VARIANT
24025 #define THUMB_VARIANT & arm_ext_v6t2
24027 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
24028 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24029 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24030 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24031 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24032 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24033 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24034 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24037 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
24038 #undef THUMB_VARIANT
24039 #define THUMB_VARIANT & arm_ext_v5exp
24041 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24042 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24043 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24044 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24046 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24047 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24049 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24050 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24051 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24052 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24054 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24055 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24056 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24057 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24059 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24060 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24062 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24063 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24064 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24065 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24068 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
24069 #undef THUMB_VARIANT
24070 #define THUMB_VARIANT & arm_ext_v6t2
24072 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
24073 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
24075 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
24076 ADDRGLDRS
), ldrd
, t_ldstd
),
24078 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24079 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24082 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
24084 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
24087 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
24088 #undef THUMB_VARIANT
24089 #define THUMB_VARIANT & arm_ext_v6
24091 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24092 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24093 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24094 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24095 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24096 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24097 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24098 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24099 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24100 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
24102 #undef THUMB_VARIANT
24103 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24105 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
24106 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24108 #undef THUMB_VARIANT
24109 #define THUMB_VARIANT & arm_ext_v6t2
24111 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24112 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24114 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
24115 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
24117 /* ARM V6 not included in V7M. */
24118 #undef THUMB_VARIANT
24119 #define THUMB_VARIANT & arm_ext_v6_notm
24120 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24121 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24122 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
24123 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
24124 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24125 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24126 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
24127 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24128 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
24129 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24130 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24131 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24132 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24133 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24134 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
24135 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
24136 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24137 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24138 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
24140 /* ARM V6 not included in V7M (eg. integer SIMD). */
24141 #undef THUMB_VARIANT
24142 #define THUMB_VARIANT & arm_ext_v6_dsp
24143 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
24144 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
24145 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24146 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24147 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24148 /* Old name for QASX. */
24149 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24150 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24151 /* Old name for QSAX. */
24152 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24153 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24154 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24155 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24156 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24157 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24158 /* Old name for SASX. */
24159 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24160 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24161 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24162 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24163 /* Old name for SHASX. */
24164 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24165 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24166 /* Old name for SHSAX. */
24167 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24168 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24169 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24170 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24171 /* Old name for SSAX. */
24172 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24173 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24174 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24175 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24176 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24177 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24178 /* Old name for UASX. */
24179 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24180 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24181 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24182 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24183 /* Old name for UHASX. */
24184 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24185 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24186 /* Old name for UHSAX. */
24187 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24188 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24189 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24190 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24191 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24192 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24193 /* Old name for UQASX. */
24194 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24195 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24196 /* Old name for UQSAX. */
24197 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24198 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24199 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24200 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24201 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24202 /* Old name for USAX. */
24203 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24204 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24205 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24206 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24207 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24208 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24209 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24210 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24211 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24212 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24213 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24214 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24215 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24216 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24217 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24218 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24219 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24220 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24221 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24222 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24223 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24224 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24225 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24226 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24227 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24228 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24229 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24230 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24231 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24232 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
24233 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
24234 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24235 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24236 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
24239 #define ARM_VARIANT & arm_ext_v6k_v6t2
24240 #undef THUMB_VARIANT
24241 #define THUMB_VARIANT & arm_ext_v6k_v6t2
24243 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
24244 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
24245 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
24246 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
24248 #undef THUMB_VARIANT
24249 #define THUMB_VARIANT & arm_ext_v6_notm
24250 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
24252 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
24253 RRnpcb
), strexd
, t_strexd
),
24255 #undef THUMB_VARIANT
24256 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24257 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
24259 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
24261 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24263 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24265 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
24268 #define ARM_VARIANT & arm_ext_sec
24269 #undef THUMB_VARIANT
24270 #define THUMB_VARIANT & arm_ext_sec
24272 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
24275 #define ARM_VARIANT & arm_ext_virt
24276 #undef THUMB_VARIANT
24277 #define THUMB_VARIANT & arm_ext_virt
24279 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
24280 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
24283 #define ARM_VARIANT & arm_ext_pan
24284 #undef THUMB_VARIANT
24285 #define THUMB_VARIANT & arm_ext_pan
24287 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
24290 #define ARM_VARIANT & arm_ext_v6t2
24291 #undef THUMB_VARIANT
24292 #define THUMB_VARIANT & arm_ext_v6t2
24294 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
24295 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
24296 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24297 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24299 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24300 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
24302 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24303 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24304 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24305 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24308 #define ARM_VARIANT & arm_ext_v3
24309 #undef THUMB_VARIANT
24310 #define THUMB_VARIANT & arm_ext_v6t2
24312 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
24313 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
24314 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
24317 #define ARM_VARIANT & arm_ext_v6t2
24318 #undef THUMB_VARIANT
24319 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24320 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24321 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24323 /* Thumb-only instructions. */
24325 #define ARM_VARIANT NULL
24326 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
24327 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
24329 /* ARM does not really have an IT instruction, so always allow it.
24330 The opcode is copied from Thumb in order to allow warnings in
24331 -mimplicit-it=[never | arm] modes. */
24333 #define ARM_VARIANT & arm_ext_v1
24334 #undef THUMB_VARIANT
24335 #define THUMB_VARIANT & arm_ext_v6t2
24337 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
24338 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
24339 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
24340 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
24341 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
24342 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24343 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24344 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24345 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24346 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24347 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24348 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24349 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24350 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24351 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24352 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24353 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24354 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24356 /* Thumb2 only instructions. */
24358 #define ARM_VARIANT NULL
24360 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24361 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24362 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24363 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24364 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24365 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24367 /* Hardware division instructions. */
24369 #define ARM_VARIANT & arm_ext_adiv
24370 #undef THUMB_VARIANT
24371 #define THUMB_VARIANT & arm_ext_div
24373 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24374 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24376 /* ARM V6M/V7 instructions. */
24378 #define ARM_VARIANT & arm_ext_barrier
24379 #undef THUMB_VARIANT
24380 #define THUMB_VARIANT & arm_ext_barrier
24382 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24383 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24384 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24386 /* ARM V7 instructions. */
24388 #define ARM_VARIANT & arm_ext_v7
24389 #undef THUMB_VARIANT
24390 #define THUMB_VARIANT & arm_ext_v7
24392 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24393 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24396 #define ARM_VARIANT & arm_ext_mp
24397 #undef THUMB_VARIANT
24398 #define THUMB_VARIANT & arm_ext_mp
24400 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24402 /* AArchv8 instructions. */
24404 #define ARM_VARIANT & arm_ext_v8
24406 /* Instructions shared between armv8-a and armv8-m. */
24407 #undef THUMB_VARIANT
24408 #define THUMB_VARIANT & arm_ext_atomics
24410 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24411 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24412 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24413 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24414 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24415 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24416 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24417 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24418 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24419 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24421 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24423 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24425 #undef THUMB_VARIANT
24426 #define THUMB_VARIANT & arm_ext_v8
24428 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24429 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24431 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24434 /* Defined in V8 but is in undefined encoding space for earlier
24435 architectures. However earlier architectures are required to treat
24436 this instuction as a semihosting trap as well. Hence while not explicitly
24437 defined as such, it is in fact correct to define the instruction for all
24439 #undef THUMB_VARIANT
24440 #define THUMB_VARIANT & arm_ext_v1
24442 #define ARM_VARIANT & arm_ext_v1
24443 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24445 /* ARMv8 T32 only. */
24447 #define ARM_VARIANT NULL
24448 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24449 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24450 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24452 /* FP for ARMv8. */
24454 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24455 #undef THUMB_VARIANT
24456 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24458 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24459 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24460 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24461 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24462 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24463 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24464 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24465 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24466 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
24467 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
24468 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
24470 /* Crypto v1 extensions. */
24472 #define ARM_VARIANT & fpu_crypto_ext_armv8
24473 #undef THUMB_VARIANT
24474 #define THUMB_VARIANT & fpu_crypto_ext_armv8
24476 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
24477 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
24478 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
24479 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
24480 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
24481 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
24482 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
24483 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
24484 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
24485 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
24486 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
24487 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
24488 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
24489 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
24492 #define ARM_VARIANT & crc_ext_armv8
24493 #undef THUMB_VARIANT
24494 #define THUMB_VARIANT & crc_ext_armv8
24495 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
24496 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
24497 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
24498 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
24499 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
24500 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
24502 /* ARMv8.2 RAS extension. */
24504 #define ARM_VARIANT & arm_ext_ras
24505 #undef THUMB_VARIANT
24506 #define THUMB_VARIANT & arm_ext_ras
24507 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
24510 #define ARM_VARIANT & arm_ext_v8_3
24511 #undef THUMB_VARIANT
24512 #define THUMB_VARIANT & arm_ext_v8_3
24513 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
24516 #define ARM_VARIANT & fpu_neon_ext_dotprod
24517 #undef THUMB_VARIANT
24518 #define THUMB_VARIANT & fpu_neon_ext_dotprod
24519 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
24520 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
24523 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
24524 #undef THUMB_VARIANT
24525 #define THUMB_VARIANT NULL
24527 cCE("wfs", e200110
, 1, (RR
), rd
),
24528 cCE("rfs", e300110
, 1, (RR
), rd
),
24529 cCE("wfc", e400110
, 1, (RR
), rd
),
24530 cCE("rfc", e500110
, 1, (RR
), rd
),
24532 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24533 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24534 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24535 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24537 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24538 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24539 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24540 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24542 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
24543 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
24544 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
24545 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
24546 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
24547 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
24548 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
24549 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
24550 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
24551 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
24552 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
24553 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
24555 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
24556 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
24557 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
24558 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
24559 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
24560 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
24561 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
24562 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
24563 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
24564 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
24565 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
24566 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
24568 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
24569 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
24570 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
24571 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
24572 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
24573 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
24574 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
24575 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
24576 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
24577 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
24578 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
24579 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
24581 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
24582 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
24583 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
24584 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
24585 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
24586 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
24587 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
24588 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
24589 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
24590 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
24591 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
24592 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
24594 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
24595 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
24596 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
24597 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
24598 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
24599 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
24600 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
24601 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
24602 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
24603 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
24604 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
24605 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
24607 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
24608 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
24609 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
24610 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
24611 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
24612 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
24613 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
24614 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
24615 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
24616 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
24617 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
24618 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
24620 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
24621 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
24622 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
24623 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
24624 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
24625 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
24626 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
24627 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
24628 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
24629 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
24630 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
24631 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
24633 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
24634 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
24635 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
24636 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
24637 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
24638 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
24639 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
24640 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
24641 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
24642 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
24643 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
24644 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
24646 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
24647 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
24648 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
24649 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
24650 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
24651 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
24652 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
24653 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
24654 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
24655 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
24656 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
24657 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
24659 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
24660 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
24661 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
24662 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
24663 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
24664 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
24665 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
24666 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
24667 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
24668 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
24669 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
24670 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
24672 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
24673 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
24674 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
24675 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
24676 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
24677 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
24678 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
24679 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
24680 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24681 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24682 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24683 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24685 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24686 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24687 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24688 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24689 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24690 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24691 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24692 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24693 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24694 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24695 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24696 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24698 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24699 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24700 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24701 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24702 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24703 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24704 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24705 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24706 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24707 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24708 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24709 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24711 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24712 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24713 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24714 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24715 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24716 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24717 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24718 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24719 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24720 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24721 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24722 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24724 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24725 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24726 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24727 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24728 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24729 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24730 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24731 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24732 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24733 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24734 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24735 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24737 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24738 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24739 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24740 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24741 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24742 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24743 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24744 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24745 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24746 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24747 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24748 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24750 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24751 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24752 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24753 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24754 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24755 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24756 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24757 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24758 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24759 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24760 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24761 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24763 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24764 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24765 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24766 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24767 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24768 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24769 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24770 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24771 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24772 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24773 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24774 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24776 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24777 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24778 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24779 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24780 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24781 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24782 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24783 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24784 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24785 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24786 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24787 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24789 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24790 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24791 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24792 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24793 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24794 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24795 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24796 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24797 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24798 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24799 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24800 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24802 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24803 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24804 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24805 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24806 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24807 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24808 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24809 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24810 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24811 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24812 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24813 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24815 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24816 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24817 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24818 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24819 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24820 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24821 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24822 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24823 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24824 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24825 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24826 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24828 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24829 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24830 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24831 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24832 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24833 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24834 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24835 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24836 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24837 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24838 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24839 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24841 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24842 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24843 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24844 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24845 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24846 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24847 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24848 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24849 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24850 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24851 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24852 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24854 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24855 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24856 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24857 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24858 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24859 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24860 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24861 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24862 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24863 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24864 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24865 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24867 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24868 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24869 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24870 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24871 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24872 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24873 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24874 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24875 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24876 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24877 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24878 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24880 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24881 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24882 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24883 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24884 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24885 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24886 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24887 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24888 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24889 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24890 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24891 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24893 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24894 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24895 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24896 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24897 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24898 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24899 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24900 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24901 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24902 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24903 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24904 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24906 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24907 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24908 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24909 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24910 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24911 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24912 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24913 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24914 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24915 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24916 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24917 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24919 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24920 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24921 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24922 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24924 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24925 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24926 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24927 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24928 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24929 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24930 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24931 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24932 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24933 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24934 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24935 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24937 /* The implementation of the FIX instruction is broken on some
24938 assemblers, in that it accepts a precision specifier as well as a
24939 rounding specifier, despite the fact that this is meaningless.
24940 To be more compatible, we accept it as well, though of course it
24941 does not set any bits. */
24942 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24943 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24944 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24945 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24946 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24947 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24948 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24949 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24950 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24951 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24952 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24953 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24954 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24956 /* Instructions that were new with the real FPA, call them V2. */
24958 #define ARM_VARIANT & fpu_fpa_ext_v2
24960 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24961 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24962 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24963 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24964 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24965 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24968 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24969 #undef THUMB_VARIANT
24970 #define THUMB_VARIANT & arm_ext_v6t2
24971 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24972 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
24973 #undef THUMB_VARIANT
24975 /* Moves and type conversions. */
24976 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24977 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24978 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24979 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24980 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24981 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24982 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24983 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24984 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24986 /* Memory operations. */
24987 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24988 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24989 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24990 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24991 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24992 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24993 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24994 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24995 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24996 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24997 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24998 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24999 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25000 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25001 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25002 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25003 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25004 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25006 /* Monadic operations. */
25007 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25008 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25009 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25011 /* Dyadic operations. */
25012 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25013 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25014 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25015 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25016 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25017 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25018 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25019 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25020 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25023 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25024 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
25025 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25026 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
25028 /* Double precision load/store are still present on single precision
25029 implementations. */
25030 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25031 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25032 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25033 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25034 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25035 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25036 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25037 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25038 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25039 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25042 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
25044 /* Moves and type conversions. */
25045 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25046 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25047 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25048 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25049 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25050 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25051 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25052 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25053 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25054 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25055 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25056 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25058 /* Monadic operations. */
25059 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25060 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25061 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25063 /* Dyadic operations. */
25064 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25065 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25066 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25067 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25068 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25069 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25070 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25071 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25072 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25075 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25076 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
25077 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25078 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
25080 /* Instructions which may belong to either the Neon or VFP instruction sets.
25081 Individual encoder functions perform additional architecture checks. */
25083 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25084 #undef THUMB_VARIANT
25085 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
25087 /* These mnemonics are unique to VFP. */
25088 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
25089 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
25090 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25091 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25092 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25093 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
25094 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
25095 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
25097 /* Mnemonics shared by Neon and VFP. */
25098 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
25100 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25101 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25102 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25103 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25104 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25105 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25107 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
25108 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
25109 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
25110 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
25113 /* NOTE: All VMOV encoding is special-cased! */
25114 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
25116 #undef THUMB_VARIANT
25117 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
25118 by different feature bits. Since we are setting the Thumb guard, we can
25119 require Thumb-1 which makes it a nop guard and set the right feature bit in
25120 do_vldr_vstr (). */
25121 #define THUMB_VARIANT & arm_ext_v4t
25122 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25123 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25126 #define ARM_VARIANT & arm_ext_fp16
25127 #undef THUMB_VARIANT
25128 #define THUMB_VARIANT & arm_ext_fp16
25129 /* New instructions added from v8.2, allowing the extraction and insertion of
25130 the upper 16 bits of a 32-bit vector register. */
25131 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
25132 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
25134 /* New backported fma/fms instructions optional in v8.2. */
25135 NUF (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
25136 NUF (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
25138 #undef THUMB_VARIANT
25139 #define THUMB_VARIANT & fpu_neon_ext_v1
25141 #define ARM_VARIANT & fpu_neon_ext_v1
25143 /* Data processing with three registers of the same length. */
25144 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
25145 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
25146 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
25147 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25148 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25149 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25150 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
25151 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25152 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25153 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25154 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25155 /* If not immediate, fall back to neon_dyadic_i64_su.
25156 shl should accept I8 I16 I32 I64,
25157 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
25158 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
25159 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
25160 /* Logic ops, types optional & ignored. */
25161 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25162 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25163 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25164 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25165 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
25166 /* Bitfield ops, untyped. */
25167 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25168 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25169 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25170 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25171 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25172 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25173 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
25174 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25175 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25176 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25177 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25178 back to neon_dyadic_if_su. */
25179 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25180 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25181 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25182 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25183 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25184 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25185 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25186 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25187 /* Comparison. Type I8 I16 I32 F32. */
25188 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
25189 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
25190 /* As above, D registers only. */
25191 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25192 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25193 /* Int and float variants, signedness unimportant. */
25194 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25195 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25196 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
25197 /* Add/sub take types I8 I16 I32 I64 F32. */
25198 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25199 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25200 /* vtst takes sizes 8, 16, 32. */
25201 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
25202 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
25203 /* VMUL takes I8 I16 I32 F32 P8. */
25204 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
25205 /* VQD{R}MULH takes S16 S32. */
25206 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25207 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25208 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25209 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25210 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25211 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25212 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25213 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25214 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25215 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25216 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25217 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25218 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25219 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25220 /* ARM v8.1 extension. */
25221 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25222 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
25223 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25225 /* Two address, int/float. Types S8 S16 S32 F32. */
25226 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25227 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25229 /* Data processing with two registers and a shift amount. */
25230 /* Right shifts, and variants with rounding.
25231 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
25232 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25233 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25234 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25235 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25236 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25237 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25238 /* Shift and insert. Sizes accepted 8 16 32 64. */
25239 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
25240 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
25241 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
25242 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
25243 /* Right shift immediate, saturating & narrowing, with rounding variants.
25244 Types accepted S16 S32 S64 U16 U32 U64. */
25245 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25246 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25247 /* As above, unsigned. Types accepted S16 S32 S64. */
25248 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25249 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25250 /* Right shift narrowing. Types accepted I16 I32 I64. */
25251 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25252 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25253 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
25254 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
25255 /* CVT with optional immediate for fixed-point variant. */
25256 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
25258 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
25260 /* Data processing, three registers of different lengths. */
25261 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
25262 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
25263 /* If not scalar, fall back to neon_dyadic_long.
25264 Vector types as above, scalar types S16 S32 U16 U32. */
25265 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25266 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25267 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
25268 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25269 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25270 /* Dyadic, narrowing insns. Types I16 I32 I64. */
25271 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25272 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25273 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25274 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25275 /* Saturating doubling multiplies. Types S16 S32. */
25276 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25277 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25278 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25279 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25280 S16 S32 U16 U32. */
25281 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
25283 /* Extract. Size 8. */
25284 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
25285 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
25287 /* Two registers, miscellaneous. */
25288 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
25289 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
25290 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
25291 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
25292 /* Vector replicate. Sizes 8 16 32. */
25293 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
25294 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25295 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
25296 /* VMOVN. Types I16 I32 I64. */
25297 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
25298 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25299 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
25300 /* VQMOVUN. Types S16 S32 S64. */
25301 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
25302 /* VZIP / VUZP. Sizes 8 16 32. */
25303 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25304 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25305 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25306 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25307 /* VQABS / VQNEG. Types S8 S16 S32. */
25308 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25309 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25310 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25311 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25312 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
25313 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25314 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
25315 /* Reciprocal estimates. Types U32 F16 F32. */
25316 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25317 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
25318 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25319 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
25320 /* VCLS. Types S8 S16 S32. */
25321 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
25322 /* VCLZ. Types I8 I16 I32. */
25323 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
25324 /* VCNT. Size 8. */
25325 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
25326 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
25327 /* Two address, untyped. */
25328 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
25329 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
25330 /* VTRN. Sizes 8 16 32. */
25331 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
25332 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
25334 /* Table lookup. Size 8. */
25335 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25336 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25338 #undef THUMB_VARIANT
25339 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25341 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25343 /* Neon element/structure load/store. */
25344 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25345 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25346 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25347 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25348 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25349 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25350 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25351 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25353 #undef THUMB_VARIANT
25354 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25356 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25357 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25358 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25359 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25360 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25361 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25362 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25363 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25364 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25365 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25367 #undef THUMB_VARIANT
25368 #define THUMB_VARIANT & fpu_vfp_ext_v3
25370 #define ARM_VARIANT & fpu_vfp_ext_v3
25372 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25373 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25374 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25375 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25376 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25377 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25378 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25379 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25380 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25383 #define ARM_VARIANT & fpu_vfp_ext_fma
25384 #undef THUMB_VARIANT
25385 #define THUMB_VARIANT & fpu_vfp_ext_fma
25386 /* Mnemonics shared by Neon, VFP, MVE and BF16. These are included in the
25387 VFP FMA variant; NEON and VFP FMA always includes the NEON
25388 FMA instructions. */
25389 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25390 TUF ("vfmat", c300850
, fc300850
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), mve_vfma
, mve_vfma
),
25391 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25393 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25394 the v form should always be used. */
25395 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25396 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25397 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25398 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25399 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25400 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25402 #undef THUMB_VARIANT
25404 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25406 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25407 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25408 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25409 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25410 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25411 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25412 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25413 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25416 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25418 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25419 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25420 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25421 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25422 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25423 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25424 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25425 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25426 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25427 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25428 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25429 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25430 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25431 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25432 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25433 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25434 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25435 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25436 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25437 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25438 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25439 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25440 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25441 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25442 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25443 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25444 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25445 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25446 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25447 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25448 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25449 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25450 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25451 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25452 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25453 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25454 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25455 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25456 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25457 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25458 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25459 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25460 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25461 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25462 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25463 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25464 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
25465 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25466 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25467 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25468 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25469 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25470 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25471 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25472 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25473 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25474 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25475 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25476 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25477 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25478 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25479 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25480 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25481 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25482 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25483 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25484 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25485 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25486 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25487 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25488 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25489 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25490 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25491 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25492 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25493 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25494 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25495 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25496 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25497 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25498 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25499 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25500 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25501 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25502 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25503 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25504 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25505 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25506 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
25507 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25508 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25509 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25510 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25511 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25512 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25513 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25514 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25515 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25516 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25517 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25518 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25519 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25520 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25521 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25522 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25523 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25524 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25525 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25526 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25527 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25528 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
25529 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25530 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25531 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25532 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25533 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25534 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25535 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25536 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25537 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25538 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25539 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25540 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25541 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25542 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25543 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25544 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25545 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25546 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25547 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25548 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25549 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25550 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25551 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25552 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25553 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25554 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25555 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25556 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25557 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25558 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25559 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25560 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25561 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25562 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25563 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25564 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25565 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25566 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25567 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25568 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25569 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25570 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25571 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25572 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25573 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25574 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25575 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25576 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25577 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25578 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25579 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
25582 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
25584 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
25585 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
25586 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
25587 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25588 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25589 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25590 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25591 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25592 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25593 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25594 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25595 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25596 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25597 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25598 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25599 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25600 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25601 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25602 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25603 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25604 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
25605 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25606 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25607 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25608 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25609 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25610 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25611 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25612 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25613 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25614 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25615 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25616 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25617 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25618 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25619 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25620 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25621 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25622 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25623 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25624 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25625 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25626 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25627 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25628 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25629 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25630 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25631 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25632 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25633 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25634 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25635 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25636 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25637 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25638 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25639 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25640 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25643 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25645 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25646 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25647 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25648 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25649 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25650 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25651 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25652 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25653 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
25654 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
25655 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
25656 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
25657 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
25658 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
25659 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
25660 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
25661 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
25662 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
25663 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
25664 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
25665 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
25666 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
25667 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
25668 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
25669 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
25670 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
25671 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
25672 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
25673 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
25674 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
25675 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
25676 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
25677 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
25678 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
25679 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
25680 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
25681 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
25682 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
25683 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
25684 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25685 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25686 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25687 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25688 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25689 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25690 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25691 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25692 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25693 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25694 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25695 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25696 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25697 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25698 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25699 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25700 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25701 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25702 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25703 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25704 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25705 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25706 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25707 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25708 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25709 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25710 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25711 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25712 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25713 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25714 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25715 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25716 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25717 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25718 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25719 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25720 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25722 /* ARMv8.5-A instructions. */
25724 #define ARM_VARIANT & arm_ext_sb
25725 #undef THUMB_VARIANT
25726 #define THUMB_VARIANT & arm_ext_sb
25727 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25730 #define ARM_VARIANT & arm_ext_predres
25731 #undef THUMB_VARIANT
25732 #define THUMB_VARIANT & arm_ext_predres
25733 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25734 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25735 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25737 /* ARMv8-M instructions. */
25739 #define ARM_VARIANT NULL
25740 #undef THUMB_VARIANT
25741 #define THUMB_VARIANT & arm_ext_v8m
25742 ToU("sg", e97fe97f
, 0, (), noargs
),
25743 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25744 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25745 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25746 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25747 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25748 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25750 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25751 instructions behave as nop if no VFP is present. */
25752 #undef THUMB_VARIANT
25753 #define THUMB_VARIANT & arm_ext_v8m_main
25754 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25755 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25757 /* Armv8.1-M Mainline instructions. */
25758 #undef THUMB_VARIANT
25759 #define THUMB_VARIANT & arm_ext_v8_1m_main
25760 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25761 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25762 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25763 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25764 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
25765 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
25766 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25767 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25768 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25770 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25771 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25772 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25773 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25774 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25776 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25777 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25778 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25780 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25781 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25783 #undef THUMB_VARIANT
25784 #define THUMB_VARIANT & mve_ext
25785 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25786 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25787 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25788 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25789 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25790 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25791 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25792 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25793 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25794 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25795 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25796 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25797 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25798 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25799 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25801 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25802 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25803 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25804 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25805 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25806 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25807 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25808 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25809 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25810 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25811 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25812 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25813 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25814 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25815 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25817 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25818 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25819 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25820 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25821 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25822 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25823 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25824 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25825 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25826 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25827 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25828 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25829 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25830 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25831 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25833 /* MVE and MVE FP only. */
25834 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25835 mCEF(vctp
, _vctp
, 1, (RRnpc
), mve_vctp
),
25836 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25837 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25838 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25839 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25840 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25841 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25842 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25843 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25844 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25845 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25846 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25847 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25848 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25849 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25850 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25851 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25853 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25854 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25855 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25856 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25857 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25858 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25859 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25860 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25861 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25862 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25863 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25864 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25865 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25866 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25867 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25868 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25869 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25870 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25871 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25872 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25874 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25875 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25876 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25877 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25878 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25879 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25880 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25881 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25882 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25883 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25884 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25885 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25886 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25887 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25888 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25889 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25890 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25892 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25893 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25894 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25895 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25896 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25897 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25898 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25899 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25900 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25901 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25902 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25903 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25904 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25905 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25906 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25907 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25908 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25909 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25910 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25911 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25913 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25914 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25915 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25916 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25917 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25919 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25920 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25921 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25922 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25923 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25924 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25925 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25926 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25927 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25928 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25929 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25930 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25931 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25932 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25933 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25934 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25935 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25937 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25938 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25939 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25940 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25941 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25942 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25943 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25944 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25945 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25946 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25947 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25948 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25950 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25951 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25952 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25954 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
25955 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
25956 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
25957 toU("lctp", _lctp
, 0, (), t_loloop
),
25959 #undef THUMB_VARIANT
25960 #define THUMB_VARIANT & mve_fp_ext
25961 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25962 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25963 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25964 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25965 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25966 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25967 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25968 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25971 #define ARM_VARIANT & fpu_vfp_ext_v1
25972 #undef THUMB_VARIANT
25973 #define THUMB_VARIANT & arm_ext_v6t2
25974 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25975 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25977 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25980 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25982 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25983 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25984 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25985 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25987 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25988 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25989 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25991 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25992 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25994 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25995 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25997 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25998 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26001 #define ARM_VARIANT & fpu_vfp_ext_v2
26003 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
26004 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
26005 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
26006 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
26009 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
26010 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
26011 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
26012 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
26013 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
26014 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26015 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26018 #define ARM_VARIANT & fpu_neon_ext_v1
26019 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26020 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
26021 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
26022 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
26023 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26024 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26025 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26026 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26027 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
26028 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
26029 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
26030 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
26031 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26032 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
26033 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26034 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26035 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26036 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26037 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26038 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
26039 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26040 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26041 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
26042 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26043 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26044 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26045 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26046 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26047 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26048 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
26049 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
26050 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26051 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26052 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26053 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
26054 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
26055 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
26058 #define ARM_VARIANT & arm_ext_v8_3
26059 #undef THUMB_VARIANT
26060 #define THUMB_VARIANT & arm_ext_v6t2_v8m
26061 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
26062 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
26065 #define ARM_VARIANT &arm_ext_bf16
26066 #undef THUMB_VARIANT
26067 #define THUMB_VARIANT &arm_ext_bf16
26068 TUF ("vdot", c000d00
, fc000d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vdot
, vdot
),
26069 TUF ("vmmla", c000c40
, fc000c40
, 3, (RNQ
, RNQ
, RNQ
), vmmla
, vmmla
),
26070 TUF ("vfmab", c300810
, fc300810
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), bfloat_vfma
, bfloat_vfma
),
26073 #define ARM_VARIANT &arm_ext_i8mm
26074 #undef THUMB_VARIANT
26075 #define THUMB_VARIANT &arm_ext_i8mm
26076 TUF ("vsmmla", c200c40
, fc200c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26077 TUF ("vummla", c200c50
, fc200c50
, 3, (RNQ
, RNQ
, RNQ
), vummla
, vummla
),
26078 TUF ("vusmmla", ca00c40
, fca00c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26079 TUF ("vusdot", c800d00
, fc800d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vusdot
, vusdot
),
26080 TUF ("vsudot", c800d10
, fc800d10
, 3, (RNDQ
, RNDQ
, RNSC
), vsudot
, vsudot
),
26083 #undef THUMB_VARIANT
26115 /* MD interface: bits in the object file. */
26117 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
26118 for use in the a.out file, and stores them in the array pointed to by buf.
26119 This knows about the endian-ness of the target machine and does
26120 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
26121 2 (short) and 4 (long) Floating numbers are put out as a series of
26122 LITTLENUMS (shorts, here at least). */
26125 md_number_to_chars (char * buf
, valueT val
, int n
)
26127 if (target_big_endian
)
26128 number_to_chars_bigendian (buf
, val
, n
);
26130 number_to_chars_littleendian (buf
, val
, n
);
26134 md_chars_to_number (char * buf
, int n
)
26137 unsigned char * where
= (unsigned char *) buf
;
26139 if (target_big_endian
)
26144 result
|= (*where
++ & 255);
26152 result
|= (where
[n
] & 255);
26159 /* MD interface: Sections. */
26161 /* Calculate the maximum variable size (i.e., excluding fr_fix)
26162 that an rs_machine_dependent frag may reach. */
26165 arm_frag_max_var (fragS
*fragp
)
26167 /* We only use rs_machine_dependent for variable-size Thumb instructions,
26168 which are either THUMB_SIZE (2) or INSN_SIZE (4).
26170 Note that we generate relaxable instructions even for cases that don't
26171 really need it, like an immediate that's a trivial constant. So we're
26172 overestimating the instruction size for some of those cases. Rather
26173 than putting more intelligence here, it would probably be better to
26174 avoid generating a relaxation frag in the first place when it can be
26175 determined up front that a short instruction will suffice. */
26177 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
26181 /* Estimate the size of a frag before relaxing. Assume everything fits in
26185 md_estimate_size_before_relax (fragS
* fragp
,
26186 segT segtype ATTRIBUTE_UNUSED
)
26192 /* Convert a machine dependent frag. */
26195 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
26197 unsigned long insn
;
26198 unsigned long old_op
;
26206 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26208 old_op
= bfd_get_16(abfd
, buf
);
26209 if (fragp
->fr_symbol
)
26211 exp
.X_op
= O_symbol
;
26212 exp
.X_add_symbol
= fragp
->fr_symbol
;
26216 exp
.X_op
= O_constant
;
26218 exp
.X_add_number
= fragp
->fr_offset
;
26219 opcode
= fragp
->fr_subtype
;
26222 case T_MNEM_ldr_pc
:
26223 case T_MNEM_ldr_pc2
:
26224 case T_MNEM_ldr_sp
:
26225 case T_MNEM_str_sp
:
26232 if (fragp
->fr_var
== 4)
26234 insn
= THUMB_OP32 (opcode
);
26235 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
26237 insn
|= (old_op
& 0x700) << 4;
26241 insn
|= (old_op
& 7) << 12;
26242 insn
|= (old_op
& 0x38) << 13;
26244 insn
|= 0x00000c00;
26245 put_thumb32_insn (buf
, insn
);
26246 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
26250 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
26252 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
26255 if (fragp
->fr_var
== 4)
26257 insn
= THUMB_OP32 (opcode
);
26258 insn
|= (old_op
& 0xf0) << 4;
26259 put_thumb32_insn (buf
, insn
);
26260 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
26264 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26265 exp
.X_add_number
-= 4;
26273 if (fragp
->fr_var
== 4)
26275 int r0off
= (opcode
== T_MNEM_mov
26276 || opcode
== T_MNEM_movs
) ? 0 : 8;
26277 insn
= THUMB_OP32 (opcode
);
26278 insn
= (insn
& 0xe1ffffff) | 0x10000000;
26279 insn
|= (old_op
& 0x700) << r0off
;
26280 put_thumb32_insn (buf
, insn
);
26281 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26285 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
26290 if (fragp
->fr_var
== 4)
26292 insn
= THUMB_OP32(opcode
);
26293 put_thumb32_insn (buf
, insn
);
26294 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
26297 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
26301 if (fragp
->fr_var
== 4)
26303 insn
= THUMB_OP32(opcode
);
26304 insn
|= (old_op
& 0xf00) << 14;
26305 put_thumb32_insn (buf
, insn
);
26306 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
26309 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
26312 case T_MNEM_add_sp
:
26313 case T_MNEM_add_pc
:
26314 case T_MNEM_inc_sp
:
26315 case T_MNEM_dec_sp
:
26316 if (fragp
->fr_var
== 4)
26318 /* ??? Choose between add and addw. */
26319 insn
= THUMB_OP32 (opcode
);
26320 insn
|= (old_op
& 0xf0) << 4;
26321 put_thumb32_insn (buf
, insn
);
26322 if (opcode
== T_MNEM_add_pc
)
26323 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
26325 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26328 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26336 if (fragp
->fr_var
== 4)
26338 insn
= THUMB_OP32 (opcode
);
26339 insn
|= (old_op
& 0xf0) << 4;
26340 insn
|= (old_op
& 0xf) << 16;
26341 put_thumb32_insn (buf
, insn
);
26342 if (insn
& (1 << 20))
26343 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26345 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26348 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26354 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
26355 (enum bfd_reloc_code_real
) reloc_type
);
26356 fixp
->fx_file
= fragp
->fr_file
;
26357 fixp
->fx_line
= fragp
->fr_line
;
26358 fragp
->fr_fix
+= fragp
->fr_var
;
26360 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26361 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
26362 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26363 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26366 /* Return the size of a relaxable immediate operand instruction.
26367 SHIFT and SIZE specify the form of the allowable immediate. */
26369 relax_immediate (fragS
*fragp
, int size
, int shift
)
26375 /* ??? Should be able to do better than this. */
26376 if (fragp
->fr_symbol
)
26379 low
= (1 << shift
) - 1;
26380 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26381 offset
= fragp
->fr_offset
;
26382 /* Force misaligned offsets to 32-bit variant. */
26385 if (offset
& ~mask
)
26390 /* Get the address of a symbol during relaxation. */
26392 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26398 sym
= fragp
->fr_symbol
;
26399 sym_frag
= symbol_get_frag (sym
);
26400 know (S_GET_SEGMENT (sym
) != absolute_section
26401 || sym_frag
== &zero_address_frag
);
26402 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26404 /* If frag has yet to be reached on this pass, assume it will
26405 move by STRETCH just as we did. If this is not so, it will
26406 be because some frag between grows, and that will force
26410 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26414 /* Adjust stretch for any alignment frag. Note that if have
26415 been expanding the earlier code, the symbol may be
26416 defined in what appears to be an earlier frag. FIXME:
26417 This doesn't handle the fr_subtype field, which specifies
26418 a maximum number of bytes to skip when doing an
26420 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26422 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26425 stretch
= - ((- stretch
)
26426 & ~ ((1 << (int) f
->fr_offset
) - 1));
26428 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
26440 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
26443 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
26448 /* Assume worst case for symbols not known to be in the same section. */
26449 if (fragp
->fr_symbol
== NULL
26450 || !S_IS_DEFINED (fragp
->fr_symbol
)
26451 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26452 || S_IS_WEAK (fragp
->fr_symbol
))
26455 val
= relaxed_symbol_addr (fragp
, stretch
);
26456 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
26457 addr
= (addr
+ 4) & ~3;
26458 /* Force misaligned targets to 32-bit variant. */
26462 if (val
< 0 || val
> 1020)
26467 /* Return the size of a relaxable add/sub immediate instruction. */
26469 relax_addsub (fragS
*fragp
, asection
*sec
)
26474 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26475 op
= bfd_get_16(sec
->owner
, buf
);
26476 if ((op
& 0xf) == ((op
>> 4) & 0xf))
26477 return relax_immediate (fragp
, 8, 0);
26479 return relax_immediate (fragp
, 3, 0);
26482 /* Return TRUE iff the definition of symbol S could be pre-empted
26483 (overridden) at link or load time. */
26485 symbol_preemptible (symbolS
*s
)
26487 /* Weak symbols can always be pre-empted. */
26491 /* Non-global symbols cannot be pre-empted. */
26492 if (! S_IS_EXTERNAL (s
))
26496 /* In ELF, a global symbol can be marked protected, or private. In that
26497 case it can't be pre-empted (other definitions in the same link unit
26498 would violate the ODR). */
26499 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
26503 /* Other global symbols might be pre-empted. */
26507 /* Return the size of a relaxable branch instruction. BITS is the
26508 size of the offset field in the narrow instruction. */
26511 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
26517 /* Assume worst case for symbols not known to be in the same section. */
26518 if (!S_IS_DEFINED (fragp
->fr_symbol
)
26519 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26520 || S_IS_WEAK (fragp
->fr_symbol
))
26524 /* A branch to a function in ARM state will require interworking. */
26525 if (S_IS_DEFINED (fragp
->fr_symbol
)
26526 && ARM_IS_FUNC (fragp
->fr_symbol
))
26530 if (symbol_preemptible (fragp
->fr_symbol
))
26533 val
= relaxed_symbol_addr (fragp
, stretch
);
26534 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
26537 /* Offset is a signed value *2 */
26539 if (val
>= limit
|| val
< -limit
)
26545 /* Relax a machine dependent frag. This returns the amount by which
26546 the current size of the frag should change. */
26549 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
26554 oldsize
= fragp
->fr_var
;
26555 switch (fragp
->fr_subtype
)
26557 case T_MNEM_ldr_pc2
:
26558 newsize
= relax_adr (fragp
, sec
, stretch
);
26560 case T_MNEM_ldr_pc
:
26561 case T_MNEM_ldr_sp
:
26562 case T_MNEM_str_sp
:
26563 newsize
= relax_immediate (fragp
, 8, 2);
26567 newsize
= relax_immediate (fragp
, 5, 2);
26571 newsize
= relax_immediate (fragp
, 5, 1);
26575 newsize
= relax_immediate (fragp
, 5, 0);
26578 newsize
= relax_adr (fragp
, sec
, stretch
);
26584 newsize
= relax_immediate (fragp
, 8, 0);
26587 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
26590 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
26592 case T_MNEM_add_sp
:
26593 case T_MNEM_add_pc
:
26594 newsize
= relax_immediate (fragp
, 8, 2);
26596 case T_MNEM_inc_sp
:
26597 case T_MNEM_dec_sp
:
26598 newsize
= relax_immediate (fragp
, 7, 2);
26604 newsize
= relax_addsub (fragp
, sec
);
26610 fragp
->fr_var
= newsize
;
26611 /* Freeze wide instructions that are at or before the same location as
26612 in the previous pass. This avoids infinite loops.
26613 Don't freeze them unconditionally because targets may be artificially
26614 misaligned by the expansion of preceding frags. */
26615 if (stretch
<= 0 && newsize
> 2)
26617 md_convert_frag (sec
->owner
, sec
, fragp
);
26621 return newsize
- oldsize
;
26624 /* Round up a section size to the appropriate boundary. */
26627 md_section_align (segT segment ATTRIBUTE_UNUSED
,
26633 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26634 of an rs_align_code fragment. */
26637 arm_handle_align (fragS
* fragP
)
26639 static unsigned char const arm_noop
[2][2][4] =
26642 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26643 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26646 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26647 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26650 static unsigned char const thumb_noop
[2][2][2] =
26653 {0xc0, 0x46}, /* LE */
26654 {0x46, 0xc0}, /* BE */
26657 {0x00, 0xbf}, /* LE */
26658 {0xbf, 0x00} /* BE */
26661 static unsigned char const wide_thumb_noop
[2][4] =
26662 { /* Wide Thumb-2 */
26663 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26664 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26667 unsigned bytes
, fix
, noop_size
;
26669 const unsigned char * noop
;
26670 const unsigned char *narrow_noop
= NULL
;
26675 if (fragP
->fr_type
!= rs_align_code
)
26678 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
26679 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
26682 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26683 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
26685 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
26687 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
26689 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26690 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
26692 narrow_noop
= thumb_noop
[1][target_big_endian
];
26693 noop
= wide_thumb_noop
[target_big_endian
];
26696 noop
= thumb_noop
[0][target_big_endian
];
26704 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26705 ? selected_cpu
: arm_arch_none
,
26707 [target_big_endian
];
26714 fragP
->fr_var
= noop_size
;
26716 if (bytes
& (noop_size
- 1))
26718 fix
= bytes
& (noop_size
- 1);
26720 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
26722 memset (p
, 0, fix
);
26729 if (bytes
& noop_size
)
26731 /* Insert a narrow noop. */
26732 memcpy (p
, narrow_noop
, noop_size
);
26734 bytes
-= noop_size
;
26738 /* Use wide noops for the remainder */
26742 while (bytes
>= noop_size
)
26744 memcpy (p
, noop
, noop_size
);
26746 bytes
-= noop_size
;
26750 fragP
->fr_fix
+= fix
;
26753 /* Called from md_do_align. Used to create an alignment
26754 frag in a code section. */
26757 arm_frag_align_code (int n
, int max
)
26761 /* We assume that there will never be a requirement
26762 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26763 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26768 _("alignments greater than %d bytes not supported in .text sections."),
26769 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26770 as_fatal ("%s", err_msg
);
26773 p
= frag_var (rs_align_code
,
26774 MAX_MEM_FOR_RS_ALIGN_CODE
,
26776 (relax_substateT
) max
,
26783 /* Perform target specific initialisation of a frag.
26784 Note - despite the name this initialisation is not done when the frag
26785 is created, but only when its type is assigned. A frag can be created
26786 and used a long time before its type is set, so beware of assuming that
26787 this initialisation is performed first. */
26791 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26793 /* Record whether this frag is in an ARM or a THUMB area. */
26794 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26797 #else /* OBJ_ELF is defined. */
26799 arm_init_frag (fragS
* fragP
, int max_chars
)
26801 bfd_boolean frag_thumb_mode
;
26803 /* If the current ARM vs THUMB mode has not already
26804 been recorded into this frag then do so now. */
26805 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26806 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26808 /* PR 21809: Do not set a mapping state for debug sections
26809 - it just confuses other tools. */
26810 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
26813 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26815 /* Record a mapping symbol for alignment frags. We will delete this
26816 later if the alignment ends up empty. */
26817 switch (fragP
->fr_type
)
26820 case rs_align_test
:
26822 mapping_state_2 (MAP_DATA
, max_chars
);
26824 case rs_align_code
:
26825 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26832 /* When we change sections we need to issue a new mapping symbol. */
26835 arm_elf_change_section (void)
26837 /* Link an unlinked unwind index table section to the .text section. */
26838 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26839 && elf_linked_to_section (now_seg
) == NULL
)
26840 elf_linked_to_section (now_seg
) = text_section
;
26844 arm_elf_section_type (const char * str
, size_t len
)
26846 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26847 return SHT_ARM_EXIDX
;
26852 /* Code to deal with unwinding tables. */
26854 static void add_unwind_adjustsp (offsetT
);
26856 /* Generate any deferred unwind frame offset. */
26859 flush_pending_unwind (void)
26863 offset
= unwind
.pending_offset
;
26864 unwind
.pending_offset
= 0;
26866 add_unwind_adjustsp (offset
);
26869 /* Add an opcode to this list for this function. Two-byte opcodes should
26870 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26874 add_unwind_opcode (valueT op
, int length
)
26876 /* Add any deferred stack adjustment. */
26877 if (unwind
.pending_offset
)
26878 flush_pending_unwind ();
26880 unwind
.sp_restored
= 0;
26882 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26884 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26885 if (unwind
.opcodes
)
26886 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26887 unwind
.opcode_alloc
);
26889 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26894 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26896 unwind
.opcode_count
++;
26900 /* Add unwind opcodes to adjust the stack pointer. */
26903 add_unwind_adjustsp (offsetT offset
)
26907 if (offset
> 0x200)
26909 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26914 /* Long form: 0xb2, uleb128. */
26915 /* This might not fit in a word so add the individual bytes,
26916 remembering the list is built in reverse order. */
26917 o
= (valueT
) ((offset
- 0x204) >> 2);
26919 add_unwind_opcode (0, 1);
26921 /* Calculate the uleb128 encoding of the offset. */
26925 bytes
[n
] = o
& 0x7f;
26931 /* Add the insn. */
26933 add_unwind_opcode (bytes
[n
- 1], 1);
26934 add_unwind_opcode (0xb2, 1);
26936 else if (offset
> 0x100)
26938 /* Two short opcodes. */
26939 add_unwind_opcode (0x3f, 1);
26940 op
= (offset
- 0x104) >> 2;
26941 add_unwind_opcode (op
, 1);
26943 else if (offset
> 0)
26945 /* Short opcode. */
26946 op
= (offset
- 4) >> 2;
26947 add_unwind_opcode (op
, 1);
26949 else if (offset
< 0)
26952 while (offset
> 0x100)
26954 add_unwind_opcode (0x7f, 1);
26957 op
= ((offset
- 4) >> 2) | 0x40;
26958 add_unwind_opcode (op
, 1);
26962 /* Finish the list of unwind opcodes for this function. */
26965 finish_unwind_opcodes (void)
26969 if (unwind
.fp_used
)
26971 /* Adjust sp as necessary. */
26972 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26973 flush_pending_unwind ();
26975 /* After restoring sp from the frame pointer. */
26976 op
= 0x90 | unwind
.fp_reg
;
26977 add_unwind_opcode (op
, 1);
26980 flush_pending_unwind ();
26984 /* Start an exception table entry. If idx is nonzero this is an index table
26988 start_unwind_section (const segT text_seg
, int idx
)
26990 const char * text_name
;
26991 const char * prefix
;
26992 const char * prefix_once
;
26993 const char * group_name
;
27001 prefix
= ELF_STRING_ARM_unwind
;
27002 prefix_once
= ELF_STRING_ARM_unwind_once
;
27003 type
= SHT_ARM_EXIDX
;
27007 prefix
= ELF_STRING_ARM_unwind_info
;
27008 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
27009 type
= SHT_PROGBITS
;
27012 text_name
= segment_name (text_seg
);
27013 if (streq (text_name
, ".text"))
27016 if (strncmp (text_name
, ".gnu.linkonce.t.",
27017 strlen (".gnu.linkonce.t.")) == 0)
27019 prefix
= prefix_once
;
27020 text_name
+= strlen (".gnu.linkonce.t.");
27023 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
27029 /* Handle COMDAT group. */
27030 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
27032 group_name
= elf_group_name (text_seg
);
27033 if (group_name
== NULL
)
27035 as_bad (_("Group section `%s' has no group signature"),
27036 segment_name (text_seg
));
27037 ignore_rest_of_line ();
27040 flags
|= SHF_GROUP
;
27044 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
27047 /* Set the section link for index tables. */
27049 elf_linked_to_section (now_seg
) = text_seg
;
27053 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
27054 personality routine data. Returns zero, or the index table value for
27055 an inline entry. */
27058 create_unwind_entry (int have_data
)
27063 /* The current word of data. */
27065 /* The number of bytes left in this word. */
27068 finish_unwind_opcodes ();
27070 /* Remember the current text section. */
27071 unwind
.saved_seg
= now_seg
;
27072 unwind
.saved_subseg
= now_subseg
;
27074 start_unwind_section (now_seg
, 0);
27076 if (unwind
.personality_routine
== NULL
)
27078 if (unwind
.personality_index
== -2)
27081 as_bad (_("handlerdata in cantunwind frame"));
27082 return 1; /* EXIDX_CANTUNWIND. */
27085 /* Use a default personality routine if none is specified. */
27086 if (unwind
.personality_index
== -1)
27088 if (unwind
.opcode_count
> 3)
27089 unwind
.personality_index
= 1;
27091 unwind
.personality_index
= 0;
27094 /* Space for the personality routine entry. */
27095 if (unwind
.personality_index
== 0)
27097 if (unwind
.opcode_count
> 3)
27098 as_bad (_("too many unwind opcodes for personality routine 0"));
27102 /* All the data is inline in the index table. */
27105 while (unwind
.opcode_count
> 0)
27107 unwind
.opcode_count
--;
27108 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27112 /* Pad with "finish" opcodes. */
27114 data
= (data
<< 8) | 0xb0;
27121 /* We get two opcodes "free" in the first word. */
27122 size
= unwind
.opcode_count
- 2;
27126 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
27127 if (unwind
.personality_index
!= -1)
27129 as_bad (_("attempt to recreate an unwind entry"));
27133 /* An extra byte is required for the opcode count. */
27134 size
= unwind
.opcode_count
+ 1;
27137 size
= (size
+ 3) >> 2;
27139 as_bad (_("too many unwind opcodes"));
27141 frag_align (2, 0, 0);
27142 record_alignment (now_seg
, 2);
27143 unwind
.table_entry
= expr_build_dot ();
27145 /* Allocate the table entry. */
27146 ptr
= frag_more ((size
<< 2) + 4);
27147 /* PR 13449: Zero the table entries in case some of them are not used. */
27148 memset (ptr
, 0, (size
<< 2) + 4);
27149 where
= frag_now_fix () - ((size
<< 2) + 4);
27151 switch (unwind
.personality_index
)
27154 /* ??? Should this be a PLT generating relocation? */
27155 /* Custom personality routine. */
27156 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
27157 BFD_RELOC_ARM_PREL31
);
27162 /* Set the first byte to the number of additional words. */
27163 data
= size
> 0 ? size
- 1 : 0;
27167 /* ABI defined personality routines. */
27169 /* Three opcodes bytes are packed into the first word. */
27176 /* The size and first two opcode bytes go in the first word. */
27177 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
27182 /* Should never happen. */
27186 /* Pack the opcodes into words (MSB first), reversing the list at the same
27188 while (unwind
.opcode_count
> 0)
27192 md_number_to_chars (ptr
, data
, 4);
27197 unwind
.opcode_count
--;
27199 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27202 /* Finish off the last word. */
27205 /* Pad with "finish" opcodes. */
27207 data
= (data
<< 8) | 0xb0;
27209 md_number_to_chars (ptr
, data
, 4);
27214 /* Add an empty descriptor if there is no user-specified data. */
27215 ptr
= frag_more (4);
27216 md_number_to_chars (ptr
, 0, 4);
27223 /* Initialize the DWARF-2 unwind information for this procedure. */
27226 tc_arm_frame_initial_instructions (void)
27228 cfi_add_CFA_def_cfa (REG_SP
, 0);
27230 #endif /* OBJ_ELF */
27232 /* Convert REGNAME to a DWARF-2 register number. */
27235 tc_arm_regname_to_dw2regnum (char *regname
)
27237 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
27241 /* PR 16694: Allow VFP registers as well. */
27242 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
27246 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
27255 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
27259 exp
.X_op
= O_secrel
;
27260 exp
.X_add_symbol
= symbol
;
27261 exp
.X_add_number
= 0;
27262 emit_expr (&exp
, size
);
27266 /* MD interface: Symbol and relocation handling. */
27268 /* Return the address within the segment that a PC-relative fixup is
27269 relative to. For ARM, PC-relative fixups applied to instructions
27270 are generally relative to the location of the fixup plus 8 bytes.
27271 Thumb branches are offset by 4, and Thumb loads relative to PC
27272 require special handling. */
27275 md_pcrel_from_section (fixS
* fixP
, segT seg
)
27277 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27279 /* If this is pc-relative and we are going to emit a relocation
27280 then we just want to put out any pipeline compensation that the linker
27281 will need. Otherwise we want to use the calculated base.
27282 For WinCE we skip the bias for externals as well, since this
27283 is how the MS ARM-CE assembler behaves and we want to be compatible. */
27285 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27286 || (arm_force_relocation (fixP
)
27288 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
27294 switch (fixP
->fx_r_type
)
27296 /* PC relative addressing on the Thumb is slightly odd as the
27297 bottom two bits of the PC are forced to zero for the
27298 calculation. This happens *after* application of the
27299 pipeline offset. However, Thumb adrl already adjusts for
27300 this, so we need not do it again. */
27301 case BFD_RELOC_ARM_THUMB_ADD
:
27304 case BFD_RELOC_ARM_THUMB_OFFSET
:
27305 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27306 case BFD_RELOC_ARM_T32_ADD_PC12
:
27307 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27308 return (base
+ 4) & ~3;
27310 /* Thumb branches are simply offset by +4. */
27311 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27312 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27313 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27314 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27315 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27316 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27317 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27318 case BFD_RELOC_ARM_THUMB_BF17
:
27319 case BFD_RELOC_ARM_THUMB_BF19
:
27320 case BFD_RELOC_ARM_THUMB_BF13
:
27321 case BFD_RELOC_ARM_THUMB_LOOP12
:
27324 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27326 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27327 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27328 && ARM_IS_FUNC (fixP
->fx_addsy
)
27329 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27330 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27333 /* BLX is like branches above, but forces the low two bits of PC to
27335 case BFD_RELOC_THUMB_PCREL_BLX
:
27337 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27338 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27339 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27340 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27341 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27342 return (base
+ 4) & ~3;
27344 /* ARM mode branches are offset by +8. However, the Windows CE
27345 loader expects the relocation not to take this into account. */
27346 case BFD_RELOC_ARM_PCREL_BLX
:
27348 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27349 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27350 && ARM_IS_FUNC (fixP
->fx_addsy
)
27351 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27352 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27355 case BFD_RELOC_ARM_PCREL_CALL
:
27357 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27358 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27359 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27360 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27361 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27364 case BFD_RELOC_ARM_PCREL_BRANCH
:
27365 case BFD_RELOC_ARM_PCREL_JUMP
:
27366 case BFD_RELOC_ARM_PLT32
:
27368 /* When handling fixups immediately, because we have already
27369 discovered the value of a symbol, or the address of the frag involved
27370 we must account for the offset by +8, as the OS loader will never see the reloc.
27371 see fixup_segment() in write.c
27372 The S_IS_EXTERNAL test handles the case of global symbols.
27373 Those need the calculated base, not just the pipe compensation the linker will need. */
27375 && fixP
->fx_addsy
!= NULL
27376 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27377 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27385 /* ARM mode loads relative to PC are also offset by +8. Unlike
27386 branches, the Windows CE loader *does* expect the relocation
27387 to take this into account. */
27388 case BFD_RELOC_ARM_OFFSET_IMM
:
27389 case BFD_RELOC_ARM_OFFSET_IMM8
:
27390 case BFD_RELOC_ARM_HWLITERAL
:
27391 case BFD_RELOC_ARM_LITERAL
:
27392 case BFD_RELOC_ARM_CP_OFF_IMM
:
27396 /* Other PC-relative relocations are un-offset. */
27402 static bfd_boolean flag_warn_syms
= TRUE
;
27405 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27407 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27408 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27409 does mean that the resulting code might be very confusing to the reader.
27410 Also this warning can be triggered if the user omits an operand before
27411 an immediate address, eg:
27415 GAS treats this as an assignment of the value of the symbol foo to a
27416 symbol LDR, and so (without this code) it will not issue any kind of
27417 warning or error message.
27419 Note - ARM instructions are case-insensitive but the strings in the hash
27420 table are all stored in lower case, so we must first ensure that name is
27422 if (flag_warn_syms
&& arm_ops_hsh
)
27424 char * nbuf
= strdup (name
);
27427 for (p
= nbuf
; *p
; p
++)
27429 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
27431 static struct hash_control
* already_warned
= NULL
;
27433 if (already_warned
== NULL
)
27434 already_warned
= hash_new ();
27435 /* Only warn about the symbol once. To keep the code
27436 simple we let hash_insert do the lookup for us. */
27437 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
27438 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
27447 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
27448 Otherwise we have no need to default values of symbols. */
27451 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
27454 if (name
[0] == '_' && name
[1] == 'G'
27455 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
27459 if (symbol_find (name
))
27460 as_bad (_("GOT already in the symbol table"));
27462 GOT_symbol
= symbol_new (name
, undefined_section
,
27463 (valueT
) 0, & zero_address_frag
);
27473 /* Subroutine of md_apply_fix. Check to see if an immediate can be
27474 computed as two separate immediate values, added together. We
27475 already know that this value cannot be computed by just one ARM
27478 static unsigned int
27479 validate_immediate_twopart (unsigned int val
,
27480 unsigned int * highpart
)
27485 for (i
= 0; i
< 32; i
+= 2)
27486 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
27492 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
27494 else if (a
& 0xff0000)
27496 if (a
& 0xff000000)
27498 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
27502 gas_assert (a
& 0xff000000);
27503 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
27506 return (a
& 0xff) | (i
<< 7);
27513 validate_offset_imm (unsigned int val
, int hwse
)
27515 if ((hwse
&& val
> 255) || val
> 4095)
27520 /* Subroutine of md_apply_fix. Do those data_ops which can take a
27521 negative immediate constant by altering the instruction. A bit of
27526 by inverting the second operand, and
27529 by negating the second operand. */
27532 negate_data_op (unsigned long * instruction
,
27533 unsigned long value
)
27536 unsigned long negated
, inverted
;
27538 negated
= encode_arm_immediate (-value
);
27539 inverted
= encode_arm_immediate (~value
);
27541 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
27544 /* First negates. */
27545 case OPCODE_SUB
: /* ADD <-> SUB */
27546 new_inst
= OPCODE_ADD
;
27551 new_inst
= OPCODE_SUB
;
27555 case OPCODE_CMP
: /* CMP <-> CMN */
27556 new_inst
= OPCODE_CMN
;
27561 new_inst
= OPCODE_CMP
;
27565 /* Now Inverted ops. */
27566 case OPCODE_MOV
: /* MOV <-> MVN */
27567 new_inst
= OPCODE_MVN
;
27572 new_inst
= OPCODE_MOV
;
27576 case OPCODE_AND
: /* AND <-> BIC */
27577 new_inst
= OPCODE_BIC
;
27582 new_inst
= OPCODE_AND
;
27586 case OPCODE_ADC
: /* ADC <-> SBC */
27587 new_inst
= OPCODE_SBC
;
27592 new_inst
= OPCODE_ADC
;
27596 /* We cannot do anything. */
27601 if (value
== (unsigned) FAIL
)
27604 *instruction
&= OPCODE_MASK
;
27605 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
27609 /* Like negate_data_op, but for Thumb-2. */
27611 static unsigned int
27612 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
27616 unsigned int negated
, inverted
;
27618 negated
= encode_thumb32_immediate (-value
);
27619 inverted
= encode_thumb32_immediate (~value
);
27621 rd
= (*instruction
>> 8) & 0xf;
27622 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
27625 /* ADD <-> SUB. Includes CMP <-> CMN. */
27626 case T2_OPCODE_SUB
:
27627 new_inst
= T2_OPCODE_ADD
;
27631 case T2_OPCODE_ADD
:
27632 new_inst
= T2_OPCODE_SUB
;
27636 /* ORR <-> ORN. Includes MOV <-> MVN. */
27637 case T2_OPCODE_ORR
:
27638 new_inst
= T2_OPCODE_ORN
;
27642 case T2_OPCODE_ORN
:
27643 new_inst
= T2_OPCODE_ORR
;
27647 /* AND <-> BIC. TST has no inverted equivalent. */
27648 case T2_OPCODE_AND
:
27649 new_inst
= T2_OPCODE_BIC
;
27656 case T2_OPCODE_BIC
:
27657 new_inst
= T2_OPCODE_AND
;
27662 case T2_OPCODE_ADC
:
27663 new_inst
= T2_OPCODE_SBC
;
27667 case T2_OPCODE_SBC
:
27668 new_inst
= T2_OPCODE_ADC
;
27672 /* We cannot do anything. */
27677 if (value
== (unsigned int)FAIL
)
27680 *instruction
&= T2_OPCODE_MASK
;
27681 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
27685 /* Read a 32-bit thumb instruction from buf. */
27687 static unsigned long
27688 get_thumb32_insn (char * buf
)
27690 unsigned long insn
;
27691 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
27692 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27697 /* We usually want to set the low bit on the address of thumb function
27698 symbols. In particular .word foo - . should have the low bit set.
27699 Generic code tries to fold the difference of two symbols to
27700 a constant. Prevent this and force a relocation when the first symbols
27701 is a thumb function. */
27704 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
27706 if (op
== O_subtract
27707 && l
->X_op
== O_symbol
27708 && r
->X_op
== O_symbol
27709 && THUMB_IS_FUNC (l
->X_add_symbol
))
27711 l
->X_op
= O_subtract
;
27712 l
->X_op_symbol
= r
->X_add_symbol
;
27713 l
->X_add_number
-= r
->X_add_number
;
27717 /* Process as normal. */
27721 /* Encode Thumb2 unconditional branches and calls. The encoding
27722 for the 2 are identical for the immediate values. */
27725 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
27727 #define T2I1I2MASK ((1 << 13) | (1 << 11))
27730 addressT S
, I1
, I2
, lo
, hi
;
27732 S
= (value
>> 24) & 0x01;
27733 I1
= (value
>> 23) & 0x01;
27734 I2
= (value
>> 22) & 0x01;
27735 hi
= (value
>> 12) & 0x3ff;
27736 lo
= (value
>> 1) & 0x7ff;
27737 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27738 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27739 newval
|= (S
<< 10) | hi
;
27740 newval2
&= ~T2I1I2MASK
;
27741 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27742 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27743 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27747 md_apply_fix (fixS
* fixP
,
27751 offsetT value
= * valP
;
27753 unsigned int newimm
;
27754 unsigned long temp
;
27756 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27758 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27760 /* Note whether this will delete the relocation. */
27762 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27765 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27766 consistency with the behaviour on 32-bit hosts. Remember value
27768 value
&= 0xffffffff;
27769 value
^= 0x80000000;
27770 value
-= 0x80000000;
27773 fixP
->fx_addnumber
= value
;
27775 /* Same treatment for fixP->fx_offset. */
27776 fixP
->fx_offset
&= 0xffffffff;
27777 fixP
->fx_offset
^= 0x80000000;
27778 fixP
->fx_offset
-= 0x80000000;
27780 switch (fixP
->fx_r_type
)
27782 case BFD_RELOC_NONE
:
27783 /* This will need to go in the object file. */
27787 case BFD_RELOC_ARM_IMMEDIATE
:
27788 /* We claim that this fixup has been processed here,
27789 even if in fact we generate an error because we do
27790 not have a reloc for it, so tc_gen_reloc will reject it. */
27793 if (fixP
->fx_addsy
)
27795 const char *msg
= 0;
27797 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27798 msg
= _("undefined symbol %s used as an immediate value");
27799 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27800 msg
= _("symbol %s is in a different section");
27801 else if (S_IS_WEAK (fixP
->fx_addsy
))
27802 msg
= _("symbol %s is weak and may be overridden later");
27806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27807 msg
, S_GET_NAME (fixP
->fx_addsy
));
27812 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27814 /* If the offset is negative, we should use encoding A2 for ADR. */
27815 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27816 newimm
= negate_data_op (&temp
, value
);
27819 newimm
= encode_arm_immediate (value
);
27821 /* If the instruction will fail, see if we can fix things up by
27822 changing the opcode. */
27823 if (newimm
== (unsigned int) FAIL
)
27824 newimm
= negate_data_op (&temp
, value
);
27825 /* MOV accepts both ARM modified immediate (A1 encoding) and
27826 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27827 When disassembling, MOV is preferred when there is no encoding
27829 if (newimm
== (unsigned int) FAIL
27830 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27831 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27832 && !((temp
>> SBIT_SHIFT
) & 0x1)
27833 && value
>= 0 && value
<= 0xffff)
27835 /* Clear bits[23:20] to change encoding from A1 to A2. */
27836 temp
&= 0xff0fffff;
27837 /* Encoding high 4bits imm. Code below will encode the remaining
27839 temp
|= (value
& 0x0000f000) << 4;
27840 newimm
= value
& 0x00000fff;
27844 if (newimm
== (unsigned int) FAIL
)
27846 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27847 _("invalid constant (%lx) after fixup"),
27848 (unsigned long) value
);
27852 newimm
|= (temp
& 0xfffff000);
27853 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27856 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27858 unsigned int highpart
= 0;
27859 unsigned int newinsn
= 0xe1a00000; /* nop. */
27861 if (fixP
->fx_addsy
)
27863 const char *msg
= 0;
27865 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27866 msg
= _("undefined symbol %s used as an immediate value");
27867 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27868 msg
= _("symbol %s is in a different section");
27869 else if (S_IS_WEAK (fixP
->fx_addsy
))
27870 msg
= _("symbol %s is weak and may be overridden later");
27874 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27875 msg
, S_GET_NAME (fixP
->fx_addsy
));
27880 newimm
= encode_arm_immediate (value
);
27881 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27883 /* If the instruction will fail, see if we can fix things up by
27884 changing the opcode. */
27885 if (newimm
== (unsigned int) FAIL
27886 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27888 /* No ? OK - try using two ADD instructions to generate
27890 newimm
= validate_immediate_twopart (value
, & highpart
);
27892 /* Yes - then make sure that the second instruction is
27894 if (newimm
!= (unsigned int) FAIL
)
27896 /* Still No ? Try using a negated value. */
27897 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27898 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27899 /* Otherwise - give up. */
27902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27903 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27908 /* Replace the first operand in the 2nd instruction (which
27909 is the PC) with the destination register. We have
27910 already added in the PC in the first instruction and we
27911 do not want to do it again. */
27912 newinsn
&= ~ 0xf0000;
27913 newinsn
|= ((newinsn
& 0x0f000) << 4);
27916 newimm
|= (temp
& 0xfffff000);
27917 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27919 highpart
|= (newinsn
& 0xfffff000);
27920 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27924 case BFD_RELOC_ARM_OFFSET_IMM
:
27925 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27927 /* Fall through. */
27929 case BFD_RELOC_ARM_LITERAL
:
27935 if (validate_offset_imm (value
, 0) == FAIL
)
27937 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27938 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27939 _("invalid literal constant: pool needs to be closer"));
27941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27942 _("bad immediate value for offset (%ld)"),
27947 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27949 newval
&= 0xfffff000;
27952 newval
&= 0xff7ff000;
27953 newval
|= value
| (sign
? INDEX_UP
: 0);
27955 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27958 case BFD_RELOC_ARM_OFFSET_IMM8
:
27959 case BFD_RELOC_ARM_HWLITERAL
:
27965 if (validate_offset_imm (value
, 1) == FAIL
)
27967 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27969 _("invalid literal constant: pool needs to be closer"));
27971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27972 _("bad immediate value for 8-bit offset (%ld)"),
27977 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27979 newval
&= 0xfffff0f0;
27982 newval
&= 0xff7ff0f0;
27983 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27985 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27988 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27989 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27990 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27991 _("bad immediate value for offset (%ld)"), (long) value
);
27994 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27996 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27999 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
28000 /* This is a complicated relocation used for all varieties of Thumb32
28001 load/store instruction with immediate offset:
28003 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
28004 *4, optional writeback(W)
28005 (doubleword load/store)
28007 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
28008 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
28009 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
28010 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
28011 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
28013 Uppercase letters indicate bits that are already encoded at
28014 this point. Lowercase letters are our problem. For the
28015 second block of instructions, the secondary opcode nybble
28016 (bits 8..11) is present, and bit 23 is zero, even if this is
28017 a PC-relative operation. */
28018 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28020 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
28022 if ((newval
& 0xf0000000) == 0xe0000000)
28024 /* Doubleword load/store: 8-bit offset, scaled by 4. */
28026 newval
|= (1 << 23);
28029 if (value
% 4 != 0)
28031 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28032 _("offset not a multiple of 4"));
28038 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28039 _("offset out of range"));
28044 else if ((newval
& 0x000f0000) == 0x000f0000)
28046 /* PC-relative, 12-bit offset. */
28048 newval
|= (1 << 23);
28053 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28054 _("offset out of range"));
28059 else if ((newval
& 0x00000100) == 0x00000100)
28061 /* Writeback: 8-bit, +/- offset. */
28063 newval
|= (1 << 9);
28068 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28069 _("offset out of range"));
28074 else if ((newval
& 0x00000f00) == 0x00000e00)
28076 /* T-instruction: positive 8-bit offset. */
28077 if (value
< 0 || value
> 0xff)
28079 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28080 _("offset out of range"));
28088 /* Positive 12-bit or negative 8-bit offset. */
28092 newval
|= (1 << 23);
28102 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28103 _("offset out of range"));
28110 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
28111 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
28114 case BFD_RELOC_ARM_SHIFT_IMM
:
28115 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28116 if (((unsigned long) value
) > 32
28118 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
28120 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28121 _("shift expression is too large"));
28126 /* Shifts of zero must be done as lsl. */
28128 else if (value
== 32)
28130 newval
&= 0xfffff07f;
28131 newval
|= (value
& 0x1f) << 7;
28132 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28135 case BFD_RELOC_ARM_T32_IMMEDIATE
:
28136 case BFD_RELOC_ARM_T32_ADD_IMM
:
28137 case BFD_RELOC_ARM_T32_IMM12
:
28138 case BFD_RELOC_ARM_T32_ADD_PC12
:
28139 /* We claim that this fixup has been processed here,
28140 even if in fact we generate an error because we do
28141 not have a reloc for it, so tc_gen_reloc will reject it. */
28145 && ! S_IS_DEFINED (fixP
->fx_addsy
))
28147 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28148 _("undefined symbol %s used as an immediate value"),
28149 S_GET_NAME (fixP
->fx_addsy
));
28153 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28155 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
28158 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28159 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28160 Thumb2 modified immediate encoding (T2). */
28161 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
28162 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28164 newimm
= encode_thumb32_immediate (value
);
28165 if (newimm
== (unsigned int) FAIL
)
28166 newimm
= thumb32_negate_data_op (&newval
, value
);
28168 if (newimm
== (unsigned int) FAIL
)
28170 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
28172 /* Turn add/sum into addw/subw. */
28173 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28174 newval
= (newval
& 0xfeffffff) | 0x02000000;
28175 /* No flat 12-bit imm encoding for addsw/subsw. */
28176 if ((newval
& 0x00100000) == 0)
28178 /* 12 bit immediate for addw/subw. */
28182 newval
^= 0x00a00000;
28185 newimm
= (unsigned int) FAIL
;
28192 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28193 UINT16 (T3 encoding), MOVW only accepts UINT16. When
28194 disassembling, MOV is preferred when there is no encoding
28196 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
28197 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28198 but with the Rn field [19:16] set to 1111. */
28199 && (((newval
>> 16) & 0xf) == 0xf)
28200 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
28201 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
28202 && value
>= 0 && value
<= 0xffff)
28204 /* Toggle bit[25] to change encoding from T2 to T3. */
28206 /* Clear bits[19:16]. */
28207 newval
&= 0xfff0ffff;
28208 /* Encoding high 4bits imm. Code below will encode the
28209 remaining low 12bits. */
28210 newval
|= (value
& 0x0000f000) << 4;
28211 newimm
= value
& 0x00000fff;
28216 if (newimm
== (unsigned int)FAIL
)
28218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28219 _("invalid constant (%lx) after fixup"),
28220 (unsigned long) value
);
28224 newval
|= (newimm
& 0x800) << 15;
28225 newval
|= (newimm
& 0x700) << 4;
28226 newval
|= (newimm
& 0x0ff);
28228 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
28229 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
28232 case BFD_RELOC_ARM_SMC
:
28233 if (((unsigned long) value
) > 0xf)
28234 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28235 _("invalid smc expression"));
28237 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28238 newval
|= (value
& 0xf);
28239 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28242 case BFD_RELOC_ARM_HVC
:
28243 if (((unsigned long) value
) > 0xffff)
28244 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28245 _("invalid hvc expression"));
28246 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28247 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
28248 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28251 case BFD_RELOC_ARM_SWI
:
28252 if (fixP
->tc_fix_data
!= 0)
28254 if (((unsigned long) value
) > 0xff)
28255 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28256 _("invalid swi expression"));
28257 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28259 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28263 if (((unsigned long) value
) > 0x00ffffff)
28264 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28265 _("invalid swi expression"));
28266 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28268 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28272 case BFD_RELOC_ARM_MULTI
:
28273 if (((unsigned long) value
) > 0xffff)
28274 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28275 _("invalid expression in load/store multiple"));
28276 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
28277 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28281 case BFD_RELOC_ARM_PCREL_CALL
:
28283 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28285 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28286 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28287 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28288 /* Flip the bl to blx. This is a simple flip
28289 bit here because we generate PCREL_CALL for
28290 unconditional bls. */
28292 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28293 newval
= newval
| 0x10000000;
28294 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28300 goto arm_branch_common
;
28302 case BFD_RELOC_ARM_PCREL_JUMP
:
28303 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28305 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28306 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28307 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28309 /* This would map to a bl<cond>, b<cond>,
28310 b<always> to a Thumb function. We
28311 need to force a relocation for this particular
28313 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28316 /* Fall through. */
28318 case BFD_RELOC_ARM_PLT32
:
28320 case BFD_RELOC_ARM_PCREL_BRANCH
:
28322 goto arm_branch_common
;
28324 case BFD_RELOC_ARM_PCREL_BLX
:
28327 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28329 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28330 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28331 && ARM_IS_FUNC (fixP
->fx_addsy
))
28333 /* Flip the blx to a bl and warn. */
28334 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28335 newval
= 0xeb000000;
28336 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28337 _("blx to '%s' an ARM ISA state function changed to bl"),
28339 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28345 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28346 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
28350 /* We are going to store value (shifted right by two) in the
28351 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28352 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28356 _("misaligned branch destination"));
28357 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
28358 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
28359 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28361 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28363 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28364 newval
|= (value
>> 2) & 0x00ffffff;
28365 /* Set the H bit on BLX instructions. */
28369 newval
|= 0x01000000;
28371 newval
&= ~0x01000000;
28373 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28377 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28378 /* CBZ can only branch forward. */
28380 /* Attempts to use CBZ to branch to the next instruction
28381 (which, strictly speaking, are prohibited) will be turned into
28384 FIXME: It may be better to remove the instruction completely and
28385 perform relaxation. */
28388 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28389 newval
= 0xbf00; /* NOP encoding T1 */
28390 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28397 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28399 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28400 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28401 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28406 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28407 if (out_of_range_p (value
, 8))
28408 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28410 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28412 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28413 newval
|= (value
& 0x1ff) >> 1;
28414 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28418 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28419 if (out_of_range_p (value
, 11))
28420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28422 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28424 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28425 newval
|= (value
& 0xfff) >> 1;
28426 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28430 /* This relocation is misnamed, it should be BRANCH21. */
28431 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28433 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28434 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28435 && ARM_IS_FUNC (fixP
->fx_addsy
)
28436 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28438 /* Force a relocation for a branch 20 bits wide. */
28441 if (out_of_range_p (value
, 20))
28442 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28443 _("conditional branch out of range"));
28445 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28448 addressT S
, J1
, J2
, lo
, hi
;
28450 S
= (value
& 0x00100000) >> 20;
28451 J2
= (value
& 0x00080000) >> 19;
28452 J1
= (value
& 0x00040000) >> 18;
28453 hi
= (value
& 0x0003f000) >> 12;
28454 lo
= (value
& 0x00000ffe) >> 1;
28456 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28457 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28458 newval
|= (S
<< 10) | hi
;
28459 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
28460 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28461 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28465 case BFD_RELOC_THUMB_PCREL_BLX
:
28466 /* If there is a blx from a thumb state function to
28467 another thumb function flip this to a bl and warn
28471 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28472 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28473 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28475 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28476 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28477 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
28479 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28480 newval
= newval
| 0x1000;
28481 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28482 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28487 goto thumb_bl_common
;
28489 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28490 /* A bl from Thumb state ISA to an internal ARM state function
28491 is converted to a blx. */
28493 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28494 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28495 && ARM_IS_FUNC (fixP
->fx_addsy
)
28496 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28498 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28499 newval
= newval
& ~0x1000;
28500 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28501 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
28507 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28508 /* For a BLX instruction, make sure that the relocation is rounded up
28509 to a word boundary. This follows the semantics of the instruction
28510 which specifies that bit 1 of the target address will come from bit
28511 1 of the base address. */
28512 value
= (value
+ 3) & ~ 3;
28515 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
28516 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28517 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28520 if (out_of_range_p (value
, 22))
28522 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
28523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28524 else if (out_of_range_p (value
, 24))
28525 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28526 _("Thumb2 branch out of range"));
28529 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28530 encode_thumb2_b_bl_offset (buf
, value
);
28534 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28535 if (out_of_range_p (value
, 24))
28536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28538 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28539 encode_thumb2_b_bl_offset (buf
, value
);
28544 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28549 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28550 md_number_to_chars (buf
, value
, 2);
28554 case BFD_RELOC_ARM_TLS_CALL
:
28555 case BFD_RELOC_ARM_THM_TLS_CALL
:
28556 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28557 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28558 case BFD_RELOC_ARM_TLS_GOTDESC
:
28559 case BFD_RELOC_ARM_TLS_GD32
:
28560 case BFD_RELOC_ARM_TLS_LE32
:
28561 case BFD_RELOC_ARM_TLS_IE32
:
28562 case BFD_RELOC_ARM_TLS_LDM32
:
28563 case BFD_RELOC_ARM_TLS_LDO32
:
28564 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28567 /* Same handling as above, but with the arm_fdpic guard. */
28568 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28569 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28570 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28573 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28578 _("Relocation supported only in FDPIC mode"));
28582 case BFD_RELOC_ARM_GOT32
:
28583 case BFD_RELOC_ARM_GOTOFF
:
28586 case BFD_RELOC_ARM_GOT_PREL
:
28587 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28588 md_number_to_chars (buf
, value
, 4);
28591 case BFD_RELOC_ARM_TARGET2
:
28592 /* TARGET2 is not partial-inplace, so we need to write the
28593 addend here for REL targets, because it won't be written out
28594 during reloc processing later. */
28595 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28596 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
28599 /* Relocations for FDPIC. */
28600 case BFD_RELOC_ARM_GOTFUNCDESC
:
28601 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28602 case BFD_RELOC_ARM_FUNCDESC
:
28605 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28606 md_number_to_chars (buf
, 0, 4);
28610 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28611 _("Relocation supported only in FDPIC mode"));
28616 case BFD_RELOC_RVA
:
28618 case BFD_RELOC_ARM_TARGET1
:
28619 case BFD_RELOC_ARM_ROSEGREL32
:
28620 case BFD_RELOC_ARM_SBREL32
:
28621 case BFD_RELOC_32_PCREL
:
28623 case BFD_RELOC_32_SECREL
:
28625 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28627 /* For WinCE we only do this for pcrel fixups. */
28628 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
28630 md_number_to_chars (buf
, value
, 4);
28634 case BFD_RELOC_ARM_PREL31
:
28635 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28637 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
28638 if ((value
^ (value
>> 1)) & 0x40000000)
28640 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28641 _("rel31 relocation overflow"));
28643 newval
|= value
& 0x7fffffff;
28644 md_number_to_chars (buf
, newval
, 4);
28649 case BFD_RELOC_ARM_CP_OFF_IMM
:
28650 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
28651 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
28652 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
28653 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28655 newval
= get_thumb32_insn (buf
);
28656 if ((newval
& 0x0f200f00) == 0x0d000900)
28658 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28659 has permitted values that are multiples of 2, in the range 0
28661 if (value
< -510 || value
> 510 || (value
& 1))
28662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28663 _("co-processor offset out of range"));
28665 else if ((newval
& 0xfe001f80) == 0xec000f80)
28667 if (value
< -511 || value
> 512 || (value
& 3))
28668 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28669 _("co-processor offset out of range"));
28671 else if (value
< -1023 || value
> 1023 || (value
& 3))
28672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28673 _("co-processor offset out of range"));
28678 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28679 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28680 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28682 newval
= get_thumb32_insn (buf
);
28685 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28686 newval
&= 0xffffff80;
28688 newval
&= 0xffffff00;
28692 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28693 newval
&= 0xff7fff80;
28695 newval
&= 0xff7fff00;
28696 if ((newval
& 0x0f200f00) == 0x0d000900)
28698 /* This is a fp16 vstr/vldr.
28700 It requires the immediate offset in the instruction is shifted
28701 left by 1 to be a half-word offset.
28703 Here, left shift by 1 first, and later right shift by 2
28704 should get the right offset. */
28707 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
28709 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28710 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28711 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28713 put_thumb32_insn (buf
, newval
);
28716 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
28717 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
28718 if (value
< -255 || value
> 255)
28719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28720 _("co-processor offset out of range"));
28722 goto cp_off_common
;
28724 case BFD_RELOC_ARM_THUMB_OFFSET
:
28725 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28726 /* Exactly what ranges, and where the offset is inserted depends
28727 on the type of instruction, we can establish this from the
28729 switch (newval
>> 12)
28731 case 4: /* PC load. */
28732 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28733 forced to zero for these loads; md_pcrel_from has already
28734 compensated for this. */
28736 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28737 _("invalid offset, target not word aligned (0x%08lX)"),
28738 (((unsigned long) fixP
->fx_frag
->fr_address
28739 + (unsigned long) fixP
->fx_where
) & ~3)
28740 + (unsigned long) value
);
28742 if (value
& ~0x3fc)
28743 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28744 _("invalid offset, value too big (0x%08lX)"),
28747 newval
|= value
>> 2;
28750 case 9: /* SP load/store. */
28751 if (value
& ~0x3fc)
28752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28753 _("invalid offset, value too big (0x%08lX)"),
28755 newval
|= value
>> 2;
28758 case 6: /* Word load/store. */
28760 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28761 _("invalid offset, value too big (0x%08lX)"),
28763 newval
|= value
<< 4; /* 6 - 2. */
28766 case 7: /* Byte load/store. */
28768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28769 _("invalid offset, value too big (0x%08lX)"),
28771 newval
|= value
<< 6;
28774 case 8: /* Halfword load/store. */
28776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28777 _("invalid offset, value too big (0x%08lX)"),
28779 newval
|= value
<< 5; /* 6 - 1. */
28783 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28784 "Unable to process relocation for thumb opcode: %lx",
28785 (unsigned long) newval
);
28788 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28791 case BFD_RELOC_ARM_THUMB_ADD
:
28792 /* This is a complicated relocation, since we use it for all of
28793 the following immediate relocations:
28797 9bit ADD/SUB SP word-aligned
28798 10bit ADD PC/SP word-aligned
28800 The type of instruction being processed is encoded in the
28807 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28809 int rd
= (newval
>> 4) & 0xf;
28810 int rs
= newval
& 0xf;
28811 int subtract
= !!(newval
& 0x8000);
28813 /* Check for HI regs, only very restricted cases allowed:
28814 Adjusting SP, and using PC or SP to get an address. */
28815 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28816 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28818 _("invalid Hi register with immediate"));
28820 /* If value is negative, choose the opposite instruction. */
28824 subtract
= !subtract
;
28826 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28827 _("immediate value out of range"));
28832 if (value
& ~0x1fc)
28833 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28834 _("invalid immediate for stack address calculation"));
28835 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28836 newval
|= value
>> 2;
28838 else if (rs
== REG_PC
|| rs
== REG_SP
)
28840 /* PR gas/18541. If the addition is for a defined symbol
28841 within range of an ADR instruction then accept it. */
28844 && fixP
->fx_addsy
!= NULL
)
28848 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28849 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28850 || S_IS_WEAK (fixP
->fx_addsy
))
28852 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28853 _("address calculation needs a strongly defined nearby symbol"));
28857 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28859 /* Round up to the next 4-byte boundary. */
28864 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28868 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28869 _("symbol too far away"));
28879 if (subtract
|| value
& ~0x3fc)
28880 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28881 _("invalid immediate for address calculation (value = 0x%08lX)"),
28882 (unsigned long) (subtract
? - value
: value
));
28883 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28885 newval
|= value
>> 2;
28890 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28891 _("immediate value out of range"));
28892 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28893 newval
|= (rd
<< 8) | value
;
28898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28899 _("immediate value out of range"));
28900 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28901 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28904 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28907 case BFD_RELOC_ARM_THUMB_IMM
:
28908 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28909 if (value
< 0 || value
> 255)
28910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28911 _("invalid immediate: %ld is out of range"),
28914 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28917 case BFD_RELOC_ARM_THUMB_SHIFT
:
28918 /* 5bit shift value (0..32). LSL cannot take 32. */
28919 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28920 temp
= newval
& 0xf800;
28921 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28923 _("invalid shift value: %ld"), (long) value
);
28924 /* Shifts of zero must be encoded as LSL. */
28926 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28927 /* Shifts of 32 are encoded as zero. */
28928 else if (value
== 32)
28930 newval
|= value
<< 6;
28931 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28934 case BFD_RELOC_VTABLE_INHERIT
:
28935 case BFD_RELOC_VTABLE_ENTRY
:
28939 case BFD_RELOC_ARM_MOVW
:
28940 case BFD_RELOC_ARM_MOVT
:
28941 case BFD_RELOC_ARM_THUMB_MOVW
:
28942 case BFD_RELOC_ARM_THUMB_MOVT
:
28943 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28945 /* REL format relocations are limited to a 16-bit addend. */
28946 if (!fixP
->fx_done
)
28948 if (value
< -0x8000 || value
> 0x7fff)
28949 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28950 _("offset out of range"));
28952 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28953 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28958 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28959 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28961 newval
= get_thumb32_insn (buf
);
28962 newval
&= 0xfbf08f00;
28963 newval
|= (value
& 0xf000) << 4;
28964 newval
|= (value
& 0x0800) << 15;
28965 newval
|= (value
& 0x0700) << 4;
28966 newval
|= (value
& 0x00ff);
28967 put_thumb32_insn (buf
, newval
);
28971 newval
= md_chars_to_number (buf
, 4);
28972 newval
&= 0xfff0f000;
28973 newval
|= value
& 0x0fff;
28974 newval
|= (value
& 0xf000) << 4;
28975 md_number_to_chars (buf
, newval
, 4);
28980 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28981 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28982 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28983 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28984 gas_assert (!fixP
->fx_done
);
28987 bfd_boolean is_mov
;
28988 bfd_vma encoded_addend
= value
;
28990 /* Check that addend can be encoded in instruction. */
28991 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28992 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28993 _("the offset 0x%08lX is not representable"),
28994 (unsigned long) encoded_addend
);
28996 /* Extract the instruction. */
28997 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28998 is_mov
= (insn
& 0xf800) == 0x2000;
29003 if (!seg
->use_rela_p
)
29004 insn
|= encoded_addend
;
29010 /* Extract the instruction. */
29011 /* Encoding is the following
29016 /* The following conditions must be true :
29021 rd
= (insn
>> 4) & 0xf;
29023 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
29024 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29025 _("Unable to process relocation for thumb opcode: %lx"),
29026 (unsigned long) insn
);
29028 /* Encode as ADD immediate8 thumb 1 code. */
29029 insn
= 0x3000 | (rd
<< 8);
29031 /* Place the encoded addend into the first 8 bits of the
29033 if (!seg
->use_rela_p
)
29034 insn
|= encoded_addend
;
29037 /* Update the instruction. */
29038 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
29042 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29043 case BFD_RELOC_ARM_ALU_PC_G0
:
29044 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29045 case BFD_RELOC_ARM_ALU_PC_G1
:
29046 case BFD_RELOC_ARM_ALU_PC_G2
:
29047 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29048 case BFD_RELOC_ARM_ALU_SB_G0
:
29049 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29050 case BFD_RELOC_ARM_ALU_SB_G1
:
29051 case BFD_RELOC_ARM_ALU_SB_G2
:
29052 gas_assert (!fixP
->fx_done
);
29053 if (!seg
->use_rela_p
)
29056 bfd_vma encoded_addend
;
29057 bfd_vma addend_abs
= llabs (value
);
29059 /* Check that the absolute value of the addend can be
29060 expressed as an 8-bit constant plus a rotation. */
29061 encoded_addend
= encode_arm_immediate (addend_abs
);
29062 if (encoded_addend
== (unsigned int) FAIL
)
29063 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29064 _("the offset 0x%08lX is not representable"),
29065 (unsigned long) addend_abs
);
29067 /* Extract the instruction. */
29068 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29070 /* If the addend is positive, use an ADD instruction.
29071 Otherwise use a SUB. Take care not to destroy the S bit. */
29072 insn
&= 0xff1fffff;
29078 /* Place the encoded addend into the first 12 bits of the
29080 insn
&= 0xfffff000;
29081 insn
|= encoded_addend
;
29083 /* Update the instruction. */
29084 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29088 case BFD_RELOC_ARM_LDR_PC_G0
:
29089 case BFD_RELOC_ARM_LDR_PC_G1
:
29090 case BFD_RELOC_ARM_LDR_PC_G2
:
29091 case BFD_RELOC_ARM_LDR_SB_G0
:
29092 case BFD_RELOC_ARM_LDR_SB_G1
:
29093 case BFD_RELOC_ARM_LDR_SB_G2
:
29094 gas_assert (!fixP
->fx_done
);
29095 if (!seg
->use_rela_p
)
29098 bfd_vma addend_abs
= llabs (value
);
29100 /* Check that the absolute value of the addend can be
29101 encoded in 12 bits. */
29102 if (addend_abs
>= 0x1000)
29103 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29104 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
29105 (unsigned long) addend_abs
);
29107 /* Extract the instruction. */
29108 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29110 /* If the addend is negative, clear bit 23 of the instruction.
29111 Otherwise set it. */
29113 insn
&= ~(1 << 23);
29117 /* Place the absolute value of the addend into the first 12 bits
29118 of the instruction. */
29119 insn
&= 0xfffff000;
29120 insn
|= addend_abs
;
29122 /* Update the instruction. */
29123 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29127 case BFD_RELOC_ARM_LDRS_PC_G0
:
29128 case BFD_RELOC_ARM_LDRS_PC_G1
:
29129 case BFD_RELOC_ARM_LDRS_PC_G2
:
29130 case BFD_RELOC_ARM_LDRS_SB_G0
:
29131 case BFD_RELOC_ARM_LDRS_SB_G1
:
29132 case BFD_RELOC_ARM_LDRS_SB_G2
:
29133 gas_assert (!fixP
->fx_done
);
29134 if (!seg
->use_rela_p
)
29137 bfd_vma addend_abs
= llabs (value
);
29139 /* Check that the absolute value of the addend can be
29140 encoded in 8 bits. */
29141 if (addend_abs
>= 0x100)
29142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29143 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29144 (unsigned long) addend_abs
);
29146 /* Extract the instruction. */
29147 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29149 /* If the addend is negative, clear bit 23 of the instruction.
29150 Otherwise set it. */
29152 insn
&= ~(1 << 23);
29156 /* Place the first four bits of the absolute value of the addend
29157 into the first 4 bits of the instruction, and the remaining
29158 four into bits 8 .. 11. */
29159 insn
&= 0xfffff0f0;
29160 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
29162 /* Update the instruction. */
29163 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29167 case BFD_RELOC_ARM_LDC_PC_G0
:
29168 case BFD_RELOC_ARM_LDC_PC_G1
:
29169 case BFD_RELOC_ARM_LDC_PC_G2
:
29170 case BFD_RELOC_ARM_LDC_SB_G0
:
29171 case BFD_RELOC_ARM_LDC_SB_G1
:
29172 case BFD_RELOC_ARM_LDC_SB_G2
:
29173 gas_assert (!fixP
->fx_done
);
29174 if (!seg
->use_rela_p
)
29177 bfd_vma addend_abs
= llabs (value
);
29179 /* Check that the absolute value of the addend is a multiple of
29180 four and, when divided by four, fits in 8 bits. */
29181 if (addend_abs
& 0x3)
29182 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29183 _("bad offset 0x%08lX (must be word-aligned)"),
29184 (unsigned long) addend_abs
);
29186 if ((addend_abs
>> 2) > 0xff)
29187 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29188 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29189 (unsigned long) addend_abs
);
29191 /* Extract the instruction. */
29192 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29194 /* If the addend is negative, clear bit 23 of the instruction.
29195 Otherwise set it. */
29197 insn
&= ~(1 << 23);
29201 /* Place the addend (divided by four) into the first eight
29202 bits of the instruction. */
29203 insn
&= 0xfffffff0;
29204 insn
|= addend_abs
>> 2;
29206 /* Update the instruction. */
29207 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29211 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29213 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29214 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29215 && ARM_IS_FUNC (fixP
->fx_addsy
)
29216 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29218 /* Force a relocation for a branch 5 bits wide. */
29221 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
29222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29225 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29227 addressT boff
= value
>> 1;
29229 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29230 newval
|= (boff
<< 7);
29231 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29235 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29237 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29238 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29239 && ARM_IS_FUNC (fixP
->fx_addsy
)
29240 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29244 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
29245 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29246 _("branch out of range"));
29248 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29250 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29252 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
29253 addressT diff
= value
- boff
;
29257 newval
|= 1 << 1; /* T bit. */
29259 else if (diff
!= 2)
29261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29262 _("out of range label-relative fixup value"));
29264 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29268 case BFD_RELOC_ARM_THUMB_BF17
:
29270 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29271 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29272 && ARM_IS_FUNC (fixP
->fx_addsy
)
29273 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29275 /* Force a relocation for a branch 17 bits wide. */
29279 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
29280 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29283 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29286 addressT immA
, immB
, immC
;
29288 immA
= (value
& 0x0001f000) >> 12;
29289 immB
= (value
& 0x00000ffc) >> 2;
29290 immC
= (value
& 0x00000002) >> 1;
29292 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29293 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29295 newval2
|= (immC
<< 11) | (immB
<< 1);
29296 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29297 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29301 case BFD_RELOC_ARM_THUMB_BF19
:
29303 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29304 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29305 && ARM_IS_FUNC (fixP
->fx_addsy
)
29306 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29308 /* Force a relocation for a branch 19 bits wide. */
29312 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
29313 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29316 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29319 addressT immA
, immB
, immC
;
29321 immA
= (value
& 0x0007f000) >> 12;
29322 immB
= (value
& 0x00000ffc) >> 2;
29323 immC
= (value
& 0x00000002) >> 1;
29325 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29326 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29328 newval2
|= (immC
<< 11) | (immB
<< 1);
29329 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29330 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29334 case BFD_RELOC_ARM_THUMB_BF13
:
29336 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29337 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29338 && ARM_IS_FUNC (fixP
->fx_addsy
)
29339 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29341 /* Force a relocation for a branch 13 bits wide. */
29345 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
29346 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29349 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29352 addressT immA
, immB
, immC
;
29354 immA
= (value
& 0x00001000) >> 12;
29355 immB
= (value
& 0x00000ffc) >> 2;
29356 immC
= (value
& 0x00000002) >> 1;
29358 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29359 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29361 newval2
|= (immC
<< 11) | (immB
<< 1);
29362 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29363 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29367 case BFD_RELOC_ARM_THUMB_LOOP12
:
29369 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29370 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29371 && ARM_IS_FUNC (fixP
->fx_addsy
)
29372 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29374 /* Force a relocation for a branch 12 bits wide. */
29378 bfd_vma insn
= get_thumb32_insn (buf
);
29379 /* le lr, <label>, le <label> or letp lr, <label> */
29380 if (((insn
& 0xffffffff) == 0xf00fc001)
29381 || ((insn
& 0xffffffff) == 0xf02fc001)
29382 || ((insn
& 0xffffffff) == 0xf01fc001))
29385 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29388 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29390 addressT imml
, immh
;
29392 immh
= (value
& 0x00000ffc) >> 2;
29393 imml
= (value
& 0x00000002) >> 1;
29395 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29396 newval
|= (imml
<< 11) | (immh
<< 1);
29397 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29401 case BFD_RELOC_ARM_V4BX
:
29402 /* This will need to go in the object file. */
29406 case BFD_RELOC_UNUSED
:
29408 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29409 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29413 /* Translate internal representation of relocation info to BFD target
29417 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29420 bfd_reloc_code_real_type code
;
29422 reloc
= XNEW (arelent
);
29424 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29425 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29426 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
29428 if (fixp
->fx_pcrel
)
29430 if (section
->use_rela_p
)
29431 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
29433 fixp
->fx_offset
= reloc
->address
;
29435 reloc
->addend
= fixp
->fx_offset
;
29437 switch (fixp
->fx_r_type
)
29440 if (fixp
->fx_pcrel
)
29442 code
= BFD_RELOC_8_PCREL
;
29445 /* Fall through. */
29448 if (fixp
->fx_pcrel
)
29450 code
= BFD_RELOC_16_PCREL
;
29453 /* Fall through. */
29456 if (fixp
->fx_pcrel
)
29458 code
= BFD_RELOC_32_PCREL
;
29461 /* Fall through. */
29463 case BFD_RELOC_ARM_MOVW
:
29464 if (fixp
->fx_pcrel
)
29466 code
= BFD_RELOC_ARM_MOVW_PCREL
;
29469 /* Fall through. */
29471 case BFD_RELOC_ARM_MOVT
:
29472 if (fixp
->fx_pcrel
)
29474 code
= BFD_RELOC_ARM_MOVT_PCREL
;
29477 /* Fall through. */
29479 case BFD_RELOC_ARM_THUMB_MOVW
:
29480 if (fixp
->fx_pcrel
)
29482 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
29485 /* Fall through. */
29487 case BFD_RELOC_ARM_THUMB_MOVT
:
29488 if (fixp
->fx_pcrel
)
29490 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
29493 /* Fall through. */
29495 case BFD_RELOC_NONE
:
29496 case BFD_RELOC_ARM_PCREL_BRANCH
:
29497 case BFD_RELOC_ARM_PCREL_BLX
:
29498 case BFD_RELOC_RVA
:
29499 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
29500 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
29501 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
29502 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29503 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29504 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29505 case BFD_RELOC_VTABLE_ENTRY
:
29506 case BFD_RELOC_VTABLE_INHERIT
:
29508 case BFD_RELOC_32_SECREL
:
29510 code
= fixp
->fx_r_type
;
29513 case BFD_RELOC_THUMB_PCREL_BLX
:
29515 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
29516 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29519 code
= BFD_RELOC_THUMB_PCREL_BLX
;
29522 case BFD_RELOC_ARM_LITERAL
:
29523 case BFD_RELOC_ARM_HWLITERAL
:
29524 /* If this is called then the a literal has
29525 been referenced across a section boundary. */
29526 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29527 _("literal referenced across section boundary"));
29531 case BFD_RELOC_ARM_TLS_CALL
:
29532 case BFD_RELOC_ARM_THM_TLS_CALL
:
29533 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29534 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29535 case BFD_RELOC_ARM_GOT32
:
29536 case BFD_RELOC_ARM_GOTOFF
:
29537 case BFD_RELOC_ARM_GOT_PREL
:
29538 case BFD_RELOC_ARM_PLT32
:
29539 case BFD_RELOC_ARM_TARGET1
:
29540 case BFD_RELOC_ARM_ROSEGREL32
:
29541 case BFD_RELOC_ARM_SBREL32
:
29542 case BFD_RELOC_ARM_PREL31
:
29543 case BFD_RELOC_ARM_TARGET2
:
29544 case BFD_RELOC_ARM_TLS_LDO32
:
29545 case BFD_RELOC_ARM_PCREL_CALL
:
29546 case BFD_RELOC_ARM_PCREL_JUMP
:
29547 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29548 case BFD_RELOC_ARM_ALU_PC_G0
:
29549 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29550 case BFD_RELOC_ARM_ALU_PC_G1
:
29551 case BFD_RELOC_ARM_ALU_PC_G2
:
29552 case BFD_RELOC_ARM_LDR_PC_G0
:
29553 case BFD_RELOC_ARM_LDR_PC_G1
:
29554 case BFD_RELOC_ARM_LDR_PC_G2
:
29555 case BFD_RELOC_ARM_LDRS_PC_G0
:
29556 case BFD_RELOC_ARM_LDRS_PC_G1
:
29557 case BFD_RELOC_ARM_LDRS_PC_G2
:
29558 case BFD_RELOC_ARM_LDC_PC_G0
:
29559 case BFD_RELOC_ARM_LDC_PC_G1
:
29560 case BFD_RELOC_ARM_LDC_PC_G2
:
29561 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29562 case BFD_RELOC_ARM_ALU_SB_G0
:
29563 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29564 case BFD_RELOC_ARM_ALU_SB_G1
:
29565 case BFD_RELOC_ARM_ALU_SB_G2
:
29566 case BFD_RELOC_ARM_LDR_SB_G0
:
29567 case BFD_RELOC_ARM_LDR_SB_G1
:
29568 case BFD_RELOC_ARM_LDR_SB_G2
:
29569 case BFD_RELOC_ARM_LDRS_SB_G0
:
29570 case BFD_RELOC_ARM_LDRS_SB_G1
:
29571 case BFD_RELOC_ARM_LDRS_SB_G2
:
29572 case BFD_RELOC_ARM_LDC_SB_G0
:
29573 case BFD_RELOC_ARM_LDC_SB_G1
:
29574 case BFD_RELOC_ARM_LDC_SB_G2
:
29575 case BFD_RELOC_ARM_V4BX
:
29576 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29577 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29578 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29579 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29580 case BFD_RELOC_ARM_GOTFUNCDESC
:
29581 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29582 case BFD_RELOC_ARM_FUNCDESC
:
29583 case BFD_RELOC_ARM_THUMB_BF17
:
29584 case BFD_RELOC_ARM_THUMB_BF19
:
29585 case BFD_RELOC_ARM_THUMB_BF13
:
29586 code
= fixp
->fx_r_type
;
29589 case BFD_RELOC_ARM_TLS_GOTDESC
:
29590 case BFD_RELOC_ARM_TLS_GD32
:
29591 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29592 case BFD_RELOC_ARM_TLS_LE32
:
29593 case BFD_RELOC_ARM_TLS_IE32
:
29594 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29595 case BFD_RELOC_ARM_TLS_LDM32
:
29596 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29597 /* BFD will include the symbol's address in the addend.
29598 But we don't want that, so subtract it out again here. */
29599 if (!S_IS_COMMON (fixp
->fx_addsy
))
29600 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
29601 code
= fixp
->fx_r_type
;
29605 case BFD_RELOC_ARM_IMMEDIATE
:
29606 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29607 _("internal relocation (type: IMMEDIATE) not fixed up"));
29610 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
29611 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29612 _("ADRL used for a symbol not defined in the same file"));
29615 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29616 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29617 case BFD_RELOC_ARM_THUMB_LOOP12
:
29618 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29619 _("%s used for a symbol not defined in the same file"),
29620 bfd_get_reloc_code_name (fixp
->fx_r_type
));
29623 case BFD_RELOC_ARM_OFFSET_IMM
:
29624 if (section
->use_rela_p
)
29626 code
= fixp
->fx_r_type
;
29630 if (fixp
->fx_addsy
!= NULL
29631 && !S_IS_DEFINED (fixp
->fx_addsy
)
29632 && S_IS_LOCAL (fixp
->fx_addsy
))
29634 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29635 _("undefined local label `%s'"),
29636 S_GET_NAME (fixp
->fx_addsy
));
29640 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29641 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29648 switch (fixp
->fx_r_type
)
29650 case BFD_RELOC_NONE
: type
= "NONE"; break;
29651 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
29652 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
29653 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
29654 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
29655 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
29656 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
29657 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
29658 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
29659 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
29660 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
29661 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
29662 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
29663 default: type
= _("<unknown>"); break;
29665 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29666 _("cannot represent %s relocation in this object file format"),
29673 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
29675 && fixp
->fx_addsy
== GOT_symbol
)
29677 code
= BFD_RELOC_ARM_GOTPC
;
29678 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
29682 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
29684 if (reloc
->howto
== NULL
)
29686 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29687 _("cannot represent %s relocation in this object file format"),
29688 bfd_get_reloc_code_name (code
));
29692 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29693 vtable entry to be used in the relocation's section offset. */
29694 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29695 reloc
->address
= fixp
->fx_offset
;
29700 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
29703 cons_fix_new_arm (fragS
* frag
,
29707 bfd_reloc_code_real_type reloc
)
29712 FIXME: @@ Should look at CPU word size. */
29716 reloc
= BFD_RELOC_8
;
29719 reloc
= BFD_RELOC_16
;
29723 reloc
= BFD_RELOC_32
;
29726 reloc
= BFD_RELOC_64
;
29731 if (exp
->X_op
== O_secrel
)
29733 exp
->X_op
= O_symbol
;
29734 reloc
= BFD_RELOC_32_SECREL
;
29738 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29741 #if defined (OBJ_COFF)
29743 arm_validate_fix (fixS
* fixP
)
29745 /* If the destination of the branch is a defined symbol which does not have
29746 the THUMB_FUNC attribute, then we must be calling a function which has
29747 the (interfacearm) attribute. We look for the Thumb entry point to that
29748 function and change the branch to refer to that function instead. */
29749 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29750 && fixP
->fx_addsy
!= NULL
29751 && S_IS_DEFINED (fixP
->fx_addsy
)
29752 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29754 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29761 arm_force_relocation (struct fix
* fixp
)
29763 #if defined (OBJ_COFF) && defined (TE_PE)
29764 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29768 /* In case we have a call or a branch to a function in ARM ISA mode from
29769 a thumb function or vice-versa force the relocation. These relocations
29770 are cleared off for some cores that might have blx and simple transformations
29774 switch (fixp
->fx_r_type
)
29776 case BFD_RELOC_ARM_PCREL_JUMP
:
29777 case BFD_RELOC_ARM_PCREL_CALL
:
29778 case BFD_RELOC_THUMB_PCREL_BLX
:
29779 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29783 case BFD_RELOC_ARM_PCREL_BLX
:
29784 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29785 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29786 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29787 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29796 /* Resolve these relocations even if the symbol is extern or weak.
29797 Technically this is probably wrong due to symbol preemption.
29798 In practice these relocations do not have enough range to be useful
29799 at dynamic link time, and some code (e.g. in the Linux kernel)
29800 expects these references to be resolved. */
29801 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29802 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29803 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29804 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29805 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29806 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29807 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29808 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29809 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29810 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29811 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29812 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29813 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29814 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29817 /* Always leave these relocations for the linker. */
29818 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29819 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29820 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29823 /* Always generate relocations against function symbols. */
29824 if (fixp
->fx_r_type
== BFD_RELOC_32
29826 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29829 return generic_force_reloc (fixp
);
29832 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29833 /* Relocations against function names must be left unadjusted,
29834 so that the linker can use this information to generate interworking
29835 stubs. The MIPS version of this function
29836 also prevents relocations that are mips-16 specific, but I do not
29837 know why it does this.
29840 There is one other problem that ought to be addressed here, but
29841 which currently is not: Taking the address of a label (rather
29842 than a function) and then later jumping to that address. Such
29843 addresses also ought to have their bottom bit set (assuming that
29844 they reside in Thumb code), but at the moment they will not. */
29847 arm_fix_adjustable (fixS
* fixP
)
29849 if (fixP
->fx_addsy
== NULL
)
29852 /* Preserve relocations against symbols with function type. */
29853 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29856 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29857 && fixP
->fx_subsy
== NULL
)
29860 /* We need the symbol name for the VTABLE entries. */
29861 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29862 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29865 /* Don't allow symbols to be discarded on GOT related relocs. */
29866 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29867 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29868 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29869 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29870 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29871 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29872 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29873 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29874 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29875 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29876 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29877 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29878 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29879 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29880 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29881 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29882 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29885 /* Similarly for group relocations. */
29886 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29887 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29888 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29891 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29892 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29893 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29894 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29895 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29896 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29897 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29898 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29899 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29902 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29903 offsets, so keep these symbols. */
29904 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29905 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29910 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29914 elf32_arm_target_format (void)
29917 return (target_big_endian
29918 ? "elf32-bigarm-symbian"
29919 : "elf32-littlearm-symbian");
29920 #elif defined (TE_VXWORKS)
29921 return (target_big_endian
29922 ? "elf32-bigarm-vxworks"
29923 : "elf32-littlearm-vxworks");
29924 #elif defined (TE_NACL)
29925 return (target_big_endian
29926 ? "elf32-bigarm-nacl"
29927 : "elf32-littlearm-nacl");
29931 if (target_big_endian
)
29932 return "elf32-bigarm-fdpic";
29934 return "elf32-littlearm-fdpic";
29938 if (target_big_endian
)
29939 return "elf32-bigarm";
29941 return "elf32-littlearm";
29947 armelf_frob_symbol (symbolS
* symp
,
29950 elf_frob_symbol (symp
, puntp
);
29954 /* MD interface: Finalization. */
29959 literal_pool
* pool
;
29961 /* Ensure that all the predication blocks are properly closed. */
29962 check_pred_blocks_finished ();
29964 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29966 /* Put it at the end of the relevant section. */
29967 subseg_set (pool
->section
, pool
->sub_section
);
29969 arm_elf_change_section ();
29976 /* Remove any excess mapping symbols generated for alignment frags in
29977 SEC. We may have created a mapping symbol before a zero byte
29978 alignment; remove it if there's a mapping symbol after the
29981 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29982 void *dummy ATTRIBUTE_UNUSED
)
29984 segment_info_type
*seginfo
= seg_info (sec
);
29987 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29990 for (fragp
= seginfo
->frchainP
->frch_root
;
29992 fragp
= fragp
->fr_next
)
29994 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29995 fragS
*next
= fragp
->fr_next
;
29997 /* Variable-sized frags have been converted to fixed size by
29998 this point. But if this was variable-sized to start with,
29999 there will be a fixed-size frag after it. So don't handle
30001 if (sym
== NULL
|| next
== NULL
)
30004 if (S_GET_VALUE (sym
) < next
->fr_address
)
30005 /* Not at the end of this frag. */
30007 know (S_GET_VALUE (sym
) == next
->fr_address
);
30011 if (next
->tc_frag_data
.first_map
!= NULL
)
30013 /* Next frag starts with a mapping symbol. Discard this
30015 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30019 if (next
->fr_next
== NULL
)
30021 /* This mapping symbol is at the end of the section. Discard
30023 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
30024 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30028 /* As long as we have empty frags without any mapping symbols,
30030 /* If the next frag is non-empty and does not start with a
30031 mapping symbol, then this mapping symbol is required. */
30032 if (next
->fr_address
!= next
->fr_next
->fr_address
)
30035 next
= next
->fr_next
;
30037 while (next
!= NULL
);
30042 /* Adjust the symbol table. This marks Thumb symbols as distinct from
30046 arm_adjust_symtab (void)
30051 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30053 if (ARM_IS_THUMB (sym
))
30055 if (THUMB_IS_FUNC (sym
))
30057 /* Mark the symbol as a Thumb function. */
30058 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
30059 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
30060 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
30062 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
30063 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
30065 as_bad (_("%s: unexpected function type: %d"),
30066 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
30068 else switch (S_GET_STORAGE_CLASS (sym
))
30071 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
30074 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
30077 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
30085 if (ARM_IS_INTERWORK (sym
))
30086 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
30093 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30095 if (ARM_IS_THUMB (sym
))
30097 elf_symbol_type
* elf_sym
;
30099 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
30100 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
30102 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
30103 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
30105 /* If it's a .thumb_func, declare it as so,
30106 otherwise tag label as .code 16. */
30107 if (THUMB_IS_FUNC (sym
))
30108 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
30109 ST_BRANCH_TO_THUMB
);
30110 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30111 elf_sym
->internal_elf_sym
.st_info
=
30112 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
30117 /* Remove any overlapping mapping symbols generated by alignment frags. */
30118 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
30119 /* Now do generic ELF adjustments. */
30120 elf_adjust_symtab ();
30124 /* MD interface: Initialization. */
30127 set_constant_flonums (void)
30131 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
30132 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
30136 /* Auto-select Thumb mode if it's the only available instruction set for the
30137 given architecture. */
30140 autoselect_thumb_from_cpu_variant (void)
30142 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
30143 opcode_select (16);
30152 if ( (arm_ops_hsh
= hash_new ()) == NULL
30153 || (arm_cond_hsh
= hash_new ()) == NULL
30154 || (arm_vcond_hsh
= hash_new ()) == NULL
30155 || (arm_shift_hsh
= hash_new ()) == NULL
30156 || (arm_psr_hsh
= hash_new ()) == NULL
30157 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
30158 || (arm_reg_hsh
= hash_new ()) == NULL
30159 || (arm_reloc_hsh
= hash_new ()) == NULL
30160 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
30161 as_fatal (_("virtual memory exhausted"));
30163 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
30164 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
30165 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
30166 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
30167 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
30168 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
30169 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
30170 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
30171 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
30172 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
30173 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
30174 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
30175 (void *) (v7m_psrs
+ i
));
30176 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
30177 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
30179 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
30181 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
30182 (void *) (barrier_opt_names
+ i
));
30184 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
30186 struct reloc_entry
* entry
= reloc_names
+ i
;
30188 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
30189 /* This makes encode_branch() use the EABI versions of this relocation. */
30190 entry
->reloc
= BFD_RELOC_UNUSED
;
30192 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
30196 set_constant_flonums ();
30198 /* Set the cpu variant based on the command-line options. We prefer
30199 -mcpu= over -march= if both are set (as for GCC); and we prefer
30200 -mfpu= over any other way of setting the floating point unit.
30201 Use of legacy options with new options are faulted. */
30204 if (mcpu_cpu_opt
|| march_cpu_opt
)
30205 as_bad (_("use of old and new-style options to set CPU type"));
30207 selected_arch
= *legacy_cpu
;
30209 else if (mcpu_cpu_opt
)
30211 selected_arch
= *mcpu_cpu_opt
;
30212 selected_ext
= *mcpu_ext_opt
;
30214 else if (march_cpu_opt
)
30216 selected_arch
= *march_cpu_opt
;
30217 selected_ext
= *march_ext_opt
;
30219 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30224 as_bad (_("use of old and new-style options to set FPU type"));
30226 selected_fpu
= *legacy_fpu
;
30229 selected_fpu
= *mfpu_opt
;
30232 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30233 || defined (TE_NetBSD) || defined (TE_VXWORKS))
30234 /* Some environments specify a default FPU. If they don't, infer it
30235 from the processor. */
30237 selected_fpu
= *mcpu_fpu_opt
;
30238 else if (march_fpu_opt
)
30239 selected_fpu
= *march_fpu_opt
;
30241 selected_fpu
= fpu_default
;
30245 if (ARM_FEATURE_ZERO (selected_fpu
))
30247 if (!no_cpu_selected ())
30248 selected_fpu
= fpu_default
;
30250 selected_fpu
= fpu_arch_fpa
;
30254 if (ARM_FEATURE_ZERO (selected_arch
))
30256 selected_arch
= cpu_default
;
30257 selected_cpu
= selected_arch
;
30259 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30261 /* Autodection of feature mode: allow all features in cpu_variant but leave
30262 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
30263 after all instruction have been processed and we can decide what CPU
30264 should be selected. */
30265 if (ARM_FEATURE_ZERO (selected_arch
))
30266 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30268 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30271 autoselect_thumb_from_cpu_variant ();
30273 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
30275 #if defined OBJ_COFF || defined OBJ_ELF
30277 unsigned int flags
= 0;
30279 #if defined OBJ_ELF
30280 flags
= meabi_flags
;
30282 switch (meabi_flags
)
30284 case EF_ARM_EABI_UNKNOWN
:
30286 /* Set the flags in the private structure. */
30287 if (uses_apcs_26
) flags
|= F_APCS26
;
30288 if (support_interwork
) flags
|= F_INTERWORK
;
30289 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
30290 if (pic_code
) flags
|= F_PIC
;
30291 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
30292 flags
|= F_SOFT_FLOAT
;
30294 switch (mfloat_abi_opt
)
30296 case ARM_FLOAT_ABI_SOFT
:
30297 case ARM_FLOAT_ABI_SOFTFP
:
30298 flags
|= F_SOFT_FLOAT
;
30301 case ARM_FLOAT_ABI_HARD
:
30302 if (flags
& F_SOFT_FLOAT
)
30303 as_bad (_("hard-float conflicts with specified fpu"));
30307 /* Using pure-endian doubles (even if soft-float). */
30308 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
30309 flags
|= F_VFP_FLOAT
;
30311 #if defined OBJ_ELF
30312 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
30313 flags
|= EF_ARM_MAVERICK_FLOAT
;
30316 case EF_ARM_EABI_VER4
:
30317 case EF_ARM_EABI_VER5
:
30318 /* No additional flags to set. */
30325 bfd_set_private_flags (stdoutput
, flags
);
30327 /* We have run out flags in the COFF header to encode the
30328 status of ATPCS support, so instead we create a dummy,
30329 empty, debug section called .arm.atpcs. */
30334 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
30338 bfd_set_section_flags (sec
, SEC_READONLY
| SEC_DEBUGGING
);
30339 bfd_set_section_size (sec
, 0);
30340 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
30346 /* Record the CPU type as well. */
30347 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
30348 mach
= bfd_mach_arm_iWMMXt2
;
30349 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
30350 mach
= bfd_mach_arm_iWMMXt
;
30351 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
30352 mach
= bfd_mach_arm_XScale
;
30353 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
30354 mach
= bfd_mach_arm_ep9312
;
30355 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
30356 mach
= bfd_mach_arm_5TE
;
30357 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
30359 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30360 mach
= bfd_mach_arm_5T
;
30362 mach
= bfd_mach_arm_5
;
30364 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30366 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30367 mach
= bfd_mach_arm_4T
;
30369 mach
= bfd_mach_arm_4
;
30371 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30372 mach
= bfd_mach_arm_3M
;
30373 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30374 mach
= bfd_mach_arm_3
;
30375 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30376 mach
= bfd_mach_arm_2a
;
30377 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30378 mach
= bfd_mach_arm_2
;
30380 mach
= bfd_mach_arm_unknown
;
30382 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30385 /* Command line processing. */
30388 Invocation line includes a switch not recognized by the base assembler.
30389 See if it's a processor-specific option.
30391 This routine is somewhat complicated by the need for backwards
30392 compatibility (since older releases of gcc can't be changed).
30393 The new options try to make the interface as compatible as
30396 New options (supported) are:
30398 -mcpu=<cpu name> Assemble for selected processor
30399 -march=<architecture name> Assemble for selected architecture
30400 -mfpu=<fpu architecture> Assemble for selected FPU.
30401 -EB/-mbig-endian Big-endian
30402 -EL/-mlittle-endian Little-endian
30403 -k Generate PIC code
30404 -mthumb Start in Thumb mode
30405 -mthumb-interwork Code supports ARM/Thumb interworking
30407 -m[no-]warn-deprecated Warn about deprecated features
30408 -m[no-]warn-syms Warn when symbols match instructions
30410 For now we will also provide support for:
30412 -mapcs-32 32-bit Program counter
30413 -mapcs-26 26-bit Program counter
30414 -macps-float Floats passed in FP registers
30415 -mapcs-reentrant Reentrant code
30417 (sometime these will probably be replaced with -mapcs=<list of options>
30418 and -matpcs=<list of options>)
30420 The remaining options are only supported for back-wards compatibility.
30421 Cpu variants, the arm part is optional:
30422 -m[arm]1 Currently not supported.
30423 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30424 -m[arm]3 Arm 3 processor
30425 -m[arm]6[xx], Arm 6 processors
30426 -m[arm]7[xx][t][[d]m] Arm 7 processors
30427 -m[arm]8[10] Arm 8 processors
30428 -m[arm]9[20][tdmi] Arm 9 processors
30429 -mstrongarm[110[0]] StrongARM processors
30430 -mxscale XScale processors
30431 -m[arm]v[2345[t[e]]] Arm architectures
30432 -mall All (except the ARM1)
30434 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
30435 -mfpe-old (No float load/store multiples)
30436 -mvfpxd VFP Single precision
30438 -mno-fpu Disable all floating point instructions
30440 The following CPU names are recognized:
30441 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
30442 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
30443 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
30444 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
30445 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
30446 arm10t arm10e, arm1020t, arm1020e, arm10200e,
30447 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
30451 const char * md_shortopts
= "m:k";
30453 #ifdef ARM_BI_ENDIAN
30454 #define OPTION_EB (OPTION_MD_BASE + 0)
30455 #define OPTION_EL (OPTION_MD_BASE + 1)
30457 #if TARGET_BYTES_BIG_ENDIAN
30458 #define OPTION_EB (OPTION_MD_BASE + 0)
30460 #define OPTION_EL (OPTION_MD_BASE + 1)
30463 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
30464 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
30466 struct option md_longopts
[] =
30469 {"EB", no_argument
, NULL
, OPTION_EB
},
30472 {"EL", no_argument
, NULL
, OPTION_EL
},
30474 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
30476 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
30478 {NULL
, no_argument
, NULL
, 0}
30481 size_t md_longopts_size
= sizeof (md_longopts
);
30483 struct arm_option_table
30485 const char * option
; /* Option name to match. */
30486 const char * help
; /* Help information. */
30487 int * var
; /* Variable to change. */
30488 int value
; /* What to change it to. */
30489 const char * deprecated
; /* If non-null, print this message. */
30492 struct arm_option_table arm_opts
[] =
30494 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
30495 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
30496 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
30497 &support_interwork
, 1, NULL
},
30498 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
30499 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
30500 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
30502 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
30503 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
30504 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
30505 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
30508 /* These are recognized by the assembler, but have no affect on code. */
30509 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
30510 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
30512 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
30513 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
30514 &warn_on_deprecated
, 0, NULL
},
30515 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
30516 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
30517 {NULL
, NULL
, NULL
, 0, NULL
}
30520 struct arm_legacy_option_table
30522 const char * option
; /* Option name to match. */
30523 const arm_feature_set
** var
; /* Variable to change. */
30524 const arm_feature_set value
; /* What to change it to. */
30525 const char * deprecated
; /* If non-null, print this message. */
30528 const struct arm_legacy_option_table arm_legacy_opts
[] =
30530 /* DON'T add any new processors to this list -- we want the whole list
30531 to go away... Add them to the processors table instead. */
30532 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30533 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30534 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30535 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30536 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30537 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30538 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30539 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30540 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30541 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30542 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30543 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30544 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30545 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30546 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30547 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30548 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30549 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30550 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30551 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30552 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30553 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30554 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30555 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30556 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30557 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30558 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30559 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30560 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30561 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30562 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30563 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30564 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30565 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30566 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30567 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30568 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30569 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30570 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30571 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30572 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30573 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30574 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30575 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30576 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30577 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30578 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30579 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30580 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30581 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30582 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30583 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30584 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30585 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30586 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30587 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30588 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30589 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30590 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30591 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30592 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30593 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30594 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30595 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30596 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30597 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30598 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30599 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30600 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
30601 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
30602 N_("use -mcpu=strongarm110")},
30603 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
30604 N_("use -mcpu=strongarm1100")},
30605 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
30606 N_("use -mcpu=strongarm1110")},
30607 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
30608 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
30609 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
30611 /* Architecture variants -- don't add any more to this list either. */
30612 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30613 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30614 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30615 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30616 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30617 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30618 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30619 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30620 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30621 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30622 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30623 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30624 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30625 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30626 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30627 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30628 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30629 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30631 /* Floating point variants -- don't add any more to this list either. */
30632 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
30633 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
30634 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
30635 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
30636 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
30638 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
30641 struct arm_cpu_option_table
30645 const arm_feature_set value
;
30646 const arm_feature_set ext
;
30647 /* For some CPUs we assume an FPU unless the user explicitly sets
30649 const arm_feature_set default_fpu
;
30650 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30652 const char * canonical_name
;
30655 /* This list should, at a minimum, contain all the cpu names
30656 recognized by GCC. */
30657 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
30659 static const struct arm_cpu_option_table arm_cpus
[] =
30661 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
30664 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
30667 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
30670 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
30673 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
30676 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
30679 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
30682 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
30685 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
30688 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
30691 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
30694 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
30697 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
30700 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
30703 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
30706 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
30709 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
30712 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
30715 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
30718 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
30721 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
30724 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
30727 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
30730 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
30733 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30736 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30739 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30742 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30745 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30748 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30751 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30754 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30757 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30760 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30763 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30766 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30769 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30772 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30775 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30778 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30781 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30784 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30787 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30790 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30793 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30796 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30800 /* For V5 or later processors we default to using VFP; but the user
30801 should really set the FPU type explicitly. */
30802 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30805 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30808 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30811 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30814 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30817 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30820 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30823 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30826 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30829 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30832 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30835 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30838 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30841 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30844 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30847 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30850 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30853 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30856 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30859 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30862 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30865 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30868 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30871 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30874 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30877 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30880 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30883 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30886 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30889 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30892 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30895 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30898 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30901 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30904 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30907 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30910 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30911 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30913 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30915 FPU_ARCH_NEON_VFP_V4
),
30916 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30917 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30918 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30919 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30920 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30921 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30922 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30924 FPU_ARCH_NEON_VFP_V4
),
30925 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30927 FPU_ARCH_NEON_VFP_V4
),
30928 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30930 FPU_ARCH_NEON_VFP_V4
),
30931 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30932 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30933 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30934 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30935 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30936 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30937 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30938 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30939 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30940 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30941 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30942 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30943 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30944 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30945 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30946 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30947 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30948 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30949 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30950 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30951 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30952 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30953 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30954 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30955 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30956 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30957 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30958 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
30959 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30960 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30961 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
30962 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30963 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30964 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30965 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30966 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30967 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30970 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30972 FPU_ARCH_VFP_V3D16
),
30973 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30974 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30976 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30977 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30978 FPU_ARCH_VFP_V3D16
),
30979 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30980 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30981 FPU_ARCH_VFP_V3D16
),
30982 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30983 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30984 FPU_ARCH_NEON_VFP_ARMV8
),
30985 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
30986 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30988 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30989 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30991 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30994 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30997 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
31000 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
31003 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
31006 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
31009 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
31012 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
31013 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
31014 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31015 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
31016 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31017 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31018 /* ??? XSCALE is really an architecture. */
31019 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
31023 /* ??? iwmmxt is not a processor. */
31024 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
31027 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
31030 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
31035 ARM_CPU_OPT ("ep9312", "ARM920T",
31036 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
31037 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
31039 /* Marvell processors. */
31040 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
31041 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31042 FPU_ARCH_VFP_V3D16
),
31043 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
31044 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31045 FPU_ARCH_NEON_VFP_V4
),
31047 /* APM X-Gene family. */
31048 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
31050 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31051 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
31052 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
31053 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31055 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31059 struct arm_ext_table
31063 const arm_feature_set merge
;
31064 const arm_feature_set clear
;
31067 struct arm_arch_option_table
31071 const arm_feature_set value
;
31072 const arm_feature_set default_fpu
;
31073 const struct arm_ext_table
* ext_table
;
31076 /* Used to add support for +E and +noE extension. */
31077 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
31078 /* Used to add support for a +E extension. */
31079 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
31080 /* Used to add support for a +noE extension. */
31081 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
31083 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
31084 ~0 & ~FPU_ENDIAN_PURE)
31086 static const struct arm_ext_table armv5te_ext_table
[] =
31088 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
31089 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31092 static const struct arm_ext_table armv7_ext_table
[] =
31094 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31095 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31098 static const struct arm_ext_table armv7ve_ext_table
[] =
31100 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
31101 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
31102 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31103 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31104 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31105 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
31106 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31108 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
31109 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31111 /* Aliases for +simd. */
31112 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31114 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31115 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31116 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31118 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31121 static const struct arm_ext_table armv7a_ext_table
[] =
31123 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31124 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31125 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31126 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31127 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31128 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
31129 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31131 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
31132 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31134 /* Aliases for +simd. */
31135 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31136 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31138 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31139 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31141 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
31142 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
31143 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31146 static const struct arm_ext_table armv7r_ext_table
[] =
31148 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
31149 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
31150 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31151 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31152 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
31153 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31154 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31155 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
31156 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31159 static const struct arm_ext_table armv7em_ext_table
[] =
31161 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
31162 /* Alias for +fp, used to be known as fpv4-sp-d16. */
31163 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
31164 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
31165 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31166 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
31167 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31170 static const struct arm_ext_table armv8a_ext_table
[] =
31172 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
31173 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31174 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31175 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31177 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31178 should use the +simd option to turn on FP. */
31179 ARM_REMOVE ("fp", ALL_FP
),
31180 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31181 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31182 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31186 static const struct arm_ext_table armv81a_ext_table
[] =
31188 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31189 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31190 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31192 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31193 should use the +simd option to turn on FP. */
31194 ARM_REMOVE ("fp", ALL_FP
),
31195 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31196 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31197 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31200 static const struct arm_ext_table armv82a_ext_table
[] =
31202 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31203 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
31204 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
31205 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31206 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31207 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31208 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31209 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31211 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31212 should use the +simd option to turn on FP. */
31213 ARM_REMOVE ("fp", ALL_FP
),
31214 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31215 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31216 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31219 static const struct arm_ext_table armv84a_ext_table
[] =
31221 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31222 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31223 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31224 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31225 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31226 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31228 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31229 should use the +simd option to turn on FP. */
31230 ARM_REMOVE ("fp", ALL_FP
),
31231 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31232 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31233 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31236 static const struct arm_ext_table armv85a_ext_table
[] =
31238 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31239 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31240 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31241 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31242 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31243 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31245 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31246 should use the +simd option to turn on FP. */
31247 ARM_REMOVE ("fp", ALL_FP
),
31248 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31251 static const struct arm_ext_table armv86a_ext_table
[] =
31253 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31254 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31257 static const struct arm_ext_table armv8m_main_ext_table
[] =
31259 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31260 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
31261 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
31262 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31263 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31266 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
31268 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31269 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
31271 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31272 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
31275 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31276 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31277 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
31278 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
31280 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31281 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
31282 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31283 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31286 static const struct arm_ext_table armv8r_ext_table
[] =
31288 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
31289 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31290 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31291 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31292 ARM_REMOVE ("fp", ALL_FP
),
31293 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
31294 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31297 /* This list should, at a minimum, contain all the architecture names
31298 recognized by GCC. */
31299 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
31300 #define ARM_ARCH_OPT2(N, V, DF, ext) \
31301 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
31303 static const struct arm_arch_option_table arm_archs
[] =
31305 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
31306 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
31307 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
31308 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31309 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31310 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
31311 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
31312 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
31313 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
31314 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
31315 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
31316 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
31317 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
31318 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
31319 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
31320 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
31321 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
31322 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31323 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31324 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
31325 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
31326 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31327 kept to preserve existing behaviour. */
31328 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31329 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31330 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
31331 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
31332 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
31333 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31334 kept to preserve existing behaviour. */
31335 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31336 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31337 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
31338 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
31339 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
31340 /* The official spelling of the ARMv7 profile variants is the dashed form.
31341 Accept the non-dashed form for compatibility with old toolchains. */
31342 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31343 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
31344 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31345 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31346 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31347 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31348 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31349 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
31350 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
31351 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
31353 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
31355 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
31356 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
31357 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
31358 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
31359 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
31360 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
31361 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
31362 ARM_ARCH_OPT2 ("armv8.6-a", ARM_ARCH_V8_6A
, FPU_ARCH_VFP
, armv86a
),
31363 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
31364 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
31365 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
31366 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31368 #undef ARM_ARCH_OPT
31370 /* ISA extensions in the co-processor and main instruction set space. */
31372 struct arm_option_extension_value_table
31376 const arm_feature_set merge_value
;
31377 const arm_feature_set clear_value
;
31378 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31379 indicates that an extension is available for all architectures while
31380 ARM_ANY marks an empty entry. */
31381 const arm_feature_set allowed_archs
[2];
31384 /* The following table must be in alphabetical order with a NULL last entry. */
31386 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31387 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
31389 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
31390 use the context sensitive approach using arm_ext_table's. */
31391 static const struct arm_option_extension_value_table arm_extensions
[] =
31393 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
31394 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31395 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31396 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
31397 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31398 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
31399 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
31401 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31402 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31403 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
31404 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
31405 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31406 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31407 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31409 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31410 | ARM_EXT2_FP16_FML
),
31411 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31412 | ARM_EXT2_FP16_FML
),
31414 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31415 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31416 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31417 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31418 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
31419 Thumb divide instruction. Due to this having the same name as the
31420 previous entry, this will be ignored when doing command-line parsing and
31421 only considered by build attribute selection code. */
31422 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31423 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31424 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
31425 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
31426 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
31427 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
31428 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
31429 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
31430 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
31431 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31432 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31433 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31434 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31435 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31436 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31437 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
31438 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
31439 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
31440 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31441 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31442 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31444 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
31445 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
31446 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31447 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
31448 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
31449 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31450 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31451 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31453 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31454 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31455 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
31456 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31457 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
31458 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
31459 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31460 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
31462 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
31463 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31464 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
31465 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
31466 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
31470 /* ISA floating-point and Advanced SIMD extensions. */
31471 struct arm_option_fpu_value_table
31474 const arm_feature_set value
;
31477 /* This list should, at a minimum, contain all the fpu names
31478 recognized by GCC. */
31479 static const struct arm_option_fpu_value_table arm_fpus
[] =
31481 {"softfpa", FPU_NONE
},
31482 {"fpe", FPU_ARCH_FPE
},
31483 {"fpe2", FPU_ARCH_FPE
},
31484 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
31485 {"fpa", FPU_ARCH_FPA
},
31486 {"fpa10", FPU_ARCH_FPA
},
31487 {"fpa11", FPU_ARCH_FPA
},
31488 {"arm7500fe", FPU_ARCH_FPA
},
31489 {"softvfp", FPU_ARCH_VFP
},
31490 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
31491 {"vfp", FPU_ARCH_VFP_V2
},
31492 {"vfp9", FPU_ARCH_VFP_V2
},
31493 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
31494 {"vfp10", FPU_ARCH_VFP_V2
},
31495 {"vfp10-r0", FPU_ARCH_VFP_V1
},
31496 {"vfpxd", FPU_ARCH_VFP_V1xD
},
31497 {"vfpv2", FPU_ARCH_VFP_V2
},
31498 {"vfpv3", FPU_ARCH_VFP_V3
},
31499 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
31500 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
31501 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
31502 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
31503 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
31504 {"arm1020t", FPU_ARCH_VFP_V1
},
31505 {"arm1020e", FPU_ARCH_VFP_V2
},
31506 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
31507 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
31508 {"maverick", FPU_ARCH_MAVERICK
},
31509 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31510 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31511 {"neon-fp16", FPU_ARCH_NEON_FP16
},
31512 {"vfpv4", FPU_ARCH_VFP_V4
},
31513 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
31514 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
31515 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
31516 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
31517 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
31518 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
31519 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
31520 {"crypto-neon-fp-armv8",
31521 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
31522 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
31523 {"crypto-neon-fp-armv8.1",
31524 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
31525 {NULL
, ARM_ARCH_NONE
}
31528 struct arm_option_value_table
31534 static const struct arm_option_value_table arm_float_abis
[] =
31536 {"hard", ARM_FLOAT_ABI_HARD
},
31537 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
31538 {"soft", ARM_FLOAT_ABI_SOFT
},
31543 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
31544 static const struct arm_option_value_table arm_eabis
[] =
31546 {"gnu", EF_ARM_EABI_UNKNOWN
},
31547 {"4", EF_ARM_EABI_VER4
},
31548 {"5", EF_ARM_EABI_VER5
},
31553 struct arm_long_option_table
31555 const char * option
; /* Substring to match. */
31556 const char * help
; /* Help information. */
31557 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
31558 const char * deprecated
; /* If non-null, print this message. */
31562 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
31563 arm_feature_set
*ext_set
,
31564 const struct arm_ext_table
*ext_table
)
31566 /* We insist on extensions being specified in alphabetical order, and with
31567 extensions being added before being removed. We achieve this by having
31568 the global ARM_EXTENSIONS table in alphabetical order, and using the
31569 ADDING_VALUE variable to indicate whether we are adding an extension (1)
31570 or removing it (0) and only allowing it to change in the order
31572 const struct arm_option_extension_value_table
* opt
= NULL
;
31573 const arm_feature_set arm_any
= ARM_ANY
;
31574 int adding_value
= -1;
31576 while (str
!= NULL
&& *str
!= 0)
31583 as_bad (_("invalid architectural extension"));
31588 ext
= strchr (str
, '+');
31593 len
= strlen (str
);
31595 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
31597 if (adding_value
!= 0)
31600 opt
= arm_extensions
;
31608 if (adding_value
== -1)
31611 opt
= arm_extensions
;
31613 else if (adding_value
!= 1)
31615 as_bad (_("must specify extensions to add before specifying "
31616 "those to remove"));
31623 as_bad (_("missing architectural extension"));
31627 gas_assert (adding_value
!= -1);
31628 gas_assert (opt
!= NULL
);
31630 if (ext_table
!= NULL
)
31632 const struct arm_ext_table
* ext_opt
= ext_table
;
31633 bfd_boolean found
= FALSE
;
31634 for (; ext_opt
->name
!= NULL
; ext_opt
++)
31635 if (ext_opt
->name_len
== len
31636 && strncmp (ext_opt
->name
, str
, len
) == 0)
31640 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
31641 /* TODO: Option not supported. When we remove the
31642 legacy table this case should error out. */
31645 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
31649 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
31650 /* TODO: Option not supported. When we remove the
31651 legacy table this case should error out. */
31653 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
31665 /* Scan over the options table trying to find an exact match. */
31666 for (; opt
->name
!= NULL
; opt
++)
31667 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31669 int i
, nb_allowed_archs
=
31670 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31671 /* Check we can apply the extension to this architecture. */
31672 for (i
= 0; i
< nb_allowed_archs
; i
++)
31675 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
31677 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
31680 if (i
== nb_allowed_archs
)
31682 as_bad (_("extension does not apply to the base architecture"));
31686 /* Add or remove the extension. */
31688 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
31690 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
31692 /* Allowing Thumb division instructions for ARMv7 in autodetection
31693 rely on this break so that duplicate extensions (extensions
31694 with the same name as a previous extension in the list) are not
31695 considered for command-line parsing. */
31699 if (opt
->name
== NULL
)
31701 /* Did we fail to find an extension because it wasn't specified in
31702 alphabetical order, or because it does not exist? */
31704 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31705 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31708 if (opt
->name
== NULL
)
31709 as_bad (_("unknown architectural extension `%s'"), str
);
31711 as_bad (_("architectural extensions must be specified in "
31712 "alphabetical order"));
31718 /* We should skip the extension we've just matched the next time
31730 arm_parse_fp16_opt (const char *str
)
31732 if (strcasecmp (str
, "ieee") == 0)
31733 fp16_format
= ARM_FP16_FORMAT_IEEE
;
31734 else if (strcasecmp (str
, "alternative") == 0)
31735 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
31738 as_bad (_("unrecognised float16 format \"%s\""), str
);
31746 arm_parse_cpu (const char *str
)
31748 const struct arm_cpu_option_table
*opt
;
31749 const char *ext
= strchr (str
, '+');
31755 len
= strlen (str
);
31759 as_bad (_("missing cpu name `%s'"), str
);
31763 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
31764 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31766 mcpu_cpu_opt
= &opt
->value
;
31767 if (mcpu_ext_opt
== NULL
)
31768 mcpu_ext_opt
= XNEW (arm_feature_set
);
31769 *mcpu_ext_opt
= opt
->ext
;
31770 mcpu_fpu_opt
= &opt
->default_fpu
;
31771 if (opt
->canonical_name
)
31773 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31774 strcpy (selected_cpu_name
, opt
->canonical_name
);
31780 if (len
>= sizeof selected_cpu_name
)
31781 len
= (sizeof selected_cpu_name
) - 1;
31783 for (i
= 0; i
< len
; i
++)
31784 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31785 selected_cpu_name
[i
] = 0;
31789 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31794 as_bad (_("unknown cpu `%s'"), str
);
31799 arm_parse_arch (const char *str
)
31801 const struct arm_arch_option_table
*opt
;
31802 const char *ext
= strchr (str
, '+');
31808 len
= strlen (str
);
31812 as_bad (_("missing architecture name `%s'"), str
);
31816 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31817 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31819 march_cpu_opt
= &opt
->value
;
31820 if (march_ext_opt
== NULL
)
31821 march_ext_opt
= XNEW (arm_feature_set
);
31822 *march_ext_opt
= arm_arch_none
;
31823 march_fpu_opt
= &opt
->default_fpu
;
31824 selected_ctx_ext_table
= opt
->ext_table
;
31825 strcpy (selected_cpu_name
, opt
->name
);
31828 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31834 as_bad (_("unknown architecture `%s'\n"), str
);
31839 arm_parse_fpu (const char * str
)
31841 const struct arm_option_fpu_value_table
* opt
;
31843 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31844 if (streq (opt
->name
, str
))
31846 mfpu_opt
= &opt
->value
;
31850 as_bad (_("unknown floating point format `%s'\n"), str
);
31855 arm_parse_float_abi (const char * str
)
31857 const struct arm_option_value_table
* opt
;
31859 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31860 if (streq (opt
->name
, str
))
31862 mfloat_abi_opt
= opt
->value
;
31866 as_bad (_("unknown floating point abi `%s'\n"), str
);
31872 arm_parse_eabi (const char * str
)
31874 const struct arm_option_value_table
*opt
;
31876 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31877 if (streq (opt
->name
, str
))
31879 meabi_flags
= opt
->value
;
31882 as_bad (_("unknown EABI `%s'\n"), str
);
31888 arm_parse_it_mode (const char * str
)
31890 bfd_boolean ret
= TRUE
;
31892 if (streq ("arm", str
))
31893 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31894 else if (streq ("thumb", str
))
31895 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31896 else if (streq ("always", str
))
31897 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31898 else if (streq ("never", str
))
31899 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31902 as_bad (_("unknown implicit IT mode `%s', should be "\
31903 "arm, thumb, always, or never."), str
);
31911 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31913 codecomposer_syntax
= TRUE
;
31914 arm_comment_chars
[0] = ';';
31915 arm_line_separator_chars
[0] = 0;
31919 struct arm_long_option_table arm_long_opts
[] =
31921 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31922 arm_parse_cpu
, NULL
},
31923 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31924 arm_parse_arch
, NULL
},
31925 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31926 arm_parse_fpu
, NULL
},
31927 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31928 arm_parse_float_abi
, NULL
},
31930 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31931 arm_parse_eabi
, NULL
},
31933 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31934 arm_parse_it_mode
, NULL
},
31935 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31936 arm_ccs_mode
, NULL
},
31938 N_("[ieee|alternative]\n\
31939 set the encoding for half precision floating point "
31940 "numbers to IEEE\n\
31941 or Arm alternative format."),
31942 arm_parse_fp16_opt
, NULL
},
31943 {NULL
, NULL
, 0, NULL
}
31947 md_parse_option (int c
, const char * arg
)
31949 struct arm_option_table
*opt
;
31950 const struct arm_legacy_option_table
*fopt
;
31951 struct arm_long_option_table
*lopt
;
31957 target_big_endian
= 1;
31963 target_big_endian
= 0;
31967 case OPTION_FIX_V4BX
:
31975 #endif /* OBJ_ELF */
31978 /* Listing option. Just ignore these, we don't support additional
31983 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31985 if (c
== opt
->option
[0]
31986 && ((arg
== NULL
&& opt
->option
[1] == 0)
31987 || streq (arg
, opt
->option
+ 1)))
31989 /* If the option is deprecated, tell the user. */
31990 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31991 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31992 arg
? arg
: "", _(opt
->deprecated
));
31994 if (opt
->var
!= NULL
)
31995 *opt
->var
= opt
->value
;
32001 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
32003 if (c
== fopt
->option
[0]
32004 && ((arg
== NULL
&& fopt
->option
[1] == 0)
32005 || streq (arg
, fopt
->option
+ 1)))
32007 /* If the option is deprecated, tell the user. */
32008 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
32009 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32010 arg
? arg
: "", _(fopt
->deprecated
));
32012 if (fopt
->var
!= NULL
)
32013 *fopt
->var
= &fopt
->value
;
32019 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32021 /* These options are expected to have an argument. */
32022 if (c
== lopt
->option
[0]
32024 && strncmp (arg
, lopt
->option
+ 1,
32025 strlen (lopt
->option
+ 1)) == 0)
32027 /* If the option is deprecated, tell the user. */
32028 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
32029 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
32030 _(lopt
->deprecated
));
32032 /* Call the sup-option parser. */
32033 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
32044 md_show_usage (FILE * fp
)
32046 struct arm_option_table
*opt
;
32047 struct arm_long_option_table
*lopt
;
32049 fprintf (fp
, _(" ARM-specific assembler options:\n"));
32051 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32052 if (opt
->help
!= NULL
)
32053 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
32055 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32056 if (lopt
->help
!= NULL
)
32057 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
32061 -EB assemble code for a big-endian cpu\n"));
32066 -EL assemble code for a little-endian cpu\n"));
32070 --fix-v4bx Allow BX in ARMv4 code\n"));
32074 --fdpic generate an FDPIC object file\n"));
32075 #endif /* OBJ_ELF */
32083 arm_feature_set flags
;
32084 } cpu_arch_ver_table
;
32086 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
32087 chronologically for architectures, with an exception for ARMv6-M and
32088 ARMv6S-M due to legacy reasons. No new architecture should have a
32089 special case. This allows for build attribute selection results to be
32090 stable when new architectures are added. */
32091 static const cpu_arch_ver_table cpu_arch_ver
[] =
32093 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
32094 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
32095 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
32096 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
32097 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
32098 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
32099 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
32100 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
32101 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
32102 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
32103 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
32104 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
32105 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
32106 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
32107 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
32108 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
32109 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
32110 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
32111 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
32112 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
32113 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
32114 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
32115 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
32116 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
32118 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
32119 always selected build attributes to match those of ARMv6-M
32120 (resp. ARMv6S-M). However, due to these architectures being a strict
32121 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
32122 would be selected when fully respecting chronology of architectures.
32123 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
32124 move them before ARMv7 architectures. */
32125 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
32126 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
32128 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
32129 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
32130 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
32131 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
32132 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
32133 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
32134 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
32135 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
32136 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
32137 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
32138 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
32139 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
32140 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
32141 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
32142 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
32143 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
32144 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_6A
},
32145 {-1, ARM_ARCH_NONE
}
32148 /* Set an attribute if it has not already been set by the user. */
32151 aeabi_set_attribute_int (int tag
, int value
)
32154 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32155 || !attributes_set_explicitly
[tag
])
32156 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
32160 aeabi_set_attribute_string (int tag
, const char *value
)
32163 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32164 || !attributes_set_explicitly
[tag
])
32165 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
32168 /* Return whether features in the *NEEDED feature set are available via
32169 extensions for the architecture whose feature set is *ARCH_FSET. */
32172 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
32173 const arm_feature_set
*needed
)
32175 int i
, nb_allowed_archs
;
32176 arm_feature_set ext_fset
;
32177 const struct arm_option_extension_value_table
*opt
;
32179 ext_fset
= arm_arch_none
;
32180 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32182 /* Extension does not provide any feature we need. */
32183 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
32187 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32188 for (i
= 0; i
< nb_allowed_archs
; i
++)
32191 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
32194 /* Extension is available, add it. */
32195 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
32196 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
32200 /* Can we enable all features in *needed? */
32201 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
32204 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32205 a given architecture feature set *ARCH_EXT_FSET including extension feature
32206 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
32207 - if true, check for an exact match of the architecture modulo extensions;
32208 - otherwise, select build attribute value of the first superset
32209 architecture released so that results remains stable when new architectures
32211 For -march/-mcpu=all the build attribute value of the most featureful
32212 architecture is returned. Tag_CPU_arch_profile result is returned in
32216 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
32217 const arm_feature_set
*ext_fset
,
32218 char *profile
, int exact_match
)
32220 arm_feature_set arch_fset
;
32221 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
32223 /* Select most featureful architecture with all its extensions if building
32224 for -march=all as the feature sets used to set build attributes. */
32225 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
32227 /* Force revisiting of decision for each new architecture. */
32228 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32230 return TAG_CPU_ARCH_V8
;
32233 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
32235 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
32237 arm_feature_set known_arch_fset
;
32239 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
32242 /* Base architecture match user-specified architecture and
32243 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
32244 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
32249 /* Base architecture match user-specified architecture only
32250 (eg. ARMv6-M in the same case as above). Record it in case we
32251 find a match with above condition. */
32252 else if (p_ver_ret
== NULL
32253 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
32259 /* Architecture has all features wanted. */
32260 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
32262 arm_feature_set added_fset
;
32264 /* Compute features added by this architecture over the one
32265 recorded in p_ver_ret. */
32266 if (p_ver_ret
!= NULL
)
32267 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
32269 /* First architecture that match incl. with extensions, or the
32270 only difference in features over the recorded match is
32271 features that were optional and are now mandatory. */
32272 if (p_ver_ret
== NULL
32273 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
32279 else if (p_ver_ret
== NULL
)
32281 arm_feature_set needed_ext_fset
;
32283 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
32285 /* Architecture has all features needed when using some
32286 extensions. Record it and continue searching in case there
32287 exist an architecture providing all needed features without
32288 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
32290 if (have_ext_for_needed_feat_p (&known_arch_fset
,
32297 if (p_ver_ret
== NULL
)
32301 /* Tag_CPU_arch_profile. */
32302 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
32303 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
32304 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
32305 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
32307 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
32309 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
32313 return p_ver_ret
->val
;
32316 /* Set the public EABI object attributes. */
32319 aeabi_set_public_attributes (void)
32321 char profile
= '\0';
32324 int fp16_optional
= 0;
32325 int skip_exact_match
= 0;
32326 arm_feature_set flags
, flags_arch
, flags_ext
;
32328 /* Autodetection mode, choose the architecture based the instructions
32330 if (no_cpu_selected ())
32332 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
32334 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
32335 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
32337 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
32338 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
32340 /* Code run during relaxation relies on selected_cpu being set. */
32341 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32342 flags_ext
= arm_arch_none
;
32343 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
32344 selected_ext
= flags_ext
;
32345 selected_cpu
= flags
;
32347 /* Otherwise, choose the architecture based on the capabilities of the
32351 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
32352 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
32353 flags_ext
= selected_ext
;
32354 flags
= selected_cpu
;
32356 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
32358 /* Allow the user to override the reported architecture. */
32359 if (!ARM_FEATURE_ZERO (selected_object_arch
))
32361 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
32362 flags_ext
= arm_arch_none
;
32365 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
32367 /* When this function is run again after relaxation has happened there is no
32368 way to determine whether an architecture or CPU was specified by the user:
32369 - selected_cpu is set above for relaxation to work;
32370 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32371 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32372 Therefore, if not in -march=all case we first try an exact match and fall
32373 back to autodetection. */
32374 if (!skip_exact_match
)
32375 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
32377 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
32379 as_bad (_("no architecture contains all the instructions used\n"));
32381 /* Tag_CPU_name. */
32382 if (selected_cpu_name
[0])
32386 q
= selected_cpu_name
;
32387 if (strncmp (q
, "armv", 4) == 0)
32392 for (i
= 0; q
[i
]; i
++)
32393 q
[i
] = TOUPPER (q
[i
]);
32395 aeabi_set_attribute_string (Tag_CPU_name
, q
);
32398 /* Tag_CPU_arch. */
32399 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
32401 /* Tag_CPU_arch_profile. */
32402 if (profile
!= '\0')
32403 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
32405 /* Tag_DSP_extension. */
32406 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
32407 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
32409 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32410 /* Tag_ARM_ISA_use. */
32411 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
32412 || ARM_FEATURE_ZERO (flags_arch
))
32413 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
32415 /* Tag_THUMB_ISA_use. */
32416 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
32417 || ARM_FEATURE_ZERO (flags_arch
))
32421 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32422 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
32424 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
32428 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
32431 /* Tag_VFP_arch. */
32432 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
32433 aeabi_set_attribute_int (Tag_VFP_arch
,
32434 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32436 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
32437 aeabi_set_attribute_int (Tag_VFP_arch
,
32438 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32440 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
32443 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
32445 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
32447 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
32450 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
32451 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
32452 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
32453 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
32454 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
32456 /* Tag_ABI_HardFP_use. */
32457 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
32458 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
32459 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
32461 /* Tag_WMMX_arch. */
32462 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
32463 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
32464 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
32465 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
32467 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
32468 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
32469 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
32470 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
32471 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
32472 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
32474 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
32476 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
32480 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
32485 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
32486 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
32487 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
32488 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
32490 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
32491 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
32492 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
32496 We set Tag_DIV_use to two when integer divide instructions have been used
32497 in ARM state, or when Thumb integer divide instructions have been used,
32498 but we have no architecture profile set, nor have we any ARM instructions.
32500 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
32501 by the base architecture.
32503 For new architectures we will have to check these tests. */
32504 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32505 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32506 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
32507 aeabi_set_attribute_int (Tag_DIV_use
, 0);
32508 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
32509 || (profile
== '\0'
32510 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
32511 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
32512 aeabi_set_attribute_int (Tag_DIV_use
, 2);
32514 /* Tag_MP_extension_use. */
32515 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
32516 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
32518 /* Tag Virtualization_use. */
32519 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
32521 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
32524 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
32526 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
32527 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
32530 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
32531 finished and free extension feature bits which will not be used anymore. */
32534 arm_md_post_relax (void)
32536 aeabi_set_public_attributes ();
32537 XDELETE (mcpu_ext_opt
);
32538 mcpu_ext_opt
= NULL
;
32539 XDELETE (march_ext_opt
);
32540 march_ext_opt
= NULL
;
32543 /* Add the default contents for the .ARM.attributes section. */
32548 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
32551 aeabi_set_public_attributes ();
32553 #endif /* OBJ_ELF */
32555 /* Parse a .cpu directive. */
32558 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
32560 const struct arm_cpu_option_table
*opt
;
32564 name
= input_line_pointer
;
32565 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32566 input_line_pointer
++;
32567 saved_char
= *input_line_pointer
;
32568 *input_line_pointer
= 0;
32570 /* Skip the first "all" entry. */
32571 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
32572 if (streq (opt
->name
, name
))
32574 selected_arch
= opt
->value
;
32575 selected_ext
= opt
->ext
;
32576 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32577 if (opt
->canonical_name
)
32578 strcpy (selected_cpu_name
, opt
->canonical_name
);
32582 for (i
= 0; opt
->name
[i
]; i
++)
32583 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32585 selected_cpu_name
[i
] = 0;
32587 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32589 *input_line_pointer
= saved_char
;
32590 demand_empty_rest_of_line ();
32593 as_bad (_("unknown cpu `%s'"), name
);
32594 *input_line_pointer
= saved_char
;
32595 ignore_rest_of_line ();
32598 /* Parse a .arch directive. */
32601 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
32603 const struct arm_arch_option_table
*opt
;
32607 name
= input_line_pointer
;
32608 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32609 input_line_pointer
++;
32610 saved_char
= *input_line_pointer
;
32611 *input_line_pointer
= 0;
32613 /* Skip the first "all" entry. */
32614 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32615 if (streq (opt
->name
, name
))
32617 selected_arch
= opt
->value
;
32618 selected_ext
= arm_arch_none
;
32619 selected_cpu
= selected_arch
;
32620 strcpy (selected_cpu_name
, opt
->name
);
32621 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32622 *input_line_pointer
= saved_char
;
32623 demand_empty_rest_of_line ();
32627 as_bad (_("unknown architecture `%s'\n"), name
);
32628 *input_line_pointer
= saved_char
;
32629 ignore_rest_of_line ();
32632 /* Parse a .object_arch directive. */
32635 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
32637 const struct arm_arch_option_table
*opt
;
32641 name
= input_line_pointer
;
32642 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32643 input_line_pointer
++;
32644 saved_char
= *input_line_pointer
;
32645 *input_line_pointer
= 0;
32647 /* Skip the first "all" entry. */
32648 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32649 if (streq (opt
->name
, name
))
32651 selected_object_arch
= opt
->value
;
32652 *input_line_pointer
= saved_char
;
32653 demand_empty_rest_of_line ();
32657 as_bad (_("unknown architecture `%s'\n"), name
);
32658 *input_line_pointer
= saved_char
;
32659 ignore_rest_of_line ();
32662 /* Parse a .arch_extension directive. */
32665 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
32667 const struct arm_option_extension_value_table
*opt
;
32670 int adding_value
= 1;
32672 name
= input_line_pointer
;
32673 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32674 input_line_pointer
++;
32675 saved_char
= *input_line_pointer
;
32676 *input_line_pointer
= 0;
32678 if (strlen (name
) >= 2
32679 && strncmp (name
, "no", 2) == 0)
32685 /* Check the context specific extension table */
32686 if (selected_ctx_ext_table
)
32688 const struct arm_ext_table
* ext_opt
;
32689 for (ext_opt
= selected_ctx_ext_table
; ext_opt
->name
!= NULL
; ext_opt
++)
32691 if (streq (ext_opt
->name
, name
))
32695 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
32696 /* TODO: Option not supported. When we remove the
32697 legacy table this case should error out. */
32699 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32703 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, ext_opt
->clear
);
32705 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32706 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32707 *input_line_pointer
= saved_char
;
32708 demand_empty_rest_of_line ();
32714 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32715 if (streq (opt
->name
, name
))
32717 int i
, nb_allowed_archs
=
32718 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
32719 for (i
= 0; i
< nb_allowed_archs
; i
++)
32722 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
32724 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
32728 if (i
== nb_allowed_archs
)
32730 as_bad (_("architectural extension `%s' is not allowed for the "
32731 "current base architecture"), name
);
32736 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32739 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
32741 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32742 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32743 *input_line_pointer
= saved_char
;
32744 demand_empty_rest_of_line ();
32745 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32746 on this return so that duplicate extensions (extensions with the
32747 same name as a previous extension in the list) are not considered
32748 for command-line parsing. */
32752 if (opt
->name
== NULL
)
32753 as_bad (_("unknown architecture extension `%s'\n"), name
);
32755 *input_line_pointer
= saved_char
;
32756 ignore_rest_of_line ();
32759 /* Parse a .fpu directive. */
32762 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
32764 const struct arm_option_fpu_value_table
*opt
;
32768 name
= input_line_pointer
;
32769 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32770 input_line_pointer
++;
32771 saved_char
= *input_line_pointer
;
32772 *input_line_pointer
= 0;
32774 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32775 if (streq (opt
->name
, name
))
32777 selected_fpu
= opt
->value
;
32778 #ifndef CPU_DEFAULT
32779 if (no_cpu_selected ())
32780 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
32783 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32784 *input_line_pointer
= saved_char
;
32785 demand_empty_rest_of_line ();
32789 as_bad (_("unknown floating point format `%s'\n"), name
);
32790 *input_line_pointer
= saved_char
;
32791 ignore_rest_of_line ();
32794 /* Copy symbol information. */
32797 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
32799 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
32803 /* Given a symbolic attribute NAME, return the proper integer value.
32804 Returns -1 if the attribute is not known. */
32807 arm_convert_symbolic_attribute (const char *name
)
32809 static const struct
32814 attribute_table
[] =
32816 /* When you modify this table you should
32817 also modify the list in doc/c-arm.texi. */
32818 #define T(tag) {#tag, tag}
32819 T (Tag_CPU_raw_name
),
32822 T (Tag_CPU_arch_profile
),
32823 T (Tag_ARM_ISA_use
),
32824 T (Tag_THUMB_ISA_use
),
32828 T (Tag_Advanced_SIMD_arch
),
32829 T (Tag_PCS_config
),
32830 T (Tag_ABI_PCS_R9_use
),
32831 T (Tag_ABI_PCS_RW_data
),
32832 T (Tag_ABI_PCS_RO_data
),
32833 T (Tag_ABI_PCS_GOT_use
),
32834 T (Tag_ABI_PCS_wchar_t
),
32835 T (Tag_ABI_FP_rounding
),
32836 T (Tag_ABI_FP_denormal
),
32837 T (Tag_ABI_FP_exceptions
),
32838 T (Tag_ABI_FP_user_exceptions
),
32839 T (Tag_ABI_FP_number_model
),
32840 T (Tag_ABI_align_needed
),
32841 T (Tag_ABI_align8_needed
),
32842 T (Tag_ABI_align_preserved
),
32843 T (Tag_ABI_align8_preserved
),
32844 T (Tag_ABI_enum_size
),
32845 T (Tag_ABI_HardFP_use
),
32846 T (Tag_ABI_VFP_args
),
32847 T (Tag_ABI_WMMX_args
),
32848 T (Tag_ABI_optimization_goals
),
32849 T (Tag_ABI_FP_optimization_goals
),
32850 T (Tag_compatibility
),
32851 T (Tag_CPU_unaligned_access
),
32852 T (Tag_FP_HP_extension
),
32853 T (Tag_VFP_HP_extension
),
32854 T (Tag_ABI_FP_16bit_format
),
32855 T (Tag_MPextension_use
),
32857 T (Tag_nodefaults
),
32858 T (Tag_also_compatible_with
),
32859 T (Tag_conformance
),
32861 T (Tag_Virtualization_use
),
32862 T (Tag_DSP_extension
),
32864 /* We deliberately do not include Tag_MPextension_use_legacy. */
32872 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32873 if (streq (name
, attribute_table
[i
].name
))
32874 return attribute_table
[i
].tag
;
32879 /* Apply sym value for relocations only in the case that they are for
32880 local symbols in the same segment as the fixup and you have the
32881 respective architectural feature for blx and simple switches. */
32884 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32887 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32888 /* PR 17444: If the local symbol is in a different section then a reloc
32889 will always be generated for it, so applying the symbol value now
32890 will result in a double offset being stored in the relocation. */
32891 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32892 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32894 switch (fixP
->fx_r_type
)
32896 case BFD_RELOC_ARM_PCREL_BLX
:
32897 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32898 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32902 case BFD_RELOC_ARM_PCREL_CALL
:
32903 case BFD_RELOC_THUMB_PCREL_BLX
:
32904 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32915 #endif /* OBJ_ELF */