1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 /* Types of processor to assemble for. */
40 #define ARM_1 0x00000001
41 #define ARM_2 0x00000002
42 #define ARM_3 0x00000004
44 #define ARM_6 0x00000008
45 #define ARM_7 ARM_6 /* same core instruction set */
46 #define ARM_8 ARM_6 /* same core instruction set */
47 #define ARM_9 ARM_6 /* same core instruction set */
48 #define ARM_CPU_MASK 0x0000000f
50 /* The following bitmasks control CPU extensions (ARM7 onwards): */
51 #define ARM_LONGMUL 0x00000010 /* allow long multiplies */
52 #define ARM_HALFWORD 0x00000020 /* allow half word loads */
53 #define ARM_THUMB 0x00000040 /* allow BX instruction */
54 #define ARM_EXT_V5 0x00000080 /* allow CLZ etc */
55 #define ARM_EXT_V5E 0x00000200 /* "El Segundo" */
57 /* Architectures are the sum of the base and extensions. */
58 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
59 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
60 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
61 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
63 /* Some useful combinations: */
64 #define ARM_ANY 0x00ffffff
65 #define ARM_2UP (ARM_ANY - ARM_1)
66 #define ARM_ALL ARM_2UP /* Not arm1 only */
67 #define ARM_3UP 0x00fffffc
68 #define ARM_6UP 0x00fffff8 /* Includes ARM7 */
70 #define FPU_CORE 0x80000000
71 #define FPU_FPA10 0x40000000
72 #define FPU_FPA11 0x40000000
75 /* Some useful combinations */
76 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY */
77 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core */
82 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
84 #define CPU_DEFAULT ARM_ALL
89 #define FPU_DEFAULT FPU_ALL
92 #define streq(a, b) (strcmp (a, b) == 0)
93 #define skip_whitespace(str) while (* (str) == ' ') ++ (str)
95 static unsigned long cpu_variant
= CPU_DEFAULT
| FPU_DEFAULT
;
96 static int target_oabi
= 0;
98 #if defined OBJ_COFF || defined OBJ_ELF
99 /* Flags stored in private area of BFD structure */
100 static boolean uses_apcs_26
= false;
101 static boolean support_interwork
= false;
102 static boolean uses_apcs_float
= false;
103 static boolean pic_code
= false;
106 /* This array holds the chars that always start a comment. If the
107 pre-processor is disabled, these aren't very useful */
108 CONST
char comment_chars
[] = "@";
110 /* This array holds the chars that only start a comment at the beginning of
111 a line. If the line seems to have the form '# 123 filename'
112 .line and .file directives will appear in the pre-processed output */
113 /* Note that input_file.c hand checks for '#' at the beginning of the
114 first line of the input file. This is because the compiler outputs
115 #NO_APP at the beginning of its output. */
116 /* Also note that comments like this one will always work. */
117 CONST
char line_comment_chars
[] = "#";
120 CONST
char line_separator_chars
[] = ";";
122 CONST
char line_separator_chars
[] = "";
125 /* Chars that can be used to separate mant from exp in floating point nums */
126 CONST
char EXP_CHARS
[] = "eE";
128 /* Chars that mean this number is a floating point constant */
132 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
134 /* Prefix characters that indicate the start of an immediate
136 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
139 symbolS
* GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
142 CONST
int md_reloc_size
= 8; /* Size of relocation record */
144 static int thumb_mode
= 0; /* 0: assemble for ARM, 1: assemble for Thumb,
145 2: assemble for Thumb even though target cpu
146 does not support thumb instructions */
147 typedef struct arm_fix
155 unsigned long instruction
;
160 bfd_reloc_code_real_type type
;
170 CONST
char * template;
174 static CONST
struct asm_shift shift
[] =
190 #define NO_SHIFT_RESTRICT 1
191 #define SHIFT_RESTRICT 0
193 #define NUM_FLOAT_VALS 8
195 CONST
char * fp_const
[] =
197 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
200 /* Number of littlenums required to hold an extended precision number */
201 #define MAX_LITTLENUMS 6
203 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
213 #define CP_T_X 0x00008000
214 #define CP_T_Y 0x00400000
215 #define CP_T_Pre 0x01000000
216 #define CP_T_UD 0x00800000
217 #define CP_T_WB 0x00200000
219 #define CONDS_BIT (0x00100000)
220 #define LOAD_BIT (0x00100000)
221 #define TRANS_BIT (0x00200000)
225 CONST
char * template;
229 /* This is to save a hash look-up in the common case */
230 #define COND_ALWAYS 0xe0000000
232 static CONST
struct asm_cond conds
[] =
236 {"cs", 0x20000000}, {"hs", 0x20000000},
237 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
252 /* Warning: If the top bit of the set_bits is set, then the standard
253 instruction bitmask is ignored, and the new bitmask is taken from
257 CONST
char * template; /* Basic flag string */
258 unsigned long set_bits
; /* Bits to set */
261 static CONST
struct asm_flg s_flag
[] =
267 static CONST
struct asm_flg ldr_flags
[] =
271 {"bt", 0x00400000 | TRANS_BIT
},
278 static CONST
struct asm_flg str_flags
[] =
282 {"bt", 0x00400000 | TRANS_BIT
},
287 static CONST
struct asm_flg byte_flag
[] =
293 static CONST
struct asm_flg cmp_flags
[] =
300 static CONST
struct asm_flg ldm_flags
[] =
313 static CONST
struct asm_flg stm_flags
[] =
326 static CONST
struct asm_flg lfm_flags
[] =
333 static CONST
struct asm_flg sfm_flags
[] =
340 static CONST
struct asm_flg round_flags
[] =
348 /* The implementation of the FIX instruction is broken on some assemblers,
349 in that it accepts a precision specifier as well as a rounding specifier,
350 despite the fact that this is meaningless. To be more compatible, we
351 accept it as well, though of course it does not set any bits. */
352 static CONST
struct asm_flg fix_flags
[] =
369 static CONST
struct asm_flg except_flag
[] =
375 static CONST
struct asm_flg cplong_flag
[] =
383 CONST
char * template;
384 unsigned long number
;
387 #define PSR_FIELD_MASK 0x000f0000
389 #define PSR_FLAGS 0x00080000
390 #define PSR_CONTROL 0x00010000 /* Undocumented instruction, its use is discouraged by ARM */
391 #define PSR_ALL 0x00090000
400 static CONST
struct asm_psr psrs
[] =
404 {"cpsr_all", CPSR_ALL
},
406 {"spsr_all", SPSR_ALL
},
409 {"cpsr_flg", CPSR_FLG
},
410 {"spsr_flg", SPSR_FLG
},
413 {"cpsr_c", CPSR_CTL
},
414 {"cpsr_ctl", CPSR_CTL
},
415 {"spsr_c", SPSR_CTL
},
416 {"spsr_ctl", SPSR_CTL
}
419 /* Functions called by parser */
420 /* ARM instructions */
421 static void do_arit
PARAMS ((char *, unsigned long));
422 static void do_cmp
PARAMS ((char *, unsigned long));
423 static void do_mov
PARAMS ((char *, unsigned long));
424 static void do_ldst
PARAMS ((char *, unsigned long));
425 static void do_ldmstm
PARAMS ((char *, unsigned long));
426 static void do_branch
PARAMS ((char *, unsigned long));
427 static void do_swi
PARAMS ((char *, unsigned long));
428 /* Pseudo Op codes */
429 static void do_adr
PARAMS ((char *, unsigned long));
430 static void do_adrl
PARAMS ((char *, unsigned long));
431 static void do_nop
PARAMS ((char *, unsigned long));
433 static void do_mul
PARAMS ((char *, unsigned long));
434 static void do_mla
PARAMS ((char *, unsigned long));
436 static void do_swap
PARAMS ((char *, unsigned long));
438 static void do_msr
PARAMS ((char *, unsigned long));
439 static void do_mrs
PARAMS ((char *, unsigned long));
441 static void do_mull
PARAMS ((char *, unsigned long));
443 static void do_bx
PARAMS ((char *, unsigned long));
446 /* Coprocessor Instructions */
447 static void do_cdp
PARAMS ((char *, unsigned long));
448 static void do_lstc
PARAMS ((char *, unsigned long));
449 static void do_co_reg
PARAMS ((char *, unsigned long));
450 static void do_fp_ctrl
PARAMS ((char *, unsigned long));
451 static void do_fp_ldst
PARAMS ((char *, unsigned long));
452 static void do_fp_ldmstm
PARAMS ((char *, unsigned long));
453 static void do_fp_dyadic
PARAMS ((char *, unsigned long));
454 static void do_fp_monadic
PARAMS ((char *, unsigned long));
455 static void do_fp_cmp
PARAMS ((char *, unsigned long));
456 static void do_fp_from_reg
PARAMS ((char *, unsigned long));
457 static void do_fp_to_reg
PARAMS ((char *, unsigned long));
459 static void fix_new_arm
PARAMS ((fragS
*, int, short, expressionS
*, int, int));
460 static int arm_reg_parse
PARAMS ((char **));
461 static int arm_psr_parse
PARAMS ((char **));
462 static void symbol_locate
PARAMS ((symbolS
*, CONST
char *, segT
, valueT
, fragS
*));
463 static int add_to_lit_pool
PARAMS ((void));
464 static unsigned validate_immediate
PARAMS ((unsigned));
465 static unsigned validate_immediate_twopart
PARAMS ((unsigned int, unsigned int *));
466 static int validate_offset_imm
PARAMS ((unsigned int, int));
467 static void opcode_select
PARAMS ((int));
468 static void end_of_line
PARAMS ((char *));
469 static int reg_required_here
PARAMS ((char **, int));
470 static int psr_required_here
PARAMS ((char **, int, int));
471 static int co_proc_number
PARAMS ((char **));
472 static int cp_opc_expr
PARAMS ((char **, int, int));
473 static int cp_reg_required_here
PARAMS ((char **, int));
474 static int fp_reg_required_here
PARAMS ((char **, int));
475 static int cp_address_offset
PARAMS ((char **));
476 static int cp_address_required_here
PARAMS ((char **));
477 static int my_get_float_expression
PARAMS ((char **));
478 static int skip_past_comma
PARAMS ((char **));
479 static int walk_no_bignums
PARAMS ((symbolS
*));
480 static int negate_data_op
PARAMS ((unsigned long *, unsigned long));
481 static int data_op2
PARAMS ((char **));
482 static int fp_op2
PARAMS ((char **));
483 static long reg_list
PARAMS ((char **));
484 static void thumb_load_store
PARAMS ((char *, int, int));
485 static int decode_shift
PARAMS ((char **, int));
486 static int ldst_extend
PARAMS ((char **, int));
487 static void thumb_add_sub
PARAMS ((char *, int));
488 static void insert_reg
PARAMS ((int));
489 static void thumb_shift
PARAMS ((char *, int));
490 static void thumb_mov_compare
PARAMS ((char *, int));
491 static void set_constant_flonums
PARAMS ((void));
492 static valueT md_chars_to_number
PARAMS ((char *, int));
493 static void insert_reg_alias
PARAMS ((char *, int));
494 static void output_inst
PARAMS ((void));
496 static bfd_reloc_code_real_type arm_parse_reloc
PARAMS ((void));
499 /* ARM instructions take 4bytes in the object file, Thumb instructions
503 /* LONGEST_INST is the longest basic instruction name without conditions or
505 * ARM7M has 4 of length 5
508 #define LONGEST_INST 5
513 CONST
char * template; /* Basic string to match */
514 unsigned long value
; /* Basic instruction code */
516 /* Compulsory suffix that must follow conds. If "", then the
517 instruction is not conditional and must have no suffix. */
518 CONST
char * comp_suffix
;
520 CONST
struct asm_flg
* flags
; /* Bits to toggle if flag 'n' set */
521 unsigned long variants
; /* Which CPU variants this exists for */
522 /* Function to call to parse args */
523 void (* parms
) PARAMS ((char *, unsigned long));
526 static CONST
struct asm_opcode insns
[] =
528 /* ARM Instructions */
529 {"and", 0x00000000, NULL
, s_flag
, ARM_ANY
, do_arit
},
530 {"eor", 0x00200000, NULL
, s_flag
, ARM_ANY
, do_arit
},
531 {"sub", 0x00400000, NULL
, s_flag
, ARM_ANY
, do_arit
},
532 {"rsb", 0x00600000, NULL
, s_flag
, ARM_ANY
, do_arit
},
533 {"add", 0x00800000, NULL
, s_flag
, ARM_ANY
, do_arit
},
534 {"adc", 0x00a00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
535 {"sbc", 0x00c00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
536 {"rsc", 0x00e00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
537 {"orr", 0x01800000, NULL
, s_flag
, ARM_ANY
, do_arit
},
538 {"bic", 0x01c00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
539 {"tst", 0x01000000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
540 {"teq", 0x01200000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
541 {"cmp", 0x01400000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
542 {"cmn", 0x01600000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
543 {"mov", 0x01a00000, NULL
, s_flag
, ARM_ANY
, do_mov
},
544 {"mvn", 0x01e00000, NULL
, s_flag
, ARM_ANY
, do_mov
},
545 {"str", 0x04000000, NULL
, str_flags
, ARM_ANY
, do_ldst
},
546 {"ldr", 0x04100000, NULL
, ldr_flags
, ARM_ANY
, do_ldst
},
547 {"stm", 0x08000000, NULL
, stm_flags
, ARM_ANY
, do_ldmstm
},
548 {"ldm", 0x08100000, NULL
, ldm_flags
, ARM_ANY
, do_ldmstm
},
549 {"swi", 0x0f000000, NULL
, NULL
, ARM_ANY
, do_swi
},
551 {"bl", 0x0b000000, NULL
, NULL
, ARM_ANY
, do_branch
},
552 {"b", 0x0a000000, NULL
, NULL
, ARM_ANY
, do_branch
},
554 {"bl", 0x0bfffffe, NULL
, NULL
, ARM_ANY
, do_branch
},
555 {"b", 0x0afffffe, NULL
, NULL
, ARM_ANY
, do_branch
},
559 {"adr", 0x028f0000, NULL
, NULL
, ARM_ANY
, do_adr
},
560 {"adrl", 0x028f0000, NULL
, NULL
, ARM_ANY
, do_adrl
},
561 {"nop", 0x01a00000, NULL
, NULL
, ARM_ANY
, do_nop
},
563 /* ARM 2 multiplies */
564 {"mul", 0x00000090, NULL
, s_flag
, ARM_2UP
, do_mul
},
565 {"mla", 0x00200090, NULL
, s_flag
, ARM_2UP
, do_mla
},
567 /* ARM 3 - swp instructions */
568 {"swp", 0x01000090, NULL
, byte_flag
, ARM_3UP
, do_swap
},
570 /* ARM 6 Coprocessor instructions */
571 {"mrs", 0x010f0000, NULL
, NULL
, ARM_6UP
, do_mrs
},
572 {"msr", 0x0120f000, NULL
, NULL
, ARM_6UP
, do_msr
},
573 /* ScottB: our code uses 0x0128f000 for msr.
574 NickC: but this is wrong because the bits 16 and 19 are handled
575 by the PSR_xxx defines above. */
577 /* ARM 7M long multiplies - need signed/unsigned flags! */
578 {"smull", 0x00c00090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
579 {"umull", 0x00800090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
580 {"smlal", 0x00e00090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
581 {"umlal", 0x00a00090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
583 /* ARM THUMB interworking */
584 {"bx", 0x012fff10, NULL
, NULL
, ARM_THUMB
, do_bx
},
586 /* Floating point instructions */
587 {"wfs", 0x0e200110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
588 {"rfs", 0x0e300110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
589 {"wfc", 0x0e400110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
590 {"rfc", 0x0e500110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
591 {"ldf", 0x0c100100, "sdep", NULL
, FPU_ALL
, do_fp_ldst
},
592 {"stf", 0x0c000100, "sdep", NULL
, FPU_ALL
, do_fp_ldst
},
593 {"lfm", 0x0c100200, NULL
, lfm_flags
, FPU_MEMMULTI
, do_fp_ldmstm
},
594 {"sfm", 0x0c000200, NULL
, sfm_flags
, FPU_MEMMULTI
, do_fp_ldmstm
},
595 {"mvf", 0x0e008100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
596 {"mnf", 0x0e108100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
597 {"abs", 0x0e208100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
598 {"rnd", 0x0e308100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
599 {"sqt", 0x0e408100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
600 {"log", 0x0e508100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
601 {"lgn", 0x0e608100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
602 {"exp", 0x0e708100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
603 {"sin", 0x0e808100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
604 {"cos", 0x0e908100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
605 {"tan", 0x0ea08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
606 {"asn", 0x0eb08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
607 {"acs", 0x0ec08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
608 {"atn", 0x0ed08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
609 {"urd", 0x0ee08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
610 {"nrm", 0x0ef08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
611 {"adf", 0x0e000100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
612 {"suf", 0x0e200100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
613 {"rsf", 0x0e300100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
614 {"muf", 0x0e100100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
615 {"dvf", 0x0e400100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
616 {"rdf", 0x0e500100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
617 {"pow", 0x0e600100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
618 {"rpw", 0x0e700100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
619 {"rmf", 0x0e800100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
620 {"fml", 0x0e900100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
621 {"fdv", 0x0ea00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
622 {"frd", 0x0eb00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
623 {"pol", 0x0ec00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
624 {"cmf", 0x0e90f110, NULL
, except_flag
, FPU_ALL
, do_fp_cmp
},
625 {"cnf", 0x0eb0f110, NULL
, except_flag
, FPU_ALL
, do_fp_cmp
},
626 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
627 be an optional suffix, but part of the instruction. To be compatible,
629 {"cmfe", 0x0ed0f110, NULL
, NULL
, FPU_ALL
, do_fp_cmp
},
630 {"cnfe", 0x0ef0f110, NULL
, NULL
, FPU_ALL
, do_fp_cmp
},
631 {"flt", 0x0e000110, "sde", round_flags
, FPU_ALL
, do_fp_from_reg
},
632 {"fix", 0x0e100110, NULL
, fix_flags
, FPU_ALL
, do_fp_to_reg
},
634 /* Generic copressor instructions */
635 {"cdp", 0x0e000000, NULL
, NULL
, ARM_2UP
, do_cdp
},
636 {"ldc", 0x0c100000, NULL
, cplong_flag
, ARM_2UP
, do_lstc
},
637 {"stc", 0x0c000000, NULL
, cplong_flag
, ARM_2UP
, do_lstc
},
638 {"mcr", 0x0e000010, NULL
, NULL
, ARM_2UP
, do_co_reg
},
639 {"mrc", 0x0e100010, NULL
, NULL
, ARM_2UP
, do_co_reg
},
642 /* defines for various bits that we will want to toggle */
644 #define INST_IMMEDIATE 0x02000000
645 #define OFFSET_REG 0x02000000
646 #define HWOFFSET_IMM 0x00400000
647 #define SHIFT_BY_REG 0x00000010
648 #define PRE_INDEX 0x01000000
649 #define INDEX_UP 0x00800000
650 #define WRITE_BACK 0x00200000
651 #define LDM_TYPE_2_OR_3 0x00400000
653 #define LITERAL_MASK 0xf000f000
654 #define COND_MASK 0xf0000000
655 #define OPCODE_MASK 0xfe1fffff
656 #define DATA_OP_SHIFT 21
658 /* Codes to distinguish the arithmetic instructions */
670 #define OPCODE_CMP 10
671 #define OPCODE_CMN 11
672 #define OPCODE_ORR 12
673 #define OPCODE_MOV 13
674 #define OPCODE_BIC 14
675 #define OPCODE_MVN 15
677 static void do_t_nop
PARAMS ((char *));
678 static void do_t_arit
PARAMS ((char *));
679 static void do_t_add
PARAMS ((char *));
680 static void do_t_asr
PARAMS ((char *));
681 static void do_t_branch9
PARAMS ((char *));
682 static void do_t_branch12
PARAMS ((char *));
683 static void do_t_branch23
PARAMS ((char *));
684 static void do_t_bx
PARAMS ((char *));
685 static void do_t_compare
PARAMS ((char *));
686 static void do_t_ldmstm
PARAMS ((char *));
687 static void do_t_ldr
PARAMS ((char *));
688 static void do_t_ldrb
PARAMS ((char *));
689 static void do_t_ldrh
PARAMS ((char *));
690 static void do_t_lds
PARAMS ((char *));
691 static void do_t_lsl
PARAMS ((char *));
692 static void do_t_lsr
PARAMS ((char *));
693 static void do_t_mov
PARAMS ((char *));
694 static void do_t_push_pop
PARAMS ((char *));
695 static void do_t_str
PARAMS ((char *));
696 static void do_t_strb
PARAMS ((char *));
697 static void do_t_strh
PARAMS ((char *));
698 static void do_t_sub
PARAMS ((char *));
699 static void do_t_swi
PARAMS ((char *));
700 static void do_t_adr
PARAMS ((char *));
702 #define T_OPCODE_MUL 0x4340
703 #define T_OPCODE_TST 0x4200
704 #define T_OPCODE_CMN 0x42c0
705 #define T_OPCODE_NEG 0x4240
706 #define T_OPCODE_MVN 0x43c0
708 #define T_OPCODE_ADD_R3 0x1800
709 #define T_OPCODE_SUB_R3 0x1a00
710 #define T_OPCODE_ADD_HI 0x4400
711 #define T_OPCODE_ADD_ST 0xb000
712 #define T_OPCODE_SUB_ST 0xb080
713 #define T_OPCODE_ADD_SP 0xa800
714 #define T_OPCODE_ADD_PC 0xa000
715 #define T_OPCODE_ADD_I8 0x3000
716 #define T_OPCODE_SUB_I8 0x3800
717 #define T_OPCODE_ADD_I3 0x1c00
718 #define T_OPCODE_SUB_I3 0x1e00
720 #define T_OPCODE_ASR_R 0x4100
721 #define T_OPCODE_LSL_R 0x4080
722 #define T_OPCODE_LSR_R 0x40c0
723 #define T_OPCODE_ASR_I 0x1000
724 #define T_OPCODE_LSL_I 0x0000
725 #define T_OPCODE_LSR_I 0x0800
727 #define T_OPCODE_MOV_I8 0x2000
728 #define T_OPCODE_CMP_I8 0x2800
729 #define T_OPCODE_CMP_LR 0x4280
730 #define T_OPCODE_MOV_HR 0x4600
731 #define T_OPCODE_CMP_HR 0x4500
733 #define T_OPCODE_LDR_PC 0x4800
734 #define T_OPCODE_LDR_SP 0x9800
735 #define T_OPCODE_STR_SP 0x9000
736 #define T_OPCODE_LDR_IW 0x6800
737 #define T_OPCODE_STR_IW 0x6000
738 #define T_OPCODE_LDR_IH 0x8800
739 #define T_OPCODE_STR_IH 0x8000
740 #define T_OPCODE_LDR_IB 0x7800
741 #define T_OPCODE_STR_IB 0x7000
742 #define T_OPCODE_LDR_RW 0x5800
743 #define T_OPCODE_STR_RW 0x5000
744 #define T_OPCODE_LDR_RH 0x5a00
745 #define T_OPCODE_STR_RH 0x5200
746 #define T_OPCODE_LDR_RB 0x5c00
747 #define T_OPCODE_STR_RB 0x5400
749 #define T_OPCODE_PUSH 0xb400
750 #define T_OPCODE_POP 0xbc00
752 #define T_OPCODE_BRANCH 0xe7fe
754 static int thumb_reg
PARAMS ((char ** str
, int hi_lo
));
756 #define THUMB_SIZE 2 /* Size of thumb instruction */
757 #define THUMB_REG_LO 0x1
758 #define THUMB_REG_HI 0x2
759 #define THUMB_REG_ANY 0x3
761 #define THUMB_H1 0x0080
762 #define THUMB_H2 0x0040
769 #define THUMB_COMPARE 1
772 #define THUMB_STORE 1
774 #define THUMB_PP_PC_LR 0x0100
776 /* These three are used for immediate shifts, do not alter */
778 #define THUMB_HALFWORD 1
783 CONST
char * template; /* Basic string to match */
784 unsigned long value
; /* Basic instruction code */
786 unsigned long variants
; /* Which CPU variants this exists for */
787 void (* parms
) PARAMS ((char *)); /* Function to call to parse args */
790 static CONST
struct thumb_opcode tinsns
[] =
792 {"adc", 0x4140, 2, ARM_THUMB
, do_t_arit
},
793 {"add", 0x0000, 2, ARM_THUMB
, do_t_add
},
794 {"and", 0x4000, 2, ARM_THUMB
, do_t_arit
},
795 {"asr", 0x0000, 2, ARM_THUMB
, do_t_asr
},
796 {"b", T_OPCODE_BRANCH
, 2, ARM_THUMB
, do_t_branch12
},
797 {"beq", 0xd0fe, 2, ARM_THUMB
, do_t_branch9
},
798 {"bne", 0xd1fe, 2, ARM_THUMB
, do_t_branch9
},
799 {"bcs", 0xd2fe, 2, ARM_THUMB
, do_t_branch9
},
800 {"bhs", 0xd2fe, 2, ARM_THUMB
, do_t_branch9
},
801 {"bcc", 0xd3fe, 2, ARM_THUMB
, do_t_branch9
},
802 {"bul", 0xd3fe, 2, ARM_THUMB
, do_t_branch9
},
803 {"blo", 0xd3fe, 2, ARM_THUMB
, do_t_branch9
},
804 {"bmi", 0xd4fe, 2, ARM_THUMB
, do_t_branch9
},
805 {"bpl", 0xd5fe, 2, ARM_THUMB
, do_t_branch9
},
806 {"bvs", 0xd6fe, 2, ARM_THUMB
, do_t_branch9
},
807 {"bvc", 0xd7fe, 2, ARM_THUMB
, do_t_branch9
},
808 {"bhi", 0xd8fe, 2, ARM_THUMB
, do_t_branch9
},
809 {"bls", 0xd9fe, 2, ARM_THUMB
, do_t_branch9
},
810 {"bge", 0xdafe, 2, ARM_THUMB
, do_t_branch9
},
811 {"blt", 0xdbfe, 2, ARM_THUMB
, do_t_branch9
},
812 {"bgt", 0xdcfe, 2, ARM_THUMB
, do_t_branch9
},
813 {"ble", 0xddfe, 2, ARM_THUMB
, do_t_branch9
},
814 {"bic", 0x4380, 2, ARM_THUMB
, do_t_arit
},
815 {"bl", 0xf7fffffe, 4, ARM_THUMB
, do_t_branch23
},
816 {"bx", 0x4700, 2, ARM_THUMB
, do_t_bx
},
817 {"cmn", T_OPCODE_CMN
, 2, ARM_THUMB
, do_t_arit
},
818 {"cmp", 0x0000, 2, ARM_THUMB
, do_t_compare
},
819 {"eor", 0x4040, 2, ARM_THUMB
, do_t_arit
},
820 {"ldmia", 0xc800, 2, ARM_THUMB
, do_t_ldmstm
},
821 {"ldr", 0x0000, 2, ARM_THUMB
, do_t_ldr
},
822 {"ldrb", 0x0000, 2, ARM_THUMB
, do_t_ldrb
},
823 {"ldrh", 0x0000, 2, ARM_THUMB
, do_t_ldrh
},
824 {"ldrsb", 0x5600, 2, ARM_THUMB
, do_t_lds
},
825 {"ldrsh", 0x5e00, 2, ARM_THUMB
, do_t_lds
},
826 {"ldsb", 0x5600, 2, ARM_THUMB
, do_t_lds
},
827 {"ldsh", 0x5e00, 2, ARM_THUMB
, do_t_lds
},
828 {"lsl", 0x0000, 2, ARM_THUMB
, do_t_lsl
},
829 {"lsr", 0x0000, 2, ARM_THUMB
, do_t_lsr
},
830 {"mov", 0x0000, 2, ARM_THUMB
, do_t_mov
},
831 {"mul", T_OPCODE_MUL
, 2, ARM_THUMB
, do_t_arit
},
832 {"mvn", T_OPCODE_MVN
, 2, ARM_THUMB
, do_t_arit
},
833 {"neg", T_OPCODE_NEG
, 2, ARM_THUMB
, do_t_arit
},
834 {"orr", 0x4300, 2, ARM_THUMB
, do_t_arit
},
835 {"pop", 0xbc00, 2, ARM_THUMB
, do_t_push_pop
},
836 {"push", 0xb400, 2, ARM_THUMB
, do_t_push_pop
},
837 {"ror", 0x41c0, 2, ARM_THUMB
, do_t_arit
},
838 {"sbc", 0x4180, 2, ARM_THUMB
, do_t_arit
},
839 {"stmia", 0xc000, 2, ARM_THUMB
, do_t_ldmstm
},
840 {"str", 0x0000, 2, ARM_THUMB
, do_t_str
},
841 {"strb", 0x0000, 2, ARM_THUMB
, do_t_strb
},
842 {"strh", 0x0000, 2, ARM_THUMB
, do_t_strh
},
843 {"swi", 0xdf00, 2, ARM_THUMB
, do_t_swi
},
844 {"sub", 0x0000, 2, ARM_THUMB
, do_t_sub
},
845 {"tst", T_OPCODE_TST
, 2, ARM_THUMB
, do_t_arit
},
847 {"adr", 0x0000, 2, ARM_THUMB
, do_t_adr
},
848 {"nop", 0x46C0, 2, ARM_THUMB
, do_t_nop
}, /* mov r8,r8 */
857 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
858 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
859 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
865 /* These are the standard names. Users can add aliases with .req */
866 static CONST
struct reg_entry reg_table
[] =
868 /* Processor Register Numbers. */
869 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
870 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
871 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
872 {"r12", 12}, {"r13", REG_SP
},{"r14", REG_LR
},{"r15", REG_PC
},
873 /* APCS conventions. */
874 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
875 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
876 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
877 {"fp", 11}, {"ip", 12}, {"sp", REG_SP
},{"lr", REG_LR
},{"pc", REG_PC
},
878 /* ATPCS additions to APCS conventions. */
879 {"wr", 7}, {"v8", 11},
881 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
882 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
883 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
884 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
885 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
886 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
887 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
888 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
889 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
890 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
891 /* ATPCS additions to float register names. */
892 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
893 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
894 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
895 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
896 /* FIXME: At some point we need to add VFP register names. */
897 /* Array terminator. */
901 #define BAD_ARGS _("Bad arguments to instruction")
902 #define BAD_PC _("r15 not allowed here")
903 #define BAD_FLAGS _("Instruction should not have flags")
904 #define BAD_COND _("Instruction is not conditional")
906 static struct hash_control
* arm_ops_hsh
= NULL
;
907 static struct hash_control
* arm_tops_hsh
= NULL
;
908 static struct hash_control
* arm_cond_hsh
= NULL
;
909 static struct hash_control
* arm_shift_hsh
= NULL
;
910 static struct hash_control
* arm_reg_hsh
= NULL
;
911 static struct hash_control
* arm_psr_hsh
= NULL
;
913 /* This table describes all the machine specific pseudo-ops the assembler
914 has to support. The fields are:
915 pseudo-op name without dot
916 function to call to execute this pseudo-op
917 Integer arg to pass to the function
920 static void s_req
PARAMS ((int));
921 static void s_align
PARAMS ((int));
922 static void s_bss
PARAMS ((int));
923 static void s_even
PARAMS ((int));
924 static void s_ltorg
PARAMS ((int));
925 static void s_arm
PARAMS ((int));
926 static void s_thumb
PARAMS ((int));
927 static void s_code
PARAMS ((int));
928 static void s_force_thumb
PARAMS ((int));
929 static void s_thumb_func
PARAMS ((int));
930 static void s_thumb_set
PARAMS ((int));
931 static void arm_s_text
PARAMS ((int));
932 static void arm_s_data
PARAMS ((int));
934 static void arm_s_section
PARAMS ((int));
935 static void s_arm_elf_cons
PARAMS ((int));
938 static int my_get_expression
PARAMS ((expressionS
*, char **));
940 CONST pseudo_typeS md_pseudo_table
[] =
942 { "req", s_req
, 0 }, /* Never called becasue '.req' does not start line */
944 { "align", s_align
, 0 },
946 { "thumb", s_thumb
, 0 },
947 { "code", s_code
, 0 },
948 { "force_thumb", s_force_thumb
, 0 },
949 { "thumb_func", s_thumb_func
, 0 },
950 { "thumb_set", s_thumb_set
, 0 },
951 { "even", s_even
, 0 },
952 { "ltorg", s_ltorg
, 0 },
953 { "pool", s_ltorg
, 0 },
954 /* Allow for the effect of section changes. */
955 { "text", arm_s_text
, 0 },
956 { "data", arm_s_data
, 0 },
958 { "section", arm_s_section
, 0 },
959 { "section.s", arm_s_section
, 0 },
960 { "sect", arm_s_section
, 0 },
961 { "sect.s", arm_s_section
, 0 },
962 { "word", s_arm_elf_cons
, 4 },
963 { "long", s_arm_elf_cons
, 4 },
967 { "extend", float_cons
, 'x' },
968 { "ldouble", float_cons
, 'x' },
969 { "packed", float_cons
, 'p' },
973 /* Stuff needed to resolve the label ambiguity
983 symbolS
* last_label_seen
;
984 static int label_is_thumb_function_name
= false;
988 #define MAX_LITERAL_POOL_SIZE 1024
990 typedef struct literalS
992 struct expressionS exp
;
993 struct arm_it
* inst
;
996 literalT literals
[MAX_LITERAL_POOL_SIZE
];
997 int next_literal_pool_place
= 0; /* Next free entry in the pool */
998 int lit_pool_num
= 1; /* Next literal pool number */
999 symbolS
* current_poolP
= NULL
;
1006 if (current_poolP
== NULL
)
1007 current_poolP
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1008 (valueT
) 0, &zero_address_frag
);
1010 /* Check if this literal value is already in the pool: */
1011 while (lit_count
< next_literal_pool_place
)
1013 if (literals
[lit_count
].exp
.X_op
== inst
.reloc
.exp
.X_op
1014 && inst
.reloc
.exp
.X_op
== O_constant
1015 && literals
[lit_count
].exp
.X_add_number
== inst
.reloc
.exp
.X_add_number
1016 && literals
[lit_count
].exp
.X_unsigned
== inst
.reloc
.exp
.X_unsigned
)
1021 if (lit_count
== next_literal_pool_place
) /* new entry */
1023 if (next_literal_pool_place
> MAX_LITERAL_POOL_SIZE
)
1025 inst
.error
= _("Literal Pool Overflow");
1029 literals
[next_literal_pool_place
].exp
= inst
.reloc
.exp
;
1030 lit_count
= next_literal_pool_place
++;
1033 inst
.reloc
.exp
.X_op
= O_symbol
;
1034 inst
.reloc
.exp
.X_add_number
= (lit_count
) * 4 - 8;
1035 inst
.reloc
.exp
.X_add_symbol
= current_poolP
;
1040 /* Can't use symbol_new here, so have to create a symbol and then at
1041 a later date assign it a value. Thats what these functions do. */
1043 symbol_locate (symbolP
, name
, segment
, valu
, frag
)
1045 CONST
char * name
; /* It is copied, the caller can modify */
1046 segT segment
; /* Segment identifier (SEG_<something>) */
1047 valueT valu
; /* Symbol value */
1048 fragS
* frag
; /* Associated fragment */
1050 unsigned int name_length
;
1051 char * preserved_copy_of_name
;
1053 name_length
= strlen (name
) + 1; /* +1 for \0 */
1054 obstack_grow (¬es
, name
, name_length
);
1055 preserved_copy_of_name
= obstack_finish (¬es
);
1056 #ifdef STRIP_UNDERSCORE
1057 if (preserved_copy_of_name
[0] == '_')
1058 preserved_copy_of_name
++;
1061 #ifdef tc_canonicalize_symbol_name
1062 preserved_copy_of_name
=
1063 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1066 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1068 S_SET_SEGMENT (symbolP
, segment
);
1069 S_SET_VALUE (symbolP
, valu
);
1070 symbol_clear_list_pointers(symbolP
);
1072 symbol_set_frag (symbolP
, frag
);
1074 /* Link to end of symbol chain. */
1076 extern int symbol_table_frozen
;
1077 if (symbol_table_frozen
)
1081 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
1083 obj_symbol_new_hook (symbolP
);
1085 #ifdef tc_symbol_new_hook
1086 tc_symbol_new_hook (symbolP
);
1090 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1091 #endif /* DEBUG_SYMS */
1094 /* Check that an immediate is valid, and if so, convert it to the right format. */
1097 validate_immediate (val
)
1103 #define rotate_left(v, n) (v << n | v >> (32 - n))
1105 for (i
= 0; i
< 32; i
+= 2)
1106 if ((a
= rotate_left (val
, i
)) <= 0xff)
1107 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const] */
1112 /* Check to see if an immediate can be computed as two seperate immediate
1113 values, added together. We already know that this value cannot be
1114 computed by just one ARM instruction. */
1117 validate_immediate_twopart (val
, highpart
)
1119 unsigned int * highpart
;
1124 for (i
= 0; i
< 32; i
+= 2)
1125 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
1131 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
1133 else if (a
& 0xff0000)
1138 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
1142 assert (a
& 0xff000000);
1144 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
1147 return (a
& 0xff) | (i
<< 7);
1154 validate_offset_imm (val
, hwse
)
1158 if ((hwse
&& val
> 255) || val
> 4095)
1166 int a ATTRIBUTE_UNUSED
;
1168 as_bad (_("Invalid syntax for .req directive."));
1173 int ignore ATTRIBUTE_UNUSED
;
1175 /* We don't support putting frags in the BSS segment, we fake it by
1176 marking in_bss, then looking at s_skip for clues?.. */
1177 subseg_set (bss_section
, 0);
1178 demand_empty_rest_of_line ();
1183 int ignore ATTRIBUTE_UNUSED
;
1185 if (!need_pass_2
) /* Never make frag if expect extra pass. */
1186 frag_align (1, 0, 0);
1188 record_alignment (now_seg
, 1);
1190 demand_empty_rest_of_line ();
1195 int ignored ATTRIBUTE_UNUSED
;
1200 if (current_poolP
== NULL
)
1203 /* Align pool as you have word accesses */
1204 /* Only make a frag if we have to ... */
1206 frag_align (2, 0, 0);
1208 record_alignment (now_seg
, 2);
1210 sprintf (sym_name
, "$$lit_\002%x", lit_pool_num
++);
1212 symbol_locate (current_poolP
, sym_name
, now_seg
,
1213 (valueT
) frag_now_fix (), frag_now
);
1214 symbol_table_insert (current_poolP
);
1216 ARM_SET_THUMB (current_poolP
, thumb_mode
);
1218 #if defined OBJ_COFF || defined OBJ_ELF
1219 ARM_SET_INTERWORK (current_poolP
, support_interwork
);
1222 while (lit_count
< next_literal_pool_place
)
1223 /* First output the expression in the instruction to the pool */
1224 emit_expr (&(literals
[lit_count
++].exp
), 4); /* .word */
1226 next_literal_pool_place
= 0;
1227 current_poolP
= NULL
;
1231 s_align (unused
) /* Same as s_align_ptwo but align 0 => align 2 */
1232 int unused ATTRIBUTE_UNUSED
;
1235 register long temp_fill
;
1236 long max_alignment
= 15;
1238 temp
= get_absolute_expression ();
1239 if (temp
> max_alignment
)
1240 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
1243 as_bad (_("Alignment negative. 0 assumed."));
1247 if (*input_line_pointer
== ',')
1249 input_line_pointer
++;
1250 temp_fill
= get_absolute_expression ();
1258 /* Only make a frag if we HAVE to. . . */
1259 if (temp
&& !need_pass_2
)
1260 frag_align (temp
, (int) temp_fill
, 0);
1261 demand_empty_rest_of_line ();
1263 record_alignment (now_seg
, temp
);
1267 s_force_thumb (ignore
)
1268 int ignore ATTRIBUTE_UNUSED
;
1270 /* If we are not already in thumb mode go into it, EVEN if
1271 the target processor does not support thumb instructions.
1272 This is used by gcc/config/arm/lib1funcs.asm for example
1273 to compile interworking support functions even if the
1274 target processor should not support interworking. */
1280 record_alignment (now_seg
, 1);
1283 demand_empty_rest_of_line ();
1287 s_thumb_func (ignore
)
1288 int ignore ATTRIBUTE_UNUSED
;
1290 /* The following label is the name/address of the start of a Thumb function.
1291 We need to know this for the interworking support. */
1293 label_is_thumb_function_name
= true;
1295 demand_empty_rest_of_line ();
1298 /* Perform a .set directive, but also mark the alias as
1299 being a thumb function. */
1305 /* XXX the following is a duplicate of the code for s_set() in read.c
1306 We cannot just call that code as we need to get at the symbol that
1308 register char * name
;
1309 register char delim
;
1310 register char * end_name
;
1311 register symbolS
* symbolP
;
1314 * Especial apologies for the random logic:
1315 * this just grew, and could be parsed much more simply!
1318 name
= input_line_pointer
;
1319 delim
= get_symbol_end ();
1320 end_name
= input_line_pointer
;
1325 if (*input_line_pointer
!= ',')
1328 as_bad (_("Expected comma after name \"%s\""), name
);
1330 ignore_rest_of_line ();
1334 input_line_pointer
++;
1337 if (name
[0] == '.' && name
[1] == '\0')
1339 /* XXX - this should not happen to .thumb_set */
1343 if ((symbolP
= symbol_find (name
)) == NULL
1344 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
1347 /* When doing symbol listings, play games with dummy fragments living
1348 outside the normal fragment chain to record the file and line info
1350 if (listing
& LISTING_SYMBOLS
)
1352 extern struct list_info_struct
* listing_tail
;
1353 fragS
* dummy_frag
= (fragS
*) xmalloc (sizeof(fragS
));
1354 memset (dummy_frag
, 0, sizeof(fragS
));
1355 dummy_frag
->fr_type
= rs_fill
;
1356 dummy_frag
->line
= listing_tail
;
1357 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
1358 dummy_frag
->fr_symbol
= symbolP
;
1362 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
1365 /* "set" symbols are local unless otherwise specified. */
1366 SF_SET_LOCAL (symbolP
);
1367 #endif /* OBJ_COFF */
1368 } /* make a new symbol */
1370 symbol_table_insert (symbolP
);
1375 && S_IS_DEFINED (symbolP
)
1376 && S_GET_SEGMENT (symbolP
) != reg_section
)
1377 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
1379 pseudo_set (symbolP
);
1381 demand_empty_rest_of_line ();
1383 /* XXX Now we come to the Thumb specific bit of code. */
1385 THUMB_SET_FUNC (symbolP
, 1);
1386 ARM_SET_THUMB (symbolP
, 1);
1387 #if defined OBJ_ELF || defined OBJ_COFF
1388 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1392 /* If we change section we must dump the literal pool first. */
1397 if (now_seg
!= text_section
)
1401 obj_elf_text (ignore
);
1411 if (flag_readonly_data_in_text
)
1413 if (now_seg
!= text_section
)
1416 else if (now_seg
!= data_section
)
1420 obj_elf_data (ignore
);
1428 arm_s_section (ignore
)
1433 obj_elf_section (ignore
);
1438 opcode_select (width
)
1446 if (! (cpu_variant
& ARM_THUMB
))
1447 as_bad (_("selected processor does not support THUMB opcodes"));
1449 /* No need to force the alignment, since we will have been
1450 coming from ARM mode, which is word-aligned. */
1451 record_alignment (now_seg
, 1);
1458 if ((cpu_variant
& ARM_ANY
) == ARM_THUMB
)
1459 as_bad (_("selected processor does not support ARM opcodes"));
1462 frag_align (2, 0, 0);
1463 record_alignment (now_seg
, 1);
1468 as_bad (_("invalid instruction size selected (%d)"), width
);
1474 int ignore ATTRIBUTE_UNUSED
;
1477 demand_empty_rest_of_line ();
1482 int ignore ATTRIBUTE_UNUSED
;
1485 demand_empty_rest_of_line ();
1490 int unused ATTRIBUTE_UNUSED
;
1494 temp
= get_absolute_expression ();
1499 opcode_select (temp
);
1503 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
1511 skip_whitespace (str
);
1514 inst
.error
= _("Garbage following instruction");
1518 skip_past_comma (str
)
1524 while ((c
= *p
) == ' ' || c
== ',')
1527 if (c
== ',' && comma
++)
1535 return comma
? SUCCESS
: FAIL
;
1538 /* A standard register must be given at this point.
1539 Shift is the place to put it in inst.instruction.
1540 Restores input start point on err.
1541 Returns the reg#, or FAIL. */
1544 reg_required_here (str
, shift
)
1548 static char buff
[128]; /* XXX */
1550 char * start
= *str
;
1552 if ((reg
= arm_reg_parse (str
)) != FAIL
&& int_register (reg
))
1555 inst
.instruction
|= reg
<< shift
;
1559 /* Restore the start point, we may have got a reg of the wrong class. */
1562 /* In the few cases where we might be able to accept something else
1563 this error can be overridden. */
1564 sprintf (buff
, _("Register expected, not '%.100s'"), start
);
1571 psr_required_here (str
, cpsr
, spsr
)
1577 char * start
= *str
;
1578 psr
= arm_psr_parse (str
);
1580 if (psr
== cpsr
|| psr
== spsr
)
1583 inst
.instruction
|= 1 << 22;
1588 /* In the few cases where we might be able to accept something else
1589 this error can be overridden. */
1590 inst
.error
= _("<psr(f)> expected");
1592 /* Restore the start point. */
1598 co_proc_number (str
)
1601 int processor
, pchar
;
1603 skip_whitespace (* str
);
1605 /* The data sheet seems to imply that just a number on its own is valid
1606 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1608 if (**str
== 'p' || **str
== 'P')
1612 if (pchar
>= '0' && pchar
<= '9')
1614 processor
= pchar
- '0';
1615 if (**str
>= '0' && **str
<= '9')
1617 processor
= processor
* 10 + *(*str
)++ - '0';
1620 inst
.error
= _("Illegal co-processor number");
1627 inst
.error
= _("Bad or missing co-processor number");
1631 inst
.instruction
|= processor
<< 8;
1636 cp_opc_expr (str
, where
, length
)
1643 skip_whitespace (* str
);
1645 memset (&expr
, '\0', sizeof (expr
));
1647 if (my_get_expression (&expr
, str
))
1649 if (expr
.X_op
!= O_constant
)
1651 inst
.error
= _("bad or missing expression");
1655 if ((expr
.X_add_number
& ((1 << length
) - 1)) != expr
.X_add_number
)
1657 inst
.error
= _("immediate co-processor expression too large");
1661 inst
.instruction
|= expr
.X_add_number
<< where
;
1666 cp_reg_required_here (str
, where
)
1671 char * start
= *str
;
1673 if ((reg
= arm_reg_parse (str
)) != FAIL
&& cp_register (reg
))
1676 inst
.instruction
|= reg
<< where
;
1680 /* In the few cases where we might be able to accept something else
1681 this error can be overridden. */
1682 inst
.error
= _("Co-processor register expected");
1684 /* Restore the start point. */
1690 fp_reg_required_here (str
, where
)
1695 char * start
= *str
;
1697 if ((reg
= arm_reg_parse (str
)) != FAIL
&& fp_register (reg
))
1700 inst
.instruction
|= reg
<< where
;
1704 /* In the few cases where we might be able to accept something else
1705 this error can be overridden. */
1706 inst
.error
= _("Floating point register expected");
1708 /* Restore the start point. */
1714 cp_address_offset (str
)
1719 skip_whitespace (* str
);
1721 if (! is_immediate_prefix (**str
))
1723 inst
.error
= _("immediate expression expected");
1729 if (my_get_expression (& inst
.reloc
.exp
, str
))
1732 if (inst
.reloc
.exp
.X_op
== O_constant
)
1734 offset
= inst
.reloc
.exp
.X_add_number
;
1738 inst
.error
= _("co-processor address must be word aligned");
1742 if (offset
> 1023 || offset
< -1023)
1744 inst
.error
= _("offset too large");
1749 inst
.instruction
|= INDEX_UP
;
1753 inst
.instruction
|= offset
>> 2;
1756 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
1762 cp_address_required_here (str
)
1774 skip_whitespace (p
);
1776 if ((reg
= reg_required_here (& p
, 16)) == FAIL
)
1779 skip_whitespace (p
);
1785 if (skip_past_comma (& p
) == SUCCESS
)
1788 write_back
= WRITE_BACK
;
1792 inst
.error
= _("pc may not be used in post-increment");
1796 if (cp_address_offset (& p
) == FAIL
)
1800 pre_inc
= PRE_INDEX
| INDEX_UP
;
1804 /* '['Rn, #expr']'[!] */
1806 if (skip_past_comma (& p
) == FAIL
)
1808 inst
.error
= _("pre-indexed expression expected");
1812 pre_inc
= PRE_INDEX
;
1814 if (cp_address_offset (& p
) == FAIL
)
1817 skip_whitespace (p
);
1821 inst
.error
= _("missing ]");
1825 skip_whitespace (p
);
1831 inst
.error
= _("pc may not be used with write-back");
1836 write_back
= WRITE_BACK
;
1842 if (my_get_expression (&inst
.reloc
.exp
, &p
))
1845 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
1846 inst
.reloc
.exp
.X_add_number
-= 8; /* PC rel adjust */
1847 inst
.reloc
.pc_rel
= 1;
1848 inst
.instruction
|= (REG_PC
<< 16);
1849 pre_inc
= PRE_INDEX
;
1852 inst
.instruction
|= write_back
| pre_inc
;
1860 unsigned long flags
;
1862 /* Do nothing really. */
1863 inst
.instruction
|= flags
; /* This is pointless. */
1871 unsigned long flags
;
1873 /* Only one syntax. */
1874 skip_whitespace (str
);
1876 if (reg_required_here (&str
, 12) == FAIL
)
1878 inst
.error
= BAD_ARGS
;
1882 if (skip_past_comma (&str
) == FAIL
1883 || psr_required_here (& str
, CPSR_ALL
, SPSR_ALL
) == FAIL
)
1885 inst
.error
= _("<psr> expected");
1889 inst
.instruction
|= flags
;
1894 /* Three possible forms: "<psr>, Rm", "<psrf>, Rm", "<psrf>, #expression". */
1898 unsigned long flags
;
1902 skip_whitespace (str
);
1904 if (psr_required_here (&str
, CPSR_ALL
, SPSR_ALL
) == SUCCESS
)
1906 inst
.instruction
|= PSR_ALL
;
1908 /* Sytax should be "<psr>, Rm" */
1909 if (skip_past_comma (&str
) == FAIL
1910 || (reg
= reg_required_here (&str
, 0)) == FAIL
)
1912 inst
.error
= BAD_ARGS
;
1918 if (psr_required_here (& str
, CPSR_FLG
, SPSR_FLG
) == SUCCESS
)
1919 inst
.instruction
|= PSR_FLAGS
;
1920 else if (psr_required_here (& str
, CPSR_CTL
, SPSR_CTL
) == SUCCESS
)
1921 inst
.instruction
|= PSR_CONTROL
;
1924 inst
.error
= BAD_ARGS
;
1928 if (skip_past_comma (&str
) == FAIL
)
1930 inst
.error
= BAD_ARGS
;
1934 /* Syntax could be "<psrf>, rm", "<psrf>, #expression" */
1936 if ((reg
= reg_required_here (& str
, 0)) != FAIL
)
1938 /* Immediate expression. */
1939 else if (is_immediate_prefix (* str
))
1944 if (my_get_expression (& inst
.reloc
.exp
, & str
))
1946 inst
.error
= _("Register or shift expression expected");
1950 if (inst
.reloc
.exp
.X_add_symbol
)
1952 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
1953 inst
.reloc
.pc_rel
= 0;
1957 unsigned value
= validate_immediate (inst
.reloc
.exp
.X_add_number
);
1958 if (value
== (unsigned) FAIL
)
1960 inst
.error
= _("Invalid constant");
1964 inst
.instruction
|= value
;
1967 flags
|= INST_IMMEDIATE
;
1971 inst
.error
= _("Error: unrecognised syntax for second argument to msr instruction");
1977 inst
.instruction
|= flags
;
1982 /* Long Multiply Parser
1983 UMULL RdLo, RdHi, Rm, Rs
1984 SMULL RdLo, RdHi, Rm, Rs
1985 UMLAL RdLo, RdHi, Rm, Rs
1986 SMLAL RdLo, RdHi, Rm, Rs
1989 do_mull (str
, flags
)
1991 unsigned long flags
;
1993 int rdlo
, rdhi
, rm
, rs
;
1995 /* Only one format "rdlo, rdhi, rm, rs" */
1996 skip_whitespace (str
);
1998 if ((rdlo
= reg_required_here (&str
, 12)) == FAIL
)
2000 inst
.error
= BAD_ARGS
;
2004 if (skip_past_comma (&str
) == FAIL
2005 || (rdhi
= reg_required_here (&str
, 16)) == FAIL
)
2007 inst
.error
= BAD_ARGS
;
2011 if (skip_past_comma (&str
) == FAIL
2012 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2014 inst
.error
= BAD_ARGS
;
2018 /* rdhi, rdlo and rm must all be different */
2019 if (rdlo
== rdhi
|| rdlo
== rm
|| rdhi
== rm
)
2020 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2022 if (skip_past_comma (&str
) == FAIL
2023 || (rs
= reg_required_here (&str
, 8)) == FAIL
)
2025 inst
.error
= BAD_ARGS
;
2029 if (rdhi
== REG_PC
|| rdhi
== REG_PC
|| rdhi
== REG_PC
|| rdhi
== REG_PC
)
2031 inst
.error
= BAD_PC
;
2035 inst
.instruction
|= flags
;
2043 unsigned long flags
;
2047 /* Only one format "rd, rm, rs" */
2048 skip_whitespace (str
);
2050 if ((rd
= reg_required_here (&str
, 16)) == FAIL
)
2052 inst
.error
= BAD_ARGS
;
2058 inst
.error
= BAD_PC
;
2062 if (skip_past_comma (&str
) == FAIL
2063 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2065 inst
.error
= BAD_ARGS
;
2071 inst
.error
= BAD_PC
;
2076 as_tsktsk (_("rd and rm should be different in mul"));
2078 if (skip_past_comma (&str
) == FAIL
2079 || (rm
= reg_required_here (&str
, 8)) == FAIL
)
2081 inst
.error
= BAD_ARGS
;
2087 inst
.error
= BAD_PC
;
2091 inst
.instruction
|= flags
;
2099 unsigned long flags
;
2103 /* Only one format "rd, rm, rs, rn" */
2104 skip_whitespace (str
);
2106 if ((rd
= reg_required_here (&str
, 16)) == FAIL
)
2108 inst
.error
= BAD_ARGS
;
2114 inst
.error
= BAD_PC
;
2118 if (skip_past_comma (&str
) == FAIL
2119 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2121 inst
.error
= BAD_ARGS
;
2127 inst
.error
= BAD_PC
;
2132 as_tsktsk (_("rd and rm should be different in mla"));
2134 if (skip_past_comma (&str
) == FAIL
2135 || (rd
= reg_required_here (&str
, 8)) == FAIL
2136 || skip_past_comma (&str
) == FAIL
2137 || (rm
= reg_required_here (&str
, 12)) == FAIL
)
2139 inst
.error
= BAD_ARGS
;
2143 if (rd
== REG_PC
|| rm
== REG_PC
)
2145 inst
.error
= BAD_PC
;
2149 inst
.instruction
|= flags
;
2154 /* Returns the index into fp_values of a floating point number, or -1 if
2155 not in the table. */
2157 my_get_float_expression (str
)
2160 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2166 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
2167 /* Look for a raw floating point number */
2168 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
2169 && (is_end_of_line
[(int)(*save_in
)] || *save_in
== '\0'))
2171 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
2173 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
2175 if (words
[j
] != fp_values
[i
][j
])
2179 if (j
== MAX_LITTLENUMS
)
2187 /* Try and parse a more complex expression, this will probably fail
2188 unless the code uses a floating point prefix (eg "0f") */
2189 save_in
= input_line_pointer
;
2190 input_line_pointer
= *str
;
2191 if (expression (&exp
) == absolute_section
2192 && exp
.X_op
== O_big
2193 && exp
.X_add_number
< 0)
2195 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2197 if (gen_to_words (words
, 5, (long)15) == 0)
2199 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
2201 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
2203 if (words
[j
] != fp_values
[i
][j
])
2207 if (j
== MAX_LITTLENUMS
)
2209 *str
= input_line_pointer
;
2210 input_line_pointer
= save_in
;
2217 *str
= input_line_pointer
;
2218 input_line_pointer
= save_in
;
2222 /* Return true if anything in the expression is a bignum */
2224 walk_no_bignums (sp
)
2227 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
2230 if (symbol_get_value_expression (sp
)->X_add_symbol
)
2232 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
2233 || (symbol_get_value_expression (sp
)->X_op_symbol
2234 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
2241 my_get_expression (ep
, str
)
2248 save_in
= input_line_pointer
;
2249 input_line_pointer
= *str
;
2250 seg
= expression (ep
);
2253 if (seg
!= absolute_section
2254 && seg
!= text_section
2255 && seg
!= data_section
2256 && seg
!= bss_section
2257 && seg
!= undefined_section
)
2259 inst
.error
= _("bad_segment");
2260 *str
= input_line_pointer
;
2261 input_line_pointer
= save_in
;
2266 /* Get rid of any bignums now, so that we don't generate an error for which
2267 we can't establish a line number later on. Big numbers are never valid
2268 in instructions, which is where this routine is always called. */
2269 if (ep
->X_op
== O_big
2270 || (ep
->X_add_symbol
2271 && (walk_no_bignums (ep
->X_add_symbol
)
2273 && walk_no_bignums (ep
->X_op_symbol
)))))
2275 inst
.error
= _("Invalid constant");
2276 *str
= input_line_pointer
;
2277 input_line_pointer
= save_in
;
2281 *str
= input_line_pointer
;
2282 input_line_pointer
= save_in
;
2286 /* unrestrict should be one if <shift> <register> is permitted for this
2290 decode_shift (str
, unrestrict
)
2294 struct asm_shift
* shft
;
2298 skip_whitespace (* str
);
2300 for (p
= *str
; isalpha (*p
); p
++)
2305 inst
.error
= _("Shift expression expected");
2311 shft
= (struct asm_shift
*) hash_find (arm_shift_hsh
, *str
);
2315 if (!strncmp (*str
, "rrx", 3)
2316 || !strncmp (*str
, "RRX", 3))
2319 inst
.instruction
|= shft
->value
;
2323 skip_whitespace (p
);
2325 if (unrestrict
&& reg_required_here (&p
, 8) != FAIL
)
2327 inst
.instruction
|= shft
->value
| SHIFT_BY_REG
;
2331 else if (is_immediate_prefix (* p
))
2335 if (my_get_expression (&inst
.reloc
.exp
, &p
))
2338 /* Validate some simple #expressions */
2339 if (inst
.reloc
.exp
.X_op
== O_constant
)
2341 unsigned num
= inst
.reloc
.exp
.X_add_number
;
2343 /* Reject operations greater than 32, or lsl #32 */
2344 if (num
> 32 || (num
== 32 && shft
->value
== 0))
2346 inst
.error
= _("Invalid immediate shift");
2350 /* Shifts of zero should be converted to lsl (which is zero)*/
2357 /* Shifts of 32 are encoded as 0, for those shifts that
2362 inst
.instruction
|= (num
<< 7) | shft
->value
;
2367 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
2368 inst
.reloc
.pc_rel
= 0;
2369 inst
.instruction
|= shft
->value
;
2375 inst
.error
= unrestrict
? _("shift requires register or #expression")
2376 : _("shift requires #expression");
2382 inst
.error
= _("Shift expression expected");
2386 /* Do those data_ops which can take a negative immediate constant */
2387 /* by altering the instuction. A bit of a hack really */
2391 by inverting the second operand, and
2394 by negating the second operand.
2397 negate_data_op (instruction
, value
)
2398 unsigned long * instruction
;
2399 unsigned long value
;
2402 unsigned long negated
, inverted
;
2404 negated
= validate_immediate (-value
);
2405 inverted
= validate_immediate (~value
);
2407 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
2411 case OPCODE_SUB
: /* ADD <-> SUB */
2412 new_inst
= OPCODE_ADD
;
2417 new_inst
= OPCODE_SUB
;
2421 case OPCODE_CMP
: /* CMP <-> CMN */
2422 new_inst
= OPCODE_CMN
;
2427 new_inst
= OPCODE_CMP
;
2431 /* Now Inverted ops */
2432 case OPCODE_MOV
: /* MOV <-> MVN */
2433 new_inst
= OPCODE_MVN
;
2438 new_inst
= OPCODE_MOV
;
2442 case OPCODE_AND
: /* AND <-> BIC */
2443 new_inst
= OPCODE_BIC
;
2448 new_inst
= OPCODE_AND
;
2452 case OPCODE_ADC
: /* ADC <-> SBC */
2453 new_inst
= OPCODE_SBC
;
2458 new_inst
= OPCODE_ADC
;
2462 /* We cannot do anything */
2467 if (value
== (unsigned) FAIL
)
2470 *instruction
&= OPCODE_MASK
;
2471 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
2482 skip_whitespace (* str
);
2484 if (reg_required_here (str
, 0) != FAIL
)
2486 if (skip_past_comma (str
) == SUCCESS
)
2487 /* Shift operation on register. */
2488 return decode_shift (str
, NO_SHIFT_RESTRICT
);
2494 /* Immediate expression */
2495 if (is_immediate_prefix (**str
))
2500 if (my_get_expression (&inst
.reloc
.exp
, str
))
2503 if (inst
.reloc
.exp
.X_add_symbol
)
2505 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
2506 inst
.reloc
.pc_rel
= 0;
2510 if (skip_past_comma (str
) == SUCCESS
)
2512 /* #x, y -- ie explicit rotation by Y */
2513 if (my_get_expression (&expr
, str
))
2516 if (expr
.X_op
!= O_constant
)
2518 inst
.error
= _("Constant expression expected");
2522 /* Rotate must be a multiple of 2 */
2523 if (((unsigned) expr
.X_add_number
) > 30
2524 || (expr
.X_add_number
& 1) != 0
2525 || ((unsigned) inst
.reloc
.exp
.X_add_number
) > 255)
2527 inst
.error
= _("Invalid constant");
2530 inst
.instruction
|= INST_IMMEDIATE
;
2531 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
2532 inst
.instruction
|= expr
.X_add_number
<< 7;
2536 /* Implicit rotation, select a suitable one */
2537 value
= validate_immediate (inst
.reloc
.exp
.X_add_number
);
2541 /* Can't be done, perhaps the code reads something like
2542 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok */
2543 if ((value
= negate_data_op (&inst
.instruction
,
2544 inst
.reloc
.exp
.X_add_number
))
2547 inst
.error
= _("Invalid constant");
2552 inst
.instruction
|= value
;
2555 inst
.instruction
|= INST_IMMEDIATE
;
2560 inst
.error
= _("Register or shift expression expected");
2569 skip_whitespace (* str
);
2571 if (fp_reg_required_here (str
, 0) != FAIL
)
2575 /* Immediate expression */
2576 if (*((*str
)++) == '#')
2582 skip_whitespace (* str
);
2584 /* First try and match exact strings, this is to guarantee that
2585 some formats will work even for cross assembly */
2587 for (i
= 0; fp_const
[i
]; i
++)
2589 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
2593 *str
+= strlen (fp_const
[i
]);
2594 if (is_end_of_line
[(int)**str
] || **str
== '\0')
2596 inst
.instruction
|= i
+ 8;
2603 /* Just because we didn't get a match doesn't mean that the
2604 constant isn't valid, just that it is in a format that we
2605 don't automatically recognize. Try parsing it with
2606 the standard expression routines. */
2607 if ((i
= my_get_float_expression (str
)) >= 0)
2609 inst
.instruction
|= i
+ 8;
2613 inst
.error
= _("Invalid floating point immediate expression");
2616 inst
.error
= _("Floating point register or immediate expression expected");
2622 do_arit (str
, flags
)
2624 unsigned long flags
;
2626 skip_whitespace (str
);
2628 if (reg_required_here (&str
, 12) == FAIL
2629 || skip_past_comma (&str
) == FAIL
2630 || reg_required_here (&str
, 16) == FAIL
2631 || skip_past_comma (&str
) == FAIL
2632 || data_op2 (&str
) == FAIL
)
2635 inst
.error
= BAD_ARGS
;
2639 inst
.instruction
|= flags
;
2647 unsigned long flags
;
2649 /* This is a pseudo-op of the form "adr rd, label" to be converted
2650 into a relative address of the form "add rd, pc, #label-.-8" */
2652 skip_whitespace (str
);
2654 if (reg_required_here (&str
, 12) == FAIL
2655 || skip_past_comma (&str
) == FAIL
2656 || my_get_expression (&inst
.reloc
.exp
, &str
))
2659 inst
.error
= BAD_ARGS
;
2662 /* Frag hacking will turn this into a sub instruction if the offset turns
2663 out to be negative. */
2664 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
2665 inst
.reloc
.exp
.X_add_number
-= 8; /* PC relative adjust */
2666 inst
.reloc
.pc_rel
= 1;
2667 inst
.instruction
|= flags
;
2673 do_adrl (str
, flags
)
2675 unsigned long flags
;
2677 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2678 into a relative address of the form:
2679 add rd, pc, #low(label-.-8)"
2680 add rd, rd, #high(label-.-8)" */
2682 skip_whitespace (str
);
2684 if (reg_required_here (& str
, 12) == FAIL
2685 || skip_past_comma (& str
) == FAIL
2686 || my_get_expression (& inst
.reloc
.exp
, & str
))
2689 inst
.error
= BAD_ARGS
;
2695 /* Frag hacking will turn this into a sub instruction if the offset turns
2696 out to be negative. */
2697 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
2698 inst
.reloc
.exp
.X_add_number
-= 8; /* PC relative adjust */
2699 inst
.reloc
.pc_rel
= 1;
2700 inst
.instruction
|= flags
;
2701 inst
.size
= INSN_SIZE
* 2;
2709 unsigned long flags
;
2711 skip_whitespace (str
);
2713 if (reg_required_here (&str
, 16) == FAIL
)
2716 inst
.error
= BAD_ARGS
;
2720 if (skip_past_comma (&str
) == FAIL
2721 || data_op2 (&str
) == FAIL
)
2724 inst
.error
= BAD_ARGS
;
2728 inst
.instruction
|= flags
;
2729 if ((flags
& 0x0000f000) == 0)
2730 inst
.instruction
|= CONDS_BIT
;
2739 unsigned long flags
;
2741 skip_whitespace (str
);
2743 if (reg_required_here (&str
, 12) == FAIL
)
2746 inst
.error
= BAD_ARGS
;
2750 if (skip_past_comma (&str
) == FAIL
2751 || data_op2 (&str
) == FAIL
)
2754 inst
.error
= BAD_ARGS
;
2758 inst
.instruction
|= flags
;
2764 ldst_extend (str
, hwse
)
2775 if (my_get_expression (& inst
.reloc
.exp
, str
))
2778 if (inst
.reloc
.exp
.X_op
== O_constant
)
2780 int value
= inst
.reloc
.exp
.X_add_number
;
2782 if ((hwse
&& (value
< -255 || value
> 255))
2783 || (value
< -4095 || value
> 4095))
2785 inst
.error
= _("address offset too large");
2795 /* Halfword and signextension instructions have the
2796 immediate value split across bits 11..8 and bits 3..0 */
2798 inst
.instruction
|= add
| HWOFFSET_IMM
| ((value
>> 4) << 8) | (value
& 0xF);
2800 inst
.instruction
|= add
| value
;
2806 inst
.instruction
|= HWOFFSET_IMM
;
2807 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
2810 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
2811 inst
.reloc
.pc_rel
= 0;
2816 add
= 0; /* and fall through */
2818 (*str
)++; /* and fall through */
2820 if (reg_required_here (str
, 0) == FAIL
)
2824 inst
.instruction
|= add
;
2827 inst
.instruction
|= add
| OFFSET_REG
;
2828 if (skip_past_comma (str
) == SUCCESS
)
2829 return decode_shift (str
, SHIFT_RESTRICT
);
2837 do_ldst (str
, flags
)
2839 unsigned long flags
;
2846 /* This is not ideal, but it is the simplest way of dealing with the
2847 ARM7T halfword instructions (since they use a different
2848 encoding, but the same mnemonic): */
2849 halfword
= (flags
& 0x80000000) != 0;
2852 /* This is actually a load/store of a halfword, or a
2853 signed-extension load */
2854 if ((cpu_variant
& ARM_HALFWORD
) == 0)
2857 = _("Processor does not support halfwords or signed bytes");
2861 inst
.instruction
= (inst
.instruction
& COND_MASK
)
2862 | (flags
& ~COND_MASK
);
2867 skip_whitespace (str
);
2869 if ((conflict_reg
= reg_required_here (& str
, 12)) == FAIL
)
2872 inst
.error
= BAD_ARGS
;
2876 if (skip_past_comma (& str
) == FAIL
)
2878 inst
.error
= _("Address expected");
2888 skip_whitespace (str
);
2890 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
2893 /* Conflicts can occur on stores as well as loads. */
2894 conflict_reg
= (conflict_reg
== reg
);
2896 skip_whitespace (str
);
2902 if (skip_past_comma (&str
) == SUCCESS
)
2904 /* [Rn],... (post inc) */
2905 if (ldst_extend (&str
, halfword
) == FAIL
)
2908 as_warn (_("%s register same as write-back base"),
2909 (inst
.instruction
& LOAD_BIT
) ? _("destination") : _("source") );
2915 inst
.instruction
|= HWOFFSET_IMM
;
2917 skip_whitespace (str
);
2922 as_warn (_("%s register same as write-back base"),
2923 (inst
.instruction
& LOAD_BIT
) ? _("destination") : _("source") );
2925 inst
.instruction
|= WRITE_BACK
;
2929 if (! (flags
& TRANS_BIT
))
2936 if (skip_past_comma (&str
) == FAIL
)
2938 inst
.error
= _("pre-indexed expression expected");
2943 if (ldst_extend (&str
, halfword
) == FAIL
)
2946 skip_whitespace (str
);
2950 inst
.error
= _("missing ]");
2954 skip_whitespace (str
);
2959 as_warn (_("%s register same as write-back base"),
2960 (inst
.instruction
& LOAD_BIT
) ? _("destination") : _("source") );
2962 inst
.instruction
|= WRITE_BACK
;
2966 else if (*str
== '=')
2968 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
2971 skip_whitespace (str
);
2973 if (my_get_expression (&inst
.reloc
.exp
, &str
))
2976 if (inst
.reloc
.exp
.X_op
!= O_constant
2977 && inst
.reloc
.exp
.X_op
!= O_symbol
)
2979 inst
.error
= _("Constant expression expected");
2983 if (inst
.reloc
.exp
.X_op
== O_constant
2984 && (value
= validate_immediate(inst
.reloc
.exp
.X_add_number
)) != FAIL
)
2986 /* This can be done with a mov instruction */
2987 inst
.instruction
&= LITERAL_MASK
;
2988 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
2989 inst
.instruction
|= (flags
& COND_MASK
) | (value
& 0xfff);
2995 /* Insert into literal pool */
2996 if (add_to_lit_pool () == FAIL
)
2999 inst
.error
= _("literal pool insertion failed");
3003 /* Change the instruction exp to point to the pool */
3006 inst
.instruction
|= HWOFFSET_IMM
;
3007 inst
.reloc
.type
= BFD_RELOC_ARM_HWLITERAL
;
3010 inst
.reloc
.type
= BFD_RELOC_ARM_LITERAL
;
3011 inst
.reloc
.pc_rel
= 1;
3012 inst
.instruction
|= (REG_PC
<< 16);
3018 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3023 inst
.instruction
|= HWOFFSET_IMM
;
3024 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
3027 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
3029 inst
.reloc
.exp
.X_add_number
-= 8; /* PC rel adjust */
3031 inst
.reloc
.pc_rel
= 1;
3032 inst
.instruction
|= (REG_PC
<< 16);
3036 if (pre_inc
&& (flags
& TRANS_BIT
))
3037 inst
.error
= _("Pre-increment instruction with translate");
3039 inst
.instruction
|= flags
| (pre_inc
? PRE_INDEX
: 0);
3052 /* We come back here if we get ranges concatenated by '+' or '|' */
3067 skip_whitespace (str
);
3069 if ((reg
= reg_required_here (& str
, -1)) == FAIL
)
3078 inst
.error
= _("Bad range in register list");
3082 for (i
= cur_reg
+ 1; i
< reg
; i
++)
3084 if (range
& (1 << i
))
3086 (_("Warning: Duplicated register (r%d) in register list"),
3094 if (range
& (1 << reg
))
3095 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3097 else if (reg
<= cur_reg
)
3098 as_tsktsk (_("Warning: Register range not in ascending order"));
3102 } while (skip_past_comma (&str
) != FAIL
3103 || (in_range
= 1, *str
++ == '-'));
3105 skip_whitespace (str
);
3109 inst
.error
= _("Missing `}'");
3117 if (my_get_expression (&expr
, &str
))
3120 if (expr
.X_op
== O_constant
)
3122 if (expr
.X_add_number
3123 != (expr
.X_add_number
& 0x0000ffff))
3125 inst
.error
= _("invalid register mask");
3129 if ((range
& expr
.X_add_number
) != 0)
3131 int regno
= range
& expr
.X_add_number
;
3134 regno
= (1 << regno
) - 1;
3136 (_("Warning: Duplicated register (r%d) in register list"),
3140 range
|= expr
.X_add_number
;
3144 if (inst
.reloc
.type
!= 0)
3146 inst
.error
= _("expression too complex");
3150 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
3151 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
3152 inst
.reloc
.pc_rel
= 0;
3156 skip_whitespace (str
);
3158 if (*str
== '|' || *str
== '+')
3163 } while (another_range
);
3170 do_ldmstm (str
, flags
)
3172 unsigned long flags
;
3177 skip_whitespace (str
);
3179 if ((base_reg
= reg_required_here (&str
, 16)) == FAIL
)
3182 if (base_reg
== REG_PC
)
3184 inst
.error
= _("r15 not allowed as base register");
3188 skip_whitespace (str
);
3192 flags
|= WRITE_BACK
;
3196 if (skip_past_comma (&str
) == FAIL
3197 || (range
= reg_list (&str
)) == FAIL
)
3200 inst
.error
= BAD_ARGS
;
3207 flags
|= LDM_TYPE_2_OR_3
;
3210 inst
.instruction
|= flags
| range
;
3218 unsigned long flags
;
3220 skip_whitespace (str
);
3222 /* Allow optional leading '#'. */
3223 if (is_immediate_prefix (*str
))
3226 if (my_get_expression (& inst
.reloc
.exp
, & str
))
3229 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
3230 inst
.reloc
.pc_rel
= 0;
3231 inst
.instruction
|= flags
;
3239 do_swap (str
, flags
)
3241 unsigned long flags
;
3245 skip_whitespace (str
);
3247 if ((reg
= reg_required_here (&str
, 12)) == FAIL
)
3252 inst
.error
= _("r15 not allowed in swap");
3256 if (skip_past_comma (&str
) == FAIL
3257 || (reg
= reg_required_here (&str
, 0)) == FAIL
)
3260 inst
.error
= BAD_ARGS
;
3266 inst
.error
= _("r15 not allowed in swap");
3270 if (skip_past_comma (&str
) == FAIL
3273 inst
.error
= BAD_ARGS
;
3277 skip_whitespace (str
);
3279 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
3284 inst
.error
= BAD_PC
;
3288 skip_whitespace (str
);
3292 inst
.error
= _("missing ]");
3296 inst
.instruction
|= flags
;
3302 do_branch (str
, flags
)
3304 unsigned long flags ATTRIBUTE_UNUSED
;
3306 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3313 /* ScottB: February 5, 1998 */
3314 /* Check to see of PLT32 reloc required for the instruction. */
3316 /* arm_parse_reloc() works on input_line_pointer.
3317 We actually want to parse the operands to the branch instruction
3318 passed in 'str'. Save the input pointer and restore it later. */
3319 save_in
= input_line_pointer
;
3320 input_line_pointer
= str
;
3321 if (inst
.reloc
.exp
.X_op
== O_symbol
3323 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32
)
3325 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
3326 inst
.reloc
.pc_rel
= 0;
3327 /* Modify str to point to after parsed operands, otherwise
3328 end_of_line() will complain about the (PLT) left in str. */
3329 str
= input_line_pointer
;
3333 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BRANCH
;
3334 inst
.reloc
.pc_rel
= 1;
3336 input_line_pointer
= save_in
;
3339 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BRANCH
;
3340 inst
.reloc
.pc_rel
= 1;
3341 #endif /* OBJ_ELF */
3350 unsigned long flags ATTRIBUTE_UNUSED
;
3354 skip_whitespace (str
);
3356 if ((reg
= reg_required_here (&str
, 0)) == FAIL
)
3358 inst
.error
= BAD_ARGS
;
3363 inst
.error
= BAD_PC
;
3371 unsigned long flags ATTRIBUTE_UNUSED
;
3373 /* Co-processor data operation.
3374 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3375 skip_whitespace (str
);
3377 if (co_proc_number (&str
) == FAIL
)
3380 inst
.error
= BAD_ARGS
;
3384 if (skip_past_comma (&str
) == FAIL
3385 || cp_opc_expr (&str
, 20,4) == FAIL
)
3388 inst
.error
= BAD_ARGS
;
3392 if (skip_past_comma (&str
) == FAIL
3393 || cp_reg_required_here (&str
, 12) == FAIL
)
3396 inst
.error
= BAD_ARGS
;
3400 if (skip_past_comma (&str
) == FAIL
3401 || cp_reg_required_here (&str
, 16) == FAIL
)
3404 inst
.error
= BAD_ARGS
;
3408 if (skip_past_comma (&str
) == FAIL
3409 || cp_reg_required_here (&str
, 0) == FAIL
)
3412 inst
.error
= BAD_ARGS
;
3416 if (skip_past_comma (&str
) == SUCCESS
)
3418 if (cp_opc_expr (&str
, 5, 3) == FAIL
)
3421 inst
.error
= BAD_ARGS
;
3431 do_lstc (str
, flags
)
3433 unsigned long flags
;
3435 /* Co-processor register load/store.
3436 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3438 skip_whitespace (str
);
3440 if (co_proc_number (&str
) == FAIL
)
3443 inst
.error
= BAD_ARGS
;
3447 if (skip_past_comma (&str
) == FAIL
3448 || cp_reg_required_here (&str
, 12) == FAIL
)
3451 inst
.error
= BAD_ARGS
;
3455 if (skip_past_comma (&str
) == FAIL
3456 || cp_address_required_here (&str
) == FAIL
)
3459 inst
.error
= BAD_ARGS
;
3463 inst
.instruction
|= flags
;
3469 do_co_reg (str
, flags
)
3471 unsigned long flags
;
3473 /* Co-processor register transfer.
3474 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3476 skip_whitespace (str
);
3478 if (co_proc_number (&str
) == FAIL
)
3481 inst
.error
= BAD_ARGS
;
3485 if (skip_past_comma (&str
) == FAIL
3486 || cp_opc_expr (&str
, 21, 3) == FAIL
)
3489 inst
.error
= BAD_ARGS
;
3493 if (skip_past_comma (&str
) == FAIL
3494 || reg_required_here (&str
, 12) == FAIL
)
3497 inst
.error
= BAD_ARGS
;
3501 if (skip_past_comma (&str
) == FAIL
3502 || cp_reg_required_here (&str
, 16) == FAIL
)
3505 inst
.error
= BAD_ARGS
;
3509 if (skip_past_comma (&str
) == FAIL
3510 || cp_reg_required_here (&str
, 0) == FAIL
)
3513 inst
.error
= BAD_ARGS
;
3517 if (skip_past_comma (&str
) == SUCCESS
)
3519 if (cp_opc_expr (&str
, 5, 3) == FAIL
)
3522 inst
.error
= BAD_ARGS
;
3528 inst
.error
= BAD_COND
;
3536 do_fp_ctrl (str
, flags
)
3538 unsigned long flags ATTRIBUTE_UNUSED
;
3540 /* FP control registers.
3541 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3543 skip_whitespace (str
);
3545 if (reg_required_here (&str
, 12) == FAIL
)
3548 inst
.error
= BAD_ARGS
;
3557 do_fp_ldst (str
, flags
)
3559 unsigned long flags ATTRIBUTE_UNUSED
;
3561 skip_whitespace (str
);
3563 switch (inst
.suffix
)
3568 inst
.instruction
|= CP_T_X
;
3571 inst
.instruction
|= CP_T_Y
;
3574 inst
.instruction
|= CP_T_X
| CP_T_Y
;
3580 if (fp_reg_required_here (&str
, 12) == FAIL
)
3583 inst
.error
= BAD_ARGS
;
3587 if (skip_past_comma (&str
) == FAIL
3588 || cp_address_required_here (&str
) == FAIL
)
3591 inst
.error
= BAD_ARGS
;
3599 do_fp_ldmstm (str
, flags
)
3601 unsigned long flags
;
3605 skip_whitespace (str
);
3607 if (fp_reg_required_here (&str
, 12) == FAIL
)
3610 inst
.error
= BAD_ARGS
;
3614 /* Get Number of registers to transfer */
3615 if (skip_past_comma (&str
) == FAIL
3616 || my_get_expression (&inst
.reloc
.exp
, &str
))
3619 inst
.error
= _("constant expression expected");
3623 if (inst
.reloc
.exp
.X_op
!= O_constant
)
3625 inst
.error
= _("Constant value required for number of registers");
3629 num_regs
= inst
.reloc
.exp
.X_add_number
;
3631 if (num_regs
< 1 || num_regs
> 4)
3633 inst
.error
= _("number of registers must be in the range [1:4]");
3640 inst
.instruction
|= CP_T_X
;
3643 inst
.instruction
|= CP_T_Y
;
3646 inst
.instruction
|= CP_T_Y
| CP_T_X
;
3660 /* The instruction specified "ea" or "fd", so we can only accept
3661 [Rn]{!}. The instruction does not really support stacking or
3662 unstacking, so we have to emulate these by setting appropriate
3663 bits and offsets. */
3664 if (skip_past_comma (&str
) == FAIL
3668 inst
.error
= BAD_ARGS
;
3673 skip_whitespace (str
);
3675 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
3678 skip_whitespace (str
);
3682 inst
.error
= BAD_ARGS
;
3693 inst
.error
= _("R15 not allowed as base register with write-back");
3700 if (flags
& CP_T_Pre
)
3703 offset
= 3 * num_regs
;
3709 /* Post-increment */
3713 offset
= 3 * num_regs
;
3717 /* No write-back, so convert this into a standard pre-increment
3718 instruction -- aesthetically more pleasing. */
3719 flags
= CP_T_Pre
| CP_T_UD
;
3724 inst
.instruction
|= flags
| offset
;
3726 else if (skip_past_comma (&str
) == FAIL
3727 || cp_address_required_here (&str
) == FAIL
)
3730 inst
.error
= BAD_ARGS
;
3738 do_fp_dyadic (str
, flags
)
3740 unsigned long flags
;
3742 skip_whitespace (str
);
3744 switch (inst
.suffix
)
3749 inst
.instruction
|= 0x00000080;
3752 inst
.instruction
|= 0x00080000;
3758 if (fp_reg_required_here (&str
, 12) == FAIL
)
3761 inst
.error
= BAD_ARGS
;
3765 if (skip_past_comma (&str
) == FAIL
3766 || fp_reg_required_here (&str
, 16) == FAIL
)
3769 inst
.error
= BAD_ARGS
;
3773 if (skip_past_comma (&str
) == FAIL
3774 || fp_op2 (&str
) == FAIL
)
3777 inst
.error
= BAD_ARGS
;
3781 inst
.instruction
|= flags
;
3787 do_fp_monadic (str
, flags
)
3789 unsigned long flags
;
3791 skip_whitespace (str
);
3793 switch (inst
.suffix
)
3798 inst
.instruction
|= 0x00000080;
3801 inst
.instruction
|= 0x00080000;
3807 if (fp_reg_required_here (&str
, 12) == FAIL
)
3810 inst
.error
= BAD_ARGS
;
3814 if (skip_past_comma (&str
) == FAIL
3815 || fp_op2 (&str
) == FAIL
)
3818 inst
.error
= BAD_ARGS
;
3822 inst
.instruction
|= flags
;
3828 do_fp_cmp (str
, flags
)
3830 unsigned long flags
;
3832 skip_whitespace (str
);
3834 if (fp_reg_required_here (&str
, 16) == FAIL
)
3837 inst
.error
= BAD_ARGS
;
3841 if (skip_past_comma (&str
) == FAIL
3842 || fp_op2 (&str
) == FAIL
)
3845 inst
.error
= BAD_ARGS
;
3849 inst
.instruction
|= flags
;
3855 do_fp_from_reg (str
, flags
)
3857 unsigned long flags
;
3859 skip_whitespace (str
);
3861 switch (inst
.suffix
)
3866 inst
.instruction
|= 0x00000080;
3869 inst
.instruction
|= 0x00080000;
3875 if (fp_reg_required_here (&str
, 16) == FAIL
)
3878 inst
.error
= BAD_ARGS
;
3882 if (skip_past_comma (&str
) == FAIL
3883 || reg_required_here (&str
, 12) == FAIL
)
3886 inst
.error
= BAD_ARGS
;
3890 inst
.instruction
|= flags
;
3896 do_fp_to_reg (str
, flags
)
3898 unsigned long flags
;
3900 skip_whitespace (str
);
3902 if (reg_required_here (&str
, 12) == FAIL
)
3905 if (skip_past_comma (&str
) == FAIL
3906 || fp_reg_required_here (&str
, 0) == FAIL
)
3909 inst
.error
= BAD_ARGS
;
3913 inst
.instruction
|= flags
;
3918 /* Thumb specific routines */
3920 /* Parse and validate that a register is of the right form, this saves
3921 repeated checking of this information in many similar cases.
3922 Unlike the 32-bit case we do not insert the register into the opcode
3923 here, since the position is often unknown until the full instruction
3926 thumb_reg (strp
, hi_lo
)
3932 if ((reg
= reg_required_here (strp
, -1)) == FAIL
)
3940 inst
.error
= _("lo register required");
3948 inst
.error
= _("hi register required");
3960 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
3963 thumb_add_sub (str
, subtract
)
3967 int Rd
, Rs
, Rn
= FAIL
;
3969 skip_whitespace (str
);
3971 if ((Rd
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
3972 || skip_past_comma (&str
) == FAIL
)
3975 inst
.error
= BAD_ARGS
;
3979 if (is_immediate_prefix (*str
))
3983 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3988 if ((Rs
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
3991 if (skip_past_comma (&str
) == FAIL
)
3993 /* Two operand format, shuffle the registers and pretend there
3998 else if (is_immediate_prefix (*str
))
4001 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4004 else if ((Rn
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4008 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4009 for the latter case, EXPR contains the immediate that was found. */
4012 /* All register format. */
4013 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
4017 inst
.error
= _("dest and source1 must be the same register");
4021 /* Can't do this for SUB */
4024 inst
.error
= _("subtract valid only on lo regs");
4028 inst
.instruction
= (T_OPCODE_ADD_HI
4029 | (Rd
> 7 ? THUMB_H1
: 0)
4030 | (Rn
> 7 ? THUMB_H2
: 0));
4031 inst
.instruction
|= (Rd
& 7) | ((Rn
& 7) << 3);
4035 inst
.instruction
= subtract
? T_OPCODE_SUB_R3
: T_OPCODE_ADD_R3
;
4036 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
4041 /* Immediate expression, now things start to get nasty. */
4043 /* First deal with HI regs, only very restricted cases allowed:
4044 Adjusting SP, and using PC or SP to get an address. */
4045 if ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
4046 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
))
4048 inst
.error
= _("invalid Hi register with immediate");
4052 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4054 /* Value isn't known yet, all we can do is store all the fragments
4055 we know about in the instruction and let the reloc hacking
4057 inst
.instruction
= (subtract
? 0x8000 : 0) | (Rd
<< 4) | Rs
;
4058 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
4062 int offset
= inst
.reloc
.exp
.X_add_number
;
4072 /* Quick check, in case offset is MIN_INT */
4075 inst
.error
= _("immediate value out of range");
4084 if (offset
& ~0x1fc)
4086 inst
.error
= _("invalid immediate value for stack adjust");
4089 inst
.instruction
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
4090 inst
.instruction
|= offset
>> 2;
4092 else if (Rs
== REG_PC
|| Rs
== REG_SP
)
4095 || (offset
& ~0x3fc))
4097 inst
.error
= _("invalid immediate for address calculation");
4100 inst
.instruction
= (Rs
== REG_PC
? T_OPCODE_ADD_PC
4102 inst
.instruction
|= (Rd
<< 8) | (offset
>> 2);
4108 inst
.error
= _("immediate value out of range");
4111 inst
.instruction
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
4112 inst
.instruction
|= (Rd
<< 8) | offset
;
4118 inst
.error
= _("immediate value out of range");
4121 inst
.instruction
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
4122 inst
.instruction
|= Rd
| (Rs
<< 3) | (offset
<< 6);
4131 thumb_shift (str
, shift
)
4135 int Rd
, Rs
, Rn
= FAIL
;
4137 skip_whitespace (str
);
4139 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4140 || skip_past_comma (&str
) == FAIL
)
4143 inst
.error
= BAD_ARGS
;
4147 if (is_immediate_prefix (*str
))
4149 /* Two operand immediate format, set Rs to Rd. */
4152 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4157 if ((Rs
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4160 if (skip_past_comma (&str
) == FAIL
)
4162 /* Two operand format, shuffle the registers and pretend there
4167 else if (is_immediate_prefix (*str
))
4170 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4173 else if ((Rn
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4177 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4178 for the latter case, EXPR contains the immediate that was found. */
4184 inst
.error
= _("source1 and dest must be same register");
4190 case THUMB_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
4191 case THUMB_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
4192 case THUMB_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
4195 inst
.instruction
|= Rd
| (Rn
<< 3);
4201 case THUMB_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
4202 case THUMB_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
4203 case THUMB_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
4206 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4208 /* Value isn't known yet, create a dummy reloc and let reloc
4209 hacking fix it up */
4211 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
4215 unsigned shift_value
= inst
.reloc
.exp
.X_add_number
;
4217 if (shift_value
> 32 || (shift_value
== 32 && shift
== THUMB_LSL
))
4219 inst
.error
= _("Invalid immediate for shift");
4223 /* Shifts of zero are handled by converting to LSL */
4224 if (shift_value
== 0)
4225 inst
.instruction
= T_OPCODE_LSL_I
;
4227 /* Shifts of 32 are encoded as a shift of zero */
4228 if (shift_value
== 32)
4231 inst
.instruction
|= shift_value
<< 6;
4234 inst
.instruction
|= Rd
| (Rs
<< 3);
4241 thumb_mov_compare (str
, move
)
4247 skip_whitespace (str
);
4249 if ((Rd
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
4250 || skip_past_comma (&str
) == FAIL
)
4253 inst
.error
= BAD_ARGS
;
4257 if (is_immediate_prefix (*str
))
4260 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4263 else if ((Rs
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4268 if (Rs
< 8 && Rd
< 8)
4270 if (move
== THUMB_MOVE
)
4271 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4272 since a MOV instruction produces unpredictable results */
4273 inst
.instruction
= T_OPCODE_ADD_I3
;
4275 inst
.instruction
= T_OPCODE_CMP_LR
;
4276 inst
.instruction
|= Rd
| (Rs
<< 3);
4280 if (move
== THUMB_MOVE
)
4281 inst
.instruction
= T_OPCODE_MOV_HR
;
4283 inst
.instruction
= T_OPCODE_CMP_HR
;
4286 inst
.instruction
|= THUMB_H1
;
4289 inst
.instruction
|= THUMB_H2
;
4291 inst
.instruction
|= (Rd
& 7) | ((Rs
& 7) << 3);
4298 inst
.error
= _("only lo regs allowed with immediate");
4302 if (move
== THUMB_MOVE
)
4303 inst
.instruction
= T_OPCODE_MOV_I8
;
4305 inst
.instruction
= T_OPCODE_CMP_I8
;
4307 inst
.instruction
|= Rd
<< 8;
4309 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4310 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
4313 unsigned value
= inst
.reloc
.exp
.X_add_number
;
4317 inst
.error
= _("invalid immediate");
4321 inst
.instruction
|= value
;
4329 thumb_load_store (str
, load_store
, size
)
4334 int Rd
, Rb
, Ro
= FAIL
;
4336 skip_whitespace (str
);
4338 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4339 || skip_past_comma (&str
) == FAIL
)
4342 inst
.error
= BAD_ARGS
;
4349 if ((Rb
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4352 if (skip_past_comma (&str
) != FAIL
)
4354 if (is_immediate_prefix (*str
))
4357 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4360 else if ((Ro
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4365 inst
.reloc
.exp
.X_op
= O_constant
;
4366 inst
.reloc
.exp
.X_add_number
= 0;
4371 inst
.error
= _("expected ']'");
4376 else if (*str
== '=')
4378 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
4381 skip_whitespace (str
);
4383 if (my_get_expression (& inst
.reloc
.exp
, & str
))
4388 if ( inst
.reloc
.exp
.X_op
!= O_constant
4389 && inst
.reloc
.exp
.X_op
!= O_symbol
)
4391 inst
.error
= "Constant expression expected";
4395 if (inst
.reloc
.exp
.X_op
== O_constant
4396 && ((inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0))
4398 /* This can be done with a mov instruction */
4400 inst
.instruction
= T_OPCODE_MOV_I8
| (Rd
<< 8);
4401 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
4405 /* Insert into literal pool */
4406 if (add_to_lit_pool () == FAIL
)
4409 inst
.error
= "literal pool insertion failed";
4413 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4414 inst
.reloc
.pc_rel
= 1;
4415 inst
.instruction
= T_OPCODE_LDR_PC
| (Rd
<< 8);
4416 inst
.reloc
.exp
.X_add_number
+= 4; /* Adjust ARM pipeline offset to Thumb */
4422 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4425 inst
.instruction
= T_OPCODE_LDR_PC
| (Rd
<< 8);
4426 inst
.reloc
.pc_rel
= 1;
4427 inst
.reloc
.exp
.X_add_number
-= 4; /* Pipeline offset */
4428 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4433 if (Rb
== REG_PC
|| Rb
== REG_SP
)
4435 if (size
!= THUMB_WORD
)
4437 inst
.error
= _("byte or halfword not valid for base register");
4440 else if (Rb
== REG_PC
&& load_store
!= THUMB_LOAD
)
4442 inst
.error
= _("R15 based store not allowed");
4445 else if (Ro
!= FAIL
)
4447 inst
.error
= _("Invalid base register for register offset");
4452 inst
.instruction
= T_OPCODE_LDR_PC
;
4453 else if (load_store
== THUMB_LOAD
)
4454 inst
.instruction
= T_OPCODE_LDR_SP
;
4456 inst
.instruction
= T_OPCODE_STR_SP
;
4458 inst
.instruction
|= Rd
<< 8;
4459 if (inst
.reloc
.exp
.X_op
== O_constant
)
4461 unsigned offset
= inst
.reloc
.exp
.X_add_number
;
4463 if (offset
& ~0x3fc)
4465 inst
.error
= _("invalid offset");
4469 inst
.instruction
|= offset
>> 2;
4472 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4476 inst
.error
= _("invalid base register in load/store");
4479 else if (Ro
== FAIL
)
4481 /* Immediate offset */
4482 if (size
== THUMB_WORD
)
4483 inst
.instruction
= (load_store
== THUMB_LOAD
4484 ? T_OPCODE_LDR_IW
: T_OPCODE_STR_IW
);
4485 else if (size
== THUMB_HALFWORD
)
4486 inst
.instruction
= (load_store
== THUMB_LOAD
4487 ? T_OPCODE_LDR_IH
: T_OPCODE_STR_IH
);
4489 inst
.instruction
= (load_store
== THUMB_LOAD
4490 ? T_OPCODE_LDR_IB
: T_OPCODE_STR_IB
);
4492 inst
.instruction
|= Rd
| (Rb
<< 3);
4494 if (inst
.reloc
.exp
.X_op
== O_constant
)
4496 unsigned offset
= inst
.reloc
.exp
.X_add_number
;
4498 if (offset
& ~(0x1f << size
))
4500 inst
.error
= _("Invalid offset");
4503 inst
.instruction
|= (offset
>> size
) << 6;
4506 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4510 /* Register offset */
4511 if (size
== THUMB_WORD
)
4512 inst
.instruction
= (load_store
== THUMB_LOAD
4513 ? T_OPCODE_LDR_RW
: T_OPCODE_STR_RW
);
4514 else if (size
== THUMB_HALFWORD
)
4515 inst
.instruction
= (load_store
== THUMB_LOAD
4516 ? T_OPCODE_LDR_RH
: T_OPCODE_STR_RH
);
4518 inst
.instruction
= (load_store
== THUMB_LOAD
4519 ? T_OPCODE_LDR_RB
: T_OPCODE_STR_RB
);
4521 inst
.instruction
|= Rd
| (Rb
<< 3) | (Ro
<< 6);
4536 /* Handle the Format 4 instructions that do not have equivalents in other
4537 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4545 skip_whitespace (str
);
4547 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4548 || skip_past_comma (&str
) == FAIL
4549 || (Rs
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4551 inst
.error
= BAD_ARGS
;
4555 if (skip_past_comma (&str
) != FAIL
)
4557 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4558 (It isn't allowed for CMP either, but that isn't handled by this
4560 if (inst
.instruction
== T_OPCODE_TST
4561 || inst
.instruction
== T_OPCODE_CMN
4562 || inst
.instruction
== T_OPCODE_NEG
4563 || inst
.instruction
== T_OPCODE_MVN
)
4565 inst
.error
= BAD_ARGS
;
4569 if ((Rn
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4574 inst
.error
= _("dest and source1 one must be the same register");
4580 if (inst
.instruction
== T_OPCODE_MUL
4582 as_tsktsk (_("Rs and Rd must be different in MUL"));
4584 inst
.instruction
|= Rd
| (Rs
<< 3);
4592 thumb_add_sub (str
, 0);
4599 thumb_shift (str
, THUMB_ASR
);
4606 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4608 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
4609 inst
.reloc
.pc_rel
= 1;
4617 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4619 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
4620 inst
.reloc
.pc_rel
= 1;
4624 /* Find the real, Thumb encoded start of a Thumb function. */
4627 find_real_start (symbolP
)
4631 const char * name
= S_GET_NAME (symbolP
);
4632 symbolS
* new_target
;
4634 /* This definiton must agree with the one in gcc/config/arm/thumb.c */
4635 #define STUB_NAME ".real_start_of"
4640 /* Names that start with '.' are local labels, not function entry points.
4641 The compiler may generate BL instructions to these labels because it
4642 needs to perform a branch to a far away location. */
4646 real_start
= malloc (strlen (name
) + strlen (STUB_NAME
) + 1);
4647 sprintf (real_start
, "%s%s", STUB_NAME
, name
);
4649 new_target
= symbol_find (real_start
);
4651 if (new_target
== NULL
)
4653 as_warn ("Failed to find real start of function: %s\n", name
);
4654 new_target
= symbolP
;
4667 if (my_get_expression (& inst
.reloc
.exp
, & str
))
4670 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
4671 inst
.reloc
.pc_rel
= 1;
4674 /* If the destination of the branch is a defined symbol which does not have
4675 the THUMB_FUNC attribute, then we must be calling a function which has
4676 the (interfacearm) attribute. We look for the Thumb entry point to that
4677 function and change the branch to refer to that function instead. */
4678 if ( inst
.reloc
.exp
.X_op
== O_symbol
4679 && inst
.reloc
.exp
.X_add_symbol
!= NULL
4680 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
4681 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
4682 inst
.reloc
.exp
.X_add_symbol
= find_real_start (inst
.reloc
.exp
.X_add_symbol
);
4691 skip_whitespace (str
);
4693 if ((reg
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4696 /* This sets THUMB_H2 from the top bit of reg. */
4697 inst
.instruction
|= reg
<< 3;
4699 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4700 should cause the alignment to be checked once it is known. This is
4701 because BX PC only works if the instruction is word aligned. */
4710 thumb_mov_compare (str
, THUMB_COMPARE
);
4720 skip_whitespace (str
);
4722 if ((Rb
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4726 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4730 if (skip_past_comma (&str
) == FAIL
4731 || (range
= reg_list (&str
)) == FAIL
)
4734 inst
.error
= BAD_ARGS
;
4738 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
4740 /* This really doesn't seem worth it. */
4741 inst
.reloc
.type
= BFD_RELOC_NONE
;
4742 inst
.error
= _("Expression too complex");
4748 inst
.error
= _("only lo-regs valid in load/store multiple");
4752 inst
.instruction
|= (Rb
<< 8) | range
;
4760 thumb_load_store (str
, THUMB_LOAD
, THUMB_WORD
);
4767 thumb_load_store (str
, THUMB_LOAD
, THUMB_BYTE
);
4774 thumb_load_store (str
, THUMB_LOAD
, THUMB_HALFWORD
);
4783 skip_whitespace (str
);
4785 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4786 || skip_past_comma (&str
) == FAIL
4788 || (Rb
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4789 || skip_past_comma (&str
) == FAIL
4790 || (Ro
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4794 inst
.error
= _("Syntax: ldrs[b] Rd, [Rb, Ro]");
4798 inst
.instruction
|= Rd
| (Rb
<< 3) | (Ro
<< 6);
4806 thumb_shift (str
, THUMB_LSL
);
4813 thumb_shift (str
, THUMB_LSR
);
4820 thumb_mov_compare (str
, THUMB_MOVE
);
4829 skip_whitespace (str
);
4831 if ((range
= reg_list (&str
)) == FAIL
)
4834 inst
.error
= BAD_ARGS
;
4838 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
4840 /* This really doesn't seem worth it. */
4841 inst
.reloc
.type
= BFD_RELOC_NONE
;
4842 inst
.error
= _("Expression too complex");
4848 if ((inst
.instruction
== T_OPCODE_PUSH
4849 && (range
& ~0xff) == 1 << REG_LR
)
4850 || (inst
.instruction
== T_OPCODE_POP
4851 && (range
& ~0xff) == 1 << REG_PC
))
4853 inst
.instruction
|= THUMB_PP_PC_LR
;
4858 inst
.error
= _("invalid register list to push/pop instruction");
4863 inst
.instruction
|= range
;
4871 thumb_load_store (str
, THUMB_STORE
, THUMB_WORD
);
4878 thumb_load_store (str
, THUMB_STORE
, THUMB_BYTE
);
4885 thumb_load_store (str
, THUMB_STORE
, THUMB_HALFWORD
);
4892 thumb_add_sub (str
, 1);
4899 skip_whitespace (str
);
4901 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4904 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
4913 /* This is a pseudo-op of the form "adr rd, label" to be converted
4914 into a relative address of the form "add rd, pc, #label-.-4" */
4915 skip_whitespace (str
);
4917 if (reg_required_here (&str
, 4) == FAIL
/* Store Rd in temporary location inside instruction. */
4918 || skip_past_comma (&str
) == FAIL
4919 || my_get_expression (&inst
.reloc
.exp
, &str
))
4922 inst
.error
= BAD_ARGS
;
4926 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
4927 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust */
4928 inst
.reloc
.pc_rel
= 1;
4929 inst
.instruction
|= REG_PC
; /* Rd is already placed into the instruction */
4937 int len
= strlen (reg_table
[entry
].name
) + 2;
4938 char * buf
= (char *) xmalloc (len
);
4939 char * buf2
= (char *) xmalloc (len
);
4942 #ifdef REGISTER_PREFIX
4943 buf
[i
++] = REGISTER_PREFIX
;
4946 strcpy (buf
+ i
, reg_table
[entry
].name
);
4948 for (i
= 0; buf
[i
]; i
++)
4949 buf2
[i
] = islower (buf
[i
]) ? toupper (buf
[i
]) : buf
[i
];
4953 hash_insert (arm_reg_hsh
, buf
, (PTR
) ®_table
[entry
]);
4954 hash_insert (arm_reg_hsh
, buf2
, (PTR
) ®_table
[entry
]);
4958 insert_reg_alias (str
, regnum
)
4962 struct reg_entry
*new =
4963 (struct reg_entry
*)xmalloc (sizeof (struct reg_entry
));
4964 char *name
= xmalloc (strlen (str
) + 1);
4968 new->number
= regnum
;
4970 hash_insert (arm_reg_hsh
, name
, (PTR
) new);
4974 set_constant_flonums ()
4978 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4979 if (atof_ieee ((char *)fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
4988 if ( (arm_ops_hsh
= hash_new ()) == NULL
4989 || (arm_tops_hsh
= hash_new ()) == NULL
4990 || (arm_cond_hsh
= hash_new ()) == NULL
4991 || (arm_shift_hsh
= hash_new ()) == NULL
4992 || (arm_reg_hsh
= hash_new ()) == NULL
4993 || (arm_psr_hsh
= hash_new ()) == NULL
)
4994 as_fatal (_("Virtual memory exhausted"));
4996 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
4997 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
4998 for (i
= 0; i
< sizeof (tinsns
) / sizeof (struct thumb_opcode
); i
++)
4999 hash_insert (arm_tops_hsh
, tinsns
[i
].template, (PTR
) (tinsns
+ i
));
5000 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
5001 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
5002 for (i
= 0; i
< sizeof (shift
) / sizeof (struct asm_shift
); i
++)
5003 hash_insert (arm_shift_hsh
, shift
[i
].template, (PTR
) (shift
+ i
));
5004 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
5005 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
5007 for (i
= 0; reg_table
[i
].name
; i
++)
5010 set_constant_flonums ();
5012 #if defined OBJ_COFF || defined OBJ_ELF
5014 unsigned int flags
= 0;
5016 /* Set the flags in the private structure */
5017 if (uses_apcs_26
) flags
|= F_APCS26
;
5018 if (support_interwork
) flags
|= F_INTERWORK
;
5019 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
5020 if (pic_code
) flags
|= F_PIC
;
5021 if ((cpu_variant
& FPU_ALL
) == FPU_NONE
) flags
|= F_SOFT_FLOAT
;
5023 bfd_set_private_flags (stdoutput
, flags
);
5030 /* Record the CPU type as well */
5031 switch (cpu_variant
& ARM_CPU_MASK
)
5034 mach
= bfd_mach_arm_2
;
5037 case ARM_3
: /* also ARM_250 */
5038 mach
= bfd_mach_arm_2a
;
5042 case ARM_6
| ARM_3
| ARM_2
: /* Actually no CPU type defined */
5043 mach
= bfd_mach_arm_4
;
5046 case ARM_7
: /* also ARM_6 */
5047 mach
= bfd_mach_arm_3
;
5051 /* Catch special cases. */
5052 if (cpu_variant
!= (FPU_DEFAULT
| CPU_DEFAULT
))
5054 if (cpu_variant
& (ARM_EXT_V5
& ARM_THUMB
))
5055 mach
= bfd_mach_arm_5T
;
5056 else if (cpu_variant
& ARM_EXT_V5
)
5057 mach
= bfd_mach_arm_5
;
5058 else if (cpu_variant
& ARM_THUMB
)
5059 mach
= bfd_mach_arm_4T
;
5060 else if ((cpu_variant
& ARM_ARCH_V4
) == ARM_ARCH_V4
)
5061 mach
= bfd_mach_arm_4
;
5062 else if (cpu_variant
& ARM_LONGMUL
)
5063 mach
= bfd_mach_arm_3M
;
5066 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
5070 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5071 for use in the a.out file, and stores them in the array pointed to by buf.
5072 This knows about the endian-ness of the target machine and does
5073 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5074 2 (short) and 4 (long) Floating numbers are put out as a series of
5075 LITTLENUMS (shorts, here at least). */
5077 md_number_to_chars (buf
, val
, n
)
5082 if (target_big_endian
)
5083 number_to_chars_bigendian (buf
, val
, n
);
5085 number_to_chars_littleendian (buf
, val
, n
);
5089 md_chars_to_number (buf
, n
)
5094 unsigned char * where
= (unsigned char *) buf
;
5096 if (target_big_endian
)
5101 result
|= (*where
++ & 255);
5109 result
|= (where
[n
] & 255);
5116 /* Turn a string in input_line_pointer into a floating point constant
5117 of type TYPE, and store the appropriate bytes in *litP. The number
5118 of LITTLENUMS emitted is stored in *sizeP . An error message is
5119 returned, or NULL on OK.
5121 Note that fp constants aren't represent in the normal way on the ARM.
5122 In big endian mode, things are as expected. However, in little endian
5123 mode fp constants are big-endian word-wise, and little-endian byte-wise
5124 within the words. For example, (double) 1.1 in big endian mode is
5125 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5126 the byte sequence 99 99 f1 3f 9a 99 99 99.
5128 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5131 md_atof (type
, litP
, sizeP
)
5137 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5169 return _("Bad call to MD_ATOF()");
5172 t
= atof_ieee (input_line_pointer
, type
, words
);
5174 input_line_pointer
= t
;
5177 if (target_big_endian
)
5179 for (i
= 0; i
< prec
; i
++)
5181 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5187 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5188 8 byte float the order is 1 0 3 2. */
5189 for (i
= 0; i
< prec
; i
+= 2)
5191 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
5192 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
5200 /* The knowledge of the PC's pipeline offset is built into the insns themselves. */
5202 md_pcrel_from (fixP
)
5206 && S_GET_SEGMENT (fixP
->fx_addsy
) == undefined_section
5207 && fixP
->fx_subsy
== NULL
)
5210 if (fixP
->fx_pcrel
&& (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_ADD
))
5212 /* PC relative addressing on the Thumb is slightly odd
5213 as the bottom two bits of the PC are forced to zero
5214 for the calculation. */
5215 return (fixP
->fx_where
+ fixP
->fx_frag
->fr_address
) & ~3;
5219 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
5220 so we un-adjust here to compensate for the accomodation. */
5221 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
+ 8;
5223 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5227 /* Round up a section size to the appropriate boundary. */
5229 md_section_align (segment
, size
)
5230 segT segment ATTRIBUTE_UNUSED
;
5236 /* Round all sects to multiple of 4 */
5237 return (size
+ 3) & ~3;
5241 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. Otherwise
5242 we have no need to default values of symbols. */
5246 md_undefined_symbol (name
)
5250 if (name
[0] == '_' && name
[1] == 'G'
5251 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
5255 if (symbol_find (name
))
5256 as_bad ("GOT already in the symbol table");
5258 GOT_symbol
= symbol_new (name
, undefined_section
,
5259 (valueT
)0, & zero_address_frag
);
5269 /* arm_reg_parse () := if it looks like a register, return its token and
5270 advance the pointer. */
5274 register char ** ccp
;
5276 char * start
= * ccp
;
5279 struct reg_entry
* reg
;
5281 #ifdef REGISTER_PREFIX
5282 if (*start
!= REGISTER_PREFIX
)
5287 #ifdef OPTIONAL_REGISTER_PREFIX
5288 if (*p
== OPTIONAL_REGISTER_PREFIX
)
5292 if (!isalpha (*p
) || !is_name_beginner (*p
))
5296 while (isalpha (c
) || isdigit (c
) || c
== '_')
5300 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, start
);
5314 register char ** ccp
;
5316 char * start
= * ccp
;
5319 CONST
struct asm_psr
* psr
;
5323 while (isalpha (c
) || c
== '_')
5327 psr
= (CONST
struct asm_psr
*) hash_find (arm_psr_hsh
, start
);
5340 md_apply_fix3 (fixP
, val
, seg
)
5345 offsetT value
= * val
;
5347 unsigned int newimm
;
5350 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5351 arm_fix_data
* arm_data
= (arm_fix_data
*) fixP
->tc_fix_data
;
5353 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
5355 /* Note whether this will delete the relocation. */
5356 #if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
5357 if ((fixP
->fx_addsy
== 0 || symbol_constant_p (fixP
->fx_addsy
))
5360 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
5364 /* If this symbol is in a different section then we need to leave it for
5365 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5366 so we have to undo it's effects here. */
5369 if (fixP
->fx_addsy
!= NULL
5370 && S_IS_DEFINED (fixP
->fx_addsy
)
5371 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
5374 && (fixP
->fx_r_type
== BFD_RELOC_ARM_PCREL_BRANCH
5378 value
+= md_pcrel_from (fixP
);
5382 fixP
->fx_addnumber
= value
; /* Remember value for emit_reloc. */
5384 switch (fixP
->fx_r_type
)
5386 case BFD_RELOC_ARM_IMMEDIATE
:
5387 newimm
= validate_immediate (value
);
5388 temp
= md_chars_to_number (buf
, INSN_SIZE
);
5390 /* If the instruction will fail, see if we can fix things up by
5391 changing the opcode. */
5392 if (newimm
== (unsigned int) FAIL
5393 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
5395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5396 _("invalid constant (%lx) after fixup"),
5397 (unsigned long) value
);
5401 newimm
|= (temp
& 0xfffff000);
5402 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
5405 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
5407 unsigned int highpart
= 0;
5408 unsigned int newinsn
= 0xe1a00000; /* nop */
5409 newimm
= validate_immediate (value
);
5410 temp
= md_chars_to_number (buf
, INSN_SIZE
);
5412 /* If the instruction will fail, see if we can fix things up by
5413 changing the opcode. */
5414 if (newimm
== (unsigned int) FAIL
5415 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
5417 /* No ? OK - try using two ADD instructions to generate the value. */
5418 newimm
= validate_immediate_twopart (value
, & highpart
);
5420 /* Yes - then make sure that the second instruction is also an add. */
5421 if (newimm
!= (unsigned int) FAIL
)
5423 /* Still No ? Try using a negated value. */
5424 else if (validate_immediate_twopart (- value
, & highpart
) != (unsigned int) FAIL
)
5425 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
5426 /* Otherwise - give up. */
5429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5430 _("Unable to compute ADRL instructions for PC offset of 0x%x"), value
);
5434 /* Replace the first operand in the 2nd instruction (which is the PC)
5435 with the destination register. We have already added in the PC in the
5436 first instruction and we do not want to do it again. */
5437 newinsn
&= ~ 0xf0000;
5438 newinsn
|= ((newinsn
& 0x0f000) << 4);
5441 newimm
|= (temp
& 0xfffff000);
5442 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
5444 highpart
|= (newinsn
& 0xfffff000);
5445 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
5449 case BFD_RELOC_ARM_OFFSET_IMM
:
5455 if (validate_offset_imm (value
, 0) == FAIL
)
5457 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5458 _("bad immediate value for offset (%ld)"), (long) value
);
5462 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5463 newval
&= 0xff7ff000;
5464 newval
|= value
| (sign
? INDEX_UP
: 0);
5465 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5468 case BFD_RELOC_ARM_OFFSET_IMM8
:
5469 case BFD_RELOC_ARM_HWLITERAL
:
5475 if (validate_offset_imm (value
, 1) == FAIL
)
5477 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
5478 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5479 _("invalid literal constant: pool needs to be closer"));
5481 as_bad (_("bad immediate value for half-word offset (%ld)"),
5486 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5487 newval
&= 0xff7ff0f0;
5488 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
5489 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5492 case BFD_RELOC_ARM_LITERAL
:
5498 if (validate_offset_imm (value
, 0) == FAIL
)
5500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5501 _("invalid literal constant: pool needs to be closer"));
5505 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5506 newval
&= 0xff7ff000;
5507 newval
|= value
| (sign
? INDEX_UP
: 0);
5508 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5511 case BFD_RELOC_ARM_SHIFT_IMM
:
5512 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5513 if (((unsigned long) value
) > 32
5515 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
5517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5518 _("shift expression is too large"));
5523 newval
&= ~0x60; /* Shifts of zero must be done as lsl */
5524 else if (value
== 32)
5526 newval
&= 0xfffff07f;
5527 newval
|= (value
& 0x1f) << 7;
5528 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5531 case BFD_RELOC_ARM_SWI
:
5532 if (arm_data
->thumb_mode
)
5534 if (((unsigned long) value
) > 0xff)
5535 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5536 _("Invalid swi expression"));
5537 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xff00;
5539 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5543 if (((unsigned long) value
) > 0x00ffffff)
5544 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5545 _("Invalid swi expression"));
5546 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff000000;
5548 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5552 case BFD_RELOC_ARM_MULTI
:
5553 if (((unsigned long) value
) > 0xffff)
5554 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5555 _("Invalid expression in load/store multiple"));
5556 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
5557 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5560 case BFD_RELOC_ARM_PCREL_BRANCH
:
5561 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5563 /* Sign-extend a 24-bit number. */
5564 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
5568 value
= fixP
->fx_offset
;
5571 /* We are going to store value (shifted right by two) in the
5572 instruction, in a 24 bit, signed field. Thus we need to check
5573 that none of the top 8 bits of the shifted value (top 7 bits of
5574 the unshifted, unsigned value) are set, or that they are all set. */
5575 if ((value
& 0xfe000000UL
) != 0
5576 && ((value
& 0xfe000000UL
) != 0xfe000000UL
))
5579 /* Normally we would be stuck at this point, since we cannot store
5580 the absolute address that is the destination of the branch in the
5581 24 bits of the branch instruction. If however, we happen to know
5582 that the destination of the branch is in the same section as the
5583 branch instruciton itself, then we can compute the relocation for
5584 ourselves and not have to bother the linker with it.
5586 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
5587 because I have not worked out how to do this for OBJ_COFF or
5590 && fixP
->fx_addsy
!= NULL
5591 && S_IS_DEFINED (fixP
->fx_addsy
)
5592 && S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
5594 /* Get pc relative value to go into the branch. */
5597 /* Permit a backward branch provided that enough bits are set.
5598 Allow a forwards branch, provided that enough bits are clear. */
5599 if ((value
& 0xfe000000UL
) == 0xfe000000UL
5600 || (value
& 0xfe000000UL
) == 0)
5604 if (! fixP
->fx_done
)
5606 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5607 _("gas can't handle same-section branch dest >= 0x04000000"));
5611 value
+= SEXT24 (newval
);
5613 if ((value
& 0xff000000UL
) != 0
5614 && (fixP
->fx_done
== 0
5615 || ((value
& 0xff000000UL
) != 0xff000000UL
)))
5616 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5617 _("out of range branch"));
5619 newval
= (value
& 0x00ffffff) | (newval
& 0xff000000);
5620 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5624 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* conditional branch */
5625 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5627 addressT diff
= (newval
& 0xff) << 1;
5632 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
5633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5634 _("Branch out of range"));
5635 newval
= (newval
& 0xff00) | ((value
& 0x1ff) >> 1);
5637 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5640 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* unconditional branch */
5641 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5643 addressT diff
= (newval
& 0x7ff) << 1;
5648 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
5649 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5650 _("Branch out of range"));
5651 newval
= (newval
& 0xf800) | ((value
& 0xfff) >> 1);
5653 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5656 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
5661 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5662 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
5663 diff
= ((newval
& 0x7ff) << 12) | ((newval2
& 0x7ff) << 1);
5664 if (diff
& 0x400000)
5667 value
= fixP
->fx_offset
;
5670 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
5671 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5672 _("Branch with link out of range"));
5674 newval
= (newval
& 0xf800) | ((value
& 0x7fffff) >> 12);
5675 newval2
= (newval2
& 0xf800) | ((value
& 0xfff) >> 1);
5676 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5677 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
5682 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
5683 md_number_to_chars (buf
, value
, 1);
5685 else if (!target_oabi
)
5687 value
= fixP
->fx_offset
;
5688 md_number_to_chars (buf
, value
, 1);
5694 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
5695 md_number_to_chars (buf
, value
, 2);
5697 else if (!target_oabi
)
5699 value
= fixP
->fx_offset
;
5700 md_number_to_chars (buf
, value
, 2);
5706 case BFD_RELOC_ARM_GOT32
:
5707 case BFD_RELOC_ARM_GOTOFF
:
5708 md_number_to_chars (buf
, 0, 4);
5714 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
5715 md_number_to_chars (buf
, value
, 4);
5717 else if (!target_oabi
)
5719 value
= fixP
->fx_offset
;
5720 md_number_to_chars (buf
, value
, 4);
5726 case BFD_RELOC_ARM_PLT32
:
5727 /* It appears the instruction is fully prepared at this point. */
5731 case BFD_RELOC_ARM_GOTPC
:
5732 md_number_to_chars (buf
, value
, 4);
5735 case BFD_RELOC_ARM_CP_OFF_IMM
:
5737 if (value
< -1023 || value
> 1023 || (value
& 3))
5738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5739 _("Illegal value for co-processor offset"));
5742 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff7fff00;
5743 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
5744 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5747 case BFD_RELOC_ARM_THUMB_OFFSET
:
5748 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5749 /* Exactly what ranges, and where the offset is inserted depends on
5750 the type of instruction, we can establish this from the top 4 bits */
5751 switch (newval
>> 12)
5753 case 4: /* PC load */
5754 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5755 forced to zero for these loads, so we will need to round
5756 up the offset if the instruction address is not word
5757 aligned (since the final address produced must be, and
5758 we can only describe word-aligned immediate offsets). */
5760 if ((fixP
->fx_frag
->fr_address
+ fixP
->fx_where
+ value
) & 3)
5761 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5762 _("Invalid offset, target not word aligned (0x%08X)"),
5763 (unsigned int)(fixP
->fx_frag
->fr_address
+ fixP
->fx_where
+ value
));
5765 if ((value
+ 2) & ~0x3fe)
5766 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5767 _("Invalid offset, value too big (0x%08X)"), value
);
5769 /* Round up, since pc will be rounded down. */
5770 newval
|= (value
+ 2) >> 2;
5773 case 9: /* SP load/store */
5775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5776 _("Invalid offset, value too big (0x%08X)"), value
);
5777 newval
|= value
>> 2;
5780 case 6: /* Word load/store */
5782 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5783 _("Invalid offset, value too big (0x%08X)"), value
);
5784 newval
|= value
<< 4; /* 6 - 2 */
5787 case 7: /* Byte load/store */
5789 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5790 _("Invalid offset, value too big (0x%08X)"), value
);
5791 newval
|= value
<< 6;
5794 case 8: /* Halfword load/store */
5796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5797 _("Invalid offset, value too big (0x%08X)"), value
);
5798 newval
|= value
<< 5; /* 6 - 1 */
5802 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5803 "Unable to process relocation for thumb opcode: %lx",
5804 (unsigned long) newval
);
5807 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5810 case BFD_RELOC_ARM_THUMB_ADD
:
5811 /* This is a complicated relocation, since we use it for all of
5812 the following immediate relocations:
5815 9bit ADD/SUB SP word-aligned
5816 10bit ADD PC/SP word-aligned
5818 The type of instruction being processed is encoded in the
5824 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5826 int rd
= (newval
>> 4) & 0xf;
5827 int rs
= newval
& 0xf;
5828 int subtract
= newval
& 0x8000;
5833 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5834 _("Invalid immediate for stack address calculation"));
5835 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
5836 newval
|= value
>> 2;
5838 else if (rs
== REG_PC
|| rs
== REG_SP
)
5842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5843 _("Invalid immediate for address calculation (value = 0x%08lX)"),
5844 (unsigned long) value
);
5845 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
5847 newval
|= value
>> 2;
5852 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5853 _("Invalid 8bit immediate"));
5854 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
5855 newval
|= (rd
<< 8) | value
;
5860 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5861 _("Invalid 3bit immediate"));
5862 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
5863 newval
|= rd
| (rs
<< 3) | (value
<< 6);
5866 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5869 case BFD_RELOC_ARM_THUMB_IMM
:
5870 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5871 switch (newval
>> 11)
5873 case 0x04: /* 8bit immediate MOV */
5874 case 0x05: /* 8bit immediate CMP */
5875 if (value
< 0 || value
> 255)
5876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5877 _("Invalid immediate: %ld is too large"),
5885 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5888 case BFD_RELOC_ARM_THUMB_SHIFT
:
5889 /* 5bit shift value (0..31) */
5890 if (value
< 0 || value
> 31)
5891 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5892 _("Illegal Thumb shift value: %ld"), (long) value
);
5893 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf03f;
5894 newval
|= value
<< 6;
5895 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5898 case BFD_RELOC_VTABLE_INHERIT
:
5899 case BFD_RELOC_VTABLE_ENTRY
:
5903 case BFD_RELOC_NONE
:
5905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5906 _("Bad relocation fixup type (%d)"), fixP
->fx_r_type
);
5912 /* Translate internal representation of relocation info to BFD target
5915 tc_gen_reloc (section
, fixp
)
5916 asection
* section ATTRIBUTE_UNUSED
;
5920 bfd_reloc_code_real_type code
;
5922 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5924 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5925 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5926 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5928 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
5930 if (fixp
->fx_pcrel
== 0)
5931 reloc
->addend
= fixp
->fx_offset
;
5933 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
5935 reloc
->addend
= fixp
->fx_offset
;
5938 switch (fixp
->fx_r_type
)
5943 code
= BFD_RELOC_8_PCREL
;
5950 code
= BFD_RELOC_16_PCREL
;
5957 code
= BFD_RELOC_32_PCREL
;
5961 case BFD_RELOC_ARM_PCREL_BRANCH
:
5963 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
5964 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
5965 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
5966 case BFD_RELOC_VTABLE_ENTRY
:
5967 case BFD_RELOC_VTABLE_INHERIT
:
5968 code
= fixp
->fx_r_type
;
5971 case BFD_RELOC_ARM_LITERAL
:
5972 case BFD_RELOC_ARM_HWLITERAL
:
5973 /* If this is called then the a literal has been referenced across
5974 a section boundary - possibly due to an implicit dump */
5975 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5976 _("Literal referenced across section boundary (Implicit dump?)"));
5980 case BFD_RELOC_ARM_GOT32
:
5981 case BFD_RELOC_ARM_GOTOFF
:
5982 case BFD_RELOC_ARM_PLT32
:
5983 code
= fixp
->fx_r_type
;
5987 case BFD_RELOC_ARM_IMMEDIATE
:
5988 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5989 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
5993 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
5994 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5995 _("ADRL used for a symbol not defined in the same file"),
5999 case BFD_RELOC_ARM_OFFSET_IMM
:
6000 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6001 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
6008 switch (fixp
->fx_r_type
)
6010 case BFD_RELOC_ARM_IMMEDIATE
: type
= "IMMEDIATE"; break;
6011 case BFD_RELOC_ARM_OFFSET_IMM
: type
= "OFFSET_IMM"; break;
6012 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
6013 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
6014 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
6015 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
6016 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
6017 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
6018 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
6019 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
6020 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
6021 default: type
= _("<unknown>"); break;
6023 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6024 _("Can not represent %s relocation in this object file format (%d)"),
6025 type
, fixp
->fx_pcrel
);
6031 if (code
== BFD_RELOC_32_PCREL
6033 && fixp
->fx_addsy
== GOT_symbol
)
6035 code
= BFD_RELOC_ARM_GOTPC
;
6036 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
6040 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6042 if (reloc
->howto
== NULL
)
6044 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6045 _("Can not represent %s relocation in this object file format"),
6046 bfd_get_reloc_code_name (code
));
6050 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
6051 vtable entry to be used in the relocation's section offset. */
6052 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6053 reloc
->address
= fixp
->fx_offset
;
6059 md_estimate_size_before_relax (fragP
, segtype
)
6060 fragS
* fragP ATTRIBUTE_UNUSED
;
6061 segT segtype ATTRIBUTE_UNUSED
;
6063 as_fatal (_("md_estimate_size_before_relax\n"));
6068 output_inst
PARAMS ((void))
6074 as_bad (inst
.error
);
6078 to
= frag_more (inst
.size
);
6080 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
6082 assert (inst
.size
== (2 * THUMB_SIZE
));
6083 md_number_to_chars (to
, inst
.instruction
>> 16, THUMB_SIZE
);
6084 md_number_to_chars (to
+ THUMB_SIZE
, inst
.instruction
, THUMB_SIZE
);
6086 else if (inst
.size
> INSN_SIZE
)
6088 assert (inst
.size
== (2 * INSN_SIZE
));
6089 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
6090 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
6093 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
6095 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
6096 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
6097 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
6112 /* Align the instruction.
6113 This may not be the right thing to do but ... */
6114 /* arm_align (2, 0); */
6115 listing_prev_line (); /* Defined in listing.h */
6117 /* Align the previous label if needed. */
6118 if (last_label_seen
!= NULL
)
6120 symbol_set_frag (last_label_seen
, frag_now
);
6121 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6122 S_SET_SEGMENT (last_label_seen
, now_seg
);
6125 memset (&inst
, '\0', sizeof (inst
));
6126 inst
.reloc
.type
= BFD_RELOC_NONE
;
6128 skip_whitespace (str
);
6130 /* Scan up to the end of the op-code, which must end in white space or
6132 for (start
= p
= str
; *p
!= '\0'; p
++)
6138 as_bad (_("No operator -- statement `%s'\n"), str
);
6144 CONST
struct thumb_opcode
* opcode
;
6148 opcode
= (CONST
struct thumb_opcode
*) hash_find (arm_tops_hsh
, str
);
6153 /* Check that this instruction is supported for this CPU. */
6154 if (thumb_mode
== 1 && (opcode
->variants
& cpu_variant
) == 0)
6156 as_bad (_("selected processor does not support this opcode"));
6160 inst
.instruction
= opcode
->value
;
6161 inst
.size
= opcode
->size
;
6162 (*opcode
->parms
)(p
);
6169 CONST
struct asm_opcode
* opcode
;
6170 unsigned long cond_code
;
6172 inst
.size
= INSN_SIZE
;
6173 /* p now points to the end of the opcode, probably white space, but we
6174 have to break the opcode up in case it contains condionals and flags;
6175 keep trying with progressively smaller basic instructions until one
6176 matches, or we run out of opcode. */
6177 q
= (p
- str
> LONGEST_INST
) ? str
+ LONGEST_INST
: p
;
6178 for (; q
!= str
; q
--)
6182 opcode
= (CONST
struct asm_opcode
*) hash_find (arm_ops_hsh
, str
);
6185 if (opcode
&& opcode
->template)
6187 unsigned long flag_bits
= 0;
6190 /* Check that this instruction is supported for this CPU. */
6191 if ((opcode
->variants
& cpu_variant
) == 0)
6194 inst
.instruction
= opcode
->value
;
6195 if (q
== p
) /* Just a simple opcode. */
6197 if (opcode
->comp_suffix
)
6199 if (*opcode
->comp_suffix
!= '\0')
6200 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
6201 str
, opcode
->comp_suffix
);
6203 /* Not a conditional instruction. */
6204 (*opcode
->parms
)(q
, 0);
6208 /* A conditional instruction with default condition. */
6209 inst
.instruction
|= COND_ALWAYS
;
6210 (*opcode
->parms
)(q
, 0);
6216 /* Not just a simple opcode. Check if extra is a conditional. */
6220 CONST
struct asm_cond
*cond
;
6224 cond
= (CONST
struct asm_cond
*) hash_find (arm_cond_hsh
, r
);
6228 if (cond
->value
== 0xf0000000)
6230 _("Warning: Use of the 'nv' conditional is deprecated\n"));
6232 cond_code
= cond
->value
;
6236 cond_code
= COND_ALWAYS
;
6239 cond_code
= COND_ALWAYS
;
6241 /* Apply the conditional, or complain it's not allowed. */
6242 if (opcode
->comp_suffix
&& *opcode
->comp_suffix
== '\0')
6244 /* Instruction isn't conditional */
6245 if (cond_code
!= COND_ALWAYS
)
6247 as_bad (_("Opcode `%s' is unconditional\n"), str
);
6252 /* Instruction is conditional: set the condition into it. */
6253 inst
.instruction
|= cond_code
;
6256 /* If there is a compulsory suffix, it should come here, before
6257 any optional flags. */
6258 if (opcode
->comp_suffix
&& *opcode
->comp_suffix
!= '\0')
6260 CONST
char *s
= opcode
->comp_suffix
;
6272 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str
,
6273 opcode
->comp_suffix
);
6280 /* The remainder, if any should now be flags for the instruction;
6281 Scan these checking each one found with the opcode. */
6285 CONST
struct asm_flg
*flag
= opcode
->flags
;
6294 for (flagno
= 0; flag
[flagno
].template; flagno
++)
6296 if (streq (r
, flag
[flagno
].template))
6298 flag_bits
|= flag
[flagno
].set_bits
;
6304 if (! flag
[flagno
].template)
6311 (*opcode
->parms
) (p
, flag_bits
);
6321 /* It wasn't an instruction, but it might be a register alias of the form
6324 skip_whitespace (q
);
6329 if (*q
&& !strncmp (q
, ".req ", 4))
6332 char * copy_of_str
= str
;
6336 skip_whitespace (q
);
6338 for (r
= q
; *r
!= '\0'; r
++)
6348 regnum
= arm_reg_parse (& q
);
6351 reg
= arm_reg_parse (& str
);
6356 insert_reg_alias (str
, regnum
);
6358 as_warn (_("register '%s' does not exist\n"), q
);
6360 else if (regnum
!= FAIL
)
6363 as_warn (_("ignoring redefinition of register alias '%s'"), copy_of_str
);
6365 /* Do not warn about redefinitions to the same alias. */
6368 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6372 as_warn (_("ignoring incomplete .req pseuso op"));
6379 as_bad (_("bad instruction `%s'"), start
);
6384 * Invocation line includes a switch not recognized by the base assembler.
6385 * See if it's a processor-specific option. These are:
6386 * Cpu variants, the arm part is optional:
6387 * -m[arm]1 Currently not supported.
6388 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6389 * -m[arm]3 Arm 3 processor
6390 * -m[arm]6[xx], Arm 6 processors
6391 * -m[arm]7[xx][t][[d]m] Arm 7 processors
6392 * -m[arm]8[10] Arm 8 processors
6393 * -m[arm]9[20][tdmi] Arm 9 processors
6394 * -mstrongarm[110[0]] StrongARM processors
6395 * -m[arm]v[2345] Arm architectures
6396 * -mall All (except the ARM1)
6398 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6399 * -mfpe-old (No float load/store multiples)
6400 * -mno-fpu Disable all floating point instructions
6401 * Run-time endian selection:
6402 * -EB big endian cpu
6403 * -EL little endian cpu
6404 * ARM Procedure Calling Standard:
6405 * -mapcs-32 32 bit APCS
6406 * -mapcs-26 26 bit APCS
6407 * -mapcs-float Pass floats in float regs
6408 * -mapcs-reentrant Position independent code
6409 * -mthumb-interwork Code supports Arm/Thumb interworking
6410 * -moabi Old ELF ABI
6413 CONST
char * md_shortopts
= "m:k";
6414 struct option md_longopts
[] =
6416 #ifdef ARM_BI_ENDIAN
6417 #define OPTION_EB (OPTION_MD_BASE + 0)
6418 {"EB", no_argument
, NULL
, OPTION_EB
},
6419 #define OPTION_EL (OPTION_MD_BASE + 1)
6420 {"EL", no_argument
, NULL
, OPTION_EL
},
6422 #define OPTION_OABI (OPTION_MD_BASE +2)
6423 {"oabi", no_argument
, NULL
, OPTION_OABI
},
6426 {NULL
, no_argument
, NULL
, 0}
6428 size_t md_longopts_size
= sizeof (md_longopts
);
6431 md_parse_option (c
, arg
)
6439 #ifdef ARM_BI_ENDIAN
6441 target_big_endian
= 1;
6444 target_big_endian
= 0;
6452 if (streq (str
, "fpa10"))
6453 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_FPA10
;
6454 else if (streq (str
, "fpa11"))
6455 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_FPA11
;
6456 else if (streq (str
, "fpe-old"))
6457 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_CORE
;
6463 if (streq (str
, "no-fpu"))
6464 cpu_variant
&= ~FPU_ALL
;
6469 if (streq (str
, "oabi"))
6475 /* Limit assembler to generating only Thumb instructions: */
6476 if (streq (str
, "thumb"))
6478 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_THUMB
;
6479 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_NONE
;
6482 else if (streq (str
, "thumb-interwork"))
6484 if ((cpu_variant
& ARM_THUMB
) == 0)
6485 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_ARCH_V4T
;
6486 #if defined OBJ_COFF || defined OBJ_ELF
6487 support_interwork
= true;
6495 if (streq (str
, "all"))
6497 cpu_variant
= ARM_ALL
| FPU_ALL
;
6500 #if defined OBJ_COFF || defined OBJ_ELF
6501 if (! strncmp (str
, "apcs-", 5))
6503 /* GCC passes on all command line options starting "-mapcs-..."
6504 to us, so we must parse them here. */
6508 if (streq (str
, "32"))
6510 uses_apcs_26
= false;
6513 else if (streq (str
, "26"))
6515 uses_apcs_26
= true;
6518 else if (streq (str
, "frame"))
6520 /* Stack frames are being generated - does not affect
6524 else if (streq (str
, "stack-check"))
6526 /* Stack checking is being performed - does not affect
6527 linkage, but does require that the functions
6528 __rt_stkovf_split_small and __rt_stkovf_split_big be
6529 present in the final link. */
6533 else if (streq (str
, "float"))
6535 /* Floating point arguments are being passed in the floating
6536 point registers. This does affect linking, since this
6537 version of the APCS is incompatible with the version that
6538 passes floating points in the integer registers. */
6540 uses_apcs_float
= true;
6543 else if (streq (str
, "reentrant"))
6545 /* Reentrant code has been generated. This does affect
6546 linking, since there is no point in linking reentrant/
6547 position independent code with absolute position code. */
6552 as_bad (_("Unrecognised APCS switch -m%s"), arg
);
6556 /* Strip off optional "arm" */
6557 if (! strncmp (str
, "arm", 3))
6563 if (streq (str
, "1"))
6564 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_1
;
6570 if (streq (str
, "2"))
6571 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_2
;
6572 else if (streq (str
, "250"))
6573 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_250
;
6579 if (streq (str
, "3"))
6580 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_3
;
6586 switch (strtol (str
, NULL
, 10))
6593 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_6
;
6601 switch (strtol (str
, & str
, 10)) /* Eat the processor name */
6614 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
;
6620 cpu_variant
|= (ARM_THUMB
| ARM_ARCH_V4
);
6624 cpu_variant
|= ARM_LONGMUL
;
6627 case 'f': /* fe => fp enabled cpu. */
6633 case 'c': /* Left over from 710c processor name. */
6634 case 'd': /* Debug */
6635 case 'i': /* Embedded ICE */
6636 /* Included for completeness in ARM processor naming. */
6646 if (streq (str
, "8") || streq (str
, "810"))
6647 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_8
| ARM_ARCH_V4
| ARM_LONGMUL
;
6653 if (streq (str
, "9"))
6654 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_9
| ARM_ARCH_V4
| ARM_LONGMUL
| ARM_THUMB
;
6655 else if (streq (str
, "920"))
6656 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_9
| ARM_ARCH_V4
| ARM_LONGMUL
;
6657 else if (streq (str
, "920t"))
6658 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_9
| ARM_ARCH_V4
| ARM_LONGMUL
| ARM_THUMB
;
6659 else if (streq (str
, "9tdmi"))
6660 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_9
| ARM_ARCH_V4
| ARM_LONGMUL
| ARM_THUMB
;
6667 if (streq (str
, "strongarm")
6668 || streq (str
, "strongarm110")
6669 || streq (str
, "strongarm1100"))
6670 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_8
| ARM_ARCH_V4
| ARM_LONGMUL
;
6676 /* Select variant based on architecture rather than processor */
6682 case 'a': cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_3
; break;
6683 case 0: cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_2
; break;
6684 default: as_bad (_("Invalid architecture variant -m%s"), arg
); break;
6689 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
;
6693 case 'm': cpu_variant
|= ARM_LONGMUL
; break;
6695 default: as_bad (_("Invalid architecture variant -m%s"), arg
); break;
6700 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_ARCH_V4
;
6704 case 't': cpu_variant
|= ARM_THUMB
; break;
6706 default: as_bad (_("Invalid architecture variant -m%s"), arg
); break;
6711 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_ARCH_V5
;
6714 case 't': cpu_variant
|= ARM_THUMB
; break;
6715 case 'e': cpu_variant
|= ARM_EXT_V5E
; break;
6717 default: as_bad (_("Invalid architecture variant -m%s"), arg
); break;
6722 as_bad (_("Invalid architecture variant -m%s"), arg
);
6729 as_bad (_("Invalid processor variant -m%s"), arg
);
6735 #if defined OBJ_ELF || defined OBJ_COFF
6754 ARM Specific Assembler Options:\n\
6755 -m[arm][<processor name>] select processor variant\n\
6756 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
6757 -mthumb only allow Thumb instructions\n\
6758 -mthumb-interwork mark the assembled code as supporting interworking\n\
6759 -mall allow any instruction\n\
6760 -mfpa10, -mfpa11 select floating point architecture\n\
6761 -mfpe-old don't allow floating-point multiple instructions\n\
6762 -mno-fpu don't allow any floating-point instructions.\n"));
6765 -k generate PIC code.\n"));
6766 #if defined OBJ_COFF || defined OBJ_ELF
6769 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n"));
6772 -mapcs-float floating point args are passed in FP regs\n"));
6775 -mapcs-reentrant the code is position independent/reentrant\n"));
6780 -moabi support the old ELF ABI\n"));
6782 #ifdef ARM_BI_ENDIAN
6785 -EB assemble code for a big endian cpu\n\
6786 -EL assemble code for a little endian cpu\n"));
6790 /* We need to be able to fix up arbitrary expressions in some statements.
6791 This is so that we can handle symbols that are an arbitrary distance from
6792 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
6793 which returns part of an address in a form which will be valid for
6794 a data instruction. We do this by pushing the expression into a symbol
6795 in the expr_section, and creating a fix for that. */
6798 fix_new_arm (frag
, where
, size
, exp
, pc_rel
, reloc
)
6807 arm_fix_data
* arm_data
;
6815 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
6819 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
6824 /* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
6825 arm_data
= (arm_fix_data
*) obstack_alloc (& notes
, sizeof (arm_fix_data
));
6826 new_fix
->tc_fix_data
= (PTR
) arm_data
;
6827 arm_data
->thumb_mode
= thumb_mode
;
6833 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6835 cons_fix_new_arm (frag
, where
, size
, exp
)
6841 bfd_reloc_code_real_type type
;
6846 * @@ Should look at CPU word size.
6851 type
= BFD_RELOC_16
;
6855 type
= BFD_RELOC_32
;
6858 type
= BFD_RELOC_64
;
6862 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
6865 /* A good place to do this, although this was probably not intended
6866 for this kind of use. We need to dump the literal pool before
6867 references are made to a null symbol pointer. */
6871 if (current_poolP
== NULL
)
6874 subseg_set (text_section
, 0); /* Put it at the end of text section. */
6876 listing_prev_line ();
6880 arm_start_line_hook ()
6882 last_label_seen
= NULL
;
6886 arm_frob_label (sym
)
6889 last_label_seen
= sym
;
6891 ARM_SET_THUMB (sym
, thumb_mode
);
6893 #if defined OBJ_COFF || defined OBJ_ELF
6894 ARM_SET_INTERWORK (sym
, support_interwork
);
6897 if (label_is_thumb_function_name
)
6899 /* When the address of a Thumb function is taken the bottom
6900 bit of that address should be set. This will allow
6901 interworking between Arm and Thumb functions to work
6904 THUMB_SET_FUNC (sym
, 1);
6906 label_is_thumb_function_name
= false;
6910 /* Adjust the symbol table. This marks Thumb symbols as distinct from
6914 arm_adjust_symtab ()
6919 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
6921 if (ARM_IS_THUMB (sym
))
6923 if (THUMB_IS_FUNC (sym
))
6925 /* Mark the symbol as a Thumb function. */
6926 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
6927 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
6928 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
6930 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
6931 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
6933 as_bad (_("%s: unexpected function type: %d"),
6934 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
6936 else switch (S_GET_STORAGE_CLASS (sym
))
6939 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
6942 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
6945 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
6947 default: /* do nothing */
6952 if (ARM_IS_INTERWORK (sym
))
6953 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
6960 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
6962 if (ARM_IS_THUMB (sym
))
6964 elf_symbol_type
* elf_sym
;
6966 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
6967 bind
= ELF_ST_BIND (elf_sym
);
6969 /* If it's a .thumb_func, declare it as so, else tag label as .code 16. */
6970 if (THUMB_IS_FUNC (sym
))
6971 elf_sym
->internal_elf_sym
.st_info
= ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
6973 elf_sym
->internal_elf_sym
.st_info
= ELF_ST_INFO (bind
, STT_ARM_16BIT
);
6982 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
6984 *input_line_pointer
= '/';
6985 input_line_pointer
+= 5;
6986 *input_line_pointer
= 0;
6994 arm_canonicalize_symbol_name (name
)
6999 if (thumb_mode
&& (len
= strlen (name
)) > 5
7000 && streq (name
+ len
- 5, "/data"))
7001 *(name
+ len
- 5) = 0;
7007 arm_validate_fix (fixP
)
7010 /* If the destination of the branch is a defined symbol which does not have
7011 the THUMB_FUNC attribute, then we must be calling a function which has
7012 the (interfacearm) attribute. We look for the Thumb entry point to that
7013 function and change the branch to refer to that function instead. */
7014 if ( fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
7015 && fixP
->fx_addsy
!= NULL
7016 && S_IS_DEFINED (fixP
->fx_addsy
)
7017 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
7019 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
7027 /* Relocations against Thumb function names must be left unadjusted,
7028 so that the linker can use this information to correctly set the
7029 bottom bit of their addresses. The MIPS version of this function
7030 also prevents relocations that are mips-16 specific, but I do not
7031 know why it does this.
7034 There is one other problem that ought to be addressed here, but
7035 which currently is not: Taking the address of a label (rather
7036 than a function) and then later jumping to that address. Such
7037 addresses also ought to have their bottom bit set (assuming that
7038 they reside in Thumb code), but at the moment they will not. */
7041 arm_fix_adjustable (fixP
)
7044 if (fixP
->fx_addsy
== NULL
)
7047 /* Prevent all adjustments to global symbols. */
7048 if (S_IS_EXTERN (fixP
->fx_addsy
))
7051 if (S_IS_WEAK (fixP
->fx_addsy
))
7054 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
7055 && fixP
->fx_subsy
== NULL
)
7058 /* We need the symbol name for the VTABLE entries */
7059 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
7060 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
7067 elf32_arm_target_format ()
7069 if (target_big_endian
)
7071 return "elf32-bigarm-oabi";
7073 return "elf32-bigarm";
7076 return "elf32-littlearm-oabi";
7078 return "elf32-littlearm";
7082 armelf_frob_symbol (symp
, puntp
)
7086 elf_frob_symbol (symp
, puntp
);
7090 arm_force_relocation (fixp
)
7093 if ( fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
7094 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
7095 || fixp
->fx_r_type
== BFD_RELOC_ARM_PCREL_BRANCH
7096 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
)
7102 static bfd_reloc_code_real_type
7112 bfd_reloc_code_real_type reloc
;
7116 #define MAP(str,reloc) { str, sizeof (str)-1, reloc }
7117 MAP ("(got)", BFD_RELOC_ARM_GOT32
),
7118 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF
),
7119 /* ScottB: Jan 30, 1998 */
7120 /* Added support for parsing "var(PLT)" branch instructions */
7121 /* generated by GCC for PLT relocs */
7122 MAP ("(plt)", BFD_RELOC_ARM_PLT32
),
7123 { NULL
, 0, BFD_RELOC_UNUSED
}
7127 for (i
= 0, ip
= input_line_pointer
;
7128 i
< sizeof (id
) && (isalnum (*ip
) || ispunct (*ip
));
7130 id
[i
] = tolower (*ip
);
7132 for (i
= 0; reloc_map
[i
].str
; i
++)
7133 if (strncmp (id
, reloc_map
[i
].str
, reloc_map
[i
].len
) == 0)
7136 input_line_pointer
+= reloc_map
[i
].len
;
7138 return reloc_map
[i
].reloc
;
7142 s_arm_elf_cons (nbytes
)
7147 #ifdef md_flush_pending_output
7148 md_flush_pending_output ();
7151 if (is_it_end_of_statement ())
7153 demand_empty_rest_of_line ();
7157 #ifdef md_cons_align
7158 md_cons_align (nbytes
);
7163 bfd_reloc_code_real_type reloc
;
7167 if (exp
.X_op
== O_symbol
7168 && * input_line_pointer
== '('
7169 && (reloc
= arm_parse_reloc()) != BFD_RELOC_UNUSED
)
7171 reloc_howto_type
* howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
7172 int size
= bfd_get_reloc_size (howto
);
7175 as_bad ("%s relocations do not fit in %d bytes", howto
->name
, nbytes
);
7178 register char * p
= frag_more ((int) nbytes
);
7179 int offset
= nbytes
- size
;
7181 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
, size
,
7186 emit_expr (& exp
, (unsigned int) nbytes
);
7188 while (*input_line_pointer
++ == ',');
7190 input_line_pointer
--; /* Put terminator back into stream. */
7191 demand_empty_rest_of_line ();
7194 #endif /* OBJ_ELF */