1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
188 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_arch_any
= ARM_ANY
;
202 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
203 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
204 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
206 static const arm_feature_set arm_cext_iwmmxt2
=
207 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
208 static const arm_feature_set arm_cext_iwmmxt
=
209 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
210 static const arm_feature_set arm_cext_xscale
=
211 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
212 static const arm_feature_set arm_cext_maverick
=
213 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
214 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
215 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v1xd
=
217 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
218 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
219 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
221 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
222 static const arm_feature_set fpu_vfp_ext_d32
=
223 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
224 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
225 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
226 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
227 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
228 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
229 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
231 static int mfloat_abi_opt
= -1;
232 /* Record user cpu selection for object attributes. */
233 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
234 /* Must be long enough to hold any of the names in arm_cpus. */
235 static char selected_cpu_name
[16];
238 static int meabi_flags
= EABI_DEFAULT
;
240 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
243 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
248 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
253 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
254 symbolS
* GOT_symbol
;
257 /* 0: assemble for ARM,
258 1: assemble for Thumb,
259 2: assemble for Thumb even though target CPU does not support thumb
261 static int thumb_mode
= 0;
262 /* A value distinct from the possible values for thumb_mode that we
263 can use to record whether thumb_mode has been copied into the
264 tc_frag_data field of a frag. */
265 #define MODE_RECORDED (1 << 4)
267 /* Specifies the intrinsic IT insn behavior mode. */
268 enum implicit_it_mode
270 IMPLICIT_IT_MODE_NEVER
= 0x00,
271 IMPLICIT_IT_MODE_ARM
= 0x01,
272 IMPLICIT_IT_MODE_THUMB
= 0x02,
273 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
275 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
277 /* If unified_syntax is true, we are processing the new unified
278 ARM/Thumb syntax. Important differences from the old ARM mode:
280 - Immediate operands do not require a # prefix.
281 - Conditional affixes always appear at the end of the
282 instruction. (For backward compatibility, those instructions
283 that formerly had them in the middle, continue to accept them
285 - The IT instruction may appear, and if it does is validated
286 against subsequent conditional affixes. It does not generate
289 Important differences from the old Thumb mode:
291 - Immediate operands do not require a # prefix.
292 - Most of the V6T2 instructions are only available in unified mode.
293 - The .N and .W suffixes are recognized and honored (it is an error
294 if they cannot be honored).
295 - All instructions set the flags if and only if they have an 's' affix.
296 - Conditional affixes may be used. They are validated against
297 preceding IT instructions. Unlike ARM mode, you cannot use a
298 conditional affix except in the scope of an IT instruction. */
300 static bfd_boolean unified_syntax
= FALSE
;
315 enum neon_el_type type
;
319 #define NEON_MAX_TYPE_ELS 4
323 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
327 enum it_instruction_type
332 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
333 if inside, should be the last one. */
334 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
335 i.e. BKPT and NOP. */
336 IT_INSN
/* The IT insn has been parsed. */
342 unsigned long instruction
;
346 /* "uncond_value" is set to the value in place of the conditional field in
347 unconditional versions of the instruction, or -1 if nothing is
350 struct neon_type vectype
;
351 /* This does not indicate an actual NEON instruction, only that
352 the mnemonic accepts neon-style type suffixes. */
354 /* Set to the opcode if the instruction needs relaxation.
355 Zero if the instruction is not relaxed. */
359 bfd_reloc_code_real_type type
;
364 enum it_instruction_type it_insn_type
;
370 struct neon_type_el vectype
;
371 unsigned present
: 1; /* Operand present. */
372 unsigned isreg
: 1; /* Operand was a register. */
373 unsigned immisreg
: 1; /* .imm field is a second register. */
374 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
375 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
376 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
377 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
378 instructions. This allows us to disambiguate ARM <-> vector insns. */
379 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
380 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
381 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
382 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
383 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
384 unsigned writeback
: 1; /* Operand has trailing ! */
385 unsigned preind
: 1; /* Preindexed address. */
386 unsigned postind
: 1; /* Postindexed address. */
387 unsigned negative
: 1; /* Index register was negated. */
388 unsigned shifted
: 1; /* Shift applied to operation. */
389 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
393 static struct arm_it inst
;
395 #define NUM_FLOAT_VALS 8
397 const char * fp_const
[] =
399 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
402 /* Number of littlenums required to hold an extended precision number. */
403 #define MAX_LITTLENUMS 6
405 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
415 #define CP_T_X 0x00008000
416 #define CP_T_Y 0x00400000
418 #define CONDS_BIT 0x00100000
419 #define LOAD_BIT 0x00100000
421 #define DOUBLE_LOAD_FLAG 0x00000001
425 const char * template_name
;
429 #define COND_ALWAYS 0xE
433 const char * template_name
;
437 struct asm_barrier_opt
439 const char * template_name
;
443 /* The bit that distinguishes CPSR and SPSR. */
444 #define SPSR_BIT (1 << 22)
446 /* The individual PSR flag bits. */
447 #define PSR_c (1 << 16)
448 #define PSR_x (1 << 17)
449 #define PSR_s (1 << 18)
450 #define PSR_f (1 << 19)
455 bfd_reloc_code_real_type reloc
;
460 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
461 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
466 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
469 /* Bits for DEFINED field in neon_typed_alias. */
470 #define NTA_HASTYPE 1
471 #define NTA_HASINDEX 2
473 struct neon_typed_alias
475 unsigned char defined
;
477 struct neon_type_el eltype
;
480 /* ARM register categories. This includes coprocessor numbers and various
481 architecture extensions' registers. */
507 /* Structure for a hash table entry for a register.
508 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
509 information which states whether a vector type or index is specified (for a
510 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
514 unsigned char number
;
516 unsigned char builtin
;
517 struct neon_typed_alias
* neon
;
520 /* Diagnostics used when we don't get a register of the expected type. */
521 const char * const reg_expected_msgs
[] =
523 N_("ARM register expected"),
524 N_("bad or missing co-processor number"),
525 N_("co-processor register expected"),
526 N_("FPA register expected"),
527 N_("VFP single precision register expected"),
528 N_("VFP/Neon double precision register expected"),
529 N_("Neon quad precision register expected"),
530 N_("VFP single or double precision register expected"),
531 N_("Neon double or quad precision register expected"),
532 N_("VFP single, double or Neon quad precision register expected"),
533 N_("VFP system register expected"),
534 N_("Maverick MVF register expected"),
535 N_("Maverick MVD register expected"),
536 N_("Maverick MVFX register expected"),
537 N_("Maverick MVDX register expected"),
538 N_("Maverick MVAX register expected"),
539 N_("Maverick DSPSC register expected"),
540 N_("iWMMXt data register expected"),
541 N_("iWMMXt control register expected"),
542 N_("iWMMXt scalar register expected"),
543 N_("XScale accumulator register expected"),
546 /* Some well known registers that we refer to directly elsewhere. */
551 /* ARM instructions take 4bytes in the object file, Thumb instructions
557 /* Basic string to match. */
558 const char * template_name
;
560 /* Parameters to instruction. */
561 unsigned int operands
[8];
563 /* Conditional tag - see opcode_lookup. */
564 unsigned int tag
: 4;
566 /* Basic instruction code. */
567 unsigned int avalue
: 28;
569 /* Thumb-format instruction code. */
572 /* Which architecture variant provides this instruction. */
573 const arm_feature_set
* avariant
;
574 const arm_feature_set
* tvariant
;
576 /* Function to call to encode instruction in ARM format. */
577 void (* aencode
) (void);
579 /* Function to call to encode instruction in Thumb format. */
580 void (* tencode
) (void);
583 /* Defines for various bits that we will want to toggle. */
584 #define INST_IMMEDIATE 0x02000000
585 #define OFFSET_REG 0x02000000
586 #define HWOFFSET_IMM 0x00400000
587 #define SHIFT_BY_REG 0x00000010
588 #define PRE_INDEX 0x01000000
589 #define INDEX_UP 0x00800000
590 #define WRITE_BACK 0x00200000
591 #define LDM_TYPE_2_OR_3 0x00400000
592 #define CPSI_MMOD 0x00020000
594 #define LITERAL_MASK 0xf000f000
595 #define OPCODE_MASK 0xfe1fffff
596 #define V4_STR_BIT 0x00000020
598 #define T2_SUBS_PC_LR 0xf3de8f00
600 #define DATA_OP_SHIFT 21
602 #define T2_OPCODE_MASK 0xfe1fffff
603 #define T2_DATA_OP_SHIFT 21
605 /* Codes to distinguish the arithmetic instructions. */
616 #define OPCODE_CMP 10
617 #define OPCODE_CMN 11
618 #define OPCODE_ORR 12
619 #define OPCODE_MOV 13
620 #define OPCODE_BIC 14
621 #define OPCODE_MVN 15
623 #define T2_OPCODE_AND 0
624 #define T2_OPCODE_BIC 1
625 #define T2_OPCODE_ORR 2
626 #define T2_OPCODE_ORN 3
627 #define T2_OPCODE_EOR 4
628 #define T2_OPCODE_ADD 8
629 #define T2_OPCODE_ADC 10
630 #define T2_OPCODE_SBC 11
631 #define T2_OPCODE_SUB 13
632 #define T2_OPCODE_RSB 14
634 #define T_OPCODE_MUL 0x4340
635 #define T_OPCODE_TST 0x4200
636 #define T_OPCODE_CMN 0x42c0
637 #define T_OPCODE_NEG 0x4240
638 #define T_OPCODE_MVN 0x43c0
640 #define T_OPCODE_ADD_R3 0x1800
641 #define T_OPCODE_SUB_R3 0x1a00
642 #define T_OPCODE_ADD_HI 0x4400
643 #define T_OPCODE_ADD_ST 0xb000
644 #define T_OPCODE_SUB_ST 0xb080
645 #define T_OPCODE_ADD_SP 0xa800
646 #define T_OPCODE_ADD_PC 0xa000
647 #define T_OPCODE_ADD_I8 0x3000
648 #define T_OPCODE_SUB_I8 0x3800
649 #define T_OPCODE_ADD_I3 0x1c00
650 #define T_OPCODE_SUB_I3 0x1e00
652 #define T_OPCODE_ASR_R 0x4100
653 #define T_OPCODE_LSL_R 0x4080
654 #define T_OPCODE_LSR_R 0x40c0
655 #define T_OPCODE_ROR_R 0x41c0
656 #define T_OPCODE_ASR_I 0x1000
657 #define T_OPCODE_LSL_I 0x0000
658 #define T_OPCODE_LSR_I 0x0800
660 #define T_OPCODE_MOV_I8 0x2000
661 #define T_OPCODE_CMP_I8 0x2800
662 #define T_OPCODE_CMP_LR 0x4280
663 #define T_OPCODE_MOV_HR 0x4600
664 #define T_OPCODE_CMP_HR 0x4500
666 #define T_OPCODE_LDR_PC 0x4800
667 #define T_OPCODE_LDR_SP 0x9800
668 #define T_OPCODE_STR_SP 0x9000
669 #define T_OPCODE_LDR_IW 0x6800
670 #define T_OPCODE_STR_IW 0x6000
671 #define T_OPCODE_LDR_IH 0x8800
672 #define T_OPCODE_STR_IH 0x8000
673 #define T_OPCODE_LDR_IB 0x7800
674 #define T_OPCODE_STR_IB 0x7000
675 #define T_OPCODE_LDR_RW 0x5800
676 #define T_OPCODE_STR_RW 0x5000
677 #define T_OPCODE_LDR_RH 0x5a00
678 #define T_OPCODE_STR_RH 0x5200
679 #define T_OPCODE_LDR_RB 0x5c00
680 #define T_OPCODE_STR_RB 0x5400
682 #define T_OPCODE_PUSH 0xb400
683 #define T_OPCODE_POP 0xbc00
685 #define T_OPCODE_BRANCH 0xe000
687 #define THUMB_SIZE 2 /* Size of thumb instruction. */
688 #define THUMB_PP_PC_LR 0x0100
689 #define THUMB_LOAD_BIT 0x0800
690 #define THUMB2_LOAD_BIT 0x00100000
692 #define BAD_ARGS _("bad arguments to instruction")
693 #define BAD_SP _("r13 not allowed here")
694 #define BAD_PC _("r15 not allowed here")
695 #define BAD_COND _("instruction cannot be conditional")
696 #define BAD_OVERLAP _("registers may not be the same")
697 #define BAD_HIREG _("lo register required")
698 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
699 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
700 #define BAD_BRANCH _("branch must be last instruction in IT block")
701 #define BAD_NOT_IT _("instruction not allowed in IT block")
702 #define BAD_FPU _("selected FPU does not support instruction")
703 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
704 #define BAD_IT_COND _("incorrect condition in IT block")
705 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
706 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
707 #define BAD_PC_ADDRESSING \
708 _("cannot use register index with PC-relative addressing")
709 #define BAD_PC_WRITEBACK \
710 _("cannot use writeback with PC-relative addressing")
712 static struct hash_control
* arm_ops_hsh
;
713 static struct hash_control
* arm_cond_hsh
;
714 static struct hash_control
* arm_shift_hsh
;
715 static struct hash_control
* arm_psr_hsh
;
716 static struct hash_control
* arm_v7m_psr_hsh
;
717 static struct hash_control
* arm_reg_hsh
;
718 static struct hash_control
* arm_reloc_hsh
;
719 static struct hash_control
* arm_barrier_opt_hsh
;
721 /* Stuff needed to resolve the label ambiguity
730 symbolS
* last_label_seen
;
731 static int label_is_thumb_function_name
= FALSE
;
733 /* Literal pool structure. Held on a per-section
734 and per-sub-section basis. */
736 #define MAX_LITERAL_POOL_SIZE 1024
737 typedef struct literal_pool
739 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
740 unsigned int next_free_entry
;
745 struct literal_pool
* next
;
748 /* Pointer to a linked list of literal pools. */
749 literal_pool
* list_of_pools
= NULL
;
752 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
754 static struct current_it now_it
;
758 now_it_compatible (int cond
)
760 return (cond
& ~1) == (now_it
.cc
& ~1);
764 conditional_insn (void)
766 return inst
.cond
!= COND_ALWAYS
;
769 static int in_it_block (void);
771 static int handle_it_state (void);
773 static void force_automatic_it_block_close (void);
775 static void it_fsm_post_encode (void);
777 #define set_it_insn_type(type) \
780 inst.it_insn_type = type; \
781 if (handle_it_state () == FAIL) \
786 #define set_it_insn_type_nonvoid(type, failret) \
789 inst.it_insn_type = type; \
790 if (handle_it_state () == FAIL) \
795 #define set_it_insn_type_last() \
798 if (inst.cond == COND_ALWAYS) \
799 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
801 set_it_insn_type (INSIDE_IT_LAST_INSN); \
807 /* This array holds the chars that always start a comment. If the
808 pre-processor is disabled, these aren't very useful. */
809 const char comment_chars
[] = "@";
811 /* This array holds the chars that only start a comment at the beginning of
812 a line. If the line seems to have the form '# 123 filename'
813 .line and .file directives will appear in the pre-processed output. */
814 /* Note that input_file.c hand checks for '#' at the beginning of the
815 first line of the input file. This is because the compiler outputs
816 #NO_APP at the beginning of its output. */
817 /* Also note that comments like this one will always work. */
818 const char line_comment_chars
[] = "#";
820 const char line_separator_chars
[] = ";";
822 /* Chars that can be used to separate mant
823 from exp in floating point numbers. */
824 const char EXP_CHARS
[] = "eE";
826 /* Chars that mean this number is a floating point constant. */
830 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
832 /* Prefix characters that indicate the start of an immediate
834 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
836 /* Separator character handling. */
838 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
841 skip_past_char (char ** str
, char c
)
852 #define skip_past_comma(str) skip_past_char (str, ',')
854 /* Arithmetic expressions (possibly involving symbols). */
856 /* Return TRUE if anything in the expression is a bignum. */
859 walk_no_bignums (symbolS
* sp
)
861 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
864 if (symbol_get_value_expression (sp
)->X_add_symbol
)
866 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
867 || (symbol_get_value_expression (sp
)->X_op_symbol
868 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
874 static int in_my_get_expression
= 0;
876 /* Third argument to my_get_expression. */
877 #define GE_NO_PREFIX 0
878 #define GE_IMM_PREFIX 1
879 #define GE_OPT_PREFIX 2
880 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
881 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
882 #define GE_OPT_PREFIX_BIG 3
885 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
890 /* In unified syntax, all prefixes are optional. */
892 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
897 case GE_NO_PREFIX
: break;
899 if (!is_immediate_prefix (**str
))
901 inst
.error
= _("immediate expression requires a # prefix");
907 case GE_OPT_PREFIX_BIG
:
908 if (is_immediate_prefix (**str
))
914 memset (ep
, 0, sizeof (expressionS
));
916 save_in
= input_line_pointer
;
917 input_line_pointer
= *str
;
918 in_my_get_expression
= 1;
919 seg
= expression (ep
);
920 in_my_get_expression
= 0;
922 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
924 /* We found a bad or missing expression in md_operand(). */
925 *str
= input_line_pointer
;
926 input_line_pointer
= save_in
;
927 if (inst
.error
== NULL
)
928 inst
.error
= (ep
->X_op
== O_absent
929 ? _("missing expression") :_("bad expression"));
934 if (seg
!= absolute_section
935 && seg
!= text_section
936 && seg
!= data_section
937 && seg
!= bss_section
938 && seg
!= undefined_section
)
940 inst
.error
= _("bad segment");
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
949 /* Get rid of any bignums now, so that we don't generate an error for which
950 we can't establish a line number later on. Big numbers are never valid
951 in instructions, which is where this routine is always called. */
952 if (prefix_mode
!= GE_OPT_PREFIX_BIG
953 && (ep
->X_op
== O_big
955 && (walk_no_bignums (ep
->X_add_symbol
)
957 && walk_no_bignums (ep
->X_op_symbol
))))))
959 inst
.error
= _("invalid constant");
960 *str
= input_line_pointer
;
961 input_line_pointer
= save_in
;
965 *str
= input_line_pointer
;
966 input_line_pointer
= save_in
;
970 /* Turn a string in input_line_pointer into a floating point constant
971 of type TYPE, and store the appropriate bytes in *LITP. The number
972 of LITTLENUMS emitted is stored in *SIZEP. An error message is
973 returned, or NULL on OK.
975 Note that fp constants aren't represent in the normal way on the ARM.
976 In big endian mode, things are as expected. However, in little endian
977 mode fp constants are big-endian word-wise, and little-endian byte-wise
978 within the words. For example, (double) 1.1 in big endian mode is
979 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
980 the byte sequence 99 99 f1 3f 9a 99 99 99.
982 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
985 md_atof (int type
, char * litP
, int * sizeP
)
988 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1020 return _("Unrecognized or unsupported floating point constant");
1023 t
= atof_ieee (input_line_pointer
, type
, words
);
1025 input_line_pointer
= t
;
1026 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1028 if (target_big_endian
)
1030 for (i
= 0; i
< prec
; i
++)
1032 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1033 litP
+= sizeof (LITTLENUM_TYPE
);
1038 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1039 for (i
= prec
- 1; i
>= 0; i
--)
1041 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1042 litP
+= sizeof (LITTLENUM_TYPE
);
1045 /* For a 4 byte float the order of elements in `words' is 1 0.
1046 For an 8 byte float the order is 1 0 3 2. */
1047 for (i
= 0; i
< prec
; i
+= 2)
1049 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1050 sizeof (LITTLENUM_TYPE
));
1051 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1052 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1053 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1060 /* We handle all bad expressions here, so that we can report the faulty
1061 instruction in the error message. */
1063 md_operand (expressionS
* exp
)
1065 if (in_my_get_expression
)
1066 exp
->X_op
= O_illegal
;
1069 /* Immediate values. */
1071 /* Generic immediate-value read function for use in directives.
1072 Accepts anything that 'expression' can fold to a constant.
1073 *val receives the number. */
1076 immediate_for_directive (int *val
)
1079 exp
.X_op
= O_illegal
;
1081 if (is_immediate_prefix (*input_line_pointer
))
1083 input_line_pointer
++;
1087 if (exp
.X_op
!= O_constant
)
1089 as_bad (_("expected #constant"));
1090 ignore_rest_of_line ();
1093 *val
= exp
.X_add_number
;
1098 /* Register parsing. */
1100 /* Generic register parser. CCP points to what should be the
1101 beginning of a register name. If it is indeed a valid register
1102 name, advance CCP over it and return the reg_entry structure;
1103 otherwise return NULL. Does not issue diagnostics. */
1105 static struct reg_entry
*
1106 arm_reg_parse_multi (char **ccp
)
1110 struct reg_entry
*reg
;
1112 #ifdef REGISTER_PREFIX
1113 if (*start
!= REGISTER_PREFIX
)
1117 #ifdef OPTIONAL_REGISTER_PREFIX
1118 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1123 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1128 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1130 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1140 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1141 enum arm_reg_type type
)
1143 /* Alternative syntaxes are accepted for a few register classes. */
1150 /* Generic coprocessor register names are allowed for these. */
1151 if (reg
&& reg
->type
== REG_TYPE_CN
)
1156 /* For backward compatibility, a bare number is valid here. */
1158 unsigned long processor
= strtoul (start
, ccp
, 10);
1159 if (*ccp
!= start
&& processor
<= 15)
1163 case REG_TYPE_MMXWC
:
1164 /* WC includes WCG. ??? I'm not sure this is true for all
1165 instructions that take WC registers. */
1166 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1177 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1178 return value is the register number or FAIL. */
1181 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1184 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1187 /* Do not allow a scalar (reg+index) to parse as a register. */
1188 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1191 if (reg
&& reg
->type
== type
)
1194 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1201 /* Parse a Neon type specifier. *STR should point at the leading '.'
1202 character. Does no verification at this stage that the type fits the opcode
1209 Can all be legally parsed by this function.
1211 Fills in neon_type struct pointer with parsed information, and updates STR
1212 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1213 type, FAIL if not. */
1216 parse_neon_type (struct neon_type
*type
, char **str
)
1223 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1225 enum neon_el_type thistype
= NT_untyped
;
1226 unsigned thissize
= -1u;
1233 /* Just a size without an explicit type. */
1237 switch (TOLOWER (*ptr
))
1239 case 'i': thistype
= NT_integer
; break;
1240 case 'f': thistype
= NT_float
; break;
1241 case 'p': thistype
= NT_poly
; break;
1242 case 's': thistype
= NT_signed
; break;
1243 case 'u': thistype
= NT_unsigned
; break;
1245 thistype
= NT_float
;
1250 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1256 /* .f is an abbreviation for .f32. */
1257 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1262 thissize
= strtoul (ptr
, &ptr
, 10);
1264 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1267 as_bad (_("bad size %d in type specifier"), thissize
);
1275 type
->el
[type
->elems
].type
= thistype
;
1276 type
->el
[type
->elems
].size
= thissize
;
1281 /* Empty/missing type is not a successful parse. */
1282 if (type
->elems
== 0)
1290 /* Errors may be set multiple times during parsing or bit encoding
1291 (particularly in the Neon bits), but usually the earliest error which is set
1292 will be the most meaningful. Avoid overwriting it with later (cascading)
1293 errors by calling this function. */
1296 first_error (const char *err
)
1302 /* Parse a single type, e.g. ".s32", leading period included. */
1304 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1307 struct neon_type optype
;
1311 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1313 if (optype
.elems
== 1)
1314 *vectype
= optype
.el
[0];
1317 first_error (_("only one type should be specified for operand"));
1323 first_error (_("vector type expected"));
1335 /* Special meanings for indices (which have a range of 0-7), which will fit into
1338 #define NEON_ALL_LANES 15
1339 #define NEON_INTERLEAVE_LANES 14
1341 /* Parse either a register or a scalar, with an optional type. Return the
1342 register number, and optionally fill in the actual type of the register
1343 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1344 type/index information in *TYPEINFO. */
1347 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1348 enum arm_reg_type
*rtype
,
1349 struct neon_typed_alias
*typeinfo
)
1352 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1353 struct neon_typed_alias atype
;
1354 struct neon_type_el parsetype
;
1358 atype
.eltype
.type
= NT_invtype
;
1359 atype
.eltype
.size
= -1;
1361 /* Try alternate syntax for some types of register. Note these are mutually
1362 exclusive with the Neon syntax extensions. */
1365 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1373 /* Undo polymorphism when a set of register types may be accepted. */
1374 if ((type
== REG_TYPE_NDQ
1375 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1376 || (type
== REG_TYPE_VFSD
1377 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1378 || (type
== REG_TYPE_NSDQ
1379 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1380 || reg
->type
== REG_TYPE_NQ
))
1381 || (type
== REG_TYPE_MMXWC
1382 && (reg
->type
== REG_TYPE_MMXWCG
)))
1383 type
= (enum arm_reg_type
) reg
->type
;
1385 if (type
!= reg
->type
)
1391 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1393 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1395 first_error (_("can't redefine type for operand"));
1398 atype
.defined
|= NTA_HASTYPE
;
1399 atype
.eltype
= parsetype
;
1402 if (skip_past_char (&str
, '[') == SUCCESS
)
1404 if (type
!= REG_TYPE_VFD
)
1406 first_error (_("only D registers may be indexed"));
1410 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1412 first_error (_("can't change index for operand"));
1416 atype
.defined
|= NTA_HASINDEX
;
1418 if (skip_past_char (&str
, ']') == SUCCESS
)
1419 atype
.index
= NEON_ALL_LANES
;
1424 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1426 if (exp
.X_op
!= O_constant
)
1428 first_error (_("constant expression required"));
1432 if (skip_past_char (&str
, ']') == FAIL
)
1435 atype
.index
= exp
.X_add_number
;
1450 /* Like arm_reg_parse, but allow allow the following extra features:
1451 - If RTYPE is non-zero, return the (possibly restricted) type of the
1452 register (e.g. Neon double or quad reg when either has been requested).
1453 - If this is a Neon vector type with additional type information, fill
1454 in the struct pointed to by VECTYPE (if non-NULL).
1455 This function will fault on encountering a scalar. */
1458 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1459 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1461 struct neon_typed_alias atype
;
1463 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1468 /* Do not allow a scalar (reg+index) to parse as a register. */
1469 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1471 first_error (_("register operand expected, but got scalar"));
1476 *vectype
= atype
.eltype
;
1483 #define NEON_SCALAR_REG(X) ((X) >> 4)
1484 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1486 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1487 have enough information to be able to do a good job bounds-checking. So, we
1488 just do easy checks here, and do further checks later. */
1491 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1495 struct neon_typed_alias atype
;
1497 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1499 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1502 if (atype
.index
== NEON_ALL_LANES
)
1504 first_error (_("scalar must have an index"));
1507 else if (atype
.index
>= 64 / elsize
)
1509 first_error (_("scalar index out of range"));
1514 *type
= atype
.eltype
;
1518 return reg
* 16 + atype
.index
;
1521 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1524 parse_reg_list (char ** strp
)
1526 char * str
= * strp
;
1530 /* We come back here if we get ranges concatenated by '+' or '|'. */
1545 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1547 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1557 first_error (_("bad range in register list"));
1561 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1563 if (range
& (1 << i
))
1565 (_("Warning: duplicated register (r%d) in register list"),
1573 if (range
& (1 << reg
))
1574 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1576 else if (reg
<= cur_reg
)
1577 as_tsktsk (_("Warning: register range not in ascending order"));
1582 while (skip_past_comma (&str
) != FAIL
1583 || (in_range
= 1, *str
++ == '-'));
1588 first_error (_("missing `}'"));
1596 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1599 if (exp
.X_op
== O_constant
)
1601 if (exp
.X_add_number
1602 != (exp
.X_add_number
& 0x0000ffff))
1604 inst
.error
= _("invalid register mask");
1608 if ((range
& exp
.X_add_number
) != 0)
1610 int regno
= range
& exp
.X_add_number
;
1613 regno
= (1 << regno
) - 1;
1615 (_("Warning: duplicated register (r%d) in register list"),
1619 range
|= exp
.X_add_number
;
1623 if (inst
.reloc
.type
!= 0)
1625 inst
.error
= _("expression too complex");
1629 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1630 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1631 inst
.reloc
.pc_rel
= 0;
1635 if (*str
== '|' || *str
== '+')
1641 while (another_range
);
1647 /* Types of registers in a list. */
1656 /* Parse a VFP register list. If the string is invalid return FAIL.
1657 Otherwise return the number of registers, and set PBASE to the first
1658 register. Parses registers of type ETYPE.
1659 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1660 - Q registers can be used to specify pairs of D registers
1661 - { } can be omitted from around a singleton register list
1662 FIXME: This is not implemented, as it would require backtracking in
1665 This could be done (the meaning isn't really ambiguous), but doesn't
1666 fit in well with the current parsing framework.
1667 - 32 D registers may be used (also true for VFPv3).
1668 FIXME: Types are ignored in these register lists, which is probably a
1672 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1677 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1681 unsigned long mask
= 0;
1686 inst
.error
= _("expecting {");
1695 regtype
= REG_TYPE_VFS
;
1700 regtype
= REG_TYPE_VFD
;
1703 case REGLIST_NEON_D
:
1704 regtype
= REG_TYPE_NDQ
;
1708 if (etype
!= REGLIST_VFP_S
)
1710 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1711 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1715 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1718 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1725 base_reg
= max_regs
;
1729 int setmask
= 1, addregs
= 1;
1731 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1733 if (new_base
== FAIL
)
1735 first_error (_(reg_expected_msgs
[regtype
]));
1739 if (new_base
>= max_regs
)
1741 first_error (_("register out of range in list"));
1745 /* Note: a value of 2 * n is returned for the register Q<n>. */
1746 if (regtype
== REG_TYPE_NQ
)
1752 if (new_base
< base_reg
)
1753 base_reg
= new_base
;
1755 if (mask
& (setmask
<< new_base
))
1757 first_error (_("invalid register list"));
1761 if ((mask
>> new_base
) != 0 && ! warned
)
1763 as_tsktsk (_("register list not in ascending order"));
1767 mask
|= setmask
<< new_base
;
1770 if (*str
== '-') /* We have the start of a range expression */
1776 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1779 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1783 if (high_range
>= max_regs
)
1785 first_error (_("register out of range in list"));
1789 if (regtype
== REG_TYPE_NQ
)
1790 high_range
= high_range
+ 1;
1792 if (high_range
<= new_base
)
1794 inst
.error
= _("register range not in ascending order");
1798 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1800 if (mask
& (setmask
<< new_base
))
1802 inst
.error
= _("invalid register list");
1806 mask
|= setmask
<< new_base
;
1811 while (skip_past_comma (&str
) != FAIL
);
1815 /* Sanity check -- should have raised a parse error above. */
1816 if (count
== 0 || count
> max_regs
)
1821 /* Final test -- the registers must be consecutive. */
1823 for (i
= 0; i
< count
; i
++)
1825 if ((mask
& (1u << i
)) == 0)
1827 inst
.error
= _("non-contiguous register range");
1837 /* True if two alias types are the same. */
1840 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1848 if (a
->defined
!= b
->defined
)
1851 if ((a
->defined
& NTA_HASTYPE
) != 0
1852 && (a
->eltype
.type
!= b
->eltype
.type
1853 || a
->eltype
.size
!= b
->eltype
.size
))
1856 if ((a
->defined
& NTA_HASINDEX
) != 0
1857 && (a
->index
!= b
->index
))
1863 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1864 The base register is put in *PBASE.
1865 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1867 The register stride (minus one) is put in bit 4 of the return value.
1868 Bits [6:5] encode the list length (minus one).
1869 The type of the list elements is put in *ELTYPE, if non-NULL. */
1871 #define NEON_LANE(X) ((X) & 0xf)
1872 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1873 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1876 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1877 struct neon_type_el
*eltype
)
1884 int leading_brace
= 0;
1885 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1886 const char *const incr_error
= _("register stride must be 1 or 2");
1887 const char *const type_error
= _("mismatched element/structure types in list");
1888 struct neon_typed_alias firsttype
;
1890 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1895 struct neon_typed_alias atype
;
1896 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1900 first_error (_(reg_expected_msgs
[rtype
]));
1907 if (rtype
== REG_TYPE_NQ
)
1913 else if (reg_incr
== -1)
1915 reg_incr
= getreg
- base_reg
;
1916 if (reg_incr
< 1 || reg_incr
> 2)
1918 first_error (_(incr_error
));
1922 else if (getreg
!= base_reg
+ reg_incr
* count
)
1924 first_error (_(incr_error
));
1928 if (! neon_alias_types_same (&atype
, &firsttype
))
1930 first_error (_(type_error
));
1934 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1938 struct neon_typed_alias htype
;
1939 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1941 lane
= NEON_INTERLEAVE_LANES
;
1942 else if (lane
!= NEON_INTERLEAVE_LANES
)
1944 first_error (_(type_error
));
1949 else if (reg_incr
!= 1)
1951 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1955 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1958 first_error (_(reg_expected_msgs
[rtype
]));
1961 if (! neon_alias_types_same (&htype
, &firsttype
))
1963 first_error (_(type_error
));
1966 count
+= hireg
+ dregs
- getreg
;
1970 /* If we're using Q registers, we can't use [] or [n] syntax. */
1971 if (rtype
== REG_TYPE_NQ
)
1977 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1981 else if (lane
!= atype
.index
)
1983 first_error (_(type_error
));
1987 else if (lane
== -1)
1988 lane
= NEON_INTERLEAVE_LANES
;
1989 else if (lane
!= NEON_INTERLEAVE_LANES
)
1991 first_error (_(type_error
));
1996 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1998 /* No lane set by [x]. We must be interleaving structures. */
2000 lane
= NEON_INTERLEAVE_LANES
;
2003 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2004 || (count
> 1 && reg_incr
== -1))
2006 first_error (_("error parsing element/structure list"));
2010 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2012 first_error (_("expected }"));
2020 *eltype
= firsttype
.eltype
;
2025 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2028 /* Parse an explicit relocation suffix on an expression. This is
2029 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2030 arm_reloc_hsh contains no entries, so this function can only
2031 succeed if there is no () after the word. Returns -1 on error,
2032 BFD_RELOC_UNUSED if there wasn't any suffix. */
2034 parse_reloc (char **str
)
2036 struct reloc_entry
*r
;
2040 return BFD_RELOC_UNUSED
;
2045 while (*q
&& *q
!= ')' && *q
!= ',')
2050 if ((r
= (struct reloc_entry
*)
2051 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2058 /* Directives: register aliases. */
2060 static struct reg_entry
*
2061 insert_reg_alias (char *str
, int number
, int type
)
2063 struct reg_entry
*new_reg
;
2066 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2068 if (new_reg
->builtin
)
2069 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2071 /* Only warn about a redefinition if it's not defined as the
2073 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2074 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2079 name
= xstrdup (str
);
2080 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2082 new_reg
->name
= name
;
2083 new_reg
->number
= number
;
2084 new_reg
->type
= type
;
2085 new_reg
->builtin
= FALSE
;
2086 new_reg
->neon
= NULL
;
2088 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2095 insert_neon_reg_alias (char *str
, int number
, int type
,
2096 struct neon_typed_alias
*atype
)
2098 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2102 first_error (_("attempt to redefine typed alias"));
2108 reg
->neon
= (struct neon_typed_alias
*)
2109 xmalloc (sizeof (struct neon_typed_alias
));
2110 *reg
->neon
= *atype
;
2114 /* Look for the .req directive. This is of the form:
2116 new_register_name .req existing_register_name
2118 If we find one, or if it looks sufficiently like one that we want to
2119 handle any error here, return TRUE. Otherwise return FALSE. */
2122 create_register_alias (char * newname
, char *p
)
2124 struct reg_entry
*old
;
2125 char *oldname
, *nbuf
;
2128 /* The input scrubber ensures that whitespace after the mnemonic is
2129 collapsed to single spaces. */
2131 if (strncmp (oldname
, " .req ", 6) != 0)
2135 if (*oldname
== '\0')
2138 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2141 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2145 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2146 the desired alias name, and p points to its end. If not, then
2147 the desired alias name is in the global original_case_string. */
2148 #ifdef TC_CASE_SENSITIVE
2151 newname
= original_case_string
;
2152 nlen
= strlen (newname
);
2155 nbuf
= (char *) alloca (nlen
+ 1);
2156 memcpy (nbuf
, newname
, nlen
);
2159 /* Create aliases under the new name as stated; an all-lowercase
2160 version of the new name; and an all-uppercase version of the new
2162 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2164 for (p
= nbuf
; *p
; p
++)
2167 if (strncmp (nbuf
, newname
, nlen
))
2169 /* If this attempt to create an additional alias fails, do not bother
2170 trying to create the all-lower case alias. We will fail and issue
2171 a second, duplicate error message. This situation arises when the
2172 programmer does something like:
2175 The second .req creates the "Foo" alias but then fails to create
2176 the artificial FOO alias because it has already been created by the
2178 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2182 for (p
= nbuf
; *p
; p
++)
2185 if (strncmp (nbuf
, newname
, nlen
))
2186 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2192 /* Create a Neon typed/indexed register alias using directives, e.g.:
2197 These typed registers can be used instead of the types specified after the
2198 Neon mnemonic, so long as all operands given have types. Types can also be
2199 specified directly, e.g.:
2200 vadd d0.s32, d1.s32, d2.s32 */
2203 create_neon_reg_alias (char *newname
, char *p
)
2205 enum arm_reg_type basetype
;
2206 struct reg_entry
*basereg
;
2207 struct reg_entry mybasereg
;
2208 struct neon_type ntype
;
2209 struct neon_typed_alias typeinfo
;
2210 char *namebuf
, *nameend
;
2213 typeinfo
.defined
= 0;
2214 typeinfo
.eltype
.type
= NT_invtype
;
2215 typeinfo
.eltype
.size
= -1;
2216 typeinfo
.index
= -1;
2220 if (strncmp (p
, " .dn ", 5) == 0)
2221 basetype
= REG_TYPE_VFD
;
2222 else if (strncmp (p
, " .qn ", 5) == 0)
2223 basetype
= REG_TYPE_NQ
;
2232 basereg
= arm_reg_parse_multi (&p
);
2234 if (basereg
&& basereg
->type
!= basetype
)
2236 as_bad (_("bad type for register"));
2240 if (basereg
== NULL
)
2243 /* Try parsing as an integer. */
2244 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2245 if (exp
.X_op
!= O_constant
)
2247 as_bad (_("expression must be constant"));
2250 basereg
= &mybasereg
;
2251 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2257 typeinfo
= *basereg
->neon
;
2259 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2261 /* We got a type. */
2262 if (typeinfo
.defined
& NTA_HASTYPE
)
2264 as_bad (_("can't redefine the type of a register alias"));
2268 typeinfo
.defined
|= NTA_HASTYPE
;
2269 if (ntype
.elems
!= 1)
2271 as_bad (_("you must specify a single type only"));
2274 typeinfo
.eltype
= ntype
.el
[0];
2277 if (skip_past_char (&p
, '[') == SUCCESS
)
2280 /* We got a scalar index. */
2282 if (typeinfo
.defined
& NTA_HASINDEX
)
2284 as_bad (_("can't redefine the index of a scalar alias"));
2288 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2290 if (exp
.X_op
!= O_constant
)
2292 as_bad (_("scalar index must be constant"));
2296 typeinfo
.defined
|= NTA_HASINDEX
;
2297 typeinfo
.index
= exp
.X_add_number
;
2299 if (skip_past_char (&p
, ']') == FAIL
)
2301 as_bad (_("expecting ]"));
2306 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2307 the desired alias name, and p points to its end. If not, then
2308 the desired alias name is in the global original_case_string. */
2309 #ifdef TC_CASE_SENSITIVE
2310 namelen
= nameend
- newname
;
2312 newname
= original_case_string
;
2313 namelen
= strlen (newname
);
2316 namebuf
= (char *) alloca (namelen
+ 1);
2317 strncpy (namebuf
, newname
, namelen
);
2318 namebuf
[namelen
] = '\0';
2320 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2321 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2323 /* Insert name in all uppercase. */
2324 for (p
= namebuf
; *p
; p
++)
2327 if (strncmp (namebuf
, newname
, namelen
))
2328 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2329 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2331 /* Insert name in all lowercase. */
2332 for (p
= namebuf
; *p
; p
++)
2335 if (strncmp (namebuf
, newname
, namelen
))
2336 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2337 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2342 /* Should never be called, as .req goes between the alias and the
2343 register name, not at the beginning of the line. */
2346 s_req (int a ATTRIBUTE_UNUSED
)
2348 as_bad (_("invalid syntax for .req directive"));
2352 s_dn (int a ATTRIBUTE_UNUSED
)
2354 as_bad (_("invalid syntax for .dn directive"));
2358 s_qn (int a ATTRIBUTE_UNUSED
)
2360 as_bad (_("invalid syntax for .qn directive"));
2363 /* The .unreq directive deletes an alias which was previously defined
2364 by .req. For example:
2370 s_unreq (int a ATTRIBUTE_UNUSED
)
2375 name
= input_line_pointer
;
2377 while (*input_line_pointer
!= 0
2378 && *input_line_pointer
!= ' '
2379 && *input_line_pointer
!= '\n')
2380 ++input_line_pointer
;
2382 saved_char
= *input_line_pointer
;
2383 *input_line_pointer
= 0;
2386 as_bad (_("invalid syntax for .unreq directive"));
2389 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2393 as_bad (_("unknown register alias '%s'"), name
);
2394 else if (reg
->builtin
)
2395 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2402 hash_delete (arm_reg_hsh
, name
, FALSE
);
2403 free ((char *) reg
->name
);
2408 /* Also locate the all upper case and all lower case versions.
2409 Do not complain if we cannot find one or the other as it
2410 was probably deleted above. */
2412 nbuf
= strdup (name
);
2413 for (p
= nbuf
; *p
; p
++)
2415 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2418 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2419 free ((char *) reg
->name
);
2425 for (p
= nbuf
; *p
; p
++)
2427 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2430 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2431 free ((char *) reg
->name
);
2441 *input_line_pointer
= saved_char
;
2442 demand_empty_rest_of_line ();
2445 /* Directives: Instruction set selection. */
2448 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2449 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2450 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2451 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2453 /* Create a new mapping symbol for the transition to STATE. */
2456 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2459 const char * symname
;
2466 type
= BSF_NO_FLAGS
;
2470 type
= BSF_NO_FLAGS
;
2474 type
= BSF_NO_FLAGS
;
2480 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2481 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2486 THUMB_SET_FUNC (symbolP
, 0);
2487 ARM_SET_THUMB (symbolP
, 0);
2488 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2492 THUMB_SET_FUNC (symbolP
, 1);
2493 ARM_SET_THUMB (symbolP
, 1);
2494 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2502 /* Save the mapping symbols for future reference. Also check that
2503 we do not place two mapping symbols at the same offset within a
2504 frag. We'll handle overlap between frags in
2505 check_mapping_symbols.
2507 If .fill or other data filling directive generates zero sized data,
2508 the mapping symbol for the following code will have the same value
2509 as the one generated for the data filling directive. In this case,
2510 we replace the old symbol with the new one at the same address. */
2513 if (frag
->tc_frag_data
.first_map
!= NULL
)
2515 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2516 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2518 frag
->tc_frag_data
.first_map
= symbolP
;
2520 if (frag
->tc_frag_data
.last_map
!= NULL
)
2522 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2523 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2524 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2526 frag
->tc_frag_data
.last_map
= symbolP
;
2529 /* We must sometimes convert a region marked as code to data during
2530 code alignment, if an odd number of bytes have to be padded. The
2531 code mapping symbol is pushed to an aligned address. */
2534 insert_data_mapping_symbol (enum mstate state
,
2535 valueT value
, fragS
*frag
, offsetT bytes
)
2537 /* If there was already a mapping symbol, remove it. */
2538 if (frag
->tc_frag_data
.last_map
!= NULL
2539 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2541 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2545 know (frag
->tc_frag_data
.first_map
== symp
);
2546 frag
->tc_frag_data
.first_map
= NULL
;
2548 frag
->tc_frag_data
.last_map
= NULL
;
2549 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2552 make_mapping_symbol (MAP_DATA
, value
, frag
);
2553 make_mapping_symbol (state
, value
+ bytes
, frag
);
2556 static void mapping_state_2 (enum mstate state
, int max_chars
);
2558 /* Set the mapping state to STATE. Only call this when about to
2559 emit some STATE bytes to the file. */
2562 mapping_state (enum mstate state
)
2564 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2566 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2568 if (mapstate
== state
)
2569 /* The mapping symbol has already been emitted.
2570 There is nothing else to do. */
2572 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2573 /* This case will be evaluated later in the next else. */
2575 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2576 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2578 /* Only add the symbol if the offset is > 0:
2579 if we're at the first frag, check it's size > 0;
2580 if we're not at the first frag, then for sure
2581 the offset is > 0. */
2582 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2583 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2586 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2589 mapping_state_2 (state
, 0);
2593 /* Same as mapping_state, but MAX_CHARS bytes have already been
2594 allocated. Put the mapping symbol that far back. */
2597 mapping_state_2 (enum mstate state
, int max_chars
)
2599 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2601 if (!SEG_NORMAL (now_seg
))
2604 if (mapstate
== state
)
2605 /* The mapping symbol has already been emitted.
2606 There is nothing else to do. */
2609 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2610 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2613 #define mapping_state(x) ((void)0)
2614 #define mapping_state_2(x, y) ((void)0)
2617 /* Find the real, Thumb encoded start of a Thumb function. */
2621 find_real_start (symbolS
* symbolP
)
2624 const char * name
= S_GET_NAME (symbolP
);
2625 symbolS
* new_target
;
2627 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2628 #define STUB_NAME ".real_start_of"
2633 /* The compiler may generate BL instructions to local labels because
2634 it needs to perform a branch to a far away location. These labels
2635 do not have a corresponding ".real_start_of" label. We check
2636 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2637 the ".real_start_of" convention for nonlocal branches. */
2638 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2641 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2642 new_target
= symbol_find (real_start
);
2644 if (new_target
== NULL
)
2646 as_warn (_("Failed to find real start of function: %s\n"), name
);
2647 new_target
= symbolP
;
2655 opcode_select (int width
)
2662 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2663 as_bad (_("selected processor does not support THUMB opcodes"));
2666 /* No need to force the alignment, since we will have been
2667 coming from ARM mode, which is word-aligned. */
2668 record_alignment (now_seg
, 1);
2675 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2676 as_bad (_("selected processor does not support ARM opcodes"));
2681 frag_align (2, 0, 0);
2683 record_alignment (now_seg
, 1);
2688 as_bad (_("invalid instruction size selected (%d)"), width
);
2693 s_arm (int ignore ATTRIBUTE_UNUSED
)
2696 demand_empty_rest_of_line ();
2700 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2703 demand_empty_rest_of_line ();
2707 s_code (int unused ATTRIBUTE_UNUSED
)
2711 temp
= get_absolute_expression ();
2716 opcode_select (temp
);
2720 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2725 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2727 /* If we are not already in thumb mode go into it, EVEN if
2728 the target processor does not support thumb instructions.
2729 This is used by gcc/config/arm/lib1funcs.asm for example
2730 to compile interworking support functions even if the
2731 target processor should not support interworking. */
2735 record_alignment (now_seg
, 1);
2738 demand_empty_rest_of_line ();
2742 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2746 /* The following label is the name/address of the start of a Thumb function.
2747 We need to know this for the interworking support. */
2748 label_is_thumb_function_name
= TRUE
;
2751 /* Perform a .set directive, but also mark the alias as
2752 being a thumb function. */
2755 s_thumb_set (int equiv
)
2757 /* XXX the following is a duplicate of the code for s_set() in read.c
2758 We cannot just call that code as we need to get at the symbol that
2765 /* Especial apologies for the random logic:
2766 This just grew, and could be parsed much more simply!
2768 name
= input_line_pointer
;
2769 delim
= get_symbol_end ();
2770 end_name
= input_line_pointer
;
2773 if (*input_line_pointer
!= ',')
2776 as_bad (_("expected comma after name \"%s\""), name
);
2778 ignore_rest_of_line ();
2782 input_line_pointer
++;
2785 if (name
[0] == '.' && name
[1] == '\0')
2787 /* XXX - this should not happen to .thumb_set. */
2791 if ((symbolP
= symbol_find (name
)) == NULL
2792 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2795 /* When doing symbol listings, play games with dummy fragments living
2796 outside the normal fragment chain to record the file and line info
2798 if (listing
& LISTING_SYMBOLS
)
2800 extern struct list_info_struct
* listing_tail
;
2801 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2803 memset (dummy_frag
, 0, sizeof (fragS
));
2804 dummy_frag
->fr_type
= rs_fill
;
2805 dummy_frag
->line
= listing_tail
;
2806 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2807 dummy_frag
->fr_symbol
= symbolP
;
2811 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2814 /* "set" symbols are local unless otherwise specified. */
2815 SF_SET_LOCAL (symbolP
);
2816 #endif /* OBJ_COFF */
2817 } /* Make a new symbol. */
2819 symbol_table_insert (symbolP
);
2824 && S_IS_DEFINED (symbolP
)
2825 && S_GET_SEGMENT (symbolP
) != reg_section
)
2826 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2828 pseudo_set (symbolP
);
2830 demand_empty_rest_of_line ();
2832 /* XXX Now we come to the Thumb specific bit of code. */
2834 THUMB_SET_FUNC (symbolP
, 1);
2835 ARM_SET_THUMB (symbolP
, 1);
2836 #if defined OBJ_ELF || defined OBJ_COFF
2837 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2841 /* Directives: Mode selection. */
2843 /* .syntax [unified|divided] - choose the new unified syntax
2844 (same for Arm and Thumb encoding, modulo slight differences in what
2845 can be represented) or the old divergent syntax for each mode. */
2847 s_syntax (int unused ATTRIBUTE_UNUSED
)
2851 name
= input_line_pointer
;
2852 delim
= get_symbol_end ();
2854 if (!strcasecmp (name
, "unified"))
2855 unified_syntax
= TRUE
;
2856 else if (!strcasecmp (name
, "divided"))
2857 unified_syntax
= FALSE
;
2860 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2863 *input_line_pointer
= delim
;
2864 demand_empty_rest_of_line ();
2867 /* Directives: sectioning and alignment. */
2869 /* Same as s_align_ptwo but align 0 => align 2. */
2872 s_align (int unused ATTRIBUTE_UNUSED
)
2877 long max_alignment
= 15;
2879 temp
= get_absolute_expression ();
2880 if (temp
> max_alignment
)
2881 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2884 as_bad (_("alignment negative. 0 assumed."));
2888 if (*input_line_pointer
== ',')
2890 input_line_pointer
++;
2891 temp_fill
= get_absolute_expression ();
2903 /* Only make a frag if we HAVE to. */
2904 if (temp
&& !need_pass_2
)
2906 if (!fill_p
&& subseg_text_p (now_seg
))
2907 frag_align_code (temp
, 0);
2909 frag_align (temp
, (int) temp_fill
, 0);
2911 demand_empty_rest_of_line ();
2913 record_alignment (now_seg
, temp
);
2917 s_bss (int ignore ATTRIBUTE_UNUSED
)
2919 /* We don't support putting frags in the BSS segment, we fake it by
2920 marking in_bss, then looking at s_skip for clues. */
2921 subseg_set (bss_section
, 0);
2922 demand_empty_rest_of_line ();
2924 #ifdef md_elf_section_change_hook
2925 md_elf_section_change_hook ();
2930 s_even (int ignore ATTRIBUTE_UNUSED
)
2932 /* Never make frag if expect extra pass. */
2934 frag_align (1, 0, 0);
2936 record_alignment (now_seg
, 1);
2938 demand_empty_rest_of_line ();
2941 /* Directives: Literal pools. */
2943 static literal_pool
*
2944 find_literal_pool (void)
2946 literal_pool
* pool
;
2948 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2950 if (pool
->section
== now_seg
2951 && pool
->sub_section
== now_subseg
)
2958 static literal_pool
*
2959 find_or_make_literal_pool (void)
2961 /* Next literal pool ID number. */
2962 static unsigned int latest_pool_num
= 1;
2963 literal_pool
* pool
;
2965 pool
= find_literal_pool ();
2969 /* Create a new pool. */
2970 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2974 pool
->next_free_entry
= 0;
2975 pool
->section
= now_seg
;
2976 pool
->sub_section
= now_subseg
;
2977 pool
->next
= list_of_pools
;
2978 pool
->symbol
= NULL
;
2980 /* Add it to the list. */
2981 list_of_pools
= pool
;
2984 /* New pools, and emptied pools, will have a NULL symbol. */
2985 if (pool
->symbol
== NULL
)
2987 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2988 (valueT
) 0, &zero_address_frag
);
2989 pool
->id
= latest_pool_num
++;
2996 /* Add the literal in the global 'inst'
2997 structure to the relevant literal pool. */
3000 add_to_lit_pool (void)
3002 literal_pool
* pool
;
3005 pool
= find_or_make_literal_pool ();
3007 /* Check if this literal value is already in the pool. */
3008 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3010 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3011 && (inst
.reloc
.exp
.X_op
== O_constant
)
3012 && (pool
->literals
[entry
].X_add_number
3013 == inst
.reloc
.exp
.X_add_number
)
3014 && (pool
->literals
[entry
].X_unsigned
3015 == inst
.reloc
.exp
.X_unsigned
))
3018 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3019 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3020 && (pool
->literals
[entry
].X_add_number
3021 == inst
.reloc
.exp
.X_add_number
)
3022 && (pool
->literals
[entry
].X_add_symbol
3023 == inst
.reloc
.exp
.X_add_symbol
)
3024 && (pool
->literals
[entry
].X_op_symbol
3025 == inst
.reloc
.exp
.X_op_symbol
))
3029 /* Do we need to create a new entry? */
3030 if (entry
== pool
->next_free_entry
)
3032 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3034 inst
.error
= _("literal pool overflow");
3038 pool
->literals
[entry
] = inst
.reloc
.exp
;
3039 pool
->next_free_entry
+= 1;
3042 inst
.reloc
.exp
.X_op
= O_symbol
;
3043 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3044 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3049 /* Can't use symbol_new here, so have to create a symbol and then at
3050 a later date assign it a value. Thats what these functions do. */
3053 symbol_locate (symbolS
* symbolP
,
3054 const char * name
, /* It is copied, the caller can modify. */
3055 segT segment
, /* Segment identifier (SEG_<something>). */
3056 valueT valu
, /* Symbol value. */
3057 fragS
* frag
) /* Associated fragment. */
3059 unsigned int name_length
;
3060 char * preserved_copy_of_name
;
3062 name_length
= strlen (name
) + 1; /* +1 for \0. */
3063 obstack_grow (¬es
, name
, name_length
);
3064 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3066 #ifdef tc_canonicalize_symbol_name
3067 preserved_copy_of_name
=
3068 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3071 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3073 S_SET_SEGMENT (symbolP
, segment
);
3074 S_SET_VALUE (symbolP
, valu
);
3075 symbol_clear_list_pointers (symbolP
);
3077 symbol_set_frag (symbolP
, frag
);
3079 /* Link to end of symbol chain. */
3081 extern int symbol_table_frozen
;
3083 if (symbol_table_frozen
)
3087 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3089 obj_symbol_new_hook (symbolP
);
3091 #ifdef tc_symbol_new_hook
3092 tc_symbol_new_hook (symbolP
);
3096 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3097 #endif /* DEBUG_SYMS */
3102 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3105 literal_pool
* pool
;
3108 pool
= find_literal_pool ();
3110 || pool
->symbol
== NULL
3111 || pool
->next_free_entry
== 0)
3114 mapping_state (MAP_DATA
);
3116 /* Align pool as you have word accesses.
3117 Only make a frag if we have to. */
3119 frag_align (2, 0, 0);
3121 record_alignment (now_seg
, 2);
3123 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3125 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3126 (valueT
) frag_now_fix (), frag_now
);
3127 symbol_table_insert (pool
->symbol
);
3129 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3131 #if defined OBJ_COFF || defined OBJ_ELF
3132 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3135 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3136 /* First output the expression in the instruction to the pool. */
3137 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3139 /* Mark the pool as empty. */
3140 pool
->next_free_entry
= 0;
3141 pool
->symbol
= NULL
;
3145 /* Forward declarations for functions below, in the MD interface
3147 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3148 static valueT
create_unwind_entry (int);
3149 static void start_unwind_section (const segT
, int);
3150 static void add_unwind_opcode (valueT
, int);
3151 static void flush_pending_unwind (void);
3153 /* Directives: Data. */
3156 s_arm_elf_cons (int nbytes
)
3160 #ifdef md_flush_pending_output
3161 md_flush_pending_output ();
3164 if (is_it_end_of_statement ())
3166 demand_empty_rest_of_line ();
3170 #ifdef md_cons_align
3171 md_cons_align (nbytes
);
3174 mapping_state (MAP_DATA
);
3178 char *base
= input_line_pointer
;
3182 if (exp
.X_op
!= O_symbol
)
3183 emit_expr (&exp
, (unsigned int) nbytes
);
3186 char *before_reloc
= input_line_pointer
;
3187 reloc
= parse_reloc (&input_line_pointer
);
3190 as_bad (_("unrecognized relocation suffix"));
3191 ignore_rest_of_line ();
3194 else if (reloc
== BFD_RELOC_UNUSED
)
3195 emit_expr (&exp
, (unsigned int) nbytes
);
3198 reloc_howto_type
*howto
= (reloc_howto_type
*)
3199 bfd_reloc_type_lookup (stdoutput
,
3200 (bfd_reloc_code_real_type
) reloc
);
3201 int size
= bfd_get_reloc_size (howto
);
3203 if (reloc
== BFD_RELOC_ARM_PLT32
)
3205 as_bad (_("(plt) is only valid on branch targets"));
3206 reloc
= BFD_RELOC_UNUSED
;
3211 as_bad (_("%s relocations do not fit in %d bytes"),
3212 howto
->name
, nbytes
);
3215 /* We've parsed an expression stopping at O_symbol.
3216 But there may be more expression left now that we
3217 have parsed the relocation marker. Parse it again.
3218 XXX Surely there is a cleaner way to do this. */
3219 char *p
= input_line_pointer
;
3221 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3222 memcpy (save_buf
, base
, input_line_pointer
- base
);
3223 memmove (base
+ (input_line_pointer
- before_reloc
),
3224 base
, before_reloc
- base
);
3226 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3228 memcpy (base
, save_buf
, p
- base
);
3230 offset
= nbytes
- size
;
3231 p
= frag_more ((int) nbytes
);
3232 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3233 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3238 while (*input_line_pointer
++ == ',');
3240 /* Put terminator back into stream. */
3241 input_line_pointer
--;
3242 demand_empty_rest_of_line ();
3245 /* Emit an expression containing a 32-bit thumb instruction.
3246 Implementation based on put_thumb32_insn. */
3249 emit_thumb32_expr (expressionS
* exp
)
3251 expressionS exp_high
= *exp
;
3253 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3254 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3255 exp
->X_add_number
&= 0xffff;
3256 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3259 /* Guess the instruction size based on the opcode. */
3262 thumb_insn_size (int opcode
)
3264 if ((unsigned int) opcode
< 0xe800u
)
3266 else if ((unsigned int) opcode
>= 0xe8000000u
)
3273 emit_insn (expressionS
*exp
, int nbytes
)
3277 if (exp
->X_op
== O_constant
)
3282 size
= thumb_insn_size (exp
->X_add_number
);
3286 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3288 as_bad (_(".inst.n operand too big. "\
3289 "Use .inst.w instead"));
3294 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3295 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3297 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3299 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3300 emit_thumb32_expr (exp
);
3302 emit_expr (exp
, (unsigned int) size
);
3304 it_fsm_post_encode ();
3308 as_bad (_("cannot determine Thumb instruction size. " \
3309 "Use .inst.n/.inst.w instead"));
3312 as_bad (_("constant expression required"));
3317 /* Like s_arm_elf_cons but do not use md_cons_align and
3318 set the mapping state to MAP_ARM/MAP_THUMB. */
3321 s_arm_elf_inst (int nbytes
)
3323 if (is_it_end_of_statement ())
3325 demand_empty_rest_of_line ();
3329 /* Calling mapping_state () here will not change ARM/THUMB,
3330 but will ensure not to be in DATA state. */
3333 mapping_state (MAP_THUMB
);
3338 as_bad (_("width suffixes are invalid in ARM mode"));
3339 ignore_rest_of_line ();
3345 mapping_state (MAP_ARM
);
3354 if (! emit_insn (& exp
, nbytes
))
3356 ignore_rest_of_line ();
3360 while (*input_line_pointer
++ == ',');
3362 /* Put terminator back into stream. */
3363 input_line_pointer
--;
3364 demand_empty_rest_of_line ();
3367 /* Parse a .rel31 directive. */
3370 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3377 if (*input_line_pointer
== '1')
3378 highbit
= 0x80000000;
3379 else if (*input_line_pointer
!= '0')
3380 as_bad (_("expected 0 or 1"));
3382 input_line_pointer
++;
3383 if (*input_line_pointer
!= ',')
3384 as_bad (_("missing comma"));
3385 input_line_pointer
++;
3387 #ifdef md_flush_pending_output
3388 md_flush_pending_output ();
3391 #ifdef md_cons_align
3395 mapping_state (MAP_DATA
);
3400 md_number_to_chars (p
, highbit
, 4);
3401 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3402 BFD_RELOC_ARM_PREL31
);
3404 demand_empty_rest_of_line ();
3407 /* Directives: AEABI stack-unwind tables. */
3409 /* Parse an unwind_fnstart directive. Simply records the current location. */
3412 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3414 demand_empty_rest_of_line ();
3415 if (unwind
.proc_start
)
3417 as_bad (_("duplicate .fnstart directive"));
3421 /* Mark the start of the function. */
3422 unwind
.proc_start
= expr_build_dot ();
3424 /* Reset the rest of the unwind info. */
3425 unwind
.opcode_count
= 0;
3426 unwind
.table_entry
= NULL
;
3427 unwind
.personality_routine
= NULL
;
3428 unwind
.personality_index
= -1;
3429 unwind
.frame_size
= 0;
3430 unwind
.fp_offset
= 0;
3431 unwind
.fp_reg
= REG_SP
;
3433 unwind
.sp_restored
= 0;
3437 /* Parse a handlerdata directive. Creates the exception handling table entry
3438 for the function. */
3441 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3443 demand_empty_rest_of_line ();
3444 if (!unwind
.proc_start
)
3445 as_bad (MISSING_FNSTART
);
3447 if (unwind
.table_entry
)
3448 as_bad (_("duplicate .handlerdata directive"));
3450 create_unwind_entry (1);
3453 /* Parse an unwind_fnend directive. Generates the index table entry. */
3456 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3461 unsigned int marked_pr_dependency
;
3463 demand_empty_rest_of_line ();
3465 if (!unwind
.proc_start
)
3467 as_bad (_(".fnend directive without .fnstart"));
3471 /* Add eh table entry. */
3472 if (unwind
.table_entry
== NULL
)
3473 val
= create_unwind_entry (0);
3477 /* Add index table entry. This is two words. */
3478 start_unwind_section (unwind
.saved_seg
, 1);
3479 frag_align (2, 0, 0);
3480 record_alignment (now_seg
, 2);
3482 ptr
= frag_more (8);
3483 where
= frag_now_fix () - 8;
3485 /* Self relative offset of the function start. */
3486 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3487 BFD_RELOC_ARM_PREL31
);
3489 /* Indicate dependency on EHABI-defined personality routines to the
3490 linker, if it hasn't been done already. */
3491 marked_pr_dependency
3492 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3493 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3494 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3496 static const char *const name
[] =
3498 "__aeabi_unwind_cpp_pr0",
3499 "__aeabi_unwind_cpp_pr1",
3500 "__aeabi_unwind_cpp_pr2"
3502 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3503 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3504 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3505 |= 1 << unwind
.personality_index
;
3509 /* Inline exception table entry. */
3510 md_number_to_chars (ptr
+ 4, val
, 4);
3512 /* Self relative offset of the table entry. */
3513 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3514 BFD_RELOC_ARM_PREL31
);
3516 /* Restore the original section. */
3517 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3519 unwind
.proc_start
= NULL
;
3523 /* Parse an unwind_cantunwind directive. */
3526 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3528 demand_empty_rest_of_line ();
3529 if (!unwind
.proc_start
)
3530 as_bad (MISSING_FNSTART
);
3532 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3533 as_bad (_("personality routine specified for cantunwind frame"));
3535 unwind
.personality_index
= -2;
3539 /* Parse a personalityindex directive. */
3542 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3546 if (!unwind
.proc_start
)
3547 as_bad (MISSING_FNSTART
);
3549 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3550 as_bad (_("duplicate .personalityindex directive"));
3554 if (exp
.X_op
!= O_constant
3555 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3557 as_bad (_("bad personality routine number"));
3558 ignore_rest_of_line ();
3562 unwind
.personality_index
= exp
.X_add_number
;
3564 demand_empty_rest_of_line ();
3568 /* Parse a personality directive. */
3571 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3575 if (!unwind
.proc_start
)
3576 as_bad (MISSING_FNSTART
);
3578 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3579 as_bad (_("duplicate .personality directive"));
3581 name
= input_line_pointer
;
3582 c
= get_symbol_end ();
3583 p
= input_line_pointer
;
3584 unwind
.personality_routine
= symbol_find_or_make (name
);
3586 demand_empty_rest_of_line ();
3590 /* Parse a directive saving core registers. */
3593 s_arm_unwind_save_core (void)
3599 range
= parse_reg_list (&input_line_pointer
);
3602 as_bad (_("expected register list"));
3603 ignore_rest_of_line ();
3607 demand_empty_rest_of_line ();
3609 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3610 into .unwind_save {..., sp...}. We aren't bothered about the value of
3611 ip because it is clobbered by calls. */
3612 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3613 && (range
& 0x3000) == 0x1000)
3615 unwind
.opcode_count
--;
3616 unwind
.sp_restored
= 0;
3617 range
= (range
| 0x2000) & ~0x1000;
3618 unwind
.pending_offset
= 0;
3624 /* See if we can use the short opcodes. These pop a block of up to 8
3625 registers starting with r4, plus maybe r14. */
3626 for (n
= 0; n
< 8; n
++)
3628 /* Break at the first non-saved register. */
3629 if ((range
& (1 << (n
+ 4))) == 0)
3632 /* See if there are any other bits set. */
3633 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3635 /* Use the long form. */
3636 op
= 0x8000 | ((range
>> 4) & 0xfff);
3637 add_unwind_opcode (op
, 2);
3641 /* Use the short form. */
3643 op
= 0xa8; /* Pop r14. */
3645 op
= 0xa0; /* Do not pop r14. */
3647 add_unwind_opcode (op
, 1);
3654 op
= 0xb100 | (range
& 0xf);
3655 add_unwind_opcode (op
, 2);
3658 /* Record the number of bytes pushed. */
3659 for (n
= 0; n
< 16; n
++)
3661 if (range
& (1 << n
))
3662 unwind
.frame_size
+= 4;
3667 /* Parse a directive saving FPA registers. */
3670 s_arm_unwind_save_fpa (int reg
)
3676 /* Get Number of registers to transfer. */
3677 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3680 exp
.X_op
= O_illegal
;
3682 if (exp
.X_op
!= O_constant
)
3684 as_bad (_("expected , <constant>"));
3685 ignore_rest_of_line ();
3689 num_regs
= exp
.X_add_number
;
3691 if (num_regs
< 1 || num_regs
> 4)
3693 as_bad (_("number of registers must be in the range [1:4]"));
3694 ignore_rest_of_line ();
3698 demand_empty_rest_of_line ();
3703 op
= 0xb4 | (num_regs
- 1);
3704 add_unwind_opcode (op
, 1);
3709 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3710 add_unwind_opcode (op
, 2);
3712 unwind
.frame_size
+= num_regs
* 12;
3716 /* Parse a directive saving VFP registers for ARMv6 and above. */
3719 s_arm_unwind_save_vfp_armv6 (void)
3724 int num_vfpv3_regs
= 0;
3725 int num_regs_below_16
;
3727 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3730 as_bad (_("expected register list"));
3731 ignore_rest_of_line ();
3735 demand_empty_rest_of_line ();
3737 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3738 than FSTMX/FLDMX-style ones). */
3740 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3742 num_vfpv3_regs
= count
;
3743 else if (start
+ count
> 16)
3744 num_vfpv3_regs
= start
+ count
- 16;
3746 if (num_vfpv3_regs
> 0)
3748 int start_offset
= start
> 16 ? start
- 16 : 0;
3749 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3750 add_unwind_opcode (op
, 2);
3753 /* Generate opcode for registers numbered in the range 0 .. 15. */
3754 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3755 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3756 if (num_regs_below_16
> 0)
3758 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3759 add_unwind_opcode (op
, 2);
3762 unwind
.frame_size
+= count
* 8;
3766 /* Parse a directive saving VFP registers for pre-ARMv6. */
3769 s_arm_unwind_save_vfp (void)
3775 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3778 as_bad (_("expected register list"));
3779 ignore_rest_of_line ();
3783 demand_empty_rest_of_line ();
3788 op
= 0xb8 | (count
- 1);
3789 add_unwind_opcode (op
, 1);
3794 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3795 add_unwind_opcode (op
, 2);
3797 unwind
.frame_size
+= count
* 8 + 4;
3801 /* Parse a directive saving iWMMXt data registers. */
3804 s_arm_unwind_save_mmxwr (void)
3812 if (*input_line_pointer
== '{')
3813 input_line_pointer
++;
3817 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3821 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3826 as_tsktsk (_("register list not in ascending order"));
3829 if (*input_line_pointer
== '-')
3831 input_line_pointer
++;
3832 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3835 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3838 else if (reg
>= hi_reg
)
3840 as_bad (_("bad register range"));
3843 for (; reg
< hi_reg
; reg
++)
3847 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3849 if (*input_line_pointer
== '}')
3850 input_line_pointer
++;
3852 demand_empty_rest_of_line ();
3854 /* Generate any deferred opcodes because we're going to be looking at
3856 flush_pending_unwind ();
3858 for (i
= 0; i
< 16; i
++)
3860 if (mask
& (1 << i
))
3861 unwind
.frame_size
+= 8;
3864 /* Attempt to combine with a previous opcode. We do this because gcc
3865 likes to output separate unwind directives for a single block of
3867 if (unwind
.opcode_count
> 0)
3869 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3870 if ((i
& 0xf8) == 0xc0)
3873 /* Only merge if the blocks are contiguous. */
3876 if ((mask
& 0xfe00) == (1 << 9))
3878 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3879 unwind
.opcode_count
--;
3882 else if (i
== 6 && unwind
.opcode_count
>= 2)
3884 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3888 op
= 0xffff << (reg
- 1);
3890 && ((mask
& op
) == (1u << (reg
- 1))))
3892 op
= (1 << (reg
+ i
+ 1)) - 1;
3893 op
&= ~((1 << reg
) - 1);
3895 unwind
.opcode_count
-= 2;
3902 /* We want to generate opcodes in the order the registers have been
3903 saved, ie. descending order. */
3904 for (reg
= 15; reg
>= -1; reg
--)
3906 /* Save registers in blocks. */
3908 || !(mask
& (1 << reg
)))
3910 /* We found an unsaved reg. Generate opcodes to save the
3917 op
= 0xc0 | (hi_reg
- 10);
3918 add_unwind_opcode (op
, 1);
3923 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3924 add_unwind_opcode (op
, 2);
3933 ignore_rest_of_line ();
3937 s_arm_unwind_save_mmxwcg (void)
3944 if (*input_line_pointer
== '{')
3945 input_line_pointer
++;
3949 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3953 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3959 as_tsktsk (_("register list not in ascending order"));
3962 if (*input_line_pointer
== '-')
3964 input_line_pointer
++;
3965 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3968 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3971 else if (reg
>= hi_reg
)
3973 as_bad (_("bad register range"));
3976 for (; reg
< hi_reg
; reg
++)
3980 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3982 if (*input_line_pointer
== '}')
3983 input_line_pointer
++;
3985 demand_empty_rest_of_line ();
3987 /* Generate any deferred opcodes because we're going to be looking at
3989 flush_pending_unwind ();
3991 for (reg
= 0; reg
< 16; reg
++)
3993 if (mask
& (1 << reg
))
3994 unwind
.frame_size
+= 4;
3997 add_unwind_opcode (op
, 2);
4000 ignore_rest_of_line ();
4004 /* Parse an unwind_save directive.
4005 If the argument is non-zero, this is a .vsave directive. */
4008 s_arm_unwind_save (int arch_v6
)
4011 struct reg_entry
*reg
;
4012 bfd_boolean had_brace
= FALSE
;
4014 if (!unwind
.proc_start
)
4015 as_bad (MISSING_FNSTART
);
4017 /* Figure out what sort of save we have. */
4018 peek
= input_line_pointer
;
4026 reg
= arm_reg_parse_multi (&peek
);
4030 as_bad (_("register expected"));
4031 ignore_rest_of_line ();
4040 as_bad (_("FPA .unwind_save does not take a register list"));
4041 ignore_rest_of_line ();
4044 input_line_pointer
= peek
;
4045 s_arm_unwind_save_fpa (reg
->number
);
4048 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4051 s_arm_unwind_save_vfp_armv6 ();
4053 s_arm_unwind_save_vfp ();
4055 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4056 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4059 as_bad (_(".unwind_save does not support this kind of register"));
4060 ignore_rest_of_line ();
4065 /* Parse an unwind_movsp directive. */
4068 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4074 if (!unwind
.proc_start
)
4075 as_bad (MISSING_FNSTART
);
4077 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4080 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4081 ignore_rest_of_line ();
4085 /* Optional constant. */
4086 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4088 if (immediate_for_directive (&offset
) == FAIL
)
4094 demand_empty_rest_of_line ();
4096 if (reg
== REG_SP
|| reg
== REG_PC
)
4098 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4102 if (unwind
.fp_reg
!= REG_SP
)
4103 as_bad (_("unexpected .unwind_movsp directive"));
4105 /* Generate opcode to restore the value. */
4107 add_unwind_opcode (op
, 1);
4109 /* Record the information for later. */
4110 unwind
.fp_reg
= reg
;
4111 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4112 unwind
.sp_restored
= 1;
4115 /* Parse an unwind_pad directive. */
4118 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4122 if (!unwind
.proc_start
)
4123 as_bad (MISSING_FNSTART
);
4125 if (immediate_for_directive (&offset
) == FAIL
)
4130 as_bad (_("stack increment must be multiple of 4"));
4131 ignore_rest_of_line ();
4135 /* Don't generate any opcodes, just record the details for later. */
4136 unwind
.frame_size
+= offset
;
4137 unwind
.pending_offset
+= offset
;
4139 demand_empty_rest_of_line ();
4142 /* Parse an unwind_setfp directive. */
4145 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4151 if (!unwind
.proc_start
)
4152 as_bad (MISSING_FNSTART
);
4154 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4155 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4158 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4160 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4162 as_bad (_("expected <reg>, <reg>"));
4163 ignore_rest_of_line ();
4167 /* Optional constant. */
4168 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4170 if (immediate_for_directive (&offset
) == FAIL
)
4176 demand_empty_rest_of_line ();
4178 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4180 as_bad (_("register must be either sp or set by a previous"
4181 "unwind_movsp directive"));
4185 /* Don't generate any opcodes, just record the information for later. */
4186 unwind
.fp_reg
= fp_reg
;
4188 if (sp_reg
== REG_SP
)
4189 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4191 unwind
.fp_offset
-= offset
;
4194 /* Parse an unwind_raw directive. */
4197 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4200 /* This is an arbitrary limit. */
4201 unsigned char op
[16];
4204 if (!unwind
.proc_start
)
4205 as_bad (MISSING_FNSTART
);
4208 if (exp
.X_op
== O_constant
4209 && skip_past_comma (&input_line_pointer
) != FAIL
)
4211 unwind
.frame_size
+= exp
.X_add_number
;
4215 exp
.X_op
= O_illegal
;
4217 if (exp
.X_op
!= O_constant
)
4219 as_bad (_("expected <offset>, <opcode>"));
4220 ignore_rest_of_line ();
4226 /* Parse the opcode. */
4231 as_bad (_("unwind opcode too long"));
4232 ignore_rest_of_line ();
4234 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4236 as_bad (_("invalid unwind opcode"));
4237 ignore_rest_of_line ();
4240 op
[count
++] = exp
.X_add_number
;
4242 /* Parse the next byte. */
4243 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4249 /* Add the opcode bytes in reverse order. */
4251 add_unwind_opcode (op
[count
], 1);
4253 demand_empty_rest_of_line ();
4257 /* Parse a .eabi_attribute directive. */
4260 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4262 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4264 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4265 attributes_set_explicitly
[tag
] = 1;
4267 #endif /* OBJ_ELF */
4269 static void s_arm_arch (int);
4270 static void s_arm_object_arch (int);
4271 static void s_arm_cpu (int);
4272 static void s_arm_fpu (int);
4273 static void s_arm_arch_extension (int);
4278 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4285 if (exp
.X_op
== O_symbol
)
4286 exp
.X_op
= O_secrel
;
4288 emit_expr (&exp
, 4);
4290 while (*input_line_pointer
++ == ',');
4292 input_line_pointer
--;
4293 demand_empty_rest_of_line ();
4297 /* This table describes all the machine specific pseudo-ops the assembler
4298 has to support. The fields are:
4299 pseudo-op name without dot
4300 function to call to execute this pseudo-op
4301 Integer arg to pass to the function. */
4303 const pseudo_typeS md_pseudo_table
[] =
4305 /* Never called because '.req' does not start a line. */
4306 { "req", s_req
, 0 },
4307 /* Following two are likewise never called. */
4310 { "unreq", s_unreq
, 0 },
4311 { "bss", s_bss
, 0 },
4312 { "align", s_align
, 0 },
4313 { "arm", s_arm
, 0 },
4314 { "thumb", s_thumb
, 0 },
4315 { "code", s_code
, 0 },
4316 { "force_thumb", s_force_thumb
, 0 },
4317 { "thumb_func", s_thumb_func
, 0 },
4318 { "thumb_set", s_thumb_set
, 0 },
4319 { "even", s_even
, 0 },
4320 { "ltorg", s_ltorg
, 0 },
4321 { "pool", s_ltorg
, 0 },
4322 { "syntax", s_syntax
, 0 },
4323 { "cpu", s_arm_cpu
, 0 },
4324 { "arch", s_arm_arch
, 0 },
4325 { "object_arch", s_arm_object_arch
, 0 },
4326 { "fpu", s_arm_fpu
, 0 },
4327 { "arch_extension", s_arm_arch_extension
, 0 },
4329 { "word", s_arm_elf_cons
, 4 },
4330 { "long", s_arm_elf_cons
, 4 },
4331 { "inst.n", s_arm_elf_inst
, 2 },
4332 { "inst.w", s_arm_elf_inst
, 4 },
4333 { "inst", s_arm_elf_inst
, 0 },
4334 { "rel31", s_arm_rel31
, 0 },
4335 { "fnstart", s_arm_unwind_fnstart
, 0 },
4336 { "fnend", s_arm_unwind_fnend
, 0 },
4337 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4338 { "personality", s_arm_unwind_personality
, 0 },
4339 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4340 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4341 { "save", s_arm_unwind_save
, 0 },
4342 { "vsave", s_arm_unwind_save
, 1 },
4343 { "movsp", s_arm_unwind_movsp
, 0 },
4344 { "pad", s_arm_unwind_pad
, 0 },
4345 { "setfp", s_arm_unwind_setfp
, 0 },
4346 { "unwind_raw", s_arm_unwind_raw
, 0 },
4347 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4351 /* These are used for dwarf. */
4355 /* These are used for dwarf2. */
4356 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4357 { "loc", dwarf2_directive_loc
, 0 },
4358 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4360 { "extend", float_cons
, 'x' },
4361 { "ldouble", float_cons
, 'x' },
4362 { "packed", float_cons
, 'p' },
4364 {"secrel32", pe_directive_secrel
, 0},
4369 /* Parser functions used exclusively in instruction operands. */
4371 /* Generic immediate-value read function for use in insn parsing.
4372 STR points to the beginning of the immediate (the leading #);
4373 VAL receives the value; if the value is outside [MIN, MAX]
4374 issue an error. PREFIX_OPT is true if the immediate prefix is
4378 parse_immediate (char **str
, int *val
, int min
, int max
,
4379 bfd_boolean prefix_opt
)
4382 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4383 if (exp
.X_op
!= O_constant
)
4385 inst
.error
= _("constant expression required");
4389 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4391 inst
.error
= _("immediate value out of range");
4395 *val
= exp
.X_add_number
;
4399 /* Less-generic immediate-value read function with the possibility of loading a
4400 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4401 instructions. Puts the result directly in inst.operands[i]. */
4404 parse_big_immediate (char **str
, int i
)
4409 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4411 if (exp
.X_op
== O_constant
)
4413 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4414 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4415 O_constant. We have to be careful not to break compilation for
4416 32-bit X_add_number, though. */
4417 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4419 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4420 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4421 inst
.operands
[i
].regisimm
= 1;
4424 else if (exp
.X_op
== O_big
4425 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4427 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4429 /* Bignums have their least significant bits in
4430 generic_bignum[0]. Make sure we put 32 bits in imm and
4431 32 bits in reg, in a (hopefully) portable way. */
4432 gas_assert (parts
!= 0);
4434 /* Make sure that the number is not too big.
4435 PR 11972: Bignums can now be sign-extended to the
4436 size of a .octa so check that the out of range bits
4437 are all zero or all one. */
4438 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4440 LITTLENUM_TYPE m
= -1;
4442 if (generic_bignum
[parts
* 2] != 0
4443 && generic_bignum
[parts
* 2] != m
)
4446 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4447 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4451 inst
.operands
[i
].imm
= 0;
4452 for (j
= 0; j
< parts
; j
++, idx
++)
4453 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4454 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4455 inst
.operands
[i
].reg
= 0;
4456 for (j
= 0; j
< parts
; j
++, idx
++)
4457 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4458 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4459 inst
.operands
[i
].regisimm
= 1;
4469 /* Returns the pseudo-register number of an FPA immediate constant,
4470 or FAIL if there isn't a valid constant here. */
4473 parse_fpa_immediate (char ** str
)
4475 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4481 /* First try and match exact strings, this is to guarantee
4482 that some formats will work even for cross assembly. */
4484 for (i
= 0; fp_const
[i
]; i
++)
4486 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4490 *str
+= strlen (fp_const
[i
]);
4491 if (is_end_of_line
[(unsigned char) **str
])
4497 /* Just because we didn't get a match doesn't mean that the constant
4498 isn't valid, just that it is in a format that we don't
4499 automatically recognize. Try parsing it with the standard
4500 expression routines. */
4502 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4504 /* Look for a raw floating point number. */
4505 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4506 && is_end_of_line
[(unsigned char) *save_in
])
4508 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4510 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4512 if (words
[j
] != fp_values
[i
][j
])
4516 if (j
== MAX_LITTLENUMS
)
4524 /* Try and parse a more complex expression, this will probably fail
4525 unless the code uses a floating point prefix (eg "0f"). */
4526 save_in
= input_line_pointer
;
4527 input_line_pointer
= *str
;
4528 if (expression (&exp
) == absolute_section
4529 && exp
.X_op
== O_big
4530 && exp
.X_add_number
< 0)
4532 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4534 if (gen_to_words (words
, 5, (long) 15) == 0)
4536 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4538 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4540 if (words
[j
] != fp_values
[i
][j
])
4544 if (j
== MAX_LITTLENUMS
)
4546 *str
= input_line_pointer
;
4547 input_line_pointer
= save_in
;
4554 *str
= input_line_pointer
;
4555 input_line_pointer
= save_in
;
4556 inst
.error
= _("invalid FPA immediate expression");
4560 /* Returns 1 if a number has "quarter-precision" float format
4561 0baBbbbbbc defgh000 00000000 00000000. */
4564 is_quarter_float (unsigned imm
)
4566 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4567 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4570 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4571 0baBbbbbbc defgh000 00000000 00000000.
4572 The zero and minus-zero cases need special handling, since they can't be
4573 encoded in the "quarter-precision" float format, but can nonetheless be
4574 loaded as integer constants. */
4577 parse_qfloat_immediate (char **ccp
, int *immed
)
4581 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4582 int found_fpchar
= 0;
4584 skip_past_char (&str
, '#');
4586 /* We must not accidentally parse an integer as a floating-point number. Make
4587 sure that the value we parse is not an integer by checking for special
4588 characters '.' or 'e'.
4589 FIXME: This is a horrible hack, but doing better is tricky because type
4590 information isn't in a very usable state at parse time. */
4592 skip_whitespace (fpnum
);
4594 if (strncmp (fpnum
, "0x", 2) == 0)
4598 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4599 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4609 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4611 unsigned fpword
= 0;
4614 /* Our FP word must be 32 bits (single-precision FP). */
4615 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4617 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4621 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4634 /* Shift operands. */
4637 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4640 struct asm_shift_name
4643 enum shift_kind kind
;
4646 /* Third argument to parse_shift. */
4647 enum parse_shift_mode
4649 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4650 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4651 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4652 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4653 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4656 /* Parse a <shift> specifier on an ARM data processing instruction.
4657 This has three forms:
4659 (LSL|LSR|ASL|ASR|ROR) Rs
4660 (LSL|LSR|ASL|ASR|ROR) #imm
4663 Note that ASL is assimilated to LSL in the instruction encoding, and
4664 RRX to ROR #0 (which cannot be written as such). */
4667 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4669 const struct asm_shift_name
*shift_name
;
4670 enum shift_kind shift
;
4675 for (p
= *str
; ISALPHA (*p
); p
++)
4680 inst
.error
= _("shift expression expected");
4684 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4687 if (shift_name
== NULL
)
4689 inst
.error
= _("shift expression expected");
4693 shift
= shift_name
->kind
;
4697 case NO_SHIFT_RESTRICT
:
4698 case SHIFT_IMMEDIATE
: break;
4700 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4701 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4703 inst
.error
= _("'LSL' or 'ASR' required");
4708 case SHIFT_LSL_IMMEDIATE
:
4709 if (shift
!= SHIFT_LSL
)
4711 inst
.error
= _("'LSL' required");
4716 case SHIFT_ASR_IMMEDIATE
:
4717 if (shift
!= SHIFT_ASR
)
4719 inst
.error
= _("'ASR' required");
4727 if (shift
!= SHIFT_RRX
)
4729 /* Whitespace can appear here if the next thing is a bare digit. */
4730 skip_whitespace (p
);
4732 if (mode
== NO_SHIFT_RESTRICT
4733 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4735 inst
.operands
[i
].imm
= reg
;
4736 inst
.operands
[i
].immisreg
= 1;
4738 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4741 inst
.operands
[i
].shift_kind
= shift
;
4742 inst
.operands
[i
].shifted
= 1;
4747 /* Parse a <shifter_operand> for an ARM data processing instruction:
4750 #<immediate>, <rotate>
4754 where <shift> is defined by parse_shift above, and <rotate> is a
4755 multiple of 2 between 0 and 30. Validation of immediate operands
4756 is deferred to md_apply_fix. */
4759 parse_shifter_operand (char **str
, int i
)
4764 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4766 inst
.operands
[i
].reg
= value
;
4767 inst
.operands
[i
].isreg
= 1;
4769 /* parse_shift will override this if appropriate */
4770 inst
.reloc
.exp
.X_op
= O_constant
;
4771 inst
.reloc
.exp
.X_add_number
= 0;
4773 if (skip_past_comma (str
) == FAIL
)
4776 /* Shift operation on register. */
4777 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4780 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4783 if (skip_past_comma (str
) == SUCCESS
)
4785 /* #x, y -- ie explicit rotation by Y. */
4786 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4789 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4791 inst
.error
= _("constant expression expected");
4795 value
= exp
.X_add_number
;
4796 if (value
< 0 || value
> 30 || value
% 2 != 0)
4798 inst
.error
= _("invalid rotation");
4801 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4803 inst
.error
= _("invalid constant");
4807 /* Convert to decoded value. md_apply_fix will put it back. */
4808 inst
.reloc
.exp
.X_add_number
4809 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4810 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4813 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4814 inst
.reloc
.pc_rel
= 0;
4818 /* Group relocation information. Each entry in the table contains the
4819 textual name of the relocation as may appear in assembler source
4820 and must end with a colon.
4821 Along with this textual name are the relocation codes to be used if
4822 the corresponding instruction is an ALU instruction (ADD or SUB only),
4823 an LDR, an LDRS, or an LDC. */
4825 struct group_reloc_table_entry
4836 /* Varieties of non-ALU group relocation. */
4843 static struct group_reloc_table_entry group_reloc_table
[] =
4844 { /* Program counter relative: */
4846 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4851 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4852 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4853 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4854 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4856 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4861 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4862 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4863 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4864 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4866 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4867 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4868 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4869 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4870 /* Section base relative */
4872 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4877 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4878 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4879 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4880 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4882 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4887 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4888 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4889 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4890 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4892 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4893 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4894 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4895 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4897 /* Given the address of a pointer pointing to the textual name of a group
4898 relocation as may appear in assembler source, attempt to find its details
4899 in group_reloc_table. The pointer will be updated to the character after
4900 the trailing colon. On failure, FAIL will be returned; SUCCESS
4901 otherwise. On success, *entry will be updated to point at the relevant
4902 group_reloc_table entry. */
4905 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4908 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4910 int length
= strlen (group_reloc_table
[i
].name
);
4912 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4913 && (*str
)[length
] == ':')
4915 *out
= &group_reloc_table
[i
];
4916 *str
+= (length
+ 1);
4924 /* Parse a <shifter_operand> for an ARM data processing instruction
4925 (as for parse_shifter_operand) where group relocations are allowed:
4928 #<immediate>, <rotate>
4929 #:<group_reloc>:<expression>
4933 where <group_reloc> is one of the strings defined in group_reloc_table.
4934 The hashes are optional.
4936 Everything else is as for parse_shifter_operand. */
4938 static parse_operand_result
4939 parse_shifter_operand_group_reloc (char **str
, int i
)
4941 /* Determine if we have the sequence of characters #: or just :
4942 coming next. If we do, then we check for a group relocation.
4943 If we don't, punt the whole lot to parse_shifter_operand. */
4945 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4946 || (*str
)[0] == ':')
4948 struct group_reloc_table_entry
*entry
;
4950 if ((*str
)[0] == '#')
4955 /* Try to parse a group relocation. Anything else is an error. */
4956 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4958 inst
.error
= _("unknown group relocation");
4959 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4962 /* We now have the group relocation table entry corresponding to
4963 the name in the assembler source. Next, we parse the expression. */
4964 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4965 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4967 /* Record the relocation type (always the ALU variant here). */
4968 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4969 gas_assert (inst
.reloc
.type
!= 0);
4971 return PARSE_OPERAND_SUCCESS
;
4974 return parse_shifter_operand (str
, i
) == SUCCESS
4975 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4977 /* Never reached. */
4980 /* Parse a Neon alignment expression. Information is written to
4981 inst.operands[i]. We assume the initial ':' has been skipped.
4983 align .imm = align << 8, .immisalign=1, .preind=0 */
4984 static parse_operand_result
4985 parse_neon_alignment (char **str
, int i
)
4990 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4992 if (exp
.X_op
!= O_constant
)
4994 inst
.error
= _("alignment must be constant");
4995 return PARSE_OPERAND_FAIL
;
4998 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4999 inst
.operands
[i
].immisalign
= 1;
5000 /* Alignments are not pre-indexes. */
5001 inst
.operands
[i
].preind
= 0;
5004 return PARSE_OPERAND_SUCCESS
;
5007 /* Parse all forms of an ARM address expression. Information is written
5008 to inst.operands[i] and/or inst.reloc.
5010 Preindexed addressing (.preind=1):
5012 [Rn, #offset] .reg=Rn .reloc.exp=offset
5013 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5014 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5015 .shift_kind=shift .reloc.exp=shift_imm
5017 These three may have a trailing ! which causes .writeback to be set also.
5019 Postindexed addressing (.postind=1, .writeback=1):
5021 [Rn], #offset .reg=Rn .reloc.exp=offset
5022 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5023 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5024 .shift_kind=shift .reloc.exp=shift_imm
5026 Unindexed addressing (.preind=0, .postind=0):
5028 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5032 [Rn]{!} shorthand for [Rn,#0]{!}
5033 =immediate .isreg=0 .reloc.exp=immediate
5034 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5036 It is the caller's responsibility to check for addressing modes not
5037 supported by the instruction, and to set inst.reloc.type. */
5039 static parse_operand_result
5040 parse_address_main (char **str
, int i
, int group_relocations
,
5041 group_reloc_type group_type
)
5046 if (skip_past_char (&p
, '[') == FAIL
)
5048 if (skip_past_char (&p
, '=') == FAIL
)
5050 /* Bare address - translate to PC-relative offset. */
5051 inst
.reloc
.pc_rel
= 1;
5052 inst
.operands
[i
].reg
= REG_PC
;
5053 inst
.operands
[i
].isreg
= 1;
5054 inst
.operands
[i
].preind
= 1;
5056 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5058 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5059 return PARSE_OPERAND_FAIL
;
5062 return PARSE_OPERAND_SUCCESS
;
5065 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5067 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5068 return PARSE_OPERAND_FAIL
;
5070 inst
.operands
[i
].reg
= reg
;
5071 inst
.operands
[i
].isreg
= 1;
5073 if (skip_past_comma (&p
) == SUCCESS
)
5075 inst
.operands
[i
].preind
= 1;
5078 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5080 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5082 inst
.operands
[i
].imm
= reg
;
5083 inst
.operands
[i
].immisreg
= 1;
5085 if (skip_past_comma (&p
) == SUCCESS
)
5086 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5087 return PARSE_OPERAND_FAIL
;
5089 else if (skip_past_char (&p
, ':') == SUCCESS
)
5091 /* FIXME: '@' should be used here, but it's filtered out by generic
5092 code before we get to see it here. This may be subject to
5094 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5096 if (result
!= PARSE_OPERAND_SUCCESS
)
5101 if (inst
.operands
[i
].negative
)
5103 inst
.operands
[i
].negative
= 0;
5107 if (group_relocations
5108 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5110 struct group_reloc_table_entry
*entry
;
5112 /* Skip over the #: or : sequence. */
5118 /* Try to parse a group relocation. Anything else is an
5120 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5122 inst
.error
= _("unknown group relocation");
5123 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5126 /* We now have the group relocation table entry corresponding to
5127 the name in the assembler source. Next, we parse the
5129 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5130 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5132 /* Record the relocation type. */
5136 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5140 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5144 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5151 if (inst
.reloc
.type
== 0)
5153 inst
.error
= _("this group relocation is not allowed on this instruction");
5154 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5158 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5159 return PARSE_OPERAND_FAIL
;
5162 else if (skip_past_char (&p
, ':') == SUCCESS
)
5164 /* FIXME: '@' should be used here, but it's filtered out by generic code
5165 before we get to see it here. This may be subject to change. */
5166 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5168 if (result
!= PARSE_OPERAND_SUCCESS
)
5172 if (skip_past_char (&p
, ']') == FAIL
)
5174 inst
.error
= _("']' expected");
5175 return PARSE_OPERAND_FAIL
;
5178 if (skip_past_char (&p
, '!') == SUCCESS
)
5179 inst
.operands
[i
].writeback
= 1;
5181 else if (skip_past_comma (&p
) == SUCCESS
)
5183 if (skip_past_char (&p
, '{') == SUCCESS
)
5185 /* [Rn], {expr} - unindexed, with option */
5186 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5187 0, 255, TRUE
) == FAIL
)
5188 return PARSE_OPERAND_FAIL
;
5190 if (skip_past_char (&p
, '}') == FAIL
)
5192 inst
.error
= _("'}' expected at end of 'option' field");
5193 return PARSE_OPERAND_FAIL
;
5195 if (inst
.operands
[i
].preind
)
5197 inst
.error
= _("cannot combine index with option");
5198 return PARSE_OPERAND_FAIL
;
5201 return PARSE_OPERAND_SUCCESS
;
5205 inst
.operands
[i
].postind
= 1;
5206 inst
.operands
[i
].writeback
= 1;
5208 if (inst
.operands
[i
].preind
)
5210 inst
.error
= _("cannot combine pre- and post-indexing");
5211 return PARSE_OPERAND_FAIL
;
5215 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5217 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5219 /* We might be using the immediate for alignment already. If we
5220 are, OR the register number into the low-order bits. */
5221 if (inst
.operands
[i
].immisalign
)
5222 inst
.operands
[i
].imm
|= reg
;
5224 inst
.operands
[i
].imm
= reg
;
5225 inst
.operands
[i
].immisreg
= 1;
5227 if (skip_past_comma (&p
) == SUCCESS
)
5228 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5229 return PARSE_OPERAND_FAIL
;
5233 if (inst
.operands
[i
].negative
)
5235 inst
.operands
[i
].negative
= 0;
5238 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5239 return PARSE_OPERAND_FAIL
;
5244 /* If at this point neither .preind nor .postind is set, we have a
5245 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5246 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5248 inst
.operands
[i
].preind
= 1;
5249 inst
.reloc
.exp
.X_op
= O_constant
;
5250 inst
.reloc
.exp
.X_add_number
= 0;
5253 return PARSE_OPERAND_SUCCESS
;
5257 parse_address (char **str
, int i
)
5259 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5263 static parse_operand_result
5264 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5266 return parse_address_main (str
, i
, 1, type
);
5269 /* Parse an operand for a MOVW or MOVT instruction. */
5271 parse_half (char **str
)
5276 skip_past_char (&p
, '#');
5277 if (strncasecmp (p
, ":lower16:", 9) == 0)
5278 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5279 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5280 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5282 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5285 skip_whitespace (p
);
5288 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5291 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5293 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5295 inst
.error
= _("constant expression expected");
5298 if (inst
.reloc
.exp
.X_add_number
< 0
5299 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5301 inst
.error
= _("immediate value out of range");
5309 /* Miscellaneous. */
5311 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5312 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5314 parse_psr (char **str
)
5317 unsigned long psr_field
;
5318 const struct asm_psr
*psr
;
5321 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5322 feature for ease of use and backwards compatibility. */
5324 if (strncasecmp (p
, "SPSR", 4) == 0)
5325 psr_field
= SPSR_BIT
;
5326 else if (strncasecmp (p
, "CPSR", 4) == 0
5327 || (strncasecmp (p
, "APSR", 4) == 0
5328 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
)))
5335 while (ISALNUM (*p
) || *p
== '_');
5337 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5349 /* A suffix follows. */
5355 while (ISALNUM (*p
) || *p
== '_');
5357 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5362 psr_field
|= psr
->field
;
5367 goto error
; /* Garbage after "[CS]PSR". */
5369 psr_field
|= (PSR_c
| PSR_f
);
5375 inst
.error
= _("flag for {c}psr instruction expected");
5379 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5380 value suitable for splatting into the AIF field of the instruction. */
5383 parse_cps_flags (char **str
)
5392 case '\0': case ',':
5395 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5396 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5397 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5400 inst
.error
= _("unrecognized CPS flag");
5405 if (saw_a_flag
== 0)
5407 inst
.error
= _("missing CPS flags");
5415 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5416 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5419 parse_endian_specifier (char **str
)
5424 if (strncasecmp (s
, "BE", 2))
5426 else if (strncasecmp (s
, "LE", 2))
5430 inst
.error
= _("valid endian specifiers are be or le");
5434 if (ISALNUM (s
[2]) || s
[2] == '_')
5436 inst
.error
= _("valid endian specifiers are be or le");
5441 return little_endian
;
5444 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5445 value suitable for poking into the rotate field of an sxt or sxta
5446 instruction, or FAIL on error. */
5449 parse_ror (char **str
)
5454 if (strncasecmp (s
, "ROR", 3) == 0)
5458 inst
.error
= _("missing rotation field after comma");
5462 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5467 case 0: *str
= s
; return 0x0;
5468 case 8: *str
= s
; return 0x1;
5469 case 16: *str
= s
; return 0x2;
5470 case 24: *str
= s
; return 0x3;
5473 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5478 /* Parse a conditional code (from conds[] below). The value returned is in the
5479 range 0 .. 14, or FAIL. */
5481 parse_cond (char **str
)
5484 const struct asm_cond
*c
;
5486 /* Condition codes are always 2 characters, so matching up to
5487 3 characters is sufficient. */
5492 while (ISALPHA (*q
) && n
< 3)
5494 cond
[n
] = TOLOWER (*q
);
5499 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5502 inst
.error
= _("condition required");
5510 /* Parse an option for a barrier instruction. Returns the encoding for the
5513 parse_barrier (char **str
)
5516 const struct asm_barrier_opt
*o
;
5519 while (ISALPHA (*q
))
5522 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5531 /* Parse the operands of a table branch instruction. Similar to a memory
5534 parse_tb (char **str
)
5539 if (skip_past_char (&p
, '[') == FAIL
)
5541 inst
.error
= _("'[' expected");
5545 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5547 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5550 inst
.operands
[0].reg
= reg
;
5552 if (skip_past_comma (&p
) == FAIL
)
5554 inst
.error
= _("',' expected");
5558 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5560 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5563 inst
.operands
[0].imm
= reg
;
5565 if (skip_past_comma (&p
) == SUCCESS
)
5567 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5569 if (inst
.reloc
.exp
.X_add_number
!= 1)
5571 inst
.error
= _("invalid shift");
5574 inst
.operands
[0].shifted
= 1;
5577 if (skip_past_char (&p
, ']') == FAIL
)
5579 inst
.error
= _("']' expected");
5586 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5587 information on the types the operands can take and how they are encoded.
5588 Up to four operands may be read; this function handles setting the
5589 ".present" field for each read operand itself.
5590 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5591 else returns FAIL. */
5594 parse_neon_mov (char **str
, int *which_operand
)
5596 int i
= *which_operand
, val
;
5597 enum arm_reg_type rtype
;
5599 struct neon_type_el optype
;
5601 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5603 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5604 inst
.operands
[i
].reg
= val
;
5605 inst
.operands
[i
].isscalar
= 1;
5606 inst
.operands
[i
].vectype
= optype
;
5607 inst
.operands
[i
++].present
= 1;
5609 if (skip_past_comma (&ptr
) == FAIL
)
5612 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5615 inst
.operands
[i
].reg
= val
;
5616 inst
.operands
[i
].isreg
= 1;
5617 inst
.operands
[i
].present
= 1;
5619 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5622 /* Cases 0, 1, 2, 3, 5 (D only). */
5623 if (skip_past_comma (&ptr
) == FAIL
)
5626 inst
.operands
[i
].reg
= val
;
5627 inst
.operands
[i
].isreg
= 1;
5628 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5629 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5630 inst
.operands
[i
].isvec
= 1;
5631 inst
.operands
[i
].vectype
= optype
;
5632 inst
.operands
[i
++].present
= 1;
5634 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5636 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5637 Case 13: VMOV <Sd>, <Rm> */
5638 inst
.operands
[i
].reg
= val
;
5639 inst
.operands
[i
].isreg
= 1;
5640 inst
.operands
[i
].present
= 1;
5642 if (rtype
== REG_TYPE_NQ
)
5644 first_error (_("can't use Neon quad register here"));
5647 else if (rtype
!= REG_TYPE_VFS
)
5650 if (skip_past_comma (&ptr
) == FAIL
)
5652 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5654 inst
.operands
[i
].reg
= val
;
5655 inst
.operands
[i
].isreg
= 1;
5656 inst
.operands
[i
].present
= 1;
5659 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5662 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5663 Case 1: VMOV<c><q> <Dd>, <Dm>
5664 Case 8: VMOV.F32 <Sd>, <Sm>
5665 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5667 inst
.operands
[i
].reg
= val
;
5668 inst
.operands
[i
].isreg
= 1;
5669 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5670 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5671 inst
.operands
[i
].isvec
= 1;
5672 inst
.operands
[i
].vectype
= optype
;
5673 inst
.operands
[i
].present
= 1;
5675 if (skip_past_comma (&ptr
) == SUCCESS
)
5680 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5683 inst
.operands
[i
].reg
= val
;
5684 inst
.operands
[i
].isreg
= 1;
5685 inst
.operands
[i
++].present
= 1;
5687 if (skip_past_comma (&ptr
) == FAIL
)
5690 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5693 inst
.operands
[i
].reg
= val
;
5694 inst
.operands
[i
].isreg
= 1;
5695 inst
.operands
[i
++].present
= 1;
5698 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5699 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5700 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5701 Case 10: VMOV.F32 <Sd>, #<imm>
5702 Case 11: VMOV.F64 <Dd>, #<imm> */
5703 inst
.operands
[i
].immisfloat
= 1;
5704 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5705 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5706 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5710 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5714 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5717 inst
.operands
[i
].reg
= val
;
5718 inst
.operands
[i
].isreg
= 1;
5719 inst
.operands
[i
++].present
= 1;
5721 if (skip_past_comma (&ptr
) == FAIL
)
5724 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5726 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5727 inst
.operands
[i
].reg
= val
;
5728 inst
.operands
[i
].isscalar
= 1;
5729 inst
.operands
[i
].present
= 1;
5730 inst
.operands
[i
].vectype
= optype
;
5732 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5734 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5735 inst
.operands
[i
].reg
= val
;
5736 inst
.operands
[i
].isreg
= 1;
5737 inst
.operands
[i
++].present
= 1;
5739 if (skip_past_comma (&ptr
) == FAIL
)
5742 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5745 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5749 inst
.operands
[i
].reg
= val
;
5750 inst
.operands
[i
].isreg
= 1;
5751 inst
.operands
[i
].isvec
= 1;
5752 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5753 inst
.operands
[i
].vectype
= optype
;
5754 inst
.operands
[i
].present
= 1;
5756 if (rtype
== REG_TYPE_VFS
)
5760 if (skip_past_comma (&ptr
) == FAIL
)
5762 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5765 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5768 inst
.operands
[i
].reg
= val
;
5769 inst
.operands
[i
].isreg
= 1;
5770 inst
.operands
[i
].isvec
= 1;
5771 inst
.operands
[i
].issingle
= 1;
5772 inst
.operands
[i
].vectype
= optype
;
5773 inst
.operands
[i
].present
= 1;
5776 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5780 inst
.operands
[i
].reg
= val
;
5781 inst
.operands
[i
].isreg
= 1;
5782 inst
.operands
[i
].isvec
= 1;
5783 inst
.operands
[i
].issingle
= 1;
5784 inst
.operands
[i
].vectype
= optype
;
5785 inst
.operands
[i
++].present
= 1;
5790 first_error (_("parse error"));
5794 /* Successfully parsed the operands. Update args. */
5800 first_error (_("expected comma"));
5804 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5808 /* Use this macro when the operand constraints are different
5809 for ARM and THUMB (e.g. ldrd). */
5810 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5811 ((arm_operand) | ((thumb_operand) << 16))
5813 /* Matcher codes for parse_operands. */
5814 enum operand_parse_code
5816 OP_stop
, /* end of line */
5818 OP_RR
, /* ARM register */
5819 OP_RRnpc
, /* ARM register, not r15 */
5820 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5821 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5822 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5823 optional trailing ! */
5824 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5825 OP_RCP
, /* Coprocessor number */
5826 OP_RCN
, /* Coprocessor register */
5827 OP_RF
, /* FPA register */
5828 OP_RVS
, /* VFP single precision register */
5829 OP_RVD
, /* VFP double precision register (0..15) */
5830 OP_RND
, /* Neon double precision register (0..31) */
5831 OP_RNQ
, /* Neon quad precision register */
5832 OP_RVSD
, /* VFP single or double precision register */
5833 OP_RNDQ
, /* Neon double or quad precision register */
5834 OP_RNSDQ
, /* Neon single, double or quad precision register */
5835 OP_RNSC
, /* Neon scalar D[X] */
5836 OP_RVC
, /* VFP control register */
5837 OP_RMF
, /* Maverick F register */
5838 OP_RMD
, /* Maverick D register */
5839 OP_RMFX
, /* Maverick FX register */
5840 OP_RMDX
, /* Maverick DX register */
5841 OP_RMAX
, /* Maverick AX register */
5842 OP_RMDS
, /* Maverick DSPSC register */
5843 OP_RIWR
, /* iWMMXt wR register */
5844 OP_RIWC
, /* iWMMXt wC register */
5845 OP_RIWG
, /* iWMMXt wCG register */
5846 OP_RXA
, /* XScale accumulator register */
5848 OP_REGLST
, /* ARM register list */
5849 OP_VRSLST
, /* VFP single-precision register list */
5850 OP_VRDLST
, /* VFP double-precision register list */
5851 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5852 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5853 OP_NSTRLST
, /* Neon element/structure list */
5855 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5856 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5857 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5858 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5859 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5860 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5861 OP_VMOV
, /* Neon VMOV operands. */
5862 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5863 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5864 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5866 OP_I0
, /* immediate zero */
5867 OP_I7
, /* immediate value 0 .. 7 */
5868 OP_I15
, /* 0 .. 15 */
5869 OP_I16
, /* 1 .. 16 */
5870 OP_I16z
, /* 0 .. 16 */
5871 OP_I31
, /* 0 .. 31 */
5872 OP_I31w
, /* 0 .. 31, optional trailing ! */
5873 OP_I32
, /* 1 .. 32 */
5874 OP_I32z
, /* 0 .. 32 */
5875 OP_I63
, /* 0 .. 63 */
5876 OP_I63s
, /* -64 .. 63 */
5877 OP_I64
, /* 1 .. 64 */
5878 OP_I64z
, /* 0 .. 64 */
5879 OP_I255
, /* 0 .. 255 */
5881 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5882 OP_I7b
, /* 0 .. 7 */
5883 OP_I15b
, /* 0 .. 15 */
5884 OP_I31b
, /* 0 .. 31 */
5886 OP_SH
, /* shifter operand */
5887 OP_SHG
, /* shifter operand with possible group relocation */
5888 OP_ADDR
, /* Memory address expression (any mode) */
5889 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5890 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5891 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5892 OP_EXP
, /* arbitrary expression */
5893 OP_EXPi
, /* same, with optional immediate prefix */
5894 OP_EXPr
, /* same, with optional relocation suffix */
5895 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5897 OP_CPSF
, /* CPS flags */
5898 OP_ENDI
, /* Endianness specifier */
5899 OP_PSR
, /* CPSR/SPSR mask for msr */
5900 OP_COND
, /* conditional code */
5901 OP_TB
, /* Table branch. */
5903 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5904 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5906 OP_RRnpc_I0
, /* ARM register or literal 0 */
5907 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5908 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5909 OP_RF_IF
, /* FPA register or immediate */
5910 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5911 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5913 /* Optional operands. */
5914 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5915 OP_oI31b
, /* 0 .. 31 */
5916 OP_oI32b
, /* 1 .. 32 */
5917 OP_oIffffb
, /* 0 .. 65535 */
5918 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5920 OP_oRR
, /* ARM register */
5921 OP_oRRnpc
, /* ARM register, not the PC */
5922 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
5923 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5924 OP_oRND
, /* Optional Neon double precision register */
5925 OP_oRNQ
, /* Optional Neon quad precision register */
5926 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5927 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5928 OP_oSHll
, /* LSL immediate */
5929 OP_oSHar
, /* ASR immediate */
5930 OP_oSHllar
, /* LSL or ASR immediate */
5931 OP_oROR
, /* ROR 0/8/16/24 */
5932 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
5934 /* Some pre-defined mixed (ARM/THUMB) operands. */
5935 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
5936 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
5937 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
5939 OP_FIRST_OPTIONAL
= OP_oI7b
5942 /* Generic instruction operand parser. This does no encoding and no
5943 semantic validation; it merely squirrels values away in the inst
5944 structure. Returns SUCCESS or FAIL depending on whether the
5945 specified grammar matched. */
5947 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
5949 unsigned const int *upat
= pattern
;
5950 char *backtrack_pos
= 0;
5951 const char *backtrack_error
= 0;
5952 int i
, val
, backtrack_index
= 0;
5953 enum arm_reg_type rtype
;
5954 parse_operand_result result
;
5955 unsigned int op_parse_code
;
5957 #define po_char_or_fail(chr) \
5960 if (skip_past_char (&str, chr) == FAIL) \
5965 #define po_reg_or_fail(regtype) \
5968 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5969 & inst.operands[i].vectype); \
5972 first_error (_(reg_expected_msgs[regtype])); \
5975 inst.operands[i].reg = val; \
5976 inst.operands[i].isreg = 1; \
5977 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5978 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5979 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5980 || rtype == REG_TYPE_VFD \
5981 || rtype == REG_TYPE_NQ); \
5985 #define po_reg_or_goto(regtype, label) \
5988 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5989 & inst.operands[i].vectype); \
5993 inst.operands[i].reg = val; \
5994 inst.operands[i].isreg = 1; \
5995 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5996 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5997 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5998 || rtype == REG_TYPE_VFD \
5999 || rtype == REG_TYPE_NQ); \
6003 #define po_imm_or_fail(min, max, popt) \
6006 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6008 inst.operands[i].imm = val; \
6012 #define po_scalar_or_goto(elsz, label) \
6015 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6018 inst.operands[i].reg = val; \
6019 inst.operands[i].isscalar = 1; \
6023 #define po_misc_or_fail(expr) \
6031 #define po_misc_or_fail_no_backtrack(expr) \
6035 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6036 backtrack_pos = 0; \
6037 if (result != PARSE_OPERAND_SUCCESS) \
6042 #define po_barrier_or_imm(str) \
6045 val = parse_barrier (&str); \
6048 if (ISALPHA (*str)) \
6055 if ((inst.instruction & 0xf0) == 0x60 \
6058 /* ISB can only take SY as an option. */ \
6059 inst.error = _("invalid barrier type"); \
6066 skip_whitespace (str
);
6068 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6070 op_parse_code
= upat
[i
];
6071 if (op_parse_code
>= 1<<16)
6072 op_parse_code
= thumb
? (op_parse_code
>> 16)
6073 : (op_parse_code
& ((1<<16)-1));
6075 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6077 /* Remember where we are in case we need to backtrack. */
6078 gas_assert (!backtrack_pos
);
6079 backtrack_pos
= str
;
6080 backtrack_error
= inst
.error
;
6081 backtrack_index
= i
;
6084 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6085 po_char_or_fail (',');
6087 switch (op_parse_code
)
6095 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6096 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6097 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6098 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6099 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6100 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6102 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6104 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6106 /* Also accept generic coprocessor regs for unknown registers. */
6108 po_reg_or_fail (REG_TYPE_CN
);
6110 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6111 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6112 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6113 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6114 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6115 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6116 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6117 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6118 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6119 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6121 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6123 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6124 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6126 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6128 /* Neon scalar. Using an element size of 8 means that some invalid
6129 scalars are accepted here, so deal with those in later code. */
6130 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6134 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6137 po_imm_or_fail (0, 0, TRUE
);
6142 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6147 po_scalar_or_goto (8, try_rr
);
6150 po_reg_or_fail (REG_TYPE_RN
);
6156 po_scalar_or_goto (8, try_nsdq
);
6159 po_reg_or_fail (REG_TYPE_NSDQ
);
6165 po_scalar_or_goto (8, try_ndq
);
6168 po_reg_or_fail (REG_TYPE_NDQ
);
6174 po_scalar_or_goto (8, try_vfd
);
6177 po_reg_or_fail (REG_TYPE_VFD
);
6182 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6183 not careful then bad things might happen. */
6184 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6189 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6192 /* There's a possibility of getting a 64-bit immediate here, so
6193 we need special handling. */
6194 if (parse_big_immediate (&str
, i
) == FAIL
)
6196 inst
.error
= _("immediate value is out of range");
6204 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6207 po_imm_or_fail (0, 63, TRUE
);
6212 po_char_or_fail ('[');
6213 po_reg_or_fail (REG_TYPE_RN
);
6214 po_char_or_fail (']');
6220 po_reg_or_fail (REG_TYPE_RN
);
6221 if (skip_past_char (&str
, '!') == SUCCESS
)
6222 inst
.operands
[i
].writeback
= 1;
6226 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6227 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6228 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6229 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6230 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6231 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6232 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6233 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6234 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6235 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6236 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6237 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6239 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6241 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6242 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6244 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6245 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6246 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6248 /* Immediate variants */
6250 po_char_or_fail ('{');
6251 po_imm_or_fail (0, 255, TRUE
);
6252 po_char_or_fail ('}');
6256 /* The expression parser chokes on a trailing !, so we have
6257 to find it first and zap it. */
6260 while (*s
&& *s
!= ',')
6265 inst
.operands
[i
].writeback
= 1;
6267 po_imm_or_fail (0, 31, TRUE
);
6275 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6280 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6285 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6287 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6289 val
= parse_reloc (&str
);
6292 inst
.error
= _("unrecognized relocation suffix");
6295 else if (val
!= BFD_RELOC_UNUSED
)
6297 inst
.operands
[i
].imm
= val
;
6298 inst
.operands
[i
].hasreloc
= 1;
6303 /* Operand for MOVW or MOVT. */
6305 po_misc_or_fail (parse_half (&str
));
6308 /* Register or expression. */
6309 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6310 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6312 /* Register or immediate. */
6313 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6314 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6316 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6318 if (!is_immediate_prefix (*str
))
6321 val
= parse_fpa_immediate (&str
);
6324 /* FPA immediates are encoded as registers 8-15.
6325 parse_fpa_immediate has already applied the offset. */
6326 inst
.operands
[i
].reg
= val
;
6327 inst
.operands
[i
].isreg
= 1;
6330 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6331 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6333 /* Two kinds of register. */
6336 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6338 || (rege
->type
!= REG_TYPE_MMXWR
6339 && rege
->type
!= REG_TYPE_MMXWC
6340 && rege
->type
!= REG_TYPE_MMXWCG
))
6342 inst
.error
= _("iWMMXt data or control register expected");
6345 inst
.operands
[i
].reg
= rege
->number
;
6346 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6352 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6354 || (rege
->type
!= REG_TYPE_MMXWC
6355 && rege
->type
!= REG_TYPE_MMXWCG
))
6357 inst
.error
= _("iWMMXt control register expected");
6360 inst
.operands
[i
].reg
= rege
->number
;
6361 inst
.operands
[i
].isreg
= 1;
6366 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6367 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6368 case OP_oROR
: val
= parse_ror (&str
); break;
6369 case OP_PSR
: val
= parse_psr (&str
); break;
6370 case OP_COND
: val
= parse_cond (&str
); break;
6371 case OP_oBARRIER_I15
:
6372 po_barrier_or_imm (str
); break;
6374 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6379 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6380 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6383 val
= parse_psr (&str
);
6387 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6390 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6392 if (strncasecmp (str
, "APSR_", 5) == 0)
6399 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6400 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6401 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6402 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6403 default: found
= 16;
6407 inst
.operands
[i
].isvec
= 1;
6408 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6409 inst
.operands
[i
].reg
= REG_PC
;
6416 po_misc_or_fail (parse_tb (&str
));
6419 /* Register lists. */
6421 val
= parse_reg_list (&str
);
6424 inst
.operands
[1].writeback
= 1;
6430 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6434 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6438 /* Allow Q registers too. */
6439 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6444 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6446 inst
.operands
[i
].issingle
= 1;
6451 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6456 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6457 &inst
.operands
[i
].vectype
);
6460 /* Addressing modes */
6462 po_misc_or_fail (parse_address (&str
, i
));
6466 po_misc_or_fail_no_backtrack (
6467 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6471 po_misc_or_fail_no_backtrack (
6472 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6476 po_misc_or_fail_no_backtrack (
6477 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6481 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6485 po_misc_or_fail_no_backtrack (
6486 parse_shifter_operand_group_reloc (&str
, i
));
6490 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6494 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6498 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6502 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6505 /* Various value-based sanity checks and shared operations. We
6506 do not signal immediate failures for the register constraints;
6507 this allows a syntax error to take precedence. */
6508 switch (op_parse_code
)
6516 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6517 inst
.error
= BAD_PC
;
6522 if (inst
.operands
[i
].isreg
)
6524 if (inst
.operands
[i
].reg
== REG_PC
)
6525 inst
.error
= BAD_PC
;
6526 else if (inst
.operands
[i
].reg
== REG_SP
)
6527 inst
.error
= BAD_SP
;
6532 if (inst
.operands
[i
].isreg
6533 && inst
.operands
[i
].reg
== REG_PC
6534 && (inst
.operands
[i
].writeback
|| thumb
))
6535 inst
.error
= BAD_PC
;
6544 case OP_oBARRIER_I15
:
6553 inst
.operands
[i
].imm
= val
;
6560 /* If we get here, this operand was successfully parsed. */
6561 inst
.operands
[i
].present
= 1;
6565 inst
.error
= BAD_ARGS
;
6570 /* The parse routine should already have set inst.error, but set a
6571 default here just in case. */
6573 inst
.error
= _("syntax error");
6577 /* Do not backtrack over a trailing optional argument that
6578 absorbed some text. We will only fail again, with the
6579 'garbage following instruction' error message, which is
6580 probably less helpful than the current one. */
6581 if (backtrack_index
== i
&& backtrack_pos
!= str
6582 && upat
[i
+1] == OP_stop
)
6585 inst
.error
= _("syntax error");
6589 /* Try again, skipping the optional argument at backtrack_pos. */
6590 str
= backtrack_pos
;
6591 inst
.error
= backtrack_error
;
6592 inst
.operands
[backtrack_index
].present
= 0;
6593 i
= backtrack_index
;
6597 /* Check that we have parsed all the arguments. */
6598 if (*str
!= '\0' && !inst
.error
)
6599 inst
.error
= _("garbage following instruction");
6601 return inst
.error
? FAIL
: SUCCESS
;
6604 #undef po_char_or_fail
6605 #undef po_reg_or_fail
6606 #undef po_reg_or_goto
6607 #undef po_imm_or_fail
6608 #undef po_scalar_or_fail
6609 #undef po_barrier_or_imm
6611 /* Shorthand macro for instruction encoding functions issuing errors. */
6612 #define constraint(expr, err) \
6623 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6624 instructions are unpredictable if these registers are used. This
6625 is the BadReg predicate in ARM's Thumb-2 documentation. */
6626 #define reject_bad_reg(reg) \
6628 if (reg == REG_SP || reg == REG_PC) \
6630 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6635 /* If REG is R13 (the stack pointer), warn that its use is
6637 #define warn_deprecated_sp(reg) \
6639 if (warn_on_deprecated && reg == REG_SP) \
6640 as_warn (_("use of r13 is deprecated")); \
6643 /* Functions for operand encoding. ARM, then Thumb. */
6645 #define rotate_left(v, n) (v << n | v >> (32 - n))
6647 /* If VAL can be encoded in the immediate field of an ARM instruction,
6648 return the encoded form. Otherwise, return FAIL. */
6651 encode_arm_immediate (unsigned int val
)
6655 for (i
= 0; i
< 32; i
+= 2)
6656 if ((a
= rotate_left (val
, i
)) <= 0xff)
6657 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6662 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6663 return the encoded form. Otherwise, return FAIL. */
6665 encode_thumb32_immediate (unsigned int val
)
6672 for (i
= 1; i
<= 24; i
++)
6675 if ((val
& ~(0xff << i
)) == 0)
6676 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6680 if (val
== ((a
<< 16) | a
))
6682 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6686 if (val
== ((a
<< 16) | a
))
6687 return 0x200 | (a
>> 8);
6691 /* Encode a VFP SP or DP register number into inst.instruction. */
6694 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6696 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6699 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6702 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6705 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6710 first_error (_("D register out of range for selected VFP version"));
6718 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6722 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6726 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6730 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6734 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6738 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6746 /* Encode a <shift> in an ARM-format instruction. The immediate,
6747 if any, is handled by md_apply_fix. */
6749 encode_arm_shift (int i
)
6751 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6752 inst
.instruction
|= SHIFT_ROR
<< 5;
6755 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6756 if (inst
.operands
[i
].immisreg
)
6758 inst
.instruction
|= SHIFT_BY_REG
;
6759 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6762 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6767 encode_arm_shifter_operand (int i
)
6769 if (inst
.operands
[i
].isreg
)
6771 inst
.instruction
|= inst
.operands
[i
].reg
;
6772 encode_arm_shift (i
);
6775 inst
.instruction
|= INST_IMMEDIATE
;
6778 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6780 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6782 gas_assert (inst
.operands
[i
].isreg
);
6783 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6785 if (inst
.operands
[i
].preind
)
6789 inst
.error
= _("instruction does not accept preindexed addressing");
6792 inst
.instruction
|= PRE_INDEX
;
6793 if (inst
.operands
[i
].writeback
)
6794 inst
.instruction
|= WRITE_BACK
;
6797 else if (inst
.operands
[i
].postind
)
6799 gas_assert (inst
.operands
[i
].writeback
);
6801 inst
.instruction
|= WRITE_BACK
;
6803 else /* unindexed - only for coprocessor */
6805 inst
.error
= _("instruction does not accept unindexed addressing");
6809 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6810 && (((inst
.instruction
& 0x000f0000) >> 16)
6811 == ((inst
.instruction
& 0x0000f000) >> 12)))
6812 as_warn ((inst
.instruction
& LOAD_BIT
)
6813 ? _("destination register same as write-back base")
6814 : _("source register same as write-back base"));
6817 /* inst.operands[i] was set up by parse_address. Encode it into an
6818 ARM-format mode 2 load or store instruction. If is_t is true,
6819 reject forms that cannot be used with a T instruction (i.e. not
6822 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6824 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6826 encode_arm_addr_mode_common (i
, is_t
);
6828 if (inst
.operands
[i
].immisreg
)
6830 constraint ((inst
.operands
[i
].imm
== REG_PC
6831 || (is_pc
&& inst
.operands
[i
].writeback
)),
6833 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6834 inst
.instruction
|= inst
.operands
[i
].imm
;
6835 if (!inst
.operands
[i
].negative
)
6836 inst
.instruction
|= INDEX_UP
;
6837 if (inst
.operands
[i
].shifted
)
6839 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6840 inst
.instruction
|= SHIFT_ROR
<< 5;
6843 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6844 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6848 else /* immediate offset in inst.reloc */
6850 if (is_pc
&& !inst
.reloc
.pc_rel
)
6852 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
6854 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
6855 cannot use PC in addressing.
6856 PC cannot be used in writeback addressing, either. */
6857 constraint ((is_t
|| inst
.operands
[i
].writeback
),
6860 /* Use of PC in str is deprecated for ARMv7. */
6861 if (warn_on_deprecated
6863 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
6864 as_warn (_("use of PC in this instruction is deprecated"));
6867 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6868 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6872 /* inst.operands[i] was set up by parse_address. Encode it into an
6873 ARM-format mode 3 load or store instruction. Reject forms that
6874 cannot be used with such instructions. If is_t is true, reject
6875 forms that cannot be used with a T instruction (i.e. not
6878 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6880 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6882 inst
.error
= _("instruction does not accept scaled register index");
6886 encode_arm_addr_mode_common (i
, is_t
);
6888 if (inst
.operands
[i
].immisreg
)
6890 constraint ((inst
.operands
[i
].imm
== REG_PC
6891 || inst
.operands
[i
].reg
== REG_PC
),
6893 inst
.instruction
|= inst
.operands
[i
].imm
;
6894 if (!inst
.operands
[i
].negative
)
6895 inst
.instruction
|= INDEX_UP
;
6897 else /* immediate offset in inst.reloc */
6899 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
6900 && inst
.operands
[i
].writeback
),
6902 inst
.instruction
|= HWOFFSET_IMM
;
6903 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6904 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6908 /* inst.operands[i] was set up by parse_address. Encode it into an
6909 ARM-format instruction. Reject all forms which cannot be encoded
6910 into a coprocessor load/store instruction. If wb_ok is false,
6911 reject use of writeback; if unind_ok is false, reject use of
6912 unindexed addressing. If reloc_override is not 0, use it instead
6913 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6914 (in which case it is preserved). */
6917 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6919 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6921 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6923 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6925 gas_assert (!inst
.operands
[i
].writeback
);
6928 inst
.error
= _("instruction does not support unindexed addressing");
6931 inst
.instruction
|= inst
.operands
[i
].imm
;
6932 inst
.instruction
|= INDEX_UP
;
6936 if (inst
.operands
[i
].preind
)
6937 inst
.instruction
|= PRE_INDEX
;
6939 if (inst
.operands
[i
].writeback
)
6941 if (inst
.operands
[i
].reg
== REG_PC
)
6943 inst
.error
= _("pc may not be used with write-back");
6948 inst
.error
= _("instruction does not support writeback");
6951 inst
.instruction
|= WRITE_BACK
;
6955 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6956 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6957 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6958 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6961 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6963 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6969 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6970 Determine whether it can be performed with a move instruction; if
6971 it can, convert inst.instruction to that move instruction and
6972 return TRUE; if it can't, convert inst.instruction to a literal-pool
6973 load and return FALSE. If this is not a valid thing to do in the
6974 current context, set inst.error and return TRUE.
6976 inst.operands[i] describes the destination register. */
6979 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6984 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6988 if ((inst
.instruction
& tbit
) == 0)
6990 inst
.error
= _("invalid pseudo operation");
6993 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6995 inst
.error
= _("constant expression expected");
6998 if (inst
.reloc
.exp
.X_op
== O_constant
)
7002 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7004 /* This can be done with a mov(1) instruction. */
7005 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7006 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7012 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7015 /* This can be done with a mov instruction. */
7016 inst
.instruction
&= LITERAL_MASK
;
7017 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7018 inst
.instruction
|= value
& 0xfff;
7022 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7025 /* This can be done with a mvn instruction. */
7026 inst
.instruction
&= LITERAL_MASK
;
7027 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7028 inst
.instruction
|= value
& 0xfff;
7034 if (add_to_lit_pool () == FAIL
)
7036 inst
.error
= _("literal pool insertion failed");
7039 inst
.operands
[1].reg
= REG_PC
;
7040 inst
.operands
[1].isreg
= 1;
7041 inst
.operands
[1].preind
= 1;
7042 inst
.reloc
.pc_rel
= 1;
7043 inst
.reloc
.type
= (thumb_p
7044 ? BFD_RELOC_ARM_THUMB_OFFSET
7046 ? BFD_RELOC_ARM_HWLITERAL
7047 : BFD_RELOC_ARM_LITERAL
));
7051 /* Functions for instruction encoding, sorted by sub-architecture.
7052 First some generics; their names are taken from the conventional
7053 bit positions for register arguments in ARM format instructions. */
7063 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7069 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7070 inst
.instruction
|= inst
.operands
[1].reg
;
7076 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7077 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7083 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7084 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7090 unsigned Rn
= inst
.operands
[2].reg
;
7091 /* Enforce restrictions on SWP instruction. */
7092 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7094 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7095 _("Rn must not overlap other operands"));
7097 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7098 if (warn_on_deprecated
7099 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7100 as_warn (_("swp{b} use is deprecated for this architecture"));
7103 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7104 inst
.instruction
|= inst
.operands
[1].reg
;
7105 inst
.instruction
|= Rn
<< 16;
7111 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7112 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7113 inst
.instruction
|= inst
.operands
[2].reg
;
7119 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7120 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7121 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7122 || inst
.reloc
.exp
.X_add_number
!= 0),
7124 inst
.instruction
|= inst
.operands
[0].reg
;
7125 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7126 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7132 inst
.instruction
|= inst
.operands
[0].imm
;
7138 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7139 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7142 /* ARM instructions, in alphabetical order by function name (except
7143 that wrapper functions appear immediately after the function they
7146 /* This is a pseudo-op of the form "adr rd, label" to be converted
7147 into a relative address of the form "add rd, pc, #label-.-8". */
7152 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7154 /* Frag hacking will turn this into a sub instruction if the offset turns
7155 out to be negative. */
7156 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7157 inst
.reloc
.pc_rel
= 1;
7158 inst
.reloc
.exp
.X_add_number
-= 8;
7161 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7162 into a relative address of the form:
7163 add rd, pc, #low(label-.-8)"
7164 add rd, rd, #high(label-.-8)" */
7169 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7171 /* Frag hacking will turn this into a sub instruction if the offset turns
7172 out to be negative. */
7173 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7174 inst
.reloc
.pc_rel
= 1;
7175 inst
.size
= INSN_SIZE
* 2;
7176 inst
.reloc
.exp
.X_add_number
-= 8;
7182 if (!inst
.operands
[1].present
)
7183 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7185 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7186 encode_arm_shifter_operand (2);
7192 if (inst
.operands
[0].present
)
7194 constraint ((inst
.instruction
& 0xf0) != 0x40
7195 && inst
.operands
[0].imm
> 0xf
7196 && inst
.operands
[0].imm
< 0x0,
7197 _("bad barrier type"));
7198 inst
.instruction
|= inst
.operands
[0].imm
;
7201 inst
.instruction
|= 0xf;
7207 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7208 constraint (msb
> 32, _("bit-field extends past end of register"));
7209 /* The instruction encoding stores the LSB and MSB,
7210 not the LSB and width. */
7211 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7212 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7213 inst
.instruction
|= (msb
- 1) << 16;
7221 /* #0 in second position is alternative syntax for bfc, which is
7222 the same instruction but with REG_PC in the Rm field. */
7223 if (!inst
.operands
[1].isreg
)
7224 inst
.operands
[1].reg
= REG_PC
;
7226 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7227 constraint (msb
> 32, _("bit-field extends past end of register"));
7228 /* The instruction encoding stores the LSB and MSB,
7229 not the LSB and width. */
7230 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7231 inst
.instruction
|= inst
.operands
[1].reg
;
7232 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7233 inst
.instruction
|= (msb
- 1) << 16;
7239 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7240 _("bit-field extends past end of register"));
7241 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7242 inst
.instruction
|= inst
.operands
[1].reg
;
7243 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7244 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7247 /* ARM V5 breakpoint instruction (argument parse)
7248 BKPT <16 bit unsigned immediate>
7249 Instruction is not conditional.
7250 The bit pattern given in insns[] has the COND_ALWAYS condition,
7251 and it is an error if the caller tried to override that. */
7256 /* Top 12 of 16 bits to bits 19:8. */
7257 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7259 /* Bottom 4 of 16 bits to bits 3:0. */
7260 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7264 encode_branch (int default_reloc
)
7266 if (inst
.operands
[0].hasreloc
)
7268 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7269 _("the only suffix valid here is '(plt)'"));
7270 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7274 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7276 inst
.reloc
.pc_rel
= 1;
7283 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7284 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7287 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7294 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7296 if (inst
.cond
== COND_ALWAYS
)
7297 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7299 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7303 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7306 /* ARM V5 branch-link-exchange instruction (argument parse)
7307 BLX <target_addr> ie BLX(1)
7308 BLX{<condition>} <Rm> ie BLX(2)
7309 Unfortunately, there are two different opcodes for this mnemonic.
7310 So, the insns[].value is not used, and the code here zaps values
7311 into inst.instruction.
7312 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7317 if (inst
.operands
[0].isreg
)
7319 /* Arg is a register; the opcode provided by insns[] is correct.
7320 It is not illegal to do "blx pc", just useless. */
7321 if (inst
.operands
[0].reg
== REG_PC
)
7322 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7324 inst
.instruction
|= inst
.operands
[0].reg
;
7328 /* Arg is an address; this instruction cannot be executed
7329 conditionally, and the opcode must be adjusted.
7330 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7331 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7332 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7333 inst
.instruction
= 0xfa000000;
7334 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7341 bfd_boolean want_reloc
;
7343 if (inst
.operands
[0].reg
== REG_PC
)
7344 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7346 inst
.instruction
|= inst
.operands
[0].reg
;
7347 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7348 it is for ARMv4t or earlier. */
7349 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7350 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7354 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7359 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7363 /* ARM v5TEJ. Jump to Jazelle code. */
7368 if (inst
.operands
[0].reg
== REG_PC
)
7369 as_tsktsk (_("use of r15 in bxj is not really useful"));
7371 inst
.instruction
|= inst
.operands
[0].reg
;
7374 /* Co-processor data operation:
7375 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7376 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7380 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7381 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7382 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7383 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7384 inst
.instruction
|= inst
.operands
[4].reg
;
7385 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7391 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7392 encode_arm_shifter_operand (1);
7395 /* Transfer between coprocessor and ARM registers.
7396 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7401 No special properties. */
7408 Rd
= inst
.operands
[2].reg
;
7411 if (inst
.instruction
== 0xee000010
7412 || inst
.instruction
== 0xfe000010)
7414 reject_bad_reg (Rd
);
7417 constraint (Rd
== REG_SP
, BAD_SP
);
7422 if (inst
.instruction
== 0xe000010)
7423 constraint (Rd
== REG_PC
, BAD_PC
);
7427 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7428 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7429 inst
.instruction
|= Rd
<< 12;
7430 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7431 inst
.instruction
|= inst
.operands
[4].reg
;
7432 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7435 /* Transfer between coprocessor register and pair of ARM registers.
7436 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7441 Two XScale instructions are special cases of these:
7443 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7444 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7446 Result unpredictable if Rd or Rn is R15. */
7453 Rd
= inst
.operands
[2].reg
;
7454 Rn
= inst
.operands
[3].reg
;
7458 reject_bad_reg (Rd
);
7459 reject_bad_reg (Rn
);
7463 constraint (Rd
== REG_PC
, BAD_PC
);
7464 constraint (Rn
== REG_PC
, BAD_PC
);
7467 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7468 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7469 inst
.instruction
|= Rd
<< 12;
7470 inst
.instruction
|= Rn
<< 16;
7471 inst
.instruction
|= inst
.operands
[4].reg
;
7477 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7478 if (inst
.operands
[1].present
)
7480 inst
.instruction
|= CPSI_MMOD
;
7481 inst
.instruction
|= inst
.operands
[1].imm
;
7488 inst
.instruction
|= inst
.operands
[0].imm
;
7494 /* There is no IT instruction in ARM mode. We
7495 process it to do the validation as if in
7496 thumb mode, just in case the code gets
7497 assembled for thumb using the unified syntax. */
7502 set_it_insn_type (IT_INSN
);
7503 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7504 now_it
.cc
= inst
.operands
[0].imm
;
7511 int base_reg
= inst
.operands
[0].reg
;
7512 int range
= inst
.operands
[1].imm
;
7514 inst
.instruction
|= base_reg
<< 16;
7515 inst
.instruction
|= range
;
7517 if (inst
.operands
[1].writeback
)
7518 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7520 if (inst
.operands
[0].writeback
)
7522 inst
.instruction
|= WRITE_BACK
;
7523 /* Check for unpredictable uses of writeback. */
7524 if (inst
.instruction
& LOAD_BIT
)
7526 /* Not allowed in LDM type 2. */
7527 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7528 && ((range
& (1 << REG_PC
)) == 0))
7529 as_warn (_("writeback of base register is UNPREDICTABLE"));
7530 /* Only allowed if base reg not in list for other types. */
7531 else if (range
& (1 << base_reg
))
7532 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7536 /* Not allowed for type 2. */
7537 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7538 as_warn (_("writeback of base register is UNPREDICTABLE"));
7539 /* Only allowed if base reg not in list, or first in list. */
7540 else if ((range
& (1 << base_reg
))
7541 && (range
& ((1 << base_reg
) - 1)))
7542 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7547 /* ARMv5TE load-consecutive (argument parse)
7556 constraint (inst
.operands
[0].reg
% 2 != 0,
7557 _("first destination register must be even"));
7558 constraint (inst
.operands
[1].present
7559 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7560 _("can only load two consecutive registers"));
7561 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7562 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7564 if (!inst
.operands
[1].present
)
7565 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7567 if (inst
.instruction
& LOAD_BIT
)
7569 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7570 register and the first register written; we have to diagnose
7571 overlap between the base and the second register written here. */
7573 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7574 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7575 as_warn (_("base register written back, and overlaps "
7576 "second destination register"));
7578 /* For an index-register load, the index register must not overlap the
7579 destination (even if not write-back). */
7580 else if (inst
.operands
[2].immisreg
7581 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7582 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7583 as_warn (_("index register overlaps destination register"));
7586 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7587 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7593 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7594 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7595 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7596 || inst
.operands
[1].negative
7597 /* This can arise if the programmer has written
7599 or if they have mistakenly used a register name as the last
7602 It is very difficult to distinguish between these two cases
7603 because "rX" might actually be a label. ie the register
7604 name has been occluded by a symbol of the same name. So we
7605 just generate a general 'bad addressing mode' type error
7606 message and leave it up to the programmer to discover the
7607 true cause and fix their mistake. */
7608 || (inst
.operands
[1].reg
== REG_PC
),
7611 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7612 || inst
.reloc
.exp
.X_add_number
!= 0,
7613 _("offset must be zero in ARM encoding"));
7615 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7617 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7618 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7619 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7625 constraint (inst
.operands
[0].reg
% 2 != 0,
7626 _("even register required"));
7627 constraint (inst
.operands
[1].present
7628 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7629 _("can only load two consecutive registers"));
7630 /* If op 1 were present and equal to PC, this function wouldn't
7631 have been called in the first place. */
7632 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7634 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7635 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7641 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7642 if (!inst
.operands
[1].isreg
)
7643 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7645 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7651 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7653 if (inst
.operands
[1].preind
)
7655 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7656 || inst
.reloc
.exp
.X_add_number
!= 0,
7657 _("this instruction requires a post-indexed address"));
7659 inst
.operands
[1].preind
= 0;
7660 inst
.operands
[1].postind
= 1;
7661 inst
.operands
[1].writeback
= 1;
7663 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7664 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7667 /* Halfword and signed-byte load/store operations. */
7672 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7673 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7674 if (!inst
.operands
[1].isreg
)
7675 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7677 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7683 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7685 if (inst
.operands
[1].preind
)
7687 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7688 || inst
.reloc
.exp
.X_add_number
!= 0,
7689 _("this instruction requires a post-indexed address"));
7691 inst
.operands
[1].preind
= 0;
7692 inst
.operands
[1].postind
= 1;
7693 inst
.operands
[1].writeback
= 1;
7695 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7696 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7699 /* Co-processor register load/store.
7700 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7704 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7705 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7706 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7712 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7713 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7714 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7715 && !(inst
.instruction
& 0x00400000))
7716 as_tsktsk (_("Rd and Rm should be different in mla"));
7718 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7719 inst
.instruction
|= inst
.operands
[1].reg
;
7720 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7721 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7727 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7728 encode_arm_shifter_operand (1);
7731 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7738 top
= (inst
.instruction
& 0x00400000) != 0;
7739 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7740 _(":lower16: not allowed this instruction"));
7741 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7742 _(":upper16: not allowed instruction"));
7743 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7744 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7746 imm
= inst
.reloc
.exp
.X_add_number
;
7747 /* The value is in two pieces: 0:11, 16:19. */
7748 inst
.instruction
|= (imm
& 0x00000fff);
7749 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7753 static void do_vfp_nsyn_opcode (const char *);
7756 do_vfp_nsyn_mrs (void)
7758 if (inst
.operands
[0].isvec
)
7760 if (inst
.operands
[1].reg
!= 1)
7761 first_error (_("operand 1 must be FPSCR"));
7762 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7763 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7764 do_vfp_nsyn_opcode ("fmstat");
7766 else if (inst
.operands
[1].isvec
)
7767 do_vfp_nsyn_opcode ("fmrx");
7775 do_vfp_nsyn_msr (void)
7777 if (inst
.operands
[0].isvec
)
7778 do_vfp_nsyn_opcode ("fmxr");
7788 unsigned Rt
= inst
.operands
[0].reg
;
7790 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7792 inst
.error
= BAD_SP
;
7796 /* APSR_ sets isvec. All other refs to PC are illegal. */
7797 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7799 inst
.error
= BAD_PC
;
7803 if (inst
.operands
[1].reg
!= 1)
7804 first_error (_("operand 1 must be FPSCR"));
7806 inst
.instruction
|= (Rt
<< 12);
7812 unsigned Rt
= inst
.operands
[1].reg
;
7815 reject_bad_reg (Rt
);
7816 else if (Rt
== REG_PC
)
7818 inst
.error
= BAD_PC
;
7822 if (inst
.operands
[0].reg
!= 1)
7823 first_error (_("operand 0 must be FPSCR"));
7825 inst
.instruction
|= (Rt
<< 12);
7831 if (do_vfp_nsyn_mrs () == SUCCESS
)
7834 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7835 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7837 _("'CPSR' or 'SPSR' expected"));
7838 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7839 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7840 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7843 /* Two possible forms:
7844 "{C|S}PSR_<field>, Rm",
7845 "{C|S}PSR_f, #expression". */
7850 if (do_vfp_nsyn_msr () == SUCCESS
)
7853 inst
.instruction
|= inst
.operands
[0].imm
;
7854 if (inst
.operands
[1].isreg
)
7855 inst
.instruction
|= inst
.operands
[1].reg
;
7858 inst
.instruction
|= INST_IMMEDIATE
;
7859 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7860 inst
.reloc
.pc_rel
= 0;
7867 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7869 if (!inst
.operands
[2].present
)
7870 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7871 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7872 inst
.instruction
|= inst
.operands
[1].reg
;
7873 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7875 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7876 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7877 as_tsktsk (_("Rd and Rm should be different in mul"));
7880 /* Long Multiply Parser
7881 UMULL RdLo, RdHi, Rm, Rs
7882 SMULL RdLo, RdHi, Rm, Rs
7883 UMLAL RdLo, RdHi, Rm, Rs
7884 SMLAL RdLo, RdHi, Rm, Rs. */
7889 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7890 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7891 inst
.instruction
|= inst
.operands
[2].reg
;
7892 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7894 /* rdhi and rdlo must be different. */
7895 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7896 as_tsktsk (_("rdhi and rdlo must be different"));
7898 /* rdhi, rdlo and rm must all be different before armv6. */
7899 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7900 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7901 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7902 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7908 if (inst
.operands
[0].present
7909 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7911 /* Architectural NOP hints are CPSR sets with no bits selected. */
7912 inst
.instruction
&= 0xf0000000;
7913 inst
.instruction
|= 0x0320f000;
7914 if (inst
.operands
[0].present
)
7915 inst
.instruction
|= inst
.operands
[0].imm
;
7919 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7920 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7921 Condition defaults to COND_ALWAYS.
7922 Error if Rd, Rn or Rm are R15. */
7927 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7928 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7929 inst
.instruction
|= inst
.operands
[2].reg
;
7930 if (inst
.operands
[3].present
)
7931 encode_arm_shift (3);
7934 /* ARM V6 PKHTB (Argument Parse). */
7939 if (!inst
.operands
[3].present
)
7941 /* If the shift specifier is omitted, turn the instruction
7942 into pkhbt rd, rm, rn. */
7943 inst
.instruction
&= 0xfff00010;
7944 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7945 inst
.instruction
|= inst
.operands
[1].reg
;
7946 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7950 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7951 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7952 inst
.instruction
|= inst
.operands
[2].reg
;
7953 encode_arm_shift (3);
7957 /* ARMv5TE: Preload-Cache
7961 Syntactically, like LDR with B=1, W=0, L=1. */
7966 constraint (!inst
.operands
[0].isreg
,
7967 _("'[' expected after PLD mnemonic"));
7968 constraint (inst
.operands
[0].postind
,
7969 _("post-indexed expression used in preload instruction"));
7970 constraint (inst
.operands
[0].writeback
,
7971 _("writeback used in preload instruction"));
7972 constraint (!inst
.operands
[0].preind
,
7973 _("unindexed addressing used in preload instruction"));
7974 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7977 /* ARMv7: PLI <addr_mode> */
7981 constraint (!inst
.operands
[0].isreg
,
7982 _("'[' expected after PLI mnemonic"));
7983 constraint (inst
.operands
[0].postind
,
7984 _("post-indexed expression used in preload instruction"));
7985 constraint (inst
.operands
[0].writeback
,
7986 _("writeback used in preload instruction"));
7987 constraint (!inst
.operands
[0].preind
,
7988 _("unindexed addressing used in preload instruction"));
7989 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7990 inst
.instruction
&= ~PRE_INDEX
;
7996 inst
.operands
[1] = inst
.operands
[0];
7997 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7998 inst
.operands
[0].isreg
= 1;
7999 inst
.operands
[0].writeback
= 1;
8000 inst
.operands
[0].reg
= REG_SP
;
8004 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8005 word at the specified address and the following word
8007 Unconditionally executed.
8008 Error if Rn is R15. */
8013 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8014 if (inst
.operands
[0].writeback
)
8015 inst
.instruction
|= WRITE_BACK
;
8018 /* ARM V6 ssat (argument parse). */
8023 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8024 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8025 inst
.instruction
|= inst
.operands
[2].reg
;
8027 if (inst
.operands
[3].present
)
8028 encode_arm_shift (3);
8031 /* ARM V6 usat (argument parse). */
8036 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8037 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8038 inst
.instruction
|= inst
.operands
[2].reg
;
8040 if (inst
.operands
[3].present
)
8041 encode_arm_shift (3);
8044 /* ARM V6 ssat16 (argument parse). */
8049 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8050 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8051 inst
.instruction
|= inst
.operands
[2].reg
;
8057 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8058 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8059 inst
.instruction
|= inst
.operands
[2].reg
;
8062 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8063 preserving the other bits.
8065 setend <endian_specifier>, where <endian_specifier> is either
8071 if (inst
.operands
[0].imm
)
8072 inst
.instruction
|= 0x200;
8078 unsigned int Rm
= (inst
.operands
[1].present
8079 ? inst
.operands
[1].reg
8080 : inst
.operands
[0].reg
);
8082 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8083 inst
.instruction
|= Rm
;
8084 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8086 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8087 inst
.instruction
|= SHIFT_BY_REG
;
8090 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8096 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8097 inst
.reloc
.pc_rel
= 0;
8103 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8104 inst
.reloc
.pc_rel
= 0;
8107 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8108 SMLAxy{cond} Rd,Rm,Rs,Rn
8109 SMLAWy{cond} Rd,Rm,Rs,Rn
8110 Error if any register is R15. */
8115 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8116 inst
.instruction
|= inst
.operands
[1].reg
;
8117 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8118 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8121 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8122 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8123 Error if any register is R15.
8124 Warning if Rdlo == Rdhi. */
8129 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8130 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8131 inst
.instruction
|= inst
.operands
[2].reg
;
8132 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8134 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8135 as_tsktsk (_("rdhi and rdlo must be different"));
8138 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8139 SMULxy{cond} Rd,Rm,Rs
8140 Error if any register is R15. */
8145 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8146 inst
.instruction
|= inst
.operands
[1].reg
;
8147 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8150 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8151 the same for both ARM and Thumb-2. */
8158 if (inst
.operands
[0].present
)
8160 reg
= inst
.operands
[0].reg
;
8161 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8166 inst
.instruction
|= reg
<< 16;
8167 inst
.instruction
|= inst
.operands
[1].imm
;
8168 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8169 inst
.instruction
|= WRITE_BACK
;
8172 /* ARM V6 strex (argument parse). */
8177 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8178 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8179 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8180 || inst
.operands
[2].negative
8181 /* See comment in do_ldrex(). */
8182 || (inst
.operands
[2].reg
== REG_PC
),
8185 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8186 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8188 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8189 || inst
.reloc
.exp
.X_add_number
!= 0,
8190 _("offset must be zero in ARM encoding"));
8192 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8193 inst
.instruction
|= inst
.operands
[1].reg
;
8194 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8195 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8201 constraint (inst
.operands
[1].reg
% 2 != 0,
8202 _("even register required"));
8203 constraint (inst
.operands
[2].present
8204 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8205 _("can only store two consecutive registers"));
8206 /* If op 2 were present and equal to PC, this function wouldn't
8207 have been called in the first place. */
8208 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8210 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8211 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8212 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8215 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8216 inst
.instruction
|= inst
.operands
[1].reg
;
8217 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8220 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8221 extends it to 32-bits, and adds the result to a value in another
8222 register. You can specify a rotation by 0, 8, 16, or 24 bits
8223 before extracting the 16-bit value.
8224 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8225 Condition defaults to COND_ALWAYS.
8226 Error if any register uses R15. */
8231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8232 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8233 inst
.instruction
|= inst
.operands
[2].reg
;
8234 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8239 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8240 Condition defaults to COND_ALWAYS.
8241 Error if any register uses R15. */
8246 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8247 inst
.instruction
|= inst
.operands
[1].reg
;
8248 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8251 /* VFP instructions. In a logical order: SP variant first, monad
8252 before dyad, arithmetic then move then load/store. */
8255 do_vfp_sp_monadic (void)
8257 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8258 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8262 do_vfp_sp_dyadic (void)
8264 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8265 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8266 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8270 do_vfp_sp_compare_z (void)
8272 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8276 do_vfp_dp_sp_cvt (void)
8278 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8279 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8283 do_vfp_sp_dp_cvt (void)
8285 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8286 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8290 do_vfp_reg_from_sp (void)
8292 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8293 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8297 do_vfp_reg2_from_sp2 (void)
8299 constraint (inst
.operands
[2].imm
!= 2,
8300 _("only two consecutive VFP SP registers allowed here"));
8301 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8302 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8303 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8307 do_vfp_sp_from_reg (void)
8309 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8310 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8314 do_vfp_sp2_from_reg2 (void)
8316 constraint (inst
.operands
[0].imm
!= 2,
8317 _("only two consecutive VFP SP registers allowed here"));
8318 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8319 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8320 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8324 do_vfp_sp_ldst (void)
8326 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8327 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8331 do_vfp_dp_ldst (void)
8333 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8334 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8339 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8341 if (inst
.operands
[0].writeback
)
8342 inst
.instruction
|= WRITE_BACK
;
8344 constraint (ldstm_type
!= VFP_LDSTMIA
,
8345 _("this addressing mode requires base-register writeback"));
8346 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8347 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8348 inst
.instruction
|= inst
.operands
[1].imm
;
8352 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8356 if (inst
.operands
[0].writeback
)
8357 inst
.instruction
|= WRITE_BACK
;
8359 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8360 _("this addressing mode requires base-register writeback"));
8362 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8363 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8365 count
= inst
.operands
[1].imm
<< 1;
8366 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8369 inst
.instruction
|= count
;
8373 do_vfp_sp_ldstmia (void)
8375 vfp_sp_ldstm (VFP_LDSTMIA
);
8379 do_vfp_sp_ldstmdb (void)
8381 vfp_sp_ldstm (VFP_LDSTMDB
);
8385 do_vfp_dp_ldstmia (void)
8387 vfp_dp_ldstm (VFP_LDSTMIA
);
8391 do_vfp_dp_ldstmdb (void)
8393 vfp_dp_ldstm (VFP_LDSTMDB
);
8397 do_vfp_xp_ldstmia (void)
8399 vfp_dp_ldstm (VFP_LDSTMIAX
);
8403 do_vfp_xp_ldstmdb (void)
8405 vfp_dp_ldstm (VFP_LDSTMDBX
);
8409 do_vfp_dp_rd_rm (void)
8411 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8412 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8416 do_vfp_dp_rn_rd (void)
8418 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8419 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8423 do_vfp_dp_rd_rn (void)
8425 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8426 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8430 do_vfp_dp_rd_rn_rm (void)
8432 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8433 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8434 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8440 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8444 do_vfp_dp_rm_rd_rn (void)
8446 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8447 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8448 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8451 /* VFPv3 instructions. */
8453 do_vfp_sp_const (void)
8455 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8456 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8457 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8461 do_vfp_dp_const (void)
8463 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8464 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8465 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8469 vfp_conv (int srcsize
)
8471 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8472 inst
.instruction
|= (immbits
& 1) << 5;
8473 inst
.instruction
|= (immbits
>> 1);
8477 do_vfp_sp_conv_16 (void)
8479 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8484 do_vfp_dp_conv_16 (void)
8486 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8491 do_vfp_sp_conv_32 (void)
8493 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8498 do_vfp_dp_conv_32 (void)
8500 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8504 /* FPA instructions. Also in a logical order. */
8509 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8510 inst
.instruction
|= inst
.operands
[1].reg
;
8514 do_fpa_ldmstm (void)
8516 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8517 switch (inst
.operands
[1].imm
)
8519 case 1: inst
.instruction
|= CP_T_X
; break;
8520 case 2: inst
.instruction
|= CP_T_Y
; break;
8521 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8526 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8528 /* The instruction specified "ea" or "fd", so we can only accept
8529 [Rn]{!}. The instruction does not really support stacking or
8530 unstacking, so we have to emulate these by setting appropriate
8531 bits and offsets. */
8532 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8533 || inst
.reloc
.exp
.X_add_number
!= 0,
8534 _("this instruction does not support indexing"));
8536 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8537 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8539 if (!(inst
.instruction
& INDEX_UP
))
8540 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8542 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8544 inst
.operands
[2].preind
= 0;
8545 inst
.operands
[2].postind
= 1;
8549 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8552 /* iWMMXt instructions: strictly in alphabetical order. */
8555 do_iwmmxt_tandorc (void)
8557 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8561 do_iwmmxt_textrc (void)
8563 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8564 inst
.instruction
|= inst
.operands
[1].imm
;
8568 do_iwmmxt_textrm (void)
8570 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8571 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8572 inst
.instruction
|= inst
.operands
[2].imm
;
8576 do_iwmmxt_tinsr (void)
8578 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8579 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8580 inst
.instruction
|= inst
.operands
[2].imm
;
8584 do_iwmmxt_tmia (void)
8586 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8587 inst
.instruction
|= inst
.operands
[1].reg
;
8588 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8592 do_iwmmxt_waligni (void)
8594 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8595 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8596 inst
.instruction
|= inst
.operands
[2].reg
;
8597 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8601 do_iwmmxt_wmerge (void)
8603 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8604 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8605 inst
.instruction
|= inst
.operands
[2].reg
;
8606 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8610 do_iwmmxt_wmov (void)
8612 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8613 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8614 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8615 inst
.instruction
|= inst
.operands
[1].reg
;
8619 do_iwmmxt_wldstbh (void)
8622 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8624 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8626 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8627 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8631 do_iwmmxt_wldstw (void)
8633 /* RIWR_RIWC clears .isreg for a control register. */
8634 if (!inst
.operands
[0].isreg
)
8636 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8637 inst
.instruction
|= 0xf0000000;
8640 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8641 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8645 do_iwmmxt_wldstd (void)
8647 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8648 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8649 && inst
.operands
[1].immisreg
)
8651 inst
.instruction
&= ~0x1a000ff;
8652 inst
.instruction
|= (0xf << 28);
8653 if (inst
.operands
[1].preind
)
8654 inst
.instruction
|= PRE_INDEX
;
8655 if (!inst
.operands
[1].negative
)
8656 inst
.instruction
|= INDEX_UP
;
8657 if (inst
.operands
[1].writeback
)
8658 inst
.instruction
|= WRITE_BACK
;
8659 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8660 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8661 inst
.instruction
|= inst
.operands
[1].imm
;
8664 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8668 do_iwmmxt_wshufh (void)
8670 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8671 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8672 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8673 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8677 do_iwmmxt_wzero (void)
8679 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8680 inst
.instruction
|= inst
.operands
[0].reg
;
8681 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8682 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8686 do_iwmmxt_wrwrwr_or_imm5 (void)
8688 if (inst
.operands
[2].isreg
)
8691 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8692 _("immediate operand requires iWMMXt2"));
8694 if (inst
.operands
[2].imm
== 0)
8696 switch ((inst
.instruction
>> 20) & 0xf)
8702 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8703 inst
.operands
[2].imm
= 16;
8704 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8710 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8711 inst
.operands
[2].imm
= 32;
8712 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8719 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8721 wrn
= (inst
.instruction
>> 16) & 0xf;
8722 inst
.instruction
&= 0xff0fff0f;
8723 inst
.instruction
|= wrn
;
8724 /* Bail out here; the instruction is now assembled. */
8729 /* Map 32 -> 0, etc. */
8730 inst
.operands
[2].imm
&= 0x1f;
8731 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8735 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8736 operations first, then control, shift, and load/store. */
8738 /* Insns like "foo X,Y,Z". */
8741 do_mav_triple (void)
8743 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8744 inst
.instruction
|= inst
.operands
[1].reg
;
8745 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8748 /* Insns like "foo W,X,Y,Z".
8749 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8754 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8755 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8756 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8757 inst
.instruction
|= inst
.operands
[3].reg
;
8760 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8764 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8767 /* Maverick shift immediate instructions.
8768 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8769 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8774 int imm
= inst
.operands
[2].imm
;
8776 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8777 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8779 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8780 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8781 Bit 4 should be 0. */
8782 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8784 inst
.instruction
|= imm
;
8787 /* XScale instructions. Also sorted arithmetic before move. */
8789 /* Xscale multiply-accumulate (argument parse)
8792 MIAxycc acc0,Rm,Rs. */
8797 inst
.instruction
|= inst
.operands
[1].reg
;
8798 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8801 /* Xscale move-accumulator-register (argument parse)
8803 MARcc acc0,RdLo,RdHi. */
8808 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8809 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8812 /* Xscale move-register-accumulator (argument parse)
8814 MRAcc RdLo,RdHi,acc0. */
8819 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8820 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8821 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8824 /* Encoding functions relevant only to Thumb. */
8826 /* inst.operands[i] is a shifted-register operand; encode
8827 it into inst.instruction in the format used by Thumb32. */
8830 encode_thumb32_shifted_operand (int i
)
8832 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8833 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8835 constraint (inst
.operands
[i
].immisreg
,
8836 _("shift by register not allowed in thumb mode"));
8837 inst
.instruction
|= inst
.operands
[i
].reg
;
8838 if (shift
== SHIFT_RRX
)
8839 inst
.instruction
|= SHIFT_ROR
<< 4;
8842 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8843 _("expression too complex"));
8845 constraint (value
> 32
8846 || (value
== 32 && (shift
== SHIFT_LSL
8847 || shift
== SHIFT_ROR
)),
8848 _("shift expression is too large"));
8852 else if (value
== 32)
8855 inst
.instruction
|= shift
<< 4;
8856 inst
.instruction
|= (value
& 0x1c) << 10;
8857 inst
.instruction
|= (value
& 0x03) << 6;
8862 /* inst.operands[i] was set up by parse_address. Encode it into a
8863 Thumb32 format load or store instruction. Reject forms that cannot
8864 be used with such instructions. If is_t is true, reject forms that
8865 cannot be used with a T instruction; if is_d is true, reject forms
8866 that cannot be used with a D instruction. If it is a store insn,
8870 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8872 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8874 constraint (!inst
.operands
[i
].isreg
,
8875 _("Instruction does not support =N addresses"));
8877 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8878 if (inst
.operands
[i
].immisreg
)
8880 constraint (is_pc
, BAD_PC_ADDRESSING
);
8881 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8882 constraint (inst
.operands
[i
].negative
,
8883 _("Thumb does not support negative register indexing"));
8884 constraint (inst
.operands
[i
].postind
,
8885 _("Thumb does not support register post-indexing"));
8886 constraint (inst
.operands
[i
].writeback
,
8887 _("Thumb does not support register indexing with writeback"));
8888 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8889 _("Thumb supports only LSL in shifted register indexing"));
8891 inst
.instruction
|= inst
.operands
[i
].imm
;
8892 if (inst
.operands
[i
].shifted
)
8894 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8895 _("expression too complex"));
8896 constraint (inst
.reloc
.exp
.X_add_number
< 0
8897 || inst
.reloc
.exp
.X_add_number
> 3,
8898 _("shift out of range"));
8899 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8901 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8903 else if (inst
.operands
[i
].preind
)
8905 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
8906 constraint (is_t
&& inst
.operands
[i
].writeback
,
8907 _("cannot use writeback with this instruction"));
8908 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
8909 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
8913 inst
.instruction
|= 0x01000000;
8914 if (inst
.operands
[i
].writeback
)
8915 inst
.instruction
|= 0x00200000;
8919 inst
.instruction
|= 0x00000c00;
8920 if (inst
.operands
[i
].writeback
)
8921 inst
.instruction
|= 0x00000100;
8923 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8925 else if (inst
.operands
[i
].postind
)
8927 gas_assert (inst
.operands
[i
].writeback
);
8928 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8929 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8932 inst
.instruction
|= 0x00200000;
8934 inst
.instruction
|= 0x00000900;
8935 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8937 else /* unindexed - only for coprocessor */
8938 inst
.error
= _("instruction does not accept unindexed addressing");
8941 /* Table of Thumb instructions which exist in both 16- and 32-bit
8942 encodings (the latter only in post-V6T2 cores). The index is the
8943 value used in the insns table below. When there is more than one
8944 possible 16-bit encoding for the instruction, this table always
8946 Also contains several pseudo-instructions used during relaxation. */
8947 #define T16_32_TAB \
8948 X(_adc, 4140, eb400000), \
8949 X(_adcs, 4140, eb500000), \
8950 X(_add, 1c00, eb000000), \
8951 X(_adds, 1c00, eb100000), \
8952 X(_addi, 0000, f1000000), \
8953 X(_addis, 0000, f1100000), \
8954 X(_add_pc,000f, f20f0000), \
8955 X(_add_sp,000d, f10d0000), \
8956 X(_adr, 000f, f20f0000), \
8957 X(_and, 4000, ea000000), \
8958 X(_ands, 4000, ea100000), \
8959 X(_asr, 1000, fa40f000), \
8960 X(_asrs, 1000, fa50f000), \
8961 X(_b, e000, f000b000), \
8962 X(_bcond, d000, f0008000), \
8963 X(_bic, 4380, ea200000), \
8964 X(_bics, 4380, ea300000), \
8965 X(_cmn, 42c0, eb100f00), \
8966 X(_cmp, 2800, ebb00f00), \
8967 X(_cpsie, b660, f3af8400), \
8968 X(_cpsid, b670, f3af8600), \
8969 X(_cpy, 4600, ea4f0000), \
8970 X(_dec_sp,80dd, f1ad0d00), \
8971 X(_eor, 4040, ea800000), \
8972 X(_eors, 4040, ea900000), \
8973 X(_inc_sp,00dd, f10d0d00), \
8974 X(_ldmia, c800, e8900000), \
8975 X(_ldr, 6800, f8500000), \
8976 X(_ldrb, 7800, f8100000), \
8977 X(_ldrh, 8800, f8300000), \
8978 X(_ldrsb, 5600, f9100000), \
8979 X(_ldrsh, 5e00, f9300000), \
8980 X(_ldr_pc,4800, f85f0000), \
8981 X(_ldr_pc2,4800, f85f0000), \
8982 X(_ldr_sp,9800, f85d0000), \
8983 X(_lsl, 0000, fa00f000), \
8984 X(_lsls, 0000, fa10f000), \
8985 X(_lsr, 0800, fa20f000), \
8986 X(_lsrs, 0800, fa30f000), \
8987 X(_mov, 2000, ea4f0000), \
8988 X(_movs, 2000, ea5f0000), \
8989 X(_mul, 4340, fb00f000), \
8990 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8991 X(_mvn, 43c0, ea6f0000), \
8992 X(_mvns, 43c0, ea7f0000), \
8993 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8994 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8995 X(_orr, 4300, ea400000), \
8996 X(_orrs, 4300, ea500000), \
8997 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8998 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8999 X(_rev, ba00, fa90f080), \
9000 X(_rev16, ba40, fa90f090), \
9001 X(_revsh, bac0, fa90f0b0), \
9002 X(_ror, 41c0, fa60f000), \
9003 X(_rors, 41c0, fa70f000), \
9004 X(_sbc, 4180, eb600000), \
9005 X(_sbcs, 4180, eb700000), \
9006 X(_stmia, c000, e8800000), \
9007 X(_str, 6000, f8400000), \
9008 X(_strb, 7000, f8000000), \
9009 X(_strh, 8000, f8200000), \
9010 X(_str_sp,9000, f84d0000), \
9011 X(_sub, 1e00, eba00000), \
9012 X(_subs, 1e00, ebb00000), \
9013 X(_subi, 8000, f1a00000), \
9014 X(_subis, 8000, f1b00000), \
9015 X(_sxtb, b240, fa4ff080), \
9016 X(_sxth, b200, fa0ff080), \
9017 X(_tst, 4200, ea100f00), \
9018 X(_uxtb, b2c0, fa5ff080), \
9019 X(_uxth, b280, fa1ff080), \
9020 X(_nop, bf00, f3af8000), \
9021 X(_yield, bf10, f3af8001), \
9022 X(_wfe, bf20, f3af8002), \
9023 X(_wfi, bf30, f3af8003), \
9024 X(_sev, bf40, f3af8004),
9026 /* To catch errors in encoding functions, the codes are all offset by
9027 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9028 as 16-bit instructions. */
9029 #define X(a,b,c) T_MNEM##a
9030 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9033 #define X(a,b,c) 0x##b
9034 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9035 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9038 #define X(a,b,c) 0x##c
9039 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9040 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9041 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9045 /* Thumb instruction encoders, in alphabetical order. */
9050 do_t_add_sub_w (void)
9054 Rd
= inst
.operands
[0].reg
;
9055 Rn
= inst
.operands
[1].reg
;
9057 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9058 is the SP-{plus,minus}-immediate form of the instruction. */
9060 constraint (Rd
== REG_PC
, BAD_PC
);
9062 reject_bad_reg (Rd
);
9064 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9065 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9068 /* Parse an add or subtract instruction. We get here with inst.instruction
9069 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9076 Rd
= inst
.operands
[0].reg
;
9077 Rs
= (inst
.operands
[1].present
9078 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9079 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9082 set_it_insn_type_last ();
9090 flags
= (inst
.instruction
== T_MNEM_adds
9091 || inst
.instruction
== T_MNEM_subs
);
9093 narrow
= !in_it_block ();
9095 narrow
= in_it_block ();
9096 if (!inst
.operands
[2].isreg
)
9100 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9102 add
= (inst
.instruction
== T_MNEM_add
9103 || inst
.instruction
== T_MNEM_adds
);
9105 if (inst
.size_req
!= 4)
9107 /* Attempt to use a narrow opcode, with relaxation if
9109 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9110 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9111 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9112 opcode
= T_MNEM_add_sp
;
9113 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9114 opcode
= T_MNEM_add_pc
;
9115 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9118 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9120 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9124 inst
.instruction
= THUMB_OP16(opcode
);
9125 inst
.instruction
|= (Rd
<< 4) | Rs
;
9126 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9127 if (inst
.size_req
!= 2)
9128 inst
.relax
= opcode
;
9131 constraint (inst
.size_req
== 2, BAD_HIREG
);
9133 if (inst
.size_req
== 4
9134 || (inst
.size_req
!= 2 && !opcode
))
9138 constraint (add
, BAD_PC
);
9139 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9140 _("only SUBS PC, LR, #const allowed"));
9141 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9142 _("expression too complex"));
9143 constraint (inst
.reloc
.exp
.X_add_number
< 0
9144 || inst
.reloc
.exp
.X_add_number
> 0xff,
9145 _("immediate value out of range"));
9146 inst
.instruction
= T2_SUBS_PC_LR
9147 | inst
.reloc
.exp
.X_add_number
;
9148 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9151 else if (Rs
== REG_PC
)
9153 /* Always use addw/subw. */
9154 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9155 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9159 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9160 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9163 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9165 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9167 inst
.instruction
|= Rd
<< 8;
9168 inst
.instruction
|= Rs
<< 16;
9173 Rn
= inst
.operands
[2].reg
;
9174 /* See if we can do this with a 16-bit instruction. */
9175 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9177 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9182 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9183 || inst
.instruction
== T_MNEM_add
)
9186 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9190 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9192 /* Thumb-1 cores (except v6-M) require at least one high
9193 register in a narrow non flag setting add. */
9194 if (Rd
> 7 || Rn
> 7
9195 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9196 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9203 inst
.instruction
= T_OPCODE_ADD_HI
;
9204 inst
.instruction
|= (Rd
& 8) << 4;
9205 inst
.instruction
|= (Rd
& 7);
9206 inst
.instruction
|= Rn
<< 3;
9212 constraint (Rd
== REG_PC
, BAD_PC
);
9213 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9214 constraint (Rs
== REG_PC
, BAD_PC
);
9215 reject_bad_reg (Rn
);
9217 /* If we get here, it can't be done in 16 bits. */
9218 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9219 _("shift must be constant"));
9220 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9221 inst
.instruction
|= Rd
<< 8;
9222 inst
.instruction
|= Rs
<< 16;
9223 encode_thumb32_shifted_operand (2);
9228 constraint (inst
.instruction
== T_MNEM_adds
9229 || inst
.instruction
== T_MNEM_subs
,
9232 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9234 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9235 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9238 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9240 inst
.instruction
|= (Rd
<< 4) | Rs
;
9241 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9245 Rn
= inst
.operands
[2].reg
;
9246 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9248 /* We now have Rd, Rs, and Rn set to registers. */
9249 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9251 /* Can't do this for SUB. */
9252 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9253 inst
.instruction
= T_OPCODE_ADD_HI
;
9254 inst
.instruction
|= (Rd
& 8) << 4;
9255 inst
.instruction
|= (Rd
& 7);
9257 inst
.instruction
|= Rn
<< 3;
9259 inst
.instruction
|= Rs
<< 3;
9261 constraint (1, _("dest must overlap one source register"));
9265 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9266 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9267 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9277 Rd
= inst
.operands
[0].reg
;
9278 reject_bad_reg (Rd
);
9280 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9282 /* Defer to section relaxation. */
9283 inst
.relax
= inst
.instruction
;
9284 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9285 inst
.instruction
|= Rd
<< 4;
9287 else if (unified_syntax
&& inst
.size_req
!= 2)
9289 /* Generate a 32-bit opcode. */
9290 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9291 inst
.instruction
|= Rd
<< 8;
9292 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9293 inst
.reloc
.pc_rel
= 1;
9297 /* Generate a 16-bit opcode. */
9298 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9299 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9300 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9301 inst
.reloc
.pc_rel
= 1;
9303 inst
.instruction
|= Rd
<< 4;
9307 /* Arithmetic instructions for which there is just one 16-bit
9308 instruction encoding, and it allows only two low registers.
9309 For maximal compatibility with ARM syntax, we allow three register
9310 operands even when Thumb-32 instructions are not available, as long
9311 as the first two are identical. For instance, both "sbc r0,r1" and
9312 "sbc r0,r0,r1" are allowed. */
9318 Rd
= inst
.operands
[0].reg
;
9319 Rs
= (inst
.operands
[1].present
9320 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9321 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9322 Rn
= inst
.operands
[2].reg
;
9324 reject_bad_reg (Rd
);
9325 reject_bad_reg (Rs
);
9326 if (inst
.operands
[2].isreg
)
9327 reject_bad_reg (Rn
);
9331 if (!inst
.operands
[2].isreg
)
9333 /* For an immediate, we always generate a 32-bit opcode;
9334 section relaxation will shrink it later if possible. */
9335 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9336 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9337 inst
.instruction
|= Rd
<< 8;
9338 inst
.instruction
|= Rs
<< 16;
9339 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9345 /* See if we can do this with a 16-bit instruction. */
9346 if (THUMB_SETS_FLAGS (inst
.instruction
))
9347 narrow
= !in_it_block ();
9349 narrow
= in_it_block ();
9351 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9353 if (inst
.operands
[2].shifted
)
9355 if (inst
.size_req
== 4)
9361 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9362 inst
.instruction
|= Rd
;
9363 inst
.instruction
|= Rn
<< 3;
9367 /* If we get here, it can't be done in 16 bits. */
9368 constraint (inst
.operands
[2].shifted
9369 && inst
.operands
[2].immisreg
,
9370 _("shift must be constant"));
9371 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9372 inst
.instruction
|= Rd
<< 8;
9373 inst
.instruction
|= Rs
<< 16;
9374 encode_thumb32_shifted_operand (2);
9379 /* On its face this is a lie - the instruction does set the
9380 flags. However, the only supported mnemonic in this mode
9382 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9384 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9385 _("unshifted register required"));
9386 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9387 constraint (Rd
!= Rs
,
9388 _("dest and source1 must be the same register"));
9390 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9391 inst
.instruction
|= Rd
;
9392 inst
.instruction
|= Rn
<< 3;
9396 /* Similarly, but for instructions where the arithmetic operation is
9397 commutative, so we can allow either of them to be different from
9398 the destination operand in a 16-bit instruction. For instance, all
9399 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9406 Rd
= inst
.operands
[0].reg
;
9407 Rs
= (inst
.operands
[1].present
9408 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9409 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9410 Rn
= inst
.operands
[2].reg
;
9412 reject_bad_reg (Rd
);
9413 reject_bad_reg (Rs
);
9414 if (inst
.operands
[2].isreg
)
9415 reject_bad_reg (Rn
);
9419 if (!inst
.operands
[2].isreg
)
9421 /* For an immediate, we always generate a 32-bit opcode;
9422 section relaxation will shrink it later if possible. */
9423 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9424 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9425 inst
.instruction
|= Rd
<< 8;
9426 inst
.instruction
|= Rs
<< 16;
9427 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9433 /* See if we can do this with a 16-bit instruction. */
9434 if (THUMB_SETS_FLAGS (inst
.instruction
))
9435 narrow
= !in_it_block ();
9437 narrow
= in_it_block ();
9439 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9441 if (inst
.operands
[2].shifted
)
9443 if (inst
.size_req
== 4)
9450 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9451 inst
.instruction
|= Rd
;
9452 inst
.instruction
|= Rn
<< 3;
9457 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9458 inst
.instruction
|= Rd
;
9459 inst
.instruction
|= Rs
<< 3;
9464 /* If we get here, it can't be done in 16 bits. */
9465 constraint (inst
.operands
[2].shifted
9466 && inst
.operands
[2].immisreg
,
9467 _("shift must be constant"));
9468 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9469 inst
.instruction
|= Rd
<< 8;
9470 inst
.instruction
|= Rs
<< 16;
9471 encode_thumb32_shifted_operand (2);
9476 /* On its face this is a lie - the instruction does set the
9477 flags. However, the only supported mnemonic in this mode
9479 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9481 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9482 _("unshifted register required"));
9483 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9485 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9486 inst
.instruction
|= Rd
;
9489 inst
.instruction
|= Rn
<< 3;
9491 inst
.instruction
|= Rs
<< 3;
9493 constraint (1, _("dest must overlap one source register"));
9500 if (inst
.operands
[0].present
)
9502 constraint ((inst
.instruction
& 0xf0) != 0x40
9503 && inst
.operands
[0].imm
> 0xf
9504 && inst
.operands
[0].imm
< 0x0,
9505 _("bad barrier type"));
9506 inst
.instruction
|= inst
.operands
[0].imm
;
9509 inst
.instruction
|= 0xf;
9516 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9517 constraint (msb
> 32, _("bit-field extends past end of register"));
9518 /* The instruction encoding stores the LSB and MSB,
9519 not the LSB and width. */
9520 Rd
= inst
.operands
[0].reg
;
9521 reject_bad_reg (Rd
);
9522 inst
.instruction
|= Rd
<< 8;
9523 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9524 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9525 inst
.instruction
|= msb
- 1;
9534 Rd
= inst
.operands
[0].reg
;
9535 reject_bad_reg (Rd
);
9537 /* #0 in second position is alternative syntax for bfc, which is
9538 the same instruction but with REG_PC in the Rm field. */
9539 if (!inst
.operands
[1].isreg
)
9543 Rn
= inst
.operands
[1].reg
;
9544 reject_bad_reg (Rn
);
9547 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9548 constraint (msb
> 32, _("bit-field extends past end of register"));
9549 /* The instruction encoding stores the LSB and MSB,
9550 not the LSB and width. */
9551 inst
.instruction
|= Rd
<< 8;
9552 inst
.instruction
|= Rn
<< 16;
9553 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9554 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9555 inst
.instruction
|= msb
- 1;
9563 Rd
= inst
.operands
[0].reg
;
9564 Rn
= inst
.operands
[1].reg
;
9566 reject_bad_reg (Rd
);
9567 reject_bad_reg (Rn
);
9569 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9570 _("bit-field extends past end of register"));
9571 inst
.instruction
|= Rd
<< 8;
9572 inst
.instruction
|= Rn
<< 16;
9573 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9574 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9575 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9578 /* ARM V5 Thumb BLX (argument parse)
9579 BLX <target_addr> which is BLX(1)
9580 BLX <Rm> which is BLX(2)
9581 Unfortunately, there are two different opcodes for this mnemonic.
9582 So, the insns[].value is not used, and the code here zaps values
9583 into inst.instruction.
9585 ??? How to take advantage of the additional two bits of displacement
9586 available in Thumb32 mode? Need new relocation? */
9591 set_it_insn_type_last ();
9593 if (inst
.operands
[0].isreg
)
9595 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9596 /* We have a register, so this is BLX(2). */
9597 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9601 /* No register. This must be BLX(1). */
9602 inst
.instruction
= 0xf000e800;
9603 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9604 inst
.reloc
.pc_rel
= 1;
9615 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9619 /* Conditional branches inside IT blocks are encoded as unconditional
9626 if (cond
!= COND_ALWAYS
)
9627 opcode
= T_MNEM_bcond
;
9629 opcode
= inst
.instruction
;
9631 if (unified_syntax
&& inst
.size_req
== 4)
9633 inst
.instruction
= THUMB_OP32(opcode
);
9634 if (cond
== COND_ALWAYS
)
9635 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9638 gas_assert (cond
!= 0xF);
9639 inst
.instruction
|= cond
<< 22;
9640 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9645 inst
.instruction
= THUMB_OP16(opcode
);
9646 if (cond
== COND_ALWAYS
)
9647 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9650 inst
.instruction
|= cond
<< 8;
9651 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9653 /* Allow section relaxation. */
9654 if (unified_syntax
&& inst
.size_req
!= 2)
9655 inst
.relax
= opcode
;
9658 inst
.reloc
.pc_rel
= 1;
9664 constraint (inst
.cond
!= COND_ALWAYS
,
9665 _("instruction is always unconditional"));
9666 if (inst
.operands
[0].present
)
9668 constraint (inst
.operands
[0].imm
> 255,
9669 _("immediate value out of range"));
9670 inst
.instruction
|= inst
.operands
[0].imm
;
9671 set_it_insn_type (NEUTRAL_IT_INSN
);
9676 do_t_branch23 (void)
9678 set_it_insn_type_last ();
9679 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9680 inst
.reloc
.pc_rel
= 1;
9682 #if defined(OBJ_COFF)
9683 /* If the destination of the branch is a defined symbol which does not have
9684 the THUMB_FUNC attribute, then we must be calling a function which has
9685 the (interfacearm) attribute. We look for the Thumb entry point to that
9686 function and change the branch to refer to that function instead. */
9687 if ( inst
.reloc
.exp
.X_op
== O_symbol
9688 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9689 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9690 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9691 inst
.reloc
.exp
.X_add_symbol
=
9692 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9699 set_it_insn_type_last ();
9700 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9701 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9702 should cause the alignment to be checked once it is known. This is
9703 because BX PC only works if the instruction is word aligned. */
9711 set_it_insn_type_last ();
9712 Rm
= inst
.operands
[0].reg
;
9713 reject_bad_reg (Rm
);
9714 inst
.instruction
|= Rm
<< 16;
9723 Rd
= inst
.operands
[0].reg
;
9724 Rm
= inst
.operands
[1].reg
;
9726 reject_bad_reg (Rd
);
9727 reject_bad_reg (Rm
);
9729 inst
.instruction
|= Rd
<< 8;
9730 inst
.instruction
|= Rm
<< 16;
9731 inst
.instruction
|= Rm
;
9737 set_it_insn_type (OUTSIDE_IT_INSN
);
9738 inst
.instruction
|= inst
.operands
[0].imm
;
9744 set_it_insn_type (OUTSIDE_IT_INSN
);
9746 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9747 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9749 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9750 inst
.instruction
= 0xf3af8000;
9751 inst
.instruction
|= imod
<< 9;
9752 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9753 if (inst
.operands
[1].present
)
9754 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9758 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9759 && (inst
.operands
[0].imm
& 4),
9760 _("selected processor does not support 'A' form "
9761 "of this instruction"));
9762 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9763 _("Thumb does not support the 2-argument "
9764 "form of this instruction"));
9765 inst
.instruction
|= inst
.operands
[0].imm
;
9769 /* THUMB CPY instruction (argument parse). */
9774 if (inst
.size_req
== 4)
9776 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9777 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9778 inst
.instruction
|= inst
.operands
[1].reg
;
9782 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9783 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9784 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9791 set_it_insn_type (OUTSIDE_IT_INSN
);
9792 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9793 inst
.instruction
|= inst
.operands
[0].reg
;
9794 inst
.reloc
.pc_rel
= 1;
9795 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9801 inst
.instruction
|= inst
.operands
[0].imm
;
9807 unsigned Rd
, Rn
, Rm
;
9809 Rd
= inst
.operands
[0].reg
;
9810 Rn
= (inst
.operands
[1].present
9811 ? inst
.operands
[1].reg
: Rd
);
9812 Rm
= inst
.operands
[2].reg
;
9814 reject_bad_reg (Rd
);
9815 reject_bad_reg (Rn
);
9816 reject_bad_reg (Rm
);
9818 inst
.instruction
|= Rd
<< 8;
9819 inst
.instruction
|= Rn
<< 16;
9820 inst
.instruction
|= Rm
;
9826 if (unified_syntax
&& inst
.size_req
== 4)
9827 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9829 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9835 unsigned int cond
= inst
.operands
[0].imm
;
9837 set_it_insn_type (IT_INSN
);
9838 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9841 /* If the condition is a negative condition, invert the mask. */
9842 if ((cond
& 0x1) == 0x0)
9844 unsigned int mask
= inst
.instruction
& 0x000f;
9846 if ((mask
& 0x7) == 0)
9847 /* no conversion needed */;
9848 else if ((mask
& 0x3) == 0)
9850 else if ((mask
& 0x1) == 0)
9855 inst
.instruction
&= 0xfff0;
9856 inst
.instruction
|= mask
;
9859 inst
.instruction
|= cond
<< 4;
9862 /* Helper function used for both push/pop and ldm/stm. */
9864 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9868 load
= (inst
.instruction
& (1 << 20)) != 0;
9870 if (mask
& (1 << 13))
9871 inst
.error
= _("SP not allowed in register list");
9873 if ((mask
& (1 << base
)) != 0
9875 inst
.error
= _("having the base register in the register list when "
9876 "using write back is UNPREDICTABLE");
9880 if (mask
& (1 << 15))
9882 if (mask
& (1 << 14))
9883 inst
.error
= _("LR and PC should not both be in register list");
9885 set_it_insn_type_last ();
9890 if (mask
& (1 << 15))
9891 inst
.error
= _("PC not allowed in register list");
9894 if ((mask
& (mask
- 1)) == 0)
9896 /* Single register transfers implemented as str/ldr. */
9899 if (inst
.instruction
& (1 << 23))
9900 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9902 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9906 if (inst
.instruction
& (1 << 23))
9907 inst
.instruction
= 0x00800000; /* ia -> [base] */
9909 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9912 inst
.instruction
|= 0xf8400000;
9914 inst
.instruction
|= 0x00100000;
9916 mask
= ffs (mask
) - 1;
9920 inst
.instruction
|= WRITE_BACK
;
9922 inst
.instruction
|= mask
;
9923 inst
.instruction
|= base
<< 16;
9929 /* This really doesn't seem worth it. */
9930 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9931 _("expression too complex"));
9932 constraint (inst
.operands
[1].writeback
,
9933 _("Thumb load/store multiple does not support {reglist}^"));
9941 /* See if we can use a 16-bit instruction. */
9942 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9943 && inst
.size_req
!= 4
9944 && !(inst
.operands
[1].imm
& ~0xff))
9946 mask
= 1 << inst
.operands
[0].reg
;
9948 if (inst
.operands
[0].reg
<= 7)
9950 if (inst
.instruction
== T_MNEM_stmia
9951 ? inst
.operands
[0].writeback
9952 : (inst
.operands
[0].writeback
9953 == !(inst
.operands
[1].imm
& mask
)))
9955 if (inst
.instruction
== T_MNEM_stmia
9956 && (inst
.operands
[1].imm
& mask
)
9957 && (inst
.operands
[1].imm
& (mask
- 1)))
9958 as_warn (_("value stored for r%d is UNKNOWN"),
9959 inst
.operands
[0].reg
);
9961 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9962 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9963 inst
.instruction
|= inst
.operands
[1].imm
;
9966 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
9968 /* This means 1 register in reg list one of 3 situations:
9969 1. Instruction is stmia, but without writeback.
9970 2. lmdia without writeback, but with Rn not in
9972 3. ldmia with writeback, but with Rn in reglist.
9973 Case 3 is UNPREDICTABLE behaviour, so we handle
9974 case 1 and 2 which can be converted into a 16-bit
9975 str or ldr. The SP cases are handled below. */
9976 unsigned long opcode
;
9977 /* First, record an error for Case 3. */
9978 if (inst
.operands
[1].imm
& mask
9979 && inst
.operands
[0].writeback
)
9981 _("having the base register in the register list when "
9982 "using write back is UNPREDICTABLE");
9984 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
9986 inst
.instruction
= THUMB_OP16 (opcode
);
9987 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9988 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
9992 else if (inst
.operands
[0] .reg
== REG_SP
)
9994 if (inst
.operands
[0].writeback
)
9997 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9998 ? T_MNEM_push
: T_MNEM_pop
);
9999 inst
.instruction
|= inst
.operands
[1].imm
;
10002 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10005 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10006 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10007 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10015 if (inst
.instruction
< 0xffff)
10016 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10018 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10019 inst
.operands
[0].writeback
);
10024 constraint (inst
.operands
[0].reg
> 7
10025 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10026 constraint (inst
.instruction
!= T_MNEM_ldmia
10027 && inst
.instruction
!= T_MNEM_stmia
,
10028 _("Thumb-2 instruction only valid in unified syntax"));
10029 if (inst
.instruction
== T_MNEM_stmia
)
10031 if (!inst
.operands
[0].writeback
)
10032 as_warn (_("this instruction will write back the base register"));
10033 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10034 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10035 as_warn (_("value stored for r%d is UNKNOWN"),
10036 inst
.operands
[0].reg
);
10040 if (!inst
.operands
[0].writeback
10041 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10042 as_warn (_("this instruction will write back the base register"));
10043 else if (inst
.operands
[0].writeback
10044 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10045 as_warn (_("this instruction will not write back the base register"));
10048 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10049 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10050 inst
.instruction
|= inst
.operands
[1].imm
;
10057 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10058 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10059 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10060 || inst
.operands
[1].negative
,
10063 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10065 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10066 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10067 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10073 if (!inst
.operands
[1].present
)
10075 constraint (inst
.operands
[0].reg
== REG_LR
,
10076 _("r14 not allowed as first register "
10077 "when second register is omitted"));
10078 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10080 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10083 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10084 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10085 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10091 unsigned long opcode
;
10094 if (inst
.operands
[0].isreg
10095 && !inst
.operands
[0].preind
10096 && inst
.operands
[0].reg
== REG_PC
)
10097 set_it_insn_type_last ();
10099 opcode
= inst
.instruction
;
10100 if (unified_syntax
)
10102 if (!inst
.operands
[1].isreg
)
10104 if (opcode
<= 0xffff)
10105 inst
.instruction
= THUMB_OP32 (opcode
);
10106 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10109 if (inst
.operands
[1].isreg
10110 && !inst
.operands
[1].writeback
10111 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10112 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10113 && opcode
<= 0xffff
10114 && inst
.size_req
!= 4)
10116 /* Insn may have a 16-bit form. */
10117 Rn
= inst
.operands
[1].reg
;
10118 if (inst
.operands
[1].immisreg
)
10120 inst
.instruction
= THUMB_OP16 (opcode
);
10122 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10124 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10125 reject_bad_reg (inst
.operands
[1].imm
);
10127 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10128 && opcode
!= T_MNEM_ldrsb
)
10129 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10130 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10137 if (inst
.reloc
.pc_rel
)
10138 opcode
= T_MNEM_ldr_pc2
;
10140 opcode
= T_MNEM_ldr_pc
;
10144 if (opcode
== T_MNEM_ldr
)
10145 opcode
= T_MNEM_ldr_sp
;
10147 opcode
= T_MNEM_str_sp
;
10149 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10153 inst
.instruction
= inst
.operands
[0].reg
;
10154 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10156 inst
.instruction
|= THUMB_OP16 (opcode
);
10157 if (inst
.size_req
== 2)
10158 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10160 inst
.relax
= opcode
;
10164 /* Definitely a 32-bit variant. */
10166 /* Do some validations regarding addressing modes. */
10167 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10168 && opcode
!= T_MNEM_str
)
10169 reject_bad_reg (inst
.operands
[1].imm
);
10171 inst
.instruction
= THUMB_OP32 (opcode
);
10172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10173 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10177 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10179 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10181 /* Only [Rn,Rm] is acceptable. */
10182 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10183 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10184 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10185 || inst
.operands
[1].negative
,
10186 _("Thumb does not support this addressing mode"));
10187 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10191 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10192 if (!inst
.operands
[1].isreg
)
10193 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10196 constraint (!inst
.operands
[1].preind
10197 || inst
.operands
[1].shifted
10198 || inst
.operands
[1].writeback
,
10199 _("Thumb does not support this addressing mode"));
10200 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10202 constraint (inst
.instruction
& 0x0600,
10203 _("byte or halfword not valid for base register"));
10204 constraint (inst
.operands
[1].reg
== REG_PC
10205 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10206 _("r15 based store not allowed"));
10207 constraint (inst
.operands
[1].immisreg
,
10208 _("invalid base register for register offset"));
10210 if (inst
.operands
[1].reg
== REG_PC
)
10211 inst
.instruction
= T_OPCODE_LDR_PC
;
10212 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10213 inst
.instruction
= T_OPCODE_LDR_SP
;
10215 inst
.instruction
= T_OPCODE_STR_SP
;
10217 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10218 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10222 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10223 if (!inst
.operands
[1].immisreg
)
10225 /* Immediate offset. */
10226 inst
.instruction
|= inst
.operands
[0].reg
;
10227 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10228 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10232 /* Register offset. */
10233 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10234 constraint (inst
.operands
[1].negative
,
10235 _("Thumb does not support this addressing mode"));
10238 switch (inst
.instruction
)
10240 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10241 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10242 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10243 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10244 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10245 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10246 case 0x5600 /* ldrsb */:
10247 case 0x5e00 /* ldrsh */: break;
10251 inst
.instruction
|= inst
.operands
[0].reg
;
10252 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10253 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10259 if (!inst
.operands
[1].present
)
10261 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10262 constraint (inst
.operands
[0].reg
== REG_LR
,
10263 _("r14 not allowed here"));
10265 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10266 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10267 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10273 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10274 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10280 unsigned Rd
, Rn
, Rm
, Ra
;
10282 Rd
= inst
.operands
[0].reg
;
10283 Rn
= inst
.operands
[1].reg
;
10284 Rm
= inst
.operands
[2].reg
;
10285 Ra
= inst
.operands
[3].reg
;
10287 reject_bad_reg (Rd
);
10288 reject_bad_reg (Rn
);
10289 reject_bad_reg (Rm
);
10290 reject_bad_reg (Ra
);
10292 inst
.instruction
|= Rd
<< 8;
10293 inst
.instruction
|= Rn
<< 16;
10294 inst
.instruction
|= Rm
;
10295 inst
.instruction
|= Ra
<< 12;
10301 unsigned RdLo
, RdHi
, Rn
, Rm
;
10303 RdLo
= inst
.operands
[0].reg
;
10304 RdHi
= inst
.operands
[1].reg
;
10305 Rn
= inst
.operands
[2].reg
;
10306 Rm
= inst
.operands
[3].reg
;
10308 reject_bad_reg (RdLo
);
10309 reject_bad_reg (RdHi
);
10310 reject_bad_reg (Rn
);
10311 reject_bad_reg (Rm
);
10313 inst
.instruction
|= RdLo
<< 12;
10314 inst
.instruction
|= RdHi
<< 8;
10315 inst
.instruction
|= Rn
<< 16;
10316 inst
.instruction
|= Rm
;
10320 do_t_mov_cmp (void)
10324 Rn
= inst
.operands
[0].reg
;
10325 Rm
= inst
.operands
[1].reg
;
10328 set_it_insn_type_last ();
10330 if (unified_syntax
)
10332 int r0off
= (inst
.instruction
== T_MNEM_mov
10333 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10334 unsigned long opcode
;
10335 bfd_boolean narrow
;
10336 bfd_boolean low_regs
;
10338 low_regs
= (Rn
<= 7 && Rm
<= 7);
10339 opcode
= inst
.instruction
;
10340 if (in_it_block ())
10341 narrow
= opcode
!= T_MNEM_movs
;
10343 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10344 if (inst
.size_req
== 4
10345 || inst
.operands
[1].shifted
)
10348 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10349 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10350 && !inst
.operands
[1].shifted
10354 inst
.instruction
= T2_SUBS_PC_LR
;
10358 if (opcode
== T_MNEM_cmp
)
10360 constraint (Rn
== REG_PC
, BAD_PC
);
10363 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10365 warn_deprecated_sp (Rm
);
10366 /* R15 was documented as a valid choice for Rm in ARMv6,
10367 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10368 tools reject R15, so we do too. */
10369 constraint (Rm
== REG_PC
, BAD_PC
);
10372 reject_bad_reg (Rm
);
10374 else if (opcode
== T_MNEM_mov
10375 || opcode
== T_MNEM_movs
)
10377 if (inst
.operands
[1].isreg
)
10379 if (opcode
== T_MNEM_movs
)
10381 reject_bad_reg (Rn
);
10382 reject_bad_reg (Rm
);
10386 /* This is mov.n. */
10387 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10388 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10390 as_warn (_("Use of r%u as a source register is "
10391 "deprecated when r%u is the destination "
10392 "register."), Rm
, Rn
);
10397 /* This is mov.w. */
10398 constraint (Rn
== REG_PC
, BAD_PC
);
10399 constraint (Rm
== REG_PC
, BAD_PC
);
10400 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10404 reject_bad_reg (Rn
);
10407 if (!inst
.operands
[1].isreg
)
10409 /* Immediate operand. */
10410 if (!in_it_block () && opcode
== T_MNEM_mov
)
10412 if (low_regs
&& narrow
)
10414 inst
.instruction
= THUMB_OP16 (opcode
);
10415 inst
.instruction
|= Rn
<< 8;
10416 if (inst
.size_req
== 2)
10417 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10419 inst
.relax
= opcode
;
10423 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10424 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10425 inst
.instruction
|= Rn
<< r0off
;
10426 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10429 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10430 && (inst
.instruction
== T_MNEM_mov
10431 || inst
.instruction
== T_MNEM_movs
))
10433 /* Register shifts are encoded as separate shift instructions. */
10434 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10436 if (in_it_block ())
10441 if (inst
.size_req
== 4)
10444 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10450 switch (inst
.operands
[1].shift_kind
)
10453 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10456 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10459 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10462 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10468 inst
.instruction
= opcode
;
10471 inst
.instruction
|= Rn
;
10472 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10477 inst
.instruction
|= CONDS_BIT
;
10479 inst
.instruction
|= Rn
<< 8;
10480 inst
.instruction
|= Rm
<< 16;
10481 inst
.instruction
|= inst
.operands
[1].imm
;
10486 /* Some mov with immediate shift have narrow variants.
10487 Register shifts are handled above. */
10488 if (low_regs
&& inst
.operands
[1].shifted
10489 && (inst
.instruction
== T_MNEM_mov
10490 || inst
.instruction
== T_MNEM_movs
))
10492 if (in_it_block ())
10493 narrow
= (inst
.instruction
== T_MNEM_mov
);
10495 narrow
= (inst
.instruction
== T_MNEM_movs
);
10500 switch (inst
.operands
[1].shift_kind
)
10502 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10503 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10504 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10505 default: narrow
= FALSE
; break;
10511 inst
.instruction
|= Rn
;
10512 inst
.instruction
|= Rm
<< 3;
10513 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10517 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10518 inst
.instruction
|= Rn
<< r0off
;
10519 encode_thumb32_shifted_operand (1);
10523 switch (inst
.instruction
)
10526 inst
.instruction
= T_OPCODE_MOV_HR
;
10527 inst
.instruction
|= (Rn
& 0x8) << 4;
10528 inst
.instruction
|= (Rn
& 0x7);
10529 inst
.instruction
|= Rm
<< 3;
10533 /* We know we have low registers at this point.
10534 Generate LSLS Rd, Rs, #0. */
10535 inst
.instruction
= T_OPCODE_LSL_I
;
10536 inst
.instruction
|= Rn
;
10537 inst
.instruction
|= Rm
<< 3;
10543 inst
.instruction
= T_OPCODE_CMP_LR
;
10544 inst
.instruction
|= Rn
;
10545 inst
.instruction
|= Rm
<< 3;
10549 inst
.instruction
= T_OPCODE_CMP_HR
;
10550 inst
.instruction
|= (Rn
& 0x8) << 4;
10551 inst
.instruction
|= (Rn
& 0x7);
10552 inst
.instruction
|= Rm
<< 3;
10559 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10561 /* PR 10443: Do not silently ignore shifted operands. */
10562 constraint (inst
.operands
[1].shifted
,
10563 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10565 if (inst
.operands
[1].isreg
)
10567 if (Rn
< 8 && Rm
< 8)
10569 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10570 since a MOV instruction produces unpredictable results. */
10571 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10572 inst
.instruction
= T_OPCODE_ADD_I3
;
10574 inst
.instruction
= T_OPCODE_CMP_LR
;
10576 inst
.instruction
|= Rn
;
10577 inst
.instruction
|= Rm
<< 3;
10581 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10582 inst
.instruction
= T_OPCODE_MOV_HR
;
10584 inst
.instruction
= T_OPCODE_CMP_HR
;
10590 constraint (Rn
> 7,
10591 _("only lo regs allowed with immediate"));
10592 inst
.instruction
|= Rn
<< 8;
10593 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10604 top
= (inst
.instruction
& 0x00800000) != 0;
10605 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10607 constraint (top
, _(":lower16: not allowed this instruction"));
10608 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10610 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10612 constraint (!top
, _(":upper16: not allowed this instruction"));
10613 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10616 Rd
= inst
.operands
[0].reg
;
10617 reject_bad_reg (Rd
);
10619 inst
.instruction
|= Rd
<< 8;
10620 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10622 imm
= inst
.reloc
.exp
.X_add_number
;
10623 inst
.instruction
|= (imm
& 0xf000) << 4;
10624 inst
.instruction
|= (imm
& 0x0800) << 15;
10625 inst
.instruction
|= (imm
& 0x0700) << 4;
10626 inst
.instruction
|= (imm
& 0x00ff);
10631 do_t_mvn_tst (void)
10635 Rn
= inst
.operands
[0].reg
;
10636 Rm
= inst
.operands
[1].reg
;
10638 if (inst
.instruction
== T_MNEM_cmp
10639 || inst
.instruction
== T_MNEM_cmn
)
10640 constraint (Rn
== REG_PC
, BAD_PC
);
10642 reject_bad_reg (Rn
);
10643 reject_bad_reg (Rm
);
10645 if (unified_syntax
)
10647 int r0off
= (inst
.instruction
== T_MNEM_mvn
10648 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10649 bfd_boolean narrow
;
10651 if (inst
.size_req
== 4
10652 || inst
.instruction
> 0xffff
10653 || inst
.operands
[1].shifted
10654 || Rn
> 7 || Rm
> 7)
10656 else if (inst
.instruction
== T_MNEM_cmn
)
10658 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10659 narrow
= !in_it_block ();
10661 narrow
= in_it_block ();
10663 if (!inst
.operands
[1].isreg
)
10665 /* For an immediate, we always generate a 32-bit opcode;
10666 section relaxation will shrink it later if possible. */
10667 if (inst
.instruction
< 0xffff)
10668 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10669 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10670 inst
.instruction
|= Rn
<< r0off
;
10671 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10675 /* See if we can do this with a 16-bit instruction. */
10678 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10679 inst
.instruction
|= Rn
;
10680 inst
.instruction
|= Rm
<< 3;
10684 constraint (inst
.operands
[1].shifted
10685 && inst
.operands
[1].immisreg
,
10686 _("shift must be constant"));
10687 if (inst
.instruction
< 0xffff)
10688 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10689 inst
.instruction
|= Rn
<< r0off
;
10690 encode_thumb32_shifted_operand (1);
10696 constraint (inst
.instruction
> 0xffff
10697 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10698 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10699 _("unshifted register required"));
10700 constraint (Rn
> 7 || Rm
> 7,
10703 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10704 inst
.instruction
|= Rn
;
10705 inst
.instruction
|= Rm
<< 3;
10715 if (do_vfp_nsyn_mrs () == SUCCESS
)
10718 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10721 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10722 _("selected processor does not support "
10723 "requested special purpose register"));
10727 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10728 _("selected processor does not support "
10729 "requested special purpose register"));
10730 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10731 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10732 _("'CPSR' or 'SPSR' expected"));
10735 Rd
= inst
.operands
[0].reg
;
10736 reject_bad_reg (Rd
);
10738 inst
.instruction
|= Rd
<< 8;
10739 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10740 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10749 if (do_vfp_nsyn_msr () == SUCCESS
)
10752 constraint (!inst
.operands
[1].isreg
,
10753 _("Thumb encoding does not support an immediate here"));
10754 flags
= inst
.operands
[0].imm
;
10757 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10758 _("selected processor does not support "
10759 "requested special purpose register"));
10763 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10764 _("selected processor does not support "
10765 "requested special purpose register"));
10769 Rn
= inst
.operands
[1].reg
;
10770 reject_bad_reg (Rn
);
10772 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10773 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10774 inst
.instruction
|= (flags
& 0xff);
10775 inst
.instruction
|= Rn
<< 16;
10781 bfd_boolean narrow
;
10782 unsigned Rd
, Rn
, Rm
;
10784 if (!inst
.operands
[2].present
)
10785 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10787 Rd
= inst
.operands
[0].reg
;
10788 Rn
= inst
.operands
[1].reg
;
10789 Rm
= inst
.operands
[2].reg
;
10791 if (unified_syntax
)
10793 if (inst
.size_req
== 4
10799 else if (inst
.instruction
== T_MNEM_muls
)
10800 narrow
= !in_it_block ();
10802 narrow
= in_it_block ();
10806 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10807 constraint (Rn
> 7 || Rm
> 7,
10814 /* 16-bit MULS/Conditional MUL. */
10815 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10816 inst
.instruction
|= Rd
;
10819 inst
.instruction
|= Rm
<< 3;
10821 inst
.instruction
|= Rn
<< 3;
10823 constraint (1, _("dest must overlap one source register"));
10827 constraint (inst
.instruction
!= T_MNEM_mul
,
10828 _("Thumb-2 MUL must not set flags"));
10830 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10831 inst
.instruction
|= Rd
<< 8;
10832 inst
.instruction
|= Rn
<< 16;
10833 inst
.instruction
|= Rm
<< 0;
10835 reject_bad_reg (Rd
);
10836 reject_bad_reg (Rn
);
10837 reject_bad_reg (Rm
);
10844 unsigned RdLo
, RdHi
, Rn
, Rm
;
10846 RdLo
= inst
.operands
[0].reg
;
10847 RdHi
= inst
.operands
[1].reg
;
10848 Rn
= inst
.operands
[2].reg
;
10849 Rm
= inst
.operands
[3].reg
;
10851 reject_bad_reg (RdLo
);
10852 reject_bad_reg (RdHi
);
10853 reject_bad_reg (Rn
);
10854 reject_bad_reg (Rm
);
10856 inst
.instruction
|= RdLo
<< 12;
10857 inst
.instruction
|= RdHi
<< 8;
10858 inst
.instruction
|= Rn
<< 16;
10859 inst
.instruction
|= Rm
;
10862 as_tsktsk (_("rdhi and rdlo must be different"));
10868 set_it_insn_type (NEUTRAL_IT_INSN
);
10870 if (unified_syntax
)
10872 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10874 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10875 inst
.instruction
|= inst
.operands
[0].imm
;
10879 /* PR9722: Check for Thumb2 availability before
10880 generating a thumb2 nop instruction. */
10881 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10883 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10884 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10887 inst
.instruction
= 0x46c0;
10892 constraint (inst
.operands
[0].present
,
10893 _("Thumb does not support NOP with hints"));
10894 inst
.instruction
= 0x46c0;
10901 if (unified_syntax
)
10903 bfd_boolean narrow
;
10905 if (THUMB_SETS_FLAGS (inst
.instruction
))
10906 narrow
= !in_it_block ();
10908 narrow
= in_it_block ();
10909 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10911 if (inst
.size_req
== 4)
10916 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10917 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10918 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10922 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10923 inst
.instruction
|= inst
.operands
[0].reg
;
10924 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10929 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10931 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10933 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10934 inst
.instruction
|= inst
.operands
[0].reg
;
10935 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10944 Rd
= inst
.operands
[0].reg
;
10945 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10947 reject_bad_reg (Rd
);
10948 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10949 reject_bad_reg (Rn
);
10951 inst
.instruction
|= Rd
<< 8;
10952 inst
.instruction
|= Rn
<< 16;
10954 if (!inst
.operands
[2].isreg
)
10956 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10957 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10963 Rm
= inst
.operands
[2].reg
;
10964 reject_bad_reg (Rm
);
10966 constraint (inst
.operands
[2].shifted
10967 && inst
.operands
[2].immisreg
,
10968 _("shift must be constant"));
10969 encode_thumb32_shifted_operand (2);
10976 unsigned Rd
, Rn
, Rm
;
10978 Rd
= inst
.operands
[0].reg
;
10979 Rn
= inst
.operands
[1].reg
;
10980 Rm
= inst
.operands
[2].reg
;
10982 reject_bad_reg (Rd
);
10983 reject_bad_reg (Rn
);
10984 reject_bad_reg (Rm
);
10986 inst
.instruction
|= Rd
<< 8;
10987 inst
.instruction
|= Rn
<< 16;
10988 inst
.instruction
|= Rm
;
10989 if (inst
.operands
[3].present
)
10991 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10992 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10993 _("expression too complex"));
10994 inst
.instruction
|= (val
& 0x1c) << 10;
10995 inst
.instruction
|= (val
& 0x03) << 6;
11002 if (!inst
.operands
[3].present
)
11006 inst
.instruction
&= ~0x00000020;
11008 /* PR 10168. Swap the Rm and Rn registers. */
11009 Rtmp
= inst
.operands
[1].reg
;
11010 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11011 inst
.operands
[2].reg
= Rtmp
;
11019 if (inst
.operands
[0].immisreg
)
11020 reject_bad_reg (inst
.operands
[0].imm
);
11022 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11026 do_t_push_pop (void)
11030 constraint (inst
.operands
[0].writeback
,
11031 _("push/pop do not support {reglist}^"));
11032 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11033 _("expression too complex"));
11035 mask
= inst
.operands
[0].imm
;
11036 if ((mask
& ~0xff) == 0)
11037 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11038 else if ((inst
.instruction
== T_MNEM_push
11039 && (mask
& ~0xff) == 1 << REG_LR
)
11040 || (inst
.instruction
== T_MNEM_pop
11041 && (mask
& ~0xff) == 1 << REG_PC
))
11043 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11044 inst
.instruction
|= THUMB_PP_PC_LR
;
11045 inst
.instruction
|= mask
& 0xff;
11047 else if (unified_syntax
)
11049 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11050 encode_thumb2_ldmstm (13, mask
, TRUE
);
11054 inst
.error
= _("invalid register list to push/pop instruction");
11064 Rd
= inst
.operands
[0].reg
;
11065 Rm
= inst
.operands
[1].reg
;
11067 reject_bad_reg (Rd
);
11068 reject_bad_reg (Rm
);
11070 inst
.instruction
|= Rd
<< 8;
11071 inst
.instruction
|= Rm
<< 16;
11072 inst
.instruction
|= Rm
;
11080 Rd
= inst
.operands
[0].reg
;
11081 Rm
= inst
.operands
[1].reg
;
11083 reject_bad_reg (Rd
);
11084 reject_bad_reg (Rm
);
11086 if (Rd
<= 7 && Rm
<= 7
11087 && inst
.size_req
!= 4)
11089 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11090 inst
.instruction
|= Rd
;
11091 inst
.instruction
|= Rm
<< 3;
11093 else if (unified_syntax
)
11095 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11096 inst
.instruction
|= Rd
<< 8;
11097 inst
.instruction
|= Rm
<< 16;
11098 inst
.instruction
|= Rm
;
11101 inst
.error
= BAD_HIREG
;
11109 Rd
= inst
.operands
[0].reg
;
11110 Rm
= inst
.operands
[1].reg
;
11112 reject_bad_reg (Rd
);
11113 reject_bad_reg (Rm
);
11115 inst
.instruction
|= Rd
<< 8;
11116 inst
.instruction
|= Rm
;
11124 Rd
= inst
.operands
[0].reg
;
11125 Rs
= (inst
.operands
[1].present
11126 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11127 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11129 reject_bad_reg (Rd
);
11130 reject_bad_reg (Rs
);
11131 if (inst
.operands
[2].isreg
)
11132 reject_bad_reg (inst
.operands
[2].reg
);
11134 inst
.instruction
|= Rd
<< 8;
11135 inst
.instruction
|= Rs
<< 16;
11136 if (!inst
.operands
[2].isreg
)
11138 bfd_boolean narrow
;
11140 if ((inst
.instruction
& 0x00100000) != 0)
11141 narrow
= !in_it_block ();
11143 narrow
= in_it_block ();
11145 if (Rd
> 7 || Rs
> 7)
11148 if (inst
.size_req
== 4 || !unified_syntax
)
11151 if (inst
.reloc
.exp
.X_op
!= O_constant
11152 || inst
.reloc
.exp
.X_add_number
!= 0)
11155 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11156 relaxation, but it doesn't seem worth the hassle. */
11159 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11160 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11161 inst
.instruction
|= Rs
<< 3;
11162 inst
.instruction
|= Rd
;
11166 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11167 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11171 encode_thumb32_shifted_operand (2);
11177 set_it_insn_type (OUTSIDE_IT_INSN
);
11178 if (inst
.operands
[0].imm
)
11179 inst
.instruction
|= 0x8;
11185 if (!inst
.operands
[1].present
)
11186 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11188 if (unified_syntax
)
11190 bfd_boolean narrow
;
11193 switch (inst
.instruction
)
11196 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11198 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11200 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11202 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11206 if (THUMB_SETS_FLAGS (inst
.instruction
))
11207 narrow
= !in_it_block ();
11209 narrow
= in_it_block ();
11210 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11212 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11214 if (inst
.operands
[2].isreg
11215 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11216 || inst
.operands
[2].reg
> 7))
11218 if (inst
.size_req
== 4)
11221 reject_bad_reg (inst
.operands
[0].reg
);
11222 reject_bad_reg (inst
.operands
[1].reg
);
11226 if (inst
.operands
[2].isreg
)
11228 reject_bad_reg (inst
.operands
[2].reg
);
11229 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11230 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11231 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11232 inst
.instruction
|= inst
.operands
[2].reg
;
11236 inst
.operands
[1].shifted
= 1;
11237 inst
.operands
[1].shift_kind
= shift_kind
;
11238 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11239 ? T_MNEM_movs
: T_MNEM_mov
);
11240 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11241 encode_thumb32_shifted_operand (1);
11242 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11243 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11248 if (inst
.operands
[2].isreg
)
11250 switch (shift_kind
)
11252 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11253 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11254 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11255 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11259 inst
.instruction
|= inst
.operands
[0].reg
;
11260 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11264 switch (shift_kind
)
11266 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11267 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11268 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11271 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11272 inst
.instruction
|= inst
.operands
[0].reg
;
11273 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11279 constraint (inst
.operands
[0].reg
> 7
11280 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11281 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11283 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11285 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11286 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11287 _("source1 and dest must be same register"));
11289 switch (inst
.instruction
)
11291 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11292 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11293 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11294 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11298 inst
.instruction
|= inst
.operands
[0].reg
;
11299 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11303 switch (inst
.instruction
)
11305 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11306 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11307 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11308 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11311 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11312 inst
.instruction
|= inst
.operands
[0].reg
;
11313 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11321 unsigned Rd
, Rn
, Rm
;
11323 Rd
= inst
.operands
[0].reg
;
11324 Rn
= inst
.operands
[1].reg
;
11325 Rm
= inst
.operands
[2].reg
;
11327 reject_bad_reg (Rd
);
11328 reject_bad_reg (Rn
);
11329 reject_bad_reg (Rm
);
11331 inst
.instruction
|= Rd
<< 8;
11332 inst
.instruction
|= Rn
<< 16;
11333 inst
.instruction
|= Rm
;
11339 unsigned Rd
, Rn
, Rm
;
11341 Rd
= inst
.operands
[0].reg
;
11342 Rm
= inst
.operands
[1].reg
;
11343 Rn
= inst
.operands
[2].reg
;
11345 reject_bad_reg (Rd
);
11346 reject_bad_reg (Rn
);
11347 reject_bad_reg (Rm
);
11349 inst
.instruction
|= Rd
<< 8;
11350 inst
.instruction
|= Rn
<< 16;
11351 inst
.instruction
|= Rm
;
11357 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11358 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11359 _("expression too complex"));
11360 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11361 inst
.instruction
|= (value
& 0xf000) >> 12;
11362 inst
.instruction
|= (value
& 0x0ff0);
11363 inst
.instruction
|= (value
& 0x000f) << 16;
11367 do_t_ssat_usat (int bias
)
11371 Rd
= inst
.operands
[0].reg
;
11372 Rn
= inst
.operands
[2].reg
;
11374 reject_bad_reg (Rd
);
11375 reject_bad_reg (Rn
);
11377 inst
.instruction
|= Rd
<< 8;
11378 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11379 inst
.instruction
|= Rn
<< 16;
11381 if (inst
.operands
[3].present
)
11383 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11385 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11387 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11388 _("expression too complex"));
11390 if (shift_amount
!= 0)
11392 constraint (shift_amount
> 31,
11393 _("shift expression is too large"));
11395 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11396 inst
.instruction
|= 0x00200000; /* sh bit. */
11398 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11399 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11407 do_t_ssat_usat (1);
11415 Rd
= inst
.operands
[0].reg
;
11416 Rn
= inst
.operands
[2].reg
;
11418 reject_bad_reg (Rd
);
11419 reject_bad_reg (Rn
);
11421 inst
.instruction
|= Rd
<< 8;
11422 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11423 inst
.instruction
|= Rn
<< 16;
11429 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11430 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11431 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11432 || inst
.operands
[2].negative
,
11435 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11437 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11438 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11439 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11440 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11446 if (!inst
.operands
[2].present
)
11447 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11449 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11450 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11451 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11454 inst
.instruction
|= inst
.operands
[0].reg
;
11455 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11456 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11457 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11463 unsigned Rd
, Rn
, Rm
;
11465 Rd
= inst
.operands
[0].reg
;
11466 Rn
= inst
.operands
[1].reg
;
11467 Rm
= inst
.operands
[2].reg
;
11469 reject_bad_reg (Rd
);
11470 reject_bad_reg (Rn
);
11471 reject_bad_reg (Rm
);
11473 inst
.instruction
|= Rd
<< 8;
11474 inst
.instruction
|= Rn
<< 16;
11475 inst
.instruction
|= Rm
;
11476 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11484 Rd
= inst
.operands
[0].reg
;
11485 Rm
= inst
.operands
[1].reg
;
11487 reject_bad_reg (Rd
);
11488 reject_bad_reg (Rm
);
11490 if (inst
.instruction
<= 0xffff
11491 && inst
.size_req
!= 4
11492 && Rd
<= 7 && Rm
<= 7
11493 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11495 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11496 inst
.instruction
|= Rd
;
11497 inst
.instruction
|= Rm
<< 3;
11499 else if (unified_syntax
)
11501 if (inst
.instruction
<= 0xffff)
11502 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11503 inst
.instruction
|= Rd
<< 8;
11504 inst
.instruction
|= Rm
;
11505 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11509 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11510 _("Thumb encoding does not support rotation"));
11511 constraint (1, BAD_HIREG
);
11518 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11527 half
= (inst
.instruction
& 0x10) != 0;
11528 set_it_insn_type_last ();
11529 constraint (inst
.operands
[0].immisreg
,
11530 _("instruction requires register index"));
11532 Rn
= inst
.operands
[0].reg
;
11533 Rm
= inst
.operands
[0].imm
;
11535 constraint (Rn
== REG_SP
, BAD_SP
);
11536 reject_bad_reg (Rm
);
11538 constraint (!half
&& inst
.operands
[0].shifted
,
11539 _("instruction does not allow shifted index"));
11540 inst
.instruction
|= (Rn
<< 16) | Rm
;
11546 do_t_ssat_usat (0);
11554 Rd
= inst
.operands
[0].reg
;
11555 Rn
= inst
.operands
[2].reg
;
11557 reject_bad_reg (Rd
);
11558 reject_bad_reg (Rn
);
11560 inst
.instruction
|= Rd
<< 8;
11561 inst
.instruction
|= inst
.operands
[1].imm
;
11562 inst
.instruction
|= Rn
<< 16;
11565 /* Neon instruction encoder helpers. */
11567 /* Encodings for the different types for various Neon opcodes. */
11569 /* An "invalid" code for the following tables. */
11572 struct neon_tab_entry
11575 unsigned float_or_poly
;
11576 unsigned scalar_or_imm
;
11579 /* Map overloaded Neon opcodes to their respective encodings. */
11580 #define NEON_ENC_TAB \
11581 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11582 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11583 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11584 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11585 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11586 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11587 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11588 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11589 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11590 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11591 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11592 /* Register variants of the following two instructions are encoded as
11593 vcge / vcgt with the operands reversed. */ \
11594 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11595 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11596 X(vfma, N_INV, 0x0000c10, N_INV), \
11597 X(vfms, N_INV, 0x0200c10, N_INV), \
11598 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11599 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11600 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11601 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11602 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11603 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11604 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11605 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11606 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11607 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11608 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11609 X(vshl, 0x0000400, N_INV, 0x0800510), \
11610 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11611 X(vand, 0x0000110, N_INV, 0x0800030), \
11612 X(vbic, 0x0100110, N_INV, 0x0800030), \
11613 X(veor, 0x1000110, N_INV, N_INV), \
11614 X(vorn, 0x0300110, N_INV, 0x0800010), \
11615 X(vorr, 0x0200110, N_INV, 0x0800010), \
11616 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11617 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11618 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11619 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11620 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11621 X(vst1, 0x0000000, 0x0800000, N_INV), \
11622 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11623 X(vst2, 0x0000100, 0x0800100, N_INV), \
11624 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11625 X(vst3, 0x0000200, 0x0800200, N_INV), \
11626 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11627 X(vst4, 0x0000300, 0x0800300, N_INV), \
11628 X(vmovn, 0x1b20200, N_INV, N_INV), \
11629 X(vtrn, 0x1b20080, N_INV, N_INV), \
11630 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11631 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11632 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11633 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11634 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11635 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11636 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11637 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11638 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11639 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11640 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11644 #define X(OPC,I,F,S) N_MNEM_##OPC
11649 static const struct neon_tab_entry neon_enc_tab
[] =
11651 #define X(OPC,I,F,S) { (I), (F), (S) }
11656 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11657 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11658 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11659 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11660 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11661 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11662 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11663 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11664 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11665 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11666 #define NEON_ENC_SINGLE_(X) \
11667 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11668 #define NEON_ENC_DOUBLE_(X) \
11669 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11671 #define NEON_ENCODE(type, inst) \
11674 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11675 inst.is_neon = 1; \
11679 #define check_neon_suffixes \
11682 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11684 as_bad (_("invalid neon suffix for non neon instruction")); \
11690 /* Define shapes for instruction operands. The following mnemonic characters
11691 are used in this table:
11693 F - VFP S<n> register
11694 D - Neon D<n> register
11695 Q - Neon Q<n> register
11699 L - D<n> register list
11701 This table is used to generate various data:
11702 - enumerations of the form NS_DDR to be used as arguments to
11704 - a table classifying shapes into single, double, quad, mixed.
11705 - a table used to drive neon_select_shape. */
11707 #define NEON_SHAPE_DEF \
11708 X(3, (D, D, D), DOUBLE), \
11709 X(3, (Q, Q, Q), QUAD), \
11710 X(3, (D, D, I), DOUBLE), \
11711 X(3, (Q, Q, I), QUAD), \
11712 X(3, (D, D, S), DOUBLE), \
11713 X(3, (Q, Q, S), QUAD), \
11714 X(2, (D, D), DOUBLE), \
11715 X(2, (Q, Q), QUAD), \
11716 X(2, (D, S), DOUBLE), \
11717 X(2, (Q, S), QUAD), \
11718 X(2, (D, R), DOUBLE), \
11719 X(2, (Q, R), QUAD), \
11720 X(2, (D, I), DOUBLE), \
11721 X(2, (Q, I), QUAD), \
11722 X(3, (D, L, D), DOUBLE), \
11723 X(2, (D, Q), MIXED), \
11724 X(2, (Q, D), MIXED), \
11725 X(3, (D, Q, I), MIXED), \
11726 X(3, (Q, D, I), MIXED), \
11727 X(3, (Q, D, D), MIXED), \
11728 X(3, (D, Q, Q), MIXED), \
11729 X(3, (Q, Q, D), MIXED), \
11730 X(3, (Q, D, S), MIXED), \
11731 X(3, (D, Q, S), MIXED), \
11732 X(4, (D, D, D, I), DOUBLE), \
11733 X(4, (Q, Q, Q, I), QUAD), \
11734 X(2, (F, F), SINGLE), \
11735 X(3, (F, F, F), SINGLE), \
11736 X(2, (F, I), SINGLE), \
11737 X(2, (F, D), MIXED), \
11738 X(2, (D, F), MIXED), \
11739 X(3, (F, F, I), MIXED), \
11740 X(4, (R, R, F, F), SINGLE), \
11741 X(4, (F, F, R, R), SINGLE), \
11742 X(3, (D, R, R), DOUBLE), \
11743 X(3, (R, R, D), DOUBLE), \
11744 X(2, (S, R), SINGLE), \
11745 X(2, (R, S), SINGLE), \
11746 X(2, (F, R), SINGLE), \
11747 X(2, (R, F), SINGLE)
11749 #define S2(A,B) NS_##A##B
11750 #define S3(A,B,C) NS_##A##B##C
11751 #define S4(A,B,C,D) NS_##A##B##C##D
11753 #define X(N, L, C) S##N L
11766 enum neon_shape_class
11774 #define X(N, L, C) SC_##C
11776 static enum neon_shape_class neon_shape_class
[] =
11794 /* Register widths of above. */
11795 static unsigned neon_shape_el_size
[] =
11806 struct neon_shape_info
11809 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11812 #define S2(A,B) { SE_##A, SE_##B }
11813 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11814 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11816 #define X(N, L, C) { N, S##N L }
11818 static struct neon_shape_info neon_shape_tab
[] =
11828 /* Bit masks used in type checking given instructions.
11829 'N_EQK' means the type must be the same as (or based on in some way) the key
11830 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11831 set, various other bits can be set as well in order to modify the meaning of
11832 the type constraint. */
11834 enum neon_type_mask
11857 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11858 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11859 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11860 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11861 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11862 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11863 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11864 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11865 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11866 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11868 N_MAX_NONSPECIAL
= N_F64
11871 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11873 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11874 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11875 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11876 #define N_SUF_32 (N_SU_32 | N_F32)
11877 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11878 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11880 /* Pass this as the first type argument to neon_check_type to ignore types
11882 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11884 /* Select a "shape" for the current instruction (describing register types or
11885 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11886 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11887 function of operand parsing, so this function doesn't need to be called.
11888 Shapes should be listed in order of decreasing length. */
11890 static enum neon_shape
11891 neon_select_shape (enum neon_shape shape
, ...)
11894 enum neon_shape first_shape
= shape
;
11896 /* Fix missing optional operands. FIXME: we don't know at this point how
11897 many arguments we should have, so this makes the assumption that we have
11898 > 1. This is true of all current Neon opcodes, I think, but may not be
11899 true in the future. */
11900 if (!inst
.operands
[1].present
)
11901 inst
.operands
[1] = inst
.operands
[0];
11903 va_start (ap
, shape
);
11905 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11910 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11912 if (!inst
.operands
[j
].present
)
11918 switch (neon_shape_tab
[shape
].el
[j
])
11921 if (!(inst
.operands
[j
].isreg
11922 && inst
.operands
[j
].isvec
11923 && inst
.operands
[j
].issingle
11924 && !inst
.operands
[j
].isquad
))
11929 if (!(inst
.operands
[j
].isreg
11930 && inst
.operands
[j
].isvec
11931 && !inst
.operands
[j
].isquad
11932 && !inst
.operands
[j
].issingle
))
11937 if (!(inst
.operands
[j
].isreg
11938 && !inst
.operands
[j
].isvec
))
11943 if (!(inst
.operands
[j
].isreg
11944 && inst
.operands
[j
].isvec
11945 && inst
.operands
[j
].isquad
11946 && !inst
.operands
[j
].issingle
))
11951 if (!(!inst
.operands
[j
].isreg
11952 && !inst
.operands
[j
].isscalar
))
11957 if (!(!inst
.operands
[j
].isreg
11958 && inst
.operands
[j
].isscalar
))
11974 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11975 first_error (_("invalid instruction shape"));
11980 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11981 means the Q bit should be set). */
11984 neon_quad (enum neon_shape shape
)
11986 return neon_shape_class
[shape
] == SC_QUAD
;
11990 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11993 /* Allow modification to be made to types which are constrained to be
11994 based on the key element, based on bits set alongside N_EQK. */
11995 if ((typebits
& N_EQK
) != 0)
11997 if ((typebits
& N_HLF
) != 0)
11999 else if ((typebits
& N_DBL
) != 0)
12001 if ((typebits
& N_SGN
) != 0)
12002 *g_type
= NT_signed
;
12003 else if ((typebits
& N_UNS
) != 0)
12004 *g_type
= NT_unsigned
;
12005 else if ((typebits
& N_INT
) != 0)
12006 *g_type
= NT_integer
;
12007 else if ((typebits
& N_FLT
) != 0)
12008 *g_type
= NT_float
;
12009 else if ((typebits
& N_SIZ
) != 0)
12010 *g_type
= NT_untyped
;
12014 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12015 operand type, i.e. the single type specified in a Neon instruction when it
12016 is the only one given. */
12018 static struct neon_type_el
12019 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12021 struct neon_type_el dest
= *key
;
12023 gas_assert ((thisarg
& N_EQK
) != 0);
12025 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12030 /* Convert Neon type and size into compact bitmask representation. */
12032 static enum neon_type_mask
12033 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12040 case 8: return N_8
;
12041 case 16: return N_16
;
12042 case 32: return N_32
;
12043 case 64: return N_64
;
12051 case 8: return N_I8
;
12052 case 16: return N_I16
;
12053 case 32: return N_I32
;
12054 case 64: return N_I64
;
12062 case 16: return N_F16
;
12063 case 32: return N_F32
;
12064 case 64: return N_F64
;
12072 case 8: return N_P8
;
12073 case 16: return N_P16
;
12081 case 8: return N_S8
;
12082 case 16: return N_S16
;
12083 case 32: return N_S32
;
12084 case 64: return N_S64
;
12092 case 8: return N_U8
;
12093 case 16: return N_U16
;
12094 case 32: return N_U32
;
12095 case 64: return N_U64
;
12106 /* Convert compact Neon bitmask type representation to a type and size. Only
12107 handles the case where a single bit is set in the mask. */
12110 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12111 enum neon_type_mask mask
)
12113 if ((mask
& N_EQK
) != 0)
12116 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12118 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12120 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12122 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12127 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12129 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12130 *type
= NT_unsigned
;
12131 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12132 *type
= NT_integer
;
12133 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12134 *type
= NT_untyped
;
12135 else if ((mask
& (N_P8
| N_P16
)) != 0)
12137 else if ((mask
& (N_F32
| N_F64
)) != 0)
12145 /* Modify a bitmask of allowed types. This is only needed for type
12149 modify_types_allowed (unsigned allowed
, unsigned mods
)
12152 enum neon_el_type type
;
12158 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12160 if (el_type_of_type_chk (&type
, &size
,
12161 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12163 neon_modify_type_size (mods
, &type
, &size
);
12164 destmask
|= type_chk_of_el_type (type
, size
);
12171 /* Check type and return type classification.
12172 The manual states (paraphrase): If one datatype is given, it indicates the
12174 - the second operand, if there is one
12175 - the operand, if there is no second operand
12176 - the result, if there are no operands.
12177 This isn't quite good enough though, so we use a concept of a "key" datatype
12178 which is set on a per-instruction basis, which is the one which matters when
12179 only one data type is written.
12180 Note: this function has side-effects (e.g. filling in missing operands). All
12181 Neon instructions should call it before performing bit encoding. */
12183 static struct neon_type_el
12184 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12187 unsigned i
, pass
, key_el
= 0;
12188 unsigned types
[NEON_MAX_TYPE_ELS
];
12189 enum neon_el_type k_type
= NT_invtype
;
12190 unsigned k_size
= -1u;
12191 struct neon_type_el badtype
= {NT_invtype
, -1};
12192 unsigned key_allowed
= 0;
12194 /* Optional registers in Neon instructions are always (not) in operand 1.
12195 Fill in the missing operand here, if it was omitted. */
12196 if (els
> 1 && !inst
.operands
[1].present
)
12197 inst
.operands
[1] = inst
.operands
[0];
12199 /* Suck up all the varargs. */
12201 for (i
= 0; i
< els
; i
++)
12203 unsigned thisarg
= va_arg (ap
, unsigned);
12204 if (thisarg
== N_IGNORE_TYPE
)
12209 types
[i
] = thisarg
;
12210 if ((thisarg
& N_KEY
) != 0)
12215 if (inst
.vectype
.elems
> 0)
12216 for (i
= 0; i
< els
; i
++)
12217 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12219 first_error (_("types specified in both the mnemonic and operands"));
12223 /* Duplicate inst.vectype elements here as necessary.
12224 FIXME: No idea if this is exactly the same as the ARM assembler,
12225 particularly when an insn takes one register and one non-register
12227 if (inst
.vectype
.elems
== 1 && els
> 1)
12230 inst
.vectype
.elems
= els
;
12231 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12232 for (j
= 0; j
< els
; j
++)
12234 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12237 else if (inst
.vectype
.elems
== 0 && els
> 0)
12240 /* No types were given after the mnemonic, so look for types specified
12241 after each operand. We allow some flexibility here; as long as the
12242 "key" operand has a type, we can infer the others. */
12243 for (j
= 0; j
< els
; j
++)
12244 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12245 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12247 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12249 for (j
= 0; j
< els
; j
++)
12250 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12251 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12256 first_error (_("operand types can't be inferred"));
12260 else if (inst
.vectype
.elems
!= els
)
12262 first_error (_("type specifier has the wrong number of parts"));
12266 for (pass
= 0; pass
< 2; pass
++)
12268 for (i
= 0; i
< els
; i
++)
12270 unsigned thisarg
= types
[i
];
12271 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12272 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12273 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12274 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12276 /* Decay more-specific signed & unsigned types to sign-insensitive
12277 integer types if sign-specific variants are unavailable. */
12278 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12279 && (types_allowed
& N_SU_ALL
) == 0)
12280 g_type
= NT_integer
;
12282 /* If only untyped args are allowed, decay any more specific types to
12283 them. Some instructions only care about signs for some element
12284 sizes, so handle that properly. */
12285 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12286 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12287 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12288 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12289 g_type
= NT_untyped
;
12293 if ((thisarg
& N_KEY
) != 0)
12297 key_allowed
= thisarg
& ~N_KEY
;
12302 if ((thisarg
& N_VFP
) != 0)
12304 enum neon_shape_el regshape
;
12305 unsigned regwidth
, match
;
12307 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12310 first_error (_("invalid instruction shape"));
12313 regshape
= neon_shape_tab
[ns
].el
[i
];
12314 regwidth
= neon_shape_el_size
[regshape
];
12316 /* In VFP mode, operands must match register widths. If we
12317 have a key operand, use its width, else use the width of
12318 the current operand. */
12324 if (regwidth
!= match
)
12326 first_error (_("operand size must match register width"));
12331 if ((thisarg
& N_EQK
) == 0)
12333 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12335 if ((given_type
& types_allowed
) == 0)
12337 first_error (_("bad type in Neon instruction"));
12343 enum neon_el_type mod_k_type
= k_type
;
12344 unsigned mod_k_size
= k_size
;
12345 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12346 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12348 first_error (_("inconsistent types in Neon instruction"));
12356 return inst
.vectype
.el
[key_el
];
12359 /* Neon-style VFP instruction forwarding. */
12361 /* Thumb VFP instructions have 0xE in the condition field. */
12364 do_vfp_cond_or_thumb (void)
12369 inst
.instruction
|= 0xe0000000;
12371 inst
.instruction
|= inst
.cond
<< 28;
12374 /* Look up and encode a simple mnemonic, for use as a helper function for the
12375 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12376 etc. It is assumed that operand parsing has already been done, and that the
12377 operands are in the form expected by the given opcode (this isn't necessarily
12378 the same as the form in which they were parsed, hence some massaging must
12379 take place before this function is called).
12380 Checks current arch version against that in the looked-up opcode. */
12383 do_vfp_nsyn_opcode (const char *opname
)
12385 const struct asm_opcode
*opcode
;
12387 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12392 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12393 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12400 inst
.instruction
= opcode
->tvalue
;
12401 opcode
->tencode ();
12405 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12406 opcode
->aencode ();
12411 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12413 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12418 do_vfp_nsyn_opcode ("fadds");
12420 do_vfp_nsyn_opcode ("fsubs");
12425 do_vfp_nsyn_opcode ("faddd");
12427 do_vfp_nsyn_opcode ("fsubd");
12431 /* Check operand types to see if this is a VFP instruction, and if so call
12435 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12437 enum neon_shape rs
;
12438 struct neon_type_el et
;
12443 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12444 et
= neon_check_type (2, rs
,
12445 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12449 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12450 et
= neon_check_type (3, rs
,
12451 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12458 if (et
.type
!= NT_invtype
)
12469 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12471 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12476 do_vfp_nsyn_opcode ("fmacs");
12478 do_vfp_nsyn_opcode ("fnmacs");
12483 do_vfp_nsyn_opcode ("fmacd");
12485 do_vfp_nsyn_opcode ("fnmacd");
12490 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12492 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12497 do_vfp_nsyn_opcode ("ffmas");
12499 do_vfp_nsyn_opcode ("ffnmas");
12504 do_vfp_nsyn_opcode ("ffmad");
12506 do_vfp_nsyn_opcode ("ffnmad");
12511 do_vfp_nsyn_mul (enum neon_shape rs
)
12514 do_vfp_nsyn_opcode ("fmuls");
12516 do_vfp_nsyn_opcode ("fmuld");
12520 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12522 int is_neg
= (inst
.instruction
& 0x80) != 0;
12523 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12528 do_vfp_nsyn_opcode ("fnegs");
12530 do_vfp_nsyn_opcode ("fabss");
12535 do_vfp_nsyn_opcode ("fnegd");
12537 do_vfp_nsyn_opcode ("fabsd");
12541 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12542 insns belong to Neon, and are handled elsewhere. */
12545 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12547 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12551 do_vfp_nsyn_opcode ("fldmdbs");
12553 do_vfp_nsyn_opcode ("fldmias");
12558 do_vfp_nsyn_opcode ("fstmdbs");
12560 do_vfp_nsyn_opcode ("fstmias");
12565 do_vfp_nsyn_sqrt (void)
12567 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12568 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12571 do_vfp_nsyn_opcode ("fsqrts");
12573 do_vfp_nsyn_opcode ("fsqrtd");
12577 do_vfp_nsyn_div (void)
12579 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12580 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12581 N_F32
| N_F64
| N_KEY
| N_VFP
);
12584 do_vfp_nsyn_opcode ("fdivs");
12586 do_vfp_nsyn_opcode ("fdivd");
12590 do_vfp_nsyn_nmul (void)
12592 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12593 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12594 N_F32
| N_F64
| N_KEY
| N_VFP
);
12598 NEON_ENCODE (SINGLE
, inst
);
12599 do_vfp_sp_dyadic ();
12603 NEON_ENCODE (DOUBLE
, inst
);
12604 do_vfp_dp_rd_rn_rm ();
12606 do_vfp_cond_or_thumb ();
12610 do_vfp_nsyn_cmp (void)
12612 if (inst
.operands
[1].isreg
)
12614 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12615 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12619 NEON_ENCODE (SINGLE
, inst
);
12620 do_vfp_sp_monadic ();
12624 NEON_ENCODE (DOUBLE
, inst
);
12625 do_vfp_dp_rd_rm ();
12630 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12631 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12633 switch (inst
.instruction
& 0x0fffffff)
12636 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12639 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12647 NEON_ENCODE (SINGLE
, inst
);
12648 do_vfp_sp_compare_z ();
12652 NEON_ENCODE (DOUBLE
, inst
);
12656 do_vfp_cond_or_thumb ();
12660 nsyn_insert_sp (void)
12662 inst
.operands
[1] = inst
.operands
[0];
12663 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12664 inst
.operands
[0].reg
= REG_SP
;
12665 inst
.operands
[0].isreg
= 1;
12666 inst
.operands
[0].writeback
= 1;
12667 inst
.operands
[0].present
= 1;
12671 do_vfp_nsyn_push (void)
12674 if (inst
.operands
[1].issingle
)
12675 do_vfp_nsyn_opcode ("fstmdbs");
12677 do_vfp_nsyn_opcode ("fstmdbd");
12681 do_vfp_nsyn_pop (void)
12684 if (inst
.operands
[1].issingle
)
12685 do_vfp_nsyn_opcode ("fldmias");
12687 do_vfp_nsyn_opcode ("fldmiad");
12690 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12691 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12694 neon_dp_fixup (struct arm_it
* insn
)
12696 unsigned int i
= insn
->instruction
;
12701 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12712 insn
->instruction
= i
;
12715 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12719 neon_logbits (unsigned x
)
12721 return ffs (x
) - 4;
12724 #define LOW4(R) ((R) & 0xf)
12725 #define HI1(R) (((R) >> 4) & 1)
12727 /* Encode insns with bit pattern:
12729 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12730 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12732 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12733 different meaning for some instruction. */
12736 neon_three_same (int isquad
, int ubit
, int size
)
12738 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12739 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12740 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12741 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12742 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12743 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12744 inst
.instruction
|= (isquad
!= 0) << 6;
12745 inst
.instruction
|= (ubit
!= 0) << 24;
12747 inst
.instruction
|= neon_logbits (size
) << 20;
12749 neon_dp_fixup (&inst
);
12752 /* Encode instructions of the form:
12754 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12755 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12757 Don't write size if SIZE == -1. */
12760 neon_two_same (int qbit
, int ubit
, int size
)
12762 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12763 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12764 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12765 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12766 inst
.instruction
|= (qbit
!= 0) << 6;
12767 inst
.instruction
|= (ubit
!= 0) << 24;
12770 inst
.instruction
|= neon_logbits (size
) << 18;
12772 neon_dp_fixup (&inst
);
12775 /* Neon instruction encoders, in approximate order of appearance. */
12778 do_neon_dyadic_i_su (void)
12780 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12781 struct neon_type_el et
= neon_check_type (3, rs
,
12782 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12783 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12787 do_neon_dyadic_i64_su (void)
12789 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12790 struct neon_type_el et
= neon_check_type (3, rs
,
12791 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12792 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12796 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12799 unsigned size
= et
.size
>> 3;
12800 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12801 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12802 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12803 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12804 inst
.instruction
|= (isquad
!= 0) << 6;
12805 inst
.instruction
|= immbits
<< 16;
12806 inst
.instruction
|= (size
>> 3) << 7;
12807 inst
.instruction
|= (size
& 0x7) << 19;
12809 inst
.instruction
|= (uval
!= 0) << 24;
12811 neon_dp_fixup (&inst
);
12815 do_neon_shl_imm (void)
12817 if (!inst
.operands
[2].isreg
)
12819 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12820 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12821 NEON_ENCODE (IMMED
, inst
);
12822 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12826 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12827 struct neon_type_el et
= neon_check_type (3, rs
,
12828 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12831 /* VSHL/VQSHL 3-register variants have syntax such as:
12833 whereas other 3-register operations encoded by neon_three_same have
12836 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12838 tmp
= inst
.operands
[2].reg
;
12839 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12840 inst
.operands
[1].reg
= tmp
;
12841 NEON_ENCODE (INTEGER
, inst
);
12842 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12847 do_neon_qshl_imm (void)
12849 if (!inst
.operands
[2].isreg
)
12851 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12852 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12854 NEON_ENCODE (IMMED
, inst
);
12855 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12856 inst
.operands
[2].imm
);
12860 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12861 struct neon_type_el et
= neon_check_type (3, rs
,
12862 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12865 /* See note in do_neon_shl_imm. */
12866 tmp
= inst
.operands
[2].reg
;
12867 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12868 inst
.operands
[1].reg
= tmp
;
12869 NEON_ENCODE (INTEGER
, inst
);
12870 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12875 do_neon_rshl (void)
12877 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12878 struct neon_type_el et
= neon_check_type (3, rs
,
12879 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12882 tmp
= inst
.operands
[2].reg
;
12883 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12884 inst
.operands
[1].reg
= tmp
;
12885 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12889 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12891 /* Handle .I8 pseudo-instructions. */
12894 /* Unfortunately, this will make everything apart from zero out-of-range.
12895 FIXME is this the intended semantics? There doesn't seem much point in
12896 accepting .I8 if so. */
12897 immediate
|= immediate
<< 8;
12903 if (immediate
== (immediate
& 0x000000ff))
12905 *immbits
= immediate
;
12908 else if (immediate
== (immediate
& 0x0000ff00))
12910 *immbits
= immediate
>> 8;
12913 else if (immediate
== (immediate
& 0x00ff0000))
12915 *immbits
= immediate
>> 16;
12918 else if (immediate
== (immediate
& 0xff000000))
12920 *immbits
= immediate
>> 24;
12923 if ((immediate
& 0xffff) != (immediate
>> 16))
12924 goto bad_immediate
;
12925 immediate
&= 0xffff;
12928 if (immediate
== (immediate
& 0x000000ff))
12930 *immbits
= immediate
;
12933 else if (immediate
== (immediate
& 0x0000ff00))
12935 *immbits
= immediate
>> 8;
12940 first_error (_("immediate value out of range"));
12944 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12948 neon_bits_same_in_bytes (unsigned imm
)
12950 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12951 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12952 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12953 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12956 /* For immediate of above form, return 0bABCD. */
12959 neon_squash_bits (unsigned imm
)
12961 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12962 | ((imm
& 0x01000000) >> 21);
12965 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12968 neon_qfloat_bits (unsigned imm
)
12970 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12973 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12974 the instruction. *OP is passed as the initial value of the op field, and
12975 may be set to a different value depending on the constant (i.e.
12976 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12977 MVN). If the immediate looks like a repeated pattern then also
12978 try smaller element sizes. */
12981 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12982 unsigned *immbits
, int *op
, int size
,
12983 enum neon_el_type type
)
12985 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12987 if (type
== NT_float
&& !float_p
)
12990 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12992 if (size
!= 32 || *op
== 1)
12994 *immbits
= neon_qfloat_bits (immlo
);
13000 if (neon_bits_same_in_bytes (immhi
)
13001 && neon_bits_same_in_bytes (immlo
))
13005 *immbits
= (neon_squash_bits (immhi
) << 4)
13006 | neon_squash_bits (immlo
);
13011 if (immhi
!= immlo
)
13017 if (immlo
== (immlo
& 0x000000ff))
13022 else if (immlo
== (immlo
& 0x0000ff00))
13024 *immbits
= immlo
>> 8;
13027 else if (immlo
== (immlo
& 0x00ff0000))
13029 *immbits
= immlo
>> 16;
13032 else if (immlo
== (immlo
& 0xff000000))
13034 *immbits
= immlo
>> 24;
13037 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13039 *immbits
= (immlo
>> 8) & 0xff;
13042 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13044 *immbits
= (immlo
>> 16) & 0xff;
13048 if ((immlo
& 0xffff) != (immlo
>> 16))
13055 if (immlo
== (immlo
& 0x000000ff))
13060 else if (immlo
== (immlo
& 0x0000ff00))
13062 *immbits
= immlo
>> 8;
13066 if ((immlo
& 0xff) != (immlo
>> 8))
13071 if (immlo
== (immlo
& 0x000000ff))
13073 /* Don't allow MVN with 8-bit immediate. */
13083 /* Write immediate bits [7:0] to the following locations:
13085 |28/24|23 19|18 16|15 4|3 0|
13086 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13088 This function is used by VMOV/VMVN/VORR/VBIC. */
13091 neon_write_immbits (unsigned immbits
)
13093 inst
.instruction
|= immbits
& 0xf;
13094 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13095 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13098 /* Invert low-order SIZE bits of XHI:XLO. */
13101 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13103 unsigned immlo
= xlo
? *xlo
: 0;
13104 unsigned immhi
= xhi
? *xhi
: 0;
13109 immlo
= (~immlo
) & 0xff;
13113 immlo
= (~immlo
) & 0xffff;
13117 immhi
= (~immhi
) & 0xffffffff;
13118 /* fall through. */
13121 immlo
= (~immlo
) & 0xffffffff;
13136 do_neon_logic (void)
13138 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13140 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13141 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13142 /* U bit and size field were set as part of the bitmask. */
13143 NEON_ENCODE (INTEGER
, inst
);
13144 neon_three_same (neon_quad (rs
), 0, -1);
13148 const int three_ops_form
= (inst
.operands
[2].present
13149 && !inst
.operands
[2].isreg
);
13150 const int immoperand
= (three_ops_form
? 2 : 1);
13151 enum neon_shape rs
= (three_ops_form
13152 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13153 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13154 struct neon_type_el et
= neon_check_type (2, rs
,
13155 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13156 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13160 if (et
.type
== NT_invtype
)
13163 if (three_ops_form
)
13164 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13165 _("first and second operands shall be the same register"));
13167 NEON_ENCODE (IMMED
, inst
);
13169 immbits
= inst
.operands
[immoperand
].imm
;
13172 /* .i64 is a pseudo-op, so the immediate must be a repeating
13174 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13175 inst
.operands
[immoperand
].reg
: 0))
13177 /* Set immbits to an invalid constant. */
13178 immbits
= 0xdeadbeef;
13185 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13189 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13193 /* Pseudo-instruction for VBIC. */
13194 neon_invert_size (&immbits
, 0, et
.size
);
13195 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13199 /* Pseudo-instruction for VORR. */
13200 neon_invert_size (&immbits
, 0, et
.size
);
13201 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13211 inst
.instruction
|= neon_quad (rs
) << 6;
13212 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13213 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13214 inst
.instruction
|= cmode
<< 8;
13215 neon_write_immbits (immbits
);
13217 neon_dp_fixup (&inst
);
13222 do_neon_bitfield (void)
13224 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13225 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13226 neon_three_same (neon_quad (rs
), 0, -1);
13230 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13233 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13234 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13236 if (et
.type
== NT_float
)
13238 NEON_ENCODE (FLOAT
, inst
);
13239 neon_three_same (neon_quad (rs
), 0, -1);
13243 NEON_ENCODE (INTEGER
, inst
);
13244 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13249 do_neon_dyadic_if_su (void)
13251 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13255 do_neon_dyadic_if_su_d (void)
13257 /* This version only allow D registers, but that constraint is enforced during
13258 operand parsing so we don't need to do anything extra here. */
13259 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13263 do_neon_dyadic_if_i_d (void)
13265 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13266 affected if we specify unsigned args. */
13267 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13270 enum vfp_or_neon_is_neon_bits
13273 NEON_CHECK_ARCH
= 2
13276 /* Call this function if an instruction which may have belonged to the VFP or
13277 Neon instruction sets, but turned out to be a Neon instruction (due to the
13278 operand types involved, etc.). We have to check and/or fix-up a couple of
13281 - Make sure the user hasn't attempted to make a Neon instruction
13283 - Alter the value in the condition code field if necessary.
13284 - Make sure that the arch supports Neon instructions.
13286 Which of these operations take place depends on bits from enum
13287 vfp_or_neon_is_neon_bits.
13289 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13290 current instruction's condition is COND_ALWAYS, the condition field is
13291 changed to inst.uncond_value. This is necessary because instructions shared
13292 between VFP and Neon may be conditional for the VFP variants only, and the
13293 unconditional Neon version must have, e.g., 0xF in the condition field. */
13296 vfp_or_neon_is_neon (unsigned check
)
13298 /* Conditions are always legal in Thumb mode (IT blocks). */
13299 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13301 if (inst
.cond
!= COND_ALWAYS
)
13303 first_error (_(BAD_COND
));
13306 if (inst
.uncond_value
!= -1)
13307 inst
.instruction
|= inst
.uncond_value
<< 28;
13310 if ((check
& NEON_CHECK_ARCH
)
13311 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13313 first_error (_(BAD_FPU
));
13321 do_neon_addsub_if_i (void)
13323 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13326 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13329 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13330 affected if we specify unsigned args. */
13331 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13334 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13336 V<op> A,B (A is operand 0, B is operand 2)
13341 so handle that case specially. */
13344 neon_exchange_operands (void)
13346 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13347 if (inst
.operands
[1].present
)
13349 /* Swap operands[1] and operands[2]. */
13350 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13351 inst
.operands
[1] = inst
.operands
[2];
13352 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13356 inst
.operands
[1] = inst
.operands
[2];
13357 inst
.operands
[2] = inst
.operands
[0];
13362 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13364 if (inst
.operands
[2].isreg
)
13367 neon_exchange_operands ();
13368 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13372 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13373 struct neon_type_el et
= neon_check_type (2, rs
,
13374 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13376 NEON_ENCODE (IMMED
, inst
);
13377 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13378 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13379 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13380 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13381 inst
.instruction
|= neon_quad (rs
) << 6;
13382 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13383 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13385 neon_dp_fixup (&inst
);
13392 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13396 do_neon_cmp_inv (void)
13398 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13404 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13407 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13408 scalars, which are encoded in 5 bits, M : Rm.
13409 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13410 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13414 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13416 unsigned regno
= NEON_SCALAR_REG (scalar
);
13417 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13422 if (regno
> 7 || elno
> 3)
13424 return regno
| (elno
<< 3);
13427 if (regno
> 15 || elno
> 1)
13429 return regno
| (elno
<< 4);
13433 first_error (_("scalar out of range for multiply instruction"));
13439 /* Encode multiply / multiply-accumulate scalar instructions. */
13442 neon_mul_mac (struct neon_type_el et
, int ubit
)
13446 /* Give a more helpful error message if we have an invalid type. */
13447 if (et
.type
== NT_invtype
)
13450 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13451 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13452 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13453 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13454 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13455 inst
.instruction
|= LOW4 (scalar
);
13456 inst
.instruction
|= HI1 (scalar
) << 5;
13457 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13458 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13459 inst
.instruction
|= (ubit
!= 0) << 24;
13461 neon_dp_fixup (&inst
);
13465 do_neon_mac_maybe_scalar (void)
13467 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13470 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13473 if (inst
.operands
[2].isscalar
)
13475 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13476 struct neon_type_el et
= neon_check_type (3, rs
,
13477 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13478 NEON_ENCODE (SCALAR
, inst
);
13479 neon_mul_mac (et
, neon_quad (rs
));
13483 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13484 affected if we specify unsigned args. */
13485 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13490 do_neon_fmac (void)
13492 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13495 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13498 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13504 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13505 struct neon_type_el et
= neon_check_type (3, rs
,
13506 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13507 neon_three_same (neon_quad (rs
), 0, et
.size
);
13510 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13511 same types as the MAC equivalents. The polynomial type for this instruction
13512 is encoded the same as the integer type. */
13517 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13520 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13523 if (inst
.operands
[2].isscalar
)
13524 do_neon_mac_maybe_scalar ();
13526 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13530 do_neon_qdmulh (void)
13532 if (inst
.operands
[2].isscalar
)
13534 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13535 struct neon_type_el et
= neon_check_type (3, rs
,
13536 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13537 NEON_ENCODE (SCALAR
, inst
);
13538 neon_mul_mac (et
, neon_quad (rs
));
13542 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13543 struct neon_type_el et
= neon_check_type (3, rs
,
13544 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13545 NEON_ENCODE (INTEGER
, inst
);
13546 /* The U bit (rounding) comes from bit mask. */
13547 neon_three_same (neon_quad (rs
), 0, et
.size
);
13552 do_neon_fcmp_absolute (void)
13554 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13555 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13556 /* Size field comes from bit mask. */
13557 neon_three_same (neon_quad (rs
), 1, -1);
13561 do_neon_fcmp_absolute_inv (void)
13563 neon_exchange_operands ();
13564 do_neon_fcmp_absolute ();
13568 do_neon_step (void)
13570 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13571 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13572 neon_three_same (neon_quad (rs
), 0, -1);
13576 do_neon_abs_neg (void)
13578 enum neon_shape rs
;
13579 struct neon_type_el et
;
13581 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13584 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13587 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13588 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13590 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13591 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13592 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13593 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13594 inst
.instruction
|= neon_quad (rs
) << 6;
13595 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13596 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13598 neon_dp_fixup (&inst
);
13604 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13605 struct neon_type_el et
= neon_check_type (2, rs
,
13606 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13607 int imm
= inst
.operands
[2].imm
;
13608 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13609 _("immediate out of range for insert"));
13610 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13616 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13617 struct neon_type_el et
= neon_check_type (2, rs
,
13618 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13619 int imm
= inst
.operands
[2].imm
;
13620 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13621 _("immediate out of range for insert"));
13622 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13626 do_neon_qshlu_imm (void)
13628 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13629 struct neon_type_el et
= neon_check_type (2, rs
,
13630 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13631 int imm
= inst
.operands
[2].imm
;
13632 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13633 _("immediate out of range for shift"));
13634 /* Only encodes the 'U present' variant of the instruction.
13635 In this case, signed types have OP (bit 8) set to 0.
13636 Unsigned types have OP set to 1. */
13637 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13638 /* The rest of the bits are the same as other immediate shifts. */
13639 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13643 do_neon_qmovn (void)
13645 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13646 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13647 /* Saturating move where operands can be signed or unsigned, and the
13648 destination has the same signedness. */
13649 NEON_ENCODE (INTEGER
, inst
);
13650 if (et
.type
== NT_unsigned
)
13651 inst
.instruction
|= 0xc0;
13653 inst
.instruction
|= 0x80;
13654 neon_two_same (0, 1, et
.size
/ 2);
13658 do_neon_qmovun (void)
13660 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13661 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13662 /* Saturating move with unsigned results. Operands must be signed. */
13663 NEON_ENCODE (INTEGER
, inst
);
13664 neon_two_same (0, 1, et
.size
/ 2);
13668 do_neon_rshift_sat_narrow (void)
13670 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13671 or unsigned. If operands are unsigned, results must also be unsigned. */
13672 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13673 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13674 int imm
= inst
.operands
[2].imm
;
13675 /* This gets the bounds check, size encoding and immediate bits calculation
13679 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13680 VQMOVN.I<size> <Dd>, <Qm>. */
13683 inst
.operands
[2].present
= 0;
13684 inst
.instruction
= N_MNEM_vqmovn
;
13689 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13690 _("immediate out of range"));
13691 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13695 do_neon_rshift_sat_narrow_u (void)
13697 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13698 or unsigned. If operands are unsigned, results must also be unsigned. */
13699 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13700 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13701 int imm
= inst
.operands
[2].imm
;
13702 /* This gets the bounds check, size encoding and immediate bits calculation
13706 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13707 VQMOVUN.I<size> <Dd>, <Qm>. */
13710 inst
.operands
[2].present
= 0;
13711 inst
.instruction
= N_MNEM_vqmovun
;
13716 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13717 _("immediate out of range"));
13718 /* FIXME: The manual is kind of unclear about what value U should have in
13719 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13721 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13725 do_neon_movn (void)
13727 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13728 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13729 NEON_ENCODE (INTEGER
, inst
);
13730 neon_two_same (0, 1, et
.size
/ 2);
13734 do_neon_rshift_narrow (void)
13736 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13737 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13738 int imm
= inst
.operands
[2].imm
;
13739 /* This gets the bounds check, size encoding and immediate bits calculation
13743 /* If immediate is zero then we are a pseudo-instruction for
13744 VMOVN.I<size> <Dd>, <Qm> */
13747 inst
.operands
[2].present
= 0;
13748 inst
.instruction
= N_MNEM_vmovn
;
13753 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13754 _("immediate out of range for narrowing operation"));
13755 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13759 do_neon_shll (void)
13761 /* FIXME: Type checking when lengthening. */
13762 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13763 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13764 unsigned imm
= inst
.operands
[2].imm
;
13766 if (imm
== et
.size
)
13768 /* Maximum shift variant. */
13769 NEON_ENCODE (INTEGER
, inst
);
13770 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13771 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13772 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13773 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13774 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13776 neon_dp_fixup (&inst
);
13780 /* A more-specific type check for non-max versions. */
13781 et
= neon_check_type (2, NS_QDI
,
13782 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13783 NEON_ENCODE (IMMED
, inst
);
13784 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13788 /* Check the various types for the VCVT instruction, and return which version
13789 the current instruction is. */
13792 neon_cvt_flavour (enum neon_shape rs
)
13794 #define CVT_VAR(C,X,Y) \
13795 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13796 if (et.type != NT_invtype) \
13798 inst.error = NULL; \
13801 struct neon_type_el et
;
13802 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13803 || rs
== NS_FF
) ? N_VFP
: 0;
13804 /* The instruction versions which take an immediate take one register
13805 argument, which is extended to the width of the full register. Thus the
13806 "source" and "destination" registers must have the same width. Hack that
13807 here by making the size equal to the key (wider, in this case) operand. */
13808 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13810 CVT_VAR (0, N_S32
, N_F32
);
13811 CVT_VAR (1, N_U32
, N_F32
);
13812 CVT_VAR (2, N_F32
, N_S32
);
13813 CVT_VAR (3, N_F32
, N_U32
);
13814 /* Half-precision conversions. */
13815 CVT_VAR (4, N_F32
, N_F16
);
13816 CVT_VAR (5, N_F16
, N_F32
);
13820 /* VFP instructions. */
13821 CVT_VAR (6, N_F32
, N_F64
);
13822 CVT_VAR (7, N_F64
, N_F32
);
13823 CVT_VAR (8, N_S32
, N_F64
| key
);
13824 CVT_VAR (9, N_U32
, N_F64
| key
);
13825 CVT_VAR (10, N_F64
| key
, N_S32
);
13826 CVT_VAR (11, N_F64
| key
, N_U32
);
13827 /* VFP instructions with bitshift. */
13828 CVT_VAR (12, N_F32
| key
, N_S16
);
13829 CVT_VAR (13, N_F32
| key
, N_U16
);
13830 CVT_VAR (14, N_F64
| key
, N_S16
);
13831 CVT_VAR (15, N_F64
| key
, N_U16
);
13832 CVT_VAR (16, N_S16
, N_F32
| key
);
13833 CVT_VAR (17, N_U16
, N_F32
| key
);
13834 CVT_VAR (18, N_S16
, N_F64
| key
);
13835 CVT_VAR (19, N_U16
, N_F64
| key
);
13841 /* Neon-syntax VFP conversions. */
13844 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13846 const char *opname
= 0;
13848 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13850 /* Conversions with immediate bitshift. */
13851 const char *enc
[] =
13875 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13877 opname
= enc
[flavour
];
13878 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13879 _("operands 0 and 1 must be the same register"));
13880 inst
.operands
[1] = inst
.operands
[2];
13881 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13886 /* Conversions without bitshift. */
13887 const char *enc
[] =
13903 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13904 opname
= enc
[flavour
];
13908 do_vfp_nsyn_opcode (opname
);
13912 do_vfp_nsyn_cvtz (void)
13914 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13915 int flavour
= neon_cvt_flavour (rs
);
13916 const char *enc
[] =
13930 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13931 do_vfp_nsyn_opcode (enc
[flavour
]);
13935 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
13937 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13938 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13939 int flavour
= neon_cvt_flavour (rs
);
13941 /* PR11109: Handle round-to-zero for VCVT conversions. */
13943 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
13944 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
13945 && (rs
== NS_FD
|| rs
== NS_FF
))
13947 do_vfp_nsyn_cvtz ();
13951 /* VFP rather than Neon conversions. */
13954 do_vfp_nsyn_cvt (rs
, flavour
);
13964 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13966 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13969 /* Fixed-point conversion with #0 immediate is encoded as an
13970 integer conversion. */
13971 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13973 immbits
= 32 - inst
.operands
[2].imm
;
13974 NEON_ENCODE (IMMED
, inst
);
13976 inst
.instruction
|= enctab
[flavour
];
13977 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13978 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13979 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13980 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13981 inst
.instruction
|= neon_quad (rs
) << 6;
13982 inst
.instruction
|= 1 << 21;
13983 inst
.instruction
|= immbits
<< 16;
13985 neon_dp_fixup (&inst
);
13993 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13995 NEON_ENCODE (INTEGER
, inst
);
13997 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14001 inst
.instruction
|= enctab
[flavour
];
14003 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14004 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14005 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14006 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14007 inst
.instruction
|= neon_quad (rs
) << 6;
14008 inst
.instruction
|= 2 << 18;
14010 neon_dp_fixup (&inst
);
14014 /* Half-precision conversions for Advanced SIMD -- neon. */
14019 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14021 as_bad (_("operand size must match register width"));
14026 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14028 as_bad (_("operand size must match register width"));
14033 inst
.instruction
= 0x3b60600;
14035 inst
.instruction
= 0x3b60700;
14037 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14038 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14039 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14040 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14041 neon_dp_fixup (&inst
);
14045 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14046 do_vfp_nsyn_cvt (rs
, flavour
);
14051 do_neon_cvtr (void)
14053 do_neon_cvt_1 (FALSE
);
14059 do_neon_cvt_1 (TRUE
);
14063 do_neon_cvtb (void)
14065 inst
.instruction
= 0xeb20a40;
14067 /* The sizes are attached to the mnemonic. */
14068 if (inst
.vectype
.el
[0].type
!= NT_invtype
14069 && inst
.vectype
.el
[0].size
== 16)
14070 inst
.instruction
|= 0x00010000;
14072 /* Programmer's syntax: the sizes are attached to the operands. */
14073 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14074 && inst
.operands
[0].vectype
.size
== 16)
14075 inst
.instruction
|= 0x00010000;
14077 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14078 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14079 do_vfp_cond_or_thumb ();
14084 do_neon_cvtt (void)
14087 inst
.instruction
|= 0x80;
14091 neon_move_immediate (void)
14093 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14094 struct neon_type_el et
= neon_check_type (2, rs
,
14095 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14096 unsigned immlo
, immhi
= 0, immbits
;
14097 int op
, cmode
, float_p
;
14099 constraint (et
.type
== NT_invtype
,
14100 _("operand size must be specified for immediate VMOV"));
14102 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14103 op
= (inst
.instruction
& (1 << 5)) != 0;
14105 immlo
= inst
.operands
[1].imm
;
14106 if (inst
.operands
[1].regisimm
)
14107 immhi
= inst
.operands
[1].reg
;
14109 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14110 _("immediate has bits set outside the operand size"));
14112 float_p
= inst
.operands
[1].immisfloat
;
14114 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14115 et
.size
, et
.type
)) == FAIL
)
14117 /* Invert relevant bits only. */
14118 neon_invert_size (&immlo
, &immhi
, et
.size
);
14119 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14120 with one or the other; those cases are caught by
14121 neon_cmode_for_move_imm. */
14123 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14124 &op
, et
.size
, et
.type
)) == FAIL
)
14126 first_error (_("immediate out of range"));
14131 inst
.instruction
&= ~(1 << 5);
14132 inst
.instruction
|= op
<< 5;
14134 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14135 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14136 inst
.instruction
|= neon_quad (rs
) << 6;
14137 inst
.instruction
|= cmode
<< 8;
14139 neon_write_immbits (immbits
);
14145 if (inst
.operands
[1].isreg
)
14147 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14149 NEON_ENCODE (INTEGER
, inst
);
14150 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14151 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14152 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14153 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14154 inst
.instruction
|= neon_quad (rs
) << 6;
14158 NEON_ENCODE (IMMED
, inst
);
14159 neon_move_immediate ();
14162 neon_dp_fixup (&inst
);
14165 /* Encode instructions of form:
14167 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14168 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14171 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14173 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14174 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14175 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14176 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14177 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14178 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14179 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14180 inst
.instruction
|= neon_logbits (size
) << 20;
14182 neon_dp_fixup (&inst
);
14186 do_neon_dyadic_long (void)
14188 /* FIXME: Type checking for lengthening op. */
14189 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14190 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14191 neon_mixed_length (et
, et
.size
);
14195 do_neon_abal (void)
14197 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14198 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14199 neon_mixed_length (et
, et
.size
);
14203 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14205 if (inst
.operands
[2].isscalar
)
14207 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14208 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14209 NEON_ENCODE (SCALAR
, inst
);
14210 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14214 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14215 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14216 NEON_ENCODE (INTEGER
, inst
);
14217 neon_mixed_length (et
, et
.size
);
14222 do_neon_mac_maybe_scalar_long (void)
14224 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14228 do_neon_dyadic_wide (void)
14230 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14231 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14232 neon_mixed_length (et
, et
.size
);
14236 do_neon_dyadic_narrow (void)
14238 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14239 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14240 /* Operand sign is unimportant, and the U bit is part of the opcode,
14241 so force the operand type to integer. */
14242 et
.type
= NT_integer
;
14243 neon_mixed_length (et
, et
.size
/ 2);
14247 do_neon_mul_sat_scalar_long (void)
14249 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14253 do_neon_vmull (void)
14255 if (inst
.operands
[2].isscalar
)
14256 do_neon_mac_maybe_scalar_long ();
14259 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14260 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14261 if (et
.type
== NT_poly
)
14262 NEON_ENCODE (POLY
, inst
);
14264 NEON_ENCODE (INTEGER
, inst
);
14265 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14266 zero. Should be OK as-is. */
14267 neon_mixed_length (et
, et
.size
);
14274 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14275 struct neon_type_el et
= neon_check_type (3, rs
,
14276 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14277 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14279 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14280 _("shift out of range"));
14281 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14282 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14283 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14284 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14285 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14286 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14287 inst
.instruction
|= neon_quad (rs
) << 6;
14288 inst
.instruction
|= imm
<< 8;
14290 neon_dp_fixup (&inst
);
14296 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14297 struct neon_type_el et
= neon_check_type (2, rs
,
14298 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14299 unsigned op
= (inst
.instruction
>> 7) & 3;
14300 /* N (width of reversed regions) is encoded as part of the bitmask. We
14301 extract it here to check the elements to be reversed are smaller.
14302 Otherwise we'd get a reserved instruction. */
14303 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14304 gas_assert (elsize
!= 0);
14305 constraint (et
.size
>= elsize
,
14306 _("elements must be smaller than reversal region"));
14307 neon_two_same (neon_quad (rs
), 1, et
.size
);
14313 if (inst
.operands
[1].isscalar
)
14315 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14316 struct neon_type_el et
= neon_check_type (2, rs
,
14317 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14318 unsigned sizebits
= et
.size
>> 3;
14319 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14320 int logsize
= neon_logbits (et
.size
);
14321 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14323 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14326 NEON_ENCODE (SCALAR
, inst
);
14327 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14328 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14329 inst
.instruction
|= LOW4 (dm
);
14330 inst
.instruction
|= HI1 (dm
) << 5;
14331 inst
.instruction
|= neon_quad (rs
) << 6;
14332 inst
.instruction
|= x
<< 17;
14333 inst
.instruction
|= sizebits
<< 16;
14335 neon_dp_fixup (&inst
);
14339 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14340 struct neon_type_el et
= neon_check_type (2, rs
,
14341 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14342 /* Duplicate ARM register to lanes of vector. */
14343 NEON_ENCODE (ARMREG
, inst
);
14346 case 8: inst
.instruction
|= 0x400000; break;
14347 case 16: inst
.instruction
|= 0x000020; break;
14348 case 32: inst
.instruction
|= 0x000000; break;
14351 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14352 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14353 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14354 inst
.instruction
|= neon_quad (rs
) << 21;
14355 /* The encoding for this instruction is identical for the ARM and Thumb
14356 variants, except for the condition field. */
14357 do_vfp_cond_or_thumb ();
14361 /* VMOV has particularly many variations. It can be one of:
14362 0. VMOV<c><q> <Qd>, <Qm>
14363 1. VMOV<c><q> <Dd>, <Dm>
14364 (Register operations, which are VORR with Rm = Rn.)
14365 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14366 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14368 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14369 (ARM register to scalar.)
14370 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14371 (Two ARM registers to vector.)
14372 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14373 (Scalar to ARM register.)
14374 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14375 (Vector to two ARM registers.)
14376 8. VMOV.F32 <Sd>, <Sm>
14377 9. VMOV.F64 <Dd>, <Dm>
14378 (VFP register moves.)
14379 10. VMOV.F32 <Sd>, #imm
14380 11. VMOV.F64 <Dd>, #imm
14381 (VFP float immediate load.)
14382 12. VMOV <Rd>, <Sm>
14383 (VFP single to ARM reg.)
14384 13. VMOV <Sd>, <Rm>
14385 (ARM reg to VFP single.)
14386 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14387 (Two ARM regs to two VFP singles.)
14388 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14389 (Two VFP singles to two ARM regs.)
14391 These cases can be disambiguated using neon_select_shape, except cases 1/9
14392 and 3/11 which depend on the operand type too.
14394 All the encoded bits are hardcoded by this function.
14396 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14397 Cases 5, 7 may be used with VFPv2 and above.
14399 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14400 can specify a type where it doesn't make sense to, and is ignored). */
14405 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14406 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14408 struct neon_type_el et
;
14409 const char *ldconst
= 0;
14413 case NS_DD
: /* case 1/9. */
14414 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14415 /* It is not an error here if no type is given. */
14417 if (et
.type
== NT_float
&& et
.size
== 64)
14419 do_vfp_nsyn_opcode ("fcpyd");
14422 /* fall through. */
14424 case NS_QQ
: /* case 0/1. */
14426 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14428 /* The architecture manual I have doesn't explicitly state which
14429 value the U bit should have for register->register moves, but
14430 the equivalent VORR instruction has U = 0, so do that. */
14431 inst
.instruction
= 0x0200110;
14432 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14433 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14434 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14435 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14436 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14437 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14438 inst
.instruction
|= neon_quad (rs
) << 6;
14440 neon_dp_fixup (&inst
);
14444 case NS_DI
: /* case 3/11. */
14445 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14447 if (et
.type
== NT_float
&& et
.size
== 64)
14449 /* case 11 (fconstd). */
14450 ldconst
= "fconstd";
14451 goto encode_fconstd
;
14453 /* fall through. */
14455 case NS_QI
: /* case 2/3. */
14456 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14458 inst
.instruction
= 0x0800010;
14459 neon_move_immediate ();
14460 neon_dp_fixup (&inst
);
14463 case NS_SR
: /* case 4. */
14465 unsigned bcdebits
= 0;
14467 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14468 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14470 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14471 logsize
= neon_logbits (et
.size
);
14473 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14475 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14476 && et
.size
!= 32, _(BAD_FPU
));
14477 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14478 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14482 case 8: bcdebits
= 0x8; break;
14483 case 16: bcdebits
= 0x1; break;
14484 case 32: bcdebits
= 0x0; break;
14488 bcdebits
|= x
<< logsize
;
14490 inst
.instruction
= 0xe000b10;
14491 do_vfp_cond_or_thumb ();
14492 inst
.instruction
|= LOW4 (dn
) << 16;
14493 inst
.instruction
|= HI1 (dn
) << 7;
14494 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14495 inst
.instruction
|= (bcdebits
& 3) << 5;
14496 inst
.instruction
|= (bcdebits
>> 2) << 21;
14500 case NS_DRR
: /* case 5 (fmdrr). */
14501 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14504 inst
.instruction
= 0xc400b10;
14505 do_vfp_cond_or_thumb ();
14506 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14507 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14508 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14509 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14512 case NS_RS
: /* case 6. */
14515 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14516 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14517 unsigned abcdebits
= 0;
14519 et
= neon_check_type (2, NS_NULL
,
14520 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14521 logsize
= neon_logbits (et
.size
);
14523 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14525 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14526 && et
.size
!= 32, _(BAD_FPU
));
14527 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14528 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14532 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14533 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14534 case 32: abcdebits
= 0x00; break;
14538 abcdebits
|= x
<< logsize
;
14539 inst
.instruction
= 0xe100b10;
14540 do_vfp_cond_or_thumb ();
14541 inst
.instruction
|= LOW4 (dn
) << 16;
14542 inst
.instruction
|= HI1 (dn
) << 7;
14543 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14544 inst
.instruction
|= (abcdebits
& 3) << 5;
14545 inst
.instruction
|= (abcdebits
>> 2) << 21;
14549 case NS_RRD
: /* case 7 (fmrrd). */
14550 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14553 inst
.instruction
= 0xc500b10;
14554 do_vfp_cond_or_thumb ();
14555 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14556 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14557 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14558 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14561 case NS_FF
: /* case 8 (fcpys). */
14562 do_vfp_nsyn_opcode ("fcpys");
14565 case NS_FI
: /* case 10 (fconsts). */
14566 ldconst
= "fconsts";
14568 if (is_quarter_float (inst
.operands
[1].imm
))
14570 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14571 do_vfp_nsyn_opcode (ldconst
);
14574 first_error (_("immediate out of range"));
14577 case NS_RF
: /* case 12 (fmrs). */
14578 do_vfp_nsyn_opcode ("fmrs");
14581 case NS_FR
: /* case 13 (fmsr). */
14582 do_vfp_nsyn_opcode ("fmsr");
14585 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14586 (one of which is a list), but we have parsed four. Do some fiddling to
14587 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14589 case NS_RRFF
: /* case 14 (fmrrs). */
14590 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14591 _("VFP registers must be adjacent"));
14592 inst
.operands
[2].imm
= 2;
14593 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14594 do_vfp_nsyn_opcode ("fmrrs");
14597 case NS_FFRR
: /* case 15 (fmsrr). */
14598 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14599 _("VFP registers must be adjacent"));
14600 inst
.operands
[1] = inst
.operands
[2];
14601 inst
.operands
[2] = inst
.operands
[3];
14602 inst
.operands
[0].imm
= 2;
14603 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14604 do_vfp_nsyn_opcode ("fmsrr");
14613 do_neon_rshift_round_imm (void)
14615 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14616 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14617 int imm
= inst
.operands
[2].imm
;
14619 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14622 inst
.operands
[2].present
= 0;
14627 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14628 _("immediate out of range for shift"));
14629 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14634 do_neon_movl (void)
14636 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14637 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14638 unsigned sizebits
= et
.size
>> 3;
14639 inst
.instruction
|= sizebits
<< 19;
14640 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14646 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14647 struct neon_type_el et
= neon_check_type (2, rs
,
14648 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14649 NEON_ENCODE (INTEGER
, inst
);
14650 neon_two_same (neon_quad (rs
), 1, et
.size
);
14654 do_neon_zip_uzp (void)
14656 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14657 struct neon_type_el et
= neon_check_type (2, rs
,
14658 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14659 if (rs
== NS_DD
&& et
.size
== 32)
14661 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14662 inst
.instruction
= N_MNEM_vtrn
;
14666 neon_two_same (neon_quad (rs
), 1, et
.size
);
14670 do_neon_sat_abs_neg (void)
14672 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14673 struct neon_type_el et
= neon_check_type (2, rs
,
14674 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14675 neon_two_same (neon_quad (rs
), 1, et
.size
);
14679 do_neon_pair_long (void)
14681 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14682 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14683 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14684 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14685 neon_two_same (neon_quad (rs
), 1, et
.size
);
14689 do_neon_recip_est (void)
14691 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14692 struct neon_type_el et
= neon_check_type (2, rs
,
14693 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14694 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14695 neon_two_same (neon_quad (rs
), 1, et
.size
);
14701 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14702 struct neon_type_el et
= neon_check_type (2, rs
,
14703 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14704 neon_two_same (neon_quad (rs
), 1, et
.size
);
14710 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14711 struct neon_type_el et
= neon_check_type (2, rs
,
14712 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14713 neon_two_same (neon_quad (rs
), 1, et
.size
);
14719 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14720 struct neon_type_el et
= neon_check_type (2, rs
,
14721 N_EQK
| N_INT
, N_8
| N_KEY
);
14722 neon_two_same (neon_quad (rs
), 1, et
.size
);
14728 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14729 neon_two_same (neon_quad (rs
), 1, -1);
14733 do_neon_tbl_tbx (void)
14735 unsigned listlenbits
;
14736 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14738 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14740 first_error (_("bad list length for table lookup"));
14744 listlenbits
= inst
.operands
[1].imm
- 1;
14745 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14746 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14747 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14748 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14749 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14750 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14751 inst
.instruction
|= listlenbits
<< 8;
14753 neon_dp_fixup (&inst
);
14757 do_neon_ldm_stm (void)
14759 /* P, U and L bits are part of bitmask. */
14760 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14761 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14763 if (inst
.operands
[1].issingle
)
14765 do_vfp_nsyn_ldm_stm (is_dbmode
);
14769 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14770 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14772 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14773 _("register list must contain at least 1 and at most 16 "
14776 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14777 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14778 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14779 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14781 inst
.instruction
|= offsetbits
;
14783 do_vfp_cond_or_thumb ();
14787 do_neon_ldr_str (void)
14789 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14791 if (inst
.operands
[0].issingle
)
14794 do_vfp_nsyn_opcode ("flds");
14796 do_vfp_nsyn_opcode ("fsts");
14801 do_vfp_nsyn_opcode ("fldd");
14803 do_vfp_nsyn_opcode ("fstd");
14807 /* "interleave" version also handles non-interleaving register VLD1/VST1
14811 do_neon_ld_st_interleave (void)
14813 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14814 N_8
| N_16
| N_32
| N_64
);
14815 unsigned alignbits
= 0;
14817 /* The bits in this table go:
14818 0: register stride of one (0) or two (1)
14819 1,2: register list length, minus one (1, 2, 3, 4).
14820 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14821 We use -1 for invalid entries. */
14822 const int typetable
[] =
14824 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14825 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14826 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14827 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14831 if (et
.type
== NT_invtype
)
14834 if (inst
.operands
[1].immisalign
)
14835 switch (inst
.operands
[1].imm
>> 8)
14837 case 64: alignbits
= 1; break;
14839 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
14840 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14841 goto bad_alignment
;
14845 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14846 goto bad_alignment
;
14851 first_error (_("bad alignment"));
14855 inst
.instruction
|= alignbits
<< 4;
14856 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14858 /* Bits [4:6] of the immediate in a list specifier encode register stride
14859 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14860 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14861 up the right value for "type" in a table based on this value and the given
14862 list style, then stick it back. */
14863 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14864 | (((inst
.instruction
>> 8) & 3) << 3);
14866 typebits
= typetable
[idx
];
14868 constraint (typebits
== -1, _("bad list type for instruction"));
14870 inst
.instruction
&= ~0xf00;
14871 inst
.instruction
|= typebits
<< 8;
14874 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14875 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14876 otherwise. The variable arguments are a list of pairs of legal (size, align)
14877 values, terminated with -1. */
14880 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14883 int result
= FAIL
, thissize
, thisalign
;
14885 if (!inst
.operands
[1].immisalign
)
14891 va_start (ap
, do_align
);
14895 thissize
= va_arg (ap
, int);
14896 if (thissize
== -1)
14898 thisalign
= va_arg (ap
, int);
14900 if (size
== thissize
&& align
== thisalign
)
14903 while (result
!= SUCCESS
);
14907 if (result
== SUCCESS
)
14910 first_error (_("unsupported alignment for instruction"));
14916 do_neon_ld_st_lane (void)
14918 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14919 int align_good
, do_align
= 0;
14920 int logsize
= neon_logbits (et
.size
);
14921 int align
= inst
.operands
[1].imm
>> 8;
14922 int n
= (inst
.instruction
>> 8) & 3;
14923 int max_el
= 64 / et
.size
;
14925 if (et
.type
== NT_invtype
)
14928 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14929 _("bad list length"));
14930 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14931 _("scalar index out of range"));
14932 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14934 _("stride of 2 unavailable when element size is 8"));
14938 case 0: /* VLD1 / VST1. */
14939 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14941 if (align_good
== FAIL
)
14945 unsigned alignbits
= 0;
14948 case 16: alignbits
= 0x1; break;
14949 case 32: alignbits
= 0x3; break;
14952 inst
.instruction
|= alignbits
<< 4;
14956 case 1: /* VLD2 / VST2. */
14957 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14959 if (align_good
== FAIL
)
14962 inst
.instruction
|= 1 << 4;
14965 case 2: /* VLD3 / VST3. */
14966 constraint (inst
.operands
[1].immisalign
,
14967 _("can't use alignment with this instruction"));
14970 case 3: /* VLD4 / VST4. */
14971 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14972 16, 64, 32, 64, 32, 128, -1);
14973 if (align_good
== FAIL
)
14977 unsigned alignbits
= 0;
14980 case 8: alignbits
= 0x1; break;
14981 case 16: alignbits
= 0x1; break;
14982 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14985 inst
.instruction
|= alignbits
<< 4;
14992 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14993 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14994 inst
.instruction
|= 1 << (4 + logsize
);
14996 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14997 inst
.instruction
|= logsize
<< 10;
15000 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15003 do_neon_ld_dup (void)
15005 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15006 int align_good
, do_align
= 0;
15008 if (et
.type
== NT_invtype
)
15011 switch ((inst
.instruction
>> 8) & 3)
15013 case 0: /* VLD1. */
15014 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15015 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15016 &do_align
, 16, 16, 32, 32, -1);
15017 if (align_good
== FAIL
)
15019 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15022 case 2: inst
.instruction
|= 1 << 5; break;
15023 default: first_error (_("bad list length")); return;
15025 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15028 case 1: /* VLD2. */
15029 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15030 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15031 if (align_good
== FAIL
)
15033 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15034 _("bad list length"));
15035 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15036 inst
.instruction
|= 1 << 5;
15037 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15040 case 2: /* VLD3. */
15041 constraint (inst
.operands
[1].immisalign
,
15042 _("can't use alignment with this instruction"));
15043 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15044 _("bad list length"));
15045 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15046 inst
.instruction
|= 1 << 5;
15047 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15050 case 3: /* VLD4. */
15052 int align
= inst
.operands
[1].imm
>> 8;
15053 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15054 16, 64, 32, 64, 32, 128, -1);
15055 if (align_good
== FAIL
)
15057 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15058 _("bad list length"));
15059 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15060 inst
.instruction
|= 1 << 5;
15061 if (et
.size
== 32 && align
== 128)
15062 inst
.instruction
|= 0x3 << 6;
15064 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15071 inst
.instruction
|= do_align
<< 4;
15074 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15075 apart from bits [11:4]. */
15078 do_neon_ldx_stx (void)
15080 if (inst
.operands
[1].isreg
)
15081 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15083 switch (NEON_LANE (inst
.operands
[0].imm
))
15085 case NEON_INTERLEAVE_LANES
:
15086 NEON_ENCODE (INTERLV
, inst
);
15087 do_neon_ld_st_interleave ();
15090 case NEON_ALL_LANES
:
15091 NEON_ENCODE (DUP
, inst
);
15096 NEON_ENCODE (LANE
, inst
);
15097 do_neon_ld_st_lane ();
15100 /* L bit comes from bit mask. */
15101 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15102 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15103 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15105 if (inst
.operands
[1].postind
)
15107 int postreg
= inst
.operands
[1].imm
& 0xf;
15108 constraint (!inst
.operands
[1].immisreg
,
15109 _("post-index must be a register"));
15110 constraint (postreg
== 0xd || postreg
== 0xf,
15111 _("bad register for post-index"));
15112 inst
.instruction
|= postreg
;
15114 else if (inst
.operands
[1].writeback
)
15116 inst
.instruction
|= 0xd;
15119 inst
.instruction
|= 0xf;
15122 inst
.instruction
|= 0xf9000000;
15124 inst
.instruction
|= 0xf4000000;
15127 /* Overall per-instruction processing. */
15129 /* We need to be able to fix up arbitrary expressions in some statements.
15130 This is so that we can handle symbols that are an arbitrary distance from
15131 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15132 which returns part of an address in a form which will be valid for
15133 a data instruction. We do this by pushing the expression into a symbol
15134 in the expr_section, and creating a fix for that. */
15137 fix_new_arm (fragS
* frag
,
15152 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15153 (enum bfd_reloc_code_real
) reloc
);
15157 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15158 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15162 /* Mark whether the fix is to a THUMB instruction, or an ARM
15164 new_fix
->tc_fix_data
= thumb_mode
;
15167 /* Create a frg for an instruction requiring relaxation. */
15169 output_relax_insn (void)
15175 /* The size of the instruction is unknown, so tie the debug info to the
15176 start of the instruction. */
15177 dwarf2_emit_insn (0);
15179 switch (inst
.reloc
.exp
.X_op
)
15182 sym
= inst
.reloc
.exp
.X_add_symbol
;
15183 offset
= inst
.reloc
.exp
.X_add_number
;
15187 offset
= inst
.reloc
.exp
.X_add_number
;
15190 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15194 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15195 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15196 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15199 /* Write a 32-bit thumb instruction to buf. */
15201 put_thumb32_insn (char * buf
, unsigned long insn
)
15203 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15204 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15208 output_inst (const char * str
)
15214 as_bad ("%s -- `%s'", inst
.error
, str
);
15219 output_relax_insn ();
15222 if (inst
.size
== 0)
15225 to
= frag_more (inst
.size
);
15226 /* PR 9814: Record the thumb mode into the current frag so that we know
15227 what type of NOP padding to use, if necessary. We override any previous
15228 setting so that if the mode has changed then the NOPS that we use will
15229 match the encoding of the last instruction in the frag. */
15230 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15232 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15234 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15235 put_thumb32_insn (to
, inst
.instruction
);
15237 else if (inst
.size
> INSN_SIZE
)
15239 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15240 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15241 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15244 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15246 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15247 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15248 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15251 dwarf2_emit_insn (inst
.size
);
15255 output_it_inst (int cond
, int mask
, char * to
)
15257 unsigned long instruction
= 0xbf00;
15260 instruction
|= mask
;
15261 instruction
|= cond
<< 4;
15265 to
= frag_more (2);
15267 dwarf2_emit_insn (2);
15271 md_number_to_chars (to
, instruction
, 2);
15276 /* Tag values used in struct asm_opcode's tag field. */
15279 OT_unconditional
, /* Instruction cannot be conditionalized.
15280 The ARM condition field is still 0xE. */
15281 OT_unconditionalF
, /* Instruction cannot be conditionalized
15282 and carries 0xF in its ARM condition field. */
15283 OT_csuffix
, /* Instruction takes a conditional suffix. */
15284 OT_csuffixF
, /* Some forms of the instruction take a conditional
15285 suffix, others place 0xF where the condition field
15287 OT_cinfix3
, /* Instruction takes a conditional infix,
15288 beginning at character index 3. (In
15289 unified mode, it becomes a suffix.) */
15290 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15291 tsts, cmps, cmns, and teqs. */
15292 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15293 character index 3, even in unified mode. Used for
15294 legacy instructions where suffix and infix forms
15295 may be ambiguous. */
15296 OT_csuf_or_in3
, /* Instruction takes either a conditional
15297 suffix or an infix at character index 3. */
15298 OT_odd_infix_unc
, /* This is the unconditional variant of an
15299 instruction that takes a conditional infix
15300 at an unusual position. In unified mode,
15301 this variant will accept a suffix. */
15302 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15303 are the conditional variants of instructions that
15304 take conditional infixes in unusual positions.
15305 The infix appears at character index
15306 (tag - OT_odd_infix_0). These are not accepted
15307 in unified mode. */
15310 /* Subroutine of md_assemble, responsible for looking up the primary
15311 opcode from the mnemonic the user wrote. STR points to the
15312 beginning of the mnemonic.
15314 This is not simply a hash table lookup, because of conditional
15315 variants. Most instructions have conditional variants, which are
15316 expressed with a _conditional affix_ to the mnemonic. If we were
15317 to encode each conditional variant as a literal string in the opcode
15318 table, it would have approximately 20,000 entries.
15320 Most mnemonics take this affix as a suffix, and in unified syntax,
15321 'most' is upgraded to 'all'. However, in the divided syntax, some
15322 instructions take the affix as an infix, notably the s-variants of
15323 the arithmetic instructions. Of those instructions, all but six
15324 have the infix appear after the third character of the mnemonic.
15326 Accordingly, the algorithm for looking up primary opcodes given
15329 1. Look up the identifier in the opcode table.
15330 If we find a match, go to step U.
15332 2. Look up the last two characters of the identifier in the
15333 conditions table. If we find a match, look up the first N-2
15334 characters of the identifier in the opcode table. If we
15335 find a match, go to step CE.
15337 3. Look up the fourth and fifth characters of the identifier in
15338 the conditions table. If we find a match, extract those
15339 characters from the identifier, and look up the remaining
15340 characters in the opcode table. If we find a match, go
15345 U. Examine the tag field of the opcode structure, in case this is
15346 one of the six instructions with its conditional infix in an
15347 unusual place. If it is, the tag tells us where to find the
15348 infix; look it up in the conditions table and set inst.cond
15349 accordingly. Otherwise, this is an unconditional instruction.
15350 Again set inst.cond accordingly. Return the opcode structure.
15352 CE. Examine the tag field to make sure this is an instruction that
15353 should receive a conditional suffix. If it is not, fail.
15354 Otherwise, set inst.cond from the suffix we already looked up,
15355 and return the opcode structure.
15357 CM. Examine the tag field to make sure this is an instruction that
15358 should receive a conditional infix after the third character.
15359 If it is not, fail. Otherwise, undo the edits to the current
15360 line of input and proceed as for case CE. */
15362 static const struct asm_opcode
*
15363 opcode_lookup (char **str
)
15367 const struct asm_opcode
*opcode
;
15368 const struct asm_cond
*cond
;
15371 /* Scan up to the end of the mnemonic, which must end in white space,
15372 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15373 for (base
= end
= *str
; *end
!= '\0'; end
++)
15374 if (*end
== ' ' || *end
== '.')
15380 /* Handle a possible width suffix and/or Neon type suffix. */
15385 /* The .w and .n suffixes are only valid if the unified syntax is in
15387 if (unified_syntax
&& end
[1] == 'w')
15389 else if (unified_syntax
&& end
[1] == 'n')
15394 inst
.vectype
.elems
= 0;
15396 *str
= end
+ offset
;
15398 if (end
[offset
] == '.')
15400 /* See if we have a Neon type suffix (possible in either unified or
15401 non-unified ARM syntax mode). */
15402 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15405 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15411 /* Look for unaffixed or special-case affixed mnemonic. */
15412 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15417 if (opcode
->tag
< OT_odd_infix_0
)
15419 inst
.cond
= COND_ALWAYS
;
15423 if (warn_on_deprecated
&& unified_syntax
)
15424 as_warn (_("conditional infixes are deprecated in unified syntax"));
15425 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15426 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15429 inst
.cond
= cond
->value
;
15433 /* Cannot have a conditional suffix on a mnemonic of less than two
15435 if (end
- base
< 3)
15438 /* Look for suffixed mnemonic. */
15440 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15441 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15443 if (opcode
&& cond
)
15446 switch (opcode
->tag
)
15448 case OT_cinfix3_legacy
:
15449 /* Ignore conditional suffixes matched on infix only mnemonics. */
15453 case OT_cinfix3_deprecated
:
15454 case OT_odd_infix_unc
:
15455 if (!unified_syntax
)
15457 /* else fall through */
15461 case OT_csuf_or_in3
:
15462 inst
.cond
= cond
->value
;
15465 case OT_unconditional
:
15466 case OT_unconditionalF
:
15468 inst
.cond
= cond
->value
;
15471 /* Delayed diagnostic. */
15472 inst
.error
= BAD_COND
;
15473 inst
.cond
= COND_ALWAYS
;
15482 /* Cannot have a usual-position infix on a mnemonic of less than
15483 six characters (five would be a suffix). */
15484 if (end
- base
< 6)
15487 /* Look for infixed mnemonic in the usual position. */
15489 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15493 memcpy (save
, affix
, 2);
15494 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15495 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15497 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15498 memcpy (affix
, save
, 2);
15501 && (opcode
->tag
== OT_cinfix3
15502 || opcode
->tag
== OT_cinfix3_deprecated
15503 || opcode
->tag
== OT_csuf_or_in3
15504 || opcode
->tag
== OT_cinfix3_legacy
))
15507 if (warn_on_deprecated
&& unified_syntax
15508 && (opcode
->tag
== OT_cinfix3
15509 || opcode
->tag
== OT_cinfix3_deprecated
))
15510 as_warn (_("conditional infixes are deprecated in unified syntax"));
15512 inst
.cond
= cond
->value
;
15519 /* This function generates an initial IT instruction, leaving its block
15520 virtually open for the new instructions. Eventually,
15521 the mask will be updated by now_it_add_mask () each time
15522 a new instruction needs to be included in the IT block.
15523 Finally, the block is closed with close_automatic_it_block ().
15524 The block closure can be requested either from md_assemble (),
15525 a tencode (), or due to a label hook. */
15528 new_automatic_it_block (int cond
)
15530 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15531 now_it
.mask
= 0x18;
15533 now_it
.block_length
= 1;
15534 mapping_state (MAP_THUMB
);
15535 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15538 /* Close an automatic IT block.
15539 See comments in new_automatic_it_block (). */
15542 close_automatic_it_block (void)
15544 now_it
.mask
= 0x10;
15545 now_it
.block_length
= 0;
15548 /* Update the mask of the current automatically-generated IT
15549 instruction. See comments in new_automatic_it_block (). */
15552 now_it_add_mask (int cond
)
15554 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15555 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15556 | ((bitvalue) << (nbit)))
15557 const int resulting_bit
= (cond
& 1);
15559 now_it
.mask
&= 0xf;
15560 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15562 (5 - now_it
.block_length
));
15563 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15565 ((5 - now_it
.block_length
) - 1) );
15566 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15569 #undef SET_BIT_VALUE
15572 /* The IT blocks handling machinery is accessed through the these functions:
15573 it_fsm_pre_encode () from md_assemble ()
15574 set_it_insn_type () optional, from the tencode functions
15575 set_it_insn_type_last () ditto
15576 in_it_block () ditto
15577 it_fsm_post_encode () from md_assemble ()
15578 force_automatic_it_block_close () from label habdling functions
15581 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15582 initializing the IT insn type with a generic initial value depending
15583 on the inst.condition.
15584 2) During the tencode function, two things may happen:
15585 a) The tencode function overrides the IT insn type by
15586 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15587 b) The tencode function queries the IT block state by
15588 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15590 Both set_it_insn_type and in_it_block run the internal FSM state
15591 handling function (handle_it_state), because: a) setting the IT insn
15592 type may incur in an invalid state (exiting the function),
15593 and b) querying the state requires the FSM to be updated.
15594 Specifically we want to avoid creating an IT block for conditional
15595 branches, so it_fsm_pre_encode is actually a guess and we can't
15596 determine whether an IT block is required until the tencode () routine
15597 has decided what type of instruction this actually it.
15598 Because of this, if set_it_insn_type and in_it_block have to be used,
15599 set_it_insn_type has to be called first.
15601 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15602 determines the insn IT type depending on the inst.cond code.
15603 When a tencode () routine encodes an instruction that can be
15604 either outside an IT block, or, in the case of being inside, has to be
15605 the last one, set_it_insn_type_last () will determine the proper
15606 IT instruction type based on the inst.cond code. Otherwise,
15607 set_it_insn_type can be called for overriding that logic or
15608 for covering other cases.
15610 Calling handle_it_state () may not transition the IT block state to
15611 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15612 still queried. Instead, if the FSM determines that the state should
15613 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15614 after the tencode () function: that's what it_fsm_post_encode () does.
15616 Since in_it_block () calls the state handling function to get an
15617 updated state, an error may occur (due to invalid insns combination).
15618 In that case, inst.error is set.
15619 Therefore, inst.error has to be checked after the execution of
15620 the tencode () routine.
15622 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15623 any pending state change (if any) that didn't take place in
15624 handle_it_state () as explained above. */
15627 it_fsm_pre_encode (void)
15629 if (inst
.cond
!= COND_ALWAYS
)
15630 inst
.it_insn_type
= INSIDE_IT_INSN
;
15632 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15634 now_it
.state_handled
= 0;
15637 /* IT state FSM handling function. */
15640 handle_it_state (void)
15642 now_it
.state_handled
= 1;
15644 switch (now_it
.state
)
15646 case OUTSIDE_IT_BLOCK
:
15647 switch (inst
.it_insn_type
)
15649 case OUTSIDE_IT_INSN
:
15652 case INSIDE_IT_INSN
:
15653 case INSIDE_IT_LAST_INSN
:
15654 if (thumb_mode
== 0)
15657 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15658 as_tsktsk (_("Warning: conditional outside an IT block"\
15663 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15664 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15666 /* Automatically generate the IT instruction. */
15667 new_automatic_it_block (inst
.cond
);
15668 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15669 close_automatic_it_block ();
15673 inst
.error
= BAD_OUT_IT
;
15679 case IF_INSIDE_IT_LAST_INSN
:
15680 case NEUTRAL_IT_INSN
:
15684 now_it
.state
= MANUAL_IT_BLOCK
;
15685 now_it
.block_length
= 0;
15690 case AUTOMATIC_IT_BLOCK
:
15691 /* Three things may happen now:
15692 a) We should increment current it block size;
15693 b) We should close current it block (closing insn or 4 insns);
15694 c) We should close current it block and start a new one (due
15695 to incompatible conditions or
15696 4 insns-length block reached). */
15698 switch (inst
.it_insn_type
)
15700 case OUTSIDE_IT_INSN
:
15701 /* The closure of the block shall happen immediatelly,
15702 so any in_it_block () call reports the block as closed. */
15703 force_automatic_it_block_close ();
15706 case INSIDE_IT_INSN
:
15707 case INSIDE_IT_LAST_INSN
:
15708 case IF_INSIDE_IT_LAST_INSN
:
15709 now_it
.block_length
++;
15711 if (now_it
.block_length
> 4
15712 || !now_it_compatible (inst
.cond
))
15714 force_automatic_it_block_close ();
15715 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15716 new_automatic_it_block (inst
.cond
);
15720 now_it_add_mask (inst
.cond
);
15723 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15724 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15725 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15726 close_automatic_it_block ();
15729 case NEUTRAL_IT_INSN
:
15730 now_it
.block_length
++;
15732 if (now_it
.block_length
> 4)
15733 force_automatic_it_block_close ();
15735 now_it_add_mask (now_it
.cc
& 1);
15739 close_automatic_it_block ();
15740 now_it
.state
= MANUAL_IT_BLOCK
;
15745 case MANUAL_IT_BLOCK
:
15747 /* Check conditional suffixes. */
15748 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15751 now_it
.mask
&= 0x1f;
15752 is_last
= (now_it
.mask
== 0x10);
15754 switch (inst
.it_insn_type
)
15756 case OUTSIDE_IT_INSN
:
15757 inst
.error
= BAD_NOT_IT
;
15760 case INSIDE_IT_INSN
:
15761 if (cond
!= inst
.cond
)
15763 inst
.error
= BAD_IT_COND
;
15768 case INSIDE_IT_LAST_INSN
:
15769 case IF_INSIDE_IT_LAST_INSN
:
15770 if (cond
!= inst
.cond
)
15772 inst
.error
= BAD_IT_COND
;
15777 inst
.error
= BAD_BRANCH
;
15782 case NEUTRAL_IT_INSN
:
15783 /* The BKPT instruction is unconditional even in an IT block. */
15787 inst
.error
= BAD_IT_IT
;
15798 it_fsm_post_encode (void)
15802 if (!now_it
.state_handled
)
15803 handle_it_state ();
15805 is_last
= (now_it
.mask
== 0x10);
15808 now_it
.state
= OUTSIDE_IT_BLOCK
;
15814 force_automatic_it_block_close (void)
15816 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15818 close_automatic_it_block ();
15819 now_it
.state
= OUTSIDE_IT_BLOCK
;
15827 if (!now_it
.state_handled
)
15828 handle_it_state ();
15830 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15834 md_assemble (char *str
)
15837 const struct asm_opcode
* opcode
;
15839 /* Align the previous label if needed. */
15840 if (last_label_seen
!= NULL
)
15842 symbol_set_frag (last_label_seen
, frag_now
);
15843 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15844 S_SET_SEGMENT (last_label_seen
, now_seg
);
15847 memset (&inst
, '\0', sizeof (inst
));
15848 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15850 opcode
= opcode_lookup (&p
);
15853 /* It wasn't an instruction, but it might be a register alias of
15854 the form alias .req reg, or a Neon .dn/.qn directive. */
15855 if (! create_register_alias (str
, p
)
15856 && ! create_neon_reg_alias (str
, p
))
15857 as_bad (_("bad instruction `%s'"), str
);
15862 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15863 as_warn (_("s suffix on comparison instruction is deprecated"));
15865 /* The value which unconditional instructions should have in place of the
15866 condition field. */
15867 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15871 arm_feature_set variant
;
15873 variant
= cpu_variant
;
15874 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15875 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15876 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15877 /* Check that this instruction is supported for this CPU. */
15878 if (!opcode
->tvariant
15879 || (thumb_mode
== 1
15880 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15882 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
15885 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15886 && opcode
->tencode
!= do_t_branch
)
15888 as_bad (_("Thumb does not support conditional execution"));
15892 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15894 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15895 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15896 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15898 /* Two things are addressed here.
15899 1) Implicit require narrow instructions on Thumb-1.
15900 This avoids relaxation accidentally introducing Thumb-2
15902 2) Reject wide instructions in non Thumb-2 cores. */
15903 if (inst
.size_req
== 0)
15905 else if (inst
.size_req
== 4)
15907 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
15913 inst
.instruction
= opcode
->tvalue
;
15915 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
15917 /* Prepare the it_insn_type for those encodings that don't set
15919 it_fsm_pre_encode ();
15921 opcode
->tencode ();
15923 it_fsm_post_encode ();
15926 if (!(inst
.error
|| inst
.relax
))
15928 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15929 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15930 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15932 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15937 /* Something has gone badly wrong if we try to relax a fixed size
15939 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15941 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15942 *opcode
->tvariant
);
15943 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15944 set those bits when Thumb-2 32-bit instructions are seen. ie.
15945 anything other than bl/blx and v6-M instructions.
15946 This is overly pessimistic for relaxable instructions. */
15947 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15949 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15950 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15951 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15954 check_neon_suffixes
;
15958 mapping_state (MAP_THUMB
);
15961 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15965 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15966 is_bx
= (opcode
->aencode
== do_bx
);
15968 /* Check that this instruction is supported for this CPU. */
15969 if (!(is_bx
&& fix_v4bx
)
15970 && !(opcode
->avariant
&&
15971 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15973 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
15978 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15982 inst
.instruction
= opcode
->avalue
;
15983 if (opcode
->tag
== OT_unconditionalF
)
15984 inst
.instruction
|= 0xF << 28;
15986 inst
.instruction
|= inst
.cond
<< 28;
15987 inst
.size
= INSN_SIZE
;
15988 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
15990 it_fsm_pre_encode ();
15991 opcode
->aencode ();
15992 it_fsm_post_encode ();
15994 /* Arm mode bx is marked as both v4T and v5 because it's still required
15995 on a hypothetical non-thumb v5 core. */
15997 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15999 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16000 *opcode
->avariant
);
16002 check_neon_suffixes
;
16006 mapping_state (MAP_ARM
);
16011 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16019 check_it_blocks_finished (void)
16024 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16025 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16026 == MANUAL_IT_BLOCK
)
16028 as_warn (_("section '%s' finished with an open IT block."),
16032 if (now_it
.state
== MANUAL_IT_BLOCK
)
16033 as_warn (_("file finished with an open IT block."));
16037 /* Various frobbings of labels and their addresses. */
16040 arm_start_line_hook (void)
16042 last_label_seen
= NULL
;
16046 arm_frob_label (symbolS
* sym
)
16048 last_label_seen
= sym
;
16050 ARM_SET_THUMB (sym
, thumb_mode
);
16052 #if defined OBJ_COFF || defined OBJ_ELF
16053 ARM_SET_INTERWORK (sym
, support_interwork
);
16056 force_automatic_it_block_close ();
16058 /* Note - do not allow local symbols (.Lxxx) to be labelled
16059 as Thumb functions. This is because these labels, whilst
16060 they exist inside Thumb code, are not the entry points for
16061 possible ARM->Thumb calls. Also, these labels can be used
16062 as part of a computed goto or switch statement. eg gcc
16063 can generate code that looks like this:
16065 ldr r2, [pc, .Laaa]
16075 The first instruction loads the address of the jump table.
16076 The second instruction converts a table index into a byte offset.
16077 The third instruction gets the jump address out of the table.
16078 The fourth instruction performs the jump.
16080 If the address stored at .Laaa is that of a symbol which has the
16081 Thumb_Func bit set, then the linker will arrange for this address
16082 to have the bottom bit set, which in turn would mean that the
16083 address computation performed by the third instruction would end
16084 up with the bottom bit set. Since the ARM is capable of unaligned
16085 word loads, the instruction would then load the incorrect address
16086 out of the jump table, and chaos would ensue. */
16087 if (label_is_thumb_function_name
16088 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16089 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16091 /* When the address of a Thumb function is taken the bottom
16092 bit of that address should be set. This will allow
16093 interworking between Arm and Thumb functions to work
16096 THUMB_SET_FUNC (sym
, 1);
16098 label_is_thumb_function_name
= FALSE
;
16101 dwarf2_emit_label (sym
);
16105 arm_data_in_code (void)
16107 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16109 *input_line_pointer
= '/';
16110 input_line_pointer
+= 5;
16111 *input_line_pointer
= 0;
16119 arm_canonicalize_symbol_name (char * name
)
16123 if (thumb_mode
&& (len
= strlen (name
)) > 5
16124 && streq (name
+ len
- 5, "/data"))
16125 *(name
+ len
- 5) = 0;
16130 /* Table of all register names defined by default. The user can
16131 define additional names with .req. Note that all register names
16132 should appear in both upper and lowercase variants. Some registers
16133 also have mixed-case names. */
16135 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16136 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16137 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16138 #define REGSET(p,t) \
16139 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16140 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16141 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16142 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16143 #define REGSETH(p,t) \
16144 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16145 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16146 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16147 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16148 #define REGSET2(p,t) \
16149 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16150 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16151 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16152 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16154 static const struct reg_entry reg_names
[] =
16156 /* ARM integer registers. */
16157 REGSET(r
, RN
), REGSET(R
, RN
),
16159 /* ATPCS synonyms. */
16160 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16161 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16162 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16164 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16165 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16166 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16168 /* Well-known aliases. */
16169 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16170 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16172 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16173 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16175 /* Coprocessor numbers. */
16176 REGSET(p
, CP
), REGSET(P
, CP
),
16178 /* Coprocessor register numbers. The "cr" variants are for backward
16180 REGSET(c
, CN
), REGSET(C
, CN
),
16181 REGSET(cr
, CN
), REGSET(CR
, CN
),
16183 /* FPA registers. */
16184 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16185 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16187 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16188 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16190 /* VFP SP registers. */
16191 REGSET(s
,VFS
), REGSET(S
,VFS
),
16192 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16194 /* VFP DP Registers. */
16195 REGSET(d
,VFD
), REGSET(D
,VFD
),
16196 /* Extra Neon DP registers. */
16197 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16199 /* Neon QP registers. */
16200 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16202 /* VFP control registers. */
16203 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16204 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16205 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16206 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16207 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16208 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16210 /* Maverick DSP coprocessor registers. */
16211 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16212 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16214 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16215 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16216 REGDEF(dspsc
,0,DSPSC
),
16218 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16219 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16220 REGDEF(DSPSC
,0,DSPSC
),
16222 /* iWMMXt data registers - p0, c0-15. */
16223 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16225 /* iWMMXt control registers - p1, c0-3. */
16226 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16227 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16228 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16229 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16231 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16232 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16233 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16234 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16235 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16237 /* XScale accumulator registers. */
16238 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16244 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16245 within psr_required_here. */
16246 static const struct asm_psr psrs
[] =
16248 /* Backward compatibility notation. Note that "all" is no longer
16249 truly all possible PSR bits. */
16250 {"all", PSR_c
| PSR_f
},
16254 /* Individual flags. */
16261 /* Combinations of flags. */
16262 {"fs", PSR_f
| PSR_s
},
16263 {"fx", PSR_f
| PSR_x
},
16264 {"fc", PSR_f
| PSR_c
},
16265 {"sf", PSR_s
| PSR_f
},
16266 {"sx", PSR_s
| PSR_x
},
16267 {"sc", PSR_s
| PSR_c
},
16268 {"xf", PSR_x
| PSR_f
},
16269 {"xs", PSR_x
| PSR_s
},
16270 {"xc", PSR_x
| PSR_c
},
16271 {"cf", PSR_c
| PSR_f
},
16272 {"cs", PSR_c
| PSR_s
},
16273 {"cx", PSR_c
| PSR_x
},
16274 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16275 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16276 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16277 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16278 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16279 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16280 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16281 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16282 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16283 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16284 {"scf", PSR_s
| PSR_c
| PSR_f
},
16285 {"scx", PSR_s
| PSR_c
| PSR_x
},
16286 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16287 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16288 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16289 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16290 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16291 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16292 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16293 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16294 {"csf", PSR_c
| PSR_s
| PSR_f
},
16295 {"csx", PSR_c
| PSR_s
| PSR_x
},
16296 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16297 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16298 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16299 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16300 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16301 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16302 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16303 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16304 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16305 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16306 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16307 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16308 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16309 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16310 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16311 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16312 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16313 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16314 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16315 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16316 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16317 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16318 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16319 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16320 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16321 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16325 {"nzcvqg", PSR_s
| PSR_f
}
16328 /* Table of V7M psr names. */
16329 static const struct asm_psr v7m_psrs
[] =
16331 {"apsr", 0 }, {"APSR", 0 },
16332 {"iapsr", 1 }, {"IAPSR", 1 },
16333 {"eapsr", 2 }, {"EAPSR", 2 },
16334 {"psr", 3 }, {"PSR", 3 },
16335 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16336 {"ipsr", 5 }, {"IPSR", 5 },
16337 {"epsr", 6 }, {"EPSR", 6 },
16338 {"iepsr", 7 }, {"IEPSR", 7 },
16339 {"msp", 8 }, {"MSP", 8 },
16340 {"psp", 9 }, {"PSP", 9 },
16341 {"primask", 16}, {"PRIMASK", 16},
16342 {"basepri", 17}, {"BASEPRI", 17},
16343 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16344 {"faultmask", 19}, {"FAULTMASK", 19},
16345 {"control", 20}, {"CONTROL", 20}
16348 /* Table of all shift-in-operand names. */
16349 static const struct asm_shift_name shift_names
[] =
16351 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16352 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16353 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16354 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16355 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16356 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16359 /* Table of all explicit relocation names. */
16361 static struct reloc_entry reloc_names
[] =
16363 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16364 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16365 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16366 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16367 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16368 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16369 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16370 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16371 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16372 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16373 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16374 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
}
16378 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16379 static const struct asm_cond conds
[] =
16383 {"cs", 0x2}, {"hs", 0x2},
16384 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16398 static struct asm_barrier_opt barrier_opt_names
[] =
16400 { "sy", 0xf }, { "SY", 0xf },
16401 { "un", 0x7 }, { "UN", 0x7 },
16402 { "st", 0xe }, { "ST", 0xe },
16403 { "unst", 0x6 }, { "UNST", 0x6 },
16404 { "ish", 0xb }, { "ISH", 0xb },
16405 { "sh", 0xb }, { "SH", 0xb },
16406 { "ishst", 0xa }, { "ISHST", 0xa },
16407 { "shst", 0xa }, { "SHST", 0xa },
16408 { "nsh", 0x7 }, { "NSH", 0x7 },
16409 { "nshst", 0x6 }, { "NSHST", 0x6 },
16410 { "osh", 0x3 }, { "OSH", 0x3 },
16411 { "oshst", 0x2 }, { "OSHST", 0x2 }
16414 /* Table of ARM-format instructions. */
16416 /* Macros for gluing together operand strings. N.B. In all cases
16417 other than OPS0, the trailing OP_stop comes from default
16418 zero-initialization of the unspecified elements of the array. */
16419 #define OPS0() { OP_stop, }
16420 #define OPS1(a) { OP_##a, }
16421 #define OPS2(a,b) { OP_##a,OP_##b, }
16422 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16423 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16424 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16425 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16427 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16428 This is useful when mixing operands for ARM and THUMB, i.e. using the
16429 MIX_ARM_THUMB_OPERANDS macro.
16430 In order to use these macros, prefix the number of operands with _
16432 #define OPS_1(a) { a, }
16433 #define OPS_2(a,b) { a,b, }
16434 #define OPS_3(a,b,c) { a,b,c, }
16435 #define OPS_4(a,b,c,d) { a,b,c,d, }
16436 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16437 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16439 /* These macros abstract out the exact format of the mnemonic table and
16440 save some repeated characters. */
16442 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16443 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16444 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16445 THUMB_VARIANT, do_##ae, do_##te }
16447 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16448 a T_MNEM_xyz enumerator. */
16449 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16450 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16451 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16452 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16454 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16455 infix after the third character. */
16456 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16457 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16458 THUMB_VARIANT, do_##ae, do_##te }
16459 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16460 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16461 THUMB_VARIANT, do_##ae, do_##te }
16462 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16463 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16464 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16465 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16466 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16467 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16468 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16469 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16471 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16472 appear in the condition table. */
16473 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16474 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16475 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16477 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16478 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16479 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16480 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16481 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16482 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16483 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16484 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16485 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16486 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16487 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16488 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16489 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16490 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16491 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16492 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16493 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16494 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16495 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16496 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16498 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16499 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16500 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16501 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16503 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16504 field is still 0xE. Many of the Thumb variants can be executed
16505 conditionally, so this is checked separately. */
16506 #define TUE(mnem, op, top, nops, ops, ae, te) \
16507 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16508 THUMB_VARIANT, do_##ae, do_##te }
16510 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16511 condition code field. */
16512 #define TUF(mnem, op, top, nops, ops, ae, te) \
16513 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16514 THUMB_VARIANT, do_##ae, do_##te }
16516 /* ARM-only variants of all the above. */
16517 #define CE(mnem, op, nops, ops, ae) \
16518 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16520 #define C3(mnem, op, nops, ops, ae) \
16521 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16523 /* Legacy mnemonics that always have conditional infix after the third
16525 #define CL(mnem, op, nops, ops, ae) \
16526 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16527 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16529 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16530 #define cCE(mnem, op, nops, ops, ae) \
16531 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16533 /* Legacy coprocessor instructions where conditional infix and conditional
16534 suffix are ambiguous. For consistency this includes all FPA instructions,
16535 not just the potentially ambiguous ones. */
16536 #define cCL(mnem, op, nops, ops, ae) \
16537 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16538 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16540 /* Coprocessor, takes either a suffix or a position-3 infix
16541 (for an FPA corner case). */
16542 #define C3E(mnem, op, nops, ops, ae) \
16543 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16544 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16546 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16547 { m1 #m2 m3, OPS##nops ops, \
16548 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16549 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16551 #define CM(m1, m2, op, nops, ops, ae) \
16552 xCM_ (m1, , m2, op, nops, ops, ae), \
16553 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16554 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16555 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16556 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16557 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16558 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16559 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16560 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16561 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16562 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16563 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16564 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16565 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16566 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16567 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16568 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16569 xCM_ (m1, le, m2, op, nops, ops, ae), \
16570 xCM_ (m1, al, m2, op, nops, ops, ae)
16572 #define UE(mnem, op, nops, ops, ae) \
16573 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16575 #define UF(mnem, op, nops, ops, ae) \
16576 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16578 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16579 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16580 use the same encoding function for each. */
16581 #define NUF(mnem, op, nops, ops, enc) \
16582 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16583 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16585 /* Neon data processing, version which indirects through neon_enc_tab for
16586 the various overloaded versions of opcodes. */
16587 #define nUF(mnem, op, nops, ops, enc) \
16588 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16589 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16591 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16593 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16594 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16595 THUMB_VARIANT, do_##enc, do_##enc }
16597 #define NCE(mnem, op, nops, ops, enc) \
16598 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16600 #define NCEF(mnem, op, nops, ops, enc) \
16601 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16603 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16604 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16605 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16606 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16608 #define nCE(mnem, op, nops, ops, enc) \
16609 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16611 #define nCEF(mnem, op, nops, ops, enc) \
16612 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16616 static const struct asm_opcode insns
[] =
16618 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16619 #define THUMB_VARIANT &arm_ext_v4t
16620 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16621 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16622 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16623 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16624 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16625 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16626 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16627 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16628 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16629 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16630 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16631 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16632 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16633 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16634 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16635 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16637 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16638 for setting PSR flag bits. They are obsolete in V6 and do not
16639 have Thumb equivalents. */
16640 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16641 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16642 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16643 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16644 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16645 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16646 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16647 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16648 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16650 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16651 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16652 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16653 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16655 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16656 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16657 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16659 OP_ADDRGLDR
),ldst
, t_ldst
),
16660 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16662 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16663 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16664 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16665 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16666 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16667 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16669 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16670 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16671 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16672 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16675 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16676 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16677 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16679 /* Thumb-compatibility pseudo ops. */
16680 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16681 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16682 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16683 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16684 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16685 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16686 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16687 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16688 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16689 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16690 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16691 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16693 /* These may simplify to neg. */
16694 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16695 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16697 #undef THUMB_VARIANT
16698 #define THUMB_VARIANT & arm_ext_v6
16700 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16702 /* V1 instructions with no Thumb analogue prior to V6T2. */
16703 #undef THUMB_VARIANT
16704 #define THUMB_VARIANT & arm_ext_v6t2
16706 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16707 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16708 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16710 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16711 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16712 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
16713 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16715 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16716 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16718 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16719 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16721 /* V1 instructions with no Thumb analogue at all. */
16722 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16723 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16725 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16726 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16727 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16728 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16729 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16730 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16731 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16732 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16735 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16736 #undef THUMB_VARIANT
16737 #define THUMB_VARIANT & arm_ext_v4t
16739 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16740 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16742 #undef THUMB_VARIANT
16743 #define THUMB_VARIANT & arm_ext_v6t2
16745 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16746 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16748 /* Generic coprocessor instructions. */
16749 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16750 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16751 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16752 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16753 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16754 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16755 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16758 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16760 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16761 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16764 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16765 #undef THUMB_VARIANT
16766 #define THUMB_VARIANT & arm_ext_msr
16768 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16769 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16772 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16773 #undef THUMB_VARIANT
16774 #define THUMB_VARIANT & arm_ext_v6t2
16776 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16777 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16778 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16779 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16780 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16781 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16782 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16783 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16786 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16787 #undef THUMB_VARIANT
16788 #define THUMB_VARIANT & arm_ext_v4t
16790 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16791 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16792 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16793 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16794 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16795 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16798 #define ARM_VARIANT & arm_ext_v4t_5
16800 /* ARM Architecture 4T. */
16801 /* Note: bx (and blx) are required on V5, even if the processor does
16802 not support Thumb. */
16803 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16806 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16807 #undef THUMB_VARIANT
16808 #define THUMB_VARIANT & arm_ext_v5t
16810 /* Note: blx has 2 variants; the .value coded here is for
16811 BLX(2). Only this variant has conditional execution. */
16812 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16813 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16815 #undef THUMB_VARIANT
16816 #define THUMB_VARIANT & arm_ext_v6t2
16818 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16819 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16820 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16821 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16822 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16823 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16824 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16825 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16828 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16829 #undef THUMB_VARIANT
16830 #define THUMB_VARIANT &arm_ext_v5exp
16832 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16833 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16834 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16835 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16837 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16838 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16840 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16841 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16842 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16843 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16845 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16846 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16847 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16848 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16850 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16851 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16853 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16854 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16855 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16856 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16859 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16860 #undef THUMB_VARIANT
16861 #define THUMB_VARIANT &arm_ext_v6t2
16863 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16864 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
16866 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
16867 ADDRGLDRS
), ldrd
, t_ldstd
),
16869 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16870 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16873 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16875 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16878 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16879 #undef THUMB_VARIANT
16880 #define THUMB_VARIANT & arm_ext_v6
16882 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16883 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16884 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16885 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16886 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16887 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16888 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16889 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16890 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16891 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16893 #undef THUMB_VARIANT
16894 #define THUMB_VARIANT & arm_ext_v6t2
16896 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
16897 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16899 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16900 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16902 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16903 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16905 /* ARM V6 not included in V7M. */
16906 #undef THUMB_VARIANT
16907 #define THUMB_VARIANT & arm_ext_v6_notm
16908 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16909 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16910 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16911 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16912 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16913 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16914 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16915 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16916 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16917 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16918 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16919 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16921 /* ARM V6 not included in V7M (eg. integer SIMD). */
16922 #undef THUMB_VARIANT
16923 #define THUMB_VARIANT & arm_ext_v6_dsp
16924 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16925 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16926 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16927 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16928 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16929 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16930 /* Old name for QASX. */
16931 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16932 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16933 /* Old name for QSAX. */
16934 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16935 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16936 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16937 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16938 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16939 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16940 /* Old name for SASX. */
16941 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16942 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16943 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16944 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16945 /* Old name for SHASX. */
16946 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16947 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16948 /* Old name for SHSAX. */
16949 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16950 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16951 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16952 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16953 /* Old name for SSAX. */
16954 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16955 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16956 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16957 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16958 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16959 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16960 /* Old name for UASX. */
16961 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16962 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16963 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16964 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16965 /* Old name for UHASX. */
16966 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16967 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16968 /* Old name for UHSAX. */
16969 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16970 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16971 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16972 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16973 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16974 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16975 /* Old name for UQASX. */
16976 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16977 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16978 /* Old name for UQSAX. */
16979 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16980 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16981 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16982 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16983 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16984 /* Old name for USAX. */
16985 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16986 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16987 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16988 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16989 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16990 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16991 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16992 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16993 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16994 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16995 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16996 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16997 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16998 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16999 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17000 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17001 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17002 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17003 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17004 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17005 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17006 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17007 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17008 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17009 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17010 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17011 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17012 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17013 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17014 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17015 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17016 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17017 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17018 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17021 #define ARM_VARIANT & arm_ext_v6k
17022 #undef THUMB_VARIANT
17023 #define THUMB_VARIANT & arm_ext_v6k
17025 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17026 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17027 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17028 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17030 #undef THUMB_VARIANT
17031 #define THUMB_VARIANT & arm_ext_v6_notm
17032 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17034 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17035 RRnpcb
), strexd
, t_strexd
),
17037 #undef THUMB_VARIANT
17038 #define THUMB_VARIANT & arm_ext_v6t2
17039 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17041 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17043 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17045 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17047 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17050 #define ARM_VARIANT & arm_ext_v6z
17052 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17055 #define ARM_VARIANT & arm_ext_v6t2
17057 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17058 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17059 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17060 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17062 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17063 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17064 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17065 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17067 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17068 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17069 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17070 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17072 /* Thumb-only instructions. */
17074 #define ARM_VARIANT NULL
17075 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17076 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17078 /* ARM does not really have an IT instruction, so always allow it.
17079 The opcode is copied from Thumb in order to allow warnings in
17080 -mimplicit-it=[never | arm] modes. */
17082 #define ARM_VARIANT & arm_ext_v1
17084 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17085 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17086 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17087 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17088 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17089 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17090 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17091 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17092 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17093 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17094 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17095 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17096 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17097 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17098 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17099 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17100 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17101 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17103 /* Thumb2 only instructions. */
17105 #define ARM_VARIANT NULL
17107 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17108 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17109 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17110 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17111 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17112 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17114 /* Thumb-2 hardware division instructions (R and M profiles only). */
17115 #undef THUMB_VARIANT
17116 #define THUMB_VARIANT & arm_ext_div
17118 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17119 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17121 /* ARM V6M/V7 instructions. */
17123 #define ARM_VARIANT & arm_ext_barrier
17124 #undef THUMB_VARIANT
17125 #define THUMB_VARIANT & arm_ext_barrier
17127 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17128 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17129 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17131 /* ARM V7 instructions. */
17133 #define ARM_VARIANT & arm_ext_v7
17134 #undef THUMB_VARIANT
17135 #define THUMB_VARIANT & arm_ext_v7
17137 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17138 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17141 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17143 cCE("wfs", e200110
, 1, (RR
), rd
),
17144 cCE("rfs", e300110
, 1, (RR
), rd
),
17145 cCE("wfc", e400110
, 1, (RR
), rd
),
17146 cCE("rfc", e500110
, 1, (RR
), rd
),
17148 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17149 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17150 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17151 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17153 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17154 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17155 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17156 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17158 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17159 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17160 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17161 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17162 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17163 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17164 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17165 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17166 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17167 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17168 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17169 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17171 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17172 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17173 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17174 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17175 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17176 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17177 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17178 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17179 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17180 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17181 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17182 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17184 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17185 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17186 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17187 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17188 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17189 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17190 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17191 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17192 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17193 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17194 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17195 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17197 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17198 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17199 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17200 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17201 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17202 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17203 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17204 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17205 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17206 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17207 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17208 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17210 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17211 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17212 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17213 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17214 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17215 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17216 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17217 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17218 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17219 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17220 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17221 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17223 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17224 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17225 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17226 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17227 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17228 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17229 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17230 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17231 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17232 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17233 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17234 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17236 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17237 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17238 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17239 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17240 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17241 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17242 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17243 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17244 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17245 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17246 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17247 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17249 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17250 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17251 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17252 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17253 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17254 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17255 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17256 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17257 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17258 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17259 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17260 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17262 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17263 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17264 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17265 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17266 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17267 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17268 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17269 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17270 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17271 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17272 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17273 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17275 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17276 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17277 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17278 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17279 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17280 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17281 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17282 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17283 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17284 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17285 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17286 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17288 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17289 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17290 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17291 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17292 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17293 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17294 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17295 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17296 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17297 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17298 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17299 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17301 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17302 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17303 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17304 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17305 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17306 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17307 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17308 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17309 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17310 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17311 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17312 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17314 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17315 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17316 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17317 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17318 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17319 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17320 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17321 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17322 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17323 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17324 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17325 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17327 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17328 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17329 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17330 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17331 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17332 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17333 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17334 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17335 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17336 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17337 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17338 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17340 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17341 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17342 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17343 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17344 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17345 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17346 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17347 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17348 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17349 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17350 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17351 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17353 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17354 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17355 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17356 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17357 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17358 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17359 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17360 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17361 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17362 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17363 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17364 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17366 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17367 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17368 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17369 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17370 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17371 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17372 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17373 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17374 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17375 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17376 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17377 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17379 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17380 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17381 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17382 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17383 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17384 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17385 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17386 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17387 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17388 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17389 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17390 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17392 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17393 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17394 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17395 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17396 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17397 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17398 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17399 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17400 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17401 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17402 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17403 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17405 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17406 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17407 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17408 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17409 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17410 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17411 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17412 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17413 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17414 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17415 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17416 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17418 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17419 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17420 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17421 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17422 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17423 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17424 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17425 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17426 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17427 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17428 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17429 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17431 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17432 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17433 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17434 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17435 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17436 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17437 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17438 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17439 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17440 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17441 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17442 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17444 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17445 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17446 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17447 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17448 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17449 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17450 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17451 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17452 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17453 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17454 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17455 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17457 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17458 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17459 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17460 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17461 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17462 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17463 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17464 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17465 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17466 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17467 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17468 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17470 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17471 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17472 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17473 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17474 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17475 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17476 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17477 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17478 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17479 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17480 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17481 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17483 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17484 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17485 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17486 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17487 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17488 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17489 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17490 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17491 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17492 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17493 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17494 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17496 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17497 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17498 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17499 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17500 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17501 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17502 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17503 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17504 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17505 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17506 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17507 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17509 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17510 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17511 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17512 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17513 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17514 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17515 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17516 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17517 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17518 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17519 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17520 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17522 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17523 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17524 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17525 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17526 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17527 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17528 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17529 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17530 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17531 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17532 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17533 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17535 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17536 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17537 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17538 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17540 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17541 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17542 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17543 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17544 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17545 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17546 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17547 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17548 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17549 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17550 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17551 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17553 /* The implementation of the FIX instruction is broken on some
17554 assemblers, in that it accepts a precision specifier as well as a
17555 rounding specifier, despite the fact that this is meaningless.
17556 To be more compatible, we accept it as well, though of course it
17557 does not set any bits. */
17558 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17559 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17560 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17561 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17562 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17563 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17564 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17565 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17566 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17567 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17568 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17569 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17570 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17572 /* Instructions that were new with the real FPA, call them V2. */
17574 #define ARM_VARIANT & fpu_fpa_ext_v2
17576 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17577 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17578 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17579 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17580 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17581 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17584 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17586 /* Moves and type conversions. */
17587 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17588 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17589 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17590 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17591 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17592 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17593 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17594 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17595 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17596 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17597 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17598 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17599 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17600 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17602 /* Memory operations. */
17603 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17604 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17605 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17606 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17607 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17608 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17609 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17610 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17611 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17612 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17613 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17614 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17615 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17616 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17617 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17618 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17619 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17620 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17622 /* Monadic operations. */
17623 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17624 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17625 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17627 /* Dyadic operations. */
17628 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17629 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17630 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17631 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17632 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17633 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17634 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17635 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17636 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17639 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17640 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17641 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17642 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17644 /* Double precision load/store are still present on single precision
17645 implementations. */
17646 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17647 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17648 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17649 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17650 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17651 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17652 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17653 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17654 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17655 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17658 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17660 /* Moves and type conversions. */
17661 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17662 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17663 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17664 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17665 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17666 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17667 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17668 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17669 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17670 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17671 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17672 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17673 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17675 /* Monadic operations. */
17676 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17677 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17678 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17680 /* Dyadic operations. */
17681 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17682 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17683 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17684 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17685 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17686 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17687 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17688 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17689 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17692 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17693 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17694 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17695 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17698 #define ARM_VARIANT & fpu_vfp_ext_v2
17700 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17701 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17702 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17703 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17705 /* Instructions which may belong to either the Neon or VFP instruction sets.
17706 Individual encoder functions perform additional architecture checks. */
17708 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17709 #undef THUMB_VARIANT
17710 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17712 /* These mnemonics are unique to VFP. */
17713 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17714 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17715 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17716 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17717 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17718 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17719 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17720 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17721 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17722 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17724 /* Mnemonics shared by Neon and VFP. */
17725 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17726 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17727 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17729 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17730 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17732 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17733 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17735 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17736 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17737 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17738 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17739 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17740 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17741 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17742 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17744 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17745 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17746 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17747 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17750 /* NOTE: All VMOV encoding is special-cased! */
17751 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17752 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17754 #undef THUMB_VARIANT
17755 #define THUMB_VARIANT & fpu_neon_ext_v1
17757 #define ARM_VARIANT & fpu_neon_ext_v1
17759 /* Data processing with three registers of the same length. */
17760 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17761 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17762 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17763 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17764 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17765 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17766 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17767 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17768 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17769 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17770 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17771 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17772 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17773 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17774 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17775 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17776 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17777 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17778 /* If not immediate, fall back to neon_dyadic_i64_su.
17779 shl_imm should accept I8 I16 I32 I64,
17780 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17781 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17782 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17783 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17784 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17785 /* Logic ops, types optional & ignored. */
17786 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17787 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17788 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17789 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17790 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17791 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17792 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17793 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17794 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17795 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17796 /* Bitfield ops, untyped. */
17797 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17798 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17799 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17800 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17801 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17802 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17803 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17804 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17805 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17806 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17807 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17808 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17809 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17810 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17811 back to neon_dyadic_if_su. */
17812 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17813 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17814 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17815 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17816 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17817 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17818 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17819 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17820 /* Comparison. Type I8 I16 I32 F32. */
17821 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17822 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17823 /* As above, D registers only. */
17824 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17825 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17826 /* Int and float variants, signedness unimportant. */
17827 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17828 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17829 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17830 /* Add/sub take types I8 I16 I32 I64 F32. */
17831 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17832 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17833 /* vtst takes sizes 8, 16, 32. */
17834 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17835 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17836 /* VMUL takes I8 I16 I32 F32 P8. */
17837 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17838 /* VQD{R}MULH takes S16 S32. */
17839 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17840 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17841 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17842 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17843 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17844 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17845 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17846 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17847 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17848 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17849 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17850 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17851 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17852 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17853 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17854 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17856 /* Two address, int/float. Types S8 S16 S32 F32. */
17857 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17858 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17860 /* Data processing with two registers and a shift amount. */
17861 /* Right shifts, and variants with rounding.
17862 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17863 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17864 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17865 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17866 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17867 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17868 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17869 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17870 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17871 /* Shift and insert. Sizes accepted 8 16 32 64. */
17872 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17873 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17874 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17875 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17876 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17877 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17878 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17879 /* Right shift immediate, saturating & narrowing, with rounding variants.
17880 Types accepted S16 S32 S64 U16 U32 U64. */
17881 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17882 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17883 /* As above, unsigned. Types accepted S16 S32 S64. */
17884 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17885 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17886 /* Right shift narrowing. Types accepted I16 I32 I64. */
17887 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17888 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17889 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17890 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17891 /* CVT with optional immediate for fixed-point variant. */
17892 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17894 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
17895 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
17897 /* Data processing, three registers of different lengths. */
17898 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17899 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17900 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17901 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17902 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17903 /* If not scalar, fall back to neon_dyadic_long.
17904 Vector types as above, scalar types S16 S32 U16 U32. */
17905 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17906 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17907 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17908 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17909 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17910 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17911 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17912 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17913 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17914 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17915 /* Saturating doubling multiplies. Types S16 S32. */
17916 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17917 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17918 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17919 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17920 S16 S32 U16 U32. */
17921 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17923 /* Extract. Size 8. */
17924 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17925 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17927 /* Two registers, miscellaneous. */
17928 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17929 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17930 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17931 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17932 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17933 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17934 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17935 /* Vector replicate. Sizes 8 16 32. */
17936 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17937 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17938 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17939 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17940 /* VMOVN. Types I16 I32 I64. */
17941 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17942 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17943 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17944 /* VQMOVUN. Types S16 S32 S64. */
17945 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17946 /* VZIP / VUZP. Sizes 8 16 32. */
17947 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17948 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17949 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17950 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17951 /* VQABS / VQNEG. Types S8 S16 S32. */
17952 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17953 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17954 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17955 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17956 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17957 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17958 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17959 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17960 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17961 /* Reciprocal estimates. Types U32 F32. */
17962 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17963 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17964 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17965 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17966 /* VCLS. Types S8 S16 S32. */
17967 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17968 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17969 /* VCLZ. Types I8 I16 I32. */
17970 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17971 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17972 /* VCNT. Size 8. */
17973 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17974 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17975 /* Two address, untyped. */
17976 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17977 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17978 /* VTRN. Sizes 8 16 32. */
17979 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17980 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17982 /* Table lookup. Size 8. */
17983 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17984 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17986 #undef THUMB_VARIANT
17987 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17989 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17991 /* Neon element/structure load/store. */
17992 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17993 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17994 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17995 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17996 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17997 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17998 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17999 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18001 #undef THUMB_VARIANT
18002 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18004 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18005 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18006 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18007 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18008 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18009 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18010 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18011 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18012 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18013 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18015 #undef THUMB_VARIANT
18016 #define THUMB_VARIANT & fpu_vfp_ext_v3
18018 #define ARM_VARIANT & fpu_vfp_ext_v3
18020 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18021 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18022 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18023 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18024 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18025 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18026 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18027 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18028 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18031 #define ARM_VARIANT &fpu_vfp_ext_fma
18032 #undef THUMB_VARIANT
18033 #define THUMB_VARIANT &fpu_vfp_ext_fma
18034 /* Mnemonics shared by Neon and VFP. These are included in the
18035 VFP FMA variant; NEON and VFP FMA always includes the NEON
18036 FMA instructions. */
18037 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18038 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18039 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18040 the v form should always be used. */
18041 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18042 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18043 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18044 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18045 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18046 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18048 #undef THUMB_VARIANT
18050 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18052 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18053 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18054 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18055 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18056 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18057 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18058 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18059 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18062 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18064 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18065 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18066 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18067 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18068 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18069 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18070 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18071 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18072 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18073 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18074 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18075 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18076 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18077 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18078 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18079 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18080 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18081 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18082 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18083 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18084 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18085 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18086 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18087 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18088 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18089 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18090 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18091 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18092 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18093 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18094 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18095 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18096 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18097 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18098 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18099 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18100 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18101 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18102 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18103 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18104 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18105 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18106 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18107 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18108 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18109 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18110 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18111 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18112 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18113 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18114 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18115 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18116 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18117 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18118 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18119 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18120 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18121 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18122 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18123 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18124 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18125 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18126 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18127 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18128 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18129 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18130 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18131 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18132 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18133 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18134 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18135 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18136 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18137 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18138 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18139 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18140 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18141 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18142 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18143 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18144 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18145 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18146 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18147 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18148 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18149 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18150 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18151 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18152 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18153 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18154 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18155 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18156 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18157 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18158 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18159 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18160 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18161 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18162 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18163 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18164 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18165 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18166 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18167 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18168 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18169 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18170 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18171 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18172 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18173 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18174 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18175 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18176 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18177 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18178 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18179 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18180 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18181 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18182 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18183 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18184 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18185 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18186 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18187 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18188 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18189 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18190 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18191 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18192 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18193 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18194 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18195 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18196 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18197 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18198 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18199 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18200 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18201 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18202 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18203 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18204 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18205 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18206 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18207 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18208 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18209 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18210 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18211 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18212 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18213 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18214 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18215 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18216 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18217 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18218 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18219 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18220 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18221 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18222 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18223 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18224 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18225 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18228 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18230 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18231 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18232 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18233 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18234 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18235 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18236 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18237 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18238 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18239 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18240 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18241 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18242 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18243 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18244 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18245 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18246 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18247 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18248 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18249 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18250 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18251 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18252 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18253 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18254 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18255 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18256 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18257 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18258 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18259 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18260 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18261 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18262 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18263 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18264 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18265 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18266 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18267 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18268 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18269 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18270 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18271 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18272 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18273 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18274 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18275 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18276 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18277 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18278 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18279 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18280 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18281 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18282 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18283 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18284 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18285 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18286 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18289 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18291 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18292 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18293 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18294 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18295 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18296 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18297 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18298 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18299 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18300 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18301 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18302 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18303 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18304 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18305 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18306 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18307 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18308 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18309 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18310 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18311 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18312 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18313 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18314 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18315 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18316 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18317 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18318 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18319 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18320 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18321 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18322 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18323 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18324 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18325 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18326 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18327 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18328 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18329 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18330 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18331 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18332 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18333 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18334 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18335 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18336 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18337 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18338 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18339 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18340 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18341 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18342 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18343 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18344 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18345 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18346 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18347 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18348 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18349 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18350 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18351 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18352 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18353 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18354 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18355 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18356 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18357 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18358 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18359 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18360 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18361 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18362 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18363 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18364 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18365 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18366 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18369 #undef THUMB_VARIANT
18396 /* MD interface: bits in the object file. */
18398 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18399 for use in the a.out file, and stores them in the array pointed to by buf.
18400 This knows about the endian-ness of the target machine and does
18401 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18402 2 (short) and 4 (long) Floating numbers are put out as a series of
18403 LITTLENUMS (shorts, here at least). */
18406 md_number_to_chars (char * buf
, valueT val
, int n
)
18408 if (target_big_endian
)
18409 number_to_chars_bigendian (buf
, val
, n
);
18411 number_to_chars_littleendian (buf
, val
, n
);
18415 md_chars_to_number (char * buf
, int n
)
18418 unsigned char * where
= (unsigned char *) buf
;
18420 if (target_big_endian
)
18425 result
|= (*where
++ & 255);
18433 result
|= (where
[n
] & 255);
18440 /* MD interface: Sections. */
18442 /* Estimate the size of a frag before relaxing. Assume everything fits in
18446 md_estimate_size_before_relax (fragS
* fragp
,
18447 segT segtype ATTRIBUTE_UNUSED
)
18453 /* Convert a machine dependent frag. */
18456 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18458 unsigned long insn
;
18459 unsigned long old_op
;
18467 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18469 old_op
= bfd_get_16(abfd
, buf
);
18470 if (fragp
->fr_symbol
)
18472 exp
.X_op
= O_symbol
;
18473 exp
.X_add_symbol
= fragp
->fr_symbol
;
18477 exp
.X_op
= O_constant
;
18479 exp
.X_add_number
= fragp
->fr_offset
;
18480 opcode
= fragp
->fr_subtype
;
18483 case T_MNEM_ldr_pc
:
18484 case T_MNEM_ldr_pc2
:
18485 case T_MNEM_ldr_sp
:
18486 case T_MNEM_str_sp
:
18493 if (fragp
->fr_var
== 4)
18495 insn
= THUMB_OP32 (opcode
);
18496 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18498 insn
|= (old_op
& 0x700) << 4;
18502 insn
|= (old_op
& 7) << 12;
18503 insn
|= (old_op
& 0x38) << 13;
18505 insn
|= 0x00000c00;
18506 put_thumb32_insn (buf
, insn
);
18507 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18511 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18513 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18516 if (fragp
->fr_var
== 4)
18518 insn
= THUMB_OP32 (opcode
);
18519 insn
|= (old_op
& 0xf0) << 4;
18520 put_thumb32_insn (buf
, insn
);
18521 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18525 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18526 exp
.X_add_number
-= 4;
18534 if (fragp
->fr_var
== 4)
18536 int r0off
= (opcode
== T_MNEM_mov
18537 || opcode
== T_MNEM_movs
) ? 0 : 8;
18538 insn
= THUMB_OP32 (opcode
);
18539 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18540 insn
|= (old_op
& 0x700) << r0off
;
18541 put_thumb32_insn (buf
, insn
);
18542 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18546 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18551 if (fragp
->fr_var
== 4)
18553 insn
= THUMB_OP32(opcode
);
18554 put_thumb32_insn (buf
, insn
);
18555 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18558 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18562 if (fragp
->fr_var
== 4)
18564 insn
= THUMB_OP32(opcode
);
18565 insn
|= (old_op
& 0xf00) << 14;
18566 put_thumb32_insn (buf
, insn
);
18567 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18570 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18573 case T_MNEM_add_sp
:
18574 case T_MNEM_add_pc
:
18575 case T_MNEM_inc_sp
:
18576 case T_MNEM_dec_sp
:
18577 if (fragp
->fr_var
== 4)
18579 /* ??? Choose between add and addw. */
18580 insn
= THUMB_OP32 (opcode
);
18581 insn
|= (old_op
& 0xf0) << 4;
18582 put_thumb32_insn (buf
, insn
);
18583 if (opcode
== T_MNEM_add_pc
)
18584 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18586 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18589 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18597 if (fragp
->fr_var
== 4)
18599 insn
= THUMB_OP32 (opcode
);
18600 insn
|= (old_op
& 0xf0) << 4;
18601 insn
|= (old_op
& 0xf) << 16;
18602 put_thumb32_insn (buf
, insn
);
18603 if (insn
& (1 << 20))
18604 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18606 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18609 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18615 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18616 (enum bfd_reloc_code_real
) reloc_type
);
18617 fixp
->fx_file
= fragp
->fr_file
;
18618 fixp
->fx_line
= fragp
->fr_line
;
18619 fragp
->fr_fix
+= fragp
->fr_var
;
18622 /* Return the size of a relaxable immediate operand instruction.
18623 SHIFT and SIZE specify the form of the allowable immediate. */
18625 relax_immediate (fragS
*fragp
, int size
, int shift
)
18631 /* ??? Should be able to do better than this. */
18632 if (fragp
->fr_symbol
)
18635 low
= (1 << shift
) - 1;
18636 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18637 offset
= fragp
->fr_offset
;
18638 /* Force misaligned offsets to 32-bit variant. */
18641 if (offset
& ~mask
)
18646 /* Get the address of a symbol during relaxation. */
18648 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18654 sym
= fragp
->fr_symbol
;
18655 sym_frag
= symbol_get_frag (sym
);
18656 know (S_GET_SEGMENT (sym
) != absolute_section
18657 || sym_frag
== &zero_address_frag
);
18658 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18660 /* If frag has yet to be reached on this pass, assume it will
18661 move by STRETCH just as we did. If this is not so, it will
18662 be because some frag between grows, and that will force
18666 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18670 /* Adjust stretch for any alignment frag. Note that if have
18671 been expanding the earlier code, the symbol may be
18672 defined in what appears to be an earlier frag. FIXME:
18673 This doesn't handle the fr_subtype field, which specifies
18674 a maximum number of bytes to skip when doing an
18676 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18678 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18681 stretch
= - ((- stretch
)
18682 & ~ ((1 << (int) f
->fr_offset
) - 1));
18684 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18696 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18699 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18704 /* Assume worst case for symbols not known to be in the same section. */
18705 if (fragp
->fr_symbol
== NULL
18706 || !S_IS_DEFINED (fragp
->fr_symbol
)
18707 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18708 || S_IS_WEAK (fragp
->fr_symbol
))
18711 val
= relaxed_symbol_addr (fragp
, stretch
);
18712 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18713 addr
= (addr
+ 4) & ~3;
18714 /* Force misaligned targets to 32-bit variant. */
18718 if (val
< 0 || val
> 1020)
18723 /* Return the size of a relaxable add/sub immediate instruction. */
18725 relax_addsub (fragS
*fragp
, asection
*sec
)
18730 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18731 op
= bfd_get_16(sec
->owner
, buf
);
18732 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18733 return relax_immediate (fragp
, 8, 0);
18735 return relax_immediate (fragp
, 3, 0);
18739 /* Return the size of a relaxable branch instruction. BITS is the
18740 size of the offset field in the narrow instruction. */
18743 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18749 /* Assume worst case for symbols not known to be in the same section. */
18750 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18751 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18752 || S_IS_WEAK (fragp
->fr_symbol
))
18756 if (S_IS_DEFINED (fragp
->fr_symbol
)
18757 && ARM_IS_FUNC (fragp
->fr_symbol
))
18761 val
= relaxed_symbol_addr (fragp
, stretch
);
18762 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18765 /* Offset is a signed value *2 */
18767 if (val
>= limit
|| val
< -limit
)
18773 /* Relax a machine dependent frag. This returns the amount by which
18774 the current size of the frag should change. */
18777 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18782 oldsize
= fragp
->fr_var
;
18783 switch (fragp
->fr_subtype
)
18785 case T_MNEM_ldr_pc2
:
18786 newsize
= relax_adr (fragp
, sec
, stretch
);
18788 case T_MNEM_ldr_pc
:
18789 case T_MNEM_ldr_sp
:
18790 case T_MNEM_str_sp
:
18791 newsize
= relax_immediate (fragp
, 8, 2);
18795 newsize
= relax_immediate (fragp
, 5, 2);
18799 newsize
= relax_immediate (fragp
, 5, 1);
18803 newsize
= relax_immediate (fragp
, 5, 0);
18806 newsize
= relax_adr (fragp
, sec
, stretch
);
18812 newsize
= relax_immediate (fragp
, 8, 0);
18815 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18818 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18820 case T_MNEM_add_sp
:
18821 case T_MNEM_add_pc
:
18822 newsize
= relax_immediate (fragp
, 8, 2);
18824 case T_MNEM_inc_sp
:
18825 case T_MNEM_dec_sp
:
18826 newsize
= relax_immediate (fragp
, 7, 2);
18832 newsize
= relax_addsub (fragp
, sec
);
18838 fragp
->fr_var
= newsize
;
18839 /* Freeze wide instructions that are at or before the same location as
18840 in the previous pass. This avoids infinite loops.
18841 Don't freeze them unconditionally because targets may be artificially
18842 misaligned by the expansion of preceding frags. */
18843 if (stretch
<= 0 && newsize
> 2)
18845 md_convert_frag (sec
->owner
, sec
, fragp
);
18849 return newsize
- oldsize
;
18852 /* Round up a section size to the appropriate boundary. */
18855 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18858 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18859 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18861 /* For a.out, force the section size to be aligned. If we don't do
18862 this, BFD will align it for us, but it will not write out the
18863 final bytes of the section. This may be a bug in BFD, but it is
18864 easier to fix it here since that is how the other a.out targets
18868 align
= bfd_get_section_alignment (stdoutput
, segment
);
18869 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18876 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18877 of an rs_align_code fragment. */
18880 arm_handle_align (fragS
* fragP
)
18882 static char const arm_noop
[2][2][4] =
18885 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18886 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18889 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18890 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18893 static char const thumb_noop
[2][2][2] =
18896 {0xc0, 0x46}, /* LE */
18897 {0x46, 0xc0}, /* BE */
18900 {0x00, 0xbf}, /* LE */
18901 {0xbf, 0x00} /* BE */
18904 static char const wide_thumb_noop
[2][4] =
18905 { /* Wide Thumb-2 */
18906 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18907 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18910 unsigned bytes
, fix
, noop_size
;
18913 const char *narrow_noop
= NULL
;
18918 if (fragP
->fr_type
!= rs_align_code
)
18921 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18922 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18925 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18926 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18928 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18930 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18932 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18934 narrow_noop
= thumb_noop
[1][target_big_endian
];
18935 noop
= wide_thumb_noop
[target_big_endian
];
18938 noop
= thumb_noop
[0][target_big_endian
];
18946 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18947 [target_big_endian
];
18954 fragP
->fr_var
= noop_size
;
18956 if (bytes
& (noop_size
- 1))
18958 fix
= bytes
& (noop_size
- 1);
18960 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18962 memset (p
, 0, fix
);
18969 if (bytes
& noop_size
)
18971 /* Insert a narrow noop. */
18972 memcpy (p
, narrow_noop
, noop_size
);
18974 bytes
-= noop_size
;
18978 /* Use wide noops for the remainder */
18982 while (bytes
>= noop_size
)
18984 memcpy (p
, noop
, noop_size
);
18986 bytes
-= noop_size
;
18990 fragP
->fr_fix
+= fix
;
18993 /* Called from md_do_align. Used to create an alignment
18994 frag in a code section. */
18997 arm_frag_align_code (int n
, int max
)
19001 /* We assume that there will never be a requirement
19002 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19003 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19008 _("alignments greater than %d bytes not supported in .text sections."),
19009 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19010 as_fatal ("%s", err_msg
);
19013 p
= frag_var (rs_align_code
,
19014 MAX_MEM_FOR_RS_ALIGN_CODE
,
19016 (relax_substateT
) max
,
19023 /* Perform target specific initialisation of a frag.
19024 Note - despite the name this initialisation is not done when the frag
19025 is created, but only when its type is assigned. A frag can be created
19026 and used a long time before its type is set, so beware of assuming that
19027 this initialisationis performed first. */
19031 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19033 /* Record whether this frag is in an ARM or a THUMB area. */
19034 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19037 #else /* OBJ_ELF is defined. */
19039 arm_init_frag (fragS
* fragP
, int max_chars
)
19041 /* If the current ARM vs THUMB mode has not already
19042 been recorded into this frag then do so now. */
19043 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19045 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19047 /* Record a mapping symbol for alignment frags. We will delete this
19048 later if the alignment ends up empty. */
19049 switch (fragP
->fr_type
)
19052 case rs_align_test
:
19054 mapping_state_2 (MAP_DATA
, max_chars
);
19056 case rs_align_code
:
19057 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19065 /* When we change sections we need to issue a new mapping symbol. */
19068 arm_elf_change_section (void)
19070 /* Link an unlinked unwind index table section to the .text section. */
19071 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19072 && elf_linked_to_section (now_seg
) == NULL
)
19073 elf_linked_to_section (now_seg
) = text_section
;
19077 arm_elf_section_type (const char * str
, size_t len
)
19079 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19080 return SHT_ARM_EXIDX
;
19085 /* Code to deal with unwinding tables. */
19087 static void add_unwind_adjustsp (offsetT
);
19089 /* Generate any deferred unwind frame offset. */
19092 flush_pending_unwind (void)
19096 offset
= unwind
.pending_offset
;
19097 unwind
.pending_offset
= 0;
19099 add_unwind_adjustsp (offset
);
19102 /* Add an opcode to this list for this function. Two-byte opcodes should
19103 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19107 add_unwind_opcode (valueT op
, int length
)
19109 /* Add any deferred stack adjustment. */
19110 if (unwind
.pending_offset
)
19111 flush_pending_unwind ();
19113 unwind
.sp_restored
= 0;
19115 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19117 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19118 if (unwind
.opcodes
)
19119 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19120 unwind
.opcode_alloc
);
19122 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19127 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19129 unwind
.opcode_count
++;
19133 /* Add unwind opcodes to adjust the stack pointer. */
19136 add_unwind_adjustsp (offsetT offset
)
19140 if (offset
> 0x200)
19142 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19147 /* Long form: 0xb2, uleb128. */
19148 /* This might not fit in a word so add the individual bytes,
19149 remembering the list is built in reverse order. */
19150 o
= (valueT
) ((offset
- 0x204) >> 2);
19152 add_unwind_opcode (0, 1);
19154 /* Calculate the uleb128 encoding of the offset. */
19158 bytes
[n
] = o
& 0x7f;
19164 /* Add the insn. */
19166 add_unwind_opcode (bytes
[n
- 1], 1);
19167 add_unwind_opcode (0xb2, 1);
19169 else if (offset
> 0x100)
19171 /* Two short opcodes. */
19172 add_unwind_opcode (0x3f, 1);
19173 op
= (offset
- 0x104) >> 2;
19174 add_unwind_opcode (op
, 1);
19176 else if (offset
> 0)
19178 /* Short opcode. */
19179 op
= (offset
- 4) >> 2;
19180 add_unwind_opcode (op
, 1);
19182 else if (offset
< 0)
19185 while (offset
> 0x100)
19187 add_unwind_opcode (0x7f, 1);
19190 op
= ((offset
- 4) >> 2) | 0x40;
19191 add_unwind_opcode (op
, 1);
19195 /* Finish the list of unwind opcodes for this function. */
19197 finish_unwind_opcodes (void)
19201 if (unwind
.fp_used
)
19203 /* Adjust sp as necessary. */
19204 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19205 flush_pending_unwind ();
19207 /* After restoring sp from the frame pointer. */
19208 op
= 0x90 | unwind
.fp_reg
;
19209 add_unwind_opcode (op
, 1);
19212 flush_pending_unwind ();
19216 /* Start an exception table entry. If idx is nonzero this is an index table
19220 start_unwind_section (const segT text_seg
, int idx
)
19222 const char * text_name
;
19223 const char * prefix
;
19224 const char * prefix_once
;
19225 const char * group_name
;
19229 size_t sec_name_len
;
19236 prefix
= ELF_STRING_ARM_unwind
;
19237 prefix_once
= ELF_STRING_ARM_unwind_once
;
19238 type
= SHT_ARM_EXIDX
;
19242 prefix
= ELF_STRING_ARM_unwind_info
;
19243 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19244 type
= SHT_PROGBITS
;
19247 text_name
= segment_name (text_seg
);
19248 if (streq (text_name
, ".text"))
19251 if (strncmp (text_name
, ".gnu.linkonce.t.",
19252 strlen (".gnu.linkonce.t.")) == 0)
19254 prefix
= prefix_once
;
19255 text_name
+= strlen (".gnu.linkonce.t.");
19258 prefix_len
= strlen (prefix
);
19259 text_len
= strlen (text_name
);
19260 sec_name_len
= prefix_len
+ text_len
;
19261 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19262 memcpy (sec_name
, prefix
, prefix_len
);
19263 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19264 sec_name
[prefix_len
+ text_len
] = '\0';
19270 /* Handle COMDAT group. */
19271 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19273 group_name
= elf_group_name (text_seg
);
19274 if (group_name
== NULL
)
19276 as_bad (_("Group section `%s' has no group signature"),
19277 segment_name (text_seg
));
19278 ignore_rest_of_line ();
19281 flags
|= SHF_GROUP
;
19285 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19287 /* Set the section link for index tables. */
19289 elf_linked_to_section (now_seg
) = text_seg
;
19293 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19294 personality routine data. Returns zero, or the index table value for
19295 and inline entry. */
19298 create_unwind_entry (int have_data
)
19303 /* The current word of data. */
19305 /* The number of bytes left in this word. */
19308 finish_unwind_opcodes ();
19310 /* Remember the current text section. */
19311 unwind
.saved_seg
= now_seg
;
19312 unwind
.saved_subseg
= now_subseg
;
19314 start_unwind_section (now_seg
, 0);
19316 if (unwind
.personality_routine
== NULL
)
19318 if (unwind
.personality_index
== -2)
19321 as_bad (_("handlerdata in cantunwind frame"));
19322 return 1; /* EXIDX_CANTUNWIND. */
19325 /* Use a default personality routine if none is specified. */
19326 if (unwind
.personality_index
== -1)
19328 if (unwind
.opcode_count
> 3)
19329 unwind
.personality_index
= 1;
19331 unwind
.personality_index
= 0;
19334 /* Space for the personality routine entry. */
19335 if (unwind
.personality_index
== 0)
19337 if (unwind
.opcode_count
> 3)
19338 as_bad (_("too many unwind opcodes for personality routine 0"));
19342 /* All the data is inline in the index table. */
19345 while (unwind
.opcode_count
> 0)
19347 unwind
.opcode_count
--;
19348 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19352 /* Pad with "finish" opcodes. */
19354 data
= (data
<< 8) | 0xb0;
19361 /* We get two opcodes "free" in the first word. */
19362 size
= unwind
.opcode_count
- 2;
19365 /* An extra byte is required for the opcode count. */
19366 size
= unwind
.opcode_count
+ 1;
19368 size
= (size
+ 3) >> 2;
19370 as_bad (_("too many unwind opcodes"));
19372 frag_align (2, 0, 0);
19373 record_alignment (now_seg
, 2);
19374 unwind
.table_entry
= expr_build_dot ();
19376 /* Allocate the table entry. */
19377 ptr
= frag_more ((size
<< 2) + 4);
19378 where
= frag_now_fix () - ((size
<< 2) + 4);
19380 switch (unwind
.personality_index
)
19383 /* ??? Should this be a PLT generating relocation? */
19384 /* Custom personality routine. */
19385 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19386 BFD_RELOC_ARM_PREL31
);
19391 /* Set the first byte to the number of additional words. */
19396 /* ABI defined personality routines. */
19398 /* Three opcodes bytes are packed into the first word. */
19405 /* The size and first two opcode bytes go in the first word. */
19406 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19411 /* Should never happen. */
19415 /* Pack the opcodes into words (MSB first), reversing the list at the same
19417 while (unwind
.opcode_count
> 0)
19421 md_number_to_chars (ptr
, data
, 4);
19426 unwind
.opcode_count
--;
19428 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19431 /* Finish off the last word. */
19434 /* Pad with "finish" opcodes. */
19436 data
= (data
<< 8) | 0xb0;
19438 md_number_to_chars (ptr
, data
, 4);
19443 /* Add an empty descriptor if there is no user-specified data. */
19444 ptr
= frag_more (4);
19445 md_number_to_chars (ptr
, 0, 4);
19452 /* Initialize the DWARF-2 unwind information for this procedure. */
19455 tc_arm_frame_initial_instructions (void)
19457 cfi_add_CFA_def_cfa (REG_SP
, 0);
19459 #endif /* OBJ_ELF */
19461 /* Convert REGNAME to a DWARF-2 register number. */
19464 tc_arm_regname_to_dw2regnum (char *regname
)
19466 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19476 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19480 exp
.X_op
= O_secrel
;
19481 exp
.X_add_symbol
= symbol
;
19482 exp
.X_add_number
= 0;
19483 emit_expr (&exp
, size
);
19487 /* MD interface: Symbol and relocation handling. */
19489 /* Return the address within the segment that a PC-relative fixup is
19490 relative to. For ARM, PC-relative fixups applied to instructions
19491 are generally relative to the location of the fixup plus 8 bytes.
19492 Thumb branches are offset by 4, and Thumb loads relative to PC
19493 require special handling. */
19496 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19498 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19500 /* If this is pc-relative and we are going to emit a relocation
19501 then we just want to put out any pipeline compensation that the linker
19502 will need. Otherwise we want to use the calculated base.
19503 For WinCE we skip the bias for externals as well, since this
19504 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19506 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19507 || (arm_force_relocation (fixP
)
19509 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19515 switch (fixP
->fx_r_type
)
19517 /* PC relative addressing on the Thumb is slightly odd as the
19518 bottom two bits of the PC are forced to zero for the
19519 calculation. This happens *after* application of the
19520 pipeline offset. However, Thumb adrl already adjusts for
19521 this, so we need not do it again. */
19522 case BFD_RELOC_ARM_THUMB_ADD
:
19525 case BFD_RELOC_ARM_THUMB_OFFSET
:
19526 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19527 case BFD_RELOC_ARM_T32_ADD_PC12
:
19528 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19529 return (base
+ 4) & ~3;
19531 /* Thumb branches are simply offset by +4. */
19532 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19533 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19534 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19535 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19536 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19539 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19541 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19542 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19543 && ARM_IS_FUNC (fixP
->fx_addsy
)
19544 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19545 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19548 /* BLX is like branches above, but forces the low two bits of PC to
19550 case BFD_RELOC_THUMB_PCREL_BLX
:
19552 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19553 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19554 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19555 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19556 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19557 return (base
+ 4) & ~3;
19559 /* ARM mode branches are offset by +8. However, the Windows CE
19560 loader expects the relocation not to take this into account. */
19561 case BFD_RELOC_ARM_PCREL_BLX
:
19563 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19564 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19565 && ARM_IS_FUNC (fixP
->fx_addsy
)
19566 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19567 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19570 case BFD_RELOC_ARM_PCREL_CALL
:
19572 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19573 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19574 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19575 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19576 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19579 case BFD_RELOC_ARM_PCREL_BRANCH
:
19580 case BFD_RELOC_ARM_PCREL_JUMP
:
19581 case BFD_RELOC_ARM_PLT32
:
19583 /* When handling fixups immediately, because we have already
19584 discovered the value of a symbol, or the address of the frag involved
19585 we must account for the offset by +8, as the OS loader will never see the reloc.
19586 see fixup_segment() in write.c
19587 The S_IS_EXTERNAL test handles the case of global symbols.
19588 Those need the calculated base, not just the pipe compensation the linker will need. */
19590 && fixP
->fx_addsy
!= NULL
19591 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19592 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19600 /* ARM mode loads relative to PC are also offset by +8. Unlike
19601 branches, the Windows CE loader *does* expect the relocation
19602 to take this into account. */
19603 case BFD_RELOC_ARM_OFFSET_IMM
:
19604 case BFD_RELOC_ARM_OFFSET_IMM8
:
19605 case BFD_RELOC_ARM_HWLITERAL
:
19606 case BFD_RELOC_ARM_LITERAL
:
19607 case BFD_RELOC_ARM_CP_OFF_IMM
:
19611 /* Other PC-relative relocations are un-offset. */
19617 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19618 Otherwise we have no need to default values of symbols. */
19621 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19624 if (name
[0] == '_' && name
[1] == 'G'
19625 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19629 if (symbol_find (name
))
19630 as_bad (_("GOT already in the symbol table"));
19632 GOT_symbol
= symbol_new (name
, undefined_section
,
19633 (valueT
) 0, & zero_address_frag
);
19643 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19644 computed as two separate immediate values, added together. We
19645 already know that this value cannot be computed by just one ARM
19648 static unsigned int
19649 validate_immediate_twopart (unsigned int val
,
19650 unsigned int * highpart
)
19655 for (i
= 0; i
< 32; i
+= 2)
19656 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19662 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19664 else if (a
& 0xff0000)
19666 if (a
& 0xff000000)
19668 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19672 gas_assert (a
& 0xff000000);
19673 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19676 return (a
& 0xff) | (i
<< 7);
19683 validate_offset_imm (unsigned int val
, int hwse
)
19685 if ((hwse
&& val
> 255) || val
> 4095)
19690 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19691 negative immediate constant by altering the instruction. A bit of
19696 by inverting the second operand, and
19699 by negating the second operand. */
19702 negate_data_op (unsigned long * instruction
,
19703 unsigned long value
)
19706 unsigned long negated
, inverted
;
19708 negated
= encode_arm_immediate (-value
);
19709 inverted
= encode_arm_immediate (~value
);
19711 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19714 /* First negates. */
19715 case OPCODE_SUB
: /* ADD <-> SUB */
19716 new_inst
= OPCODE_ADD
;
19721 new_inst
= OPCODE_SUB
;
19725 case OPCODE_CMP
: /* CMP <-> CMN */
19726 new_inst
= OPCODE_CMN
;
19731 new_inst
= OPCODE_CMP
;
19735 /* Now Inverted ops. */
19736 case OPCODE_MOV
: /* MOV <-> MVN */
19737 new_inst
= OPCODE_MVN
;
19742 new_inst
= OPCODE_MOV
;
19746 case OPCODE_AND
: /* AND <-> BIC */
19747 new_inst
= OPCODE_BIC
;
19752 new_inst
= OPCODE_AND
;
19756 case OPCODE_ADC
: /* ADC <-> SBC */
19757 new_inst
= OPCODE_SBC
;
19762 new_inst
= OPCODE_ADC
;
19766 /* We cannot do anything. */
19771 if (value
== (unsigned) FAIL
)
19774 *instruction
&= OPCODE_MASK
;
19775 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19779 /* Like negate_data_op, but for Thumb-2. */
19781 static unsigned int
19782 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19786 unsigned int negated
, inverted
;
19788 negated
= encode_thumb32_immediate (-value
);
19789 inverted
= encode_thumb32_immediate (~value
);
19791 rd
= (*instruction
>> 8) & 0xf;
19792 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19795 /* ADD <-> SUB. Includes CMP <-> CMN. */
19796 case T2_OPCODE_SUB
:
19797 new_inst
= T2_OPCODE_ADD
;
19801 case T2_OPCODE_ADD
:
19802 new_inst
= T2_OPCODE_SUB
;
19806 /* ORR <-> ORN. Includes MOV <-> MVN. */
19807 case T2_OPCODE_ORR
:
19808 new_inst
= T2_OPCODE_ORN
;
19812 case T2_OPCODE_ORN
:
19813 new_inst
= T2_OPCODE_ORR
;
19817 /* AND <-> BIC. TST has no inverted equivalent. */
19818 case T2_OPCODE_AND
:
19819 new_inst
= T2_OPCODE_BIC
;
19826 case T2_OPCODE_BIC
:
19827 new_inst
= T2_OPCODE_AND
;
19832 case T2_OPCODE_ADC
:
19833 new_inst
= T2_OPCODE_SBC
;
19837 case T2_OPCODE_SBC
:
19838 new_inst
= T2_OPCODE_ADC
;
19842 /* We cannot do anything. */
19847 if (value
== (unsigned int)FAIL
)
19850 *instruction
&= T2_OPCODE_MASK
;
19851 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19855 /* Read a 32-bit thumb instruction from buf. */
19856 static unsigned long
19857 get_thumb32_insn (char * buf
)
19859 unsigned long insn
;
19860 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19861 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19867 /* We usually want to set the low bit on the address of thumb function
19868 symbols. In particular .word foo - . should have the low bit set.
19869 Generic code tries to fold the difference of two symbols to
19870 a constant. Prevent this and force a relocation when the first symbols
19871 is a thumb function. */
19874 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19876 if (op
== O_subtract
19877 && l
->X_op
== O_symbol
19878 && r
->X_op
== O_symbol
19879 && THUMB_IS_FUNC (l
->X_add_symbol
))
19881 l
->X_op
= O_subtract
;
19882 l
->X_op_symbol
= r
->X_add_symbol
;
19883 l
->X_add_number
-= r
->X_add_number
;
19887 /* Process as normal. */
19891 /* Encode Thumb2 unconditional branches and calls. The encoding
19892 for the 2 are identical for the immediate values. */
19895 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
19897 #define T2I1I2MASK ((1 << 13) | (1 << 11))
19900 addressT S
, I1
, I2
, lo
, hi
;
19902 S
= (value
>> 24) & 0x01;
19903 I1
= (value
>> 23) & 0x01;
19904 I2
= (value
>> 22) & 0x01;
19905 hi
= (value
>> 12) & 0x3ff;
19906 lo
= (value
>> 1) & 0x7ff;
19907 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19908 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19909 newval
|= (S
<< 10) | hi
;
19910 newval2
&= ~T2I1I2MASK
;
19911 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
19912 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19913 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19917 md_apply_fix (fixS
* fixP
,
19921 offsetT value
= * valP
;
19923 unsigned int newimm
;
19924 unsigned long temp
;
19926 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19928 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19930 /* Note whether this will delete the relocation. */
19932 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19935 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19936 consistency with the behaviour on 32-bit hosts. Remember value
19938 value
&= 0xffffffff;
19939 value
^= 0x80000000;
19940 value
-= 0x80000000;
19943 fixP
->fx_addnumber
= value
;
19945 /* Same treatment for fixP->fx_offset. */
19946 fixP
->fx_offset
&= 0xffffffff;
19947 fixP
->fx_offset
^= 0x80000000;
19948 fixP
->fx_offset
-= 0x80000000;
19950 switch (fixP
->fx_r_type
)
19952 case BFD_RELOC_NONE
:
19953 /* This will need to go in the object file. */
19957 case BFD_RELOC_ARM_IMMEDIATE
:
19958 /* We claim that this fixup has been processed here,
19959 even if in fact we generate an error because we do
19960 not have a reloc for it, so tc_gen_reloc will reject it. */
19963 if (fixP
->fx_addsy
)
19965 const char *msg
= 0;
19967 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19968 msg
= _("undefined symbol %s used as an immediate value");
19969 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19970 msg
= _("symbol %s is in a different section");
19971 else if (S_IS_WEAK (fixP
->fx_addsy
))
19972 msg
= _("symbol %s is weak and may be overridden later");
19976 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19977 msg
, S_GET_NAME (fixP
->fx_addsy
));
19982 newimm
= encode_arm_immediate (value
);
19983 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19985 /* If the instruction will fail, see if we can fix things up by
19986 changing the opcode. */
19987 if (newimm
== (unsigned int) FAIL
19988 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19990 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19991 _("invalid constant (%lx) after fixup"),
19992 (unsigned long) value
);
19996 newimm
|= (temp
& 0xfffff000);
19997 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20000 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20002 unsigned int highpart
= 0;
20003 unsigned int newinsn
= 0xe1a00000; /* nop. */
20005 if (fixP
->fx_addsy
)
20007 const char *msg
= 0;
20009 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20010 msg
= _("undefined symbol %s used as an immediate value");
20011 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20012 msg
= _("symbol %s is in a different section");
20013 else if (S_IS_WEAK (fixP
->fx_addsy
))
20014 msg
= _("symbol %s is weak and may be overridden later");
20018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20019 msg
, S_GET_NAME (fixP
->fx_addsy
));
20024 newimm
= encode_arm_immediate (value
);
20025 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20027 /* If the instruction will fail, see if we can fix things up by
20028 changing the opcode. */
20029 if (newimm
== (unsigned int) FAIL
20030 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20032 /* No ? OK - try using two ADD instructions to generate
20034 newimm
= validate_immediate_twopart (value
, & highpart
);
20036 /* Yes - then make sure that the second instruction is
20038 if (newimm
!= (unsigned int) FAIL
)
20040 /* Still No ? Try using a negated value. */
20041 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20042 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20043 /* Otherwise - give up. */
20046 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20047 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20052 /* Replace the first operand in the 2nd instruction (which
20053 is the PC) with the destination register. We have
20054 already added in the PC in the first instruction and we
20055 do not want to do it again. */
20056 newinsn
&= ~ 0xf0000;
20057 newinsn
|= ((newinsn
& 0x0f000) << 4);
20060 newimm
|= (temp
& 0xfffff000);
20061 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20063 highpart
|= (newinsn
& 0xfffff000);
20064 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20068 case BFD_RELOC_ARM_OFFSET_IMM
:
20069 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20072 case BFD_RELOC_ARM_LITERAL
:
20078 if (validate_offset_imm (value
, 0) == FAIL
)
20080 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20081 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20082 _("invalid literal constant: pool needs to be closer"));
20084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20085 _("bad immediate value for offset (%ld)"),
20090 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20091 newval
&= 0xff7ff000;
20092 newval
|= value
| (sign
? INDEX_UP
: 0);
20093 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20096 case BFD_RELOC_ARM_OFFSET_IMM8
:
20097 case BFD_RELOC_ARM_HWLITERAL
:
20103 if (validate_offset_imm (value
, 1) == FAIL
)
20105 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20107 _("invalid literal constant: pool needs to be closer"));
20109 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20114 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20115 newval
&= 0xff7ff0f0;
20116 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20117 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20120 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20121 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20122 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20123 _("bad immediate value for offset (%ld)"), (long) value
);
20126 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20128 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20131 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20132 /* This is a complicated relocation used for all varieties of Thumb32
20133 load/store instruction with immediate offset:
20135 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20136 *4, optional writeback(W)
20137 (doubleword load/store)
20139 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20140 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20141 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20142 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20143 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20145 Uppercase letters indicate bits that are already encoded at
20146 this point. Lowercase letters are our problem. For the
20147 second block of instructions, the secondary opcode nybble
20148 (bits 8..11) is present, and bit 23 is zero, even if this is
20149 a PC-relative operation. */
20150 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20152 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20154 if ((newval
& 0xf0000000) == 0xe0000000)
20156 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20158 newval
|= (1 << 23);
20161 if (value
% 4 != 0)
20163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20164 _("offset not a multiple of 4"));
20170 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20171 _("offset out of range"));
20176 else if ((newval
& 0x000f0000) == 0x000f0000)
20178 /* PC-relative, 12-bit offset. */
20180 newval
|= (1 << 23);
20185 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20186 _("offset out of range"));
20191 else if ((newval
& 0x00000100) == 0x00000100)
20193 /* Writeback: 8-bit, +/- offset. */
20195 newval
|= (1 << 9);
20200 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20201 _("offset out of range"));
20206 else if ((newval
& 0x00000f00) == 0x00000e00)
20208 /* T-instruction: positive 8-bit offset. */
20209 if (value
< 0 || value
> 0xff)
20211 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20212 _("offset out of range"));
20220 /* Positive 12-bit or negative 8-bit offset. */
20224 newval
|= (1 << 23);
20234 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20235 _("offset out of range"));
20242 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20243 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20246 case BFD_RELOC_ARM_SHIFT_IMM
:
20247 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20248 if (((unsigned long) value
) > 32
20250 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20252 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20253 _("shift expression is too large"));
20258 /* Shifts of zero must be done as lsl. */
20260 else if (value
== 32)
20262 newval
&= 0xfffff07f;
20263 newval
|= (value
& 0x1f) << 7;
20264 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20267 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20268 case BFD_RELOC_ARM_T32_ADD_IMM
:
20269 case BFD_RELOC_ARM_T32_IMM12
:
20270 case BFD_RELOC_ARM_T32_ADD_PC12
:
20271 /* We claim that this fixup has been processed here,
20272 even if in fact we generate an error because we do
20273 not have a reloc for it, so tc_gen_reloc will reject it. */
20277 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20280 _("undefined symbol %s used as an immediate value"),
20281 S_GET_NAME (fixP
->fx_addsy
));
20285 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20287 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20290 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20291 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20293 newimm
= encode_thumb32_immediate (value
);
20294 if (newimm
== (unsigned int) FAIL
)
20295 newimm
= thumb32_negate_data_op (&newval
, value
);
20297 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20298 && newimm
== (unsigned int) FAIL
)
20300 /* Turn add/sum into addw/subw. */
20301 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20302 newval
= (newval
& 0xfeffffff) | 0x02000000;
20303 /* No flat 12-bit imm encoding for addsw/subsw. */
20304 if ((newval
& 0x00100000) == 0)
20306 /* 12 bit immediate for addw/subw. */
20310 newval
^= 0x00a00000;
20313 newimm
= (unsigned int) FAIL
;
20319 if (newimm
== (unsigned int)FAIL
)
20321 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20322 _("invalid constant (%lx) after fixup"),
20323 (unsigned long) value
);
20327 newval
|= (newimm
& 0x800) << 15;
20328 newval
|= (newimm
& 0x700) << 4;
20329 newval
|= (newimm
& 0x0ff);
20331 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20332 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20335 case BFD_RELOC_ARM_SMC
:
20336 if (((unsigned long) value
) > 0xffff)
20337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20338 _("invalid smc expression"));
20339 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20340 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20341 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20344 case BFD_RELOC_ARM_SWI
:
20345 if (fixP
->tc_fix_data
!= 0)
20347 if (((unsigned long) value
) > 0xff)
20348 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20349 _("invalid swi expression"));
20350 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20352 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20356 if (((unsigned long) value
) > 0x00ffffff)
20357 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20358 _("invalid swi expression"));
20359 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20361 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20365 case BFD_RELOC_ARM_MULTI
:
20366 if (((unsigned long) value
) > 0xffff)
20367 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20368 _("invalid expression in load/store multiple"));
20369 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20370 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20374 case BFD_RELOC_ARM_PCREL_CALL
:
20376 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20378 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20379 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20380 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20381 /* Flip the bl to blx. This is a simple flip
20382 bit here because we generate PCREL_CALL for
20383 unconditional bls. */
20385 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20386 newval
= newval
| 0x10000000;
20387 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20393 goto arm_branch_common
;
20395 case BFD_RELOC_ARM_PCREL_JUMP
:
20396 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20398 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20399 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20400 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20402 /* This would map to a bl<cond>, b<cond>,
20403 b<always> to a Thumb function. We
20404 need to force a relocation for this particular
20406 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20410 case BFD_RELOC_ARM_PLT32
:
20412 case BFD_RELOC_ARM_PCREL_BRANCH
:
20414 goto arm_branch_common
;
20416 case BFD_RELOC_ARM_PCREL_BLX
:
20419 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20421 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20422 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20423 && ARM_IS_FUNC (fixP
->fx_addsy
))
20425 /* Flip the blx to a bl and warn. */
20426 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20427 newval
= 0xeb000000;
20428 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20429 _("blx to '%s' an ARM ISA state function changed to bl"),
20431 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20437 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20438 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20442 /* We are going to store value (shifted right by two) in the
20443 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20444 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20445 also be be clear. */
20447 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20448 _("misaligned branch destination"));
20449 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20450 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20452 _("branch out of range"));
20454 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20456 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20457 newval
|= (value
>> 2) & 0x00ffffff;
20458 /* Set the H bit on BLX instructions. */
20462 newval
|= 0x01000000;
20464 newval
&= ~0x01000000;
20466 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20470 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20471 /* CBZ can only branch forward. */
20473 /* Attempts to use CBZ to branch to the next instruction
20474 (which, strictly speaking, are prohibited) will be turned into
20477 FIXME: It may be better to remove the instruction completely and
20478 perform relaxation. */
20481 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20482 newval
= 0xbf00; /* NOP encoding T1 */
20483 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20488 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20489 _("branch out of range"));
20491 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20493 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20494 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20495 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20500 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20501 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20503 _("branch out of range"));
20505 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20507 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20508 newval
|= (value
& 0x1ff) >> 1;
20509 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20513 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20514 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20515 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20516 _("branch out of range"));
20518 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20520 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20521 newval
|= (value
& 0xfff) >> 1;
20522 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20526 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20528 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20529 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20530 && S_IS_DEFINED (fixP
->fx_addsy
)
20531 && ARM_IS_FUNC (fixP
->fx_addsy
)
20532 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20534 /* Force a relocation for a branch 20 bits wide. */
20537 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20539 _("conditional branch out of range"));
20541 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20544 addressT S
, J1
, J2
, lo
, hi
;
20546 S
= (value
& 0x00100000) >> 20;
20547 J2
= (value
& 0x00080000) >> 19;
20548 J1
= (value
& 0x00040000) >> 18;
20549 hi
= (value
& 0x0003f000) >> 12;
20550 lo
= (value
& 0x00000ffe) >> 1;
20552 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20553 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20554 newval
|= (S
<< 10) | hi
;
20555 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20556 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20557 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20561 case BFD_RELOC_THUMB_PCREL_BLX
:
20563 /* If there is a blx from a thumb state function to
20564 another thumb function flip this to a bl and warn
20568 && S_IS_DEFINED (fixP
->fx_addsy
)
20569 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20570 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20571 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20573 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20574 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20575 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20577 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20578 newval
= newval
| 0x1000;
20579 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20580 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20585 goto thumb_bl_common
;
20587 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20589 /* A bl from Thumb state ISA to an internal ARM state function
20590 is converted to a blx. */
20592 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20593 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20594 && S_IS_DEFINED (fixP
->fx_addsy
)
20595 && ARM_IS_FUNC (fixP
->fx_addsy
)
20596 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20598 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20599 newval
= newval
& ~0x1000;
20600 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20601 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20608 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20609 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20610 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20613 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20614 /* For a BLX instruction, make sure that the relocation is rounded up
20615 to a word boundary. This follows the semantics of the instruction
20616 which specifies that bit 1 of the target address will come from bit
20617 1 of the base address. */
20618 value
= (value
+ 1) & ~ 1;
20621 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20623 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20625 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20626 _("branch out of range"));
20628 else if ((value
& ~0x1ffffff)
20629 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20632 _("Thumb2 branch out of range"));
20636 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20637 encode_thumb2_b_bl_offset (buf
, value
);
20641 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20642 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20644 _("branch out of range"));
20646 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20647 encode_thumb2_b_bl_offset (buf
, value
);
20652 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20653 md_number_to_chars (buf
, value
, 1);
20657 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20658 md_number_to_chars (buf
, value
, 2);
20662 case BFD_RELOC_ARM_TLS_GD32
:
20663 case BFD_RELOC_ARM_TLS_LE32
:
20664 case BFD_RELOC_ARM_TLS_IE32
:
20665 case BFD_RELOC_ARM_TLS_LDM32
:
20666 case BFD_RELOC_ARM_TLS_LDO32
:
20667 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20670 case BFD_RELOC_ARM_GOT32
:
20671 case BFD_RELOC_ARM_GOTOFF
:
20672 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20673 md_number_to_chars (buf
, 0, 4);
20676 case BFD_RELOC_ARM_GOT_PREL
:
20677 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20678 md_number_to_chars (buf
, value
, 4);
20681 case BFD_RELOC_ARM_TARGET2
:
20682 /* TARGET2 is not partial-inplace, so we need to write the
20683 addend here for REL targets, because it won't be written out
20684 during reloc processing later. */
20685 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20686 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20690 case BFD_RELOC_RVA
:
20692 case BFD_RELOC_ARM_TARGET1
:
20693 case BFD_RELOC_ARM_ROSEGREL32
:
20694 case BFD_RELOC_ARM_SBREL32
:
20695 case BFD_RELOC_32_PCREL
:
20697 case BFD_RELOC_32_SECREL
:
20699 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20701 /* For WinCE we only do this for pcrel fixups. */
20702 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20704 md_number_to_chars (buf
, value
, 4);
20708 case BFD_RELOC_ARM_PREL31
:
20709 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20711 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20712 if ((value
^ (value
>> 1)) & 0x40000000)
20714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20715 _("rel31 relocation overflow"));
20717 newval
|= value
& 0x7fffffff;
20718 md_number_to_chars (buf
, newval
, 4);
20723 case BFD_RELOC_ARM_CP_OFF_IMM
:
20724 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20725 if (value
< -1023 || value
> 1023 || (value
& 3))
20726 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20727 _("co-processor offset out of range"));
20732 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20733 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20734 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20736 newval
= get_thumb32_insn (buf
);
20737 newval
&= 0xff7fff00;
20738 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20739 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20740 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20741 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20743 put_thumb32_insn (buf
, newval
);
20746 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20747 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20748 if (value
< -255 || value
> 255)
20749 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20750 _("co-processor offset out of range"));
20752 goto cp_off_common
;
20754 case BFD_RELOC_ARM_THUMB_OFFSET
:
20755 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20756 /* Exactly what ranges, and where the offset is inserted depends
20757 on the type of instruction, we can establish this from the
20759 switch (newval
>> 12)
20761 case 4: /* PC load. */
20762 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20763 forced to zero for these loads; md_pcrel_from has already
20764 compensated for this. */
20766 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20767 _("invalid offset, target not word aligned (0x%08lX)"),
20768 (((unsigned long) fixP
->fx_frag
->fr_address
20769 + (unsigned long) fixP
->fx_where
) & ~3)
20770 + (unsigned long) value
);
20772 if (value
& ~0x3fc)
20773 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20774 _("invalid offset, value too big (0x%08lX)"),
20777 newval
|= value
>> 2;
20780 case 9: /* SP load/store. */
20781 if (value
& ~0x3fc)
20782 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20783 _("invalid offset, value too big (0x%08lX)"),
20785 newval
|= value
>> 2;
20788 case 6: /* Word load/store. */
20790 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20791 _("invalid offset, value too big (0x%08lX)"),
20793 newval
|= value
<< 4; /* 6 - 2. */
20796 case 7: /* Byte load/store. */
20798 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20799 _("invalid offset, value too big (0x%08lX)"),
20801 newval
|= value
<< 6;
20804 case 8: /* Halfword load/store. */
20806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20807 _("invalid offset, value too big (0x%08lX)"),
20809 newval
|= value
<< 5; /* 6 - 1. */
20813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20814 "Unable to process relocation for thumb opcode: %lx",
20815 (unsigned long) newval
);
20818 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20821 case BFD_RELOC_ARM_THUMB_ADD
:
20822 /* This is a complicated relocation, since we use it for all of
20823 the following immediate relocations:
20827 9bit ADD/SUB SP word-aligned
20828 10bit ADD PC/SP word-aligned
20830 The type of instruction being processed is encoded in the
20837 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20839 int rd
= (newval
>> 4) & 0xf;
20840 int rs
= newval
& 0xf;
20841 int subtract
= !!(newval
& 0x8000);
20843 /* Check for HI regs, only very restricted cases allowed:
20844 Adjusting SP, and using PC or SP to get an address. */
20845 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20846 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20847 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20848 _("invalid Hi register with immediate"));
20850 /* If value is negative, choose the opposite instruction. */
20854 subtract
= !subtract
;
20856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20857 _("immediate value out of range"));
20862 if (value
& ~0x1fc)
20863 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20864 _("invalid immediate for stack address calculation"));
20865 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20866 newval
|= value
>> 2;
20868 else if (rs
== REG_PC
|| rs
== REG_SP
)
20870 if (subtract
|| value
& ~0x3fc)
20871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20872 _("invalid immediate for address calculation (value = 0x%08lX)"),
20873 (unsigned long) value
);
20874 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20876 newval
|= value
>> 2;
20881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20882 _("immediate value out of range"));
20883 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20884 newval
|= (rd
<< 8) | value
;
20889 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20890 _("immediate value out of range"));
20891 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20892 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20895 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20898 case BFD_RELOC_ARM_THUMB_IMM
:
20899 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20900 if (value
< 0 || value
> 255)
20901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20902 _("invalid immediate: %ld is out of range"),
20905 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20908 case BFD_RELOC_ARM_THUMB_SHIFT
:
20909 /* 5bit shift value (0..32). LSL cannot take 32. */
20910 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20911 temp
= newval
& 0xf800;
20912 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20913 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20914 _("invalid shift value: %ld"), (long) value
);
20915 /* Shifts of zero must be encoded as LSL. */
20917 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20918 /* Shifts of 32 are encoded as zero. */
20919 else if (value
== 32)
20921 newval
|= value
<< 6;
20922 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20925 case BFD_RELOC_VTABLE_INHERIT
:
20926 case BFD_RELOC_VTABLE_ENTRY
:
20930 case BFD_RELOC_ARM_MOVW
:
20931 case BFD_RELOC_ARM_MOVT
:
20932 case BFD_RELOC_ARM_THUMB_MOVW
:
20933 case BFD_RELOC_ARM_THUMB_MOVT
:
20934 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20936 /* REL format relocations are limited to a 16-bit addend. */
20937 if (!fixP
->fx_done
)
20939 if (value
< -0x8000 || value
> 0x7fff)
20940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20941 _("offset out of range"));
20943 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20944 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20949 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20950 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20952 newval
= get_thumb32_insn (buf
);
20953 newval
&= 0xfbf08f00;
20954 newval
|= (value
& 0xf000) << 4;
20955 newval
|= (value
& 0x0800) << 15;
20956 newval
|= (value
& 0x0700) << 4;
20957 newval
|= (value
& 0x00ff);
20958 put_thumb32_insn (buf
, newval
);
20962 newval
= md_chars_to_number (buf
, 4);
20963 newval
&= 0xfff0f000;
20964 newval
|= value
& 0x0fff;
20965 newval
|= (value
& 0xf000) << 4;
20966 md_number_to_chars (buf
, newval
, 4);
20971 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20972 case BFD_RELOC_ARM_ALU_PC_G0
:
20973 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20974 case BFD_RELOC_ARM_ALU_PC_G1
:
20975 case BFD_RELOC_ARM_ALU_PC_G2
:
20976 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20977 case BFD_RELOC_ARM_ALU_SB_G0
:
20978 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20979 case BFD_RELOC_ARM_ALU_SB_G1
:
20980 case BFD_RELOC_ARM_ALU_SB_G2
:
20981 gas_assert (!fixP
->fx_done
);
20982 if (!seg
->use_rela_p
)
20985 bfd_vma encoded_addend
;
20986 bfd_vma addend_abs
= abs (value
);
20988 /* Check that the absolute value of the addend can be
20989 expressed as an 8-bit constant plus a rotation. */
20990 encoded_addend
= encode_arm_immediate (addend_abs
);
20991 if (encoded_addend
== (unsigned int) FAIL
)
20992 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20993 _("the offset 0x%08lX is not representable"),
20994 (unsigned long) addend_abs
);
20996 /* Extract the instruction. */
20997 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20999 /* If the addend is positive, use an ADD instruction.
21000 Otherwise use a SUB. Take care not to destroy the S bit. */
21001 insn
&= 0xff1fffff;
21007 /* Place the encoded addend into the first 12 bits of the
21009 insn
&= 0xfffff000;
21010 insn
|= encoded_addend
;
21012 /* Update the instruction. */
21013 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21017 case BFD_RELOC_ARM_LDR_PC_G0
:
21018 case BFD_RELOC_ARM_LDR_PC_G1
:
21019 case BFD_RELOC_ARM_LDR_PC_G2
:
21020 case BFD_RELOC_ARM_LDR_SB_G0
:
21021 case BFD_RELOC_ARM_LDR_SB_G1
:
21022 case BFD_RELOC_ARM_LDR_SB_G2
:
21023 gas_assert (!fixP
->fx_done
);
21024 if (!seg
->use_rela_p
)
21027 bfd_vma addend_abs
= abs (value
);
21029 /* Check that the absolute value of the addend can be
21030 encoded in 12 bits. */
21031 if (addend_abs
>= 0x1000)
21032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21033 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21034 (unsigned long) addend_abs
);
21036 /* Extract the instruction. */
21037 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21039 /* If the addend is negative, clear bit 23 of the instruction.
21040 Otherwise set it. */
21042 insn
&= ~(1 << 23);
21046 /* Place the absolute value of the addend into the first 12 bits
21047 of the instruction. */
21048 insn
&= 0xfffff000;
21049 insn
|= addend_abs
;
21051 /* Update the instruction. */
21052 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21056 case BFD_RELOC_ARM_LDRS_PC_G0
:
21057 case BFD_RELOC_ARM_LDRS_PC_G1
:
21058 case BFD_RELOC_ARM_LDRS_PC_G2
:
21059 case BFD_RELOC_ARM_LDRS_SB_G0
:
21060 case BFD_RELOC_ARM_LDRS_SB_G1
:
21061 case BFD_RELOC_ARM_LDRS_SB_G2
:
21062 gas_assert (!fixP
->fx_done
);
21063 if (!seg
->use_rela_p
)
21066 bfd_vma addend_abs
= abs (value
);
21068 /* Check that the absolute value of the addend can be
21069 encoded in 8 bits. */
21070 if (addend_abs
>= 0x100)
21071 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21072 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21073 (unsigned long) addend_abs
);
21075 /* Extract the instruction. */
21076 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21078 /* If the addend is negative, clear bit 23 of the instruction.
21079 Otherwise set it. */
21081 insn
&= ~(1 << 23);
21085 /* Place the first four bits of the absolute value of the addend
21086 into the first 4 bits of the instruction, and the remaining
21087 four into bits 8 .. 11. */
21088 insn
&= 0xfffff0f0;
21089 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21091 /* Update the instruction. */
21092 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21096 case BFD_RELOC_ARM_LDC_PC_G0
:
21097 case BFD_RELOC_ARM_LDC_PC_G1
:
21098 case BFD_RELOC_ARM_LDC_PC_G2
:
21099 case BFD_RELOC_ARM_LDC_SB_G0
:
21100 case BFD_RELOC_ARM_LDC_SB_G1
:
21101 case BFD_RELOC_ARM_LDC_SB_G2
:
21102 gas_assert (!fixP
->fx_done
);
21103 if (!seg
->use_rela_p
)
21106 bfd_vma addend_abs
= abs (value
);
21108 /* Check that the absolute value of the addend is a multiple of
21109 four and, when divided by four, fits in 8 bits. */
21110 if (addend_abs
& 0x3)
21111 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21112 _("bad offset 0x%08lX (must be word-aligned)"),
21113 (unsigned long) addend_abs
);
21115 if ((addend_abs
>> 2) > 0xff)
21116 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21117 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21118 (unsigned long) addend_abs
);
21120 /* Extract the instruction. */
21121 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21123 /* If the addend is negative, clear bit 23 of the instruction.
21124 Otherwise set it. */
21126 insn
&= ~(1 << 23);
21130 /* Place the addend (divided by four) into the first eight
21131 bits of the instruction. */
21132 insn
&= 0xfffffff0;
21133 insn
|= addend_abs
>> 2;
21135 /* Update the instruction. */
21136 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21140 case BFD_RELOC_ARM_V4BX
:
21141 /* This will need to go in the object file. */
21145 case BFD_RELOC_UNUSED
:
21147 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21148 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21152 /* Translate internal representation of relocation info to BFD target
21156 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21159 bfd_reloc_code_real_type code
;
21161 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21163 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21164 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21165 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21167 if (fixp
->fx_pcrel
)
21169 if (section
->use_rela_p
)
21170 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21172 fixp
->fx_offset
= reloc
->address
;
21174 reloc
->addend
= fixp
->fx_offset
;
21176 switch (fixp
->fx_r_type
)
21179 if (fixp
->fx_pcrel
)
21181 code
= BFD_RELOC_8_PCREL
;
21186 if (fixp
->fx_pcrel
)
21188 code
= BFD_RELOC_16_PCREL
;
21193 if (fixp
->fx_pcrel
)
21195 code
= BFD_RELOC_32_PCREL
;
21199 case BFD_RELOC_ARM_MOVW
:
21200 if (fixp
->fx_pcrel
)
21202 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21206 case BFD_RELOC_ARM_MOVT
:
21207 if (fixp
->fx_pcrel
)
21209 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21213 case BFD_RELOC_ARM_THUMB_MOVW
:
21214 if (fixp
->fx_pcrel
)
21216 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21220 case BFD_RELOC_ARM_THUMB_MOVT
:
21221 if (fixp
->fx_pcrel
)
21223 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21227 case BFD_RELOC_NONE
:
21228 case BFD_RELOC_ARM_PCREL_BRANCH
:
21229 case BFD_RELOC_ARM_PCREL_BLX
:
21230 case BFD_RELOC_RVA
:
21231 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21232 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21233 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21234 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21235 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21236 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21237 case BFD_RELOC_VTABLE_ENTRY
:
21238 case BFD_RELOC_VTABLE_INHERIT
:
21240 case BFD_RELOC_32_SECREL
:
21242 code
= fixp
->fx_r_type
;
21245 case BFD_RELOC_THUMB_PCREL_BLX
:
21247 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21248 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21251 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21254 case BFD_RELOC_ARM_LITERAL
:
21255 case BFD_RELOC_ARM_HWLITERAL
:
21256 /* If this is called then the a literal has
21257 been referenced across a section boundary. */
21258 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21259 _("literal referenced across section boundary"));
21263 case BFD_RELOC_ARM_GOT32
:
21264 case BFD_RELOC_ARM_GOTOFF
:
21265 case BFD_RELOC_ARM_GOT_PREL
:
21266 case BFD_RELOC_ARM_PLT32
:
21267 case BFD_RELOC_ARM_TARGET1
:
21268 case BFD_RELOC_ARM_ROSEGREL32
:
21269 case BFD_RELOC_ARM_SBREL32
:
21270 case BFD_RELOC_ARM_PREL31
:
21271 case BFD_RELOC_ARM_TARGET2
:
21272 case BFD_RELOC_ARM_TLS_LE32
:
21273 case BFD_RELOC_ARM_TLS_LDO32
:
21274 case BFD_RELOC_ARM_PCREL_CALL
:
21275 case BFD_RELOC_ARM_PCREL_JUMP
:
21276 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21277 case BFD_RELOC_ARM_ALU_PC_G0
:
21278 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21279 case BFD_RELOC_ARM_ALU_PC_G1
:
21280 case BFD_RELOC_ARM_ALU_PC_G2
:
21281 case BFD_RELOC_ARM_LDR_PC_G0
:
21282 case BFD_RELOC_ARM_LDR_PC_G1
:
21283 case BFD_RELOC_ARM_LDR_PC_G2
:
21284 case BFD_RELOC_ARM_LDRS_PC_G0
:
21285 case BFD_RELOC_ARM_LDRS_PC_G1
:
21286 case BFD_RELOC_ARM_LDRS_PC_G2
:
21287 case BFD_RELOC_ARM_LDC_PC_G0
:
21288 case BFD_RELOC_ARM_LDC_PC_G1
:
21289 case BFD_RELOC_ARM_LDC_PC_G2
:
21290 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21291 case BFD_RELOC_ARM_ALU_SB_G0
:
21292 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21293 case BFD_RELOC_ARM_ALU_SB_G1
:
21294 case BFD_RELOC_ARM_ALU_SB_G2
:
21295 case BFD_RELOC_ARM_LDR_SB_G0
:
21296 case BFD_RELOC_ARM_LDR_SB_G1
:
21297 case BFD_RELOC_ARM_LDR_SB_G2
:
21298 case BFD_RELOC_ARM_LDRS_SB_G0
:
21299 case BFD_RELOC_ARM_LDRS_SB_G1
:
21300 case BFD_RELOC_ARM_LDRS_SB_G2
:
21301 case BFD_RELOC_ARM_LDC_SB_G0
:
21302 case BFD_RELOC_ARM_LDC_SB_G1
:
21303 case BFD_RELOC_ARM_LDC_SB_G2
:
21304 case BFD_RELOC_ARM_V4BX
:
21305 code
= fixp
->fx_r_type
;
21308 case BFD_RELOC_ARM_TLS_GD32
:
21309 case BFD_RELOC_ARM_TLS_IE32
:
21310 case BFD_RELOC_ARM_TLS_LDM32
:
21311 /* BFD will include the symbol's address in the addend.
21312 But we don't want that, so subtract it out again here. */
21313 if (!S_IS_COMMON (fixp
->fx_addsy
))
21314 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21315 code
= fixp
->fx_r_type
;
21319 case BFD_RELOC_ARM_IMMEDIATE
:
21320 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21321 _("internal relocation (type: IMMEDIATE) not fixed up"));
21324 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21325 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21326 _("ADRL used for a symbol not defined in the same file"));
21329 case BFD_RELOC_ARM_OFFSET_IMM
:
21330 if (section
->use_rela_p
)
21332 code
= fixp
->fx_r_type
;
21336 if (fixp
->fx_addsy
!= NULL
21337 && !S_IS_DEFINED (fixp
->fx_addsy
)
21338 && S_IS_LOCAL (fixp
->fx_addsy
))
21340 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21341 _("undefined local label `%s'"),
21342 S_GET_NAME (fixp
->fx_addsy
));
21346 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21347 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21354 switch (fixp
->fx_r_type
)
21356 case BFD_RELOC_NONE
: type
= "NONE"; break;
21357 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21358 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21359 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21360 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21361 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21362 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21363 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21364 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21365 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21366 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21367 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21368 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21369 default: type
= _("<unknown>"); break;
21371 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21372 _("cannot represent %s relocation in this object file format"),
21379 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21381 && fixp
->fx_addsy
== GOT_symbol
)
21383 code
= BFD_RELOC_ARM_GOTPC
;
21384 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21388 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21390 if (reloc
->howto
== NULL
)
21392 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21393 _("cannot represent %s relocation in this object file format"),
21394 bfd_get_reloc_code_name (code
));
21398 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21399 vtable entry to be used in the relocation's section offset. */
21400 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21401 reloc
->address
= fixp
->fx_offset
;
21406 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21409 cons_fix_new_arm (fragS
* frag
,
21414 bfd_reloc_code_real_type type
;
21418 FIXME: @@ Should look at CPU word size. */
21422 type
= BFD_RELOC_8
;
21425 type
= BFD_RELOC_16
;
21429 type
= BFD_RELOC_32
;
21432 type
= BFD_RELOC_64
;
21437 if (exp
->X_op
== O_secrel
)
21439 exp
->X_op
= O_symbol
;
21440 type
= BFD_RELOC_32_SECREL
;
21444 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21447 #if defined (OBJ_COFF)
21449 arm_validate_fix (fixS
* fixP
)
21451 /* If the destination of the branch is a defined symbol which does not have
21452 the THUMB_FUNC attribute, then we must be calling a function which has
21453 the (interfacearm) attribute. We look for the Thumb entry point to that
21454 function and change the branch to refer to that function instead. */
21455 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21456 && fixP
->fx_addsy
!= NULL
21457 && S_IS_DEFINED (fixP
->fx_addsy
)
21458 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21460 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21467 arm_force_relocation (struct fix
* fixp
)
21469 #if defined (OBJ_COFF) && defined (TE_PE)
21470 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21474 /* In case we have a call or a branch to a function in ARM ISA mode from
21475 a thumb function or vice-versa force the relocation. These relocations
21476 are cleared off for some cores that might have blx and simple transformations
21480 switch (fixp
->fx_r_type
)
21482 case BFD_RELOC_ARM_PCREL_JUMP
:
21483 case BFD_RELOC_ARM_PCREL_CALL
:
21484 case BFD_RELOC_THUMB_PCREL_BLX
:
21485 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21489 case BFD_RELOC_ARM_PCREL_BLX
:
21490 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21491 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21492 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21493 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21502 /* Resolve these relocations even if the symbol is extern or weak. */
21503 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21504 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21505 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21506 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21507 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21508 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21509 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21512 /* Always leave these relocations for the linker. */
21513 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21514 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21515 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21518 /* Always generate relocations against function symbols. */
21519 if (fixp
->fx_r_type
== BFD_RELOC_32
21521 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21524 return generic_force_reloc (fixp
);
21527 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21528 /* Relocations against function names must be left unadjusted,
21529 so that the linker can use this information to generate interworking
21530 stubs. The MIPS version of this function
21531 also prevents relocations that are mips-16 specific, but I do not
21532 know why it does this.
21535 There is one other problem that ought to be addressed here, but
21536 which currently is not: Taking the address of a label (rather
21537 than a function) and then later jumping to that address. Such
21538 addresses also ought to have their bottom bit set (assuming that
21539 they reside in Thumb code), but at the moment they will not. */
21542 arm_fix_adjustable (fixS
* fixP
)
21544 if (fixP
->fx_addsy
== NULL
)
21547 /* Preserve relocations against symbols with function type. */
21548 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21551 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21552 && fixP
->fx_subsy
== NULL
)
21555 /* We need the symbol name for the VTABLE entries. */
21556 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21557 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21560 /* Don't allow symbols to be discarded on GOT related relocs. */
21561 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21562 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21563 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21564 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21565 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21566 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21567 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21568 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21569 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21572 /* Similarly for group relocations. */
21573 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21574 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21575 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21578 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21579 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21580 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21581 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21582 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21583 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21584 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21585 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21586 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21591 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21596 elf32_arm_target_format (void)
21599 return (target_big_endian
21600 ? "elf32-bigarm-symbian"
21601 : "elf32-littlearm-symbian");
21602 #elif defined (TE_VXWORKS)
21603 return (target_big_endian
21604 ? "elf32-bigarm-vxworks"
21605 : "elf32-littlearm-vxworks");
21607 if (target_big_endian
)
21608 return "elf32-bigarm";
21610 return "elf32-littlearm";
21615 armelf_frob_symbol (symbolS
* symp
,
21618 elf_frob_symbol (symp
, puntp
);
21622 /* MD interface: Finalization. */
21627 literal_pool
* pool
;
21629 /* Ensure that all the IT blocks are properly closed. */
21630 check_it_blocks_finished ();
21632 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21634 /* Put it at the end of the relevant section. */
21635 subseg_set (pool
->section
, pool
->sub_section
);
21637 arm_elf_change_section ();
21644 /* Remove any excess mapping symbols generated for alignment frags in
21645 SEC. We may have created a mapping symbol before a zero byte
21646 alignment; remove it if there's a mapping symbol after the
21649 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21650 void *dummy ATTRIBUTE_UNUSED
)
21652 segment_info_type
*seginfo
= seg_info (sec
);
21655 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21658 for (fragp
= seginfo
->frchainP
->frch_root
;
21660 fragp
= fragp
->fr_next
)
21662 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21663 fragS
*next
= fragp
->fr_next
;
21665 /* Variable-sized frags have been converted to fixed size by
21666 this point. But if this was variable-sized to start with,
21667 there will be a fixed-size frag after it. So don't handle
21669 if (sym
== NULL
|| next
== NULL
)
21672 if (S_GET_VALUE (sym
) < next
->fr_address
)
21673 /* Not at the end of this frag. */
21675 know (S_GET_VALUE (sym
) == next
->fr_address
);
21679 if (next
->tc_frag_data
.first_map
!= NULL
)
21681 /* Next frag starts with a mapping symbol. Discard this
21683 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21687 if (next
->fr_next
== NULL
)
21689 /* This mapping symbol is at the end of the section. Discard
21691 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21692 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21696 /* As long as we have empty frags without any mapping symbols,
21698 /* If the next frag is non-empty and does not start with a
21699 mapping symbol, then this mapping symbol is required. */
21700 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21703 next
= next
->fr_next
;
21705 while (next
!= NULL
);
21710 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21714 arm_adjust_symtab (void)
21719 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21721 if (ARM_IS_THUMB (sym
))
21723 if (THUMB_IS_FUNC (sym
))
21725 /* Mark the symbol as a Thumb function. */
21726 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21727 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21728 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21730 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21731 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21733 as_bad (_("%s: unexpected function type: %d"),
21734 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21736 else switch (S_GET_STORAGE_CLASS (sym
))
21739 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21742 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21745 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21753 if (ARM_IS_INTERWORK (sym
))
21754 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21761 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21763 if (ARM_IS_THUMB (sym
))
21765 elf_symbol_type
* elf_sym
;
21767 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21768 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21770 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21771 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21773 /* If it's a .thumb_func, declare it as so,
21774 otherwise tag label as .code 16. */
21775 if (THUMB_IS_FUNC (sym
))
21776 elf_sym
->internal_elf_sym
.st_info
=
21777 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21778 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21779 elf_sym
->internal_elf_sym
.st_info
=
21780 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21785 /* Remove any overlapping mapping symbols generated by alignment frags. */
21786 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21790 /* MD interface: Initialization. */
21793 set_constant_flonums (void)
21797 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21798 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21802 /* Auto-select Thumb mode if it's the only available instruction set for the
21803 given architecture. */
21806 autoselect_thumb_from_cpu_variant (void)
21808 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21809 opcode_select (16);
21818 if ( (arm_ops_hsh
= hash_new ()) == NULL
21819 || (arm_cond_hsh
= hash_new ()) == NULL
21820 || (arm_shift_hsh
= hash_new ()) == NULL
21821 || (arm_psr_hsh
= hash_new ()) == NULL
21822 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21823 || (arm_reg_hsh
= hash_new ()) == NULL
21824 || (arm_reloc_hsh
= hash_new ()) == NULL
21825 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21826 as_fatal (_("virtual memory exhausted"));
21828 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21829 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21830 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21831 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21832 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21833 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21834 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21835 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21836 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21837 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21838 (void *) (v7m_psrs
+ i
));
21839 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21840 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21842 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21844 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21845 (void *) (barrier_opt_names
+ i
));
21847 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21848 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21851 set_constant_flonums ();
21853 /* Set the cpu variant based on the command-line options. We prefer
21854 -mcpu= over -march= if both are set (as for GCC); and we prefer
21855 -mfpu= over any other way of setting the floating point unit.
21856 Use of legacy options with new options are faulted. */
21859 if (mcpu_cpu_opt
|| march_cpu_opt
)
21860 as_bad (_("use of old and new-style options to set CPU type"));
21862 mcpu_cpu_opt
= legacy_cpu
;
21864 else if (!mcpu_cpu_opt
)
21865 mcpu_cpu_opt
= march_cpu_opt
;
21870 as_bad (_("use of old and new-style options to set FPU type"));
21872 mfpu_opt
= legacy_fpu
;
21874 else if (!mfpu_opt
)
21876 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21877 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21878 /* Some environments specify a default FPU. If they don't, infer it
21879 from the processor. */
21881 mfpu_opt
= mcpu_fpu_opt
;
21883 mfpu_opt
= march_fpu_opt
;
21885 mfpu_opt
= &fpu_default
;
21891 if (mcpu_cpu_opt
!= NULL
)
21892 mfpu_opt
= &fpu_default
;
21893 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21894 mfpu_opt
= &fpu_arch_vfp_v2
;
21896 mfpu_opt
= &fpu_arch_fpa
;
21902 mcpu_cpu_opt
= &cpu_default
;
21903 selected_cpu
= cpu_default
;
21907 selected_cpu
= *mcpu_cpu_opt
;
21909 mcpu_cpu_opt
= &arm_arch_any
;
21912 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21914 autoselect_thumb_from_cpu_variant ();
21916 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21918 #if defined OBJ_COFF || defined OBJ_ELF
21920 unsigned int flags
= 0;
21922 #if defined OBJ_ELF
21923 flags
= meabi_flags
;
21925 switch (meabi_flags
)
21927 case EF_ARM_EABI_UNKNOWN
:
21929 /* Set the flags in the private structure. */
21930 if (uses_apcs_26
) flags
|= F_APCS26
;
21931 if (support_interwork
) flags
|= F_INTERWORK
;
21932 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21933 if (pic_code
) flags
|= F_PIC
;
21934 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21935 flags
|= F_SOFT_FLOAT
;
21937 switch (mfloat_abi_opt
)
21939 case ARM_FLOAT_ABI_SOFT
:
21940 case ARM_FLOAT_ABI_SOFTFP
:
21941 flags
|= F_SOFT_FLOAT
;
21944 case ARM_FLOAT_ABI_HARD
:
21945 if (flags
& F_SOFT_FLOAT
)
21946 as_bad (_("hard-float conflicts with specified fpu"));
21950 /* Using pure-endian doubles (even if soft-float). */
21951 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21952 flags
|= F_VFP_FLOAT
;
21954 #if defined OBJ_ELF
21955 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21956 flags
|= EF_ARM_MAVERICK_FLOAT
;
21959 case EF_ARM_EABI_VER4
:
21960 case EF_ARM_EABI_VER5
:
21961 /* No additional flags to set. */
21968 bfd_set_private_flags (stdoutput
, flags
);
21970 /* We have run out flags in the COFF header to encode the
21971 status of ATPCS support, so instead we create a dummy,
21972 empty, debug section called .arm.atpcs. */
21977 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21981 bfd_set_section_flags
21982 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21983 bfd_set_section_size (stdoutput
, sec
, 0);
21984 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21990 /* Record the CPU type as well. */
21991 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21992 mach
= bfd_mach_arm_iWMMXt2
;
21993 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21994 mach
= bfd_mach_arm_iWMMXt
;
21995 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21996 mach
= bfd_mach_arm_XScale
;
21997 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21998 mach
= bfd_mach_arm_ep9312
;
21999 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22000 mach
= bfd_mach_arm_5TE
;
22001 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22003 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22004 mach
= bfd_mach_arm_5T
;
22006 mach
= bfd_mach_arm_5
;
22008 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22010 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22011 mach
= bfd_mach_arm_4T
;
22013 mach
= bfd_mach_arm_4
;
22015 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22016 mach
= bfd_mach_arm_3M
;
22017 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22018 mach
= bfd_mach_arm_3
;
22019 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22020 mach
= bfd_mach_arm_2a
;
22021 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22022 mach
= bfd_mach_arm_2
;
22024 mach
= bfd_mach_arm_unknown
;
22026 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22029 /* Command line processing. */
22032 Invocation line includes a switch not recognized by the base assembler.
22033 See if it's a processor-specific option.
22035 This routine is somewhat complicated by the need for backwards
22036 compatibility (since older releases of gcc can't be changed).
22037 The new options try to make the interface as compatible as
22040 New options (supported) are:
22042 -mcpu=<cpu name> Assemble for selected processor
22043 -march=<architecture name> Assemble for selected architecture
22044 -mfpu=<fpu architecture> Assemble for selected FPU.
22045 -EB/-mbig-endian Big-endian
22046 -EL/-mlittle-endian Little-endian
22047 -k Generate PIC code
22048 -mthumb Start in Thumb mode
22049 -mthumb-interwork Code supports ARM/Thumb interworking
22051 -m[no-]warn-deprecated Warn about deprecated features
22053 For now we will also provide support for:
22055 -mapcs-32 32-bit Program counter
22056 -mapcs-26 26-bit Program counter
22057 -macps-float Floats passed in FP registers
22058 -mapcs-reentrant Reentrant code
22060 (sometime these will probably be replaced with -mapcs=<list of options>
22061 and -matpcs=<list of options>)
22063 The remaining options are only supported for back-wards compatibility.
22064 Cpu variants, the arm part is optional:
22065 -m[arm]1 Currently not supported.
22066 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22067 -m[arm]3 Arm 3 processor
22068 -m[arm]6[xx], Arm 6 processors
22069 -m[arm]7[xx][t][[d]m] Arm 7 processors
22070 -m[arm]8[10] Arm 8 processors
22071 -m[arm]9[20][tdmi] Arm 9 processors
22072 -mstrongarm[110[0]] StrongARM processors
22073 -mxscale XScale processors
22074 -m[arm]v[2345[t[e]]] Arm architectures
22075 -mall All (except the ARM1)
22077 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22078 -mfpe-old (No float load/store multiples)
22079 -mvfpxd VFP Single precision
22081 -mno-fpu Disable all floating point instructions
22083 The following CPU names are recognized:
22084 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22085 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22086 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22087 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22088 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22089 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22090 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22094 const char * md_shortopts
= "m:k";
22096 #ifdef ARM_BI_ENDIAN
22097 #define OPTION_EB (OPTION_MD_BASE + 0)
22098 #define OPTION_EL (OPTION_MD_BASE + 1)
22100 #if TARGET_BYTES_BIG_ENDIAN
22101 #define OPTION_EB (OPTION_MD_BASE + 0)
22103 #define OPTION_EL (OPTION_MD_BASE + 1)
22106 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22108 struct option md_longopts
[] =
22111 {"EB", no_argument
, NULL
, OPTION_EB
},
22114 {"EL", no_argument
, NULL
, OPTION_EL
},
22116 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22117 {NULL
, no_argument
, NULL
, 0}
22120 size_t md_longopts_size
= sizeof (md_longopts
);
22122 struct arm_option_table
22124 char *option
; /* Option name to match. */
22125 char *help
; /* Help information. */
22126 int *var
; /* Variable to change. */
22127 int value
; /* What to change it to. */
22128 char *deprecated
; /* If non-null, print this message. */
22131 struct arm_option_table arm_opts
[] =
22133 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22134 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22135 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22136 &support_interwork
, 1, NULL
},
22137 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22138 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22139 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22141 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22142 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22143 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22144 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22147 /* These are recognized by the assembler, but have no affect on code. */
22148 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22149 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22151 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22152 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22153 &warn_on_deprecated
, 0, NULL
},
22154 {NULL
, NULL
, NULL
, 0, NULL
}
22157 struct arm_legacy_option_table
22159 char *option
; /* Option name to match. */
22160 const arm_feature_set
**var
; /* Variable to change. */
22161 const arm_feature_set value
; /* What to change it to. */
22162 char *deprecated
; /* If non-null, print this message. */
22165 const struct arm_legacy_option_table arm_legacy_opts
[] =
22167 /* DON'T add any new processors to this list -- we want the whole list
22168 to go away... Add them to the processors table instead. */
22169 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22170 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22171 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22172 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22173 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22174 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22175 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22176 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22177 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22178 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22179 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22180 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22181 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22182 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22183 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22184 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22185 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22186 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22187 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22188 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22189 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22190 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22191 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22192 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22193 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22194 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22195 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22196 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22197 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22198 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22199 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22200 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22201 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22202 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22203 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22204 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22205 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22206 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22207 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22208 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22209 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22210 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22211 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22212 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22213 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22214 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22215 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22216 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22217 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22218 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22219 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22220 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22221 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22222 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22223 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22224 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22225 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22226 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22227 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22228 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22229 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22230 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22231 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22232 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22233 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22234 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22235 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22236 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22237 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22238 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22239 N_("use -mcpu=strongarm110")},
22240 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22241 N_("use -mcpu=strongarm1100")},
22242 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22243 N_("use -mcpu=strongarm1110")},
22244 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22245 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22246 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22248 /* Architecture variants -- don't add any more to this list either. */
22249 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22250 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22251 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22252 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22253 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22254 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22255 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22256 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22257 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22258 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22259 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22260 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22261 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22262 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22263 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22264 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22265 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22266 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22268 /* Floating point variants -- don't add any more to this list either. */
22269 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22270 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22271 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22272 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22273 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22275 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22278 struct arm_cpu_option_table
22281 const arm_feature_set value
;
22282 /* For some CPUs we assume an FPU unless the user explicitly sets
22284 const arm_feature_set default_fpu
;
22285 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22287 const char *canonical_name
;
22290 /* This list should, at a minimum, contain all the cpu names
22291 recognized by GCC. */
22292 static const struct arm_cpu_option_table arm_cpus
[] =
22294 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22295 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22296 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22297 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22298 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22299 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22300 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22301 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22302 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22303 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22304 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22305 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22306 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22307 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22308 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22309 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22310 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22311 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22312 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22313 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22314 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22315 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22316 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22317 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22318 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22319 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22320 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22321 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22322 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22323 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22324 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22325 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22326 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22327 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22328 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22329 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22330 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22331 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22332 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22333 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22334 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22335 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22336 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22337 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22338 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22339 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22340 /* For V5 or later processors we default to using VFP; but the user
22341 should really set the FPU type explicitly. */
22342 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22343 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22344 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22345 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22346 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22347 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22348 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22349 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22350 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22351 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22352 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22353 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22354 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22355 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22356 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22357 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22358 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22359 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22360 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22361 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22362 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22363 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22364 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22365 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22366 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22367 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22368 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22369 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"},
22370 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"},
22371 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22372 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22373 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22374 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22375 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, "Cortex-A5"},
22376 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22377 | FPU_NEON_EXT_V1
),
22379 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22380 | FPU_NEON_EXT_V1
),
22382 {"cortex-a15", ARM_ARCH_V7A
, FPU_ARCH_NEON_VFP_V4
,
22384 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"},
22385 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
22387 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"},
22388 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"},
22389 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, "Cortex-M1"},
22390 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, "Cortex-M0"},
22391 /* ??? XSCALE is really an architecture. */
22392 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22393 /* ??? iwmmxt is not a processor. */
22394 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22395 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22396 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22398 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22399 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22402 struct arm_arch_option_table
22405 const arm_feature_set value
;
22406 const arm_feature_set default_fpu
;
22409 /* This list should, at a minimum, contain all the architecture names
22410 recognized by GCC. */
22411 static const struct arm_arch_option_table arm_archs
[] =
22413 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22414 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22415 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22416 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22417 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22418 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22419 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22420 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22421 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22422 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22423 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22424 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22425 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22426 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22427 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22428 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22429 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22430 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22431 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22432 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22433 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22434 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22435 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22436 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22437 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22438 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22439 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22440 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22441 /* The official spelling of the ARMv7 profile variants is the dashed form.
22442 Accept the non-dashed form for compatibility with old toolchains. */
22443 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22444 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22445 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22446 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22447 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22448 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22449 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22450 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22451 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22452 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22453 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22456 /* ISA extensions in the co-processor and main instruction set space. */
22457 struct arm_option_extension_value_table
22460 const arm_feature_set value
;
22461 const arm_feature_set allowed_archs
;
22464 /* The following table must be in alphabetical order with a NULL last entry.
22466 static const struct arm_option_extension_value_table arm_extensions
[] =
22468 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
},
22469 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
},
22470 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
},
22471 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
},
22472 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22475 /* ISA floating-point and Advanced SIMD extensions. */
22476 struct arm_option_fpu_value_table
22479 const arm_feature_set value
;
22482 /* This list should, at a minimum, contain all the fpu names
22483 recognized by GCC. */
22484 static const struct arm_option_fpu_value_table arm_fpus
[] =
22486 {"softfpa", FPU_NONE
},
22487 {"fpe", FPU_ARCH_FPE
},
22488 {"fpe2", FPU_ARCH_FPE
},
22489 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22490 {"fpa", FPU_ARCH_FPA
},
22491 {"fpa10", FPU_ARCH_FPA
},
22492 {"fpa11", FPU_ARCH_FPA
},
22493 {"arm7500fe", FPU_ARCH_FPA
},
22494 {"softvfp", FPU_ARCH_VFP
},
22495 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22496 {"vfp", FPU_ARCH_VFP_V2
},
22497 {"vfp9", FPU_ARCH_VFP_V2
},
22498 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22499 {"vfp10", FPU_ARCH_VFP_V2
},
22500 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22501 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22502 {"vfpv2", FPU_ARCH_VFP_V2
},
22503 {"vfpv3", FPU_ARCH_VFP_V3
},
22504 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22505 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22506 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22507 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22508 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22509 {"arm1020t", FPU_ARCH_VFP_V1
},
22510 {"arm1020e", FPU_ARCH_VFP_V2
},
22511 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22512 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22513 {"maverick", FPU_ARCH_MAVERICK
},
22514 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22515 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22516 {"vfpv4", FPU_ARCH_VFP_V4
},
22517 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22518 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22519 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22520 {NULL
, ARM_ARCH_NONE
}
22523 struct arm_option_value_table
22529 static const struct arm_option_value_table arm_float_abis
[] =
22531 {"hard", ARM_FLOAT_ABI_HARD
},
22532 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22533 {"soft", ARM_FLOAT_ABI_SOFT
},
22538 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22539 static const struct arm_option_value_table arm_eabis
[] =
22541 {"gnu", EF_ARM_EABI_UNKNOWN
},
22542 {"4", EF_ARM_EABI_VER4
},
22543 {"5", EF_ARM_EABI_VER5
},
22548 struct arm_long_option_table
22550 char * option
; /* Substring to match. */
22551 char * help
; /* Help information. */
22552 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22553 char * deprecated
; /* If non-null, print this message. */
22557 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22559 arm_feature_set
*ext_set
= (arm_feature_set
*)
22560 xmalloc (sizeof (arm_feature_set
));
22562 /* We insist on extensions being specified in alphabetical order, and with
22563 extensions being added before being removed. We achieve this by having
22564 the global ARM_EXTENSIONS table in alphabetical order, and using the
22565 ADDING_VALUE variable to indicate whether we are adding an extension (1)
22566 or removing it (0) and only allowing it to change in the order
22568 const struct arm_option_extension_value_table
* opt
= NULL
;
22569 int adding_value
= -1;
22571 /* Copy the feature set, so that we can modify it. */
22572 *ext_set
= **opt_p
;
22575 while (str
!= NULL
&& *str
!= 0)
22582 as_bad (_("invalid architectural extension"));
22587 ext
= strchr (str
, '+');
22590 optlen
= ext
- str
;
22592 optlen
= strlen (str
);
22595 && strncmp (str
, "no", 2) == 0)
22597 if (adding_value
!= 0)
22600 opt
= arm_extensions
;
22606 else if (optlen
> 0)
22608 if (adding_value
== -1)
22611 opt
= arm_extensions
;
22613 else if (adding_value
!= 1)
22615 as_bad (_("must specify extensions to add before specifying "
22616 "those to remove"));
22623 as_bad (_("missing architectural extension"));
22627 gas_assert (adding_value
!= -1);
22628 gas_assert (opt
!= NULL
);
22630 /* Scan over the options table trying to find an exact match. */
22631 for (; opt
->name
!= NULL
; opt
++)
22632 if (strncmp (opt
->name
, str
, optlen
) == 0
22633 && strlen (opt
->name
) == optlen
)
22635 /* Check we can apply the extension to this architecture. */
22636 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
22638 as_bad (_("extension does not apply to the base architecture"));
22642 /* Add or remove the extension. */
22644 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22646 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
22651 if (opt
->name
== NULL
)
22653 /* Did we fail to find an extension because it wasn't specified in
22654 alphabetical order, or because it does not exist? */
22656 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22657 if (strncmp (opt
->name
, str
, optlen
) == 0)
22660 if (opt
->name
== NULL
)
22661 as_bad (_("unknown architectural extension `%s'"), str
);
22663 as_bad (_("architectural extensions must be specified in "
22664 "alphabetical order"));
22670 /* We should skip the extension we've just matched the next time
22682 arm_parse_cpu (char * str
)
22684 const struct arm_cpu_option_table
* opt
;
22685 char * ext
= strchr (str
, '+');
22689 optlen
= ext
- str
;
22691 optlen
= strlen (str
);
22695 as_bad (_("missing cpu name `%s'"), str
);
22699 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22700 if (strncmp (opt
->name
, str
, optlen
) == 0)
22702 mcpu_cpu_opt
= &opt
->value
;
22703 mcpu_fpu_opt
= &opt
->default_fpu
;
22704 if (opt
->canonical_name
)
22705 strcpy (selected_cpu_name
, opt
->canonical_name
);
22710 for (i
= 0; i
< optlen
; i
++)
22711 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22712 selected_cpu_name
[i
] = 0;
22716 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22721 as_bad (_("unknown cpu `%s'"), str
);
22726 arm_parse_arch (char * str
)
22728 const struct arm_arch_option_table
*opt
;
22729 char *ext
= strchr (str
, '+');
22733 optlen
= ext
- str
;
22735 optlen
= strlen (str
);
22739 as_bad (_("missing architecture name `%s'"), str
);
22743 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22744 if (strncmp (opt
->name
, str
, optlen
) == 0)
22746 march_cpu_opt
= &opt
->value
;
22747 march_fpu_opt
= &opt
->default_fpu
;
22748 strcpy (selected_cpu_name
, opt
->name
);
22751 return arm_parse_extension (ext
, &march_cpu_opt
);
22756 as_bad (_("unknown architecture `%s'\n"), str
);
22761 arm_parse_fpu (char * str
)
22763 const struct arm_option_fpu_value_table
* opt
;
22765 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22766 if (streq (opt
->name
, str
))
22768 mfpu_opt
= &opt
->value
;
22772 as_bad (_("unknown floating point format `%s'\n"), str
);
22777 arm_parse_float_abi (char * str
)
22779 const struct arm_option_value_table
* opt
;
22781 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22782 if (streq (opt
->name
, str
))
22784 mfloat_abi_opt
= opt
->value
;
22788 as_bad (_("unknown floating point abi `%s'\n"), str
);
22794 arm_parse_eabi (char * str
)
22796 const struct arm_option_value_table
*opt
;
22798 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22799 if (streq (opt
->name
, str
))
22801 meabi_flags
= opt
->value
;
22804 as_bad (_("unknown EABI `%s'\n"), str
);
22810 arm_parse_it_mode (char * str
)
22812 bfd_boolean ret
= TRUE
;
22814 if (streq ("arm", str
))
22815 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22816 else if (streq ("thumb", str
))
22817 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22818 else if (streq ("always", str
))
22819 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22820 else if (streq ("never", str
))
22821 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22824 as_bad (_("unknown implicit IT mode `%s', should be "\
22825 "arm, thumb, always, or never."), str
);
22832 struct arm_long_option_table arm_long_opts
[] =
22834 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22835 arm_parse_cpu
, NULL
},
22836 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22837 arm_parse_arch
, NULL
},
22838 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22839 arm_parse_fpu
, NULL
},
22840 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22841 arm_parse_float_abi
, NULL
},
22843 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22844 arm_parse_eabi
, NULL
},
22846 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22847 arm_parse_it_mode
, NULL
},
22848 {NULL
, NULL
, 0, NULL
}
22852 md_parse_option (int c
, char * arg
)
22854 struct arm_option_table
*opt
;
22855 const struct arm_legacy_option_table
*fopt
;
22856 struct arm_long_option_table
*lopt
;
22862 target_big_endian
= 1;
22868 target_big_endian
= 0;
22872 case OPTION_FIX_V4BX
:
22877 /* Listing option. Just ignore these, we don't support additional
22882 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22884 if (c
== opt
->option
[0]
22885 && ((arg
== NULL
&& opt
->option
[1] == 0)
22886 || streq (arg
, opt
->option
+ 1)))
22888 /* If the option is deprecated, tell the user. */
22889 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22890 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22891 arg
? arg
: "", _(opt
->deprecated
));
22893 if (opt
->var
!= NULL
)
22894 *opt
->var
= opt
->value
;
22900 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22902 if (c
== fopt
->option
[0]
22903 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22904 || streq (arg
, fopt
->option
+ 1)))
22906 /* If the option is deprecated, tell the user. */
22907 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22908 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22909 arg
? arg
: "", _(fopt
->deprecated
));
22911 if (fopt
->var
!= NULL
)
22912 *fopt
->var
= &fopt
->value
;
22918 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22920 /* These options are expected to have an argument. */
22921 if (c
== lopt
->option
[0]
22923 && strncmp (arg
, lopt
->option
+ 1,
22924 strlen (lopt
->option
+ 1)) == 0)
22926 /* If the option is deprecated, tell the user. */
22927 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22928 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22929 _(lopt
->deprecated
));
22931 /* Call the sup-option parser. */
22932 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22943 md_show_usage (FILE * fp
)
22945 struct arm_option_table
*opt
;
22946 struct arm_long_option_table
*lopt
;
22948 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22950 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22951 if (opt
->help
!= NULL
)
22952 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22954 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22955 if (lopt
->help
!= NULL
)
22956 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22960 -EB assemble code for a big-endian cpu\n"));
22965 -EL assemble code for a little-endian cpu\n"));
22969 --fix-v4bx Allow BX in ARMv4 code\n"));
22977 arm_feature_set flags
;
22978 } cpu_arch_ver_table
;
22980 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22981 least features first. */
22982 static const cpu_arch_ver_table cpu_arch_ver
[] =
22988 {4, ARM_ARCH_V5TE
},
22989 {5, ARM_ARCH_V5TEJ
},
22993 {11, ARM_ARCH_V6M
},
22994 {8, ARM_ARCH_V6T2
},
22995 {10, ARM_ARCH_V7A
},
22996 {10, ARM_ARCH_V7R
},
22997 {10, ARM_ARCH_V7M
},
23001 /* Set an attribute if it has not already been set by the user. */
23003 aeabi_set_attribute_int (int tag
, int value
)
23006 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23007 || !attributes_set_explicitly
[tag
])
23008 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
23012 aeabi_set_attribute_string (int tag
, const char *value
)
23015 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23016 || !attributes_set_explicitly
[tag
])
23017 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
23020 /* Set the public EABI object attributes. */
23022 aeabi_set_public_attributes (void)
23025 arm_feature_set flags
;
23026 arm_feature_set tmp
;
23027 const cpu_arch_ver_table
*p
;
23029 /* Choose the architecture based on the capabilities of the requested cpu
23030 (if any) and/or the instructions actually used. */
23031 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
23032 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
23033 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
23034 /*Allow the user to override the reported architecture. */
23037 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
23038 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
23043 for (p
= cpu_arch_ver
; p
->val
; p
++)
23045 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
23048 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
23052 /* The table lookup above finds the last architecture to contribute
23053 a new feature. Unfortunately, Tag13 is a subset of the union of
23054 v6T2 and v7-M, so it is never seen as contributing a new feature.
23055 We can not search for the last entry which is entirely used,
23056 because if no CPU is specified we build up only those flags
23057 actually used. Perhaps we should separate out the specified
23058 and implicit cases. Avoid taking this path for -march=all by
23059 checking for contradictory v7-A / v7-M features. */
23061 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
23062 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
23063 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
23066 /* Tag_CPU_name. */
23067 if (selected_cpu_name
[0])
23071 q
= selected_cpu_name
;
23072 if (strncmp (q
, "armv", 4) == 0)
23077 for (i
= 0; q
[i
]; i
++)
23078 q
[i
] = TOUPPER (q
[i
]);
23080 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23083 /* Tag_CPU_arch. */
23084 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23086 /* Tag_CPU_arch_profile. */
23087 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23088 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23089 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23090 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23091 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23092 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23094 /* Tag_ARM_ISA_use. */
23095 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23097 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23099 /* Tag_THUMB_ISA_use. */
23100 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23102 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23103 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23105 /* Tag_VFP_arch. */
23106 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23107 aeabi_set_attribute_int (Tag_VFP_arch
,
23108 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23110 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23111 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23112 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23113 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23114 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23115 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23116 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23117 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23118 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23120 /* Tag_ABI_HardFP_use. */
23121 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23122 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23123 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23125 /* Tag_WMMX_arch. */
23126 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23127 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23128 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23129 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23131 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23132 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23133 aeabi_set_attribute_int
23134 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23137 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23138 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23139 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23142 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23143 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23144 /* Fill this in when gas supports v7a sdiv/udiv.
23145 else if (... v7a with div extension used ...)
23146 aeabi_set_attribute_int (Tag_DIV_use, 2); */
23148 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23151 /* Add the default contents for the .ARM.attributes section. */
23155 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23158 aeabi_set_public_attributes ();
23160 #endif /* OBJ_ELF */
23163 /* Parse a .cpu directive. */
23166 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23168 const struct arm_cpu_option_table
*opt
;
23172 name
= input_line_pointer
;
23173 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23174 input_line_pointer
++;
23175 saved_char
= *input_line_pointer
;
23176 *input_line_pointer
= 0;
23178 /* Skip the first "all" entry. */
23179 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23180 if (streq (opt
->name
, name
))
23182 mcpu_cpu_opt
= &opt
->value
;
23183 selected_cpu
= opt
->value
;
23184 if (opt
->canonical_name
)
23185 strcpy (selected_cpu_name
, opt
->canonical_name
);
23189 for (i
= 0; opt
->name
[i
]; i
++)
23190 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23191 selected_cpu_name
[i
] = 0;
23193 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23194 *input_line_pointer
= saved_char
;
23195 demand_empty_rest_of_line ();
23198 as_bad (_("unknown cpu `%s'"), name
);
23199 *input_line_pointer
= saved_char
;
23200 ignore_rest_of_line ();
23204 /* Parse a .arch directive. */
23207 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23209 const struct arm_arch_option_table
*opt
;
23213 name
= input_line_pointer
;
23214 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23215 input_line_pointer
++;
23216 saved_char
= *input_line_pointer
;
23217 *input_line_pointer
= 0;
23219 /* Skip the first "all" entry. */
23220 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23221 if (streq (opt
->name
, name
))
23223 mcpu_cpu_opt
= &opt
->value
;
23224 selected_cpu
= opt
->value
;
23225 strcpy (selected_cpu_name
, opt
->name
);
23226 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23227 *input_line_pointer
= saved_char
;
23228 demand_empty_rest_of_line ();
23232 as_bad (_("unknown architecture `%s'\n"), name
);
23233 *input_line_pointer
= saved_char
;
23234 ignore_rest_of_line ();
23238 /* Parse a .object_arch directive. */
23241 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23243 const struct arm_arch_option_table
*opt
;
23247 name
= input_line_pointer
;
23248 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23249 input_line_pointer
++;
23250 saved_char
= *input_line_pointer
;
23251 *input_line_pointer
= 0;
23253 /* Skip the first "all" entry. */
23254 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23255 if (streq (opt
->name
, name
))
23257 object_arch
= &opt
->value
;
23258 *input_line_pointer
= saved_char
;
23259 demand_empty_rest_of_line ();
23263 as_bad (_("unknown architecture `%s'\n"), name
);
23264 *input_line_pointer
= saved_char
;
23265 ignore_rest_of_line ();
23268 /* Parse a .arch_extension directive. */
23271 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
23273 const struct arm_option_extension_value_table
*opt
;
23276 int adding_value
= 1;
23278 name
= input_line_pointer
;
23279 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23280 input_line_pointer
++;
23281 saved_char
= *input_line_pointer
;
23282 *input_line_pointer
= 0;
23284 if (strlen (name
) >= 2
23285 && strncmp (name
, "no", 2) == 0)
23291 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23292 if (streq (opt
->name
, name
))
23294 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
23296 as_bad (_("architectural extension `%s' is not allowed for the "
23297 "current base architecture"), name
);
23302 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
23304 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
23306 mcpu_cpu_opt
= &selected_cpu
;
23307 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23308 *input_line_pointer
= saved_char
;
23309 demand_empty_rest_of_line ();
23313 if (opt
->name
== NULL
)
23314 as_bad (_("unknown architecture `%s'\n"), name
);
23316 *input_line_pointer
= saved_char
;
23317 ignore_rest_of_line ();
23320 /* Parse a .fpu directive. */
23323 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23325 const struct arm_option_fpu_value_table
*opt
;
23329 name
= input_line_pointer
;
23330 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23331 input_line_pointer
++;
23332 saved_char
= *input_line_pointer
;
23333 *input_line_pointer
= 0;
23335 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23336 if (streq (opt
->name
, name
))
23338 mfpu_opt
= &opt
->value
;
23339 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23340 *input_line_pointer
= saved_char
;
23341 demand_empty_rest_of_line ();
23345 as_bad (_("unknown floating point format `%s'\n"), name
);
23346 *input_line_pointer
= saved_char
;
23347 ignore_rest_of_line ();
23350 /* Copy symbol information. */
23353 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23355 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23359 /* Given a symbolic attribute NAME, return the proper integer value.
23360 Returns -1 if the attribute is not known. */
23363 arm_convert_symbolic_attribute (const char *name
)
23365 static const struct
23370 attribute_table
[] =
23372 /* When you modify this table you should
23373 also modify the list in doc/c-arm.texi. */
23374 #define T(tag) {#tag, tag}
23375 T (Tag_CPU_raw_name
),
23378 T (Tag_CPU_arch_profile
),
23379 T (Tag_ARM_ISA_use
),
23380 T (Tag_THUMB_ISA_use
),
23384 T (Tag_Advanced_SIMD_arch
),
23385 T (Tag_PCS_config
),
23386 T (Tag_ABI_PCS_R9_use
),
23387 T (Tag_ABI_PCS_RW_data
),
23388 T (Tag_ABI_PCS_RO_data
),
23389 T (Tag_ABI_PCS_GOT_use
),
23390 T (Tag_ABI_PCS_wchar_t
),
23391 T (Tag_ABI_FP_rounding
),
23392 T (Tag_ABI_FP_denormal
),
23393 T (Tag_ABI_FP_exceptions
),
23394 T (Tag_ABI_FP_user_exceptions
),
23395 T (Tag_ABI_FP_number_model
),
23396 T (Tag_ABI_align_needed
),
23397 T (Tag_ABI_align8_needed
),
23398 T (Tag_ABI_align_preserved
),
23399 T (Tag_ABI_align8_preserved
),
23400 T (Tag_ABI_enum_size
),
23401 T (Tag_ABI_HardFP_use
),
23402 T (Tag_ABI_VFP_args
),
23403 T (Tag_ABI_WMMX_args
),
23404 T (Tag_ABI_optimization_goals
),
23405 T (Tag_ABI_FP_optimization_goals
),
23406 T (Tag_compatibility
),
23407 T (Tag_CPU_unaligned_access
),
23408 T (Tag_FP_HP_extension
),
23409 T (Tag_VFP_HP_extension
),
23410 T (Tag_ABI_FP_16bit_format
),
23411 T (Tag_MPextension_use
),
23413 T (Tag_nodefaults
),
23414 T (Tag_also_compatible_with
),
23415 T (Tag_conformance
),
23417 T (Tag_Virtualization_use
),
23418 /* We deliberately do not include Tag_MPextension_use_legacy. */
23426 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23427 if (streq (name
, attribute_table
[i
].name
))
23428 return attribute_table
[i
].tag
;
23434 /* Apply sym value for relocations only in the case that
23435 they are for local symbols and you have the respective
23436 architectural feature for blx and simple switches. */
23438 arm_apply_sym_value (struct fix
* fixP
)
23441 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23442 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
23444 switch (fixP
->fx_r_type
)
23446 case BFD_RELOC_ARM_PCREL_BLX
:
23447 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23448 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23452 case BFD_RELOC_ARM_PCREL_CALL
:
23453 case BFD_RELOC_THUMB_PCREL_BLX
:
23454 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23465 #endif /* OBJ_ELF */