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Warn abouyt "bx pc" not being very useful.
[deliverable/binutils-gdb.git] / gas / config / tc-arm.c
1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modified by David Taylor (dtaylor@armltd.co.uk)
6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 02111-1307, USA. */
23
24 #include <ctype.h>
25 #include <string.h>
26 #define NO_RELOC 0
27 #include "as.h"
28
29 /* Need TARGET_CPU. */
30 #include "config.h"
31 #include "subsegs.h"
32 #include "obstack.h"
33 #include "symbols.h"
34 #include "listing.h"
35
36 #ifdef OBJ_ELF
37 #include "elf/arm.h"
38 #endif
39
40 /* Types of processor to assemble for. */
41 #define ARM_1 0x00000001
42 #define ARM_2 0x00000002
43 #define ARM_3 0x00000004
44 #define ARM_250 ARM_3
45 #define ARM_6 0x00000008
46 #define ARM_7 ARM_6 /* Same core instruction set. */
47 #define ARM_8 ARM_6 /* Same core instruction set. */
48 #define ARM_9 ARM_6 /* Same core instruction set. */
49 #define ARM_CPU_MASK 0x0000000f
50
51 /* The following bitmasks control CPU extensions (ARM7 onwards): */
52 #define ARM_LONGMUL 0x00000010 /* Allow long multiplies. */
53 #define ARM_HALFWORD 0x00000020 /* Allow half word loads. */
54 #define ARM_THUMB 0x00000040 /* Allow BX instruction. */
55 #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
56
57 /* Architectures are the sum of the base and extensions. */
58 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
59 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
60 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
61 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
62
63 /* Some useful combinations: */
64 #define ARM_ANY 0x00ffffff
65 #define ARM_2UP (ARM_ANY - ARM_1)
66 #define ARM_ALL ARM_2UP /* Not arm1 only. */
67 #define ARM_3UP 0x00fffffc
68 #define ARM_6UP 0x00fffff8 /* Includes ARM7. */
69
70 #define FPU_CORE 0x80000000
71 #define FPU_FPA10 0x40000000
72 #define FPU_FPA11 0x40000000
73 #define FPU_NONE 0
74
75 /* Some useful combinations. */
76 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY. */
77 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core. */
78
79 #ifndef CPU_DEFAULT
80 #if defined __thumb__
81 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
82 #else
83 #define CPU_DEFAULT ARM_ALL
84 #endif
85 #endif
86
87 #ifndef FPU_DEFAULT
88 #define FPU_DEFAULT FPU_ALL
89 #endif
90
91 #define streq(a, b) (strcmp (a, b) == 0)
92 #define skip_whitespace(str) while (*(str) == ' ') ++(str)
93
94 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
95 static int target_oabi = 0;
96
97 #if defined OBJ_COFF || defined OBJ_ELF
98 /* Flags stored in private area of BFD structure. */
99 static boolean uses_apcs_26 = false;
100 static boolean support_interwork = false;
101 static boolean uses_apcs_float = false;
102 static boolean pic_code = false;
103 #endif
104
105 /* This array holds the chars that always start a comment. If the
106 pre-processor is disabled, these aren't very useful. */
107 CONST char comment_chars[] = "@";
108
109 /* This array holds the chars that only start a comment at the beginning of
110 a line. If the line seems to have the form '# 123 filename'
111 .line and .file directives will appear in the pre-processed output. */
112 /* Note that input_file.c hand checks for '#' at the beginning of the
113 first line of the input file. This is because the compiler outputs
114 #NO_APP at the beginning of its output. */
115 /* Also note that comments like this one will always work. */
116 CONST char line_comment_chars[] = "#";
117
118 CONST char line_separator_chars[] = ";";
119
120 /* Chars that can be used to separate mant
121 from exp in floating point numbers. */
122 CONST char EXP_CHARS[] = "eE";
123
124 /* Chars that mean this number is a floating point constant. */
125 /* As in 0f12.456 */
126 /* or 0d1.2345e12 */
127
128 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
129
130 /* Prefix characters that indicate the start of an immediate
131 value. */
132 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
133
134 #ifdef OBJ_ELF
135 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
136 symbolS * GOT_symbol;
137 #endif
138
139 /* Size of relocation record. */
140 CONST int md_reloc_size = 8;
141
142 /* 0: assemble for ARM,
143 1: assemble for Thumb,
144 2: assemble for Thumb even though target CPU does not support thumb
145 instructions. */
146 static int thumb_mode = 0;
147
148 typedef struct arm_fix
149 {
150 int thumb_mode;
151 } arm_fix_data;
152
153 struct arm_it
154 {
155 CONST char * error;
156 unsigned long instruction;
157 int suffix;
158 int size;
159 struct
160 {
161 bfd_reloc_code_real_type type;
162 expressionS exp;
163 int pc_rel;
164 } reloc;
165 };
166
167 struct arm_it inst;
168
169 struct asm_shift
170 {
171 CONST char * template;
172 unsigned long value;
173 };
174
175 static CONST struct asm_shift shift[] =
176 {
177 {"asl", 0},
178 {"lsl", 0},
179 {"lsr", 0x00000020},
180 {"asr", 0x00000040},
181 {"ror", 0x00000060},
182 {"rrx", 0x00000060},
183 {"ASL", 0},
184 {"LSL", 0},
185 {"LSR", 0x00000020},
186 {"ASR", 0x00000040},
187 {"ROR", 0x00000060},
188 {"RRX", 0x00000060}
189 };
190
191 #define NO_SHIFT_RESTRICT 1
192 #define SHIFT_RESTRICT 0
193
194 #define NUM_FLOAT_VALS 8
195
196 CONST char * fp_const[] =
197 {
198 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
199 };
200
201 /* Number of littlenums required to hold an extended precision number. */
202 #define MAX_LITTLENUMS 6
203
204 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
205
206 #define FAIL (-1)
207 #define SUCCESS (0)
208
209 #define SUFF_S 1
210 #define SUFF_D 2
211 #define SUFF_E 3
212 #define SUFF_P 4
213
214 #define CP_T_X 0x00008000
215 #define CP_T_Y 0x00400000
216 #define CP_T_Pre 0x01000000
217 #define CP_T_UD 0x00800000
218 #define CP_T_WB 0x00200000
219
220 #define CONDS_BIT (0x00100000)
221 #define LOAD_BIT (0x00100000)
222 #define TRANS_BIT (0x00200000)
223
224 struct asm_cond
225 {
226 CONST char * template;
227 unsigned long value;
228 };
229
230 /* This is to save a hash look-up in the common case. */
231 #define COND_ALWAYS 0xe0000000
232
233 static CONST struct asm_cond conds[] =
234 {
235 {"eq", 0x00000000},
236 {"ne", 0x10000000},
237 {"cs", 0x20000000}, {"hs", 0x20000000},
238 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
239 {"mi", 0x40000000},
240 {"pl", 0x50000000},
241 {"vs", 0x60000000},
242 {"vc", 0x70000000},
243 {"hi", 0x80000000},
244 {"ls", 0x90000000},
245 {"ge", 0xa0000000},
246 {"lt", 0xb0000000},
247 {"gt", 0xc0000000},
248 {"le", 0xd0000000},
249 {"al", 0xe0000000},
250 {"nv", 0xf0000000}
251 };
252
253 /* Warning: If the top bit of the set_bits is set, then the standard
254 instruction bitmask is ignored, and the new bitmask is taken from
255 the set_bits: */
256 struct asm_flg
257 {
258 CONST char * template; /* Basic flag string. */
259 unsigned long set_bits; /* Bits to set. */
260 };
261
262 static CONST struct asm_flg s_flag[] =
263 {
264 {"s", CONDS_BIT},
265 {NULL, 0}
266 };
267
268 static CONST struct asm_flg ldr_flags[] =
269 {
270 {"b", 0x00400000},
271 {"t", TRANS_BIT},
272 {"bt", 0x00400000 | TRANS_BIT},
273 {"h", 0x801000b0},
274 {"sh", 0x801000f0},
275 {"sb", 0x801000d0},
276 {NULL, 0}
277 };
278
279 static CONST struct asm_flg str_flags[] =
280 {
281 {"b", 0x00400000},
282 {"t", TRANS_BIT},
283 {"bt", 0x00400000 | TRANS_BIT},
284 {"h", 0x800000b0},
285 {NULL, 0}
286 };
287
288 static CONST struct asm_flg byte_flag[] =
289 {
290 {"b", 0x00400000},
291 {NULL, 0}
292 };
293
294 static CONST struct asm_flg cmp_flags[] =
295 {
296 {"s", CONDS_BIT},
297 {"p", 0x0010f000},
298 {NULL, 0}
299 };
300
301 static CONST struct asm_flg ldm_flags[] =
302 {
303 {"ed", 0x01800000},
304 {"fd", 0x00800000},
305 {"ea", 0x01000000},
306 {"fa", 0x08000000},
307 {"ib", 0x01800000},
308 {"ia", 0x00800000},
309 {"db", 0x01000000},
310 {"da", 0x08000000},
311 {NULL, 0}
312 };
313
314 static CONST struct asm_flg stm_flags[] =
315 {
316 {"ed", 0x08000000},
317 {"fd", 0x01000000},
318 {"ea", 0x00800000},
319 {"fa", 0x01800000},
320 {"ib", 0x01800000},
321 {"ia", 0x00800000},
322 {"db", 0x01000000},
323 {"da", 0x08000000},
324 {NULL, 0}
325 };
326
327 static CONST struct asm_flg lfm_flags[] =
328 {
329 {"fd", 0x00800000},
330 {"ea", 0x01000000},
331 {NULL, 0}
332 };
333
334 static CONST struct asm_flg sfm_flags[] =
335 {
336 {"fd", 0x01000000},
337 {"ea", 0x00800000},
338 {NULL, 0}
339 };
340
341 static CONST struct asm_flg round_flags[] =
342 {
343 {"p", 0x00000020},
344 {"m", 0x00000040},
345 {"z", 0x00000060},
346 {NULL, 0}
347 };
348
349 /* The implementation of the FIX instruction is broken on some assemblers,
350 in that it accepts a precision specifier as well as a rounding specifier,
351 despite the fact that this is meaningless. To be more compatible, we
352 accept it as well, though of course it does not set any bits. */
353 static CONST struct asm_flg fix_flags[] =
354 {
355 {"p", 0x00000020},
356 {"m", 0x00000040},
357 {"z", 0x00000060},
358 {"sp", 0x00000020},
359 {"sm", 0x00000040},
360 {"sz", 0x00000060},
361 {"dp", 0x00000020},
362 {"dm", 0x00000040},
363 {"dz", 0x00000060},
364 {"ep", 0x00000020},
365 {"em", 0x00000040},
366 {"ez", 0x00000060},
367 {NULL, 0}
368 };
369
370 static CONST struct asm_flg except_flag[] =
371 {
372 {"e", 0x00400000},
373 {NULL, 0}
374 };
375
376 static CONST struct asm_flg cplong_flag[] =
377 {
378 {"l", 0x00400000},
379 {NULL, 0}
380 };
381
382 struct asm_psr
383 {
384 CONST char * template;
385 boolean cpsr;
386 unsigned long field;
387 };
388
389 /* The bit that distnguishes CPSR and SPSR. */
390 #define SPSR_BIT (1 << 22)
391
392 /* How many bits to shift the PSR_xxx bits up by. */
393 #define PSR_SHIFT 16
394
395 #define PSR_c (1 << 0)
396 #define PSR_x (1 << 1)
397 #define PSR_s (1 << 2)
398 #define PSR_f (1 << 3)
399
400 static CONST struct asm_psr psrs[] =
401 {
402 {"CPSR", true, PSR_c | PSR_f},
403 {"CPSR_all", true, PSR_c | PSR_f},
404 {"SPSR", false, PSR_c | PSR_f},
405 {"SPSR_all", false, PSR_c | PSR_f},
406 {"CPSR_flg", true, PSR_f},
407 {"CPSR_f", true, PSR_f},
408 {"SPSR_flg", false, PSR_f},
409 {"SPSR_f", false, PSR_f},
410 {"CPSR_c", true, PSR_c},
411 {"CPSR_ctl", true, PSR_c},
412 {"SPSR_c", false, PSR_c},
413 {"SPSR_ctl", false, PSR_c},
414 {"CPSR_x", true, PSR_x},
415 {"CPSR_s", true, PSR_s},
416 {"SPSR_x", false, PSR_x},
417 {"SPSR_s", false, PSR_s},
418 /* Combinations of flags. */
419 {"CPSR_fs", true, PSR_f | PSR_s},
420 {"CPSR_fx", true, PSR_f | PSR_x},
421 {"CPSR_fc", true, PSR_f | PSR_c},
422 {"CPSR_sf", true, PSR_s | PSR_f},
423 {"CPSR_sx", true, PSR_s | PSR_x},
424 {"CPSR_sc", true, PSR_s | PSR_c},
425 {"CPSR_xf", true, PSR_x | PSR_f},
426 {"CPSR_xs", true, PSR_x | PSR_s},
427 {"CPSR_xc", true, PSR_x | PSR_c},
428 {"CPSR_cf", true, PSR_c | PSR_f},
429 {"CPSR_cs", true, PSR_c | PSR_s},
430 {"CPSR_cx", true, PSR_c | PSR_x},
431 {"CPSR_fsx", true, PSR_f | PSR_s | PSR_x},
432 {"CPSR_fsc", true, PSR_f | PSR_s | PSR_c},
433 {"CPSR_fxs", true, PSR_f | PSR_x | PSR_s},
434 {"CPSR_fxc", true, PSR_f | PSR_x | PSR_c},
435 {"CPSR_fcs", true, PSR_f | PSR_c | PSR_s},
436 {"CPSR_fcx", true, PSR_f | PSR_c | PSR_x},
437 {"CPSR_sfx", true, PSR_s | PSR_f | PSR_x},
438 {"CPSR_sfc", true, PSR_s | PSR_f | PSR_c},
439 {"CPSR_sxf", true, PSR_s | PSR_x | PSR_f},
440 {"CPSR_sxc", true, PSR_s | PSR_x | PSR_c},
441 {"CPSR_scf", true, PSR_s | PSR_c | PSR_f},
442 {"CPSR_scx", true, PSR_s | PSR_c | PSR_x},
443 {"CPSR_xfs", true, PSR_x | PSR_f | PSR_s},
444 {"CPSR_xfc", true, PSR_x | PSR_f | PSR_c},
445 {"CPSR_xsf", true, PSR_x | PSR_s | PSR_f},
446 {"CPSR_xsc", true, PSR_x | PSR_s | PSR_c},
447 {"CPSR_xcf", true, PSR_x | PSR_c | PSR_f},
448 {"CPSR_xcs", true, PSR_x | PSR_c | PSR_s},
449 {"CPSR_cfs", true, PSR_c | PSR_f | PSR_s},
450 {"CPSR_cfx", true, PSR_c | PSR_f | PSR_x},
451 {"CPSR_csf", true, PSR_c | PSR_s | PSR_f},
452 {"CPSR_csx", true, PSR_c | PSR_s | PSR_x},
453 {"CPSR_cxf", true, PSR_c | PSR_x | PSR_f},
454 {"CPSR_cxs", true, PSR_c | PSR_x | PSR_s},
455 {"CPSR_fsxc", true, PSR_f | PSR_s | PSR_x | PSR_c},
456 {"CPSR_fscx", true, PSR_f | PSR_s | PSR_c | PSR_x},
457 {"CPSR_fxsc", true, PSR_f | PSR_x | PSR_s | PSR_c},
458 {"CPSR_fxcs", true, PSR_f | PSR_x | PSR_c | PSR_s},
459 {"CPSR_fcsx", true, PSR_f | PSR_c | PSR_s | PSR_x},
460 {"CPSR_fcxs", true, PSR_f | PSR_c | PSR_x | PSR_s},
461 {"CPSR_sfxc", true, PSR_s | PSR_f | PSR_x | PSR_c},
462 {"CPSR_sfcx", true, PSR_s | PSR_f | PSR_c | PSR_x},
463 {"CPSR_sxfc", true, PSR_s | PSR_x | PSR_f | PSR_c},
464 {"CPSR_sxcf", true, PSR_s | PSR_x | PSR_c | PSR_f},
465 {"CPSR_scfx", true, PSR_s | PSR_c | PSR_f | PSR_x},
466 {"CPSR_scxf", true, PSR_s | PSR_c | PSR_x | PSR_f},
467 {"CPSR_xfsc", true, PSR_x | PSR_f | PSR_s | PSR_c},
468 {"CPSR_xfcs", true, PSR_x | PSR_f | PSR_c | PSR_s},
469 {"CPSR_xsfc", true, PSR_x | PSR_s | PSR_f | PSR_c},
470 {"CPSR_xscf", true, PSR_x | PSR_s | PSR_c | PSR_f},
471 {"CPSR_xcfs", true, PSR_x | PSR_c | PSR_f | PSR_s},
472 {"CPSR_xcsf", true, PSR_x | PSR_c | PSR_s | PSR_f},
473 {"CPSR_cfsx", true, PSR_c | PSR_f | PSR_s | PSR_x},
474 {"CPSR_cfxs", true, PSR_c | PSR_f | PSR_x | PSR_s},
475 {"CPSR_csfx", true, PSR_c | PSR_s | PSR_f | PSR_x},
476 {"CPSR_csxf", true, PSR_c | PSR_s | PSR_x | PSR_f},
477 {"CPSR_cxfs", true, PSR_c | PSR_x | PSR_f | PSR_s},
478 {"CPSR_cxsf", true, PSR_c | PSR_x | PSR_s | PSR_f},
479 {"SPSR_fs", false, PSR_f | PSR_s},
480 {"SPSR_fx", false, PSR_f | PSR_x},
481 {"SPSR_fc", false, PSR_f | PSR_c},
482 {"SPSR_sf", false, PSR_s | PSR_f},
483 {"SPSR_sx", false, PSR_s | PSR_x},
484 {"SPSR_sc", false, PSR_s | PSR_c},
485 {"SPSR_xf", false, PSR_x | PSR_f},
486 {"SPSR_xs", false, PSR_x | PSR_s},
487 {"SPSR_xc", false, PSR_x | PSR_c},
488 {"SPSR_cf", false, PSR_c | PSR_f},
489 {"SPSR_cs", false, PSR_c | PSR_s},
490 {"SPSR_cx", false, PSR_c | PSR_x},
491 {"SPSR_fsx", false, PSR_f | PSR_s | PSR_x},
492 {"SPSR_fsc", false, PSR_f | PSR_s | PSR_c},
493 {"SPSR_fxs", false, PSR_f | PSR_x | PSR_s},
494 {"SPSR_fxc", false, PSR_f | PSR_x | PSR_c},
495 {"SPSR_fcs", false, PSR_f | PSR_c | PSR_s},
496 {"SPSR_fcx", false, PSR_f | PSR_c | PSR_x},
497 {"SPSR_sfx", false, PSR_s | PSR_f | PSR_x},
498 {"SPSR_sfc", false, PSR_s | PSR_f | PSR_c},
499 {"SPSR_sxf", false, PSR_s | PSR_x | PSR_f},
500 {"SPSR_sxc", false, PSR_s | PSR_x | PSR_c},
501 {"SPSR_scf", false, PSR_s | PSR_c | PSR_f},
502 {"SPSR_scx", false, PSR_s | PSR_c | PSR_x},
503 {"SPSR_xfs", false, PSR_x | PSR_f | PSR_s},
504 {"SPSR_xfc", false, PSR_x | PSR_f | PSR_c},
505 {"SPSR_xsf", false, PSR_x | PSR_s | PSR_f},
506 {"SPSR_xsc", false, PSR_x | PSR_s | PSR_c},
507 {"SPSR_xcf", false, PSR_x | PSR_c | PSR_f},
508 {"SPSR_xcs", false, PSR_x | PSR_c | PSR_s},
509 {"SPSR_cfs", false, PSR_c | PSR_f | PSR_s},
510 {"SPSR_cfx", false, PSR_c | PSR_f | PSR_x},
511 {"SPSR_csf", false, PSR_c | PSR_s | PSR_f},
512 {"SPSR_csx", false, PSR_c | PSR_s | PSR_x},
513 {"SPSR_cxf", false, PSR_c | PSR_x | PSR_f},
514 {"SPSR_cxs", false, PSR_c | PSR_x | PSR_s},
515 {"SPSR_fsxc", false, PSR_f | PSR_s | PSR_x | PSR_c},
516 {"SPSR_fscx", false, PSR_f | PSR_s | PSR_c | PSR_x},
517 {"SPSR_fxsc", false, PSR_f | PSR_x | PSR_s | PSR_c},
518 {"SPSR_fxcs", false, PSR_f | PSR_x | PSR_c | PSR_s},
519 {"SPSR_fcsx", false, PSR_f | PSR_c | PSR_s | PSR_x},
520 {"SPSR_fcxs", false, PSR_f | PSR_c | PSR_x | PSR_s},
521 {"SPSR_sfxc", false, PSR_s | PSR_f | PSR_x | PSR_c},
522 {"SPSR_sfcx", false, PSR_s | PSR_f | PSR_c | PSR_x},
523 {"SPSR_sxfc", false, PSR_s | PSR_x | PSR_f | PSR_c},
524 {"SPSR_sxcf", false, PSR_s | PSR_x | PSR_c | PSR_f},
525 {"SPSR_scfx", false, PSR_s | PSR_c | PSR_f | PSR_x},
526 {"SPSR_scxf", false, PSR_s | PSR_c | PSR_x | PSR_f},
527 {"SPSR_xfsc", false, PSR_x | PSR_f | PSR_s | PSR_c},
528 {"SPSR_xfcs", false, PSR_x | PSR_f | PSR_c | PSR_s},
529 {"SPSR_xsfc", false, PSR_x | PSR_s | PSR_f | PSR_c},
530 {"SPSR_xscf", false, PSR_x | PSR_s | PSR_c | PSR_f},
531 {"SPSR_xcfs", false, PSR_x | PSR_c | PSR_f | PSR_s},
532 {"SPSR_xcsf", false, PSR_x | PSR_c | PSR_s | PSR_f},
533 {"SPSR_cfsx", false, PSR_c | PSR_f | PSR_s | PSR_x},
534 {"SPSR_cfxs", false, PSR_c | PSR_f | PSR_x | PSR_s},
535 {"SPSR_csfx", false, PSR_c | PSR_s | PSR_f | PSR_x},
536 {"SPSR_csxf", false, PSR_c | PSR_s | PSR_x | PSR_f},
537 {"SPSR_cxfs", false, PSR_c | PSR_x | PSR_f | PSR_s},
538 {"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f},
539 /* For backwards compatability with older toolchain we also
540 support lower case versions of some of these flags. */
541 {"cpsr", true, PSR_c | PSR_f},
542 {"cpsr_all", true, PSR_c | PSR_f},
543 {"spsr", false, PSR_c | PSR_f},
544 {"spsr_all", false, PSR_c | PSR_f},
545 {"cpsr_flg", true, PSR_f},
546 {"cpsr_f", true, PSR_f},
547 {"spsr_flg", false, PSR_f},
548 {"spsr_f", false, PSR_f},
549 {"cpsr_c", true, PSR_c},
550 {"cpsr_ctl", true, PSR_c},
551 {"spsr_c", false, PSR_c},
552 {"spsr_ctl", false, PSR_c}
553 };
554
555 /* Functions called by parser. */
556 /* ARM instructions. */
557 static void do_arit PARAMS ((char *, unsigned long));
558 static void do_cmp PARAMS ((char *, unsigned long));
559 static void do_mov PARAMS ((char *, unsigned long));
560 static void do_ldst PARAMS ((char *, unsigned long));
561 static void do_ldmstm PARAMS ((char *, unsigned long));
562 static void do_branch PARAMS ((char *, unsigned long));
563 static void do_swi PARAMS ((char *, unsigned long));
564 /* Pseudo Op codes. */
565 static void do_adr PARAMS ((char *, unsigned long));
566 static void do_adrl PARAMS ((char *, unsigned long));
567 static void do_nop PARAMS ((char *, unsigned long));
568 /* ARM 2. */
569 static void do_mul PARAMS ((char *, unsigned long));
570 static void do_mla PARAMS ((char *, unsigned long));
571 /* ARM 3. */
572 static void do_swap PARAMS ((char *, unsigned long));
573 /* ARM 6. */
574 static void do_msr PARAMS ((char *, unsigned long));
575 static void do_mrs PARAMS ((char *, unsigned long));
576 /* ARM 7M. */
577 static void do_mull PARAMS ((char *, unsigned long));
578 /* ARM THUMB. */
579 static void do_bx PARAMS ((char *, unsigned long));
580
581 /* Coprocessor Instructions. */
582 static void do_cdp PARAMS ((char *, unsigned long));
583 static void do_lstc PARAMS ((char *, unsigned long));
584 static void do_co_reg PARAMS ((char *, unsigned long));
585 static void do_fp_ctrl PARAMS ((char *, unsigned long));
586 static void do_fp_ldst PARAMS ((char *, unsigned long));
587 static void do_fp_ldmstm PARAMS ((char *, unsigned long));
588 static void do_fp_dyadic PARAMS ((char *, unsigned long));
589 static void do_fp_monadic PARAMS ((char *, unsigned long));
590 static void do_fp_cmp PARAMS ((char *, unsigned long));
591 static void do_fp_from_reg PARAMS ((char *, unsigned long));
592 static void do_fp_to_reg PARAMS ((char *, unsigned long));
593
594 static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
595 static int arm_reg_parse PARAMS ((char **));
596 static CONST struct asm_psr * arm_psr_parse PARAMS ((char **));
597 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
598 static int add_to_lit_pool PARAMS ((void));
599 static unsigned validate_immediate PARAMS ((unsigned));
600 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
601 static int validate_offset_imm PARAMS ((unsigned int, int));
602 static void opcode_select PARAMS ((int));
603 static void end_of_line PARAMS ((char *));
604 static int reg_required_here PARAMS ((char **, int));
605 static int psr_required_here PARAMS ((char **));
606 static int co_proc_number PARAMS ((char **));
607 static int cp_opc_expr PARAMS ((char **, int, int));
608 static int cp_reg_required_here PARAMS ((char **, int));
609 static int fp_reg_required_here PARAMS ((char **, int));
610 static int cp_address_offset PARAMS ((char **));
611 static int cp_address_required_here PARAMS ((char **));
612 static int my_get_float_expression PARAMS ((char **));
613 static int skip_past_comma PARAMS ((char **));
614 static int walk_no_bignums PARAMS ((symbolS *));
615 static int negate_data_op PARAMS ((unsigned long *, unsigned long));
616 static int data_op2 PARAMS ((char **));
617 static int fp_op2 PARAMS ((char **));
618 static long reg_list PARAMS ((char **));
619 static void thumb_load_store PARAMS ((char *, int, int));
620 static int decode_shift PARAMS ((char **, int));
621 static int ldst_extend PARAMS ((char **, int));
622 static void thumb_add_sub PARAMS ((char *, int));
623 static void insert_reg PARAMS ((int));
624 static void thumb_shift PARAMS ((char *, int));
625 static void thumb_mov_compare PARAMS ((char *, int));
626 static void set_constant_flonums PARAMS ((void));
627 static valueT md_chars_to_number PARAMS ((char *, int));
628 static void insert_reg_alias PARAMS ((char *, int));
629 static void output_inst PARAMS ((void));
630 #ifdef OBJ_ELF
631 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
632 #endif
633
634 /* ARM instructions take 4bytes in the object file, Thumb instructions
635 take 2: */
636 #define INSN_SIZE 4
637
638 /* LONGEST_INST is the longest basic instruction name without conditions or
639 flags. ARM7M has 4 of length 5. */
640
641 #define LONGEST_INST 5
642
643 struct asm_opcode
644 {
645 /* Basic string to match. */
646 CONST char * template;
647
648 /* Basic instruction code. */
649 unsigned long value;
650
651 /* Compulsory suffix that must follow conds. If "", then the
652 instruction is not conditional and must have no suffix. */
653 CONST char * comp_suffix;
654
655 /* Bits to toggle if flag 'n' set. */
656 CONST struct asm_flg * flags;
657
658 /* Which CPU variants this exists for. */
659 unsigned long variants;
660
661 /* Function to call to parse args. */
662 void (* parms) PARAMS ((char *, unsigned long));
663 };
664
665 static CONST struct asm_opcode insns[] =
666 {
667 /* ARM Instructions. */
668 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
669 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
670 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
671 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
672 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
673 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
674 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
675 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
676 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
677 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
678 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
679 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
680 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
681 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
682 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
683 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
684 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
685 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
686 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
687 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
688 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
689 #ifdef TE_WINCE
690 {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch},
691 {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},
692 #else
693 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
694 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
695 #endif
696
697 /* Pseudo ops. */
698 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
699 {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
700 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
701
702 /* ARM 2 multiplies. */
703 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
704 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
705
706 /* ARM 3 - swp instructions. */
707 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
708
709 /* ARM 6 Coprocessor instructions. */
710 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
711 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
712 /* ScottB: our code uses 0x0128f000 for msr.
713 NickC: but this is wrong because the bits 16 through 19 are
714 handled by the PSR_xxx defines above. */
715
716 /* ARM 7M long multiplies - need signed/unsigned flags! */
717 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
718 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
719 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
720 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
721
722 /* ARM THUMB interworking. */
723 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
724
725 /* Floating point instructions. */
726 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
727 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
728 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
729 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
730 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
731 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
732 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
733 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
734 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
735 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
736 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
737 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
738 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
739 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
740 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
741 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
742 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
743 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
744 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
745 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
746 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
747 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
748 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
749 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
750 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
751 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
752 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
753 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
754 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
755 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
756 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
757 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
758 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
759 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
760 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
761 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
762 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
763 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
764 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
765 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
766 be an optional suffix, but part of the instruction. To be compatible,
767 we accept either. */
768 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
769 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
770 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
771 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
772
773 /* Generic copressor instructions. */
774 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
775 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
776 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
777 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
778 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
779 };
780
781 /* Defines for various bits that we will want to toggle. */
782 #define INST_IMMEDIATE 0x02000000
783 #define OFFSET_REG 0x02000000
784 #define HWOFFSET_IMM 0x00400000
785 #define SHIFT_BY_REG 0x00000010
786 #define PRE_INDEX 0x01000000
787 #define INDEX_UP 0x00800000
788 #define WRITE_BACK 0x00200000
789 #define LDM_TYPE_2_OR_3 0x00400000
790
791 #define LITERAL_MASK 0xf000f000
792 #define COND_MASK 0xf0000000
793 #define OPCODE_MASK 0xfe1fffff
794 #define DATA_OP_SHIFT 21
795
796 /* Codes to distinguish the arithmetic instructions. */
797 #define OPCODE_AND 0
798 #define OPCODE_EOR 1
799 #define OPCODE_SUB 2
800 #define OPCODE_RSB 3
801 #define OPCODE_ADD 4
802 #define OPCODE_ADC 5
803 #define OPCODE_SBC 6
804 #define OPCODE_RSC 7
805 #define OPCODE_TST 8
806 #define OPCODE_TEQ 9
807 #define OPCODE_CMP 10
808 #define OPCODE_CMN 11
809 #define OPCODE_ORR 12
810 #define OPCODE_MOV 13
811 #define OPCODE_BIC 14
812 #define OPCODE_MVN 15
813
814 static void do_t_nop PARAMS ((char *));
815 static void do_t_arit PARAMS ((char *));
816 static void do_t_add PARAMS ((char *));
817 static void do_t_asr PARAMS ((char *));
818 static void do_t_branch9 PARAMS ((char *));
819 static void do_t_branch12 PARAMS ((char *));
820 static void do_t_branch23 PARAMS ((char *));
821 static void do_t_bx PARAMS ((char *));
822 static void do_t_compare PARAMS ((char *));
823 static void do_t_ldmstm PARAMS ((char *));
824 static void do_t_ldr PARAMS ((char *));
825 static void do_t_ldrb PARAMS ((char *));
826 static void do_t_ldrh PARAMS ((char *));
827 static void do_t_lds PARAMS ((char *));
828 static void do_t_lsl PARAMS ((char *));
829 static void do_t_lsr PARAMS ((char *));
830 static void do_t_mov PARAMS ((char *));
831 static void do_t_push_pop PARAMS ((char *));
832 static void do_t_str PARAMS ((char *));
833 static void do_t_strb PARAMS ((char *));
834 static void do_t_strh PARAMS ((char *));
835 static void do_t_sub PARAMS ((char *));
836 static void do_t_swi PARAMS ((char *));
837 static void do_t_adr PARAMS ((char *));
838
839 #define T_OPCODE_MUL 0x4340
840 #define T_OPCODE_TST 0x4200
841 #define T_OPCODE_CMN 0x42c0
842 #define T_OPCODE_NEG 0x4240
843 #define T_OPCODE_MVN 0x43c0
844
845 #define T_OPCODE_ADD_R3 0x1800
846 #define T_OPCODE_SUB_R3 0x1a00
847 #define T_OPCODE_ADD_HI 0x4400
848 #define T_OPCODE_ADD_ST 0xb000
849 #define T_OPCODE_SUB_ST 0xb080
850 #define T_OPCODE_ADD_SP 0xa800
851 #define T_OPCODE_ADD_PC 0xa000
852 #define T_OPCODE_ADD_I8 0x3000
853 #define T_OPCODE_SUB_I8 0x3800
854 #define T_OPCODE_ADD_I3 0x1c00
855 #define T_OPCODE_SUB_I3 0x1e00
856
857 #define T_OPCODE_ASR_R 0x4100
858 #define T_OPCODE_LSL_R 0x4080
859 #define T_OPCODE_LSR_R 0x40c0
860 #define T_OPCODE_ASR_I 0x1000
861 #define T_OPCODE_LSL_I 0x0000
862 #define T_OPCODE_LSR_I 0x0800
863
864 #define T_OPCODE_MOV_I8 0x2000
865 #define T_OPCODE_CMP_I8 0x2800
866 #define T_OPCODE_CMP_LR 0x4280
867 #define T_OPCODE_MOV_HR 0x4600
868 #define T_OPCODE_CMP_HR 0x4500
869
870 #define T_OPCODE_LDR_PC 0x4800
871 #define T_OPCODE_LDR_SP 0x9800
872 #define T_OPCODE_STR_SP 0x9000
873 #define T_OPCODE_LDR_IW 0x6800
874 #define T_OPCODE_STR_IW 0x6000
875 #define T_OPCODE_LDR_IH 0x8800
876 #define T_OPCODE_STR_IH 0x8000
877 #define T_OPCODE_LDR_IB 0x7800
878 #define T_OPCODE_STR_IB 0x7000
879 #define T_OPCODE_LDR_RW 0x5800
880 #define T_OPCODE_STR_RW 0x5000
881 #define T_OPCODE_LDR_RH 0x5a00
882 #define T_OPCODE_STR_RH 0x5200
883 #define T_OPCODE_LDR_RB 0x5c00
884 #define T_OPCODE_STR_RB 0x5400
885
886 #define T_OPCODE_PUSH 0xb400
887 #define T_OPCODE_POP 0xbc00
888
889 #define T_OPCODE_BRANCH 0xe7fe
890
891 static int thumb_reg PARAMS ((char ** str, int hi_lo));
892
893 #define THUMB_SIZE 2 /* Size of thumb instruction. */
894 #define THUMB_REG_LO 0x1
895 #define THUMB_REG_HI 0x2
896 #define THUMB_REG_ANY 0x3
897
898 #define THUMB_H1 0x0080
899 #define THUMB_H2 0x0040
900
901 #define THUMB_ASR 0
902 #define THUMB_LSL 1
903 #define THUMB_LSR 2
904
905 #define THUMB_MOVE 0
906 #define THUMB_COMPARE 1
907
908 #define THUMB_LOAD 0
909 #define THUMB_STORE 1
910
911 #define THUMB_PP_PC_LR 0x0100
912
913 /* These three are used for immediate shifts, do not alter. */
914 #define THUMB_WORD 2
915 #define THUMB_HALFWORD 1
916 #define THUMB_BYTE 0
917
918 struct thumb_opcode
919 {
920 /* Basic string to match. */
921 CONST char * template;
922
923 /* Basic instruction code. */
924 unsigned long value;
925
926 int size;
927
928 /* Which CPU variants this exists for. */
929 unsigned long variants;
930
931 /* Function to call to parse args. */
932 void (* parms) PARAMS ((char *));
933 };
934
935 static CONST struct thumb_opcode tinsns[] =
936 {
937 {"adc", 0x4140, 2, ARM_THUMB, do_t_arit},
938 {"add", 0x0000, 2, ARM_THUMB, do_t_add},
939 {"and", 0x4000, 2, ARM_THUMB, do_t_arit},
940 {"asr", 0x0000, 2, ARM_THUMB, do_t_asr},
941 {"b", T_OPCODE_BRANCH, 2, ARM_THUMB, do_t_branch12},
942 {"beq", 0xd0fe, 2, ARM_THUMB, do_t_branch9},
943 {"bne", 0xd1fe, 2, ARM_THUMB, do_t_branch9},
944 {"bcs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
945 {"bhs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
946 {"bcc", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
947 {"bul", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
948 {"blo", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
949 {"bmi", 0xd4fe, 2, ARM_THUMB, do_t_branch9},
950 {"bpl", 0xd5fe, 2, ARM_THUMB, do_t_branch9},
951 {"bvs", 0xd6fe, 2, ARM_THUMB, do_t_branch9},
952 {"bvc", 0xd7fe, 2, ARM_THUMB, do_t_branch9},
953 {"bhi", 0xd8fe, 2, ARM_THUMB, do_t_branch9},
954 {"bls", 0xd9fe, 2, ARM_THUMB, do_t_branch9},
955 {"bge", 0xdafe, 2, ARM_THUMB, do_t_branch9},
956 {"blt", 0xdbfe, 2, ARM_THUMB, do_t_branch9},
957 {"bgt", 0xdcfe, 2, ARM_THUMB, do_t_branch9},
958 {"ble", 0xddfe, 2, ARM_THUMB, do_t_branch9},
959 {"bal", 0xdefe, 2, ARM_THUMB, do_t_branch9},
960 {"bic", 0x4380, 2, ARM_THUMB, do_t_arit},
961 {"bl", 0xf7fffffe, 4, ARM_THUMB, do_t_branch23},
962 {"bx", 0x4700, 2, ARM_THUMB, do_t_bx},
963 {"cmn", T_OPCODE_CMN, 2, ARM_THUMB, do_t_arit},
964 {"cmp", 0x0000, 2, ARM_THUMB, do_t_compare},
965 {"eor", 0x4040, 2, ARM_THUMB, do_t_arit},
966 {"ldmia", 0xc800, 2, ARM_THUMB, do_t_ldmstm},
967 {"ldr", 0x0000, 2, ARM_THUMB, do_t_ldr},
968 {"ldrb", 0x0000, 2, ARM_THUMB, do_t_ldrb},
969 {"ldrh", 0x0000, 2, ARM_THUMB, do_t_ldrh},
970 {"ldrsb", 0x5600, 2, ARM_THUMB, do_t_lds},
971 {"ldrsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
972 {"ldsb", 0x5600, 2, ARM_THUMB, do_t_lds},
973 {"ldsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
974 {"lsl", 0x0000, 2, ARM_THUMB, do_t_lsl},
975 {"lsr", 0x0000, 2, ARM_THUMB, do_t_lsr},
976 {"mov", 0x0000, 2, ARM_THUMB, do_t_mov},
977 {"mul", T_OPCODE_MUL, 2, ARM_THUMB, do_t_arit},
978 {"mvn", T_OPCODE_MVN, 2, ARM_THUMB, do_t_arit},
979 {"neg", T_OPCODE_NEG, 2, ARM_THUMB, do_t_arit},
980 {"orr", 0x4300, 2, ARM_THUMB, do_t_arit},
981 {"pop", 0xbc00, 2, ARM_THUMB, do_t_push_pop},
982 {"push", 0xb400, 2, ARM_THUMB, do_t_push_pop},
983 {"ror", 0x41c0, 2, ARM_THUMB, do_t_arit},
984 {"sbc", 0x4180, 2, ARM_THUMB, do_t_arit},
985 {"stmia", 0xc000, 2, ARM_THUMB, do_t_ldmstm},
986 {"str", 0x0000, 2, ARM_THUMB, do_t_str},
987 {"strb", 0x0000, 2, ARM_THUMB, do_t_strb},
988 {"strh", 0x0000, 2, ARM_THUMB, do_t_strh},
989 {"swi", 0xdf00, 2, ARM_THUMB, do_t_swi},
990 {"sub", 0x0000, 2, ARM_THUMB, do_t_sub},
991 {"tst", T_OPCODE_TST, 2, ARM_THUMB, do_t_arit},
992 /* Pseudo ops: */
993 {"adr", 0x0000, 2, ARM_THUMB, do_t_adr},
994 {"nop", 0x46C0, 2, ARM_THUMB, do_t_nop}, /* mov r8,r8 */
995 };
996
997 struct reg_entry
998 {
999 CONST char * name;
1000 int number;
1001 };
1002
1003 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
1004 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
1005 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
1006
1007 #define REG_PC 15
1008 #define REG_LR 14
1009 #define REG_SP 13
1010
1011 /* These are the standard names. Users can add aliases with .req. */
1012 static CONST struct reg_entry reg_table[] =
1013 {
1014 /* Processor Register Numbers. */
1015 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
1016 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
1017 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
1018 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
1019 /* APCS conventions. */
1020 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
1021 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
1022 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
1023 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
1024 /* ATPCS additions to APCS conventions. */
1025 {"wr", 7}, {"v8", 11},
1026 /* FP Registers. */
1027 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
1028 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
1029 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
1030 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
1031 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
1032 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
1033 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
1034 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
1035 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
1036 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
1037 /* ATPCS additions to float register names. */
1038 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
1039 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
1040 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
1041 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
1042 /* FIXME: At some point we need to add VFP register names. */
1043 /* Array terminator. */
1044 {NULL, 0}
1045 };
1046
1047 #define BAD_ARGS _("Bad arguments to instruction")
1048 #define BAD_PC _("r15 not allowed here")
1049 #define BAD_FLAGS _("Instruction should not have flags")
1050 #define BAD_COND _("Instruction is not conditional")
1051
1052 static struct hash_control * arm_ops_hsh = NULL;
1053 static struct hash_control * arm_tops_hsh = NULL;
1054 static struct hash_control * arm_cond_hsh = NULL;
1055 static struct hash_control * arm_shift_hsh = NULL;
1056 static struct hash_control * arm_reg_hsh = NULL;
1057 static struct hash_control * arm_psr_hsh = NULL;
1058
1059 /* This table describes all the machine specific pseudo-ops the assembler
1060 has to support. The fields are:
1061 pseudo-op name without dot
1062 function to call to execute this pseudo-op
1063 Integer arg to pass to the function. */
1064
1065 static void s_req PARAMS ((int));
1066 static void s_align PARAMS ((int));
1067 static void s_bss PARAMS ((int));
1068 static void s_even PARAMS ((int));
1069 static void s_ltorg PARAMS ((int));
1070 static void s_arm PARAMS ((int));
1071 static void s_thumb PARAMS ((int));
1072 static void s_code PARAMS ((int));
1073 static void s_force_thumb PARAMS ((int));
1074 static void s_thumb_func PARAMS ((int));
1075 static void s_thumb_set PARAMS ((int));
1076 static void arm_s_text PARAMS ((int));
1077 static void arm_s_data PARAMS ((int));
1078 #ifdef OBJ_ELF
1079 static void arm_s_section PARAMS ((int));
1080 static void s_arm_elf_cons PARAMS ((int));
1081 #endif
1082
1083 static int my_get_expression PARAMS ((expressionS *, char **));
1084
1085 CONST pseudo_typeS md_pseudo_table[] =
1086 {
1087 /* Never called becasue '.req' does not start line. */
1088 { "req", s_req, 0 },
1089 { "bss", s_bss, 0 },
1090 { "align", s_align, 0 },
1091 { "arm", s_arm, 0 },
1092 { "thumb", s_thumb, 0 },
1093 { "code", s_code, 0 },
1094 { "force_thumb", s_force_thumb, 0 },
1095 { "thumb_func", s_thumb_func, 0 },
1096 { "thumb_set", s_thumb_set, 0 },
1097 { "even", s_even, 0 },
1098 { "ltorg", s_ltorg, 0 },
1099 { "pool", s_ltorg, 0 },
1100 /* Allow for the effect of section changes. */
1101 { "text", arm_s_text, 0 },
1102 { "data", arm_s_data, 0 },
1103 #ifdef OBJ_ELF
1104 { "section", arm_s_section, 0 },
1105 { "section.s", arm_s_section, 0 },
1106 { "sect", arm_s_section, 0 },
1107 { "sect.s", arm_s_section, 0 },
1108 { "word", s_arm_elf_cons, 4 },
1109 { "long", s_arm_elf_cons, 4 },
1110 #else
1111 { "word", cons, 4},
1112 #endif
1113 { "extend", float_cons, 'x' },
1114 { "ldouble", float_cons, 'x' },
1115 { "packed", float_cons, 'p' },
1116 { 0, 0, 0 }
1117 };
1118
1119 /* Stuff needed to resolve the label ambiguity
1120 As:
1121 ...
1122 label: <insn>
1123 may differ from:
1124 ...
1125 label:
1126 <insn>
1127 */
1128
1129 symbolS * last_label_seen;
1130 static int label_is_thumb_function_name = false;
1131
1132 /* Literal stuff. */
1133
1134 #define MAX_LITERAL_POOL_SIZE 1024
1135
1136 typedef struct literalS
1137 {
1138 struct expressionS exp;
1139 struct arm_it * inst;
1140 } literalT;
1141
1142 literalT literals[MAX_LITERAL_POOL_SIZE];
1143
1144 /* Next free entry in the pool. */
1145 int next_literal_pool_place = 0;
1146
1147 /* Next literal pool number. */
1148 int lit_pool_num = 1;
1149
1150 symbolS * current_poolP = NULL;
1151
1152 static int
1153 add_to_lit_pool ()
1154 {
1155 int lit_count = 0;
1156
1157 if (current_poolP == NULL)
1158 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
1159 (valueT) 0, &zero_address_frag);
1160
1161 /* Check if this literal value is already in the pool: */
1162 while (lit_count < next_literal_pool_place)
1163 {
1164 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1165 && inst.reloc.exp.X_op == O_constant
1166 && (literals[lit_count].exp.X_add_number
1167 == inst.reloc.exp.X_add_number)
1168 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
1169 break;
1170 lit_count++;
1171 }
1172
1173 if (lit_count == next_literal_pool_place) /* New entry. */
1174 {
1175 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
1176 {
1177 inst.error = _("Literal Pool Overflow");
1178 return FAIL;
1179 }
1180
1181 literals[next_literal_pool_place].exp = inst.reloc.exp;
1182 lit_count = next_literal_pool_place++;
1183 }
1184
1185 inst.reloc.exp.X_op = O_symbol;
1186 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1187 inst.reloc.exp.X_add_symbol = current_poolP;
1188
1189 return SUCCESS;
1190 }
1191
1192 /* Can't use symbol_new here, so have to create a symbol and then at
1193 a later date assign it a value. Thats what these functions do. */
1194
1195 static void
1196 symbol_locate (symbolP, name, segment, valu, frag)
1197 symbolS * symbolP;
1198 CONST char * name; /* It is copied, the caller can modify. */
1199 segT segment; /* Segment identifier (SEG_<something>). */
1200 valueT valu; /* Symbol value. */
1201 fragS * frag; /* Associated fragment. */
1202 {
1203 unsigned int name_length;
1204 char * preserved_copy_of_name;
1205
1206 name_length = strlen (name) + 1; /* +1 for \0. */
1207 obstack_grow (&notes, name, name_length);
1208 preserved_copy_of_name = obstack_finish (&notes);
1209 #ifdef STRIP_UNDERSCORE
1210 if (preserved_copy_of_name[0] == '_')
1211 preserved_copy_of_name++;
1212 #endif
1213
1214 #ifdef tc_canonicalize_symbol_name
1215 preserved_copy_of_name =
1216 tc_canonicalize_symbol_name (preserved_copy_of_name);
1217 #endif
1218
1219 S_SET_NAME (symbolP, preserved_copy_of_name);
1220
1221 S_SET_SEGMENT (symbolP, segment);
1222 S_SET_VALUE (symbolP, valu);
1223 symbol_clear_list_pointers(symbolP);
1224
1225 symbol_set_frag (symbolP, frag);
1226
1227 /* Link to end of symbol chain. */
1228 {
1229 extern int symbol_table_frozen;
1230 if (symbol_table_frozen)
1231 abort ();
1232 }
1233
1234 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1235
1236 obj_symbol_new_hook (symbolP);
1237
1238 #ifdef tc_symbol_new_hook
1239 tc_symbol_new_hook (symbolP);
1240 #endif
1241
1242 #ifdef DEBUG_SYMS
1243 verify_symbol_chain (symbol_rootP, symbol_lastP);
1244 #endif /* DEBUG_SYMS */
1245 }
1246
1247 /* Check that an immediate is valid.
1248 If so, convert it to the right format. */
1249
1250 static unsigned int
1251 validate_immediate (val)
1252 unsigned int val;
1253 {
1254 unsigned int a;
1255 unsigned int i;
1256
1257 #define rotate_left(v, n) (v << n | v >> (32 - n))
1258
1259 for (i = 0; i < 32; i += 2)
1260 if ((a = rotate_left (val, i)) <= 0xff)
1261 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
1262
1263 return FAIL;
1264 }
1265
1266 /* Check to see if an immediate can be computed as two seperate immediate
1267 values, added together. We already know that this value cannot be
1268 computed by just one ARM instruction. */
1269
1270 static unsigned int
1271 validate_immediate_twopart (val, highpart)
1272 unsigned int val;
1273 unsigned int * highpart;
1274 {
1275 unsigned int a;
1276 unsigned int i;
1277
1278 for (i = 0; i < 32; i += 2)
1279 if (((a = rotate_left (val, i)) & 0xff) != 0)
1280 {
1281 if (a & 0xff00)
1282 {
1283 if (a & ~ 0xffff)
1284 continue;
1285 * highpart = (a >> 8) | ((i + 24) << 7);
1286 }
1287 else if (a & 0xff0000)
1288 {
1289 if (a & 0xff000000)
1290 continue;
1291 * highpart = (a >> 16) | ((i + 16) << 7);
1292 }
1293 else
1294 {
1295 assert (a & 0xff000000);
1296 * highpart = (a >> 24) | ((i + 8) << 7);
1297 }
1298
1299 return (a & 0xff) | (i << 7);
1300 }
1301
1302 return FAIL;
1303 }
1304
1305 static int
1306 validate_offset_imm (val, hwse)
1307 unsigned int val;
1308 int hwse;
1309 {
1310 if ((hwse && val > 255) || val > 4095)
1311 return FAIL;
1312 return val;
1313 }
1314
1315 static void
1316 s_req (a)
1317 int a ATTRIBUTE_UNUSED;
1318 {
1319 as_bad (_("Invalid syntax for .req directive."));
1320 }
1321
1322 static void
1323 s_bss (ignore)
1324 int ignore ATTRIBUTE_UNUSED;
1325 {
1326 /* We don't support putting frags in the BSS segment, we fake it by
1327 marking in_bss, then looking at s_skip for clues. */
1328 subseg_set (bss_section, 0);
1329 demand_empty_rest_of_line ();
1330 }
1331
1332 static void
1333 s_even (ignore)
1334 int ignore ATTRIBUTE_UNUSED;
1335 {
1336 /* Never make frag if expect extra pass. */
1337 if (!need_pass_2)
1338 frag_align (1, 0, 0);
1339
1340 record_alignment (now_seg, 1);
1341
1342 demand_empty_rest_of_line ();
1343 }
1344
1345 static void
1346 s_ltorg (ignored)
1347 int ignored ATTRIBUTE_UNUSED;
1348 {
1349 int lit_count = 0;
1350 char sym_name[20];
1351
1352 if (current_poolP == NULL)
1353 return;
1354
1355 /* Align pool as you have word accesses.
1356 Only make a frag if we have to. */
1357 if (!need_pass_2)
1358 frag_align (2, 0, 0);
1359
1360 record_alignment (now_seg, 2);
1361
1362 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1363
1364 symbol_locate (current_poolP, sym_name, now_seg,
1365 (valueT) frag_now_fix (), frag_now);
1366 symbol_table_insert (current_poolP);
1367
1368 ARM_SET_THUMB (current_poolP, thumb_mode);
1369
1370 #if defined OBJ_COFF || defined OBJ_ELF
1371 ARM_SET_INTERWORK (current_poolP, support_interwork);
1372 #endif
1373
1374 while (lit_count < next_literal_pool_place)
1375 /* First output the expression in the instruction to the pool. */
1376 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1377
1378 next_literal_pool_place = 0;
1379 current_poolP = NULL;
1380 }
1381
1382 /* Same as s_align_ptwo but align 0 => align 2. */
1383
1384 static void
1385 s_align (unused)
1386 int unused ATTRIBUTE_UNUSED;
1387 {
1388 register int temp;
1389 register long temp_fill;
1390 long max_alignment = 15;
1391
1392 temp = get_absolute_expression ();
1393 if (temp > max_alignment)
1394 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1395 else if (temp < 0)
1396 {
1397 as_bad (_("Alignment negative. 0 assumed."));
1398 temp = 0;
1399 }
1400
1401 if (*input_line_pointer == ',')
1402 {
1403 input_line_pointer++;
1404 temp_fill = get_absolute_expression ();
1405 }
1406 else
1407 temp_fill = 0;
1408
1409 if (!temp)
1410 temp = 2;
1411
1412 /* Only make a frag if we HAVE to. */
1413 if (temp && !need_pass_2)
1414 frag_align (temp, (int) temp_fill, 0);
1415 demand_empty_rest_of_line ();
1416
1417 record_alignment (now_seg, temp);
1418 }
1419
1420 static void
1421 s_force_thumb (ignore)
1422 int ignore ATTRIBUTE_UNUSED;
1423 {
1424 /* If we are not already in thumb mode go into it, EVEN if
1425 the target processor does not support thumb instructions.
1426 This is used by gcc/config/arm/lib1funcs.asm for example
1427 to compile interworking support functions even if the
1428 target processor should not support interworking. */
1429 if (! thumb_mode)
1430 {
1431 thumb_mode = 2;
1432
1433 record_alignment (now_seg, 1);
1434 }
1435
1436 demand_empty_rest_of_line ();
1437 }
1438
1439 static void
1440 s_thumb_func (ignore)
1441 int ignore ATTRIBUTE_UNUSED;
1442 {
1443 if (! thumb_mode)
1444 opcode_select (16);
1445
1446 /* The following label is the name/address of the start of a Thumb function.
1447 We need to know this for the interworking support. */
1448 label_is_thumb_function_name = true;
1449
1450 demand_empty_rest_of_line ();
1451 }
1452
1453 /* Perform a .set directive, but also mark the alias as
1454 being a thumb function. */
1455
1456 static void
1457 s_thumb_set (equiv)
1458 int equiv;
1459 {
1460 /* XXX the following is a duplicate of the code for s_set() in read.c
1461 We cannot just call that code as we need to get at the symbol that
1462 is created. */
1463 register char * name;
1464 register char delim;
1465 register char * end_name;
1466 register symbolS * symbolP;
1467
1468 /* Especial apologies for the random logic:
1469 This just grew, and could be parsed much more simply!
1470 Dean - in haste. */
1471 name = input_line_pointer;
1472 delim = get_symbol_end ();
1473 end_name = input_line_pointer;
1474 *end_name = delim;
1475
1476 SKIP_WHITESPACE ();
1477
1478 if (*input_line_pointer != ',')
1479 {
1480 *end_name = 0;
1481 as_bad (_("Expected comma after name \"%s\""), name);
1482 *end_name = delim;
1483 ignore_rest_of_line ();
1484 return;
1485 }
1486
1487 input_line_pointer++;
1488 *end_name = 0;
1489
1490 if (name[0] == '.' && name[1] == '\0')
1491 {
1492 /* XXX - this should not happen to .thumb_set. */
1493 abort ();
1494 }
1495
1496 if ((symbolP = symbol_find (name)) == NULL
1497 && (symbolP = md_undefined_symbol (name)) == NULL)
1498 {
1499 #ifndef NO_LISTING
1500 /* When doing symbol listings, play games with dummy fragments living
1501 outside the normal fragment chain to record the file and line info
1502 for this symbol. */
1503 if (listing & LISTING_SYMBOLS)
1504 {
1505 extern struct list_info_struct * listing_tail;
1506 fragS * dummy_frag = (fragS *) xmalloc (sizeof (fragS));
1507
1508 memset (dummy_frag, 0, sizeof (fragS));
1509 dummy_frag->fr_type = rs_fill;
1510 dummy_frag->line = listing_tail;
1511 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1512 dummy_frag->fr_symbol = symbolP;
1513 }
1514 else
1515 #endif
1516 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1517
1518 #ifdef OBJ_COFF
1519 /* "set" symbols are local unless otherwise specified. */
1520 SF_SET_LOCAL (symbolP);
1521 #endif /* OBJ_COFF */
1522 } /* Make a new symbol. */
1523
1524 symbol_table_insert (symbolP);
1525
1526 * end_name = delim;
1527
1528 if (equiv
1529 && S_IS_DEFINED (symbolP)
1530 && S_GET_SEGMENT (symbolP) != reg_section)
1531 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1532
1533 pseudo_set (symbolP);
1534
1535 demand_empty_rest_of_line ();
1536
1537 /* XXX Now we come to the Thumb specific bit of code. */
1538
1539 THUMB_SET_FUNC (symbolP, 1);
1540 ARM_SET_THUMB (symbolP, 1);
1541 #if defined OBJ_ELF || defined OBJ_COFF
1542 ARM_SET_INTERWORK (symbolP, support_interwork);
1543 #endif
1544 }
1545
1546 /* If we change section we must dump the literal pool first. */
1547
1548 static void
1549 arm_s_text (ignore)
1550 int ignore;
1551 {
1552 if (now_seg != text_section)
1553 s_ltorg (0);
1554
1555 #ifdef OBJ_ELF
1556 obj_elf_text (ignore);
1557 #else
1558 s_text (ignore);
1559 #endif
1560 }
1561
1562 static void
1563 arm_s_data (ignore)
1564 int ignore;
1565 {
1566 if (flag_readonly_data_in_text)
1567 {
1568 if (now_seg != text_section)
1569 s_ltorg (0);
1570 }
1571 else if (now_seg != data_section)
1572 s_ltorg (0);
1573
1574 #ifdef OBJ_ELF
1575 obj_elf_data (ignore);
1576 #else
1577 s_data (ignore);
1578 #endif
1579 }
1580
1581 #ifdef OBJ_ELF
1582 static void
1583 arm_s_section (ignore)
1584 int ignore;
1585 {
1586 s_ltorg (0);
1587
1588 obj_elf_section (ignore);
1589 }
1590 #endif
1591
1592 static void
1593 opcode_select (width)
1594 int width;
1595 {
1596 switch (width)
1597 {
1598 case 16:
1599 if (! thumb_mode)
1600 {
1601 if (! (cpu_variant & ARM_THUMB))
1602 as_bad (_("selected processor does not support THUMB opcodes"));
1603
1604 thumb_mode = 1;
1605 /* No need to force the alignment, since we will have been
1606 coming from ARM mode, which is word-aligned. */
1607 record_alignment (now_seg, 1);
1608 }
1609 break;
1610
1611 case 32:
1612 if (thumb_mode)
1613 {
1614 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1615 as_bad (_("selected processor does not support ARM opcodes"));
1616
1617 thumb_mode = 0;
1618
1619 if (!need_pass_2)
1620 frag_align (2, 0, 0);
1621
1622 record_alignment (now_seg, 1);
1623 }
1624 break;
1625
1626 default:
1627 as_bad (_("invalid instruction size selected (%d)"), width);
1628 }
1629 }
1630
1631 static void
1632 s_arm (ignore)
1633 int ignore ATTRIBUTE_UNUSED;
1634 {
1635 opcode_select (32);
1636 demand_empty_rest_of_line ();
1637 }
1638
1639 static void
1640 s_thumb (ignore)
1641 int ignore ATTRIBUTE_UNUSED;
1642 {
1643 opcode_select (16);
1644 demand_empty_rest_of_line ();
1645 }
1646
1647 static void
1648 s_code (unused)
1649 int unused ATTRIBUTE_UNUSED;
1650 {
1651 register int temp;
1652
1653 temp = get_absolute_expression ();
1654 switch (temp)
1655 {
1656 case 16:
1657 case 32:
1658 opcode_select (temp);
1659 break;
1660
1661 default:
1662 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1663 }
1664 }
1665
1666 static void
1667 end_of_line (str)
1668 char * str;
1669 {
1670 skip_whitespace (str);
1671
1672 if (* str != '\0')
1673 inst.error = _("Garbage following instruction");
1674 }
1675
1676 static int
1677 skip_past_comma (str)
1678 char ** str;
1679 {
1680 char * p = * str, c;
1681 int comma = 0;
1682
1683 while ((c = *p) == ' ' || c == ',')
1684 {
1685 p++;
1686 if (c == ',' && comma++)
1687 return FAIL;
1688 }
1689
1690 if (c == '\0')
1691 return FAIL;
1692
1693 *str = p;
1694 return comma ? SUCCESS : FAIL;
1695 }
1696
1697 /* A standard register must be given at this point.
1698 SHIFT is the place to put it in inst.instruction.
1699 Restores input start point on error.
1700 Returns the reg#, or FAIL. */
1701
1702 static int
1703 reg_required_here (str, shift)
1704 char ** str;
1705 int shift;
1706 {
1707 static char buff [128]; /* XXX */
1708 int reg;
1709 char * start = * str;
1710
1711 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1712 {
1713 if (shift >= 0)
1714 inst.instruction |= reg << shift;
1715 return reg;
1716 }
1717
1718 /* Restore the start point, we may have got a reg of the wrong class. */
1719 *str = start;
1720
1721 /* In the few cases where we might be able to accept something else
1722 this error can be overridden. */
1723 sprintf (buff, _("Register expected, not '%.100s'"), start);
1724 inst.error = buff;
1725
1726 return FAIL;
1727 }
1728
1729 static CONST struct asm_psr *
1730 arm_psr_parse (ccp)
1731 register char ** ccp;
1732 {
1733 char * start = * ccp;
1734 char c;
1735 char * p;
1736 CONST struct asm_psr * psr;
1737
1738 p = start;
1739
1740 /* Skip to the end of the next word in the input stream. */
1741 do
1742 {
1743 c = *p++;
1744 }
1745 while (isalpha (c) || c == '_');
1746
1747 /* Terminate the word. */
1748 *--p = 0;
1749
1750 /* Now locate the word in the psr hash table. */
1751 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
1752
1753 /* Restore the input stream. */
1754 *p = c;
1755
1756 /* If we found a valid match, advance the
1757 stream pointer past the end of the word. */
1758 *ccp = p;
1759
1760 return psr;
1761 }
1762
1763 /* Parse the input looking for a PSR flag. */
1764
1765 static int
1766 psr_required_here (str)
1767 char ** str;
1768 {
1769 char * start = * str;
1770 CONST struct asm_psr * psr;
1771
1772 psr = arm_psr_parse (str);
1773
1774 if (psr)
1775 {
1776 /* If this is the SPSR that is being modified, set the R bit. */
1777 if (! psr->cpsr)
1778 inst.instruction |= SPSR_BIT;
1779
1780 /* Set the psr flags in the MSR instruction. */
1781 inst.instruction |= psr->field << PSR_SHIFT;
1782
1783 return SUCCESS;
1784 }
1785
1786 /* In the few cases where we might be able to accept
1787 something else this error can be overridden. */
1788 inst.error = _("flag for {c}psr instruction expected");
1789
1790 /* Restore the start point. */
1791 *str = start;
1792 return FAIL;
1793 }
1794
1795 static int
1796 co_proc_number (str)
1797 char ** str;
1798 {
1799 int processor, pchar;
1800
1801 skip_whitespace (* str);
1802
1803 /* The data sheet seems to imply that just a number on its own is valid
1804 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1805 accept either. */
1806 if (**str == 'p' || **str == 'P')
1807 (*str)++;
1808
1809 pchar = *(*str)++;
1810 if (pchar >= '0' && pchar <= '9')
1811 {
1812 processor = pchar - '0';
1813 if (**str >= '0' && **str <= '9')
1814 {
1815 processor = processor * 10 + *(*str)++ - '0';
1816 if (processor > 15)
1817 {
1818 inst.error = _("Illegal co-processor number");
1819 return FAIL;
1820 }
1821 }
1822 }
1823 else
1824 {
1825 inst.error = _("Bad or missing co-processor number");
1826 return FAIL;
1827 }
1828
1829 inst.instruction |= processor << 8;
1830 return SUCCESS;
1831 }
1832
1833 static int
1834 cp_opc_expr (str, where, length)
1835 char ** str;
1836 int where;
1837 int length;
1838 {
1839 expressionS expr;
1840
1841 skip_whitespace (* str);
1842
1843 memset (&expr, '\0', sizeof (expr));
1844
1845 if (my_get_expression (&expr, str))
1846 return FAIL;
1847 if (expr.X_op != O_constant)
1848 {
1849 inst.error = _("bad or missing expression");
1850 return FAIL;
1851 }
1852
1853 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1854 {
1855 inst.error = _("immediate co-processor expression too large");
1856 return FAIL;
1857 }
1858
1859 inst.instruction |= expr.X_add_number << where;
1860 return SUCCESS;
1861 }
1862
1863 static int
1864 cp_reg_required_here (str, where)
1865 char ** str;
1866 int where;
1867 {
1868 int reg;
1869 char * start = *str;
1870
1871 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1872 {
1873 reg &= 15;
1874 inst.instruction |= reg << where;
1875 return reg;
1876 }
1877
1878 /* In the few cases where we might be able to accept something else
1879 this error can be overridden. */
1880 inst.error = _("Co-processor register expected");
1881
1882 /* Restore the start point. */
1883 *str = start;
1884 return FAIL;
1885 }
1886
1887 static int
1888 fp_reg_required_here (str, where)
1889 char ** str;
1890 int where;
1891 {
1892 int reg;
1893 char * start = * str;
1894
1895 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1896 {
1897 reg &= 7;
1898 inst.instruction |= reg << where;
1899 return reg;
1900 }
1901
1902 /* In the few cases where we might be able to accept something else
1903 this error can be overridden. */
1904 inst.error = _("Floating point register expected");
1905
1906 /* Restore the start point. */
1907 *str = start;
1908 return FAIL;
1909 }
1910
1911 static int
1912 cp_address_offset (str)
1913 char ** str;
1914 {
1915 int offset;
1916
1917 skip_whitespace (* str);
1918
1919 if (! is_immediate_prefix (**str))
1920 {
1921 inst.error = _("immediate expression expected");
1922 return FAIL;
1923 }
1924
1925 (*str)++;
1926
1927 if (my_get_expression (& inst.reloc.exp, str))
1928 return FAIL;
1929
1930 if (inst.reloc.exp.X_op == O_constant)
1931 {
1932 offset = inst.reloc.exp.X_add_number;
1933
1934 if (offset & 3)
1935 {
1936 inst.error = _("co-processor address must be word aligned");
1937 return FAIL;
1938 }
1939
1940 if (offset > 1023 || offset < -1023)
1941 {
1942 inst.error = _("offset too large");
1943 return FAIL;
1944 }
1945
1946 if (offset >= 0)
1947 inst.instruction |= INDEX_UP;
1948 else
1949 offset = -offset;
1950
1951 inst.instruction |= offset >> 2;
1952 }
1953 else
1954 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1955
1956 return SUCCESS;
1957 }
1958
1959 static int
1960 cp_address_required_here (str)
1961 char ** str;
1962 {
1963 char * p = * str;
1964 int pre_inc = 0;
1965 int write_back = 0;
1966
1967 if (*p == '[')
1968 {
1969 int reg;
1970
1971 p++;
1972 skip_whitespace (p);
1973
1974 if ((reg = reg_required_here (& p, 16)) == FAIL)
1975 return FAIL;
1976
1977 skip_whitespace (p);
1978
1979 if (*p == ']')
1980 {
1981 p++;
1982
1983 if (skip_past_comma (& p) == SUCCESS)
1984 {
1985 /* [Rn], #expr */
1986 write_back = WRITE_BACK;
1987
1988 if (reg == REG_PC)
1989 {
1990 inst.error = _("pc may not be used in post-increment");
1991 return FAIL;
1992 }
1993
1994 if (cp_address_offset (& p) == FAIL)
1995 return FAIL;
1996 }
1997 else
1998 pre_inc = PRE_INDEX | INDEX_UP;
1999 }
2000 else
2001 {
2002 /* '['Rn, #expr']'[!] */
2003
2004 if (skip_past_comma (& p) == FAIL)
2005 {
2006 inst.error = _("pre-indexed expression expected");
2007 return FAIL;
2008 }
2009
2010 pre_inc = PRE_INDEX;
2011
2012 if (cp_address_offset (& p) == FAIL)
2013 return FAIL;
2014
2015 skip_whitespace (p);
2016
2017 if (*p++ != ']')
2018 {
2019 inst.error = _("missing ]");
2020 return FAIL;
2021 }
2022
2023 skip_whitespace (p);
2024
2025 if (*p == '!')
2026 {
2027 if (reg == REG_PC)
2028 {
2029 inst.error = _("pc may not be used with write-back");
2030 return FAIL;
2031 }
2032
2033 p++;
2034 write_back = WRITE_BACK;
2035 }
2036 }
2037 }
2038 else
2039 {
2040 if (my_get_expression (&inst.reloc.exp, &p))
2041 return FAIL;
2042
2043 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
2044 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
2045 inst.reloc.pc_rel = 1;
2046 inst.instruction |= (REG_PC << 16);
2047 pre_inc = PRE_INDEX;
2048 }
2049
2050 inst.instruction |= write_back | pre_inc;
2051 *str = p;
2052 return SUCCESS;
2053 }
2054
2055 static void
2056 do_nop (str, flags)
2057 char * str;
2058 unsigned long flags;
2059 {
2060 /* Do nothing really. */
2061 inst.instruction |= flags; /* This is pointless. */
2062 end_of_line (str);
2063 return;
2064 }
2065
2066 static void
2067 do_mrs (str, flags)
2068 char *str;
2069 unsigned long flags;
2070 {
2071 int skip = 0;
2072
2073 /* Only one syntax. */
2074 skip_whitespace (str);
2075
2076 if (reg_required_here (&str, 12) == FAIL)
2077 {
2078 inst.error = BAD_ARGS;
2079 return;
2080 }
2081
2082 if (skip_past_comma (&str) == FAIL)
2083 {
2084 inst.error = _("comma expected after register name");
2085 return;
2086 }
2087
2088 skip_whitespace (str);
2089
2090 if ( strcmp (str, "CPSR") == 0
2091 || strcmp (str, "SPSR") == 0
2092 /* Lower case versions for backwards compatability. */
2093 || strcmp (str, "cpsr") == 0
2094 || strcmp (str, "spsr") == 0)
2095 skip = 4;
2096
2097 /* This is for backwards compatability with older toolchains. */
2098 else if ( strcmp (str, "cpsr_all") == 0
2099 || strcmp (str, "spsr_all") == 0)
2100 skip = 8;
2101 else
2102 {
2103 inst.error = _("{C|S}PSR expected");
2104 return;
2105 }
2106
2107 if (* str == 's' || * str == 'S')
2108 inst.instruction |= SPSR_BIT;
2109 str += skip;
2110
2111 inst.instruction |= flags;
2112 end_of_line (str);
2113 }
2114
2115 /* Two possible forms:
2116 "{C|S}PSR_<field>, Rm",
2117 "{C|S}PSR_f, #expression". */
2118
2119 static void
2120 do_msr (str, flags)
2121 char * str;
2122 unsigned long flags;
2123 {
2124 skip_whitespace (str);
2125
2126 if (psr_required_here (& str) == FAIL)
2127 return;
2128
2129 if (skip_past_comma (& str) == FAIL)
2130 {
2131 inst.error = _("comma missing after psr flags");
2132 return;
2133 }
2134
2135 skip_whitespace (str);
2136
2137 if (reg_required_here (& str, 0) != FAIL)
2138 {
2139 inst.error = NULL;
2140 inst.instruction |= flags;
2141 end_of_line (str);
2142 return;
2143 }
2144
2145 if (! is_immediate_prefix (* str))
2146 {
2147 inst.error =
2148 _("only a register or immediate value can follow a psr flag");
2149 return;
2150 }
2151
2152 str ++;
2153 inst.error = NULL;
2154
2155 if (my_get_expression (& inst.reloc.exp, & str))
2156 {
2157 inst.error =
2158 _("only a register or immediate value can follow a psr flag");
2159 return;
2160 }
2161
2162 if (inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
2163 {
2164 inst.error = _("can only set flag field with immediate value");
2165 return;
2166 }
2167
2168 flags |= INST_IMMEDIATE;
2169
2170 if (inst.reloc.exp.X_add_symbol)
2171 {
2172 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2173 inst.reloc.pc_rel = 0;
2174 }
2175 else
2176 {
2177 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
2178
2179 if (value == (unsigned) FAIL)
2180 {
2181 inst.error = _("Invalid constant");
2182 return;
2183 }
2184
2185 inst.instruction |= value;
2186 }
2187
2188 inst.error = NULL;
2189 inst.instruction |= flags;
2190 end_of_line (str);
2191 }
2192
2193 /* Long Multiply Parser
2194 UMULL RdLo, RdHi, Rm, Rs
2195 SMULL RdLo, RdHi, Rm, Rs
2196 UMLAL RdLo, RdHi, Rm, Rs
2197 SMLAL RdLo, RdHi, Rm, Rs. */
2198
2199 static void
2200 do_mull (str, flags)
2201 char * str;
2202 unsigned long flags;
2203 {
2204 int rdlo, rdhi, rm, rs;
2205
2206 /* Only one format "rdlo, rdhi, rm, rs". */
2207 skip_whitespace (str);
2208
2209 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
2210 {
2211 inst.error = BAD_ARGS;
2212 return;
2213 }
2214
2215 if (skip_past_comma (&str) == FAIL
2216 || (rdhi = reg_required_here (&str, 16)) == FAIL)
2217 {
2218 inst.error = BAD_ARGS;
2219 return;
2220 }
2221
2222 if (skip_past_comma (&str) == FAIL
2223 || (rm = reg_required_here (&str, 0)) == FAIL)
2224 {
2225 inst.error = BAD_ARGS;
2226 return;
2227 }
2228
2229 /* rdhi, rdlo and rm must all be different. */
2230 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
2231 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2232
2233 if (skip_past_comma (&str) == FAIL
2234 || (rs = reg_required_here (&str, 8)) == FAIL)
2235 {
2236 inst.error = BAD_ARGS;
2237 return;
2238 }
2239
2240 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2241 {
2242 inst.error = BAD_PC;
2243 return;
2244 }
2245
2246 inst.instruction |= flags;
2247 end_of_line (str);
2248 return;
2249 }
2250
2251 static void
2252 do_mul (str, flags)
2253 char * str;
2254 unsigned long flags;
2255 {
2256 int rd, rm;
2257
2258 /* Only one format "rd, rm, rs". */
2259 skip_whitespace (str);
2260
2261 if ((rd = reg_required_here (&str, 16)) == FAIL)
2262 {
2263 inst.error = BAD_ARGS;
2264 return;
2265 }
2266
2267 if (rd == REG_PC)
2268 {
2269 inst.error = BAD_PC;
2270 return;
2271 }
2272
2273 if (skip_past_comma (&str) == FAIL
2274 || (rm = reg_required_here (&str, 0)) == FAIL)
2275 {
2276 inst.error = BAD_ARGS;
2277 return;
2278 }
2279
2280 if (rm == REG_PC)
2281 {
2282 inst.error = BAD_PC;
2283 return;
2284 }
2285
2286 if (rm == rd)
2287 as_tsktsk (_("rd and rm should be different in mul"));
2288
2289 if (skip_past_comma (&str) == FAIL
2290 || (rm = reg_required_here (&str, 8)) == FAIL)
2291 {
2292 inst.error = BAD_ARGS;
2293 return;
2294 }
2295
2296 if (rm == REG_PC)
2297 {
2298 inst.error = BAD_PC;
2299 return;
2300 }
2301
2302 inst.instruction |= flags;
2303 end_of_line (str);
2304 return;
2305 }
2306
2307 static void
2308 do_mla (str, flags)
2309 char * str;
2310 unsigned long flags;
2311 {
2312 int rd, rm;
2313
2314 /* Only one format "rd, rm, rs, rn". */
2315 skip_whitespace (str);
2316
2317 if ((rd = reg_required_here (&str, 16)) == FAIL)
2318 {
2319 inst.error = BAD_ARGS;
2320 return;
2321 }
2322
2323 if (rd == REG_PC)
2324 {
2325 inst.error = BAD_PC;
2326 return;
2327 }
2328
2329 if (skip_past_comma (&str) == FAIL
2330 || (rm = reg_required_here (&str, 0)) == FAIL)
2331 {
2332 inst.error = BAD_ARGS;
2333 return;
2334 }
2335
2336 if (rm == REG_PC)
2337 {
2338 inst.error = BAD_PC;
2339 return;
2340 }
2341
2342 if (rm == rd)
2343 as_tsktsk (_("rd and rm should be different in mla"));
2344
2345 if (skip_past_comma (&str) == FAIL
2346 || (rd = reg_required_here (&str, 8)) == FAIL
2347 || skip_past_comma (&str) == FAIL
2348 || (rm = reg_required_here (&str, 12)) == FAIL)
2349 {
2350 inst.error = BAD_ARGS;
2351 return;
2352 }
2353
2354 if (rd == REG_PC || rm == REG_PC)
2355 {
2356 inst.error = BAD_PC;
2357 return;
2358 }
2359
2360 inst.instruction |= flags;
2361 end_of_line (str);
2362 return;
2363 }
2364
2365 /* Returns the index into fp_values of a floating point number,
2366 or -1 if not in the table. */
2367
2368 static int
2369 my_get_float_expression (str)
2370 char ** str;
2371 {
2372 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2373 char * save_in;
2374 expressionS exp;
2375 int i;
2376 int j;
2377
2378 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2379
2380 /* Look for a raw floating point number. */
2381 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2382 && is_end_of_line[(unsigned char) *save_in])
2383 {
2384 for (i = 0; i < NUM_FLOAT_VALS; i++)
2385 {
2386 for (j = 0; j < MAX_LITTLENUMS; j++)
2387 {
2388 if (words[j] != fp_values[i][j])
2389 break;
2390 }
2391
2392 if (j == MAX_LITTLENUMS)
2393 {
2394 *str = save_in;
2395 return i;
2396 }
2397 }
2398 }
2399
2400 /* Try and parse a more complex expression, this will probably fail
2401 unless the code uses a floating point prefix (eg "0f"). */
2402 save_in = input_line_pointer;
2403 input_line_pointer = *str;
2404 if (expression (&exp) == absolute_section
2405 && exp.X_op == O_big
2406 && exp.X_add_number < 0)
2407 {
2408 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2409 Ditto for 15. */
2410 if (gen_to_words (words, 5, (long) 15) == 0)
2411 {
2412 for (i = 0; i < NUM_FLOAT_VALS; i++)
2413 {
2414 for (j = 0; j < MAX_LITTLENUMS; j++)
2415 {
2416 if (words[j] != fp_values[i][j])
2417 break;
2418 }
2419
2420 if (j == MAX_LITTLENUMS)
2421 {
2422 *str = input_line_pointer;
2423 input_line_pointer = save_in;
2424 return i;
2425 }
2426 }
2427 }
2428 }
2429
2430 *str = input_line_pointer;
2431 input_line_pointer = save_in;
2432 return -1;
2433 }
2434
2435 /* Return true if anything in the expression is a bignum. */
2436
2437 static int
2438 walk_no_bignums (sp)
2439 symbolS * sp;
2440 {
2441 if (symbol_get_value_expression (sp)->X_op == O_big)
2442 return 1;
2443
2444 if (symbol_get_value_expression (sp)->X_add_symbol)
2445 {
2446 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
2447 || (symbol_get_value_expression (sp)->X_op_symbol
2448 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
2449 }
2450
2451 return 0;
2452 }
2453
2454 static int
2455 my_get_expression (ep, str)
2456 expressionS * ep;
2457 char ** str;
2458 {
2459 char * save_in;
2460 segT seg;
2461
2462 save_in = input_line_pointer;
2463 input_line_pointer = *str;
2464 seg = expression (ep);
2465
2466 #ifdef OBJ_AOUT
2467 if (seg != absolute_section
2468 && seg != text_section
2469 && seg != data_section
2470 && seg != bss_section
2471 && seg != undefined_section)
2472 {
2473 inst.error = _("bad_segment");
2474 *str = input_line_pointer;
2475 input_line_pointer = save_in;
2476 return 1;
2477 }
2478 #endif
2479
2480 /* Get rid of any bignums now, so that we don't generate an error for which
2481 we can't establish a line number later on. Big numbers are never valid
2482 in instructions, which is where this routine is always called. */
2483 if (ep->X_op == O_big
2484 || (ep->X_add_symbol
2485 && (walk_no_bignums (ep->X_add_symbol)
2486 || (ep->X_op_symbol
2487 && walk_no_bignums (ep->X_op_symbol)))))
2488 {
2489 inst.error = _("Invalid constant");
2490 *str = input_line_pointer;
2491 input_line_pointer = save_in;
2492 return 1;
2493 }
2494
2495 *str = input_line_pointer;
2496 input_line_pointer = save_in;
2497 return 0;
2498 }
2499
2500 /* UNRESTRICT should be one if <shift> <register> is permitted for this
2501 instruction. */
2502
2503 static int
2504 decode_shift (str, unrestrict)
2505 char ** str;
2506 int unrestrict;
2507 {
2508 struct asm_shift * shft;
2509 char * p;
2510 char c;
2511
2512 skip_whitespace (* str);
2513
2514 for (p = * str; isalpha (* p); p ++)
2515 ;
2516
2517 if (p == * str)
2518 {
2519 inst.error = _("Shift expression expected");
2520 return FAIL;
2521 }
2522
2523 c = * p;
2524 * p = '\0';
2525 shft = (struct asm_shift *) hash_find (arm_shift_hsh, * str);
2526 * p = c;
2527 if (shft)
2528 {
2529 if ( ! strncmp (* str, "rrx", 3)
2530 || ! strncmp (* str, "RRX", 3))
2531 {
2532 * str = p;
2533 inst.instruction |= shft->value;
2534 return SUCCESS;
2535 }
2536
2537 skip_whitespace (p);
2538
2539 if (unrestrict && reg_required_here (& p, 8) != FAIL)
2540 {
2541 inst.instruction |= shft->value | SHIFT_BY_REG;
2542 * str = p;
2543 return SUCCESS;
2544 }
2545 else if (is_immediate_prefix (* p))
2546 {
2547 inst.error = NULL;
2548 p ++;
2549
2550 if (my_get_expression (& inst.reloc.exp, & p))
2551 return FAIL;
2552
2553 /* Validate some simple #expressions. */
2554 if (inst.reloc.exp.X_op == O_constant)
2555 {
2556 unsigned num = inst.reloc.exp.X_add_number;
2557
2558 /* Reject operations greater than 32, or lsl #32. */
2559 if (num > 32 || (num == 32 && shft->value == 0))
2560 {
2561 inst.error = _("Invalid immediate shift");
2562 return FAIL;
2563 }
2564
2565 /* Shifts of zero should be converted to lsl
2566 (which is zero). */
2567 if (num == 0)
2568 {
2569 * str = p;
2570 return SUCCESS;
2571 }
2572
2573 /* Shifts of 32 are encoded as 0, for those shifts that
2574 support it. */
2575 if (num == 32)
2576 num = 0;
2577
2578 inst.instruction |= (num << 7) | shft->value;
2579 * str = p;
2580 return SUCCESS;
2581 }
2582
2583 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2584 inst.reloc.pc_rel = 0;
2585 inst.instruction |= shft->value;
2586
2587 * str = p;
2588 return SUCCESS;
2589 }
2590 else
2591 {
2592 inst.error = (unrestrict
2593 ? _("shift requires register or #expression")
2594 : _("shift requires #expression"));
2595 * str = p;
2596 return FAIL;
2597 }
2598 }
2599
2600 inst.error = _("Shift expression expected");
2601 return FAIL;
2602 }
2603
2604 /* Do those data_ops which can take a negative immediate constant
2605 by altering the instuction. A bit of a hack really.
2606 MOV <-> MVN
2607 AND <-> BIC
2608 ADC <-> SBC
2609 by inverting the second operand, and
2610 ADD <-> SUB
2611 CMP <-> CMN
2612 by negating the second operand. */
2613
2614 static int
2615 negate_data_op (instruction, value)
2616 unsigned long * instruction;
2617 unsigned long value;
2618 {
2619 int op, new_inst;
2620 unsigned long negated, inverted;
2621
2622 negated = validate_immediate (-value);
2623 inverted = validate_immediate (~value);
2624
2625 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2626 switch (op)
2627 {
2628 /* First negates. */
2629 case OPCODE_SUB: /* ADD <-> SUB */
2630 new_inst = OPCODE_ADD;
2631 value = negated;
2632 break;
2633
2634 case OPCODE_ADD:
2635 new_inst = OPCODE_SUB;
2636 value = negated;
2637 break;
2638
2639 case OPCODE_CMP: /* CMP <-> CMN */
2640 new_inst = OPCODE_CMN;
2641 value = negated;
2642 break;
2643
2644 case OPCODE_CMN:
2645 new_inst = OPCODE_CMP;
2646 value = negated;
2647 break;
2648
2649 /* Now Inverted ops. */
2650 case OPCODE_MOV: /* MOV <-> MVN */
2651 new_inst = OPCODE_MVN;
2652 value = inverted;
2653 break;
2654
2655 case OPCODE_MVN:
2656 new_inst = OPCODE_MOV;
2657 value = inverted;
2658 break;
2659
2660 case OPCODE_AND: /* AND <-> BIC */
2661 new_inst = OPCODE_BIC;
2662 value = inverted;
2663 break;
2664
2665 case OPCODE_BIC:
2666 new_inst = OPCODE_AND;
2667 value = inverted;
2668 break;
2669
2670 case OPCODE_ADC: /* ADC <-> SBC */
2671 new_inst = OPCODE_SBC;
2672 value = inverted;
2673 break;
2674
2675 case OPCODE_SBC:
2676 new_inst = OPCODE_ADC;
2677 value = inverted;
2678 break;
2679
2680 /* We cannot do anything. */
2681 default:
2682 return FAIL;
2683 }
2684
2685 if (value == (unsigned) FAIL)
2686 return FAIL;
2687
2688 *instruction &= OPCODE_MASK;
2689 *instruction |= new_inst << DATA_OP_SHIFT;
2690 return value;
2691 }
2692
2693 static int
2694 data_op2 (str)
2695 char ** str;
2696 {
2697 int value;
2698 expressionS expr;
2699
2700 skip_whitespace (* str);
2701
2702 if (reg_required_here (str, 0) != FAIL)
2703 {
2704 if (skip_past_comma (str) == SUCCESS)
2705 /* Shift operation on register. */
2706 return decode_shift (str, NO_SHIFT_RESTRICT);
2707
2708 return SUCCESS;
2709 }
2710 else
2711 {
2712 /* Immediate expression. */
2713 if (is_immediate_prefix (**str))
2714 {
2715 (*str)++;
2716 inst.error = NULL;
2717
2718 if (my_get_expression (&inst.reloc.exp, str))
2719 return FAIL;
2720
2721 if (inst.reloc.exp.X_add_symbol)
2722 {
2723 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2724 inst.reloc.pc_rel = 0;
2725 }
2726 else
2727 {
2728 if (skip_past_comma (str) == SUCCESS)
2729 {
2730 /* #x, y -- ie explicit rotation by Y. */
2731 if (my_get_expression (&expr, str))
2732 return FAIL;
2733
2734 if (expr.X_op != O_constant)
2735 {
2736 inst.error = _("Constant expression expected");
2737 return FAIL;
2738 }
2739
2740 /* Rotate must be a multiple of 2. */
2741 if (((unsigned) expr.X_add_number) > 30
2742 || (expr.X_add_number & 1) != 0
2743 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2744 {
2745 inst.error = _("Invalid constant");
2746 return FAIL;
2747 }
2748 inst.instruction |= INST_IMMEDIATE;
2749 inst.instruction |= inst.reloc.exp.X_add_number;
2750 inst.instruction |= expr.X_add_number << 7;
2751 return SUCCESS;
2752 }
2753
2754 /* Implicit rotation, select a suitable one. */
2755 value = validate_immediate (inst.reloc.exp.X_add_number);
2756
2757 if (value == FAIL)
2758 {
2759 /* Can't be done. Perhaps the code reads something like
2760 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
2761 if ((value = negate_data_op (&inst.instruction,
2762 inst.reloc.exp.X_add_number))
2763 == FAIL)
2764 {
2765 inst.error = _("Invalid constant");
2766 return FAIL;
2767 }
2768 }
2769
2770 inst.instruction |= value;
2771 }
2772
2773 inst.instruction |= INST_IMMEDIATE;
2774 return SUCCESS;
2775 }
2776
2777 (*str)++;
2778 inst.error = _("Register or shift expression expected");
2779 return FAIL;
2780 }
2781 }
2782
2783 static int
2784 fp_op2 (str)
2785 char ** str;
2786 {
2787 skip_whitespace (* str);
2788
2789 if (fp_reg_required_here (str, 0) != FAIL)
2790 return SUCCESS;
2791 else
2792 {
2793 /* Immediate expression. */
2794 if (*((*str)++) == '#')
2795 {
2796 int i;
2797
2798 inst.error = NULL;
2799
2800 skip_whitespace (* str);
2801
2802 /* First try and match exact strings, this is to guarantee
2803 that some formats will work even for cross assembly. */
2804
2805 for (i = 0; fp_const[i]; i++)
2806 {
2807 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2808 {
2809 char *start = *str;
2810
2811 *str += strlen (fp_const[i]);
2812 if (is_end_of_line[(unsigned char) **str])
2813 {
2814 inst.instruction |= i + 8;
2815 return SUCCESS;
2816 }
2817 *str = start;
2818 }
2819 }
2820
2821 /* Just because we didn't get a match doesn't mean that the
2822 constant isn't valid, just that it is in a format that we
2823 don't automatically recognize. Try parsing it with
2824 the standard expression routines. */
2825 if ((i = my_get_float_expression (str)) >= 0)
2826 {
2827 inst.instruction |= i + 8;
2828 return SUCCESS;
2829 }
2830
2831 inst.error = _("Invalid floating point immediate expression");
2832 return FAIL;
2833 }
2834 inst.error =
2835 _("Floating point register or immediate expression expected");
2836 return FAIL;
2837 }
2838 }
2839
2840 static void
2841 do_arit (str, flags)
2842 char * str;
2843 unsigned long flags;
2844 {
2845 skip_whitespace (str);
2846
2847 if (reg_required_here (&str, 12) == FAIL
2848 || skip_past_comma (&str) == FAIL
2849 || reg_required_here (&str, 16) == FAIL
2850 || skip_past_comma (&str) == FAIL
2851 || data_op2 (&str) == FAIL)
2852 {
2853 if (!inst.error)
2854 inst.error = BAD_ARGS;
2855 return;
2856 }
2857
2858 inst.instruction |= flags;
2859 end_of_line (str);
2860 return;
2861 }
2862
2863 static void
2864 do_adr (str, flags)
2865 char * str;
2866 unsigned long flags;
2867 {
2868 /* This is a pseudo-op of the form "adr rd, label" to be converted
2869 into a relative address of the form "add rd, pc, #label-.-8". */
2870 skip_whitespace (str);
2871
2872 if (reg_required_here (&str, 12) == FAIL
2873 || skip_past_comma (&str) == FAIL
2874 || my_get_expression (&inst.reloc.exp, &str))
2875 {
2876 if (!inst.error)
2877 inst.error = BAD_ARGS;
2878 return;
2879 }
2880
2881 /* Frag hacking will turn this into a sub instruction if the offset turns
2882 out to be negative. */
2883 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2884 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
2885 inst.reloc.pc_rel = 1;
2886 inst.instruction |= flags;
2887
2888 end_of_line (str);
2889 }
2890
2891 static void
2892 do_adrl (str, flags)
2893 char * str;
2894 unsigned long flags;
2895 {
2896 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2897 into a relative address of the form:
2898 add rd, pc, #low(label-.-8)"
2899 add rd, rd, #high(label-.-8)" */
2900
2901 skip_whitespace (str);
2902
2903 if (reg_required_here (& str, 12) == FAIL
2904 || skip_past_comma (& str) == FAIL
2905 || my_get_expression (& inst.reloc.exp, & str))
2906 {
2907 if (!inst.error)
2908 inst.error = BAD_ARGS;
2909 return;
2910 }
2911
2912 end_of_line (str);
2913
2914 /* Frag hacking will turn this into a sub instruction if the offset turns
2915 out to be negative. */
2916 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
2917 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2918 inst.reloc.pc_rel = 1;
2919 inst.instruction |= flags;
2920 inst.size = INSN_SIZE * 2;
2921
2922 return;
2923 }
2924
2925 static void
2926 do_cmp (str, flags)
2927 char * str;
2928 unsigned long flags;
2929 {
2930 skip_whitespace (str);
2931
2932 if (reg_required_here (&str, 16) == FAIL)
2933 {
2934 if (!inst.error)
2935 inst.error = BAD_ARGS;
2936 return;
2937 }
2938
2939 if (skip_past_comma (&str) == FAIL
2940 || data_op2 (&str) == FAIL)
2941 {
2942 if (!inst.error)
2943 inst.error = BAD_ARGS;
2944 return;
2945 }
2946
2947 inst.instruction |= flags;
2948 if ((flags & 0x0000f000) == 0)
2949 inst.instruction |= CONDS_BIT;
2950
2951 end_of_line (str);
2952 return;
2953 }
2954
2955 static void
2956 do_mov (str, flags)
2957 char * str;
2958 unsigned long flags;
2959 {
2960 skip_whitespace (str);
2961
2962 if (reg_required_here (&str, 12) == FAIL)
2963 {
2964 if (!inst.error)
2965 inst.error = BAD_ARGS;
2966 return;
2967 }
2968
2969 if (skip_past_comma (&str) == FAIL
2970 || data_op2 (&str) == FAIL)
2971 {
2972 if (!inst.error)
2973 inst.error = BAD_ARGS;
2974 return;
2975 }
2976
2977 inst.instruction |= flags;
2978 end_of_line (str);
2979 return;
2980 }
2981
2982 static int
2983 ldst_extend (str, hwse)
2984 char ** str;
2985 int hwse;
2986 {
2987 int add = INDEX_UP;
2988
2989 switch (**str)
2990 {
2991 case '#':
2992 case '$':
2993 (*str)++;
2994 if (my_get_expression (& inst.reloc.exp, str))
2995 return FAIL;
2996
2997 if (inst.reloc.exp.X_op == O_constant)
2998 {
2999 int value = inst.reloc.exp.X_add_number;
3000
3001 if ((hwse && (value < -255 || value > 255))
3002 || (value < -4095 || value > 4095))
3003 {
3004 inst.error = _("address offset too large");
3005 return FAIL;
3006 }
3007
3008 if (value < 0)
3009 {
3010 value = -value;
3011 add = 0;
3012 }
3013
3014 /* Halfword and signextension instructions have the
3015 immediate value split across bits 11..8 and bits 3..0. */
3016 if (hwse)
3017 inst.instruction |= (add | HWOFFSET_IMM
3018 | ((value >> 4) << 8) | (value & 0xF));
3019 else
3020 inst.instruction |= add | value;
3021 }
3022 else
3023 {
3024 if (hwse)
3025 {
3026 inst.instruction |= HWOFFSET_IMM;
3027 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3028 }
3029 else
3030 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3031 inst.reloc.pc_rel = 0;
3032 }
3033 return SUCCESS;
3034
3035 case '-':
3036 add = 0;
3037 /* Fall through. */
3038
3039 case '+':
3040 (*str)++;
3041 /* Fall through. */
3042
3043 default:
3044 if (reg_required_here (str, 0) == FAIL)
3045 return FAIL;
3046
3047 if (hwse)
3048 inst.instruction |= add;
3049 else
3050 {
3051 inst.instruction |= add | OFFSET_REG;
3052 if (skip_past_comma (str) == SUCCESS)
3053 return decode_shift (str, SHIFT_RESTRICT);
3054 }
3055
3056 return SUCCESS;
3057 }
3058 }
3059
3060 static void
3061 do_ldst (str, flags)
3062 char *str;
3063 unsigned long flags;
3064 {
3065 int halfword = 0;
3066 int pre_inc = 0;
3067 int conflict_reg;
3068 int value;
3069
3070 /* This is not ideal, but it is the simplest way of dealing with the
3071 ARM7T halfword instructions (since they use a different
3072 encoding, but the same mnemonic): */
3073 halfword = (flags & 0x80000000) != 0;
3074 if (halfword)
3075 {
3076 /* This is actually a load/store of a halfword, or a
3077 signed-extension load. */
3078 if ((cpu_variant & ARM_HALFWORD) == 0)
3079 {
3080 inst.error
3081 = _("Processor does not support halfwords or signed bytes");
3082 return;
3083 }
3084
3085 inst.instruction = ((inst.instruction & COND_MASK)
3086 | (flags & ~COND_MASK));
3087
3088 flags = 0;
3089 }
3090
3091 skip_whitespace (str);
3092
3093 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
3094 {
3095 if (!inst.error)
3096 inst.error = BAD_ARGS;
3097 return;
3098 }
3099
3100 if (skip_past_comma (& str) == FAIL)
3101 {
3102 inst.error = _("Address expected");
3103 return;
3104 }
3105
3106 if (*str == '[')
3107 {
3108 int reg;
3109
3110 str++;
3111
3112 skip_whitespace (str);
3113
3114 if ((reg = reg_required_here (&str, 16)) == FAIL)
3115 return;
3116
3117 /* Conflicts can occur on stores as well as loads. */
3118 conflict_reg = (conflict_reg == reg);
3119
3120 skip_whitespace (str);
3121
3122 if (*str == ']')
3123 {
3124 str ++;
3125
3126 if (skip_past_comma (&str) == SUCCESS)
3127 {
3128 /* [Rn],... (post inc) */
3129 if (ldst_extend (&str, halfword) == FAIL)
3130 return;
3131 if (conflict_reg)
3132 as_warn (_("%s register same as write-back base"),
3133 ((inst.instruction & LOAD_BIT)
3134 ? _("destination") : _("source")));
3135 }
3136 else
3137 {
3138 /* [Rn] */
3139 if (halfword)
3140 inst.instruction |= HWOFFSET_IMM;
3141
3142 skip_whitespace (str);
3143
3144 if (*str == '!')
3145 {
3146 if (conflict_reg)
3147 as_warn (_("%s register same as write-back base"),
3148 ((inst.instruction & LOAD_BIT)
3149 ? _("destination") : _("source")));
3150 str++;
3151 inst.instruction |= WRITE_BACK;
3152 }
3153
3154 flags |= INDEX_UP;
3155 if (! (flags & TRANS_BIT))
3156 pre_inc = 1;
3157 }
3158 }
3159 else
3160 {
3161 /* [Rn,...] */
3162 if (skip_past_comma (&str) == FAIL)
3163 {
3164 inst.error = _("pre-indexed expression expected");
3165 return;
3166 }
3167
3168 pre_inc = 1;
3169 if (ldst_extend (&str, halfword) == FAIL)
3170 return;
3171
3172 skip_whitespace (str);
3173
3174 if (*str++ != ']')
3175 {
3176 inst.error = _("missing ]");
3177 return;
3178 }
3179
3180 skip_whitespace (str);
3181
3182 if (*str == '!')
3183 {
3184 if (conflict_reg)
3185 as_warn (_("%s register same as write-back base"),
3186 ((inst.instruction & LOAD_BIT)
3187 ? _("destination") : _("source")));
3188 str++;
3189 inst.instruction |= WRITE_BACK;
3190 }
3191 }
3192 }
3193 else if (*str == '=')
3194 {
3195 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
3196 str++;
3197
3198 skip_whitespace (str);
3199
3200 if (my_get_expression (&inst.reloc.exp, &str))
3201 return;
3202
3203 if (inst.reloc.exp.X_op != O_constant
3204 && inst.reloc.exp.X_op != O_symbol)
3205 {
3206 inst.error = _("Constant expression expected");
3207 return;
3208 }
3209
3210 if (inst.reloc.exp.X_op == O_constant
3211 && (value = validate_immediate (inst.reloc.exp.X_add_number)) != FAIL)
3212 {
3213 /* This can be done with a mov instruction. */
3214 inst.instruction &= LITERAL_MASK;
3215 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
3216 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
3217 end_of_line (str);
3218 return;
3219 }
3220 else
3221 {
3222 /* Insert into literal pool. */
3223 if (add_to_lit_pool () == FAIL)
3224 {
3225 if (!inst.error)
3226 inst.error = _("literal pool insertion failed");
3227 return;
3228 }
3229
3230 /* Change the instruction exp to point to the pool. */
3231 if (halfword)
3232 {
3233 inst.instruction |= HWOFFSET_IMM;
3234 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
3235 }
3236 else
3237 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
3238 inst.reloc.pc_rel = 1;
3239 inst.instruction |= (REG_PC << 16);
3240 pre_inc = 1;
3241 }
3242 }
3243 else
3244 {
3245 if (my_get_expression (&inst.reloc.exp, &str))
3246 return;
3247
3248 if (halfword)
3249 {
3250 inst.instruction |= HWOFFSET_IMM;
3251 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3252 }
3253 else
3254 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3255 #ifndef TE_WINCE
3256 /* PC rel adjust. */
3257 inst.reloc.exp.X_add_number -= 8;
3258 #endif
3259 inst.reloc.pc_rel = 1;
3260 inst.instruction |= (REG_PC << 16);
3261 pre_inc = 1;
3262 }
3263
3264 if (pre_inc && (flags & TRANS_BIT))
3265 inst.error = _("Pre-increment instruction with translate");
3266
3267 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
3268 end_of_line (str);
3269 return;
3270 }
3271
3272 static long
3273 reg_list (strp)
3274 char ** strp;
3275 {
3276 char * str = * strp;
3277 long range = 0;
3278 int another_range;
3279
3280 /* We come back here if we get ranges concatenated by '+' or '|'. */
3281 do
3282 {
3283 another_range = 0;
3284
3285 if (*str == '{')
3286 {
3287 int in_range = 0;
3288 int cur_reg = -1;
3289
3290 str++;
3291 do
3292 {
3293 int reg;
3294
3295 skip_whitespace (str);
3296
3297 if ((reg = reg_required_here (& str, -1)) == FAIL)
3298 return FAIL;
3299
3300 if (in_range)
3301 {
3302 int i;
3303
3304 if (reg <= cur_reg)
3305 {
3306 inst.error = _("Bad range in register list");
3307 return FAIL;
3308 }
3309
3310 for (i = cur_reg + 1; i < reg; i++)
3311 {
3312 if (range & (1 << i))
3313 as_tsktsk
3314 (_("Warning: Duplicated register (r%d) in register list"),
3315 i);
3316 else
3317 range |= 1 << i;
3318 }
3319 in_range = 0;
3320 }
3321
3322 if (range & (1 << reg))
3323 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3324 reg);
3325 else if (reg <= cur_reg)
3326 as_tsktsk (_("Warning: Register range not in ascending order"));
3327
3328 range |= 1 << reg;
3329 cur_reg = reg;
3330 }
3331 while (skip_past_comma (&str) != FAIL
3332 || (in_range = 1, *str++ == '-'));
3333 str--;
3334 skip_whitespace (str);
3335
3336 if (*str++ != '}')
3337 {
3338 inst.error = _("Missing `}'");
3339 return FAIL;
3340 }
3341 }
3342 else
3343 {
3344 expressionS expr;
3345
3346 if (my_get_expression (&expr, &str))
3347 return FAIL;
3348
3349 if (expr.X_op == O_constant)
3350 {
3351 if (expr.X_add_number
3352 != (expr.X_add_number & 0x0000ffff))
3353 {
3354 inst.error = _("invalid register mask");
3355 return FAIL;
3356 }
3357
3358 if ((range & expr.X_add_number) != 0)
3359 {
3360 int regno = range & expr.X_add_number;
3361
3362 regno &= -regno;
3363 regno = (1 << regno) - 1;
3364 as_tsktsk
3365 (_("Warning: Duplicated register (r%d) in register list"),
3366 regno);
3367 }
3368
3369 range |= expr.X_add_number;
3370 }
3371 else
3372 {
3373 if (inst.reloc.type != 0)
3374 {
3375 inst.error = _("expression too complex");
3376 return FAIL;
3377 }
3378
3379 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
3380 inst.reloc.type = BFD_RELOC_ARM_MULTI;
3381 inst.reloc.pc_rel = 0;
3382 }
3383 }
3384
3385 skip_whitespace (str);
3386
3387 if (*str == '|' || *str == '+')
3388 {
3389 str++;
3390 another_range = 1;
3391 }
3392 }
3393 while (another_range);
3394
3395 *strp = str;
3396 return range;
3397 }
3398
3399 static void
3400 do_ldmstm (str, flags)
3401 char * str;
3402 unsigned long flags;
3403 {
3404 int base_reg;
3405 long range;
3406
3407 skip_whitespace (str);
3408
3409 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
3410 return;
3411
3412 if (base_reg == REG_PC)
3413 {
3414 inst.error = _("r15 not allowed as base register");
3415 return;
3416 }
3417
3418 skip_whitespace (str);
3419
3420 if (*str == '!')
3421 {
3422 flags |= WRITE_BACK;
3423 str++;
3424 }
3425
3426 if (skip_past_comma (&str) == FAIL
3427 || (range = reg_list (&str)) == FAIL)
3428 {
3429 if (! inst.error)
3430 inst.error = BAD_ARGS;
3431 return;
3432 }
3433
3434 if (*str == '^')
3435 {
3436 str++;
3437 flags |= LDM_TYPE_2_OR_3;
3438 }
3439
3440 inst.instruction |= flags | range;
3441 end_of_line (str);
3442 return;
3443 }
3444
3445 static void
3446 do_swi (str, flags)
3447 char * str;
3448 unsigned long flags;
3449 {
3450 skip_whitespace (str);
3451
3452 /* Allow optional leading '#'. */
3453 if (is_immediate_prefix (*str))
3454 str++;
3455
3456 if (my_get_expression (& inst.reloc.exp, & str))
3457 return;
3458
3459 inst.reloc.type = BFD_RELOC_ARM_SWI;
3460 inst.reloc.pc_rel = 0;
3461 inst.instruction |= flags;
3462
3463 end_of_line (str);
3464
3465 return;
3466 }
3467
3468 static void
3469 do_swap (str, flags)
3470 char * str;
3471 unsigned long flags;
3472 {
3473 int reg;
3474
3475 skip_whitespace (str);
3476
3477 if ((reg = reg_required_here (&str, 12)) == FAIL)
3478 return;
3479
3480 if (reg == REG_PC)
3481 {
3482 inst.error = _("r15 not allowed in swap");
3483 return;
3484 }
3485
3486 if (skip_past_comma (&str) == FAIL
3487 || (reg = reg_required_here (&str, 0)) == FAIL)
3488 {
3489 if (!inst.error)
3490 inst.error = BAD_ARGS;
3491 return;
3492 }
3493
3494 if (reg == REG_PC)
3495 {
3496 inst.error = _("r15 not allowed in swap");
3497 return;
3498 }
3499
3500 if (skip_past_comma (&str) == FAIL
3501 || *str++ != '[')
3502 {
3503 inst.error = BAD_ARGS;
3504 return;
3505 }
3506
3507 skip_whitespace (str);
3508
3509 if ((reg = reg_required_here (&str, 16)) == FAIL)
3510 return;
3511
3512 if (reg == REG_PC)
3513 {
3514 inst.error = BAD_PC;
3515 return;
3516 }
3517
3518 skip_whitespace (str);
3519
3520 if (*str++ != ']')
3521 {
3522 inst.error = _("missing ]");
3523 return;
3524 }
3525
3526 inst.instruction |= flags;
3527 end_of_line (str);
3528 return;
3529 }
3530
3531 static void
3532 do_branch (str, flags)
3533 char * str;
3534 unsigned long flags ATTRIBUTE_UNUSED;
3535 {
3536 if (my_get_expression (&inst.reloc.exp, &str))
3537 return;
3538
3539 #ifdef OBJ_ELF
3540 {
3541 char * save_in;
3542
3543 /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
3544 required for the instruction. */
3545
3546 /* arm_parse_reloc () works on input_line_pointer.
3547 We actually want to parse the operands to the branch instruction
3548 passed in 'str'. Save the input pointer and restore it later. */
3549 save_in = input_line_pointer;
3550 input_line_pointer = str;
3551 if (inst.reloc.exp.X_op == O_symbol
3552 && *str == '('
3553 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3554 {
3555 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3556 inst.reloc.pc_rel = 0;
3557 /* Modify str to point to after parsed operands, otherwise
3558 end_of_line() will complain about the (PLT) left in str. */
3559 str = input_line_pointer;
3560 }
3561 else
3562 {
3563 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3564 inst.reloc.pc_rel = 1;
3565 }
3566 input_line_pointer = save_in;
3567 }
3568 #else
3569 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3570 inst.reloc.pc_rel = 1;
3571 #endif /* OBJ_ELF */
3572
3573 end_of_line (str);
3574 return;
3575 }
3576
3577 static void
3578 do_bx (str, flags)
3579 char * str;
3580 unsigned long flags ATTRIBUTE_UNUSED;
3581 {
3582 int reg;
3583
3584 skip_whitespace (str);
3585
3586 if ((reg = reg_required_here (&str, 0)) == FAIL)
3587 {
3588 inst.error = BAD_ARGS;
3589 return;
3590 }
3591
3592 /* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */
3593 if (reg == REG_PC)
3594 as_tsktsk (_("Use of r15 in bx in ARM mode is not really useful"));
3595
3596 end_of_line (str);
3597 }
3598
3599 static void
3600 do_cdp (str, flags)
3601 char * str;
3602 unsigned long flags ATTRIBUTE_UNUSED;
3603 {
3604 /* Co-processor data operation.
3605 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3606 skip_whitespace (str);
3607
3608 if (co_proc_number (&str) == FAIL)
3609 {
3610 if (!inst.error)
3611 inst.error = BAD_ARGS;
3612 return;
3613 }
3614
3615 if (skip_past_comma (&str) == FAIL
3616 || cp_opc_expr (&str, 20,4) == FAIL)
3617 {
3618 if (!inst.error)
3619 inst.error = BAD_ARGS;
3620 return;
3621 }
3622
3623 if (skip_past_comma (&str) == FAIL
3624 || cp_reg_required_here (&str, 12) == FAIL)
3625 {
3626 if (!inst.error)
3627 inst.error = BAD_ARGS;
3628 return;
3629 }
3630
3631 if (skip_past_comma (&str) == FAIL
3632 || cp_reg_required_here (&str, 16) == FAIL)
3633 {
3634 if (!inst.error)
3635 inst.error = BAD_ARGS;
3636 return;
3637 }
3638
3639 if (skip_past_comma (&str) == FAIL
3640 || cp_reg_required_here (&str, 0) == FAIL)
3641 {
3642 if (!inst.error)
3643 inst.error = BAD_ARGS;
3644 return;
3645 }
3646
3647 if (skip_past_comma (&str) == SUCCESS)
3648 {
3649 if (cp_opc_expr (&str, 5, 3) == FAIL)
3650 {
3651 if (!inst.error)
3652 inst.error = BAD_ARGS;
3653 return;
3654 }
3655 }
3656
3657 end_of_line (str);
3658 return;
3659 }
3660
3661 static void
3662 do_lstc (str, flags)
3663 char * str;
3664 unsigned long flags;
3665 {
3666 /* Co-processor register load/store.
3667 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3668
3669 skip_whitespace (str);
3670
3671 if (co_proc_number (&str) == FAIL)
3672 {
3673 if (!inst.error)
3674 inst.error = BAD_ARGS;
3675 return;
3676 }
3677
3678 if (skip_past_comma (&str) == FAIL
3679 || cp_reg_required_here (&str, 12) == FAIL)
3680 {
3681 if (!inst.error)
3682 inst.error = BAD_ARGS;
3683 return;
3684 }
3685
3686 if (skip_past_comma (&str) == FAIL
3687 || cp_address_required_here (&str) == FAIL)
3688 {
3689 if (! inst.error)
3690 inst.error = BAD_ARGS;
3691 return;
3692 }
3693
3694 inst.instruction |= flags;
3695 end_of_line (str);
3696 return;
3697 }
3698
3699 static void
3700 do_co_reg (str, flags)
3701 char * str;
3702 unsigned long flags;
3703 {
3704 /* Co-processor register transfer.
3705 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3706
3707 skip_whitespace (str);
3708
3709 if (co_proc_number (&str) == FAIL)
3710 {
3711 if (!inst.error)
3712 inst.error = BAD_ARGS;
3713 return;
3714 }
3715
3716 if (skip_past_comma (&str) == FAIL
3717 || cp_opc_expr (&str, 21, 3) == FAIL)
3718 {
3719 if (!inst.error)
3720 inst.error = BAD_ARGS;
3721 return;
3722 }
3723
3724 if (skip_past_comma (&str) == FAIL
3725 || reg_required_here (&str, 12) == FAIL)
3726 {
3727 if (!inst.error)
3728 inst.error = BAD_ARGS;
3729 return;
3730 }
3731
3732 if (skip_past_comma (&str) == FAIL
3733 || cp_reg_required_here (&str, 16) == FAIL)
3734 {
3735 if (!inst.error)
3736 inst.error = BAD_ARGS;
3737 return;
3738 }
3739
3740 if (skip_past_comma (&str) == FAIL
3741 || cp_reg_required_here (&str, 0) == FAIL)
3742 {
3743 if (!inst.error)
3744 inst.error = BAD_ARGS;
3745 return;
3746 }
3747
3748 if (skip_past_comma (&str) == SUCCESS)
3749 {
3750 if (cp_opc_expr (&str, 5, 3) == FAIL)
3751 {
3752 if (!inst.error)
3753 inst.error = BAD_ARGS;
3754 return;
3755 }
3756 }
3757 if (flags)
3758 {
3759 inst.error = BAD_COND;
3760 }
3761
3762 end_of_line (str);
3763 return;
3764 }
3765
3766 static void
3767 do_fp_ctrl (str, flags)
3768 char * str;
3769 unsigned long flags ATTRIBUTE_UNUSED;
3770 {
3771 /* FP control registers.
3772 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3773
3774 skip_whitespace (str);
3775
3776 if (reg_required_here (&str, 12) == FAIL)
3777 {
3778 if (!inst.error)
3779 inst.error = BAD_ARGS;
3780 return;
3781 }
3782
3783 end_of_line (str);
3784 return;
3785 }
3786
3787 static void
3788 do_fp_ldst (str, flags)
3789 char * str;
3790 unsigned long flags ATTRIBUTE_UNUSED;
3791 {
3792 skip_whitespace (str);
3793
3794 switch (inst.suffix)
3795 {
3796 case SUFF_S:
3797 break;
3798 case SUFF_D:
3799 inst.instruction |= CP_T_X;
3800 break;
3801 case SUFF_E:
3802 inst.instruction |= CP_T_Y;
3803 break;
3804 case SUFF_P:
3805 inst.instruction |= CP_T_X | CP_T_Y;
3806 break;
3807 default:
3808 abort ();
3809 }
3810
3811 if (fp_reg_required_here (&str, 12) == FAIL)
3812 {
3813 if (!inst.error)
3814 inst.error = BAD_ARGS;
3815 return;
3816 }
3817
3818 if (skip_past_comma (&str) == FAIL
3819 || cp_address_required_here (&str) == FAIL)
3820 {
3821 if (!inst.error)
3822 inst.error = BAD_ARGS;
3823 return;
3824 }
3825
3826 end_of_line (str);
3827 }
3828
3829 static void
3830 do_fp_ldmstm (str, flags)
3831 char * str;
3832 unsigned long flags;
3833 {
3834 int num_regs;
3835
3836 skip_whitespace (str);
3837
3838 if (fp_reg_required_here (&str, 12) == FAIL)
3839 {
3840 if (! inst.error)
3841 inst.error = BAD_ARGS;
3842 return;
3843 }
3844
3845 /* Get Number of registers to transfer. */
3846 if (skip_past_comma (&str) == FAIL
3847 || my_get_expression (&inst.reloc.exp, &str))
3848 {
3849 if (! inst.error)
3850 inst.error = _("constant expression expected");
3851 return;
3852 }
3853
3854 if (inst.reloc.exp.X_op != O_constant)
3855 {
3856 inst.error = _("Constant value required for number of registers");
3857 return;
3858 }
3859
3860 num_regs = inst.reloc.exp.X_add_number;
3861
3862 if (num_regs < 1 || num_regs > 4)
3863 {
3864 inst.error = _("number of registers must be in the range [1:4]");
3865 return;
3866 }
3867
3868 switch (num_regs)
3869 {
3870 case 1:
3871 inst.instruction |= CP_T_X;
3872 break;
3873 case 2:
3874 inst.instruction |= CP_T_Y;
3875 break;
3876 case 3:
3877 inst.instruction |= CP_T_Y | CP_T_X;
3878 break;
3879 case 4:
3880 break;
3881 default:
3882 abort ();
3883 }
3884
3885 if (flags)
3886 {
3887 int reg;
3888 int write_back;
3889 int offset;
3890
3891 /* The instruction specified "ea" or "fd", so we can only accept
3892 [Rn]{!}. The instruction does not really support stacking or
3893 unstacking, so we have to emulate these by setting appropriate
3894 bits and offsets. */
3895 if (skip_past_comma (&str) == FAIL
3896 || *str != '[')
3897 {
3898 if (! inst.error)
3899 inst.error = BAD_ARGS;
3900 return;
3901 }
3902
3903 str++;
3904 skip_whitespace (str);
3905
3906 if ((reg = reg_required_here (&str, 16)) == FAIL)
3907 return;
3908
3909 skip_whitespace (str);
3910
3911 if (*str != ']')
3912 {
3913 inst.error = BAD_ARGS;
3914 return;
3915 }
3916
3917 str++;
3918 if (*str == '!')
3919 {
3920 write_back = 1;
3921 str++;
3922 if (reg == REG_PC)
3923 {
3924 inst.error =
3925 _("R15 not allowed as base register with write-back");
3926 return;
3927 }
3928 }
3929 else
3930 write_back = 0;
3931
3932 if (flags & CP_T_Pre)
3933 {
3934 /* Pre-decrement. */
3935 offset = 3 * num_regs;
3936 if (write_back)
3937 flags |= CP_T_WB;
3938 }
3939 else
3940 {
3941 /* Post-increment. */
3942 if (write_back)
3943 {
3944 flags |= CP_T_WB;
3945 offset = 3 * num_regs;
3946 }
3947 else
3948 {
3949 /* No write-back, so convert this into a standard pre-increment
3950 instruction -- aesthetically more pleasing. */
3951 flags = CP_T_Pre | CP_T_UD;
3952 offset = 0;
3953 }
3954 }
3955
3956 inst.instruction |= flags | offset;
3957 }
3958 else if (skip_past_comma (&str) == FAIL
3959 || cp_address_required_here (&str) == FAIL)
3960 {
3961 if (! inst.error)
3962 inst.error = BAD_ARGS;
3963 return;
3964 }
3965
3966 end_of_line (str);
3967 }
3968
3969 static void
3970 do_fp_dyadic (str, flags)
3971 char * str;
3972 unsigned long flags;
3973 {
3974 skip_whitespace (str);
3975
3976 switch (inst.suffix)
3977 {
3978 case SUFF_S:
3979 break;
3980 case SUFF_D:
3981 inst.instruction |= 0x00000080;
3982 break;
3983 case SUFF_E:
3984 inst.instruction |= 0x00080000;
3985 break;
3986 default:
3987 abort ();
3988 }
3989
3990 if (fp_reg_required_here (&str, 12) == FAIL)
3991 {
3992 if (! inst.error)
3993 inst.error = BAD_ARGS;
3994 return;
3995 }
3996
3997 if (skip_past_comma (&str) == FAIL
3998 || fp_reg_required_here (&str, 16) == FAIL)
3999 {
4000 if (! inst.error)
4001 inst.error = BAD_ARGS;
4002 return;
4003 }
4004
4005 if (skip_past_comma (&str) == FAIL
4006 || fp_op2 (&str) == FAIL)
4007 {
4008 if (! inst.error)
4009 inst.error = BAD_ARGS;
4010 return;
4011 }
4012
4013 inst.instruction |= flags;
4014 end_of_line (str);
4015 return;
4016 }
4017
4018 static void
4019 do_fp_monadic (str, flags)
4020 char * str;
4021 unsigned long flags;
4022 {
4023 skip_whitespace (str);
4024
4025 switch (inst.suffix)
4026 {
4027 case SUFF_S:
4028 break;
4029 case SUFF_D:
4030 inst.instruction |= 0x00000080;
4031 break;
4032 case SUFF_E:
4033 inst.instruction |= 0x00080000;
4034 break;
4035 default:
4036 abort ();
4037 }
4038
4039 if (fp_reg_required_here (&str, 12) == FAIL)
4040 {
4041 if (! inst.error)
4042 inst.error = BAD_ARGS;
4043 return;
4044 }
4045
4046 if (skip_past_comma (&str) == FAIL
4047 || fp_op2 (&str) == FAIL)
4048 {
4049 if (! inst.error)
4050 inst.error = BAD_ARGS;
4051 return;
4052 }
4053
4054 inst.instruction |= flags;
4055 end_of_line (str);
4056 return;
4057 }
4058
4059 static void
4060 do_fp_cmp (str, flags)
4061 char * str;
4062 unsigned long flags;
4063 {
4064 skip_whitespace (str);
4065
4066 if (fp_reg_required_here (&str, 16) == FAIL)
4067 {
4068 if (! inst.error)
4069 inst.error = BAD_ARGS;
4070 return;
4071 }
4072
4073 if (skip_past_comma (&str) == FAIL
4074 || fp_op2 (&str) == FAIL)
4075 {
4076 if (! inst.error)
4077 inst.error = BAD_ARGS;
4078 return;
4079 }
4080
4081 inst.instruction |= flags;
4082 end_of_line (str);
4083 return;
4084 }
4085
4086 static void
4087 do_fp_from_reg (str, flags)
4088 char * str;
4089 unsigned long flags;
4090 {
4091 skip_whitespace (str);
4092
4093 switch (inst.suffix)
4094 {
4095 case SUFF_S:
4096 break;
4097 case SUFF_D:
4098 inst.instruction |= 0x00000080;
4099 break;
4100 case SUFF_E:
4101 inst.instruction |= 0x00080000;
4102 break;
4103 default:
4104 abort ();
4105 }
4106
4107 if (fp_reg_required_here (&str, 16) == FAIL)
4108 {
4109 if (! inst.error)
4110 inst.error = BAD_ARGS;
4111 return;
4112 }
4113
4114 if (skip_past_comma (&str) == FAIL
4115 || reg_required_here (&str, 12) == FAIL)
4116 {
4117 if (! inst.error)
4118 inst.error = BAD_ARGS;
4119 return;
4120 }
4121
4122 inst.instruction |= flags;
4123 end_of_line (str);
4124 return;
4125 }
4126
4127 static void
4128 do_fp_to_reg (str, flags)
4129 char * str;
4130 unsigned long flags;
4131 {
4132 skip_whitespace (str);
4133
4134 if (reg_required_here (&str, 12) == FAIL)
4135 return;
4136
4137 if (skip_past_comma (&str) == FAIL
4138 || fp_reg_required_here (&str, 0) == FAIL)
4139 {
4140 if (! inst.error)
4141 inst.error = BAD_ARGS;
4142 return;
4143 }
4144
4145 inst.instruction |= flags;
4146 end_of_line (str);
4147 return;
4148 }
4149
4150 /* Thumb specific routines. */
4151
4152 /* Parse and validate that a register is of the right form, this saves
4153 repeated checking of this information in many similar cases.
4154 Unlike the 32-bit case we do not insert the register into the opcode
4155 here, since the position is often unknown until the full instruction
4156 has been parsed. */
4157
4158 static int
4159 thumb_reg (strp, hi_lo)
4160 char ** strp;
4161 int hi_lo;
4162 {
4163 int reg;
4164
4165 if ((reg = reg_required_here (strp, -1)) == FAIL)
4166 return FAIL;
4167
4168 switch (hi_lo)
4169 {
4170 case THUMB_REG_LO:
4171 if (reg > 7)
4172 {
4173 inst.error = _("lo register required");
4174 return FAIL;
4175 }
4176 break;
4177
4178 case THUMB_REG_HI:
4179 if (reg < 8)
4180 {
4181 inst.error = _("hi register required");
4182 return FAIL;
4183 }
4184 break;
4185
4186 default:
4187 break;
4188 }
4189
4190 return reg;
4191 }
4192
4193 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
4194 was SUB. */
4195
4196 static void
4197 thumb_add_sub (str, subtract)
4198 char * str;
4199 int subtract;
4200 {
4201 int Rd, Rs, Rn = FAIL;
4202
4203 skip_whitespace (str);
4204
4205 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4206 || skip_past_comma (&str) == FAIL)
4207 {
4208 if (! inst.error)
4209 inst.error = BAD_ARGS;
4210 return;
4211 }
4212
4213 if (is_immediate_prefix (*str))
4214 {
4215 Rs = Rd;
4216 str++;
4217 if (my_get_expression (&inst.reloc.exp, &str))
4218 return;
4219 }
4220 else
4221 {
4222 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4223 return;
4224
4225 if (skip_past_comma (&str) == FAIL)
4226 {
4227 /* Two operand format, shuffle the registers
4228 and pretend there are 3. */
4229 Rn = Rs;
4230 Rs = Rd;
4231 }
4232 else if (is_immediate_prefix (*str))
4233 {
4234 str++;
4235 if (my_get_expression (&inst.reloc.exp, &str))
4236 return;
4237 }
4238 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4239 return;
4240 }
4241
4242 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4243 for the latter case, EXPR contains the immediate that was found. */
4244 if (Rn != FAIL)
4245 {
4246 /* All register format. */
4247 if (Rd > 7 || Rs > 7 || Rn > 7)
4248 {
4249 if (Rs != Rd)
4250 {
4251 inst.error = _("dest and source1 must be the same register");
4252 return;
4253 }
4254
4255 /* Can't do this for SUB. */
4256 if (subtract)
4257 {
4258 inst.error = _("subtract valid only on lo regs");
4259 return;
4260 }
4261
4262 inst.instruction = (T_OPCODE_ADD_HI
4263 | (Rd > 7 ? THUMB_H1 : 0)
4264 | (Rn > 7 ? THUMB_H2 : 0));
4265 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
4266 }
4267 else
4268 {
4269 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
4270 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
4271 }
4272 }
4273 else
4274 {
4275 /* Immediate expression, now things start to get nasty. */
4276
4277 /* First deal with HI regs, only very restricted cases allowed:
4278 Adjusting SP, and using PC or SP to get an address. */
4279 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
4280 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
4281 {
4282 inst.error = _("invalid Hi register with immediate");
4283 return;
4284 }
4285
4286 if (inst.reloc.exp.X_op != O_constant)
4287 {
4288 /* Value isn't known yet, all we can do is store all the fragments
4289 we know about in the instruction and let the reloc hacking
4290 work it all out. */
4291 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
4292 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4293 }
4294 else
4295 {
4296 int offset = inst.reloc.exp.X_add_number;
4297
4298 if (subtract)
4299 offset = -offset;
4300
4301 if (offset < 0)
4302 {
4303 offset = -offset;
4304 subtract = 1;
4305
4306 /* Quick check, in case offset is MIN_INT. */
4307 if (offset < 0)
4308 {
4309 inst.error = _("immediate value out of range");
4310 return;
4311 }
4312 }
4313 else
4314 subtract = 0;
4315
4316 if (Rd == REG_SP)
4317 {
4318 if (offset & ~0x1fc)
4319 {
4320 inst.error = _("invalid immediate value for stack adjust");
4321 return;
4322 }
4323 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
4324 inst.instruction |= offset >> 2;
4325 }
4326 else if (Rs == REG_PC || Rs == REG_SP)
4327 {
4328 if (subtract
4329 || (offset & ~0x3fc))
4330 {
4331 inst.error = _("invalid immediate for address calculation");
4332 return;
4333 }
4334 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
4335 : T_OPCODE_ADD_SP);
4336 inst.instruction |= (Rd << 8) | (offset >> 2);
4337 }
4338 else if (Rs == Rd)
4339 {
4340 if (offset & ~0xff)
4341 {
4342 inst.error = _("immediate value out of range");
4343 return;
4344 }
4345 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
4346 inst.instruction |= (Rd << 8) | offset;
4347 }
4348 else
4349 {
4350 if (offset & ~0x7)
4351 {
4352 inst.error = _("immediate value out of range");
4353 return;
4354 }
4355 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
4356 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
4357 }
4358 }
4359 }
4360
4361 end_of_line (str);
4362 }
4363
4364 static void
4365 thumb_shift (str, shift)
4366 char * str;
4367 int shift;
4368 {
4369 int Rd, Rs, Rn = FAIL;
4370
4371 skip_whitespace (str);
4372
4373 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4374 || skip_past_comma (&str) == FAIL)
4375 {
4376 if (! inst.error)
4377 inst.error = BAD_ARGS;
4378 return;
4379 }
4380
4381 if (is_immediate_prefix (*str))
4382 {
4383 /* Two operand immediate format, set Rs to Rd. */
4384 Rs = Rd;
4385 str ++;
4386 if (my_get_expression (&inst.reloc.exp, &str))
4387 return;
4388 }
4389 else
4390 {
4391 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4392 return;
4393
4394 if (skip_past_comma (&str) == FAIL)
4395 {
4396 /* Two operand format, shuffle the registers
4397 and pretend there are 3. */
4398 Rn = Rs;
4399 Rs = Rd;
4400 }
4401 else if (is_immediate_prefix (*str))
4402 {
4403 str++;
4404 if (my_get_expression (&inst.reloc.exp, &str))
4405 return;
4406 }
4407 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4408 return;
4409 }
4410
4411 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4412 for the latter case, EXPR contains the immediate that was found. */
4413
4414 if (Rn != FAIL)
4415 {
4416 if (Rs != Rd)
4417 {
4418 inst.error = _("source1 and dest must be same register");
4419 return;
4420 }
4421
4422 switch (shift)
4423 {
4424 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
4425 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
4426 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
4427 }
4428
4429 inst.instruction |= Rd | (Rn << 3);
4430 }
4431 else
4432 {
4433 switch (shift)
4434 {
4435 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
4436 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
4437 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
4438 }
4439
4440 if (inst.reloc.exp.X_op != O_constant)
4441 {
4442 /* Value isn't known yet, create a dummy reloc and let reloc
4443 hacking fix it up. */
4444 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
4445 }
4446 else
4447 {
4448 unsigned shift_value = inst.reloc.exp.X_add_number;
4449
4450 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
4451 {
4452 inst.error = _("Invalid immediate for shift");
4453 return;
4454 }
4455
4456 /* Shifts of zero are handled by converting to LSL. */
4457 if (shift_value == 0)
4458 inst.instruction = T_OPCODE_LSL_I;
4459
4460 /* Shifts of 32 are encoded as a shift of zero. */
4461 if (shift_value == 32)
4462 shift_value = 0;
4463
4464 inst.instruction |= shift_value << 6;
4465 }
4466
4467 inst.instruction |= Rd | (Rs << 3);
4468 }
4469
4470 end_of_line (str);
4471 }
4472
4473 static void
4474 thumb_mov_compare (str, move)
4475 char * str;
4476 int move;
4477 {
4478 int Rd, Rs = FAIL;
4479
4480 skip_whitespace (str);
4481
4482 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4483 || skip_past_comma (&str) == FAIL)
4484 {
4485 if (! inst.error)
4486 inst.error = BAD_ARGS;
4487 return;
4488 }
4489
4490 if (is_immediate_prefix (*str))
4491 {
4492 str++;
4493 if (my_get_expression (&inst.reloc.exp, &str))
4494 return;
4495 }
4496 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4497 return;
4498
4499 if (Rs != FAIL)
4500 {
4501 if (Rs < 8 && Rd < 8)
4502 {
4503 if (move == THUMB_MOVE)
4504 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4505 since a MOV instruction produces unpredictable results. */
4506 inst.instruction = T_OPCODE_ADD_I3;
4507 else
4508 inst.instruction = T_OPCODE_CMP_LR;
4509 inst.instruction |= Rd | (Rs << 3);
4510 }
4511 else
4512 {
4513 if (move == THUMB_MOVE)
4514 inst.instruction = T_OPCODE_MOV_HR;
4515 else
4516 inst.instruction = T_OPCODE_CMP_HR;
4517
4518 if (Rd > 7)
4519 inst.instruction |= THUMB_H1;
4520
4521 if (Rs > 7)
4522 inst.instruction |= THUMB_H2;
4523
4524 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4525 }
4526 }
4527 else
4528 {
4529 if (Rd > 7)
4530 {
4531 inst.error = _("only lo regs allowed with immediate");
4532 return;
4533 }
4534
4535 if (move == THUMB_MOVE)
4536 inst.instruction = T_OPCODE_MOV_I8;
4537 else
4538 inst.instruction = T_OPCODE_CMP_I8;
4539
4540 inst.instruction |= Rd << 8;
4541
4542 if (inst.reloc.exp.X_op != O_constant)
4543 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4544 else
4545 {
4546 unsigned value = inst.reloc.exp.X_add_number;
4547
4548 if (value > 255)
4549 {
4550 inst.error = _("invalid immediate");
4551 return;
4552 }
4553
4554 inst.instruction |= value;
4555 }
4556 }
4557
4558 end_of_line (str);
4559 }
4560
4561 static void
4562 thumb_load_store (str, load_store, size)
4563 char * str;
4564 int load_store;
4565 int size;
4566 {
4567 int Rd, Rb, Ro = FAIL;
4568
4569 skip_whitespace (str);
4570
4571 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4572 || skip_past_comma (&str) == FAIL)
4573 {
4574 if (! inst.error)
4575 inst.error = BAD_ARGS;
4576 return;
4577 }
4578
4579 if (*str == '[')
4580 {
4581 str++;
4582 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4583 return;
4584
4585 if (skip_past_comma (&str) != FAIL)
4586 {
4587 if (is_immediate_prefix (*str))
4588 {
4589 str++;
4590 if (my_get_expression (&inst.reloc.exp, &str))
4591 return;
4592 }
4593 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4594 return;
4595 }
4596 else
4597 {
4598 inst.reloc.exp.X_op = O_constant;
4599 inst.reloc.exp.X_add_number = 0;
4600 }
4601
4602 if (*str != ']')
4603 {
4604 inst.error = _("expected ']'");
4605 return;
4606 }
4607 str++;
4608 }
4609 else if (*str == '=')
4610 {
4611 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
4612 str++;
4613
4614 skip_whitespace (str);
4615
4616 if (my_get_expression (& inst.reloc.exp, & str))
4617 return;
4618
4619 end_of_line (str);
4620
4621 if ( inst.reloc.exp.X_op != O_constant
4622 && inst.reloc.exp.X_op != O_symbol)
4623 {
4624 inst.error = "Constant expression expected";
4625 return;
4626 }
4627
4628 if (inst.reloc.exp.X_op == O_constant
4629 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4630 {
4631 /* This can be done with a mov instruction. */
4632
4633 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4634 inst.instruction |= inst.reloc.exp.X_add_number;
4635 return;
4636 }
4637
4638 /* Insert into literal pool. */
4639 if (add_to_lit_pool () == FAIL)
4640 {
4641 if (!inst.error)
4642 inst.error = "literal pool insertion failed";
4643 return;
4644 }
4645
4646 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4647 inst.reloc.pc_rel = 1;
4648 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4649 /* Adjust ARM pipeline offset to Thumb. */
4650 inst.reloc.exp.X_add_number += 4;
4651
4652 return;
4653 }
4654 else
4655 {
4656 if (my_get_expression (&inst.reloc.exp, &str))
4657 return;
4658
4659 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4660 inst.reloc.pc_rel = 1;
4661 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset. */
4662 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4663 end_of_line (str);
4664 return;
4665 }
4666
4667 if (Rb == REG_PC || Rb == REG_SP)
4668 {
4669 if (size != THUMB_WORD)
4670 {
4671 inst.error = _("byte or halfword not valid for base register");
4672 return;
4673 }
4674 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4675 {
4676 inst.error = _("R15 based store not allowed");
4677 return;
4678 }
4679 else if (Ro != FAIL)
4680 {
4681 inst.error = _("Invalid base register for register offset");
4682 return;
4683 }
4684
4685 if (Rb == REG_PC)
4686 inst.instruction = T_OPCODE_LDR_PC;
4687 else if (load_store == THUMB_LOAD)
4688 inst.instruction = T_OPCODE_LDR_SP;
4689 else
4690 inst.instruction = T_OPCODE_STR_SP;
4691
4692 inst.instruction |= Rd << 8;
4693 if (inst.reloc.exp.X_op == O_constant)
4694 {
4695 unsigned offset = inst.reloc.exp.X_add_number;
4696
4697 if (offset & ~0x3fc)
4698 {
4699 inst.error = _("invalid offset");
4700 return;
4701 }
4702
4703 inst.instruction |= offset >> 2;
4704 }
4705 else
4706 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4707 }
4708 else if (Rb > 7)
4709 {
4710 inst.error = _("invalid base register in load/store");
4711 return;
4712 }
4713 else if (Ro == FAIL)
4714 {
4715 /* Immediate offset. */
4716 if (size == THUMB_WORD)
4717 inst.instruction = (load_store == THUMB_LOAD
4718 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4719 else if (size == THUMB_HALFWORD)
4720 inst.instruction = (load_store == THUMB_LOAD
4721 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4722 else
4723 inst.instruction = (load_store == THUMB_LOAD
4724 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4725
4726 inst.instruction |= Rd | (Rb << 3);
4727
4728 if (inst.reloc.exp.X_op == O_constant)
4729 {
4730 unsigned offset = inst.reloc.exp.X_add_number;
4731
4732 if (offset & ~(0x1f << size))
4733 {
4734 inst.error = _("Invalid offset");
4735 return;
4736 }
4737 inst.instruction |= (offset >> size) << 6;
4738 }
4739 else
4740 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4741 }
4742 else
4743 {
4744 /* Register offset. */
4745 if (size == THUMB_WORD)
4746 inst.instruction = (load_store == THUMB_LOAD
4747 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4748 else if (size == THUMB_HALFWORD)
4749 inst.instruction = (load_store == THUMB_LOAD
4750 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4751 else
4752 inst.instruction = (load_store == THUMB_LOAD
4753 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4754
4755 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4756 }
4757
4758 end_of_line (str);
4759 }
4760
4761 static void
4762 do_t_nop (str)
4763 char * str;
4764 {
4765 /* Do nothing. */
4766 end_of_line (str);
4767 return;
4768 }
4769
4770 /* Handle the Format 4 instructions that do not have equivalents in other
4771 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4772 BIC and MVN. */
4773
4774 static void
4775 do_t_arit (str)
4776 char * str;
4777 {
4778 int Rd, Rs, Rn;
4779
4780 skip_whitespace (str);
4781
4782 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4783 || skip_past_comma (&str) == FAIL
4784 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4785 {
4786 inst.error = BAD_ARGS;
4787 return;
4788 }
4789
4790 if (skip_past_comma (&str) != FAIL)
4791 {
4792 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4793 (It isn't allowed for CMP either, but that isn't handled by this
4794 function.) */
4795 if (inst.instruction == T_OPCODE_TST
4796 || inst.instruction == T_OPCODE_CMN
4797 || inst.instruction == T_OPCODE_NEG
4798 || inst.instruction == T_OPCODE_MVN)
4799 {
4800 inst.error = BAD_ARGS;
4801 return;
4802 }
4803
4804 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4805 return;
4806
4807 if (Rs != Rd)
4808 {
4809 inst.error = _("dest and source1 one must be the same register");
4810 return;
4811 }
4812 Rs = Rn;
4813 }
4814
4815 if (inst.instruction == T_OPCODE_MUL
4816 && Rs == Rd)
4817 as_tsktsk (_("Rs and Rd must be different in MUL"));
4818
4819 inst.instruction |= Rd | (Rs << 3);
4820 end_of_line (str);
4821 }
4822
4823 static void
4824 do_t_add (str)
4825 char * str;
4826 {
4827 thumb_add_sub (str, 0);
4828 }
4829
4830 static void
4831 do_t_asr (str)
4832 char * str;
4833 {
4834 thumb_shift (str, THUMB_ASR);
4835 }
4836
4837 static void
4838 do_t_branch9 (str)
4839 char * str;
4840 {
4841 if (my_get_expression (&inst.reloc.exp, &str))
4842 return;
4843 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4844 inst.reloc.pc_rel = 1;
4845 end_of_line (str);
4846 }
4847
4848 static void
4849 do_t_branch12 (str)
4850 char * str;
4851 {
4852 if (my_get_expression (&inst.reloc.exp, &str))
4853 return;
4854 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4855 inst.reloc.pc_rel = 1;
4856 end_of_line (str);
4857 }
4858
4859 /* Find the real, Thumb encoded start of a Thumb function. */
4860
4861 static symbolS *
4862 find_real_start (symbolP)
4863 symbolS * symbolP;
4864 {
4865 char * real_start;
4866 const char * name = S_GET_NAME (symbolP);
4867 symbolS * new_target;
4868
4869 /* This definiton must agree with the one in gcc/config/arm/thumb.c. */
4870 #define STUB_NAME ".real_start_of"
4871
4872 if (name == NULL)
4873 abort ();
4874
4875 /* Names that start with '.' are local labels, not function entry points.
4876 The compiler may generate BL instructions to these labels because it
4877 needs to perform a branch to a far away location. */
4878 if (name[0] == '.')
4879 return symbolP;
4880
4881 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
4882 sprintf (real_start, "%s%s", STUB_NAME, name);
4883
4884 new_target = symbol_find (real_start);
4885
4886 if (new_target == NULL)
4887 {
4888 as_warn ("Failed to find real start of function: %s\n", name);
4889 new_target = symbolP;
4890 }
4891
4892 free (real_start);
4893
4894 return new_target;
4895 }
4896
4897 static void
4898 do_t_branch23 (str)
4899 char * str;
4900 {
4901 if (my_get_expression (& inst.reloc.exp, & str))
4902 return;
4903
4904 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4905 inst.reloc.pc_rel = 1;
4906 end_of_line (str);
4907
4908 /* If the destination of the branch is a defined symbol which does not have
4909 the THUMB_FUNC attribute, then we must be calling a function which has
4910 the (interfacearm) attribute. We look for the Thumb entry point to that
4911 function and change the branch to refer to that function instead. */
4912 if ( inst.reloc.exp.X_op == O_symbol
4913 && inst.reloc.exp.X_add_symbol != NULL
4914 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
4915 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
4916 inst.reloc.exp.X_add_symbol =
4917 find_real_start (inst.reloc.exp.X_add_symbol);
4918 }
4919
4920 static void
4921 do_t_bx (str)
4922 char * str;
4923 {
4924 int reg;
4925
4926 skip_whitespace (str);
4927
4928 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4929 return;
4930
4931 /* This sets THUMB_H2 from the top bit of reg. */
4932 inst.instruction |= reg << 3;
4933
4934 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4935 should cause the alignment to be checked once it is known. This is
4936 because BX PC only works if the instruction is word aligned. */
4937
4938 end_of_line (str);
4939 }
4940
4941 static void
4942 do_t_compare (str)
4943 char * str;
4944 {
4945 thumb_mov_compare (str, THUMB_COMPARE);
4946 }
4947
4948 static void
4949 do_t_ldmstm (str)
4950 char * str;
4951 {
4952 int Rb;
4953 long range;
4954
4955 skip_whitespace (str);
4956
4957 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4958 return;
4959
4960 if (*str != '!')
4961 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4962 else
4963 str++;
4964
4965 if (skip_past_comma (&str) == FAIL
4966 || (range = reg_list (&str)) == FAIL)
4967 {
4968 if (! inst.error)
4969 inst.error = BAD_ARGS;
4970 return;
4971 }
4972
4973 if (inst.reloc.type != BFD_RELOC_NONE)
4974 {
4975 /* This really doesn't seem worth it. */
4976 inst.reloc.type = BFD_RELOC_NONE;
4977 inst.error = _("Expression too complex");
4978 return;
4979 }
4980
4981 if (range & ~0xff)
4982 {
4983 inst.error = _("only lo-regs valid in load/store multiple");
4984 return;
4985 }
4986
4987 inst.instruction |= (Rb << 8) | range;
4988 end_of_line (str);
4989 }
4990
4991 static void
4992 do_t_ldr (str)
4993 char * str;
4994 {
4995 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
4996 }
4997
4998 static void
4999 do_t_ldrb (str)
5000 char * str;
5001 {
5002 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
5003 }
5004
5005 static void
5006 do_t_ldrh (str)
5007 char * str;
5008 {
5009 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
5010 }
5011
5012 static void
5013 do_t_lds (str)
5014 char * str;
5015 {
5016 int Rd, Rb, Ro;
5017
5018 skip_whitespace (str);
5019
5020 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5021 || skip_past_comma (&str) == FAIL
5022 || *str++ != '['
5023 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5024 || skip_past_comma (&str) == FAIL
5025 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5026 || *str++ != ']')
5027 {
5028 if (! inst.error)
5029 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
5030 return;
5031 }
5032
5033 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
5034 end_of_line (str);
5035 }
5036
5037 static void
5038 do_t_lsl (str)
5039 char * str;
5040 {
5041 thumb_shift (str, THUMB_LSL);
5042 }
5043
5044 static void
5045 do_t_lsr (str)
5046 char * str;
5047 {
5048 thumb_shift (str, THUMB_LSR);
5049 }
5050
5051 static void
5052 do_t_mov (str)
5053 char * str;
5054 {
5055 thumb_mov_compare (str, THUMB_MOVE);
5056 }
5057
5058 static void
5059 do_t_push_pop (str)
5060 char * str;
5061 {
5062 long range;
5063
5064 skip_whitespace (str);
5065
5066 if ((range = reg_list (&str)) == FAIL)
5067 {
5068 if (! inst.error)
5069 inst.error = BAD_ARGS;
5070 return;
5071 }
5072
5073 if (inst.reloc.type != BFD_RELOC_NONE)
5074 {
5075 /* This really doesn't seem worth it. */
5076 inst.reloc.type = BFD_RELOC_NONE;
5077 inst.error = _("Expression too complex");
5078 return;
5079 }
5080
5081 if (range & ~0xff)
5082 {
5083 if ((inst.instruction == T_OPCODE_PUSH
5084 && (range & ~0xff) == 1 << REG_LR)
5085 || (inst.instruction == T_OPCODE_POP
5086 && (range & ~0xff) == 1 << REG_PC))
5087 {
5088 inst.instruction |= THUMB_PP_PC_LR;
5089 range &= 0xff;
5090 }
5091 else
5092 {
5093 inst.error = _("invalid register list to push/pop instruction");
5094 return;
5095 }
5096 }
5097
5098 inst.instruction |= range;
5099 end_of_line (str);
5100 }
5101
5102 static void
5103 do_t_str (str)
5104 char * str;
5105 {
5106 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
5107 }
5108
5109 static void
5110 do_t_strb (str)
5111 char * str;
5112 {
5113 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
5114 }
5115
5116 static void
5117 do_t_strh (str)
5118 char * str;
5119 {
5120 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
5121 }
5122
5123 static void
5124 do_t_sub (str)
5125 char * str;
5126 {
5127 thumb_add_sub (str, 1);
5128 }
5129
5130 static void
5131 do_t_swi (str)
5132 char * str;
5133 {
5134 skip_whitespace (str);
5135
5136 if (my_get_expression (&inst.reloc.exp, &str))
5137 return;
5138
5139 inst.reloc.type = BFD_RELOC_ARM_SWI;
5140 end_of_line (str);
5141 return;
5142 }
5143
5144 static void
5145 do_t_adr (str)
5146 char * str;
5147 {
5148 int reg;
5149
5150 /* This is a pseudo-op of the form "adr rd, label" to be converted
5151 into a relative address of the form "add rd, pc, #label-.-4". */
5152 skip_whitespace (str);
5153
5154 /* Store Rd in temporary location inside instruction. */
5155 if ((reg = reg_required_here (&str, 4)) == FAIL
5156 || (reg > 7) /* For Thumb reg must be r0..r7. */
5157 || skip_past_comma (&str) == FAIL
5158 || my_get_expression (&inst.reloc.exp, &str))
5159 {
5160 if (!inst.error)
5161 inst.error = BAD_ARGS;
5162 return;
5163 }
5164
5165 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5166 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
5167 inst.reloc.pc_rel = 1;
5168 inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */
5169
5170 end_of_line (str);
5171 }
5172
5173 static void
5174 insert_reg (entry)
5175 int entry;
5176 {
5177 int len = strlen (reg_table[entry].name) + 2;
5178 char * buf = (char *) xmalloc (len);
5179 char * buf2 = (char *) xmalloc (len);
5180 int i = 0;
5181
5182 #ifdef REGISTER_PREFIX
5183 buf[i++] = REGISTER_PREFIX;
5184 #endif
5185
5186 strcpy (buf + i, reg_table[entry].name);
5187
5188 for (i = 0; buf[i]; i++)
5189 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
5190
5191 buf2[i] = '\0';
5192
5193 hash_insert (arm_reg_hsh, buf, (PTR) & reg_table[entry]);
5194 hash_insert (arm_reg_hsh, buf2, (PTR) & reg_table[entry]);
5195 }
5196
5197 static void
5198 insert_reg_alias (str, regnum)
5199 char *str;
5200 int regnum;
5201 {
5202 struct reg_entry *new =
5203 (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
5204 char *name = xmalloc (strlen (str) + 1);
5205 strcpy (name, str);
5206
5207 new->name = name;
5208 new->number = regnum;
5209
5210 hash_insert (arm_reg_hsh, name, (PTR) new);
5211 }
5212
5213 static void
5214 set_constant_flonums ()
5215 {
5216 int i;
5217
5218 for (i = 0; i < NUM_FLOAT_VALS; i++)
5219 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
5220 abort ();
5221 }
5222
5223 void
5224 md_begin ()
5225 {
5226 unsigned mach;
5227 unsigned int i;
5228
5229 if ( (arm_ops_hsh = hash_new ()) == NULL
5230 || (arm_tops_hsh = hash_new ()) == NULL
5231 || (arm_cond_hsh = hash_new ()) == NULL
5232 || (arm_shift_hsh = hash_new ()) == NULL
5233 || (arm_reg_hsh = hash_new ()) == NULL
5234 || (arm_psr_hsh = hash_new ()) == NULL)
5235 as_fatal (_("Virtual memory exhausted"));
5236
5237 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
5238 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
5239 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
5240 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
5241 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
5242 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
5243 for (i = 0; i < sizeof (shift) / sizeof (struct asm_shift); i++)
5244 hash_insert (arm_shift_hsh, shift[i].template, (PTR) (shift + i));
5245 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
5246 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
5247
5248 for (i = 0; reg_table[i].name; i++)
5249 insert_reg (i);
5250
5251 set_constant_flonums ();
5252
5253 #if defined OBJ_COFF || defined OBJ_ELF
5254 {
5255 unsigned int flags = 0;
5256
5257 /* Set the flags in the private structure. */
5258 if (uses_apcs_26) flags |= F_APCS26;
5259 if (support_interwork) flags |= F_INTERWORK;
5260 if (uses_apcs_float) flags |= F_APCS_FLOAT;
5261 if (pic_code) flags |= F_PIC;
5262 if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
5263
5264 bfd_set_private_flags (stdoutput, flags);
5265 }
5266 #endif
5267
5268 /* Record the CPU type as well. */
5269 switch (cpu_variant & ARM_CPU_MASK)
5270 {
5271 case ARM_2:
5272 mach = bfd_mach_arm_2;
5273 break;
5274
5275 case ARM_3: /* Also ARM_250. */
5276 mach = bfd_mach_arm_2a;
5277 break;
5278
5279 default:
5280 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */
5281 mach = bfd_mach_arm_4;
5282 break;
5283
5284 case ARM_7: /* Also ARM_6. */
5285 mach = bfd_mach_arm_3;
5286 break;
5287 }
5288
5289 /* Catch special cases. */
5290 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
5291 {
5292 if (cpu_variant & (ARM_EXT_V5 & ARM_THUMB))
5293 mach = bfd_mach_arm_5T;
5294 else if (cpu_variant & ARM_EXT_V5)
5295 mach = bfd_mach_arm_5;
5296 else if (cpu_variant & ARM_THUMB)
5297 mach = bfd_mach_arm_4T;
5298 else if ((cpu_variant & ARM_ARCH_V4) == ARM_ARCH_V4)
5299 mach = bfd_mach_arm_4;
5300 else if (cpu_variant & ARM_LONGMUL)
5301 mach = bfd_mach_arm_3M;
5302 }
5303
5304 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
5305 }
5306
5307 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5308 for use in the a.out file, and stores them in the array pointed to by buf.
5309 This knows about the endian-ness of the target machine and does
5310 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5311 2 (short) and 4 (long) Floating numbers are put out as a series of
5312 LITTLENUMS (shorts, here at least). */
5313
5314 void
5315 md_number_to_chars (buf, val, n)
5316 char * buf;
5317 valueT val;
5318 int n;
5319 {
5320 if (target_big_endian)
5321 number_to_chars_bigendian (buf, val, n);
5322 else
5323 number_to_chars_littleendian (buf, val, n);
5324 }
5325
5326 static valueT
5327 md_chars_to_number (buf, n)
5328 char * buf;
5329 int n;
5330 {
5331 valueT result = 0;
5332 unsigned char * where = (unsigned char *) buf;
5333
5334 if (target_big_endian)
5335 {
5336 while (n--)
5337 {
5338 result <<= 8;
5339 result |= (*where++ & 255);
5340 }
5341 }
5342 else
5343 {
5344 while (n--)
5345 {
5346 result <<= 8;
5347 result |= (where[n] & 255);
5348 }
5349 }
5350
5351 return result;
5352 }
5353
5354 /* Turn a string in input_line_pointer into a floating point constant
5355 of type TYPE, and store the appropriate bytes in *LITP. The number
5356 of LITTLENUMS emitted is stored in *SIZEP. An error message is
5357 returned, or NULL on OK.
5358
5359 Note that fp constants aren't represent in the normal way on the ARM.
5360 In big endian mode, things are as expected. However, in little endian
5361 mode fp constants are big-endian word-wise, and little-endian byte-wise
5362 within the words. For example, (double) 1.1 in big endian mode is
5363 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5364 the byte sequence 99 99 f1 3f 9a 99 99 99.
5365
5366 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5367
5368 char *
5369 md_atof (type, litP, sizeP)
5370 char type;
5371 char * litP;
5372 int * sizeP;
5373 {
5374 int prec;
5375 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5376 char *t;
5377 int i;
5378
5379 switch (type)
5380 {
5381 case 'f':
5382 case 'F':
5383 case 's':
5384 case 'S':
5385 prec = 2;
5386 break;
5387
5388 case 'd':
5389 case 'D':
5390 case 'r':
5391 case 'R':
5392 prec = 4;
5393 break;
5394
5395 case 'x':
5396 case 'X':
5397 prec = 6;
5398 break;
5399
5400 case 'p':
5401 case 'P':
5402 prec = 6;
5403 break;
5404
5405 default:
5406 *sizeP = 0;
5407 return _("Bad call to MD_ATOF()");
5408 }
5409
5410 t = atof_ieee (input_line_pointer, type, words);
5411 if (t)
5412 input_line_pointer = t;
5413 *sizeP = prec * 2;
5414
5415 if (target_big_endian)
5416 {
5417 for (i = 0; i < prec; i++)
5418 {
5419 md_number_to_chars (litP, (valueT) words[i], 2);
5420 litP += 2;
5421 }
5422 }
5423 else
5424 {
5425 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5426 8 byte float the order is 1 0 3 2. */
5427 for (i = 0; i < prec; i += 2)
5428 {
5429 md_number_to_chars (litP, (valueT) words[i + 1], 2);
5430 md_number_to_chars (litP + 2, (valueT) words[i], 2);
5431 litP += 4;
5432 }
5433 }
5434
5435 return 0;
5436 }
5437
5438 /* The knowledge of the PC's pipeline offset is built into the insns
5439 themselves. */
5440
5441 long
5442 md_pcrel_from (fixP)
5443 fixS * fixP;
5444 {
5445 if (fixP->fx_addsy
5446 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
5447 && fixP->fx_subsy == NULL)
5448 return 0;
5449
5450 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
5451 {
5452 /* PC relative addressing on the Thumb is slightly odd
5453 as the bottom two bits of the PC are forced to zero
5454 for the calculation. */
5455 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
5456 }
5457
5458 #ifdef TE_WINCE
5459 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
5460 so we un-adjust here to compensate for the accomodation. */
5461 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
5462 #else
5463 return fixP->fx_where + fixP->fx_frag->fr_address;
5464 #endif
5465 }
5466
5467 /* Round up a section size to the appropriate boundary. */
5468
5469 valueT
5470 md_section_align (segment, size)
5471 segT segment ATTRIBUTE_UNUSED;
5472 valueT size;
5473 {
5474 #ifdef OBJ_ELF
5475 return size;
5476 #else
5477 /* Round all sects to multiple of 4. */
5478 return (size + 3) & ~3;
5479 #endif
5480 }
5481
5482 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
5483 Otherwise we have no need to default values of symbols. */
5484
5485 symbolS *
5486 md_undefined_symbol (name)
5487 char * name ATTRIBUTE_UNUSED;
5488 {
5489 #ifdef OBJ_ELF
5490 if (name[0] == '_' && name[1] == 'G'
5491 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5492 {
5493 if (!GOT_symbol)
5494 {
5495 if (symbol_find (name))
5496 as_bad ("GOT already in the symbol table");
5497
5498 GOT_symbol = symbol_new (name, undefined_section,
5499 (valueT) 0, & zero_address_frag);
5500 }
5501
5502 return GOT_symbol;
5503 }
5504 #endif
5505
5506 return 0;
5507 }
5508
5509 /* arm_reg_parse () := if it looks like a register, return its token and
5510 advance the pointer. */
5511
5512 static int
5513 arm_reg_parse (ccp)
5514 register char ** ccp;
5515 {
5516 char * start = * ccp;
5517 char c;
5518 char * p;
5519 struct reg_entry * reg;
5520
5521 #ifdef REGISTER_PREFIX
5522 if (*start != REGISTER_PREFIX)
5523 return FAIL;
5524 p = start + 1;
5525 #else
5526 p = start;
5527 #ifdef OPTIONAL_REGISTER_PREFIX
5528 if (*p == OPTIONAL_REGISTER_PREFIX)
5529 p++, start++;
5530 #endif
5531 #endif
5532 if (!isalpha (*p) || !is_name_beginner (*p))
5533 return FAIL;
5534
5535 c = *p++;
5536 while (isalpha (c) || isdigit (c) || c == '_')
5537 c = *p++;
5538
5539 *--p = 0;
5540 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5541 *p = c;
5542
5543 if (reg)
5544 {
5545 *ccp = p;
5546 return reg->number;
5547 }
5548
5549 return FAIL;
5550 }
5551
5552 int
5553 md_apply_fix3 (fixP, val, seg)
5554 fixS * fixP;
5555 valueT * val;
5556 segT seg;
5557 {
5558 offsetT value = * val;
5559 offsetT newval;
5560 unsigned int newimm;
5561 unsigned long temp;
5562 int sign;
5563 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5564 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
5565
5566 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5567
5568 /* Note whether this will delete the relocation. */
5569 #if 0
5570 /* Patch from REarnshaw to JDavis (disabled for the moment, since it
5571 doesn't work fully.) */
5572 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
5573 && !fixP->fx_pcrel)
5574 #else
5575 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5576 #endif
5577 fixP->fx_done = 1;
5578
5579 /* If this symbol is in a different section then we need to leave it for
5580 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5581 so we have to undo it's effects here. */
5582 if (fixP->fx_pcrel)
5583 {
5584 if (fixP->fx_addsy != NULL
5585 && S_IS_DEFINED (fixP->fx_addsy)
5586 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5587 {
5588 if (target_oabi
5589 && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
5590 || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
5591 ))
5592 value = 0;
5593 else
5594 value += md_pcrel_from (fixP);
5595 }
5596 }
5597
5598 /* Remember value for emit_reloc. */
5599 fixP->fx_addnumber = value;
5600
5601 switch (fixP->fx_r_type)
5602 {
5603 case BFD_RELOC_ARM_IMMEDIATE:
5604 newimm = validate_immediate (value);
5605 temp = md_chars_to_number (buf, INSN_SIZE);
5606
5607 /* If the instruction will fail, see if we can fix things up by
5608 changing the opcode. */
5609 if (newimm == (unsigned int) FAIL
5610 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
5611 {
5612 as_bad_where (fixP->fx_file, fixP->fx_line,
5613 _("invalid constant (%lx) after fixup"),
5614 (unsigned long) value);
5615 break;
5616 }
5617
5618 newimm |= (temp & 0xfffff000);
5619 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5620 break;
5621
5622 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5623 {
5624 unsigned int highpart = 0;
5625 unsigned int newinsn = 0xe1a00000; /* nop. */
5626 newimm = validate_immediate (value);
5627 temp = md_chars_to_number (buf, INSN_SIZE);
5628
5629 /* If the instruction will fail, see if we can fix things up by
5630 changing the opcode. */
5631 if (newimm == (unsigned int) FAIL
5632 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
5633 {
5634 /* No ? OK - try using two ADD instructions to generate
5635 the value. */
5636 newimm = validate_immediate_twopart (value, & highpart);
5637
5638 /* Yes - then make sure that the second instruction is
5639 also an add. */
5640 if (newimm != (unsigned int) FAIL)
5641 newinsn = temp;
5642 /* Still No ? Try using a negated value. */
5643 else if (validate_immediate_twopart (- value, & highpart) != (unsigned int) FAIL)
5644 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
5645 /* Otherwise - give up. */
5646 else
5647 {
5648 as_bad_where (fixP->fx_file, fixP->fx_line,
5649 _("Unable to compute ADRL instructions for PC offset of 0x%x"),
5650 value);
5651 break;
5652 }
5653
5654 /* Replace the first operand in the 2nd instruction (which
5655 is the PC) with the destination register. We have
5656 already added in the PC in the first instruction and we
5657 do not want to do it again. */
5658 newinsn &= ~0xf0000;
5659 newinsn |= ((newinsn & 0x0f000) << 4);
5660 }
5661
5662 newimm |= (temp & 0xfffff000);
5663 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5664
5665 highpart |= (newinsn & 0xfffff000);
5666 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
5667 }
5668 break;
5669
5670 case BFD_RELOC_ARM_OFFSET_IMM:
5671 sign = value >= 0;
5672
5673 if (value < 0)
5674 value = -value;
5675
5676 if (validate_offset_imm (value, 0) == FAIL)
5677 {
5678 as_bad_where (fixP->fx_file, fixP->fx_line,
5679 _("bad immediate value for offset (%ld)"),
5680 (long) value);
5681 break;
5682 }
5683
5684 newval = md_chars_to_number (buf, INSN_SIZE);
5685 newval &= 0xff7ff000;
5686 newval |= value | (sign ? INDEX_UP : 0);
5687 md_number_to_chars (buf, newval, INSN_SIZE);
5688 break;
5689
5690 case BFD_RELOC_ARM_OFFSET_IMM8:
5691 case BFD_RELOC_ARM_HWLITERAL:
5692 sign = value >= 0;
5693
5694 if (value < 0)
5695 value = -value;
5696
5697 if (validate_offset_imm (value, 1) == FAIL)
5698 {
5699 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5700 as_bad_where (fixP->fx_file, fixP->fx_line,
5701 _("invalid literal constant: pool needs to be closer"));
5702 else
5703 as_bad (_("bad immediate value for half-word offset (%ld)"),
5704 (long) value);
5705 break;
5706 }
5707
5708 newval = md_chars_to_number (buf, INSN_SIZE);
5709 newval &= 0xff7ff0f0;
5710 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
5711 md_number_to_chars (buf, newval, INSN_SIZE);
5712 break;
5713
5714 case BFD_RELOC_ARM_LITERAL:
5715 sign = value >= 0;
5716
5717 if (value < 0)
5718 value = -value;
5719
5720 if (validate_offset_imm (value, 0) == FAIL)
5721 {
5722 as_bad_where (fixP->fx_file, fixP->fx_line,
5723 _("invalid literal constant: pool needs to be closer"));
5724 break;
5725 }
5726
5727 newval = md_chars_to_number (buf, INSN_SIZE);
5728 newval &= 0xff7ff000;
5729 newval |= value | (sign ? INDEX_UP : 0);
5730 md_number_to_chars (buf, newval, INSN_SIZE);
5731 break;
5732
5733 case BFD_RELOC_ARM_SHIFT_IMM:
5734 newval = md_chars_to_number (buf, INSN_SIZE);
5735 if (((unsigned long) value) > 32
5736 || (value == 32
5737 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5738 {
5739 as_bad_where (fixP->fx_file, fixP->fx_line,
5740 _("shift expression is too large"));
5741 break;
5742 }
5743
5744 if (value == 0)
5745 /* Shifts of zero must be done as lsl. */
5746 newval &= ~0x60;
5747 else if (value == 32)
5748 value = 0;
5749 newval &= 0xfffff07f;
5750 newval |= (value & 0x1f) << 7;
5751 md_number_to_chars (buf, newval, INSN_SIZE);
5752 break;
5753
5754 case BFD_RELOC_ARM_SWI:
5755 if (arm_data->thumb_mode)
5756 {
5757 if (((unsigned long) value) > 0xff)
5758 as_bad_where (fixP->fx_file, fixP->fx_line,
5759 _("Invalid swi expression"));
5760 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5761 newval |= value;
5762 md_number_to_chars (buf, newval, THUMB_SIZE);
5763 }
5764 else
5765 {
5766 if (((unsigned long) value) > 0x00ffffff)
5767 as_bad_where (fixP->fx_file, fixP->fx_line,
5768 _("Invalid swi expression"));
5769 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5770 newval |= value;
5771 md_number_to_chars (buf, newval, INSN_SIZE);
5772 }
5773 break;
5774
5775 case BFD_RELOC_ARM_MULTI:
5776 if (((unsigned long) value) > 0xffff)
5777 as_bad_where (fixP->fx_file, fixP->fx_line,
5778 _("Invalid expression in load/store multiple"));
5779 newval = value | md_chars_to_number (buf, INSN_SIZE);
5780 md_number_to_chars (buf, newval, INSN_SIZE);
5781 break;
5782
5783 case BFD_RELOC_ARM_PCREL_BRANCH:
5784 newval = md_chars_to_number (buf, INSN_SIZE);
5785
5786 /* Sign-extend a 24-bit number. */
5787 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
5788
5789 #ifdef OBJ_ELF
5790 if (! target_oabi)
5791 value = fixP->fx_offset;
5792 #endif
5793
5794 /* We are going to store value (shifted right by two) in the
5795 instruction, in a 24 bit, signed field. Thus we need to check
5796 that none of the top 8 bits of the shifted value (top 7 bits of
5797 the unshifted, unsigned value) are set, or that they are all set. */
5798 if ((value & ~ ((offsetT) 0x1ffffff)) != 0
5799 && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
5800 {
5801 #ifdef OBJ_ELF
5802 /* Normally we would be stuck at this point, since we cannot store
5803 the absolute address that is the destination of the branch in the
5804 24 bits of the branch instruction. If however, we happen to know
5805 that the destination of the branch is in the same section as the
5806 branch instruciton itself, then we can compute the relocation for
5807 ourselves and not have to bother the linker with it.
5808
5809 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
5810 because I have not worked out how to do this for OBJ_COFF or
5811 target_oabi. */
5812 if (! target_oabi
5813 && fixP->fx_addsy != NULL
5814 && S_IS_DEFINED (fixP->fx_addsy)
5815 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
5816 {
5817 /* Get pc relative value to go into the branch. */
5818 value = * val;
5819
5820 /* Permit a backward branch provided that enough bits
5821 are set. Allow a forwards branch, provided that
5822 enough bits are clear. */
5823 if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
5824 || (value & ~ ((offsetT) 0x1ffffff)) == 0)
5825 fixP->fx_done = 1;
5826 }
5827
5828 if (! fixP->fx_done)
5829 #endif
5830 as_bad_where (fixP->fx_file, fixP->fx_line,
5831 _("gas can't handle same-section branch dest >= 0x04000000"));
5832 }
5833
5834 value >>= 2;
5835 value += SEXT24 (newval);
5836
5837 if ( (value & ~ ((offsetT) 0xffffff)) != 0
5838 && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
5839 as_bad_where (fixP->fx_file, fixP->fx_line,
5840 _("out of range branch"));
5841
5842 newval = (value & 0x00ffffff) | (newval & 0xff000000);
5843 md_number_to_chars (buf, newval, INSN_SIZE);
5844 break;
5845
5846 case BFD_RELOC_ARM_PCREL_BLX:
5847 {
5848 offsetT hbit;
5849 newval = md_chars_to_number (buf, INSN_SIZE);
5850
5851 #ifdef OBJ_ELF
5852 if (! target_oabi)
5853 value = fixP->fx_offset;
5854 #endif
5855 hbit = (value >> 1) & 1;
5856 value = (value >> 2) & 0x00ffffff;
5857 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
5858 newval = value | (newval & 0xfe000000) | (hbit << 24);
5859 md_number_to_chars (buf, newval, INSN_SIZE);
5860 }
5861 break;
5862
5863 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
5864 newval = md_chars_to_number (buf, THUMB_SIZE);
5865 {
5866 addressT diff = (newval & 0xff) << 1;
5867 if (diff & 0x100)
5868 diff |= ~0xff;
5869
5870 value += diff;
5871 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
5872 as_bad_where (fixP->fx_file, fixP->fx_line,
5873 _("Branch out of range"));
5874 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5875 }
5876 md_number_to_chars (buf, newval, THUMB_SIZE);
5877 break;
5878
5879 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
5880 newval = md_chars_to_number (buf, THUMB_SIZE);
5881 {
5882 addressT diff = (newval & 0x7ff) << 1;
5883 if (diff & 0x800)
5884 diff |= ~0x7ff;
5885
5886 value += diff;
5887 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
5888 as_bad_where (fixP->fx_file, fixP->fx_line,
5889 _("Branch out of range"));
5890 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5891 }
5892 md_number_to_chars (buf, newval, THUMB_SIZE);
5893 break;
5894
5895 case BFD_RELOC_THUMB_PCREL_BLX:
5896 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5897 {
5898 offsetT newval2;
5899 addressT diff;
5900
5901 newval = md_chars_to_number (buf, THUMB_SIZE);
5902 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
5903 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5904 if (diff & 0x400000)
5905 diff |= ~0x3fffff;
5906 #ifdef OBJ_ELF
5907 value = fixP->fx_offset;
5908 #endif
5909 value += diff;
5910 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
5911 as_bad_where (fixP->fx_file, fixP->fx_line,
5912 _("Branch with link out of range"));
5913
5914 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5915 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5916 md_number_to_chars (buf, newval, THUMB_SIZE);
5917 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
5918 }
5919 break;
5920
5921 case BFD_RELOC_8:
5922 if (fixP->fx_done || fixP->fx_pcrel)
5923 md_number_to_chars (buf, value, 1);
5924 #ifdef OBJ_ELF
5925 else if (!target_oabi)
5926 {
5927 value = fixP->fx_offset;
5928 md_number_to_chars (buf, value, 1);
5929 }
5930 #endif
5931 break;
5932
5933 case BFD_RELOC_16:
5934 if (fixP->fx_done || fixP->fx_pcrel)
5935 md_number_to_chars (buf, value, 2);
5936 #ifdef OBJ_ELF
5937 else if (!target_oabi)
5938 {
5939 value = fixP->fx_offset;
5940 md_number_to_chars (buf, value, 2);
5941 }
5942 #endif
5943 break;
5944
5945 #ifdef OBJ_ELF
5946 case BFD_RELOC_ARM_GOT32:
5947 case BFD_RELOC_ARM_GOTOFF:
5948 md_number_to_chars (buf, 0, 4);
5949 break;
5950 #endif
5951
5952 case BFD_RELOC_RVA:
5953 case BFD_RELOC_32:
5954 if (fixP->fx_done || fixP->fx_pcrel)
5955 md_number_to_chars (buf, value, 4);
5956 #ifdef OBJ_ELF
5957 else if (!target_oabi)
5958 {
5959 value = fixP->fx_offset;
5960 md_number_to_chars (buf, value, 4);
5961 }
5962 #endif
5963 break;
5964
5965 #ifdef OBJ_ELF
5966 case BFD_RELOC_ARM_PLT32:
5967 /* It appears the instruction is fully prepared at this point. */
5968 break;
5969 #endif
5970
5971 case BFD_RELOC_ARM_GOTPC:
5972 md_number_to_chars (buf, value, 4);
5973 break;
5974
5975 case BFD_RELOC_ARM_CP_OFF_IMM:
5976 sign = value >= 0;
5977 if (value < -1023 || value > 1023 || (value & 3))
5978 as_bad_where (fixP->fx_file, fixP->fx_line,
5979 _("Illegal value for co-processor offset"));
5980 if (value < 0)
5981 value = -value;
5982 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
5983 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
5984 md_number_to_chars (buf, newval, INSN_SIZE);
5985 break;
5986
5987 case BFD_RELOC_ARM_THUMB_OFFSET:
5988 newval = md_chars_to_number (buf, THUMB_SIZE);
5989 /* Exactly what ranges, and where the offset is inserted depends
5990 on the type of instruction, we can establish this from the
5991 top 4 bits. */
5992 switch (newval >> 12)
5993 {
5994 case 4: /* PC load. */
5995 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5996 forced to zero for these loads, so we will need to round
5997 up the offset if the instruction address is not word
5998 aligned (since the final address produced must be, and
5999 we can only describe word-aligned immediate offsets). */
6000
6001 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
6002 as_bad_where (fixP->fx_file, fixP->fx_line,
6003 _("Invalid offset, target not word aligned (0x%08X)"),
6004 (unsigned int) (fixP->fx_frag->fr_address
6005 + fixP->fx_where + value));
6006
6007 if ((value + 2) & ~0x3fe)
6008 as_bad_where (fixP->fx_file, fixP->fx_line,
6009 _("Invalid offset, value too big (0x%08X)"), value);
6010
6011 /* Round up, since pc will be rounded down. */
6012 newval |= (value + 2) >> 2;
6013 break;
6014
6015 case 9: /* SP load/store. */
6016 if (value & ~0x3fc)
6017 as_bad_where (fixP->fx_file, fixP->fx_line,
6018 _("Invalid offset, value too big (0x%08X)"), value);
6019 newval |= value >> 2;
6020 break;
6021
6022 case 6: /* Word load/store. */
6023 if (value & ~0x7c)
6024 as_bad_where (fixP->fx_file, fixP->fx_line,
6025 _("Invalid offset, value too big (0x%08X)"), value);
6026 newval |= value << 4; /* 6 - 2. */
6027 break;
6028
6029 case 7: /* Byte load/store. */
6030 if (value & ~0x1f)
6031 as_bad_where (fixP->fx_file, fixP->fx_line,
6032 _("Invalid offset, value too big (0x%08X)"), value);
6033 newval |= value << 6;
6034 break;
6035
6036 case 8: /* Halfword load/store. */
6037 if (value & ~0x3e)
6038 as_bad_where (fixP->fx_file, fixP->fx_line,
6039 _("Invalid offset, value too big (0x%08X)"), value);
6040 newval |= value << 5; /* 6 - 1. */
6041 break;
6042
6043 default:
6044 as_bad_where (fixP->fx_file, fixP->fx_line,
6045 "Unable to process relocation for thumb opcode: %lx",
6046 (unsigned long) newval);
6047 break;
6048 }
6049 md_number_to_chars (buf, newval, THUMB_SIZE);
6050 break;
6051
6052 case BFD_RELOC_ARM_THUMB_ADD:
6053 /* This is a complicated relocation, since we use it for all of
6054 the following immediate relocations:
6055
6056 3bit ADD/SUB
6057 8bit ADD/SUB
6058 9bit ADD/SUB SP word-aligned
6059 10bit ADD PC/SP word-aligned
6060
6061 The type of instruction being processed is encoded in the
6062 instruction field:
6063
6064 0x8000 SUB
6065 0x00F0 Rd
6066 0x000F Rs
6067 */
6068 newval = md_chars_to_number (buf, THUMB_SIZE);
6069 {
6070 int rd = (newval >> 4) & 0xf;
6071 int rs = newval & 0xf;
6072 int subtract = newval & 0x8000;
6073
6074 if (rd == REG_SP)
6075 {
6076 if (value & ~0x1fc)
6077 as_bad_where (fixP->fx_file, fixP->fx_line,
6078 _("Invalid immediate for stack address calculation"));
6079 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
6080 newval |= value >> 2;
6081 }
6082 else if (rs == REG_PC || rs == REG_SP)
6083 {
6084 if (subtract ||
6085 value & ~0x3fc)
6086 as_bad_where (fixP->fx_file, fixP->fx_line,
6087 _("Invalid immediate for address calculation (value = 0x%08lX)"),
6088 (unsigned long) value);
6089 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
6090 newval |= rd << 8;
6091 newval |= value >> 2;
6092 }
6093 else if (rs == rd)
6094 {
6095 if (value & ~0xff)
6096 as_bad_where (fixP->fx_file, fixP->fx_line,
6097 _("Invalid 8bit immediate"));
6098 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
6099 newval |= (rd << 8) | value;
6100 }
6101 else
6102 {
6103 if (value & ~0x7)
6104 as_bad_where (fixP->fx_file, fixP->fx_line,
6105 _("Invalid 3bit immediate"));
6106 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
6107 newval |= rd | (rs << 3) | (value << 6);
6108 }
6109 }
6110 md_number_to_chars (buf, newval, THUMB_SIZE);
6111 break;
6112
6113 case BFD_RELOC_ARM_THUMB_IMM:
6114 newval = md_chars_to_number (buf, THUMB_SIZE);
6115 switch (newval >> 11)
6116 {
6117 case 0x04: /* 8bit immediate MOV. */
6118 case 0x05: /* 8bit immediate CMP. */
6119 if (value < 0 || value > 255)
6120 as_bad_where (fixP->fx_file, fixP->fx_line,
6121 _("Invalid immediate: %ld is too large"),
6122 (long) value);
6123 newval |= value;
6124 break;
6125
6126 default:
6127 abort ();
6128 }
6129 md_number_to_chars (buf, newval, THUMB_SIZE);
6130 break;
6131
6132 case BFD_RELOC_ARM_THUMB_SHIFT:
6133 /* 5bit shift value (0..31). */
6134 if (value < 0 || value > 31)
6135 as_bad_where (fixP->fx_file, fixP->fx_line,
6136 _("Illegal Thumb shift value: %ld"), (long) value);
6137 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
6138 newval |= value << 6;
6139 md_number_to_chars (buf, newval, THUMB_SIZE);
6140 break;
6141
6142 case BFD_RELOC_VTABLE_INHERIT:
6143 case BFD_RELOC_VTABLE_ENTRY:
6144 fixP->fx_done = 0;
6145 return 1;
6146
6147 case BFD_RELOC_NONE:
6148 default:
6149 as_bad_where (fixP->fx_file, fixP->fx_line,
6150 _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
6151 }
6152
6153 return 1;
6154 }
6155
6156 /* Translate internal representation of relocation info to BFD target
6157 format. */
6158
6159 arelent *
6160 tc_gen_reloc (section, fixp)
6161 asection * section ATTRIBUTE_UNUSED;
6162 fixS * fixp;
6163 {
6164 arelent * reloc;
6165 bfd_reloc_code_real_type code;
6166
6167 reloc = (arelent *) xmalloc (sizeof (arelent));
6168
6169 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6170 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6171 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6172
6173 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
6174 #ifndef OBJ_ELF
6175 if (fixp->fx_pcrel == 0)
6176 reloc->addend = fixp->fx_offset;
6177 else
6178 reloc->addend = fixp->fx_offset = reloc->address;
6179 #else /* OBJ_ELF */
6180 reloc->addend = fixp->fx_offset;
6181 #endif
6182
6183 switch (fixp->fx_r_type)
6184 {
6185 case BFD_RELOC_8:
6186 if (fixp->fx_pcrel)
6187 {
6188 code = BFD_RELOC_8_PCREL;
6189 break;
6190 }
6191
6192 case BFD_RELOC_16:
6193 if (fixp->fx_pcrel)
6194 {
6195 code = BFD_RELOC_16_PCREL;
6196 break;
6197 }
6198
6199 case BFD_RELOC_32:
6200 if (fixp->fx_pcrel)
6201 {
6202 code = BFD_RELOC_32_PCREL;
6203 break;
6204 }
6205
6206 case BFD_RELOC_ARM_PCREL_BRANCH:
6207 case BFD_RELOC_ARM_PCREL_BLX:
6208 case BFD_RELOC_RVA:
6209 case BFD_RELOC_THUMB_PCREL_BRANCH9:
6210 case BFD_RELOC_THUMB_PCREL_BRANCH12:
6211 case BFD_RELOC_THUMB_PCREL_BRANCH23:
6212 case BFD_RELOC_THUMB_PCREL_BLX:
6213 case BFD_RELOC_VTABLE_ENTRY:
6214 case BFD_RELOC_VTABLE_INHERIT:
6215 code = fixp->fx_r_type;
6216 break;
6217
6218 case BFD_RELOC_ARM_LITERAL:
6219 case BFD_RELOC_ARM_HWLITERAL:
6220 /* If this is called then the a literal has been referenced across
6221 a section boundary - possibly due to an implicit dump. */
6222 as_bad_where (fixp->fx_file, fixp->fx_line,
6223 _("Literal referenced across section boundary (Implicit dump?)"));
6224 return NULL;
6225
6226 #ifdef OBJ_ELF
6227 case BFD_RELOC_ARM_GOT32:
6228 case BFD_RELOC_ARM_GOTOFF:
6229 case BFD_RELOC_ARM_PLT32:
6230 code = fixp->fx_r_type;
6231 break;
6232 #endif
6233
6234 case BFD_RELOC_ARM_IMMEDIATE:
6235 as_bad_where (fixp->fx_file, fixp->fx_line,
6236 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
6237 fixp->fx_r_type);
6238 return NULL;
6239
6240 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
6241 as_bad_where (fixp->fx_file, fixp->fx_line,
6242 _("ADRL used for a symbol not defined in the same file"),
6243 fixp->fx_r_type);
6244 return NULL;
6245
6246 case BFD_RELOC_ARM_OFFSET_IMM:
6247 as_bad_where (fixp->fx_file, fixp->fx_line,
6248 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
6249 fixp->fx_r_type);
6250 return NULL;
6251
6252 default:
6253 {
6254 char * type;
6255
6256 switch (fixp->fx_r_type)
6257 {
6258 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
6259 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
6260 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
6261 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
6262 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
6263 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
6264 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
6265 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
6266 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
6267 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
6268 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
6269 default: type = _("<unknown>"); break;
6270 }
6271 as_bad_where (fixp->fx_file, fixp->fx_line,
6272 _("Can not represent %s relocation in this object file format (%d)"),
6273 type, fixp->fx_pcrel);
6274 return NULL;
6275 }
6276 }
6277
6278 #ifdef OBJ_ELF
6279 if (code == BFD_RELOC_32_PCREL
6280 && GOT_symbol
6281 && fixp->fx_addsy == GOT_symbol)
6282 {
6283 code = BFD_RELOC_ARM_GOTPC;
6284 reloc->addend = fixp->fx_offset = reloc->address;
6285 }
6286 #endif
6287
6288 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6289
6290 if (reloc->howto == NULL)
6291 {
6292 as_bad_where (fixp->fx_file, fixp->fx_line,
6293 _("Can not represent %s relocation in this object file format"),
6294 bfd_get_reloc_code_name (code));
6295 return NULL;
6296 }
6297
6298 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
6299 vtable entry to be used in the relocation's section offset. */
6300 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6301 reloc->address = fixp->fx_offset;
6302
6303 return reloc;
6304 }
6305
6306 int
6307 md_estimate_size_before_relax (fragP, segtype)
6308 fragS * fragP ATTRIBUTE_UNUSED;
6309 segT segtype ATTRIBUTE_UNUSED;
6310 {
6311 as_fatal (_("md_estimate_size_before_relax\n"));
6312 return 1;
6313 }
6314
6315 static void
6316 output_inst PARAMS ((void))
6317 {
6318 char * to = NULL;
6319
6320 if (inst.error)
6321 {
6322 as_bad (inst.error);
6323 return;
6324 }
6325
6326 to = frag_more (inst.size);
6327
6328 if (thumb_mode && (inst.size > THUMB_SIZE))
6329 {
6330 assert (inst.size == (2 * THUMB_SIZE));
6331 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
6332 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
6333 }
6334 else if (inst.size > INSN_SIZE)
6335 {
6336 assert (inst.size == (2 * INSN_SIZE));
6337 md_number_to_chars (to, inst.instruction, INSN_SIZE);
6338 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
6339 }
6340 else
6341 md_number_to_chars (to, inst.instruction, inst.size);
6342
6343 if (inst.reloc.type != BFD_RELOC_NONE)
6344 fix_new_arm (frag_now, to - frag_now->fr_literal,
6345 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
6346 inst.reloc.type);
6347
6348 return;
6349 }
6350
6351 void
6352 md_assemble (str)
6353 char * str;
6354 {
6355 char c;
6356 char * p;
6357 char * q;
6358 char * start;
6359
6360 /* Align the instruction.
6361 This may not be the right thing to do but ... */
6362 #if 0
6363 arm_align (2, 0);
6364 #endif
6365 listing_prev_line (); /* Defined in listing.h. */
6366
6367 /* Align the previous label if needed. */
6368 if (last_label_seen != NULL)
6369 {
6370 symbol_set_frag (last_label_seen, frag_now);
6371 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6372 S_SET_SEGMENT (last_label_seen, now_seg);
6373 }
6374
6375 memset (&inst, '\0', sizeof (inst));
6376 inst.reloc.type = BFD_RELOC_NONE;
6377
6378 skip_whitespace (str);
6379
6380 /* Scan up to the end of the op-code, which must end in white space or
6381 end of string. */
6382 for (start = p = str; *p != '\0'; p++)
6383 if (*p == ' ')
6384 break;
6385
6386 if (p == str)
6387 {
6388 as_bad (_("No operator -- statement `%s'\n"), str);
6389 return;
6390 }
6391
6392 if (thumb_mode)
6393 {
6394 CONST struct thumb_opcode * opcode;
6395
6396 c = *p;
6397 *p = '\0';
6398 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
6399 *p = c;
6400
6401 if (opcode)
6402 {
6403 /* Check that this instruction is supported for this CPU. */
6404 if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
6405 {
6406 as_bad (_("selected processor does not support this opcode"));
6407 return;
6408 }
6409
6410 inst.instruction = opcode->value;
6411 inst.size = opcode->size;
6412 (*opcode->parms) (p);
6413 output_inst ();
6414 return;
6415 }
6416 }
6417 else
6418 {
6419 CONST struct asm_opcode * opcode;
6420 unsigned long cond_code;
6421
6422 inst.size = INSN_SIZE;
6423 /* P now points to the end of the opcode, probably white space, but we
6424 have to break the opcode up in case it contains condionals and flags;
6425 keep trying with progressively smaller basic instructions until one
6426 matches, or we run out of opcode. */
6427 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
6428
6429 for (; q != str; q--)
6430 {
6431 c = *q;
6432 *q = '\0';
6433
6434 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
6435 *q = c;
6436
6437 if (opcode && opcode->template)
6438 {
6439 unsigned long flag_bits = 0;
6440 char * r;
6441
6442 /* Check that this instruction is supported for this CPU. */
6443 if ((opcode->variants & cpu_variant) == 0)
6444 goto try_shorter;
6445
6446 inst.instruction = opcode->value;
6447 if (q == p) /* Just a simple opcode. */
6448 {
6449 if (opcode->comp_suffix)
6450 {
6451 if (*opcode->comp_suffix != '\0')
6452 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
6453 str, opcode->comp_suffix);
6454 else
6455 /* Not a conditional instruction. */
6456 (*opcode->parms) (q, 0);
6457 }
6458 else
6459 {
6460 /* A conditional instruction with default condition. */
6461 inst.instruction |= COND_ALWAYS;
6462 (*opcode->parms) (q, 0);
6463 }
6464 output_inst ();
6465 return;
6466 }
6467
6468 /* Not just a simple opcode. Check if extra is a
6469 conditional. */
6470 r = q;
6471 if (p - r >= 2)
6472 {
6473 CONST struct asm_cond *cond;
6474 char d = *(r + 2);
6475
6476 *(r + 2) = '\0';
6477 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
6478 *(r + 2) = d;
6479 if (cond)
6480 {
6481 if (cond->value == 0xf0000000)
6482 as_tsktsk (
6483 _("Warning: Use of the 'nv' conditional is deprecated\n"));
6484
6485 cond_code = cond->value;
6486 r += 2;
6487 }
6488 else
6489 cond_code = COND_ALWAYS;
6490 }
6491 else
6492 cond_code = COND_ALWAYS;
6493
6494 /* Apply the conditional, or complain it's not allowed. */
6495 if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
6496 {
6497 /* Instruction isn't conditional. */
6498 if (cond_code != COND_ALWAYS)
6499 {
6500 as_bad (_("Opcode `%s' is unconditional\n"), str);
6501 return;
6502 }
6503 }
6504 else
6505 /* Instruction is conditional: set the condition into it. */
6506 inst.instruction |= cond_code;
6507
6508 /* If there is a compulsory suffix, it should come here
6509 before any optional flags. */
6510 if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
6511 {
6512 CONST char *s = opcode->comp_suffix;
6513
6514 while (*s)
6515 {
6516 inst.suffix++;
6517 if (*r == *s)
6518 break;
6519 s++;
6520 }
6521
6522 if (*s == '\0')
6523 {
6524 as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
6525 str, opcode->comp_suffix);
6526 return;
6527 }
6528
6529 r++;
6530 }
6531
6532 /* The remainder, if any should now be flags for the instruction;
6533 Scan these checking each one found with the opcode. */
6534 if (r != p)
6535 {
6536 char d;
6537 CONST struct asm_flg *flag = opcode->flags;
6538
6539 if (flag)
6540 {
6541 int flagno;
6542
6543 d = *p;
6544 *p = '\0';
6545
6546 for (flagno = 0; flag[flagno].template; flagno++)
6547 {
6548 if (streq (r, flag[flagno].template))
6549 {
6550 flag_bits |= flag[flagno].set_bits;
6551 break;
6552 }
6553 }
6554
6555 *p = d;
6556 if (! flag[flagno].template)
6557 goto try_shorter;
6558 }
6559 else
6560 goto try_shorter;
6561 }
6562
6563 (*opcode->parms) (p, flag_bits);
6564 output_inst ();
6565 return;
6566 }
6567
6568 try_shorter:
6569 ;
6570 }
6571 }
6572
6573 /* It wasn't an instruction, but it might be a register alias of the form
6574 alias .req reg. */
6575 q = p;
6576 skip_whitespace (q);
6577
6578 c = *p;
6579 *p = '\0';
6580
6581 if (*q && !strncmp (q, ".req ", 4))
6582 {
6583 int reg;
6584 char * copy_of_str = str;
6585 char * r;
6586
6587 q += 4;
6588 skip_whitespace (q);
6589
6590 for (r = q; *r != '\0'; r++)
6591 if (*r == ' ')
6592 break;
6593
6594 if (r != q)
6595 {
6596 int regnum;
6597 char d = *r;
6598
6599 *r = '\0';
6600 regnum = arm_reg_parse (& q);
6601 *r = d;
6602
6603 reg = arm_reg_parse (& str);
6604
6605 if (reg == FAIL)
6606 {
6607 if (regnum != FAIL)
6608 insert_reg_alias (str, regnum);
6609 else
6610 as_warn (_("register '%s' does not exist\n"), q);
6611 }
6612 else if (regnum != FAIL)
6613 {
6614 if (reg != regnum)
6615 as_warn (_("ignoring redefinition of register alias '%s'"),
6616 copy_of_str);
6617
6618 /* Do not warn about redefinitions to the same alias. */
6619 }
6620 else
6621 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6622 copy_of_str, q);
6623 }
6624 else
6625 as_warn (_("ignoring incomplete .req pseuso op"));
6626
6627 *p = c;
6628 return;
6629 }
6630
6631 *p = c;
6632 as_bad (_("bad instruction `%s'"), start);
6633 }
6634
6635 /* md_parse_option
6636 Invocation line includes a switch not recognized by the base assembler.
6637 See if it's a processor-specific option. These are:
6638 Cpu variants, the arm part is optional:
6639 -m[arm]1 Currently not supported.
6640 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6641 -m[arm]3 Arm 3 processor
6642 -m[arm]6[xx], Arm 6 processors
6643 -m[arm]7[xx][t][[d]m] Arm 7 processors
6644 -m[arm]8[10] Arm 8 processors
6645 -m[arm]9[20][tdmi] Arm 9 processors
6646 -mstrongarm[110[0]] StrongARM processors
6647 -m[arm]v[2345[t]] Arm architectures
6648 -mall All (except the ARM1)
6649 FP variants:
6650 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6651 -mfpe-old (No float load/store multiples)
6652 -mno-fpu Disable all floating point instructions
6653 Run-time endian selection:
6654 -EB big endian cpu
6655 -EL little endian cpu
6656 ARM Procedure Calling Standard:
6657 -mapcs-32 32 bit APCS
6658 -mapcs-26 26 bit APCS
6659 -mapcs-float Pass floats in float regs
6660 -mapcs-reentrant Position independent code
6661 -mthumb-interwork Code supports Arm/Thumb interworking
6662 -moabi Old ELF ABI */
6663
6664 CONST char * md_shortopts = "m:k";
6665
6666 struct option md_longopts[] =
6667 {
6668 #ifdef ARM_BI_ENDIAN
6669 #define OPTION_EB (OPTION_MD_BASE + 0)
6670 {"EB", no_argument, NULL, OPTION_EB},
6671 #define OPTION_EL (OPTION_MD_BASE + 1)
6672 {"EL", no_argument, NULL, OPTION_EL},
6673 #ifdef OBJ_ELF
6674 #define OPTION_OABI (OPTION_MD_BASE +2)
6675 {"oabi", no_argument, NULL, OPTION_OABI},
6676 #endif
6677 #endif
6678 {NULL, no_argument, NULL, 0}
6679 };
6680
6681 size_t md_longopts_size = sizeof (md_longopts);
6682
6683 int
6684 md_parse_option (c, arg)
6685 int c;
6686 char * arg;
6687 {
6688 char * str = arg;
6689
6690 switch (c)
6691 {
6692 #ifdef ARM_BI_ENDIAN
6693 case OPTION_EB:
6694 target_big_endian = 1;
6695 break;
6696 case OPTION_EL:
6697 target_big_endian = 0;
6698 break;
6699 #endif
6700
6701 case 'm':
6702 switch (*str)
6703 {
6704 case 'f':
6705 if (streq (str, "fpa10"))
6706 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
6707 else if (streq (str, "fpa11"))
6708 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
6709 else if (streq (str, "fpe-old"))
6710 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
6711 else
6712 goto bad;
6713 break;
6714
6715 case 'n':
6716 if (streq (str, "no-fpu"))
6717 cpu_variant &= ~FPU_ALL;
6718 break;
6719
6720 #ifdef OBJ_ELF
6721 case 'o':
6722 if (streq (str, "oabi"))
6723 target_oabi = true;
6724 break;
6725 #endif
6726
6727 case 't':
6728 /* Limit assembler to generating only Thumb instructions: */
6729 if (streq (str, "thumb"))
6730 {
6731 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
6732 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
6733 thumb_mode = 1;
6734 }
6735 else if (streq (str, "thumb-interwork"))
6736 {
6737 if ((cpu_variant & ARM_THUMB) == 0)
6738 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
6739 #if defined OBJ_COFF || defined OBJ_ELF
6740 support_interwork = true;
6741 #endif
6742 }
6743 else
6744 goto bad;
6745 break;
6746
6747 default:
6748 if (streq (str, "all"))
6749 {
6750 cpu_variant = ARM_ALL | FPU_ALL;
6751 return 1;
6752 }
6753 #if defined OBJ_COFF || defined OBJ_ELF
6754 if (! strncmp (str, "apcs-", 5))
6755 {
6756 /* GCC passes on all command line options starting "-mapcs-..."
6757 to us, so we must parse them here. */
6758
6759 str += 5;
6760
6761 if (streq (str, "32"))
6762 {
6763 uses_apcs_26 = false;
6764 return 1;
6765 }
6766 else if (streq (str, "26"))
6767 {
6768 uses_apcs_26 = true;
6769 return 1;
6770 }
6771 else if (streq (str, "frame"))
6772 {
6773 /* Stack frames are being generated - does not affect
6774 linkage of code. */
6775 return 1;
6776 }
6777 else if (streq (str, "stack-check"))
6778 {
6779 /* Stack checking is being performed - does not affect
6780 linkage, but does require that the functions
6781 __rt_stkovf_split_small and __rt_stkovf_split_big be
6782 present in the final link. */
6783
6784 return 1;
6785 }
6786 else if (streq (str, "float"))
6787 {
6788 /* Floating point arguments are being passed in the floating
6789 point registers. This does affect linking, since this
6790 version of the APCS is incompatible with the version that
6791 passes floating points in the integer registers. */
6792
6793 uses_apcs_float = true;
6794 return 1;
6795 }
6796 else if (streq (str, "reentrant"))
6797 {
6798 /* Reentrant code has been generated. This does affect
6799 linking, since there is no point in linking reentrant/
6800 position independent code with absolute position code. */
6801 pic_code = true;
6802 return 1;
6803 }
6804
6805 as_bad (_("Unrecognised APCS switch -m%s"), arg);
6806 return 0;
6807 }
6808 #endif
6809 /* Strip off optional "arm". */
6810 if (! strncmp (str, "arm", 3))
6811 str += 3;
6812
6813 switch (*str)
6814 {
6815 case '1':
6816 if (streq (str, "1"))
6817 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6818 else
6819 goto bad;
6820 break;
6821
6822 case '2':
6823 if (streq (str, "2"))
6824 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6825 else if (streq (str, "250"))
6826 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6827 else
6828 goto bad;
6829 break;
6830
6831 case '3':
6832 if (streq (str, "3"))
6833 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6834 else
6835 goto bad;
6836 break;
6837
6838 case '6':
6839 switch (strtol (str, NULL, 10))
6840 {
6841 case 6:
6842 case 60:
6843 case 600:
6844 case 610:
6845 case 620:
6846 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6847 break;
6848 default:
6849 goto bad;
6850 }
6851 break;
6852
6853 case '7':
6854 /* Eat the processor name. */
6855 switch (strtol (str, & str, 10))
6856 {
6857 case 7:
6858 case 70:
6859 case 700:
6860 case 710:
6861 case 720:
6862 case 7100:
6863 case 7500:
6864 break;
6865 default:
6866 goto bad;
6867 }
6868 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6869 for (; *str; str++)
6870 {
6871 switch (*str)
6872 {
6873 case 't':
6874 cpu_variant |= (ARM_THUMB | ARM_ARCH_V4);
6875 break;
6876
6877 case 'm':
6878 cpu_variant |= ARM_LONGMUL;
6879 break;
6880
6881 case 'f': /* fe => fp enabled cpu. */
6882 if (str[1] == 'e')
6883 ++ str;
6884 else
6885 goto bad;
6886
6887 case 'c': /* Left over from 710c processor name. */
6888 case 'd': /* Debug. */
6889 case 'i': /* Embedded ICE. */
6890 /* Included for completeness in ARM processor naming. */
6891 break;
6892
6893 default:
6894 goto bad;
6895 }
6896 }
6897 break;
6898
6899 case '8':
6900 if (streq (str, "8") || streq (str, "810"))
6901 cpu_variant = (cpu_variant & ~ARM_ANY)
6902 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6903 else
6904 goto bad;
6905 break;
6906
6907 case '9':
6908 if (streq (str, "9"))
6909 cpu_variant = (cpu_variant & ~ARM_ANY)
6910 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6911 else if (streq (str, "920"))
6912 cpu_variant = (cpu_variant & ~ARM_ANY)
6913 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL;
6914 else if (streq (str, "920t"))
6915 cpu_variant = (cpu_variant & ~ARM_ANY)
6916 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6917 else if (streq (str, "9tdmi"))
6918 cpu_variant = (cpu_variant & ~ARM_ANY)
6919 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6920 else
6921 goto bad;
6922 break;
6923
6924 case 's':
6925 if (streq (str, "strongarm")
6926 || streq (str, "strongarm110")
6927 || streq (str, "strongarm1100"))
6928 cpu_variant = (cpu_variant & ~ARM_ANY)
6929 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6930 else
6931 goto bad;
6932 break;
6933
6934 case 'v':
6935 /* Select variant based on architecture rather than
6936 processor. */
6937 switch (*++str)
6938 {
6939 case '2':
6940 switch (*++str)
6941 {
6942 case 'a':
6943 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6944 break;
6945 case 0:
6946 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6947 break;
6948 default:
6949 as_bad (_("Invalid architecture variant -m%s"), arg);
6950 break;
6951 }
6952 break;
6953
6954 case '3':
6955 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6956
6957 switch (*++str)
6958 {
6959 case 'm': cpu_variant |= ARM_LONGMUL; break;
6960 case 0: break;
6961 default:
6962 as_bad (_("Invalid architecture variant -m%s"), arg);
6963 break;
6964 }
6965 break;
6966
6967 case '4':
6968 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4;
6969
6970 switch (*++str)
6971 {
6972 case 't': cpu_variant |= ARM_THUMB; break;
6973 case 0: break;
6974 default:
6975 as_bad (_("Invalid architecture variant -m%s"), arg);
6976 break;
6977 }
6978 break;
6979
6980 case '5':
6981 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
6982 switch (*++str)
6983 {
6984 case 't': cpu_variant |= ARM_THUMB; break;
6985 case 0: break;
6986 default:
6987 as_bad (_("Invalid architecture variant -m%s"), arg);
6988 break;
6989 }
6990 break;
6991
6992 default:
6993 as_bad (_("Invalid architecture variant -m%s"), arg);
6994 break;
6995 }
6996 break;
6997
6998 default:
6999 bad:
7000 as_bad (_("Invalid processor variant -m%s"), arg);
7001 return 0;
7002 }
7003 }
7004 break;
7005
7006 #if defined OBJ_ELF || defined OBJ_COFF
7007 case 'k':
7008 pic_code = 1;
7009 break;
7010 #endif
7011
7012 default:
7013 return 0;
7014 }
7015
7016 return 1;
7017 }
7018
7019 void
7020 md_show_usage (fp)
7021 FILE * fp;
7022 {
7023 fprintf (fp, _("\
7024 ARM Specific Assembler Options:\n\
7025 -m[arm][<processor name>] select processor variant\n\
7026 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
7027 -mthumb only allow Thumb instructions\n\
7028 -mthumb-interwork mark the assembled code as supporting interworking\n\
7029 -mall allow any instruction\n\
7030 -mfpa10, -mfpa11 select floating point architecture\n\
7031 -mfpe-old don't allow floating-point multiple instructions\n\
7032 -mno-fpu don't allow any floating-point instructions.\n\
7033 -k generate PIC code.\n"));
7034 #if defined OBJ_COFF || defined OBJ_ELF
7035 fprintf (fp, _("\
7036 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
7037 -mapcs-float floating point args are passed in FP regs\n\
7038 -mapcs-reentrant the code is position independent/reentrant\n"));
7039 #endif
7040 #ifdef OBJ_ELF
7041 fprintf (fp, _("\
7042 -moabi support the old ELF ABI\n"));
7043 #endif
7044 #ifdef ARM_BI_ENDIAN
7045 fprintf (fp, _("\
7046 -EB assemble code for a big endian cpu\n\
7047 -EL assemble code for a little endian cpu\n"));
7048 #endif
7049 }
7050
7051 /* We need to be able to fix up arbitrary expressions in some statements.
7052 This is so that we can handle symbols that are an arbitrary distance from
7053 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7054 which returns part of an address in a form which will be valid for
7055 a data instruction. We do this by pushing the expression into a symbol
7056 in the expr_section, and creating a fix for that. */
7057
7058 static void
7059 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
7060 fragS * frag;
7061 int where;
7062 short int size;
7063 expressionS * exp;
7064 int pc_rel;
7065 int reloc;
7066 {
7067 fixS * new_fix;
7068 arm_fix_data * arm_data;
7069
7070 switch (exp->X_op)
7071 {
7072 case O_constant:
7073 case O_symbol:
7074 case O_add:
7075 case O_subtract:
7076 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
7077 break;
7078
7079 default:
7080 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
7081 pc_rel, reloc);
7082 break;
7083 }
7084
7085 /* Mark whether the fix is to a THUMB instruction, or an ARM
7086 instruction. */
7087 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
7088 new_fix->tc_fix_data = (PTR) arm_data;
7089 arm_data->thumb_mode = thumb_mode;
7090
7091 return;
7092 }
7093
7094 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7095
7096 void
7097 cons_fix_new_arm (frag, where, size, exp)
7098 fragS * frag;
7099 int where;
7100 int size;
7101 expressionS * exp;
7102 {
7103 bfd_reloc_code_real_type type;
7104 int pcrel = 0;
7105
7106 /* Pick a reloc.
7107 FIXME: @@ Should look at CPU word size. */
7108 switch (size)
7109 {
7110 case 1:
7111 type = BFD_RELOC_8;
7112 break;
7113 case 2:
7114 type = BFD_RELOC_16;
7115 break;
7116 case 4:
7117 default:
7118 type = BFD_RELOC_32;
7119 break;
7120 case 8:
7121 type = BFD_RELOC_64;
7122 break;
7123 }
7124
7125 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
7126 }
7127
7128 /* A good place to do this, although this was probably not intended
7129 for this kind of use. We need to dump the literal pool before
7130 references are made to a null symbol pointer. */
7131
7132 void
7133 arm_cleanup ()
7134 {
7135 if (current_poolP == NULL)
7136 return;
7137
7138 /* Put it at the end of text section. */
7139 subseg_set (text_section, 0);
7140 s_ltorg (0);
7141 listing_prev_line ();
7142 }
7143
7144 void
7145 arm_start_line_hook ()
7146 {
7147 last_label_seen = NULL;
7148 }
7149
7150 void
7151 arm_frob_label (sym)
7152 symbolS * sym;
7153 {
7154 last_label_seen = sym;
7155
7156 ARM_SET_THUMB (sym, thumb_mode);
7157
7158 #if defined OBJ_COFF || defined OBJ_ELF
7159 ARM_SET_INTERWORK (sym, support_interwork);
7160 #endif
7161
7162 if (label_is_thumb_function_name)
7163 {
7164 /* When the address of a Thumb function is taken the bottom
7165 bit of that address should be set. This will allow
7166 interworking between Arm and Thumb functions to work
7167 correctly. */
7168
7169 THUMB_SET_FUNC (sym, 1);
7170
7171 label_is_thumb_function_name = false;
7172 }
7173 }
7174
7175 /* Adjust the symbol table. This marks Thumb symbols as distinct from
7176 ARM ones. */
7177
7178 void
7179 arm_adjust_symtab ()
7180 {
7181 #ifdef OBJ_COFF
7182 symbolS * sym;
7183
7184 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
7185 {
7186 if (ARM_IS_THUMB (sym))
7187 {
7188 if (THUMB_IS_FUNC (sym))
7189 {
7190 /* Mark the symbol as a Thumb function. */
7191 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
7192 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
7193 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
7194
7195 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
7196 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
7197 else
7198 as_bad (_("%s: unexpected function type: %d"),
7199 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
7200 }
7201 else switch (S_GET_STORAGE_CLASS (sym))
7202 {
7203 case C_EXT:
7204 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
7205 break;
7206 case C_STAT:
7207 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
7208 break;
7209 case C_LABEL:
7210 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
7211 break;
7212 default:
7213 /* Do nothing. */
7214 break;
7215 }
7216 }
7217
7218 if (ARM_IS_INTERWORK (sym))
7219 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
7220 }
7221 #endif
7222 #ifdef OBJ_ELF
7223 symbolS *sym;
7224 char bind;
7225
7226 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
7227 {
7228 if (ARM_IS_THUMB (sym))
7229 {
7230 elf_symbol_type *elf_sym;
7231
7232 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
7233 bind = ELF_ST_BIND (elf_sym);
7234
7235 /* If it's a .thumb_func, declare it as so,
7236 otherwise tag label as .code 16. */
7237 if (THUMB_IS_FUNC (sym))
7238 elf_sym->internal_elf_sym.st_info =
7239 ELF_ST_INFO (bind, STT_ARM_TFUNC);
7240 else
7241 elf_sym->internal_elf_sym.st_info =
7242 ELF_ST_INFO (bind, STT_ARM_16BIT);
7243 }
7244 }
7245 #endif
7246 }
7247
7248 int
7249 arm_data_in_code ()
7250 {
7251 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
7252 {
7253 *input_line_pointer = '/';
7254 input_line_pointer += 5;
7255 *input_line_pointer = 0;
7256 return 1;
7257 }
7258
7259 return 0;
7260 }
7261
7262 char *
7263 arm_canonicalize_symbol_name (name)
7264 char *name;
7265 {
7266 int len;
7267
7268 if (thumb_mode && (len = strlen (name)) > 5
7269 && streq (name + len - 5, "/data"))
7270 *(name + len - 5) = 0;
7271
7272 return name;
7273 }
7274
7275 boolean
7276 arm_validate_fix (fixP)
7277 fixS *fixP;
7278 {
7279 /* If the destination of the branch is a defined symbol which does not have
7280 the THUMB_FUNC attribute, then we must be calling a function which has
7281 the (interfacearm) attribute. We look for the Thumb entry point to that
7282 function and change the branch to refer to that function instead. */
7283 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
7284 && fixP->fx_addsy != NULL
7285 && S_IS_DEFINED (fixP->fx_addsy)
7286 && ! THUMB_IS_FUNC (fixP->fx_addsy))
7287 {
7288 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
7289 return true;
7290 }
7291
7292 return false;
7293 }
7294
7295 #ifdef OBJ_ELF
7296 /* Relocations against Thumb function names must be left unadjusted,
7297 so that the linker can use this information to correctly set the
7298 bottom bit of their addresses. The MIPS version of this function
7299 also prevents relocations that are mips-16 specific, but I do not
7300 know why it does this.
7301
7302 FIXME:
7303 There is one other problem that ought to be addressed here, but
7304 which currently is not: Taking the address of a label (rather
7305 than a function) and then later jumping to that address. Such
7306 addresses also ought to have their bottom bit set (assuming that
7307 they reside in Thumb code), but at the moment they will not. */
7308
7309 boolean
7310 arm_fix_adjustable (fixP)
7311 fixS *fixP;
7312 {
7313 if (fixP->fx_addsy == NULL)
7314 return 1;
7315
7316 /* Prevent all adjustments to global symbols. */
7317 if (S_IS_EXTERN (fixP->fx_addsy))
7318 return 0;
7319
7320 if (S_IS_WEAK (fixP->fx_addsy))
7321 return 0;
7322
7323 if (THUMB_IS_FUNC (fixP->fx_addsy)
7324 && fixP->fx_subsy == NULL)
7325 return 0;
7326
7327 /* We need the symbol name for the VTABLE entries. */
7328 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7329 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7330 return 0;
7331
7332 return 1;
7333 }
7334
7335 const char *
7336 elf32_arm_target_format ()
7337 {
7338 if (target_big_endian)
7339 {
7340 if (target_oabi)
7341 return "elf32-bigarm-oabi";
7342 else
7343 return "elf32-bigarm";
7344 }
7345 else
7346 {
7347 if (target_oabi)
7348 return "elf32-littlearm-oabi";
7349 else
7350 return "elf32-littlearm";
7351 }
7352 }
7353
7354 void
7355 armelf_frob_symbol (symp, puntp)
7356 symbolS * symp;
7357 int * puntp;
7358 {
7359 elf_frob_symbol (symp, puntp);
7360 }
7361
7362 int
7363 arm_force_relocation (fixp)
7364 struct fix * fixp;
7365 {
7366 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7367 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
7368 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
7369 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
7370 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
7371 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
7372 return 1;
7373
7374 return 0;
7375 }
7376
7377 static bfd_reloc_code_real_type
7378 arm_parse_reloc ()
7379 {
7380 char id [16];
7381 char * ip;
7382 unsigned int i;
7383 static struct
7384 {
7385 char * str;
7386 int len;
7387 bfd_reloc_code_real_type reloc;
7388 }
7389 reloc_map[] =
7390 {
7391 #define MAP(str,reloc) { str, sizeof (str)-1, reloc }
7392 MAP ("(got)", BFD_RELOC_ARM_GOT32),
7393 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
7394 /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)"
7395 branch instructions generated by GCC for PLT relocs. */
7396 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
7397 { NULL, 0, BFD_RELOC_UNUSED }
7398 #undef MAP
7399 };
7400
7401 for (i = 0, ip = input_line_pointer;
7402 i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
7403 i++, ip++)
7404 id[i] = tolower (*ip);
7405
7406 for (i = 0; reloc_map[i].str; i++)
7407 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
7408 break;
7409
7410 input_line_pointer += reloc_map[i].len;
7411
7412 return reloc_map[i].reloc;
7413 }
7414
7415 static void
7416 s_arm_elf_cons (nbytes)
7417 int nbytes;
7418 {
7419 expressionS exp;
7420
7421 #ifdef md_flush_pending_output
7422 md_flush_pending_output ();
7423 #endif
7424
7425 if (is_it_end_of_statement ())
7426 {
7427 demand_empty_rest_of_line ();
7428 return;
7429 }
7430
7431 #ifdef md_cons_align
7432 md_cons_align (nbytes);
7433 #endif
7434
7435 do
7436 {
7437 bfd_reloc_code_real_type reloc;
7438
7439 expression (& exp);
7440
7441 if (exp.X_op == O_symbol
7442 && *input_line_pointer == '('
7443 && (reloc = arm_parse_reloc ()) != BFD_RELOC_UNUSED)
7444 {
7445 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
7446 int size = bfd_get_reloc_size (howto);
7447
7448 if (size > nbytes)
7449 as_bad ("%s relocations do not fit in %d bytes",
7450 howto->name, nbytes);
7451 else
7452 {
7453 register char *p = frag_more ((int) nbytes);
7454 int offset = nbytes - size;
7455
7456 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7457 &exp, 0, reloc);
7458 }
7459 }
7460 else
7461 emit_expr (&exp, (unsigned int) nbytes);
7462 }
7463 while (*input_line_pointer++ == ',');
7464
7465 /* Put terminator back into stream. */
7466 input_line_pointer --;
7467 demand_empty_rest_of_line ();
7468 }
7469
7470 #endif /* OBJ_ELF */
GDB Binutils - Deliverables
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