1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
146 static int fix_v4bx
= FALSE
;
148 /* Variables that we set while parsing command-line options. Once all
149 options have been read we re-process these values to set the real
151 static const arm_feature_set
*legacy_cpu
= NULL
;
152 static const arm_feature_set
*legacy_fpu
= NULL
;
154 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
155 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
156 static const arm_feature_set
*march_cpu_opt
= NULL
;
157 static const arm_feature_set
*march_fpu_opt
= NULL
;
158 static const arm_feature_set
*mfpu_opt
= NULL
;
159 static const arm_feature_set
*object_arch
= NULL
;
161 /* Constants for known architecture features. */
162 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
163 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
164 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
165 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
166 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
167 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
168 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
169 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
170 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
173 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
176 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
177 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
178 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
179 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
180 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
181 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
182 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
183 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
184 static const arm_feature_set arm_ext_v4t_5
=
185 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
186 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
187 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
188 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
189 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
190 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
191 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
192 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
193 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
194 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
195 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
196 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
201 static const arm_feature_set arm_ext_m
=
202 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
204 static const arm_feature_set arm_arch_any
= ARM_ANY
;
205 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
206 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
207 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
209 static const arm_feature_set arm_cext_iwmmxt2
=
210 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
211 static const arm_feature_set arm_cext_iwmmxt
=
212 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
213 static const arm_feature_set arm_cext_xscale
=
214 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
215 static const arm_feature_set arm_cext_maverick
=
216 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
217 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
218 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
219 static const arm_feature_set fpu_vfp_ext_v1xd
=
220 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
221 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
222 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
223 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
224 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
225 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
226 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
228 static int mfloat_abi_opt
= -1;
229 /* Record user cpu selection for object attributes. */
230 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
231 /* Must be long enough to hold any of the names in arm_cpus. */
232 static char selected_cpu_name
[16];
235 static int meabi_flags
= EABI_DEFAULT
;
237 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
243 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
248 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
249 symbolS
* GOT_symbol
;
252 /* 0: assemble for ARM,
253 1: assemble for Thumb,
254 2: assemble for Thumb even though target CPU does not support thumb
256 static int thumb_mode
= 0;
258 /* If unified_syntax is true, we are processing the new unified
259 ARM/Thumb syntax. Important differences from the old ARM mode:
261 - Immediate operands do not require a # prefix.
262 - Conditional affixes always appear at the end of the
263 instruction. (For backward compatibility, those instructions
264 that formerly had them in the middle, continue to accept them
266 - The IT instruction may appear, and if it does is validated
267 against subsequent conditional affixes. It does not generate
270 Important differences from the old Thumb mode:
272 - Immediate operands do not require a # prefix.
273 - Most of the V6T2 instructions are only available in unified mode.
274 - The .N and .W suffixes are recognized and honored (it is an error
275 if they cannot be honored).
276 - All instructions set the flags if and only if they have an 's' affix.
277 - Conditional affixes may be used. They are validated against
278 preceding IT instructions. Unlike ARM mode, you cannot use a
279 conditional affix except in the scope of an IT instruction. */
281 static bfd_boolean unified_syntax
= FALSE
;
296 enum neon_el_type type
;
300 #define NEON_MAX_TYPE_ELS 4
304 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
311 unsigned long instruction
;
315 /* "uncond_value" is set to the value in place of the conditional field in
316 unconditional versions of the instruction, or -1 if nothing is
319 struct neon_type vectype
;
320 /* Set to the opcode if the instruction needs relaxation.
321 Zero if the instruction is not relaxed. */
325 bfd_reloc_code_real_type type
;
334 struct neon_type_el vectype
;
335 unsigned present
: 1; /* Operand present. */
336 unsigned isreg
: 1; /* Operand was a register. */
337 unsigned immisreg
: 1; /* .imm field is a second register. */
338 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
339 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
340 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
341 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
342 instructions. This allows us to disambiguate ARM <-> vector insns. */
343 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
344 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
345 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
346 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
347 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
348 unsigned writeback
: 1; /* Operand has trailing ! */
349 unsigned preind
: 1; /* Preindexed address. */
350 unsigned postind
: 1; /* Postindexed address. */
351 unsigned negative
: 1; /* Index register was negated. */
352 unsigned shifted
: 1; /* Shift applied to operation. */
353 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
357 static struct arm_it inst
;
359 #define NUM_FLOAT_VALS 8
361 const char * fp_const
[] =
363 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
366 /* Number of littlenums required to hold an extended precision number. */
367 #define MAX_LITTLENUMS 6
369 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
379 #define CP_T_X 0x00008000
380 #define CP_T_Y 0x00400000
382 #define CONDS_BIT 0x00100000
383 #define LOAD_BIT 0x00100000
385 #define DOUBLE_LOAD_FLAG 0x00000001
389 const char * template;
393 #define COND_ALWAYS 0xE
397 const char *template;
401 struct asm_barrier_opt
403 const char *template;
407 /* The bit that distinguishes CPSR and SPSR. */
408 #define SPSR_BIT (1 << 22)
410 /* The individual PSR flag bits. */
411 #define PSR_c (1 << 16)
412 #define PSR_x (1 << 17)
413 #define PSR_s (1 << 18)
414 #define PSR_f (1 << 19)
419 bfd_reloc_code_real_type reloc
;
424 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
425 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
430 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
433 /* Bits for DEFINED field in neon_typed_alias. */
434 #define NTA_HASTYPE 1
435 #define NTA_HASINDEX 2
437 struct neon_typed_alias
439 unsigned char defined
;
441 struct neon_type_el eltype
;
444 /* ARM register categories. This includes coprocessor numbers and various
445 architecture extensions' registers. */
471 /* Structure for a hash table entry for a register.
472 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
473 information which states whether a vector type or index is specified (for a
474 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
478 unsigned char number
;
480 unsigned char builtin
;
481 struct neon_typed_alias
*neon
;
484 /* Diagnostics used when we don't get a register of the expected type. */
485 const char *const reg_expected_msgs
[] =
487 N_("ARM register expected"),
488 N_("bad or missing co-processor number"),
489 N_("co-processor register expected"),
490 N_("FPA register expected"),
491 N_("VFP single precision register expected"),
492 N_("VFP/Neon double precision register expected"),
493 N_("Neon quad precision register expected"),
494 N_("VFP single or double precision register expected"),
495 N_("Neon double or quad precision register expected"),
496 N_("VFP single, double or Neon quad precision register expected"),
497 N_("VFP system register expected"),
498 N_("Maverick MVF register expected"),
499 N_("Maverick MVD register expected"),
500 N_("Maverick MVFX register expected"),
501 N_("Maverick MVDX register expected"),
502 N_("Maverick MVAX register expected"),
503 N_("Maverick DSPSC register expected"),
504 N_("iWMMXt data register expected"),
505 N_("iWMMXt control register expected"),
506 N_("iWMMXt scalar register expected"),
507 N_("XScale accumulator register expected"),
510 /* Some well known registers that we refer to directly elsewhere. */
515 /* ARM instructions take 4bytes in the object file, Thumb instructions
521 /* Basic string to match. */
522 const char *template;
524 /* Parameters to instruction. */
525 unsigned char operands
[8];
527 /* Conditional tag - see opcode_lookup. */
528 unsigned int tag
: 4;
530 /* Basic instruction code. */
531 unsigned int avalue
: 28;
533 /* Thumb-format instruction code. */
536 /* Which architecture variant provides this instruction. */
537 const arm_feature_set
*avariant
;
538 const arm_feature_set
*tvariant
;
540 /* Function to call to encode instruction in ARM format. */
541 void (* aencode
) (void);
543 /* Function to call to encode instruction in Thumb format. */
544 void (* tencode
) (void);
547 /* Defines for various bits that we will want to toggle. */
548 #define INST_IMMEDIATE 0x02000000
549 #define OFFSET_REG 0x02000000
550 #define HWOFFSET_IMM 0x00400000
551 #define SHIFT_BY_REG 0x00000010
552 #define PRE_INDEX 0x01000000
553 #define INDEX_UP 0x00800000
554 #define WRITE_BACK 0x00200000
555 #define LDM_TYPE_2_OR_3 0x00400000
556 #define CPSI_MMOD 0x00020000
558 #define LITERAL_MASK 0xf000f000
559 #define OPCODE_MASK 0xfe1fffff
560 #define V4_STR_BIT 0x00000020
562 #define T2_SUBS_PC_LR 0xf3de8f00
564 #define DATA_OP_SHIFT 21
566 #define T2_OPCODE_MASK 0xfe1fffff
567 #define T2_DATA_OP_SHIFT 21
569 /* Codes to distinguish the arithmetic instructions. */
580 #define OPCODE_CMP 10
581 #define OPCODE_CMN 11
582 #define OPCODE_ORR 12
583 #define OPCODE_MOV 13
584 #define OPCODE_BIC 14
585 #define OPCODE_MVN 15
587 #define T2_OPCODE_AND 0
588 #define T2_OPCODE_BIC 1
589 #define T2_OPCODE_ORR 2
590 #define T2_OPCODE_ORN 3
591 #define T2_OPCODE_EOR 4
592 #define T2_OPCODE_ADD 8
593 #define T2_OPCODE_ADC 10
594 #define T2_OPCODE_SBC 11
595 #define T2_OPCODE_SUB 13
596 #define T2_OPCODE_RSB 14
598 #define T_OPCODE_MUL 0x4340
599 #define T_OPCODE_TST 0x4200
600 #define T_OPCODE_CMN 0x42c0
601 #define T_OPCODE_NEG 0x4240
602 #define T_OPCODE_MVN 0x43c0
604 #define T_OPCODE_ADD_R3 0x1800
605 #define T_OPCODE_SUB_R3 0x1a00
606 #define T_OPCODE_ADD_HI 0x4400
607 #define T_OPCODE_ADD_ST 0xb000
608 #define T_OPCODE_SUB_ST 0xb080
609 #define T_OPCODE_ADD_SP 0xa800
610 #define T_OPCODE_ADD_PC 0xa000
611 #define T_OPCODE_ADD_I8 0x3000
612 #define T_OPCODE_SUB_I8 0x3800
613 #define T_OPCODE_ADD_I3 0x1c00
614 #define T_OPCODE_SUB_I3 0x1e00
616 #define T_OPCODE_ASR_R 0x4100
617 #define T_OPCODE_LSL_R 0x4080
618 #define T_OPCODE_LSR_R 0x40c0
619 #define T_OPCODE_ROR_R 0x41c0
620 #define T_OPCODE_ASR_I 0x1000
621 #define T_OPCODE_LSL_I 0x0000
622 #define T_OPCODE_LSR_I 0x0800
624 #define T_OPCODE_MOV_I8 0x2000
625 #define T_OPCODE_CMP_I8 0x2800
626 #define T_OPCODE_CMP_LR 0x4280
627 #define T_OPCODE_MOV_HR 0x4600
628 #define T_OPCODE_CMP_HR 0x4500
630 #define T_OPCODE_LDR_PC 0x4800
631 #define T_OPCODE_LDR_SP 0x9800
632 #define T_OPCODE_STR_SP 0x9000
633 #define T_OPCODE_LDR_IW 0x6800
634 #define T_OPCODE_STR_IW 0x6000
635 #define T_OPCODE_LDR_IH 0x8800
636 #define T_OPCODE_STR_IH 0x8000
637 #define T_OPCODE_LDR_IB 0x7800
638 #define T_OPCODE_STR_IB 0x7000
639 #define T_OPCODE_LDR_RW 0x5800
640 #define T_OPCODE_STR_RW 0x5000
641 #define T_OPCODE_LDR_RH 0x5a00
642 #define T_OPCODE_STR_RH 0x5200
643 #define T_OPCODE_LDR_RB 0x5c00
644 #define T_OPCODE_STR_RB 0x5400
646 #define T_OPCODE_PUSH 0xb400
647 #define T_OPCODE_POP 0xbc00
649 #define T_OPCODE_BRANCH 0xe000
651 #define THUMB_SIZE 2 /* Size of thumb instruction. */
652 #define THUMB_PP_PC_LR 0x0100
653 #define THUMB_LOAD_BIT 0x0800
654 #define THUMB2_LOAD_BIT 0x00100000
656 #define BAD_ARGS _("bad arguments to instruction")
657 #define BAD_PC _("r15 not allowed here")
658 #define BAD_COND _("instruction cannot be conditional")
659 #define BAD_OVERLAP _("registers may not be the same")
660 #define BAD_HIREG _("lo register required")
661 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
662 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
663 #define BAD_BRANCH _("branch must be last instruction in IT block")
664 #define BAD_NOT_IT _("instruction not allowed in IT block")
665 #define BAD_FPU _("selected FPU does not support instruction")
667 static struct hash_control
*arm_ops_hsh
;
668 static struct hash_control
*arm_cond_hsh
;
669 static struct hash_control
*arm_shift_hsh
;
670 static struct hash_control
*arm_psr_hsh
;
671 static struct hash_control
*arm_v7m_psr_hsh
;
672 static struct hash_control
*arm_reg_hsh
;
673 static struct hash_control
*arm_reloc_hsh
;
674 static struct hash_control
*arm_barrier_opt_hsh
;
676 /* Stuff needed to resolve the label ambiguity
685 symbolS
* last_label_seen
;
686 static int label_is_thumb_function_name
= FALSE
;
688 /* Literal pool structure. Held on a per-section
689 and per-sub-section basis. */
691 #define MAX_LITERAL_POOL_SIZE 1024
692 typedef struct literal_pool
694 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
695 unsigned int next_free_entry
;
700 struct literal_pool
* next
;
703 /* Pointer to a linked list of literal pools. */
704 literal_pool
* list_of_pools
= NULL
;
706 /* State variables for IT block handling. */
707 static bfd_boolean current_it_mask
= 0;
708 static int current_cc
;
712 /* This array holds the chars that always start a comment. If the
713 pre-processor is disabled, these aren't very useful. */
714 const char comment_chars
[] = "@";
716 /* This array holds the chars that only start a comment at the beginning of
717 a line. If the line seems to have the form '# 123 filename'
718 .line and .file directives will appear in the pre-processed output. */
719 /* Note that input_file.c hand checks for '#' at the beginning of the
720 first line of the input file. This is because the compiler outputs
721 #NO_APP at the beginning of its output. */
722 /* Also note that comments like this one will always work. */
723 const char line_comment_chars
[] = "#";
725 const char line_separator_chars
[] = ";";
727 /* Chars that can be used to separate mant
728 from exp in floating point numbers. */
729 const char EXP_CHARS
[] = "eE";
731 /* Chars that mean this number is a floating point constant. */
735 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
737 /* Prefix characters that indicate the start of an immediate
739 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
741 /* Separator character handling. */
743 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
746 skip_past_char (char ** str
, char c
)
756 #define skip_past_comma(str) skip_past_char (str, ',')
758 /* Arithmetic expressions (possibly involving symbols). */
760 /* Return TRUE if anything in the expression is a bignum. */
763 walk_no_bignums (symbolS
* sp
)
765 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
768 if (symbol_get_value_expression (sp
)->X_add_symbol
)
770 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
771 || (symbol_get_value_expression (sp
)->X_op_symbol
772 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
778 static int in_my_get_expression
= 0;
780 /* Third argument to my_get_expression. */
781 #define GE_NO_PREFIX 0
782 #define GE_IMM_PREFIX 1
783 #define GE_OPT_PREFIX 2
784 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
785 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
786 #define GE_OPT_PREFIX_BIG 3
789 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
794 /* In unified syntax, all prefixes are optional. */
796 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
801 case GE_NO_PREFIX
: break;
803 if (!is_immediate_prefix (**str
))
805 inst
.error
= _("immediate expression requires a # prefix");
811 case GE_OPT_PREFIX_BIG
:
812 if (is_immediate_prefix (**str
))
818 memset (ep
, 0, sizeof (expressionS
));
820 save_in
= input_line_pointer
;
821 input_line_pointer
= *str
;
822 in_my_get_expression
= 1;
823 seg
= expression (ep
);
824 in_my_get_expression
= 0;
826 if (ep
->X_op
== O_illegal
)
828 /* We found a bad expression in md_operand(). */
829 *str
= input_line_pointer
;
830 input_line_pointer
= save_in
;
831 if (inst
.error
== NULL
)
832 inst
.error
= _("bad expression");
837 if (seg
!= absolute_section
838 && seg
!= text_section
839 && seg
!= data_section
840 && seg
!= bss_section
841 && seg
!= undefined_section
)
843 inst
.error
= _("bad segment");
844 *str
= input_line_pointer
;
845 input_line_pointer
= save_in
;
850 /* Get rid of any bignums now, so that we don't generate an error for which
851 we can't establish a line number later on. Big numbers are never valid
852 in instructions, which is where this routine is always called. */
853 if (prefix_mode
!= GE_OPT_PREFIX_BIG
854 && (ep
->X_op
== O_big
856 && (walk_no_bignums (ep
->X_add_symbol
)
858 && walk_no_bignums (ep
->X_op_symbol
))))))
860 inst
.error
= _("invalid constant");
861 *str
= input_line_pointer
;
862 input_line_pointer
= save_in
;
866 *str
= input_line_pointer
;
867 input_line_pointer
= save_in
;
871 /* Turn a string in input_line_pointer into a floating point constant
872 of type TYPE, and store the appropriate bytes in *LITP. The number
873 of LITTLENUMS emitted is stored in *SIZEP. An error message is
874 returned, or NULL on OK.
876 Note that fp constants aren't represent in the normal way on the ARM.
877 In big endian mode, things are as expected. However, in little endian
878 mode fp constants are big-endian word-wise, and little-endian byte-wise
879 within the words. For example, (double) 1.1 in big endian mode is
880 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
881 the byte sequence 99 99 f1 3f 9a 99 99 99.
883 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
886 md_atof (int type
, char * litP
, int * sizeP
)
889 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
921 return _("Unrecognized or unsupported floating point constant");
924 t
= atof_ieee (input_line_pointer
, type
, words
);
926 input_line_pointer
= t
;
927 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
929 if (target_big_endian
)
931 for (i
= 0; i
< prec
; i
++)
933 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
934 litP
+= sizeof (LITTLENUM_TYPE
);
939 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
940 for (i
= prec
- 1; i
>= 0; i
--)
942 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
943 litP
+= sizeof (LITTLENUM_TYPE
);
946 /* For a 4 byte float the order of elements in `words' is 1 0.
947 For an 8 byte float the order is 1 0 3 2. */
948 for (i
= 0; i
< prec
; i
+= 2)
950 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
951 sizeof (LITTLENUM_TYPE
));
952 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
953 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
954 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
961 /* We handle all bad expressions here, so that we can report the faulty
962 instruction in the error message. */
964 md_operand (expressionS
* expr
)
966 if (in_my_get_expression
)
967 expr
->X_op
= O_illegal
;
970 /* Immediate values. */
972 /* Generic immediate-value read function for use in directives.
973 Accepts anything that 'expression' can fold to a constant.
974 *val receives the number. */
977 immediate_for_directive (int *val
)
980 exp
.X_op
= O_illegal
;
982 if (is_immediate_prefix (*input_line_pointer
))
984 input_line_pointer
++;
988 if (exp
.X_op
!= O_constant
)
990 as_bad (_("expected #constant"));
991 ignore_rest_of_line ();
994 *val
= exp
.X_add_number
;
999 /* Register parsing. */
1001 /* Generic register parser. CCP points to what should be the
1002 beginning of a register name. If it is indeed a valid register
1003 name, advance CCP over it and return the reg_entry structure;
1004 otherwise return NULL. Does not issue diagnostics. */
1006 static struct reg_entry
*
1007 arm_reg_parse_multi (char **ccp
)
1011 struct reg_entry
*reg
;
1013 #ifdef REGISTER_PREFIX
1014 if (*start
!= REGISTER_PREFIX
)
1018 #ifdef OPTIONAL_REGISTER_PREFIX
1019 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1024 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1029 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1031 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1041 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1042 enum arm_reg_type type
)
1044 /* Alternative syntaxes are accepted for a few register classes. */
1051 /* Generic coprocessor register names are allowed for these. */
1052 if (reg
&& reg
->type
== REG_TYPE_CN
)
1057 /* For backward compatibility, a bare number is valid here. */
1059 unsigned long processor
= strtoul (start
, ccp
, 10);
1060 if (*ccp
!= start
&& processor
<= 15)
1064 case REG_TYPE_MMXWC
:
1065 /* WC includes WCG. ??? I'm not sure this is true for all
1066 instructions that take WC registers. */
1067 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1078 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1079 return value is the register number or FAIL. */
1082 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1085 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1088 /* Do not allow a scalar (reg+index) to parse as a register. */
1089 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1092 if (reg
&& reg
->type
== type
)
1095 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1102 /* Parse a Neon type specifier. *STR should point at the leading '.'
1103 character. Does no verification at this stage that the type fits the opcode
1110 Can all be legally parsed by this function.
1112 Fills in neon_type struct pointer with parsed information, and updates STR
1113 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1114 type, FAIL if not. */
1117 parse_neon_type (struct neon_type
*type
, char **str
)
1124 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1126 enum neon_el_type thistype
= NT_untyped
;
1127 unsigned thissize
= -1u;
1134 /* Just a size without an explicit type. */
1138 switch (TOLOWER (*ptr
))
1140 case 'i': thistype
= NT_integer
; break;
1141 case 'f': thistype
= NT_float
; break;
1142 case 'p': thistype
= NT_poly
; break;
1143 case 's': thistype
= NT_signed
; break;
1144 case 'u': thistype
= NT_unsigned
; break;
1146 thistype
= NT_float
;
1151 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1157 /* .f is an abbreviation for .f32. */
1158 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1163 thissize
= strtoul (ptr
, &ptr
, 10);
1165 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1168 as_bad (_("bad size %d in type specifier"), thissize
);
1176 type
->el
[type
->elems
].type
= thistype
;
1177 type
->el
[type
->elems
].size
= thissize
;
1182 /* Empty/missing type is not a successful parse. */
1183 if (type
->elems
== 0)
1191 /* Errors may be set multiple times during parsing or bit encoding
1192 (particularly in the Neon bits), but usually the earliest error which is set
1193 will be the most meaningful. Avoid overwriting it with later (cascading)
1194 errors by calling this function. */
1197 first_error (const char *err
)
1203 /* Parse a single type, e.g. ".s32", leading period included. */
1205 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1208 struct neon_type optype
;
1212 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1214 if (optype
.elems
== 1)
1215 *vectype
= optype
.el
[0];
1218 first_error (_("only one type should be specified for operand"));
1224 first_error (_("vector type expected"));
1236 /* Special meanings for indices (which have a range of 0-7), which will fit into
1239 #define NEON_ALL_LANES 15
1240 #define NEON_INTERLEAVE_LANES 14
1242 /* Parse either a register or a scalar, with an optional type. Return the
1243 register number, and optionally fill in the actual type of the register
1244 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1245 type/index information in *TYPEINFO. */
1248 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1249 enum arm_reg_type
*rtype
,
1250 struct neon_typed_alias
*typeinfo
)
1253 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1254 struct neon_typed_alias atype
;
1255 struct neon_type_el parsetype
;
1259 atype
.eltype
.type
= NT_invtype
;
1260 atype
.eltype
.size
= -1;
1262 /* Try alternate syntax for some types of register. Note these are mutually
1263 exclusive with the Neon syntax extensions. */
1266 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1274 /* Undo polymorphism when a set of register types may be accepted. */
1275 if ((type
== REG_TYPE_NDQ
1276 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1277 || (type
== REG_TYPE_VFSD
1278 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1279 || (type
== REG_TYPE_NSDQ
1280 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1281 || reg
->type
== REG_TYPE_NQ
))
1282 || (type
== REG_TYPE_MMXWC
1283 && (reg
->type
== REG_TYPE_MMXWCG
)))
1286 if (type
!= reg
->type
)
1292 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1294 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1296 first_error (_("can't redefine type for operand"));
1299 atype
.defined
|= NTA_HASTYPE
;
1300 atype
.eltype
= parsetype
;
1303 if (skip_past_char (&str
, '[') == SUCCESS
)
1305 if (type
!= REG_TYPE_VFD
)
1307 first_error (_("only D registers may be indexed"));
1311 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1313 first_error (_("can't change index for operand"));
1317 atype
.defined
|= NTA_HASINDEX
;
1319 if (skip_past_char (&str
, ']') == SUCCESS
)
1320 atype
.index
= NEON_ALL_LANES
;
1325 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1327 if (exp
.X_op
!= O_constant
)
1329 first_error (_("constant expression required"));
1333 if (skip_past_char (&str
, ']') == FAIL
)
1336 atype
.index
= exp
.X_add_number
;
1351 /* Like arm_reg_parse, but allow allow the following extra features:
1352 - If RTYPE is non-zero, return the (possibly restricted) type of the
1353 register (e.g. Neon double or quad reg when either has been requested).
1354 - If this is a Neon vector type with additional type information, fill
1355 in the struct pointed to by VECTYPE (if non-NULL).
1356 This function will fault on encountering a scalar. */
1359 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1360 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1362 struct neon_typed_alias atype
;
1364 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1369 /* Do not allow a scalar (reg+index) to parse as a register. */
1370 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1372 first_error (_("register operand expected, but got scalar"));
1377 *vectype
= atype
.eltype
;
1384 #define NEON_SCALAR_REG(X) ((X) >> 4)
1385 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1387 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1388 have enough information to be able to do a good job bounds-checking. So, we
1389 just do easy checks here, and do further checks later. */
1392 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1396 struct neon_typed_alias atype
;
1398 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1400 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1403 if (atype
.index
== NEON_ALL_LANES
)
1405 first_error (_("scalar must have an index"));
1408 else if (atype
.index
>= 64 / elsize
)
1410 first_error (_("scalar index out of range"));
1415 *type
= atype
.eltype
;
1419 return reg
* 16 + atype
.index
;
1422 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1424 parse_reg_list (char ** strp
)
1426 char * str
= * strp
;
1430 /* We come back here if we get ranges concatenated by '+' or '|'. */
1445 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1447 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1457 first_error (_("bad range in register list"));
1461 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1463 if (range
& (1 << i
))
1465 (_("Warning: duplicated register (r%d) in register list"),
1473 if (range
& (1 << reg
))
1474 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1476 else if (reg
<= cur_reg
)
1477 as_tsktsk (_("Warning: register range not in ascending order"));
1482 while (skip_past_comma (&str
) != FAIL
1483 || (in_range
= 1, *str
++ == '-'));
1488 first_error (_("missing `}'"));
1496 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1499 if (expr
.X_op
== O_constant
)
1501 if (expr
.X_add_number
1502 != (expr
.X_add_number
& 0x0000ffff))
1504 inst
.error
= _("invalid register mask");
1508 if ((range
& expr
.X_add_number
) != 0)
1510 int regno
= range
& expr
.X_add_number
;
1513 regno
= (1 << regno
) - 1;
1515 (_("Warning: duplicated register (r%d) in register list"),
1519 range
|= expr
.X_add_number
;
1523 if (inst
.reloc
.type
!= 0)
1525 inst
.error
= _("expression too complex");
1529 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1530 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1531 inst
.reloc
.pc_rel
= 0;
1535 if (*str
== '|' || *str
== '+')
1541 while (another_range
);
1547 /* Types of registers in a list. */
1556 /* Parse a VFP register list. If the string is invalid return FAIL.
1557 Otherwise return the number of registers, and set PBASE to the first
1558 register. Parses registers of type ETYPE.
1559 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1560 - Q registers can be used to specify pairs of D registers
1561 - { } can be omitted from around a singleton register list
1562 FIXME: This is not implemented, as it would require backtracking in
1565 This could be done (the meaning isn't really ambiguous), but doesn't
1566 fit in well with the current parsing framework.
1567 - 32 D registers may be used (also true for VFPv3).
1568 FIXME: Types are ignored in these register lists, which is probably a
1572 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1577 enum arm_reg_type regtype
= 0;
1581 unsigned long mask
= 0;
1586 inst
.error
= _("expecting {");
1595 regtype
= REG_TYPE_VFS
;
1600 regtype
= REG_TYPE_VFD
;
1603 case REGLIST_NEON_D
:
1604 regtype
= REG_TYPE_NDQ
;
1608 if (etype
!= REGLIST_VFP_S
)
1610 /* VFPv3 allows 32 D registers. */
1611 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1615 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1618 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1625 base_reg
= max_regs
;
1629 int setmask
= 1, addregs
= 1;
1631 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1633 if (new_base
== FAIL
)
1635 first_error (_(reg_expected_msgs
[regtype
]));
1639 if (new_base
>= max_regs
)
1641 first_error (_("register out of range in list"));
1645 /* Note: a value of 2 * n is returned for the register Q<n>. */
1646 if (regtype
== REG_TYPE_NQ
)
1652 if (new_base
< base_reg
)
1653 base_reg
= new_base
;
1655 if (mask
& (setmask
<< new_base
))
1657 first_error (_("invalid register list"));
1661 if ((mask
>> new_base
) != 0 && ! warned
)
1663 as_tsktsk (_("register list not in ascending order"));
1667 mask
|= setmask
<< new_base
;
1670 if (*str
== '-') /* We have the start of a range expression */
1676 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1679 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1683 if (high_range
>= max_regs
)
1685 first_error (_("register out of range in list"));
1689 if (regtype
== REG_TYPE_NQ
)
1690 high_range
= high_range
+ 1;
1692 if (high_range
<= new_base
)
1694 inst
.error
= _("register range not in ascending order");
1698 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1700 if (mask
& (setmask
<< new_base
))
1702 inst
.error
= _("invalid register list");
1706 mask
|= setmask
<< new_base
;
1711 while (skip_past_comma (&str
) != FAIL
);
1715 /* Sanity check -- should have raised a parse error above. */
1716 if (count
== 0 || count
> max_regs
)
1721 /* Final test -- the registers must be consecutive. */
1723 for (i
= 0; i
< count
; i
++)
1725 if ((mask
& (1u << i
)) == 0)
1727 inst
.error
= _("non-contiguous register range");
1737 /* True if two alias types are the same. */
1740 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1748 if (a
->defined
!= b
->defined
)
1751 if ((a
->defined
& NTA_HASTYPE
) != 0
1752 && (a
->eltype
.type
!= b
->eltype
.type
1753 || a
->eltype
.size
!= b
->eltype
.size
))
1756 if ((a
->defined
& NTA_HASINDEX
) != 0
1757 && (a
->index
!= b
->index
))
1763 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1764 The base register is put in *PBASE.
1765 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1767 The register stride (minus one) is put in bit 4 of the return value.
1768 Bits [6:5] encode the list length (minus one).
1769 The type of the list elements is put in *ELTYPE, if non-NULL. */
1771 #define NEON_LANE(X) ((X) & 0xf)
1772 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1773 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1776 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1777 struct neon_type_el
*eltype
)
1784 int leading_brace
= 0;
1785 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1787 const char *const incr_error
= "register stride must be 1 or 2";
1788 const char *const type_error
= "mismatched element/structure types in list";
1789 struct neon_typed_alias firsttype
;
1791 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1796 struct neon_typed_alias atype
;
1797 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1801 first_error (_(reg_expected_msgs
[rtype
]));
1808 if (rtype
== REG_TYPE_NQ
)
1815 else if (reg_incr
== -1)
1817 reg_incr
= getreg
- base_reg
;
1818 if (reg_incr
< 1 || reg_incr
> 2)
1820 first_error (_(incr_error
));
1824 else if (getreg
!= base_reg
+ reg_incr
* count
)
1826 first_error (_(incr_error
));
1830 if (!neon_alias_types_same (&atype
, &firsttype
))
1832 first_error (_(type_error
));
1836 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1840 struct neon_typed_alias htype
;
1841 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1843 lane
= NEON_INTERLEAVE_LANES
;
1844 else if (lane
!= NEON_INTERLEAVE_LANES
)
1846 first_error (_(type_error
));
1851 else if (reg_incr
!= 1)
1853 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1857 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1860 first_error (_(reg_expected_msgs
[rtype
]));
1863 if (!neon_alias_types_same (&htype
, &firsttype
))
1865 first_error (_(type_error
));
1868 count
+= hireg
+ dregs
- getreg
;
1872 /* If we're using Q registers, we can't use [] or [n] syntax. */
1873 if (rtype
== REG_TYPE_NQ
)
1879 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1883 else if (lane
!= atype
.index
)
1885 first_error (_(type_error
));
1889 else if (lane
== -1)
1890 lane
= NEON_INTERLEAVE_LANES
;
1891 else if (lane
!= NEON_INTERLEAVE_LANES
)
1893 first_error (_(type_error
));
1898 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1900 /* No lane set by [x]. We must be interleaving structures. */
1902 lane
= NEON_INTERLEAVE_LANES
;
1905 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1906 || (count
> 1 && reg_incr
== -1))
1908 first_error (_("error parsing element/structure list"));
1912 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1914 first_error (_("expected }"));
1922 *eltype
= firsttype
.eltype
;
1927 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1930 /* Parse an explicit relocation suffix on an expression. This is
1931 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1932 arm_reloc_hsh contains no entries, so this function can only
1933 succeed if there is no () after the word. Returns -1 on error,
1934 BFD_RELOC_UNUSED if there wasn't any suffix. */
1936 parse_reloc (char **str
)
1938 struct reloc_entry
*r
;
1942 return BFD_RELOC_UNUSED
;
1947 while (*q
&& *q
!= ')' && *q
!= ',')
1952 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1959 /* Directives: register aliases. */
1961 static struct reg_entry
*
1962 insert_reg_alias (char *str
, int number
, int type
)
1964 struct reg_entry
*new;
1967 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1970 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1972 /* Only warn about a redefinition if it's not defined as the
1974 else if (new->number
!= number
|| new->type
!= type
)
1975 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1980 name
= xstrdup (str
);
1981 new = xmalloc (sizeof (struct reg_entry
));
1984 new->number
= number
;
1986 new->builtin
= FALSE
;
1989 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1996 insert_neon_reg_alias (char *str
, int number
, int type
,
1997 struct neon_typed_alias
*atype
)
1999 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2003 first_error (_("attempt to redefine typed alias"));
2009 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2010 *reg
->neon
= *atype
;
2014 /* Look for the .req directive. This is of the form:
2016 new_register_name .req existing_register_name
2018 If we find one, or if it looks sufficiently like one that we want to
2019 handle any error here, return TRUE. Otherwise return FALSE. */
2022 create_register_alias (char * newname
, char *p
)
2024 struct reg_entry
*old
;
2025 char *oldname
, *nbuf
;
2028 /* The input scrubber ensures that whitespace after the mnemonic is
2029 collapsed to single spaces. */
2031 if (strncmp (oldname
, " .req ", 6) != 0)
2035 if (*oldname
== '\0')
2038 old
= hash_find (arm_reg_hsh
, oldname
);
2041 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2045 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2046 the desired alias name, and p points to its end. If not, then
2047 the desired alias name is in the global original_case_string. */
2048 #ifdef TC_CASE_SENSITIVE
2051 newname
= original_case_string
;
2052 nlen
= strlen (newname
);
2055 nbuf
= alloca (nlen
+ 1);
2056 memcpy (nbuf
, newname
, nlen
);
2059 /* Create aliases under the new name as stated; an all-lowercase
2060 version of the new name; and an all-uppercase version of the new
2062 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2064 for (p
= nbuf
; *p
; p
++)
2067 if (strncmp (nbuf
, newname
, nlen
))
2069 /* If this attempt to create an additional alias fails, do not bother
2070 trying to create the all-lower case alias. We will fail and issue
2071 a second, duplicate error message. This situation arises when the
2072 programmer does something like:
2075 The second .req creates the "Foo" alias but then fails to create
2076 the artificial FOO alias because it has already been created by the
2078 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2082 for (p
= nbuf
; *p
; p
++)
2085 if (strncmp (nbuf
, newname
, nlen
))
2086 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2092 /* Create a Neon typed/indexed register alias using directives, e.g.:
2097 These typed registers can be used instead of the types specified after the
2098 Neon mnemonic, so long as all operands given have types. Types can also be
2099 specified directly, e.g.:
2100 vadd d0.s32, d1.s32, d2.s32 */
2103 create_neon_reg_alias (char *newname
, char *p
)
2105 enum arm_reg_type basetype
;
2106 struct reg_entry
*basereg
;
2107 struct reg_entry mybasereg
;
2108 struct neon_type ntype
;
2109 struct neon_typed_alias typeinfo
;
2110 char *namebuf
, *nameend
;
2113 typeinfo
.defined
= 0;
2114 typeinfo
.eltype
.type
= NT_invtype
;
2115 typeinfo
.eltype
.size
= -1;
2116 typeinfo
.index
= -1;
2120 if (strncmp (p
, " .dn ", 5) == 0)
2121 basetype
= REG_TYPE_VFD
;
2122 else if (strncmp (p
, " .qn ", 5) == 0)
2123 basetype
= REG_TYPE_NQ
;
2132 basereg
= arm_reg_parse_multi (&p
);
2134 if (basereg
&& basereg
->type
!= basetype
)
2136 as_bad (_("bad type for register"));
2140 if (basereg
== NULL
)
2143 /* Try parsing as an integer. */
2144 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2145 if (exp
.X_op
!= O_constant
)
2147 as_bad (_("expression must be constant"));
2150 basereg
= &mybasereg
;
2151 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2157 typeinfo
= *basereg
->neon
;
2159 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2161 /* We got a type. */
2162 if (typeinfo
.defined
& NTA_HASTYPE
)
2164 as_bad (_("can't redefine the type of a register alias"));
2168 typeinfo
.defined
|= NTA_HASTYPE
;
2169 if (ntype
.elems
!= 1)
2171 as_bad (_("you must specify a single type only"));
2174 typeinfo
.eltype
= ntype
.el
[0];
2177 if (skip_past_char (&p
, '[') == SUCCESS
)
2180 /* We got a scalar index. */
2182 if (typeinfo
.defined
& NTA_HASINDEX
)
2184 as_bad (_("can't redefine the index of a scalar alias"));
2188 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2190 if (exp
.X_op
!= O_constant
)
2192 as_bad (_("scalar index must be constant"));
2196 typeinfo
.defined
|= NTA_HASINDEX
;
2197 typeinfo
.index
= exp
.X_add_number
;
2199 if (skip_past_char (&p
, ']') == FAIL
)
2201 as_bad (_("expecting ]"));
2206 namelen
= nameend
- newname
;
2207 namebuf
= alloca (namelen
+ 1);
2208 strncpy (namebuf
, newname
, namelen
);
2209 namebuf
[namelen
] = '\0';
2211 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2212 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2214 /* Insert name in all uppercase. */
2215 for (p
= namebuf
; *p
; p
++)
2218 if (strncmp (namebuf
, newname
, namelen
))
2219 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2220 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2222 /* Insert name in all lowercase. */
2223 for (p
= namebuf
; *p
; p
++)
2226 if (strncmp (namebuf
, newname
, namelen
))
2227 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2228 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2233 /* Should never be called, as .req goes between the alias and the
2234 register name, not at the beginning of the line. */
2236 s_req (int a ATTRIBUTE_UNUSED
)
2238 as_bad (_("invalid syntax for .req directive"));
2242 s_dn (int a ATTRIBUTE_UNUSED
)
2244 as_bad (_("invalid syntax for .dn directive"));
2248 s_qn (int a ATTRIBUTE_UNUSED
)
2250 as_bad (_("invalid syntax for .qn directive"));
2253 /* The .unreq directive deletes an alias which was previously defined
2254 by .req. For example:
2260 s_unreq (int a ATTRIBUTE_UNUSED
)
2265 name
= input_line_pointer
;
2267 while (*input_line_pointer
!= 0
2268 && *input_line_pointer
!= ' '
2269 && *input_line_pointer
!= '\n')
2270 ++input_line_pointer
;
2272 saved_char
= *input_line_pointer
;
2273 *input_line_pointer
= 0;
2276 as_bad (_("invalid syntax for .unreq directive"));
2279 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2282 as_bad (_("unknown register alias '%s'"), name
);
2283 else if (reg
->builtin
)
2284 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2291 hash_delete (arm_reg_hsh
, name
);
2292 free ((char *) reg
->name
);
2297 /* Also locate the all upper case and all lower case versions.
2298 Do not complain if we cannot find one or the other as it
2299 was probably deleted above. */
2301 nbuf
= strdup (name
);
2302 for (p
= nbuf
; *p
; p
++)
2304 reg
= hash_find (arm_reg_hsh
, nbuf
);
2307 hash_delete (arm_reg_hsh
, nbuf
);
2308 free ((char *) reg
->name
);
2314 for (p
= nbuf
; *p
; p
++)
2316 reg
= hash_find (arm_reg_hsh
, nbuf
);
2319 hash_delete (arm_reg_hsh
, nbuf
);
2320 free ((char *) reg
->name
);
2330 *input_line_pointer
= saved_char
;
2331 demand_empty_rest_of_line ();
2334 /* Directives: Instruction set selection. */
2337 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2338 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2339 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2340 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2342 static enum mstate mapstate
= MAP_UNDEFINED
;
2345 mapping_state (enum mstate state
)
2348 const char * symname
;
2351 if (mapstate
== state
)
2352 /* The mapping symbol has already been emitted.
2353 There is nothing else to do. */
2362 type
= BSF_NO_FLAGS
;
2366 type
= BSF_NO_FLAGS
;
2370 type
= BSF_NO_FLAGS
;
2378 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2380 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2381 symbol_table_insert (symbolP
);
2382 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2387 THUMB_SET_FUNC (symbolP
, 0);
2388 ARM_SET_THUMB (symbolP
, 0);
2389 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2393 THUMB_SET_FUNC (symbolP
, 1);
2394 ARM_SET_THUMB (symbolP
, 1);
2395 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2404 #define mapping_state(x) /* nothing */
2407 /* Find the real, Thumb encoded start of a Thumb function. */
2410 find_real_start (symbolS
* symbolP
)
2413 const char * name
= S_GET_NAME (symbolP
);
2414 symbolS
* new_target
;
2416 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2417 #define STUB_NAME ".real_start_of"
2422 /* The compiler may generate BL instructions to local labels because
2423 it needs to perform a branch to a far away location. These labels
2424 do not have a corresponding ".real_start_of" label. We check
2425 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2426 the ".real_start_of" convention for nonlocal branches. */
2427 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2430 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2431 new_target
= symbol_find (real_start
);
2433 if (new_target
== NULL
)
2435 as_warn (_("Failed to find real start of function: %s\n"), name
);
2436 new_target
= symbolP
;
2443 opcode_select (int width
)
2450 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2451 as_bad (_("selected processor does not support THUMB opcodes"));
2454 /* No need to force the alignment, since we will have been
2455 coming from ARM mode, which is word-aligned. */
2456 record_alignment (now_seg
, 1);
2458 mapping_state (MAP_THUMB
);
2464 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2465 as_bad (_("selected processor does not support ARM opcodes"));
2470 frag_align (2, 0, 0);
2472 record_alignment (now_seg
, 1);
2474 mapping_state (MAP_ARM
);
2478 as_bad (_("invalid instruction size selected (%d)"), width
);
2483 s_arm (int ignore ATTRIBUTE_UNUSED
)
2486 demand_empty_rest_of_line ();
2490 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2493 demand_empty_rest_of_line ();
2497 s_code (int unused ATTRIBUTE_UNUSED
)
2501 temp
= get_absolute_expression ();
2506 opcode_select (temp
);
2510 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2515 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2517 /* If we are not already in thumb mode go into it, EVEN if
2518 the target processor does not support thumb instructions.
2519 This is used by gcc/config/arm/lib1funcs.asm for example
2520 to compile interworking support functions even if the
2521 target processor should not support interworking. */
2525 record_alignment (now_seg
, 1);
2528 demand_empty_rest_of_line ();
2532 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2536 /* The following label is the name/address of the start of a Thumb function.
2537 We need to know this for the interworking support. */
2538 label_is_thumb_function_name
= TRUE
;
2541 /* Perform a .set directive, but also mark the alias as
2542 being a thumb function. */
2545 s_thumb_set (int equiv
)
2547 /* XXX the following is a duplicate of the code for s_set() in read.c
2548 We cannot just call that code as we need to get at the symbol that
2555 /* Especial apologies for the random logic:
2556 This just grew, and could be parsed much more simply!
2558 name
= input_line_pointer
;
2559 delim
= get_symbol_end ();
2560 end_name
= input_line_pointer
;
2563 if (*input_line_pointer
!= ',')
2566 as_bad (_("expected comma after name \"%s\""), name
);
2568 ignore_rest_of_line ();
2572 input_line_pointer
++;
2575 if (name
[0] == '.' && name
[1] == '\0')
2577 /* XXX - this should not happen to .thumb_set. */
2581 if ((symbolP
= symbol_find (name
)) == NULL
2582 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2585 /* When doing symbol listings, play games with dummy fragments living
2586 outside the normal fragment chain to record the file and line info
2588 if (listing
& LISTING_SYMBOLS
)
2590 extern struct list_info_struct
* listing_tail
;
2591 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2593 memset (dummy_frag
, 0, sizeof (fragS
));
2594 dummy_frag
->fr_type
= rs_fill
;
2595 dummy_frag
->line
= listing_tail
;
2596 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2597 dummy_frag
->fr_symbol
= symbolP
;
2601 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2604 /* "set" symbols are local unless otherwise specified. */
2605 SF_SET_LOCAL (symbolP
);
2606 #endif /* OBJ_COFF */
2607 } /* Make a new symbol. */
2609 symbol_table_insert (symbolP
);
2614 && S_IS_DEFINED (symbolP
)
2615 && S_GET_SEGMENT (symbolP
) != reg_section
)
2616 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2618 pseudo_set (symbolP
);
2620 demand_empty_rest_of_line ();
2622 /* XXX Now we come to the Thumb specific bit of code. */
2624 THUMB_SET_FUNC (symbolP
, 1);
2625 ARM_SET_THUMB (symbolP
, 1);
2626 #if defined OBJ_ELF || defined OBJ_COFF
2627 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2631 /* Directives: Mode selection. */
2633 /* .syntax [unified|divided] - choose the new unified syntax
2634 (same for Arm and Thumb encoding, modulo slight differences in what
2635 can be represented) or the old divergent syntax for each mode. */
2637 s_syntax (int unused ATTRIBUTE_UNUSED
)
2641 name
= input_line_pointer
;
2642 delim
= get_symbol_end ();
2644 if (!strcasecmp (name
, "unified"))
2645 unified_syntax
= TRUE
;
2646 else if (!strcasecmp (name
, "divided"))
2647 unified_syntax
= FALSE
;
2650 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2653 *input_line_pointer
= delim
;
2654 demand_empty_rest_of_line ();
2657 /* Directives: sectioning and alignment. */
2659 /* Same as s_align_ptwo but align 0 => align 2. */
2662 s_align (int unused ATTRIBUTE_UNUSED
)
2667 long max_alignment
= 15;
2669 temp
= get_absolute_expression ();
2670 if (temp
> max_alignment
)
2671 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2674 as_bad (_("alignment negative. 0 assumed."));
2678 if (*input_line_pointer
== ',')
2680 input_line_pointer
++;
2681 temp_fill
= get_absolute_expression ();
2693 /* Only make a frag if we HAVE to. */
2694 if (temp
&& !need_pass_2
)
2696 if (!fill_p
&& subseg_text_p (now_seg
))
2697 frag_align_code (temp
, 0);
2699 frag_align (temp
, (int) temp_fill
, 0);
2701 demand_empty_rest_of_line ();
2703 record_alignment (now_seg
, temp
);
2707 s_bss (int ignore ATTRIBUTE_UNUSED
)
2709 /* We don't support putting frags in the BSS segment, we fake it by
2710 marking in_bss, then looking at s_skip for clues. */
2711 subseg_set (bss_section
, 0);
2712 demand_empty_rest_of_line ();
2713 mapping_state (MAP_DATA
);
2717 s_even (int ignore ATTRIBUTE_UNUSED
)
2719 /* Never make frag if expect extra pass. */
2721 frag_align (1, 0, 0);
2723 record_alignment (now_seg
, 1);
2725 demand_empty_rest_of_line ();
2728 /* Directives: Literal pools. */
2730 static literal_pool
*
2731 find_literal_pool (void)
2733 literal_pool
* pool
;
2735 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2737 if (pool
->section
== now_seg
2738 && pool
->sub_section
== now_subseg
)
2745 static literal_pool
*
2746 find_or_make_literal_pool (void)
2748 /* Next literal pool ID number. */
2749 static unsigned int latest_pool_num
= 1;
2750 literal_pool
* pool
;
2752 pool
= find_literal_pool ();
2756 /* Create a new pool. */
2757 pool
= xmalloc (sizeof (* pool
));
2761 pool
->next_free_entry
= 0;
2762 pool
->section
= now_seg
;
2763 pool
->sub_section
= now_subseg
;
2764 pool
->next
= list_of_pools
;
2765 pool
->symbol
= NULL
;
2767 /* Add it to the list. */
2768 list_of_pools
= pool
;
2771 /* New pools, and emptied pools, will have a NULL symbol. */
2772 if (pool
->symbol
== NULL
)
2774 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2775 (valueT
) 0, &zero_address_frag
);
2776 pool
->id
= latest_pool_num
++;
2783 /* Add the literal in the global 'inst'
2784 structure to the relevant literal pool. */
2787 add_to_lit_pool (void)
2789 literal_pool
* pool
;
2792 pool
= find_or_make_literal_pool ();
2794 /* Check if this literal value is already in the pool. */
2795 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2797 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2798 && (inst
.reloc
.exp
.X_op
== O_constant
)
2799 && (pool
->literals
[entry
].X_add_number
2800 == inst
.reloc
.exp
.X_add_number
)
2801 && (pool
->literals
[entry
].X_unsigned
2802 == inst
.reloc
.exp
.X_unsigned
))
2805 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2806 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2807 && (pool
->literals
[entry
].X_add_number
2808 == inst
.reloc
.exp
.X_add_number
)
2809 && (pool
->literals
[entry
].X_add_symbol
2810 == inst
.reloc
.exp
.X_add_symbol
)
2811 && (pool
->literals
[entry
].X_op_symbol
2812 == inst
.reloc
.exp
.X_op_symbol
))
2816 /* Do we need to create a new entry? */
2817 if (entry
== pool
->next_free_entry
)
2819 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2821 inst
.error
= _("literal pool overflow");
2825 pool
->literals
[entry
] = inst
.reloc
.exp
;
2826 pool
->next_free_entry
+= 1;
2829 inst
.reloc
.exp
.X_op
= O_symbol
;
2830 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2831 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2836 /* Can't use symbol_new here, so have to create a symbol and then at
2837 a later date assign it a value. Thats what these functions do. */
2840 symbol_locate (symbolS
* symbolP
,
2841 const char * name
, /* It is copied, the caller can modify. */
2842 segT segment
, /* Segment identifier (SEG_<something>). */
2843 valueT valu
, /* Symbol value. */
2844 fragS
* frag
) /* Associated fragment. */
2846 unsigned int name_length
;
2847 char * preserved_copy_of_name
;
2849 name_length
= strlen (name
) + 1; /* +1 for \0. */
2850 obstack_grow (¬es
, name
, name_length
);
2851 preserved_copy_of_name
= obstack_finish (¬es
);
2853 #ifdef tc_canonicalize_symbol_name
2854 preserved_copy_of_name
=
2855 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2858 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2860 S_SET_SEGMENT (symbolP
, segment
);
2861 S_SET_VALUE (symbolP
, valu
);
2862 symbol_clear_list_pointers (symbolP
);
2864 symbol_set_frag (symbolP
, frag
);
2866 /* Link to end of symbol chain. */
2868 extern int symbol_table_frozen
;
2870 if (symbol_table_frozen
)
2874 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2876 obj_symbol_new_hook (symbolP
);
2878 #ifdef tc_symbol_new_hook
2879 tc_symbol_new_hook (symbolP
);
2883 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2884 #endif /* DEBUG_SYMS */
2889 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2892 literal_pool
* pool
;
2895 pool
= find_literal_pool ();
2897 || pool
->symbol
== NULL
2898 || pool
->next_free_entry
== 0)
2901 mapping_state (MAP_DATA
);
2903 /* Align pool as you have word accesses.
2904 Only make a frag if we have to. */
2906 frag_align (2, 0, 0);
2908 record_alignment (now_seg
, 2);
2910 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2912 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2913 (valueT
) frag_now_fix (), frag_now
);
2914 symbol_table_insert (pool
->symbol
);
2916 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2918 #if defined OBJ_COFF || defined OBJ_ELF
2919 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2922 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2923 /* First output the expression in the instruction to the pool. */
2924 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2926 /* Mark the pool as empty. */
2927 pool
->next_free_entry
= 0;
2928 pool
->symbol
= NULL
;
2932 /* Forward declarations for functions below, in the MD interface
2934 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2935 static valueT
create_unwind_entry (int);
2936 static void start_unwind_section (const segT
, int);
2937 static void add_unwind_opcode (valueT
, int);
2938 static void flush_pending_unwind (void);
2940 /* Directives: Data. */
2943 s_arm_elf_cons (int nbytes
)
2947 #ifdef md_flush_pending_output
2948 md_flush_pending_output ();
2951 if (is_it_end_of_statement ())
2953 demand_empty_rest_of_line ();
2957 #ifdef md_cons_align
2958 md_cons_align (nbytes
);
2961 mapping_state (MAP_DATA
);
2965 char *base
= input_line_pointer
;
2969 if (exp
.X_op
!= O_symbol
)
2970 emit_expr (&exp
, (unsigned int) nbytes
);
2973 char *before_reloc
= input_line_pointer
;
2974 reloc
= parse_reloc (&input_line_pointer
);
2977 as_bad (_("unrecognized relocation suffix"));
2978 ignore_rest_of_line ();
2981 else if (reloc
== BFD_RELOC_UNUSED
)
2982 emit_expr (&exp
, (unsigned int) nbytes
);
2985 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2986 int size
= bfd_get_reloc_size (howto
);
2988 if (reloc
== BFD_RELOC_ARM_PLT32
)
2990 as_bad (_("(plt) is only valid on branch targets"));
2991 reloc
= BFD_RELOC_UNUSED
;
2996 as_bad (_("%s relocations do not fit in %d bytes"),
2997 howto
->name
, nbytes
);
3000 /* We've parsed an expression stopping at O_symbol.
3001 But there may be more expression left now that we
3002 have parsed the relocation marker. Parse it again.
3003 XXX Surely there is a cleaner way to do this. */
3004 char *p
= input_line_pointer
;
3006 char *save_buf
= alloca (input_line_pointer
- base
);
3007 memcpy (save_buf
, base
, input_line_pointer
- base
);
3008 memmove (base
+ (input_line_pointer
- before_reloc
),
3009 base
, before_reloc
- base
);
3011 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3013 memcpy (base
, save_buf
, p
- base
);
3015 offset
= nbytes
- size
;
3016 p
= frag_more ((int) nbytes
);
3017 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3018 size
, &exp
, 0, reloc
);
3023 while (*input_line_pointer
++ == ',');
3025 /* Put terminator back into stream. */
3026 input_line_pointer
--;
3027 demand_empty_rest_of_line ();
3031 /* Parse a .rel31 directive. */
3034 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3041 if (*input_line_pointer
== '1')
3042 highbit
= 0x80000000;
3043 else if (*input_line_pointer
!= '0')
3044 as_bad (_("expected 0 or 1"));
3046 input_line_pointer
++;
3047 if (*input_line_pointer
!= ',')
3048 as_bad (_("missing comma"));
3049 input_line_pointer
++;
3051 #ifdef md_flush_pending_output
3052 md_flush_pending_output ();
3055 #ifdef md_cons_align
3059 mapping_state (MAP_DATA
);
3064 md_number_to_chars (p
, highbit
, 4);
3065 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3066 BFD_RELOC_ARM_PREL31
);
3068 demand_empty_rest_of_line ();
3071 /* Directives: AEABI stack-unwind tables. */
3073 /* Parse an unwind_fnstart directive. Simply records the current location. */
3076 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3078 demand_empty_rest_of_line ();
3079 /* Mark the start of the function. */
3080 unwind
.proc_start
= expr_build_dot ();
3082 /* Reset the rest of the unwind info. */
3083 unwind
.opcode_count
= 0;
3084 unwind
.table_entry
= NULL
;
3085 unwind
.personality_routine
= NULL
;
3086 unwind
.personality_index
= -1;
3087 unwind
.frame_size
= 0;
3088 unwind
.fp_offset
= 0;
3091 unwind
.sp_restored
= 0;
3095 /* Parse a handlerdata directive. Creates the exception handling table entry
3096 for the function. */
3099 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3101 demand_empty_rest_of_line ();
3102 if (unwind
.table_entry
)
3103 as_bad (_("duplicate .handlerdata directive"));
3105 create_unwind_entry (1);
3108 /* Parse an unwind_fnend directive. Generates the index table entry. */
3111 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3117 demand_empty_rest_of_line ();
3119 /* Add eh table entry. */
3120 if (unwind
.table_entry
== NULL
)
3121 val
= create_unwind_entry (0);
3125 /* Add index table entry. This is two words. */
3126 start_unwind_section (unwind
.saved_seg
, 1);
3127 frag_align (2, 0, 0);
3128 record_alignment (now_seg
, 2);
3130 ptr
= frag_more (8);
3131 where
= frag_now_fix () - 8;
3133 /* Self relative offset of the function start. */
3134 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3135 BFD_RELOC_ARM_PREL31
);
3137 /* Indicate dependency on EHABI-defined personality routines to the
3138 linker, if it hasn't been done already. */
3139 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3140 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3142 static const char *const name
[] =
3144 "__aeabi_unwind_cpp_pr0",
3145 "__aeabi_unwind_cpp_pr1",
3146 "__aeabi_unwind_cpp_pr2"
3148 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3149 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3150 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3151 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3152 = marked_pr_dependency
;
3156 /* Inline exception table entry. */
3157 md_number_to_chars (ptr
+ 4, val
, 4);
3159 /* Self relative offset of the table entry. */
3160 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3161 BFD_RELOC_ARM_PREL31
);
3163 /* Restore the original section. */
3164 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3168 /* Parse an unwind_cantunwind directive. */
3171 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3173 demand_empty_rest_of_line ();
3174 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3175 as_bad (_("personality routine specified for cantunwind frame"));
3177 unwind
.personality_index
= -2;
3181 /* Parse a personalityindex directive. */
3184 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3188 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3189 as_bad (_("duplicate .personalityindex directive"));
3193 if (exp
.X_op
!= O_constant
3194 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3196 as_bad (_("bad personality routine number"));
3197 ignore_rest_of_line ();
3201 unwind
.personality_index
= exp
.X_add_number
;
3203 demand_empty_rest_of_line ();
3207 /* Parse a personality directive. */
3210 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3214 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3215 as_bad (_("duplicate .personality directive"));
3217 name
= input_line_pointer
;
3218 c
= get_symbol_end ();
3219 p
= input_line_pointer
;
3220 unwind
.personality_routine
= symbol_find_or_make (name
);
3222 demand_empty_rest_of_line ();
3226 /* Parse a directive saving core registers. */
3229 s_arm_unwind_save_core (void)
3235 range
= parse_reg_list (&input_line_pointer
);
3238 as_bad (_("expected register list"));
3239 ignore_rest_of_line ();
3243 demand_empty_rest_of_line ();
3245 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3246 into .unwind_save {..., sp...}. We aren't bothered about the value of
3247 ip because it is clobbered by calls. */
3248 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3249 && (range
& 0x3000) == 0x1000)
3251 unwind
.opcode_count
--;
3252 unwind
.sp_restored
= 0;
3253 range
= (range
| 0x2000) & ~0x1000;
3254 unwind
.pending_offset
= 0;
3260 /* See if we can use the short opcodes. These pop a block of up to 8
3261 registers starting with r4, plus maybe r14. */
3262 for (n
= 0; n
< 8; n
++)
3264 /* Break at the first non-saved register. */
3265 if ((range
& (1 << (n
+ 4))) == 0)
3268 /* See if there are any other bits set. */
3269 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3271 /* Use the long form. */
3272 op
= 0x8000 | ((range
>> 4) & 0xfff);
3273 add_unwind_opcode (op
, 2);
3277 /* Use the short form. */
3279 op
= 0xa8; /* Pop r14. */
3281 op
= 0xa0; /* Do not pop r14. */
3283 add_unwind_opcode (op
, 1);
3290 op
= 0xb100 | (range
& 0xf);
3291 add_unwind_opcode (op
, 2);
3294 /* Record the number of bytes pushed. */
3295 for (n
= 0; n
< 16; n
++)
3297 if (range
& (1 << n
))
3298 unwind
.frame_size
+= 4;
3303 /* Parse a directive saving FPA registers. */
3306 s_arm_unwind_save_fpa (int reg
)
3312 /* Get Number of registers to transfer. */
3313 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3316 exp
.X_op
= O_illegal
;
3318 if (exp
.X_op
!= O_constant
)
3320 as_bad (_("expected , <constant>"));
3321 ignore_rest_of_line ();
3325 num_regs
= exp
.X_add_number
;
3327 if (num_regs
< 1 || num_regs
> 4)
3329 as_bad (_("number of registers must be in the range [1:4]"));
3330 ignore_rest_of_line ();
3334 demand_empty_rest_of_line ();
3339 op
= 0xb4 | (num_regs
- 1);
3340 add_unwind_opcode (op
, 1);
3345 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3346 add_unwind_opcode (op
, 2);
3348 unwind
.frame_size
+= num_regs
* 12;
3352 /* Parse a directive saving VFP registers for ARMv6 and above. */
3355 s_arm_unwind_save_vfp_armv6 (void)
3360 int num_vfpv3_regs
= 0;
3361 int num_regs_below_16
;
3363 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3366 as_bad (_("expected register list"));
3367 ignore_rest_of_line ();
3371 demand_empty_rest_of_line ();
3373 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3374 than FSTMX/FLDMX-style ones). */
3376 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3378 num_vfpv3_regs
= count
;
3379 else if (start
+ count
> 16)
3380 num_vfpv3_regs
= start
+ count
- 16;
3382 if (num_vfpv3_regs
> 0)
3384 int start_offset
= start
> 16 ? start
- 16 : 0;
3385 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3386 add_unwind_opcode (op
, 2);
3389 /* Generate opcode for registers numbered in the range 0 .. 15. */
3390 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3391 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3392 if (num_regs_below_16
> 0)
3394 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3395 add_unwind_opcode (op
, 2);
3398 unwind
.frame_size
+= count
* 8;
3402 /* Parse a directive saving VFP registers for pre-ARMv6. */
3405 s_arm_unwind_save_vfp (void)
3411 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3414 as_bad (_("expected register list"));
3415 ignore_rest_of_line ();
3419 demand_empty_rest_of_line ();
3424 op
= 0xb8 | (count
- 1);
3425 add_unwind_opcode (op
, 1);
3430 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3431 add_unwind_opcode (op
, 2);
3433 unwind
.frame_size
+= count
* 8 + 4;
3437 /* Parse a directive saving iWMMXt data registers. */
3440 s_arm_unwind_save_mmxwr (void)
3448 if (*input_line_pointer
== '{')
3449 input_line_pointer
++;
3453 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3457 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3462 as_tsktsk (_("register list not in ascending order"));
3465 if (*input_line_pointer
== '-')
3467 input_line_pointer
++;
3468 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3471 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3474 else if (reg
>= hi_reg
)
3476 as_bad (_("bad register range"));
3479 for (; reg
< hi_reg
; reg
++)
3483 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3485 if (*input_line_pointer
== '}')
3486 input_line_pointer
++;
3488 demand_empty_rest_of_line ();
3490 /* Generate any deferred opcodes because we're going to be looking at
3492 flush_pending_unwind ();
3494 for (i
= 0; i
< 16; i
++)
3496 if (mask
& (1 << i
))
3497 unwind
.frame_size
+= 8;
3500 /* Attempt to combine with a previous opcode. We do this because gcc
3501 likes to output separate unwind directives for a single block of
3503 if (unwind
.opcode_count
> 0)
3505 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3506 if ((i
& 0xf8) == 0xc0)
3509 /* Only merge if the blocks are contiguous. */
3512 if ((mask
& 0xfe00) == (1 << 9))
3514 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3515 unwind
.opcode_count
--;
3518 else if (i
== 6 && unwind
.opcode_count
>= 2)
3520 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3524 op
= 0xffff << (reg
- 1);
3526 && ((mask
& op
) == (1u << (reg
- 1))))
3528 op
= (1 << (reg
+ i
+ 1)) - 1;
3529 op
&= ~((1 << reg
) - 1);
3531 unwind
.opcode_count
-= 2;
3538 /* We want to generate opcodes in the order the registers have been
3539 saved, ie. descending order. */
3540 for (reg
= 15; reg
>= -1; reg
--)
3542 /* Save registers in blocks. */
3544 || !(mask
& (1 << reg
)))
3546 /* We found an unsaved reg. Generate opcodes to save the
3553 op
= 0xc0 | (hi_reg
- 10);
3554 add_unwind_opcode (op
, 1);
3559 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3560 add_unwind_opcode (op
, 2);
3569 ignore_rest_of_line ();
3573 s_arm_unwind_save_mmxwcg (void)
3580 if (*input_line_pointer
== '{')
3581 input_line_pointer
++;
3585 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3589 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3595 as_tsktsk (_("register list not in ascending order"));
3598 if (*input_line_pointer
== '-')
3600 input_line_pointer
++;
3601 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3604 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3607 else if (reg
>= hi_reg
)
3609 as_bad (_("bad register range"));
3612 for (; reg
< hi_reg
; reg
++)
3616 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3618 if (*input_line_pointer
== '}')
3619 input_line_pointer
++;
3621 demand_empty_rest_of_line ();
3623 /* Generate any deferred opcodes because we're going to be looking at
3625 flush_pending_unwind ();
3627 for (reg
= 0; reg
< 16; reg
++)
3629 if (mask
& (1 << reg
))
3630 unwind
.frame_size
+= 4;
3633 add_unwind_opcode (op
, 2);
3636 ignore_rest_of_line ();
3640 /* Parse an unwind_save directive.
3641 If the argument is non-zero, this is a .vsave directive. */
3644 s_arm_unwind_save (int arch_v6
)
3647 struct reg_entry
*reg
;
3648 bfd_boolean had_brace
= FALSE
;
3650 /* Figure out what sort of save we have. */
3651 peek
= input_line_pointer
;
3659 reg
= arm_reg_parse_multi (&peek
);
3663 as_bad (_("register expected"));
3664 ignore_rest_of_line ();
3673 as_bad (_("FPA .unwind_save does not take a register list"));
3674 ignore_rest_of_line ();
3677 input_line_pointer
= peek
;
3678 s_arm_unwind_save_fpa (reg
->number
);
3681 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3684 s_arm_unwind_save_vfp_armv6 ();
3686 s_arm_unwind_save_vfp ();
3688 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3689 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3692 as_bad (_(".unwind_save does not support this kind of register"));
3693 ignore_rest_of_line ();
3698 /* Parse an unwind_movsp directive. */
3701 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3707 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3710 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3711 ignore_rest_of_line ();
3715 /* Optional constant. */
3716 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3718 if (immediate_for_directive (&offset
) == FAIL
)
3724 demand_empty_rest_of_line ();
3726 if (reg
== REG_SP
|| reg
== REG_PC
)
3728 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3732 if (unwind
.fp_reg
!= REG_SP
)
3733 as_bad (_("unexpected .unwind_movsp directive"));
3735 /* Generate opcode to restore the value. */
3737 add_unwind_opcode (op
, 1);
3739 /* Record the information for later. */
3740 unwind
.fp_reg
= reg
;
3741 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3742 unwind
.sp_restored
= 1;
3745 /* Parse an unwind_pad directive. */
3748 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3752 if (immediate_for_directive (&offset
) == FAIL
)
3757 as_bad (_("stack increment must be multiple of 4"));
3758 ignore_rest_of_line ();
3762 /* Don't generate any opcodes, just record the details for later. */
3763 unwind
.frame_size
+= offset
;
3764 unwind
.pending_offset
+= offset
;
3766 demand_empty_rest_of_line ();
3769 /* Parse an unwind_setfp directive. */
3772 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3778 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3779 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3782 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3784 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3786 as_bad (_("expected <reg>, <reg>"));
3787 ignore_rest_of_line ();
3791 /* Optional constant. */
3792 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3794 if (immediate_for_directive (&offset
) == FAIL
)
3800 demand_empty_rest_of_line ();
3802 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3804 as_bad (_("register must be either sp or set by a previous"
3805 "unwind_movsp directive"));
3809 /* Don't generate any opcodes, just record the information for later. */
3810 unwind
.fp_reg
= fp_reg
;
3813 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3815 unwind
.fp_offset
-= offset
;
3818 /* Parse an unwind_raw directive. */
3821 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3824 /* This is an arbitrary limit. */
3825 unsigned char op
[16];
3829 if (exp
.X_op
== O_constant
3830 && skip_past_comma (&input_line_pointer
) != FAIL
)
3832 unwind
.frame_size
+= exp
.X_add_number
;
3836 exp
.X_op
= O_illegal
;
3838 if (exp
.X_op
!= O_constant
)
3840 as_bad (_("expected <offset>, <opcode>"));
3841 ignore_rest_of_line ();
3847 /* Parse the opcode. */
3852 as_bad (_("unwind opcode too long"));
3853 ignore_rest_of_line ();
3855 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3857 as_bad (_("invalid unwind opcode"));
3858 ignore_rest_of_line ();
3861 op
[count
++] = exp
.X_add_number
;
3863 /* Parse the next byte. */
3864 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3870 /* Add the opcode bytes in reverse order. */
3872 add_unwind_opcode (op
[count
], 1);
3874 demand_empty_rest_of_line ();
3878 /* Parse a .eabi_attribute directive. */
3881 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3883 s_vendor_attribute (OBJ_ATTR_PROC
);
3885 #endif /* OBJ_ELF */
3887 static void s_arm_arch (int);
3888 static void s_arm_object_arch (int);
3889 static void s_arm_cpu (int);
3890 static void s_arm_fpu (int);
3895 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3902 if (exp
.X_op
== O_symbol
)
3903 exp
.X_op
= O_secrel
;
3905 emit_expr (&exp
, 4);
3907 while (*input_line_pointer
++ == ',');
3909 input_line_pointer
--;
3910 demand_empty_rest_of_line ();
3914 /* This table describes all the machine specific pseudo-ops the assembler
3915 has to support. The fields are:
3916 pseudo-op name without dot
3917 function to call to execute this pseudo-op
3918 Integer arg to pass to the function. */
3920 const pseudo_typeS md_pseudo_table
[] =
3922 /* Never called because '.req' does not start a line. */
3923 { "req", s_req
, 0 },
3924 /* Following two are likewise never called. */
3927 { "unreq", s_unreq
, 0 },
3928 { "bss", s_bss
, 0 },
3929 { "align", s_align
, 0 },
3930 { "arm", s_arm
, 0 },
3931 { "thumb", s_thumb
, 0 },
3932 { "code", s_code
, 0 },
3933 { "force_thumb", s_force_thumb
, 0 },
3934 { "thumb_func", s_thumb_func
, 0 },
3935 { "thumb_set", s_thumb_set
, 0 },
3936 { "even", s_even
, 0 },
3937 { "ltorg", s_ltorg
, 0 },
3938 { "pool", s_ltorg
, 0 },
3939 { "syntax", s_syntax
, 0 },
3940 { "cpu", s_arm_cpu
, 0 },
3941 { "arch", s_arm_arch
, 0 },
3942 { "object_arch", s_arm_object_arch
, 0 },
3943 { "fpu", s_arm_fpu
, 0 },
3945 { "word", s_arm_elf_cons
, 4 },
3946 { "long", s_arm_elf_cons
, 4 },
3947 { "rel31", s_arm_rel31
, 0 },
3948 { "fnstart", s_arm_unwind_fnstart
, 0 },
3949 { "fnend", s_arm_unwind_fnend
, 0 },
3950 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3951 { "personality", s_arm_unwind_personality
, 0 },
3952 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3953 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3954 { "save", s_arm_unwind_save
, 0 },
3955 { "vsave", s_arm_unwind_save
, 1 },
3956 { "movsp", s_arm_unwind_movsp
, 0 },
3957 { "pad", s_arm_unwind_pad
, 0 },
3958 { "setfp", s_arm_unwind_setfp
, 0 },
3959 { "unwind_raw", s_arm_unwind_raw
, 0 },
3960 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3964 /* These are used for dwarf. */
3968 /* These are used for dwarf2. */
3969 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3970 { "loc", dwarf2_directive_loc
, 0 },
3971 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3973 { "extend", float_cons
, 'x' },
3974 { "ldouble", float_cons
, 'x' },
3975 { "packed", float_cons
, 'p' },
3977 {"secrel32", pe_directive_secrel
, 0},
3982 /* Parser functions used exclusively in instruction operands. */
3984 /* Generic immediate-value read function for use in insn parsing.
3985 STR points to the beginning of the immediate (the leading #);
3986 VAL receives the value; if the value is outside [MIN, MAX]
3987 issue an error. PREFIX_OPT is true if the immediate prefix is
3991 parse_immediate (char **str
, int *val
, int min
, int max
,
3992 bfd_boolean prefix_opt
)
3995 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3996 if (exp
.X_op
!= O_constant
)
3998 inst
.error
= _("constant expression required");
4002 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4004 inst
.error
= _("immediate value out of range");
4008 *val
= exp
.X_add_number
;
4012 /* Less-generic immediate-value read function with the possibility of loading a
4013 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4014 instructions. Puts the result directly in inst.operands[i]. */
4017 parse_big_immediate (char **str
, int i
)
4022 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4024 if (exp
.X_op
== O_constant
)
4026 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4027 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4028 O_constant. We have to be careful not to break compilation for
4029 32-bit X_add_number, though. */
4030 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4032 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4033 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4034 inst
.operands
[i
].regisimm
= 1;
4037 else if (exp
.X_op
== O_big
4038 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4039 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4041 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4042 /* Bignums have their least significant bits in
4043 generic_bignum[0]. Make sure we put 32 bits in imm and
4044 32 bits in reg, in a (hopefully) portable way. */
4045 assert (parts
!= 0);
4046 inst
.operands
[i
].imm
= 0;
4047 for (j
= 0; j
< parts
; j
++, idx
++)
4048 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4049 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4050 inst
.operands
[i
].reg
= 0;
4051 for (j
= 0; j
< parts
; j
++, idx
++)
4052 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4053 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4054 inst
.operands
[i
].regisimm
= 1;
4064 /* Returns the pseudo-register number of an FPA immediate constant,
4065 or FAIL if there isn't a valid constant here. */
4068 parse_fpa_immediate (char ** str
)
4070 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4076 /* First try and match exact strings, this is to guarantee
4077 that some formats will work even for cross assembly. */
4079 for (i
= 0; fp_const
[i
]; i
++)
4081 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4085 *str
+= strlen (fp_const
[i
]);
4086 if (is_end_of_line
[(unsigned char) **str
])
4092 /* Just because we didn't get a match doesn't mean that the constant
4093 isn't valid, just that it is in a format that we don't
4094 automatically recognize. Try parsing it with the standard
4095 expression routines. */
4097 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4099 /* Look for a raw floating point number. */
4100 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4101 && is_end_of_line
[(unsigned char) *save_in
])
4103 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4105 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4107 if (words
[j
] != fp_values
[i
][j
])
4111 if (j
== MAX_LITTLENUMS
)
4119 /* Try and parse a more complex expression, this will probably fail
4120 unless the code uses a floating point prefix (eg "0f"). */
4121 save_in
= input_line_pointer
;
4122 input_line_pointer
= *str
;
4123 if (expression (&exp
) == absolute_section
4124 && exp
.X_op
== O_big
4125 && exp
.X_add_number
< 0)
4127 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4129 if (gen_to_words (words
, 5, (long) 15) == 0)
4131 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4133 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4135 if (words
[j
] != fp_values
[i
][j
])
4139 if (j
== MAX_LITTLENUMS
)
4141 *str
= input_line_pointer
;
4142 input_line_pointer
= save_in
;
4149 *str
= input_line_pointer
;
4150 input_line_pointer
= save_in
;
4151 inst
.error
= _("invalid FPA immediate expression");
4155 /* Returns 1 if a number has "quarter-precision" float format
4156 0baBbbbbbc defgh000 00000000 00000000. */
4159 is_quarter_float (unsigned imm
)
4161 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4162 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4165 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4166 0baBbbbbbc defgh000 00000000 00000000.
4167 The zero and minus-zero cases need special handling, since they can't be
4168 encoded in the "quarter-precision" float format, but can nonetheless be
4169 loaded as integer constants. */
4172 parse_qfloat_immediate (char **ccp
, int *immed
)
4176 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4177 int found_fpchar
= 0;
4179 skip_past_char (&str
, '#');
4181 /* We must not accidentally parse an integer as a floating-point number. Make
4182 sure that the value we parse is not an integer by checking for special
4183 characters '.' or 'e'.
4184 FIXME: This is a horrible hack, but doing better is tricky because type
4185 information isn't in a very usable state at parse time. */
4187 skip_whitespace (fpnum
);
4189 if (strncmp (fpnum
, "0x", 2) == 0)
4193 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4194 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4204 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4206 unsigned fpword
= 0;
4209 /* Our FP word must be 32 bits (single-precision FP). */
4210 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4212 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4216 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4229 /* Shift operands. */
4232 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4235 struct asm_shift_name
4238 enum shift_kind kind
;
4241 /* Third argument to parse_shift. */
4242 enum parse_shift_mode
4244 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4245 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4246 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4247 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4248 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4251 /* Parse a <shift> specifier on an ARM data processing instruction.
4252 This has three forms:
4254 (LSL|LSR|ASL|ASR|ROR) Rs
4255 (LSL|LSR|ASL|ASR|ROR) #imm
4258 Note that ASL is assimilated to LSL in the instruction encoding, and
4259 RRX to ROR #0 (which cannot be written as such). */
4262 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4264 const struct asm_shift_name
*shift_name
;
4265 enum shift_kind shift
;
4270 for (p
= *str
; ISALPHA (*p
); p
++)
4275 inst
.error
= _("shift expression expected");
4279 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4281 if (shift_name
== NULL
)
4283 inst
.error
= _("shift expression expected");
4287 shift
= shift_name
->kind
;
4291 case NO_SHIFT_RESTRICT
:
4292 case SHIFT_IMMEDIATE
: break;
4294 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4295 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4297 inst
.error
= _("'LSL' or 'ASR' required");
4302 case SHIFT_LSL_IMMEDIATE
:
4303 if (shift
!= SHIFT_LSL
)
4305 inst
.error
= _("'LSL' required");
4310 case SHIFT_ASR_IMMEDIATE
:
4311 if (shift
!= SHIFT_ASR
)
4313 inst
.error
= _("'ASR' required");
4321 if (shift
!= SHIFT_RRX
)
4323 /* Whitespace can appear here if the next thing is a bare digit. */
4324 skip_whitespace (p
);
4326 if (mode
== NO_SHIFT_RESTRICT
4327 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4329 inst
.operands
[i
].imm
= reg
;
4330 inst
.operands
[i
].immisreg
= 1;
4332 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4335 inst
.operands
[i
].shift_kind
= shift
;
4336 inst
.operands
[i
].shifted
= 1;
4341 /* Parse a <shifter_operand> for an ARM data processing instruction:
4344 #<immediate>, <rotate>
4348 where <shift> is defined by parse_shift above, and <rotate> is a
4349 multiple of 2 between 0 and 30. Validation of immediate operands
4350 is deferred to md_apply_fix. */
4353 parse_shifter_operand (char **str
, int i
)
4358 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4360 inst
.operands
[i
].reg
= value
;
4361 inst
.operands
[i
].isreg
= 1;
4363 /* parse_shift will override this if appropriate */
4364 inst
.reloc
.exp
.X_op
= O_constant
;
4365 inst
.reloc
.exp
.X_add_number
= 0;
4367 if (skip_past_comma (str
) == FAIL
)
4370 /* Shift operation on register. */
4371 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4374 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4377 if (skip_past_comma (str
) == SUCCESS
)
4379 /* #x, y -- ie explicit rotation by Y. */
4380 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4383 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4385 inst
.error
= _("constant expression expected");
4389 value
= expr
.X_add_number
;
4390 if (value
< 0 || value
> 30 || value
% 2 != 0)
4392 inst
.error
= _("invalid rotation");
4395 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4397 inst
.error
= _("invalid constant");
4401 /* Convert to decoded value. md_apply_fix will put it back. */
4402 inst
.reloc
.exp
.X_add_number
4403 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4404 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4407 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4408 inst
.reloc
.pc_rel
= 0;
4412 /* Group relocation information. Each entry in the table contains the
4413 textual name of the relocation as may appear in assembler source
4414 and must end with a colon.
4415 Along with this textual name are the relocation codes to be used if
4416 the corresponding instruction is an ALU instruction (ADD or SUB only),
4417 an LDR, an LDRS, or an LDC. */
4419 struct group_reloc_table_entry
4430 /* Varieties of non-ALU group relocation. */
4437 static struct group_reloc_table_entry group_reloc_table
[] =
4438 { /* Program counter relative: */
4440 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4445 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4446 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4447 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4448 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4450 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4455 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4456 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4457 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4458 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4460 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4461 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4462 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4463 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4464 /* Section base relative */
4466 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4471 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4472 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4473 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4474 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4476 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4481 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4482 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4483 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4484 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4486 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4487 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4488 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4489 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4491 /* Given the address of a pointer pointing to the textual name of a group
4492 relocation as may appear in assembler source, attempt to find its details
4493 in group_reloc_table. The pointer will be updated to the character after
4494 the trailing colon. On failure, FAIL will be returned; SUCCESS
4495 otherwise. On success, *entry will be updated to point at the relevant
4496 group_reloc_table entry. */
4499 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4502 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4504 int length
= strlen (group_reloc_table
[i
].name
);
4506 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4507 && (*str
)[length
] == ':')
4509 *out
= &group_reloc_table
[i
];
4510 *str
+= (length
+ 1);
4518 /* Parse a <shifter_operand> for an ARM data processing instruction
4519 (as for parse_shifter_operand) where group relocations are allowed:
4522 #<immediate>, <rotate>
4523 #:<group_reloc>:<expression>
4527 where <group_reloc> is one of the strings defined in group_reloc_table.
4528 The hashes are optional.
4530 Everything else is as for parse_shifter_operand. */
4532 static parse_operand_result
4533 parse_shifter_operand_group_reloc (char **str
, int i
)
4535 /* Determine if we have the sequence of characters #: or just :
4536 coming next. If we do, then we check for a group relocation.
4537 If we don't, punt the whole lot to parse_shifter_operand. */
4539 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4540 || (*str
)[0] == ':')
4542 struct group_reloc_table_entry
*entry
;
4544 if ((*str
)[0] == '#')
4549 /* Try to parse a group relocation. Anything else is an error. */
4550 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4552 inst
.error
= _("unknown group relocation");
4553 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4556 /* We now have the group relocation table entry corresponding to
4557 the name in the assembler source. Next, we parse the expression. */
4558 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4559 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4561 /* Record the relocation type (always the ALU variant here). */
4562 inst
.reloc
.type
= entry
->alu_code
;
4563 assert (inst
.reloc
.type
!= 0);
4565 return PARSE_OPERAND_SUCCESS
;
4568 return parse_shifter_operand (str
, i
) == SUCCESS
4569 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4571 /* Never reached. */
4574 /* Parse all forms of an ARM address expression. Information is written
4575 to inst.operands[i] and/or inst.reloc.
4577 Preindexed addressing (.preind=1):
4579 [Rn, #offset] .reg=Rn .reloc.exp=offset
4580 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4581 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4582 .shift_kind=shift .reloc.exp=shift_imm
4584 These three may have a trailing ! which causes .writeback to be set also.
4586 Postindexed addressing (.postind=1, .writeback=1):
4588 [Rn], #offset .reg=Rn .reloc.exp=offset
4589 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4590 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4591 .shift_kind=shift .reloc.exp=shift_imm
4593 Unindexed addressing (.preind=0, .postind=0):
4595 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4599 [Rn]{!} shorthand for [Rn,#0]{!}
4600 =immediate .isreg=0 .reloc.exp=immediate
4601 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4603 It is the caller's responsibility to check for addressing modes not
4604 supported by the instruction, and to set inst.reloc.type. */
4606 static parse_operand_result
4607 parse_address_main (char **str
, int i
, int group_relocations
,
4608 group_reloc_type group_type
)
4613 if (skip_past_char (&p
, '[') == FAIL
)
4615 if (skip_past_char (&p
, '=') == FAIL
)
4617 /* bare address - translate to PC-relative offset */
4618 inst
.reloc
.pc_rel
= 1;
4619 inst
.operands
[i
].reg
= REG_PC
;
4620 inst
.operands
[i
].isreg
= 1;
4621 inst
.operands
[i
].preind
= 1;
4623 /* else a load-constant pseudo op, no special treatment needed here */
4625 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4626 return PARSE_OPERAND_FAIL
;
4629 return PARSE_OPERAND_SUCCESS
;
4632 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4634 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4635 return PARSE_OPERAND_FAIL
;
4637 inst
.operands
[i
].reg
= reg
;
4638 inst
.operands
[i
].isreg
= 1;
4640 if (skip_past_comma (&p
) == SUCCESS
)
4642 inst
.operands
[i
].preind
= 1;
4645 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4647 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4649 inst
.operands
[i
].imm
= reg
;
4650 inst
.operands
[i
].immisreg
= 1;
4652 if (skip_past_comma (&p
) == SUCCESS
)
4653 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4654 return PARSE_OPERAND_FAIL
;
4656 else if (skip_past_char (&p
, ':') == SUCCESS
)
4658 /* FIXME: '@' should be used here, but it's filtered out by generic
4659 code before we get to see it here. This may be subject to
4662 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4663 if (exp
.X_op
!= O_constant
)
4665 inst
.error
= _("alignment must be constant");
4666 return PARSE_OPERAND_FAIL
;
4668 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4669 inst
.operands
[i
].immisalign
= 1;
4670 /* Alignments are not pre-indexes. */
4671 inst
.operands
[i
].preind
= 0;
4675 if (inst
.operands
[i
].negative
)
4677 inst
.operands
[i
].negative
= 0;
4681 if (group_relocations
4682 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4684 struct group_reloc_table_entry
*entry
;
4686 /* Skip over the #: or : sequence. */
4692 /* Try to parse a group relocation. Anything else is an
4694 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4696 inst
.error
= _("unknown group relocation");
4697 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4700 /* We now have the group relocation table entry corresponding to
4701 the name in the assembler source. Next, we parse the
4703 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4704 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4706 /* Record the relocation type. */
4710 inst
.reloc
.type
= entry
->ldr_code
;
4714 inst
.reloc
.type
= entry
->ldrs_code
;
4718 inst
.reloc
.type
= entry
->ldc_code
;
4725 if (inst
.reloc
.type
== 0)
4727 inst
.error
= _("this group relocation is not allowed on this instruction");
4728 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4732 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4733 return PARSE_OPERAND_FAIL
;
4737 if (skip_past_char (&p
, ']') == FAIL
)
4739 inst
.error
= _("']' expected");
4740 return PARSE_OPERAND_FAIL
;
4743 if (skip_past_char (&p
, '!') == SUCCESS
)
4744 inst
.operands
[i
].writeback
= 1;
4746 else if (skip_past_comma (&p
) == SUCCESS
)
4748 if (skip_past_char (&p
, '{') == SUCCESS
)
4750 /* [Rn], {expr} - unindexed, with option */
4751 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4752 0, 255, TRUE
) == FAIL
)
4753 return PARSE_OPERAND_FAIL
;
4755 if (skip_past_char (&p
, '}') == FAIL
)
4757 inst
.error
= _("'}' expected at end of 'option' field");
4758 return PARSE_OPERAND_FAIL
;
4760 if (inst
.operands
[i
].preind
)
4762 inst
.error
= _("cannot combine index with option");
4763 return PARSE_OPERAND_FAIL
;
4766 return PARSE_OPERAND_SUCCESS
;
4770 inst
.operands
[i
].postind
= 1;
4771 inst
.operands
[i
].writeback
= 1;
4773 if (inst
.operands
[i
].preind
)
4775 inst
.error
= _("cannot combine pre- and post-indexing");
4776 return PARSE_OPERAND_FAIL
;
4780 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4782 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4784 /* We might be using the immediate for alignment already. If we
4785 are, OR the register number into the low-order bits. */
4786 if (inst
.operands
[i
].immisalign
)
4787 inst
.operands
[i
].imm
|= reg
;
4789 inst
.operands
[i
].imm
= reg
;
4790 inst
.operands
[i
].immisreg
= 1;
4792 if (skip_past_comma (&p
) == SUCCESS
)
4793 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4794 return PARSE_OPERAND_FAIL
;
4798 if (inst
.operands
[i
].negative
)
4800 inst
.operands
[i
].negative
= 0;
4803 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4804 return PARSE_OPERAND_FAIL
;
4809 /* If at this point neither .preind nor .postind is set, we have a
4810 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4811 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4813 inst
.operands
[i
].preind
= 1;
4814 inst
.reloc
.exp
.X_op
= O_constant
;
4815 inst
.reloc
.exp
.X_add_number
= 0;
4818 return PARSE_OPERAND_SUCCESS
;
4822 parse_address (char **str
, int i
)
4824 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4828 static parse_operand_result
4829 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4831 return parse_address_main (str
, i
, 1, type
);
4834 /* Parse an operand for a MOVW or MOVT instruction. */
4836 parse_half (char **str
)
4841 skip_past_char (&p
, '#');
4842 if (strncasecmp (p
, ":lower16:", 9) == 0)
4843 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4844 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4845 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4847 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4850 skip_whitespace (p
);
4853 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4856 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4858 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4860 inst
.error
= _("constant expression expected");
4863 if (inst
.reloc
.exp
.X_add_number
< 0
4864 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4866 inst
.error
= _("immediate value out of range");
4874 /* Miscellaneous. */
4876 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4877 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4879 parse_psr (char **str
)
4882 unsigned long psr_field
;
4883 const struct asm_psr
*psr
;
4886 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4887 feature for ease of use and backwards compatibility. */
4889 if (strncasecmp (p
, "SPSR", 4) == 0)
4890 psr_field
= SPSR_BIT
;
4891 else if (strncasecmp (p
, "CPSR", 4) == 0)
4898 while (ISALNUM (*p
) || *p
== '_');
4900 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4911 /* A suffix follows. */
4917 while (ISALNUM (*p
) || *p
== '_');
4919 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4923 psr_field
|= psr
->field
;
4928 goto error
; /* Garbage after "[CS]PSR". */
4930 psr_field
|= (PSR_c
| PSR_f
);
4936 inst
.error
= _("flag for {c}psr instruction expected");
4940 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4941 value suitable for splatting into the AIF field of the instruction. */
4944 parse_cps_flags (char **str
)
4953 case '\0': case ',':
4956 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4957 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4958 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4961 inst
.error
= _("unrecognized CPS flag");
4966 if (saw_a_flag
== 0)
4968 inst
.error
= _("missing CPS flags");
4976 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4977 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4980 parse_endian_specifier (char **str
)
4985 if (strncasecmp (s
, "BE", 2))
4987 else if (strncasecmp (s
, "LE", 2))
4991 inst
.error
= _("valid endian specifiers are be or le");
4995 if (ISALNUM (s
[2]) || s
[2] == '_')
4997 inst
.error
= _("valid endian specifiers are be or le");
5002 return little_endian
;
5005 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5006 value suitable for poking into the rotate field of an sxt or sxta
5007 instruction, or FAIL on error. */
5010 parse_ror (char **str
)
5015 if (strncasecmp (s
, "ROR", 3) == 0)
5019 inst
.error
= _("missing rotation field after comma");
5023 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5028 case 0: *str
= s
; return 0x0;
5029 case 8: *str
= s
; return 0x1;
5030 case 16: *str
= s
; return 0x2;
5031 case 24: *str
= s
; return 0x3;
5034 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5039 /* Parse a conditional code (from conds[] below). The value returned is in the
5040 range 0 .. 14, or FAIL. */
5042 parse_cond (char **str
)
5045 const struct asm_cond
*c
;
5048 while (ISALPHA (*q
))
5051 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
5054 inst
.error
= _("condition required");
5062 /* Parse an option for a barrier instruction. Returns the encoding for the
5065 parse_barrier (char **str
)
5068 const struct asm_barrier_opt
*o
;
5071 while (ISALPHA (*q
))
5074 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5082 /* Parse the operands of a table branch instruction. Similar to a memory
5085 parse_tb (char **str
)
5090 if (skip_past_char (&p
, '[') == FAIL
)
5092 inst
.error
= _("'[' expected");
5096 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5098 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5101 inst
.operands
[0].reg
= reg
;
5103 if (skip_past_comma (&p
) == FAIL
)
5105 inst
.error
= _("',' expected");
5109 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5111 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5114 inst
.operands
[0].imm
= reg
;
5116 if (skip_past_comma (&p
) == SUCCESS
)
5118 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5120 if (inst
.reloc
.exp
.X_add_number
!= 1)
5122 inst
.error
= _("invalid shift");
5125 inst
.operands
[0].shifted
= 1;
5128 if (skip_past_char (&p
, ']') == FAIL
)
5130 inst
.error
= _("']' expected");
5137 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5138 information on the types the operands can take and how they are encoded.
5139 Up to four operands may be read; this function handles setting the
5140 ".present" field for each read operand itself.
5141 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5142 else returns FAIL. */
5145 parse_neon_mov (char **str
, int *which_operand
)
5147 int i
= *which_operand
, val
;
5148 enum arm_reg_type rtype
;
5150 struct neon_type_el optype
;
5152 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5154 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5155 inst
.operands
[i
].reg
= val
;
5156 inst
.operands
[i
].isscalar
= 1;
5157 inst
.operands
[i
].vectype
= optype
;
5158 inst
.operands
[i
++].present
= 1;
5160 if (skip_past_comma (&ptr
) == FAIL
)
5163 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5166 inst
.operands
[i
].reg
= val
;
5167 inst
.operands
[i
].isreg
= 1;
5168 inst
.operands
[i
].present
= 1;
5170 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5173 /* Cases 0, 1, 2, 3, 5 (D only). */
5174 if (skip_past_comma (&ptr
) == FAIL
)
5177 inst
.operands
[i
].reg
= val
;
5178 inst
.operands
[i
].isreg
= 1;
5179 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5180 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5181 inst
.operands
[i
].isvec
= 1;
5182 inst
.operands
[i
].vectype
= optype
;
5183 inst
.operands
[i
++].present
= 1;
5185 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5187 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5188 Case 13: VMOV <Sd>, <Rm> */
5189 inst
.operands
[i
].reg
= val
;
5190 inst
.operands
[i
].isreg
= 1;
5191 inst
.operands
[i
].present
= 1;
5193 if (rtype
== REG_TYPE_NQ
)
5195 first_error (_("can't use Neon quad register here"));
5198 else if (rtype
!= REG_TYPE_VFS
)
5201 if (skip_past_comma (&ptr
) == FAIL
)
5203 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5205 inst
.operands
[i
].reg
= val
;
5206 inst
.operands
[i
].isreg
= 1;
5207 inst
.operands
[i
].present
= 1;
5210 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5211 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5212 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5213 Case 10: VMOV.F32 <Sd>, #<imm>
5214 Case 11: VMOV.F64 <Dd>, #<imm> */
5215 inst
.operands
[i
].immisfloat
= 1;
5216 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5217 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5218 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5220 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5223 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5224 Case 1: VMOV<c><q> <Dd>, <Dm>
5225 Case 8: VMOV.F32 <Sd>, <Sm>
5226 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5228 inst
.operands
[i
].reg
= val
;
5229 inst
.operands
[i
].isreg
= 1;
5230 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5231 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5232 inst
.operands
[i
].isvec
= 1;
5233 inst
.operands
[i
].vectype
= optype
;
5234 inst
.operands
[i
].present
= 1;
5236 if (skip_past_comma (&ptr
) == SUCCESS
)
5241 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5244 inst
.operands
[i
].reg
= val
;
5245 inst
.operands
[i
].isreg
= 1;
5246 inst
.operands
[i
++].present
= 1;
5248 if (skip_past_comma (&ptr
) == FAIL
)
5251 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5254 inst
.operands
[i
].reg
= val
;
5255 inst
.operands
[i
].isreg
= 1;
5256 inst
.operands
[i
++].present
= 1;
5261 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5265 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5268 inst
.operands
[i
].reg
= val
;
5269 inst
.operands
[i
].isreg
= 1;
5270 inst
.operands
[i
++].present
= 1;
5272 if (skip_past_comma (&ptr
) == FAIL
)
5275 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5277 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5278 inst
.operands
[i
].reg
= val
;
5279 inst
.operands
[i
].isscalar
= 1;
5280 inst
.operands
[i
].present
= 1;
5281 inst
.operands
[i
].vectype
= optype
;
5283 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5285 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5286 inst
.operands
[i
].reg
= val
;
5287 inst
.operands
[i
].isreg
= 1;
5288 inst
.operands
[i
++].present
= 1;
5290 if (skip_past_comma (&ptr
) == FAIL
)
5293 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5296 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5300 inst
.operands
[i
].reg
= val
;
5301 inst
.operands
[i
].isreg
= 1;
5302 inst
.operands
[i
].isvec
= 1;
5303 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5304 inst
.operands
[i
].vectype
= optype
;
5305 inst
.operands
[i
].present
= 1;
5307 if (rtype
== REG_TYPE_VFS
)
5311 if (skip_past_comma (&ptr
) == FAIL
)
5313 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5316 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5319 inst
.operands
[i
].reg
= val
;
5320 inst
.operands
[i
].isreg
= 1;
5321 inst
.operands
[i
].isvec
= 1;
5322 inst
.operands
[i
].issingle
= 1;
5323 inst
.operands
[i
].vectype
= optype
;
5324 inst
.operands
[i
].present
= 1;
5327 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5331 inst
.operands
[i
].reg
= val
;
5332 inst
.operands
[i
].isreg
= 1;
5333 inst
.operands
[i
].isvec
= 1;
5334 inst
.operands
[i
].issingle
= 1;
5335 inst
.operands
[i
].vectype
= optype
;
5336 inst
.operands
[i
++].present
= 1;
5341 first_error (_("parse error"));
5345 /* Successfully parsed the operands. Update args. */
5351 first_error (_("expected comma"));
5355 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5359 /* Matcher codes for parse_operands. */
5360 enum operand_parse_code
5362 OP_stop
, /* end of line */
5364 OP_RR
, /* ARM register */
5365 OP_RRnpc
, /* ARM register, not r15 */
5366 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5367 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5368 OP_RCP
, /* Coprocessor number */
5369 OP_RCN
, /* Coprocessor register */
5370 OP_RF
, /* FPA register */
5371 OP_RVS
, /* VFP single precision register */
5372 OP_RVD
, /* VFP double precision register (0..15) */
5373 OP_RND
, /* Neon double precision register (0..31) */
5374 OP_RNQ
, /* Neon quad precision register */
5375 OP_RVSD
, /* VFP single or double precision register */
5376 OP_RNDQ
, /* Neon double or quad precision register */
5377 OP_RNSDQ
, /* Neon single, double or quad precision register */
5378 OP_RNSC
, /* Neon scalar D[X] */
5379 OP_RVC
, /* VFP control register */
5380 OP_RMF
, /* Maverick F register */
5381 OP_RMD
, /* Maverick D register */
5382 OP_RMFX
, /* Maverick FX register */
5383 OP_RMDX
, /* Maverick DX register */
5384 OP_RMAX
, /* Maverick AX register */
5385 OP_RMDS
, /* Maverick DSPSC register */
5386 OP_RIWR
, /* iWMMXt wR register */
5387 OP_RIWC
, /* iWMMXt wC register */
5388 OP_RIWG
, /* iWMMXt wCG register */
5389 OP_RXA
, /* XScale accumulator register */
5391 OP_REGLST
, /* ARM register list */
5392 OP_VRSLST
, /* VFP single-precision register list */
5393 OP_VRDLST
, /* VFP double-precision register list */
5394 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5395 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5396 OP_NSTRLST
, /* Neon element/structure list */
5398 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5399 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5400 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5401 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5402 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5403 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5404 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5405 OP_VMOV
, /* Neon VMOV operands. */
5406 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5407 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5408 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5410 OP_I0
, /* immediate zero */
5411 OP_I7
, /* immediate value 0 .. 7 */
5412 OP_I15
, /* 0 .. 15 */
5413 OP_I16
, /* 1 .. 16 */
5414 OP_I16z
, /* 0 .. 16 */
5415 OP_I31
, /* 0 .. 31 */
5416 OP_I31w
, /* 0 .. 31, optional trailing ! */
5417 OP_I32
, /* 1 .. 32 */
5418 OP_I32z
, /* 0 .. 32 */
5419 OP_I63
, /* 0 .. 63 */
5420 OP_I63s
, /* -64 .. 63 */
5421 OP_I64
, /* 1 .. 64 */
5422 OP_I64z
, /* 0 .. 64 */
5423 OP_I255
, /* 0 .. 255 */
5425 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5426 OP_I7b
, /* 0 .. 7 */
5427 OP_I15b
, /* 0 .. 15 */
5428 OP_I31b
, /* 0 .. 31 */
5430 OP_SH
, /* shifter operand */
5431 OP_SHG
, /* shifter operand with possible group relocation */
5432 OP_ADDR
, /* Memory address expression (any mode) */
5433 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5434 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5435 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5436 OP_EXP
, /* arbitrary expression */
5437 OP_EXPi
, /* same, with optional immediate prefix */
5438 OP_EXPr
, /* same, with optional relocation suffix */
5439 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5441 OP_CPSF
, /* CPS flags */
5442 OP_ENDI
, /* Endianness specifier */
5443 OP_PSR
, /* CPSR/SPSR mask for msr */
5444 OP_COND
, /* conditional code */
5445 OP_TB
, /* Table branch. */
5447 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5448 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5450 OP_RRnpc_I0
, /* ARM register or literal 0 */
5451 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5452 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5453 OP_RF_IF
, /* FPA register or immediate */
5454 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5455 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5457 /* Optional operands. */
5458 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5459 OP_oI31b
, /* 0 .. 31 */
5460 OP_oI32b
, /* 1 .. 32 */
5461 OP_oIffffb
, /* 0 .. 65535 */
5462 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5464 OP_oRR
, /* ARM register */
5465 OP_oRRnpc
, /* ARM register, not the PC */
5466 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5467 OP_oRND
, /* Optional Neon double precision register */
5468 OP_oRNQ
, /* Optional Neon quad precision register */
5469 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5470 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5471 OP_oSHll
, /* LSL immediate */
5472 OP_oSHar
, /* ASR immediate */
5473 OP_oSHllar
, /* LSL or ASR immediate */
5474 OP_oROR
, /* ROR 0/8/16/24 */
5475 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5477 OP_FIRST_OPTIONAL
= OP_oI7b
5480 /* Generic instruction operand parser. This does no encoding and no
5481 semantic validation; it merely squirrels values away in the inst
5482 structure. Returns SUCCESS or FAIL depending on whether the
5483 specified grammar matched. */
5485 parse_operands (char *str
, const unsigned char *pattern
)
5487 unsigned const char *upat
= pattern
;
5488 char *backtrack_pos
= 0;
5489 const char *backtrack_error
= 0;
5490 int i
, val
, backtrack_index
= 0;
5491 enum arm_reg_type rtype
;
5492 parse_operand_result result
;
5494 #define po_char_or_fail(chr) do { \
5495 if (skip_past_char (&str, chr) == FAIL) \
5499 #define po_reg_or_fail(regtype) do { \
5500 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5501 &inst.operands[i].vectype); \
5504 first_error (_(reg_expected_msgs[regtype])); \
5507 inst.operands[i].reg = val; \
5508 inst.operands[i].isreg = 1; \
5509 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5510 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5511 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5512 || rtype == REG_TYPE_VFD \
5513 || rtype == REG_TYPE_NQ); \
5516 #define po_reg_or_goto(regtype, label) do { \
5517 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5518 &inst.operands[i].vectype); \
5522 inst.operands[i].reg = val; \
5523 inst.operands[i].isreg = 1; \
5524 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5525 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5526 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5527 || rtype == REG_TYPE_VFD \
5528 || rtype == REG_TYPE_NQ); \
5531 #define po_imm_or_fail(min, max, popt) do { \
5532 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5534 inst.operands[i].imm = val; \
5537 #define po_scalar_or_goto(elsz, label) do { \
5538 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5541 inst.operands[i].reg = val; \
5542 inst.operands[i].isscalar = 1; \
5545 #define po_misc_or_fail(expr) do { \
5550 #define po_misc_or_fail_no_backtrack(expr) do { \
5552 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5553 backtrack_pos = 0; \
5554 if (result != PARSE_OPERAND_SUCCESS) \
5558 skip_whitespace (str
);
5560 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5562 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5564 /* Remember where we are in case we need to backtrack. */
5565 assert (!backtrack_pos
);
5566 backtrack_pos
= str
;
5567 backtrack_error
= inst
.error
;
5568 backtrack_index
= i
;
5571 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5572 po_char_or_fail (',');
5580 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5581 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5582 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5583 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5584 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5585 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5587 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5589 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5591 /* Also accept generic coprocessor regs for unknown registers. */
5593 po_reg_or_fail (REG_TYPE_CN
);
5595 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5596 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5597 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5598 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5599 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5600 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5601 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5602 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5603 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5604 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5606 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5608 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5609 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5611 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5613 /* Neon scalar. Using an element size of 8 means that some invalid
5614 scalars are accepted here, so deal with those in later code. */
5615 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5617 /* WARNING: We can expand to two operands here. This has the potential
5618 to totally confuse the backtracking mechanism! It will be OK at
5619 least as long as we don't try to use optional args as well,
5623 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5624 inst
.operands
[i
].present
= 1;
5626 skip_past_comma (&str
);
5627 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5630 /* Optional register operand was omitted. Unfortunately, it's in
5631 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5632 here (this is a bit grotty). */
5633 inst
.operands
[i
] = inst
.operands
[i
-1];
5634 inst
.operands
[i
-1].present
= 0;
5637 /* There's a possibility of getting a 64-bit immediate here, so
5638 we need special handling. */
5639 if (parse_big_immediate (&str
, i
) == FAIL
)
5641 inst
.error
= _("immediate value is out of range");
5649 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5652 po_imm_or_fail (0, 0, TRUE
);
5657 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5662 po_scalar_or_goto (8, try_rr
);
5665 po_reg_or_fail (REG_TYPE_RN
);
5671 po_scalar_or_goto (8, try_nsdq
);
5674 po_reg_or_fail (REG_TYPE_NSDQ
);
5680 po_scalar_or_goto (8, try_ndq
);
5683 po_reg_or_fail (REG_TYPE_NDQ
);
5689 po_scalar_or_goto (8, try_vfd
);
5692 po_reg_or_fail (REG_TYPE_VFD
);
5697 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5698 not careful then bad things might happen. */
5699 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5704 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5707 /* There's a possibility of getting a 64-bit immediate here, so
5708 we need special handling. */
5709 if (parse_big_immediate (&str
, i
) == FAIL
)
5711 inst
.error
= _("immediate value is out of range");
5719 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5722 po_imm_or_fail (0, 63, TRUE
);
5727 po_char_or_fail ('[');
5728 po_reg_or_fail (REG_TYPE_RN
);
5729 po_char_or_fail (']');
5734 po_reg_or_fail (REG_TYPE_RN
);
5735 if (skip_past_char (&str
, '!') == SUCCESS
)
5736 inst
.operands
[i
].writeback
= 1;
5740 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5741 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5742 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5743 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5744 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5745 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5746 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5747 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5748 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5749 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5750 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5751 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5753 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5755 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5756 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5758 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5759 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5760 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5762 /* Immediate variants */
5764 po_char_or_fail ('{');
5765 po_imm_or_fail (0, 255, TRUE
);
5766 po_char_or_fail ('}');
5770 /* The expression parser chokes on a trailing !, so we have
5771 to find it first and zap it. */
5774 while (*s
&& *s
!= ',')
5779 inst
.operands
[i
].writeback
= 1;
5781 po_imm_or_fail (0, 31, TRUE
);
5789 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5794 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5799 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5801 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5803 val
= parse_reloc (&str
);
5806 inst
.error
= _("unrecognized relocation suffix");
5809 else if (val
!= BFD_RELOC_UNUSED
)
5811 inst
.operands
[i
].imm
= val
;
5812 inst
.operands
[i
].hasreloc
= 1;
5817 /* Operand for MOVW or MOVT. */
5819 po_misc_or_fail (parse_half (&str
));
5822 /* Register or expression */
5823 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5824 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5826 /* Register or immediate */
5827 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5828 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5830 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5832 if (!is_immediate_prefix (*str
))
5835 val
= parse_fpa_immediate (&str
);
5838 /* FPA immediates are encoded as registers 8-15.
5839 parse_fpa_immediate has already applied the offset. */
5840 inst
.operands
[i
].reg
= val
;
5841 inst
.operands
[i
].isreg
= 1;
5844 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5845 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5847 /* Two kinds of register */
5850 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5852 || (rege
->type
!= REG_TYPE_MMXWR
5853 && rege
->type
!= REG_TYPE_MMXWC
5854 && rege
->type
!= REG_TYPE_MMXWCG
))
5856 inst
.error
= _("iWMMXt data or control register expected");
5859 inst
.operands
[i
].reg
= rege
->number
;
5860 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5866 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5868 || (rege
->type
!= REG_TYPE_MMXWC
5869 && rege
->type
!= REG_TYPE_MMXWCG
))
5871 inst
.error
= _("iWMMXt control register expected");
5874 inst
.operands
[i
].reg
= rege
->number
;
5875 inst
.operands
[i
].isreg
= 1;
5880 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5881 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5882 case OP_oROR
: val
= parse_ror (&str
); break;
5883 case OP_PSR
: val
= parse_psr (&str
); break;
5884 case OP_COND
: val
= parse_cond (&str
); break;
5885 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5888 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5889 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5892 val
= parse_psr (&str
);
5896 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5899 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5901 if (strncasecmp (str
, "APSR_", 5) == 0)
5908 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5909 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5910 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5911 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5912 default: found
= 16;
5916 inst
.operands
[i
].isvec
= 1;
5923 po_misc_or_fail (parse_tb (&str
));
5926 /* Register lists */
5928 val
= parse_reg_list (&str
);
5931 inst
.operands
[1].writeback
= 1;
5937 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5941 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5945 /* Allow Q registers too. */
5946 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5951 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5953 inst
.operands
[i
].issingle
= 1;
5958 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5963 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5964 &inst
.operands
[i
].vectype
);
5967 /* Addressing modes */
5969 po_misc_or_fail (parse_address (&str
, i
));
5973 po_misc_or_fail_no_backtrack (
5974 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5978 po_misc_or_fail_no_backtrack (
5979 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5983 po_misc_or_fail_no_backtrack (
5984 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5988 po_misc_or_fail (parse_shifter_operand (&str
, i
));
5992 po_misc_or_fail_no_backtrack (
5993 parse_shifter_operand_group_reloc (&str
, i
));
5997 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6001 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6005 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6009 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6012 /* Various value-based sanity checks and shared operations. We
6013 do not signal immediate failures for the register constraints;
6014 this allows a syntax error to take precedence. */
6023 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6024 inst
.error
= BAD_PC
;
6042 inst
.operands
[i
].imm
= val
;
6049 /* If we get here, this operand was successfully parsed. */
6050 inst
.operands
[i
].present
= 1;
6054 inst
.error
= BAD_ARGS
;
6059 /* The parse routine should already have set inst.error, but set a
6060 default here just in case. */
6062 inst
.error
= _("syntax error");
6066 /* Do not backtrack over a trailing optional argument that
6067 absorbed some text. We will only fail again, with the
6068 'garbage following instruction' error message, which is
6069 probably less helpful than the current one. */
6070 if (backtrack_index
== i
&& backtrack_pos
!= str
6071 && upat
[i
+1] == OP_stop
)
6074 inst
.error
= _("syntax error");
6078 /* Try again, skipping the optional argument at backtrack_pos. */
6079 str
= backtrack_pos
;
6080 inst
.error
= backtrack_error
;
6081 inst
.operands
[backtrack_index
].present
= 0;
6082 i
= backtrack_index
;
6086 /* Check that we have parsed all the arguments. */
6087 if (*str
!= '\0' && !inst
.error
)
6088 inst
.error
= _("garbage following instruction");
6090 return inst
.error
? FAIL
: SUCCESS
;
6093 #undef po_char_or_fail
6094 #undef po_reg_or_fail
6095 #undef po_reg_or_goto
6096 #undef po_imm_or_fail
6097 #undef po_scalar_or_fail
6099 /* Shorthand macro for instruction encoding functions issuing errors. */
6100 #define constraint(expr, err) do { \
6108 /* Functions for operand encoding. ARM, then Thumb. */
6110 #define rotate_left(v, n) (v << n | v >> (32 - n))
6112 /* If VAL can be encoded in the immediate field of an ARM instruction,
6113 return the encoded form. Otherwise, return FAIL. */
6116 encode_arm_immediate (unsigned int val
)
6120 for (i
= 0; i
< 32; i
+= 2)
6121 if ((a
= rotate_left (val
, i
)) <= 0xff)
6122 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6127 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6128 return the encoded form. Otherwise, return FAIL. */
6130 encode_thumb32_immediate (unsigned int val
)
6137 for (i
= 1; i
<= 24; i
++)
6140 if ((val
& ~(0xff << i
)) == 0)
6141 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6145 if (val
== ((a
<< 16) | a
))
6147 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6151 if (val
== ((a
<< 16) | a
))
6152 return 0x200 | (a
>> 8);
6156 /* Encode a VFP SP or DP register number into inst.instruction. */
6159 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6161 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6164 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6167 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6170 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6175 first_error (_("D register out of range for selected VFP version"));
6183 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6187 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6191 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6195 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6199 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6203 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6211 /* Encode a <shift> in an ARM-format instruction. The immediate,
6212 if any, is handled by md_apply_fix. */
6214 encode_arm_shift (int i
)
6216 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6217 inst
.instruction
|= SHIFT_ROR
<< 5;
6220 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6221 if (inst
.operands
[i
].immisreg
)
6223 inst
.instruction
|= SHIFT_BY_REG
;
6224 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6227 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6232 encode_arm_shifter_operand (int i
)
6234 if (inst
.operands
[i
].isreg
)
6236 inst
.instruction
|= inst
.operands
[i
].reg
;
6237 encode_arm_shift (i
);
6240 inst
.instruction
|= INST_IMMEDIATE
;
6243 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6245 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6247 assert (inst
.operands
[i
].isreg
);
6248 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6250 if (inst
.operands
[i
].preind
)
6254 inst
.error
= _("instruction does not accept preindexed addressing");
6257 inst
.instruction
|= PRE_INDEX
;
6258 if (inst
.operands
[i
].writeback
)
6259 inst
.instruction
|= WRITE_BACK
;
6262 else if (inst
.operands
[i
].postind
)
6264 assert (inst
.operands
[i
].writeback
);
6266 inst
.instruction
|= WRITE_BACK
;
6268 else /* unindexed - only for coprocessor */
6270 inst
.error
= _("instruction does not accept unindexed addressing");
6274 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6275 && (((inst
.instruction
& 0x000f0000) >> 16)
6276 == ((inst
.instruction
& 0x0000f000) >> 12)))
6277 as_warn ((inst
.instruction
& LOAD_BIT
)
6278 ? _("destination register same as write-back base")
6279 : _("source register same as write-back base"));
6282 /* inst.operands[i] was set up by parse_address. Encode it into an
6283 ARM-format mode 2 load or store instruction. If is_t is true,
6284 reject forms that cannot be used with a T instruction (i.e. not
6287 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6289 encode_arm_addr_mode_common (i
, is_t
);
6291 if (inst
.operands
[i
].immisreg
)
6293 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6294 inst
.instruction
|= inst
.operands
[i
].imm
;
6295 if (!inst
.operands
[i
].negative
)
6296 inst
.instruction
|= INDEX_UP
;
6297 if (inst
.operands
[i
].shifted
)
6299 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6300 inst
.instruction
|= SHIFT_ROR
<< 5;
6303 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6304 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6308 else /* immediate offset in inst.reloc */
6310 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6311 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6315 /* inst.operands[i] was set up by parse_address. Encode it into an
6316 ARM-format mode 3 load or store instruction. Reject forms that
6317 cannot be used with such instructions. If is_t is true, reject
6318 forms that cannot be used with a T instruction (i.e. not
6321 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6323 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6325 inst
.error
= _("instruction does not accept scaled register index");
6329 encode_arm_addr_mode_common (i
, is_t
);
6331 if (inst
.operands
[i
].immisreg
)
6333 inst
.instruction
|= inst
.operands
[i
].imm
;
6334 if (!inst
.operands
[i
].negative
)
6335 inst
.instruction
|= INDEX_UP
;
6337 else /* immediate offset in inst.reloc */
6339 inst
.instruction
|= HWOFFSET_IMM
;
6340 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6341 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6345 /* inst.operands[i] was set up by parse_address. Encode it into an
6346 ARM-format instruction. Reject all forms which cannot be encoded
6347 into a coprocessor load/store instruction. If wb_ok is false,
6348 reject use of writeback; if unind_ok is false, reject use of
6349 unindexed addressing. If reloc_override is not 0, use it instead
6350 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6351 (in which case it is preserved). */
6354 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6356 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6358 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6360 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6362 assert (!inst
.operands
[i
].writeback
);
6365 inst
.error
= _("instruction does not support unindexed addressing");
6368 inst
.instruction
|= inst
.operands
[i
].imm
;
6369 inst
.instruction
|= INDEX_UP
;
6373 if (inst
.operands
[i
].preind
)
6374 inst
.instruction
|= PRE_INDEX
;
6376 if (inst
.operands
[i
].writeback
)
6378 if (inst
.operands
[i
].reg
== REG_PC
)
6380 inst
.error
= _("pc may not be used with write-back");
6385 inst
.error
= _("instruction does not support writeback");
6388 inst
.instruction
|= WRITE_BACK
;
6392 inst
.reloc
.type
= reloc_override
;
6393 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6394 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6395 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6398 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6400 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6406 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6407 Determine whether it can be performed with a move instruction; if
6408 it can, convert inst.instruction to that move instruction and
6409 return 1; if it can't, convert inst.instruction to a literal-pool
6410 load and return 0. If this is not a valid thing to do in the
6411 current context, set inst.error and return 1.
6413 inst.operands[i] describes the destination register. */
6416 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6421 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6425 if ((inst
.instruction
& tbit
) == 0)
6427 inst
.error
= _("invalid pseudo operation");
6430 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6432 inst
.error
= _("constant expression expected");
6435 if (inst
.reloc
.exp
.X_op
== O_constant
)
6439 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6441 /* This can be done with a mov(1) instruction. */
6442 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6443 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6449 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6452 /* This can be done with a mov instruction. */
6453 inst
.instruction
&= LITERAL_MASK
;
6454 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6455 inst
.instruction
|= value
& 0xfff;
6459 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6462 /* This can be done with a mvn instruction. */
6463 inst
.instruction
&= LITERAL_MASK
;
6464 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6465 inst
.instruction
|= value
& 0xfff;
6471 if (add_to_lit_pool () == FAIL
)
6473 inst
.error
= _("literal pool insertion failed");
6476 inst
.operands
[1].reg
= REG_PC
;
6477 inst
.operands
[1].isreg
= 1;
6478 inst
.operands
[1].preind
= 1;
6479 inst
.reloc
.pc_rel
= 1;
6480 inst
.reloc
.type
= (thumb_p
6481 ? BFD_RELOC_ARM_THUMB_OFFSET
6483 ? BFD_RELOC_ARM_HWLITERAL
6484 : BFD_RELOC_ARM_LITERAL
));
6488 /* Functions for instruction encoding, sorted by sub-architecture.
6489 First some generics; their names are taken from the conventional
6490 bit positions for register arguments in ARM format instructions. */
6500 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6506 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6507 inst
.instruction
|= inst
.operands
[1].reg
;
6513 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6514 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6520 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6521 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6527 unsigned Rn
= inst
.operands
[2].reg
;
6528 /* Enforce restrictions on SWP instruction. */
6529 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6530 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6531 _("Rn must not overlap other operands"));
6532 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6533 inst
.instruction
|= inst
.operands
[1].reg
;
6534 inst
.instruction
|= Rn
<< 16;
6540 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6541 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6542 inst
.instruction
|= inst
.operands
[2].reg
;
6548 inst
.instruction
|= inst
.operands
[0].reg
;
6549 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6550 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6556 inst
.instruction
|= inst
.operands
[0].imm
;
6562 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6563 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6566 /* ARM instructions, in alphabetical order by function name (except
6567 that wrapper functions appear immediately after the function they
6570 /* This is a pseudo-op of the form "adr rd, label" to be converted
6571 into a relative address of the form "add rd, pc, #label-.-8". */
6576 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6578 /* Frag hacking will turn this into a sub instruction if the offset turns
6579 out to be negative. */
6580 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6581 inst
.reloc
.pc_rel
= 1;
6582 inst
.reloc
.exp
.X_add_number
-= 8;
6585 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6586 into a relative address of the form:
6587 add rd, pc, #low(label-.-8)"
6588 add rd, rd, #high(label-.-8)" */
6593 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6595 /* Frag hacking will turn this into a sub instruction if the offset turns
6596 out to be negative. */
6597 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6598 inst
.reloc
.pc_rel
= 1;
6599 inst
.size
= INSN_SIZE
* 2;
6600 inst
.reloc
.exp
.X_add_number
-= 8;
6606 if (!inst
.operands
[1].present
)
6607 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6608 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6609 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6610 encode_arm_shifter_operand (2);
6616 if (inst
.operands
[0].present
)
6618 constraint ((inst
.instruction
& 0xf0) != 0x40
6619 && inst
.operands
[0].imm
!= 0xf,
6620 _("bad barrier type"));
6621 inst
.instruction
|= inst
.operands
[0].imm
;
6624 inst
.instruction
|= 0xf;
6630 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6631 constraint (msb
> 32, _("bit-field extends past end of register"));
6632 /* The instruction encoding stores the LSB and MSB,
6633 not the LSB and width. */
6634 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6635 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6636 inst
.instruction
|= (msb
- 1) << 16;
6644 /* #0 in second position is alternative syntax for bfc, which is
6645 the same instruction but with REG_PC in the Rm field. */
6646 if (!inst
.operands
[1].isreg
)
6647 inst
.operands
[1].reg
= REG_PC
;
6649 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6650 constraint (msb
> 32, _("bit-field extends past end of register"));
6651 /* The instruction encoding stores the LSB and MSB,
6652 not the LSB and width. */
6653 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6654 inst
.instruction
|= inst
.operands
[1].reg
;
6655 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6656 inst
.instruction
|= (msb
- 1) << 16;
6662 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6663 _("bit-field extends past end of register"));
6664 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6665 inst
.instruction
|= inst
.operands
[1].reg
;
6666 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6667 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6670 /* ARM V5 breakpoint instruction (argument parse)
6671 BKPT <16 bit unsigned immediate>
6672 Instruction is not conditional.
6673 The bit pattern given in insns[] has the COND_ALWAYS condition,
6674 and it is an error if the caller tried to override that. */
6679 /* Top 12 of 16 bits to bits 19:8. */
6680 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6682 /* Bottom 4 of 16 bits to bits 3:0. */
6683 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6687 encode_branch (int default_reloc
)
6689 if (inst
.operands
[0].hasreloc
)
6691 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6692 _("the only suffix valid here is '(plt)'"));
6693 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6697 inst
.reloc
.type
= default_reloc
;
6699 inst
.reloc
.pc_rel
= 1;
6706 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6707 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6710 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6717 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6719 if (inst
.cond
== COND_ALWAYS
)
6720 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6722 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6726 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6729 /* ARM V5 branch-link-exchange instruction (argument parse)
6730 BLX <target_addr> ie BLX(1)
6731 BLX{<condition>} <Rm> ie BLX(2)
6732 Unfortunately, there are two different opcodes for this mnemonic.
6733 So, the insns[].value is not used, and the code here zaps values
6734 into inst.instruction.
6735 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6740 if (inst
.operands
[0].isreg
)
6742 /* Arg is a register; the opcode provided by insns[] is correct.
6743 It is not illegal to do "blx pc", just useless. */
6744 if (inst
.operands
[0].reg
== REG_PC
)
6745 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6747 inst
.instruction
|= inst
.operands
[0].reg
;
6751 /* Arg is an address; this instruction cannot be executed
6752 conditionally, and the opcode must be adjusted. */
6753 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6754 inst
.instruction
= 0xfa000000;
6756 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6757 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6760 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6767 bfd_boolean want_reloc
;
6769 if (inst
.operands
[0].reg
== REG_PC
)
6770 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6772 inst
.instruction
|= inst
.operands
[0].reg
;
6773 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
6774 it is for ARMv4t or earlier. */
6775 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
6776 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
6780 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
6785 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
6789 /* ARM v5TEJ. Jump to Jazelle code. */
6794 if (inst
.operands
[0].reg
== REG_PC
)
6795 as_tsktsk (_("use of r15 in bxj is not really useful"));
6797 inst
.instruction
|= inst
.operands
[0].reg
;
6800 /* Co-processor data operation:
6801 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6802 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6806 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6807 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6808 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6809 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6810 inst
.instruction
|= inst
.operands
[4].reg
;
6811 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6817 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6818 encode_arm_shifter_operand (1);
6821 /* Transfer between coprocessor and ARM registers.
6822 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6827 No special properties. */
6832 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6833 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6834 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6835 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6836 inst
.instruction
|= inst
.operands
[4].reg
;
6837 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6840 /* Transfer between coprocessor register and pair of ARM registers.
6841 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6846 Two XScale instructions are special cases of these:
6848 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6849 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6851 Result unpredictable if Rd or Rn is R15. */
6856 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6857 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6858 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6859 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6860 inst
.instruction
|= inst
.operands
[4].reg
;
6866 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6867 if (inst
.operands
[1].present
)
6869 inst
.instruction
|= CPSI_MMOD
;
6870 inst
.instruction
|= inst
.operands
[1].imm
;
6877 inst
.instruction
|= inst
.operands
[0].imm
;
6883 /* There is no IT instruction in ARM mode. We
6884 process it but do not generate code for it. */
6891 int base_reg
= inst
.operands
[0].reg
;
6892 int range
= inst
.operands
[1].imm
;
6894 inst
.instruction
|= base_reg
<< 16;
6895 inst
.instruction
|= range
;
6897 if (inst
.operands
[1].writeback
)
6898 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6900 if (inst
.operands
[0].writeback
)
6902 inst
.instruction
|= WRITE_BACK
;
6903 /* Check for unpredictable uses of writeback. */
6904 if (inst
.instruction
& LOAD_BIT
)
6906 /* Not allowed in LDM type 2. */
6907 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6908 && ((range
& (1 << REG_PC
)) == 0))
6909 as_warn (_("writeback of base register is UNPREDICTABLE"));
6910 /* Only allowed if base reg not in list for other types. */
6911 else if (range
& (1 << base_reg
))
6912 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6916 /* Not allowed for type 2. */
6917 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6918 as_warn (_("writeback of base register is UNPREDICTABLE"));
6919 /* Only allowed if base reg not in list, or first in list. */
6920 else if ((range
& (1 << base_reg
))
6921 && (range
& ((1 << base_reg
) - 1)))
6922 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6927 /* ARMv5TE load-consecutive (argument parse)
6936 constraint (inst
.operands
[0].reg
% 2 != 0,
6937 _("first destination register must be even"));
6938 constraint (inst
.operands
[1].present
6939 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6940 _("can only load two consecutive registers"));
6941 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6942 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6944 if (!inst
.operands
[1].present
)
6945 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6947 if (inst
.instruction
& LOAD_BIT
)
6949 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6950 register and the first register written; we have to diagnose
6951 overlap between the base and the second register written here. */
6953 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6954 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6955 as_warn (_("base register written back, and overlaps "
6956 "second destination register"));
6958 /* For an index-register load, the index register must not overlap the
6959 destination (even if not write-back). */
6960 else if (inst
.operands
[2].immisreg
6961 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6962 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6963 as_warn (_("index register overlaps destination register"));
6966 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6967 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6973 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6974 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6975 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6976 || inst
.operands
[1].negative
6977 /* This can arise if the programmer has written
6979 or if they have mistakenly used a register name as the last
6982 It is very difficult to distinguish between these two cases
6983 because "rX" might actually be a label. ie the register
6984 name has been occluded by a symbol of the same name. So we
6985 just generate a general 'bad addressing mode' type error
6986 message and leave it up to the programmer to discover the
6987 true cause and fix their mistake. */
6988 || (inst
.operands
[1].reg
== REG_PC
),
6991 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6992 || inst
.reloc
.exp
.X_add_number
!= 0,
6993 _("offset must be zero in ARM encoding"));
6995 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6996 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6997 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7003 constraint (inst
.operands
[0].reg
% 2 != 0,
7004 _("even register required"));
7005 constraint (inst
.operands
[1].present
7006 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7007 _("can only load two consecutive registers"));
7008 /* If op 1 were present and equal to PC, this function wouldn't
7009 have been called in the first place. */
7010 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7012 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7013 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7020 if (!inst
.operands
[1].isreg
)
7021 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7023 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7029 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7031 if (inst
.operands
[1].preind
)
7033 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7034 || inst
.reloc
.exp
.X_add_number
!= 0,
7035 _("this instruction requires a post-indexed address"));
7037 inst
.operands
[1].preind
= 0;
7038 inst
.operands
[1].postind
= 1;
7039 inst
.operands
[1].writeback
= 1;
7041 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7042 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7045 /* Halfword and signed-byte load/store operations. */
7050 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7051 if (!inst
.operands
[1].isreg
)
7052 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7054 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7060 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7062 if (inst
.operands
[1].preind
)
7064 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7065 || inst
.reloc
.exp
.X_add_number
!= 0,
7066 _("this instruction requires a post-indexed address"));
7068 inst
.operands
[1].preind
= 0;
7069 inst
.operands
[1].postind
= 1;
7070 inst
.operands
[1].writeback
= 1;
7072 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7073 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7076 /* Co-processor register load/store.
7077 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7081 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7082 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7083 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7089 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7090 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7091 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7092 && !(inst
.instruction
& 0x00400000))
7093 as_tsktsk (_("Rd and Rm should be different in mla"));
7095 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7096 inst
.instruction
|= inst
.operands
[1].reg
;
7097 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7098 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7104 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7105 encode_arm_shifter_operand (1);
7108 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7115 top
= (inst
.instruction
& 0x00400000) != 0;
7116 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7117 _(":lower16: not allowed this instruction"));
7118 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7119 _(":upper16: not allowed instruction"));
7120 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7121 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7123 imm
= inst
.reloc
.exp
.X_add_number
;
7124 /* The value is in two pieces: 0:11, 16:19. */
7125 inst
.instruction
|= (imm
& 0x00000fff);
7126 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7130 static void do_vfp_nsyn_opcode (const char *);
7133 do_vfp_nsyn_mrs (void)
7135 if (inst
.operands
[0].isvec
)
7137 if (inst
.operands
[1].reg
!= 1)
7138 first_error (_("operand 1 must be FPSCR"));
7139 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7140 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7141 do_vfp_nsyn_opcode ("fmstat");
7143 else if (inst
.operands
[1].isvec
)
7144 do_vfp_nsyn_opcode ("fmrx");
7152 do_vfp_nsyn_msr (void)
7154 if (inst
.operands
[0].isvec
)
7155 do_vfp_nsyn_opcode ("fmxr");
7165 if (do_vfp_nsyn_mrs () == SUCCESS
)
7168 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7169 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7171 _("'CPSR' or 'SPSR' expected"));
7172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7173 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7176 /* Two possible forms:
7177 "{C|S}PSR_<field>, Rm",
7178 "{C|S}PSR_f, #expression". */
7183 if (do_vfp_nsyn_msr () == SUCCESS
)
7186 inst
.instruction
|= inst
.operands
[0].imm
;
7187 if (inst
.operands
[1].isreg
)
7188 inst
.instruction
|= inst
.operands
[1].reg
;
7191 inst
.instruction
|= INST_IMMEDIATE
;
7192 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7193 inst
.reloc
.pc_rel
= 0;
7200 if (!inst
.operands
[2].present
)
7201 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7202 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7203 inst
.instruction
|= inst
.operands
[1].reg
;
7204 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7206 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7207 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7208 as_tsktsk (_("Rd and Rm should be different in mul"));
7211 /* Long Multiply Parser
7212 UMULL RdLo, RdHi, Rm, Rs
7213 SMULL RdLo, RdHi, Rm, Rs
7214 UMLAL RdLo, RdHi, Rm, Rs
7215 SMLAL RdLo, RdHi, Rm, Rs. */
7220 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7221 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7222 inst
.instruction
|= inst
.operands
[2].reg
;
7223 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7225 /* rdhi and rdlo must be different. */
7226 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7227 as_tsktsk (_("rdhi and rdlo must be different"));
7229 /* rdhi, rdlo and rm must all be different before armv6. */
7230 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7231 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7232 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7233 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7239 if (inst
.operands
[0].present
)
7241 /* Architectural NOP hints are CPSR sets with no bits selected. */
7242 inst
.instruction
&= 0xf0000000;
7243 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7247 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7248 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7249 Condition defaults to COND_ALWAYS.
7250 Error if Rd, Rn or Rm are R15. */
7255 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7256 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7257 inst
.instruction
|= inst
.operands
[2].reg
;
7258 if (inst
.operands
[3].present
)
7259 encode_arm_shift (3);
7262 /* ARM V6 PKHTB (Argument Parse). */
7267 if (!inst
.operands
[3].present
)
7269 /* If the shift specifier is omitted, turn the instruction
7270 into pkhbt rd, rm, rn. */
7271 inst
.instruction
&= 0xfff00010;
7272 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7273 inst
.instruction
|= inst
.operands
[1].reg
;
7274 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7278 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7279 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7280 inst
.instruction
|= inst
.operands
[2].reg
;
7281 encode_arm_shift (3);
7285 /* ARMv5TE: Preload-Cache
7289 Syntactically, like LDR with B=1, W=0, L=1. */
7294 constraint (!inst
.operands
[0].isreg
,
7295 _("'[' expected after PLD mnemonic"));
7296 constraint (inst
.operands
[0].postind
,
7297 _("post-indexed expression used in preload instruction"));
7298 constraint (inst
.operands
[0].writeback
,
7299 _("writeback used in preload instruction"));
7300 constraint (!inst
.operands
[0].preind
,
7301 _("unindexed addressing used in preload instruction"));
7302 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7305 /* ARMv7: PLI <addr_mode> */
7309 constraint (!inst
.operands
[0].isreg
,
7310 _("'[' expected after PLI mnemonic"));
7311 constraint (inst
.operands
[0].postind
,
7312 _("post-indexed expression used in preload instruction"));
7313 constraint (inst
.operands
[0].writeback
,
7314 _("writeback used in preload instruction"));
7315 constraint (!inst
.operands
[0].preind
,
7316 _("unindexed addressing used in preload instruction"));
7317 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7318 inst
.instruction
&= ~PRE_INDEX
;
7324 inst
.operands
[1] = inst
.operands
[0];
7325 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7326 inst
.operands
[0].isreg
= 1;
7327 inst
.operands
[0].writeback
= 1;
7328 inst
.operands
[0].reg
= REG_SP
;
7332 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7333 word at the specified address and the following word
7335 Unconditionally executed.
7336 Error if Rn is R15. */
7341 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7342 if (inst
.operands
[0].writeback
)
7343 inst
.instruction
|= WRITE_BACK
;
7346 /* ARM V6 ssat (argument parse). */
7351 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7352 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7353 inst
.instruction
|= inst
.operands
[2].reg
;
7355 if (inst
.operands
[3].present
)
7356 encode_arm_shift (3);
7359 /* ARM V6 usat (argument parse). */
7364 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7365 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7366 inst
.instruction
|= inst
.operands
[2].reg
;
7368 if (inst
.operands
[3].present
)
7369 encode_arm_shift (3);
7372 /* ARM V6 ssat16 (argument parse). */
7377 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7378 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7379 inst
.instruction
|= inst
.operands
[2].reg
;
7385 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7386 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7387 inst
.instruction
|= inst
.operands
[2].reg
;
7390 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7391 preserving the other bits.
7393 setend <endian_specifier>, where <endian_specifier> is either
7399 if (inst
.operands
[0].imm
)
7400 inst
.instruction
|= 0x200;
7406 unsigned int Rm
= (inst
.operands
[1].present
7407 ? inst
.operands
[1].reg
7408 : inst
.operands
[0].reg
);
7410 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7411 inst
.instruction
|= Rm
;
7412 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7414 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7415 inst
.instruction
|= SHIFT_BY_REG
;
7418 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7424 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7425 inst
.reloc
.pc_rel
= 0;
7431 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7432 inst
.reloc
.pc_rel
= 0;
7435 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7436 SMLAxy{cond} Rd,Rm,Rs,Rn
7437 SMLAWy{cond} Rd,Rm,Rs,Rn
7438 Error if any register is R15. */
7443 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7444 inst
.instruction
|= inst
.operands
[1].reg
;
7445 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7446 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7449 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7450 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7451 Error if any register is R15.
7452 Warning if Rdlo == Rdhi. */
7457 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7458 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7459 inst
.instruction
|= inst
.operands
[2].reg
;
7460 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7462 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7463 as_tsktsk (_("rdhi and rdlo must be different"));
7466 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7467 SMULxy{cond} Rd,Rm,Rs
7468 Error if any register is R15. */
7473 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7474 inst
.instruction
|= inst
.operands
[1].reg
;
7475 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7478 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7479 the same for both ARM and Thumb-2. */
7486 if (inst
.operands
[0].present
)
7488 reg
= inst
.operands
[0].reg
;
7489 constraint (reg
!= 13, _("SRS base register must be r13"));
7494 inst
.instruction
|= reg
<< 16;
7495 inst
.instruction
|= inst
.operands
[1].imm
;
7496 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7497 inst
.instruction
|= WRITE_BACK
;
7500 /* ARM V6 strex (argument parse). */
7505 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7506 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7507 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7508 || inst
.operands
[2].negative
7509 /* See comment in do_ldrex(). */
7510 || (inst
.operands
[2].reg
== REG_PC
),
7513 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7514 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7516 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7517 || inst
.reloc
.exp
.X_add_number
!= 0,
7518 _("offset must be zero in ARM encoding"));
7520 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7521 inst
.instruction
|= inst
.operands
[1].reg
;
7522 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7523 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7529 constraint (inst
.operands
[1].reg
% 2 != 0,
7530 _("even register required"));
7531 constraint (inst
.operands
[2].present
7532 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7533 _("can only store two consecutive registers"));
7534 /* If op 2 were present and equal to PC, this function wouldn't
7535 have been called in the first place. */
7536 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7538 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7539 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7540 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7543 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7544 inst
.instruction
|= inst
.operands
[1].reg
;
7545 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7548 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7549 extends it to 32-bits, and adds the result to a value in another
7550 register. You can specify a rotation by 0, 8, 16, or 24 bits
7551 before extracting the 16-bit value.
7552 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7553 Condition defaults to COND_ALWAYS.
7554 Error if any register uses R15. */
7559 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7560 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7561 inst
.instruction
|= inst
.operands
[2].reg
;
7562 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7567 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7568 Condition defaults to COND_ALWAYS.
7569 Error if any register uses R15. */
7574 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7575 inst
.instruction
|= inst
.operands
[1].reg
;
7576 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7579 /* VFP instructions. In a logical order: SP variant first, monad
7580 before dyad, arithmetic then move then load/store. */
7583 do_vfp_sp_monadic (void)
7585 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7586 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7590 do_vfp_sp_dyadic (void)
7592 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7593 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7594 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7598 do_vfp_sp_compare_z (void)
7600 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7604 do_vfp_dp_sp_cvt (void)
7606 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7607 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7611 do_vfp_sp_dp_cvt (void)
7613 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7614 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7618 do_vfp_reg_from_sp (void)
7620 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7621 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7625 do_vfp_reg2_from_sp2 (void)
7627 constraint (inst
.operands
[2].imm
!= 2,
7628 _("only two consecutive VFP SP registers allowed here"));
7629 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7630 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7631 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7635 do_vfp_sp_from_reg (void)
7637 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7638 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7642 do_vfp_sp2_from_reg2 (void)
7644 constraint (inst
.operands
[0].imm
!= 2,
7645 _("only two consecutive VFP SP registers allowed here"));
7646 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7647 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7648 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7652 do_vfp_sp_ldst (void)
7654 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7655 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7659 do_vfp_dp_ldst (void)
7661 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7662 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7667 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7669 if (inst
.operands
[0].writeback
)
7670 inst
.instruction
|= WRITE_BACK
;
7672 constraint (ldstm_type
!= VFP_LDSTMIA
,
7673 _("this addressing mode requires base-register writeback"));
7674 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7675 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7676 inst
.instruction
|= inst
.operands
[1].imm
;
7680 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7684 if (inst
.operands
[0].writeback
)
7685 inst
.instruction
|= WRITE_BACK
;
7687 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7688 _("this addressing mode requires base-register writeback"));
7690 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7691 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7693 count
= inst
.operands
[1].imm
<< 1;
7694 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7697 inst
.instruction
|= count
;
7701 do_vfp_sp_ldstmia (void)
7703 vfp_sp_ldstm (VFP_LDSTMIA
);
7707 do_vfp_sp_ldstmdb (void)
7709 vfp_sp_ldstm (VFP_LDSTMDB
);
7713 do_vfp_dp_ldstmia (void)
7715 vfp_dp_ldstm (VFP_LDSTMIA
);
7719 do_vfp_dp_ldstmdb (void)
7721 vfp_dp_ldstm (VFP_LDSTMDB
);
7725 do_vfp_xp_ldstmia (void)
7727 vfp_dp_ldstm (VFP_LDSTMIAX
);
7731 do_vfp_xp_ldstmdb (void)
7733 vfp_dp_ldstm (VFP_LDSTMDBX
);
7737 do_vfp_dp_rd_rm (void)
7739 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7740 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7744 do_vfp_dp_rn_rd (void)
7746 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7747 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7751 do_vfp_dp_rd_rn (void)
7753 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7754 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7758 do_vfp_dp_rd_rn_rm (void)
7760 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7761 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7762 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7768 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7772 do_vfp_dp_rm_rd_rn (void)
7774 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7775 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7776 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7779 /* VFPv3 instructions. */
7781 do_vfp_sp_const (void)
7783 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7784 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7785 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7789 do_vfp_dp_const (void)
7791 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7792 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7793 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7797 vfp_conv (int srcsize
)
7799 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7800 inst
.instruction
|= (immbits
& 1) << 5;
7801 inst
.instruction
|= (immbits
>> 1);
7805 do_vfp_sp_conv_16 (void)
7807 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7812 do_vfp_dp_conv_16 (void)
7814 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7819 do_vfp_sp_conv_32 (void)
7821 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7826 do_vfp_dp_conv_32 (void)
7828 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7832 /* FPA instructions. Also in a logical order. */
7837 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7838 inst
.instruction
|= inst
.operands
[1].reg
;
7842 do_fpa_ldmstm (void)
7844 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7845 switch (inst
.operands
[1].imm
)
7847 case 1: inst
.instruction
|= CP_T_X
; break;
7848 case 2: inst
.instruction
|= CP_T_Y
; break;
7849 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7854 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7856 /* The instruction specified "ea" or "fd", so we can only accept
7857 [Rn]{!}. The instruction does not really support stacking or
7858 unstacking, so we have to emulate these by setting appropriate
7859 bits and offsets. */
7860 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7861 || inst
.reloc
.exp
.X_add_number
!= 0,
7862 _("this instruction does not support indexing"));
7864 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7865 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7867 if (!(inst
.instruction
& INDEX_UP
))
7868 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7870 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7872 inst
.operands
[2].preind
= 0;
7873 inst
.operands
[2].postind
= 1;
7877 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7880 /* iWMMXt instructions: strictly in alphabetical order. */
7883 do_iwmmxt_tandorc (void)
7885 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7889 do_iwmmxt_textrc (void)
7891 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7892 inst
.instruction
|= inst
.operands
[1].imm
;
7896 do_iwmmxt_textrm (void)
7898 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7899 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7900 inst
.instruction
|= inst
.operands
[2].imm
;
7904 do_iwmmxt_tinsr (void)
7906 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7907 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7908 inst
.instruction
|= inst
.operands
[2].imm
;
7912 do_iwmmxt_tmia (void)
7914 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7915 inst
.instruction
|= inst
.operands
[1].reg
;
7916 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7920 do_iwmmxt_waligni (void)
7922 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7923 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7924 inst
.instruction
|= inst
.operands
[2].reg
;
7925 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7929 do_iwmmxt_wmerge (void)
7931 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7932 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7933 inst
.instruction
|= inst
.operands
[2].reg
;
7934 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
7938 do_iwmmxt_wmov (void)
7940 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7941 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7942 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7943 inst
.instruction
|= inst
.operands
[1].reg
;
7947 do_iwmmxt_wldstbh (void)
7950 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7952 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7954 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7955 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7959 do_iwmmxt_wldstw (void)
7961 /* RIWR_RIWC clears .isreg for a control register. */
7962 if (!inst
.operands
[0].isreg
)
7964 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7965 inst
.instruction
|= 0xf0000000;
7968 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7969 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7973 do_iwmmxt_wldstd (void)
7975 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7976 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
7977 && inst
.operands
[1].immisreg
)
7979 inst
.instruction
&= ~0x1a000ff;
7980 inst
.instruction
|= (0xf << 28);
7981 if (inst
.operands
[1].preind
)
7982 inst
.instruction
|= PRE_INDEX
;
7983 if (!inst
.operands
[1].negative
)
7984 inst
.instruction
|= INDEX_UP
;
7985 if (inst
.operands
[1].writeback
)
7986 inst
.instruction
|= WRITE_BACK
;
7987 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7988 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
7989 inst
.instruction
|= inst
.operands
[1].imm
;
7992 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7996 do_iwmmxt_wshufh (void)
7998 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7999 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8000 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8001 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8005 do_iwmmxt_wzero (void)
8007 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8008 inst
.instruction
|= inst
.operands
[0].reg
;
8009 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8010 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8014 do_iwmmxt_wrwrwr_or_imm5 (void)
8016 if (inst
.operands
[2].isreg
)
8019 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8020 _("immediate operand requires iWMMXt2"));
8022 if (inst
.operands
[2].imm
== 0)
8024 switch ((inst
.instruction
>> 20) & 0xf)
8030 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8031 inst
.operands
[2].imm
= 16;
8032 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8038 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8039 inst
.operands
[2].imm
= 32;
8040 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8047 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8049 wrn
= (inst
.instruction
>> 16) & 0xf;
8050 inst
.instruction
&= 0xff0fff0f;
8051 inst
.instruction
|= wrn
;
8052 /* Bail out here; the instruction is now assembled. */
8057 /* Map 32 -> 0, etc. */
8058 inst
.operands
[2].imm
&= 0x1f;
8059 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8063 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8064 operations first, then control, shift, and load/store. */
8066 /* Insns like "foo X,Y,Z". */
8069 do_mav_triple (void)
8071 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8072 inst
.instruction
|= inst
.operands
[1].reg
;
8073 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8076 /* Insns like "foo W,X,Y,Z".
8077 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8082 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8083 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8084 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8085 inst
.instruction
|= inst
.operands
[3].reg
;
8088 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8092 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8095 /* Maverick shift immediate instructions.
8096 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8097 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8102 int imm
= inst
.operands
[2].imm
;
8104 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8105 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8107 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8108 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8109 Bit 4 should be 0. */
8110 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8112 inst
.instruction
|= imm
;
8115 /* XScale instructions. Also sorted arithmetic before move. */
8117 /* Xscale multiply-accumulate (argument parse)
8120 MIAxycc acc0,Rm,Rs. */
8125 inst
.instruction
|= inst
.operands
[1].reg
;
8126 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8129 /* Xscale move-accumulator-register (argument parse)
8131 MARcc acc0,RdLo,RdHi. */
8136 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8137 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8140 /* Xscale move-register-accumulator (argument parse)
8142 MRAcc RdLo,RdHi,acc0. */
8147 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8148 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8149 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8152 /* Encoding functions relevant only to Thumb. */
8154 /* inst.operands[i] is a shifted-register operand; encode
8155 it into inst.instruction in the format used by Thumb32. */
8158 encode_thumb32_shifted_operand (int i
)
8160 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8161 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8163 constraint (inst
.operands
[i
].immisreg
,
8164 _("shift by register not allowed in thumb mode"));
8165 inst
.instruction
|= inst
.operands
[i
].reg
;
8166 if (shift
== SHIFT_RRX
)
8167 inst
.instruction
|= SHIFT_ROR
<< 4;
8170 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8171 _("expression too complex"));
8173 constraint (value
> 32
8174 || (value
== 32 && (shift
== SHIFT_LSL
8175 || shift
== SHIFT_ROR
)),
8176 _("shift expression is too large"));
8180 else if (value
== 32)
8183 inst
.instruction
|= shift
<< 4;
8184 inst
.instruction
|= (value
& 0x1c) << 10;
8185 inst
.instruction
|= (value
& 0x03) << 6;
8190 /* inst.operands[i] was set up by parse_address. Encode it into a
8191 Thumb32 format load or store instruction. Reject forms that cannot
8192 be used with such instructions. If is_t is true, reject forms that
8193 cannot be used with a T instruction; if is_d is true, reject forms
8194 that cannot be used with a D instruction. */
8197 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8199 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8201 constraint (!inst
.operands
[i
].isreg
,
8202 _("Instruction does not support =N addresses"));
8204 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8205 if (inst
.operands
[i
].immisreg
)
8207 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8208 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8209 constraint (inst
.operands
[i
].negative
,
8210 _("Thumb does not support negative register indexing"));
8211 constraint (inst
.operands
[i
].postind
,
8212 _("Thumb does not support register post-indexing"));
8213 constraint (inst
.operands
[i
].writeback
,
8214 _("Thumb does not support register indexing with writeback"));
8215 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8216 _("Thumb supports only LSL in shifted register indexing"));
8218 inst
.instruction
|= inst
.operands
[i
].imm
;
8219 if (inst
.operands
[i
].shifted
)
8221 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8222 _("expression too complex"));
8223 constraint (inst
.reloc
.exp
.X_add_number
< 0
8224 || inst
.reloc
.exp
.X_add_number
> 3,
8225 _("shift out of range"));
8226 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8228 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8230 else if (inst
.operands
[i
].preind
)
8232 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8233 _("cannot use writeback with PC-relative addressing"));
8234 constraint (is_t
&& inst
.operands
[i
].writeback
,
8235 _("cannot use writeback with this instruction"));
8239 inst
.instruction
|= 0x01000000;
8240 if (inst
.operands
[i
].writeback
)
8241 inst
.instruction
|= 0x00200000;
8245 inst
.instruction
|= 0x00000c00;
8246 if (inst
.operands
[i
].writeback
)
8247 inst
.instruction
|= 0x00000100;
8249 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8251 else if (inst
.operands
[i
].postind
)
8253 assert (inst
.operands
[i
].writeback
);
8254 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8255 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8258 inst
.instruction
|= 0x00200000;
8260 inst
.instruction
|= 0x00000900;
8261 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8263 else /* unindexed - only for coprocessor */
8264 inst
.error
= _("instruction does not accept unindexed addressing");
8267 /* Table of Thumb instructions which exist in both 16- and 32-bit
8268 encodings (the latter only in post-V6T2 cores). The index is the
8269 value used in the insns table below. When there is more than one
8270 possible 16-bit encoding for the instruction, this table always
8272 Also contains several pseudo-instructions used during relaxation. */
8273 #define T16_32_TAB \
8274 X(adc, 4140, eb400000), \
8275 X(adcs, 4140, eb500000), \
8276 X(add, 1c00, eb000000), \
8277 X(adds, 1c00, eb100000), \
8278 X(addi, 0000, f1000000), \
8279 X(addis, 0000, f1100000), \
8280 X(add_pc,000f, f20f0000), \
8281 X(add_sp,000d, f10d0000), \
8282 X(adr, 000f, f20f0000), \
8283 X(and, 4000, ea000000), \
8284 X(ands, 4000, ea100000), \
8285 X(asr, 1000, fa40f000), \
8286 X(asrs, 1000, fa50f000), \
8287 X(b, e000, f000b000), \
8288 X(bcond, d000, f0008000), \
8289 X(bic, 4380, ea200000), \
8290 X(bics, 4380, ea300000), \
8291 X(cmn, 42c0, eb100f00), \
8292 X(cmp, 2800, ebb00f00), \
8293 X(cpsie, b660, f3af8400), \
8294 X(cpsid, b670, f3af8600), \
8295 X(cpy, 4600, ea4f0000), \
8296 X(dec_sp,80dd, f1ad0d00), \
8297 X(eor, 4040, ea800000), \
8298 X(eors, 4040, ea900000), \
8299 X(inc_sp,00dd, f10d0d00), \
8300 X(ldmia, c800, e8900000), \
8301 X(ldr, 6800, f8500000), \
8302 X(ldrb, 7800, f8100000), \
8303 X(ldrh, 8800, f8300000), \
8304 X(ldrsb, 5600, f9100000), \
8305 X(ldrsh, 5e00, f9300000), \
8306 X(ldr_pc,4800, f85f0000), \
8307 X(ldr_pc2,4800, f85f0000), \
8308 X(ldr_sp,9800, f85d0000), \
8309 X(lsl, 0000, fa00f000), \
8310 X(lsls, 0000, fa10f000), \
8311 X(lsr, 0800, fa20f000), \
8312 X(lsrs, 0800, fa30f000), \
8313 X(mov, 2000, ea4f0000), \
8314 X(movs, 2000, ea5f0000), \
8315 X(mul, 4340, fb00f000), \
8316 X(muls, 4340, ffffffff), /* no 32b muls */ \
8317 X(mvn, 43c0, ea6f0000), \
8318 X(mvns, 43c0, ea7f0000), \
8319 X(neg, 4240, f1c00000), /* rsb #0 */ \
8320 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8321 X(orr, 4300, ea400000), \
8322 X(orrs, 4300, ea500000), \
8323 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8324 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8325 X(rev, ba00, fa90f080), \
8326 X(rev16, ba40, fa90f090), \
8327 X(revsh, bac0, fa90f0b0), \
8328 X(ror, 41c0, fa60f000), \
8329 X(rors, 41c0, fa70f000), \
8330 X(sbc, 4180, eb600000), \
8331 X(sbcs, 4180, eb700000), \
8332 X(stmia, c000, e8800000), \
8333 X(str, 6000, f8400000), \
8334 X(strb, 7000, f8000000), \
8335 X(strh, 8000, f8200000), \
8336 X(str_sp,9000, f84d0000), \
8337 X(sub, 1e00, eba00000), \
8338 X(subs, 1e00, ebb00000), \
8339 X(subi, 8000, f1a00000), \
8340 X(subis, 8000, f1b00000), \
8341 X(sxtb, b240, fa4ff080), \
8342 X(sxth, b200, fa0ff080), \
8343 X(tst, 4200, ea100f00), \
8344 X(uxtb, b2c0, fa5ff080), \
8345 X(uxth, b280, fa1ff080), \
8346 X(nop, bf00, f3af8000), \
8347 X(yield, bf10, f3af8001), \
8348 X(wfe, bf20, f3af8002), \
8349 X(wfi, bf30, f3af8003), \
8350 X(sev, bf40, f3af9004), /* typo, 8004? */
8352 /* To catch errors in encoding functions, the codes are all offset by
8353 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8354 as 16-bit instructions. */
8355 #define X(a,b,c) T_MNEM_##a
8356 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8359 #define X(a,b,c) 0x##b
8360 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8361 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8364 #define X(a,b,c) 0x##c
8365 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8366 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8367 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8371 /* Thumb instruction encoders, in alphabetical order. */
8375 do_t_add_sub_w (void)
8379 Rd
= inst
.operands
[0].reg
;
8380 Rn
= inst
.operands
[1].reg
;
8382 constraint (Rd
== 15, _("PC not allowed as destination"));
8383 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8384 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8387 /* Parse an add or subtract instruction. We get here with inst.instruction
8388 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8395 Rd
= inst
.operands
[0].reg
;
8396 Rs
= (inst
.operands
[1].present
8397 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8398 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8406 flags
= (inst
.instruction
== T_MNEM_adds
8407 || inst
.instruction
== T_MNEM_subs
);
8409 narrow
= (current_it_mask
== 0);
8411 narrow
= (current_it_mask
!= 0);
8412 if (!inst
.operands
[2].isreg
)
8416 add
= (inst
.instruction
== T_MNEM_add
8417 || inst
.instruction
== T_MNEM_adds
);
8419 if (inst
.size_req
!= 4)
8421 /* Attempt to use a narrow opcode, with relaxation if
8423 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8424 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8425 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8426 opcode
= T_MNEM_add_sp
;
8427 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8428 opcode
= T_MNEM_add_pc
;
8429 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8432 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8434 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8438 inst
.instruction
= THUMB_OP16(opcode
);
8439 inst
.instruction
|= (Rd
<< 4) | Rs
;
8440 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8441 if (inst
.size_req
!= 2)
8442 inst
.relax
= opcode
;
8445 constraint (inst
.size_req
== 2, BAD_HIREG
);
8447 if (inst
.size_req
== 4
8448 || (inst
.size_req
!= 2 && !opcode
))
8452 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8453 _("only SUBS PC, LR, #const allowed"));
8454 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8455 _("expression too complex"));
8456 constraint (inst
.reloc
.exp
.X_add_number
< 0
8457 || inst
.reloc
.exp
.X_add_number
> 0xff,
8458 _("immediate value out of range"));
8459 inst
.instruction
= T2_SUBS_PC_LR
8460 | inst
.reloc
.exp
.X_add_number
;
8461 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8464 else if (Rs
== REG_PC
)
8466 /* Always use addw/subw. */
8467 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8468 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8472 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8473 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8476 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8478 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8480 inst
.instruction
|= Rd
<< 8;
8481 inst
.instruction
|= Rs
<< 16;
8486 Rn
= inst
.operands
[2].reg
;
8487 /* See if we can do this with a 16-bit instruction. */
8488 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8490 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8495 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8496 || inst
.instruction
== T_MNEM_add
)
8499 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8503 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
8505 /* Thumb-1 cores (except v6-M) require at least one high
8506 register in a narrow non flag setting add. */
8507 if (Rd
> 7 || Rn
> 7
8508 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
8509 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
8516 inst
.instruction
= T_OPCODE_ADD_HI
;
8517 inst
.instruction
|= (Rd
& 8) << 4;
8518 inst
.instruction
|= (Rd
& 7);
8519 inst
.instruction
|= Rn
<< 3;
8524 /* If we get here, it can't be done in 16 bits. */
8525 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8526 _("shift must be constant"));
8527 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8528 inst
.instruction
|= Rd
<< 8;
8529 inst
.instruction
|= Rs
<< 16;
8530 encode_thumb32_shifted_operand (2);
8535 constraint (inst
.instruction
== T_MNEM_adds
8536 || inst
.instruction
== T_MNEM_subs
,
8539 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8541 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8542 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8545 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8547 inst
.instruction
|= (Rd
<< 4) | Rs
;
8548 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8552 Rn
= inst
.operands
[2].reg
;
8553 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8555 /* We now have Rd, Rs, and Rn set to registers. */
8556 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8558 /* Can't do this for SUB. */
8559 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8560 inst
.instruction
= T_OPCODE_ADD_HI
;
8561 inst
.instruction
|= (Rd
& 8) << 4;
8562 inst
.instruction
|= (Rd
& 7);
8564 inst
.instruction
|= Rn
<< 3;
8566 inst
.instruction
|= Rs
<< 3;
8568 constraint (1, _("dest must overlap one source register"));
8572 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8573 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8574 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8582 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8584 /* Defer to section relaxation. */
8585 inst
.relax
= inst
.instruction
;
8586 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8587 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8589 else if (unified_syntax
&& inst
.size_req
!= 2)
8591 /* Generate a 32-bit opcode. */
8592 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8593 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8594 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8595 inst
.reloc
.pc_rel
= 1;
8599 /* Generate a 16-bit opcode. */
8600 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8601 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8602 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8603 inst
.reloc
.pc_rel
= 1;
8605 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8609 /* Arithmetic instructions for which there is just one 16-bit
8610 instruction encoding, and it allows only two low registers.
8611 For maximal compatibility with ARM syntax, we allow three register
8612 operands even when Thumb-32 instructions are not available, as long
8613 as the first two are identical. For instance, both "sbc r0,r1" and
8614 "sbc r0,r0,r1" are allowed. */
8620 Rd
= inst
.operands
[0].reg
;
8621 Rs
= (inst
.operands
[1].present
8622 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8623 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8624 Rn
= inst
.operands
[2].reg
;
8628 if (!inst
.operands
[2].isreg
)
8630 /* For an immediate, we always generate a 32-bit opcode;
8631 section relaxation will shrink it later if possible. */
8632 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8633 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8634 inst
.instruction
|= Rd
<< 8;
8635 inst
.instruction
|= Rs
<< 16;
8636 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8642 /* See if we can do this with a 16-bit instruction. */
8643 if (THUMB_SETS_FLAGS (inst
.instruction
))
8644 narrow
= current_it_mask
== 0;
8646 narrow
= current_it_mask
!= 0;
8648 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8650 if (inst
.operands
[2].shifted
)
8652 if (inst
.size_req
== 4)
8658 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8659 inst
.instruction
|= Rd
;
8660 inst
.instruction
|= Rn
<< 3;
8664 /* If we get here, it can't be done in 16 bits. */
8665 constraint (inst
.operands
[2].shifted
8666 && inst
.operands
[2].immisreg
,
8667 _("shift must be constant"));
8668 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8669 inst
.instruction
|= Rd
<< 8;
8670 inst
.instruction
|= Rs
<< 16;
8671 encode_thumb32_shifted_operand (2);
8676 /* On its face this is a lie - the instruction does set the
8677 flags. However, the only supported mnemonic in this mode
8679 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8681 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8682 _("unshifted register required"));
8683 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8684 constraint (Rd
!= Rs
,
8685 _("dest and source1 must be the same register"));
8687 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8688 inst
.instruction
|= Rd
;
8689 inst
.instruction
|= Rn
<< 3;
8693 /* Similarly, but for instructions where the arithmetic operation is
8694 commutative, so we can allow either of them to be different from
8695 the destination operand in a 16-bit instruction. For instance, all
8696 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8703 Rd
= inst
.operands
[0].reg
;
8704 Rs
= (inst
.operands
[1].present
8705 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8706 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8707 Rn
= inst
.operands
[2].reg
;
8711 if (!inst
.operands
[2].isreg
)
8713 /* For an immediate, we always generate a 32-bit opcode;
8714 section relaxation will shrink it later if possible. */
8715 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8716 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8717 inst
.instruction
|= Rd
<< 8;
8718 inst
.instruction
|= Rs
<< 16;
8719 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8725 /* See if we can do this with a 16-bit instruction. */
8726 if (THUMB_SETS_FLAGS (inst
.instruction
))
8727 narrow
= current_it_mask
== 0;
8729 narrow
= current_it_mask
!= 0;
8731 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8733 if (inst
.operands
[2].shifted
)
8735 if (inst
.size_req
== 4)
8742 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8743 inst
.instruction
|= Rd
;
8744 inst
.instruction
|= Rn
<< 3;
8749 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8750 inst
.instruction
|= Rd
;
8751 inst
.instruction
|= Rs
<< 3;
8756 /* If we get here, it can't be done in 16 bits. */
8757 constraint (inst
.operands
[2].shifted
8758 && inst
.operands
[2].immisreg
,
8759 _("shift must be constant"));
8760 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8761 inst
.instruction
|= Rd
<< 8;
8762 inst
.instruction
|= Rs
<< 16;
8763 encode_thumb32_shifted_operand (2);
8768 /* On its face this is a lie - the instruction does set the
8769 flags. However, the only supported mnemonic in this mode
8771 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8773 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8774 _("unshifted register required"));
8775 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8777 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8778 inst
.instruction
|= Rd
;
8781 inst
.instruction
|= Rn
<< 3;
8783 inst
.instruction
|= Rs
<< 3;
8785 constraint (1, _("dest must overlap one source register"));
8792 if (inst
.operands
[0].present
)
8794 constraint ((inst
.instruction
& 0xf0) != 0x40
8795 && inst
.operands
[0].imm
!= 0xf,
8796 _("bad barrier type"));
8797 inst
.instruction
|= inst
.operands
[0].imm
;
8800 inst
.instruction
|= 0xf;
8806 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8807 constraint (msb
> 32, _("bit-field extends past end of register"));
8808 /* The instruction encoding stores the LSB and MSB,
8809 not the LSB and width. */
8810 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8811 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8812 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8813 inst
.instruction
|= msb
- 1;
8821 /* #0 in second position is alternative syntax for bfc, which is
8822 the same instruction but with REG_PC in the Rm field. */
8823 if (!inst
.operands
[1].isreg
)
8824 inst
.operands
[1].reg
= REG_PC
;
8826 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8827 constraint (msb
> 32, _("bit-field extends past end of register"));
8828 /* The instruction encoding stores the LSB and MSB,
8829 not the LSB and width. */
8830 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8831 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8832 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8833 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8834 inst
.instruction
|= msb
- 1;
8840 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8841 _("bit-field extends past end of register"));
8842 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8843 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8844 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8845 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8846 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8849 /* ARM V5 Thumb BLX (argument parse)
8850 BLX <target_addr> which is BLX(1)
8851 BLX <Rm> which is BLX(2)
8852 Unfortunately, there are two different opcodes for this mnemonic.
8853 So, the insns[].value is not used, and the code here zaps values
8854 into inst.instruction.
8856 ??? How to take advantage of the additional two bits of displacement
8857 available in Thumb32 mode? Need new relocation? */
8862 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8863 if (inst
.operands
[0].isreg
)
8864 /* We have a register, so this is BLX(2). */
8865 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8868 /* No register. This must be BLX(1). */
8869 inst
.instruction
= 0xf000e800;
8871 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8872 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8875 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8876 inst
.reloc
.pc_rel
= 1;
8886 if (current_it_mask
)
8888 /* Conditional branches inside IT blocks are encoded as unconditional
8891 /* A branch must be the last instruction in an IT block. */
8892 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8897 if (cond
!= COND_ALWAYS
)
8898 opcode
= T_MNEM_bcond
;
8900 opcode
= inst
.instruction
;
8902 if (unified_syntax
&& inst
.size_req
== 4)
8904 inst
.instruction
= THUMB_OP32(opcode
);
8905 if (cond
== COND_ALWAYS
)
8906 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8909 assert (cond
!= 0xF);
8910 inst
.instruction
|= cond
<< 22;
8911 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8916 inst
.instruction
= THUMB_OP16(opcode
);
8917 if (cond
== COND_ALWAYS
)
8918 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8921 inst
.instruction
|= cond
<< 8;
8922 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8924 /* Allow section relaxation. */
8925 if (unified_syntax
&& inst
.size_req
!= 2)
8926 inst
.relax
= opcode
;
8929 inst
.reloc
.pc_rel
= 1;
8935 constraint (inst
.cond
!= COND_ALWAYS
,
8936 _("instruction is always unconditional"));
8937 if (inst
.operands
[0].present
)
8939 constraint (inst
.operands
[0].imm
> 255,
8940 _("immediate value out of range"));
8941 inst
.instruction
|= inst
.operands
[0].imm
;
8946 do_t_branch23 (void)
8948 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8949 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8950 inst
.reloc
.pc_rel
= 1;
8952 /* If the destination of the branch is a defined symbol which does not have
8953 the THUMB_FUNC attribute, then we must be calling a function which has
8954 the (interfacearm) attribute. We look for the Thumb entry point to that
8955 function and change the branch to refer to that function instead. */
8956 if ( inst
.reloc
.exp
.X_op
== O_symbol
8957 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8958 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8959 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8960 inst
.reloc
.exp
.X_add_symbol
=
8961 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8967 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8968 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8969 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8970 should cause the alignment to be checked once it is known. This is
8971 because BX PC only works if the instruction is word aligned. */
8977 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8978 if (inst
.operands
[0].reg
== REG_PC
)
8979 as_tsktsk (_("use of r15 in bxj is not really useful"));
8981 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8987 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8988 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8989 inst
.instruction
|= inst
.operands
[1].reg
;
8995 constraint (current_it_mask
, BAD_NOT_IT
);
8996 inst
.instruction
|= inst
.operands
[0].imm
;
9002 constraint (current_it_mask
, BAD_NOT_IT
);
9004 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9005 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9007 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9008 inst
.instruction
= 0xf3af8000;
9009 inst
.instruction
|= imod
<< 9;
9010 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9011 if (inst
.operands
[1].present
)
9012 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9016 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9017 && (inst
.operands
[0].imm
& 4),
9018 _("selected processor does not support 'A' form "
9019 "of this instruction"));
9020 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9021 _("Thumb does not support the 2-argument "
9022 "form of this instruction"));
9023 inst
.instruction
|= inst
.operands
[0].imm
;
9027 /* THUMB CPY instruction (argument parse). */
9032 if (inst
.size_req
== 4)
9034 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9035 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9036 inst
.instruction
|= inst
.operands
[1].reg
;
9040 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9041 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9042 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9049 constraint (current_it_mask
, BAD_NOT_IT
);
9050 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9051 inst
.instruction
|= inst
.operands
[0].reg
;
9052 inst
.reloc
.pc_rel
= 1;
9053 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9059 inst
.instruction
|= inst
.operands
[0].imm
;
9065 if (!inst
.operands
[1].present
)
9066 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9067 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9068 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9069 inst
.instruction
|= inst
.operands
[2].reg
;
9075 if (unified_syntax
&& inst
.size_req
== 4)
9076 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9078 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9084 unsigned int cond
= inst
.operands
[0].imm
;
9086 constraint (current_it_mask
, BAD_NOT_IT
);
9087 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9090 /* If the condition is a negative condition, invert the mask. */
9091 if ((cond
& 0x1) == 0x0)
9093 unsigned int mask
= inst
.instruction
& 0x000f;
9095 if ((mask
& 0x7) == 0)
9096 /* no conversion needed */;
9097 else if ((mask
& 0x3) == 0)
9099 else if ((mask
& 0x1) == 0)
9104 inst
.instruction
&= 0xfff0;
9105 inst
.instruction
|= mask
;
9108 inst
.instruction
|= cond
<< 4;
9111 /* Helper function used for both push/pop and ldm/stm. */
9113 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9117 load
= (inst
.instruction
& (1 << 20)) != 0;
9119 if (mask
& (1 << 13))
9120 inst
.error
= _("SP not allowed in register list");
9123 if (mask
& (1 << 14)
9124 && mask
& (1 << 15))
9125 inst
.error
= _("LR and PC should not both be in register list");
9127 if ((mask
& (1 << base
)) != 0
9129 as_warn (_("base register should not be in register list "
9130 "when written back"));
9134 if (mask
& (1 << 15))
9135 inst
.error
= _("PC not allowed in register list");
9137 if (mask
& (1 << base
))
9138 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9141 if ((mask
& (mask
- 1)) == 0)
9143 /* Single register transfers implemented as str/ldr. */
9146 if (inst
.instruction
& (1 << 23))
9147 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9149 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9153 if (inst
.instruction
& (1 << 23))
9154 inst
.instruction
= 0x00800000; /* ia -> [base] */
9156 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9159 inst
.instruction
|= 0xf8400000;
9161 inst
.instruction
|= 0x00100000;
9163 mask
= ffs (mask
) - 1;
9167 inst
.instruction
|= WRITE_BACK
;
9169 inst
.instruction
|= mask
;
9170 inst
.instruction
|= base
<< 16;
9176 /* This really doesn't seem worth it. */
9177 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9178 _("expression too complex"));
9179 constraint (inst
.operands
[1].writeback
,
9180 _("Thumb load/store multiple does not support {reglist}^"));
9188 /* See if we can use a 16-bit instruction. */
9189 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9190 && inst
.size_req
!= 4
9191 && !(inst
.operands
[1].imm
& ~0xff))
9193 mask
= 1 << inst
.operands
[0].reg
;
9195 if (inst
.operands
[0].reg
<= 7
9196 && (inst
.instruction
== T_MNEM_stmia
9197 ? inst
.operands
[0].writeback
9198 : (inst
.operands
[0].writeback
9199 == !(inst
.operands
[1].imm
& mask
))))
9201 if (inst
.instruction
== T_MNEM_stmia
9202 && (inst
.operands
[1].imm
& mask
)
9203 && (inst
.operands
[1].imm
& (mask
- 1)))
9204 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9205 inst
.operands
[0].reg
);
9207 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9208 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9209 inst
.instruction
|= inst
.operands
[1].imm
;
9212 else if (inst
.operands
[0] .reg
== REG_SP
9213 && inst
.operands
[0].writeback
)
9215 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9216 ? T_MNEM_push
: T_MNEM_pop
);
9217 inst
.instruction
|= inst
.operands
[1].imm
;
9224 if (inst
.instruction
< 0xffff)
9225 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9227 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9228 inst
.operands
[0].writeback
);
9233 constraint (inst
.operands
[0].reg
> 7
9234 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9235 constraint (inst
.instruction
!= T_MNEM_ldmia
9236 && inst
.instruction
!= T_MNEM_stmia
,
9237 _("Thumb-2 instruction only valid in unified syntax"));
9238 if (inst
.instruction
== T_MNEM_stmia
)
9240 if (!inst
.operands
[0].writeback
)
9241 as_warn (_("this instruction will write back the base register"));
9242 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9243 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9244 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9245 inst
.operands
[0].reg
);
9249 if (!inst
.operands
[0].writeback
9250 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9251 as_warn (_("this instruction will write back the base register"));
9252 else if (inst
.operands
[0].writeback
9253 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9254 as_warn (_("this instruction will not write back the base register"));
9257 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9258 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9259 inst
.instruction
|= inst
.operands
[1].imm
;
9266 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9267 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9268 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9269 || inst
.operands
[1].negative
,
9272 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9273 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9274 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9280 if (!inst
.operands
[1].present
)
9282 constraint (inst
.operands
[0].reg
== REG_LR
,
9283 _("r14 not allowed as first register "
9284 "when second register is omitted"));
9285 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9287 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9290 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9291 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9292 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9298 unsigned long opcode
;
9301 opcode
= inst
.instruction
;
9304 if (!inst
.operands
[1].isreg
)
9306 if (opcode
<= 0xffff)
9307 inst
.instruction
= THUMB_OP32 (opcode
);
9308 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9311 if (inst
.operands
[1].isreg
9312 && !inst
.operands
[1].writeback
9313 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9314 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9316 && inst
.size_req
!= 4)
9318 /* Insn may have a 16-bit form. */
9319 Rn
= inst
.operands
[1].reg
;
9320 if (inst
.operands
[1].immisreg
)
9322 inst
.instruction
= THUMB_OP16 (opcode
);
9324 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9327 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9328 && opcode
!= T_MNEM_ldrsb
)
9329 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9330 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9337 if (inst
.reloc
.pc_rel
)
9338 opcode
= T_MNEM_ldr_pc2
;
9340 opcode
= T_MNEM_ldr_pc
;
9344 if (opcode
== T_MNEM_ldr
)
9345 opcode
= T_MNEM_ldr_sp
;
9347 opcode
= T_MNEM_str_sp
;
9349 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9353 inst
.instruction
= inst
.operands
[0].reg
;
9354 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9356 inst
.instruction
|= THUMB_OP16 (opcode
);
9357 if (inst
.size_req
== 2)
9358 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9360 inst
.relax
= opcode
;
9364 /* Definitely a 32-bit variant. */
9365 inst
.instruction
= THUMB_OP32 (opcode
);
9366 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9367 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9371 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9373 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9375 /* Only [Rn,Rm] is acceptable. */
9376 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9377 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9378 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9379 || inst
.operands
[1].negative
,
9380 _("Thumb does not support this addressing mode"));
9381 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9385 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9386 if (!inst
.operands
[1].isreg
)
9387 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9390 constraint (!inst
.operands
[1].preind
9391 || inst
.operands
[1].shifted
9392 || inst
.operands
[1].writeback
,
9393 _("Thumb does not support this addressing mode"));
9394 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9396 constraint (inst
.instruction
& 0x0600,
9397 _("byte or halfword not valid for base register"));
9398 constraint (inst
.operands
[1].reg
== REG_PC
9399 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9400 _("r15 based store not allowed"));
9401 constraint (inst
.operands
[1].immisreg
,
9402 _("invalid base register for register offset"));
9404 if (inst
.operands
[1].reg
== REG_PC
)
9405 inst
.instruction
= T_OPCODE_LDR_PC
;
9406 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9407 inst
.instruction
= T_OPCODE_LDR_SP
;
9409 inst
.instruction
= T_OPCODE_STR_SP
;
9411 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9412 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9416 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9417 if (!inst
.operands
[1].immisreg
)
9419 /* Immediate offset. */
9420 inst
.instruction
|= inst
.operands
[0].reg
;
9421 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9422 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9426 /* Register offset. */
9427 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9428 constraint (inst
.operands
[1].negative
,
9429 _("Thumb does not support this addressing mode"));
9432 switch (inst
.instruction
)
9434 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9435 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9436 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9437 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9438 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9439 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9440 case 0x5600 /* ldrsb */:
9441 case 0x5e00 /* ldrsh */: break;
9445 inst
.instruction
|= inst
.operands
[0].reg
;
9446 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9447 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9453 if (!inst
.operands
[1].present
)
9455 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9456 constraint (inst
.operands
[0].reg
== REG_LR
,
9457 _("r14 not allowed here"));
9459 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9460 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9461 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9467 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9468 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9474 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9475 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9476 inst
.instruction
|= inst
.operands
[2].reg
;
9477 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9483 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9484 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9485 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9486 inst
.instruction
|= inst
.operands
[3].reg
;
9494 int r0off
= (inst
.instruction
== T_MNEM_mov
9495 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9496 unsigned long opcode
;
9498 bfd_boolean low_regs
;
9500 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9501 opcode
= inst
.instruction
;
9502 if (current_it_mask
)
9503 narrow
= opcode
!= T_MNEM_movs
;
9505 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9506 if (inst
.size_req
== 4
9507 || inst
.operands
[1].shifted
)
9510 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9511 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
9512 && !inst
.operands
[1].shifted
9513 && inst
.operands
[0].reg
== REG_PC
9514 && inst
.operands
[1].reg
== REG_LR
)
9516 inst
.instruction
= T2_SUBS_PC_LR
;
9520 if (!inst
.operands
[1].isreg
)
9522 /* Immediate operand. */
9523 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9525 if (low_regs
&& narrow
)
9527 inst
.instruction
= THUMB_OP16 (opcode
);
9528 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9529 if (inst
.size_req
== 2)
9530 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9532 inst
.relax
= opcode
;
9536 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9537 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9538 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9539 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9542 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
9543 && (inst
.instruction
== T_MNEM_mov
9544 || inst
.instruction
== T_MNEM_movs
))
9546 /* Register shifts are encoded as separate shift instructions. */
9547 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
9549 if (current_it_mask
)
9554 if (inst
.size_req
== 4)
9557 if (!low_regs
|| inst
.operands
[1].imm
> 7)
9560 if (inst
.operands
[0].reg
!= inst
.operands
[1].reg
)
9563 switch (inst
.operands
[1].shift_kind
)
9566 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
9569 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
9572 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
9575 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
9581 inst
.instruction
= opcode
;
9584 inst
.instruction
|= inst
.operands
[0].reg
;
9585 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
9590 inst
.instruction
|= CONDS_BIT
;
9592 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9593 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9594 inst
.instruction
|= inst
.operands
[1].imm
;
9599 /* Some mov with immediate shift have narrow variants.
9600 Register shifts are handled above. */
9601 if (low_regs
&& inst
.operands
[1].shifted
9602 && (inst
.instruction
== T_MNEM_mov
9603 || inst
.instruction
== T_MNEM_movs
))
9605 if (current_it_mask
)
9606 narrow
= (inst
.instruction
== T_MNEM_mov
);
9608 narrow
= (inst
.instruction
== T_MNEM_movs
);
9613 switch (inst
.operands
[1].shift_kind
)
9615 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9616 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9617 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9618 default: narrow
= FALSE
; break;
9624 inst
.instruction
|= inst
.operands
[0].reg
;
9625 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9626 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9630 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9631 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9632 encode_thumb32_shifted_operand (1);
9636 switch (inst
.instruction
)
9639 inst
.instruction
= T_OPCODE_MOV_HR
;
9640 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9641 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9642 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9646 /* We know we have low registers at this point.
9647 Generate ADD Rd, Rs, #0. */
9648 inst
.instruction
= T_OPCODE_ADD_I3
;
9649 inst
.instruction
|= inst
.operands
[0].reg
;
9650 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9656 inst
.instruction
= T_OPCODE_CMP_LR
;
9657 inst
.instruction
|= inst
.operands
[0].reg
;
9658 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9662 inst
.instruction
= T_OPCODE_CMP_HR
;
9663 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9664 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9665 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9672 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9673 if (inst
.operands
[1].isreg
)
9675 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9677 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9678 since a MOV instruction produces unpredictable results. */
9679 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9680 inst
.instruction
= T_OPCODE_ADD_I3
;
9682 inst
.instruction
= T_OPCODE_CMP_LR
;
9684 inst
.instruction
|= inst
.operands
[0].reg
;
9685 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9689 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9690 inst
.instruction
= T_OPCODE_MOV_HR
;
9692 inst
.instruction
= T_OPCODE_CMP_HR
;
9698 constraint (inst
.operands
[0].reg
> 7,
9699 _("only lo regs allowed with immediate"));
9700 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9701 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9711 top
= (inst
.instruction
& 0x00800000) != 0;
9712 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9714 constraint (top
, _(":lower16: not allowed this instruction"));
9715 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9717 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9719 constraint (!top
, _(":upper16: not allowed this instruction"));
9720 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9723 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9724 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9726 imm
= inst
.reloc
.exp
.X_add_number
;
9727 inst
.instruction
|= (imm
& 0xf000) << 4;
9728 inst
.instruction
|= (imm
& 0x0800) << 15;
9729 inst
.instruction
|= (imm
& 0x0700) << 4;
9730 inst
.instruction
|= (imm
& 0x00ff);
9739 int r0off
= (inst
.instruction
== T_MNEM_mvn
9740 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9743 if (inst
.size_req
== 4
9744 || inst
.instruction
> 0xffff
9745 || inst
.operands
[1].shifted
9746 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9748 else if (inst
.instruction
== T_MNEM_cmn
)
9750 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9751 narrow
= (current_it_mask
== 0);
9753 narrow
= (current_it_mask
!= 0);
9755 if (!inst
.operands
[1].isreg
)
9757 /* For an immediate, we always generate a 32-bit opcode;
9758 section relaxation will shrink it later if possible. */
9759 if (inst
.instruction
< 0xffff)
9760 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9761 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9762 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9763 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9767 /* See if we can do this with a 16-bit instruction. */
9770 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9771 inst
.instruction
|= inst
.operands
[0].reg
;
9772 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9776 constraint (inst
.operands
[1].shifted
9777 && inst
.operands
[1].immisreg
,
9778 _("shift must be constant"));
9779 if (inst
.instruction
< 0xffff)
9780 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9781 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9782 encode_thumb32_shifted_operand (1);
9788 constraint (inst
.instruction
> 0xffff
9789 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9790 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9791 _("unshifted register required"));
9792 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9795 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9796 inst
.instruction
|= inst
.operands
[0].reg
;
9797 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9806 if (do_vfp_nsyn_mrs () == SUCCESS
)
9809 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9812 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
9813 _("selected processor does not support "
9814 "requested special purpose register"));
9818 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9819 _("selected processor does not support "
9820 "requested special purpose register %x"));
9821 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9822 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9823 _("'CPSR' or 'SPSR' expected"));
9826 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9827 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9828 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9836 if (do_vfp_nsyn_msr () == SUCCESS
)
9839 constraint (!inst
.operands
[1].isreg
,
9840 _("Thumb encoding does not support an immediate here"));
9841 flags
= inst
.operands
[0].imm
;
9844 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9845 _("selected processor does not support "
9846 "requested special purpose register"));
9850 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
9851 _("selected processor does not support "
9852 "requested special purpose register"));
9855 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9856 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9857 inst
.instruction
|= (flags
& 0xff);
9858 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9864 if (!inst
.operands
[2].present
)
9865 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9867 /* There is no 32-bit MULS and no 16-bit MUL. */
9868 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9870 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9871 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9872 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9873 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9877 constraint (!unified_syntax
9878 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9879 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9882 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9883 inst
.instruction
|= inst
.operands
[0].reg
;
9885 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9886 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9887 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9888 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9890 constraint (1, _("dest must overlap one source register"));
9897 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9898 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9899 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9900 inst
.instruction
|= inst
.operands
[3].reg
;
9902 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9903 as_tsktsk (_("rdhi and rdlo must be different"));
9911 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9913 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9914 inst
.instruction
|= inst
.operands
[0].imm
;
9918 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9919 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9924 constraint (inst
.operands
[0].present
,
9925 _("Thumb does not support NOP with hints"));
9926 inst
.instruction
= 0x46c0;
9937 if (THUMB_SETS_FLAGS (inst
.instruction
))
9938 narrow
= (current_it_mask
== 0);
9940 narrow
= (current_it_mask
!= 0);
9941 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9943 if (inst
.size_req
== 4)
9948 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9949 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9950 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9954 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9955 inst
.instruction
|= inst
.operands
[0].reg
;
9956 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9961 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9963 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9965 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9966 inst
.instruction
|= inst
.operands
[0].reg
;
9967 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9974 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9975 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9976 inst
.instruction
|= inst
.operands
[2].reg
;
9977 if (inst
.operands
[3].present
)
9979 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9980 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9981 _("expression too complex"));
9982 inst
.instruction
|= (val
& 0x1c) << 10;
9983 inst
.instruction
|= (val
& 0x03) << 6;
9990 if (!inst
.operands
[3].present
)
9991 inst
.instruction
&= ~0x00000020;
9998 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10002 do_t_push_pop (void)
10006 constraint (inst
.operands
[0].writeback
,
10007 _("push/pop do not support {reglist}^"));
10008 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10009 _("expression too complex"));
10011 mask
= inst
.operands
[0].imm
;
10012 if ((mask
& ~0xff) == 0)
10013 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10014 else if ((inst
.instruction
== T_MNEM_push
10015 && (mask
& ~0xff) == 1 << REG_LR
)
10016 || (inst
.instruction
== T_MNEM_pop
10017 && (mask
& ~0xff) == 1 << REG_PC
))
10019 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10020 inst
.instruction
|= THUMB_PP_PC_LR
;
10021 inst
.instruction
|= mask
& 0xff;
10023 else if (unified_syntax
)
10025 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10026 encode_thumb2_ldmstm (13, mask
, TRUE
);
10030 inst
.error
= _("invalid register list to push/pop instruction");
10038 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10039 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10045 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10046 && inst
.size_req
!= 4)
10048 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10049 inst
.instruction
|= inst
.operands
[0].reg
;
10050 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10052 else if (unified_syntax
)
10054 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10055 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10056 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10057 inst
.instruction
|= inst
.operands
[1].reg
;
10060 inst
.error
= BAD_HIREG
;
10068 Rd
= inst
.operands
[0].reg
;
10069 Rs
= (inst
.operands
[1].present
10070 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10071 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10073 inst
.instruction
|= Rd
<< 8;
10074 inst
.instruction
|= Rs
<< 16;
10075 if (!inst
.operands
[2].isreg
)
10077 bfd_boolean narrow
;
10079 if ((inst
.instruction
& 0x00100000) != 0)
10080 narrow
= (current_it_mask
== 0);
10082 narrow
= (current_it_mask
!= 0);
10084 if (Rd
> 7 || Rs
> 7)
10087 if (inst
.size_req
== 4 || !unified_syntax
)
10090 if (inst
.reloc
.exp
.X_op
!= O_constant
10091 || inst
.reloc
.exp
.X_add_number
!= 0)
10094 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10095 relaxation, but it doesn't seem worth the hassle. */
10098 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10099 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10100 inst
.instruction
|= Rs
<< 3;
10101 inst
.instruction
|= Rd
;
10105 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10106 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10110 encode_thumb32_shifted_operand (2);
10116 constraint (current_it_mask
, BAD_NOT_IT
);
10117 if (inst
.operands
[0].imm
)
10118 inst
.instruction
|= 0x8;
10124 if (!inst
.operands
[1].present
)
10125 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10127 if (unified_syntax
)
10129 bfd_boolean narrow
;
10132 switch (inst
.instruction
)
10135 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10137 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10139 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10141 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10145 if (THUMB_SETS_FLAGS (inst
.instruction
))
10146 narrow
= (current_it_mask
== 0);
10148 narrow
= (current_it_mask
!= 0);
10149 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10151 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10153 if (inst
.operands
[2].isreg
10154 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10155 || inst
.operands
[2].reg
> 7))
10157 if (inst
.size_req
== 4)
10162 if (inst
.operands
[2].isreg
)
10164 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10165 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10166 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10167 inst
.instruction
|= inst
.operands
[2].reg
;
10171 inst
.operands
[1].shifted
= 1;
10172 inst
.operands
[1].shift_kind
= shift_kind
;
10173 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10174 ? T_MNEM_movs
: T_MNEM_mov
);
10175 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10176 encode_thumb32_shifted_operand (1);
10177 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10178 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10183 if (inst
.operands
[2].isreg
)
10185 switch (shift_kind
)
10187 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10188 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10189 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10190 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10194 inst
.instruction
|= inst
.operands
[0].reg
;
10195 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10199 switch (shift_kind
)
10201 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10202 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10203 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10206 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10207 inst
.instruction
|= inst
.operands
[0].reg
;
10208 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10214 constraint (inst
.operands
[0].reg
> 7
10215 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10216 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10218 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10220 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10221 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10222 _("source1 and dest must be same register"));
10224 switch (inst
.instruction
)
10226 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10227 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10228 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10229 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10233 inst
.instruction
|= inst
.operands
[0].reg
;
10234 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10238 switch (inst
.instruction
)
10240 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10241 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10242 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10243 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10246 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10247 inst
.instruction
|= inst
.operands
[0].reg
;
10248 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10256 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10257 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10258 inst
.instruction
|= inst
.operands
[2].reg
;
10264 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10265 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10266 _("expression too complex"));
10267 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10268 inst
.instruction
|= (value
& 0xf000) >> 12;
10269 inst
.instruction
|= (value
& 0x0ff0);
10270 inst
.instruction
|= (value
& 0x000f) << 16;
10276 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10277 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10278 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10280 if (inst
.operands
[3].present
)
10282 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10283 _("expression too complex"));
10285 if (inst
.reloc
.exp
.X_add_number
!= 0)
10287 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10288 inst
.instruction
|= 0x00200000; /* sh bit */
10289 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10290 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10292 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10299 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10300 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10301 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10307 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10308 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10309 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10310 || inst
.operands
[2].negative
,
10313 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10314 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10315 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10316 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10322 if (!inst
.operands
[2].present
)
10323 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10325 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10326 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10327 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10328 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10331 inst
.instruction
|= inst
.operands
[0].reg
;
10332 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10333 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10334 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10340 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10341 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10342 inst
.instruction
|= inst
.operands
[2].reg
;
10343 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10349 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10350 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10351 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10353 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10354 inst
.instruction
|= inst
.operands
[0].reg
;
10355 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10357 else if (unified_syntax
)
10359 if (inst
.instruction
<= 0xffff)
10360 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10361 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10362 inst
.instruction
|= inst
.operands
[1].reg
;
10363 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10367 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10368 _("Thumb encoding does not support rotation"));
10369 constraint (1, BAD_HIREG
);
10376 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10384 half
= (inst
.instruction
& 0x10) != 0;
10385 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10386 constraint (inst
.operands
[0].immisreg
,
10387 _("instruction requires register index"));
10388 constraint (inst
.operands
[0].imm
== 15,
10389 _("PC is not a valid index register"));
10390 constraint (!half
&& inst
.operands
[0].shifted
,
10391 _("instruction does not allow shifted index"));
10392 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10398 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10399 inst
.instruction
|= inst
.operands
[1].imm
;
10400 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10402 if (inst
.operands
[3].present
)
10404 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10405 _("expression too complex"));
10406 if (inst
.reloc
.exp
.X_add_number
!= 0)
10408 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10409 inst
.instruction
|= 0x00200000; /* sh bit */
10411 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10412 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10414 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10421 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10422 inst
.instruction
|= inst
.operands
[1].imm
;
10423 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10426 /* Neon instruction encoder helpers. */
10428 /* Encodings for the different types for various Neon opcodes. */
10430 /* An "invalid" code for the following tables. */
10433 struct neon_tab_entry
10436 unsigned float_or_poly
;
10437 unsigned scalar_or_imm
;
10440 /* Map overloaded Neon opcodes to their respective encodings. */
10441 #define NEON_ENC_TAB \
10442 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10443 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10444 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10445 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10446 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10447 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10448 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10449 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10450 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10451 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10452 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10453 /* Register variants of the following two instructions are encoded as
10454 vcge / vcgt with the operands reversed. */ \
10455 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10456 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10457 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10458 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10459 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10460 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10461 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10462 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10463 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10464 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10465 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10466 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10467 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10468 X(vshl, 0x0000400, N_INV, 0x0800510), \
10469 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10470 X(vand, 0x0000110, N_INV, 0x0800030), \
10471 X(vbic, 0x0100110, N_INV, 0x0800030), \
10472 X(veor, 0x1000110, N_INV, N_INV), \
10473 X(vorn, 0x0300110, N_INV, 0x0800010), \
10474 X(vorr, 0x0200110, N_INV, 0x0800010), \
10475 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10476 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10477 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10478 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10479 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10480 X(vst1, 0x0000000, 0x0800000, N_INV), \
10481 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10482 X(vst2, 0x0000100, 0x0800100, N_INV), \
10483 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10484 X(vst3, 0x0000200, 0x0800200, N_INV), \
10485 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10486 X(vst4, 0x0000300, 0x0800300, N_INV), \
10487 X(vmovn, 0x1b20200, N_INV, N_INV), \
10488 X(vtrn, 0x1b20080, N_INV, N_INV), \
10489 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10490 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10491 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10492 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10493 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10494 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10495 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10496 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10497 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10501 #define X(OPC,I,F,S) N_MNEM_##OPC
10506 static const struct neon_tab_entry neon_enc_tab
[] =
10508 #define X(OPC,I,F,S) { (I), (F), (S) }
10513 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10514 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10515 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10516 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10517 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10518 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10519 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10520 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10521 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10522 #define NEON_ENC_SINGLE(X) \
10523 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10524 #define NEON_ENC_DOUBLE(X) \
10525 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10527 /* Define shapes for instruction operands. The following mnemonic characters
10528 are used in this table:
10530 F - VFP S<n> register
10531 D - Neon D<n> register
10532 Q - Neon Q<n> register
10536 L - D<n> register list
10538 This table is used to generate various data:
10539 - enumerations of the form NS_DDR to be used as arguments to
10541 - a table classifying shapes into single, double, quad, mixed.
10542 - a table used to drive neon_select_shape. */
10544 #define NEON_SHAPE_DEF \
10545 X(3, (D, D, D), DOUBLE), \
10546 X(3, (Q, Q, Q), QUAD), \
10547 X(3, (D, D, I), DOUBLE), \
10548 X(3, (Q, Q, I), QUAD), \
10549 X(3, (D, D, S), DOUBLE), \
10550 X(3, (Q, Q, S), QUAD), \
10551 X(2, (D, D), DOUBLE), \
10552 X(2, (Q, Q), QUAD), \
10553 X(2, (D, S), DOUBLE), \
10554 X(2, (Q, S), QUAD), \
10555 X(2, (D, R), DOUBLE), \
10556 X(2, (Q, R), QUAD), \
10557 X(2, (D, I), DOUBLE), \
10558 X(2, (Q, I), QUAD), \
10559 X(3, (D, L, D), DOUBLE), \
10560 X(2, (D, Q), MIXED), \
10561 X(2, (Q, D), MIXED), \
10562 X(3, (D, Q, I), MIXED), \
10563 X(3, (Q, D, I), MIXED), \
10564 X(3, (Q, D, D), MIXED), \
10565 X(3, (D, Q, Q), MIXED), \
10566 X(3, (Q, Q, D), MIXED), \
10567 X(3, (Q, D, S), MIXED), \
10568 X(3, (D, Q, S), MIXED), \
10569 X(4, (D, D, D, I), DOUBLE), \
10570 X(4, (Q, Q, Q, I), QUAD), \
10571 X(2, (F, F), SINGLE), \
10572 X(3, (F, F, F), SINGLE), \
10573 X(2, (F, I), SINGLE), \
10574 X(2, (F, D), MIXED), \
10575 X(2, (D, F), MIXED), \
10576 X(3, (F, F, I), MIXED), \
10577 X(4, (R, R, F, F), SINGLE), \
10578 X(4, (F, F, R, R), SINGLE), \
10579 X(3, (D, R, R), DOUBLE), \
10580 X(3, (R, R, D), DOUBLE), \
10581 X(2, (S, R), SINGLE), \
10582 X(2, (R, S), SINGLE), \
10583 X(2, (F, R), SINGLE), \
10584 X(2, (R, F), SINGLE)
10586 #define S2(A,B) NS_##A##B
10587 #define S3(A,B,C) NS_##A##B##C
10588 #define S4(A,B,C,D) NS_##A##B##C##D
10590 #define X(N, L, C) S##N L
10603 enum neon_shape_class
10611 #define X(N, L, C) SC_##C
10613 static enum neon_shape_class neon_shape_class
[] =
10631 /* Register widths of above. */
10632 static unsigned neon_shape_el_size
[] =
10643 struct neon_shape_info
10646 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10649 #define S2(A,B) { SE_##A, SE_##B }
10650 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10651 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10653 #define X(N, L, C) { N, S##N L }
10655 static struct neon_shape_info neon_shape_tab
[] =
10665 /* Bit masks used in type checking given instructions.
10666 'N_EQK' means the type must be the same as (or based on in some way) the key
10667 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10668 set, various other bits can be set as well in order to modify the meaning of
10669 the type constraint. */
10671 enum neon_type_mask
10693 N_KEY
= 0x100000, /* key element (main type specifier). */
10694 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10695 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10696 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10697 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10698 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10699 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10700 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10701 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10702 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10704 N_MAX_NONSPECIAL
= N_F64
10707 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10709 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10710 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10711 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10712 #define N_SUF_32 (N_SU_32 | N_F32)
10713 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10714 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10716 /* Pass this as the first type argument to neon_check_type to ignore types
10718 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10720 /* Select a "shape" for the current instruction (describing register types or
10721 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10722 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10723 function of operand parsing, so this function doesn't need to be called.
10724 Shapes should be listed in order of decreasing length. */
10726 static enum neon_shape
10727 neon_select_shape (enum neon_shape shape
, ...)
10730 enum neon_shape first_shape
= shape
;
10732 /* Fix missing optional operands. FIXME: we don't know at this point how
10733 many arguments we should have, so this makes the assumption that we have
10734 > 1. This is true of all current Neon opcodes, I think, but may not be
10735 true in the future. */
10736 if (!inst
.operands
[1].present
)
10737 inst
.operands
[1] = inst
.operands
[0];
10739 va_start (ap
, shape
);
10741 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10746 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10748 if (!inst
.operands
[j
].present
)
10754 switch (neon_shape_tab
[shape
].el
[j
])
10757 if (!(inst
.operands
[j
].isreg
10758 && inst
.operands
[j
].isvec
10759 && inst
.operands
[j
].issingle
10760 && !inst
.operands
[j
].isquad
))
10765 if (!(inst
.operands
[j
].isreg
10766 && inst
.operands
[j
].isvec
10767 && !inst
.operands
[j
].isquad
10768 && !inst
.operands
[j
].issingle
))
10773 if (!(inst
.operands
[j
].isreg
10774 && !inst
.operands
[j
].isvec
))
10779 if (!(inst
.operands
[j
].isreg
10780 && inst
.operands
[j
].isvec
10781 && inst
.operands
[j
].isquad
10782 && !inst
.operands
[j
].issingle
))
10787 if (!(!inst
.operands
[j
].isreg
10788 && !inst
.operands
[j
].isscalar
))
10793 if (!(!inst
.operands
[j
].isreg
10794 && inst
.operands
[j
].isscalar
))
10808 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10809 first_error (_("invalid instruction shape"));
10814 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10815 means the Q bit should be set). */
10818 neon_quad (enum neon_shape shape
)
10820 return neon_shape_class
[shape
] == SC_QUAD
;
10824 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10827 /* Allow modification to be made to types which are constrained to be
10828 based on the key element, based on bits set alongside N_EQK. */
10829 if ((typebits
& N_EQK
) != 0)
10831 if ((typebits
& N_HLF
) != 0)
10833 else if ((typebits
& N_DBL
) != 0)
10835 if ((typebits
& N_SGN
) != 0)
10836 *g_type
= NT_signed
;
10837 else if ((typebits
& N_UNS
) != 0)
10838 *g_type
= NT_unsigned
;
10839 else if ((typebits
& N_INT
) != 0)
10840 *g_type
= NT_integer
;
10841 else if ((typebits
& N_FLT
) != 0)
10842 *g_type
= NT_float
;
10843 else if ((typebits
& N_SIZ
) != 0)
10844 *g_type
= NT_untyped
;
10848 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10849 operand type, i.e. the single type specified in a Neon instruction when it
10850 is the only one given. */
10852 static struct neon_type_el
10853 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10855 struct neon_type_el dest
= *key
;
10857 assert ((thisarg
& N_EQK
) != 0);
10859 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10864 /* Convert Neon type and size into compact bitmask representation. */
10866 static enum neon_type_mask
10867 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10874 case 8: return N_8
;
10875 case 16: return N_16
;
10876 case 32: return N_32
;
10877 case 64: return N_64
;
10885 case 8: return N_I8
;
10886 case 16: return N_I16
;
10887 case 32: return N_I32
;
10888 case 64: return N_I64
;
10896 case 32: return N_F32
;
10897 case 64: return N_F64
;
10905 case 8: return N_P8
;
10906 case 16: return N_P16
;
10914 case 8: return N_S8
;
10915 case 16: return N_S16
;
10916 case 32: return N_S32
;
10917 case 64: return N_S64
;
10925 case 8: return N_U8
;
10926 case 16: return N_U16
;
10927 case 32: return N_U32
;
10928 case 64: return N_U64
;
10939 /* Convert compact Neon bitmask type representation to a type and size. Only
10940 handles the case where a single bit is set in the mask. */
10943 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10944 enum neon_type_mask mask
)
10946 if ((mask
& N_EQK
) != 0)
10949 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10951 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10953 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10955 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10960 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10962 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10963 *type
= NT_unsigned
;
10964 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10965 *type
= NT_integer
;
10966 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10967 *type
= NT_untyped
;
10968 else if ((mask
& (N_P8
| N_P16
)) != 0)
10970 else if ((mask
& (N_F32
| N_F64
)) != 0)
10978 /* Modify a bitmask of allowed types. This is only needed for type
10982 modify_types_allowed (unsigned allowed
, unsigned mods
)
10985 enum neon_el_type type
;
10991 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10993 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10995 neon_modify_type_size (mods
, &type
, &size
);
10996 destmask
|= type_chk_of_el_type (type
, size
);
11003 /* Check type and return type classification.
11004 The manual states (paraphrase): If one datatype is given, it indicates the
11006 - the second operand, if there is one
11007 - the operand, if there is no second operand
11008 - the result, if there are no operands.
11009 This isn't quite good enough though, so we use a concept of a "key" datatype
11010 which is set on a per-instruction basis, which is the one which matters when
11011 only one data type is written.
11012 Note: this function has side-effects (e.g. filling in missing operands). All
11013 Neon instructions should call it before performing bit encoding. */
11015 static struct neon_type_el
11016 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11019 unsigned i
, pass
, key_el
= 0;
11020 unsigned types
[NEON_MAX_TYPE_ELS
];
11021 enum neon_el_type k_type
= NT_invtype
;
11022 unsigned k_size
= -1u;
11023 struct neon_type_el badtype
= {NT_invtype
, -1};
11024 unsigned key_allowed
= 0;
11026 /* Optional registers in Neon instructions are always (not) in operand 1.
11027 Fill in the missing operand here, if it was omitted. */
11028 if (els
> 1 && !inst
.operands
[1].present
)
11029 inst
.operands
[1] = inst
.operands
[0];
11031 /* Suck up all the varargs. */
11033 for (i
= 0; i
< els
; i
++)
11035 unsigned thisarg
= va_arg (ap
, unsigned);
11036 if (thisarg
== N_IGNORE_TYPE
)
11041 types
[i
] = thisarg
;
11042 if ((thisarg
& N_KEY
) != 0)
11047 if (inst
.vectype
.elems
> 0)
11048 for (i
= 0; i
< els
; i
++)
11049 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11051 first_error (_("types specified in both the mnemonic and operands"));
11055 /* Duplicate inst.vectype elements here as necessary.
11056 FIXME: No idea if this is exactly the same as the ARM assembler,
11057 particularly when an insn takes one register and one non-register
11059 if (inst
.vectype
.elems
== 1 && els
> 1)
11062 inst
.vectype
.elems
= els
;
11063 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11064 for (j
= 0; j
< els
; j
++)
11066 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11069 else if (inst
.vectype
.elems
== 0 && els
> 0)
11072 /* No types were given after the mnemonic, so look for types specified
11073 after each operand. We allow some flexibility here; as long as the
11074 "key" operand has a type, we can infer the others. */
11075 for (j
= 0; j
< els
; j
++)
11076 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11077 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11079 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11081 for (j
= 0; j
< els
; j
++)
11082 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11083 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11088 first_error (_("operand types can't be inferred"));
11092 else if (inst
.vectype
.elems
!= els
)
11094 first_error (_("type specifier has the wrong number of parts"));
11098 for (pass
= 0; pass
< 2; pass
++)
11100 for (i
= 0; i
< els
; i
++)
11102 unsigned thisarg
= types
[i
];
11103 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11104 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11105 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11106 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11108 /* Decay more-specific signed & unsigned types to sign-insensitive
11109 integer types if sign-specific variants are unavailable. */
11110 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11111 && (types_allowed
& N_SU_ALL
) == 0)
11112 g_type
= NT_integer
;
11114 /* If only untyped args are allowed, decay any more specific types to
11115 them. Some instructions only care about signs for some element
11116 sizes, so handle that properly. */
11117 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11118 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11119 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11120 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11121 g_type
= NT_untyped
;
11125 if ((thisarg
& N_KEY
) != 0)
11129 key_allowed
= thisarg
& ~N_KEY
;
11134 if ((thisarg
& N_VFP
) != 0)
11136 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11137 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11139 /* In VFP mode, operands must match register widths. If we
11140 have a key operand, use its width, else use the width of
11141 the current operand. */
11147 if (regwidth
!= match
)
11149 first_error (_("operand size must match register width"));
11154 if ((thisarg
& N_EQK
) == 0)
11156 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11158 if ((given_type
& types_allowed
) == 0)
11160 first_error (_("bad type in Neon instruction"));
11166 enum neon_el_type mod_k_type
= k_type
;
11167 unsigned mod_k_size
= k_size
;
11168 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11169 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11171 first_error (_("inconsistent types in Neon instruction"));
11179 return inst
.vectype
.el
[key_el
];
11182 /* Neon-style VFP instruction forwarding. */
11184 /* Thumb VFP instructions have 0xE in the condition field. */
11187 do_vfp_cond_or_thumb (void)
11190 inst
.instruction
|= 0xe0000000;
11192 inst
.instruction
|= inst
.cond
<< 28;
11195 /* Look up and encode a simple mnemonic, for use as a helper function for the
11196 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11197 etc. It is assumed that operand parsing has already been done, and that the
11198 operands are in the form expected by the given opcode (this isn't necessarily
11199 the same as the form in which they were parsed, hence some massaging must
11200 take place before this function is called).
11201 Checks current arch version against that in the looked-up opcode. */
11204 do_vfp_nsyn_opcode (const char *opname
)
11206 const struct asm_opcode
*opcode
;
11208 opcode
= hash_find (arm_ops_hsh
, opname
);
11213 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11214 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11219 inst
.instruction
= opcode
->tvalue
;
11220 opcode
->tencode ();
11224 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11225 opcode
->aencode ();
11230 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11232 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11237 do_vfp_nsyn_opcode ("fadds");
11239 do_vfp_nsyn_opcode ("fsubs");
11244 do_vfp_nsyn_opcode ("faddd");
11246 do_vfp_nsyn_opcode ("fsubd");
11250 /* Check operand types to see if this is a VFP instruction, and if so call
11254 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11256 enum neon_shape rs
;
11257 struct neon_type_el et
;
11262 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11263 et
= neon_check_type (2, rs
,
11264 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11268 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11269 et
= neon_check_type (3, rs
,
11270 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11277 if (et
.type
!= NT_invtype
)
11289 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11291 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11296 do_vfp_nsyn_opcode ("fmacs");
11298 do_vfp_nsyn_opcode ("fmscs");
11303 do_vfp_nsyn_opcode ("fmacd");
11305 do_vfp_nsyn_opcode ("fmscd");
11310 do_vfp_nsyn_mul (enum neon_shape rs
)
11313 do_vfp_nsyn_opcode ("fmuls");
11315 do_vfp_nsyn_opcode ("fmuld");
11319 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11321 int is_neg
= (inst
.instruction
& 0x80) != 0;
11322 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11327 do_vfp_nsyn_opcode ("fnegs");
11329 do_vfp_nsyn_opcode ("fabss");
11334 do_vfp_nsyn_opcode ("fnegd");
11336 do_vfp_nsyn_opcode ("fabsd");
11340 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11341 insns belong to Neon, and are handled elsewhere. */
11344 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11346 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11350 do_vfp_nsyn_opcode ("fldmdbs");
11352 do_vfp_nsyn_opcode ("fldmias");
11357 do_vfp_nsyn_opcode ("fstmdbs");
11359 do_vfp_nsyn_opcode ("fstmias");
11364 do_vfp_nsyn_sqrt (void)
11366 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11367 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11370 do_vfp_nsyn_opcode ("fsqrts");
11372 do_vfp_nsyn_opcode ("fsqrtd");
11376 do_vfp_nsyn_div (void)
11378 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11379 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11380 N_F32
| N_F64
| N_KEY
| N_VFP
);
11383 do_vfp_nsyn_opcode ("fdivs");
11385 do_vfp_nsyn_opcode ("fdivd");
11389 do_vfp_nsyn_nmul (void)
11391 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11392 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11393 N_F32
| N_F64
| N_KEY
| N_VFP
);
11397 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11398 do_vfp_sp_dyadic ();
11402 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11403 do_vfp_dp_rd_rn_rm ();
11405 do_vfp_cond_or_thumb ();
11409 do_vfp_nsyn_cmp (void)
11411 if (inst
.operands
[1].isreg
)
11413 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11414 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11418 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11419 do_vfp_sp_monadic ();
11423 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11424 do_vfp_dp_rd_rm ();
11429 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11430 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11432 switch (inst
.instruction
& 0x0fffffff)
11435 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11438 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11446 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11447 do_vfp_sp_compare_z ();
11451 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11455 do_vfp_cond_or_thumb ();
11459 nsyn_insert_sp (void)
11461 inst
.operands
[1] = inst
.operands
[0];
11462 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11463 inst
.operands
[0].reg
= 13;
11464 inst
.operands
[0].isreg
= 1;
11465 inst
.operands
[0].writeback
= 1;
11466 inst
.operands
[0].present
= 1;
11470 do_vfp_nsyn_push (void)
11473 if (inst
.operands
[1].issingle
)
11474 do_vfp_nsyn_opcode ("fstmdbs");
11476 do_vfp_nsyn_opcode ("fstmdbd");
11480 do_vfp_nsyn_pop (void)
11483 if (inst
.operands
[1].issingle
)
11484 do_vfp_nsyn_opcode ("fldmias");
11486 do_vfp_nsyn_opcode ("fldmiad");
11489 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11490 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11493 neon_dp_fixup (unsigned i
)
11497 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11511 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11515 neon_logbits (unsigned x
)
11517 return ffs (x
) - 4;
11520 #define LOW4(R) ((R) & 0xf)
11521 #define HI1(R) (((R) >> 4) & 1)
11523 /* Encode insns with bit pattern:
11525 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11526 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11528 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11529 different meaning for some instruction. */
11532 neon_three_same (int isquad
, int ubit
, int size
)
11534 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11535 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11536 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11537 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11538 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11539 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11540 inst
.instruction
|= (isquad
!= 0) << 6;
11541 inst
.instruction
|= (ubit
!= 0) << 24;
11543 inst
.instruction
|= neon_logbits (size
) << 20;
11545 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11548 /* Encode instructions of the form:
11550 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11551 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11553 Don't write size if SIZE == -1. */
11556 neon_two_same (int qbit
, int ubit
, int size
)
11558 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11559 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11560 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11561 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11562 inst
.instruction
|= (qbit
!= 0) << 6;
11563 inst
.instruction
|= (ubit
!= 0) << 24;
11566 inst
.instruction
|= neon_logbits (size
) << 18;
11568 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11571 /* Neon instruction encoders, in approximate order of appearance. */
11574 do_neon_dyadic_i_su (void)
11576 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11577 struct neon_type_el et
= neon_check_type (3, rs
,
11578 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11579 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11583 do_neon_dyadic_i64_su (void)
11585 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11586 struct neon_type_el et
= neon_check_type (3, rs
,
11587 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11588 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11592 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11595 unsigned size
= et
.size
>> 3;
11596 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11597 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11598 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11599 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11600 inst
.instruction
|= (isquad
!= 0) << 6;
11601 inst
.instruction
|= immbits
<< 16;
11602 inst
.instruction
|= (size
>> 3) << 7;
11603 inst
.instruction
|= (size
& 0x7) << 19;
11605 inst
.instruction
|= (uval
!= 0) << 24;
11607 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11611 do_neon_shl_imm (void)
11613 if (!inst
.operands
[2].isreg
)
11615 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11616 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11617 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11618 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11622 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11623 struct neon_type_el et
= neon_check_type (3, rs
,
11624 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11627 /* VSHL/VQSHL 3-register variants have syntax such as:
11629 whereas other 3-register operations encoded by neon_three_same have
11632 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11634 tmp
= inst
.operands
[2].reg
;
11635 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11636 inst
.operands
[1].reg
= tmp
;
11637 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11638 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11643 do_neon_qshl_imm (void)
11645 if (!inst
.operands
[2].isreg
)
11647 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11648 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11650 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11651 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11652 inst
.operands
[2].imm
);
11656 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11657 struct neon_type_el et
= neon_check_type (3, rs
,
11658 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11661 /* See note in do_neon_shl_imm. */
11662 tmp
= inst
.operands
[2].reg
;
11663 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11664 inst
.operands
[1].reg
= tmp
;
11665 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11666 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11671 do_neon_rshl (void)
11673 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11674 struct neon_type_el et
= neon_check_type (3, rs
,
11675 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11678 tmp
= inst
.operands
[2].reg
;
11679 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11680 inst
.operands
[1].reg
= tmp
;
11681 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11685 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11687 /* Handle .I8 pseudo-instructions. */
11690 /* Unfortunately, this will make everything apart from zero out-of-range.
11691 FIXME is this the intended semantics? There doesn't seem much point in
11692 accepting .I8 if so. */
11693 immediate
|= immediate
<< 8;
11699 if (immediate
== (immediate
& 0x000000ff))
11701 *immbits
= immediate
;
11704 else if (immediate
== (immediate
& 0x0000ff00))
11706 *immbits
= immediate
>> 8;
11709 else if (immediate
== (immediate
& 0x00ff0000))
11711 *immbits
= immediate
>> 16;
11714 else if (immediate
== (immediate
& 0xff000000))
11716 *immbits
= immediate
>> 24;
11719 if ((immediate
& 0xffff) != (immediate
>> 16))
11720 goto bad_immediate
;
11721 immediate
&= 0xffff;
11724 if (immediate
== (immediate
& 0x000000ff))
11726 *immbits
= immediate
;
11729 else if (immediate
== (immediate
& 0x0000ff00))
11731 *immbits
= immediate
>> 8;
11736 first_error (_("immediate value out of range"));
11740 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11744 neon_bits_same_in_bytes (unsigned imm
)
11746 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11747 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11748 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11749 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11752 /* For immediate of above form, return 0bABCD. */
11755 neon_squash_bits (unsigned imm
)
11757 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11758 | ((imm
& 0x01000000) >> 21);
11761 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11764 neon_qfloat_bits (unsigned imm
)
11766 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11769 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11770 the instruction. *OP is passed as the initial value of the op field, and
11771 may be set to a different value depending on the constant (i.e.
11772 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11773 MVN). If the immediate looks like a repeated pattern then also
11774 try smaller element sizes. */
11777 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
11778 unsigned *immbits
, int *op
, int size
,
11779 enum neon_el_type type
)
11781 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11783 if (type
== NT_float
&& !float_p
)
11786 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11788 if (size
!= 32 || *op
== 1)
11790 *immbits
= neon_qfloat_bits (immlo
);
11796 if (neon_bits_same_in_bytes (immhi
)
11797 && neon_bits_same_in_bytes (immlo
))
11801 *immbits
= (neon_squash_bits (immhi
) << 4)
11802 | neon_squash_bits (immlo
);
11807 if (immhi
!= immlo
)
11813 if (immlo
== (immlo
& 0x000000ff))
11818 else if (immlo
== (immlo
& 0x0000ff00))
11820 *immbits
= immlo
>> 8;
11823 else if (immlo
== (immlo
& 0x00ff0000))
11825 *immbits
= immlo
>> 16;
11828 else if (immlo
== (immlo
& 0xff000000))
11830 *immbits
= immlo
>> 24;
11833 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11835 *immbits
= (immlo
>> 8) & 0xff;
11838 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11840 *immbits
= (immlo
>> 16) & 0xff;
11844 if ((immlo
& 0xffff) != (immlo
>> 16))
11851 if (immlo
== (immlo
& 0x000000ff))
11856 else if (immlo
== (immlo
& 0x0000ff00))
11858 *immbits
= immlo
>> 8;
11862 if ((immlo
& 0xff) != (immlo
>> 8))
11867 if (immlo
== (immlo
& 0x000000ff))
11869 /* Don't allow MVN with 8-bit immediate. */
11879 /* Write immediate bits [7:0] to the following locations:
11881 |28/24|23 19|18 16|15 4|3 0|
11882 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11884 This function is used by VMOV/VMVN/VORR/VBIC. */
11887 neon_write_immbits (unsigned immbits
)
11889 inst
.instruction
|= immbits
& 0xf;
11890 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11891 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11894 /* Invert low-order SIZE bits of XHI:XLO. */
11897 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11899 unsigned immlo
= xlo
? *xlo
: 0;
11900 unsigned immhi
= xhi
? *xhi
: 0;
11905 immlo
= (~immlo
) & 0xff;
11909 immlo
= (~immlo
) & 0xffff;
11913 immhi
= (~immhi
) & 0xffffffff;
11914 /* fall through. */
11917 immlo
= (~immlo
) & 0xffffffff;
11932 do_neon_logic (void)
11934 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11936 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11937 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11938 /* U bit and size field were set as part of the bitmask. */
11939 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11940 neon_three_same (neon_quad (rs
), 0, -1);
11944 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11945 struct neon_type_el et
= neon_check_type (2, rs
,
11946 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11947 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11951 if (et
.type
== NT_invtype
)
11954 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11956 immbits
= inst
.operands
[1].imm
;
11959 /* .i64 is a pseudo-op, so the immediate must be a repeating
11961 if (immbits
!= (inst
.operands
[1].regisimm
?
11962 inst
.operands
[1].reg
: 0))
11964 /* Set immbits to an invalid constant. */
11965 immbits
= 0xdeadbeef;
11972 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11976 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11980 /* Pseudo-instruction for VBIC. */
11981 neon_invert_size (&immbits
, 0, et
.size
);
11982 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11986 /* Pseudo-instruction for VORR. */
11987 neon_invert_size (&immbits
, 0, et
.size
);
11988 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11998 inst
.instruction
|= neon_quad (rs
) << 6;
11999 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12000 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12001 inst
.instruction
|= cmode
<< 8;
12002 neon_write_immbits (immbits
);
12004 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12009 do_neon_bitfield (void)
12011 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12012 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12013 neon_three_same (neon_quad (rs
), 0, -1);
12017 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12020 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12021 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12023 if (et
.type
== NT_float
)
12025 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12026 neon_three_same (neon_quad (rs
), 0, -1);
12030 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12031 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12036 do_neon_dyadic_if_su (void)
12038 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12042 do_neon_dyadic_if_su_d (void)
12044 /* This version only allow D registers, but that constraint is enforced during
12045 operand parsing so we don't need to do anything extra here. */
12046 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12050 do_neon_dyadic_if_i_d (void)
12052 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12053 affected if we specify unsigned args. */
12054 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12057 enum vfp_or_neon_is_neon_bits
12060 NEON_CHECK_ARCH
= 2
12063 /* Call this function if an instruction which may have belonged to the VFP or
12064 Neon instruction sets, but turned out to be a Neon instruction (due to the
12065 operand types involved, etc.). We have to check and/or fix-up a couple of
12068 - Make sure the user hasn't attempted to make a Neon instruction
12070 - Alter the value in the condition code field if necessary.
12071 - Make sure that the arch supports Neon instructions.
12073 Which of these operations take place depends on bits from enum
12074 vfp_or_neon_is_neon_bits.
12076 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12077 current instruction's condition is COND_ALWAYS, the condition field is
12078 changed to inst.uncond_value. This is necessary because instructions shared
12079 between VFP and Neon may be conditional for the VFP variants only, and the
12080 unconditional Neon version must have, e.g., 0xF in the condition field. */
12083 vfp_or_neon_is_neon (unsigned check
)
12085 /* Conditions are always legal in Thumb mode (IT blocks). */
12086 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12088 if (inst
.cond
!= COND_ALWAYS
)
12090 first_error (_(BAD_COND
));
12093 if (inst
.uncond_value
!= -1)
12094 inst
.instruction
|= inst
.uncond_value
<< 28;
12097 if ((check
& NEON_CHECK_ARCH
)
12098 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12100 first_error (_(BAD_FPU
));
12108 do_neon_addsub_if_i (void)
12110 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12113 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12116 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12117 affected if we specify unsigned args. */
12118 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12121 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12123 V<op> A,B (A is operand 0, B is operand 2)
12128 so handle that case specially. */
12131 neon_exchange_operands (void)
12133 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12134 if (inst
.operands
[1].present
)
12136 /* Swap operands[1] and operands[2]. */
12137 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12138 inst
.operands
[1] = inst
.operands
[2];
12139 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12143 inst
.operands
[1] = inst
.operands
[2];
12144 inst
.operands
[2] = inst
.operands
[0];
12149 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12151 if (inst
.operands
[2].isreg
)
12154 neon_exchange_operands ();
12155 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12159 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12160 struct neon_type_el et
= neon_check_type (2, rs
,
12161 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12163 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12164 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12165 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12166 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12167 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12168 inst
.instruction
|= neon_quad (rs
) << 6;
12169 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12170 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12172 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12179 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12183 do_neon_cmp_inv (void)
12185 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12191 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12194 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12195 scalars, which are encoded in 5 bits, M : Rm.
12196 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12197 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12201 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12203 unsigned regno
= NEON_SCALAR_REG (scalar
);
12204 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12209 if (regno
> 7 || elno
> 3)
12211 return regno
| (elno
<< 3);
12214 if (regno
> 15 || elno
> 1)
12216 return regno
| (elno
<< 4);
12220 first_error (_("scalar out of range for multiply instruction"));
12226 /* Encode multiply / multiply-accumulate scalar instructions. */
12229 neon_mul_mac (struct neon_type_el et
, int ubit
)
12233 /* Give a more helpful error message if we have an invalid type. */
12234 if (et
.type
== NT_invtype
)
12237 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12238 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12239 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12240 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12241 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12242 inst
.instruction
|= LOW4 (scalar
);
12243 inst
.instruction
|= HI1 (scalar
) << 5;
12244 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12245 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12246 inst
.instruction
|= (ubit
!= 0) << 24;
12248 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12252 do_neon_mac_maybe_scalar (void)
12254 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12257 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12260 if (inst
.operands
[2].isscalar
)
12262 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12263 struct neon_type_el et
= neon_check_type (3, rs
,
12264 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12265 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12266 neon_mul_mac (et
, neon_quad (rs
));
12270 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12271 affected if we specify unsigned args. */
12272 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12279 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12280 struct neon_type_el et
= neon_check_type (3, rs
,
12281 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12282 neon_three_same (neon_quad (rs
), 0, et
.size
);
12285 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12286 same types as the MAC equivalents. The polynomial type for this instruction
12287 is encoded the same as the integer type. */
12292 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12295 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12298 if (inst
.operands
[2].isscalar
)
12299 do_neon_mac_maybe_scalar ();
12301 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12305 do_neon_qdmulh (void)
12307 if (inst
.operands
[2].isscalar
)
12309 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12310 struct neon_type_el et
= neon_check_type (3, rs
,
12311 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12312 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12313 neon_mul_mac (et
, neon_quad (rs
));
12317 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12318 struct neon_type_el et
= neon_check_type (3, rs
,
12319 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12320 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12321 /* The U bit (rounding) comes from bit mask. */
12322 neon_three_same (neon_quad (rs
), 0, et
.size
);
12327 do_neon_fcmp_absolute (void)
12329 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12330 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12331 /* Size field comes from bit mask. */
12332 neon_three_same (neon_quad (rs
), 1, -1);
12336 do_neon_fcmp_absolute_inv (void)
12338 neon_exchange_operands ();
12339 do_neon_fcmp_absolute ();
12343 do_neon_step (void)
12345 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12346 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12347 neon_three_same (neon_quad (rs
), 0, -1);
12351 do_neon_abs_neg (void)
12353 enum neon_shape rs
;
12354 struct neon_type_el et
;
12356 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12359 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12362 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12363 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12365 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12366 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12367 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12368 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12369 inst
.instruction
|= neon_quad (rs
) << 6;
12370 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12371 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12373 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12379 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12380 struct neon_type_el et
= neon_check_type (2, rs
,
12381 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12382 int imm
= inst
.operands
[2].imm
;
12383 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12384 _("immediate out of range for insert"));
12385 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12391 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12392 struct neon_type_el et
= neon_check_type (2, rs
,
12393 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12394 int imm
= inst
.operands
[2].imm
;
12395 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12396 _("immediate out of range for insert"));
12397 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12401 do_neon_qshlu_imm (void)
12403 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12404 struct neon_type_el et
= neon_check_type (2, rs
,
12405 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12406 int imm
= inst
.operands
[2].imm
;
12407 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12408 _("immediate out of range for shift"));
12409 /* Only encodes the 'U present' variant of the instruction.
12410 In this case, signed types have OP (bit 8) set to 0.
12411 Unsigned types have OP set to 1. */
12412 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12413 /* The rest of the bits are the same as other immediate shifts. */
12414 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12418 do_neon_qmovn (void)
12420 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12421 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12422 /* Saturating move where operands can be signed or unsigned, and the
12423 destination has the same signedness. */
12424 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12425 if (et
.type
== NT_unsigned
)
12426 inst
.instruction
|= 0xc0;
12428 inst
.instruction
|= 0x80;
12429 neon_two_same (0, 1, et
.size
/ 2);
12433 do_neon_qmovun (void)
12435 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12436 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12437 /* Saturating move with unsigned results. Operands must be signed. */
12438 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12439 neon_two_same (0, 1, et
.size
/ 2);
12443 do_neon_rshift_sat_narrow (void)
12445 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12446 or unsigned. If operands are unsigned, results must also be unsigned. */
12447 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12448 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12449 int imm
= inst
.operands
[2].imm
;
12450 /* This gets the bounds check, size encoding and immediate bits calculation
12454 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12455 VQMOVN.I<size> <Dd>, <Qm>. */
12458 inst
.operands
[2].present
= 0;
12459 inst
.instruction
= N_MNEM_vqmovn
;
12464 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12465 _("immediate out of range"));
12466 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12470 do_neon_rshift_sat_narrow_u (void)
12472 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12473 or unsigned. If operands are unsigned, results must also be unsigned. */
12474 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12475 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12476 int imm
= inst
.operands
[2].imm
;
12477 /* This gets the bounds check, size encoding and immediate bits calculation
12481 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12482 VQMOVUN.I<size> <Dd>, <Qm>. */
12485 inst
.operands
[2].present
= 0;
12486 inst
.instruction
= N_MNEM_vqmovun
;
12491 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12492 _("immediate out of range"));
12493 /* FIXME: The manual is kind of unclear about what value U should have in
12494 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12496 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12500 do_neon_movn (void)
12502 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12503 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12504 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12505 neon_two_same (0, 1, et
.size
/ 2);
12509 do_neon_rshift_narrow (void)
12511 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12512 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12513 int imm
= inst
.operands
[2].imm
;
12514 /* This gets the bounds check, size encoding and immediate bits calculation
12518 /* If immediate is zero then we are a pseudo-instruction for
12519 VMOVN.I<size> <Dd>, <Qm> */
12522 inst
.operands
[2].present
= 0;
12523 inst
.instruction
= N_MNEM_vmovn
;
12528 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12529 _("immediate out of range for narrowing operation"));
12530 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12534 do_neon_shll (void)
12536 /* FIXME: Type checking when lengthening. */
12537 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12538 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12539 unsigned imm
= inst
.operands
[2].imm
;
12541 if (imm
== et
.size
)
12543 /* Maximum shift variant. */
12544 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12545 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12546 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12547 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12548 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12549 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12551 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12555 /* A more-specific type check for non-max versions. */
12556 et
= neon_check_type (2, NS_QDI
,
12557 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12558 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12559 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12563 /* Check the various types for the VCVT instruction, and return which version
12564 the current instruction is. */
12567 neon_cvt_flavour (enum neon_shape rs
)
12569 #define CVT_VAR(C,X,Y) \
12570 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12571 if (et.type != NT_invtype) \
12573 inst.error = NULL; \
12576 struct neon_type_el et
;
12577 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12578 || rs
== NS_FF
) ? N_VFP
: 0;
12579 /* The instruction versions which take an immediate take one register
12580 argument, which is extended to the width of the full register. Thus the
12581 "source" and "destination" registers must have the same width. Hack that
12582 here by making the size equal to the key (wider, in this case) operand. */
12583 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12585 CVT_VAR (0, N_S32
, N_F32
);
12586 CVT_VAR (1, N_U32
, N_F32
);
12587 CVT_VAR (2, N_F32
, N_S32
);
12588 CVT_VAR (3, N_F32
, N_U32
);
12592 /* VFP instructions. */
12593 CVT_VAR (4, N_F32
, N_F64
);
12594 CVT_VAR (5, N_F64
, N_F32
);
12595 CVT_VAR (6, N_S32
, N_F64
| key
);
12596 CVT_VAR (7, N_U32
, N_F64
| key
);
12597 CVT_VAR (8, N_F64
| key
, N_S32
);
12598 CVT_VAR (9, N_F64
| key
, N_U32
);
12599 /* VFP instructions with bitshift. */
12600 CVT_VAR (10, N_F32
| key
, N_S16
);
12601 CVT_VAR (11, N_F32
| key
, N_U16
);
12602 CVT_VAR (12, N_F64
| key
, N_S16
);
12603 CVT_VAR (13, N_F64
| key
, N_U16
);
12604 CVT_VAR (14, N_S16
, N_F32
| key
);
12605 CVT_VAR (15, N_U16
, N_F32
| key
);
12606 CVT_VAR (16, N_S16
, N_F64
| key
);
12607 CVT_VAR (17, N_U16
, N_F64
| key
);
12613 /* Neon-syntax VFP conversions. */
12616 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12618 const char *opname
= 0;
12620 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12622 /* Conversions with immediate bitshift. */
12623 const char *enc
[] =
12645 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12647 opname
= enc
[flavour
];
12648 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12649 _("operands 0 and 1 must be the same register"));
12650 inst
.operands
[1] = inst
.operands
[2];
12651 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12656 /* Conversions without bitshift. */
12657 const char *enc
[] =
12671 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12672 opname
= enc
[flavour
];
12676 do_vfp_nsyn_opcode (opname
);
12680 do_vfp_nsyn_cvtz (void)
12682 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12683 int flavour
= neon_cvt_flavour (rs
);
12684 const char *enc
[] =
12696 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12697 do_vfp_nsyn_opcode (enc
[flavour
]);
12703 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12704 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12705 int flavour
= neon_cvt_flavour (rs
);
12707 /* VFP rather than Neon conversions. */
12710 do_vfp_nsyn_cvt (rs
, flavour
);
12719 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12722 /* Fixed-point conversion with #0 immediate is encoded as an
12723 integer conversion. */
12724 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12726 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12727 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12728 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12730 inst
.instruction
|= enctab
[flavour
];
12731 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12732 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12733 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12734 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12735 inst
.instruction
|= neon_quad (rs
) << 6;
12736 inst
.instruction
|= 1 << 21;
12737 inst
.instruction
|= immbits
<< 16;
12739 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12747 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12749 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12751 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12755 inst
.instruction
|= enctab
[flavour
];
12757 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12758 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12759 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12760 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12761 inst
.instruction
|= neon_quad (rs
) << 6;
12762 inst
.instruction
|= 2 << 18;
12764 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12769 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12770 do_vfp_nsyn_cvt (rs
, flavour
);
12775 neon_move_immediate (void)
12777 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12778 struct neon_type_el et
= neon_check_type (2, rs
,
12779 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12780 unsigned immlo
, immhi
= 0, immbits
;
12781 int op
, cmode
, float_p
;
12783 constraint (et
.type
== NT_invtype
,
12784 _("operand size must be specified for immediate VMOV"));
12786 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12787 op
= (inst
.instruction
& (1 << 5)) != 0;
12789 immlo
= inst
.operands
[1].imm
;
12790 if (inst
.operands
[1].regisimm
)
12791 immhi
= inst
.operands
[1].reg
;
12793 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12794 _("immediate has bits set outside the operand size"));
12796 float_p
= inst
.operands
[1].immisfloat
;
12798 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
12799 et
.size
, et
.type
)) == FAIL
)
12801 /* Invert relevant bits only. */
12802 neon_invert_size (&immlo
, &immhi
, et
.size
);
12803 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12804 with one or the other; those cases are caught by
12805 neon_cmode_for_move_imm. */
12807 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
12808 &op
, et
.size
, et
.type
)) == FAIL
)
12810 first_error (_("immediate out of range"));
12815 inst
.instruction
&= ~(1 << 5);
12816 inst
.instruction
|= op
<< 5;
12818 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12819 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12820 inst
.instruction
|= neon_quad (rs
) << 6;
12821 inst
.instruction
|= cmode
<< 8;
12823 neon_write_immbits (immbits
);
12829 if (inst
.operands
[1].isreg
)
12831 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12833 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12834 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12835 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12836 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12837 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12838 inst
.instruction
|= neon_quad (rs
) << 6;
12842 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12843 neon_move_immediate ();
12846 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12849 /* Encode instructions of form:
12851 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12852 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
12855 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12857 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12858 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12859 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12860 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12861 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12862 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12863 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12864 inst
.instruction
|= neon_logbits (size
) << 20;
12866 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12870 do_neon_dyadic_long (void)
12872 /* FIXME: Type checking for lengthening op. */
12873 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12874 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12875 neon_mixed_length (et
, et
.size
);
12879 do_neon_abal (void)
12881 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12882 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12883 neon_mixed_length (et
, et
.size
);
12887 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12889 if (inst
.operands
[2].isscalar
)
12891 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12892 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12893 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12894 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12898 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12899 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12900 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12901 neon_mixed_length (et
, et
.size
);
12906 do_neon_mac_maybe_scalar_long (void)
12908 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12912 do_neon_dyadic_wide (void)
12914 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12915 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12916 neon_mixed_length (et
, et
.size
);
12920 do_neon_dyadic_narrow (void)
12922 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12923 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12924 /* Operand sign is unimportant, and the U bit is part of the opcode,
12925 so force the operand type to integer. */
12926 et
.type
= NT_integer
;
12927 neon_mixed_length (et
, et
.size
/ 2);
12931 do_neon_mul_sat_scalar_long (void)
12933 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12937 do_neon_vmull (void)
12939 if (inst
.operands
[2].isscalar
)
12940 do_neon_mac_maybe_scalar_long ();
12943 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12944 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12945 if (et
.type
== NT_poly
)
12946 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12948 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12949 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12950 zero. Should be OK as-is. */
12951 neon_mixed_length (et
, et
.size
);
12958 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12959 struct neon_type_el et
= neon_check_type (3, rs
,
12960 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12961 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12962 constraint (imm
>= (neon_quad (rs
) ? 16 : 8), _("shift out of range"));
12963 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12964 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12965 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12966 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12967 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12968 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12969 inst
.instruction
|= neon_quad (rs
) << 6;
12970 inst
.instruction
|= imm
<< 8;
12972 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12978 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12979 struct neon_type_el et
= neon_check_type (2, rs
,
12980 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12981 unsigned op
= (inst
.instruction
>> 7) & 3;
12982 /* N (width of reversed regions) is encoded as part of the bitmask. We
12983 extract it here to check the elements to be reversed are smaller.
12984 Otherwise we'd get a reserved instruction. */
12985 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12986 assert (elsize
!= 0);
12987 constraint (et
.size
>= elsize
,
12988 _("elements must be smaller than reversal region"));
12989 neon_two_same (neon_quad (rs
), 1, et
.size
);
12995 if (inst
.operands
[1].isscalar
)
12997 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12998 struct neon_type_el et
= neon_check_type (2, rs
,
12999 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13000 unsigned sizebits
= et
.size
>> 3;
13001 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13002 int logsize
= neon_logbits (et
.size
);
13003 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13005 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13008 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13009 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13010 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13011 inst
.instruction
|= LOW4 (dm
);
13012 inst
.instruction
|= HI1 (dm
) << 5;
13013 inst
.instruction
|= neon_quad (rs
) << 6;
13014 inst
.instruction
|= x
<< 17;
13015 inst
.instruction
|= sizebits
<< 16;
13017 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13021 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13022 struct neon_type_el et
= neon_check_type (2, rs
,
13023 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13024 /* Duplicate ARM register to lanes of vector. */
13025 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13028 case 8: inst
.instruction
|= 0x400000; break;
13029 case 16: inst
.instruction
|= 0x000020; break;
13030 case 32: inst
.instruction
|= 0x000000; break;
13033 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13034 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13035 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13036 inst
.instruction
|= neon_quad (rs
) << 21;
13037 /* The encoding for this instruction is identical for the ARM and Thumb
13038 variants, except for the condition field. */
13039 do_vfp_cond_or_thumb ();
13043 /* VMOV has particularly many variations. It can be one of:
13044 0. VMOV<c><q> <Qd>, <Qm>
13045 1. VMOV<c><q> <Dd>, <Dm>
13046 (Register operations, which are VORR with Rm = Rn.)
13047 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13048 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13050 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13051 (ARM register to scalar.)
13052 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13053 (Two ARM registers to vector.)
13054 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13055 (Scalar to ARM register.)
13056 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13057 (Vector to two ARM registers.)
13058 8. VMOV.F32 <Sd>, <Sm>
13059 9. VMOV.F64 <Dd>, <Dm>
13060 (VFP register moves.)
13061 10. VMOV.F32 <Sd>, #imm
13062 11. VMOV.F64 <Dd>, #imm
13063 (VFP float immediate load.)
13064 12. VMOV <Rd>, <Sm>
13065 (VFP single to ARM reg.)
13066 13. VMOV <Sd>, <Rm>
13067 (ARM reg to VFP single.)
13068 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13069 (Two ARM regs to two VFP singles.)
13070 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13071 (Two VFP singles to two ARM regs.)
13073 These cases can be disambiguated using neon_select_shape, except cases 1/9
13074 and 3/11 which depend on the operand type too.
13076 All the encoded bits are hardcoded by this function.
13078 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13079 Cases 5, 7 may be used with VFPv2 and above.
13081 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13082 can specify a type where it doesn't make sense to, and is ignored). */
13087 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13088 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13090 struct neon_type_el et
;
13091 const char *ldconst
= 0;
13095 case NS_DD
: /* case 1/9. */
13096 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13097 /* It is not an error here if no type is given. */
13099 if (et
.type
== NT_float
&& et
.size
== 64)
13101 do_vfp_nsyn_opcode ("fcpyd");
13104 /* fall through. */
13106 case NS_QQ
: /* case 0/1. */
13108 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13110 /* The architecture manual I have doesn't explicitly state which
13111 value the U bit should have for register->register moves, but
13112 the equivalent VORR instruction has U = 0, so do that. */
13113 inst
.instruction
= 0x0200110;
13114 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13115 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13116 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13117 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13118 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13119 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13120 inst
.instruction
|= neon_quad (rs
) << 6;
13122 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13126 case NS_DI
: /* case 3/11. */
13127 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13129 if (et
.type
== NT_float
&& et
.size
== 64)
13131 /* case 11 (fconstd). */
13132 ldconst
= "fconstd";
13133 goto encode_fconstd
;
13135 /* fall through. */
13137 case NS_QI
: /* case 2/3. */
13138 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13140 inst
.instruction
= 0x0800010;
13141 neon_move_immediate ();
13142 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13145 case NS_SR
: /* case 4. */
13147 unsigned bcdebits
= 0;
13148 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13149 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13150 int logsize
= neon_logbits (et
.size
);
13151 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13152 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13154 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13156 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13157 && et
.size
!= 32, _(BAD_FPU
));
13158 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13159 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13163 case 8: bcdebits
= 0x8; break;
13164 case 16: bcdebits
= 0x1; break;
13165 case 32: bcdebits
= 0x0; break;
13169 bcdebits
|= x
<< logsize
;
13171 inst
.instruction
= 0xe000b10;
13172 do_vfp_cond_or_thumb ();
13173 inst
.instruction
|= LOW4 (dn
) << 16;
13174 inst
.instruction
|= HI1 (dn
) << 7;
13175 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13176 inst
.instruction
|= (bcdebits
& 3) << 5;
13177 inst
.instruction
|= (bcdebits
>> 2) << 21;
13181 case NS_DRR
: /* case 5 (fmdrr). */
13182 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13185 inst
.instruction
= 0xc400b10;
13186 do_vfp_cond_or_thumb ();
13187 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13188 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13189 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13190 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13193 case NS_RS
: /* case 6. */
13195 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13196 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
13197 unsigned logsize
= neon_logbits (et
.size
);
13198 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13199 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
13200 unsigned abcdebits
= 0;
13202 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13204 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13205 && et
.size
!= 32, _(BAD_FPU
));
13206 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13207 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13211 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
13212 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
13213 case 32: abcdebits
= 0x00; break;
13217 abcdebits
|= x
<< logsize
;
13218 inst
.instruction
= 0xe100b10;
13219 do_vfp_cond_or_thumb ();
13220 inst
.instruction
|= LOW4 (dn
) << 16;
13221 inst
.instruction
|= HI1 (dn
) << 7;
13222 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13223 inst
.instruction
|= (abcdebits
& 3) << 5;
13224 inst
.instruction
|= (abcdebits
>> 2) << 21;
13228 case NS_RRD
: /* case 7 (fmrrd). */
13229 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13232 inst
.instruction
= 0xc500b10;
13233 do_vfp_cond_or_thumb ();
13234 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13235 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13236 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13237 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13240 case NS_FF
: /* case 8 (fcpys). */
13241 do_vfp_nsyn_opcode ("fcpys");
13244 case NS_FI
: /* case 10 (fconsts). */
13245 ldconst
= "fconsts";
13247 if (is_quarter_float (inst
.operands
[1].imm
))
13249 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13250 do_vfp_nsyn_opcode (ldconst
);
13253 first_error (_("immediate out of range"));
13256 case NS_RF
: /* case 12 (fmrs). */
13257 do_vfp_nsyn_opcode ("fmrs");
13260 case NS_FR
: /* case 13 (fmsr). */
13261 do_vfp_nsyn_opcode ("fmsr");
13264 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13265 (one of which is a list), but we have parsed four. Do some fiddling to
13266 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13268 case NS_RRFF
: /* case 14 (fmrrs). */
13269 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13270 _("VFP registers must be adjacent"));
13271 inst
.operands
[2].imm
= 2;
13272 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13273 do_vfp_nsyn_opcode ("fmrrs");
13276 case NS_FFRR
: /* case 15 (fmsrr). */
13277 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13278 _("VFP registers must be adjacent"));
13279 inst
.operands
[1] = inst
.operands
[2];
13280 inst
.operands
[2] = inst
.operands
[3];
13281 inst
.operands
[0].imm
= 2;
13282 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13283 do_vfp_nsyn_opcode ("fmsrr");
13292 do_neon_rshift_round_imm (void)
13294 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13295 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13296 int imm
= inst
.operands
[2].imm
;
13298 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13301 inst
.operands
[2].present
= 0;
13306 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13307 _("immediate out of range for shift"));
13308 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13313 do_neon_movl (void)
13315 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13316 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13317 unsigned sizebits
= et
.size
>> 3;
13318 inst
.instruction
|= sizebits
<< 19;
13319 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13325 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13326 struct neon_type_el et
= neon_check_type (2, rs
,
13327 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13328 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13329 neon_two_same (neon_quad (rs
), 1, et
.size
);
13333 do_neon_zip_uzp (void)
13335 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13336 struct neon_type_el et
= neon_check_type (2, rs
,
13337 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13338 if (rs
== NS_DD
&& et
.size
== 32)
13340 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13341 inst
.instruction
= N_MNEM_vtrn
;
13345 neon_two_same (neon_quad (rs
), 1, et
.size
);
13349 do_neon_sat_abs_neg (void)
13351 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13352 struct neon_type_el et
= neon_check_type (2, rs
,
13353 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13354 neon_two_same (neon_quad (rs
), 1, et
.size
);
13358 do_neon_pair_long (void)
13360 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13361 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13362 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13363 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13364 neon_two_same (neon_quad (rs
), 1, et
.size
);
13368 do_neon_recip_est (void)
13370 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13371 struct neon_type_el et
= neon_check_type (2, rs
,
13372 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13373 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13374 neon_two_same (neon_quad (rs
), 1, et
.size
);
13380 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13381 struct neon_type_el et
= neon_check_type (2, rs
,
13382 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13383 neon_two_same (neon_quad (rs
), 1, et
.size
);
13389 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13390 struct neon_type_el et
= neon_check_type (2, rs
,
13391 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13392 neon_two_same (neon_quad (rs
), 1, et
.size
);
13398 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13399 struct neon_type_el et
= neon_check_type (2, rs
,
13400 N_EQK
| N_INT
, N_8
| N_KEY
);
13401 neon_two_same (neon_quad (rs
), 1, et
.size
);
13407 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13408 neon_two_same (neon_quad (rs
), 1, -1);
13412 do_neon_tbl_tbx (void)
13414 unsigned listlenbits
;
13415 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13417 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13419 first_error (_("bad list length for table lookup"));
13423 listlenbits
= inst
.operands
[1].imm
- 1;
13424 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13425 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13426 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13427 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13428 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13429 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13430 inst
.instruction
|= listlenbits
<< 8;
13432 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13436 do_neon_ldm_stm (void)
13438 /* P, U and L bits are part of bitmask. */
13439 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13440 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13442 if (inst
.operands
[1].issingle
)
13444 do_vfp_nsyn_ldm_stm (is_dbmode
);
13448 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13449 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13451 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13452 _("register list must contain at least 1 and at most 16 "
13455 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13456 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13457 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13458 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13460 inst
.instruction
|= offsetbits
;
13462 do_vfp_cond_or_thumb ();
13466 do_neon_ldr_str (void)
13468 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13470 if (inst
.operands
[0].issingle
)
13473 do_vfp_nsyn_opcode ("flds");
13475 do_vfp_nsyn_opcode ("fsts");
13480 do_vfp_nsyn_opcode ("fldd");
13482 do_vfp_nsyn_opcode ("fstd");
13486 /* "interleave" version also handles non-interleaving register VLD1/VST1
13490 do_neon_ld_st_interleave (void)
13492 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13493 N_8
| N_16
| N_32
| N_64
);
13494 unsigned alignbits
= 0;
13496 /* The bits in this table go:
13497 0: register stride of one (0) or two (1)
13498 1,2: register list length, minus one (1, 2, 3, 4).
13499 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13500 We use -1 for invalid entries. */
13501 const int typetable
[] =
13503 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13504 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13505 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13506 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13510 if (et
.type
== NT_invtype
)
13513 if (inst
.operands
[1].immisalign
)
13514 switch (inst
.operands
[1].imm
>> 8)
13516 case 64: alignbits
= 1; break;
13518 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13519 goto bad_alignment
;
13523 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13524 goto bad_alignment
;
13529 first_error (_("bad alignment"));
13533 inst
.instruction
|= alignbits
<< 4;
13534 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13536 /* Bits [4:6] of the immediate in a list specifier encode register stride
13537 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13538 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13539 up the right value for "type" in a table based on this value and the given
13540 list style, then stick it back. */
13541 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13542 | (((inst
.instruction
>> 8) & 3) << 3);
13544 typebits
= typetable
[idx
];
13546 constraint (typebits
== -1, _("bad list type for instruction"));
13548 inst
.instruction
&= ~0xf00;
13549 inst
.instruction
|= typebits
<< 8;
13552 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13553 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13554 otherwise. The variable arguments are a list of pairs of legal (size, align)
13555 values, terminated with -1. */
13558 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13561 int result
= FAIL
, thissize
, thisalign
;
13563 if (!inst
.operands
[1].immisalign
)
13569 va_start (ap
, do_align
);
13573 thissize
= va_arg (ap
, int);
13574 if (thissize
== -1)
13576 thisalign
= va_arg (ap
, int);
13578 if (size
== thissize
&& align
== thisalign
)
13581 while (result
!= SUCCESS
);
13585 if (result
== SUCCESS
)
13588 first_error (_("unsupported alignment for instruction"));
13594 do_neon_ld_st_lane (void)
13596 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13597 int align_good
, do_align
= 0;
13598 int logsize
= neon_logbits (et
.size
);
13599 int align
= inst
.operands
[1].imm
>> 8;
13600 int n
= (inst
.instruction
>> 8) & 3;
13601 int max_el
= 64 / et
.size
;
13603 if (et
.type
== NT_invtype
)
13606 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13607 _("bad list length"));
13608 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13609 _("scalar index out of range"));
13610 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13612 _("stride of 2 unavailable when element size is 8"));
13616 case 0: /* VLD1 / VST1. */
13617 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13619 if (align_good
== FAIL
)
13623 unsigned alignbits
= 0;
13626 case 16: alignbits
= 0x1; break;
13627 case 32: alignbits
= 0x3; break;
13630 inst
.instruction
|= alignbits
<< 4;
13634 case 1: /* VLD2 / VST2. */
13635 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13637 if (align_good
== FAIL
)
13640 inst
.instruction
|= 1 << 4;
13643 case 2: /* VLD3 / VST3. */
13644 constraint (inst
.operands
[1].immisalign
,
13645 _("can't use alignment with this instruction"));
13648 case 3: /* VLD4 / VST4. */
13649 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13650 16, 64, 32, 64, 32, 128, -1);
13651 if (align_good
== FAIL
)
13655 unsigned alignbits
= 0;
13658 case 8: alignbits
= 0x1; break;
13659 case 16: alignbits
= 0x1; break;
13660 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13663 inst
.instruction
|= alignbits
<< 4;
13670 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13671 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13672 inst
.instruction
|= 1 << (4 + logsize
);
13674 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13675 inst
.instruction
|= logsize
<< 10;
13678 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13681 do_neon_ld_dup (void)
13683 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13684 int align_good
, do_align
= 0;
13686 if (et
.type
== NT_invtype
)
13689 switch ((inst
.instruction
>> 8) & 3)
13691 case 0: /* VLD1. */
13692 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13693 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13694 &do_align
, 16, 16, 32, 32, -1);
13695 if (align_good
== FAIL
)
13697 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13700 case 2: inst
.instruction
|= 1 << 5; break;
13701 default: first_error (_("bad list length")); return;
13703 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13706 case 1: /* VLD2. */
13707 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13708 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13709 if (align_good
== FAIL
)
13711 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13712 _("bad list length"));
13713 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13714 inst
.instruction
|= 1 << 5;
13715 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13718 case 2: /* VLD3. */
13719 constraint (inst
.operands
[1].immisalign
,
13720 _("can't use alignment with this instruction"));
13721 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13722 _("bad list length"));
13723 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13724 inst
.instruction
|= 1 << 5;
13725 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13728 case 3: /* VLD4. */
13730 int align
= inst
.operands
[1].imm
>> 8;
13731 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13732 16, 64, 32, 64, 32, 128, -1);
13733 if (align_good
== FAIL
)
13735 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13736 _("bad list length"));
13737 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13738 inst
.instruction
|= 1 << 5;
13739 if (et
.size
== 32 && align
== 128)
13740 inst
.instruction
|= 0x3 << 6;
13742 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13749 inst
.instruction
|= do_align
<< 4;
13752 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13753 apart from bits [11:4]. */
13756 do_neon_ldx_stx (void)
13758 switch (NEON_LANE (inst
.operands
[0].imm
))
13760 case NEON_INTERLEAVE_LANES
:
13761 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13762 do_neon_ld_st_interleave ();
13765 case NEON_ALL_LANES
:
13766 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13771 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13772 do_neon_ld_st_lane ();
13775 /* L bit comes from bit mask. */
13776 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13777 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13778 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13780 if (inst
.operands
[1].postind
)
13782 int postreg
= inst
.operands
[1].imm
& 0xf;
13783 constraint (!inst
.operands
[1].immisreg
,
13784 _("post-index must be a register"));
13785 constraint (postreg
== 0xd || postreg
== 0xf,
13786 _("bad register for post-index"));
13787 inst
.instruction
|= postreg
;
13789 else if (inst
.operands
[1].writeback
)
13791 inst
.instruction
|= 0xd;
13794 inst
.instruction
|= 0xf;
13797 inst
.instruction
|= 0xf9000000;
13799 inst
.instruction
|= 0xf4000000;
13802 /* Overall per-instruction processing. */
13804 /* We need to be able to fix up arbitrary expressions in some statements.
13805 This is so that we can handle symbols that are an arbitrary distance from
13806 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13807 which returns part of an address in a form which will be valid for
13808 a data instruction. We do this by pushing the expression into a symbol
13809 in the expr_section, and creating a fix for that. */
13812 fix_new_arm (fragS
* frag
,
13827 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13831 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13836 /* Mark whether the fix is to a THUMB instruction, or an ARM
13838 new_fix
->tc_fix_data
= thumb_mode
;
13841 /* Create a frg for an instruction requiring relaxation. */
13843 output_relax_insn (void)
13849 /* The size of the instruction is unknown, so tie the debug info to the
13850 start of the instruction. */
13851 dwarf2_emit_insn (0);
13853 switch (inst
.reloc
.exp
.X_op
)
13856 sym
= inst
.reloc
.exp
.X_add_symbol
;
13857 offset
= inst
.reloc
.exp
.X_add_number
;
13861 offset
= inst
.reloc
.exp
.X_add_number
;
13864 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13868 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13869 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13870 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13873 /* Write a 32-bit thumb instruction to buf. */
13875 put_thumb32_insn (char * buf
, unsigned long insn
)
13877 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13878 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13882 output_inst (const char * str
)
13888 as_bad ("%s -- `%s'", inst
.error
, str
);
13893 output_relax_insn ();
13896 if (inst
.size
== 0)
13899 to
= frag_more (inst
.size
);
13901 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13903 assert (inst
.size
== (2 * THUMB_SIZE
));
13904 put_thumb32_insn (to
, inst
.instruction
);
13906 else if (inst
.size
> INSN_SIZE
)
13908 assert (inst
.size
== (2 * INSN_SIZE
));
13909 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13910 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13913 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13915 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13916 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13917 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13920 dwarf2_emit_insn (inst
.size
);
13923 /* Tag values used in struct asm_opcode's tag field. */
13926 OT_unconditional
, /* Instruction cannot be conditionalized.
13927 The ARM condition field is still 0xE. */
13928 OT_unconditionalF
, /* Instruction cannot be conditionalized
13929 and carries 0xF in its ARM condition field. */
13930 OT_csuffix
, /* Instruction takes a conditional suffix. */
13931 OT_csuffixF
, /* Some forms of the instruction take a conditional
13932 suffix, others place 0xF where the condition field
13934 OT_cinfix3
, /* Instruction takes a conditional infix,
13935 beginning at character index 3. (In
13936 unified mode, it becomes a suffix.) */
13937 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13938 tsts, cmps, cmns, and teqs. */
13939 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13940 character index 3, even in unified mode. Used for
13941 legacy instructions where suffix and infix forms
13942 may be ambiguous. */
13943 OT_csuf_or_in3
, /* Instruction takes either a conditional
13944 suffix or an infix at character index 3. */
13945 OT_odd_infix_unc
, /* This is the unconditional variant of an
13946 instruction that takes a conditional infix
13947 at an unusual position. In unified mode,
13948 this variant will accept a suffix. */
13949 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13950 are the conditional variants of instructions that
13951 take conditional infixes in unusual positions.
13952 The infix appears at character index
13953 (tag - OT_odd_infix_0). These are not accepted
13954 in unified mode. */
13957 /* Subroutine of md_assemble, responsible for looking up the primary
13958 opcode from the mnemonic the user wrote. STR points to the
13959 beginning of the mnemonic.
13961 This is not simply a hash table lookup, because of conditional
13962 variants. Most instructions have conditional variants, which are
13963 expressed with a _conditional affix_ to the mnemonic. If we were
13964 to encode each conditional variant as a literal string in the opcode
13965 table, it would have approximately 20,000 entries.
13967 Most mnemonics take this affix as a suffix, and in unified syntax,
13968 'most' is upgraded to 'all'. However, in the divided syntax, some
13969 instructions take the affix as an infix, notably the s-variants of
13970 the arithmetic instructions. Of those instructions, all but six
13971 have the infix appear after the third character of the mnemonic.
13973 Accordingly, the algorithm for looking up primary opcodes given
13976 1. Look up the identifier in the opcode table.
13977 If we find a match, go to step U.
13979 2. Look up the last two characters of the identifier in the
13980 conditions table. If we find a match, look up the first N-2
13981 characters of the identifier in the opcode table. If we
13982 find a match, go to step CE.
13984 3. Look up the fourth and fifth characters of the identifier in
13985 the conditions table. If we find a match, extract those
13986 characters from the identifier, and look up the remaining
13987 characters in the opcode table. If we find a match, go
13992 U. Examine the tag field of the opcode structure, in case this is
13993 one of the six instructions with its conditional infix in an
13994 unusual place. If it is, the tag tells us where to find the
13995 infix; look it up in the conditions table and set inst.cond
13996 accordingly. Otherwise, this is an unconditional instruction.
13997 Again set inst.cond accordingly. Return the opcode structure.
13999 CE. Examine the tag field to make sure this is an instruction that
14000 should receive a conditional suffix. If it is not, fail.
14001 Otherwise, set inst.cond from the suffix we already looked up,
14002 and return the opcode structure.
14004 CM. Examine the tag field to make sure this is an instruction that
14005 should receive a conditional infix after the third character.
14006 If it is not, fail. Otherwise, undo the edits to the current
14007 line of input and proceed as for case CE. */
14009 static const struct asm_opcode
*
14010 opcode_lookup (char **str
)
14014 const struct asm_opcode
*opcode
;
14015 const struct asm_cond
*cond
;
14017 bfd_boolean neon_supported
;
14019 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
14021 /* Scan up to the end of the mnemonic, which must end in white space,
14022 '.' (in unified mode, or for Neon instructions), or end of string. */
14023 for (base
= end
= *str
; *end
!= '\0'; end
++)
14024 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14030 /* Handle a possible width suffix and/or Neon type suffix. */
14035 /* The .w and .n suffixes are only valid if the unified syntax is in
14037 if (unified_syntax
&& end
[1] == 'w')
14039 else if (unified_syntax
&& end
[1] == 'n')
14044 inst
.vectype
.elems
= 0;
14046 *str
= end
+ offset
;
14048 if (end
[offset
] == '.')
14050 /* See if we have a Neon type suffix (possible in either unified or
14051 non-unified ARM syntax mode). */
14052 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14055 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14061 /* Look for unaffixed or special-case affixed mnemonic. */
14062 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14066 if (opcode
->tag
< OT_odd_infix_0
)
14068 inst
.cond
= COND_ALWAYS
;
14072 if (unified_syntax
)
14073 as_warn (_("conditional infixes are deprecated in unified syntax"));
14074 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14075 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14078 inst
.cond
= cond
->value
;
14082 /* Cannot have a conditional suffix on a mnemonic of less than two
14084 if (end
- base
< 3)
14087 /* Look for suffixed mnemonic. */
14089 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14090 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
14091 if (opcode
&& cond
)
14094 switch (opcode
->tag
)
14096 case OT_cinfix3_legacy
:
14097 /* Ignore conditional suffixes matched on infix only mnemonics. */
14101 case OT_cinfix3_deprecated
:
14102 case OT_odd_infix_unc
:
14103 if (!unified_syntax
)
14105 /* else fall through */
14109 case OT_csuf_or_in3
:
14110 inst
.cond
= cond
->value
;
14113 case OT_unconditional
:
14114 case OT_unconditionalF
:
14117 inst
.cond
= cond
->value
;
14121 /* delayed diagnostic */
14122 inst
.error
= BAD_COND
;
14123 inst
.cond
= COND_ALWAYS
;
14132 /* Cannot have a usual-position infix on a mnemonic of less than
14133 six characters (five would be a suffix). */
14134 if (end
- base
< 6)
14137 /* Look for infixed mnemonic in the usual position. */
14139 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14143 memcpy (save
, affix
, 2);
14144 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14145 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14146 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14147 memcpy (affix
, save
, 2);
14150 && (opcode
->tag
== OT_cinfix3
14151 || opcode
->tag
== OT_cinfix3_deprecated
14152 || opcode
->tag
== OT_csuf_or_in3
14153 || opcode
->tag
== OT_cinfix3_legacy
))
14157 && (opcode
->tag
== OT_cinfix3
14158 || opcode
->tag
== OT_cinfix3_deprecated
))
14159 as_warn (_("conditional infixes are deprecated in unified syntax"));
14161 inst
.cond
= cond
->value
;
14169 md_assemble (char *str
)
14172 const struct asm_opcode
* opcode
;
14174 /* Align the previous label if needed. */
14175 if (last_label_seen
!= NULL
)
14177 symbol_set_frag (last_label_seen
, frag_now
);
14178 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
14179 S_SET_SEGMENT (last_label_seen
, now_seg
);
14182 memset (&inst
, '\0', sizeof (inst
));
14183 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
14185 opcode
= opcode_lookup (&p
);
14188 /* It wasn't an instruction, but it might be a register alias of
14189 the form alias .req reg, or a Neon .dn/.qn directive. */
14190 if (!create_register_alias (str
, p
)
14191 && !create_neon_reg_alias (str
, p
))
14192 as_bad (_("bad instruction `%s'"), str
);
14197 if (opcode
->tag
== OT_cinfix3_deprecated
)
14198 as_warn (_("s suffix on comparison instruction is deprecated"));
14200 /* The value which unconditional instructions should have in place of the
14201 condition field. */
14202 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
14206 arm_feature_set variant
;
14208 variant
= cpu_variant
;
14209 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14210 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
14211 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
14212 /* Check that this instruction is supported for this CPU. */
14213 if (!opcode
->tvariant
14214 || (thumb_mode
== 1
14215 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14217 as_bad (_("selected processor does not support `%s'"), str
);
14220 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14221 && opcode
->tencode
!= do_t_branch
)
14223 as_bad (_("Thumb does not support conditional execution"));
14227 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
) && !inst
.size_req
)
14229 /* Implicit require narrow instructions on Thumb-1. This avoids
14230 relaxation accidentally introducing Thumb-2 instructions. */
14231 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
14232 && !ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
))
14236 /* Check conditional suffixes. */
14237 if (current_it_mask
)
14240 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14241 current_it_mask
<<= 1;
14242 current_it_mask
&= 0x1f;
14243 /* The BKPT instruction is unconditional even in an IT block. */
14245 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14247 as_bad (_("incorrect condition in IT block"));
14251 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14253 as_bad (_("thumb conditional instruction not in IT block"));
14257 mapping_state (MAP_THUMB
);
14258 inst
.instruction
= opcode
->tvalue
;
14260 if (!parse_operands (p
, opcode
->operands
))
14261 opcode
->tencode ();
14263 /* Clear current_it_mask at the end of an IT block. */
14264 if (current_it_mask
== 0x10)
14265 current_it_mask
= 0;
14267 if (!(inst
.error
|| inst
.relax
))
14269 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14270 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14271 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14273 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14278 /* Something has gone badly wrong if we try to relax a fixed size
14280 assert (inst
.size_req
== 0 || !inst
.relax
);
14282 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14283 *opcode
->tvariant
);
14284 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14285 set those bits when Thumb-2 32-bit instructions are seen. ie.
14286 anything other than bl/blx and v6-M instructions.
14287 This is overly pessimistic for relaxable instructions. */
14288 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14290 && !ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
))
14291 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14294 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14298 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
14299 is_bx
= (opcode
->aencode
== do_bx
);
14301 /* Check that this instruction is supported for this CPU. */
14302 if (!(is_bx
&& fix_v4bx
)
14303 && !(opcode
->avariant
&&
14304 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
14306 as_bad (_("selected processor does not support `%s'"), str
);
14311 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14315 mapping_state (MAP_ARM
);
14316 inst
.instruction
= opcode
->avalue
;
14317 if (opcode
->tag
== OT_unconditionalF
)
14318 inst
.instruction
|= 0xF << 28;
14320 inst
.instruction
|= inst
.cond
<< 28;
14321 inst
.size
= INSN_SIZE
;
14322 if (!parse_operands (p
, opcode
->operands
))
14323 opcode
->aencode ();
14324 /* Arm mode bx is marked as both v4T and v5 because it's still required
14325 on a hypothetical non-thumb v5 core. */
14327 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14329 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14330 *opcode
->avariant
);
14334 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14341 /* Various frobbings of labels and their addresses. */
14344 arm_start_line_hook (void)
14346 last_label_seen
= NULL
;
14350 arm_frob_label (symbolS
* sym
)
14352 last_label_seen
= sym
;
14354 ARM_SET_THUMB (sym
, thumb_mode
);
14356 #if defined OBJ_COFF || defined OBJ_ELF
14357 ARM_SET_INTERWORK (sym
, support_interwork
);
14360 /* Note - do not allow local symbols (.Lxxx) to be labelled
14361 as Thumb functions. This is because these labels, whilst
14362 they exist inside Thumb code, are not the entry points for
14363 possible ARM->Thumb calls. Also, these labels can be used
14364 as part of a computed goto or switch statement. eg gcc
14365 can generate code that looks like this:
14367 ldr r2, [pc, .Laaa]
14377 The first instruction loads the address of the jump table.
14378 The second instruction converts a table index into a byte offset.
14379 The third instruction gets the jump address out of the table.
14380 The fourth instruction performs the jump.
14382 If the address stored at .Laaa is that of a symbol which has the
14383 Thumb_Func bit set, then the linker will arrange for this address
14384 to have the bottom bit set, which in turn would mean that the
14385 address computation performed by the third instruction would end
14386 up with the bottom bit set. Since the ARM is capable of unaligned
14387 word loads, the instruction would then load the incorrect address
14388 out of the jump table, and chaos would ensue. */
14389 if (label_is_thumb_function_name
14390 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14391 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14393 /* When the address of a Thumb function is taken the bottom
14394 bit of that address should be set. This will allow
14395 interworking between Arm and Thumb functions to work
14398 THUMB_SET_FUNC (sym
, 1);
14400 label_is_thumb_function_name
= FALSE
;
14403 dwarf2_emit_label (sym
);
14407 arm_data_in_code (void)
14409 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14411 *input_line_pointer
= '/';
14412 input_line_pointer
+= 5;
14413 *input_line_pointer
= 0;
14421 arm_canonicalize_symbol_name (char * name
)
14425 if (thumb_mode
&& (len
= strlen (name
)) > 5
14426 && streq (name
+ len
- 5, "/data"))
14427 *(name
+ len
- 5) = 0;
14432 /* Table of all register names defined by default. The user can
14433 define additional names with .req. Note that all register names
14434 should appear in both upper and lowercase variants. Some registers
14435 also have mixed-case names. */
14437 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14438 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14439 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14440 #define REGSET(p,t) \
14441 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14442 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14443 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14444 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14445 #define REGSETH(p,t) \
14446 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14447 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14448 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14449 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14450 #define REGSET2(p,t) \
14451 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14452 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14453 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14454 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14456 static const struct reg_entry reg_names
[] =
14458 /* ARM integer registers. */
14459 REGSET(r
, RN
), REGSET(R
, RN
),
14461 /* ATPCS synonyms. */
14462 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14463 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14464 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14466 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14467 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14468 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14470 /* Well-known aliases. */
14471 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14472 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14474 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14475 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14477 /* Coprocessor numbers. */
14478 REGSET(p
, CP
), REGSET(P
, CP
),
14480 /* Coprocessor register numbers. The "cr" variants are for backward
14482 REGSET(c
, CN
), REGSET(C
, CN
),
14483 REGSET(cr
, CN
), REGSET(CR
, CN
),
14485 /* FPA registers. */
14486 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14487 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14489 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14490 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14492 /* VFP SP registers. */
14493 REGSET(s
,VFS
), REGSET(S
,VFS
),
14494 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14496 /* VFP DP Registers. */
14497 REGSET(d
,VFD
), REGSET(D
,VFD
),
14498 /* Extra Neon DP registers. */
14499 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14501 /* Neon QP registers. */
14502 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14504 /* VFP control registers. */
14505 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14506 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14507 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
14508 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
14509 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
14510 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
14512 /* Maverick DSP coprocessor registers. */
14513 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14514 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14516 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14517 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14518 REGDEF(dspsc
,0,DSPSC
),
14520 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14521 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14522 REGDEF(DSPSC
,0,DSPSC
),
14524 /* iWMMXt data registers - p0, c0-15. */
14525 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14527 /* iWMMXt control registers - p1, c0-3. */
14528 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14529 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14530 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14531 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14533 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14534 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14535 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14536 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14537 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14539 /* XScale accumulator registers. */
14540 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14546 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14547 within psr_required_here. */
14548 static const struct asm_psr psrs
[] =
14550 /* Backward compatibility notation. Note that "all" is no longer
14551 truly all possible PSR bits. */
14552 {"all", PSR_c
| PSR_f
},
14556 /* Individual flags. */
14561 /* Combinations of flags. */
14562 {"fs", PSR_f
| PSR_s
},
14563 {"fx", PSR_f
| PSR_x
},
14564 {"fc", PSR_f
| PSR_c
},
14565 {"sf", PSR_s
| PSR_f
},
14566 {"sx", PSR_s
| PSR_x
},
14567 {"sc", PSR_s
| PSR_c
},
14568 {"xf", PSR_x
| PSR_f
},
14569 {"xs", PSR_x
| PSR_s
},
14570 {"xc", PSR_x
| PSR_c
},
14571 {"cf", PSR_c
| PSR_f
},
14572 {"cs", PSR_c
| PSR_s
},
14573 {"cx", PSR_c
| PSR_x
},
14574 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14575 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14576 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14577 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14578 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14579 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14580 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14581 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14582 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14583 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14584 {"scf", PSR_s
| PSR_c
| PSR_f
},
14585 {"scx", PSR_s
| PSR_c
| PSR_x
},
14586 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14587 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14588 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14589 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14590 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14591 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14592 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14593 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14594 {"csf", PSR_c
| PSR_s
| PSR_f
},
14595 {"csx", PSR_c
| PSR_s
| PSR_x
},
14596 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14597 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14598 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14599 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14600 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14601 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14602 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14603 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14604 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14605 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14606 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14607 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14608 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14609 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14610 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14611 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14612 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14613 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14614 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14615 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14616 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14617 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14618 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14619 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14620 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14621 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14624 /* Table of V7M psr names. */
14625 static const struct asm_psr v7m_psrs
[] =
14627 {"apsr", 0 }, {"APSR", 0 },
14628 {"iapsr", 1 }, {"IAPSR", 1 },
14629 {"eapsr", 2 }, {"EAPSR", 2 },
14630 {"psr", 3 }, {"PSR", 3 },
14631 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14632 {"ipsr", 5 }, {"IPSR", 5 },
14633 {"epsr", 6 }, {"EPSR", 6 },
14634 {"iepsr", 7 }, {"IEPSR", 7 },
14635 {"msp", 8 }, {"MSP", 8 },
14636 {"psp", 9 }, {"PSP", 9 },
14637 {"primask", 16}, {"PRIMASK", 16},
14638 {"basepri", 17}, {"BASEPRI", 17},
14639 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14640 {"faultmask", 19}, {"FAULTMASK", 19},
14641 {"control", 20}, {"CONTROL", 20}
14644 /* Table of all shift-in-operand names. */
14645 static const struct asm_shift_name shift_names
[] =
14647 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14648 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14649 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14650 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14651 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14652 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14655 /* Table of all explicit relocation names. */
14657 static struct reloc_entry reloc_names
[] =
14659 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14660 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14661 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14662 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14663 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14664 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14665 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14666 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14667 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14668 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14669 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14673 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14674 static const struct asm_cond conds
[] =
14678 {"cs", 0x2}, {"hs", 0x2},
14679 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14693 static struct asm_barrier_opt barrier_opt_names
[] =
14701 /* Table of ARM-format instructions. */
14703 /* Macros for gluing together operand strings. N.B. In all cases
14704 other than OPS0, the trailing OP_stop comes from default
14705 zero-initialization of the unspecified elements of the array. */
14706 #define OPS0() { OP_stop, }
14707 #define OPS1(a) { OP_##a, }
14708 #define OPS2(a,b) { OP_##a,OP_##b, }
14709 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14710 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14711 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14712 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14714 /* These macros abstract out the exact format of the mnemonic table and
14715 save some repeated characters. */
14717 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14718 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14719 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14720 THUMB_VARIANT, do_##ae, do_##te }
14722 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14723 a T_MNEM_xyz enumerator. */
14724 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14725 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14726 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14727 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14729 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14730 infix after the third character. */
14731 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14732 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14733 THUMB_VARIANT, do_##ae, do_##te }
14734 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14735 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14736 THUMB_VARIANT, do_##ae, do_##te }
14737 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14738 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14739 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14740 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14741 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14742 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14743 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14744 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14746 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14747 appear in the condition table. */
14748 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14749 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14750 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14752 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14753 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14754 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14755 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14756 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14757 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14758 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14759 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14760 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14761 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14762 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14763 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14764 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14765 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14766 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14767 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14768 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14769 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14770 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14771 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14773 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14774 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14775 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14776 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14778 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14779 field is still 0xE. Many of the Thumb variants can be executed
14780 conditionally, so this is checked separately. */
14781 #define TUE(mnem, op, top, nops, ops, ae, te) \
14782 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14783 THUMB_VARIANT, do_##ae, do_##te }
14785 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14786 condition code field. */
14787 #define TUF(mnem, op, top, nops, ops, ae, te) \
14788 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14789 THUMB_VARIANT, do_##ae, do_##te }
14791 /* ARM-only variants of all the above. */
14792 #define CE(mnem, op, nops, ops, ae) \
14793 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14795 #define C3(mnem, op, nops, ops, ae) \
14796 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14798 /* Legacy mnemonics that always have conditional infix after the third
14800 #define CL(mnem, op, nops, ops, ae) \
14801 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14802 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14804 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14805 #define cCE(mnem, op, nops, ops, ae) \
14806 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14808 /* Legacy coprocessor instructions where conditional infix and conditional
14809 suffix are ambiguous. For consistency this includes all FPA instructions,
14810 not just the potentially ambiguous ones. */
14811 #define cCL(mnem, op, nops, ops, ae) \
14812 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14813 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14815 /* Coprocessor, takes either a suffix or a position-3 infix
14816 (for an FPA corner case). */
14817 #define C3E(mnem, op, nops, ops, ae) \
14818 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14819 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14821 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14822 { #m1 #m2 #m3, OPS##nops ops, \
14823 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14824 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14826 #define CM(m1, m2, op, nops, ops, ae) \
14827 xCM_(m1, , m2, op, nops, ops, ae), \
14828 xCM_(m1, eq, m2, op, nops, ops, ae), \
14829 xCM_(m1, ne, m2, op, nops, ops, ae), \
14830 xCM_(m1, cs, m2, op, nops, ops, ae), \
14831 xCM_(m1, hs, m2, op, nops, ops, ae), \
14832 xCM_(m1, cc, m2, op, nops, ops, ae), \
14833 xCM_(m1, ul, m2, op, nops, ops, ae), \
14834 xCM_(m1, lo, m2, op, nops, ops, ae), \
14835 xCM_(m1, mi, m2, op, nops, ops, ae), \
14836 xCM_(m1, pl, m2, op, nops, ops, ae), \
14837 xCM_(m1, vs, m2, op, nops, ops, ae), \
14838 xCM_(m1, vc, m2, op, nops, ops, ae), \
14839 xCM_(m1, hi, m2, op, nops, ops, ae), \
14840 xCM_(m1, ls, m2, op, nops, ops, ae), \
14841 xCM_(m1, ge, m2, op, nops, ops, ae), \
14842 xCM_(m1, lt, m2, op, nops, ops, ae), \
14843 xCM_(m1, gt, m2, op, nops, ops, ae), \
14844 xCM_(m1, le, m2, op, nops, ops, ae), \
14845 xCM_(m1, al, m2, op, nops, ops, ae)
14847 #define UE(mnem, op, nops, ops, ae) \
14848 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14850 #define UF(mnem, op, nops, ops, ae) \
14851 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14853 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14854 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14855 use the same encoding function for each. */
14856 #define NUF(mnem, op, nops, ops, enc) \
14857 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14858 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14860 /* Neon data processing, version which indirects through neon_enc_tab for
14861 the various overloaded versions of opcodes. */
14862 #define nUF(mnem, op, nops, ops, enc) \
14863 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14864 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14866 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14868 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14869 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14870 THUMB_VARIANT, do_##enc, do_##enc }
14872 #define NCE(mnem, op, nops, ops, enc) \
14873 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14875 #define NCEF(mnem, op, nops, ops, enc) \
14876 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14878 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14879 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14880 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14881 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14883 #define nCE(mnem, op, nops, ops, enc) \
14884 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14886 #define nCEF(mnem, op, nops, ops, enc) \
14887 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14891 /* Thumb-only, unconditional. */
14892 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14894 static const struct asm_opcode insns
[] =
14896 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14897 #define THUMB_VARIANT &arm_ext_v4t
14898 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14899 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14900 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14901 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14902 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14903 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14904 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14905 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14906 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14907 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14908 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14909 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14910 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14911 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14912 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14913 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14915 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14916 for setting PSR flag bits. They are obsolete in V6 and do not
14917 have Thumb equivalents. */
14918 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14919 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14920 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14921 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14922 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14923 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14924 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14925 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14926 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14928 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14929 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14930 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14931 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14933 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14934 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14935 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14936 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14938 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14939 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14940 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14941 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14942 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14943 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14945 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14946 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14947 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14948 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14951 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14952 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14953 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14955 /* Thumb-compatibility pseudo ops. */
14956 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14957 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14958 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14959 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14960 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14961 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14962 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14963 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14964 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14965 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14966 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14967 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14969 /* These may simplify to neg. */
14970 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14971 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14973 #undef THUMB_VARIANT
14974 #define THUMB_VARIANT &arm_ext_v6
14975 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14977 /* V1 instructions with no Thumb analogue prior to V6T2. */
14978 #undef THUMB_VARIANT
14979 #define THUMB_VARIANT &arm_ext_v6t2
14980 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14981 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14982 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14984 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14985 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14986 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14987 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14989 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14990 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14992 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14993 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14995 /* V1 instructions with no Thumb analogue at all. */
14996 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14997 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14999 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15000 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15001 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15002 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15003 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15004 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15005 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15006 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15009 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
15010 #undef THUMB_VARIANT
15011 #define THUMB_VARIANT &arm_ext_v4t
15012 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15013 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15015 #undef THUMB_VARIANT
15016 #define THUMB_VARIANT &arm_ext_v6t2
15017 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15018 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
15020 /* Generic coprocessor instructions. */
15021 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15022 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15023 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15024 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15025 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15026 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15027 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15030 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15031 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15032 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15035 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15036 #undef THUMB_VARIANT
15037 #define THUMB_VARIANT &arm_ext_msr
15038 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
15039 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
15042 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15043 #undef THUMB_VARIANT
15044 #define THUMB_VARIANT &arm_ext_v6t2
15045 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15046 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15047 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15048 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15049 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15050 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15051 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15052 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15055 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15056 #undef THUMB_VARIANT
15057 #define THUMB_VARIANT &arm_ext_v4t
15058 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15059 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15060 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15061 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15062 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15063 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15066 #define ARM_VARIANT &arm_ext_v4t_5
15067 /* ARM Architecture 4T. */
15068 /* Note: bx (and blx) are required on V5, even if the processor does
15069 not support Thumb. */
15070 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
15073 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15074 #undef THUMB_VARIANT
15075 #define THUMB_VARIANT &arm_ext_v5t
15076 /* Note: blx has 2 variants; the .value coded here is for
15077 BLX(2). Only this variant has conditional execution. */
15078 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
15079 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
15081 #undef THUMB_VARIANT
15082 #define THUMB_VARIANT &arm_ext_v6t2
15083 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
15084 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15085 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15086 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15087 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15088 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15089 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15090 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15093 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15094 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15095 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15096 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15097 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15099 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15100 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15102 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15103 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15104 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15105 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15107 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15108 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15109 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15110 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15112 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15113 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15115 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15116 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15117 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15118 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15121 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15122 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
15123 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15124 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15126 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15127 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15130 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15131 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
15134 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15135 #undef THUMB_VARIANT
15136 #define THUMB_VARIANT &arm_ext_v6
15137 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15138 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15139 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15140 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15141 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15142 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15143 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15144 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15145 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15146 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
15148 #undef THUMB_VARIANT
15149 #define THUMB_VARIANT &arm_ext_v6t2
15150 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
15151 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
15152 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15153 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15155 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
15156 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
15158 /* ARM V6 not included in V7M (eg. integer SIMD). */
15159 #undef THUMB_VARIANT
15160 #define THUMB_VARIANT &arm_ext_v6_notm
15161 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
15162 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
15163 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
15164 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15165 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15166 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15167 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15168 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15169 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15170 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15171 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15172 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15173 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15174 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15175 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15176 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15177 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15178 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15179 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15180 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15181 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15182 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15183 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15184 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15185 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15186 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15187 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15188 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15189 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15190 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15191 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15192 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15193 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15194 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15195 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15196 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15197 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15198 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15199 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15200 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15201 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
15202 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
15203 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15204 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15205 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
15206 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
15207 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15208 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15209 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15210 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15211 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15212 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15213 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15214 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15215 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15216 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15217 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15218 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15219 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15220 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15221 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15222 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15223 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15224 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15225 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15226 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15227 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15228 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15229 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15230 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15231 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15232 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15233 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15234 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15235 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
15236 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
15237 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
15238 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
15239 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
15240 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
15241 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15242 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15243 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15246 #define ARM_VARIANT &arm_ext_v6k
15247 #undef THUMB_VARIANT
15248 #define THUMB_VARIANT &arm_ext_v6k
15249 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15250 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15251 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15252 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15254 #undef THUMB_VARIANT
15255 #define THUMB_VARIANT &arm_ext_v6_notm
15256 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15257 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15259 #undef THUMB_VARIANT
15260 #define THUMB_VARIANT &arm_ext_v6t2
15261 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15262 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15263 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15264 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15265 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15268 #define ARM_VARIANT &arm_ext_v6z
15269 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15272 #define ARM_VARIANT &arm_ext_v6t2
15273 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15274 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15275 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15276 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15278 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15279 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15280 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15281 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15283 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15284 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15285 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15286 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15288 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15289 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15290 /* ARM does not really have an IT instruction, so always allow it. */
15292 #define ARM_VARIANT &arm_ext_v1
15293 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15294 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15295 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15296 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15297 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15298 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15299 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15300 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15301 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15302 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15303 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15304 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15305 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15306 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15307 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15309 /* Thumb2 only instructions. */
15311 #define ARM_VARIANT NULL
15313 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15314 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15315 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15316 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15318 /* Thumb-2 hardware division instructions (R and M profiles only). */
15319 #undef THUMB_VARIANT
15320 #define THUMB_VARIANT &arm_ext_div
15321 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15322 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15324 /* ARM V6M/V7 instructions. */
15326 #define ARM_VARIANT &arm_ext_barrier
15327 #undef THUMB_VARIANT
15328 #define THUMB_VARIANT &arm_ext_barrier
15329 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15330 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15331 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15333 /* ARM V7 instructions. */
15335 #define ARM_VARIANT &arm_ext_v7
15336 #undef THUMB_VARIANT
15337 #define THUMB_VARIANT &arm_ext_v7
15338 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15339 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15342 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15343 cCE(wfs
, e200110
, 1, (RR
), rd
),
15344 cCE(rfs
, e300110
, 1, (RR
), rd
),
15345 cCE(wfc
, e400110
, 1, (RR
), rd
),
15346 cCE(rfc
, e500110
, 1, (RR
), rd
),
15348 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15349 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15350 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15351 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15353 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15354 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15355 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15356 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15358 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15359 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15360 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15361 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15362 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15363 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15364 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15365 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15366 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15367 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15368 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15369 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15371 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15372 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15373 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15374 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15375 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15376 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15377 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15378 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15379 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15380 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15381 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15382 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15384 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15385 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15386 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15387 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15388 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15389 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15390 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15391 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15392 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15393 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15394 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15395 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15397 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15398 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15399 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15400 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15401 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15402 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15403 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15404 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15405 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15406 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15407 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15408 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15410 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15411 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15412 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15413 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15414 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15415 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15416 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15417 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15418 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15419 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15420 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15421 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15423 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15424 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15425 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15426 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15427 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15428 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15429 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15430 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15431 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15432 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15433 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15434 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15436 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15437 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15438 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15439 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15440 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15441 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15442 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15443 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15444 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15445 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15446 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15447 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15449 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15450 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
15451 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
15452 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
15453 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
15454 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
15455 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
15456 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
15457 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
15458 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
15459 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
15460 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
15462 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
15463 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
15464 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15465 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15466 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15467 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15468 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15469 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15470 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15471 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15472 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15473 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15475 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15476 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15477 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15478 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15479 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15480 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15481 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15482 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15483 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15484 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15485 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15486 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15488 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15489 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15490 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15491 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15492 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15493 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15494 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15495 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15496 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15497 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15498 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15499 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15501 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15502 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15503 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15504 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15505 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15506 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15507 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15508 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15509 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15510 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15511 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15512 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15514 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15515 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15516 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15517 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15518 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15519 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15520 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15521 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15522 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15523 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15524 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15525 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15527 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15528 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15529 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15530 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15531 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15532 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15533 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15534 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15535 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15536 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15537 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15538 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15540 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15541 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15542 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15543 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15544 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15545 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15546 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15547 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15548 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15549 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15550 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15551 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15553 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15554 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15555 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15556 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15557 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15558 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15559 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15560 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15561 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15562 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15563 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15564 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15566 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15567 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15568 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15569 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15570 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15571 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15572 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15573 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15574 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15575 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15576 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15577 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15579 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15580 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15581 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15582 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15583 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15584 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15585 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15586 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15587 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15588 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15589 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15590 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15592 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15593 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15594 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15595 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15596 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15597 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15598 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15599 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15600 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15601 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15602 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15603 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15605 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15606 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15607 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15608 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15609 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15610 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15611 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15612 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15613 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15614 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15615 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15616 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15618 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15619 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15620 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15621 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15622 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15623 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15624 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15625 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15626 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15627 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15628 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15629 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15631 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15632 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15633 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15634 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15635 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15636 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15637 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15638 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15639 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15640 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15641 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15642 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15644 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15645 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15646 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15647 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15648 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15649 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15650 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15651 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15652 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15653 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15654 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15655 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15657 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15658 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15659 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15660 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15661 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15662 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15663 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15664 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15665 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15666 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15667 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15668 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15670 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15671 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15672 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15673 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15674 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15675 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15676 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15677 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15678 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15679 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15680 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15681 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15683 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15684 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15685 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15686 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15687 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15688 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15689 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15690 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15691 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15692 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15693 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15694 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15696 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15697 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15698 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15699 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15700 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15701 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15702 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15703 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15704 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15705 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15706 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15707 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15709 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15710 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15711 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15712 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15713 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15714 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15715 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15716 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15717 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15718 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15719 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15720 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15722 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15723 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15724 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15725 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15726 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15727 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15728 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15729 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15730 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15731 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15732 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15733 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15735 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15736 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15737 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15738 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15740 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15741 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15742 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15743 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15744 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15745 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15746 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15747 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15748 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15749 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15750 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15751 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15753 /* The implementation of the FIX instruction is broken on some
15754 assemblers, in that it accepts a precision specifier as well as a
15755 rounding specifier, despite the fact that this is meaningless.
15756 To be more compatible, we accept it as well, though of course it
15757 does not set any bits. */
15758 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15759 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15760 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15761 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15762 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15763 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15764 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15765 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15766 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15767 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15768 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15769 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15770 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15772 /* Instructions that were new with the real FPA, call them V2. */
15774 #define ARM_VARIANT &fpu_fpa_ext_v2
15775 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15776 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15777 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15778 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15779 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15780 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15783 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15784 /* Moves and type conversions. */
15785 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15786 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15787 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15788 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15789 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15790 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15791 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15792 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15793 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15794 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15795 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15796 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15798 /* Memory operations. */
15799 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15800 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15801 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15802 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15803 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15804 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15805 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15806 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15807 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15808 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15809 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15810 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15811 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15812 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15813 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15814 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15815 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15816 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15818 /* Monadic operations. */
15819 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15820 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15821 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15823 /* Dyadic operations. */
15824 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15825 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15826 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15827 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15828 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15829 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15830 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15831 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15832 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15835 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15836 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15837 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15838 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15841 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15842 /* Moves and type conversions. */
15843 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15844 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15845 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15846 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15847 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15848 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15849 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15850 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15851 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15852 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15853 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15854 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15855 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15857 /* Memory operations. */
15858 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15859 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15860 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15861 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15862 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15863 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15864 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15865 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15866 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15867 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15869 /* Monadic operations. */
15870 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15871 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15872 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15874 /* Dyadic operations. */
15875 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15876 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15877 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15878 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15879 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15880 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15881 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15882 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15883 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15886 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15887 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15888 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15889 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15892 #define ARM_VARIANT &fpu_vfp_ext_v2
15893 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15894 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15895 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15896 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15898 /* Instructions which may belong to either the Neon or VFP instruction sets.
15899 Individual encoder functions perform additional architecture checks. */
15901 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15902 #undef THUMB_VARIANT
15903 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15904 /* These mnemonics are unique to VFP. */
15905 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15906 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15907 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15908 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15909 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15910 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15911 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15912 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15913 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15914 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15916 /* Mnemonics shared by Neon and VFP. */
15917 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15918 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15919 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15921 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15922 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15924 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15925 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15927 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15928 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15929 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15930 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15931 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15932 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15933 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15934 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15936 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15938 /* NOTE: All VMOV encoding is special-cased! */
15939 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15940 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15942 #undef THUMB_VARIANT
15943 #define THUMB_VARIANT &fpu_neon_ext_v1
15945 #define ARM_VARIANT &fpu_neon_ext_v1
15946 /* Data processing with three registers of the same length. */
15947 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15948 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15949 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15950 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15951 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15952 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15953 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15954 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15955 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15956 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15957 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15958 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15959 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15960 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15961 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15962 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15963 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15964 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15965 /* If not immediate, fall back to neon_dyadic_i64_su.
15966 shl_imm should accept I8 I16 I32 I64,
15967 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15968 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15969 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15970 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15971 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15972 /* Logic ops, types optional & ignored. */
15973 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15974 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15975 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15976 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15977 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15978 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15979 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15980 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15981 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15982 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15983 /* Bitfield ops, untyped. */
15984 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15985 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15986 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15987 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15988 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15989 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15990 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15991 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15992 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15993 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15994 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15995 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15996 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15997 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15998 back to neon_dyadic_if_su. */
15999 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16000 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16001 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16002 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16003 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16004 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16005 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16006 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16007 /* Comparison. Type I8 I16 I32 F32. */
16008 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
16009 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
16010 /* As above, D registers only. */
16011 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16012 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16013 /* Int and float variants, signedness unimportant. */
16014 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16015 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16016 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
16017 /* Add/sub take types I8 I16 I32 I64 F32. */
16018 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16019 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16020 /* vtst takes sizes 8, 16, 32. */
16021 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
16022 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
16023 /* VMUL takes I8 I16 I32 F32 P8. */
16024 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
16025 /* VQD{R}MULH takes S16 S32. */
16026 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16027 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16028 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16029 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16030 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16031 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16032 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16033 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16034 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16035 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16036 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16037 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16038 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16039 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16040 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16041 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16043 /* Two address, int/float. Types S8 S16 S32 F32. */
16044 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16045 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16047 /* Data processing with two registers and a shift amount. */
16048 /* Right shifts, and variants with rounding.
16049 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16050 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16051 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16052 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16053 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16054 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16055 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16056 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16057 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16058 /* Shift and insert. Sizes accepted 8 16 32 64. */
16059 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
16060 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
16061 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
16062 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
16063 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16064 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
16065 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
16066 /* Right shift immediate, saturating & narrowing, with rounding variants.
16067 Types accepted S16 S32 S64 U16 U32 U64. */
16068 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16069 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16070 /* As above, unsigned. Types accepted S16 S32 S64. */
16071 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16072 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16073 /* Right shift narrowing. Types accepted I16 I32 I64. */
16074 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16075 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16076 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16077 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
16078 /* CVT with optional immediate for fixed-point variant. */
16079 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
16081 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
16082 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
16084 /* Data processing, three registers of different lengths. */
16085 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16086 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
16087 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16088 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16089 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16090 /* If not scalar, fall back to neon_dyadic_long.
16091 Vector types as above, scalar types S16 S32 U16 U32. */
16092 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16093 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16094 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16095 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16096 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16097 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16098 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16099 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16100 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16101 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16102 /* Saturating doubling multiplies. Types S16 S32. */
16103 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16104 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16105 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16106 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16107 S16 S32 U16 U32. */
16108 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
16110 /* Extract. Size 8. */
16111 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
16112 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
16114 /* Two registers, miscellaneous. */
16115 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16116 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
16117 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
16118 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
16119 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
16120 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
16121 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
16122 /* Vector replicate. Sizes 8 16 32. */
16123 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
16124 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
16125 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16126 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
16127 /* VMOVN. Types I16 I32 I64. */
16128 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
16129 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16130 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
16131 /* VQMOVUN. Types S16 S32 S64. */
16132 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
16133 /* VZIP / VUZP. Sizes 8 16 32. */
16134 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16135 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16136 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16137 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16138 /* VQABS / VQNEG. Types S8 S16 S32. */
16139 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16140 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16141 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16142 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16143 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16144 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16145 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
16146 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16147 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
16148 /* Reciprocal estimates. Types U32 F32. */
16149 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16150 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
16151 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16152 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
16153 /* VCLS. Types S8 S16 S32. */
16154 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
16155 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
16156 /* VCLZ. Types I8 I16 I32. */
16157 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
16158 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
16159 /* VCNT. Size 8. */
16160 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
16161 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
16162 /* Two address, untyped. */
16163 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
16164 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
16165 /* VTRN. Sizes 8 16 32. */
16166 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
16167 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
16169 /* Table lookup. Size 8. */
16170 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16171 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16173 #undef THUMB_VARIANT
16174 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16176 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16177 /* Neon element/structure load/store. */
16178 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16179 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16180 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16181 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16182 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16183 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16184 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16185 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16187 #undef THUMB_VARIANT
16188 #define THUMB_VARIANT &fpu_vfp_ext_v3
16190 #define ARM_VARIANT &fpu_vfp_ext_v3
16191 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
16192 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
16193 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16194 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16195 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16196 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16197 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16198 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16199 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16200 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16201 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16202 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16203 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16204 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16205 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16206 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16207 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16208 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16210 #undef THUMB_VARIANT
16212 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16213 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16214 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16215 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16216 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16217 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16218 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16219 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
16220 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
16223 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16224 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
16225 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
16226 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
16227 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
16228 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
16229 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
16230 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
16231 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
16232 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
16233 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16234 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16235 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16236 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16237 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16238 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16239 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16240 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16241 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16242 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
16243 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
16244 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16245 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16246 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16247 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16248 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16249 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16250 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
16251 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16252 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16253 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16254 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16255 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16256 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16257 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16258 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16259 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16260 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16261 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16262 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16263 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16264 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16265 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16266 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16267 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16268 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16269 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16270 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16271 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16272 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16273 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16274 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16275 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16276 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16277 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16278 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16279 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16280 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16281 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16282 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16283 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16284 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16285 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16286 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16287 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16288 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16289 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16290 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16291 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16292 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16293 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16294 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16295 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16296 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16297 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16298 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16299 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16300 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16301 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16302 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16303 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16304 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16305 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16306 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16307 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16308 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16309 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16310 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16311 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16312 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16313 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16314 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16315 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16316 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16317 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16318 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16319 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16320 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16321 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16322 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16323 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16324 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16325 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16326 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16327 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16328 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16329 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16330 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16331 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16332 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16333 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16334 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16335 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16336 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16337 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16338 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16339 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16340 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16341 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16342 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16343 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16344 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16345 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16346 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16347 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16348 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16349 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16350 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16351 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16352 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16353 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16354 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16355 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16356 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16357 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16358 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16359 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16360 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16361 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16362 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16363 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16364 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16365 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16366 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16367 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16368 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16369 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16370 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16371 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16372 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16373 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16374 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16375 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16376 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16377 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16378 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16379 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16380 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16381 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16382 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16383 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16384 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16385 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16388 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16389 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16390 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16391 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16392 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16393 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16394 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16395 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16396 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16397 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16398 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16399 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16400 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16401 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16402 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16403 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16404 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16405 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16406 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16407 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16408 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16409 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16410 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16411 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16412 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16413 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16414 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16415 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16416 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16417 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16418 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16419 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16420 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16421 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16422 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16423 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16424 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16425 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16426 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16427 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16428 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16429 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16430 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16431 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16432 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16433 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16434 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16435 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16436 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16437 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16438 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16439 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16440 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16441 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16442 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16443 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16444 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16445 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16448 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16449 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16450 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16451 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16452 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16453 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16454 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16455 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16456 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16457 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
16458 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
16459 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
16460 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
16461 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
16462 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
16463 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
16464 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
16465 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
16466 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
16467 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
16468 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
16469 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
16470 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
16471 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
16472 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
16473 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
16474 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
16475 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
16476 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
16477 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
16478 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
16479 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
16480 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
16481 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
16482 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
16483 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
16484 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
16485 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
16486 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
16487 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
16488 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
16489 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
16490 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
16491 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
16492 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
16493 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
16494 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
16495 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
16496 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
16497 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
16498 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
16499 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
16500 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
16501 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
16502 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
16503 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16504 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16505 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16506 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16507 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16508 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16509 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
16510 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
16511 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
16512 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
16513 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16514 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16515 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16516 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16517 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16518 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16519 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16520 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16521 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16522 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16523 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16524 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16527 #undef THUMB_VARIANT
16554 /* MD interface: bits in the object file. */
16556 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16557 for use in the a.out file, and stores them in the array pointed to by buf.
16558 This knows about the endian-ness of the target machine and does
16559 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16560 2 (short) and 4 (long) Floating numbers are put out as a series of
16561 LITTLENUMS (shorts, here at least). */
16564 md_number_to_chars (char * buf
, valueT val
, int n
)
16566 if (target_big_endian
)
16567 number_to_chars_bigendian (buf
, val
, n
);
16569 number_to_chars_littleendian (buf
, val
, n
);
16573 md_chars_to_number (char * buf
, int n
)
16576 unsigned char * where
= (unsigned char *) buf
;
16578 if (target_big_endian
)
16583 result
|= (*where
++ & 255);
16591 result
|= (where
[n
] & 255);
16598 /* MD interface: Sections. */
16600 /* Estimate the size of a frag before relaxing. Assume everything fits in
16604 md_estimate_size_before_relax (fragS
* fragp
,
16605 segT segtype ATTRIBUTE_UNUSED
)
16611 /* Convert a machine dependent frag. */
16614 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16616 unsigned long insn
;
16617 unsigned long old_op
;
16625 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16627 old_op
= bfd_get_16(abfd
, buf
);
16628 if (fragp
->fr_symbol
)
16630 exp
.X_op
= O_symbol
;
16631 exp
.X_add_symbol
= fragp
->fr_symbol
;
16635 exp
.X_op
= O_constant
;
16637 exp
.X_add_number
= fragp
->fr_offset
;
16638 opcode
= fragp
->fr_subtype
;
16641 case T_MNEM_ldr_pc
:
16642 case T_MNEM_ldr_pc2
:
16643 case T_MNEM_ldr_sp
:
16644 case T_MNEM_str_sp
:
16651 if (fragp
->fr_var
== 4)
16653 insn
= THUMB_OP32 (opcode
);
16654 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16656 insn
|= (old_op
& 0x700) << 4;
16660 insn
|= (old_op
& 7) << 12;
16661 insn
|= (old_op
& 0x38) << 13;
16663 insn
|= 0x00000c00;
16664 put_thumb32_insn (buf
, insn
);
16665 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16669 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16671 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16674 if (fragp
->fr_var
== 4)
16676 insn
= THUMB_OP32 (opcode
);
16677 insn
|= (old_op
& 0xf0) << 4;
16678 put_thumb32_insn (buf
, insn
);
16679 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16683 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16684 exp
.X_add_number
-= 4;
16692 if (fragp
->fr_var
== 4)
16694 int r0off
= (opcode
== T_MNEM_mov
16695 || opcode
== T_MNEM_movs
) ? 0 : 8;
16696 insn
= THUMB_OP32 (opcode
);
16697 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16698 insn
|= (old_op
& 0x700) << r0off
;
16699 put_thumb32_insn (buf
, insn
);
16700 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16704 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16709 if (fragp
->fr_var
== 4)
16711 insn
= THUMB_OP32(opcode
);
16712 put_thumb32_insn (buf
, insn
);
16713 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16716 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16720 if (fragp
->fr_var
== 4)
16722 insn
= THUMB_OP32(opcode
);
16723 insn
|= (old_op
& 0xf00) << 14;
16724 put_thumb32_insn (buf
, insn
);
16725 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16728 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16731 case T_MNEM_add_sp
:
16732 case T_MNEM_add_pc
:
16733 case T_MNEM_inc_sp
:
16734 case T_MNEM_dec_sp
:
16735 if (fragp
->fr_var
== 4)
16737 /* ??? Choose between add and addw. */
16738 insn
= THUMB_OP32 (opcode
);
16739 insn
|= (old_op
& 0xf0) << 4;
16740 put_thumb32_insn (buf
, insn
);
16741 if (opcode
== T_MNEM_add_pc
)
16742 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16744 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16747 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16755 if (fragp
->fr_var
== 4)
16757 insn
= THUMB_OP32 (opcode
);
16758 insn
|= (old_op
& 0xf0) << 4;
16759 insn
|= (old_op
& 0xf) << 16;
16760 put_thumb32_insn (buf
, insn
);
16761 if (insn
& (1 << 20))
16762 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16764 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16767 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16773 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16775 fixp
->fx_file
= fragp
->fr_file
;
16776 fixp
->fx_line
= fragp
->fr_line
;
16777 fragp
->fr_fix
+= fragp
->fr_var
;
16780 /* Return the size of a relaxable immediate operand instruction.
16781 SHIFT and SIZE specify the form of the allowable immediate. */
16783 relax_immediate (fragS
*fragp
, int size
, int shift
)
16789 /* ??? Should be able to do better than this. */
16790 if (fragp
->fr_symbol
)
16793 low
= (1 << shift
) - 1;
16794 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16795 offset
= fragp
->fr_offset
;
16796 /* Force misaligned offsets to 32-bit variant. */
16799 if (offset
& ~mask
)
16804 /* Get the address of a symbol during relaxation. */
16806 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
16812 sym
= fragp
->fr_symbol
;
16813 sym_frag
= symbol_get_frag (sym
);
16814 know (S_GET_SEGMENT (sym
) != absolute_section
16815 || sym_frag
== &zero_address_frag
);
16816 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
16818 /* If frag has yet to be reached on this pass, assume it will
16819 move by STRETCH just as we did. If this is not so, it will
16820 be because some frag between grows, and that will force
16824 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16828 /* Adjust stretch for any alignment frag. Note that if have
16829 been expanding the earlier code, the symbol may be
16830 defined in what appears to be an earlier frag. FIXME:
16831 This doesn't handle the fr_subtype field, which specifies
16832 a maximum number of bytes to skip when doing an
16834 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16836 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16839 stretch
= - ((- stretch
)
16840 & ~ ((1 << (int) f
->fr_offset
) - 1));
16842 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16854 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16857 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
16862 /* Assume worst case for symbols not known to be in the same section. */
16863 if (!S_IS_DEFINED (fragp
->fr_symbol
)
16864 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16867 val
= relaxed_symbol_addr (fragp
, stretch
);
16868 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16869 addr
= (addr
+ 4) & ~3;
16870 /* Force misaligned targets to 32-bit variant. */
16874 if (val
< 0 || val
> 1020)
16879 /* Return the size of a relaxable add/sub immediate instruction. */
16881 relax_addsub (fragS
*fragp
, asection
*sec
)
16886 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16887 op
= bfd_get_16(sec
->owner
, buf
);
16888 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16889 return relax_immediate (fragp
, 8, 0);
16891 return relax_immediate (fragp
, 3, 0);
16895 /* Return the size of a relaxable branch instruction. BITS is the
16896 size of the offset field in the narrow instruction. */
16899 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
16905 /* Assume worst case for symbols not known to be in the same section. */
16906 if (!S_IS_DEFINED (fragp
->fr_symbol
)
16907 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16910 val
= relaxed_symbol_addr (fragp
, stretch
);
16911 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16914 /* Offset is a signed value *2 */
16916 if (val
>= limit
|| val
< -limit
)
16922 /* Relax a machine dependent frag. This returns the amount by which
16923 the current size of the frag should change. */
16926 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16931 oldsize
= fragp
->fr_var
;
16932 switch (fragp
->fr_subtype
)
16934 case T_MNEM_ldr_pc2
:
16935 newsize
= relax_adr (fragp
, sec
, stretch
);
16937 case T_MNEM_ldr_pc
:
16938 case T_MNEM_ldr_sp
:
16939 case T_MNEM_str_sp
:
16940 newsize
= relax_immediate (fragp
, 8, 2);
16944 newsize
= relax_immediate (fragp
, 5, 2);
16948 newsize
= relax_immediate (fragp
, 5, 1);
16952 newsize
= relax_immediate (fragp
, 5, 0);
16955 newsize
= relax_adr (fragp
, sec
, stretch
);
16961 newsize
= relax_immediate (fragp
, 8, 0);
16964 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
16967 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
16969 case T_MNEM_add_sp
:
16970 case T_MNEM_add_pc
:
16971 newsize
= relax_immediate (fragp
, 8, 2);
16973 case T_MNEM_inc_sp
:
16974 case T_MNEM_dec_sp
:
16975 newsize
= relax_immediate (fragp
, 7, 2);
16981 newsize
= relax_addsub (fragp
, sec
);
16987 fragp
->fr_var
= newsize
;
16988 /* Freeze wide instructions that are at or before the same location as
16989 in the previous pass. This avoids infinite loops.
16990 Don't freeze them unconditionally because targets may be artificially
16991 misaligned by the expansion of preceding frags. */
16992 if (stretch
<= 0 && newsize
> 2)
16994 md_convert_frag (sec
->owner
, sec
, fragp
);
16998 return newsize
- oldsize
;
17001 /* Round up a section size to the appropriate boundary. */
17004 md_section_align (segT segment ATTRIBUTE_UNUSED
,
17007 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
17008 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
17010 /* For a.out, force the section size to be aligned. If we don't do
17011 this, BFD will align it for us, but it will not write out the
17012 final bytes of the section. This may be a bug in BFD, but it is
17013 easier to fix it here since that is how the other a.out targets
17017 align
= bfd_get_section_alignment (stdoutput
, segment
);
17018 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
17025 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
17026 of an rs_align_code fragment. */
17029 arm_handle_align (fragS
* fragP
)
17031 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
17032 static char const thumb_noop
[2] = { 0xc0, 0x46 };
17033 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
17034 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
17036 int bytes
, fix
, noop_size
;
17040 if (fragP
->fr_type
!= rs_align_code
)
17043 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
17044 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
17047 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17048 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
17050 if (fragP
->tc_frag_data
)
17052 if (target_big_endian
)
17053 noop
= thumb_bigend_noop
;
17056 noop_size
= sizeof (thumb_noop
);
17060 if (target_big_endian
)
17061 noop
= arm_bigend_noop
;
17064 noop_size
= sizeof (arm_noop
);
17067 if (bytes
& (noop_size
- 1))
17069 fix
= bytes
& (noop_size
- 1);
17070 memset (p
, 0, fix
);
17075 while (bytes
>= noop_size
)
17077 memcpy (p
, noop
, noop_size
);
17079 bytes
-= noop_size
;
17083 fragP
->fr_fix
+= fix
;
17084 fragP
->fr_var
= noop_size
;
17087 /* Called from md_do_align. Used to create an alignment
17088 frag in a code section. */
17091 arm_frag_align_code (int n
, int max
)
17095 /* We assume that there will never be a requirement
17096 to support alignments greater than 32 bytes. */
17097 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17098 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17100 p
= frag_var (rs_align_code
,
17101 MAX_MEM_FOR_RS_ALIGN_CODE
,
17103 (relax_substateT
) max
,
17110 /* Perform target specific initialisation of a frag. */
17113 arm_init_frag (fragS
* fragP
)
17115 /* Record whether this frag is in an ARM or a THUMB area. */
17116 fragP
->tc_frag_data
= thumb_mode
;
17120 /* When we change sections we need to issue a new mapping symbol. */
17123 arm_elf_change_section (void)
17126 segment_info_type
*seginfo
;
17128 /* Link an unlinked unwind index table section to the .text section. */
17129 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
17130 && elf_linked_to_section (now_seg
) == NULL
)
17131 elf_linked_to_section (now_seg
) = text_section
;
17133 if (!SEG_NORMAL (now_seg
))
17136 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
17138 /* We can ignore sections that only contain debug info. */
17139 if ((flags
& SEC_ALLOC
) == 0)
17142 seginfo
= seg_info (now_seg
);
17143 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
17144 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
17148 arm_elf_section_type (const char * str
, size_t len
)
17150 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
17151 return SHT_ARM_EXIDX
;
17156 /* Code to deal with unwinding tables. */
17158 static void add_unwind_adjustsp (offsetT
);
17160 /* Generate any deferred unwind frame offset. */
17163 flush_pending_unwind (void)
17167 offset
= unwind
.pending_offset
;
17168 unwind
.pending_offset
= 0;
17170 add_unwind_adjustsp (offset
);
17173 /* Add an opcode to this list for this function. Two-byte opcodes should
17174 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17178 add_unwind_opcode (valueT op
, int length
)
17180 /* Add any deferred stack adjustment. */
17181 if (unwind
.pending_offset
)
17182 flush_pending_unwind ();
17184 unwind
.sp_restored
= 0;
17186 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
17188 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
17189 if (unwind
.opcodes
)
17190 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
17191 unwind
.opcode_alloc
);
17193 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
17198 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
17200 unwind
.opcode_count
++;
17204 /* Add unwind opcodes to adjust the stack pointer. */
17207 add_unwind_adjustsp (offsetT offset
)
17211 if (offset
> 0x200)
17213 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17218 /* Long form: 0xb2, uleb128. */
17219 /* This might not fit in a word so add the individual bytes,
17220 remembering the list is built in reverse order. */
17221 o
= (valueT
) ((offset
- 0x204) >> 2);
17223 add_unwind_opcode (0, 1);
17225 /* Calculate the uleb128 encoding of the offset. */
17229 bytes
[n
] = o
& 0x7f;
17235 /* Add the insn. */
17237 add_unwind_opcode (bytes
[n
- 1], 1);
17238 add_unwind_opcode (0xb2, 1);
17240 else if (offset
> 0x100)
17242 /* Two short opcodes. */
17243 add_unwind_opcode (0x3f, 1);
17244 op
= (offset
- 0x104) >> 2;
17245 add_unwind_opcode (op
, 1);
17247 else if (offset
> 0)
17249 /* Short opcode. */
17250 op
= (offset
- 4) >> 2;
17251 add_unwind_opcode (op
, 1);
17253 else if (offset
< 0)
17256 while (offset
> 0x100)
17258 add_unwind_opcode (0x7f, 1);
17261 op
= ((offset
- 4) >> 2) | 0x40;
17262 add_unwind_opcode (op
, 1);
17266 /* Finish the list of unwind opcodes for this function. */
17268 finish_unwind_opcodes (void)
17272 if (unwind
.fp_used
)
17274 /* Adjust sp as necessary. */
17275 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
17276 flush_pending_unwind ();
17278 /* After restoring sp from the frame pointer. */
17279 op
= 0x90 | unwind
.fp_reg
;
17280 add_unwind_opcode (op
, 1);
17283 flush_pending_unwind ();
17287 /* Start an exception table entry. If idx is nonzero this is an index table
17291 start_unwind_section (const segT text_seg
, int idx
)
17293 const char * text_name
;
17294 const char * prefix
;
17295 const char * prefix_once
;
17296 const char * group_name
;
17300 size_t sec_name_len
;
17307 prefix
= ELF_STRING_ARM_unwind
;
17308 prefix_once
= ELF_STRING_ARM_unwind_once
;
17309 type
= SHT_ARM_EXIDX
;
17313 prefix
= ELF_STRING_ARM_unwind_info
;
17314 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17315 type
= SHT_PROGBITS
;
17318 text_name
= segment_name (text_seg
);
17319 if (streq (text_name
, ".text"))
17322 if (strncmp (text_name
, ".gnu.linkonce.t.",
17323 strlen (".gnu.linkonce.t.")) == 0)
17325 prefix
= prefix_once
;
17326 text_name
+= strlen (".gnu.linkonce.t.");
17329 prefix_len
= strlen (prefix
);
17330 text_len
= strlen (text_name
);
17331 sec_name_len
= prefix_len
+ text_len
;
17332 sec_name
= xmalloc (sec_name_len
+ 1);
17333 memcpy (sec_name
, prefix
, prefix_len
);
17334 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17335 sec_name
[prefix_len
+ text_len
] = '\0';
17341 /* Handle COMDAT group. */
17342 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17344 group_name
= elf_group_name (text_seg
);
17345 if (group_name
== NULL
)
17347 as_bad (_("Group section `%s' has no group signature"),
17348 segment_name (text_seg
));
17349 ignore_rest_of_line ();
17352 flags
|= SHF_GROUP
;
17356 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17358 /* Set the section link for index tables. */
17360 elf_linked_to_section (now_seg
) = text_seg
;
17364 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17365 personality routine data. Returns zero, or the index table value for
17366 and inline entry. */
17369 create_unwind_entry (int have_data
)
17374 /* The current word of data. */
17376 /* The number of bytes left in this word. */
17379 finish_unwind_opcodes ();
17381 /* Remember the current text section. */
17382 unwind
.saved_seg
= now_seg
;
17383 unwind
.saved_subseg
= now_subseg
;
17385 start_unwind_section (now_seg
, 0);
17387 if (unwind
.personality_routine
== NULL
)
17389 if (unwind
.personality_index
== -2)
17392 as_bad (_("handlerdata in cantunwind frame"));
17393 return 1; /* EXIDX_CANTUNWIND. */
17396 /* Use a default personality routine if none is specified. */
17397 if (unwind
.personality_index
== -1)
17399 if (unwind
.opcode_count
> 3)
17400 unwind
.personality_index
= 1;
17402 unwind
.personality_index
= 0;
17405 /* Space for the personality routine entry. */
17406 if (unwind
.personality_index
== 0)
17408 if (unwind
.opcode_count
> 3)
17409 as_bad (_("too many unwind opcodes for personality routine 0"));
17413 /* All the data is inline in the index table. */
17416 while (unwind
.opcode_count
> 0)
17418 unwind
.opcode_count
--;
17419 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17423 /* Pad with "finish" opcodes. */
17425 data
= (data
<< 8) | 0xb0;
17432 /* We get two opcodes "free" in the first word. */
17433 size
= unwind
.opcode_count
- 2;
17436 /* An extra byte is required for the opcode count. */
17437 size
= unwind
.opcode_count
+ 1;
17439 size
= (size
+ 3) >> 2;
17441 as_bad (_("too many unwind opcodes"));
17443 frag_align (2, 0, 0);
17444 record_alignment (now_seg
, 2);
17445 unwind
.table_entry
= expr_build_dot ();
17447 /* Allocate the table entry. */
17448 ptr
= frag_more ((size
<< 2) + 4);
17449 where
= frag_now_fix () - ((size
<< 2) + 4);
17451 switch (unwind
.personality_index
)
17454 /* ??? Should this be a PLT generating relocation? */
17455 /* Custom personality routine. */
17456 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
17457 BFD_RELOC_ARM_PREL31
);
17462 /* Set the first byte to the number of additional words. */
17467 /* ABI defined personality routines. */
17469 /* Three opcodes bytes are packed into the first word. */
17476 /* The size and first two opcode bytes go in the first word. */
17477 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
17482 /* Should never happen. */
17486 /* Pack the opcodes into words (MSB first), reversing the list at the same
17488 while (unwind
.opcode_count
> 0)
17492 md_number_to_chars (ptr
, data
, 4);
17497 unwind
.opcode_count
--;
17499 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17502 /* Finish off the last word. */
17505 /* Pad with "finish" opcodes. */
17507 data
= (data
<< 8) | 0xb0;
17509 md_number_to_chars (ptr
, data
, 4);
17514 /* Add an empty descriptor if there is no user-specified data. */
17515 ptr
= frag_more (4);
17516 md_number_to_chars (ptr
, 0, 4);
17523 /* Initialize the DWARF-2 unwind information for this procedure. */
17526 tc_arm_frame_initial_instructions (void)
17528 cfi_add_CFA_def_cfa (REG_SP
, 0);
17530 #endif /* OBJ_ELF */
17532 /* Convert REGNAME to a DWARF-2 register number. */
17535 tc_arm_regname_to_dw2regnum (char *regname
)
17537 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
17547 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
17551 expr
.X_op
= O_secrel
;
17552 expr
.X_add_symbol
= symbol
;
17553 expr
.X_add_number
= 0;
17554 emit_expr (&expr
, size
);
17558 /* MD interface: Symbol and relocation handling. */
17560 /* Return the address within the segment that a PC-relative fixup is
17561 relative to. For ARM, PC-relative fixups applied to instructions
17562 are generally relative to the location of the fixup plus 8 bytes.
17563 Thumb branches are offset by 4, and Thumb loads relative to PC
17564 require special handling. */
17567 md_pcrel_from_section (fixS
* fixP
, segT seg
)
17569 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
17571 /* If this is pc-relative and we are going to emit a relocation
17572 then we just want to put out any pipeline compensation that the linker
17573 will need. Otherwise we want to use the calculated base.
17574 For WinCE we skip the bias for externals as well, since this
17575 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17577 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
17578 || (arm_force_relocation (fixP
)
17580 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17585 switch (fixP
->fx_r_type
)
17587 /* PC relative addressing on the Thumb is slightly odd as the
17588 bottom two bits of the PC are forced to zero for the
17589 calculation. This happens *after* application of the
17590 pipeline offset. However, Thumb adrl already adjusts for
17591 this, so we need not do it again. */
17592 case BFD_RELOC_ARM_THUMB_ADD
:
17595 case BFD_RELOC_ARM_THUMB_OFFSET
:
17596 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17597 case BFD_RELOC_ARM_T32_ADD_PC12
:
17598 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17599 return (base
+ 4) & ~3;
17601 /* Thumb branches are simply offset by +4. */
17602 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17603 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17604 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17605 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17606 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17607 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17608 case BFD_RELOC_THUMB_PCREL_BLX
:
17611 /* ARM mode branches are offset by +8. However, the Windows CE
17612 loader expects the relocation not to take this into account. */
17613 case BFD_RELOC_ARM_PCREL_BRANCH
:
17614 case BFD_RELOC_ARM_PCREL_CALL
:
17615 case BFD_RELOC_ARM_PCREL_JUMP
:
17616 case BFD_RELOC_ARM_PCREL_BLX
:
17617 case BFD_RELOC_ARM_PLT32
:
17619 /* When handling fixups immediately, because we have already
17620 discovered the value of a symbol, or the address of the frag involved
17621 we must account for the offset by +8, as the OS loader will never see the reloc.
17622 see fixup_segment() in write.c
17623 The S_IS_EXTERNAL test handles the case of global symbols.
17624 Those need the calculated base, not just the pipe compensation the linker will need. */
17626 && fixP
->fx_addsy
!= NULL
17627 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17628 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17635 /* ARM mode loads relative to PC are also offset by +8. Unlike
17636 branches, the Windows CE loader *does* expect the relocation
17637 to take this into account. */
17638 case BFD_RELOC_ARM_OFFSET_IMM
:
17639 case BFD_RELOC_ARM_OFFSET_IMM8
:
17640 case BFD_RELOC_ARM_HWLITERAL
:
17641 case BFD_RELOC_ARM_LITERAL
:
17642 case BFD_RELOC_ARM_CP_OFF_IMM
:
17646 /* Other PC-relative relocations are un-offset. */
17652 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17653 Otherwise we have no need to default values of symbols. */
17656 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17659 if (name
[0] == '_' && name
[1] == 'G'
17660 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17664 if (symbol_find (name
))
17665 as_bad (_("GOT already in the symbol table"));
17667 GOT_symbol
= symbol_new (name
, undefined_section
,
17668 (valueT
) 0, & zero_address_frag
);
17678 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17679 computed as two separate immediate values, added together. We
17680 already know that this value cannot be computed by just one ARM
17683 static unsigned int
17684 validate_immediate_twopart (unsigned int val
,
17685 unsigned int * highpart
)
17690 for (i
= 0; i
< 32; i
+= 2)
17691 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17697 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17699 else if (a
& 0xff0000)
17701 if (a
& 0xff000000)
17703 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17707 assert (a
& 0xff000000);
17708 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17711 return (a
& 0xff) | (i
<< 7);
17718 validate_offset_imm (unsigned int val
, int hwse
)
17720 if ((hwse
&& val
> 255) || val
> 4095)
17725 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17726 negative immediate constant by altering the instruction. A bit of
17731 by inverting the second operand, and
17734 by negating the second operand. */
17737 negate_data_op (unsigned long * instruction
,
17738 unsigned long value
)
17741 unsigned long negated
, inverted
;
17743 negated
= encode_arm_immediate (-value
);
17744 inverted
= encode_arm_immediate (~value
);
17746 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17749 /* First negates. */
17750 case OPCODE_SUB
: /* ADD <-> SUB */
17751 new_inst
= OPCODE_ADD
;
17756 new_inst
= OPCODE_SUB
;
17760 case OPCODE_CMP
: /* CMP <-> CMN */
17761 new_inst
= OPCODE_CMN
;
17766 new_inst
= OPCODE_CMP
;
17770 /* Now Inverted ops. */
17771 case OPCODE_MOV
: /* MOV <-> MVN */
17772 new_inst
= OPCODE_MVN
;
17777 new_inst
= OPCODE_MOV
;
17781 case OPCODE_AND
: /* AND <-> BIC */
17782 new_inst
= OPCODE_BIC
;
17787 new_inst
= OPCODE_AND
;
17791 case OPCODE_ADC
: /* ADC <-> SBC */
17792 new_inst
= OPCODE_SBC
;
17797 new_inst
= OPCODE_ADC
;
17801 /* We cannot do anything. */
17806 if (value
== (unsigned) FAIL
)
17809 *instruction
&= OPCODE_MASK
;
17810 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17814 /* Like negate_data_op, but for Thumb-2. */
17816 static unsigned int
17817 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
17821 unsigned int negated
, inverted
;
17823 negated
= encode_thumb32_immediate (-value
);
17824 inverted
= encode_thumb32_immediate (~value
);
17826 rd
= (*instruction
>> 8) & 0xf;
17827 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17830 /* ADD <-> SUB. Includes CMP <-> CMN. */
17831 case T2_OPCODE_SUB
:
17832 new_inst
= T2_OPCODE_ADD
;
17836 case T2_OPCODE_ADD
:
17837 new_inst
= T2_OPCODE_SUB
;
17841 /* ORR <-> ORN. Includes MOV <-> MVN. */
17842 case T2_OPCODE_ORR
:
17843 new_inst
= T2_OPCODE_ORN
;
17847 case T2_OPCODE_ORN
:
17848 new_inst
= T2_OPCODE_ORR
;
17852 /* AND <-> BIC. TST has no inverted equivalent. */
17853 case T2_OPCODE_AND
:
17854 new_inst
= T2_OPCODE_BIC
;
17861 case T2_OPCODE_BIC
:
17862 new_inst
= T2_OPCODE_AND
;
17867 case T2_OPCODE_ADC
:
17868 new_inst
= T2_OPCODE_SBC
;
17872 case T2_OPCODE_SBC
:
17873 new_inst
= T2_OPCODE_ADC
;
17877 /* We cannot do anything. */
17882 if (value
== (unsigned int)FAIL
)
17885 *instruction
&= T2_OPCODE_MASK
;
17886 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17890 /* Read a 32-bit thumb instruction from buf. */
17891 static unsigned long
17892 get_thumb32_insn (char * buf
)
17894 unsigned long insn
;
17895 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17896 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17902 /* We usually want to set the low bit on the address of thumb function
17903 symbols. In particular .word foo - . should have the low bit set.
17904 Generic code tries to fold the difference of two symbols to
17905 a constant. Prevent this and force a relocation when the first symbols
17906 is a thumb function. */
17908 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17910 if (op
== O_subtract
17911 && l
->X_op
== O_symbol
17912 && r
->X_op
== O_symbol
17913 && THUMB_IS_FUNC (l
->X_add_symbol
))
17915 l
->X_op
= O_subtract
;
17916 l
->X_op_symbol
= r
->X_add_symbol
;
17917 l
->X_add_number
-= r
->X_add_number
;
17920 /* Process as normal. */
17925 md_apply_fix (fixS
* fixP
,
17929 offsetT value
= * valP
;
17931 unsigned int newimm
;
17932 unsigned long temp
;
17934 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17936 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17938 /* Note whether this will delete the relocation. */
17940 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17943 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17944 consistency with the behaviour on 32-bit hosts. Remember value
17946 value
&= 0xffffffff;
17947 value
^= 0x80000000;
17948 value
-= 0x80000000;
17951 fixP
->fx_addnumber
= value
;
17953 /* Same treatment for fixP->fx_offset. */
17954 fixP
->fx_offset
&= 0xffffffff;
17955 fixP
->fx_offset
^= 0x80000000;
17956 fixP
->fx_offset
-= 0x80000000;
17958 switch (fixP
->fx_r_type
)
17960 case BFD_RELOC_NONE
:
17961 /* This will need to go in the object file. */
17965 case BFD_RELOC_ARM_IMMEDIATE
:
17966 /* We claim that this fixup has been processed here,
17967 even if in fact we generate an error because we do
17968 not have a reloc for it, so tc_gen_reloc will reject it. */
17972 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17975 _("undefined symbol %s used as an immediate value"),
17976 S_GET_NAME (fixP
->fx_addsy
));
17980 newimm
= encode_arm_immediate (value
);
17981 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17983 /* If the instruction will fail, see if we can fix things up by
17984 changing the opcode. */
17985 if (newimm
== (unsigned int) FAIL
17986 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17988 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17989 _("invalid constant (%lx) after fixup"),
17990 (unsigned long) value
);
17994 newimm
|= (temp
& 0xfffff000);
17995 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17998 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18000 unsigned int highpart
= 0;
18001 unsigned int newinsn
= 0xe1a00000; /* nop. */
18003 newimm
= encode_arm_immediate (value
);
18004 temp
= md_chars_to_number (buf
, INSN_SIZE
);
18006 /* If the instruction will fail, see if we can fix things up by
18007 changing the opcode. */
18008 if (newimm
== (unsigned int) FAIL
18009 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
18011 /* No ? OK - try using two ADD instructions to generate
18013 newimm
= validate_immediate_twopart (value
, & highpart
);
18015 /* Yes - then make sure that the second instruction is
18017 if (newimm
!= (unsigned int) FAIL
)
18019 /* Still No ? Try using a negated value. */
18020 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
18021 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
18022 /* Otherwise - give up. */
18025 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18026 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18031 /* Replace the first operand in the 2nd instruction (which
18032 is the PC) with the destination register. We have
18033 already added in the PC in the first instruction and we
18034 do not want to do it again. */
18035 newinsn
&= ~ 0xf0000;
18036 newinsn
|= ((newinsn
& 0x0f000) << 4);
18039 newimm
|= (temp
& 0xfffff000);
18040 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18042 highpart
|= (newinsn
& 0xfffff000);
18043 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
18047 case BFD_RELOC_ARM_OFFSET_IMM
:
18048 if (!fixP
->fx_done
&& seg
->use_rela_p
)
18051 case BFD_RELOC_ARM_LITERAL
:
18057 if (validate_offset_imm (value
, 0) == FAIL
)
18059 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
18060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18061 _("invalid literal constant: pool needs to be closer"));
18063 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18064 _("bad immediate value for offset (%ld)"),
18069 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18070 newval
&= 0xff7ff000;
18071 newval
|= value
| (sign
? INDEX_UP
: 0);
18072 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18075 case BFD_RELOC_ARM_OFFSET_IMM8
:
18076 case BFD_RELOC_ARM_HWLITERAL
:
18082 if (validate_offset_imm (value
, 1) == FAIL
)
18084 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
18085 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18086 _("invalid literal constant: pool needs to be closer"));
18088 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18093 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18094 newval
&= 0xff7ff0f0;
18095 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
18096 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18099 case BFD_RELOC_ARM_T32_OFFSET_U8
:
18100 if (value
< 0 || value
> 1020 || value
% 4 != 0)
18101 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18102 _("bad immediate value for offset (%ld)"), (long) value
);
18105 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
18107 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
18110 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18111 /* This is a complicated relocation used for all varieties of Thumb32
18112 load/store instruction with immediate offset:
18114 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18115 *4, optional writeback(W)
18116 (doubleword load/store)
18118 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18119 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18120 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18121 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18122 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18124 Uppercase letters indicate bits that are already encoded at
18125 this point. Lowercase letters are our problem. For the
18126 second block of instructions, the secondary opcode nybble
18127 (bits 8..11) is present, and bit 23 is zero, even if this is
18128 a PC-relative operation. */
18129 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18131 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
18133 if ((newval
& 0xf0000000) == 0xe0000000)
18135 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18137 newval
|= (1 << 23);
18140 if (value
% 4 != 0)
18142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18143 _("offset not a multiple of 4"));
18149 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18150 _("offset out of range"));
18155 else if ((newval
& 0x000f0000) == 0x000f0000)
18157 /* PC-relative, 12-bit offset. */
18159 newval
|= (1 << 23);
18164 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18165 _("offset out of range"));
18170 else if ((newval
& 0x00000100) == 0x00000100)
18172 /* Writeback: 8-bit, +/- offset. */
18174 newval
|= (1 << 9);
18179 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18180 _("offset out of range"));
18185 else if ((newval
& 0x00000f00) == 0x00000e00)
18187 /* T-instruction: positive 8-bit offset. */
18188 if (value
< 0 || value
> 0xff)
18190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18191 _("offset out of range"));
18199 /* Positive 12-bit or negative 8-bit offset. */
18203 newval
|= (1 << 23);
18213 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18214 _("offset out of range"));
18221 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
18222 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
18225 case BFD_RELOC_ARM_SHIFT_IMM
:
18226 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18227 if (((unsigned long) value
) > 32
18229 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
18231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18232 _("shift expression is too large"));
18237 /* Shifts of zero must be done as lsl. */
18239 else if (value
== 32)
18241 newval
&= 0xfffff07f;
18242 newval
|= (value
& 0x1f) << 7;
18243 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18246 case BFD_RELOC_ARM_T32_IMMEDIATE
:
18247 case BFD_RELOC_ARM_T32_ADD_IMM
:
18248 case BFD_RELOC_ARM_T32_IMM12
:
18249 case BFD_RELOC_ARM_T32_ADD_PC12
:
18250 /* We claim that this fixup has been processed here,
18251 even if in fact we generate an error because we do
18252 not have a reloc for it, so tc_gen_reloc will reject it. */
18256 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18258 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18259 _("undefined symbol %s used as an immediate value"),
18260 S_GET_NAME (fixP
->fx_addsy
));
18264 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18266 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
18269 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18270 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18272 newimm
= encode_thumb32_immediate (value
);
18273 if (newimm
== (unsigned int) FAIL
)
18274 newimm
= thumb32_negate_data_op (&newval
, value
);
18276 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
18277 && newimm
== (unsigned int) FAIL
)
18279 /* Turn add/sum into addw/subw. */
18280 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18281 newval
= (newval
& 0xfeffffff) | 0x02000000;
18283 /* 12 bit immediate for addw/subw. */
18287 newval
^= 0x00a00000;
18290 newimm
= (unsigned int) FAIL
;
18295 if (newimm
== (unsigned int)FAIL
)
18297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18298 _("invalid constant (%lx) after fixup"),
18299 (unsigned long) value
);
18303 newval
|= (newimm
& 0x800) << 15;
18304 newval
|= (newimm
& 0x700) << 4;
18305 newval
|= (newimm
& 0x0ff);
18307 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18308 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18311 case BFD_RELOC_ARM_SMC
:
18312 if (((unsigned long) value
) > 0xffff)
18313 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18314 _("invalid smc expression"));
18315 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18316 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18317 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18320 case BFD_RELOC_ARM_SWI
:
18321 if (fixP
->tc_fix_data
!= 0)
18323 if (((unsigned long) value
) > 0xff)
18324 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18325 _("invalid swi expression"));
18326 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18328 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18332 if (((unsigned long) value
) > 0x00ffffff)
18333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18334 _("invalid swi expression"));
18335 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18337 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18341 case BFD_RELOC_ARM_MULTI
:
18342 if (((unsigned long) value
) > 0xffff)
18343 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18344 _("invalid expression in load/store multiple"));
18345 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
18346 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18350 case BFD_RELOC_ARM_PCREL_CALL
:
18351 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18352 if ((newval
& 0xf0000000) == 0xf0000000)
18356 goto arm_branch_common
;
18358 case BFD_RELOC_ARM_PCREL_JUMP
:
18359 case BFD_RELOC_ARM_PLT32
:
18361 case BFD_RELOC_ARM_PCREL_BRANCH
:
18363 goto arm_branch_common
;
18365 case BFD_RELOC_ARM_PCREL_BLX
:
18368 /* We are going to store value (shifted right by two) in the
18369 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18370 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18371 also be be clear. */
18373 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18374 _("misaligned branch destination"));
18375 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
18376 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
18377 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18378 _("branch out of range"));
18380 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18382 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18383 newval
|= (value
>> 2) & 0x00ffffff;
18384 /* Set the H bit on BLX instructions. */
18388 newval
|= 0x01000000;
18390 newval
&= ~0x01000000;
18392 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18396 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
18397 /* CBZ can only branch forward. */
18399 /* Attempts to use CBZ to branch to the next instruction
18400 (which, strictly speaking, are prohibited) will be turned into
18403 FIXME: It may be better to remove the instruction completely and
18404 perform relaxation. */
18407 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18408 newval
= 0xbf00; /* NOP encoding T1 */
18409 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18414 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18415 _("branch out of range"));
18417 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18419 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18420 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
18421 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18426 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
18427 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
18428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18429 _("branch out of range"));
18431 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18433 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18434 newval
|= (value
& 0x1ff) >> 1;
18435 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18439 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
18440 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
18441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18442 _("branch out of range"));
18444 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18446 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18447 newval
|= (value
& 0xfff) >> 1;
18448 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18452 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18453 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
18454 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18455 _("conditional branch out of range"));
18457 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18460 addressT S
, J1
, J2
, lo
, hi
;
18462 S
= (value
& 0x00100000) >> 20;
18463 J2
= (value
& 0x00080000) >> 19;
18464 J1
= (value
& 0x00040000) >> 18;
18465 hi
= (value
& 0x0003f000) >> 12;
18466 lo
= (value
& 0x00000ffe) >> 1;
18468 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18469 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18470 newval
|= (S
<< 10) | hi
;
18471 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
18472 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18473 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18477 case BFD_RELOC_THUMB_PCREL_BLX
:
18478 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18479 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
18480 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18481 _("branch out of range"));
18483 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
18484 /* For a BLX instruction, make sure that the relocation is rounded up
18485 to a word boundary. This follows the semantics of the instruction
18486 which specifies that bit 1 of the target address will come from bit
18487 1 of the base address. */
18488 value
= (value
+ 1) & ~ 1;
18490 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18494 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18495 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18496 newval
|= (value
& 0x7fffff) >> 12;
18497 newval2
|= (value
& 0xfff) >> 1;
18498 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18499 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18503 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18504 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
18505 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18506 _("branch out of range"));
18508 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18511 addressT S
, I1
, I2
, lo
, hi
;
18513 S
= (value
& 0x01000000) >> 24;
18514 I1
= (value
& 0x00800000) >> 23;
18515 I2
= (value
& 0x00400000) >> 22;
18516 hi
= (value
& 0x003ff000) >> 12;
18517 lo
= (value
& 0x00000ffe) >> 1;
18522 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18523 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18524 newval
|= (S
<< 10) | hi
;
18525 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
18526 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18527 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18532 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18533 md_number_to_chars (buf
, value
, 1);
18537 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18538 md_number_to_chars (buf
, value
, 2);
18542 case BFD_RELOC_ARM_TLS_GD32
:
18543 case BFD_RELOC_ARM_TLS_LE32
:
18544 case BFD_RELOC_ARM_TLS_IE32
:
18545 case BFD_RELOC_ARM_TLS_LDM32
:
18546 case BFD_RELOC_ARM_TLS_LDO32
:
18547 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
18550 case BFD_RELOC_ARM_GOT32
:
18551 case BFD_RELOC_ARM_GOTOFF
:
18552 case BFD_RELOC_ARM_TARGET2
:
18553 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18554 md_number_to_chars (buf
, 0, 4);
18558 case BFD_RELOC_RVA
:
18560 case BFD_RELOC_ARM_TARGET1
:
18561 case BFD_RELOC_ARM_ROSEGREL32
:
18562 case BFD_RELOC_ARM_SBREL32
:
18563 case BFD_RELOC_32_PCREL
:
18565 case BFD_RELOC_32_SECREL
:
18567 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18569 /* For WinCE we only do this for pcrel fixups. */
18570 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
18572 md_number_to_chars (buf
, value
, 4);
18576 case BFD_RELOC_ARM_PREL31
:
18577 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18579 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
18580 if ((value
^ (value
>> 1)) & 0x40000000)
18582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18583 _("rel31 relocation overflow"));
18585 newval
|= value
& 0x7fffffff;
18586 md_number_to_chars (buf
, newval
, 4);
18591 case BFD_RELOC_ARM_CP_OFF_IMM
:
18592 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18593 if (value
< -1023 || value
> 1023 || (value
& 3))
18594 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18595 _("co-processor offset out of range"));
18600 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18601 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18602 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18604 newval
= get_thumb32_insn (buf
);
18605 newval
&= 0xff7fff00;
18606 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18607 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18608 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18609 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18611 put_thumb32_insn (buf
, newval
);
18614 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18615 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18616 if (value
< -255 || value
> 255)
18617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18618 _("co-processor offset out of range"));
18620 goto cp_off_common
;
18622 case BFD_RELOC_ARM_THUMB_OFFSET
:
18623 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18624 /* Exactly what ranges, and where the offset is inserted depends
18625 on the type of instruction, we can establish this from the
18627 switch (newval
>> 12)
18629 case 4: /* PC load. */
18630 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18631 forced to zero for these loads; md_pcrel_from has already
18632 compensated for this. */
18634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18635 _("invalid offset, target not word aligned (0x%08lX)"),
18636 (((unsigned long) fixP
->fx_frag
->fr_address
18637 + (unsigned long) fixP
->fx_where
) & ~3)
18638 + (unsigned long) value
);
18640 if (value
& ~0x3fc)
18641 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18642 _("invalid offset, value too big (0x%08lX)"),
18645 newval
|= value
>> 2;
18648 case 9: /* SP load/store. */
18649 if (value
& ~0x3fc)
18650 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18651 _("invalid offset, value too big (0x%08lX)"),
18653 newval
|= value
>> 2;
18656 case 6: /* Word load/store. */
18658 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18659 _("invalid offset, value too big (0x%08lX)"),
18661 newval
|= value
<< 4; /* 6 - 2. */
18664 case 7: /* Byte load/store. */
18666 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18667 _("invalid offset, value too big (0x%08lX)"),
18669 newval
|= value
<< 6;
18672 case 8: /* Halfword load/store. */
18674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18675 _("invalid offset, value too big (0x%08lX)"),
18677 newval
|= value
<< 5; /* 6 - 1. */
18681 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18682 "Unable to process relocation for thumb opcode: %lx",
18683 (unsigned long) newval
);
18686 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18689 case BFD_RELOC_ARM_THUMB_ADD
:
18690 /* This is a complicated relocation, since we use it for all of
18691 the following immediate relocations:
18695 9bit ADD/SUB SP word-aligned
18696 10bit ADD PC/SP word-aligned
18698 The type of instruction being processed is encoded in the
18705 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18707 int rd
= (newval
>> 4) & 0xf;
18708 int rs
= newval
& 0xf;
18709 int subtract
= !!(newval
& 0x8000);
18711 /* Check for HI regs, only very restricted cases allowed:
18712 Adjusting SP, and using PC or SP to get an address. */
18713 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18714 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18716 _("invalid Hi register with immediate"));
18718 /* If value is negative, choose the opposite instruction. */
18722 subtract
= !subtract
;
18724 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18725 _("immediate value out of range"));
18730 if (value
& ~0x1fc)
18731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18732 _("invalid immediate for stack address calculation"));
18733 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18734 newval
|= value
>> 2;
18736 else if (rs
== REG_PC
|| rs
== REG_SP
)
18738 if (subtract
|| value
& ~0x3fc)
18739 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18740 _("invalid immediate for address calculation (value = 0x%08lX)"),
18741 (unsigned long) value
);
18742 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18744 newval
|= value
>> 2;
18749 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18750 _("immediate value out of range"));
18751 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18752 newval
|= (rd
<< 8) | value
;
18757 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18758 _("immediate value out of range"));
18759 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18760 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18763 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18766 case BFD_RELOC_ARM_THUMB_IMM
:
18767 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18768 if (value
< 0 || value
> 255)
18769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18770 _("invalid immediate: %ld is out of range"),
18773 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18776 case BFD_RELOC_ARM_THUMB_SHIFT
:
18777 /* 5bit shift value (0..32). LSL cannot take 32. */
18778 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18779 temp
= newval
& 0xf800;
18780 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18781 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18782 _("invalid shift value: %ld"), (long) value
);
18783 /* Shifts of zero must be encoded as LSL. */
18785 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18786 /* Shifts of 32 are encoded as zero. */
18787 else if (value
== 32)
18789 newval
|= value
<< 6;
18790 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18793 case BFD_RELOC_VTABLE_INHERIT
:
18794 case BFD_RELOC_VTABLE_ENTRY
:
18798 case BFD_RELOC_ARM_MOVW
:
18799 case BFD_RELOC_ARM_MOVT
:
18800 case BFD_RELOC_ARM_THUMB_MOVW
:
18801 case BFD_RELOC_ARM_THUMB_MOVT
:
18802 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18804 /* REL format relocations are limited to a 16-bit addend. */
18805 if (!fixP
->fx_done
)
18807 if (value
< -0x1000 || value
> 0xffff)
18808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18809 _("offset out of range"));
18811 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18812 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18817 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18818 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18820 newval
= get_thumb32_insn (buf
);
18821 newval
&= 0xfbf08f00;
18822 newval
|= (value
& 0xf000) << 4;
18823 newval
|= (value
& 0x0800) << 15;
18824 newval
|= (value
& 0x0700) << 4;
18825 newval
|= (value
& 0x00ff);
18826 put_thumb32_insn (buf
, newval
);
18830 newval
= md_chars_to_number (buf
, 4);
18831 newval
&= 0xfff0f000;
18832 newval
|= value
& 0x0fff;
18833 newval
|= (value
& 0xf000) << 4;
18834 md_number_to_chars (buf
, newval
, 4);
18839 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18840 case BFD_RELOC_ARM_ALU_PC_G0
:
18841 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18842 case BFD_RELOC_ARM_ALU_PC_G1
:
18843 case BFD_RELOC_ARM_ALU_PC_G2
:
18844 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18845 case BFD_RELOC_ARM_ALU_SB_G0
:
18846 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18847 case BFD_RELOC_ARM_ALU_SB_G1
:
18848 case BFD_RELOC_ARM_ALU_SB_G2
:
18849 assert (!fixP
->fx_done
);
18850 if (!seg
->use_rela_p
)
18853 bfd_vma encoded_addend
;
18854 bfd_vma addend_abs
= abs (value
);
18856 /* Check that the absolute value of the addend can be
18857 expressed as an 8-bit constant plus a rotation. */
18858 encoded_addend
= encode_arm_immediate (addend_abs
);
18859 if (encoded_addend
== (unsigned int) FAIL
)
18860 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18861 _("the offset 0x%08lX is not representable"),
18862 (unsigned long) addend_abs
);
18864 /* Extract the instruction. */
18865 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18867 /* If the addend is positive, use an ADD instruction.
18868 Otherwise use a SUB. Take care not to destroy the S bit. */
18869 insn
&= 0xff1fffff;
18875 /* Place the encoded addend into the first 12 bits of the
18877 insn
&= 0xfffff000;
18878 insn
|= encoded_addend
;
18880 /* Update the instruction. */
18881 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18885 case BFD_RELOC_ARM_LDR_PC_G0
:
18886 case BFD_RELOC_ARM_LDR_PC_G1
:
18887 case BFD_RELOC_ARM_LDR_PC_G2
:
18888 case BFD_RELOC_ARM_LDR_SB_G0
:
18889 case BFD_RELOC_ARM_LDR_SB_G1
:
18890 case BFD_RELOC_ARM_LDR_SB_G2
:
18891 assert (!fixP
->fx_done
);
18892 if (!seg
->use_rela_p
)
18895 bfd_vma addend_abs
= abs (value
);
18897 /* Check that the absolute value of the addend can be
18898 encoded in 12 bits. */
18899 if (addend_abs
>= 0x1000)
18900 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18901 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18902 (unsigned long) addend_abs
);
18904 /* Extract the instruction. */
18905 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18907 /* If the addend is negative, clear bit 23 of the instruction.
18908 Otherwise set it. */
18910 insn
&= ~(1 << 23);
18914 /* Place the absolute value of the addend into the first 12 bits
18915 of the instruction. */
18916 insn
&= 0xfffff000;
18917 insn
|= addend_abs
;
18919 /* Update the instruction. */
18920 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18924 case BFD_RELOC_ARM_LDRS_PC_G0
:
18925 case BFD_RELOC_ARM_LDRS_PC_G1
:
18926 case BFD_RELOC_ARM_LDRS_PC_G2
:
18927 case BFD_RELOC_ARM_LDRS_SB_G0
:
18928 case BFD_RELOC_ARM_LDRS_SB_G1
:
18929 case BFD_RELOC_ARM_LDRS_SB_G2
:
18930 assert (!fixP
->fx_done
);
18931 if (!seg
->use_rela_p
)
18934 bfd_vma addend_abs
= abs (value
);
18936 /* Check that the absolute value of the addend can be
18937 encoded in 8 bits. */
18938 if (addend_abs
>= 0x100)
18939 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18940 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18941 (unsigned long) addend_abs
);
18943 /* Extract the instruction. */
18944 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18946 /* If the addend is negative, clear bit 23 of the instruction.
18947 Otherwise set it. */
18949 insn
&= ~(1 << 23);
18953 /* Place the first four bits of the absolute value of the addend
18954 into the first 4 bits of the instruction, and the remaining
18955 four into bits 8 .. 11. */
18956 insn
&= 0xfffff0f0;
18957 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18959 /* Update the instruction. */
18960 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18964 case BFD_RELOC_ARM_LDC_PC_G0
:
18965 case BFD_RELOC_ARM_LDC_PC_G1
:
18966 case BFD_RELOC_ARM_LDC_PC_G2
:
18967 case BFD_RELOC_ARM_LDC_SB_G0
:
18968 case BFD_RELOC_ARM_LDC_SB_G1
:
18969 case BFD_RELOC_ARM_LDC_SB_G2
:
18970 assert (!fixP
->fx_done
);
18971 if (!seg
->use_rela_p
)
18974 bfd_vma addend_abs
= abs (value
);
18976 /* Check that the absolute value of the addend is a multiple of
18977 four and, when divided by four, fits in 8 bits. */
18978 if (addend_abs
& 0x3)
18979 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18980 _("bad offset 0x%08lX (must be word-aligned)"),
18981 (unsigned long) addend_abs
);
18983 if ((addend_abs
>> 2) > 0xff)
18984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18985 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18986 (unsigned long) addend_abs
);
18988 /* Extract the instruction. */
18989 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18991 /* If the addend is negative, clear bit 23 of the instruction.
18992 Otherwise set it. */
18994 insn
&= ~(1 << 23);
18998 /* Place the addend (divided by four) into the first eight
18999 bits of the instruction. */
19000 insn
&= 0xfffffff0;
19001 insn
|= addend_abs
>> 2;
19003 /* Update the instruction. */
19004 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19008 case BFD_RELOC_ARM_V4BX
:
19009 /* This will need to go in the object file. */
19013 case BFD_RELOC_UNUSED
:
19015 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19016 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
19020 /* Translate internal representation of relocation info to BFD target
19024 tc_gen_reloc (asection
*section
, fixS
*fixp
)
19027 bfd_reloc_code_real_type code
;
19029 reloc
= xmalloc (sizeof (arelent
));
19031 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
19032 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
19033 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
19035 if (fixp
->fx_pcrel
)
19037 if (section
->use_rela_p
)
19038 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
19040 fixp
->fx_offset
= reloc
->address
;
19042 reloc
->addend
= fixp
->fx_offset
;
19044 switch (fixp
->fx_r_type
)
19047 if (fixp
->fx_pcrel
)
19049 code
= BFD_RELOC_8_PCREL
;
19054 if (fixp
->fx_pcrel
)
19056 code
= BFD_RELOC_16_PCREL
;
19061 if (fixp
->fx_pcrel
)
19063 code
= BFD_RELOC_32_PCREL
;
19067 case BFD_RELOC_ARM_MOVW
:
19068 if (fixp
->fx_pcrel
)
19070 code
= BFD_RELOC_ARM_MOVW_PCREL
;
19074 case BFD_RELOC_ARM_MOVT
:
19075 if (fixp
->fx_pcrel
)
19077 code
= BFD_RELOC_ARM_MOVT_PCREL
;
19081 case BFD_RELOC_ARM_THUMB_MOVW
:
19082 if (fixp
->fx_pcrel
)
19084 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
19088 case BFD_RELOC_ARM_THUMB_MOVT
:
19089 if (fixp
->fx_pcrel
)
19091 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
19095 case BFD_RELOC_NONE
:
19096 case BFD_RELOC_ARM_PCREL_BRANCH
:
19097 case BFD_RELOC_ARM_PCREL_BLX
:
19098 case BFD_RELOC_RVA
:
19099 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19100 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19101 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19102 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19103 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19104 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19105 case BFD_RELOC_THUMB_PCREL_BLX
:
19106 case BFD_RELOC_VTABLE_ENTRY
:
19107 case BFD_RELOC_VTABLE_INHERIT
:
19109 case BFD_RELOC_32_SECREL
:
19111 code
= fixp
->fx_r_type
;
19114 case BFD_RELOC_ARM_LITERAL
:
19115 case BFD_RELOC_ARM_HWLITERAL
:
19116 /* If this is called then the a literal has
19117 been referenced across a section boundary. */
19118 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19119 _("literal referenced across section boundary"));
19123 case BFD_RELOC_ARM_GOT32
:
19124 case BFD_RELOC_ARM_GOTOFF
:
19125 case BFD_RELOC_ARM_PLT32
:
19126 case BFD_RELOC_ARM_TARGET1
:
19127 case BFD_RELOC_ARM_ROSEGREL32
:
19128 case BFD_RELOC_ARM_SBREL32
:
19129 case BFD_RELOC_ARM_PREL31
:
19130 case BFD_RELOC_ARM_TARGET2
:
19131 case BFD_RELOC_ARM_TLS_LE32
:
19132 case BFD_RELOC_ARM_TLS_LDO32
:
19133 case BFD_RELOC_ARM_PCREL_CALL
:
19134 case BFD_RELOC_ARM_PCREL_JUMP
:
19135 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19136 case BFD_RELOC_ARM_ALU_PC_G0
:
19137 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19138 case BFD_RELOC_ARM_ALU_PC_G1
:
19139 case BFD_RELOC_ARM_ALU_PC_G2
:
19140 case BFD_RELOC_ARM_LDR_PC_G0
:
19141 case BFD_RELOC_ARM_LDR_PC_G1
:
19142 case BFD_RELOC_ARM_LDR_PC_G2
:
19143 case BFD_RELOC_ARM_LDRS_PC_G0
:
19144 case BFD_RELOC_ARM_LDRS_PC_G1
:
19145 case BFD_RELOC_ARM_LDRS_PC_G2
:
19146 case BFD_RELOC_ARM_LDC_PC_G0
:
19147 case BFD_RELOC_ARM_LDC_PC_G1
:
19148 case BFD_RELOC_ARM_LDC_PC_G2
:
19149 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19150 case BFD_RELOC_ARM_ALU_SB_G0
:
19151 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19152 case BFD_RELOC_ARM_ALU_SB_G1
:
19153 case BFD_RELOC_ARM_ALU_SB_G2
:
19154 case BFD_RELOC_ARM_LDR_SB_G0
:
19155 case BFD_RELOC_ARM_LDR_SB_G1
:
19156 case BFD_RELOC_ARM_LDR_SB_G2
:
19157 case BFD_RELOC_ARM_LDRS_SB_G0
:
19158 case BFD_RELOC_ARM_LDRS_SB_G1
:
19159 case BFD_RELOC_ARM_LDRS_SB_G2
:
19160 case BFD_RELOC_ARM_LDC_SB_G0
:
19161 case BFD_RELOC_ARM_LDC_SB_G1
:
19162 case BFD_RELOC_ARM_LDC_SB_G2
:
19163 case BFD_RELOC_ARM_V4BX
:
19164 code
= fixp
->fx_r_type
;
19167 case BFD_RELOC_ARM_TLS_GD32
:
19168 case BFD_RELOC_ARM_TLS_IE32
:
19169 case BFD_RELOC_ARM_TLS_LDM32
:
19170 /* BFD will include the symbol's address in the addend.
19171 But we don't want that, so subtract it out again here. */
19172 if (!S_IS_COMMON (fixp
->fx_addsy
))
19173 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
19174 code
= fixp
->fx_r_type
;
19178 case BFD_RELOC_ARM_IMMEDIATE
:
19179 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19180 _("internal relocation (type: IMMEDIATE) not fixed up"));
19183 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19184 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19185 _("ADRL used for a symbol not defined in the same file"));
19188 case BFD_RELOC_ARM_OFFSET_IMM
:
19189 if (section
->use_rela_p
)
19191 code
= fixp
->fx_r_type
;
19195 if (fixp
->fx_addsy
!= NULL
19196 && !S_IS_DEFINED (fixp
->fx_addsy
)
19197 && S_IS_LOCAL (fixp
->fx_addsy
))
19199 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19200 _("undefined local label `%s'"),
19201 S_GET_NAME (fixp
->fx_addsy
));
19205 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19206 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19213 switch (fixp
->fx_r_type
)
19215 case BFD_RELOC_NONE
: type
= "NONE"; break;
19216 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
19217 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
19218 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
19219 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
19220 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
19221 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
19222 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
19223 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
19224 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
19225 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
19226 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
19227 default: type
= _("<unknown>"); break;
19229 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19230 _("cannot represent %s relocation in this object file format"),
19237 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
19239 && fixp
->fx_addsy
== GOT_symbol
)
19241 code
= BFD_RELOC_ARM_GOTPC
;
19242 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
19246 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
19248 if (reloc
->howto
== NULL
)
19250 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19251 _("cannot represent %s relocation in this object file format"),
19252 bfd_get_reloc_code_name (code
));
19256 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19257 vtable entry to be used in the relocation's section offset. */
19258 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19259 reloc
->address
= fixp
->fx_offset
;
19264 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19267 cons_fix_new_arm (fragS
* frag
,
19272 bfd_reloc_code_real_type type
;
19276 FIXME: @@ Should look at CPU word size. */
19280 type
= BFD_RELOC_8
;
19283 type
= BFD_RELOC_16
;
19287 type
= BFD_RELOC_32
;
19290 type
= BFD_RELOC_64
;
19295 if (exp
->X_op
== O_secrel
)
19297 exp
->X_op
= O_symbol
;
19298 type
= BFD_RELOC_32_SECREL
;
19302 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
19305 #if defined OBJ_COFF || defined OBJ_ELF
19307 arm_validate_fix (fixS
* fixP
)
19309 /* If the destination of the branch is a defined symbol which does not have
19310 the THUMB_FUNC attribute, then we must be calling a function which has
19311 the (interfacearm) attribute. We look for the Thumb entry point to that
19312 function and change the branch to refer to that function instead. */
19313 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
19314 && fixP
->fx_addsy
!= NULL
19315 && S_IS_DEFINED (fixP
->fx_addsy
)
19316 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
19318 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
19324 arm_force_relocation (struct fix
* fixp
)
19326 #if defined (OBJ_COFF) && defined (TE_PE)
19327 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
19331 /* Resolve these relocations even if the symbol is extern or weak. */
19332 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
19333 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
19334 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
19335 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
19336 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19337 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
19338 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
19341 /* Always leave these relocations for the linker. */
19342 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19343 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19344 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19347 /* Always generate relocations against function symbols. */
19348 if (fixp
->fx_r_type
== BFD_RELOC_32
19350 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
19353 return generic_force_reloc (fixp
);
19356 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19357 /* Relocations against function names must be left unadjusted,
19358 so that the linker can use this information to generate interworking
19359 stubs. The MIPS version of this function
19360 also prevents relocations that are mips-16 specific, but I do not
19361 know why it does this.
19364 There is one other problem that ought to be addressed here, but
19365 which currently is not: Taking the address of a label (rather
19366 than a function) and then later jumping to that address. Such
19367 addresses also ought to have their bottom bit set (assuming that
19368 they reside in Thumb code), but at the moment they will not. */
19371 arm_fix_adjustable (fixS
* fixP
)
19373 if (fixP
->fx_addsy
== NULL
)
19376 /* Preserve relocations against symbols with function type. */
19377 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
19380 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
19381 && fixP
->fx_subsy
== NULL
)
19384 /* We need the symbol name for the VTABLE entries. */
19385 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
19386 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19389 /* Don't allow symbols to be discarded on GOT related relocs. */
19390 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
19391 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
19392 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
19393 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
19394 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
19395 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
19396 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
19397 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
19398 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
19401 /* Similarly for group relocations. */
19402 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19403 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19404 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19409 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19414 elf32_arm_target_format (void)
19417 return (target_big_endian
19418 ? "elf32-bigarm-symbian"
19419 : "elf32-littlearm-symbian");
19420 #elif defined (TE_VXWORKS)
19421 return (target_big_endian
19422 ? "elf32-bigarm-vxworks"
19423 : "elf32-littlearm-vxworks");
19425 if (target_big_endian
)
19426 return "elf32-bigarm";
19428 return "elf32-littlearm";
19433 armelf_frob_symbol (symbolS
* symp
,
19436 elf_frob_symbol (symp
, puntp
);
19440 /* MD interface: Finalization. */
19442 /* A good place to do this, although this was probably not intended
19443 for this kind of use. We need to dump the literal pool before
19444 references are made to a null symbol pointer. */
19449 literal_pool
* pool
;
19451 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
19453 /* Put it at the end of the relevant section. */
19454 subseg_set (pool
->section
, pool
->sub_section
);
19456 arm_elf_change_section ();
19462 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19466 arm_adjust_symtab (void)
19471 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19473 if (ARM_IS_THUMB (sym
))
19475 if (THUMB_IS_FUNC (sym
))
19477 /* Mark the symbol as a Thumb function. */
19478 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
19479 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
19480 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
19482 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
19483 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
19485 as_bad (_("%s: unexpected function type: %d"),
19486 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
19488 else switch (S_GET_STORAGE_CLASS (sym
))
19491 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
19494 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
19497 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
19505 if (ARM_IS_INTERWORK (sym
))
19506 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
19513 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19515 if (ARM_IS_THUMB (sym
))
19517 elf_symbol_type
* elf_sym
;
19519 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
19520 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
19522 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
19523 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
19525 /* If it's a .thumb_func, declare it as so,
19526 otherwise tag label as .code 16. */
19527 if (THUMB_IS_FUNC (sym
))
19528 elf_sym
->internal_elf_sym
.st_info
=
19529 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
19530 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
19531 elf_sym
->internal_elf_sym
.st_info
=
19532 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
19539 /* MD interface: Initialization. */
19542 set_constant_flonums (void)
19546 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
19547 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
19551 /* Auto-select Thumb mode if it's the only available instruction set for the
19552 given architecture. */
19555 autoselect_thumb_from_cpu_variant (void)
19557 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19558 opcode_select (16);
19567 if ( (arm_ops_hsh
= hash_new ()) == NULL
19568 || (arm_cond_hsh
= hash_new ()) == NULL
19569 || (arm_shift_hsh
= hash_new ()) == NULL
19570 || (arm_psr_hsh
= hash_new ()) == NULL
19571 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
19572 || (arm_reg_hsh
= hash_new ()) == NULL
19573 || (arm_reloc_hsh
= hash_new ()) == NULL
19574 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
19575 as_fatal (_("virtual memory exhausted"));
19577 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
19578 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
19579 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19580 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
19581 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19582 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
19583 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19584 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
19585 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19586 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
19587 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19588 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
19590 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19592 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19593 (PTR
) (barrier_opt_names
+ i
));
19595 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19596 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
19599 set_constant_flonums ();
19601 /* Set the cpu variant based on the command-line options. We prefer
19602 -mcpu= over -march= if both are set (as for GCC); and we prefer
19603 -mfpu= over any other way of setting the floating point unit.
19604 Use of legacy options with new options are faulted. */
19607 if (mcpu_cpu_opt
|| march_cpu_opt
)
19608 as_bad (_("use of old and new-style options to set CPU type"));
19610 mcpu_cpu_opt
= legacy_cpu
;
19612 else if (!mcpu_cpu_opt
)
19613 mcpu_cpu_opt
= march_cpu_opt
;
19618 as_bad (_("use of old and new-style options to set FPU type"));
19620 mfpu_opt
= legacy_fpu
;
19622 else if (!mfpu_opt
)
19624 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19625 /* Some environments specify a default FPU. If they don't, infer it
19626 from the processor. */
19628 mfpu_opt
= mcpu_fpu_opt
;
19630 mfpu_opt
= march_fpu_opt
;
19632 mfpu_opt
= &fpu_default
;
19638 if (mcpu_cpu_opt
!= NULL
)
19639 mfpu_opt
= &fpu_default
;
19640 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19641 mfpu_opt
= &fpu_arch_vfp_v2
;
19643 mfpu_opt
= &fpu_arch_fpa
;
19649 mcpu_cpu_opt
= &cpu_default
;
19650 selected_cpu
= cpu_default
;
19654 selected_cpu
= *mcpu_cpu_opt
;
19656 mcpu_cpu_opt
= &arm_arch_any
;
19659 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19661 autoselect_thumb_from_cpu_variant ();
19663 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19665 #if defined OBJ_COFF || defined OBJ_ELF
19667 unsigned int flags
= 0;
19669 #if defined OBJ_ELF
19670 flags
= meabi_flags
;
19672 switch (meabi_flags
)
19674 case EF_ARM_EABI_UNKNOWN
:
19676 /* Set the flags in the private structure. */
19677 if (uses_apcs_26
) flags
|= F_APCS26
;
19678 if (support_interwork
) flags
|= F_INTERWORK
;
19679 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19680 if (pic_code
) flags
|= F_PIC
;
19681 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19682 flags
|= F_SOFT_FLOAT
;
19684 switch (mfloat_abi_opt
)
19686 case ARM_FLOAT_ABI_SOFT
:
19687 case ARM_FLOAT_ABI_SOFTFP
:
19688 flags
|= F_SOFT_FLOAT
;
19691 case ARM_FLOAT_ABI_HARD
:
19692 if (flags
& F_SOFT_FLOAT
)
19693 as_bad (_("hard-float conflicts with specified fpu"));
19697 /* Using pure-endian doubles (even if soft-float). */
19698 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19699 flags
|= F_VFP_FLOAT
;
19701 #if defined OBJ_ELF
19702 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19703 flags
|= EF_ARM_MAVERICK_FLOAT
;
19706 case EF_ARM_EABI_VER4
:
19707 case EF_ARM_EABI_VER5
:
19708 /* No additional flags to set. */
19715 bfd_set_private_flags (stdoutput
, flags
);
19717 /* We have run out flags in the COFF header to encode the
19718 status of ATPCS support, so instead we create a dummy,
19719 empty, debug section called .arm.atpcs. */
19724 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19728 bfd_set_section_flags
19729 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19730 bfd_set_section_size (stdoutput
, sec
, 0);
19731 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19737 /* Record the CPU type as well. */
19738 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
19739 mach
= bfd_mach_arm_iWMMXt2
;
19740 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19741 mach
= bfd_mach_arm_iWMMXt
;
19742 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19743 mach
= bfd_mach_arm_XScale
;
19744 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19745 mach
= bfd_mach_arm_ep9312
;
19746 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19747 mach
= bfd_mach_arm_5TE
;
19748 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19750 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19751 mach
= bfd_mach_arm_5T
;
19753 mach
= bfd_mach_arm_5
;
19755 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19757 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19758 mach
= bfd_mach_arm_4T
;
19760 mach
= bfd_mach_arm_4
;
19762 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19763 mach
= bfd_mach_arm_3M
;
19764 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19765 mach
= bfd_mach_arm_3
;
19766 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19767 mach
= bfd_mach_arm_2a
;
19768 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19769 mach
= bfd_mach_arm_2
;
19771 mach
= bfd_mach_arm_unknown
;
19773 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19776 /* Command line processing. */
19779 Invocation line includes a switch not recognized by the base assembler.
19780 See if it's a processor-specific option.
19782 This routine is somewhat complicated by the need for backwards
19783 compatibility (since older releases of gcc can't be changed).
19784 The new options try to make the interface as compatible as
19787 New options (supported) are:
19789 -mcpu=<cpu name> Assemble for selected processor
19790 -march=<architecture name> Assemble for selected architecture
19791 -mfpu=<fpu architecture> Assemble for selected FPU.
19792 -EB/-mbig-endian Big-endian
19793 -EL/-mlittle-endian Little-endian
19794 -k Generate PIC code
19795 -mthumb Start in Thumb mode
19796 -mthumb-interwork Code supports ARM/Thumb interworking
19798 For now we will also provide support for:
19800 -mapcs-32 32-bit Program counter
19801 -mapcs-26 26-bit Program counter
19802 -macps-float Floats passed in FP registers
19803 -mapcs-reentrant Reentrant code
19805 (sometime these will probably be replaced with -mapcs=<list of options>
19806 and -matpcs=<list of options>)
19808 The remaining options are only supported for back-wards compatibility.
19809 Cpu variants, the arm part is optional:
19810 -m[arm]1 Currently not supported.
19811 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19812 -m[arm]3 Arm 3 processor
19813 -m[arm]6[xx], Arm 6 processors
19814 -m[arm]7[xx][t][[d]m] Arm 7 processors
19815 -m[arm]8[10] Arm 8 processors
19816 -m[arm]9[20][tdmi] Arm 9 processors
19817 -mstrongarm[110[0]] StrongARM processors
19818 -mxscale XScale processors
19819 -m[arm]v[2345[t[e]]] Arm architectures
19820 -mall All (except the ARM1)
19822 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19823 -mfpe-old (No float load/store multiples)
19824 -mvfpxd VFP Single precision
19826 -mno-fpu Disable all floating point instructions
19828 The following CPU names are recognized:
19829 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19830 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19831 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19832 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19833 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19834 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19835 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19839 const char * md_shortopts
= "m:k";
19841 #ifdef ARM_BI_ENDIAN
19842 #define OPTION_EB (OPTION_MD_BASE + 0)
19843 #define OPTION_EL (OPTION_MD_BASE + 1)
19845 #if TARGET_BYTES_BIG_ENDIAN
19846 #define OPTION_EB (OPTION_MD_BASE + 0)
19848 #define OPTION_EL (OPTION_MD_BASE + 1)
19851 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
19853 struct option md_longopts
[] =
19856 {"EB", no_argument
, NULL
, OPTION_EB
},
19859 {"EL", no_argument
, NULL
, OPTION_EL
},
19861 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
19862 {NULL
, no_argument
, NULL
, 0}
19865 size_t md_longopts_size
= sizeof (md_longopts
);
19867 struct arm_option_table
19869 char *option
; /* Option name to match. */
19870 char *help
; /* Help information. */
19871 int *var
; /* Variable to change. */
19872 int value
; /* What to change it to. */
19873 char *deprecated
; /* If non-null, print this message. */
19876 struct arm_option_table arm_opts
[] =
19878 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19879 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19880 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19881 &support_interwork
, 1, NULL
},
19882 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19883 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19884 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19886 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19887 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19888 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19889 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19892 /* These are recognized by the assembler, but have no affect on code. */
19893 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19894 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19895 {NULL
, NULL
, NULL
, 0, NULL
}
19898 struct arm_legacy_option_table
19900 char *option
; /* Option name to match. */
19901 const arm_feature_set
**var
; /* Variable to change. */
19902 const arm_feature_set value
; /* What to change it to. */
19903 char *deprecated
; /* If non-null, print this message. */
19906 const struct arm_legacy_option_table arm_legacy_opts
[] =
19908 /* DON'T add any new processors to this list -- we want the whole list
19909 to go away... Add them to the processors table instead. */
19910 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19911 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19912 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19913 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19914 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19915 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19916 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19917 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19918 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19919 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19920 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19921 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19922 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19923 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19924 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19925 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19926 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19927 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19928 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19929 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19930 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19931 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19932 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19933 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19934 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19935 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19936 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19937 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19938 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19939 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19940 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19941 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19942 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19943 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19944 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19945 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19946 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19947 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19948 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19949 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19950 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19951 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19952 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19953 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19954 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19955 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19956 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19957 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19958 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19959 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19960 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19961 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19962 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19963 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19964 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19965 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19966 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19967 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19968 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19969 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19970 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19971 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19972 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19973 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19974 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19975 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19976 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19977 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19978 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19979 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19980 N_("use -mcpu=strongarm110")},
19981 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19982 N_("use -mcpu=strongarm1100")},
19983 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19984 N_("use -mcpu=strongarm1110")},
19985 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19986 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19987 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19989 /* Architecture variants -- don't add any more to this list either. */
19990 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19991 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19992 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19993 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19994 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19995 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19996 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19997 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19998 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19999 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
20000 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20001 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20002 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20003 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20004 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20005 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20006 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20007 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20009 /* Floating point variants -- don't add any more to this list either. */
20010 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
20011 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
20012 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
20013 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
20014 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
20016 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
20019 struct arm_cpu_option_table
20022 const arm_feature_set value
;
20023 /* For some CPUs we assume an FPU unless the user explicitly sets
20025 const arm_feature_set default_fpu
;
20026 /* The canonical name of the CPU, or NULL to use NAME converted to upper
20028 const char *canonical_name
;
20031 /* This list should, at a minimum, contain all the cpu names
20032 recognized by GCC. */
20033 static const struct arm_cpu_option_table arm_cpus
[] =
20035 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
20036 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
20037 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
20038 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20039 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20040 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20041 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20042 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20043 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20044 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20045 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20046 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20047 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20048 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20049 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20050 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20051 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20052 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20053 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20054 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20055 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20056 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20057 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20058 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20059 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20060 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20061 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20062 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20063 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20064 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20065 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20066 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20067 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20068 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20069 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20070 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20071 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20072 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20073 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20074 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
20075 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20076 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20077 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20078 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20079 /* For V5 or later processors we default to using VFP; but the user
20080 should really set the FPU type explicitly. */
20081 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20082 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20083 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20084 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20085 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20086 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20087 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
20088 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20089 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20090 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
20091 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20092 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20093 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20094 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20095 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20096 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
20097 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20098 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20099 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20100 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
20101 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20102 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
20103 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
20104 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
20105 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
20106 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
20107 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
20108 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
20109 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
20110 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
20111 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
20112 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20113 | FPU_NEON_EXT_V1
),
20115 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
20116 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
20117 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
20118 /* ??? XSCALE is really an architecture. */
20119 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20120 /* ??? iwmmxt is not a processor. */
20121 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
20122 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
20123 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20125 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
20126 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
20129 struct arm_arch_option_table
20132 const arm_feature_set value
;
20133 const arm_feature_set default_fpu
;
20136 /* This list should, at a minimum, contain all the architecture names
20137 recognized by GCC. */
20138 static const struct arm_arch_option_table arm_archs
[] =
20140 {"all", ARM_ANY
, FPU_ARCH_FPA
},
20141 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
20142 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
20143 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20144 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20145 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
20146 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
20147 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
20148 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
20149 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
20150 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
20151 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
20152 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
20153 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
20154 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
20155 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
20156 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
20157 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20158 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20159 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
20160 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
20161 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
20162 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
20163 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
20164 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
20165 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
20166 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
20167 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
20168 /* The official spelling of the ARMv7 profile variants is the dashed form.
20169 Accept the non-dashed form for compatibility with old toolchains. */
20170 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20171 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20172 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20173 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20174 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20175 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20176 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
20177 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
20178 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
20179 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
20182 /* ISA extensions in the co-processor space. */
20183 struct arm_option_cpu_value_table
20186 const arm_feature_set value
;
20189 static const struct arm_option_cpu_value_table arm_extensions
[] =
20191 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
20192 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
20193 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
20194 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
20195 {NULL
, ARM_ARCH_NONE
}
20198 /* This list should, at a minimum, contain all the fpu names
20199 recognized by GCC. */
20200 static const struct arm_option_cpu_value_table arm_fpus
[] =
20202 {"softfpa", FPU_NONE
},
20203 {"fpe", FPU_ARCH_FPE
},
20204 {"fpe2", FPU_ARCH_FPE
},
20205 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
20206 {"fpa", FPU_ARCH_FPA
},
20207 {"fpa10", FPU_ARCH_FPA
},
20208 {"fpa11", FPU_ARCH_FPA
},
20209 {"arm7500fe", FPU_ARCH_FPA
},
20210 {"softvfp", FPU_ARCH_VFP
},
20211 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
20212 {"vfp", FPU_ARCH_VFP_V2
},
20213 {"vfp9", FPU_ARCH_VFP_V2
},
20214 {"vfp3", FPU_ARCH_VFP_V3
},
20215 {"vfp10", FPU_ARCH_VFP_V2
},
20216 {"vfp10-r0", FPU_ARCH_VFP_V1
},
20217 {"vfpxd", FPU_ARCH_VFP_V1xD
},
20218 {"arm1020t", FPU_ARCH_VFP_V1
},
20219 {"arm1020e", FPU_ARCH_VFP_V2
},
20220 {"arm1136jfs", FPU_ARCH_VFP_V2
},
20221 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
20222 {"maverick", FPU_ARCH_MAVERICK
},
20223 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
20224 {NULL
, ARM_ARCH_NONE
}
20227 struct arm_option_value_table
20233 static const struct arm_option_value_table arm_float_abis
[] =
20235 {"hard", ARM_FLOAT_ABI_HARD
},
20236 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
20237 {"soft", ARM_FLOAT_ABI_SOFT
},
20242 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20243 static const struct arm_option_value_table arm_eabis
[] =
20245 {"gnu", EF_ARM_EABI_UNKNOWN
},
20246 {"4", EF_ARM_EABI_VER4
},
20247 {"5", EF_ARM_EABI_VER5
},
20252 struct arm_long_option_table
20254 char * option
; /* Substring to match. */
20255 char * help
; /* Help information. */
20256 int (* func
) (char * subopt
); /* Function to decode sub-option. */
20257 char * deprecated
; /* If non-null, print this message. */
20261 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
20263 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
20265 /* Copy the feature set, so that we can modify it. */
20266 *ext_set
= **opt_p
;
20269 while (str
!= NULL
&& *str
!= 0)
20271 const struct arm_option_cpu_value_table
* opt
;
20277 as_bad (_("invalid architectural extension"));
20282 ext
= strchr (str
, '+');
20285 optlen
= ext
- str
;
20287 optlen
= strlen (str
);
20291 as_bad (_("missing architectural extension"));
20295 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
20296 if (strncmp (opt
->name
, str
, optlen
) == 0)
20298 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
20302 if (opt
->name
== NULL
)
20304 as_bad (_("unknown architectural extension `%s'"), str
);
20315 arm_parse_cpu (char * str
)
20317 const struct arm_cpu_option_table
* opt
;
20318 char * ext
= strchr (str
, '+');
20322 optlen
= ext
- str
;
20324 optlen
= strlen (str
);
20328 as_bad (_("missing cpu name `%s'"), str
);
20332 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
20333 if (strncmp (opt
->name
, str
, optlen
) == 0)
20335 mcpu_cpu_opt
= &opt
->value
;
20336 mcpu_fpu_opt
= &opt
->default_fpu
;
20337 if (opt
->canonical_name
)
20338 strcpy (selected_cpu_name
, opt
->canonical_name
);
20342 for (i
= 0; i
< optlen
; i
++)
20343 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20344 selected_cpu_name
[i
] = 0;
20348 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
20353 as_bad (_("unknown cpu `%s'"), str
);
20358 arm_parse_arch (char * str
)
20360 const struct arm_arch_option_table
*opt
;
20361 char *ext
= strchr (str
, '+');
20365 optlen
= ext
- str
;
20367 optlen
= strlen (str
);
20371 as_bad (_("missing architecture name `%s'"), str
);
20375 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
20376 if (streq (opt
->name
, str
))
20378 march_cpu_opt
= &opt
->value
;
20379 march_fpu_opt
= &opt
->default_fpu
;
20380 strcpy (selected_cpu_name
, opt
->name
);
20383 return arm_parse_extension (ext
, &march_cpu_opt
);
20388 as_bad (_("unknown architecture `%s'\n"), str
);
20393 arm_parse_fpu (char * str
)
20395 const struct arm_option_cpu_value_table
* opt
;
20397 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20398 if (streq (opt
->name
, str
))
20400 mfpu_opt
= &opt
->value
;
20404 as_bad (_("unknown floating point format `%s'\n"), str
);
20409 arm_parse_float_abi (char * str
)
20411 const struct arm_option_value_table
* opt
;
20413 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
20414 if (streq (opt
->name
, str
))
20416 mfloat_abi_opt
= opt
->value
;
20420 as_bad (_("unknown floating point abi `%s'\n"), str
);
20426 arm_parse_eabi (char * str
)
20428 const struct arm_option_value_table
*opt
;
20430 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
20431 if (streq (opt
->name
, str
))
20433 meabi_flags
= opt
->value
;
20436 as_bad (_("unknown EABI `%s'\n"), str
);
20441 struct arm_long_option_table arm_long_opts
[] =
20443 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20444 arm_parse_cpu
, NULL
},
20445 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20446 arm_parse_arch
, NULL
},
20447 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20448 arm_parse_fpu
, NULL
},
20449 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20450 arm_parse_float_abi
, NULL
},
20452 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
20453 arm_parse_eabi
, NULL
},
20455 {NULL
, NULL
, 0, NULL
}
20459 md_parse_option (int c
, char * arg
)
20461 struct arm_option_table
*opt
;
20462 const struct arm_legacy_option_table
*fopt
;
20463 struct arm_long_option_table
*lopt
;
20469 target_big_endian
= 1;
20475 target_big_endian
= 0;
20479 case OPTION_FIX_V4BX
:
20484 /* Listing option. Just ignore these, we don't support additional
20489 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20491 if (c
== opt
->option
[0]
20492 && ((arg
== NULL
&& opt
->option
[1] == 0)
20493 || streq (arg
, opt
->option
+ 1)))
20495 #if WARN_DEPRECATED
20496 /* If the option is deprecated, tell the user. */
20497 if (opt
->deprecated
!= NULL
)
20498 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20499 arg
? arg
: "", _(opt
->deprecated
));
20502 if (opt
->var
!= NULL
)
20503 *opt
->var
= opt
->value
;
20509 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
20511 if (c
== fopt
->option
[0]
20512 && ((arg
== NULL
&& fopt
->option
[1] == 0)
20513 || streq (arg
, fopt
->option
+ 1)))
20515 #if WARN_DEPRECATED
20516 /* If the option is deprecated, tell the user. */
20517 if (fopt
->deprecated
!= NULL
)
20518 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20519 arg
? arg
: "", _(fopt
->deprecated
));
20522 if (fopt
->var
!= NULL
)
20523 *fopt
->var
= &fopt
->value
;
20529 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20531 /* These options are expected to have an argument. */
20532 if (c
== lopt
->option
[0]
20534 && strncmp (arg
, lopt
->option
+ 1,
20535 strlen (lopt
->option
+ 1)) == 0)
20537 #if WARN_DEPRECATED
20538 /* If the option is deprecated, tell the user. */
20539 if (lopt
->deprecated
!= NULL
)
20540 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
20541 _(lopt
->deprecated
));
20544 /* Call the sup-option parser. */
20545 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
20556 md_show_usage (FILE * fp
)
20558 struct arm_option_table
*opt
;
20559 struct arm_long_option_table
*lopt
;
20561 fprintf (fp
, _(" ARM-specific assembler options:\n"));
20563 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20564 if (opt
->help
!= NULL
)
20565 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
20567 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20568 if (lopt
->help
!= NULL
)
20569 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
20573 -EB assemble code for a big-endian cpu\n"));
20578 -EL assemble code for a little-endian cpu\n"));
20582 --fix-v4bx Allow BX in ARMv4 code\n"));
20590 arm_feature_set flags
;
20591 } cpu_arch_ver_table
;
20593 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20594 least features first. */
20595 static const cpu_arch_ver_table cpu_arch_ver
[] =
20600 {4, ARM_ARCH_V5TE
},
20601 {5, ARM_ARCH_V5TEJ
},
20606 {8, ARM_ARCH_V6T2
},
20607 {10, ARM_ARCH_V7A
},
20608 {10, ARM_ARCH_V7R
},
20609 {10, ARM_ARCH_V7M
},
20613 /* Set the public EABI object attributes. */
20615 aeabi_set_public_attributes (void)
20618 arm_feature_set flags
;
20619 arm_feature_set tmp
;
20620 const cpu_arch_ver_table
*p
;
20622 /* Choose the architecture based on the capabilities of the requested cpu
20623 (if any) and/or the instructions actually used. */
20624 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20625 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20626 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20627 /*Allow the user to override the reported architecture. */
20630 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
20631 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
20636 for (p
= cpu_arch_ver
; p
->val
; p
++)
20638 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20641 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20645 /* Tag_CPU_name. */
20646 if (selected_cpu_name
[0])
20650 p
= selected_cpu_name
;
20651 if (strncmp (p
, "armv", 4) == 0)
20656 for (i
= 0; p
[i
]; i
++)
20657 p
[i
] = TOUPPER (p
[i
]);
20659 bfd_elf_add_proc_attr_string (stdoutput
, 5, p
);
20661 /* Tag_CPU_arch. */
20662 bfd_elf_add_proc_attr_int (stdoutput
, 6, arch
);
20663 /* Tag_CPU_arch_profile. */
20664 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20665 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'A');
20666 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20667 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'R');
20668 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
20669 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'M');
20670 /* Tag_ARM_ISA_use. */
20671 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20672 bfd_elf_add_proc_attr_int (stdoutput
, 8, 1);
20673 /* Tag_THUMB_ISA_use. */
20674 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20675 bfd_elf_add_proc_attr_int (stdoutput
, 9,
20676 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20677 /* Tag_VFP_arch. */
20678 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20679 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20680 bfd_elf_add_proc_attr_int (stdoutput
, 10, 3);
20681 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20682 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20683 bfd_elf_add_proc_attr_int (stdoutput
, 10, 2);
20684 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20685 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20686 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20687 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20688 bfd_elf_add_proc_attr_int (stdoutput
, 10, 1);
20689 /* Tag_WMMX_arch. */
20690 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20691 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20692 bfd_elf_add_proc_attr_int (stdoutput
, 11, 1);
20693 /* Tag_NEON_arch. */
20694 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
20695 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
20696 bfd_elf_add_proc_attr_int (stdoutput
, 12, 1);
20699 /* Add the default contents for the .ARM.attributes section. */
20703 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20706 aeabi_set_public_attributes ();
20708 #endif /* OBJ_ELF */
20711 /* Parse a .cpu directive. */
20714 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20716 const struct arm_cpu_option_table
*opt
;
20720 name
= input_line_pointer
;
20721 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20722 input_line_pointer
++;
20723 saved_char
= *input_line_pointer
;
20724 *input_line_pointer
= 0;
20726 /* Skip the first "all" entry. */
20727 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20728 if (streq (opt
->name
, name
))
20730 mcpu_cpu_opt
= &opt
->value
;
20731 selected_cpu
= opt
->value
;
20732 if (opt
->canonical_name
)
20733 strcpy (selected_cpu_name
, opt
->canonical_name
);
20737 for (i
= 0; opt
->name
[i
]; i
++)
20738 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20739 selected_cpu_name
[i
] = 0;
20741 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20742 *input_line_pointer
= saved_char
;
20743 demand_empty_rest_of_line ();
20746 as_bad (_("unknown cpu `%s'"), name
);
20747 *input_line_pointer
= saved_char
;
20748 ignore_rest_of_line ();
20752 /* Parse a .arch directive. */
20755 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20757 const struct arm_arch_option_table
*opt
;
20761 name
= input_line_pointer
;
20762 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20763 input_line_pointer
++;
20764 saved_char
= *input_line_pointer
;
20765 *input_line_pointer
= 0;
20767 /* Skip the first "all" entry. */
20768 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20769 if (streq (opt
->name
, name
))
20771 mcpu_cpu_opt
= &opt
->value
;
20772 selected_cpu
= opt
->value
;
20773 strcpy (selected_cpu_name
, opt
->name
);
20774 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20775 *input_line_pointer
= saved_char
;
20776 demand_empty_rest_of_line ();
20780 as_bad (_("unknown architecture `%s'\n"), name
);
20781 *input_line_pointer
= saved_char
;
20782 ignore_rest_of_line ();
20786 /* Parse a .object_arch directive. */
20789 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
20791 const struct arm_arch_option_table
*opt
;
20795 name
= input_line_pointer
;
20796 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20797 input_line_pointer
++;
20798 saved_char
= *input_line_pointer
;
20799 *input_line_pointer
= 0;
20801 /* Skip the first "all" entry. */
20802 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20803 if (streq (opt
->name
, name
))
20805 object_arch
= &opt
->value
;
20806 *input_line_pointer
= saved_char
;
20807 demand_empty_rest_of_line ();
20811 as_bad (_("unknown architecture `%s'\n"), name
);
20812 *input_line_pointer
= saved_char
;
20813 ignore_rest_of_line ();
20817 /* Parse a .fpu directive. */
20820 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20822 const struct arm_option_cpu_value_table
*opt
;
20826 name
= input_line_pointer
;
20827 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20828 input_line_pointer
++;
20829 saved_char
= *input_line_pointer
;
20830 *input_line_pointer
= 0;
20832 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20833 if (streq (opt
->name
, name
))
20835 mfpu_opt
= &opt
->value
;
20836 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20837 *input_line_pointer
= saved_char
;
20838 demand_empty_rest_of_line ();
20842 as_bad (_("unknown floating point format `%s'\n"), name
);
20843 *input_line_pointer
= saved_char
;
20844 ignore_rest_of_line ();
20847 /* Copy symbol information. */
20849 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
20851 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);