1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
188 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_arch_any
= ARM_ANY
;
202 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
203 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
204 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
206 static const arm_feature_set arm_cext_iwmmxt2
=
207 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
208 static const arm_feature_set arm_cext_iwmmxt
=
209 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
210 static const arm_feature_set arm_cext_xscale
=
211 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
212 static const arm_feature_set arm_cext_maverick
=
213 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
214 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
215 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v1xd
=
217 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
218 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
219 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
221 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
222 static const arm_feature_set fpu_vfp_ext_d32
=
223 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
224 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
225 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
226 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
227 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
228 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
229 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
231 static int mfloat_abi_opt
= -1;
232 /* Record user cpu selection for object attributes. */
233 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
234 /* Must be long enough to hold any of the names in arm_cpus. */
235 static char selected_cpu_name
[16];
238 static int meabi_flags
= EABI_DEFAULT
;
240 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
243 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
248 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
253 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
254 symbolS
* GOT_symbol
;
257 /* 0: assemble for ARM,
258 1: assemble for Thumb,
259 2: assemble for Thumb even though target CPU does not support thumb
261 static int thumb_mode
= 0;
262 /* A value distinct from the possible values for thumb_mode that we
263 can use to record whether thumb_mode has been copied into the
264 tc_frag_data field of a frag. */
265 #define MODE_RECORDED (1 << 4)
267 /* Specifies the intrinsic IT insn behavior mode. */
268 enum implicit_it_mode
270 IMPLICIT_IT_MODE_NEVER
= 0x00,
271 IMPLICIT_IT_MODE_ARM
= 0x01,
272 IMPLICIT_IT_MODE_THUMB
= 0x02,
273 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
275 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
277 /* If unified_syntax is true, we are processing the new unified
278 ARM/Thumb syntax. Important differences from the old ARM mode:
280 - Immediate operands do not require a # prefix.
281 - Conditional affixes always appear at the end of the
282 instruction. (For backward compatibility, those instructions
283 that formerly had them in the middle, continue to accept them
285 - The IT instruction may appear, and if it does is validated
286 against subsequent conditional affixes. It does not generate
289 Important differences from the old Thumb mode:
291 - Immediate operands do not require a # prefix.
292 - Most of the V6T2 instructions are only available in unified mode.
293 - The .N and .W suffixes are recognized and honored (it is an error
294 if they cannot be honored).
295 - All instructions set the flags if and only if they have an 's' affix.
296 - Conditional affixes may be used. They are validated against
297 preceding IT instructions. Unlike ARM mode, you cannot use a
298 conditional affix except in the scope of an IT instruction. */
300 static bfd_boolean unified_syntax
= FALSE
;
315 enum neon_el_type type
;
319 #define NEON_MAX_TYPE_ELS 4
323 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
327 enum it_instruction_type
332 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
333 if inside, should be the last one. */
334 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
335 i.e. BKPT and NOP. */
336 IT_INSN
/* The IT insn has been parsed. */
342 unsigned long instruction
;
346 /* "uncond_value" is set to the value in place of the conditional field in
347 unconditional versions of the instruction, or -1 if nothing is
350 struct neon_type vectype
;
351 /* This does not indicate an actual NEON instruction, only that
352 the mnemonic accepts neon-style type suffixes. */
354 /* Set to the opcode if the instruction needs relaxation.
355 Zero if the instruction is not relaxed. */
359 bfd_reloc_code_real_type type
;
364 enum it_instruction_type it_insn_type
;
370 struct neon_type_el vectype
;
371 unsigned present
: 1; /* Operand present. */
372 unsigned isreg
: 1; /* Operand was a register. */
373 unsigned immisreg
: 1; /* .imm field is a second register. */
374 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
375 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
376 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
377 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
378 instructions. This allows us to disambiguate ARM <-> vector insns. */
379 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
380 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
381 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
382 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
383 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
384 unsigned writeback
: 1; /* Operand has trailing ! */
385 unsigned preind
: 1; /* Preindexed address. */
386 unsigned postind
: 1; /* Postindexed address. */
387 unsigned negative
: 1; /* Index register was negated. */
388 unsigned shifted
: 1; /* Shift applied to operation. */
389 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
393 static struct arm_it inst
;
395 #define NUM_FLOAT_VALS 8
397 const char * fp_const
[] =
399 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
402 /* Number of littlenums required to hold an extended precision number. */
403 #define MAX_LITTLENUMS 6
405 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
415 #define CP_T_X 0x00008000
416 #define CP_T_Y 0x00400000
418 #define CONDS_BIT 0x00100000
419 #define LOAD_BIT 0x00100000
421 #define DOUBLE_LOAD_FLAG 0x00000001
425 const char * template_name
;
429 #define COND_ALWAYS 0xE
433 const char * template_name
;
437 struct asm_barrier_opt
439 const char * template_name
;
443 /* The bit that distinguishes CPSR and SPSR. */
444 #define SPSR_BIT (1 << 22)
446 /* The individual PSR flag bits. */
447 #define PSR_c (1 << 16)
448 #define PSR_x (1 << 17)
449 #define PSR_s (1 << 18)
450 #define PSR_f (1 << 19)
455 bfd_reloc_code_real_type reloc
;
460 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
461 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
466 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
469 /* Bits for DEFINED field in neon_typed_alias. */
470 #define NTA_HASTYPE 1
471 #define NTA_HASINDEX 2
473 struct neon_typed_alias
475 unsigned char defined
;
477 struct neon_type_el eltype
;
480 /* ARM register categories. This includes coprocessor numbers and various
481 architecture extensions' registers. */
507 /* Structure for a hash table entry for a register.
508 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
509 information which states whether a vector type or index is specified (for a
510 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
514 unsigned char number
;
516 unsigned char builtin
;
517 struct neon_typed_alias
* neon
;
520 /* Diagnostics used when we don't get a register of the expected type. */
521 const char * const reg_expected_msgs
[] =
523 N_("ARM register expected"),
524 N_("bad or missing co-processor number"),
525 N_("co-processor register expected"),
526 N_("FPA register expected"),
527 N_("VFP single precision register expected"),
528 N_("VFP/Neon double precision register expected"),
529 N_("Neon quad precision register expected"),
530 N_("VFP single or double precision register expected"),
531 N_("Neon double or quad precision register expected"),
532 N_("VFP single, double or Neon quad precision register expected"),
533 N_("VFP system register expected"),
534 N_("Maverick MVF register expected"),
535 N_("Maverick MVD register expected"),
536 N_("Maverick MVFX register expected"),
537 N_("Maverick MVDX register expected"),
538 N_("Maverick MVAX register expected"),
539 N_("Maverick DSPSC register expected"),
540 N_("iWMMXt data register expected"),
541 N_("iWMMXt control register expected"),
542 N_("iWMMXt scalar register expected"),
543 N_("XScale accumulator register expected"),
546 /* Some well known registers that we refer to directly elsewhere. */
551 /* ARM instructions take 4bytes in the object file, Thumb instructions
557 /* Basic string to match. */
558 const char * template_name
;
560 /* Parameters to instruction. */
561 unsigned int operands
[8];
563 /* Conditional tag - see opcode_lookup. */
564 unsigned int tag
: 4;
566 /* Basic instruction code. */
567 unsigned int avalue
: 28;
569 /* Thumb-format instruction code. */
572 /* Which architecture variant provides this instruction. */
573 const arm_feature_set
* avariant
;
574 const arm_feature_set
* tvariant
;
576 /* Function to call to encode instruction in ARM format. */
577 void (* aencode
) (void);
579 /* Function to call to encode instruction in Thumb format. */
580 void (* tencode
) (void);
583 /* Defines for various bits that we will want to toggle. */
584 #define INST_IMMEDIATE 0x02000000
585 #define OFFSET_REG 0x02000000
586 #define HWOFFSET_IMM 0x00400000
587 #define SHIFT_BY_REG 0x00000010
588 #define PRE_INDEX 0x01000000
589 #define INDEX_UP 0x00800000
590 #define WRITE_BACK 0x00200000
591 #define LDM_TYPE_2_OR_3 0x00400000
592 #define CPSI_MMOD 0x00020000
594 #define LITERAL_MASK 0xf000f000
595 #define OPCODE_MASK 0xfe1fffff
596 #define V4_STR_BIT 0x00000020
598 #define T2_SUBS_PC_LR 0xf3de8f00
600 #define DATA_OP_SHIFT 21
602 #define T2_OPCODE_MASK 0xfe1fffff
603 #define T2_DATA_OP_SHIFT 21
605 /* Codes to distinguish the arithmetic instructions. */
616 #define OPCODE_CMP 10
617 #define OPCODE_CMN 11
618 #define OPCODE_ORR 12
619 #define OPCODE_MOV 13
620 #define OPCODE_BIC 14
621 #define OPCODE_MVN 15
623 #define T2_OPCODE_AND 0
624 #define T2_OPCODE_BIC 1
625 #define T2_OPCODE_ORR 2
626 #define T2_OPCODE_ORN 3
627 #define T2_OPCODE_EOR 4
628 #define T2_OPCODE_ADD 8
629 #define T2_OPCODE_ADC 10
630 #define T2_OPCODE_SBC 11
631 #define T2_OPCODE_SUB 13
632 #define T2_OPCODE_RSB 14
634 #define T_OPCODE_MUL 0x4340
635 #define T_OPCODE_TST 0x4200
636 #define T_OPCODE_CMN 0x42c0
637 #define T_OPCODE_NEG 0x4240
638 #define T_OPCODE_MVN 0x43c0
640 #define T_OPCODE_ADD_R3 0x1800
641 #define T_OPCODE_SUB_R3 0x1a00
642 #define T_OPCODE_ADD_HI 0x4400
643 #define T_OPCODE_ADD_ST 0xb000
644 #define T_OPCODE_SUB_ST 0xb080
645 #define T_OPCODE_ADD_SP 0xa800
646 #define T_OPCODE_ADD_PC 0xa000
647 #define T_OPCODE_ADD_I8 0x3000
648 #define T_OPCODE_SUB_I8 0x3800
649 #define T_OPCODE_ADD_I3 0x1c00
650 #define T_OPCODE_SUB_I3 0x1e00
652 #define T_OPCODE_ASR_R 0x4100
653 #define T_OPCODE_LSL_R 0x4080
654 #define T_OPCODE_LSR_R 0x40c0
655 #define T_OPCODE_ROR_R 0x41c0
656 #define T_OPCODE_ASR_I 0x1000
657 #define T_OPCODE_LSL_I 0x0000
658 #define T_OPCODE_LSR_I 0x0800
660 #define T_OPCODE_MOV_I8 0x2000
661 #define T_OPCODE_CMP_I8 0x2800
662 #define T_OPCODE_CMP_LR 0x4280
663 #define T_OPCODE_MOV_HR 0x4600
664 #define T_OPCODE_CMP_HR 0x4500
666 #define T_OPCODE_LDR_PC 0x4800
667 #define T_OPCODE_LDR_SP 0x9800
668 #define T_OPCODE_STR_SP 0x9000
669 #define T_OPCODE_LDR_IW 0x6800
670 #define T_OPCODE_STR_IW 0x6000
671 #define T_OPCODE_LDR_IH 0x8800
672 #define T_OPCODE_STR_IH 0x8000
673 #define T_OPCODE_LDR_IB 0x7800
674 #define T_OPCODE_STR_IB 0x7000
675 #define T_OPCODE_LDR_RW 0x5800
676 #define T_OPCODE_STR_RW 0x5000
677 #define T_OPCODE_LDR_RH 0x5a00
678 #define T_OPCODE_STR_RH 0x5200
679 #define T_OPCODE_LDR_RB 0x5c00
680 #define T_OPCODE_STR_RB 0x5400
682 #define T_OPCODE_PUSH 0xb400
683 #define T_OPCODE_POP 0xbc00
685 #define T_OPCODE_BRANCH 0xe000
687 #define THUMB_SIZE 2 /* Size of thumb instruction. */
688 #define THUMB_PP_PC_LR 0x0100
689 #define THUMB_LOAD_BIT 0x0800
690 #define THUMB2_LOAD_BIT 0x00100000
692 #define BAD_ARGS _("bad arguments to instruction")
693 #define BAD_SP _("r13 not allowed here")
694 #define BAD_PC _("r15 not allowed here")
695 #define BAD_COND _("instruction cannot be conditional")
696 #define BAD_OVERLAP _("registers may not be the same")
697 #define BAD_HIREG _("lo register required")
698 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
699 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
700 #define BAD_BRANCH _("branch must be last instruction in IT block")
701 #define BAD_NOT_IT _("instruction not allowed in IT block")
702 #define BAD_FPU _("selected FPU does not support instruction")
703 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
704 #define BAD_IT_COND _("incorrect condition in IT block")
705 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
706 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
707 #define BAD_PC_ADDRESSING \
708 _("cannot use register index with PC-relative addressing")
709 #define BAD_PC_WRITEBACK \
710 _("cannot use writeback with PC-relative addressing")
712 static struct hash_control
* arm_ops_hsh
;
713 static struct hash_control
* arm_cond_hsh
;
714 static struct hash_control
* arm_shift_hsh
;
715 static struct hash_control
* arm_psr_hsh
;
716 static struct hash_control
* arm_v7m_psr_hsh
;
717 static struct hash_control
* arm_reg_hsh
;
718 static struct hash_control
* arm_reloc_hsh
;
719 static struct hash_control
* arm_barrier_opt_hsh
;
721 /* Stuff needed to resolve the label ambiguity
730 symbolS
* last_label_seen
;
731 static int label_is_thumb_function_name
= FALSE
;
733 /* Literal pool structure. Held on a per-section
734 and per-sub-section basis. */
736 #define MAX_LITERAL_POOL_SIZE 1024
737 typedef struct literal_pool
739 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
740 unsigned int next_free_entry
;
745 struct literal_pool
* next
;
748 /* Pointer to a linked list of literal pools. */
749 literal_pool
* list_of_pools
= NULL
;
752 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
754 static struct current_it now_it
;
758 now_it_compatible (int cond
)
760 return (cond
& ~1) == (now_it
.cc
& ~1);
764 conditional_insn (void)
766 return inst
.cond
!= COND_ALWAYS
;
769 static int in_it_block (void);
771 static int handle_it_state (void);
773 static void force_automatic_it_block_close (void);
775 static void it_fsm_post_encode (void);
777 #define set_it_insn_type(type) \
780 inst.it_insn_type = type; \
781 if (handle_it_state () == FAIL) \
786 #define set_it_insn_type_nonvoid(type, failret) \
789 inst.it_insn_type = type; \
790 if (handle_it_state () == FAIL) \
795 #define set_it_insn_type_last() \
798 if (inst.cond == COND_ALWAYS) \
799 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
801 set_it_insn_type (INSIDE_IT_LAST_INSN); \
807 /* This array holds the chars that always start a comment. If the
808 pre-processor is disabled, these aren't very useful. */
809 const char comment_chars
[] = "@";
811 /* This array holds the chars that only start a comment at the beginning of
812 a line. If the line seems to have the form '# 123 filename'
813 .line and .file directives will appear in the pre-processed output. */
814 /* Note that input_file.c hand checks for '#' at the beginning of the
815 first line of the input file. This is because the compiler outputs
816 #NO_APP at the beginning of its output. */
817 /* Also note that comments like this one will always work. */
818 const char line_comment_chars
[] = "#";
820 const char line_separator_chars
[] = ";";
822 /* Chars that can be used to separate mant
823 from exp in floating point numbers. */
824 const char EXP_CHARS
[] = "eE";
826 /* Chars that mean this number is a floating point constant. */
830 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
832 /* Prefix characters that indicate the start of an immediate
834 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
836 /* Separator character handling. */
838 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
841 skip_past_char (char ** str
, char c
)
852 #define skip_past_comma(str) skip_past_char (str, ',')
854 /* Arithmetic expressions (possibly involving symbols). */
856 /* Return TRUE if anything in the expression is a bignum. */
859 walk_no_bignums (symbolS
* sp
)
861 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
864 if (symbol_get_value_expression (sp
)->X_add_symbol
)
866 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
867 || (symbol_get_value_expression (sp
)->X_op_symbol
868 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
874 static int in_my_get_expression
= 0;
876 /* Third argument to my_get_expression. */
877 #define GE_NO_PREFIX 0
878 #define GE_IMM_PREFIX 1
879 #define GE_OPT_PREFIX 2
880 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
881 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
882 #define GE_OPT_PREFIX_BIG 3
885 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
890 /* In unified syntax, all prefixes are optional. */
892 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
897 case GE_NO_PREFIX
: break;
899 if (!is_immediate_prefix (**str
))
901 inst
.error
= _("immediate expression requires a # prefix");
907 case GE_OPT_PREFIX_BIG
:
908 if (is_immediate_prefix (**str
))
914 memset (ep
, 0, sizeof (expressionS
));
916 save_in
= input_line_pointer
;
917 input_line_pointer
= *str
;
918 in_my_get_expression
= 1;
919 seg
= expression (ep
);
920 in_my_get_expression
= 0;
922 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
924 /* We found a bad or missing expression in md_operand(). */
925 *str
= input_line_pointer
;
926 input_line_pointer
= save_in
;
927 if (inst
.error
== NULL
)
928 inst
.error
= (ep
->X_op
== O_absent
929 ? _("missing expression") :_("bad expression"));
934 if (seg
!= absolute_section
935 && seg
!= text_section
936 && seg
!= data_section
937 && seg
!= bss_section
938 && seg
!= undefined_section
)
940 inst
.error
= _("bad segment");
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
947 /* Get rid of any bignums now, so that we don't generate an error for which
948 we can't establish a line number later on. Big numbers are never valid
949 in instructions, which is where this routine is always called. */
950 if (prefix_mode
!= GE_OPT_PREFIX_BIG
951 && (ep
->X_op
== O_big
953 && (walk_no_bignums (ep
->X_add_symbol
)
955 && walk_no_bignums (ep
->X_op_symbol
))))))
957 inst
.error
= _("invalid constant");
958 *str
= input_line_pointer
;
959 input_line_pointer
= save_in
;
963 *str
= input_line_pointer
;
964 input_line_pointer
= save_in
;
968 /* Turn a string in input_line_pointer into a floating point constant
969 of type TYPE, and store the appropriate bytes in *LITP. The number
970 of LITTLENUMS emitted is stored in *SIZEP. An error message is
971 returned, or NULL on OK.
973 Note that fp constants aren't represent in the normal way on the ARM.
974 In big endian mode, things are as expected. However, in little endian
975 mode fp constants are big-endian word-wise, and little-endian byte-wise
976 within the words. For example, (double) 1.1 in big endian mode is
977 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
978 the byte sequence 99 99 f1 3f 9a 99 99 99.
980 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
983 md_atof (int type
, char * litP
, int * sizeP
)
986 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1018 return _("Unrecognized or unsupported floating point constant");
1021 t
= atof_ieee (input_line_pointer
, type
, words
);
1023 input_line_pointer
= t
;
1024 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1026 if (target_big_endian
)
1028 for (i
= 0; i
< prec
; i
++)
1030 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1031 litP
+= sizeof (LITTLENUM_TYPE
);
1036 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1037 for (i
= prec
- 1; i
>= 0; i
--)
1039 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1040 litP
+= sizeof (LITTLENUM_TYPE
);
1043 /* For a 4 byte float the order of elements in `words' is 1 0.
1044 For an 8 byte float the order is 1 0 3 2. */
1045 for (i
= 0; i
< prec
; i
+= 2)
1047 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1048 sizeof (LITTLENUM_TYPE
));
1049 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1050 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1051 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1058 /* We handle all bad expressions here, so that we can report the faulty
1059 instruction in the error message. */
1061 md_operand (expressionS
* exp
)
1063 if (in_my_get_expression
)
1064 exp
->X_op
= O_illegal
;
1067 /* Immediate values. */
1069 /* Generic immediate-value read function for use in directives.
1070 Accepts anything that 'expression' can fold to a constant.
1071 *val receives the number. */
1074 immediate_for_directive (int *val
)
1077 exp
.X_op
= O_illegal
;
1079 if (is_immediate_prefix (*input_line_pointer
))
1081 input_line_pointer
++;
1085 if (exp
.X_op
!= O_constant
)
1087 as_bad (_("expected #constant"));
1088 ignore_rest_of_line ();
1091 *val
= exp
.X_add_number
;
1096 /* Register parsing. */
1098 /* Generic register parser. CCP points to what should be the
1099 beginning of a register name. If it is indeed a valid register
1100 name, advance CCP over it and return the reg_entry structure;
1101 otherwise return NULL. Does not issue diagnostics. */
1103 static struct reg_entry
*
1104 arm_reg_parse_multi (char **ccp
)
1108 struct reg_entry
*reg
;
1110 #ifdef REGISTER_PREFIX
1111 if (*start
!= REGISTER_PREFIX
)
1115 #ifdef OPTIONAL_REGISTER_PREFIX
1116 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1121 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1126 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1128 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1138 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1139 enum arm_reg_type type
)
1141 /* Alternative syntaxes are accepted for a few register classes. */
1148 /* Generic coprocessor register names are allowed for these. */
1149 if (reg
&& reg
->type
== REG_TYPE_CN
)
1154 /* For backward compatibility, a bare number is valid here. */
1156 unsigned long processor
= strtoul (start
, ccp
, 10);
1157 if (*ccp
!= start
&& processor
<= 15)
1161 case REG_TYPE_MMXWC
:
1162 /* WC includes WCG. ??? I'm not sure this is true for all
1163 instructions that take WC registers. */
1164 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1175 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1176 return value is the register number or FAIL. */
1179 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1182 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1185 /* Do not allow a scalar (reg+index) to parse as a register. */
1186 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1189 if (reg
&& reg
->type
== type
)
1192 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1199 /* Parse a Neon type specifier. *STR should point at the leading '.'
1200 character. Does no verification at this stage that the type fits the opcode
1207 Can all be legally parsed by this function.
1209 Fills in neon_type struct pointer with parsed information, and updates STR
1210 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1211 type, FAIL if not. */
1214 parse_neon_type (struct neon_type
*type
, char **str
)
1221 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1223 enum neon_el_type thistype
= NT_untyped
;
1224 unsigned thissize
= -1u;
1231 /* Just a size without an explicit type. */
1235 switch (TOLOWER (*ptr
))
1237 case 'i': thistype
= NT_integer
; break;
1238 case 'f': thistype
= NT_float
; break;
1239 case 'p': thistype
= NT_poly
; break;
1240 case 's': thistype
= NT_signed
; break;
1241 case 'u': thistype
= NT_unsigned
; break;
1243 thistype
= NT_float
;
1248 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1254 /* .f is an abbreviation for .f32. */
1255 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1260 thissize
= strtoul (ptr
, &ptr
, 10);
1262 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1265 as_bad (_("bad size %d in type specifier"), thissize
);
1273 type
->el
[type
->elems
].type
= thistype
;
1274 type
->el
[type
->elems
].size
= thissize
;
1279 /* Empty/missing type is not a successful parse. */
1280 if (type
->elems
== 0)
1288 /* Errors may be set multiple times during parsing or bit encoding
1289 (particularly in the Neon bits), but usually the earliest error which is set
1290 will be the most meaningful. Avoid overwriting it with later (cascading)
1291 errors by calling this function. */
1294 first_error (const char *err
)
1300 /* Parse a single type, e.g. ".s32", leading period included. */
1302 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1305 struct neon_type optype
;
1309 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1311 if (optype
.elems
== 1)
1312 *vectype
= optype
.el
[0];
1315 first_error (_("only one type should be specified for operand"));
1321 first_error (_("vector type expected"));
1333 /* Special meanings for indices (which have a range of 0-7), which will fit into
1336 #define NEON_ALL_LANES 15
1337 #define NEON_INTERLEAVE_LANES 14
1339 /* Parse either a register or a scalar, with an optional type. Return the
1340 register number, and optionally fill in the actual type of the register
1341 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1342 type/index information in *TYPEINFO. */
1345 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1346 enum arm_reg_type
*rtype
,
1347 struct neon_typed_alias
*typeinfo
)
1350 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1351 struct neon_typed_alias atype
;
1352 struct neon_type_el parsetype
;
1356 atype
.eltype
.type
= NT_invtype
;
1357 atype
.eltype
.size
= -1;
1359 /* Try alternate syntax for some types of register. Note these are mutually
1360 exclusive with the Neon syntax extensions. */
1363 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1371 /* Undo polymorphism when a set of register types may be accepted. */
1372 if ((type
== REG_TYPE_NDQ
1373 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1374 || (type
== REG_TYPE_VFSD
1375 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1376 || (type
== REG_TYPE_NSDQ
1377 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1378 || reg
->type
== REG_TYPE_NQ
))
1379 || (type
== REG_TYPE_MMXWC
1380 && (reg
->type
== REG_TYPE_MMXWCG
)))
1381 type
= (enum arm_reg_type
) reg
->type
;
1383 if (type
!= reg
->type
)
1389 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1391 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1393 first_error (_("can't redefine type for operand"));
1396 atype
.defined
|= NTA_HASTYPE
;
1397 atype
.eltype
= parsetype
;
1400 if (skip_past_char (&str
, '[') == SUCCESS
)
1402 if (type
!= REG_TYPE_VFD
)
1404 first_error (_("only D registers may be indexed"));
1408 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1410 first_error (_("can't change index for operand"));
1414 atype
.defined
|= NTA_HASINDEX
;
1416 if (skip_past_char (&str
, ']') == SUCCESS
)
1417 atype
.index
= NEON_ALL_LANES
;
1422 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1424 if (exp
.X_op
!= O_constant
)
1426 first_error (_("constant expression required"));
1430 if (skip_past_char (&str
, ']') == FAIL
)
1433 atype
.index
= exp
.X_add_number
;
1448 /* Like arm_reg_parse, but allow allow the following extra features:
1449 - If RTYPE is non-zero, return the (possibly restricted) type of the
1450 register (e.g. Neon double or quad reg when either has been requested).
1451 - If this is a Neon vector type with additional type information, fill
1452 in the struct pointed to by VECTYPE (if non-NULL).
1453 This function will fault on encountering a scalar. */
1456 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1457 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1459 struct neon_typed_alias atype
;
1461 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1466 /* Do not allow a scalar (reg+index) to parse as a register. */
1467 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1469 first_error (_("register operand expected, but got scalar"));
1474 *vectype
= atype
.eltype
;
1481 #define NEON_SCALAR_REG(X) ((X) >> 4)
1482 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1484 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1485 have enough information to be able to do a good job bounds-checking. So, we
1486 just do easy checks here, and do further checks later. */
1489 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1493 struct neon_typed_alias atype
;
1495 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1497 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1500 if (atype
.index
== NEON_ALL_LANES
)
1502 first_error (_("scalar must have an index"));
1505 else if (atype
.index
>= 64 / elsize
)
1507 first_error (_("scalar index out of range"));
1512 *type
= atype
.eltype
;
1516 return reg
* 16 + atype
.index
;
1519 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1522 parse_reg_list (char ** strp
)
1524 char * str
= * strp
;
1528 /* We come back here if we get ranges concatenated by '+' or '|'. */
1543 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1545 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1555 first_error (_("bad range in register list"));
1559 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1561 if (range
& (1 << i
))
1563 (_("Warning: duplicated register (r%d) in register list"),
1571 if (range
& (1 << reg
))
1572 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1574 else if (reg
<= cur_reg
)
1575 as_tsktsk (_("Warning: register range not in ascending order"));
1580 while (skip_past_comma (&str
) != FAIL
1581 || (in_range
= 1, *str
++ == '-'));
1586 first_error (_("missing `}'"));
1594 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1597 if (exp
.X_op
== O_constant
)
1599 if (exp
.X_add_number
1600 != (exp
.X_add_number
& 0x0000ffff))
1602 inst
.error
= _("invalid register mask");
1606 if ((range
& exp
.X_add_number
) != 0)
1608 int regno
= range
& exp
.X_add_number
;
1611 regno
= (1 << regno
) - 1;
1613 (_("Warning: duplicated register (r%d) in register list"),
1617 range
|= exp
.X_add_number
;
1621 if (inst
.reloc
.type
!= 0)
1623 inst
.error
= _("expression too complex");
1627 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1628 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1629 inst
.reloc
.pc_rel
= 0;
1633 if (*str
== '|' || *str
== '+')
1639 while (another_range
);
1645 /* Types of registers in a list. */
1654 /* Parse a VFP register list. If the string is invalid return FAIL.
1655 Otherwise return the number of registers, and set PBASE to the first
1656 register. Parses registers of type ETYPE.
1657 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1658 - Q registers can be used to specify pairs of D registers
1659 - { } can be omitted from around a singleton register list
1660 FIXME: This is not implemented, as it would require backtracking in
1663 This could be done (the meaning isn't really ambiguous), but doesn't
1664 fit in well with the current parsing framework.
1665 - 32 D registers may be used (also true for VFPv3).
1666 FIXME: Types are ignored in these register lists, which is probably a
1670 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1675 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1679 unsigned long mask
= 0;
1684 inst
.error
= _("expecting {");
1693 regtype
= REG_TYPE_VFS
;
1698 regtype
= REG_TYPE_VFD
;
1701 case REGLIST_NEON_D
:
1702 regtype
= REG_TYPE_NDQ
;
1706 if (etype
!= REGLIST_VFP_S
)
1708 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1709 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1713 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1716 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1723 base_reg
= max_regs
;
1727 int setmask
= 1, addregs
= 1;
1729 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1731 if (new_base
== FAIL
)
1733 first_error (_(reg_expected_msgs
[regtype
]));
1737 if (new_base
>= max_regs
)
1739 first_error (_("register out of range in list"));
1743 /* Note: a value of 2 * n is returned for the register Q<n>. */
1744 if (regtype
== REG_TYPE_NQ
)
1750 if (new_base
< base_reg
)
1751 base_reg
= new_base
;
1753 if (mask
& (setmask
<< new_base
))
1755 first_error (_("invalid register list"));
1759 if ((mask
>> new_base
) != 0 && ! warned
)
1761 as_tsktsk (_("register list not in ascending order"));
1765 mask
|= setmask
<< new_base
;
1768 if (*str
== '-') /* We have the start of a range expression */
1774 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1777 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1781 if (high_range
>= max_regs
)
1783 first_error (_("register out of range in list"));
1787 if (regtype
== REG_TYPE_NQ
)
1788 high_range
= high_range
+ 1;
1790 if (high_range
<= new_base
)
1792 inst
.error
= _("register range not in ascending order");
1796 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1798 if (mask
& (setmask
<< new_base
))
1800 inst
.error
= _("invalid register list");
1804 mask
|= setmask
<< new_base
;
1809 while (skip_past_comma (&str
) != FAIL
);
1813 /* Sanity check -- should have raised a parse error above. */
1814 if (count
== 0 || count
> max_regs
)
1819 /* Final test -- the registers must be consecutive. */
1821 for (i
= 0; i
< count
; i
++)
1823 if ((mask
& (1u << i
)) == 0)
1825 inst
.error
= _("non-contiguous register range");
1835 /* True if two alias types are the same. */
1838 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1846 if (a
->defined
!= b
->defined
)
1849 if ((a
->defined
& NTA_HASTYPE
) != 0
1850 && (a
->eltype
.type
!= b
->eltype
.type
1851 || a
->eltype
.size
!= b
->eltype
.size
))
1854 if ((a
->defined
& NTA_HASINDEX
) != 0
1855 && (a
->index
!= b
->index
))
1861 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1862 The base register is put in *PBASE.
1863 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1865 The register stride (minus one) is put in bit 4 of the return value.
1866 Bits [6:5] encode the list length (minus one).
1867 The type of the list elements is put in *ELTYPE, if non-NULL. */
1869 #define NEON_LANE(X) ((X) & 0xf)
1870 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1871 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1874 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1875 struct neon_type_el
*eltype
)
1882 int leading_brace
= 0;
1883 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1885 const char *const incr_error
= _("register stride must be 1 or 2");
1886 const char *const type_error
= _("mismatched element/structure types in list");
1887 struct neon_typed_alias firsttype
;
1889 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1894 struct neon_typed_alias atype
;
1895 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1899 first_error (_(reg_expected_msgs
[rtype
]));
1906 if (rtype
== REG_TYPE_NQ
)
1913 else if (reg_incr
== -1)
1915 reg_incr
= getreg
- base_reg
;
1916 if (reg_incr
< 1 || reg_incr
> 2)
1918 first_error (_(incr_error
));
1922 else if (getreg
!= base_reg
+ reg_incr
* count
)
1924 first_error (_(incr_error
));
1928 if (! neon_alias_types_same (&atype
, &firsttype
))
1930 first_error (_(type_error
));
1934 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1938 struct neon_typed_alias htype
;
1939 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1941 lane
= NEON_INTERLEAVE_LANES
;
1942 else if (lane
!= NEON_INTERLEAVE_LANES
)
1944 first_error (_(type_error
));
1949 else if (reg_incr
!= 1)
1951 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1955 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1958 first_error (_(reg_expected_msgs
[rtype
]));
1961 if (! neon_alias_types_same (&htype
, &firsttype
))
1963 first_error (_(type_error
));
1966 count
+= hireg
+ dregs
- getreg
;
1970 /* If we're using Q registers, we can't use [] or [n] syntax. */
1971 if (rtype
== REG_TYPE_NQ
)
1977 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1981 else if (lane
!= atype
.index
)
1983 first_error (_(type_error
));
1987 else if (lane
== -1)
1988 lane
= NEON_INTERLEAVE_LANES
;
1989 else if (lane
!= NEON_INTERLEAVE_LANES
)
1991 first_error (_(type_error
));
1996 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1998 /* No lane set by [x]. We must be interleaving structures. */
2000 lane
= NEON_INTERLEAVE_LANES
;
2003 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2004 || (count
> 1 && reg_incr
== -1))
2006 first_error (_("error parsing element/structure list"));
2010 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2012 first_error (_("expected }"));
2020 *eltype
= firsttype
.eltype
;
2025 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2028 /* Parse an explicit relocation suffix on an expression. This is
2029 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2030 arm_reloc_hsh contains no entries, so this function can only
2031 succeed if there is no () after the word. Returns -1 on error,
2032 BFD_RELOC_UNUSED if there wasn't any suffix. */
2034 parse_reloc (char **str
)
2036 struct reloc_entry
*r
;
2040 return BFD_RELOC_UNUSED
;
2045 while (*q
&& *q
!= ')' && *q
!= ',')
2050 if ((r
= (struct reloc_entry
*)
2051 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2058 /* Directives: register aliases. */
2060 static struct reg_entry
*
2061 insert_reg_alias (char *str
, int number
, int type
)
2063 struct reg_entry
*new_reg
;
2066 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2068 if (new_reg
->builtin
)
2069 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2071 /* Only warn about a redefinition if it's not defined as the
2073 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2074 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2079 name
= xstrdup (str
);
2080 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2082 new_reg
->name
= name
;
2083 new_reg
->number
= number
;
2084 new_reg
->type
= type
;
2085 new_reg
->builtin
= FALSE
;
2086 new_reg
->neon
= NULL
;
2088 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2095 insert_neon_reg_alias (char *str
, int number
, int type
,
2096 struct neon_typed_alias
*atype
)
2098 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2102 first_error (_("attempt to redefine typed alias"));
2108 reg
->neon
= (struct neon_typed_alias
*)
2109 xmalloc (sizeof (struct neon_typed_alias
));
2110 *reg
->neon
= *atype
;
2114 /* Look for the .req directive. This is of the form:
2116 new_register_name .req existing_register_name
2118 If we find one, or if it looks sufficiently like one that we want to
2119 handle any error here, return TRUE. Otherwise return FALSE. */
2122 create_register_alias (char * newname
, char *p
)
2124 struct reg_entry
*old
;
2125 char *oldname
, *nbuf
;
2128 /* The input scrubber ensures that whitespace after the mnemonic is
2129 collapsed to single spaces. */
2131 if (strncmp (oldname
, " .req ", 6) != 0)
2135 if (*oldname
== '\0')
2138 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2141 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2145 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2146 the desired alias name, and p points to its end. If not, then
2147 the desired alias name is in the global original_case_string. */
2148 #ifdef TC_CASE_SENSITIVE
2151 newname
= original_case_string
;
2152 nlen
= strlen (newname
);
2155 nbuf
= (char *) alloca (nlen
+ 1);
2156 memcpy (nbuf
, newname
, nlen
);
2159 /* Create aliases under the new name as stated; an all-lowercase
2160 version of the new name; and an all-uppercase version of the new
2162 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2164 for (p
= nbuf
; *p
; p
++)
2167 if (strncmp (nbuf
, newname
, nlen
))
2169 /* If this attempt to create an additional alias fails, do not bother
2170 trying to create the all-lower case alias. We will fail and issue
2171 a second, duplicate error message. This situation arises when the
2172 programmer does something like:
2175 The second .req creates the "Foo" alias but then fails to create
2176 the artificial FOO alias because it has already been created by the
2178 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2182 for (p
= nbuf
; *p
; p
++)
2185 if (strncmp (nbuf
, newname
, nlen
))
2186 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2192 /* Create a Neon typed/indexed register alias using directives, e.g.:
2197 These typed registers can be used instead of the types specified after the
2198 Neon mnemonic, so long as all operands given have types. Types can also be
2199 specified directly, e.g.:
2200 vadd d0.s32, d1.s32, d2.s32 */
2203 create_neon_reg_alias (char *newname
, char *p
)
2205 enum arm_reg_type basetype
;
2206 struct reg_entry
*basereg
;
2207 struct reg_entry mybasereg
;
2208 struct neon_type ntype
;
2209 struct neon_typed_alias typeinfo
;
2210 char *namebuf
, *nameend
;
2213 typeinfo
.defined
= 0;
2214 typeinfo
.eltype
.type
= NT_invtype
;
2215 typeinfo
.eltype
.size
= -1;
2216 typeinfo
.index
= -1;
2220 if (strncmp (p
, " .dn ", 5) == 0)
2221 basetype
= REG_TYPE_VFD
;
2222 else if (strncmp (p
, " .qn ", 5) == 0)
2223 basetype
= REG_TYPE_NQ
;
2232 basereg
= arm_reg_parse_multi (&p
);
2234 if (basereg
&& basereg
->type
!= basetype
)
2236 as_bad (_("bad type for register"));
2240 if (basereg
== NULL
)
2243 /* Try parsing as an integer. */
2244 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2245 if (exp
.X_op
!= O_constant
)
2247 as_bad (_("expression must be constant"));
2250 basereg
= &mybasereg
;
2251 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2257 typeinfo
= *basereg
->neon
;
2259 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2261 /* We got a type. */
2262 if (typeinfo
.defined
& NTA_HASTYPE
)
2264 as_bad (_("can't redefine the type of a register alias"));
2268 typeinfo
.defined
|= NTA_HASTYPE
;
2269 if (ntype
.elems
!= 1)
2271 as_bad (_("you must specify a single type only"));
2274 typeinfo
.eltype
= ntype
.el
[0];
2277 if (skip_past_char (&p
, '[') == SUCCESS
)
2280 /* We got a scalar index. */
2282 if (typeinfo
.defined
& NTA_HASINDEX
)
2284 as_bad (_("can't redefine the index of a scalar alias"));
2288 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2290 if (exp
.X_op
!= O_constant
)
2292 as_bad (_("scalar index must be constant"));
2296 typeinfo
.defined
|= NTA_HASINDEX
;
2297 typeinfo
.index
= exp
.X_add_number
;
2299 if (skip_past_char (&p
, ']') == FAIL
)
2301 as_bad (_("expecting ]"));
2306 namelen
= nameend
- newname
;
2307 namebuf
= (char *) alloca (namelen
+ 1);
2308 strncpy (namebuf
, newname
, namelen
);
2309 namebuf
[namelen
] = '\0';
2311 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2312 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2314 /* Insert name in all uppercase. */
2315 for (p
= namebuf
; *p
; p
++)
2318 if (strncmp (namebuf
, newname
, namelen
))
2319 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2320 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2322 /* Insert name in all lowercase. */
2323 for (p
= namebuf
; *p
; p
++)
2326 if (strncmp (namebuf
, newname
, namelen
))
2327 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2328 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2333 /* Should never be called, as .req goes between the alias and the
2334 register name, not at the beginning of the line. */
2337 s_req (int a ATTRIBUTE_UNUSED
)
2339 as_bad (_("invalid syntax for .req directive"));
2343 s_dn (int a ATTRIBUTE_UNUSED
)
2345 as_bad (_("invalid syntax for .dn directive"));
2349 s_qn (int a ATTRIBUTE_UNUSED
)
2351 as_bad (_("invalid syntax for .qn directive"));
2354 /* The .unreq directive deletes an alias which was previously defined
2355 by .req. For example:
2361 s_unreq (int a ATTRIBUTE_UNUSED
)
2366 name
= input_line_pointer
;
2368 while (*input_line_pointer
!= 0
2369 && *input_line_pointer
!= ' '
2370 && *input_line_pointer
!= '\n')
2371 ++input_line_pointer
;
2373 saved_char
= *input_line_pointer
;
2374 *input_line_pointer
= 0;
2377 as_bad (_("invalid syntax for .unreq directive"));
2380 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2384 as_bad (_("unknown register alias '%s'"), name
);
2385 else if (reg
->builtin
)
2386 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2393 hash_delete (arm_reg_hsh
, name
, FALSE
);
2394 free ((char *) reg
->name
);
2399 /* Also locate the all upper case and all lower case versions.
2400 Do not complain if we cannot find one or the other as it
2401 was probably deleted above. */
2403 nbuf
= strdup (name
);
2404 for (p
= nbuf
; *p
; p
++)
2406 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2409 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2410 free ((char *) reg
->name
);
2416 for (p
= nbuf
; *p
; p
++)
2418 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2421 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2422 free ((char *) reg
->name
);
2432 *input_line_pointer
= saved_char
;
2433 demand_empty_rest_of_line ();
2436 /* Directives: Instruction set selection. */
2439 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2440 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2441 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2442 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2444 /* Create a new mapping symbol for the transition to STATE. */
2447 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2450 const char * symname
;
2457 type
= BSF_NO_FLAGS
;
2461 type
= BSF_NO_FLAGS
;
2465 type
= BSF_NO_FLAGS
;
2471 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2472 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2477 THUMB_SET_FUNC (symbolP
, 0);
2478 ARM_SET_THUMB (symbolP
, 0);
2479 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2483 THUMB_SET_FUNC (symbolP
, 1);
2484 ARM_SET_THUMB (symbolP
, 1);
2485 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2493 /* Save the mapping symbols for future reference. Also check that
2494 we do not place two mapping symbols at the same offset within a
2495 frag. We'll handle overlap between frags in
2496 check_mapping_symbols.
2498 If .fill or other data filling directive generates zero sized data,
2499 the mapping symbol for the following code will have the same value
2500 as the one generated for the data filling directive. In this case,
2501 we replace the old symbol with the new one at the same address. */
2504 if (frag
->tc_frag_data
.first_map
!= NULL
)
2506 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2507 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2509 frag
->tc_frag_data
.first_map
= symbolP
;
2511 if (frag
->tc_frag_data
.last_map
!= NULL
)
2513 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2514 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2515 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2517 frag
->tc_frag_data
.last_map
= symbolP
;
2520 /* We must sometimes convert a region marked as code to data during
2521 code alignment, if an odd number of bytes have to be padded. The
2522 code mapping symbol is pushed to an aligned address. */
2525 insert_data_mapping_symbol (enum mstate state
,
2526 valueT value
, fragS
*frag
, offsetT bytes
)
2528 /* If there was already a mapping symbol, remove it. */
2529 if (frag
->tc_frag_data
.last_map
!= NULL
2530 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2532 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2536 know (frag
->tc_frag_data
.first_map
== symp
);
2537 frag
->tc_frag_data
.first_map
= NULL
;
2539 frag
->tc_frag_data
.last_map
= NULL
;
2540 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2543 make_mapping_symbol (MAP_DATA
, value
, frag
);
2544 make_mapping_symbol (state
, value
+ bytes
, frag
);
2547 static void mapping_state_2 (enum mstate state
, int max_chars
);
2549 /* Set the mapping state to STATE. Only call this when about to
2550 emit some STATE bytes to the file. */
2553 mapping_state (enum mstate state
)
2555 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2557 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2559 if (mapstate
== state
)
2560 /* The mapping symbol has already been emitted.
2561 There is nothing else to do. */
2563 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2564 /* This case will be evaluated later in the next else. */
2566 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2567 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2569 /* Only add the symbol if the offset is > 0:
2570 if we're at the first frag, check it's size > 0;
2571 if we're not at the first frag, then for sure
2572 the offset is > 0. */
2573 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2574 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2577 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2580 mapping_state_2 (state
, 0);
2584 /* Same as mapping_state, but MAX_CHARS bytes have already been
2585 allocated. Put the mapping symbol that far back. */
2588 mapping_state_2 (enum mstate state
, int max_chars
)
2590 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2592 if (!SEG_NORMAL (now_seg
))
2595 if (mapstate
== state
)
2596 /* The mapping symbol has already been emitted.
2597 There is nothing else to do. */
2600 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2601 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2604 #define mapping_state(x) ((void)0)
2605 #define mapping_state_2(x, y) ((void)0)
2608 /* Find the real, Thumb encoded start of a Thumb function. */
2612 find_real_start (symbolS
* symbolP
)
2615 const char * name
= S_GET_NAME (symbolP
);
2616 symbolS
* new_target
;
2618 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2619 #define STUB_NAME ".real_start_of"
2624 /* The compiler may generate BL instructions to local labels because
2625 it needs to perform a branch to a far away location. These labels
2626 do not have a corresponding ".real_start_of" label. We check
2627 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2628 the ".real_start_of" convention for nonlocal branches. */
2629 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2632 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2633 new_target
= symbol_find (real_start
);
2635 if (new_target
== NULL
)
2637 as_warn (_("Failed to find real start of function: %s\n"), name
);
2638 new_target
= symbolP
;
2646 opcode_select (int width
)
2653 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2654 as_bad (_("selected processor does not support THUMB opcodes"));
2657 /* No need to force the alignment, since we will have been
2658 coming from ARM mode, which is word-aligned. */
2659 record_alignment (now_seg
, 1);
2666 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2667 as_bad (_("selected processor does not support ARM opcodes"));
2672 frag_align (2, 0, 0);
2674 record_alignment (now_seg
, 1);
2679 as_bad (_("invalid instruction size selected (%d)"), width
);
2684 s_arm (int ignore ATTRIBUTE_UNUSED
)
2687 demand_empty_rest_of_line ();
2691 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2694 demand_empty_rest_of_line ();
2698 s_code (int unused ATTRIBUTE_UNUSED
)
2702 temp
= get_absolute_expression ();
2707 opcode_select (temp
);
2711 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2716 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2718 /* If we are not already in thumb mode go into it, EVEN if
2719 the target processor does not support thumb instructions.
2720 This is used by gcc/config/arm/lib1funcs.asm for example
2721 to compile interworking support functions even if the
2722 target processor should not support interworking. */
2726 record_alignment (now_seg
, 1);
2729 demand_empty_rest_of_line ();
2733 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2737 /* The following label is the name/address of the start of a Thumb function.
2738 We need to know this for the interworking support. */
2739 label_is_thumb_function_name
= TRUE
;
2742 /* Perform a .set directive, but also mark the alias as
2743 being a thumb function. */
2746 s_thumb_set (int equiv
)
2748 /* XXX the following is a duplicate of the code for s_set() in read.c
2749 We cannot just call that code as we need to get at the symbol that
2756 /* Especial apologies for the random logic:
2757 This just grew, and could be parsed much more simply!
2759 name
= input_line_pointer
;
2760 delim
= get_symbol_end ();
2761 end_name
= input_line_pointer
;
2764 if (*input_line_pointer
!= ',')
2767 as_bad (_("expected comma after name \"%s\""), name
);
2769 ignore_rest_of_line ();
2773 input_line_pointer
++;
2776 if (name
[0] == '.' && name
[1] == '\0')
2778 /* XXX - this should not happen to .thumb_set. */
2782 if ((symbolP
= symbol_find (name
)) == NULL
2783 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2786 /* When doing symbol listings, play games with dummy fragments living
2787 outside the normal fragment chain to record the file and line info
2789 if (listing
& LISTING_SYMBOLS
)
2791 extern struct list_info_struct
* listing_tail
;
2792 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2794 memset (dummy_frag
, 0, sizeof (fragS
));
2795 dummy_frag
->fr_type
= rs_fill
;
2796 dummy_frag
->line
= listing_tail
;
2797 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2798 dummy_frag
->fr_symbol
= symbolP
;
2802 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2805 /* "set" symbols are local unless otherwise specified. */
2806 SF_SET_LOCAL (symbolP
);
2807 #endif /* OBJ_COFF */
2808 } /* Make a new symbol. */
2810 symbol_table_insert (symbolP
);
2815 && S_IS_DEFINED (symbolP
)
2816 && S_GET_SEGMENT (symbolP
) != reg_section
)
2817 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2819 pseudo_set (symbolP
);
2821 demand_empty_rest_of_line ();
2823 /* XXX Now we come to the Thumb specific bit of code. */
2825 THUMB_SET_FUNC (symbolP
, 1);
2826 ARM_SET_THUMB (symbolP
, 1);
2827 #if defined OBJ_ELF || defined OBJ_COFF
2828 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2832 /* Directives: Mode selection. */
2834 /* .syntax [unified|divided] - choose the new unified syntax
2835 (same for Arm and Thumb encoding, modulo slight differences in what
2836 can be represented) or the old divergent syntax for each mode. */
2838 s_syntax (int unused ATTRIBUTE_UNUSED
)
2842 name
= input_line_pointer
;
2843 delim
= get_symbol_end ();
2845 if (!strcasecmp (name
, "unified"))
2846 unified_syntax
= TRUE
;
2847 else if (!strcasecmp (name
, "divided"))
2848 unified_syntax
= FALSE
;
2851 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2854 *input_line_pointer
= delim
;
2855 demand_empty_rest_of_line ();
2858 /* Directives: sectioning and alignment. */
2860 /* Same as s_align_ptwo but align 0 => align 2. */
2863 s_align (int unused ATTRIBUTE_UNUSED
)
2868 long max_alignment
= 15;
2870 temp
= get_absolute_expression ();
2871 if (temp
> max_alignment
)
2872 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2875 as_bad (_("alignment negative. 0 assumed."));
2879 if (*input_line_pointer
== ',')
2881 input_line_pointer
++;
2882 temp_fill
= get_absolute_expression ();
2894 /* Only make a frag if we HAVE to. */
2895 if (temp
&& !need_pass_2
)
2897 if (!fill_p
&& subseg_text_p (now_seg
))
2898 frag_align_code (temp
, 0);
2900 frag_align (temp
, (int) temp_fill
, 0);
2902 demand_empty_rest_of_line ();
2904 record_alignment (now_seg
, temp
);
2908 s_bss (int ignore ATTRIBUTE_UNUSED
)
2910 /* We don't support putting frags in the BSS segment, we fake it by
2911 marking in_bss, then looking at s_skip for clues. */
2912 subseg_set (bss_section
, 0);
2913 demand_empty_rest_of_line ();
2915 #ifdef md_elf_section_change_hook
2916 md_elf_section_change_hook ();
2921 s_even (int ignore ATTRIBUTE_UNUSED
)
2923 /* Never make frag if expect extra pass. */
2925 frag_align (1, 0, 0);
2927 record_alignment (now_seg
, 1);
2929 demand_empty_rest_of_line ();
2932 /* Directives: Literal pools. */
2934 static literal_pool
*
2935 find_literal_pool (void)
2937 literal_pool
* pool
;
2939 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2941 if (pool
->section
== now_seg
2942 && pool
->sub_section
== now_subseg
)
2949 static literal_pool
*
2950 find_or_make_literal_pool (void)
2952 /* Next literal pool ID number. */
2953 static unsigned int latest_pool_num
= 1;
2954 literal_pool
* pool
;
2956 pool
= find_literal_pool ();
2960 /* Create a new pool. */
2961 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2965 pool
->next_free_entry
= 0;
2966 pool
->section
= now_seg
;
2967 pool
->sub_section
= now_subseg
;
2968 pool
->next
= list_of_pools
;
2969 pool
->symbol
= NULL
;
2971 /* Add it to the list. */
2972 list_of_pools
= pool
;
2975 /* New pools, and emptied pools, will have a NULL symbol. */
2976 if (pool
->symbol
== NULL
)
2978 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2979 (valueT
) 0, &zero_address_frag
);
2980 pool
->id
= latest_pool_num
++;
2987 /* Add the literal in the global 'inst'
2988 structure to the relevant literal pool. */
2991 add_to_lit_pool (void)
2993 literal_pool
* pool
;
2996 pool
= find_or_make_literal_pool ();
2998 /* Check if this literal value is already in the pool. */
2999 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3001 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3002 && (inst
.reloc
.exp
.X_op
== O_constant
)
3003 && (pool
->literals
[entry
].X_add_number
3004 == inst
.reloc
.exp
.X_add_number
)
3005 && (pool
->literals
[entry
].X_unsigned
3006 == inst
.reloc
.exp
.X_unsigned
))
3009 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3010 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3011 && (pool
->literals
[entry
].X_add_number
3012 == inst
.reloc
.exp
.X_add_number
)
3013 && (pool
->literals
[entry
].X_add_symbol
3014 == inst
.reloc
.exp
.X_add_symbol
)
3015 && (pool
->literals
[entry
].X_op_symbol
3016 == inst
.reloc
.exp
.X_op_symbol
))
3020 /* Do we need to create a new entry? */
3021 if (entry
== pool
->next_free_entry
)
3023 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3025 inst
.error
= _("literal pool overflow");
3029 pool
->literals
[entry
] = inst
.reloc
.exp
;
3030 pool
->next_free_entry
+= 1;
3033 inst
.reloc
.exp
.X_op
= O_symbol
;
3034 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3035 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3040 /* Can't use symbol_new here, so have to create a symbol and then at
3041 a later date assign it a value. Thats what these functions do. */
3044 symbol_locate (symbolS
* symbolP
,
3045 const char * name
, /* It is copied, the caller can modify. */
3046 segT segment
, /* Segment identifier (SEG_<something>). */
3047 valueT valu
, /* Symbol value. */
3048 fragS
* frag
) /* Associated fragment. */
3050 unsigned int name_length
;
3051 char * preserved_copy_of_name
;
3053 name_length
= strlen (name
) + 1; /* +1 for \0. */
3054 obstack_grow (¬es
, name
, name_length
);
3055 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3057 #ifdef tc_canonicalize_symbol_name
3058 preserved_copy_of_name
=
3059 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3062 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3064 S_SET_SEGMENT (symbolP
, segment
);
3065 S_SET_VALUE (symbolP
, valu
);
3066 symbol_clear_list_pointers (symbolP
);
3068 symbol_set_frag (symbolP
, frag
);
3070 /* Link to end of symbol chain. */
3072 extern int symbol_table_frozen
;
3074 if (symbol_table_frozen
)
3078 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3080 obj_symbol_new_hook (symbolP
);
3082 #ifdef tc_symbol_new_hook
3083 tc_symbol_new_hook (symbolP
);
3087 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3088 #endif /* DEBUG_SYMS */
3093 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3096 literal_pool
* pool
;
3099 pool
= find_literal_pool ();
3101 || pool
->symbol
== NULL
3102 || pool
->next_free_entry
== 0)
3105 mapping_state (MAP_DATA
);
3107 /* Align pool as you have word accesses.
3108 Only make a frag if we have to. */
3110 frag_align (2, 0, 0);
3112 record_alignment (now_seg
, 2);
3114 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3116 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3117 (valueT
) frag_now_fix (), frag_now
);
3118 symbol_table_insert (pool
->symbol
);
3120 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3122 #if defined OBJ_COFF || defined OBJ_ELF
3123 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3126 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3127 /* First output the expression in the instruction to the pool. */
3128 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3130 /* Mark the pool as empty. */
3131 pool
->next_free_entry
= 0;
3132 pool
->symbol
= NULL
;
3136 /* Forward declarations for functions below, in the MD interface
3138 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3139 static valueT
create_unwind_entry (int);
3140 static void start_unwind_section (const segT
, int);
3141 static void add_unwind_opcode (valueT
, int);
3142 static void flush_pending_unwind (void);
3144 /* Directives: Data. */
3147 s_arm_elf_cons (int nbytes
)
3151 #ifdef md_flush_pending_output
3152 md_flush_pending_output ();
3155 if (is_it_end_of_statement ())
3157 demand_empty_rest_of_line ();
3161 #ifdef md_cons_align
3162 md_cons_align (nbytes
);
3165 mapping_state (MAP_DATA
);
3169 char *base
= input_line_pointer
;
3173 if (exp
.X_op
!= O_symbol
)
3174 emit_expr (&exp
, (unsigned int) nbytes
);
3177 char *before_reloc
= input_line_pointer
;
3178 reloc
= parse_reloc (&input_line_pointer
);
3181 as_bad (_("unrecognized relocation suffix"));
3182 ignore_rest_of_line ();
3185 else if (reloc
== BFD_RELOC_UNUSED
)
3186 emit_expr (&exp
, (unsigned int) nbytes
);
3189 reloc_howto_type
*howto
= (reloc_howto_type
*)
3190 bfd_reloc_type_lookup (stdoutput
,
3191 (bfd_reloc_code_real_type
) reloc
);
3192 int size
= bfd_get_reloc_size (howto
);
3194 if (reloc
== BFD_RELOC_ARM_PLT32
)
3196 as_bad (_("(plt) is only valid on branch targets"));
3197 reloc
= BFD_RELOC_UNUSED
;
3202 as_bad (_("%s relocations do not fit in %d bytes"),
3203 howto
->name
, nbytes
);
3206 /* We've parsed an expression stopping at O_symbol.
3207 But there may be more expression left now that we
3208 have parsed the relocation marker. Parse it again.
3209 XXX Surely there is a cleaner way to do this. */
3210 char *p
= input_line_pointer
;
3212 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3213 memcpy (save_buf
, base
, input_line_pointer
- base
);
3214 memmove (base
+ (input_line_pointer
- before_reloc
),
3215 base
, before_reloc
- base
);
3217 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3219 memcpy (base
, save_buf
, p
- base
);
3221 offset
= nbytes
- size
;
3222 p
= frag_more ((int) nbytes
);
3223 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3224 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3229 while (*input_line_pointer
++ == ',');
3231 /* Put terminator back into stream. */
3232 input_line_pointer
--;
3233 demand_empty_rest_of_line ();
3236 /* Emit an expression containing a 32-bit thumb instruction.
3237 Implementation based on put_thumb32_insn. */
3240 emit_thumb32_expr (expressionS
* exp
)
3242 expressionS exp_high
= *exp
;
3244 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3245 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3246 exp
->X_add_number
&= 0xffff;
3247 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3250 /* Guess the instruction size based on the opcode. */
3253 thumb_insn_size (int opcode
)
3255 if ((unsigned int) opcode
< 0xe800u
)
3257 else if ((unsigned int) opcode
>= 0xe8000000u
)
3264 emit_insn (expressionS
*exp
, int nbytes
)
3268 if (exp
->X_op
== O_constant
)
3273 size
= thumb_insn_size (exp
->X_add_number
);
3277 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3279 as_bad (_(".inst.n operand too big. "\
3280 "Use .inst.w instead"));
3285 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3286 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3288 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3290 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3291 emit_thumb32_expr (exp
);
3293 emit_expr (exp
, (unsigned int) size
);
3295 it_fsm_post_encode ();
3299 as_bad (_("cannot determine Thumb instruction size. " \
3300 "Use .inst.n/.inst.w instead"));
3303 as_bad (_("constant expression required"));
3308 /* Like s_arm_elf_cons but do not use md_cons_align and
3309 set the mapping state to MAP_ARM/MAP_THUMB. */
3312 s_arm_elf_inst (int nbytes
)
3314 if (is_it_end_of_statement ())
3316 demand_empty_rest_of_line ();
3320 /* Calling mapping_state () here will not change ARM/THUMB,
3321 but will ensure not to be in DATA state. */
3324 mapping_state (MAP_THUMB
);
3329 as_bad (_("width suffixes are invalid in ARM mode"));
3330 ignore_rest_of_line ();
3336 mapping_state (MAP_ARM
);
3345 if (! emit_insn (& exp
, nbytes
))
3347 ignore_rest_of_line ();
3351 while (*input_line_pointer
++ == ',');
3353 /* Put terminator back into stream. */
3354 input_line_pointer
--;
3355 demand_empty_rest_of_line ();
3358 /* Parse a .rel31 directive. */
3361 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3368 if (*input_line_pointer
== '1')
3369 highbit
= 0x80000000;
3370 else if (*input_line_pointer
!= '0')
3371 as_bad (_("expected 0 or 1"));
3373 input_line_pointer
++;
3374 if (*input_line_pointer
!= ',')
3375 as_bad (_("missing comma"));
3376 input_line_pointer
++;
3378 #ifdef md_flush_pending_output
3379 md_flush_pending_output ();
3382 #ifdef md_cons_align
3386 mapping_state (MAP_DATA
);
3391 md_number_to_chars (p
, highbit
, 4);
3392 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3393 BFD_RELOC_ARM_PREL31
);
3395 demand_empty_rest_of_line ();
3398 /* Directives: AEABI stack-unwind tables. */
3400 /* Parse an unwind_fnstart directive. Simply records the current location. */
3403 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3405 demand_empty_rest_of_line ();
3406 if (unwind
.proc_start
)
3408 as_bad (_("duplicate .fnstart directive"));
3412 /* Mark the start of the function. */
3413 unwind
.proc_start
= expr_build_dot ();
3415 /* Reset the rest of the unwind info. */
3416 unwind
.opcode_count
= 0;
3417 unwind
.table_entry
= NULL
;
3418 unwind
.personality_routine
= NULL
;
3419 unwind
.personality_index
= -1;
3420 unwind
.frame_size
= 0;
3421 unwind
.fp_offset
= 0;
3422 unwind
.fp_reg
= REG_SP
;
3424 unwind
.sp_restored
= 0;
3428 /* Parse a handlerdata directive. Creates the exception handling table entry
3429 for the function. */
3432 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3434 demand_empty_rest_of_line ();
3435 if (!unwind
.proc_start
)
3436 as_bad (MISSING_FNSTART
);
3438 if (unwind
.table_entry
)
3439 as_bad (_("duplicate .handlerdata directive"));
3441 create_unwind_entry (1);
3444 /* Parse an unwind_fnend directive. Generates the index table entry. */
3447 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3452 unsigned int marked_pr_dependency
;
3454 demand_empty_rest_of_line ();
3456 if (!unwind
.proc_start
)
3458 as_bad (_(".fnend directive without .fnstart"));
3462 /* Add eh table entry. */
3463 if (unwind
.table_entry
== NULL
)
3464 val
= create_unwind_entry (0);
3468 /* Add index table entry. This is two words. */
3469 start_unwind_section (unwind
.saved_seg
, 1);
3470 frag_align (2, 0, 0);
3471 record_alignment (now_seg
, 2);
3473 ptr
= frag_more (8);
3474 where
= frag_now_fix () - 8;
3476 /* Self relative offset of the function start. */
3477 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3478 BFD_RELOC_ARM_PREL31
);
3480 /* Indicate dependency on EHABI-defined personality routines to the
3481 linker, if it hasn't been done already. */
3482 marked_pr_dependency
3483 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3484 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3485 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3487 static const char *const name
[] =
3489 "__aeabi_unwind_cpp_pr0",
3490 "__aeabi_unwind_cpp_pr1",
3491 "__aeabi_unwind_cpp_pr2"
3493 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3494 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3495 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3496 |= 1 << unwind
.personality_index
;
3500 /* Inline exception table entry. */
3501 md_number_to_chars (ptr
+ 4, val
, 4);
3503 /* Self relative offset of the table entry. */
3504 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3505 BFD_RELOC_ARM_PREL31
);
3507 /* Restore the original section. */
3508 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3510 unwind
.proc_start
= NULL
;
3514 /* Parse an unwind_cantunwind directive. */
3517 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3519 demand_empty_rest_of_line ();
3520 if (!unwind
.proc_start
)
3521 as_bad (MISSING_FNSTART
);
3523 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3524 as_bad (_("personality routine specified for cantunwind frame"));
3526 unwind
.personality_index
= -2;
3530 /* Parse a personalityindex directive. */
3533 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3537 if (!unwind
.proc_start
)
3538 as_bad (MISSING_FNSTART
);
3540 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3541 as_bad (_("duplicate .personalityindex directive"));
3545 if (exp
.X_op
!= O_constant
3546 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3548 as_bad (_("bad personality routine number"));
3549 ignore_rest_of_line ();
3553 unwind
.personality_index
= exp
.X_add_number
;
3555 demand_empty_rest_of_line ();
3559 /* Parse a personality directive. */
3562 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3566 if (!unwind
.proc_start
)
3567 as_bad (MISSING_FNSTART
);
3569 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3570 as_bad (_("duplicate .personality directive"));
3572 name
= input_line_pointer
;
3573 c
= get_symbol_end ();
3574 p
= input_line_pointer
;
3575 unwind
.personality_routine
= symbol_find_or_make (name
);
3577 demand_empty_rest_of_line ();
3581 /* Parse a directive saving core registers. */
3584 s_arm_unwind_save_core (void)
3590 range
= parse_reg_list (&input_line_pointer
);
3593 as_bad (_("expected register list"));
3594 ignore_rest_of_line ();
3598 demand_empty_rest_of_line ();
3600 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3601 into .unwind_save {..., sp...}. We aren't bothered about the value of
3602 ip because it is clobbered by calls. */
3603 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3604 && (range
& 0x3000) == 0x1000)
3606 unwind
.opcode_count
--;
3607 unwind
.sp_restored
= 0;
3608 range
= (range
| 0x2000) & ~0x1000;
3609 unwind
.pending_offset
= 0;
3615 /* See if we can use the short opcodes. These pop a block of up to 8
3616 registers starting with r4, plus maybe r14. */
3617 for (n
= 0; n
< 8; n
++)
3619 /* Break at the first non-saved register. */
3620 if ((range
& (1 << (n
+ 4))) == 0)
3623 /* See if there are any other bits set. */
3624 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3626 /* Use the long form. */
3627 op
= 0x8000 | ((range
>> 4) & 0xfff);
3628 add_unwind_opcode (op
, 2);
3632 /* Use the short form. */
3634 op
= 0xa8; /* Pop r14. */
3636 op
= 0xa0; /* Do not pop r14. */
3638 add_unwind_opcode (op
, 1);
3645 op
= 0xb100 | (range
& 0xf);
3646 add_unwind_opcode (op
, 2);
3649 /* Record the number of bytes pushed. */
3650 for (n
= 0; n
< 16; n
++)
3652 if (range
& (1 << n
))
3653 unwind
.frame_size
+= 4;
3658 /* Parse a directive saving FPA registers. */
3661 s_arm_unwind_save_fpa (int reg
)
3667 /* Get Number of registers to transfer. */
3668 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3671 exp
.X_op
= O_illegal
;
3673 if (exp
.X_op
!= O_constant
)
3675 as_bad (_("expected , <constant>"));
3676 ignore_rest_of_line ();
3680 num_regs
= exp
.X_add_number
;
3682 if (num_regs
< 1 || num_regs
> 4)
3684 as_bad (_("number of registers must be in the range [1:4]"));
3685 ignore_rest_of_line ();
3689 demand_empty_rest_of_line ();
3694 op
= 0xb4 | (num_regs
- 1);
3695 add_unwind_opcode (op
, 1);
3700 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3701 add_unwind_opcode (op
, 2);
3703 unwind
.frame_size
+= num_regs
* 12;
3707 /* Parse a directive saving VFP registers for ARMv6 and above. */
3710 s_arm_unwind_save_vfp_armv6 (void)
3715 int num_vfpv3_regs
= 0;
3716 int num_regs_below_16
;
3718 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3721 as_bad (_("expected register list"));
3722 ignore_rest_of_line ();
3726 demand_empty_rest_of_line ();
3728 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3729 than FSTMX/FLDMX-style ones). */
3731 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3733 num_vfpv3_regs
= count
;
3734 else if (start
+ count
> 16)
3735 num_vfpv3_regs
= start
+ count
- 16;
3737 if (num_vfpv3_regs
> 0)
3739 int start_offset
= start
> 16 ? start
- 16 : 0;
3740 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3741 add_unwind_opcode (op
, 2);
3744 /* Generate opcode for registers numbered in the range 0 .. 15. */
3745 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3746 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3747 if (num_regs_below_16
> 0)
3749 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3750 add_unwind_opcode (op
, 2);
3753 unwind
.frame_size
+= count
* 8;
3757 /* Parse a directive saving VFP registers for pre-ARMv6. */
3760 s_arm_unwind_save_vfp (void)
3766 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3769 as_bad (_("expected register list"));
3770 ignore_rest_of_line ();
3774 demand_empty_rest_of_line ();
3779 op
= 0xb8 | (count
- 1);
3780 add_unwind_opcode (op
, 1);
3785 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3786 add_unwind_opcode (op
, 2);
3788 unwind
.frame_size
+= count
* 8 + 4;
3792 /* Parse a directive saving iWMMXt data registers. */
3795 s_arm_unwind_save_mmxwr (void)
3803 if (*input_line_pointer
== '{')
3804 input_line_pointer
++;
3808 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3812 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3817 as_tsktsk (_("register list not in ascending order"));
3820 if (*input_line_pointer
== '-')
3822 input_line_pointer
++;
3823 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3826 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3829 else if (reg
>= hi_reg
)
3831 as_bad (_("bad register range"));
3834 for (; reg
< hi_reg
; reg
++)
3838 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3840 if (*input_line_pointer
== '}')
3841 input_line_pointer
++;
3843 demand_empty_rest_of_line ();
3845 /* Generate any deferred opcodes because we're going to be looking at
3847 flush_pending_unwind ();
3849 for (i
= 0; i
< 16; i
++)
3851 if (mask
& (1 << i
))
3852 unwind
.frame_size
+= 8;
3855 /* Attempt to combine with a previous opcode. We do this because gcc
3856 likes to output separate unwind directives for a single block of
3858 if (unwind
.opcode_count
> 0)
3860 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3861 if ((i
& 0xf8) == 0xc0)
3864 /* Only merge if the blocks are contiguous. */
3867 if ((mask
& 0xfe00) == (1 << 9))
3869 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3870 unwind
.opcode_count
--;
3873 else if (i
== 6 && unwind
.opcode_count
>= 2)
3875 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3879 op
= 0xffff << (reg
- 1);
3881 && ((mask
& op
) == (1u << (reg
- 1))))
3883 op
= (1 << (reg
+ i
+ 1)) - 1;
3884 op
&= ~((1 << reg
) - 1);
3886 unwind
.opcode_count
-= 2;
3893 /* We want to generate opcodes in the order the registers have been
3894 saved, ie. descending order. */
3895 for (reg
= 15; reg
>= -1; reg
--)
3897 /* Save registers in blocks. */
3899 || !(mask
& (1 << reg
)))
3901 /* We found an unsaved reg. Generate opcodes to save the
3908 op
= 0xc0 | (hi_reg
- 10);
3909 add_unwind_opcode (op
, 1);
3914 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3915 add_unwind_opcode (op
, 2);
3924 ignore_rest_of_line ();
3928 s_arm_unwind_save_mmxwcg (void)
3935 if (*input_line_pointer
== '{')
3936 input_line_pointer
++;
3940 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3944 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3950 as_tsktsk (_("register list not in ascending order"));
3953 if (*input_line_pointer
== '-')
3955 input_line_pointer
++;
3956 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3959 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3962 else if (reg
>= hi_reg
)
3964 as_bad (_("bad register range"));
3967 for (; reg
< hi_reg
; reg
++)
3971 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3973 if (*input_line_pointer
== '}')
3974 input_line_pointer
++;
3976 demand_empty_rest_of_line ();
3978 /* Generate any deferred opcodes because we're going to be looking at
3980 flush_pending_unwind ();
3982 for (reg
= 0; reg
< 16; reg
++)
3984 if (mask
& (1 << reg
))
3985 unwind
.frame_size
+= 4;
3988 add_unwind_opcode (op
, 2);
3991 ignore_rest_of_line ();
3995 /* Parse an unwind_save directive.
3996 If the argument is non-zero, this is a .vsave directive. */
3999 s_arm_unwind_save (int arch_v6
)
4002 struct reg_entry
*reg
;
4003 bfd_boolean had_brace
= FALSE
;
4005 if (!unwind
.proc_start
)
4006 as_bad (MISSING_FNSTART
);
4008 /* Figure out what sort of save we have. */
4009 peek
= input_line_pointer
;
4017 reg
= arm_reg_parse_multi (&peek
);
4021 as_bad (_("register expected"));
4022 ignore_rest_of_line ();
4031 as_bad (_("FPA .unwind_save does not take a register list"));
4032 ignore_rest_of_line ();
4035 input_line_pointer
= peek
;
4036 s_arm_unwind_save_fpa (reg
->number
);
4039 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4042 s_arm_unwind_save_vfp_armv6 ();
4044 s_arm_unwind_save_vfp ();
4046 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4047 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4050 as_bad (_(".unwind_save does not support this kind of register"));
4051 ignore_rest_of_line ();
4056 /* Parse an unwind_movsp directive. */
4059 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4065 if (!unwind
.proc_start
)
4066 as_bad (MISSING_FNSTART
);
4068 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4071 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4072 ignore_rest_of_line ();
4076 /* Optional constant. */
4077 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4079 if (immediate_for_directive (&offset
) == FAIL
)
4085 demand_empty_rest_of_line ();
4087 if (reg
== REG_SP
|| reg
== REG_PC
)
4089 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4093 if (unwind
.fp_reg
!= REG_SP
)
4094 as_bad (_("unexpected .unwind_movsp directive"));
4096 /* Generate opcode to restore the value. */
4098 add_unwind_opcode (op
, 1);
4100 /* Record the information for later. */
4101 unwind
.fp_reg
= reg
;
4102 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4103 unwind
.sp_restored
= 1;
4106 /* Parse an unwind_pad directive. */
4109 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4113 if (!unwind
.proc_start
)
4114 as_bad (MISSING_FNSTART
);
4116 if (immediate_for_directive (&offset
) == FAIL
)
4121 as_bad (_("stack increment must be multiple of 4"));
4122 ignore_rest_of_line ();
4126 /* Don't generate any opcodes, just record the details for later. */
4127 unwind
.frame_size
+= offset
;
4128 unwind
.pending_offset
+= offset
;
4130 demand_empty_rest_of_line ();
4133 /* Parse an unwind_setfp directive. */
4136 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4142 if (!unwind
.proc_start
)
4143 as_bad (MISSING_FNSTART
);
4145 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4146 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4149 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4151 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4153 as_bad (_("expected <reg>, <reg>"));
4154 ignore_rest_of_line ();
4158 /* Optional constant. */
4159 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4161 if (immediate_for_directive (&offset
) == FAIL
)
4167 demand_empty_rest_of_line ();
4169 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4171 as_bad (_("register must be either sp or set by a previous"
4172 "unwind_movsp directive"));
4176 /* Don't generate any opcodes, just record the information for later. */
4177 unwind
.fp_reg
= fp_reg
;
4179 if (sp_reg
== REG_SP
)
4180 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4182 unwind
.fp_offset
-= offset
;
4185 /* Parse an unwind_raw directive. */
4188 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4191 /* This is an arbitrary limit. */
4192 unsigned char op
[16];
4195 if (!unwind
.proc_start
)
4196 as_bad (MISSING_FNSTART
);
4199 if (exp
.X_op
== O_constant
4200 && skip_past_comma (&input_line_pointer
) != FAIL
)
4202 unwind
.frame_size
+= exp
.X_add_number
;
4206 exp
.X_op
= O_illegal
;
4208 if (exp
.X_op
!= O_constant
)
4210 as_bad (_("expected <offset>, <opcode>"));
4211 ignore_rest_of_line ();
4217 /* Parse the opcode. */
4222 as_bad (_("unwind opcode too long"));
4223 ignore_rest_of_line ();
4225 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4227 as_bad (_("invalid unwind opcode"));
4228 ignore_rest_of_line ();
4231 op
[count
++] = exp
.X_add_number
;
4233 /* Parse the next byte. */
4234 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4240 /* Add the opcode bytes in reverse order. */
4242 add_unwind_opcode (op
[count
], 1);
4244 demand_empty_rest_of_line ();
4248 /* Parse a .eabi_attribute directive. */
4251 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4253 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4255 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4256 attributes_set_explicitly
[tag
] = 1;
4258 #endif /* OBJ_ELF */
4260 static void s_arm_arch (int);
4261 static void s_arm_object_arch (int);
4262 static void s_arm_cpu (int);
4263 static void s_arm_fpu (int);
4268 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4275 if (exp
.X_op
== O_symbol
)
4276 exp
.X_op
= O_secrel
;
4278 emit_expr (&exp
, 4);
4280 while (*input_line_pointer
++ == ',');
4282 input_line_pointer
--;
4283 demand_empty_rest_of_line ();
4287 /* This table describes all the machine specific pseudo-ops the assembler
4288 has to support. The fields are:
4289 pseudo-op name without dot
4290 function to call to execute this pseudo-op
4291 Integer arg to pass to the function. */
4293 const pseudo_typeS md_pseudo_table
[] =
4295 /* Never called because '.req' does not start a line. */
4296 { "req", s_req
, 0 },
4297 /* Following two are likewise never called. */
4300 { "unreq", s_unreq
, 0 },
4301 { "bss", s_bss
, 0 },
4302 { "align", s_align
, 0 },
4303 { "arm", s_arm
, 0 },
4304 { "thumb", s_thumb
, 0 },
4305 { "code", s_code
, 0 },
4306 { "force_thumb", s_force_thumb
, 0 },
4307 { "thumb_func", s_thumb_func
, 0 },
4308 { "thumb_set", s_thumb_set
, 0 },
4309 { "even", s_even
, 0 },
4310 { "ltorg", s_ltorg
, 0 },
4311 { "pool", s_ltorg
, 0 },
4312 { "syntax", s_syntax
, 0 },
4313 { "cpu", s_arm_cpu
, 0 },
4314 { "arch", s_arm_arch
, 0 },
4315 { "object_arch", s_arm_object_arch
, 0 },
4316 { "fpu", s_arm_fpu
, 0 },
4318 { "word", s_arm_elf_cons
, 4 },
4319 { "long", s_arm_elf_cons
, 4 },
4320 { "inst.n", s_arm_elf_inst
, 2 },
4321 { "inst.w", s_arm_elf_inst
, 4 },
4322 { "inst", s_arm_elf_inst
, 0 },
4323 { "rel31", s_arm_rel31
, 0 },
4324 { "fnstart", s_arm_unwind_fnstart
, 0 },
4325 { "fnend", s_arm_unwind_fnend
, 0 },
4326 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4327 { "personality", s_arm_unwind_personality
, 0 },
4328 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4329 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4330 { "save", s_arm_unwind_save
, 0 },
4331 { "vsave", s_arm_unwind_save
, 1 },
4332 { "movsp", s_arm_unwind_movsp
, 0 },
4333 { "pad", s_arm_unwind_pad
, 0 },
4334 { "setfp", s_arm_unwind_setfp
, 0 },
4335 { "unwind_raw", s_arm_unwind_raw
, 0 },
4336 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4340 /* These are used for dwarf. */
4344 /* These are used for dwarf2. */
4345 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4346 { "loc", dwarf2_directive_loc
, 0 },
4347 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4349 { "extend", float_cons
, 'x' },
4350 { "ldouble", float_cons
, 'x' },
4351 { "packed", float_cons
, 'p' },
4353 {"secrel32", pe_directive_secrel
, 0},
4358 /* Parser functions used exclusively in instruction operands. */
4360 /* Generic immediate-value read function for use in insn parsing.
4361 STR points to the beginning of the immediate (the leading #);
4362 VAL receives the value; if the value is outside [MIN, MAX]
4363 issue an error. PREFIX_OPT is true if the immediate prefix is
4367 parse_immediate (char **str
, int *val
, int min
, int max
,
4368 bfd_boolean prefix_opt
)
4371 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4372 if (exp
.X_op
!= O_constant
)
4374 inst
.error
= _("constant expression required");
4378 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4380 inst
.error
= _("immediate value out of range");
4384 *val
= exp
.X_add_number
;
4388 /* Less-generic immediate-value read function with the possibility of loading a
4389 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4390 instructions. Puts the result directly in inst.operands[i]. */
4393 parse_big_immediate (char **str
, int i
)
4398 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4400 if (exp
.X_op
== O_constant
)
4402 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4403 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4404 O_constant. We have to be careful not to break compilation for
4405 32-bit X_add_number, though. */
4406 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4408 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4409 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4410 inst
.operands
[i
].regisimm
= 1;
4413 else if (exp
.X_op
== O_big
4414 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4415 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4417 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4418 /* Bignums have their least significant bits in
4419 generic_bignum[0]. Make sure we put 32 bits in imm and
4420 32 bits in reg, in a (hopefully) portable way. */
4421 gas_assert (parts
!= 0);
4422 inst
.operands
[i
].imm
= 0;
4423 for (j
= 0; j
< parts
; j
++, idx
++)
4424 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4425 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4426 inst
.operands
[i
].reg
= 0;
4427 for (j
= 0; j
< parts
; j
++, idx
++)
4428 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4429 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4430 inst
.operands
[i
].regisimm
= 1;
4440 /* Returns the pseudo-register number of an FPA immediate constant,
4441 or FAIL if there isn't a valid constant here. */
4444 parse_fpa_immediate (char ** str
)
4446 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4452 /* First try and match exact strings, this is to guarantee
4453 that some formats will work even for cross assembly. */
4455 for (i
= 0; fp_const
[i
]; i
++)
4457 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4461 *str
+= strlen (fp_const
[i
]);
4462 if (is_end_of_line
[(unsigned char) **str
])
4468 /* Just because we didn't get a match doesn't mean that the constant
4469 isn't valid, just that it is in a format that we don't
4470 automatically recognize. Try parsing it with the standard
4471 expression routines. */
4473 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4475 /* Look for a raw floating point number. */
4476 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4477 && is_end_of_line
[(unsigned char) *save_in
])
4479 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4481 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4483 if (words
[j
] != fp_values
[i
][j
])
4487 if (j
== MAX_LITTLENUMS
)
4495 /* Try and parse a more complex expression, this will probably fail
4496 unless the code uses a floating point prefix (eg "0f"). */
4497 save_in
= input_line_pointer
;
4498 input_line_pointer
= *str
;
4499 if (expression (&exp
) == absolute_section
4500 && exp
.X_op
== O_big
4501 && exp
.X_add_number
< 0)
4503 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4505 if (gen_to_words (words
, 5, (long) 15) == 0)
4507 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4509 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4511 if (words
[j
] != fp_values
[i
][j
])
4515 if (j
== MAX_LITTLENUMS
)
4517 *str
= input_line_pointer
;
4518 input_line_pointer
= save_in
;
4525 *str
= input_line_pointer
;
4526 input_line_pointer
= save_in
;
4527 inst
.error
= _("invalid FPA immediate expression");
4531 /* Returns 1 if a number has "quarter-precision" float format
4532 0baBbbbbbc defgh000 00000000 00000000. */
4535 is_quarter_float (unsigned imm
)
4537 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4538 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4541 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4542 0baBbbbbbc defgh000 00000000 00000000.
4543 The zero and minus-zero cases need special handling, since they can't be
4544 encoded in the "quarter-precision" float format, but can nonetheless be
4545 loaded as integer constants. */
4548 parse_qfloat_immediate (char **ccp
, int *immed
)
4552 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4553 int found_fpchar
= 0;
4555 skip_past_char (&str
, '#');
4557 /* We must not accidentally parse an integer as a floating-point number. Make
4558 sure that the value we parse is not an integer by checking for special
4559 characters '.' or 'e'.
4560 FIXME: This is a horrible hack, but doing better is tricky because type
4561 information isn't in a very usable state at parse time. */
4563 skip_whitespace (fpnum
);
4565 if (strncmp (fpnum
, "0x", 2) == 0)
4569 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4570 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4580 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4582 unsigned fpword
= 0;
4585 /* Our FP word must be 32 bits (single-precision FP). */
4586 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4588 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4592 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4605 /* Shift operands. */
4608 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4611 struct asm_shift_name
4614 enum shift_kind kind
;
4617 /* Third argument to parse_shift. */
4618 enum parse_shift_mode
4620 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4621 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4622 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4623 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4624 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4627 /* Parse a <shift> specifier on an ARM data processing instruction.
4628 This has three forms:
4630 (LSL|LSR|ASL|ASR|ROR) Rs
4631 (LSL|LSR|ASL|ASR|ROR) #imm
4634 Note that ASL is assimilated to LSL in the instruction encoding, and
4635 RRX to ROR #0 (which cannot be written as such). */
4638 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4640 const struct asm_shift_name
*shift_name
;
4641 enum shift_kind shift
;
4646 for (p
= *str
; ISALPHA (*p
); p
++)
4651 inst
.error
= _("shift expression expected");
4655 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4658 if (shift_name
== NULL
)
4660 inst
.error
= _("shift expression expected");
4664 shift
= shift_name
->kind
;
4668 case NO_SHIFT_RESTRICT
:
4669 case SHIFT_IMMEDIATE
: break;
4671 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4672 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4674 inst
.error
= _("'LSL' or 'ASR' required");
4679 case SHIFT_LSL_IMMEDIATE
:
4680 if (shift
!= SHIFT_LSL
)
4682 inst
.error
= _("'LSL' required");
4687 case SHIFT_ASR_IMMEDIATE
:
4688 if (shift
!= SHIFT_ASR
)
4690 inst
.error
= _("'ASR' required");
4698 if (shift
!= SHIFT_RRX
)
4700 /* Whitespace can appear here if the next thing is a bare digit. */
4701 skip_whitespace (p
);
4703 if (mode
== NO_SHIFT_RESTRICT
4704 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4706 inst
.operands
[i
].imm
= reg
;
4707 inst
.operands
[i
].immisreg
= 1;
4709 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4712 inst
.operands
[i
].shift_kind
= shift
;
4713 inst
.operands
[i
].shifted
= 1;
4718 /* Parse a <shifter_operand> for an ARM data processing instruction:
4721 #<immediate>, <rotate>
4725 where <shift> is defined by parse_shift above, and <rotate> is a
4726 multiple of 2 between 0 and 30. Validation of immediate operands
4727 is deferred to md_apply_fix. */
4730 parse_shifter_operand (char **str
, int i
)
4735 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4737 inst
.operands
[i
].reg
= value
;
4738 inst
.operands
[i
].isreg
= 1;
4740 /* parse_shift will override this if appropriate */
4741 inst
.reloc
.exp
.X_op
= O_constant
;
4742 inst
.reloc
.exp
.X_add_number
= 0;
4744 if (skip_past_comma (str
) == FAIL
)
4747 /* Shift operation on register. */
4748 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4751 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4754 if (skip_past_comma (str
) == SUCCESS
)
4756 /* #x, y -- ie explicit rotation by Y. */
4757 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4760 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4762 inst
.error
= _("constant expression expected");
4766 value
= exp
.X_add_number
;
4767 if (value
< 0 || value
> 30 || value
% 2 != 0)
4769 inst
.error
= _("invalid rotation");
4772 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4774 inst
.error
= _("invalid constant");
4778 /* Convert to decoded value. md_apply_fix will put it back. */
4779 inst
.reloc
.exp
.X_add_number
4780 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4781 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4784 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4785 inst
.reloc
.pc_rel
= 0;
4789 /* Group relocation information. Each entry in the table contains the
4790 textual name of the relocation as may appear in assembler source
4791 and must end with a colon.
4792 Along with this textual name are the relocation codes to be used if
4793 the corresponding instruction is an ALU instruction (ADD or SUB only),
4794 an LDR, an LDRS, or an LDC. */
4796 struct group_reloc_table_entry
4807 /* Varieties of non-ALU group relocation. */
4814 static struct group_reloc_table_entry group_reloc_table
[] =
4815 { /* Program counter relative: */
4817 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4822 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4823 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4824 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4825 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4827 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4832 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4833 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4834 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4835 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4837 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4838 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4839 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4840 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4841 /* Section base relative */
4843 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4848 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4849 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4850 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4851 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4853 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4858 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4859 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4860 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4861 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4863 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4864 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4865 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4866 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4868 /* Given the address of a pointer pointing to the textual name of a group
4869 relocation as may appear in assembler source, attempt to find its details
4870 in group_reloc_table. The pointer will be updated to the character after
4871 the trailing colon. On failure, FAIL will be returned; SUCCESS
4872 otherwise. On success, *entry will be updated to point at the relevant
4873 group_reloc_table entry. */
4876 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4879 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4881 int length
= strlen (group_reloc_table
[i
].name
);
4883 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4884 && (*str
)[length
] == ':')
4886 *out
= &group_reloc_table
[i
];
4887 *str
+= (length
+ 1);
4895 /* Parse a <shifter_operand> for an ARM data processing instruction
4896 (as for parse_shifter_operand) where group relocations are allowed:
4899 #<immediate>, <rotate>
4900 #:<group_reloc>:<expression>
4904 where <group_reloc> is one of the strings defined in group_reloc_table.
4905 The hashes are optional.
4907 Everything else is as for parse_shifter_operand. */
4909 static parse_operand_result
4910 parse_shifter_operand_group_reloc (char **str
, int i
)
4912 /* Determine if we have the sequence of characters #: or just :
4913 coming next. If we do, then we check for a group relocation.
4914 If we don't, punt the whole lot to parse_shifter_operand. */
4916 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4917 || (*str
)[0] == ':')
4919 struct group_reloc_table_entry
*entry
;
4921 if ((*str
)[0] == '#')
4926 /* Try to parse a group relocation. Anything else is an error. */
4927 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4929 inst
.error
= _("unknown group relocation");
4930 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4933 /* We now have the group relocation table entry corresponding to
4934 the name in the assembler source. Next, we parse the expression. */
4935 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4936 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4938 /* Record the relocation type (always the ALU variant here). */
4939 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4940 gas_assert (inst
.reloc
.type
!= 0);
4942 return PARSE_OPERAND_SUCCESS
;
4945 return parse_shifter_operand (str
, i
) == SUCCESS
4946 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4948 /* Never reached. */
4951 /* Parse a Neon alignment expression. Information is written to
4952 inst.operands[i]. We assume the initial ':' has been skipped.
4954 align .imm = align << 8, .immisalign=1, .preind=0 */
4955 static parse_operand_result
4956 parse_neon_alignment (char **str
, int i
)
4961 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4963 if (exp
.X_op
!= O_constant
)
4965 inst
.error
= _("alignment must be constant");
4966 return PARSE_OPERAND_FAIL
;
4969 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4970 inst
.operands
[i
].immisalign
= 1;
4971 /* Alignments are not pre-indexes. */
4972 inst
.operands
[i
].preind
= 0;
4975 return PARSE_OPERAND_SUCCESS
;
4978 /* Parse all forms of an ARM address expression. Information is written
4979 to inst.operands[i] and/or inst.reloc.
4981 Preindexed addressing (.preind=1):
4983 [Rn, #offset] .reg=Rn .reloc.exp=offset
4984 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4985 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4986 .shift_kind=shift .reloc.exp=shift_imm
4988 These three may have a trailing ! which causes .writeback to be set also.
4990 Postindexed addressing (.postind=1, .writeback=1):
4992 [Rn], #offset .reg=Rn .reloc.exp=offset
4993 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4994 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4995 .shift_kind=shift .reloc.exp=shift_imm
4997 Unindexed addressing (.preind=0, .postind=0):
4999 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5003 [Rn]{!} shorthand for [Rn,#0]{!}
5004 =immediate .isreg=0 .reloc.exp=immediate
5005 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5007 It is the caller's responsibility to check for addressing modes not
5008 supported by the instruction, and to set inst.reloc.type. */
5010 static parse_operand_result
5011 parse_address_main (char **str
, int i
, int group_relocations
,
5012 group_reloc_type group_type
)
5017 if (skip_past_char (&p
, '[') == FAIL
)
5019 if (skip_past_char (&p
, '=') == FAIL
)
5021 /* Bare address - translate to PC-relative offset. */
5022 inst
.reloc
.pc_rel
= 1;
5023 inst
.operands
[i
].reg
= REG_PC
;
5024 inst
.operands
[i
].isreg
= 1;
5025 inst
.operands
[i
].preind
= 1;
5027 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5029 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5030 return PARSE_OPERAND_FAIL
;
5033 return PARSE_OPERAND_SUCCESS
;
5036 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5038 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5039 return PARSE_OPERAND_FAIL
;
5041 inst
.operands
[i
].reg
= reg
;
5042 inst
.operands
[i
].isreg
= 1;
5044 if (skip_past_comma (&p
) == SUCCESS
)
5046 inst
.operands
[i
].preind
= 1;
5049 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5051 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5053 inst
.operands
[i
].imm
= reg
;
5054 inst
.operands
[i
].immisreg
= 1;
5056 if (skip_past_comma (&p
) == SUCCESS
)
5057 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5058 return PARSE_OPERAND_FAIL
;
5060 else if (skip_past_char (&p
, ':') == SUCCESS
)
5062 /* FIXME: '@' should be used here, but it's filtered out by generic
5063 code before we get to see it here. This may be subject to
5065 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5067 if (result
!= PARSE_OPERAND_SUCCESS
)
5072 if (inst
.operands
[i
].negative
)
5074 inst
.operands
[i
].negative
= 0;
5078 if (group_relocations
5079 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5081 struct group_reloc_table_entry
*entry
;
5083 /* Skip over the #: or : sequence. */
5089 /* Try to parse a group relocation. Anything else is an
5091 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5093 inst
.error
= _("unknown group relocation");
5094 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5097 /* We now have the group relocation table entry corresponding to
5098 the name in the assembler source. Next, we parse the
5100 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5101 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5103 /* Record the relocation type. */
5107 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5111 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5115 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5122 if (inst
.reloc
.type
== 0)
5124 inst
.error
= _("this group relocation is not allowed on this instruction");
5125 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5129 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5130 return PARSE_OPERAND_FAIL
;
5133 else if (skip_past_char (&p
, ':') == SUCCESS
)
5135 /* FIXME: '@' should be used here, but it's filtered out by generic code
5136 before we get to see it here. This may be subject to change. */
5137 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5139 if (result
!= PARSE_OPERAND_SUCCESS
)
5143 if (skip_past_char (&p
, ']') == FAIL
)
5145 inst
.error
= _("']' expected");
5146 return PARSE_OPERAND_FAIL
;
5149 if (skip_past_char (&p
, '!') == SUCCESS
)
5150 inst
.operands
[i
].writeback
= 1;
5152 else if (skip_past_comma (&p
) == SUCCESS
)
5154 if (skip_past_char (&p
, '{') == SUCCESS
)
5156 /* [Rn], {expr} - unindexed, with option */
5157 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5158 0, 255, TRUE
) == FAIL
)
5159 return PARSE_OPERAND_FAIL
;
5161 if (skip_past_char (&p
, '}') == FAIL
)
5163 inst
.error
= _("'}' expected at end of 'option' field");
5164 return PARSE_OPERAND_FAIL
;
5166 if (inst
.operands
[i
].preind
)
5168 inst
.error
= _("cannot combine index with option");
5169 return PARSE_OPERAND_FAIL
;
5172 return PARSE_OPERAND_SUCCESS
;
5176 inst
.operands
[i
].postind
= 1;
5177 inst
.operands
[i
].writeback
= 1;
5179 if (inst
.operands
[i
].preind
)
5181 inst
.error
= _("cannot combine pre- and post-indexing");
5182 return PARSE_OPERAND_FAIL
;
5186 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5188 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5190 /* We might be using the immediate for alignment already. If we
5191 are, OR the register number into the low-order bits. */
5192 if (inst
.operands
[i
].immisalign
)
5193 inst
.operands
[i
].imm
|= reg
;
5195 inst
.operands
[i
].imm
= reg
;
5196 inst
.operands
[i
].immisreg
= 1;
5198 if (skip_past_comma (&p
) == SUCCESS
)
5199 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5200 return PARSE_OPERAND_FAIL
;
5204 if (inst
.operands
[i
].negative
)
5206 inst
.operands
[i
].negative
= 0;
5209 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5210 return PARSE_OPERAND_FAIL
;
5215 /* If at this point neither .preind nor .postind is set, we have a
5216 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5217 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5219 inst
.operands
[i
].preind
= 1;
5220 inst
.reloc
.exp
.X_op
= O_constant
;
5221 inst
.reloc
.exp
.X_add_number
= 0;
5224 return PARSE_OPERAND_SUCCESS
;
5228 parse_address (char **str
, int i
)
5230 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5234 static parse_operand_result
5235 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5237 return parse_address_main (str
, i
, 1, type
);
5240 /* Parse an operand for a MOVW or MOVT instruction. */
5242 parse_half (char **str
)
5247 skip_past_char (&p
, '#');
5248 if (strncasecmp (p
, ":lower16:", 9) == 0)
5249 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5250 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5251 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5253 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5256 skip_whitespace (p
);
5259 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5262 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5264 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5266 inst
.error
= _("constant expression expected");
5269 if (inst
.reloc
.exp
.X_add_number
< 0
5270 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5272 inst
.error
= _("immediate value out of range");
5280 /* Miscellaneous. */
5282 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5283 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5285 parse_psr (char **str
)
5288 unsigned long psr_field
;
5289 const struct asm_psr
*psr
;
5292 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5293 feature for ease of use and backwards compatibility. */
5295 if (strncasecmp (p
, "SPSR", 4) == 0)
5296 psr_field
= SPSR_BIT
;
5297 else if (strncasecmp (p
, "CPSR", 4) == 0)
5304 while (ISALNUM (*p
) || *p
== '_');
5306 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5318 /* A suffix follows. */
5324 while (ISALNUM (*p
) || *p
== '_');
5326 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5331 psr_field
|= psr
->field
;
5336 goto error
; /* Garbage after "[CS]PSR". */
5338 psr_field
|= (PSR_c
| PSR_f
);
5344 inst
.error
= _("flag for {c}psr instruction expected");
5348 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5349 value suitable for splatting into the AIF field of the instruction. */
5352 parse_cps_flags (char **str
)
5361 case '\0': case ',':
5364 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5365 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5366 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5369 inst
.error
= _("unrecognized CPS flag");
5374 if (saw_a_flag
== 0)
5376 inst
.error
= _("missing CPS flags");
5384 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5385 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5388 parse_endian_specifier (char **str
)
5393 if (strncasecmp (s
, "BE", 2))
5395 else if (strncasecmp (s
, "LE", 2))
5399 inst
.error
= _("valid endian specifiers are be or le");
5403 if (ISALNUM (s
[2]) || s
[2] == '_')
5405 inst
.error
= _("valid endian specifiers are be or le");
5410 return little_endian
;
5413 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5414 value suitable for poking into the rotate field of an sxt or sxta
5415 instruction, or FAIL on error. */
5418 parse_ror (char **str
)
5423 if (strncasecmp (s
, "ROR", 3) == 0)
5427 inst
.error
= _("missing rotation field after comma");
5431 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5436 case 0: *str
= s
; return 0x0;
5437 case 8: *str
= s
; return 0x1;
5438 case 16: *str
= s
; return 0x2;
5439 case 24: *str
= s
; return 0x3;
5442 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5447 /* Parse a conditional code (from conds[] below). The value returned is in the
5448 range 0 .. 14, or FAIL. */
5450 parse_cond (char **str
)
5453 const struct asm_cond
*c
;
5455 /* Condition codes are always 2 characters, so matching up to
5456 3 characters is sufficient. */
5461 while (ISALPHA (*q
) && n
< 3)
5463 cond
[n
] = TOLOWER (*q
);
5468 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5471 inst
.error
= _("condition required");
5479 /* Parse an option for a barrier instruction. Returns the encoding for the
5482 parse_barrier (char **str
)
5485 const struct asm_barrier_opt
*o
;
5488 while (ISALPHA (*q
))
5491 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5500 /* Parse the operands of a table branch instruction. Similar to a memory
5503 parse_tb (char **str
)
5508 if (skip_past_char (&p
, '[') == FAIL
)
5510 inst
.error
= _("'[' expected");
5514 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5516 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5519 inst
.operands
[0].reg
= reg
;
5521 if (skip_past_comma (&p
) == FAIL
)
5523 inst
.error
= _("',' expected");
5527 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5529 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5532 inst
.operands
[0].imm
= reg
;
5534 if (skip_past_comma (&p
) == SUCCESS
)
5536 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5538 if (inst
.reloc
.exp
.X_add_number
!= 1)
5540 inst
.error
= _("invalid shift");
5543 inst
.operands
[0].shifted
= 1;
5546 if (skip_past_char (&p
, ']') == FAIL
)
5548 inst
.error
= _("']' expected");
5555 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5556 information on the types the operands can take and how they are encoded.
5557 Up to four operands may be read; this function handles setting the
5558 ".present" field for each read operand itself.
5559 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5560 else returns FAIL. */
5563 parse_neon_mov (char **str
, int *which_operand
)
5565 int i
= *which_operand
, val
;
5566 enum arm_reg_type rtype
;
5568 struct neon_type_el optype
;
5570 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5572 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5573 inst
.operands
[i
].reg
= val
;
5574 inst
.operands
[i
].isscalar
= 1;
5575 inst
.operands
[i
].vectype
= optype
;
5576 inst
.operands
[i
++].present
= 1;
5578 if (skip_past_comma (&ptr
) == FAIL
)
5581 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5584 inst
.operands
[i
].reg
= val
;
5585 inst
.operands
[i
].isreg
= 1;
5586 inst
.operands
[i
].present
= 1;
5588 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5591 /* Cases 0, 1, 2, 3, 5 (D only). */
5592 if (skip_past_comma (&ptr
) == FAIL
)
5595 inst
.operands
[i
].reg
= val
;
5596 inst
.operands
[i
].isreg
= 1;
5597 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5598 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5599 inst
.operands
[i
].isvec
= 1;
5600 inst
.operands
[i
].vectype
= optype
;
5601 inst
.operands
[i
++].present
= 1;
5603 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5605 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5606 Case 13: VMOV <Sd>, <Rm> */
5607 inst
.operands
[i
].reg
= val
;
5608 inst
.operands
[i
].isreg
= 1;
5609 inst
.operands
[i
].present
= 1;
5611 if (rtype
== REG_TYPE_NQ
)
5613 first_error (_("can't use Neon quad register here"));
5616 else if (rtype
!= REG_TYPE_VFS
)
5619 if (skip_past_comma (&ptr
) == FAIL
)
5621 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5623 inst
.operands
[i
].reg
= val
;
5624 inst
.operands
[i
].isreg
= 1;
5625 inst
.operands
[i
].present
= 1;
5628 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5631 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5632 Case 1: VMOV<c><q> <Dd>, <Dm>
5633 Case 8: VMOV.F32 <Sd>, <Sm>
5634 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5636 inst
.operands
[i
].reg
= val
;
5637 inst
.operands
[i
].isreg
= 1;
5638 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5639 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5640 inst
.operands
[i
].isvec
= 1;
5641 inst
.operands
[i
].vectype
= optype
;
5642 inst
.operands
[i
].present
= 1;
5644 if (skip_past_comma (&ptr
) == SUCCESS
)
5649 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5652 inst
.operands
[i
].reg
= val
;
5653 inst
.operands
[i
].isreg
= 1;
5654 inst
.operands
[i
++].present
= 1;
5656 if (skip_past_comma (&ptr
) == FAIL
)
5659 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5662 inst
.operands
[i
].reg
= val
;
5663 inst
.operands
[i
].isreg
= 1;
5664 inst
.operands
[i
++].present
= 1;
5667 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5668 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5669 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5670 Case 10: VMOV.F32 <Sd>, #<imm>
5671 Case 11: VMOV.F64 <Dd>, #<imm> */
5672 inst
.operands
[i
].immisfloat
= 1;
5673 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5674 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5675 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5679 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5683 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5686 inst
.operands
[i
].reg
= val
;
5687 inst
.operands
[i
].isreg
= 1;
5688 inst
.operands
[i
++].present
= 1;
5690 if (skip_past_comma (&ptr
) == FAIL
)
5693 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5695 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5696 inst
.operands
[i
].reg
= val
;
5697 inst
.operands
[i
].isscalar
= 1;
5698 inst
.operands
[i
].present
= 1;
5699 inst
.operands
[i
].vectype
= optype
;
5701 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5703 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5704 inst
.operands
[i
].reg
= val
;
5705 inst
.operands
[i
].isreg
= 1;
5706 inst
.operands
[i
++].present
= 1;
5708 if (skip_past_comma (&ptr
) == FAIL
)
5711 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5714 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5718 inst
.operands
[i
].reg
= val
;
5719 inst
.operands
[i
].isreg
= 1;
5720 inst
.operands
[i
].isvec
= 1;
5721 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5722 inst
.operands
[i
].vectype
= optype
;
5723 inst
.operands
[i
].present
= 1;
5725 if (rtype
== REG_TYPE_VFS
)
5729 if (skip_past_comma (&ptr
) == FAIL
)
5731 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5734 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5737 inst
.operands
[i
].reg
= val
;
5738 inst
.operands
[i
].isreg
= 1;
5739 inst
.operands
[i
].isvec
= 1;
5740 inst
.operands
[i
].issingle
= 1;
5741 inst
.operands
[i
].vectype
= optype
;
5742 inst
.operands
[i
].present
= 1;
5745 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5749 inst
.operands
[i
].reg
= val
;
5750 inst
.operands
[i
].isreg
= 1;
5751 inst
.operands
[i
].isvec
= 1;
5752 inst
.operands
[i
].issingle
= 1;
5753 inst
.operands
[i
].vectype
= optype
;
5754 inst
.operands
[i
++].present
= 1;
5759 first_error (_("parse error"));
5763 /* Successfully parsed the operands. Update args. */
5769 first_error (_("expected comma"));
5773 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5777 /* Use this macro when the operand constraints are different
5778 for ARM and THUMB (e.g. ldrd). */
5779 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5780 ((arm_operand) | ((thumb_operand) << 16))
5782 /* Matcher codes for parse_operands. */
5783 enum operand_parse_code
5785 OP_stop
, /* end of line */
5787 OP_RR
, /* ARM register */
5788 OP_RRnpc
, /* ARM register, not r15 */
5789 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5790 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5791 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5792 optional trailing ! */
5793 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5794 OP_RCP
, /* Coprocessor number */
5795 OP_RCN
, /* Coprocessor register */
5796 OP_RF
, /* FPA register */
5797 OP_RVS
, /* VFP single precision register */
5798 OP_RVD
, /* VFP double precision register (0..15) */
5799 OP_RND
, /* Neon double precision register (0..31) */
5800 OP_RNQ
, /* Neon quad precision register */
5801 OP_RVSD
, /* VFP single or double precision register */
5802 OP_RNDQ
, /* Neon double or quad precision register */
5803 OP_RNSDQ
, /* Neon single, double or quad precision register */
5804 OP_RNSC
, /* Neon scalar D[X] */
5805 OP_RVC
, /* VFP control register */
5806 OP_RMF
, /* Maverick F register */
5807 OP_RMD
, /* Maverick D register */
5808 OP_RMFX
, /* Maverick FX register */
5809 OP_RMDX
, /* Maverick DX register */
5810 OP_RMAX
, /* Maverick AX register */
5811 OP_RMDS
, /* Maverick DSPSC register */
5812 OP_RIWR
, /* iWMMXt wR register */
5813 OP_RIWC
, /* iWMMXt wC register */
5814 OP_RIWG
, /* iWMMXt wCG register */
5815 OP_RXA
, /* XScale accumulator register */
5817 OP_REGLST
, /* ARM register list */
5818 OP_VRSLST
, /* VFP single-precision register list */
5819 OP_VRDLST
, /* VFP double-precision register list */
5820 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5821 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5822 OP_NSTRLST
, /* Neon element/structure list */
5824 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5825 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5826 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5827 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5828 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5829 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5830 OP_VMOV
, /* Neon VMOV operands. */
5831 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5832 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5833 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5835 OP_I0
, /* immediate zero */
5836 OP_I7
, /* immediate value 0 .. 7 */
5837 OP_I15
, /* 0 .. 15 */
5838 OP_I16
, /* 1 .. 16 */
5839 OP_I16z
, /* 0 .. 16 */
5840 OP_I31
, /* 0 .. 31 */
5841 OP_I31w
, /* 0 .. 31, optional trailing ! */
5842 OP_I32
, /* 1 .. 32 */
5843 OP_I32z
, /* 0 .. 32 */
5844 OP_I63
, /* 0 .. 63 */
5845 OP_I63s
, /* -64 .. 63 */
5846 OP_I64
, /* 1 .. 64 */
5847 OP_I64z
, /* 0 .. 64 */
5848 OP_I255
, /* 0 .. 255 */
5850 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5851 OP_I7b
, /* 0 .. 7 */
5852 OP_I15b
, /* 0 .. 15 */
5853 OP_I31b
, /* 0 .. 31 */
5855 OP_SH
, /* shifter operand */
5856 OP_SHG
, /* shifter operand with possible group relocation */
5857 OP_ADDR
, /* Memory address expression (any mode) */
5858 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5859 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5860 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5861 OP_EXP
, /* arbitrary expression */
5862 OP_EXPi
, /* same, with optional immediate prefix */
5863 OP_EXPr
, /* same, with optional relocation suffix */
5864 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5866 OP_CPSF
, /* CPS flags */
5867 OP_ENDI
, /* Endianness specifier */
5868 OP_PSR
, /* CPSR/SPSR mask for msr */
5869 OP_COND
, /* conditional code */
5870 OP_TB
, /* Table branch. */
5872 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5873 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5875 OP_RRnpc_I0
, /* ARM register or literal 0 */
5876 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5877 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5878 OP_RF_IF
, /* FPA register or immediate */
5879 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5880 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5882 /* Optional operands. */
5883 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5884 OP_oI31b
, /* 0 .. 31 */
5885 OP_oI32b
, /* 1 .. 32 */
5886 OP_oIffffb
, /* 0 .. 65535 */
5887 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5889 OP_oRR
, /* ARM register */
5890 OP_oRRnpc
, /* ARM register, not the PC */
5891 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
5892 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5893 OP_oRND
, /* Optional Neon double precision register */
5894 OP_oRNQ
, /* Optional Neon quad precision register */
5895 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5896 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5897 OP_oSHll
, /* LSL immediate */
5898 OP_oSHar
, /* ASR immediate */
5899 OP_oSHllar
, /* LSL or ASR immediate */
5900 OP_oROR
, /* ROR 0/8/16/24 */
5901 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5903 /* Some pre-defined mixed (ARM/THUMB) operands. */
5904 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
5905 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
5906 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
5908 OP_FIRST_OPTIONAL
= OP_oI7b
5911 /* Generic instruction operand parser. This does no encoding and no
5912 semantic validation; it merely squirrels values away in the inst
5913 structure. Returns SUCCESS or FAIL depending on whether the
5914 specified grammar matched. */
5916 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
5918 unsigned const int *upat
= pattern
;
5919 char *backtrack_pos
= 0;
5920 const char *backtrack_error
= 0;
5921 int i
, val
, backtrack_index
= 0;
5922 enum arm_reg_type rtype
;
5923 parse_operand_result result
;
5924 unsigned int op_parse_code
;
5926 #define po_char_or_fail(chr) \
5929 if (skip_past_char (&str, chr) == FAIL) \
5934 #define po_reg_or_fail(regtype) \
5937 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5938 & inst.operands[i].vectype); \
5941 first_error (_(reg_expected_msgs[regtype])); \
5944 inst.operands[i].reg = val; \
5945 inst.operands[i].isreg = 1; \
5946 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5947 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5948 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5949 || rtype == REG_TYPE_VFD \
5950 || rtype == REG_TYPE_NQ); \
5954 #define po_reg_or_goto(regtype, label) \
5957 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5958 & inst.operands[i].vectype); \
5962 inst.operands[i].reg = val; \
5963 inst.operands[i].isreg = 1; \
5964 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5965 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5966 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5967 || rtype == REG_TYPE_VFD \
5968 || rtype == REG_TYPE_NQ); \
5972 #define po_imm_or_fail(min, max, popt) \
5975 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5977 inst.operands[i].imm = val; \
5981 #define po_scalar_or_goto(elsz, label) \
5984 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5987 inst.operands[i].reg = val; \
5988 inst.operands[i].isscalar = 1; \
5992 #define po_misc_or_fail(expr) \
6000 #define po_misc_or_fail_no_backtrack(expr) \
6004 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6005 backtrack_pos = 0; \
6006 if (result != PARSE_OPERAND_SUCCESS) \
6011 skip_whitespace (str
);
6013 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6015 op_parse_code
= upat
[i
];
6016 if (op_parse_code
>= 1<<16)
6017 op_parse_code
= thumb
? (op_parse_code
>> 16)
6018 : (op_parse_code
& ((1<<16)-1));
6020 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6022 /* Remember where we are in case we need to backtrack. */
6023 gas_assert (!backtrack_pos
);
6024 backtrack_pos
= str
;
6025 backtrack_error
= inst
.error
;
6026 backtrack_index
= i
;
6029 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6030 po_char_or_fail (',');
6032 switch (op_parse_code
)
6040 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6041 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6042 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6043 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6044 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6045 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6047 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6049 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6051 /* Also accept generic coprocessor regs for unknown registers. */
6053 po_reg_or_fail (REG_TYPE_CN
);
6055 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6056 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6057 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6058 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6059 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6060 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6061 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6062 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6063 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6064 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6066 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6068 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6069 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6071 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6073 /* Neon scalar. Using an element size of 8 means that some invalid
6074 scalars are accepted here, so deal with those in later code. */
6075 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6079 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6082 po_imm_or_fail (0, 0, TRUE
);
6087 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6092 po_scalar_or_goto (8, try_rr
);
6095 po_reg_or_fail (REG_TYPE_RN
);
6101 po_scalar_or_goto (8, try_nsdq
);
6104 po_reg_or_fail (REG_TYPE_NSDQ
);
6110 po_scalar_or_goto (8, try_ndq
);
6113 po_reg_or_fail (REG_TYPE_NDQ
);
6119 po_scalar_or_goto (8, try_vfd
);
6122 po_reg_or_fail (REG_TYPE_VFD
);
6127 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6128 not careful then bad things might happen. */
6129 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6134 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6137 /* There's a possibility of getting a 64-bit immediate here, so
6138 we need special handling. */
6139 if (parse_big_immediate (&str
, i
) == FAIL
)
6141 inst
.error
= _("immediate value is out of range");
6149 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6152 po_imm_or_fail (0, 63, TRUE
);
6157 po_char_or_fail ('[');
6158 po_reg_or_fail (REG_TYPE_RN
);
6159 po_char_or_fail (']');
6165 po_reg_or_fail (REG_TYPE_RN
);
6166 if (skip_past_char (&str
, '!') == SUCCESS
)
6167 inst
.operands
[i
].writeback
= 1;
6171 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6172 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6173 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6174 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6175 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6176 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6177 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6178 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6179 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6180 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6181 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6182 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6184 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6186 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6187 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6189 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6190 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6191 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6193 /* Immediate variants */
6195 po_char_or_fail ('{');
6196 po_imm_or_fail (0, 255, TRUE
);
6197 po_char_or_fail ('}');
6201 /* The expression parser chokes on a trailing !, so we have
6202 to find it first and zap it. */
6205 while (*s
&& *s
!= ',')
6210 inst
.operands
[i
].writeback
= 1;
6212 po_imm_or_fail (0, 31, TRUE
);
6220 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6225 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6230 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6232 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6234 val
= parse_reloc (&str
);
6237 inst
.error
= _("unrecognized relocation suffix");
6240 else if (val
!= BFD_RELOC_UNUSED
)
6242 inst
.operands
[i
].imm
= val
;
6243 inst
.operands
[i
].hasreloc
= 1;
6248 /* Operand for MOVW or MOVT. */
6250 po_misc_or_fail (parse_half (&str
));
6253 /* Register or expression. */
6254 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6255 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6257 /* Register or immediate. */
6258 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6259 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6261 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6263 if (!is_immediate_prefix (*str
))
6266 val
= parse_fpa_immediate (&str
);
6269 /* FPA immediates are encoded as registers 8-15.
6270 parse_fpa_immediate has already applied the offset. */
6271 inst
.operands
[i
].reg
= val
;
6272 inst
.operands
[i
].isreg
= 1;
6275 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6276 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6278 /* Two kinds of register. */
6281 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6283 || (rege
->type
!= REG_TYPE_MMXWR
6284 && rege
->type
!= REG_TYPE_MMXWC
6285 && rege
->type
!= REG_TYPE_MMXWCG
))
6287 inst
.error
= _("iWMMXt data or control register expected");
6290 inst
.operands
[i
].reg
= rege
->number
;
6291 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6297 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6299 || (rege
->type
!= REG_TYPE_MMXWC
6300 && rege
->type
!= REG_TYPE_MMXWCG
))
6302 inst
.error
= _("iWMMXt control register expected");
6305 inst
.operands
[i
].reg
= rege
->number
;
6306 inst
.operands
[i
].isreg
= 1;
6311 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6312 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6313 case OP_oROR
: val
= parse_ror (&str
); break;
6314 case OP_PSR
: val
= parse_psr (&str
); break;
6315 case OP_COND
: val
= parse_cond (&str
); break;
6316 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
6319 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6320 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6323 val
= parse_psr (&str
);
6327 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6330 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6332 if (strncasecmp (str
, "APSR_", 5) == 0)
6339 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6340 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6341 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6342 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6343 default: found
= 16;
6347 inst
.operands
[i
].isvec
= 1;
6348 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6349 inst
.operands
[i
].reg
= REG_PC
;
6356 po_misc_or_fail (parse_tb (&str
));
6359 /* Register lists. */
6361 val
= parse_reg_list (&str
);
6364 inst
.operands
[1].writeback
= 1;
6370 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6374 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6378 /* Allow Q registers too. */
6379 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6384 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6386 inst
.operands
[i
].issingle
= 1;
6391 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6396 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6397 &inst
.operands
[i
].vectype
);
6400 /* Addressing modes */
6402 po_misc_or_fail (parse_address (&str
, i
));
6406 po_misc_or_fail_no_backtrack (
6407 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6411 po_misc_or_fail_no_backtrack (
6412 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6416 po_misc_or_fail_no_backtrack (
6417 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6421 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6425 po_misc_or_fail_no_backtrack (
6426 parse_shifter_operand_group_reloc (&str
, i
));
6430 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6434 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6438 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6442 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6445 /* Various value-based sanity checks and shared operations. We
6446 do not signal immediate failures for the register constraints;
6447 this allows a syntax error to take precedence. */
6448 switch (op_parse_code
)
6456 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6457 inst
.error
= BAD_PC
;
6462 if (inst
.operands
[i
].isreg
)
6464 if (inst
.operands
[i
].reg
== REG_PC
)
6465 inst
.error
= BAD_PC
;
6466 else if (inst
.operands
[i
].reg
== REG_SP
)
6467 inst
.error
= BAD_SP
;
6472 if (inst
.operands
[i
].isreg
6473 && inst
.operands
[i
].reg
== REG_PC
6474 && (inst
.operands
[i
].writeback
|| thumb
))
6475 inst
.error
= BAD_PC
;
6493 inst
.operands
[i
].imm
= val
;
6500 /* If we get here, this operand was successfully parsed. */
6501 inst
.operands
[i
].present
= 1;
6505 inst
.error
= BAD_ARGS
;
6510 /* The parse routine should already have set inst.error, but set a
6511 default here just in case. */
6513 inst
.error
= _("syntax error");
6517 /* Do not backtrack over a trailing optional argument that
6518 absorbed some text. We will only fail again, with the
6519 'garbage following instruction' error message, which is
6520 probably less helpful than the current one. */
6521 if (backtrack_index
== i
&& backtrack_pos
!= str
6522 && upat
[i
+1] == OP_stop
)
6525 inst
.error
= _("syntax error");
6529 /* Try again, skipping the optional argument at backtrack_pos. */
6530 str
= backtrack_pos
;
6531 inst
.error
= backtrack_error
;
6532 inst
.operands
[backtrack_index
].present
= 0;
6533 i
= backtrack_index
;
6537 /* Check that we have parsed all the arguments. */
6538 if (*str
!= '\0' && !inst
.error
)
6539 inst
.error
= _("garbage following instruction");
6541 return inst
.error
? FAIL
: SUCCESS
;
6544 #undef po_char_or_fail
6545 #undef po_reg_or_fail
6546 #undef po_reg_or_goto
6547 #undef po_imm_or_fail
6548 #undef po_scalar_or_fail
6550 /* Shorthand macro for instruction encoding functions issuing errors. */
6551 #define constraint(expr, err) \
6562 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6563 instructions are unpredictable if these registers are used. This
6564 is the BadReg predicate in ARM's Thumb-2 documentation. */
6565 #define reject_bad_reg(reg) \
6567 if (reg == REG_SP || reg == REG_PC) \
6569 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6574 /* If REG is R13 (the stack pointer), warn that its use is
6576 #define warn_deprecated_sp(reg) \
6578 if (warn_on_deprecated && reg == REG_SP) \
6579 as_warn (_("use of r13 is deprecated")); \
6582 /* Functions for operand encoding. ARM, then Thumb. */
6584 #define rotate_left(v, n) (v << n | v >> (32 - n))
6586 /* If VAL can be encoded in the immediate field of an ARM instruction,
6587 return the encoded form. Otherwise, return FAIL. */
6590 encode_arm_immediate (unsigned int val
)
6594 for (i
= 0; i
< 32; i
+= 2)
6595 if ((a
= rotate_left (val
, i
)) <= 0xff)
6596 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6601 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6602 return the encoded form. Otherwise, return FAIL. */
6604 encode_thumb32_immediate (unsigned int val
)
6611 for (i
= 1; i
<= 24; i
++)
6614 if ((val
& ~(0xff << i
)) == 0)
6615 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6619 if (val
== ((a
<< 16) | a
))
6621 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6625 if (val
== ((a
<< 16) | a
))
6626 return 0x200 | (a
>> 8);
6630 /* Encode a VFP SP or DP register number into inst.instruction. */
6633 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6635 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6638 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6641 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6644 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6649 first_error (_("D register out of range for selected VFP version"));
6657 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6661 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6665 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6669 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6673 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6677 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6685 /* Encode a <shift> in an ARM-format instruction. The immediate,
6686 if any, is handled by md_apply_fix. */
6688 encode_arm_shift (int i
)
6690 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6691 inst
.instruction
|= SHIFT_ROR
<< 5;
6694 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6695 if (inst
.operands
[i
].immisreg
)
6697 inst
.instruction
|= SHIFT_BY_REG
;
6698 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6701 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6706 encode_arm_shifter_operand (int i
)
6708 if (inst
.operands
[i
].isreg
)
6710 inst
.instruction
|= inst
.operands
[i
].reg
;
6711 encode_arm_shift (i
);
6714 inst
.instruction
|= INST_IMMEDIATE
;
6717 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6719 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6721 gas_assert (inst
.operands
[i
].isreg
);
6722 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6724 if (inst
.operands
[i
].preind
)
6728 inst
.error
= _("instruction does not accept preindexed addressing");
6731 inst
.instruction
|= PRE_INDEX
;
6732 if (inst
.operands
[i
].writeback
)
6733 inst
.instruction
|= WRITE_BACK
;
6736 else if (inst
.operands
[i
].postind
)
6738 gas_assert (inst
.operands
[i
].writeback
);
6740 inst
.instruction
|= WRITE_BACK
;
6742 else /* unindexed - only for coprocessor */
6744 inst
.error
= _("instruction does not accept unindexed addressing");
6748 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6749 && (((inst
.instruction
& 0x000f0000) >> 16)
6750 == ((inst
.instruction
& 0x0000f000) >> 12)))
6751 as_warn ((inst
.instruction
& LOAD_BIT
)
6752 ? _("destination register same as write-back base")
6753 : _("source register same as write-back base"));
6756 /* inst.operands[i] was set up by parse_address. Encode it into an
6757 ARM-format mode 2 load or store instruction. If is_t is true,
6758 reject forms that cannot be used with a T instruction (i.e. not
6761 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6763 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6765 encode_arm_addr_mode_common (i
, is_t
);
6767 if (inst
.operands
[i
].immisreg
)
6769 constraint ((inst
.operands
[i
].imm
== REG_PC
6770 || (is_pc
&& inst
.operands
[i
].writeback
)),
6772 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6773 inst
.instruction
|= inst
.operands
[i
].imm
;
6774 if (!inst
.operands
[i
].negative
)
6775 inst
.instruction
|= INDEX_UP
;
6776 if (inst
.operands
[i
].shifted
)
6778 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6779 inst
.instruction
|= SHIFT_ROR
<< 5;
6782 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6783 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6787 else /* immediate offset in inst.reloc */
6789 if (is_pc
&& !inst
.reloc
.pc_rel
)
6791 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
6792 /* BAD_PC_ADDRESSING Condition =
6794 which becomes !is_load || is_t. */
6795 constraint ((!is_load
|| is_t
),
6799 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6800 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6804 /* inst.operands[i] was set up by parse_address. Encode it into an
6805 ARM-format mode 3 load or store instruction. Reject forms that
6806 cannot be used with such instructions. If is_t is true, reject
6807 forms that cannot be used with a T instruction (i.e. not
6810 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6812 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6814 inst
.error
= _("instruction does not accept scaled register index");
6818 encode_arm_addr_mode_common (i
, is_t
);
6820 if (inst
.operands
[i
].immisreg
)
6822 constraint ((inst
.operands
[i
].imm
== REG_PC
6823 || inst
.operands
[i
].reg
== REG_PC
),
6825 inst
.instruction
|= inst
.operands
[i
].imm
;
6826 if (!inst
.operands
[i
].negative
)
6827 inst
.instruction
|= INDEX_UP
;
6829 else /* immediate offset in inst.reloc */
6831 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
6832 && inst
.operands
[i
].writeback
),
6834 inst
.instruction
|= HWOFFSET_IMM
;
6835 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6836 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6840 /* inst.operands[i] was set up by parse_address. Encode it into an
6841 ARM-format instruction. Reject all forms which cannot be encoded
6842 into a coprocessor load/store instruction. If wb_ok is false,
6843 reject use of writeback; if unind_ok is false, reject use of
6844 unindexed addressing. If reloc_override is not 0, use it instead
6845 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6846 (in which case it is preserved). */
6849 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6851 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6853 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6855 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6857 gas_assert (!inst
.operands
[i
].writeback
);
6860 inst
.error
= _("instruction does not support unindexed addressing");
6863 inst
.instruction
|= inst
.operands
[i
].imm
;
6864 inst
.instruction
|= INDEX_UP
;
6868 if (inst
.operands
[i
].preind
)
6869 inst
.instruction
|= PRE_INDEX
;
6871 if (inst
.operands
[i
].writeback
)
6873 if (inst
.operands
[i
].reg
== REG_PC
)
6875 inst
.error
= _("pc may not be used with write-back");
6880 inst
.error
= _("instruction does not support writeback");
6883 inst
.instruction
|= WRITE_BACK
;
6887 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6888 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6889 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6890 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6893 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6895 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6901 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6902 Determine whether it can be performed with a move instruction; if
6903 it can, convert inst.instruction to that move instruction and
6904 return TRUE; if it can't, convert inst.instruction to a literal-pool
6905 load and return FALSE. If this is not a valid thing to do in the
6906 current context, set inst.error and return TRUE.
6908 inst.operands[i] describes the destination register. */
6911 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6916 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6920 if ((inst
.instruction
& tbit
) == 0)
6922 inst
.error
= _("invalid pseudo operation");
6925 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6927 inst
.error
= _("constant expression expected");
6930 if (inst
.reloc
.exp
.X_op
== O_constant
)
6934 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6936 /* This can be done with a mov(1) instruction. */
6937 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6938 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6944 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6947 /* This can be done with a mov instruction. */
6948 inst
.instruction
&= LITERAL_MASK
;
6949 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6950 inst
.instruction
|= value
& 0xfff;
6954 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6957 /* This can be done with a mvn instruction. */
6958 inst
.instruction
&= LITERAL_MASK
;
6959 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6960 inst
.instruction
|= value
& 0xfff;
6966 if (add_to_lit_pool () == FAIL
)
6968 inst
.error
= _("literal pool insertion failed");
6971 inst
.operands
[1].reg
= REG_PC
;
6972 inst
.operands
[1].isreg
= 1;
6973 inst
.operands
[1].preind
= 1;
6974 inst
.reloc
.pc_rel
= 1;
6975 inst
.reloc
.type
= (thumb_p
6976 ? BFD_RELOC_ARM_THUMB_OFFSET
6978 ? BFD_RELOC_ARM_HWLITERAL
6979 : BFD_RELOC_ARM_LITERAL
));
6983 /* Functions for instruction encoding, sorted by sub-architecture.
6984 First some generics; their names are taken from the conventional
6985 bit positions for register arguments in ARM format instructions. */
6995 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7001 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7002 inst
.instruction
|= inst
.operands
[1].reg
;
7008 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7009 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7015 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7016 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7022 unsigned Rn
= inst
.operands
[2].reg
;
7023 /* Enforce restrictions on SWP instruction. */
7024 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7026 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7027 _("Rn must not overlap other operands"));
7029 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7030 if (warn_on_deprecated
7031 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7032 as_warn (_("swp{b} use is deprecated for this architecture"));
7035 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7036 inst
.instruction
|= inst
.operands
[1].reg
;
7037 inst
.instruction
|= Rn
<< 16;
7043 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7044 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7045 inst
.instruction
|= inst
.operands
[2].reg
;
7051 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7052 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7053 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7054 || inst
.reloc
.exp
.X_add_number
!= 0),
7056 inst
.instruction
|= inst
.operands
[0].reg
;
7057 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7058 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7064 inst
.instruction
|= inst
.operands
[0].imm
;
7070 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7071 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7074 /* ARM instructions, in alphabetical order by function name (except
7075 that wrapper functions appear immediately after the function they
7078 /* This is a pseudo-op of the form "adr rd, label" to be converted
7079 into a relative address of the form "add rd, pc, #label-.-8". */
7084 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7086 /* Frag hacking will turn this into a sub instruction if the offset turns
7087 out to be negative. */
7088 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7089 inst
.reloc
.pc_rel
= 1;
7090 inst
.reloc
.exp
.X_add_number
-= 8;
7093 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7094 into a relative address of the form:
7095 add rd, pc, #low(label-.-8)"
7096 add rd, rd, #high(label-.-8)" */
7101 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7103 /* Frag hacking will turn this into a sub instruction if the offset turns
7104 out to be negative. */
7105 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7106 inst
.reloc
.pc_rel
= 1;
7107 inst
.size
= INSN_SIZE
* 2;
7108 inst
.reloc
.exp
.X_add_number
-= 8;
7114 if (!inst
.operands
[1].present
)
7115 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7117 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7118 encode_arm_shifter_operand (2);
7124 if (inst
.operands
[0].present
)
7126 constraint ((inst
.instruction
& 0xf0) != 0x40
7127 && inst
.operands
[0].imm
!= 0xf,
7128 _("bad barrier type"));
7129 inst
.instruction
|= inst
.operands
[0].imm
;
7132 inst
.instruction
|= 0xf;
7138 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7139 constraint (msb
> 32, _("bit-field extends past end of register"));
7140 /* The instruction encoding stores the LSB and MSB,
7141 not the LSB and width. */
7142 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7143 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7144 inst
.instruction
|= (msb
- 1) << 16;
7152 /* #0 in second position is alternative syntax for bfc, which is
7153 the same instruction but with REG_PC in the Rm field. */
7154 if (!inst
.operands
[1].isreg
)
7155 inst
.operands
[1].reg
= REG_PC
;
7157 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7158 constraint (msb
> 32, _("bit-field extends past end of register"));
7159 /* The instruction encoding stores the LSB and MSB,
7160 not the LSB and width. */
7161 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7162 inst
.instruction
|= inst
.operands
[1].reg
;
7163 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7164 inst
.instruction
|= (msb
- 1) << 16;
7170 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7171 _("bit-field extends past end of register"));
7172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7173 inst
.instruction
|= inst
.operands
[1].reg
;
7174 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7175 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7178 /* ARM V5 breakpoint instruction (argument parse)
7179 BKPT <16 bit unsigned immediate>
7180 Instruction is not conditional.
7181 The bit pattern given in insns[] has the COND_ALWAYS condition,
7182 and it is an error if the caller tried to override that. */
7187 /* Top 12 of 16 bits to bits 19:8. */
7188 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7190 /* Bottom 4 of 16 bits to bits 3:0. */
7191 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7195 encode_branch (int default_reloc
)
7197 if (inst
.operands
[0].hasreloc
)
7199 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7200 _("the only suffix valid here is '(plt)'"));
7201 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7205 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7207 inst
.reloc
.pc_rel
= 1;
7214 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7215 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7218 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7225 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7227 if (inst
.cond
== COND_ALWAYS
)
7228 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7230 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7234 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7237 /* ARM V5 branch-link-exchange instruction (argument parse)
7238 BLX <target_addr> ie BLX(1)
7239 BLX{<condition>} <Rm> ie BLX(2)
7240 Unfortunately, there are two different opcodes for this mnemonic.
7241 So, the insns[].value is not used, and the code here zaps values
7242 into inst.instruction.
7243 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7248 if (inst
.operands
[0].isreg
)
7250 /* Arg is a register; the opcode provided by insns[] is correct.
7251 It is not illegal to do "blx pc", just useless. */
7252 if (inst
.operands
[0].reg
== REG_PC
)
7253 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7255 inst
.instruction
|= inst
.operands
[0].reg
;
7259 /* Arg is an address; this instruction cannot be executed
7260 conditionally, and the opcode must be adjusted.
7261 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7262 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7263 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7264 inst
.instruction
= 0xfa000000;
7265 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7272 bfd_boolean want_reloc
;
7274 if (inst
.operands
[0].reg
== REG_PC
)
7275 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7277 inst
.instruction
|= inst
.operands
[0].reg
;
7278 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7279 it is for ARMv4t or earlier. */
7280 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7281 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7285 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7290 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7294 /* ARM v5TEJ. Jump to Jazelle code. */
7299 if (inst
.operands
[0].reg
== REG_PC
)
7300 as_tsktsk (_("use of r15 in bxj is not really useful"));
7302 inst
.instruction
|= inst
.operands
[0].reg
;
7305 /* Co-processor data operation:
7306 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7307 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7311 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7312 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7313 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7314 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7315 inst
.instruction
|= inst
.operands
[4].reg
;
7316 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7322 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7323 encode_arm_shifter_operand (1);
7326 /* Transfer between coprocessor and ARM registers.
7327 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7332 No special properties. */
7339 Rd
= inst
.operands
[2].reg
;
7342 if (inst
.instruction
== 0xee000010
7343 || inst
.instruction
== 0xfe000010)
7345 reject_bad_reg (Rd
);
7348 constraint (Rd
== REG_SP
, BAD_SP
);
7353 if (inst
.instruction
== 0xe000010)
7354 constraint (Rd
== REG_PC
, BAD_PC
);
7358 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7359 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7360 inst
.instruction
|= Rd
<< 12;
7361 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7362 inst
.instruction
|= inst
.operands
[4].reg
;
7363 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7366 /* Transfer between coprocessor register and pair of ARM registers.
7367 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7372 Two XScale instructions are special cases of these:
7374 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7375 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7377 Result unpredictable if Rd or Rn is R15. */
7384 Rd
= inst
.operands
[2].reg
;
7385 Rn
= inst
.operands
[3].reg
;
7389 reject_bad_reg (Rd
);
7390 reject_bad_reg (Rn
);
7394 constraint (Rd
== REG_PC
, BAD_PC
);
7395 constraint (Rn
== REG_PC
, BAD_PC
);
7398 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7399 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7400 inst
.instruction
|= Rd
<< 12;
7401 inst
.instruction
|= Rn
<< 16;
7402 inst
.instruction
|= inst
.operands
[4].reg
;
7408 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7409 if (inst
.operands
[1].present
)
7411 inst
.instruction
|= CPSI_MMOD
;
7412 inst
.instruction
|= inst
.operands
[1].imm
;
7419 inst
.instruction
|= inst
.operands
[0].imm
;
7425 /* There is no IT instruction in ARM mode. We
7426 process it to do the validation as if in
7427 thumb mode, just in case the code gets
7428 assembled for thumb using the unified syntax. */
7433 set_it_insn_type (IT_INSN
);
7434 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7435 now_it
.cc
= inst
.operands
[0].imm
;
7442 int base_reg
= inst
.operands
[0].reg
;
7443 int range
= inst
.operands
[1].imm
;
7445 inst
.instruction
|= base_reg
<< 16;
7446 inst
.instruction
|= range
;
7448 if (inst
.operands
[1].writeback
)
7449 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7451 if (inst
.operands
[0].writeback
)
7453 inst
.instruction
|= WRITE_BACK
;
7454 /* Check for unpredictable uses of writeback. */
7455 if (inst
.instruction
& LOAD_BIT
)
7457 /* Not allowed in LDM type 2. */
7458 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7459 && ((range
& (1 << REG_PC
)) == 0))
7460 as_warn (_("writeback of base register is UNPREDICTABLE"));
7461 /* Only allowed if base reg not in list for other types. */
7462 else if (range
& (1 << base_reg
))
7463 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7467 /* Not allowed for type 2. */
7468 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7469 as_warn (_("writeback of base register is UNPREDICTABLE"));
7470 /* Only allowed if base reg not in list, or first in list. */
7471 else if ((range
& (1 << base_reg
))
7472 && (range
& ((1 << base_reg
) - 1)))
7473 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7478 /* ARMv5TE load-consecutive (argument parse)
7487 constraint (inst
.operands
[0].reg
% 2 != 0,
7488 _("first destination register must be even"));
7489 constraint (inst
.operands
[1].present
7490 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7491 _("can only load two consecutive registers"));
7492 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7493 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7495 if (!inst
.operands
[1].present
)
7496 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7498 if (inst
.instruction
& LOAD_BIT
)
7500 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7501 register and the first register written; we have to diagnose
7502 overlap between the base and the second register written here. */
7504 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7505 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7506 as_warn (_("base register written back, and overlaps "
7507 "second destination register"));
7509 /* For an index-register load, the index register must not overlap the
7510 destination (even if not write-back). */
7511 else if (inst
.operands
[2].immisreg
7512 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7513 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7514 as_warn (_("index register overlaps destination register"));
7517 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7518 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7524 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7525 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7526 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7527 || inst
.operands
[1].negative
7528 /* This can arise if the programmer has written
7530 or if they have mistakenly used a register name as the last
7533 It is very difficult to distinguish between these two cases
7534 because "rX" might actually be a label. ie the register
7535 name has been occluded by a symbol of the same name. So we
7536 just generate a general 'bad addressing mode' type error
7537 message and leave it up to the programmer to discover the
7538 true cause and fix their mistake. */
7539 || (inst
.operands
[1].reg
== REG_PC
),
7542 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7543 || inst
.reloc
.exp
.X_add_number
!= 0,
7544 _("offset must be zero in ARM encoding"));
7546 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7548 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7549 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7550 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7556 constraint (inst
.operands
[0].reg
% 2 != 0,
7557 _("even register required"));
7558 constraint (inst
.operands
[1].present
7559 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7560 _("can only load two consecutive registers"));
7561 /* If op 1 were present and equal to PC, this function wouldn't
7562 have been called in the first place. */
7563 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7565 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7566 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7572 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7573 if (!inst
.operands
[1].isreg
)
7574 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7576 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7582 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7584 if (inst
.operands
[1].preind
)
7586 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7587 || inst
.reloc
.exp
.X_add_number
!= 0,
7588 _("this instruction requires a post-indexed address"));
7590 inst
.operands
[1].preind
= 0;
7591 inst
.operands
[1].postind
= 1;
7592 inst
.operands
[1].writeback
= 1;
7594 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7595 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7598 /* Halfword and signed-byte load/store operations. */
7603 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7604 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7605 if (!inst
.operands
[1].isreg
)
7606 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7608 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7614 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7616 if (inst
.operands
[1].preind
)
7618 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7619 || inst
.reloc
.exp
.X_add_number
!= 0,
7620 _("this instruction requires a post-indexed address"));
7622 inst
.operands
[1].preind
= 0;
7623 inst
.operands
[1].postind
= 1;
7624 inst
.operands
[1].writeback
= 1;
7626 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7627 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7630 /* Co-processor register load/store.
7631 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7635 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7636 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7637 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7643 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7644 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7645 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7646 && !(inst
.instruction
& 0x00400000))
7647 as_tsktsk (_("Rd and Rm should be different in mla"));
7649 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7650 inst
.instruction
|= inst
.operands
[1].reg
;
7651 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7652 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7658 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7659 encode_arm_shifter_operand (1);
7662 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7669 top
= (inst
.instruction
& 0x00400000) != 0;
7670 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7671 _(":lower16: not allowed this instruction"));
7672 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7673 _(":upper16: not allowed instruction"));
7674 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7675 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7677 imm
= inst
.reloc
.exp
.X_add_number
;
7678 /* The value is in two pieces: 0:11, 16:19. */
7679 inst
.instruction
|= (imm
& 0x00000fff);
7680 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7684 static void do_vfp_nsyn_opcode (const char *);
7687 do_vfp_nsyn_mrs (void)
7689 if (inst
.operands
[0].isvec
)
7691 if (inst
.operands
[1].reg
!= 1)
7692 first_error (_("operand 1 must be FPSCR"));
7693 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7694 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7695 do_vfp_nsyn_opcode ("fmstat");
7697 else if (inst
.operands
[1].isvec
)
7698 do_vfp_nsyn_opcode ("fmrx");
7706 do_vfp_nsyn_msr (void)
7708 if (inst
.operands
[0].isvec
)
7709 do_vfp_nsyn_opcode ("fmxr");
7719 unsigned Rt
= inst
.operands
[0].reg
;
7721 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7723 inst
.error
= BAD_SP
;
7727 /* APSR_ sets isvec. All other refs to PC are illegal. */
7728 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7730 inst
.error
= BAD_PC
;
7734 if (inst
.operands
[1].reg
!= 1)
7735 first_error (_("operand 1 must be FPSCR"));
7737 inst
.instruction
|= (Rt
<< 12);
7743 unsigned Rt
= inst
.operands
[1].reg
;
7746 reject_bad_reg (Rt
);
7747 else if (Rt
== REG_PC
)
7749 inst
.error
= BAD_PC
;
7753 if (inst
.operands
[0].reg
!= 1)
7754 first_error (_("operand 0 must be FPSCR"));
7756 inst
.instruction
|= (Rt
<< 12);
7762 if (do_vfp_nsyn_mrs () == SUCCESS
)
7765 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7766 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7768 _("'CPSR' or 'SPSR' expected"));
7769 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7770 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7771 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7774 /* Two possible forms:
7775 "{C|S}PSR_<field>, Rm",
7776 "{C|S}PSR_f, #expression". */
7781 if (do_vfp_nsyn_msr () == SUCCESS
)
7784 inst
.instruction
|= inst
.operands
[0].imm
;
7785 if (inst
.operands
[1].isreg
)
7786 inst
.instruction
|= inst
.operands
[1].reg
;
7789 inst
.instruction
|= INST_IMMEDIATE
;
7790 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7791 inst
.reloc
.pc_rel
= 0;
7798 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7800 if (!inst
.operands
[2].present
)
7801 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7802 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7803 inst
.instruction
|= inst
.operands
[1].reg
;
7804 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7806 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7807 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7808 as_tsktsk (_("Rd and Rm should be different in mul"));
7811 /* Long Multiply Parser
7812 UMULL RdLo, RdHi, Rm, Rs
7813 SMULL RdLo, RdHi, Rm, Rs
7814 UMLAL RdLo, RdHi, Rm, Rs
7815 SMLAL RdLo, RdHi, Rm, Rs. */
7820 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7821 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7822 inst
.instruction
|= inst
.operands
[2].reg
;
7823 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7825 /* rdhi and rdlo must be different. */
7826 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7827 as_tsktsk (_("rdhi and rdlo must be different"));
7829 /* rdhi, rdlo and rm must all be different before armv6. */
7830 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7831 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7832 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7833 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7839 if (inst
.operands
[0].present
7840 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7842 /* Architectural NOP hints are CPSR sets with no bits selected. */
7843 inst
.instruction
&= 0xf0000000;
7844 inst
.instruction
|= 0x0320f000;
7845 if (inst
.operands
[0].present
)
7846 inst
.instruction
|= inst
.operands
[0].imm
;
7850 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7851 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7852 Condition defaults to COND_ALWAYS.
7853 Error if Rd, Rn or Rm are R15. */
7858 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7859 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7860 inst
.instruction
|= inst
.operands
[2].reg
;
7861 if (inst
.operands
[3].present
)
7862 encode_arm_shift (3);
7865 /* ARM V6 PKHTB (Argument Parse). */
7870 if (!inst
.operands
[3].present
)
7872 /* If the shift specifier is omitted, turn the instruction
7873 into pkhbt rd, rm, rn. */
7874 inst
.instruction
&= 0xfff00010;
7875 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7876 inst
.instruction
|= inst
.operands
[1].reg
;
7877 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7881 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7882 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7883 inst
.instruction
|= inst
.operands
[2].reg
;
7884 encode_arm_shift (3);
7888 /* ARMv5TE: Preload-Cache
7892 Syntactically, like LDR with B=1, W=0, L=1. */
7897 constraint (!inst
.operands
[0].isreg
,
7898 _("'[' expected after PLD mnemonic"));
7899 constraint (inst
.operands
[0].postind
,
7900 _("post-indexed expression used in preload instruction"));
7901 constraint (inst
.operands
[0].writeback
,
7902 _("writeback used in preload instruction"));
7903 constraint (!inst
.operands
[0].preind
,
7904 _("unindexed addressing used in preload instruction"));
7905 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7908 /* ARMv7: PLI <addr_mode> */
7912 constraint (!inst
.operands
[0].isreg
,
7913 _("'[' expected after PLI mnemonic"));
7914 constraint (inst
.operands
[0].postind
,
7915 _("post-indexed expression used in preload instruction"));
7916 constraint (inst
.operands
[0].writeback
,
7917 _("writeback used in preload instruction"));
7918 constraint (!inst
.operands
[0].preind
,
7919 _("unindexed addressing used in preload instruction"));
7920 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7921 inst
.instruction
&= ~PRE_INDEX
;
7927 inst
.operands
[1] = inst
.operands
[0];
7928 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7929 inst
.operands
[0].isreg
= 1;
7930 inst
.operands
[0].writeback
= 1;
7931 inst
.operands
[0].reg
= REG_SP
;
7935 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7936 word at the specified address and the following word
7938 Unconditionally executed.
7939 Error if Rn is R15. */
7944 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7945 if (inst
.operands
[0].writeback
)
7946 inst
.instruction
|= WRITE_BACK
;
7949 /* ARM V6 ssat (argument parse). */
7954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7955 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7956 inst
.instruction
|= inst
.operands
[2].reg
;
7958 if (inst
.operands
[3].present
)
7959 encode_arm_shift (3);
7962 /* ARM V6 usat (argument parse). */
7967 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7968 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7969 inst
.instruction
|= inst
.operands
[2].reg
;
7971 if (inst
.operands
[3].present
)
7972 encode_arm_shift (3);
7975 /* ARM V6 ssat16 (argument parse). */
7980 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7981 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7982 inst
.instruction
|= inst
.operands
[2].reg
;
7988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7989 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7990 inst
.instruction
|= inst
.operands
[2].reg
;
7993 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7994 preserving the other bits.
7996 setend <endian_specifier>, where <endian_specifier> is either
8002 if (inst
.operands
[0].imm
)
8003 inst
.instruction
|= 0x200;
8009 unsigned int Rm
= (inst
.operands
[1].present
8010 ? inst
.operands
[1].reg
8011 : inst
.operands
[0].reg
);
8013 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8014 inst
.instruction
|= Rm
;
8015 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8017 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8018 inst
.instruction
|= SHIFT_BY_REG
;
8021 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8027 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8028 inst
.reloc
.pc_rel
= 0;
8034 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8035 inst
.reloc
.pc_rel
= 0;
8038 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8039 SMLAxy{cond} Rd,Rm,Rs,Rn
8040 SMLAWy{cond} Rd,Rm,Rs,Rn
8041 Error if any register is R15. */
8046 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8047 inst
.instruction
|= inst
.operands
[1].reg
;
8048 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8049 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8052 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8053 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8054 Error if any register is R15.
8055 Warning if Rdlo == Rdhi. */
8060 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8061 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8062 inst
.instruction
|= inst
.operands
[2].reg
;
8063 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8065 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8066 as_tsktsk (_("rdhi and rdlo must be different"));
8069 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8070 SMULxy{cond} Rd,Rm,Rs
8071 Error if any register is R15. */
8076 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8077 inst
.instruction
|= inst
.operands
[1].reg
;
8078 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8081 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8082 the same for both ARM and Thumb-2. */
8089 if (inst
.operands
[0].present
)
8091 reg
= inst
.operands
[0].reg
;
8092 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8097 inst
.instruction
|= reg
<< 16;
8098 inst
.instruction
|= inst
.operands
[1].imm
;
8099 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8100 inst
.instruction
|= WRITE_BACK
;
8103 /* ARM V6 strex (argument parse). */
8108 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8109 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8110 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8111 || inst
.operands
[2].negative
8112 /* See comment in do_ldrex(). */
8113 || (inst
.operands
[2].reg
== REG_PC
),
8116 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8117 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8119 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8120 || inst
.reloc
.exp
.X_add_number
!= 0,
8121 _("offset must be zero in ARM encoding"));
8123 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8124 inst
.instruction
|= inst
.operands
[1].reg
;
8125 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8126 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8132 constraint (inst
.operands
[1].reg
% 2 != 0,
8133 _("even register required"));
8134 constraint (inst
.operands
[2].present
8135 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8136 _("can only store two consecutive registers"));
8137 /* If op 2 were present and equal to PC, this function wouldn't
8138 have been called in the first place. */
8139 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8141 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8142 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8143 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8146 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8147 inst
.instruction
|= inst
.operands
[1].reg
;
8148 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8151 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8152 extends it to 32-bits, and adds the result to a value in another
8153 register. You can specify a rotation by 0, 8, 16, or 24 bits
8154 before extracting the 16-bit value.
8155 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8156 Condition defaults to COND_ALWAYS.
8157 Error if any register uses R15. */
8162 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8163 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8164 inst
.instruction
|= inst
.operands
[2].reg
;
8165 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8170 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8171 Condition defaults to COND_ALWAYS.
8172 Error if any register uses R15. */
8177 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8178 inst
.instruction
|= inst
.operands
[1].reg
;
8179 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8182 /* VFP instructions. In a logical order: SP variant first, monad
8183 before dyad, arithmetic then move then load/store. */
8186 do_vfp_sp_monadic (void)
8188 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8189 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8193 do_vfp_sp_dyadic (void)
8195 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8196 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8197 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8201 do_vfp_sp_compare_z (void)
8203 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8207 do_vfp_dp_sp_cvt (void)
8209 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8210 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8214 do_vfp_sp_dp_cvt (void)
8216 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8217 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8221 do_vfp_reg_from_sp (void)
8223 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8224 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8228 do_vfp_reg2_from_sp2 (void)
8230 constraint (inst
.operands
[2].imm
!= 2,
8231 _("only two consecutive VFP SP registers allowed here"));
8232 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8233 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8234 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8238 do_vfp_sp_from_reg (void)
8240 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8241 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8245 do_vfp_sp2_from_reg2 (void)
8247 constraint (inst
.operands
[0].imm
!= 2,
8248 _("only two consecutive VFP SP registers allowed here"));
8249 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8250 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8251 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8255 do_vfp_sp_ldst (void)
8257 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8258 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8262 do_vfp_dp_ldst (void)
8264 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8265 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8270 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8272 if (inst
.operands
[0].writeback
)
8273 inst
.instruction
|= WRITE_BACK
;
8275 constraint (ldstm_type
!= VFP_LDSTMIA
,
8276 _("this addressing mode requires base-register writeback"));
8277 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8278 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8279 inst
.instruction
|= inst
.operands
[1].imm
;
8283 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8287 if (inst
.operands
[0].writeback
)
8288 inst
.instruction
|= WRITE_BACK
;
8290 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8291 _("this addressing mode requires base-register writeback"));
8293 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8294 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8296 count
= inst
.operands
[1].imm
<< 1;
8297 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8300 inst
.instruction
|= count
;
8304 do_vfp_sp_ldstmia (void)
8306 vfp_sp_ldstm (VFP_LDSTMIA
);
8310 do_vfp_sp_ldstmdb (void)
8312 vfp_sp_ldstm (VFP_LDSTMDB
);
8316 do_vfp_dp_ldstmia (void)
8318 vfp_dp_ldstm (VFP_LDSTMIA
);
8322 do_vfp_dp_ldstmdb (void)
8324 vfp_dp_ldstm (VFP_LDSTMDB
);
8328 do_vfp_xp_ldstmia (void)
8330 vfp_dp_ldstm (VFP_LDSTMIAX
);
8334 do_vfp_xp_ldstmdb (void)
8336 vfp_dp_ldstm (VFP_LDSTMDBX
);
8340 do_vfp_dp_rd_rm (void)
8342 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8343 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8347 do_vfp_dp_rn_rd (void)
8349 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8350 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8354 do_vfp_dp_rd_rn (void)
8356 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8357 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8361 do_vfp_dp_rd_rn_rm (void)
8363 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8364 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8365 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8371 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8375 do_vfp_dp_rm_rd_rn (void)
8377 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8378 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8379 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8382 /* VFPv3 instructions. */
8384 do_vfp_sp_const (void)
8386 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8387 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8388 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8392 do_vfp_dp_const (void)
8394 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8395 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8396 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8400 vfp_conv (int srcsize
)
8402 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8403 inst
.instruction
|= (immbits
& 1) << 5;
8404 inst
.instruction
|= (immbits
>> 1);
8408 do_vfp_sp_conv_16 (void)
8410 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8415 do_vfp_dp_conv_16 (void)
8417 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8422 do_vfp_sp_conv_32 (void)
8424 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8429 do_vfp_dp_conv_32 (void)
8431 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8435 /* FPA instructions. Also in a logical order. */
8440 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8441 inst
.instruction
|= inst
.operands
[1].reg
;
8445 do_fpa_ldmstm (void)
8447 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8448 switch (inst
.operands
[1].imm
)
8450 case 1: inst
.instruction
|= CP_T_X
; break;
8451 case 2: inst
.instruction
|= CP_T_Y
; break;
8452 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8457 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8459 /* The instruction specified "ea" or "fd", so we can only accept
8460 [Rn]{!}. The instruction does not really support stacking or
8461 unstacking, so we have to emulate these by setting appropriate
8462 bits and offsets. */
8463 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8464 || inst
.reloc
.exp
.X_add_number
!= 0,
8465 _("this instruction does not support indexing"));
8467 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8468 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8470 if (!(inst
.instruction
& INDEX_UP
))
8471 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8473 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8475 inst
.operands
[2].preind
= 0;
8476 inst
.operands
[2].postind
= 1;
8480 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8483 /* iWMMXt instructions: strictly in alphabetical order. */
8486 do_iwmmxt_tandorc (void)
8488 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8492 do_iwmmxt_textrc (void)
8494 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8495 inst
.instruction
|= inst
.operands
[1].imm
;
8499 do_iwmmxt_textrm (void)
8501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8502 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8503 inst
.instruction
|= inst
.operands
[2].imm
;
8507 do_iwmmxt_tinsr (void)
8509 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8510 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8511 inst
.instruction
|= inst
.operands
[2].imm
;
8515 do_iwmmxt_tmia (void)
8517 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8518 inst
.instruction
|= inst
.operands
[1].reg
;
8519 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8523 do_iwmmxt_waligni (void)
8525 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8526 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8527 inst
.instruction
|= inst
.operands
[2].reg
;
8528 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8532 do_iwmmxt_wmerge (void)
8534 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8535 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8536 inst
.instruction
|= inst
.operands
[2].reg
;
8537 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8541 do_iwmmxt_wmov (void)
8543 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8544 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8545 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8546 inst
.instruction
|= inst
.operands
[1].reg
;
8550 do_iwmmxt_wldstbh (void)
8553 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8555 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8557 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8558 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8562 do_iwmmxt_wldstw (void)
8564 /* RIWR_RIWC clears .isreg for a control register. */
8565 if (!inst
.operands
[0].isreg
)
8567 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8568 inst
.instruction
|= 0xf0000000;
8571 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8572 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8576 do_iwmmxt_wldstd (void)
8578 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8579 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8580 && inst
.operands
[1].immisreg
)
8582 inst
.instruction
&= ~0x1a000ff;
8583 inst
.instruction
|= (0xf << 28);
8584 if (inst
.operands
[1].preind
)
8585 inst
.instruction
|= PRE_INDEX
;
8586 if (!inst
.operands
[1].negative
)
8587 inst
.instruction
|= INDEX_UP
;
8588 if (inst
.operands
[1].writeback
)
8589 inst
.instruction
|= WRITE_BACK
;
8590 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8591 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8592 inst
.instruction
|= inst
.operands
[1].imm
;
8595 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8599 do_iwmmxt_wshufh (void)
8601 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8602 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8603 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8604 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8608 do_iwmmxt_wzero (void)
8610 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8611 inst
.instruction
|= inst
.operands
[0].reg
;
8612 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8613 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8617 do_iwmmxt_wrwrwr_or_imm5 (void)
8619 if (inst
.operands
[2].isreg
)
8622 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8623 _("immediate operand requires iWMMXt2"));
8625 if (inst
.operands
[2].imm
== 0)
8627 switch ((inst
.instruction
>> 20) & 0xf)
8633 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8634 inst
.operands
[2].imm
= 16;
8635 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8641 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8642 inst
.operands
[2].imm
= 32;
8643 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8650 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8652 wrn
= (inst
.instruction
>> 16) & 0xf;
8653 inst
.instruction
&= 0xff0fff0f;
8654 inst
.instruction
|= wrn
;
8655 /* Bail out here; the instruction is now assembled. */
8660 /* Map 32 -> 0, etc. */
8661 inst
.operands
[2].imm
&= 0x1f;
8662 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8666 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8667 operations first, then control, shift, and load/store. */
8669 /* Insns like "foo X,Y,Z". */
8672 do_mav_triple (void)
8674 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8675 inst
.instruction
|= inst
.operands
[1].reg
;
8676 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8679 /* Insns like "foo W,X,Y,Z".
8680 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8685 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8686 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8687 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8688 inst
.instruction
|= inst
.operands
[3].reg
;
8691 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8695 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8698 /* Maverick shift immediate instructions.
8699 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8700 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8705 int imm
= inst
.operands
[2].imm
;
8707 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8708 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8710 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8711 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8712 Bit 4 should be 0. */
8713 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8715 inst
.instruction
|= imm
;
8718 /* XScale instructions. Also sorted arithmetic before move. */
8720 /* Xscale multiply-accumulate (argument parse)
8723 MIAxycc acc0,Rm,Rs. */
8728 inst
.instruction
|= inst
.operands
[1].reg
;
8729 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8732 /* Xscale move-accumulator-register (argument parse)
8734 MARcc acc0,RdLo,RdHi. */
8739 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8740 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8743 /* Xscale move-register-accumulator (argument parse)
8745 MRAcc RdLo,RdHi,acc0. */
8750 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8751 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8752 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8755 /* Encoding functions relevant only to Thumb. */
8757 /* inst.operands[i] is a shifted-register operand; encode
8758 it into inst.instruction in the format used by Thumb32. */
8761 encode_thumb32_shifted_operand (int i
)
8763 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8764 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8766 constraint (inst
.operands
[i
].immisreg
,
8767 _("shift by register not allowed in thumb mode"));
8768 inst
.instruction
|= inst
.operands
[i
].reg
;
8769 if (shift
== SHIFT_RRX
)
8770 inst
.instruction
|= SHIFT_ROR
<< 4;
8773 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8774 _("expression too complex"));
8776 constraint (value
> 32
8777 || (value
== 32 && (shift
== SHIFT_LSL
8778 || shift
== SHIFT_ROR
)),
8779 _("shift expression is too large"));
8783 else if (value
== 32)
8786 inst
.instruction
|= shift
<< 4;
8787 inst
.instruction
|= (value
& 0x1c) << 10;
8788 inst
.instruction
|= (value
& 0x03) << 6;
8793 /* inst.operands[i] was set up by parse_address. Encode it into a
8794 Thumb32 format load or store instruction. Reject forms that cannot
8795 be used with such instructions. If is_t is true, reject forms that
8796 cannot be used with a T instruction; if is_d is true, reject forms
8797 that cannot be used with a D instruction. If it is a store insn,
8801 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8803 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8805 constraint (!inst
.operands
[i
].isreg
,
8806 _("Instruction does not support =N addresses"));
8808 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8809 if (inst
.operands
[i
].immisreg
)
8811 constraint (is_pc
, BAD_PC_ADDRESSING
);
8812 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8813 constraint (inst
.operands
[i
].negative
,
8814 _("Thumb does not support negative register indexing"));
8815 constraint (inst
.operands
[i
].postind
,
8816 _("Thumb does not support register post-indexing"));
8817 constraint (inst
.operands
[i
].writeback
,
8818 _("Thumb does not support register indexing with writeback"));
8819 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8820 _("Thumb supports only LSL in shifted register indexing"));
8822 inst
.instruction
|= inst
.operands
[i
].imm
;
8823 if (inst
.operands
[i
].shifted
)
8825 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8826 _("expression too complex"));
8827 constraint (inst
.reloc
.exp
.X_add_number
< 0
8828 || inst
.reloc
.exp
.X_add_number
> 3,
8829 _("shift out of range"));
8830 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8832 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8834 else if (inst
.operands
[i
].preind
)
8836 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
8837 constraint (is_t
&& inst
.operands
[i
].writeback
,
8838 _("cannot use writeback with this instruction"));
8839 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
8840 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
8844 inst
.instruction
|= 0x01000000;
8845 if (inst
.operands
[i
].writeback
)
8846 inst
.instruction
|= 0x00200000;
8850 inst
.instruction
|= 0x00000c00;
8851 if (inst
.operands
[i
].writeback
)
8852 inst
.instruction
|= 0x00000100;
8854 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8856 else if (inst
.operands
[i
].postind
)
8858 gas_assert (inst
.operands
[i
].writeback
);
8859 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8860 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8863 inst
.instruction
|= 0x00200000;
8865 inst
.instruction
|= 0x00000900;
8866 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8868 else /* unindexed - only for coprocessor */
8869 inst
.error
= _("instruction does not accept unindexed addressing");
8872 /* Table of Thumb instructions which exist in both 16- and 32-bit
8873 encodings (the latter only in post-V6T2 cores). The index is the
8874 value used in the insns table below. When there is more than one
8875 possible 16-bit encoding for the instruction, this table always
8877 Also contains several pseudo-instructions used during relaxation. */
8878 #define T16_32_TAB \
8879 X(_adc, 4140, eb400000), \
8880 X(_adcs, 4140, eb500000), \
8881 X(_add, 1c00, eb000000), \
8882 X(_adds, 1c00, eb100000), \
8883 X(_addi, 0000, f1000000), \
8884 X(_addis, 0000, f1100000), \
8885 X(_add_pc,000f, f20f0000), \
8886 X(_add_sp,000d, f10d0000), \
8887 X(_adr, 000f, f20f0000), \
8888 X(_and, 4000, ea000000), \
8889 X(_ands, 4000, ea100000), \
8890 X(_asr, 1000, fa40f000), \
8891 X(_asrs, 1000, fa50f000), \
8892 X(_b, e000, f000b000), \
8893 X(_bcond, d000, f0008000), \
8894 X(_bic, 4380, ea200000), \
8895 X(_bics, 4380, ea300000), \
8896 X(_cmn, 42c0, eb100f00), \
8897 X(_cmp, 2800, ebb00f00), \
8898 X(_cpsie, b660, f3af8400), \
8899 X(_cpsid, b670, f3af8600), \
8900 X(_cpy, 4600, ea4f0000), \
8901 X(_dec_sp,80dd, f1ad0d00), \
8902 X(_eor, 4040, ea800000), \
8903 X(_eors, 4040, ea900000), \
8904 X(_inc_sp,00dd, f10d0d00), \
8905 X(_ldmia, c800, e8900000), \
8906 X(_ldr, 6800, f8500000), \
8907 X(_ldrb, 7800, f8100000), \
8908 X(_ldrh, 8800, f8300000), \
8909 X(_ldrsb, 5600, f9100000), \
8910 X(_ldrsh, 5e00, f9300000), \
8911 X(_ldr_pc,4800, f85f0000), \
8912 X(_ldr_pc2,4800, f85f0000), \
8913 X(_ldr_sp,9800, f85d0000), \
8914 X(_lsl, 0000, fa00f000), \
8915 X(_lsls, 0000, fa10f000), \
8916 X(_lsr, 0800, fa20f000), \
8917 X(_lsrs, 0800, fa30f000), \
8918 X(_mov, 2000, ea4f0000), \
8919 X(_movs, 2000, ea5f0000), \
8920 X(_mul, 4340, fb00f000), \
8921 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8922 X(_mvn, 43c0, ea6f0000), \
8923 X(_mvns, 43c0, ea7f0000), \
8924 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8925 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8926 X(_orr, 4300, ea400000), \
8927 X(_orrs, 4300, ea500000), \
8928 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8929 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8930 X(_rev, ba00, fa90f080), \
8931 X(_rev16, ba40, fa90f090), \
8932 X(_revsh, bac0, fa90f0b0), \
8933 X(_ror, 41c0, fa60f000), \
8934 X(_rors, 41c0, fa70f000), \
8935 X(_sbc, 4180, eb600000), \
8936 X(_sbcs, 4180, eb700000), \
8937 X(_stmia, c000, e8800000), \
8938 X(_str, 6000, f8400000), \
8939 X(_strb, 7000, f8000000), \
8940 X(_strh, 8000, f8200000), \
8941 X(_str_sp,9000, f84d0000), \
8942 X(_sub, 1e00, eba00000), \
8943 X(_subs, 1e00, ebb00000), \
8944 X(_subi, 8000, f1a00000), \
8945 X(_subis, 8000, f1b00000), \
8946 X(_sxtb, b240, fa4ff080), \
8947 X(_sxth, b200, fa0ff080), \
8948 X(_tst, 4200, ea100f00), \
8949 X(_uxtb, b2c0, fa5ff080), \
8950 X(_uxth, b280, fa1ff080), \
8951 X(_nop, bf00, f3af8000), \
8952 X(_yield, bf10, f3af8001), \
8953 X(_wfe, bf20, f3af8002), \
8954 X(_wfi, bf30, f3af8003), \
8955 X(_sev, bf40, f3af8004),
8957 /* To catch errors in encoding functions, the codes are all offset by
8958 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8959 as 16-bit instructions. */
8960 #define X(a,b,c) T_MNEM##a
8961 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8964 #define X(a,b,c) 0x##b
8965 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8966 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8969 #define X(a,b,c) 0x##c
8970 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8971 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8972 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8976 /* Thumb instruction encoders, in alphabetical order. */
8981 do_t_add_sub_w (void)
8985 Rd
= inst
.operands
[0].reg
;
8986 Rn
= inst
.operands
[1].reg
;
8988 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
8989 is the SP-{plus,minus}-immediate form of the instruction. */
8991 constraint (Rd
== REG_PC
, BAD_PC
);
8993 reject_bad_reg (Rd
);
8995 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8996 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8999 /* Parse an add or subtract instruction. We get here with inst.instruction
9000 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9007 Rd
= inst
.operands
[0].reg
;
9008 Rs
= (inst
.operands
[1].present
9009 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9010 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9013 set_it_insn_type_last ();
9021 flags
= (inst
.instruction
== T_MNEM_adds
9022 || inst
.instruction
== T_MNEM_subs
);
9024 narrow
= !in_it_block ();
9026 narrow
= in_it_block ();
9027 if (!inst
.operands
[2].isreg
)
9031 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9033 add
= (inst
.instruction
== T_MNEM_add
9034 || inst
.instruction
== T_MNEM_adds
);
9036 if (inst
.size_req
!= 4)
9038 /* Attempt to use a narrow opcode, with relaxation if
9040 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9041 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9042 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9043 opcode
= T_MNEM_add_sp
;
9044 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9045 opcode
= T_MNEM_add_pc
;
9046 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9049 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9051 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9055 inst
.instruction
= THUMB_OP16(opcode
);
9056 inst
.instruction
|= (Rd
<< 4) | Rs
;
9057 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9058 if (inst
.size_req
!= 2)
9059 inst
.relax
= opcode
;
9062 constraint (inst
.size_req
== 2, BAD_HIREG
);
9064 if (inst
.size_req
== 4
9065 || (inst
.size_req
!= 2 && !opcode
))
9069 constraint (add
, BAD_PC
);
9070 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9071 _("only SUBS PC, LR, #const allowed"));
9072 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9073 _("expression too complex"));
9074 constraint (inst
.reloc
.exp
.X_add_number
< 0
9075 || inst
.reloc
.exp
.X_add_number
> 0xff,
9076 _("immediate value out of range"));
9077 inst
.instruction
= T2_SUBS_PC_LR
9078 | inst
.reloc
.exp
.X_add_number
;
9079 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9082 else if (Rs
== REG_PC
)
9084 /* Always use addw/subw. */
9085 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9086 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9090 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9091 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9094 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9096 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9098 inst
.instruction
|= Rd
<< 8;
9099 inst
.instruction
|= Rs
<< 16;
9104 Rn
= inst
.operands
[2].reg
;
9105 /* See if we can do this with a 16-bit instruction. */
9106 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9108 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9113 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9114 || inst
.instruction
== T_MNEM_add
)
9117 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9121 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9123 /* Thumb-1 cores (except v6-M) require at least one high
9124 register in a narrow non flag setting add. */
9125 if (Rd
> 7 || Rn
> 7
9126 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9127 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9134 inst
.instruction
= T_OPCODE_ADD_HI
;
9135 inst
.instruction
|= (Rd
& 8) << 4;
9136 inst
.instruction
|= (Rd
& 7);
9137 inst
.instruction
|= Rn
<< 3;
9143 constraint (Rd
== REG_PC
, BAD_PC
);
9144 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9145 constraint (Rs
== REG_PC
, BAD_PC
);
9146 reject_bad_reg (Rn
);
9148 /* If we get here, it can't be done in 16 bits. */
9149 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9150 _("shift must be constant"));
9151 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9152 inst
.instruction
|= Rd
<< 8;
9153 inst
.instruction
|= Rs
<< 16;
9154 encode_thumb32_shifted_operand (2);
9159 constraint (inst
.instruction
== T_MNEM_adds
9160 || inst
.instruction
== T_MNEM_subs
,
9163 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9165 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9166 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9169 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9171 inst
.instruction
|= (Rd
<< 4) | Rs
;
9172 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9176 Rn
= inst
.operands
[2].reg
;
9177 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9179 /* We now have Rd, Rs, and Rn set to registers. */
9180 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9182 /* Can't do this for SUB. */
9183 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9184 inst
.instruction
= T_OPCODE_ADD_HI
;
9185 inst
.instruction
|= (Rd
& 8) << 4;
9186 inst
.instruction
|= (Rd
& 7);
9188 inst
.instruction
|= Rn
<< 3;
9190 inst
.instruction
|= Rs
<< 3;
9192 constraint (1, _("dest must overlap one source register"));
9196 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9197 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9198 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9208 Rd
= inst
.operands
[0].reg
;
9209 reject_bad_reg (Rd
);
9211 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9213 /* Defer to section relaxation. */
9214 inst
.relax
= inst
.instruction
;
9215 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9216 inst
.instruction
|= Rd
<< 4;
9218 else if (unified_syntax
&& inst
.size_req
!= 2)
9220 /* Generate a 32-bit opcode. */
9221 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9222 inst
.instruction
|= Rd
<< 8;
9223 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9224 inst
.reloc
.pc_rel
= 1;
9228 /* Generate a 16-bit opcode. */
9229 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9230 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9231 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9232 inst
.reloc
.pc_rel
= 1;
9234 inst
.instruction
|= Rd
<< 4;
9238 /* Arithmetic instructions for which there is just one 16-bit
9239 instruction encoding, and it allows only two low registers.
9240 For maximal compatibility with ARM syntax, we allow three register
9241 operands even when Thumb-32 instructions are not available, as long
9242 as the first two are identical. For instance, both "sbc r0,r1" and
9243 "sbc r0,r0,r1" are allowed. */
9249 Rd
= inst
.operands
[0].reg
;
9250 Rs
= (inst
.operands
[1].present
9251 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9252 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9253 Rn
= inst
.operands
[2].reg
;
9255 reject_bad_reg (Rd
);
9256 reject_bad_reg (Rs
);
9257 if (inst
.operands
[2].isreg
)
9258 reject_bad_reg (Rn
);
9262 if (!inst
.operands
[2].isreg
)
9264 /* For an immediate, we always generate a 32-bit opcode;
9265 section relaxation will shrink it later if possible. */
9266 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9267 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9268 inst
.instruction
|= Rd
<< 8;
9269 inst
.instruction
|= Rs
<< 16;
9270 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9276 /* See if we can do this with a 16-bit instruction. */
9277 if (THUMB_SETS_FLAGS (inst
.instruction
))
9278 narrow
= !in_it_block ();
9280 narrow
= in_it_block ();
9282 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9284 if (inst
.operands
[2].shifted
)
9286 if (inst
.size_req
== 4)
9292 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9293 inst
.instruction
|= Rd
;
9294 inst
.instruction
|= Rn
<< 3;
9298 /* If we get here, it can't be done in 16 bits. */
9299 constraint (inst
.operands
[2].shifted
9300 && inst
.operands
[2].immisreg
,
9301 _("shift must be constant"));
9302 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9303 inst
.instruction
|= Rd
<< 8;
9304 inst
.instruction
|= Rs
<< 16;
9305 encode_thumb32_shifted_operand (2);
9310 /* On its face this is a lie - the instruction does set the
9311 flags. However, the only supported mnemonic in this mode
9313 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9315 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9316 _("unshifted register required"));
9317 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9318 constraint (Rd
!= Rs
,
9319 _("dest and source1 must be the same register"));
9321 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9322 inst
.instruction
|= Rd
;
9323 inst
.instruction
|= Rn
<< 3;
9327 /* Similarly, but for instructions where the arithmetic operation is
9328 commutative, so we can allow either of them to be different from
9329 the destination operand in a 16-bit instruction. For instance, all
9330 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9337 Rd
= inst
.operands
[0].reg
;
9338 Rs
= (inst
.operands
[1].present
9339 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9340 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9341 Rn
= inst
.operands
[2].reg
;
9343 reject_bad_reg (Rd
);
9344 reject_bad_reg (Rs
);
9345 if (inst
.operands
[2].isreg
)
9346 reject_bad_reg (Rn
);
9350 if (!inst
.operands
[2].isreg
)
9352 /* For an immediate, we always generate a 32-bit opcode;
9353 section relaxation will shrink it later if possible. */
9354 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9355 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9356 inst
.instruction
|= Rd
<< 8;
9357 inst
.instruction
|= Rs
<< 16;
9358 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9364 /* See if we can do this with a 16-bit instruction. */
9365 if (THUMB_SETS_FLAGS (inst
.instruction
))
9366 narrow
= !in_it_block ();
9368 narrow
= in_it_block ();
9370 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9372 if (inst
.operands
[2].shifted
)
9374 if (inst
.size_req
== 4)
9381 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9382 inst
.instruction
|= Rd
;
9383 inst
.instruction
|= Rn
<< 3;
9388 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9389 inst
.instruction
|= Rd
;
9390 inst
.instruction
|= Rs
<< 3;
9395 /* If we get here, it can't be done in 16 bits. */
9396 constraint (inst
.operands
[2].shifted
9397 && inst
.operands
[2].immisreg
,
9398 _("shift must be constant"));
9399 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9400 inst
.instruction
|= Rd
<< 8;
9401 inst
.instruction
|= Rs
<< 16;
9402 encode_thumb32_shifted_operand (2);
9407 /* On its face this is a lie - the instruction does set the
9408 flags. However, the only supported mnemonic in this mode
9410 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9412 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9413 _("unshifted register required"));
9414 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9416 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9417 inst
.instruction
|= Rd
;
9420 inst
.instruction
|= Rn
<< 3;
9422 inst
.instruction
|= Rs
<< 3;
9424 constraint (1, _("dest must overlap one source register"));
9431 if (inst
.operands
[0].present
)
9433 constraint ((inst
.instruction
& 0xf0) != 0x40
9434 && inst
.operands
[0].imm
!= 0xf,
9435 _("bad barrier type"));
9436 inst
.instruction
|= inst
.operands
[0].imm
;
9439 inst
.instruction
|= 0xf;
9446 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9447 constraint (msb
> 32, _("bit-field extends past end of register"));
9448 /* The instruction encoding stores the LSB and MSB,
9449 not the LSB and width. */
9450 Rd
= inst
.operands
[0].reg
;
9451 reject_bad_reg (Rd
);
9452 inst
.instruction
|= Rd
<< 8;
9453 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9454 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9455 inst
.instruction
|= msb
- 1;
9464 Rd
= inst
.operands
[0].reg
;
9465 reject_bad_reg (Rd
);
9467 /* #0 in second position is alternative syntax for bfc, which is
9468 the same instruction but with REG_PC in the Rm field. */
9469 if (!inst
.operands
[1].isreg
)
9473 Rn
= inst
.operands
[1].reg
;
9474 reject_bad_reg (Rn
);
9477 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9478 constraint (msb
> 32, _("bit-field extends past end of register"));
9479 /* The instruction encoding stores the LSB and MSB,
9480 not the LSB and width. */
9481 inst
.instruction
|= Rd
<< 8;
9482 inst
.instruction
|= Rn
<< 16;
9483 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9484 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9485 inst
.instruction
|= msb
- 1;
9493 Rd
= inst
.operands
[0].reg
;
9494 Rn
= inst
.operands
[1].reg
;
9496 reject_bad_reg (Rd
);
9497 reject_bad_reg (Rn
);
9499 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9500 _("bit-field extends past end of register"));
9501 inst
.instruction
|= Rd
<< 8;
9502 inst
.instruction
|= Rn
<< 16;
9503 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9504 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9505 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9508 /* ARM V5 Thumb BLX (argument parse)
9509 BLX <target_addr> which is BLX(1)
9510 BLX <Rm> which is BLX(2)
9511 Unfortunately, there are two different opcodes for this mnemonic.
9512 So, the insns[].value is not used, and the code here zaps values
9513 into inst.instruction.
9515 ??? How to take advantage of the additional two bits of displacement
9516 available in Thumb32 mode? Need new relocation? */
9521 set_it_insn_type_last ();
9523 if (inst
.operands
[0].isreg
)
9525 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9526 /* We have a register, so this is BLX(2). */
9527 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9531 /* No register. This must be BLX(1). */
9532 inst
.instruction
= 0xf000e800;
9533 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9534 inst
.reloc
.pc_rel
= 1;
9545 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9549 /* Conditional branches inside IT blocks are encoded as unconditional
9556 if (cond
!= COND_ALWAYS
)
9557 opcode
= T_MNEM_bcond
;
9559 opcode
= inst
.instruction
;
9561 if (unified_syntax
&& inst
.size_req
== 4)
9563 inst
.instruction
= THUMB_OP32(opcode
);
9564 if (cond
== COND_ALWAYS
)
9565 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9568 gas_assert (cond
!= 0xF);
9569 inst
.instruction
|= cond
<< 22;
9570 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9575 inst
.instruction
= THUMB_OP16(opcode
);
9576 if (cond
== COND_ALWAYS
)
9577 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9580 inst
.instruction
|= cond
<< 8;
9581 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9583 /* Allow section relaxation. */
9584 if (unified_syntax
&& inst
.size_req
!= 2)
9585 inst
.relax
= opcode
;
9588 inst
.reloc
.pc_rel
= 1;
9594 constraint (inst
.cond
!= COND_ALWAYS
,
9595 _("instruction is always unconditional"));
9596 if (inst
.operands
[0].present
)
9598 constraint (inst
.operands
[0].imm
> 255,
9599 _("immediate value out of range"));
9600 inst
.instruction
|= inst
.operands
[0].imm
;
9601 set_it_insn_type (NEUTRAL_IT_INSN
);
9606 do_t_branch23 (void)
9608 set_it_insn_type_last ();
9609 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9610 inst
.reloc
.pc_rel
= 1;
9612 #if defined(OBJ_COFF)
9613 /* If the destination of the branch is a defined symbol which does not have
9614 the THUMB_FUNC attribute, then we must be calling a function which has
9615 the (interfacearm) attribute. We look for the Thumb entry point to that
9616 function and change the branch to refer to that function instead. */
9617 if ( inst
.reloc
.exp
.X_op
== O_symbol
9618 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9619 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9620 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9621 inst
.reloc
.exp
.X_add_symbol
=
9622 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9629 set_it_insn_type_last ();
9630 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9631 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9632 should cause the alignment to be checked once it is known. This is
9633 because BX PC only works if the instruction is word aligned. */
9641 set_it_insn_type_last ();
9642 Rm
= inst
.operands
[0].reg
;
9643 reject_bad_reg (Rm
);
9644 inst
.instruction
|= Rm
<< 16;
9653 Rd
= inst
.operands
[0].reg
;
9654 Rm
= inst
.operands
[1].reg
;
9656 reject_bad_reg (Rd
);
9657 reject_bad_reg (Rm
);
9659 inst
.instruction
|= Rd
<< 8;
9660 inst
.instruction
|= Rm
<< 16;
9661 inst
.instruction
|= Rm
;
9667 set_it_insn_type (OUTSIDE_IT_INSN
);
9668 inst
.instruction
|= inst
.operands
[0].imm
;
9674 set_it_insn_type (OUTSIDE_IT_INSN
);
9676 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9677 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9679 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9680 inst
.instruction
= 0xf3af8000;
9681 inst
.instruction
|= imod
<< 9;
9682 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9683 if (inst
.operands
[1].present
)
9684 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9688 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9689 && (inst
.operands
[0].imm
& 4),
9690 _("selected processor does not support 'A' form "
9691 "of this instruction"));
9692 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9693 _("Thumb does not support the 2-argument "
9694 "form of this instruction"));
9695 inst
.instruction
|= inst
.operands
[0].imm
;
9699 /* THUMB CPY instruction (argument parse). */
9704 if (inst
.size_req
== 4)
9706 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9707 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9708 inst
.instruction
|= inst
.operands
[1].reg
;
9712 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9713 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9714 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9721 set_it_insn_type (OUTSIDE_IT_INSN
);
9722 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9723 inst
.instruction
|= inst
.operands
[0].reg
;
9724 inst
.reloc
.pc_rel
= 1;
9725 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9731 inst
.instruction
|= inst
.operands
[0].imm
;
9737 unsigned Rd
, Rn
, Rm
;
9739 Rd
= inst
.operands
[0].reg
;
9740 Rn
= (inst
.operands
[1].present
9741 ? inst
.operands
[1].reg
: Rd
);
9742 Rm
= inst
.operands
[2].reg
;
9744 reject_bad_reg (Rd
);
9745 reject_bad_reg (Rn
);
9746 reject_bad_reg (Rm
);
9748 inst
.instruction
|= Rd
<< 8;
9749 inst
.instruction
|= Rn
<< 16;
9750 inst
.instruction
|= Rm
;
9756 if (unified_syntax
&& inst
.size_req
== 4)
9757 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9759 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9765 unsigned int cond
= inst
.operands
[0].imm
;
9767 set_it_insn_type (IT_INSN
);
9768 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9771 /* If the condition is a negative condition, invert the mask. */
9772 if ((cond
& 0x1) == 0x0)
9774 unsigned int mask
= inst
.instruction
& 0x000f;
9776 if ((mask
& 0x7) == 0)
9777 /* no conversion needed */;
9778 else if ((mask
& 0x3) == 0)
9780 else if ((mask
& 0x1) == 0)
9785 inst
.instruction
&= 0xfff0;
9786 inst
.instruction
|= mask
;
9789 inst
.instruction
|= cond
<< 4;
9792 /* Helper function used for both push/pop and ldm/stm. */
9794 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9798 load
= (inst
.instruction
& (1 << 20)) != 0;
9800 if (mask
& (1 << 13))
9801 inst
.error
= _("SP not allowed in register list");
9803 if ((mask
& (1 << base
)) != 0
9805 inst
.error
= _("having the base register in the register list when "
9806 "using write back is UNPREDICTABLE");
9810 if (mask
& (1 << 15))
9812 if (mask
& (1 << 14))
9813 inst
.error
= _("LR and PC should not both be in register list");
9815 set_it_insn_type_last ();
9820 if (mask
& (1 << 15))
9821 inst
.error
= _("PC not allowed in register list");
9824 if ((mask
& (mask
- 1)) == 0)
9826 /* Single register transfers implemented as str/ldr. */
9829 if (inst
.instruction
& (1 << 23))
9830 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9832 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9836 if (inst
.instruction
& (1 << 23))
9837 inst
.instruction
= 0x00800000; /* ia -> [base] */
9839 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9842 inst
.instruction
|= 0xf8400000;
9844 inst
.instruction
|= 0x00100000;
9846 mask
= ffs (mask
) - 1;
9850 inst
.instruction
|= WRITE_BACK
;
9852 inst
.instruction
|= mask
;
9853 inst
.instruction
|= base
<< 16;
9859 /* This really doesn't seem worth it. */
9860 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9861 _("expression too complex"));
9862 constraint (inst
.operands
[1].writeback
,
9863 _("Thumb load/store multiple does not support {reglist}^"));
9871 /* See if we can use a 16-bit instruction. */
9872 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9873 && inst
.size_req
!= 4
9874 && !(inst
.operands
[1].imm
& ~0xff))
9876 mask
= 1 << inst
.operands
[0].reg
;
9878 if (inst
.operands
[0].reg
<= 7
9879 && (inst
.instruction
== T_MNEM_stmia
9880 ? inst
.operands
[0].writeback
9881 : (inst
.operands
[0].writeback
9882 == !(inst
.operands
[1].imm
& mask
))))
9884 if (inst
.instruction
== T_MNEM_stmia
9885 && (inst
.operands
[1].imm
& mask
)
9886 && (inst
.operands
[1].imm
& (mask
- 1)))
9887 as_warn (_("value stored for r%d is UNKNOWN"),
9888 inst
.operands
[0].reg
);
9890 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9891 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9892 inst
.instruction
|= inst
.operands
[1].imm
;
9895 else if (inst
.operands
[0] .reg
== REG_SP
9896 && inst
.operands
[0].writeback
)
9898 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9899 ? T_MNEM_push
: T_MNEM_pop
);
9900 inst
.instruction
|= inst
.operands
[1].imm
;
9907 if (inst
.instruction
< 0xffff)
9908 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9910 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9911 inst
.operands
[0].writeback
);
9916 constraint (inst
.operands
[0].reg
> 7
9917 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9918 constraint (inst
.instruction
!= T_MNEM_ldmia
9919 && inst
.instruction
!= T_MNEM_stmia
,
9920 _("Thumb-2 instruction only valid in unified syntax"));
9921 if (inst
.instruction
== T_MNEM_stmia
)
9923 if (!inst
.operands
[0].writeback
)
9924 as_warn (_("this instruction will write back the base register"));
9925 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9926 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9927 as_warn (_("value stored for r%d is UNKNOWN"),
9928 inst
.operands
[0].reg
);
9932 if (!inst
.operands
[0].writeback
9933 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9934 as_warn (_("this instruction will write back the base register"));
9935 else if (inst
.operands
[0].writeback
9936 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9937 as_warn (_("this instruction will not write back the base register"));
9940 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9941 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9942 inst
.instruction
|= inst
.operands
[1].imm
;
9949 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9950 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9951 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9952 || inst
.operands
[1].negative
,
9955 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9957 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9958 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9959 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9965 if (!inst
.operands
[1].present
)
9967 constraint (inst
.operands
[0].reg
== REG_LR
,
9968 _("r14 not allowed as first register "
9969 "when second register is omitted"));
9970 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9972 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9975 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9976 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9977 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9983 unsigned long opcode
;
9986 if (inst
.operands
[0].isreg
9987 && !inst
.operands
[0].preind
9988 && inst
.operands
[0].reg
== REG_PC
)
9989 set_it_insn_type_last ();
9991 opcode
= inst
.instruction
;
9994 if (!inst
.operands
[1].isreg
)
9996 if (opcode
<= 0xffff)
9997 inst
.instruction
= THUMB_OP32 (opcode
);
9998 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10001 if (inst
.operands
[1].isreg
10002 && !inst
.operands
[1].writeback
10003 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10004 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10005 && opcode
<= 0xffff
10006 && inst
.size_req
!= 4)
10008 /* Insn may have a 16-bit form. */
10009 Rn
= inst
.operands
[1].reg
;
10010 if (inst
.operands
[1].immisreg
)
10012 inst
.instruction
= THUMB_OP16 (opcode
);
10014 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10016 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10017 reject_bad_reg (inst
.operands
[1].imm
);
10019 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10020 && opcode
!= T_MNEM_ldrsb
)
10021 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10022 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10029 if (inst
.reloc
.pc_rel
)
10030 opcode
= T_MNEM_ldr_pc2
;
10032 opcode
= T_MNEM_ldr_pc
;
10036 if (opcode
== T_MNEM_ldr
)
10037 opcode
= T_MNEM_ldr_sp
;
10039 opcode
= T_MNEM_str_sp
;
10041 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10045 inst
.instruction
= inst
.operands
[0].reg
;
10046 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10048 inst
.instruction
|= THUMB_OP16 (opcode
);
10049 if (inst
.size_req
== 2)
10050 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10052 inst
.relax
= opcode
;
10056 /* Definitely a 32-bit variant. */
10058 /* Do some validations regarding addressing modes. */
10059 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10060 && opcode
!= T_MNEM_str
)
10061 reject_bad_reg (inst
.operands
[1].imm
);
10063 inst
.instruction
= THUMB_OP32 (opcode
);
10064 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10065 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10069 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10071 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10073 /* Only [Rn,Rm] is acceptable. */
10074 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10075 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10076 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10077 || inst
.operands
[1].negative
,
10078 _("Thumb does not support this addressing mode"));
10079 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10083 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10084 if (!inst
.operands
[1].isreg
)
10085 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10088 constraint (!inst
.operands
[1].preind
10089 || inst
.operands
[1].shifted
10090 || inst
.operands
[1].writeback
,
10091 _("Thumb does not support this addressing mode"));
10092 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10094 constraint (inst
.instruction
& 0x0600,
10095 _("byte or halfword not valid for base register"));
10096 constraint (inst
.operands
[1].reg
== REG_PC
10097 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10098 _("r15 based store not allowed"));
10099 constraint (inst
.operands
[1].immisreg
,
10100 _("invalid base register for register offset"));
10102 if (inst
.operands
[1].reg
== REG_PC
)
10103 inst
.instruction
= T_OPCODE_LDR_PC
;
10104 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10105 inst
.instruction
= T_OPCODE_LDR_SP
;
10107 inst
.instruction
= T_OPCODE_STR_SP
;
10109 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10110 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10114 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10115 if (!inst
.operands
[1].immisreg
)
10117 /* Immediate offset. */
10118 inst
.instruction
|= inst
.operands
[0].reg
;
10119 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10120 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10124 /* Register offset. */
10125 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10126 constraint (inst
.operands
[1].negative
,
10127 _("Thumb does not support this addressing mode"));
10130 switch (inst
.instruction
)
10132 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10133 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10134 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10135 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10136 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10137 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10138 case 0x5600 /* ldrsb */:
10139 case 0x5e00 /* ldrsh */: break;
10143 inst
.instruction
|= inst
.operands
[0].reg
;
10144 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10145 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10151 if (!inst
.operands
[1].present
)
10153 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10154 constraint (inst
.operands
[0].reg
== REG_LR
,
10155 _("r14 not allowed here"));
10157 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10158 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10159 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10165 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10166 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10172 unsigned Rd
, Rn
, Rm
, Ra
;
10174 Rd
= inst
.operands
[0].reg
;
10175 Rn
= inst
.operands
[1].reg
;
10176 Rm
= inst
.operands
[2].reg
;
10177 Ra
= inst
.operands
[3].reg
;
10179 reject_bad_reg (Rd
);
10180 reject_bad_reg (Rn
);
10181 reject_bad_reg (Rm
);
10182 reject_bad_reg (Ra
);
10184 inst
.instruction
|= Rd
<< 8;
10185 inst
.instruction
|= Rn
<< 16;
10186 inst
.instruction
|= Rm
;
10187 inst
.instruction
|= Ra
<< 12;
10193 unsigned RdLo
, RdHi
, Rn
, Rm
;
10195 RdLo
= inst
.operands
[0].reg
;
10196 RdHi
= inst
.operands
[1].reg
;
10197 Rn
= inst
.operands
[2].reg
;
10198 Rm
= inst
.operands
[3].reg
;
10200 reject_bad_reg (RdLo
);
10201 reject_bad_reg (RdHi
);
10202 reject_bad_reg (Rn
);
10203 reject_bad_reg (Rm
);
10205 inst
.instruction
|= RdLo
<< 12;
10206 inst
.instruction
|= RdHi
<< 8;
10207 inst
.instruction
|= Rn
<< 16;
10208 inst
.instruction
|= Rm
;
10212 do_t_mov_cmp (void)
10216 Rn
= inst
.operands
[0].reg
;
10217 Rm
= inst
.operands
[1].reg
;
10220 set_it_insn_type_last ();
10222 if (unified_syntax
)
10224 int r0off
= (inst
.instruction
== T_MNEM_mov
10225 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10226 unsigned long opcode
;
10227 bfd_boolean narrow
;
10228 bfd_boolean low_regs
;
10230 low_regs
= (Rn
<= 7 && Rm
<= 7);
10231 opcode
= inst
.instruction
;
10232 if (in_it_block ())
10233 narrow
= opcode
!= T_MNEM_movs
;
10235 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10236 if (inst
.size_req
== 4
10237 || inst
.operands
[1].shifted
)
10240 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10241 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10242 && !inst
.operands
[1].shifted
10246 inst
.instruction
= T2_SUBS_PC_LR
;
10250 if (opcode
== T_MNEM_cmp
)
10252 constraint (Rn
== REG_PC
, BAD_PC
);
10255 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10257 warn_deprecated_sp (Rm
);
10258 /* R15 was documented as a valid choice for Rm in ARMv6,
10259 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10260 tools reject R15, so we do too. */
10261 constraint (Rm
== REG_PC
, BAD_PC
);
10264 reject_bad_reg (Rm
);
10266 else if (opcode
== T_MNEM_mov
10267 || opcode
== T_MNEM_movs
)
10269 if (inst
.operands
[1].isreg
)
10271 if (opcode
== T_MNEM_movs
)
10273 reject_bad_reg (Rn
);
10274 reject_bad_reg (Rm
);
10276 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10277 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10278 reject_bad_reg (Rm
);
10281 reject_bad_reg (Rn
);
10284 if (!inst
.operands
[1].isreg
)
10286 /* Immediate operand. */
10287 if (!in_it_block () && opcode
== T_MNEM_mov
)
10289 if (low_regs
&& narrow
)
10291 inst
.instruction
= THUMB_OP16 (opcode
);
10292 inst
.instruction
|= Rn
<< 8;
10293 if (inst
.size_req
== 2)
10294 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10296 inst
.relax
= opcode
;
10300 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10301 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10302 inst
.instruction
|= Rn
<< r0off
;
10303 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10306 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10307 && (inst
.instruction
== T_MNEM_mov
10308 || inst
.instruction
== T_MNEM_movs
))
10310 /* Register shifts are encoded as separate shift instructions. */
10311 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10313 if (in_it_block ())
10318 if (inst
.size_req
== 4)
10321 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10327 switch (inst
.operands
[1].shift_kind
)
10330 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10333 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10336 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10339 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10345 inst
.instruction
= opcode
;
10348 inst
.instruction
|= Rn
;
10349 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10354 inst
.instruction
|= CONDS_BIT
;
10356 inst
.instruction
|= Rn
<< 8;
10357 inst
.instruction
|= Rm
<< 16;
10358 inst
.instruction
|= inst
.operands
[1].imm
;
10363 /* Some mov with immediate shift have narrow variants.
10364 Register shifts are handled above. */
10365 if (low_regs
&& inst
.operands
[1].shifted
10366 && (inst
.instruction
== T_MNEM_mov
10367 || inst
.instruction
== T_MNEM_movs
))
10369 if (in_it_block ())
10370 narrow
= (inst
.instruction
== T_MNEM_mov
);
10372 narrow
= (inst
.instruction
== T_MNEM_movs
);
10377 switch (inst
.operands
[1].shift_kind
)
10379 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10380 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10381 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10382 default: narrow
= FALSE
; break;
10388 inst
.instruction
|= Rn
;
10389 inst
.instruction
|= Rm
<< 3;
10390 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10394 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10395 inst
.instruction
|= Rn
<< r0off
;
10396 encode_thumb32_shifted_operand (1);
10400 switch (inst
.instruction
)
10403 inst
.instruction
= T_OPCODE_MOV_HR
;
10404 inst
.instruction
|= (Rn
& 0x8) << 4;
10405 inst
.instruction
|= (Rn
& 0x7);
10406 inst
.instruction
|= Rm
<< 3;
10410 /* We know we have low registers at this point.
10411 Generate LSLS Rd, Rs, #0. */
10412 inst
.instruction
= T_OPCODE_LSL_I
;
10413 inst
.instruction
|= Rn
;
10414 inst
.instruction
|= Rm
<< 3;
10420 inst
.instruction
= T_OPCODE_CMP_LR
;
10421 inst
.instruction
|= Rn
;
10422 inst
.instruction
|= Rm
<< 3;
10426 inst
.instruction
= T_OPCODE_CMP_HR
;
10427 inst
.instruction
|= (Rn
& 0x8) << 4;
10428 inst
.instruction
|= (Rn
& 0x7);
10429 inst
.instruction
|= Rm
<< 3;
10436 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10438 /* PR 10443: Do not silently ignore shifted operands. */
10439 constraint (inst
.operands
[1].shifted
,
10440 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10442 if (inst
.operands
[1].isreg
)
10444 if (Rn
< 8 && Rm
< 8)
10446 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10447 since a MOV instruction produces unpredictable results. */
10448 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10449 inst
.instruction
= T_OPCODE_ADD_I3
;
10451 inst
.instruction
= T_OPCODE_CMP_LR
;
10453 inst
.instruction
|= Rn
;
10454 inst
.instruction
|= Rm
<< 3;
10458 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10459 inst
.instruction
= T_OPCODE_MOV_HR
;
10461 inst
.instruction
= T_OPCODE_CMP_HR
;
10467 constraint (Rn
> 7,
10468 _("only lo regs allowed with immediate"));
10469 inst
.instruction
|= Rn
<< 8;
10470 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10481 top
= (inst
.instruction
& 0x00800000) != 0;
10482 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10484 constraint (top
, _(":lower16: not allowed this instruction"));
10485 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10487 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10489 constraint (!top
, _(":upper16: not allowed this instruction"));
10490 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10493 Rd
= inst
.operands
[0].reg
;
10494 reject_bad_reg (Rd
);
10496 inst
.instruction
|= Rd
<< 8;
10497 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10499 imm
= inst
.reloc
.exp
.X_add_number
;
10500 inst
.instruction
|= (imm
& 0xf000) << 4;
10501 inst
.instruction
|= (imm
& 0x0800) << 15;
10502 inst
.instruction
|= (imm
& 0x0700) << 4;
10503 inst
.instruction
|= (imm
& 0x00ff);
10508 do_t_mvn_tst (void)
10512 Rn
= inst
.operands
[0].reg
;
10513 Rm
= inst
.operands
[1].reg
;
10515 if (inst
.instruction
== T_MNEM_cmp
10516 || inst
.instruction
== T_MNEM_cmn
)
10517 constraint (Rn
== REG_PC
, BAD_PC
);
10519 reject_bad_reg (Rn
);
10520 reject_bad_reg (Rm
);
10522 if (unified_syntax
)
10524 int r0off
= (inst
.instruction
== T_MNEM_mvn
10525 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10526 bfd_boolean narrow
;
10528 if (inst
.size_req
== 4
10529 || inst
.instruction
> 0xffff
10530 || inst
.operands
[1].shifted
10531 || Rn
> 7 || Rm
> 7)
10533 else if (inst
.instruction
== T_MNEM_cmn
)
10535 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10536 narrow
= !in_it_block ();
10538 narrow
= in_it_block ();
10540 if (!inst
.operands
[1].isreg
)
10542 /* For an immediate, we always generate a 32-bit opcode;
10543 section relaxation will shrink it later if possible. */
10544 if (inst
.instruction
< 0xffff)
10545 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10546 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10547 inst
.instruction
|= Rn
<< r0off
;
10548 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10552 /* See if we can do this with a 16-bit instruction. */
10555 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10556 inst
.instruction
|= Rn
;
10557 inst
.instruction
|= Rm
<< 3;
10561 constraint (inst
.operands
[1].shifted
10562 && inst
.operands
[1].immisreg
,
10563 _("shift must be constant"));
10564 if (inst
.instruction
< 0xffff)
10565 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10566 inst
.instruction
|= Rn
<< r0off
;
10567 encode_thumb32_shifted_operand (1);
10573 constraint (inst
.instruction
> 0xffff
10574 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10575 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10576 _("unshifted register required"));
10577 constraint (Rn
> 7 || Rm
> 7,
10580 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10581 inst
.instruction
|= Rn
;
10582 inst
.instruction
|= Rm
<< 3;
10592 if (do_vfp_nsyn_mrs () == SUCCESS
)
10595 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10598 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10599 _("selected processor does not support "
10600 "requested special purpose register"));
10604 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10605 _("selected processor does not support "
10606 "requested special purpose register"));
10607 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10608 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10609 _("'CPSR' or 'SPSR' expected"));
10612 Rd
= inst
.operands
[0].reg
;
10613 reject_bad_reg (Rd
);
10615 inst
.instruction
|= Rd
<< 8;
10616 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10617 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10626 if (do_vfp_nsyn_msr () == SUCCESS
)
10629 constraint (!inst
.operands
[1].isreg
,
10630 _("Thumb encoding does not support an immediate here"));
10631 flags
= inst
.operands
[0].imm
;
10634 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10635 _("selected processor does not support "
10636 "requested special purpose register"));
10640 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10641 _("selected processor does not support "
10642 "requested special purpose register"));
10646 Rn
= inst
.operands
[1].reg
;
10647 reject_bad_reg (Rn
);
10649 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10650 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10651 inst
.instruction
|= (flags
& 0xff);
10652 inst
.instruction
|= Rn
<< 16;
10658 bfd_boolean narrow
;
10659 unsigned Rd
, Rn
, Rm
;
10661 if (!inst
.operands
[2].present
)
10662 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10664 Rd
= inst
.operands
[0].reg
;
10665 Rn
= inst
.operands
[1].reg
;
10666 Rm
= inst
.operands
[2].reg
;
10668 if (unified_syntax
)
10670 if (inst
.size_req
== 4
10676 else if (inst
.instruction
== T_MNEM_muls
)
10677 narrow
= !in_it_block ();
10679 narrow
= in_it_block ();
10683 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10684 constraint (Rn
> 7 || Rm
> 7,
10691 /* 16-bit MULS/Conditional MUL. */
10692 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10693 inst
.instruction
|= Rd
;
10696 inst
.instruction
|= Rm
<< 3;
10698 inst
.instruction
|= Rn
<< 3;
10700 constraint (1, _("dest must overlap one source register"));
10704 constraint (inst
.instruction
!= T_MNEM_mul
,
10705 _("Thumb-2 MUL must not set flags"));
10707 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10708 inst
.instruction
|= Rd
<< 8;
10709 inst
.instruction
|= Rn
<< 16;
10710 inst
.instruction
|= Rm
<< 0;
10712 reject_bad_reg (Rd
);
10713 reject_bad_reg (Rn
);
10714 reject_bad_reg (Rm
);
10721 unsigned RdLo
, RdHi
, Rn
, Rm
;
10723 RdLo
= inst
.operands
[0].reg
;
10724 RdHi
= inst
.operands
[1].reg
;
10725 Rn
= inst
.operands
[2].reg
;
10726 Rm
= inst
.operands
[3].reg
;
10728 reject_bad_reg (RdLo
);
10729 reject_bad_reg (RdHi
);
10730 reject_bad_reg (Rn
);
10731 reject_bad_reg (Rm
);
10733 inst
.instruction
|= RdLo
<< 12;
10734 inst
.instruction
|= RdHi
<< 8;
10735 inst
.instruction
|= Rn
<< 16;
10736 inst
.instruction
|= Rm
;
10739 as_tsktsk (_("rdhi and rdlo must be different"));
10745 set_it_insn_type (NEUTRAL_IT_INSN
);
10747 if (unified_syntax
)
10749 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10751 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10752 inst
.instruction
|= inst
.operands
[0].imm
;
10756 /* PR9722: Check for Thumb2 availability before
10757 generating a thumb2 nop instruction. */
10758 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10760 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10761 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10764 inst
.instruction
= 0x46c0;
10769 constraint (inst
.operands
[0].present
,
10770 _("Thumb does not support NOP with hints"));
10771 inst
.instruction
= 0x46c0;
10778 if (unified_syntax
)
10780 bfd_boolean narrow
;
10782 if (THUMB_SETS_FLAGS (inst
.instruction
))
10783 narrow
= !in_it_block ();
10785 narrow
= in_it_block ();
10786 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10788 if (inst
.size_req
== 4)
10793 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10794 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10795 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10799 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10800 inst
.instruction
|= inst
.operands
[0].reg
;
10801 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10806 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10808 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10810 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10811 inst
.instruction
|= inst
.operands
[0].reg
;
10812 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10821 Rd
= inst
.operands
[0].reg
;
10822 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10824 reject_bad_reg (Rd
);
10825 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10826 reject_bad_reg (Rn
);
10828 inst
.instruction
|= Rd
<< 8;
10829 inst
.instruction
|= Rn
<< 16;
10831 if (!inst
.operands
[2].isreg
)
10833 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10834 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10840 Rm
= inst
.operands
[2].reg
;
10841 reject_bad_reg (Rm
);
10843 constraint (inst
.operands
[2].shifted
10844 && inst
.operands
[2].immisreg
,
10845 _("shift must be constant"));
10846 encode_thumb32_shifted_operand (2);
10853 unsigned Rd
, Rn
, Rm
;
10855 Rd
= inst
.operands
[0].reg
;
10856 Rn
= inst
.operands
[1].reg
;
10857 Rm
= inst
.operands
[2].reg
;
10859 reject_bad_reg (Rd
);
10860 reject_bad_reg (Rn
);
10861 reject_bad_reg (Rm
);
10863 inst
.instruction
|= Rd
<< 8;
10864 inst
.instruction
|= Rn
<< 16;
10865 inst
.instruction
|= Rm
;
10866 if (inst
.operands
[3].present
)
10868 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10869 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10870 _("expression too complex"));
10871 inst
.instruction
|= (val
& 0x1c) << 10;
10872 inst
.instruction
|= (val
& 0x03) << 6;
10879 if (!inst
.operands
[3].present
)
10883 inst
.instruction
&= ~0x00000020;
10885 /* PR 10168. Swap the Rm and Rn registers. */
10886 Rtmp
= inst
.operands
[1].reg
;
10887 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10888 inst
.operands
[2].reg
= Rtmp
;
10896 if (inst
.operands
[0].immisreg
)
10897 reject_bad_reg (inst
.operands
[0].imm
);
10899 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10903 do_t_push_pop (void)
10907 constraint (inst
.operands
[0].writeback
,
10908 _("push/pop do not support {reglist}^"));
10909 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10910 _("expression too complex"));
10912 mask
= inst
.operands
[0].imm
;
10913 if ((mask
& ~0xff) == 0)
10914 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10915 else if ((inst
.instruction
== T_MNEM_push
10916 && (mask
& ~0xff) == 1 << REG_LR
)
10917 || (inst
.instruction
== T_MNEM_pop
10918 && (mask
& ~0xff) == 1 << REG_PC
))
10920 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10921 inst
.instruction
|= THUMB_PP_PC_LR
;
10922 inst
.instruction
|= mask
& 0xff;
10924 else if (unified_syntax
)
10926 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10927 encode_thumb2_ldmstm (13, mask
, TRUE
);
10931 inst
.error
= _("invalid register list to push/pop instruction");
10941 Rd
= inst
.operands
[0].reg
;
10942 Rm
= inst
.operands
[1].reg
;
10944 reject_bad_reg (Rd
);
10945 reject_bad_reg (Rm
);
10947 inst
.instruction
|= Rd
<< 8;
10948 inst
.instruction
|= Rm
<< 16;
10949 inst
.instruction
|= Rm
;
10957 Rd
= inst
.operands
[0].reg
;
10958 Rm
= inst
.operands
[1].reg
;
10960 reject_bad_reg (Rd
);
10961 reject_bad_reg (Rm
);
10963 if (Rd
<= 7 && Rm
<= 7
10964 && inst
.size_req
!= 4)
10966 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10967 inst
.instruction
|= Rd
;
10968 inst
.instruction
|= Rm
<< 3;
10970 else if (unified_syntax
)
10972 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10973 inst
.instruction
|= Rd
<< 8;
10974 inst
.instruction
|= Rm
<< 16;
10975 inst
.instruction
|= Rm
;
10978 inst
.error
= BAD_HIREG
;
10986 Rd
= inst
.operands
[0].reg
;
10987 Rm
= inst
.operands
[1].reg
;
10989 reject_bad_reg (Rd
);
10990 reject_bad_reg (Rm
);
10992 inst
.instruction
|= Rd
<< 8;
10993 inst
.instruction
|= Rm
;
11001 Rd
= inst
.operands
[0].reg
;
11002 Rs
= (inst
.operands
[1].present
11003 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11004 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11006 reject_bad_reg (Rd
);
11007 reject_bad_reg (Rs
);
11008 if (inst
.operands
[2].isreg
)
11009 reject_bad_reg (inst
.operands
[2].reg
);
11011 inst
.instruction
|= Rd
<< 8;
11012 inst
.instruction
|= Rs
<< 16;
11013 if (!inst
.operands
[2].isreg
)
11015 bfd_boolean narrow
;
11017 if ((inst
.instruction
& 0x00100000) != 0)
11018 narrow
= !in_it_block ();
11020 narrow
= in_it_block ();
11022 if (Rd
> 7 || Rs
> 7)
11025 if (inst
.size_req
== 4 || !unified_syntax
)
11028 if (inst
.reloc
.exp
.X_op
!= O_constant
11029 || inst
.reloc
.exp
.X_add_number
!= 0)
11032 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11033 relaxation, but it doesn't seem worth the hassle. */
11036 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11037 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11038 inst
.instruction
|= Rs
<< 3;
11039 inst
.instruction
|= Rd
;
11043 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11044 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11048 encode_thumb32_shifted_operand (2);
11054 set_it_insn_type (OUTSIDE_IT_INSN
);
11055 if (inst
.operands
[0].imm
)
11056 inst
.instruction
|= 0x8;
11062 if (!inst
.operands
[1].present
)
11063 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11065 if (unified_syntax
)
11067 bfd_boolean narrow
;
11070 switch (inst
.instruction
)
11073 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11075 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11077 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11079 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11083 if (THUMB_SETS_FLAGS (inst
.instruction
))
11084 narrow
= !in_it_block ();
11086 narrow
= in_it_block ();
11087 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11089 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11091 if (inst
.operands
[2].isreg
11092 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11093 || inst
.operands
[2].reg
> 7))
11095 if (inst
.size_req
== 4)
11098 reject_bad_reg (inst
.operands
[0].reg
);
11099 reject_bad_reg (inst
.operands
[1].reg
);
11103 if (inst
.operands
[2].isreg
)
11105 reject_bad_reg (inst
.operands
[2].reg
);
11106 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11107 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11108 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11109 inst
.instruction
|= inst
.operands
[2].reg
;
11113 inst
.operands
[1].shifted
= 1;
11114 inst
.operands
[1].shift_kind
= shift_kind
;
11115 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11116 ? T_MNEM_movs
: T_MNEM_mov
);
11117 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11118 encode_thumb32_shifted_operand (1);
11119 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11120 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11125 if (inst
.operands
[2].isreg
)
11127 switch (shift_kind
)
11129 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11130 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11131 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11132 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11136 inst
.instruction
|= inst
.operands
[0].reg
;
11137 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11141 switch (shift_kind
)
11143 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11144 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11145 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11148 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11149 inst
.instruction
|= inst
.operands
[0].reg
;
11150 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11156 constraint (inst
.operands
[0].reg
> 7
11157 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11158 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11160 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11162 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11163 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11164 _("source1 and dest must be same register"));
11166 switch (inst
.instruction
)
11168 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11169 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11170 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11171 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11175 inst
.instruction
|= inst
.operands
[0].reg
;
11176 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11180 switch (inst
.instruction
)
11182 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11183 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11184 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11185 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11188 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11189 inst
.instruction
|= inst
.operands
[0].reg
;
11190 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11198 unsigned Rd
, Rn
, Rm
;
11200 Rd
= inst
.operands
[0].reg
;
11201 Rn
= inst
.operands
[1].reg
;
11202 Rm
= inst
.operands
[2].reg
;
11204 reject_bad_reg (Rd
);
11205 reject_bad_reg (Rn
);
11206 reject_bad_reg (Rm
);
11208 inst
.instruction
|= Rd
<< 8;
11209 inst
.instruction
|= Rn
<< 16;
11210 inst
.instruction
|= Rm
;
11216 unsigned Rd
, Rn
, Rm
;
11218 Rd
= inst
.operands
[0].reg
;
11219 Rm
= inst
.operands
[1].reg
;
11220 Rn
= inst
.operands
[2].reg
;
11222 reject_bad_reg (Rd
);
11223 reject_bad_reg (Rn
);
11224 reject_bad_reg (Rm
);
11226 inst
.instruction
|= Rd
<< 8;
11227 inst
.instruction
|= Rn
<< 16;
11228 inst
.instruction
|= Rm
;
11234 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11235 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11236 _("expression too complex"));
11237 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11238 inst
.instruction
|= (value
& 0xf000) >> 12;
11239 inst
.instruction
|= (value
& 0x0ff0);
11240 inst
.instruction
|= (value
& 0x000f) << 16;
11244 do_t_ssat_usat (int bias
)
11248 Rd
= inst
.operands
[0].reg
;
11249 Rn
= inst
.operands
[2].reg
;
11251 reject_bad_reg (Rd
);
11252 reject_bad_reg (Rn
);
11254 inst
.instruction
|= Rd
<< 8;
11255 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11256 inst
.instruction
|= Rn
<< 16;
11258 if (inst
.operands
[3].present
)
11260 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11262 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11264 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11265 _("expression too complex"));
11267 if (shift_amount
!= 0)
11269 constraint (shift_amount
> 31,
11270 _("shift expression is too large"));
11272 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11273 inst
.instruction
|= 0x00200000; /* sh bit. */
11275 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11276 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11284 do_t_ssat_usat (1);
11292 Rd
= inst
.operands
[0].reg
;
11293 Rn
= inst
.operands
[2].reg
;
11295 reject_bad_reg (Rd
);
11296 reject_bad_reg (Rn
);
11298 inst
.instruction
|= Rd
<< 8;
11299 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11300 inst
.instruction
|= Rn
<< 16;
11306 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11307 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11308 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11309 || inst
.operands
[2].negative
,
11312 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11314 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11315 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11316 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11317 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11323 if (!inst
.operands
[2].present
)
11324 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11326 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11327 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11328 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11331 inst
.instruction
|= inst
.operands
[0].reg
;
11332 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11333 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11334 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11340 unsigned Rd
, Rn
, Rm
;
11342 Rd
= inst
.operands
[0].reg
;
11343 Rn
= inst
.operands
[1].reg
;
11344 Rm
= inst
.operands
[2].reg
;
11346 reject_bad_reg (Rd
);
11347 reject_bad_reg (Rn
);
11348 reject_bad_reg (Rm
);
11350 inst
.instruction
|= Rd
<< 8;
11351 inst
.instruction
|= Rn
<< 16;
11352 inst
.instruction
|= Rm
;
11353 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11361 Rd
= inst
.operands
[0].reg
;
11362 Rm
= inst
.operands
[1].reg
;
11364 reject_bad_reg (Rd
);
11365 reject_bad_reg (Rm
);
11367 if (inst
.instruction
<= 0xffff
11368 && inst
.size_req
!= 4
11369 && Rd
<= 7 && Rm
<= 7
11370 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11372 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11373 inst
.instruction
|= Rd
;
11374 inst
.instruction
|= Rm
<< 3;
11376 else if (unified_syntax
)
11378 if (inst
.instruction
<= 0xffff)
11379 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11380 inst
.instruction
|= Rd
<< 8;
11381 inst
.instruction
|= Rm
;
11382 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11386 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11387 _("Thumb encoding does not support rotation"));
11388 constraint (1, BAD_HIREG
);
11395 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11404 half
= (inst
.instruction
& 0x10) != 0;
11405 set_it_insn_type_last ();
11406 constraint (inst
.operands
[0].immisreg
,
11407 _("instruction requires register index"));
11409 Rn
= inst
.operands
[0].reg
;
11410 Rm
= inst
.operands
[0].imm
;
11412 constraint (Rn
== REG_SP
, BAD_SP
);
11413 reject_bad_reg (Rm
);
11415 constraint (!half
&& inst
.operands
[0].shifted
,
11416 _("instruction does not allow shifted index"));
11417 inst
.instruction
|= (Rn
<< 16) | Rm
;
11423 do_t_ssat_usat (0);
11431 Rd
= inst
.operands
[0].reg
;
11432 Rn
= inst
.operands
[2].reg
;
11434 reject_bad_reg (Rd
);
11435 reject_bad_reg (Rn
);
11437 inst
.instruction
|= Rd
<< 8;
11438 inst
.instruction
|= inst
.operands
[1].imm
;
11439 inst
.instruction
|= Rn
<< 16;
11442 /* Neon instruction encoder helpers. */
11444 /* Encodings for the different types for various Neon opcodes. */
11446 /* An "invalid" code for the following tables. */
11449 struct neon_tab_entry
11452 unsigned float_or_poly
;
11453 unsigned scalar_or_imm
;
11456 /* Map overloaded Neon opcodes to their respective encodings. */
11457 #define NEON_ENC_TAB \
11458 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11459 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11460 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11461 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11462 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11463 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11464 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11465 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11466 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11467 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11468 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11469 /* Register variants of the following two instructions are encoded as
11470 vcge / vcgt with the operands reversed. */ \
11471 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11472 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11473 X(vfma, N_INV, 0x0000c10, N_INV), \
11474 X(vfms, N_INV, 0x0200c10, N_INV), \
11475 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11476 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11477 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11478 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11479 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11480 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11481 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11482 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11483 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11484 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11485 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11486 X(vshl, 0x0000400, N_INV, 0x0800510), \
11487 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11488 X(vand, 0x0000110, N_INV, 0x0800030), \
11489 X(vbic, 0x0100110, N_INV, 0x0800030), \
11490 X(veor, 0x1000110, N_INV, N_INV), \
11491 X(vorn, 0x0300110, N_INV, 0x0800010), \
11492 X(vorr, 0x0200110, N_INV, 0x0800010), \
11493 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11494 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11495 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11496 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11497 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11498 X(vst1, 0x0000000, 0x0800000, N_INV), \
11499 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11500 X(vst2, 0x0000100, 0x0800100, N_INV), \
11501 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11502 X(vst3, 0x0000200, 0x0800200, N_INV), \
11503 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11504 X(vst4, 0x0000300, 0x0800300, N_INV), \
11505 X(vmovn, 0x1b20200, N_INV, N_INV), \
11506 X(vtrn, 0x1b20080, N_INV, N_INV), \
11507 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11508 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11509 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11510 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11511 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11512 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11513 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11514 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11515 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11516 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11517 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11521 #define X(OPC,I,F,S) N_MNEM_##OPC
11526 static const struct neon_tab_entry neon_enc_tab
[] =
11528 #define X(OPC,I,F,S) { (I), (F), (S) }
11533 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11534 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11535 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11536 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11537 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11538 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11539 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11540 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11541 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11542 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11543 #define NEON_ENC_SINGLE_(X) \
11544 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11545 #define NEON_ENC_DOUBLE_(X) \
11546 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11548 #define NEON_ENCODE(type, inst) \
11551 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11552 inst.is_neon = 1; \
11556 #define check_neon_suffixes \
11559 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11561 as_bad (_("invalid neon suffix for non neon instruction")); \
11567 /* Define shapes for instruction operands. The following mnemonic characters
11568 are used in this table:
11570 F - VFP S<n> register
11571 D - Neon D<n> register
11572 Q - Neon Q<n> register
11576 L - D<n> register list
11578 This table is used to generate various data:
11579 - enumerations of the form NS_DDR to be used as arguments to
11581 - a table classifying shapes into single, double, quad, mixed.
11582 - a table used to drive neon_select_shape. */
11584 #define NEON_SHAPE_DEF \
11585 X(3, (D, D, D), DOUBLE), \
11586 X(3, (Q, Q, Q), QUAD), \
11587 X(3, (D, D, I), DOUBLE), \
11588 X(3, (Q, Q, I), QUAD), \
11589 X(3, (D, D, S), DOUBLE), \
11590 X(3, (Q, Q, S), QUAD), \
11591 X(2, (D, D), DOUBLE), \
11592 X(2, (Q, Q), QUAD), \
11593 X(2, (D, S), DOUBLE), \
11594 X(2, (Q, S), QUAD), \
11595 X(2, (D, R), DOUBLE), \
11596 X(2, (Q, R), QUAD), \
11597 X(2, (D, I), DOUBLE), \
11598 X(2, (Q, I), QUAD), \
11599 X(3, (D, L, D), DOUBLE), \
11600 X(2, (D, Q), MIXED), \
11601 X(2, (Q, D), MIXED), \
11602 X(3, (D, Q, I), MIXED), \
11603 X(3, (Q, D, I), MIXED), \
11604 X(3, (Q, D, D), MIXED), \
11605 X(3, (D, Q, Q), MIXED), \
11606 X(3, (Q, Q, D), MIXED), \
11607 X(3, (Q, D, S), MIXED), \
11608 X(3, (D, Q, S), MIXED), \
11609 X(4, (D, D, D, I), DOUBLE), \
11610 X(4, (Q, Q, Q, I), QUAD), \
11611 X(2, (F, F), SINGLE), \
11612 X(3, (F, F, F), SINGLE), \
11613 X(2, (F, I), SINGLE), \
11614 X(2, (F, D), MIXED), \
11615 X(2, (D, F), MIXED), \
11616 X(3, (F, F, I), MIXED), \
11617 X(4, (R, R, F, F), SINGLE), \
11618 X(4, (F, F, R, R), SINGLE), \
11619 X(3, (D, R, R), DOUBLE), \
11620 X(3, (R, R, D), DOUBLE), \
11621 X(2, (S, R), SINGLE), \
11622 X(2, (R, S), SINGLE), \
11623 X(2, (F, R), SINGLE), \
11624 X(2, (R, F), SINGLE)
11626 #define S2(A,B) NS_##A##B
11627 #define S3(A,B,C) NS_##A##B##C
11628 #define S4(A,B,C,D) NS_##A##B##C##D
11630 #define X(N, L, C) S##N L
11643 enum neon_shape_class
11651 #define X(N, L, C) SC_##C
11653 static enum neon_shape_class neon_shape_class
[] =
11671 /* Register widths of above. */
11672 static unsigned neon_shape_el_size
[] =
11683 struct neon_shape_info
11686 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11689 #define S2(A,B) { SE_##A, SE_##B }
11690 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11691 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11693 #define X(N, L, C) { N, S##N L }
11695 static struct neon_shape_info neon_shape_tab
[] =
11705 /* Bit masks used in type checking given instructions.
11706 'N_EQK' means the type must be the same as (or based on in some way) the key
11707 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11708 set, various other bits can be set as well in order to modify the meaning of
11709 the type constraint. */
11711 enum neon_type_mask
11734 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11735 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11736 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11737 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11738 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11739 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11740 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11741 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11742 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11743 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11745 N_MAX_NONSPECIAL
= N_F64
11748 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11750 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11751 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11752 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11753 #define N_SUF_32 (N_SU_32 | N_F32)
11754 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11755 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11757 /* Pass this as the first type argument to neon_check_type to ignore types
11759 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11761 /* Select a "shape" for the current instruction (describing register types or
11762 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11763 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11764 function of operand parsing, so this function doesn't need to be called.
11765 Shapes should be listed in order of decreasing length. */
11767 static enum neon_shape
11768 neon_select_shape (enum neon_shape shape
, ...)
11771 enum neon_shape first_shape
= shape
;
11773 /* Fix missing optional operands. FIXME: we don't know at this point how
11774 many arguments we should have, so this makes the assumption that we have
11775 > 1. This is true of all current Neon opcodes, I think, but may not be
11776 true in the future. */
11777 if (!inst
.operands
[1].present
)
11778 inst
.operands
[1] = inst
.operands
[0];
11780 va_start (ap
, shape
);
11782 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11787 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11789 if (!inst
.operands
[j
].present
)
11795 switch (neon_shape_tab
[shape
].el
[j
])
11798 if (!(inst
.operands
[j
].isreg
11799 && inst
.operands
[j
].isvec
11800 && inst
.operands
[j
].issingle
11801 && !inst
.operands
[j
].isquad
))
11806 if (!(inst
.operands
[j
].isreg
11807 && inst
.operands
[j
].isvec
11808 && !inst
.operands
[j
].isquad
11809 && !inst
.operands
[j
].issingle
))
11814 if (!(inst
.operands
[j
].isreg
11815 && !inst
.operands
[j
].isvec
))
11820 if (!(inst
.operands
[j
].isreg
11821 && inst
.operands
[j
].isvec
11822 && inst
.operands
[j
].isquad
11823 && !inst
.operands
[j
].issingle
))
11828 if (!(!inst
.operands
[j
].isreg
11829 && !inst
.operands
[j
].isscalar
))
11834 if (!(!inst
.operands
[j
].isreg
11835 && inst
.operands
[j
].isscalar
))
11851 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11852 first_error (_("invalid instruction shape"));
11857 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11858 means the Q bit should be set). */
11861 neon_quad (enum neon_shape shape
)
11863 return neon_shape_class
[shape
] == SC_QUAD
;
11867 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11870 /* Allow modification to be made to types which are constrained to be
11871 based on the key element, based on bits set alongside N_EQK. */
11872 if ((typebits
& N_EQK
) != 0)
11874 if ((typebits
& N_HLF
) != 0)
11876 else if ((typebits
& N_DBL
) != 0)
11878 if ((typebits
& N_SGN
) != 0)
11879 *g_type
= NT_signed
;
11880 else if ((typebits
& N_UNS
) != 0)
11881 *g_type
= NT_unsigned
;
11882 else if ((typebits
& N_INT
) != 0)
11883 *g_type
= NT_integer
;
11884 else if ((typebits
& N_FLT
) != 0)
11885 *g_type
= NT_float
;
11886 else if ((typebits
& N_SIZ
) != 0)
11887 *g_type
= NT_untyped
;
11891 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11892 operand type, i.e. the single type specified in a Neon instruction when it
11893 is the only one given. */
11895 static struct neon_type_el
11896 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11898 struct neon_type_el dest
= *key
;
11900 gas_assert ((thisarg
& N_EQK
) != 0);
11902 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11907 /* Convert Neon type and size into compact bitmask representation. */
11909 static enum neon_type_mask
11910 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11917 case 8: return N_8
;
11918 case 16: return N_16
;
11919 case 32: return N_32
;
11920 case 64: return N_64
;
11928 case 8: return N_I8
;
11929 case 16: return N_I16
;
11930 case 32: return N_I32
;
11931 case 64: return N_I64
;
11939 case 16: return N_F16
;
11940 case 32: return N_F32
;
11941 case 64: return N_F64
;
11949 case 8: return N_P8
;
11950 case 16: return N_P16
;
11958 case 8: return N_S8
;
11959 case 16: return N_S16
;
11960 case 32: return N_S32
;
11961 case 64: return N_S64
;
11969 case 8: return N_U8
;
11970 case 16: return N_U16
;
11971 case 32: return N_U32
;
11972 case 64: return N_U64
;
11983 /* Convert compact Neon bitmask type representation to a type and size. Only
11984 handles the case where a single bit is set in the mask. */
11987 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11988 enum neon_type_mask mask
)
11990 if ((mask
& N_EQK
) != 0)
11993 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11995 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11997 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11999 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12004 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12006 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12007 *type
= NT_unsigned
;
12008 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12009 *type
= NT_integer
;
12010 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12011 *type
= NT_untyped
;
12012 else if ((mask
& (N_P8
| N_P16
)) != 0)
12014 else if ((mask
& (N_F32
| N_F64
)) != 0)
12022 /* Modify a bitmask of allowed types. This is only needed for type
12026 modify_types_allowed (unsigned allowed
, unsigned mods
)
12029 enum neon_el_type type
;
12035 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12037 if (el_type_of_type_chk (&type
, &size
,
12038 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12040 neon_modify_type_size (mods
, &type
, &size
);
12041 destmask
|= type_chk_of_el_type (type
, size
);
12048 /* Check type and return type classification.
12049 The manual states (paraphrase): If one datatype is given, it indicates the
12051 - the second operand, if there is one
12052 - the operand, if there is no second operand
12053 - the result, if there are no operands.
12054 This isn't quite good enough though, so we use a concept of a "key" datatype
12055 which is set on a per-instruction basis, which is the one which matters when
12056 only one data type is written.
12057 Note: this function has side-effects (e.g. filling in missing operands). All
12058 Neon instructions should call it before performing bit encoding. */
12060 static struct neon_type_el
12061 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12064 unsigned i
, pass
, key_el
= 0;
12065 unsigned types
[NEON_MAX_TYPE_ELS
];
12066 enum neon_el_type k_type
= NT_invtype
;
12067 unsigned k_size
= -1u;
12068 struct neon_type_el badtype
= {NT_invtype
, -1};
12069 unsigned key_allowed
= 0;
12071 /* Optional registers in Neon instructions are always (not) in operand 1.
12072 Fill in the missing operand here, if it was omitted. */
12073 if (els
> 1 && !inst
.operands
[1].present
)
12074 inst
.operands
[1] = inst
.operands
[0];
12076 /* Suck up all the varargs. */
12078 for (i
= 0; i
< els
; i
++)
12080 unsigned thisarg
= va_arg (ap
, unsigned);
12081 if (thisarg
== N_IGNORE_TYPE
)
12086 types
[i
] = thisarg
;
12087 if ((thisarg
& N_KEY
) != 0)
12092 if (inst
.vectype
.elems
> 0)
12093 for (i
= 0; i
< els
; i
++)
12094 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12096 first_error (_("types specified in both the mnemonic and operands"));
12100 /* Duplicate inst.vectype elements here as necessary.
12101 FIXME: No idea if this is exactly the same as the ARM assembler,
12102 particularly when an insn takes one register and one non-register
12104 if (inst
.vectype
.elems
== 1 && els
> 1)
12107 inst
.vectype
.elems
= els
;
12108 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12109 for (j
= 0; j
< els
; j
++)
12111 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12114 else if (inst
.vectype
.elems
== 0 && els
> 0)
12117 /* No types were given after the mnemonic, so look for types specified
12118 after each operand. We allow some flexibility here; as long as the
12119 "key" operand has a type, we can infer the others. */
12120 for (j
= 0; j
< els
; j
++)
12121 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12122 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12124 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12126 for (j
= 0; j
< els
; j
++)
12127 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12128 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12133 first_error (_("operand types can't be inferred"));
12137 else if (inst
.vectype
.elems
!= els
)
12139 first_error (_("type specifier has the wrong number of parts"));
12143 for (pass
= 0; pass
< 2; pass
++)
12145 for (i
= 0; i
< els
; i
++)
12147 unsigned thisarg
= types
[i
];
12148 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12149 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12150 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12151 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12153 /* Decay more-specific signed & unsigned types to sign-insensitive
12154 integer types if sign-specific variants are unavailable. */
12155 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12156 && (types_allowed
& N_SU_ALL
) == 0)
12157 g_type
= NT_integer
;
12159 /* If only untyped args are allowed, decay any more specific types to
12160 them. Some instructions only care about signs for some element
12161 sizes, so handle that properly. */
12162 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12163 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12164 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12165 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12166 g_type
= NT_untyped
;
12170 if ((thisarg
& N_KEY
) != 0)
12174 key_allowed
= thisarg
& ~N_KEY
;
12179 if ((thisarg
& N_VFP
) != 0)
12181 enum neon_shape_el regshape
;
12182 unsigned regwidth
, match
;
12184 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12187 first_error (_("invalid instruction shape"));
12190 regshape
= neon_shape_tab
[ns
].el
[i
];
12191 regwidth
= neon_shape_el_size
[regshape
];
12193 /* In VFP mode, operands must match register widths. If we
12194 have a key operand, use its width, else use the width of
12195 the current operand. */
12201 if (regwidth
!= match
)
12203 first_error (_("operand size must match register width"));
12208 if ((thisarg
& N_EQK
) == 0)
12210 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12212 if ((given_type
& types_allowed
) == 0)
12214 first_error (_("bad type in Neon instruction"));
12220 enum neon_el_type mod_k_type
= k_type
;
12221 unsigned mod_k_size
= k_size
;
12222 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12223 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12225 first_error (_("inconsistent types in Neon instruction"));
12233 return inst
.vectype
.el
[key_el
];
12236 /* Neon-style VFP instruction forwarding. */
12238 /* Thumb VFP instructions have 0xE in the condition field. */
12241 do_vfp_cond_or_thumb (void)
12246 inst
.instruction
|= 0xe0000000;
12248 inst
.instruction
|= inst
.cond
<< 28;
12251 /* Look up and encode a simple mnemonic, for use as a helper function for the
12252 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12253 etc. It is assumed that operand parsing has already been done, and that the
12254 operands are in the form expected by the given opcode (this isn't necessarily
12255 the same as the form in which they were parsed, hence some massaging must
12256 take place before this function is called).
12257 Checks current arch version against that in the looked-up opcode. */
12260 do_vfp_nsyn_opcode (const char *opname
)
12262 const struct asm_opcode
*opcode
;
12264 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12269 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12270 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12277 inst
.instruction
= opcode
->tvalue
;
12278 opcode
->tencode ();
12282 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12283 opcode
->aencode ();
12288 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12290 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12295 do_vfp_nsyn_opcode ("fadds");
12297 do_vfp_nsyn_opcode ("fsubs");
12302 do_vfp_nsyn_opcode ("faddd");
12304 do_vfp_nsyn_opcode ("fsubd");
12308 /* Check operand types to see if this is a VFP instruction, and if so call
12312 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12314 enum neon_shape rs
;
12315 struct neon_type_el et
;
12320 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12321 et
= neon_check_type (2, rs
,
12322 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12326 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12327 et
= neon_check_type (3, rs
,
12328 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12335 if (et
.type
!= NT_invtype
)
12346 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12348 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12353 do_vfp_nsyn_opcode ("fmacs");
12355 do_vfp_nsyn_opcode ("fnmacs");
12360 do_vfp_nsyn_opcode ("fmacd");
12362 do_vfp_nsyn_opcode ("fnmacd");
12367 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12369 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12374 do_vfp_nsyn_opcode ("ffmas");
12376 do_vfp_nsyn_opcode ("ffnmas");
12381 do_vfp_nsyn_opcode ("ffmad");
12383 do_vfp_nsyn_opcode ("ffnmad");
12388 do_vfp_nsyn_mul (enum neon_shape rs
)
12391 do_vfp_nsyn_opcode ("fmuls");
12393 do_vfp_nsyn_opcode ("fmuld");
12397 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12399 int is_neg
= (inst
.instruction
& 0x80) != 0;
12400 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12405 do_vfp_nsyn_opcode ("fnegs");
12407 do_vfp_nsyn_opcode ("fabss");
12412 do_vfp_nsyn_opcode ("fnegd");
12414 do_vfp_nsyn_opcode ("fabsd");
12418 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12419 insns belong to Neon, and are handled elsewhere. */
12422 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12424 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12428 do_vfp_nsyn_opcode ("fldmdbs");
12430 do_vfp_nsyn_opcode ("fldmias");
12435 do_vfp_nsyn_opcode ("fstmdbs");
12437 do_vfp_nsyn_opcode ("fstmias");
12442 do_vfp_nsyn_sqrt (void)
12444 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12445 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12448 do_vfp_nsyn_opcode ("fsqrts");
12450 do_vfp_nsyn_opcode ("fsqrtd");
12454 do_vfp_nsyn_div (void)
12456 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12457 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12458 N_F32
| N_F64
| N_KEY
| N_VFP
);
12461 do_vfp_nsyn_opcode ("fdivs");
12463 do_vfp_nsyn_opcode ("fdivd");
12467 do_vfp_nsyn_nmul (void)
12469 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12470 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12471 N_F32
| N_F64
| N_KEY
| N_VFP
);
12475 NEON_ENCODE (SINGLE
, inst
);
12476 do_vfp_sp_dyadic ();
12480 NEON_ENCODE (DOUBLE
, inst
);
12481 do_vfp_dp_rd_rn_rm ();
12483 do_vfp_cond_or_thumb ();
12487 do_vfp_nsyn_cmp (void)
12489 if (inst
.operands
[1].isreg
)
12491 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12492 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12496 NEON_ENCODE (SINGLE
, inst
);
12497 do_vfp_sp_monadic ();
12501 NEON_ENCODE (DOUBLE
, inst
);
12502 do_vfp_dp_rd_rm ();
12507 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12508 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12510 switch (inst
.instruction
& 0x0fffffff)
12513 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12516 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12524 NEON_ENCODE (SINGLE
, inst
);
12525 do_vfp_sp_compare_z ();
12529 NEON_ENCODE (DOUBLE
, inst
);
12533 do_vfp_cond_or_thumb ();
12537 nsyn_insert_sp (void)
12539 inst
.operands
[1] = inst
.operands
[0];
12540 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12541 inst
.operands
[0].reg
= REG_SP
;
12542 inst
.operands
[0].isreg
= 1;
12543 inst
.operands
[0].writeback
= 1;
12544 inst
.operands
[0].present
= 1;
12548 do_vfp_nsyn_push (void)
12551 if (inst
.operands
[1].issingle
)
12552 do_vfp_nsyn_opcode ("fstmdbs");
12554 do_vfp_nsyn_opcode ("fstmdbd");
12558 do_vfp_nsyn_pop (void)
12561 if (inst
.operands
[1].issingle
)
12562 do_vfp_nsyn_opcode ("fldmias");
12564 do_vfp_nsyn_opcode ("fldmiad");
12567 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12568 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12571 neon_dp_fixup (struct arm_it
* insn
)
12573 unsigned int i
= insn
->instruction
;
12578 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12589 insn
->instruction
= i
;
12592 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12596 neon_logbits (unsigned x
)
12598 return ffs (x
) - 4;
12601 #define LOW4(R) ((R) & 0xf)
12602 #define HI1(R) (((R) >> 4) & 1)
12604 /* Encode insns with bit pattern:
12606 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12607 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12609 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12610 different meaning for some instruction. */
12613 neon_three_same (int isquad
, int ubit
, int size
)
12615 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12616 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12617 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12618 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12619 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12620 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12621 inst
.instruction
|= (isquad
!= 0) << 6;
12622 inst
.instruction
|= (ubit
!= 0) << 24;
12624 inst
.instruction
|= neon_logbits (size
) << 20;
12626 neon_dp_fixup (&inst
);
12629 /* Encode instructions of the form:
12631 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12632 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12634 Don't write size if SIZE == -1. */
12637 neon_two_same (int qbit
, int ubit
, int size
)
12639 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12640 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12641 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12642 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12643 inst
.instruction
|= (qbit
!= 0) << 6;
12644 inst
.instruction
|= (ubit
!= 0) << 24;
12647 inst
.instruction
|= neon_logbits (size
) << 18;
12649 neon_dp_fixup (&inst
);
12652 /* Neon instruction encoders, in approximate order of appearance. */
12655 do_neon_dyadic_i_su (void)
12657 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12658 struct neon_type_el et
= neon_check_type (3, rs
,
12659 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12660 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12664 do_neon_dyadic_i64_su (void)
12666 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12667 struct neon_type_el et
= neon_check_type (3, rs
,
12668 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12669 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12673 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12676 unsigned size
= et
.size
>> 3;
12677 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12678 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12679 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12680 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12681 inst
.instruction
|= (isquad
!= 0) << 6;
12682 inst
.instruction
|= immbits
<< 16;
12683 inst
.instruction
|= (size
>> 3) << 7;
12684 inst
.instruction
|= (size
& 0x7) << 19;
12686 inst
.instruction
|= (uval
!= 0) << 24;
12688 neon_dp_fixup (&inst
);
12692 do_neon_shl_imm (void)
12694 if (!inst
.operands
[2].isreg
)
12696 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12697 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12698 NEON_ENCODE (IMMED
, inst
);
12699 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12703 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12704 struct neon_type_el et
= neon_check_type (3, rs
,
12705 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12708 /* VSHL/VQSHL 3-register variants have syntax such as:
12710 whereas other 3-register operations encoded by neon_three_same have
12713 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12715 tmp
= inst
.operands
[2].reg
;
12716 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12717 inst
.operands
[1].reg
= tmp
;
12718 NEON_ENCODE (INTEGER
, inst
);
12719 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12724 do_neon_qshl_imm (void)
12726 if (!inst
.operands
[2].isreg
)
12728 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12729 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12731 NEON_ENCODE (IMMED
, inst
);
12732 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12733 inst
.operands
[2].imm
);
12737 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12738 struct neon_type_el et
= neon_check_type (3, rs
,
12739 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12742 /* See note in do_neon_shl_imm. */
12743 tmp
= inst
.operands
[2].reg
;
12744 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12745 inst
.operands
[1].reg
= tmp
;
12746 NEON_ENCODE (INTEGER
, inst
);
12747 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12752 do_neon_rshl (void)
12754 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12755 struct neon_type_el et
= neon_check_type (3, rs
,
12756 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12759 tmp
= inst
.operands
[2].reg
;
12760 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12761 inst
.operands
[1].reg
= tmp
;
12762 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12766 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12768 /* Handle .I8 pseudo-instructions. */
12771 /* Unfortunately, this will make everything apart from zero out-of-range.
12772 FIXME is this the intended semantics? There doesn't seem much point in
12773 accepting .I8 if so. */
12774 immediate
|= immediate
<< 8;
12780 if (immediate
== (immediate
& 0x000000ff))
12782 *immbits
= immediate
;
12785 else if (immediate
== (immediate
& 0x0000ff00))
12787 *immbits
= immediate
>> 8;
12790 else if (immediate
== (immediate
& 0x00ff0000))
12792 *immbits
= immediate
>> 16;
12795 else if (immediate
== (immediate
& 0xff000000))
12797 *immbits
= immediate
>> 24;
12800 if ((immediate
& 0xffff) != (immediate
>> 16))
12801 goto bad_immediate
;
12802 immediate
&= 0xffff;
12805 if (immediate
== (immediate
& 0x000000ff))
12807 *immbits
= immediate
;
12810 else if (immediate
== (immediate
& 0x0000ff00))
12812 *immbits
= immediate
>> 8;
12817 first_error (_("immediate value out of range"));
12821 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12825 neon_bits_same_in_bytes (unsigned imm
)
12827 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12828 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12829 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12830 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12833 /* For immediate of above form, return 0bABCD. */
12836 neon_squash_bits (unsigned imm
)
12838 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12839 | ((imm
& 0x01000000) >> 21);
12842 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12845 neon_qfloat_bits (unsigned imm
)
12847 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12850 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12851 the instruction. *OP is passed as the initial value of the op field, and
12852 may be set to a different value depending on the constant (i.e.
12853 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12854 MVN). If the immediate looks like a repeated pattern then also
12855 try smaller element sizes. */
12858 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12859 unsigned *immbits
, int *op
, int size
,
12860 enum neon_el_type type
)
12862 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12864 if (type
== NT_float
&& !float_p
)
12867 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12869 if (size
!= 32 || *op
== 1)
12871 *immbits
= neon_qfloat_bits (immlo
);
12877 if (neon_bits_same_in_bytes (immhi
)
12878 && neon_bits_same_in_bytes (immlo
))
12882 *immbits
= (neon_squash_bits (immhi
) << 4)
12883 | neon_squash_bits (immlo
);
12888 if (immhi
!= immlo
)
12894 if (immlo
== (immlo
& 0x000000ff))
12899 else if (immlo
== (immlo
& 0x0000ff00))
12901 *immbits
= immlo
>> 8;
12904 else if (immlo
== (immlo
& 0x00ff0000))
12906 *immbits
= immlo
>> 16;
12909 else if (immlo
== (immlo
& 0xff000000))
12911 *immbits
= immlo
>> 24;
12914 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12916 *immbits
= (immlo
>> 8) & 0xff;
12919 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12921 *immbits
= (immlo
>> 16) & 0xff;
12925 if ((immlo
& 0xffff) != (immlo
>> 16))
12932 if (immlo
== (immlo
& 0x000000ff))
12937 else if (immlo
== (immlo
& 0x0000ff00))
12939 *immbits
= immlo
>> 8;
12943 if ((immlo
& 0xff) != (immlo
>> 8))
12948 if (immlo
== (immlo
& 0x000000ff))
12950 /* Don't allow MVN with 8-bit immediate. */
12960 /* Write immediate bits [7:0] to the following locations:
12962 |28/24|23 19|18 16|15 4|3 0|
12963 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12965 This function is used by VMOV/VMVN/VORR/VBIC. */
12968 neon_write_immbits (unsigned immbits
)
12970 inst
.instruction
|= immbits
& 0xf;
12971 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12972 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12975 /* Invert low-order SIZE bits of XHI:XLO. */
12978 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12980 unsigned immlo
= xlo
? *xlo
: 0;
12981 unsigned immhi
= xhi
? *xhi
: 0;
12986 immlo
= (~immlo
) & 0xff;
12990 immlo
= (~immlo
) & 0xffff;
12994 immhi
= (~immhi
) & 0xffffffff;
12995 /* fall through. */
12998 immlo
= (~immlo
) & 0xffffffff;
13013 do_neon_logic (void)
13015 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13017 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13018 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13019 /* U bit and size field were set as part of the bitmask. */
13020 NEON_ENCODE (INTEGER
, inst
);
13021 neon_three_same (neon_quad (rs
), 0, -1);
13025 const int three_ops_form
= (inst
.operands
[2].present
13026 && !inst
.operands
[2].isreg
);
13027 const int immoperand
= (three_ops_form
? 2 : 1);
13028 enum neon_shape rs
= (three_ops_form
13029 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13030 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13031 struct neon_type_el et
= neon_check_type (2, rs
,
13032 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13033 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13037 if (et
.type
== NT_invtype
)
13040 if (three_ops_form
)
13041 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13042 _("first and second operands shall be the same register"));
13044 NEON_ENCODE (IMMED
, inst
);
13046 immbits
= inst
.operands
[immoperand
].imm
;
13049 /* .i64 is a pseudo-op, so the immediate must be a repeating
13051 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13052 inst
.operands
[immoperand
].reg
: 0))
13054 /* Set immbits to an invalid constant. */
13055 immbits
= 0xdeadbeef;
13062 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13066 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13070 /* Pseudo-instruction for VBIC. */
13071 neon_invert_size (&immbits
, 0, et
.size
);
13072 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13076 /* Pseudo-instruction for VORR. */
13077 neon_invert_size (&immbits
, 0, et
.size
);
13078 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13088 inst
.instruction
|= neon_quad (rs
) << 6;
13089 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13090 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13091 inst
.instruction
|= cmode
<< 8;
13092 neon_write_immbits (immbits
);
13094 neon_dp_fixup (&inst
);
13099 do_neon_bitfield (void)
13101 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13102 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13103 neon_three_same (neon_quad (rs
), 0, -1);
13107 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13110 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13111 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13113 if (et
.type
== NT_float
)
13115 NEON_ENCODE (FLOAT
, inst
);
13116 neon_three_same (neon_quad (rs
), 0, -1);
13120 NEON_ENCODE (INTEGER
, inst
);
13121 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13126 do_neon_dyadic_if_su (void)
13128 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13132 do_neon_dyadic_if_su_d (void)
13134 /* This version only allow D registers, but that constraint is enforced during
13135 operand parsing so we don't need to do anything extra here. */
13136 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13140 do_neon_dyadic_if_i_d (void)
13142 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13143 affected if we specify unsigned args. */
13144 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13147 enum vfp_or_neon_is_neon_bits
13150 NEON_CHECK_ARCH
= 2
13153 /* Call this function if an instruction which may have belonged to the VFP or
13154 Neon instruction sets, but turned out to be a Neon instruction (due to the
13155 operand types involved, etc.). We have to check and/or fix-up a couple of
13158 - Make sure the user hasn't attempted to make a Neon instruction
13160 - Alter the value in the condition code field if necessary.
13161 - Make sure that the arch supports Neon instructions.
13163 Which of these operations take place depends on bits from enum
13164 vfp_or_neon_is_neon_bits.
13166 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13167 current instruction's condition is COND_ALWAYS, the condition field is
13168 changed to inst.uncond_value. This is necessary because instructions shared
13169 between VFP and Neon may be conditional for the VFP variants only, and the
13170 unconditional Neon version must have, e.g., 0xF in the condition field. */
13173 vfp_or_neon_is_neon (unsigned check
)
13175 /* Conditions are always legal in Thumb mode (IT blocks). */
13176 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13178 if (inst
.cond
!= COND_ALWAYS
)
13180 first_error (_(BAD_COND
));
13183 if (inst
.uncond_value
!= -1)
13184 inst
.instruction
|= inst
.uncond_value
<< 28;
13187 if ((check
& NEON_CHECK_ARCH
)
13188 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13190 first_error (_(BAD_FPU
));
13198 do_neon_addsub_if_i (void)
13200 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13203 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13206 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13207 affected if we specify unsigned args. */
13208 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13211 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13213 V<op> A,B (A is operand 0, B is operand 2)
13218 so handle that case specially. */
13221 neon_exchange_operands (void)
13223 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13224 if (inst
.operands
[1].present
)
13226 /* Swap operands[1] and operands[2]. */
13227 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13228 inst
.operands
[1] = inst
.operands
[2];
13229 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13233 inst
.operands
[1] = inst
.operands
[2];
13234 inst
.operands
[2] = inst
.operands
[0];
13239 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13241 if (inst
.operands
[2].isreg
)
13244 neon_exchange_operands ();
13245 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13249 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13250 struct neon_type_el et
= neon_check_type (2, rs
,
13251 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13253 NEON_ENCODE (IMMED
, inst
);
13254 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13255 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13256 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13257 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13258 inst
.instruction
|= neon_quad (rs
) << 6;
13259 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13260 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13262 neon_dp_fixup (&inst
);
13269 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13273 do_neon_cmp_inv (void)
13275 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13281 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13284 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13285 scalars, which are encoded in 5 bits, M : Rm.
13286 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13287 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13291 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13293 unsigned regno
= NEON_SCALAR_REG (scalar
);
13294 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13299 if (regno
> 7 || elno
> 3)
13301 return regno
| (elno
<< 3);
13304 if (regno
> 15 || elno
> 1)
13306 return regno
| (elno
<< 4);
13310 first_error (_("scalar out of range for multiply instruction"));
13316 /* Encode multiply / multiply-accumulate scalar instructions. */
13319 neon_mul_mac (struct neon_type_el et
, int ubit
)
13323 /* Give a more helpful error message if we have an invalid type. */
13324 if (et
.type
== NT_invtype
)
13327 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13328 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13329 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13330 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13331 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13332 inst
.instruction
|= LOW4 (scalar
);
13333 inst
.instruction
|= HI1 (scalar
) << 5;
13334 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13335 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13336 inst
.instruction
|= (ubit
!= 0) << 24;
13338 neon_dp_fixup (&inst
);
13342 do_neon_mac_maybe_scalar (void)
13344 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13347 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13350 if (inst
.operands
[2].isscalar
)
13352 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13353 struct neon_type_el et
= neon_check_type (3, rs
,
13354 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13355 NEON_ENCODE (SCALAR
, inst
);
13356 neon_mul_mac (et
, neon_quad (rs
));
13360 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13361 affected if we specify unsigned args. */
13362 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13367 do_neon_fmac (void)
13369 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13372 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13375 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13381 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13382 struct neon_type_el et
= neon_check_type (3, rs
,
13383 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13384 neon_three_same (neon_quad (rs
), 0, et
.size
);
13387 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13388 same types as the MAC equivalents. The polynomial type for this instruction
13389 is encoded the same as the integer type. */
13394 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13397 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13400 if (inst
.operands
[2].isscalar
)
13401 do_neon_mac_maybe_scalar ();
13403 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13407 do_neon_qdmulh (void)
13409 if (inst
.operands
[2].isscalar
)
13411 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13412 struct neon_type_el et
= neon_check_type (3, rs
,
13413 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13414 NEON_ENCODE (SCALAR
, inst
);
13415 neon_mul_mac (et
, neon_quad (rs
));
13419 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13420 struct neon_type_el et
= neon_check_type (3, rs
,
13421 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13422 NEON_ENCODE (INTEGER
, inst
);
13423 /* The U bit (rounding) comes from bit mask. */
13424 neon_three_same (neon_quad (rs
), 0, et
.size
);
13429 do_neon_fcmp_absolute (void)
13431 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13432 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13433 /* Size field comes from bit mask. */
13434 neon_three_same (neon_quad (rs
), 1, -1);
13438 do_neon_fcmp_absolute_inv (void)
13440 neon_exchange_operands ();
13441 do_neon_fcmp_absolute ();
13445 do_neon_step (void)
13447 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13448 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13449 neon_three_same (neon_quad (rs
), 0, -1);
13453 do_neon_abs_neg (void)
13455 enum neon_shape rs
;
13456 struct neon_type_el et
;
13458 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13461 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13464 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13465 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13467 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13468 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13469 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13470 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13471 inst
.instruction
|= neon_quad (rs
) << 6;
13472 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13473 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13475 neon_dp_fixup (&inst
);
13481 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13482 struct neon_type_el et
= neon_check_type (2, rs
,
13483 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13484 int imm
= inst
.operands
[2].imm
;
13485 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13486 _("immediate out of range for insert"));
13487 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13493 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13494 struct neon_type_el et
= neon_check_type (2, rs
,
13495 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13496 int imm
= inst
.operands
[2].imm
;
13497 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13498 _("immediate out of range for insert"));
13499 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13503 do_neon_qshlu_imm (void)
13505 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13506 struct neon_type_el et
= neon_check_type (2, rs
,
13507 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13508 int imm
= inst
.operands
[2].imm
;
13509 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13510 _("immediate out of range for shift"));
13511 /* Only encodes the 'U present' variant of the instruction.
13512 In this case, signed types have OP (bit 8) set to 0.
13513 Unsigned types have OP set to 1. */
13514 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13515 /* The rest of the bits are the same as other immediate shifts. */
13516 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13520 do_neon_qmovn (void)
13522 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13523 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13524 /* Saturating move where operands can be signed or unsigned, and the
13525 destination has the same signedness. */
13526 NEON_ENCODE (INTEGER
, inst
);
13527 if (et
.type
== NT_unsigned
)
13528 inst
.instruction
|= 0xc0;
13530 inst
.instruction
|= 0x80;
13531 neon_two_same (0, 1, et
.size
/ 2);
13535 do_neon_qmovun (void)
13537 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13538 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13539 /* Saturating move with unsigned results. Operands must be signed. */
13540 NEON_ENCODE (INTEGER
, inst
);
13541 neon_two_same (0, 1, et
.size
/ 2);
13545 do_neon_rshift_sat_narrow (void)
13547 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13548 or unsigned. If operands are unsigned, results must also be unsigned. */
13549 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13550 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13551 int imm
= inst
.operands
[2].imm
;
13552 /* This gets the bounds check, size encoding and immediate bits calculation
13556 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13557 VQMOVN.I<size> <Dd>, <Qm>. */
13560 inst
.operands
[2].present
= 0;
13561 inst
.instruction
= N_MNEM_vqmovn
;
13566 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13567 _("immediate out of range"));
13568 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13572 do_neon_rshift_sat_narrow_u (void)
13574 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13575 or unsigned. If operands are unsigned, results must also be unsigned. */
13576 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13577 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13578 int imm
= inst
.operands
[2].imm
;
13579 /* This gets the bounds check, size encoding and immediate bits calculation
13583 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13584 VQMOVUN.I<size> <Dd>, <Qm>. */
13587 inst
.operands
[2].present
= 0;
13588 inst
.instruction
= N_MNEM_vqmovun
;
13593 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13594 _("immediate out of range"));
13595 /* FIXME: The manual is kind of unclear about what value U should have in
13596 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13598 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13602 do_neon_movn (void)
13604 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13605 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13606 NEON_ENCODE (INTEGER
, inst
);
13607 neon_two_same (0, 1, et
.size
/ 2);
13611 do_neon_rshift_narrow (void)
13613 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13614 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13615 int imm
= inst
.operands
[2].imm
;
13616 /* This gets the bounds check, size encoding and immediate bits calculation
13620 /* If immediate is zero then we are a pseudo-instruction for
13621 VMOVN.I<size> <Dd>, <Qm> */
13624 inst
.operands
[2].present
= 0;
13625 inst
.instruction
= N_MNEM_vmovn
;
13630 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13631 _("immediate out of range for narrowing operation"));
13632 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13636 do_neon_shll (void)
13638 /* FIXME: Type checking when lengthening. */
13639 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13640 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13641 unsigned imm
= inst
.operands
[2].imm
;
13643 if (imm
== et
.size
)
13645 /* Maximum shift variant. */
13646 NEON_ENCODE (INTEGER
, inst
);
13647 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13648 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13649 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13650 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13651 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13653 neon_dp_fixup (&inst
);
13657 /* A more-specific type check for non-max versions. */
13658 et
= neon_check_type (2, NS_QDI
,
13659 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13660 NEON_ENCODE (IMMED
, inst
);
13661 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13665 /* Check the various types for the VCVT instruction, and return which version
13666 the current instruction is. */
13669 neon_cvt_flavour (enum neon_shape rs
)
13671 #define CVT_VAR(C,X,Y) \
13672 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13673 if (et.type != NT_invtype) \
13675 inst.error = NULL; \
13678 struct neon_type_el et
;
13679 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13680 || rs
== NS_FF
) ? N_VFP
: 0;
13681 /* The instruction versions which take an immediate take one register
13682 argument, which is extended to the width of the full register. Thus the
13683 "source" and "destination" registers must have the same width. Hack that
13684 here by making the size equal to the key (wider, in this case) operand. */
13685 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13687 CVT_VAR (0, N_S32
, N_F32
);
13688 CVT_VAR (1, N_U32
, N_F32
);
13689 CVT_VAR (2, N_F32
, N_S32
);
13690 CVT_VAR (3, N_F32
, N_U32
);
13691 /* Half-precision conversions. */
13692 CVT_VAR (4, N_F32
, N_F16
);
13693 CVT_VAR (5, N_F16
, N_F32
);
13697 /* VFP instructions. */
13698 CVT_VAR (6, N_F32
, N_F64
);
13699 CVT_VAR (7, N_F64
, N_F32
);
13700 CVT_VAR (8, N_S32
, N_F64
| key
);
13701 CVT_VAR (9, N_U32
, N_F64
| key
);
13702 CVT_VAR (10, N_F64
| key
, N_S32
);
13703 CVT_VAR (11, N_F64
| key
, N_U32
);
13704 /* VFP instructions with bitshift. */
13705 CVT_VAR (12, N_F32
| key
, N_S16
);
13706 CVT_VAR (13, N_F32
| key
, N_U16
);
13707 CVT_VAR (14, N_F64
| key
, N_S16
);
13708 CVT_VAR (15, N_F64
| key
, N_U16
);
13709 CVT_VAR (16, N_S16
, N_F32
| key
);
13710 CVT_VAR (17, N_U16
, N_F32
| key
);
13711 CVT_VAR (18, N_S16
, N_F64
| key
);
13712 CVT_VAR (19, N_U16
, N_F64
| key
);
13718 /* Neon-syntax VFP conversions. */
13721 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13723 const char *opname
= 0;
13725 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13727 /* Conversions with immediate bitshift. */
13728 const char *enc
[] =
13752 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13754 opname
= enc
[flavour
];
13755 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13756 _("operands 0 and 1 must be the same register"));
13757 inst
.operands
[1] = inst
.operands
[2];
13758 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13763 /* Conversions without bitshift. */
13764 const char *enc
[] =
13780 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13781 opname
= enc
[flavour
];
13785 do_vfp_nsyn_opcode (opname
);
13789 do_vfp_nsyn_cvtz (void)
13791 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13792 int flavour
= neon_cvt_flavour (rs
);
13793 const char *enc
[] =
13807 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13808 do_vfp_nsyn_opcode (enc
[flavour
]);
13812 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
13814 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13815 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13816 int flavour
= neon_cvt_flavour (rs
);
13818 /* PR11109: Handle round-to-zero for VCVT conversions. */
13820 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
13821 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
13822 && (rs
== NS_FD
|| rs
== NS_FF
))
13824 do_vfp_nsyn_cvtz ();
13828 /* VFP rather than Neon conversions. */
13831 do_vfp_nsyn_cvt (rs
, flavour
);
13841 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13843 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13846 /* Fixed-point conversion with #0 immediate is encoded as an
13847 integer conversion. */
13848 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13850 immbits
= 32 - inst
.operands
[2].imm
;
13851 NEON_ENCODE (IMMED
, inst
);
13853 inst
.instruction
|= enctab
[flavour
];
13854 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13855 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13856 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13857 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13858 inst
.instruction
|= neon_quad (rs
) << 6;
13859 inst
.instruction
|= 1 << 21;
13860 inst
.instruction
|= immbits
<< 16;
13862 neon_dp_fixup (&inst
);
13870 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13872 NEON_ENCODE (INTEGER
, inst
);
13874 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13878 inst
.instruction
|= enctab
[flavour
];
13880 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13881 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13882 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13883 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13884 inst
.instruction
|= neon_quad (rs
) << 6;
13885 inst
.instruction
|= 2 << 18;
13887 neon_dp_fixup (&inst
);
13891 /* Half-precision conversions for Advanced SIMD -- neon. */
13896 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13898 as_bad (_("operand size must match register width"));
13903 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13905 as_bad (_("operand size must match register width"));
13910 inst
.instruction
= 0x3b60600;
13912 inst
.instruction
= 0x3b60700;
13914 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13915 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13916 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13917 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13918 neon_dp_fixup (&inst
);
13922 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13923 do_vfp_nsyn_cvt (rs
, flavour
);
13928 do_neon_cvtr (void)
13930 do_neon_cvt_1 (FALSE
);
13936 do_neon_cvt_1 (TRUE
);
13940 do_neon_cvtb (void)
13942 inst
.instruction
= 0xeb20a40;
13944 /* The sizes are attached to the mnemonic. */
13945 if (inst
.vectype
.el
[0].type
!= NT_invtype
13946 && inst
.vectype
.el
[0].size
== 16)
13947 inst
.instruction
|= 0x00010000;
13949 /* Programmer's syntax: the sizes are attached to the operands. */
13950 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13951 && inst
.operands
[0].vectype
.size
== 16)
13952 inst
.instruction
|= 0x00010000;
13954 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13955 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13956 do_vfp_cond_or_thumb ();
13961 do_neon_cvtt (void)
13964 inst
.instruction
|= 0x80;
13968 neon_move_immediate (void)
13970 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13971 struct neon_type_el et
= neon_check_type (2, rs
,
13972 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13973 unsigned immlo
, immhi
= 0, immbits
;
13974 int op
, cmode
, float_p
;
13976 constraint (et
.type
== NT_invtype
,
13977 _("operand size must be specified for immediate VMOV"));
13979 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13980 op
= (inst
.instruction
& (1 << 5)) != 0;
13982 immlo
= inst
.operands
[1].imm
;
13983 if (inst
.operands
[1].regisimm
)
13984 immhi
= inst
.operands
[1].reg
;
13986 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13987 _("immediate has bits set outside the operand size"));
13989 float_p
= inst
.operands
[1].immisfloat
;
13991 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13992 et
.size
, et
.type
)) == FAIL
)
13994 /* Invert relevant bits only. */
13995 neon_invert_size (&immlo
, &immhi
, et
.size
);
13996 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13997 with one or the other; those cases are caught by
13998 neon_cmode_for_move_imm. */
14000 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14001 &op
, et
.size
, et
.type
)) == FAIL
)
14003 first_error (_("immediate out of range"));
14008 inst
.instruction
&= ~(1 << 5);
14009 inst
.instruction
|= op
<< 5;
14011 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14012 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14013 inst
.instruction
|= neon_quad (rs
) << 6;
14014 inst
.instruction
|= cmode
<< 8;
14016 neon_write_immbits (immbits
);
14022 if (inst
.operands
[1].isreg
)
14024 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14026 NEON_ENCODE (INTEGER
, inst
);
14027 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14028 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14029 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14030 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14031 inst
.instruction
|= neon_quad (rs
) << 6;
14035 NEON_ENCODE (IMMED
, inst
);
14036 neon_move_immediate ();
14039 neon_dp_fixup (&inst
);
14042 /* Encode instructions of form:
14044 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14045 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14048 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14050 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14051 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14052 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14053 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14054 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14055 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14056 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14057 inst
.instruction
|= neon_logbits (size
) << 20;
14059 neon_dp_fixup (&inst
);
14063 do_neon_dyadic_long (void)
14065 /* FIXME: Type checking for lengthening op. */
14066 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14067 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14068 neon_mixed_length (et
, et
.size
);
14072 do_neon_abal (void)
14074 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14075 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14076 neon_mixed_length (et
, et
.size
);
14080 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14082 if (inst
.operands
[2].isscalar
)
14084 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14085 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14086 NEON_ENCODE (SCALAR
, inst
);
14087 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14091 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14092 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14093 NEON_ENCODE (INTEGER
, inst
);
14094 neon_mixed_length (et
, et
.size
);
14099 do_neon_mac_maybe_scalar_long (void)
14101 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14105 do_neon_dyadic_wide (void)
14107 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14108 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14109 neon_mixed_length (et
, et
.size
);
14113 do_neon_dyadic_narrow (void)
14115 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14116 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14117 /* Operand sign is unimportant, and the U bit is part of the opcode,
14118 so force the operand type to integer. */
14119 et
.type
= NT_integer
;
14120 neon_mixed_length (et
, et
.size
/ 2);
14124 do_neon_mul_sat_scalar_long (void)
14126 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14130 do_neon_vmull (void)
14132 if (inst
.operands
[2].isscalar
)
14133 do_neon_mac_maybe_scalar_long ();
14136 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14137 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14138 if (et
.type
== NT_poly
)
14139 NEON_ENCODE (POLY
, inst
);
14141 NEON_ENCODE (INTEGER
, inst
);
14142 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14143 zero. Should be OK as-is. */
14144 neon_mixed_length (et
, et
.size
);
14151 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14152 struct neon_type_el et
= neon_check_type (3, rs
,
14153 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14154 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14156 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14157 _("shift out of range"));
14158 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14159 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14160 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14161 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14162 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14163 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14164 inst
.instruction
|= neon_quad (rs
) << 6;
14165 inst
.instruction
|= imm
<< 8;
14167 neon_dp_fixup (&inst
);
14173 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14174 struct neon_type_el et
= neon_check_type (2, rs
,
14175 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14176 unsigned op
= (inst
.instruction
>> 7) & 3;
14177 /* N (width of reversed regions) is encoded as part of the bitmask. We
14178 extract it here to check the elements to be reversed are smaller.
14179 Otherwise we'd get a reserved instruction. */
14180 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14181 gas_assert (elsize
!= 0);
14182 constraint (et
.size
>= elsize
,
14183 _("elements must be smaller than reversal region"));
14184 neon_two_same (neon_quad (rs
), 1, et
.size
);
14190 if (inst
.operands
[1].isscalar
)
14192 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14193 struct neon_type_el et
= neon_check_type (2, rs
,
14194 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14195 unsigned sizebits
= et
.size
>> 3;
14196 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14197 int logsize
= neon_logbits (et
.size
);
14198 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14200 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14203 NEON_ENCODE (SCALAR
, inst
);
14204 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14205 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14206 inst
.instruction
|= LOW4 (dm
);
14207 inst
.instruction
|= HI1 (dm
) << 5;
14208 inst
.instruction
|= neon_quad (rs
) << 6;
14209 inst
.instruction
|= x
<< 17;
14210 inst
.instruction
|= sizebits
<< 16;
14212 neon_dp_fixup (&inst
);
14216 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14217 struct neon_type_el et
= neon_check_type (2, rs
,
14218 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14219 /* Duplicate ARM register to lanes of vector. */
14220 NEON_ENCODE (ARMREG
, inst
);
14223 case 8: inst
.instruction
|= 0x400000; break;
14224 case 16: inst
.instruction
|= 0x000020; break;
14225 case 32: inst
.instruction
|= 0x000000; break;
14228 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14229 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14230 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14231 inst
.instruction
|= neon_quad (rs
) << 21;
14232 /* The encoding for this instruction is identical for the ARM and Thumb
14233 variants, except for the condition field. */
14234 do_vfp_cond_or_thumb ();
14238 /* VMOV has particularly many variations. It can be one of:
14239 0. VMOV<c><q> <Qd>, <Qm>
14240 1. VMOV<c><q> <Dd>, <Dm>
14241 (Register operations, which are VORR with Rm = Rn.)
14242 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14243 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14245 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14246 (ARM register to scalar.)
14247 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14248 (Two ARM registers to vector.)
14249 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14250 (Scalar to ARM register.)
14251 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14252 (Vector to two ARM registers.)
14253 8. VMOV.F32 <Sd>, <Sm>
14254 9. VMOV.F64 <Dd>, <Dm>
14255 (VFP register moves.)
14256 10. VMOV.F32 <Sd>, #imm
14257 11. VMOV.F64 <Dd>, #imm
14258 (VFP float immediate load.)
14259 12. VMOV <Rd>, <Sm>
14260 (VFP single to ARM reg.)
14261 13. VMOV <Sd>, <Rm>
14262 (ARM reg to VFP single.)
14263 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14264 (Two ARM regs to two VFP singles.)
14265 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14266 (Two VFP singles to two ARM regs.)
14268 These cases can be disambiguated using neon_select_shape, except cases 1/9
14269 and 3/11 which depend on the operand type too.
14271 All the encoded bits are hardcoded by this function.
14273 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14274 Cases 5, 7 may be used with VFPv2 and above.
14276 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14277 can specify a type where it doesn't make sense to, and is ignored). */
14282 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14283 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14285 struct neon_type_el et
;
14286 const char *ldconst
= 0;
14290 case NS_DD
: /* case 1/9. */
14291 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14292 /* It is not an error here if no type is given. */
14294 if (et
.type
== NT_float
&& et
.size
== 64)
14296 do_vfp_nsyn_opcode ("fcpyd");
14299 /* fall through. */
14301 case NS_QQ
: /* case 0/1. */
14303 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14305 /* The architecture manual I have doesn't explicitly state which
14306 value the U bit should have for register->register moves, but
14307 the equivalent VORR instruction has U = 0, so do that. */
14308 inst
.instruction
= 0x0200110;
14309 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14310 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14311 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14312 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14313 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14314 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14315 inst
.instruction
|= neon_quad (rs
) << 6;
14317 neon_dp_fixup (&inst
);
14321 case NS_DI
: /* case 3/11. */
14322 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14324 if (et
.type
== NT_float
&& et
.size
== 64)
14326 /* case 11 (fconstd). */
14327 ldconst
= "fconstd";
14328 goto encode_fconstd
;
14330 /* fall through. */
14332 case NS_QI
: /* case 2/3. */
14333 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14335 inst
.instruction
= 0x0800010;
14336 neon_move_immediate ();
14337 neon_dp_fixup (&inst
);
14340 case NS_SR
: /* case 4. */
14342 unsigned bcdebits
= 0;
14344 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14345 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14347 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14348 logsize
= neon_logbits (et
.size
);
14350 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14352 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14353 && et
.size
!= 32, _(BAD_FPU
));
14354 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14355 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14359 case 8: bcdebits
= 0x8; break;
14360 case 16: bcdebits
= 0x1; break;
14361 case 32: bcdebits
= 0x0; break;
14365 bcdebits
|= x
<< logsize
;
14367 inst
.instruction
= 0xe000b10;
14368 do_vfp_cond_or_thumb ();
14369 inst
.instruction
|= LOW4 (dn
) << 16;
14370 inst
.instruction
|= HI1 (dn
) << 7;
14371 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14372 inst
.instruction
|= (bcdebits
& 3) << 5;
14373 inst
.instruction
|= (bcdebits
>> 2) << 21;
14377 case NS_DRR
: /* case 5 (fmdrr). */
14378 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14381 inst
.instruction
= 0xc400b10;
14382 do_vfp_cond_or_thumb ();
14383 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14384 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14385 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14386 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14389 case NS_RS
: /* case 6. */
14392 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14393 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14394 unsigned abcdebits
= 0;
14396 et
= neon_check_type (2, NS_NULL
,
14397 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14398 logsize
= neon_logbits (et
.size
);
14400 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14402 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14403 && et
.size
!= 32, _(BAD_FPU
));
14404 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14405 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14409 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14410 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14411 case 32: abcdebits
= 0x00; break;
14415 abcdebits
|= x
<< logsize
;
14416 inst
.instruction
= 0xe100b10;
14417 do_vfp_cond_or_thumb ();
14418 inst
.instruction
|= LOW4 (dn
) << 16;
14419 inst
.instruction
|= HI1 (dn
) << 7;
14420 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14421 inst
.instruction
|= (abcdebits
& 3) << 5;
14422 inst
.instruction
|= (abcdebits
>> 2) << 21;
14426 case NS_RRD
: /* case 7 (fmrrd). */
14427 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14430 inst
.instruction
= 0xc500b10;
14431 do_vfp_cond_or_thumb ();
14432 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14433 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14434 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14435 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14438 case NS_FF
: /* case 8 (fcpys). */
14439 do_vfp_nsyn_opcode ("fcpys");
14442 case NS_FI
: /* case 10 (fconsts). */
14443 ldconst
= "fconsts";
14445 if (is_quarter_float (inst
.operands
[1].imm
))
14447 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14448 do_vfp_nsyn_opcode (ldconst
);
14451 first_error (_("immediate out of range"));
14454 case NS_RF
: /* case 12 (fmrs). */
14455 do_vfp_nsyn_opcode ("fmrs");
14458 case NS_FR
: /* case 13 (fmsr). */
14459 do_vfp_nsyn_opcode ("fmsr");
14462 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14463 (one of which is a list), but we have parsed four. Do some fiddling to
14464 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14466 case NS_RRFF
: /* case 14 (fmrrs). */
14467 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14468 _("VFP registers must be adjacent"));
14469 inst
.operands
[2].imm
= 2;
14470 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14471 do_vfp_nsyn_opcode ("fmrrs");
14474 case NS_FFRR
: /* case 15 (fmsrr). */
14475 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14476 _("VFP registers must be adjacent"));
14477 inst
.operands
[1] = inst
.operands
[2];
14478 inst
.operands
[2] = inst
.operands
[3];
14479 inst
.operands
[0].imm
= 2;
14480 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14481 do_vfp_nsyn_opcode ("fmsrr");
14490 do_neon_rshift_round_imm (void)
14492 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14493 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14494 int imm
= inst
.operands
[2].imm
;
14496 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14499 inst
.operands
[2].present
= 0;
14504 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14505 _("immediate out of range for shift"));
14506 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14511 do_neon_movl (void)
14513 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14514 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14515 unsigned sizebits
= et
.size
>> 3;
14516 inst
.instruction
|= sizebits
<< 19;
14517 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14523 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14524 struct neon_type_el et
= neon_check_type (2, rs
,
14525 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14526 NEON_ENCODE (INTEGER
, inst
);
14527 neon_two_same (neon_quad (rs
), 1, et
.size
);
14531 do_neon_zip_uzp (void)
14533 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14534 struct neon_type_el et
= neon_check_type (2, rs
,
14535 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14536 if (rs
== NS_DD
&& et
.size
== 32)
14538 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14539 inst
.instruction
= N_MNEM_vtrn
;
14543 neon_two_same (neon_quad (rs
), 1, et
.size
);
14547 do_neon_sat_abs_neg (void)
14549 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14550 struct neon_type_el et
= neon_check_type (2, rs
,
14551 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14552 neon_two_same (neon_quad (rs
), 1, et
.size
);
14556 do_neon_pair_long (void)
14558 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14559 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14560 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14561 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14562 neon_two_same (neon_quad (rs
), 1, et
.size
);
14566 do_neon_recip_est (void)
14568 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14569 struct neon_type_el et
= neon_check_type (2, rs
,
14570 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14571 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14572 neon_two_same (neon_quad (rs
), 1, et
.size
);
14578 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14579 struct neon_type_el et
= neon_check_type (2, rs
,
14580 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14581 neon_two_same (neon_quad (rs
), 1, et
.size
);
14587 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14588 struct neon_type_el et
= neon_check_type (2, rs
,
14589 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14590 neon_two_same (neon_quad (rs
), 1, et
.size
);
14596 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14597 struct neon_type_el et
= neon_check_type (2, rs
,
14598 N_EQK
| N_INT
, N_8
| N_KEY
);
14599 neon_two_same (neon_quad (rs
), 1, et
.size
);
14605 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14606 neon_two_same (neon_quad (rs
), 1, -1);
14610 do_neon_tbl_tbx (void)
14612 unsigned listlenbits
;
14613 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14615 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14617 first_error (_("bad list length for table lookup"));
14621 listlenbits
= inst
.operands
[1].imm
- 1;
14622 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14623 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14624 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14625 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14626 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14627 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14628 inst
.instruction
|= listlenbits
<< 8;
14630 neon_dp_fixup (&inst
);
14634 do_neon_ldm_stm (void)
14636 /* P, U and L bits are part of bitmask. */
14637 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14638 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14640 if (inst
.operands
[1].issingle
)
14642 do_vfp_nsyn_ldm_stm (is_dbmode
);
14646 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14647 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14649 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14650 _("register list must contain at least 1 and at most 16 "
14653 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14654 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14655 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14656 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14658 inst
.instruction
|= offsetbits
;
14660 do_vfp_cond_or_thumb ();
14664 do_neon_ldr_str (void)
14666 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14668 if (inst
.operands
[0].issingle
)
14671 do_vfp_nsyn_opcode ("flds");
14673 do_vfp_nsyn_opcode ("fsts");
14678 do_vfp_nsyn_opcode ("fldd");
14680 do_vfp_nsyn_opcode ("fstd");
14684 /* "interleave" version also handles non-interleaving register VLD1/VST1
14688 do_neon_ld_st_interleave (void)
14690 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14691 N_8
| N_16
| N_32
| N_64
);
14692 unsigned alignbits
= 0;
14694 /* The bits in this table go:
14695 0: register stride of one (0) or two (1)
14696 1,2: register list length, minus one (1, 2, 3, 4).
14697 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14698 We use -1 for invalid entries. */
14699 const int typetable
[] =
14701 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14702 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14703 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14704 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14708 if (et
.type
== NT_invtype
)
14711 if (inst
.operands
[1].immisalign
)
14712 switch (inst
.operands
[1].imm
>> 8)
14714 case 64: alignbits
= 1; break;
14716 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
14717 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14718 goto bad_alignment
;
14722 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14723 goto bad_alignment
;
14728 first_error (_("bad alignment"));
14732 inst
.instruction
|= alignbits
<< 4;
14733 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14735 /* Bits [4:6] of the immediate in a list specifier encode register stride
14736 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14737 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14738 up the right value for "type" in a table based on this value and the given
14739 list style, then stick it back. */
14740 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14741 | (((inst
.instruction
>> 8) & 3) << 3);
14743 typebits
= typetable
[idx
];
14745 constraint (typebits
== -1, _("bad list type for instruction"));
14747 inst
.instruction
&= ~0xf00;
14748 inst
.instruction
|= typebits
<< 8;
14751 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14752 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14753 otherwise. The variable arguments are a list of pairs of legal (size, align)
14754 values, terminated with -1. */
14757 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14760 int result
= FAIL
, thissize
, thisalign
;
14762 if (!inst
.operands
[1].immisalign
)
14768 va_start (ap
, do_align
);
14772 thissize
= va_arg (ap
, int);
14773 if (thissize
== -1)
14775 thisalign
= va_arg (ap
, int);
14777 if (size
== thissize
&& align
== thisalign
)
14780 while (result
!= SUCCESS
);
14784 if (result
== SUCCESS
)
14787 first_error (_("unsupported alignment for instruction"));
14793 do_neon_ld_st_lane (void)
14795 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14796 int align_good
, do_align
= 0;
14797 int logsize
= neon_logbits (et
.size
);
14798 int align
= inst
.operands
[1].imm
>> 8;
14799 int n
= (inst
.instruction
>> 8) & 3;
14800 int max_el
= 64 / et
.size
;
14802 if (et
.type
== NT_invtype
)
14805 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14806 _("bad list length"));
14807 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14808 _("scalar index out of range"));
14809 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14811 _("stride of 2 unavailable when element size is 8"));
14815 case 0: /* VLD1 / VST1. */
14816 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14818 if (align_good
== FAIL
)
14822 unsigned alignbits
= 0;
14825 case 16: alignbits
= 0x1; break;
14826 case 32: alignbits
= 0x3; break;
14829 inst
.instruction
|= alignbits
<< 4;
14833 case 1: /* VLD2 / VST2. */
14834 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14836 if (align_good
== FAIL
)
14839 inst
.instruction
|= 1 << 4;
14842 case 2: /* VLD3 / VST3. */
14843 constraint (inst
.operands
[1].immisalign
,
14844 _("can't use alignment with this instruction"));
14847 case 3: /* VLD4 / VST4. */
14848 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14849 16, 64, 32, 64, 32, 128, -1);
14850 if (align_good
== FAIL
)
14854 unsigned alignbits
= 0;
14857 case 8: alignbits
= 0x1; break;
14858 case 16: alignbits
= 0x1; break;
14859 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14862 inst
.instruction
|= alignbits
<< 4;
14869 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14870 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14871 inst
.instruction
|= 1 << (4 + logsize
);
14873 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14874 inst
.instruction
|= logsize
<< 10;
14877 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14880 do_neon_ld_dup (void)
14882 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14883 int align_good
, do_align
= 0;
14885 if (et
.type
== NT_invtype
)
14888 switch ((inst
.instruction
>> 8) & 3)
14890 case 0: /* VLD1. */
14891 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14892 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14893 &do_align
, 16, 16, 32, 32, -1);
14894 if (align_good
== FAIL
)
14896 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14899 case 2: inst
.instruction
|= 1 << 5; break;
14900 default: first_error (_("bad list length")); return;
14902 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14905 case 1: /* VLD2. */
14906 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14907 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14908 if (align_good
== FAIL
)
14910 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14911 _("bad list length"));
14912 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14913 inst
.instruction
|= 1 << 5;
14914 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14917 case 2: /* VLD3. */
14918 constraint (inst
.operands
[1].immisalign
,
14919 _("can't use alignment with this instruction"));
14920 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14921 _("bad list length"));
14922 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14923 inst
.instruction
|= 1 << 5;
14924 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14927 case 3: /* VLD4. */
14929 int align
= inst
.operands
[1].imm
>> 8;
14930 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14931 16, 64, 32, 64, 32, 128, -1);
14932 if (align_good
== FAIL
)
14934 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14935 _("bad list length"));
14936 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14937 inst
.instruction
|= 1 << 5;
14938 if (et
.size
== 32 && align
== 128)
14939 inst
.instruction
|= 0x3 << 6;
14941 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14948 inst
.instruction
|= do_align
<< 4;
14951 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14952 apart from bits [11:4]. */
14955 do_neon_ldx_stx (void)
14957 if (inst
.operands
[1].isreg
)
14958 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
14960 switch (NEON_LANE (inst
.operands
[0].imm
))
14962 case NEON_INTERLEAVE_LANES
:
14963 NEON_ENCODE (INTERLV
, inst
);
14964 do_neon_ld_st_interleave ();
14967 case NEON_ALL_LANES
:
14968 NEON_ENCODE (DUP
, inst
);
14973 NEON_ENCODE (LANE
, inst
);
14974 do_neon_ld_st_lane ();
14977 /* L bit comes from bit mask. */
14978 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14979 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14980 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14982 if (inst
.operands
[1].postind
)
14984 int postreg
= inst
.operands
[1].imm
& 0xf;
14985 constraint (!inst
.operands
[1].immisreg
,
14986 _("post-index must be a register"));
14987 constraint (postreg
== 0xd || postreg
== 0xf,
14988 _("bad register for post-index"));
14989 inst
.instruction
|= postreg
;
14991 else if (inst
.operands
[1].writeback
)
14993 inst
.instruction
|= 0xd;
14996 inst
.instruction
|= 0xf;
14999 inst
.instruction
|= 0xf9000000;
15001 inst
.instruction
|= 0xf4000000;
15004 /* Overall per-instruction processing. */
15006 /* We need to be able to fix up arbitrary expressions in some statements.
15007 This is so that we can handle symbols that are an arbitrary distance from
15008 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15009 which returns part of an address in a form which will be valid for
15010 a data instruction. We do this by pushing the expression into a symbol
15011 in the expr_section, and creating a fix for that. */
15014 fix_new_arm (fragS
* frag
,
15029 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15030 (enum bfd_reloc_code_real
) reloc
);
15034 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15035 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15039 /* Mark whether the fix is to a THUMB instruction, or an ARM
15041 new_fix
->tc_fix_data
= thumb_mode
;
15044 /* Create a frg for an instruction requiring relaxation. */
15046 output_relax_insn (void)
15052 /* The size of the instruction is unknown, so tie the debug info to the
15053 start of the instruction. */
15054 dwarf2_emit_insn (0);
15056 switch (inst
.reloc
.exp
.X_op
)
15059 sym
= inst
.reloc
.exp
.X_add_symbol
;
15060 offset
= inst
.reloc
.exp
.X_add_number
;
15064 offset
= inst
.reloc
.exp
.X_add_number
;
15067 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15071 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15072 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15073 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15076 /* Write a 32-bit thumb instruction to buf. */
15078 put_thumb32_insn (char * buf
, unsigned long insn
)
15080 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15081 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15085 output_inst (const char * str
)
15091 as_bad ("%s -- `%s'", inst
.error
, str
);
15096 output_relax_insn ();
15099 if (inst
.size
== 0)
15102 to
= frag_more (inst
.size
);
15103 /* PR 9814: Record the thumb mode into the current frag so that we know
15104 what type of NOP padding to use, if necessary. We override any previous
15105 setting so that if the mode has changed then the NOPS that we use will
15106 match the encoding of the last instruction in the frag. */
15107 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15109 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15111 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15112 put_thumb32_insn (to
, inst
.instruction
);
15114 else if (inst
.size
> INSN_SIZE
)
15116 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15117 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15118 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15121 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15123 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15124 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15125 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15128 dwarf2_emit_insn (inst
.size
);
15132 output_it_inst (int cond
, int mask
, char * to
)
15134 unsigned long instruction
= 0xbf00;
15137 instruction
|= mask
;
15138 instruction
|= cond
<< 4;
15142 to
= frag_more (2);
15144 dwarf2_emit_insn (2);
15148 md_number_to_chars (to
, instruction
, 2);
15153 /* Tag values used in struct asm_opcode's tag field. */
15156 OT_unconditional
, /* Instruction cannot be conditionalized.
15157 The ARM condition field is still 0xE. */
15158 OT_unconditionalF
, /* Instruction cannot be conditionalized
15159 and carries 0xF in its ARM condition field. */
15160 OT_csuffix
, /* Instruction takes a conditional suffix. */
15161 OT_csuffixF
, /* Some forms of the instruction take a conditional
15162 suffix, others place 0xF where the condition field
15164 OT_cinfix3
, /* Instruction takes a conditional infix,
15165 beginning at character index 3. (In
15166 unified mode, it becomes a suffix.) */
15167 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15168 tsts, cmps, cmns, and teqs. */
15169 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15170 character index 3, even in unified mode. Used for
15171 legacy instructions where suffix and infix forms
15172 may be ambiguous. */
15173 OT_csuf_or_in3
, /* Instruction takes either a conditional
15174 suffix or an infix at character index 3. */
15175 OT_odd_infix_unc
, /* This is the unconditional variant of an
15176 instruction that takes a conditional infix
15177 at an unusual position. In unified mode,
15178 this variant will accept a suffix. */
15179 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15180 are the conditional variants of instructions that
15181 take conditional infixes in unusual positions.
15182 The infix appears at character index
15183 (tag - OT_odd_infix_0). These are not accepted
15184 in unified mode. */
15187 /* Subroutine of md_assemble, responsible for looking up the primary
15188 opcode from the mnemonic the user wrote. STR points to the
15189 beginning of the mnemonic.
15191 This is not simply a hash table lookup, because of conditional
15192 variants. Most instructions have conditional variants, which are
15193 expressed with a _conditional affix_ to the mnemonic. If we were
15194 to encode each conditional variant as a literal string in the opcode
15195 table, it would have approximately 20,000 entries.
15197 Most mnemonics take this affix as a suffix, and in unified syntax,
15198 'most' is upgraded to 'all'. However, in the divided syntax, some
15199 instructions take the affix as an infix, notably the s-variants of
15200 the arithmetic instructions. Of those instructions, all but six
15201 have the infix appear after the third character of the mnemonic.
15203 Accordingly, the algorithm for looking up primary opcodes given
15206 1. Look up the identifier in the opcode table.
15207 If we find a match, go to step U.
15209 2. Look up the last two characters of the identifier in the
15210 conditions table. If we find a match, look up the first N-2
15211 characters of the identifier in the opcode table. If we
15212 find a match, go to step CE.
15214 3. Look up the fourth and fifth characters of the identifier in
15215 the conditions table. If we find a match, extract those
15216 characters from the identifier, and look up the remaining
15217 characters in the opcode table. If we find a match, go
15222 U. Examine the tag field of the opcode structure, in case this is
15223 one of the six instructions with its conditional infix in an
15224 unusual place. If it is, the tag tells us where to find the
15225 infix; look it up in the conditions table and set inst.cond
15226 accordingly. Otherwise, this is an unconditional instruction.
15227 Again set inst.cond accordingly. Return the opcode structure.
15229 CE. Examine the tag field to make sure this is an instruction that
15230 should receive a conditional suffix. If it is not, fail.
15231 Otherwise, set inst.cond from the suffix we already looked up,
15232 and return the opcode structure.
15234 CM. Examine the tag field to make sure this is an instruction that
15235 should receive a conditional infix after the third character.
15236 If it is not, fail. Otherwise, undo the edits to the current
15237 line of input and proceed as for case CE. */
15239 static const struct asm_opcode
*
15240 opcode_lookup (char **str
)
15244 const struct asm_opcode
*opcode
;
15245 const struct asm_cond
*cond
;
15248 /* Scan up to the end of the mnemonic, which must end in white space,
15249 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15250 for (base
= end
= *str
; *end
!= '\0'; end
++)
15251 if (*end
== ' ' || *end
== '.')
15257 /* Handle a possible width suffix and/or Neon type suffix. */
15262 /* The .w and .n suffixes are only valid if the unified syntax is in
15264 if (unified_syntax
&& end
[1] == 'w')
15266 else if (unified_syntax
&& end
[1] == 'n')
15271 inst
.vectype
.elems
= 0;
15273 *str
= end
+ offset
;
15275 if (end
[offset
] == '.')
15277 /* See if we have a Neon type suffix (possible in either unified or
15278 non-unified ARM syntax mode). */
15279 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15282 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15288 /* Look for unaffixed or special-case affixed mnemonic. */
15289 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15294 if (opcode
->tag
< OT_odd_infix_0
)
15296 inst
.cond
= COND_ALWAYS
;
15300 if (warn_on_deprecated
&& unified_syntax
)
15301 as_warn (_("conditional infixes are deprecated in unified syntax"));
15302 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15303 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15306 inst
.cond
= cond
->value
;
15310 /* Cannot have a conditional suffix on a mnemonic of less than two
15312 if (end
- base
< 3)
15315 /* Look for suffixed mnemonic. */
15317 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15318 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15320 if (opcode
&& cond
)
15323 switch (opcode
->tag
)
15325 case OT_cinfix3_legacy
:
15326 /* Ignore conditional suffixes matched on infix only mnemonics. */
15330 case OT_cinfix3_deprecated
:
15331 case OT_odd_infix_unc
:
15332 if (!unified_syntax
)
15334 /* else fall through */
15338 case OT_csuf_or_in3
:
15339 inst
.cond
= cond
->value
;
15342 case OT_unconditional
:
15343 case OT_unconditionalF
:
15345 inst
.cond
= cond
->value
;
15348 /* Delayed diagnostic. */
15349 inst
.error
= BAD_COND
;
15350 inst
.cond
= COND_ALWAYS
;
15359 /* Cannot have a usual-position infix on a mnemonic of less than
15360 six characters (five would be a suffix). */
15361 if (end
- base
< 6)
15364 /* Look for infixed mnemonic in the usual position. */
15366 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15370 memcpy (save
, affix
, 2);
15371 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15372 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15374 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15375 memcpy (affix
, save
, 2);
15378 && (opcode
->tag
== OT_cinfix3
15379 || opcode
->tag
== OT_cinfix3_deprecated
15380 || opcode
->tag
== OT_csuf_or_in3
15381 || opcode
->tag
== OT_cinfix3_legacy
))
15384 if (warn_on_deprecated
&& unified_syntax
15385 && (opcode
->tag
== OT_cinfix3
15386 || opcode
->tag
== OT_cinfix3_deprecated
))
15387 as_warn (_("conditional infixes are deprecated in unified syntax"));
15389 inst
.cond
= cond
->value
;
15396 /* This function generates an initial IT instruction, leaving its block
15397 virtually open for the new instructions. Eventually,
15398 the mask will be updated by now_it_add_mask () each time
15399 a new instruction needs to be included in the IT block.
15400 Finally, the block is closed with close_automatic_it_block ().
15401 The block closure can be requested either from md_assemble (),
15402 a tencode (), or due to a label hook. */
15405 new_automatic_it_block (int cond
)
15407 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15408 now_it
.mask
= 0x18;
15410 now_it
.block_length
= 1;
15411 mapping_state (MAP_THUMB
);
15412 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15415 /* Close an automatic IT block.
15416 See comments in new_automatic_it_block (). */
15419 close_automatic_it_block (void)
15421 now_it
.mask
= 0x10;
15422 now_it
.block_length
= 0;
15425 /* Update the mask of the current automatically-generated IT
15426 instruction. See comments in new_automatic_it_block (). */
15429 now_it_add_mask (int cond
)
15431 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15432 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15433 | ((bitvalue) << (nbit)))
15434 const int resulting_bit
= (cond
& 1);
15436 now_it
.mask
&= 0xf;
15437 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15439 (5 - now_it
.block_length
));
15440 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15442 ((5 - now_it
.block_length
) - 1) );
15443 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15446 #undef SET_BIT_VALUE
15449 /* The IT blocks handling machinery is accessed through the these functions:
15450 it_fsm_pre_encode () from md_assemble ()
15451 set_it_insn_type () optional, from the tencode functions
15452 set_it_insn_type_last () ditto
15453 in_it_block () ditto
15454 it_fsm_post_encode () from md_assemble ()
15455 force_automatic_it_block_close () from label habdling functions
15458 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15459 initializing the IT insn type with a generic initial value depending
15460 on the inst.condition.
15461 2) During the tencode function, two things may happen:
15462 a) The tencode function overrides the IT insn type by
15463 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15464 b) The tencode function queries the IT block state by
15465 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15467 Both set_it_insn_type and in_it_block run the internal FSM state
15468 handling function (handle_it_state), because: a) setting the IT insn
15469 type may incur in an invalid state (exiting the function),
15470 and b) querying the state requires the FSM to be updated.
15471 Specifically we want to avoid creating an IT block for conditional
15472 branches, so it_fsm_pre_encode is actually a guess and we can't
15473 determine whether an IT block is required until the tencode () routine
15474 has decided what type of instruction this actually it.
15475 Because of this, if set_it_insn_type and in_it_block have to be used,
15476 set_it_insn_type has to be called first.
15478 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15479 determines the insn IT type depending on the inst.cond code.
15480 When a tencode () routine encodes an instruction that can be
15481 either outside an IT block, or, in the case of being inside, has to be
15482 the last one, set_it_insn_type_last () will determine the proper
15483 IT instruction type based on the inst.cond code. Otherwise,
15484 set_it_insn_type can be called for overriding that logic or
15485 for covering other cases.
15487 Calling handle_it_state () may not transition the IT block state to
15488 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15489 still queried. Instead, if the FSM determines that the state should
15490 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15491 after the tencode () function: that's what it_fsm_post_encode () does.
15493 Since in_it_block () calls the state handling function to get an
15494 updated state, an error may occur (due to invalid insns combination).
15495 In that case, inst.error is set.
15496 Therefore, inst.error has to be checked after the execution of
15497 the tencode () routine.
15499 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15500 any pending state change (if any) that didn't take place in
15501 handle_it_state () as explained above. */
15504 it_fsm_pre_encode (void)
15506 if (inst
.cond
!= COND_ALWAYS
)
15507 inst
.it_insn_type
= INSIDE_IT_INSN
;
15509 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15511 now_it
.state_handled
= 0;
15514 /* IT state FSM handling function. */
15517 handle_it_state (void)
15519 now_it
.state_handled
= 1;
15521 switch (now_it
.state
)
15523 case OUTSIDE_IT_BLOCK
:
15524 switch (inst
.it_insn_type
)
15526 case OUTSIDE_IT_INSN
:
15529 case INSIDE_IT_INSN
:
15530 case INSIDE_IT_LAST_INSN
:
15531 if (thumb_mode
== 0)
15534 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15535 as_tsktsk (_("Warning: conditional outside an IT block"\
15540 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15541 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15543 /* Automatically generate the IT instruction. */
15544 new_automatic_it_block (inst
.cond
);
15545 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15546 close_automatic_it_block ();
15550 inst
.error
= BAD_OUT_IT
;
15556 case IF_INSIDE_IT_LAST_INSN
:
15557 case NEUTRAL_IT_INSN
:
15561 now_it
.state
= MANUAL_IT_BLOCK
;
15562 now_it
.block_length
= 0;
15567 case AUTOMATIC_IT_BLOCK
:
15568 /* Three things may happen now:
15569 a) We should increment current it block size;
15570 b) We should close current it block (closing insn or 4 insns);
15571 c) We should close current it block and start a new one (due
15572 to incompatible conditions or
15573 4 insns-length block reached). */
15575 switch (inst
.it_insn_type
)
15577 case OUTSIDE_IT_INSN
:
15578 /* The closure of the block shall happen immediatelly,
15579 so any in_it_block () call reports the block as closed. */
15580 force_automatic_it_block_close ();
15583 case INSIDE_IT_INSN
:
15584 case INSIDE_IT_LAST_INSN
:
15585 case IF_INSIDE_IT_LAST_INSN
:
15586 now_it
.block_length
++;
15588 if (now_it
.block_length
> 4
15589 || !now_it_compatible (inst
.cond
))
15591 force_automatic_it_block_close ();
15592 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15593 new_automatic_it_block (inst
.cond
);
15597 now_it_add_mask (inst
.cond
);
15600 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15601 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15602 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15603 close_automatic_it_block ();
15606 case NEUTRAL_IT_INSN
:
15607 now_it
.block_length
++;
15609 if (now_it
.block_length
> 4)
15610 force_automatic_it_block_close ();
15612 now_it_add_mask (now_it
.cc
& 1);
15616 close_automatic_it_block ();
15617 now_it
.state
= MANUAL_IT_BLOCK
;
15622 case MANUAL_IT_BLOCK
:
15624 /* Check conditional suffixes. */
15625 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15628 now_it
.mask
&= 0x1f;
15629 is_last
= (now_it
.mask
== 0x10);
15631 switch (inst
.it_insn_type
)
15633 case OUTSIDE_IT_INSN
:
15634 inst
.error
= BAD_NOT_IT
;
15637 case INSIDE_IT_INSN
:
15638 if (cond
!= inst
.cond
)
15640 inst
.error
= BAD_IT_COND
;
15645 case INSIDE_IT_LAST_INSN
:
15646 case IF_INSIDE_IT_LAST_INSN
:
15647 if (cond
!= inst
.cond
)
15649 inst
.error
= BAD_IT_COND
;
15654 inst
.error
= BAD_BRANCH
;
15659 case NEUTRAL_IT_INSN
:
15660 /* The BKPT instruction is unconditional even in an IT block. */
15664 inst
.error
= BAD_IT_IT
;
15675 it_fsm_post_encode (void)
15679 if (!now_it
.state_handled
)
15680 handle_it_state ();
15682 is_last
= (now_it
.mask
== 0x10);
15685 now_it
.state
= OUTSIDE_IT_BLOCK
;
15691 force_automatic_it_block_close (void)
15693 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15695 close_automatic_it_block ();
15696 now_it
.state
= OUTSIDE_IT_BLOCK
;
15704 if (!now_it
.state_handled
)
15705 handle_it_state ();
15707 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15711 md_assemble (char *str
)
15714 const struct asm_opcode
* opcode
;
15716 /* Align the previous label if needed. */
15717 if (last_label_seen
!= NULL
)
15719 symbol_set_frag (last_label_seen
, frag_now
);
15720 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15721 S_SET_SEGMENT (last_label_seen
, now_seg
);
15724 memset (&inst
, '\0', sizeof (inst
));
15725 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15727 opcode
= opcode_lookup (&p
);
15730 /* It wasn't an instruction, but it might be a register alias of
15731 the form alias .req reg, or a Neon .dn/.qn directive. */
15732 if (! create_register_alias (str
, p
)
15733 && ! create_neon_reg_alias (str
, p
))
15734 as_bad (_("bad instruction `%s'"), str
);
15739 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15740 as_warn (_("s suffix on comparison instruction is deprecated"));
15742 /* The value which unconditional instructions should have in place of the
15743 condition field. */
15744 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15748 arm_feature_set variant
;
15750 variant
= cpu_variant
;
15751 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15752 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15753 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15754 /* Check that this instruction is supported for this CPU. */
15755 if (!opcode
->tvariant
15756 || (thumb_mode
== 1
15757 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15759 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
15762 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15763 && opcode
->tencode
!= do_t_branch
)
15765 as_bad (_("Thumb does not support conditional execution"));
15769 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15771 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15772 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15773 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15775 /* Two things are addressed here.
15776 1) Implicit require narrow instructions on Thumb-1.
15777 This avoids relaxation accidentally introducing Thumb-2
15779 2) Reject wide instructions in non Thumb-2 cores. */
15780 if (inst
.size_req
== 0)
15782 else if (inst
.size_req
== 4)
15784 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
15790 inst
.instruction
= opcode
->tvalue
;
15792 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
15794 /* Prepare the it_insn_type for those encodings that don't set
15796 it_fsm_pre_encode ();
15798 opcode
->tencode ();
15800 it_fsm_post_encode ();
15803 if (!(inst
.error
|| inst
.relax
))
15805 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15806 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15807 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15809 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15814 /* Something has gone badly wrong if we try to relax a fixed size
15816 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15818 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15819 *opcode
->tvariant
);
15820 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15821 set those bits when Thumb-2 32-bit instructions are seen. ie.
15822 anything other than bl/blx and v6-M instructions.
15823 This is overly pessimistic for relaxable instructions. */
15824 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15826 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15827 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15828 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15831 check_neon_suffixes
;
15835 mapping_state (MAP_THUMB
);
15838 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15842 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15843 is_bx
= (opcode
->aencode
== do_bx
);
15845 /* Check that this instruction is supported for this CPU. */
15846 if (!(is_bx
&& fix_v4bx
)
15847 && !(opcode
->avariant
&&
15848 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15850 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
15855 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15859 inst
.instruction
= opcode
->avalue
;
15860 if (opcode
->tag
== OT_unconditionalF
)
15861 inst
.instruction
|= 0xF << 28;
15863 inst
.instruction
|= inst
.cond
<< 28;
15864 inst
.size
= INSN_SIZE
;
15865 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
15867 it_fsm_pre_encode ();
15868 opcode
->aencode ();
15869 it_fsm_post_encode ();
15871 /* Arm mode bx is marked as both v4T and v5 because it's still required
15872 on a hypothetical non-thumb v5 core. */
15874 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15876 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15877 *opcode
->avariant
);
15879 check_neon_suffixes
;
15883 mapping_state (MAP_ARM
);
15888 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15896 check_it_blocks_finished (void)
15901 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15902 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15903 == MANUAL_IT_BLOCK
)
15905 as_warn (_("section '%s' finished with an open IT block."),
15909 if (now_it
.state
== MANUAL_IT_BLOCK
)
15910 as_warn (_("file finished with an open IT block."));
15914 /* Various frobbings of labels and their addresses. */
15917 arm_start_line_hook (void)
15919 last_label_seen
= NULL
;
15923 arm_frob_label (symbolS
* sym
)
15925 last_label_seen
= sym
;
15927 ARM_SET_THUMB (sym
, thumb_mode
);
15929 #if defined OBJ_COFF || defined OBJ_ELF
15930 ARM_SET_INTERWORK (sym
, support_interwork
);
15933 force_automatic_it_block_close ();
15935 /* Note - do not allow local symbols (.Lxxx) to be labelled
15936 as Thumb functions. This is because these labels, whilst
15937 they exist inside Thumb code, are not the entry points for
15938 possible ARM->Thumb calls. Also, these labels can be used
15939 as part of a computed goto or switch statement. eg gcc
15940 can generate code that looks like this:
15942 ldr r2, [pc, .Laaa]
15952 The first instruction loads the address of the jump table.
15953 The second instruction converts a table index into a byte offset.
15954 The third instruction gets the jump address out of the table.
15955 The fourth instruction performs the jump.
15957 If the address stored at .Laaa is that of a symbol which has the
15958 Thumb_Func bit set, then the linker will arrange for this address
15959 to have the bottom bit set, which in turn would mean that the
15960 address computation performed by the third instruction would end
15961 up with the bottom bit set. Since the ARM is capable of unaligned
15962 word loads, the instruction would then load the incorrect address
15963 out of the jump table, and chaos would ensue. */
15964 if (label_is_thumb_function_name
15965 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
15966 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
15968 /* When the address of a Thumb function is taken the bottom
15969 bit of that address should be set. This will allow
15970 interworking between Arm and Thumb functions to work
15973 THUMB_SET_FUNC (sym
, 1);
15975 label_is_thumb_function_name
= FALSE
;
15978 dwarf2_emit_label (sym
);
15982 arm_data_in_code (void)
15984 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
15986 *input_line_pointer
= '/';
15987 input_line_pointer
+= 5;
15988 *input_line_pointer
= 0;
15996 arm_canonicalize_symbol_name (char * name
)
16000 if (thumb_mode
&& (len
= strlen (name
)) > 5
16001 && streq (name
+ len
- 5, "/data"))
16002 *(name
+ len
- 5) = 0;
16007 /* Table of all register names defined by default. The user can
16008 define additional names with .req. Note that all register names
16009 should appear in both upper and lowercase variants. Some registers
16010 also have mixed-case names. */
16012 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16013 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16014 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16015 #define REGSET(p,t) \
16016 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16017 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16018 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16019 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16020 #define REGSETH(p,t) \
16021 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16022 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16023 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16024 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16025 #define REGSET2(p,t) \
16026 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16027 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16028 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16029 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16031 static const struct reg_entry reg_names
[] =
16033 /* ARM integer registers. */
16034 REGSET(r
, RN
), REGSET(R
, RN
),
16036 /* ATPCS synonyms. */
16037 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16038 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16039 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16041 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16042 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16043 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16045 /* Well-known aliases. */
16046 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16047 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16049 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16050 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16052 /* Coprocessor numbers. */
16053 REGSET(p
, CP
), REGSET(P
, CP
),
16055 /* Coprocessor register numbers. The "cr" variants are for backward
16057 REGSET(c
, CN
), REGSET(C
, CN
),
16058 REGSET(cr
, CN
), REGSET(CR
, CN
),
16060 /* FPA registers. */
16061 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16062 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16064 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16065 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16067 /* VFP SP registers. */
16068 REGSET(s
,VFS
), REGSET(S
,VFS
),
16069 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16071 /* VFP DP Registers. */
16072 REGSET(d
,VFD
), REGSET(D
,VFD
),
16073 /* Extra Neon DP registers. */
16074 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16076 /* Neon QP registers. */
16077 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16079 /* VFP control registers. */
16080 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16081 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16082 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16083 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16084 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16085 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16087 /* Maverick DSP coprocessor registers. */
16088 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16089 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16091 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16092 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16093 REGDEF(dspsc
,0,DSPSC
),
16095 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16096 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16097 REGDEF(DSPSC
,0,DSPSC
),
16099 /* iWMMXt data registers - p0, c0-15. */
16100 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16102 /* iWMMXt control registers - p1, c0-3. */
16103 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16104 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16105 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16106 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16108 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16109 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16110 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16111 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16112 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16114 /* XScale accumulator registers. */
16115 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16121 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16122 within psr_required_here. */
16123 static const struct asm_psr psrs
[] =
16125 /* Backward compatibility notation. Note that "all" is no longer
16126 truly all possible PSR bits. */
16127 {"all", PSR_c
| PSR_f
},
16131 /* Individual flags. */
16136 /* Combinations of flags. */
16137 {"fs", PSR_f
| PSR_s
},
16138 {"fx", PSR_f
| PSR_x
},
16139 {"fc", PSR_f
| PSR_c
},
16140 {"sf", PSR_s
| PSR_f
},
16141 {"sx", PSR_s
| PSR_x
},
16142 {"sc", PSR_s
| PSR_c
},
16143 {"xf", PSR_x
| PSR_f
},
16144 {"xs", PSR_x
| PSR_s
},
16145 {"xc", PSR_x
| PSR_c
},
16146 {"cf", PSR_c
| PSR_f
},
16147 {"cs", PSR_c
| PSR_s
},
16148 {"cx", PSR_c
| PSR_x
},
16149 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16150 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16151 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16152 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16153 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16154 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16155 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16156 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16157 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16158 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16159 {"scf", PSR_s
| PSR_c
| PSR_f
},
16160 {"scx", PSR_s
| PSR_c
| PSR_x
},
16161 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16162 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16163 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16164 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16165 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16166 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16167 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16168 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16169 {"csf", PSR_c
| PSR_s
| PSR_f
},
16170 {"csx", PSR_c
| PSR_s
| PSR_x
},
16171 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16172 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16173 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16174 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16175 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16176 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16177 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16178 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16179 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16180 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16181 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16182 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16183 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16184 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16185 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16186 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16187 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16188 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16189 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16190 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16191 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16192 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16193 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16194 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16195 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16196 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16199 /* Table of V7M psr names. */
16200 static const struct asm_psr v7m_psrs
[] =
16202 {"apsr", 0 }, {"APSR", 0 },
16203 {"iapsr", 1 }, {"IAPSR", 1 },
16204 {"eapsr", 2 }, {"EAPSR", 2 },
16205 {"psr", 3 }, {"PSR", 3 },
16206 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16207 {"ipsr", 5 }, {"IPSR", 5 },
16208 {"epsr", 6 }, {"EPSR", 6 },
16209 {"iepsr", 7 }, {"IEPSR", 7 },
16210 {"msp", 8 }, {"MSP", 8 },
16211 {"psp", 9 }, {"PSP", 9 },
16212 {"primask", 16}, {"PRIMASK", 16},
16213 {"basepri", 17}, {"BASEPRI", 17},
16214 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16215 {"faultmask", 19}, {"FAULTMASK", 19},
16216 {"control", 20}, {"CONTROL", 20}
16219 /* Table of all shift-in-operand names. */
16220 static const struct asm_shift_name shift_names
[] =
16222 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16223 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16224 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16225 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16226 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16227 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16230 /* Table of all explicit relocation names. */
16232 static struct reloc_entry reloc_names
[] =
16234 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16235 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16236 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16237 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16238 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16239 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16240 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16241 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16242 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16243 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16244 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16245 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
}
16249 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16250 static const struct asm_cond conds
[] =
16254 {"cs", 0x2}, {"hs", 0x2},
16255 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16269 static struct asm_barrier_opt barrier_opt_names
[] =
16277 /* Table of ARM-format instructions. */
16279 /* Macros for gluing together operand strings. N.B. In all cases
16280 other than OPS0, the trailing OP_stop comes from default
16281 zero-initialization of the unspecified elements of the array. */
16282 #define OPS0() { OP_stop, }
16283 #define OPS1(a) { OP_##a, }
16284 #define OPS2(a,b) { OP_##a,OP_##b, }
16285 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16286 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16287 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16288 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16290 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16291 This is useful when mixing operands for ARM and THUMB, i.e. using the
16292 MIX_ARM_THUMB_OPERANDS macro.
16293 In order to use these macros, prefix the number of operands with _
16295 #define OPS_1(a) { a, }
16296 #define OPS_2(a,b) { a,b, }
16297 #define OPS_3(a,b,c) { a,b,c, }
16298 #define OPS_4(a,b,c,d) { a,b,c,d, }
16299 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16300 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16302 /* These macros abstract out the exact format of the mnemonic table and
16303 save some repeated characters. */
16305 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16306 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16307 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16308 THUMB_VARIANT, do_##ae, do_##te }
16310 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16311 a T_MNEM_xyz enumerator. */
16312 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16313 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16314 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16315 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16317 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16318 infix after the third character. */
16319 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16320 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16321 THUMB_VARIANT, do_##ae, do_##te }
16322 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16323 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16324 THUMB_VARIANT, do_##ae, do_##te }
16325 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16326 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16327 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16328 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16329 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16330 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16331 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16332 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16334 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16335 appear in the condition table. */
16336 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16337 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16338 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16340 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16341 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16342 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16343 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16344 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16345 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16346 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16347 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16348 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16349 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16350 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16351 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16352 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16353 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16354 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16355 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16356 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16357 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16358 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16359 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16361 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16362 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16363 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16364 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16366 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16367 field is still 0xE. Many of the Thumb variants can be executed
16368 conditionally, so this is checked separately. */
16369 #define TUE(mnem, op, top, nops, ops, ae, te) \
16370 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16371 THUMB_VARIANT, do_##ae, do_##te }
16373 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16374 condition code field. */
16375 #define TUF(mnem, op, top, nops, ops, ae, te) \
16376 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16377 THUMB_VARIANT, do_##ae, do_##te }
16379 /* ARM-only variants of all the above. */
16380 #define CE(mnem, op, nops, ops, ae) \
16381 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16383 #define C3(mnem, op, nops, ops, ae) \
16384 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16386 /* Legacy mnemonics that always have conditional infix after the third
16388 #define CL(mnem, op, nops, ops, ae) \
16389 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16390 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16392 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16393 #define cCE(mnem, op, nops, ops, ae) \
16394 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16396 /* Legacy coprocessor instructions where conditional infix and conditional
16397 suffix are ambiguous. For consistency this includes all FPA instructions,
16398 not just the potentially ambiguous ones. */
16399 #define cCL(mnem, op, nops, ops, ae) \
16400 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16401 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16403 /* Coprocessor, takes either a suffix or a position-3 infix
16404 (for an FPA corner case). */
16405 #define C3E(mnem, op, nops, ops, ae) \
16406 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16407 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16409 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16410 { m1 #m2 m3, OPS##nops ops, \
16411 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16412 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16414 #define CM(m1, m2, op, nops, ops, ae) \
16415 xCM_ (m1, , m2, op, nops, ops, ae), \
16416 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16417 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16418 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16419 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16420 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16421 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16422 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16423 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16424 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16425 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16426 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16427 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16428 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16429 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16430 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16431 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16432 xCM_ (m1, le, m2, op, nops, ops, ae), \
16433 xCM_ (m1, al, m2, op, nops, ops, ae)
16435 #define UE(mnem, op, nops, ops, ae) \
16436 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16438 #define UF(mnem, op, nops, ops, ae) \
16439 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16441 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16442 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16443 use the same encoding function for each. */
16444 #define NUF(mnem, op, nops, ops, enc) \
16445 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16446 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16448 /* Neon data processing, version which indirects through neon_enc_tab for
16449 the various overloaded versions of opcodes. */
16450 #define nUF(mnem, op, nops, ops, enc) \
16451 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16452 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16454 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16456 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16457 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16458 THUMB_VARIANT, do_##enc, do_##enc }
16460 #define NCE(mnem, op, nops, ops, enc) \
16461 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16463 #define NCEF(mnem, op, nops, ops, enc) \
16464 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16466 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16467 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16468 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16469 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16471 #define nCE(mnem, op, nops, ops, enc) \
16472 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16474 #define nCEF(mnem, op, nops, ops, enc) \
16475 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16479 static const struct asm_opcode insns
[] =
16481 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16482 #define THUMB_VARIANT &arm_ext_v4t
16483 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16484 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16485 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16486 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16487 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16488 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16489 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16490 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16491 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16492 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16493 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16494 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16495 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16496 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16497 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16498 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16500 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16501 for setting PSR flag bits. They are obsolete in V6 and do not
16502 have Thumb equivalents. */
16503 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16504 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16505 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16506 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16507 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16508 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16509 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16510 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16511 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16513 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16514 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16515 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16516 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16518 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16519 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16520 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16522 OP_ADDRGLDR
),ldst
, t_ldst
),
16523 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16525 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16526 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16527 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16528 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16529 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16530 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16532 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16533 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16534 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16535 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16538 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16539 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16540 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16542 /* Thumb-compatibility pseudo ops. */
16543 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16544 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16545 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16546 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16547 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16548 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16549 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16550 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16551 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16552 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16553 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16554 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16556 /* These may simplify to neg. */
16557 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16558 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16560 #undef THUMB_VARIANT
16561 #define THUMB_VARIANT & arm_ext_v6
16563 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16565 /* V1 instructions with no Thumb analogue prior to V6T2. */
16566 #undef THUMB_VARIANT
16567 #define THUMB_VARIANT & arm_ext_v6t2
16569 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16570 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16571 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16573 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16574 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16575 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
16576 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16578 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16579 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16581 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16582 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16584 /* V1 instructions with no Thumb analogue at all. */
16585 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16586 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16588 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16589 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16590 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16591 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16592 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16593 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16594 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16595 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16598 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16599 #undef THUMB_VARIANT
16600 #define THUMB_VARIANT & arm_ext_v4t
16602 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16603 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16605 #undef THUMB_VARIANT
16606 #define THUMB_VARIANT & arm_ext_v6t2
16608 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16609 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16611 /* Generic coprocessor instructions. */
16612 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16613 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16614 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16615 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16616 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16617 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16618 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16621 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16623 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16624 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16627 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16628 #undef THUMB_VARIANT
16629 #define THUMB_VARIANT & arm_ext_msr
16631 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16632 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16635 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16636 #undef THUMB_VARIANT
16637 #define THUMB_VARIANT & arm_ext_v6t2
16639 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16640 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16641 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16642 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16643 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16644 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16645 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16646 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16649 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16650 #undef THUMB_VARIANT
16651 #define THUMB_VARIANT & arm_ext_v4t
16653 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16654 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16655 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16656 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16657 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16658 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16661 #define ARM_VARIANT & arm_ext_v4t_5
16663 /* ARM Architecture 4T. */
16664 /* Note: bx (and blx) are required on V5, even if the processor does
16665 not support Thumb. */
16666 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16669 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16670 #undef THUMB_VARIANT
16671 #define THUMB_VARIANT & arm_ext_v5t
16673 /* Note: blx has 2 variants; the .value coded here is for
16674 BLX(2). Only this variant has conditional execution. */
16675 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16676 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16678 #undef THUMB_VARIANT
16679 #define THUMB_VARIANT & arm_ext_v6t2
16681 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16682 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16683 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16684 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16685 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16686 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16687 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16688 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16691 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16692 #undef THUMB_VARIANT
16693 #define THUMB_VARIANT &arm_ext_v5exp
16695 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16696 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16697 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16698 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16700 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16701 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16703 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16704 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16705 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16706 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16708 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16709 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16710 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16711 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16713 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16714 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16716 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16717 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16718 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16719 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16722 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16723 #undef THUMB_VARIANT
16724 #define THUMB_VARIANT &arm_ext_v6t2
16726 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16727 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
16729 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
16730 ADDRGLDRS
), ldrd
, t_ldstd
),
16732 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16733 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16736 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16738 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16741 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16742 #undef THUMB_VARIANT
16743 #define THUMB_VARIANT & arm_ext_v6
16745 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16746 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16747 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16748 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16749 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16750 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16751 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16752 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16753 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16754 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16756 #undef THUMB_VARIANT
16757 #define THUMB_VARIANT & arm_ext_v6t2
16759 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
16760 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16762 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16763 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16765 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16766 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16768 /* ARM V6 not included in V7M. */
16769 #undef THUMB_VARIANT
16770 #define THUMB_VARIANT & arm_ext_v6_notm
16771 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16772 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16773 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16774 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16775 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16776 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16777 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16778 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16779 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16780 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16781 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16782 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16784 /* ARM V6 not included in V7M (eg. integer SIMD). */
16785 #undef THUMB_VARIANT
16786 #define THUMB_VARIANT & arm_ext_v6_dsp
16787 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16788 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16789 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16790 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16791 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16792 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16793 /* Old name for QASX. */
16794 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16795 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16796 /* Old name for QSAX. */
16797 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16798 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16799 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16800 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16801 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16802 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16803 /* Old name for SASX. */
16804 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16805 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16806 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16807 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16808 /* Old name for SHASX. */
16809 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16810 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16811 /* Old name for SHSAX. */
16812 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16813 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16814 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16815 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16816 /* Old name for SSAX. */
16817 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16818 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16819 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16820 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16821 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16822 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16823 /* Old name for UASX. */
16824 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16825 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16826 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16827 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16828 /* Old name for UHASX. */
16829 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16830 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16831 /* Old name for UHSAX. */
16832 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16833 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16834 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16835 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16836 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16837 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16838 /* Old name for UQASX. */
16839 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16840 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16841 /* Old name for UQSAX. */
16842 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16843 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16844 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16845 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16846 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16847 /* Old name for USAX. */
16848 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16849 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16850 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16851 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16852 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16853 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16854 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16855 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16856 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16857 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16858 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16859 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16860 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16861 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16862 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16863 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16864 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16865 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16866 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16867 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16868 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16869 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16870 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16871 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16872 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16873 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16874 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16875 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16876 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16877 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16878 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16879 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16880 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16881 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16884 #define ARM_VARIANT & arm_ext_v6k
16885 #undef THUMB_VARIANT
16886 #define THUMB_VARIANT & arm_ext_v6k
16888 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
16889 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
16890 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
16891 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
16893 #undef THUMB_VARIANT
16894 #define THUMB_VARIANT & arm_ext_v6_notm
16895 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
16897 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
16898 RRnpcb
), strexd
, t_strexd
),
16900 #undef THUMB_VARIANT
16901 #define THUMB_VARIANT & arm_ext_v6t2
16902 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
16904 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
16906 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16908 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16910 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16913 #define ARM_VARIANT & arm_ext_v6z
16915 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16918 #define ARM_VARIANT & arm_ext_v6t2
16920 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16921 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16922 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16923 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16925 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16926 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16927 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16928 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
16930 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16931 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16932 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16933 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16935 /* Thumb-only instructions. */
16937 #define ARM_VARIANT NULL
16938 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
16939 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
16941 /* ARM does not really have an IT instruction, so always allow it.
16942 The opcode is copied from Thumb in order to allow warnings in
16943 -mimplicit-it=[never | arm] modes. */
16945 #define ARM_VARIANT & arm_ext_v1
16947 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
16948 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
16949 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
16950 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
16951 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
16952 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
16953 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
16954 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
16955 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
16956 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
16957 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
16958 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
16959 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
16960 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
16961 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
16962 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
16963 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16964 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16966 /* Thumb2 only instructions. */
16968 #define ARM_VARIANT NULL
16970 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16971 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16972 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16973 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16974 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
16975 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
16977 /* Thumb-2 hardware division instructions (R and M profiles only). */
16978 #undef THUMB_VARIANT
16979 #define THUMB_VARIANT & arm_ext_div
16981 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16982 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16984 /* ARM V6M/V7 instructions. */
16986 #define ARM_VARIANT & arm_ext_barrier
16987 #undef THUMB_VARIANT
16988 #define THUMB_VARIANT & arm_ext_barrier
16990 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
16991 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
16992 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
16994 /* ARM V7 instructions. */
16996 #define ARM_VARIANT & arm_ext_v7
16997 #undef THUMB_VARIANT
16998 #define THUMB_VARIANT & arm_ext_v7
17000 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17001 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17004 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17006 cCE("wfs", e200110
, 1, (RR
), rd
),
17007 cCE("rfs", e300110
, 1, (RR
), rd
),
17008 cCE("wfc", e400110
, 1, (RR
), rd
),
17009 cCE("rfc", e500110
, 1, (RR
), rd
),
17011 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17012 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17013 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17014 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17016 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17017 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17018 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17019 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17021 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17022 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17023 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17024 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17025 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17026 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17027 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17028 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17029 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17030 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17031 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17032 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17034 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17035 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17036 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17037 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17038 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17039 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17040 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17041 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17042 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17043 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17044 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17045 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17047 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17048 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17049 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17050 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17051 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17052 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17053 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17054 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17055 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17056 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17057 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17058 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17060 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17061 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17062 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17063 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17064 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17065 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17066 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17067 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17068 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17069 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17070 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17071 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17073 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17074 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17075 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17076 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17077 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17078 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17079 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17080 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17081 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17082 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17083 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17084 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17086 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17087 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17088 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17089 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17090 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17091 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17092 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17093 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17094 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17095 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17096 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17097 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17099 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17100 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17101 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17102 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17103 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17104 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17105 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17106 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17107 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17108 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17109 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17110 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17112 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17113 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17114 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17115 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17116 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17117 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17118 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17119 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17120 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17121 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17122 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17123 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17125 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17126 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17127 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17128 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17129 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17130 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17131 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17132 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17133 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17134 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17135 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17136 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17138 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17139 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17140 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17141 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17142 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17143 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17144 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17145 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17146 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17147 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17148 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17149 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17151 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17152 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17153 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17154 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17155 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17156 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17157 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17158 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17159 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17160 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17161 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17162 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17164 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17165 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17166 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17167 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17168 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17169 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17170 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17171 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17172 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17173 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17174 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17175 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17177 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17178 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17179 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17180 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17181 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17182 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17183 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17184 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17185 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17186 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17187 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17188 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17190 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17191 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17192 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17193 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17194 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17195 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17196 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17197 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17198 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17199 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17200 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17201 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17203 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17204 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17205 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17206 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17207 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17208 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17209 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17210 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17211 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17212 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17213 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17214 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17216 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17217 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17218 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17219 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17220 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17221 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17222 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17223 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17224 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17225 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17226 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17227 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17229 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17230 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17231 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17232 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17233 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17234 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17235 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17236 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17237 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17238 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17239 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17240 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17242 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17243 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17244 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17245 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17246 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17247 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17248 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17249 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17250 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17251 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17252 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17253 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17255 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17256 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17257 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17258 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17259 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17260 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17261 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17262 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17263 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17264 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17265 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17266 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17268 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17269 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17270 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17271 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17272 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17273 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17274 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17275 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17276 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17277 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17278 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17279 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17281 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17282 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17283 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17284 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17285 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17286 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17287 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17288 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17289 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17290 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17291 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17292 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17294 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17295 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17296 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17297 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17298 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17299 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17300 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17301 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17302 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17303 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17304 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17305 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17307 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17308 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17309 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17310 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17311 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17312 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17313 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17314 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17315 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17316 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17317 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17318 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17320 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17321 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17322 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17323 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17324 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17325 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17326 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17327 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17328 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17329 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17330 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17331 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17333 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17334 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17335 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17336 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17337 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17338 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17339 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17340 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17341 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17342 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17343 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17344 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17346 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17347 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17348 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17349 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17350 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17351 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17352 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17353 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17354 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17355 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17356 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17357 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17359 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17360 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17361 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17362 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17363 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17364 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17365 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17366 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17367 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17368 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17369 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17370 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17372 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17373 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17374 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17375 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17376 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17377 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17378 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17379 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17380 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17381 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17382 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17383 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17385 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17386 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17387 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17388 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17389 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17390 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17391 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17392 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17393 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17394 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17395 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17396 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17398 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17399 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17400 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17401 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17403 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17404 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17405 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17406 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17407 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17408 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17409 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17410 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17411 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17412 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17413 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17414 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17416 /* The implementation of the FIX instruction is broken on some
17417 assemblers, in that it accepts a precision specifier as well as a
17418 rounding specifier, despite the fact that this is meaningless.
17419 To be more compatible, we accept it as well, though of course it
17420 does not set any bits. */
17421 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17422 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17423 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17424 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17425 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17426 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17427 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17428 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17429 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17430 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17431 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17432 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17433 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17435 /* Instructions that were new with the real FPA, call them V2. */
17437 #define ARM_VARIANT & fpu_fpa_ext_v2
17439 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17440 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17441 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17442 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17443 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17444 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17447 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17449 /* Moves and type conversions. */
17450 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17451 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17452 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17453 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17454 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17455 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17456 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17457 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17458 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17459 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17460 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17461 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17462 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17463 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17465 /* Memory operations. */
17466 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17467 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17468 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17469 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17470 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17471 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17472 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17473 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17474 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17475 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17476 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17477 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17478 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17479 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17480 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17481 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17482 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17483 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17485 /* Monadic operations. */
17486 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17487 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17488 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17490 /* Dyadic operations. */
17491 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17492 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17493 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17494 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17495 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17496 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17497 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17498 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17499 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17502 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17503 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17504 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17505 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17507 /* Double precision load/store are still present on single precision
17508 implementations. */
17509 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17510 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17511 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17512 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17513 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17514 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17515 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17516 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17517 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17518 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17521 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17523 /* Moves and type conversions. */
17524 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17525 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17526 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17527 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17528 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17529 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17530 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17531 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17532 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17533 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17534 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17535 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17536 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17538 /* Monadic operations. */
17539 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17540 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17541 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17543 /* Dyadic operations. */
17544 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17545 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17546 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17547 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17548 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17549 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17550 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17551 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17552 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17555 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17556 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17557 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17558 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17561 #define ARM_VARIANT & fpu_vfp_ext_v2
17563 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17564 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17565 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17566 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17568 /* Instructions which may belong to either the Neon or VFP instruction sets.
17569 Individual encoder functions perform additional architecture checks. */
17571 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17572 #undef THUMB_VARIANT
17573 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17575 /* These mnemonics are unique to VFP. */
17576 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17577 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17578 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17579 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17580 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17581 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17582 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17583 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17584 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17585 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17587 /* Mnemonics shared by Neon and VFP. */
17588 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17589 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17590 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17592 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17593 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17595 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17596 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17598 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17599 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17600 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17601 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17602 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17603 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17604 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17605 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17607 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17608 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17609 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17610 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17613 /* NOTE: All VMOV encoding is special-cased! */
17614 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17615 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17617 #undef THUMB_VARIANT
17618 #define THUMB_VARIANT & fpu_neon_ext_v1
17620 #define ARM_VARIANT & fpu_neon_ext_v1
17622 /* Data processing with three registers of the same length. */
17623 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17624 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17625 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17626 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17627 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17628 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17629 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17630 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17631 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17632 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17633 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17634 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17635 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17636 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17637 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17638 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17639 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17640 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17641 /* If not immediate, fall back to neon_dyadic_i64_su.
17642 shl_imm should accept I8 I16 I32 I64,
17643 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17644 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17645 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17646 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17647 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17648 /* Logic ops, types optional & ignored. */
17649 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17650 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17651 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17652 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17653 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17654 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17655 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17656 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17657 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17658 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17659 /* Bitfield ops, untyped. */
17660 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17661 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17662 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17663 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17664 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17665 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17666 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17667 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17668 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17669 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17670 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17671 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17672 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17673 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17674 back to neon_dyadic_if_su. */
17675 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17676 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17677 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17678 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17679 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17680 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17681 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17682 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17683 /* Comparison. Type I8 I16 I32 F32. */
17684 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17685 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17686 /* As above, D registers only. */
17687 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17688 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17689 /* Int and float variants, signedness unimportant. */
17690 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17691 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17692 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17693 /* Add/sub take types I8 I16 I32 I64 F32. */
17694 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17695 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17696 /* vtst takes sizes 8, 16, 32. */
17697 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17698 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17699 /* VMUL takes I8 I16 I32 F32 P8. */
17700 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17701 /* VQD{R}MULH takes S16 S32. */
17702 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17703 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17704 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17705 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17706 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17707 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17708 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17709 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17710 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17711 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17712 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17713 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17714 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17715 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17716 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17717 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17719 /* Two address, int/float. Types S8 S16 S32 F32. */
17720 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17721 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17723 /* Data processing with two registers and a shift amount. */
17724 /* Right shifts, and variants with rounding.
17725 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17726 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17727 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17728 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17729 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17730 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17731 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17732 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17733 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17734 /* Shift and insert. Sizes accepted 8 16 32 64. */
17735 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17736 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17737 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17738 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17739 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17740 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17741 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17742 /* Right shift immediate, saturating & narrowing, with rounding variants.
17743 Types accepted S16 S32 S64 U16 U32 U64. */
17744 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17745 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17746 /* As above, unsigned. Types accepted S16 S32 S64. */
17747 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17748 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17749 /* Right shift narrowing. Types accepted I16 I32 I64. */
17750 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17751 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17752 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17753 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17754 /* CVT with optional immediate for fixed-point variant. */
17755 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17757 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
17758 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
17760 /* Data processing, three registers of different lengths. */
17761 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17762 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17763 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17764 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17765 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17766 /* If not scalar, fall back to neon_dyadic_long.
17767 Vector types as above, scalar types S16 S32 U16 U32. */
17768 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17769 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17770 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17771 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17772 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17773 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17774 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17775 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17776 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17777 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17778 /* Saturating doubling multiplies. Types S16 S32. */
17779 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17780 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17781 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17782 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17783 S16 S32 U16 U32. */
17784 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17786 /* Extract. Size 8. */
17787 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17788 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17790 /* Two registers, miscellaneous. */
17791 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17792 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17793 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17794 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17795 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17796 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17797 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17798 /* Vector replicate. Sizes 8 16 32. */
17799 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17800 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17801 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17802 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17803 /* VMOVN. Types I16 I32 I64. */
17804 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17805 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17806 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17807 /* VQMOVUN. Types S16 S32 S64. */
17808 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17809 /* VZIP / VUZP. Sizes 8 16 32. */
17810 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17811 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17812 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17813 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17814 /* VQABS / VQNEG. Types S8 S16 S32. */
17815 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17816 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17817 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17818 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17819 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17820 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17821 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17822 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17823 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17824 /* Reciprocal estimates. Types U32 F32. */
17825 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17826 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17827 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17828 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17829 /* VCLS. Types S8 S16 S32. */
17830 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17831 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17832 /* VCLZ. Types I8 I16 I32. */
17833 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17834 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17835 /* VCNT. Size 8. */
17836 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17837 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17838 /* Two address, untyped. */
17839 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17840 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17841 /* VTRN. Sizes 8 16 32. */
17842 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17843 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17845 /* Table lookup. Size 8. */
17846 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17847 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17849 #undef THUMB_VARIANT
17850 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17852 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17854 /* Neon element/structure load/store. */
17855 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17856 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17857 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17858 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17859 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17860 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17861 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17862 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17864 #undef THUMB_VARIANT
17865 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
17867 #define ARM_VARIANT &fpu_vfp_ext_v3xd
17868 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17869 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17870 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17871 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17872 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17873 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17874 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17875 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17876 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17878 #undef THUMB_VARIANT
17879 #define THUMB_VARIANT & fpu_vfp_ext_v3
17881 #define ARM_VARIANT & fpu_vfp_ext_v3
17883 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17884 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17885 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17886 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17887 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17888 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17889 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17890 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17891 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17894 #define ARM_VARIANT &fpu_vfp_ext_fma
17895 #undef THUMB_VARIANT
17896 #define THUMB_VARIANT &fpu_vfp_ext_fma
17897 /* Mnemonics shared by Neon and VFP. These are included in the
17898 VFP FMA variant; NEON and VFP FMA always includes the NEON
17899 FMA instructions. */
17900 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17901 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17902 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
17903 the v form should always be used. */
17904 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17905 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17906 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17907 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17908 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17909 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17911 #undef THUMB_VARIANT
17913 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17915 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17916 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17917 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17918 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17919 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17920 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17921 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17922 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17925 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17927 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
17928 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
17929 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
17930 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
17931 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
17932 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
17933 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
17934 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
17935 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
17936 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17937 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17938 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17939 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17940 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17941 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17942 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17943 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17944 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17945 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
17946 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
17947 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17948 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17949 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17950 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17951 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17952 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17953 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
17954 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
17955 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
17956 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
17957 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
17958 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
17959 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
17960 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
17961 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17962 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17963 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17964 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17965 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17966 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17967 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17968 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17969 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17970 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17971 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17972 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17973 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
17974 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17975 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17976 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17977 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17978 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17979 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17980 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17981 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17982 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17983 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17984 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17985 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17986 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17987 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17988 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17989 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17990 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17991 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17992 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17993 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17994 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17995 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17996 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17997 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17998 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17999 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18000 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18001 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18002 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18003 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18004 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18005 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18006 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18007 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18008 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18009 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18010 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18011 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18012 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18013 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18014 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18015 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18016 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18017 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18018 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18019 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18020 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18021 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18022 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18023 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18024 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18025 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18026 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18027 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18028 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18029 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18030 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18031 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18032 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18033 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18034 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18035 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18036 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18037 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18038 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18039 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18040 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18041 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18042 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18043 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18044 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18045 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18046 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18047 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18048 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18049 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18050 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18051 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18052 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18053 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18054 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18055 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18056 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18057 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18058 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18059 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18060 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18061 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18062 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18063 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18064 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18065 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18066 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18067 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18068 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18069 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18070 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18071 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18072 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18073 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18074 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18075 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18076 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18077 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18078 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18079 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18080 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18081 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18082 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18083 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18084 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18085 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18086 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18087 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18088 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18091 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18093 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18094 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18095 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18096 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18097 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18098 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18099 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18100 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18101 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18102 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18103 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18104 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18105 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18106 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18107 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18108 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18109 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18110 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18111 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18112 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18113 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18114 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18115 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18116 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18117 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18118 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18119 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18120 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18121 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18122 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18123 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18124 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18125 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18126 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18127 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18128 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18129 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18130 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18131 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18132 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18133 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18134 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18135 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18136 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18137 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18138 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18139 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18140 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18141 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18142 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18143 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18144 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18145 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18146 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18147 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18148 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18149 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18152 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18154 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18155 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18156 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18157 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18158 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18159 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18160 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18161 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18162 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18163 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18164 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18165 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18166 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18167 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18168 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18169 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18170 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18171 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18172 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18173 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18174 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18175 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18176 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18177 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18178 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18179 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18180 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18181 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18182 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18183 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18184 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18185 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18186 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18187 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18188 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18189 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18190 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18191 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18192 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18193 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18194 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18195 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18196 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18197 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18198 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18199 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18200 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18201 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18202 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18203 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18204 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18205 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18206 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18207 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18208 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18209 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18210 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18211 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18212 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18213 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18214 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18215 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18216 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18217 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18218 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18219 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18220 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18221 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18222 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18223 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18224 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18225 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18226 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18227 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18228 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18229 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18232 #undef THUMB_VARIANT
18259 /* MD interface: bits in the object file. */
18261 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18262 for use in the a.out file, and stores them in the array pointed to by buf.
18263 This knows about the endian-ness of the target machine and does
18264 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18265 2 (short) and 4 (long) Floating numbers are put out as a series of
18266 LITTLENUMS (shorts, here at least). */
18269 md_number_to_chars (char * buf
, valueT val
, int n
)
18271 if (target_big_endian
)
18272 number_to_chars_bigendian (buf
, val
, n
);
18274 number_to_chars_littleendian (buf
, val
, n
);
18278 md_chars_to_number (char * buf
, int n
)
18281 unsigned char * where
= (unsigned char *) buf
;
18283 if (target_big_endian
)
18288 result
|= (*where
++ & 255);
18296 result
|= (where
[n
] & 255);
18303 /* MD interface: Sections. */
18305 /* Estimate the size of a frag before relaxing. Assume everything fits in
18309 md_estimate_size_before_relax (fragS
* fragp
,
18310 segT segtype ATTRIBUTE_UNUSED
)
18316 /* Convert a machine dependent frag. */
18319 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18321 unsigned long insn
;
18322 unsigned long old_op
;
18330 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18332 old_op
= bfd_get_16(abfd
, buf
);
18333 if (fragp
->fr_symbol
)
18335 exp
.X_op
= O_symbol
;
18336 exp
.X_add_symbol
= fragp
->fr_symbol
;
18340 exp
.X_op
= O_constant
;
18342 exp
.X_add_number
= fragp
->fr_offset
;
18343 opcode
= fragp
->fr_subtype
;
18346 case T_MNEM_ldr_pc
:
18347 case T_MNEM_ldr_pc2
:
18348 case T_MNEM_ldr_sp
:
18349 case T_MNEM_str_sp
:
18356 if (fragp
->fr_var
== 4)
18358 insn
= THUMB_OP32 (opcode
);
18359 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18361 insn
|= (old_op
& 0x700) << 4;
18365 insn
|= (old_op
& 7) << 12;
18366 insn
|= (old_op
& 0x38) << 13;
18368 insn
|= 0x00000c00;
18369 put_thumb32_insn (buf
, insn
);
18370 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18374 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18376 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18379 if (fragp
->fr_var
== 4)
18381 insn
= THUMB_OP32 (opcode
);
18382 insn
|= (old_op
& 0xf0) << 4;
18383 put_thumb32_insn (buf
, insn
);
18384 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18388 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18389 exp
.X_add_number
-= 4;
18397 if (fragp
->fr_var
== 4)
18399 int r0off
= (opcode
== T_MNEM_mov
18400 || opcode
== T_MNEM_movs
) ? 0 : 8;
18401 insn
= THUMB_OP32 (opcode
);
18402 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18403 insn
|= (old_op
& 0x700) << r0off
;
18404 put_thumb32_insn (buf
, insn
);
18405 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18409 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18414 if (fragp
->fr_var
== 4)
18416 insn
= THUMB_OP32(opcode
);
18417 put_thumb32_insn (buf
, insn
);
18418 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18421 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18425 if (fragp
->fr_var
== 4)
18427 insn
= THUMB_OP32(opcode
);
18428 insn
|= (old_op
& 0xf00) << 14;
18429 put_thumb32_insn (buf
, insn
);
18430 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18433 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18436 case T_MNEM_add_sp
:
18437 case T_MNEM_add_pc
:
18438 case T_MNEM_inc_sp
:
18439 case T_MNEM_dec_sp
:
18440 if (fragp
->fr_var
== 4)
18442 /* ??? Choose between add and addw. */
18443 insn
= THUMB_OP32 (opcode
);
18444 insn
|= (old_op
& 0xf0) << 4;
18445 put_thumb32_insn (buf
, insn
);
18446 if (opcode
== T_MNEM_add_pc
)
18447 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18449 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18452 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18460 if (fragp
->fr_var
== 4)
18462 insn
= THUMB_OP32 (opcode
);
18463 insn
|= (old_op
& 0xf0) << 4;
18464 insn
|= (old_op
& 0xf) << 16;
18465 put_thumb32_insn (buf
, insn
);
18466 if (insn
& (1 << 20))
18467 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18469 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18472 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18478 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18479 (enum bfd_reloc_code_real
) reloc_type
);
18480 fixp
->fx_file
= fragp
->fr_file
;
18481 fixp
->fx_line
= fragp
->fr_line
;
18482 fragp
->fr_fix
+= fragp
->fr_var
;
18485 /* Return the size of a relaxable immediate operand instruction.
18486 SHIFT and SIZE specify the form of the allowable immediate. */
18488 relax_immediate (fragS
*fragp
, int size
, int shift
)
18494 /* ??? Should be able to do better than this. */
18495 if (fragp
->fr_symbol
)
18498 low
= (1 << shift
) - 1;
18499 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18500 offset
= fragp
->fr_offset
;
18501 /* Force misaligned offsets to 32-bit variant. */
18504 if (offset
& ~mask
)
18509 /* Get the address of a symbol during relaxation. */
18511 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18517 sym
= fragp
->fr_symbol
;
18518 sym_frag
= symbol_get_frag (sym
);
18519 know (S_GET_SEGMENT (sym
) != absolute_section
18520 || sym_frag
== &zero_address_frag
);
18521 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18523 /* If frag has yet to be reached on this pass, assume it will
18524 move by STRETCH just as we did. If this is not so, it will
18525 be because some frag between grows, and that will force
18529 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18533 /* Adjust stretch for any alignment frag. Note that if have
18534 been expanding the earlier code, the symbol may be
18535 defined in what appears to be an earlier frag. FIXME:
18536 This doesn't handle the fr_subtype field, which specifies
18537 a maximum number of bytes to skip when doing an
18539 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18541 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18544 stretch
= - ((- stretch
)
18545 & ~ ((1 << (int) f
->fr_offset
) - 1));
18547 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18559 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18562 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18567 /* Assume worst case for symbols not known to be in the same section. */
18568 if (fragp
->fr_symbol
== NULL
18569 || !S_IS_DEFINED (fragp
->fr_symbol
)
18570 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18571 || S_IS_WEAK (fragp
->fr_symbol
))
18574 val
= relaxed_symbol_addr (fragp
, stretch
);
18575 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18576 addr
= (addr
+ 4) & ~3;
18577 /* Force misaligned targets to 32-bit variant. */
18581 if (val
< 0 || val
> 1020)
18586 /* Return the size of a relaxable add/sub immediate instruction. */
18588 relax_addsub (fragS
*fragp
, asection
*sec
)
18593 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18594 op
= bfd_get_16(sec
->owner
, buf
);
18595 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18596 return relax_immediate (fragp
, 8, 0);
18598 return relax_immediate (fragp
, 3, 0);
18602 /* Return the size of a relaxable branch instruction. BITS is the
18603 size of the offset field in the narrow instruction. */
18606 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18612 /* Assume worst case for symbols not known to be in the same section. */
18613 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18614 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18615 || S_IS_WEAK (fragp
->fr_symbol
))
18619 if (S_IS_DEFINED (fragp
->fr_symbol
)
18620 && ARM_IS_FUNC (fragp
->fr_symbol
))
18624 val
= relaxed_symbol_addr (fragp
, stretch
);
18625 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18628 /* Offset is a signed value *2 */
18630 if (val
>= limit
|| val
< -limit
)
18636 /* Relax a machine dependent frag. This returns the amount by which
18637 the current size of the frag should change. */
18640 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18645 oldsize
= fragp
->fr_var
;
18646 switch (fragp
->fr_subtype
)
18648 case T_MNEM_ldr_pc2
:
18649 newsize
= relax_adr (fragp
, sec
, stretch
);
18651 case T_MNEM_ldr_pc
:
18652 case T_MNEM_ldr_sp
:
18653 case T_MNEM_str_sp
:
18654 newsize
= relax_immediate (fragp
, 8, 2);
18658 newsize
= relax_immediate (fragp
, 5, 2);
18662 newsize
= relax_immediate (fragp
, 5, 1);
18666 newsize
= relax_immediate (fragp
, 5, 0);
18669 newsize
= relax_adr (fragp
, sec
, stretch
);
18675 newsize
= relax_immediate (fragp
, 8, 0);
18678 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18681 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18683 case T_MNEM_add_sp
:
18684 case T_MNEM_add_pc
:
18685 newsize
= relax_immediate (fragp
, 8, 2);
18687 case T_MNEM_inc_sp
:
18688 case T_MNEM_dec_sp
:
18689 newsize
= relax_immediate (fragp
, 7, 2);
18695 newsize
= relax_addsub (fragp
, sec
);
18701 fragp
->fr_var
= newsize
;
18702 /* Freeze wide instructions that are at or before the same location as
18703 in the previous pass. This avoids infinite loops.
18704 Don't freeze them unconditionally because targets may be artificially
18705 misaligned by the expansion of preceding frags. */
18706 if (stretch
<= 0 && newsize
> 2)
18708 md_convert_frag (sec
->owner
, sec
, fragp
);
18712 return newsize
- oldsize
;
18715 /* Round up a section size to the appropriate boundary. */
18718 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18721 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18722 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18724 /* For a.out, force the section size to be aligned. If we don't do
18725 this, BFD will align it for us, but it will not write out the
18726 final bytes of the section. This may be a bug in BFD, but it is
18727 easier to fix it here since that is how the other a.out targets
18731 align
= bfd_get_section_alignment (stdoutput
, segment
);
18732 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18739 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18740 of an rs_align_code fragment. */
18743 arm_handle_align (fragS
* fragP
)
18745 static char const arm_noop
[2][2][4] =
18748 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18749 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18752 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18753 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18756 static char const thumb_noop
[2][2][2] =
18759 {0xc0, 0x46}, /* LE */
18760 {0x46, 0xc0}, /* BE */
18763 {0x00, 0xbf}, /* LE */
18764 {0xbf, 0x00} /* BE */
18767 static char const wide_thumb_noop
[2][4] =
18768 { /* Wide Thumb-2 */
18769 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18770 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18773 unsigned bytes
, fix
, noop_size
;
18776 const char *narrow_noop
= NULL
;
18781 if (fragP
->fr_type
!= rs_align_code
)
18784 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18785 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18788 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18789 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18791 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18793 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18795 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18797 narrow_noop
= thumb_noop
[1][target_big_endian
];
18798 noop
= wide_thumb_noop
[target_big_endian
];
18801 noop
= thumb_noop
[0][target_big_endian
];
18809 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18810 [target_big_endian
];
18817 fragP
->fr_var
= noop_size
;
18819 if (bytes
& (noop_size
- 1))
18821 fix
= bytes
& (noop_size
- 1);
18823 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18825 memset (p
, 0, fix
);
18832 if (bytes
& noop_size
)
18834 /* Insert a narrow noop. */
18835 memcpy (p
, narrow_noop
, noop_size
);
18837 bytes
-= noop_size
;
18841 /* Use wide noops for the remainder */
18845 while (bytes
>= noop_size
)
18847 memcpy (p
, noop
, noop_size
);
18849 bytes
-= noop_size
;
18853 fragP
->fr_fix
+= fix
;
18856 /* Called from md_do_align. Used to create an alignment
18857 frag in a code section. */
18860 arm_frag_align_code (int n
, int max
)
18864 /* We assume that there will never be a requirement
18865 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18866 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18871 _("alignments greater than %d bytes not supported in .text sections."),
18872 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18873 as_fatal ("%s", err_msg
);
18876 p
= frag_var (rs_align_code
,
18877 MAX_MEM_FOR_RS_ALIGN_CODE
,
18879 (relax_substateT
) max
,
18886 /* Perform target specific initialisation of a frag.
18887 Note - despite the name this initialisation is not done when the frag
18888 is created, but only when its type is assigned. A frag can be created
18889 and used a long time before its type is set, so beware of assuming that
18890 this initialisationis performed first. */
18894 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18896 /* Record whether this frag is in an ARM or a THUMB area. */
18897 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18900 #else /* OBJ_ELF is defined. */
18902 arm_init_frag (fragS
* fragP
, int max_chars
)
18904 /* If the current ARM vs THUMB mode has not already
18905 been recorded into this frag then do so now. */
18906 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18908 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18910 /* Record a mapping symbol for alignment frags. We will delete this
18911 later if the alignment ends up empty. */
18912 switch (fragP
->fr_type
)
18915 case rs_align_test
:
18917 mapping_state_2 (MAP_DATA
, max_chars
);
18919 case rs_align_code
:
18920 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
18928 /* When we change sections we need to issue a new mapping symbol. */
18931 arm_elf_change_section (void)
18933 /* Link an unlinked unwind index table section to the .text section. */
18934 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
18935 && elf_linked_to_section (now_seg
) == NULL
)
18936 elf_linked_to_section (now_seg
) = text_section
;
18940 arm_elf_section_type (const char * str
, size_t len
)
18942 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
18943 return SHT_ARM_EXIDX
;
18948 /* Code to deal with unwinding tables. */
18950 static void add_unwind_adjustsp (offsetT
);
18952 /* Generate any deferred unwind frame offset. */
18955 flush_pending_unwind (void)
18959 offset
= unwind
.pending_offset
;
18960 unwind
.pending_offset
= 0;
18962 add_unwind_adjustsp (offset
);
18965 /* Add an opcode to this list for this function. Two-byte opcodes should
18966 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
18970 add_unwind_opcode (valueT op
, int length
)
18972 /* Add any deferred stack adjustment. */
18973 if (unwind
.pending_offset
)
18974 flush_pending_unwind ();
18976 unwind
.sp_restored
= 0;
18978 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
18980 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
18981 if (unwind
.opcodes
)
18982 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
18983 unwind
.opcode_alloc
);
18985 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
18990 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
18992 unwind
.opcode_count
++;
18996 /* Add unwind opcodes to adjust the stack pointer. */
18999 add_unwind_adjustsp (offsetT offset
)
19003 if (offset
> 0x200)
19005 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19010 /* Long form: 0xb2, uleb128. */
19011 /* This might not fit in a word so add the individual bytes,
19012 remembering the list is built in reverse order. */
19013 o
= (valueT
) ((offset
- 0x204) >> 2);
19015 add_unwind_opcode (0, 1);
19017 /* Calculate the uleb128 encoding of the offset. */
19021 bytes
[n
] = o
& 0x7f;
19027 /* Add the insn. */
19029 add_unwind_opcode (bytes
[n
- 1], 1);
19030 add_unwind_opcode (0xb2, 1);
19032 else if (offset
> 0x100)
19034 /* Two short opcodes. */
19035 add_unwind_opcode (0x3f, 1);
19036 op
= (offset
- 0x104) >> 2;
19037 add_unwind_opcode (op
, 1);
19039 else if (offset
> 0)
19041 /* Short opcode. */
19042 op
= (offset
- 4) >> 2;
19043 add_unwind_opcode (op
, 1);
19045 else if (offset
< 0)
19048 while (offset
> 0x100)
19050 add_unwind_opcode (0x7f, 1);
19053 op
= ((offset
- 4) >> 2) | 0x40;
19054 add_unwind_opcode (op
, 1);
19058 /* Finish the list of unwind opcodes for this function. */
19060 finish_unwind_opcodes (void)
19064 if (unwind
.fp_used
)
19066 /* Adjust sp as necessary. */
19067 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19068 flush_pending_unwind ();
19070 /* After restoring sp from the frame pointer. */
19071 op
= 0x90 | unwind
.fp_reg
;
19072 add_unwind_opcode (op
, 1);
19075 flush_pending_unwind ();
19079 /* Start an exception table entry. If idx is nonzero this is an index table
19083 start_unwind_section (const segT text_seg
, int idx
)
19085 const char * text_name
;
19086 const char * prefix
;
19087 const char * prefix_once
;
19088 const char * group_name
;
19092 size_t sec_name_len
;
19099 prefix
= ELF_STRING_ARM_unwind
;
19100 prefix_once
= ELF_STRING_ARM_unwind_once
;
19101 type
= SHT_ARM_EXIDX
;
19105 prefix
= ELF_STRING_ARM_unwind_info
;
19106 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19107 type
= SHT_PROGBITS
;
19110 text_name
= segment_name (text_seg
);
19111 if (streq (text_name
, ".text"))
19114 if (strncmp (text_name
, ".gnu.linkonce.t.",
19115 strlen (".gnu.linkonce.t.")) == 0)
19117 prefix
= prefix_once
;
19118 text_name
+= strlen (".gnu.linkonce.t.");
19121 prefix_len
= strlen (prefix
);
19122 text_len
= strlen (text_name
);
19123 sec_name_len
= prefix_len
+ text_len
;
19124 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19125 memcpy (sec_name
, prefix
, prefix_len
);
19126 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19127 sec_name
[prefix_len
+ text_len
] = '\0';
19133 /* Handle COMDAT group. */
19134 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19136 group_name
= elf_group_name (text_seg
);
19137 if (group_name
== NULL
)
19139 as_bad (_("Group section `%s' has no group signature"),
19140 segment_name (text_seg
));
19141 ignore_rest_of_line ();
19144 flags
|= SHF_GROUP
;
19148 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19150 /* Set the section link for index tables. */
19152 elf_linked_to_section (now_seg
) = text_seg
;
19156 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19157 personality routine data. Returns zero, or the index table value for
19158 and inline entry. */
19161 create_unwind_entry (int have_data
)
19166 /* The current word of data. */
19168 /* The number of bytes left in this word. */
19171 finish_unwind_opcodes ();
19173 /* Remember the current text section. */
19174 unwind
.saved_seg
= now_seg
;
19175 unwind
.saved_subseg
= now_subseg
;
19177 start_unwind_section (now_seg
, 0);
19179 if (unwind
.personality_routine
== NULL
)
19181 if (unwind
.personality_index
== -2)
19184 as_bad (_("handlerdata in cantunwind frame"));
19185 return 1; /* EXIDX_CANTUNWIND. */
19188 /* Use a default personality routine if none is specified. */
19189 if (unwind
.personality_index
== -1)
19191 if (unwind
.opcode_count
> 3)
19192 unwind
.personality_index
= 1;
19194 unwind
.personality_index
= 0;
19197 /* Space for the personality routine entry. */
19198 if (unwind
.personality_index
== 0)
19200 if (unwind
.opcode_count
> 3)
19201 as_bad (_("too many unwind opcodes for personality routine 0"));
19205 /* All the data is inline in the index table. */
19208 while (unwind
.opcode_count
> 0)
19210 unwind
.opcode_count
--;
19211 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19215 /* Pad with "finish" opcodes. */
19217 data
= (data
<< 8) | 0xb0;
19224 /* We get two opcodes "free" in the first word. */
19225 size
= unwind
.opcode_count
- 2;
19228 /* An extra byte is required for the opcode count. */
19229 size
= unwind
.opcode_count
+ 1;
19231 size
= (size
+ 3) >> 2;
19233 as_bad (_("too many unwind opcodes"));
19235 frag_align (2, 0, 0);
19236 record_alignment (now_seg
, 2);
19237 unwind
.table_entry
= expr_build_dot ();
19239 /* Allocate the table entry. */
19240 ptr
= frag_more ((size
<< 2) + 4);
19241 where
= frag_now_fix () - ((size
<< 2) + 4);
19243 switch (unwind
.personality_index
)
19246 /* ??? Should this be a PLT generating relocation? */
19247 /* Custom personality routine. */
19248 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19249 BFD_RELOC_ARM_PREL31
);
19254 /* Set the first byte to the number of additional words. */
19259 /* ABI defined personality routines. */
19261 /* Three opcodes bytes are packed into the first word. */
19268 /* The size and first two opcode bytes go in the first word. */
19269 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19274 /* Should never happen. */
19278 /* Pack the opcodes into words (MSB first), reversing the list at the same
19280 while (unwind
.opcode_count
> 0)
19284 md_number_to_chars (ptr
, data
, 4);
19289 unwind
.opcode_count
--;
19291 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19294 /* Finish off the last word. */
19297 /* Pad with "finish" opcodes. */
19299 data
= (data
<< 8) | 0xb0;
19301 md_number_to_chars (ptr
, data
, 4);
19306 /* Add an empty descriptor if there is no user-specified data. */
19307 ptr
= frag_more (4);
19308 md_number_to_chars (ptr
, 0, 4);
19315 /* Initialize the DWARF-2 unwind information for this procedure. */
19318 tc_arm_frame_initial_instructions (void)
19320 cfi_add_CFA_def_cfa (REG_SP
, 0);
19322 #endif /* OBJ_ELF */
19324 /* Convert REGNAME to a DWARF-2 register number. */
19327 tc_arm_regname_to_dw2regnum (char *regname
)
19329 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19339 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19343 exp
.X_op
= O_secrel
;
19344 exp
.X_add_symbol
= symbol
;
19345 exp
.X_add_number
= 0;
19346 emit_expr (&exp
, size
);
19350 /* MD interface: Symbol and relocation handling. */
19352 /* Return the address within the segment that a PC-relative fixup is
19353 relative to. For ARM, PC-relative fixups applied to instructions
19354 are generally relative to the location of the fixup plus 8 bytes.
19355 Thumb branches are offset by 4, and Thumb loads relative to PC
19356 require special handling. */
19359 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19361 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19363 /* If this is pc-relative and we are going to emit a relocation
19364 then we just want to put out any pipeline compensation that the linker
19365 will need. Otherwise we want to use the calculated base.
19366 For WinCE we skip the bias for externals as well, since this
19367 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19369 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19370 || (arm_force_relocation (fixP
)
19372 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19378 switch (fixP
->fx_r_type
)
19380 /* PC relative addressing on the Thumb is slightly odd as the
19381 bottom two bits of the PC are forced to zero for the
19382 calculation. This happens *after* application of the
19383 pipeline offset. However, Thumb adrl already adjusts for
19384 this, so we need not do it again. */
19385 case BFD_RELOC_ARM_THUMB_ADD
:
19388 case BFD_RELOC_ARM_THUMB_OFFSET
:
19389 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19390 case BFD_RELOC_ARM_T32_ADD_PC12
:
19391 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19392 return (base
+ 4) & ~3;
19394 /* Thumb branches are simply offset by +4. */
19395 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19396 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19397 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19398 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19399 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19402 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19404 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19405 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19406 && ARM_IS_FUNC (fixP
->fx_addsy
)
19407 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19408 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19411 /* BLX is like branches above, but forces the low two bits of PC to
19413 case BFD_RELOC_THUMB_PCREL_BLX
:
19415 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19416 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19417 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19418 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19419 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19420 return (base
+ 4) & ~3;
19422 /* ARM mode branches are offset by +8. However, the Windows CE
19423 loader expects the relocation not to take this into account. */
19424 case BFD_RELOC_ARM_PCREL_BLX
:
19426 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19427 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19428 && ARM_IS_FUNC (fixP
->fx_addsy
)
19429 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19430 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19433 case BFD_RELOC_ARM_PCREL_CALL
:
19435 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19436 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19437 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19438 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19439 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19442 case BFD_RELOC_ARM_PCREL_BRANCH
:
19443 case BFD_RELOC_ARM_PCREL_JUMP
:
19444 case BFD_RELOC_ARM_PLT32
:
19446 /* When handling fixups immediately, because we have already
19447 discovered the value of a symbol, or the address of the frag involved
19448 we must account for the offset by +8, as the OS loader will never see the reloc.
19449 see fixup_segment() in write.c
19450 The S_IS_EXTERNAL test handles the case of global symbols.
19451 Those need the calculated base, not just the pipe compensation the linker will need. */
19453 && fixP
->fx_addsy
!= NULL
19454 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19455 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19463 /* ARM mode loads relative to PC are also offset by +8. Unlike
19464 branches, the Windows CE loader *does* expect the relocation
19465 to take this into account. */
19466 case BFD_RELOC_ARM_OFFSET_IMM
:
19467 case BFD_RELOC_ARM_OFFSET_IMM8
:
19468 case BFD_RELOC_ARM_HWLITERAL
:
19469 case BFD_RELOC_ARM_LITERAL
:
19470 case BFD_RELOC_ARM_CP_OFF_IMM
:
19474 /* Other PC-relative relocations are un-offset. */
19480 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19481 Otherwise we have no need to default values of symbols. */
19484 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19487 if (name
[0] == '_' && name
[1] == 'G'
19488 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19492 if (symbol_find (name
))
19493 as_bad (_("GOT already in the symbol table"));
19495 GOT_symbol
= symbol_new (name
, undefined_section
,
19496 (valueT
) 0, & zero_address_frag
);
19506 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19507 computed as two separate immediate values, added together. We
19508 already know that this value cannot be computed by just one ARM
19511 static unsigned int
19512 validate_immediate_twopart (unsigned int val
,
19513 unsigned int * highpart
)
19518 for (i
= 0; i
< 32; i
+= 2)
19519 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19525 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19527 else if (a
& 0xff0000)
19529 if (a
& 0xff000000)
19531 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19535 gas_assert (a
& 0xff000000);
19536 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19539 return (a
& 0xff) | (i
<< 7);
19546 validate_offset_imm (unsigned int val
, int hwse
)
19548 if ((hwse
&& val
> 255) || val
> 4095)
19553 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19554 negative immediate constant by altering the instruction. A bit of
19559 by inverting the second operand, and
19562 by negating the second operand. */
19565 negate_data_op (unsigned long * instruction
,
19566 unsigned long value
)
19569 unsigned long negated
, inverted
;
19571 negated
= encode_arm_immediate (-value
);
19572 inverted
= encode_arm_immediate (~value
);
19574 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19577 /* First negates. */
19578 case OPCODE_SUB
: /* ADD <-> SUB */
19579 new_inst
= OPCODE_ADD
;
19584 new_inst
= OPCODE_SUB
;
19588 case OPCODE_CMP
: /* CMP <-> CMN */
19589 new_inst
= OPCODE_CMN
;
19594 new_inst
= OPCODE_CMP
;
19598 /* Now Inverted ops. */
19599 case OPCODE_MOV
: /* MOV <-> MVN */
19600 new_inst
= OPCODE_MVN
;
19605 new_inst
= OPCODE_MOV
;
19609 case OPCODE_AND
: /* AND <-> BIC */
19610 new_inst
= OPCODE_BIC
;
19615 new_inst
= OPCODE_AND
;
19619 case OPCODE_ADC
: /* ADC <-> SBC */
19620 new_inst
= OPCODE_SBC
;
19625 new_inst
= OPCODE_ADC
;
19629 /* We cannot do anything. */
19634 if (value
== (unsigned) FAIL
)
19637 *instruction
&= OPCODE_MASK
;
19638 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19642 /* Like negate_data_op, but for Thumb-2. */
19644 static unsigned int
19645 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19649 unsigned int negated
, inverted
;
19651 negated
= encode_thumb32_immediate (-value
);
19652 inverted
= encode_thumb32_immediate (~value
);
19654 rd
= (*instruction
>> 8) & 0xf;
19655 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19658 /* ADD <-> SUB. Includes CMP <-> CMN. */
19659 case T2_OPCODE_SUB
:
19660 new_inst
= T2_OPCODE_ADD
;
19664 case T2_OPCODE_ADD
:
19665 new_inst
= T2_OPCODE_SUB
;
19669 /* ORR <-> ORN. Includes MOV <-> MVN. */
19670 case T2_OPCODE_ORR
:
19671 new_inst
= T2_OPCODE_ORN
;
19675 case T2_OPCODE_ORN
:
19676 new_inst
= T2_OPCODE_ORR
;
19680 /* AND <-> BIC. TST has no inverted equivalent. */
19681 case T2_OPCODE_AND
:
19682 new_inst
= T2_OPCODE_BIC
;
19689 case T2_OPCODE_BIC
:
19690 new_inst
= T2_OPCODE_AND
;
19695 case T2_OPCODE_ADC
:
19696 new_inst
= T2_OPCODE_SBC
;
19700 case T2_OPCODE_SBC
:
19701 new_inst
= T2_OPCODE_ADC
;
19705 /* We cannot do anything. */
19710 if (value
== (unsigned int)FAIL
)
19713 *instruction
&= T2_OPCODE_MASK
;
19714 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19718 /* Read a 32-bit thumb instruction from buf. */
19719 static unsigned long
19720 get_thumb32_insn (char * buf
)
19722 unsigned long insn
;
19723 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19724 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19730 /* We usually want to set the low bit on the address of thumb function
19731 symbols. In particular .word foo - . should have the low bit set.
19732 Generic code tries to fold the difference of two symbols to
19733 a constant. Prevent this and force a relocation when the first symbols
19734 is a thumb function. */
19737 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19739 if (op
== O_subtract
19740 && l
->X_op
== O_symbol
19741 && r
->X_op
== O_symbol
19742 && THUMB_IS_FUNC (l
->X_add_symbol
))
19744 l
->X_op
= O_subtract
;
19745 l
->X_op_symbol
= r
->X_add_symbol
;
19746 l
->X_add_number
-= r
->X_add_number
;
19750 /* Process as normal. */
19754 /* Encode Thumb2 unconditional branches and calls. The encoding
19755 for the 2 are identical for the immediate values. */
19758 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
19760 #define T2I1I2MASK ((1 << 13) | (1 << 11))
19763 addressT S
, I1
, I2
, lo
, hi
;
19765 S
= (value
>> 24) & 0x01;
19766 I1
= (value
>> 23) & 0x01;
19767 I2
= (value
>> 22) & 0x01;
19768 hi
= (value
>> 12) & 0x3ff;
19769 lo
= (value
>> 1) & 0x7ff;
19770 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19771 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19772 newval
|= (S
<< 10) | hi
;
19773 newval2
&= ~T2I1I2MASK
;
19774 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
19775 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19776 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19780 md_apply_fix (fixS
* fixP
,
19784 offsetT value
= * valP
;
19786 unsigned int newimm
;
19787 unsigned long temp
;
19789 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19791 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19793 /* Note whether this will delete the relocation. */
19795 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19798 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19799 consistency with the behaviour on 32-bit hosts. Remember value
19801 value
&= 0xffffffff;
19802 value
^= 0x80000000;
19803 value
-= 0x80000000;
19806 fixP
->fx_addnumber
= value
;
19808 /* Same treatment for fixP->fx_offset. */
19809 fixP
->fx_offset
&= 0xffffffff;
19810 fixP
->fx_offset
^= 0x80000000;
19811 fixP
->fx_offset
-= 0x80000000;
19813 switch (fixP
->fx_r_type
)
19815 case BFD_RELOC_NONE
:
19816 /* This will need to go in the object file. */
19820 case BFD_RELOC_ARM_IMMEDIATE
:
19821 /* We claim that this fixup has been processed here,
19822 even if in fact we generate an error because we do
19823 not have a reloc for it, so tc_gen_reloc will reject it. */
19826 if (fixP
->fx_addsy
)
19828 const char *msg
= 0;
19830 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19831 msg
= _("undefined symbol %s used as an immediate value");
19832 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19833 msg
= _("symbol %s is in a different section");
19834 else if (S_IS_WEAK (fixP
->fx_addsy
))
19835 msg
= _("symbol %s is weak and may be overridden later");
19839 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19840 msg
, S_GET_NAME (fixP
->fx_addsy
));
19845 newimm
= encode_arm_immediate (value
);
19846 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19848 /* If the instruction will fail, see if we can fix things up by
19849 changing the opcode. */
19850 if (newimm
== (unsigned int) FAIL
19851 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19853 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19854 _("invalid constant (%lx) after fixup"),
19855 (unsigned long) value
);
19859 newimm
|= (temp
& 0xfffff000);
19860 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19863 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19865 unsigned int highpart
= 0;
19866 unsigned int newinsn
= 0xe1a00000; /* nop. */
19868 if (fixP
->fx_addsy
)
19870 const char *msg
= 0;
19872 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19873 msg
= _("undefined symbol %s used as an immediate value");
19874 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19875 msg
= _("symbol %s is in a different section");
19876 else if (S_IS_WEAK (fixP
->fx_addsy
))
19877 msg
= _("symbol %s is weak and may be overridden later");
19881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19882 msg
, S_GET_NAME (fixP
->fx_addsy
));
19887 newimm
= encode_arm_immediate (value
);
19888 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19890 /* If the instruction will fail, see if we can fix things up by
19891 changing the opcode. */
19892 if (newimm
== (unsigned int) FAIL
19893 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19895 /* No ? OK - try using two ADD instructions to generate
19897 newimm
= validate_immediate_twopart (value
, & highpart
);
19899 /* Yes - then make sure that the second instruction is
19901 if (newimm
!= (unsigned int) FAIL
)
19903 /* Still No ? Try using a negated value. */
19904 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19905 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19906 /* Otherwise - give up. */
19909 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19910 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19915 /* Replace the first operand in the 2nd instruction (which
19916 is the PC) with the destination register. We have
19917 already added in the PC in the first instruction and we
19918 do not want to do it again. */
19919 newinsn
&= ~ 0xf0000;
19920 newinsn
|= ((newinsn
& 0x0f000) << 4);
19923 newimm
|= (temp
& 0xfffff000);
19924 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19926 highpart
|= (newinsn
& 0xfffff000);
19927 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
19931 case BFD_RELOC_ARM_OFFSET_IMM
:
19932 if (!fixP
->fx_done
&& seg
->use_rela_p
)
19935 case BFD_RELOC_ARM_LITERAL
:
19941 if (validate_offset_imm (value
, 0) == FAIL
)
19943 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
19944 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19945 _("invalid literal constant: pool needs to be closer"));
19947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19948 _("bad immediate value for offset (%ld)"),
19953 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19954 newval
&= 0xff7ff000;
19955 newval
|= value
| (sign
? INDEX_UP
: 0);
19956 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19959 case BFD_RELOC_ARM_OFFSET_IMM8
:
19960 case BFD_RELOC_ARM_HWLITERAL
:
19966 if (validate_offset_imm (value
, 1) == FAIL
)
19968 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
19969 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19970 _("invalid literal constant: pool needs to be closer"));
19972 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
19977 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19978 newval
&= 0xff7ff0f0;
19979 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
19980 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19983 case BFD_RELOC_ARM_T32_OFFSET_U8
:
19984 if (value
< 0 || value
> 1020 || value
% 4 != 0)
19985 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19986 _("bad immediate value for offset (%ld)"), (long) value
);
19989 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
19991 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
19994 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19995 /* This is a complicated relocation used for all varieties of Thumb32
19996 load/store instruction with immediate offset:
19998 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
19999 *4, optional writeback(W)
20000 (doubleword load/store)
20002 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20003 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20004 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20005 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20006 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20008 Uppercase letters indicate bits that are already encoded at
20009 this point. Lowercase letters are our problem. For the
20010 second block of instructions, the secondary opcode nybble
20011 (bits 8..11) is present, and bit 23 is zero, even if this is
20012 a PC-relative operation. */
20013 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20015 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20017 if ((newval
& 0xf0000000) == 0xe0000000)
20019 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20021 newval
|= (1 << 23);
20024 if (value
% 4 != 0)
20026 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20027 _("offset not a multiple of 4"));
20033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20034 _("offset out of range"));
20039 else if ((newval
& 0x000f0000) == 0x000f0000)
20041 /* PC-relative, 12-bit offset. */
20043 newval
|= (1 << 23);
20048 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20049 _("offset out of range"));
20054 else if ((newval
& 0x00000100) == 0x00000100)
20056 /* Writeback: 8-bit, +/- offset. */
20058 newval
|= (1 << 9);
20063 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20064 _("offset out of range"));
20069 else if ((newval
& 0x00000f00) == 0x00000e00)
20071 /* T-instruction: positive 8-bit offset. */
20072 if (value
< 0 || value
> 0xff)
20074 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20075 _("offset out of range"));
20083 /* Positive 12-bit or negative 8-bit offset. */
20087 newval
|= (1 << 23);
20097 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20098 _("offset out of range"));
20105 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20106 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20109 case BFD_RELOC_ARM_SHIFT_IMM
:
20110 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20111 if (((unsigned long) value
) > 32
20113 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20115 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20116 _("shift expression is too large"));
20121 /* Shifts of zero must be done as lsl. */
20123 else if (value
== 32)
20125 newval
&= 0xfffff07f;
20126 newval
|= (value
& 0x1f) << 7;
20127 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20130 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20131 case BFD_RELOC_ARM_T32_ADD_IMM
:
20132 case BFD_RELOC_ARM_T32_IMM12
:
20133 case BFD_RELOC_ARM_T32_ADD_PC12
:
20134 /* We claim that this fixup has been processed here,
20135 even if in fact we generate an error because we do
20136 not have a reloc for it, so tc_gen_reloc will reject it. */
20140 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20143 _("undefined symbol %s used as an immediate value"),
20144 S_GET_NAME (fixP
->fx_addsy
));
20148 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20150 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20153 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20154 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20156 newimm
= encode_thumb32_immediate (value
);
20157 if (newimm
== (unsigned int) FAIL
)
20158 newimm
= thumb32_negate_data_op (&newval
, value
);
20160 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20161 && newimm
== (unsigned int) FAIL
)
20163 /* Turn add/sum into addw/subw. */
20164 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20165 newval
= (newval
& 0xfeffffff) | 0x02000000;
20167 /* 12 bit immediate for addw/subw. */
20171 newval
^= 0x00a00000;
20174 newimm
= (unsigned int) FAIL
;
20179 if (newimm
== (unsigned int)FAIL
)
20181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20182 _("invalid constant (%lx) after fixup"),
20183 (unsigned long) value
);
20187 newval
|= (newimm
& 0x800) << 15;
20188 newval
|= (newimm
& 0x700) << 4;
20189 newval
|= (newimm
& 0x0ff);
20191 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20192 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20195 case BFD_RELOC_ARM_SMC
:
20196 if (((unsigned long) value
) > 0xffff)
20197 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20198 _("invalid smc expression"));
20199 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20200 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20201 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20204 case BFD_RELOC_ARM_SWI
:
20205 if (fixP
->tc_fix_data
!= 0)
20207 if (((unsigned long) value
) > 0xff)
20208 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20209 _("invalid swi expression"));
20210 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20212 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20216 if (((unsigned long) value
) > 0x00ffffff)
20217 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20218 _("invalid swi expression"));
20219 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20221 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20225 case BFD_RELOC_ARM_MULTI
:
20226 if (((unsigned long) value
) > 0xffff)
20227 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20228 _("invalid expression in load/store multiple"));
20229 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20230 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20234 case BFD_RELOC_ARM_PCREL_CALL
:
20236 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20238 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20239 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20240 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20241 /* Flip the bl to blx. This is a simple flip
20242 bit here because we generate PCREL_CALL for
20243 unconditional bls. */
20245 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20246 newval
= newval
| 0x10000000;
20247 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20253 goto arm_branch_common
;
20255 case BFD_RELOC_ARM_PCREL_JUMP
:
20256 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20258 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20259 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20260 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20262 /* This would map to a bl<cond>, b<cond>,
20263 b<always> to a Thumb function. We
20264 need to force a relocation for this particular
20266 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20270 case BFD_RELOC_ARM_PLT32
:
20272 case BFD_RELOC_ARM_PCREL_BRANCH
:
20274 goto arm_branch_common
;
20276 case BFD_RELOC_ARM_PCREL_BLX
:
20279 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20281 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20282 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20283 && ARM_IS_FUNC (fixP
->fx_addsy
))
20285 /* Flip the blx to a bl and warn. */
20286 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20287 newval
= 0xeb000000;
20288 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20289 _("blx to '%s' an ARM ISA state function changed to bl"),
20291 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20297 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20298 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20302 /* We are going to store value (shifted right by two) in the
20303 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20304 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20305 also be be clear. */
20307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20308 _("misaligned branch destination"));
20309 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20310 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20311 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20312 _("branch out of range"));
20314 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20316 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20317 newval
|= (value
>> 2) & 0x00ffffff;
20318 /* Set the H bit on BLX instructions. */
20322 newval
|= 0x01000000;
20324 newval
&= ~0x01000000;
20326 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20330 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20331 /* CBZ can only branch forward. */
20333 /* Attempts to use CBZ to branch to the next instruction
20334 (which, strictly speaking, are prohibited) will be turned into
20337 FIXME: It may be better to remove the instruction completely and
20338 perform relaxation. */
20341 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20342 newval
= 0xbf00; /* NOP encoding T1 */
20343 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20348 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20349 _("branch out of range"));
20351 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20353 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20354 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20355 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20360 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20361 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20362 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20363 _("branch out of range"));
20365 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20367 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20368 newval
|= (value
& 0x1ff) >> 1;
20369 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20373 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20374 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20375 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20376 _("branch out of range"));
20378 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20380 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20381 newval
|= (value
& 0xfff) >> 1;
20382 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20386 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20388 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20389 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20390 && S_IS_DEFINED (fixP
->fx_addsy
)
20391 && ARM_IS_FUNC (fixP
->fx_addsy
)
20392 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20394 /* Force a relocation for a branch 20 bits wide. */
20397 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20398 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20399 _("conditional branch out of range"));
20401 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20404 addressT S
, J1
, J2
, lo
, hi
;
20406 S
= (value
& 0x00100000) >> 20;
20407 J2
= (value
& 0x00080000) >> 19;
20408 J1
= (value
& 0x00040000) >> 18;
20409 hi
= (value
& 0x0003f000) >> 12;
20410 lo
= (value
& 0x00000ffe) >> 1;
20412 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20413 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20414 newval
|= (S
<< 10) | hi
;
20415 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20416 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20417 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20421 case BFD_RELOC_THUMB_PCREL_BLX
:
20423 /* If there is a blx from a thumb state function to
20424 another thumb function flip this to a bl and warn
20428 && S_IS_DEFINED (fixP
->fx_addsy
)
20429 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20430 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20431 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20433 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20434 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20435 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20437 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20438 newval
= newval
| 0x1000;
20439 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20440 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20445 goto thumb_bl_common
;
20447 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20449 /* A bl from Thumb state ISA to an internal ARM state function
20450 is converted to a blx. */
20452 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20453 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20454 && S_IS_DEFINED (fixP
->fx_addsy
)
20455 && ARM_IS_FUNC (fixP
->fx_addsy
)
20456 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20458 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20459 newval
= newval
& ~0x1000;
20460 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20461 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20468 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20469 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20470 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20473 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20474 /* For a BLX instruction, make sure that the relocation is rounded up
20475 to a word boundary. This follows the semantics of the instruction
20476 which specifies that bit 1 of the target address will come from bit
20477 1 of the base address. */
20478 value
= (value
+ 1) & ~ 1;
20481 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20483 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20485 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20486 _("branch out of range"));
20488 else if ((value
& ~0x1ffffff)
20489 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20491 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20492 _("Thumb2 branch out of range"));
20496 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20497 encode_thumb2_b_bl_offset (buf
, value
);
20501 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20502 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20504 _("branch out of range"));
20506 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20507 encode_thumb2_b_bl_offset (buf
, value
);
20512 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20513 md_number_to_chars (buf
, value
, 1);
20517 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20518 md_number_to_chars (buf
, value
, 2);
20522 case BFD_RELOC_ARM_TLS_GD32
:
20523 case BFD_RELOC_ARM_TLS_LE32
:
20524 case BFD_RELOC_ARM_TLS_IE32
:
20525 case BFD_RELOC_ARM_TLS_LDM32
:
20526 case BFD_RELOC_ARM_TLS_LDO32
:
20527 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20530 case BFD_RELOC_ARM_GOT32
:
20531 case BFD_RELOC_ARM_GOTOFF
:
20532 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20533 md_number_to_chars (buf
, 0, 4);
20536 case BFD_RELOC_ARM_GOT_PREL
:
20537 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20538 md_number_to_chars (buf
, value
, 4);
20541 case BFD_RELOC_ARM_TARGET2
:
20542 /* TARGET2 is not partial-inplace, so we need to write the
20543 addend here for REL targets, because it won't be written out
20544 during reloc processing later. */
20545 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20546 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20550 case BFD_RELOC_RVA
:
20552 case BFD_RELOC_ARM_TARGET1
:
20553 case BFD_RELOC_ARM_ROSEGREL32
:
20554 case BFD_RELOC_ARM_SBREL32
:
20555 case BFD_RELOC_32_PCREL
:
20557 case BFD_RELOC_32_SECREL
:
20559 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20561 /* For WinCE we only do this for pcrel fixups. */
20562 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20564 md_number_to_chars (buf
, value
, 4);
20568 case BFD_RELOC_ARM_PREL31
:
20569 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20571 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20572 if ((value
^ (value
>> 1)) & 0x40000000)
20574 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20575 _("rel31 relocation overflow"));
20577 newval
|= value
& 0x7fffffff;
20578 md_number_to_chars (buf
, newval
, 4);
20583 case BFD_RELOC_ARM_CP_OFF_IMM
:
20584 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20585 if (value
< -1023 || value
> 1023 || (value
& 3))
20586 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20587 _("co-processor offset out of range"));
20592 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20593 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20594 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20596 newval
= get_thumb32_insn (buf
);
20597 newval
&= 0xff7fff00;
20598 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20599 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20600 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20601 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20603 put_thumb32_insn (buf
, newval
);
20606 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20607 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20608 if (value
< -255 || value
> 255)
20609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20610 _("co-processor offset out of range"));
20612 goto cp_off_common
;
20614 case BFD_RELOC_ARM_THUMB_OFFSET
:
20615 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20616 /* Exactly what ranges, and where the offset is inserted depends
20617 on the type of instruction, we can establish this from the
20619 switch (newval
>> 12)
20621 case 4: /* PC load. */
20622 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20623 forced to zero for these loads; md_pcrel_from has already
20624 compensated for this. */
20626 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20627 _("invalid offset, target not word aligned (0x%08lX)"),
20628 (((unsigned long) fixP
->fx_frag
->fr_address
20629 + (unsigned long) fixP
->fx_where
) & ~3)
20630 + (unsigned long) value
);
20632 if (value
& ~0x3fc)
20633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20634 _("invalid offset, value too big (0x%08lX)"),
20637 newval
|= value
>> 2;
20640 case 9: /* SP load/store. */
20641 if (value
& ~0x3fc)
20642 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20643 _("invalid offset, value too big (0x%08lX)"),
20645 newval
|= value
>> 2;
20648 case 6: /* Word load/store. */
20650 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20651 _("invalid offset, value too big (0x%08lX)"),
20653 newval
|= value
<< 4; /* 6 - 2. */
20656 case 7: /* Byte load/store. */
20658 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20659 _("invalid offset, value too big (0x%08lX)"),
20661 newval
|= value
<< 6;
20664 case 8: /* Halfword load/store. */
20666 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20667 _("invalid offset, value too big (0x%08lX)"),
20669 newval
|= value
<< 5; /* 6 - 1. */
20673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20674 "Unable to process relocation for thumb opcode: %lx",
20675 (unsigned long) newval
);
20678 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20681 case BFD_RELOC_ARM_THUMB_ADD
:
20682 /* This is a complicated relocation, since we use it for all of
20683 the following immediate relocations:
20687 9bit ADD/SUB SP word-aligned
20688 10bit ADD PC/SP word-aligned
20690 The type of instruction being processed is encoded in the
20697 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20699 int rd
= (newval
>> 4) & 0xf;
20700 int rs
= newval
& 0xf;
20701 int subtract
= !!(newval
& 0x8000);
20703 /* Check for HI regs, only very restricted cases allowed:
20704 Adjusting SP, and using PC or SP to get an address. */
20705 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20706 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20707 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20708 _("invalid Hi register with immediate"));
20710 /* If value is negative, choose the opposite instruction. */
20714 subtract
= !subtract
;
20716 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20717 _("immediate value out of range"));
20722 if (value
& ~0x1fc)
20723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20724 _("invalid immediate for stack address calculation"));
20725 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20726 newval
|= value
>> 2;
20728 else if (rs
== REG_PC
|| rs
== REG_SP
)
20730 if (subtract
|| value
& ~0x3fc)
20731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20732 _("invalid immediate for address calculation (value = 0x%08lX)"),
20733 (unsigned long) value
);
20734 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20736 newval
|= value
>> 2;
20741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20742 _("immediate value out of range"));
20743 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20744 newval
|= (rd
<< 8) | value
;
20749 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20750 _("immediate value out of range"));
20751 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20752 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20755 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20758 case BFD_RELOC_ARM_THUMB_IMM
:
20759 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20760 if (value
< 0 || value
> 255)
20761 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20762 _("invalid immediate: %ld is out of range"),
20765 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20768 case BFD_RELOC_ARM_THUMB_SHIFT
:
20769 /* 5bit shift value (0..32). LSL cannot take 32. */
20770 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20771 temp
= newval
& 0xf800;
20772 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20773 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20774 _("invalid shift value: %ld"), (long) value
);
20775 /* Shifts of zero must be encoded as LSL. */
20777 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20778 /* Shifts of 32 are encoded as zero. */
20779 else if (value
== 32)
20781 newval
|= value
<< 6;
20782 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20785 case BFD_RELOC_VTABLE_INHERIT
:
20786 case BFD_RELOC_VTABLE_ENTRY
:
20790 case BFD_RELOC_ARM_MOVW
:
20791 case BFD_RELOC_ARM_MOVT
:
20792 case BFD_RELOC_ARM_THUMB_MOVW
:
20793 case BFD_RELOC_ARM_THUMB_MOVT
:
20794 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20796 /* REL format relocations are limited to a 16-bit addend. */
20797 if (!fixP
->fx_done
)
20799 if (value
< -0x8000 || value
> 0x7fff)
20800 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20801 _("offset out of range"));
20803 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20804 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20809 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20810 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20812 newval
= get_thumb32_insn (buf
);
20813 newval
&= 0xfbf08f00;
20814 newval
|= (value
& 0xf000) << 4;
20815 newval
|= (value
& 0x0800) << 15;
20816 newval
|= (value
& 0x0700) << 4;
20817 newval
|= (value
& 0x00ff);
20818 put_thumb32_insn (buf
, newval
);
20822 newval
= md_chars_to_number (buf
, 4);
20823 newval
&= 0xfff0f000;
20824 newval
|= value
& 0x0fff;
20825 newval
|= (value
& 0xf000) << 4;
20826 md_number_to_chars (buf
, newval
, 4);
20831 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20832 case BFD_RELOC_ARM_ALU_PC_G0
:
20833 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20834 case BFD_RELOC_ARM_ALU_PC_G1
:
20835 case BFD_RELOC_ARM_ALU_PC_G2
:
20836 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20837 case BFD_RELOC_ARM_ALU_SB_G0
:
20838 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20839 case BFD_RELOC_ARM_ALU_SB_G1
:
20840 case BFD_RELOC_ARM_ALU_SB_G2
:
20841 gas_assert (!fixP
->fx_done
);
20842 if (!seg
->use_rela_p
)
20845 bfd_vma encoded_addend
;
20846 bfd_vma addend_abs
= abs (value
);
20848 /* Check that the absolute value of the addend can be
20849 expressed as an 8-bit constant plus a rotation. */
20850 encoded_addend
= encode_arm_immediate (addend_abs
);
20851 if (encoded_addend
== (unsigned int) FAIL
)
20852 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20853 _("the offset 0x%08lX is not representable"),
20854 (unsigned long) addend_abs
);
20856 /* Extract the instruction. */
20857 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20859 /* If the addend is positive, use an ADD instruction.
20860 Otherwise use a SUB. Take care not to destroy the S bit. */
20861 insn
&= 0xff1fffff;
20867 /* Place the encoded addend into the first 12 bits of the
20869 insn
&= 0xfffff000;
20870 insn
|= encoded_addend
;
20872 /* Update the instruction. */
20873 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20877 case BFD_RELOC_ARM_LDR_PC_G0
:
20878 case BFD_RELOC_ARM_LDR_PC_G1
:
20879 case BFD_RELOC_ARM_LDR_PC_G2
:
20880 case BFD_RELOC_ARM_LDR_SB_G0
:
20881 case BFD_RELOC_ARM_LDR_SB_G1
:
20882 case BFD_RELOC_ARM_LDR_SB_G2
:
20883 gas_assert (!fixP
->fx_done
);
20884 if (!seg
->use_rela_p
)
20887 bfd_vma addend_abs
= abs (value
);
20889 /* Check that the absolute value of the addend can be
20890 encoded in 12 bits. */
20891 if (addend_abs
>= 0x1000)
20892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20893 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20894 (unsigned long) addend_abs
);
20896 /* Extract the instruction. */
20897 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20899 /* If the addend is negative, clear bit 23 of the instruction.
20900 Otherwise set it. */
20902 insn
&= ~(1 << 23);
20906 /* Place the absolute value of the addend into the first 12 bits
20907 of the instruction. */
20908 insn
&= 0xfffff000;
20909 insn
|= addend_abs
;
20911 /* Update the instruction. */
20912 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20916 case BFD_RELOC_ARM_LDRS_PC_G0
:
20917 case BFD_RELOC_ARM_LDRS_PC_G1
:
20918 case BFD_RELOC_ARM_LDRS_PC_G2
:
20919 case BFD_RELOC_ARM_LDRS_SB_G0
:
20920 case BFD_RELOC_ARM_LDRS_SB_G1
:
20921 case BFD_RELOC_ARM_LDRS_SB_G2
:
20922 gas_assert (!fixP
->fx_done
);
20923 if (!seg
->use_rela_p
)
20926 bfd_vma addend_abs
= abs (value
);
20928 /* Check that the absolute value of the addend can be
20929 encoded in 8 bits. */
20930 if (addend_abs
>= 0x100)
20931 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20932 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
20933 (unsigned long) addend_abs
);
20935 /* Extract the instruction. */
20936 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20938 /* If the addend is negative, clear bit 23 of the instruction.
20939 Otherwise set it. */
20941 insn
&= ~(1 << 23);
20945 /* Place the first four bits of the absolute value of the addend
20946 into the first 4 bits of the instruction, and the remaining
20947 four into bits 8 .. 11. */
20948 insn
&= 0xfffff0f0;
20949 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
20951 /* Update the instruction. */
20952 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20956 case BFD_RELOC_ARM_LDC_PC_G0
:
20957 case BFD_RELOC_ARM_LDC_PC_G1
:
20958 case BFD_RELOC_ARM_LDC_PC_G2
:
20959 case BFD_RELOC_ARM_LDC_SB_G0
:
20960 case BFD_RELOC_ARM_LDC_SB_G1
:
20961 case BFD_RELOC_ARM_LDC_SB_G2
:
20962 gas_assert (!fixP
->fx_done
);
20963 if (!seg
->use_rela_p
)
20966 bfd_vma addend_abs
= abs (value
);
20968 /* Check that the absolute value of the addend is a multiple of
20969 four and, when divided by four, fits in 8 bits. */
20970 if (addend_abs
& 0x3)
20971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20972 _("bad offset 0x%08lX (must be word-aligned)"),
20973 (unsigned long) addend_abs
);
20975 if ((addend_abs
>> 2) > 0xff)
20976 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20977 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
20978 (unsigned long) addend_abs
);
20980 /* Extract the instruction. */
20981 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20983 /* If the addend is negative, clear bit 23 of the instruction.
20984 Otherwise set it. */
20986 insn
&= ~(1 << 23);
20990 /* Place the addend (divided by four) into the first eight
20991 bits of the instruction. */
20992 insn
&= 0xfffffff0;
20993 insn
|= addend_abs
>> 2;
20995 /* Update the instruction. */
20996 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21000 case BFD_RELOC_ARM_V4BX
:
21001 /* This will need to go in the object file. */
21005 case BFD_RELOC_UNUSED
:
21007 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21008 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21012 /* Translate internal representation of relocation info to BFD target
21016 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21019 bfd_reloc_code_real_type code
;
21021 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21023 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21024 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21025 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21027 if (fixp
->fx_pcrel
)
21029 if (section
->use_rela_p
)
21030 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21032 fixp
->fx_offset
= reloc
->address
;
21034 reloc
->addend
= fixp
->fx_offset
;
21036 switch (fixp
->fx_r_type
)
21039 if (fixp
->fx_pcrel
)
21041 code
= BFD_RELOC_8_PCREL
;
21046 if (fixp
->fx_pcrel
)
21048 code
= BFD_RELOC_16_PCREL
;
21053 if (fixp
->fx_pcrel
)
21055 code
= BFD_RELOC_32_PCREL
;
21059 case BFD_RELOC_ARM_MOVW
:
21060 if (fixp
->fx_pcrel
)
21062 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21066 case BFD_RELOC_ARM_MOVT
:
21067 if (fixp
->fx_pcrel
)
21069 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21073 case BFD_RELOC_ARM_THUMB_MOVW
:
21074 if (fixp
->fx_pcrel
)
21076 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21080 case BFD_RELOC_ARM_THUMB_MOVT
:
21081 if (fixp
->fx_pcrel
)
21083 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21087 case BFD_RELOC_NONE
:
21088 case BFD_RELOC_ARM_PCREL_BRANCH
:
21089 case BFD_RELOC_ARM_PCREL_BLX
:
21090 case BFD_RELOC_RVA
:
21091 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21092 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21093 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21094 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21095 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21096 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21097 case BFD_RELOC_VTABLE_ENTRY
:
21098 case BFD_RELOC_VTABLE_INHERIT
:
21100 case BFD_RELOC_32_SECREL
:
21102 code
= fixp
->fx_r_type
;
21105 case BFD_RELOC_THUMB_PCREL_BLX
:
21107 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21108 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21111 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21114 case BFD_RELOC_ARM_LITERAL
:
21115 case BFD_RELOC_ARM_HWLITERAL
:
21116 /* If this is called then the a literal has
21117 been referenced across a section boundary. */
21118 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21119 _("literal referenced across section boundary"));
21123 case BFD_RELOC_ARM_GOT32
:
21124 case BFD_RELOC_ARM_GOTOFF
:
21125 case BFD_RELOC_ARM_GOT_PREL
:
21126 case BFD_RELOC_ARM_PLT32
:
21127 case BFD_RELOC_ARM_TARGET1
:
21128 case BFD_RELOC_ARM_ROSEGREL32
:
21129 case BFD_RELOC_ARM_SBREL32
:
21130 case BFD_RELOC_ARM_PREL31
:
21131 case BFD_RELOC_ARM_TARGET2
:
21132 case BFD_RELOC_ARM_TLS_LE32
:
21133 case BFD_RELOC_ARM_TLS_LDO32
:
21134 case BFD_RELOC_ARM_PCREL_CALL
:
21135 case BFD_RELOC_ARM_PCREL_JUMP
:
21136 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21137 case BFD_RELOC_ARM_ALU_PC_G0
:
21138 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21139 case BFD_RELOC_ARM_ALU_PC_G1
:
21140 case BFD_RELOC_ARM_ALU_PC_G2
:
21141 case BFD_RELOC_ARM_LDR_PC_G0
:
21142 case BFD_RELOC_ARM_LDR_PC_G1
:
21143 case BFD_RELOC_ARM_LDR_PC_G2
:
21144 case BFD_RELOC_ARM_LDRS_PC_G0
:
21145 case BFD_RELOC_ARM_LDRS_PC_G1
:
21146 case BFD_RELOC_ARM_LDRS_PC_G2
:
21147 case BFD_RELOC_ARM_LDC_PC_G0
:
21148 case BFD_RELOC_ARM_LDC_PC_G1
:
21149 case BFD_RELOC_ARM_LDC_PC_G2
:
21150 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21151 case BFD_RELOC_ARM_ALU_SB_G0
:
21152 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21153 case BFD_RELOC_ARM_ALU_SB_G1
:
21154 case BFD_RELOC_ARM_ALU_SB_G2
:
21155 case BFD_RELOC_ARM_LDR_SB_G0
:
21156 case BFD_RELOC_ARM_LDR_SB_G1
:
21157 case BFD_RELOC_ARM_LDR_SB_G2
:
21158 case BFD_RELOC_ARM_LDRS_SB_G0
:
21159 case BFD_RELOC_ARM_LDRS_SB_G1
:
21160 case BFD_RELOC_ARM_LDRS_SB_G2
:
21161 case BFD_RELOC_ARM_LDC_SB_G0
:
21162 case BFD_RELOC_ARM_LDC_SB_G1
:
21163 case BFD_RELOC_ARM_LDC_SB_G2
:
21164 case BFD_RELOC_ARM_V4BX
:
21165 code
= fixp
->fx_r_type
;
21168 case BFD_RELOC_ARM_TLS_GD32
:
21169 case BFD_RELOC_ARM_TLS_IE32
:
21170 case BFD_RELOC_ARM_TLS_LDM32
:
21171 /* BFD will include the symbol's address in the addend.
21172 But we don't want that, so subtract it out again here. */
21173 if (!S_IS_COMMON (fixp
->fx_addsy
))
21174 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21175 code
= fixp
->fx_r_type
;
21179 case BFD_RELOC_ARM_IMMEDIATE
:
21180 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21181 _("internal relocation (type: IMMEDIATE) not fixed up"));
21184 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21185 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21186 _("ADRL used for a symbol not defined in the same file"));
21189 case BFD_RELOC_ARM_OFFSET_IMM
:
21190 if (section
->use_rela_p
)
21192 code
= fixp
->fx_r_type
;
21196 if (fixp
->fx_addsy
!= NULL
21197 && !S_IS_DEFINED (fixp
->fx_addsy
)
21198 && S_IS_LOCAL (fixp
->fx_addsy
))
21200 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21201 _("undefined local label `%s'"),
21202 S_GET_NAME (fixp
->fx_addsy
));
21206 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21207 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21214 switch (fixp
->fx_r_type
)
21216 case BFD_RELOC_NONE
: type
= "NONE"; break;
21217 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21218 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21219 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21220 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21221 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21222 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21223 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21224 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21225 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21226 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21227 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21228 default: type
= _("<unknown>"); break;
21230 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21231 _("cannot represent %s relocation in this object file format"),
21238 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21240 && fixp
->fx_addsy
== GOT_symbol
)
21242 code
= BFD_RELOC_ARM_GOTPC
;
21243 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21247 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21249 if (reloc
->howto
== NULL
)
21251 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21252 _("cannot represent %s relocation in this object file format"),
21253 bfd_get_reloc_code_name (code
));
21257 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21258 vtable entry to be used in the relocation's section offset. */
21259 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21260 reloc
->address
= fixp
->fx_offset
;
21265 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21268 cons_fix_new_arm (fragS
* frag
,
21273 bfd_reloc_code_real_type type
;
21277 FIXME: @@ Should look at CPU word size. */
21281 type
= BFD_RELOC_8
;
21284 type
= BFD_RELOC_16
;
21288 type
= BFD_RELOC_32
;
21291 type
= BFD_RELOC_64
;
21296 if (exp
->X_op
== O_secrel
)
21298 exp
->X_op
= O_symbol
;
21299 type
= BFD_RELOC_32_SECREL
;
21303 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21306 #if defined (OBJ_COFF)
21308 arm_validate_fix (fixS
* fixP
)
21310 /* If the destination of the branch is a defined symbol which does not have
21311 the THUMB_FUNC attribute, then we must be calling a function which has
21312 the (interfacearm) attribute. We look for the Thumb entry point to that
21313 function and change the branch to refer to that function instead. */
21314 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21315 && fixP
->fx_addsy
!= NULL
21316 && S_IS_DEFINED (fixP
->fx_addsy
)
21317 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21319 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21326 arm_force_relocation (struct fix
* fixp
)
21328 #if defined (OBJ_COFF) && defined (TE_PE)
21329 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21333 /* In case we have a call or a branch to a function in ARM ISA mode from
21334 a thumb function or vice-versa force the relocation. These relocations
21335 are cleared off for some cores that might have blx and simple transformations
21339 switch (fixp
->fx_r_type
)
21341 case BFD_RELOC_ARM_PCREL_JUMP
:
21342 case BFD_RELOC_ARM_PCREL_CALL
:
21343 case BFD_RELOC_THUMB_PCREL_BLX
:
21344 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21348 case BFD_RELOC_ARM_PCREL_BLX
:
21349 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21350 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21351 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21352 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21361 /* Resolve these relocations even if the symbol is extern or weak. */
21362 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21363 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21364 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21365 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21366 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21367 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21368 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21371 /* Always leave these relocations for the linker. */
21372 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21373 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21374 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21377 /* Always generate relocations against function symbols. */
21378 if (fixp
->fx_r_type
== BFD_RELOC_32
21380 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21383 return generic_force_reloc (fixp
);
21386 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21387 /* Relocations against function names must be left unadjusted,
21388 so that the linker can use this information to generate interworking
21389 stubs. The MIPS version of this function
21390 also prevents relocations that are mips-16 specific, but I do not
21391 know why it does this.
21394 There is one other problem that ought to be addressed here, but
21395 which currently is not: Taking the address of a label (rather
21396 than a function) and then later jumping to that address. Such
21397 addresses also ought to have their bottom bit set (assuming that
21398 they reside in Thumb code), but at the moment they will not. */
21401 arm_fix_adjustable (fixS
* fixP
)
21403 if (fixP
->fx_addsy
== NULL
)
21406 /* Preserve relocations against symbols with function type. */
21407 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21410 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21411 && fixP
->fx_subsy
== NULL
)
21414 /* We need the symbol name for the VTABLE entries. */
21415 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21416 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21419 /* Don't allow symbols to be discarded on GOT related relocs. */
21420 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21421 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21422 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21423 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21424 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21425 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21426 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21427 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21428 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21431 /* Similarly for group relocations. */
21432 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21433 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21434 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21437 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21438 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21439 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21440 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21441 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21442 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21443 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21444 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21445 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21450 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21455 elf32_arm_target_format (void)
21458 return (target_big_endian
21459 ? "elf32-bigarm-symbian"
21460 : "elf32-littlearm-symbian");
21461 #elif defined (TE_VXWORKS)
21462 return (target_big_endian
21463 ? "elf32-bigarm-vxworks"
21464 : "elf32-littlearm-vxworks");
21466 if (target_big_endian
)
21467 return "elf32-bigarm";
21469 return "elf32-littlearm";
21474 armelf_frob_symbol (symbolS
* symp
,
21477 elf_frob_symbol (symp
, puntp
);
21481 /* MD interface: Finalization. */
21486 literal_pool
* pool
;
21488 /* Ensure that all the IT blocks are properly closed. */
21489 check_it_blocks_finished ();
21491 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21493 /* Put it at the end of the relevant section. */
21494 subseg_set (pool
->section
, pool
->sub_section
);
21496 arm_elf_change_section ();
21503 /* Remove any excess mapping symbols generated for alignment frags in
21504 SEC. We may have created a mapping symbol before a zero byte
21505 alignment; remove it if there's a mapping symbol after the
21508 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21509 void *dummy ATTRIBUTE_UNUSED
)
21511 segment_info_type
*seginfo
= seg_info (sec
);
21514 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21517 for (fragp
= seginfo
->frchainP
->frch_root
;
21519 fragp
= fragp
->fr_next
)
21521 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21522 fragS
*next
= fragp
->fr_next
;
21524 /* Variable-sized frags have been converted to fixed size by
21525 this point. But if this was variable-sized to start with,
21526 there will be a fixed-size frag after it. So don't handle
21528 if (sym
== NULL
|| next
== NULL
)
21531 if (S_GET_VALUE (sym
) < next
->fr_address
)
21532 /* Not at the end of this frag. */
21534 know (S_GET_VALUE (sym
) == next
->fr_address
);
21538 if (next
->tc_frag_data
.first_map
!= NULL
)
21540 /* Next frag starts with a mapping symbol. Discard this
21542 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21546 if (next
->fr_next
== NULL
)
21548 /* This mapping symbol is at the end of the section. Discard
21550 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21551 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21555 /* As long as we have empty frags without any mapping symbols,
21557 /* If the next frag is non-empty and does not start with a
21558 mapping symbol, then this mapping symbol is required. */
21559 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21562 next
= next
->fr_next
;
21564 while (next
!= NULL
);
21569 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21573 arm_adjust_symtab (void)
21578 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21580 if (ARM_IS_THUMB (sym
))
21582 if (THUMB_IS_FUNC (sym
))
21584 /* Mark the symbol as a Thumb function. */
21585 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21586 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21587 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21589 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21590 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21592 as_bad (_("%s: unexpected function type: %d"),
21593 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21595 else switch (S_GET_STORAGE_CLASS (sym
))
21598 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21601 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21604 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21612 if (ARM_IS_INTERWORK (sym
))
21613 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21620 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21622 if (ARM_IS_THUMB (sym
))
21624 elf_symbol_type
* elf_sym
;
21626 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21627 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21629 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21630 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21632 /* If it's a .thumb_func, declare it as so,
21633 otherwise tag label as .code 16. */
21634 if (THUMB_IS_FUNC (sym
))
21635 elf_sym
->internal_elf_sym
.st_info
=
21636 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21637 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21638 elf_sym
->internal_elf_sym
.st_info
=
21639 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21644 /* Remove any overlapping mapping symbols generated by alignment frags. */
21645 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21649 /* MD interface: Initialization. */
21652 set_constant_flonums (void)
21656 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21657 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21661 /* Auto-select Thumb mode if it's the only available instruction set for the
21662 given architecture. */
21665 autoselect_thumb_from_cpu_variant (void)
21667 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21668 opcode_select (16);
21677 if ( (arm_ops_hsh
= hash_new ()) == NULL
21678 || (arm_cond_hsh
= hash_new ()) == NULL
21679 || (arm_shift_hsh
= hash_new ()) == NULL
21680 || (arm_psr_hsh
= hash_new ()) == NULL
21681 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21682 || (arm_reg_hsh
= hash_new ()) == NULL
21683 || (arm_reloc_hsh
= hash_new ()) == NULL
21684 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21685 as_fatal (_("virtual memory exhausted"));
21687 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21688 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21689 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21690 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21691 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21692 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21693 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21694 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21695 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21696 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21697 (void *) (v7m_psrs
+ i
));
21698 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21699 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21701 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21703 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21704 (void *) (barrier_opt_names
+ i
));
21706 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21707 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21710 set_constant_flonums ();
21712 /* Set the cpu variant based on the command-line options. We prefer
21713 -mcpu= over -march= if both are set (as for GCC); and we prefer
21714 -mfpu= over any other way of setting the floating point unit.
21715 Use of legacy options with new options are faulted. */
21718 if (mcpu_cpu_opt
|| march_cpu_opt
)
21719 as_bad (_("use of old and new-style options to set CPU type"));
21721 mcpu_cpu_opt
= legacy_cpu
;
21723 else if (!mcpu_cpu_opt
)
21724 mcpu_cpu_opt
= march_cpu_opt
;
21729 as_bad (_("use of old and new-style options to set FPU type"));
21731 mfpu_opt
= legacy_fpu
;
21733 else if (!mfpu_opt
)
21735 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21736 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21737 /* Some environments specify a default FPU. If they don't, infer it
21738 from the processor. */
21740 mfpu_opt
= mcpu_fpu_opt
;
21742 mfpu_opt
= march_fpu_opt
;
21744 mfpu_opt
= &fpu_default
;
21750 if (mcpu_cpu_opt
!= NULL
)
21751 mfpu_opt
= &fpu_default
;
21752 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21753 mfpu_opt
= &fpu_arch_vfp_v2
;
21755 mfpu_opt
= &fpu_arch_fpa
;
21761 mcpu_cpu_opt
= &cpu_default
;
21762 selected_cpu
= cpu_default
;
21766 selected_cpu
= *mcpu_cpu_opt
;
21768 mcpu_cpu_opt
= &arm_arch_any
;
21771 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21773 autoselect_thumb_from_cpu_variant ();
21775 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21777 #if defined OBJ_COFF || defined OBJ_ELF
21779 unsigned int flags
= 0;
21781 #if defined OBJ_ELF
21782 flags
= meabi_flags
;
21784 switch (meabi_flags
)
21786 case EF_ARM_EABI_UNKNOWN
:
21788 /* Set the flags in the private structure. */
21789 if (uses_apcs_26
) flags
|= F_APCS26
;
21790 if (support_interwork
) flags
|= F_INTERWORK
;
21791 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21792 if (pic_code
) flags
|= F_PIC
;
21793 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21794 flags
|= F_SOFT_FLOAT
;
21796 switch (mfloat_abi_opt
)
21798 case ARM_FLOAT_ABI_SOFT
:
21799 case ARM_FLOAT_ABI_SOFTFP
:
21800 flags
|= F_SOFT_FLOAT
;
21803 case ARM_FLOAT_ABI_HARD
:
21804 if (flags
& F_SOFT_FLOAT
)
21805 as_bad (_("hard-float conflicts with specified fpu"));
21809 /* Using pure-endian doubles (even if soft-float). */
21810 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21811 flags
|= F_VFP_FLOAT
;
21813 #if defined OBJ_ELF
21814 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21815 flags
|= EF_ARM_MAVERICK_FLOAT
;
21818 case EF_ARM_EABI_VER4
:
21819 case EF_ARM_EABI_VER5
:
21820 /* No additional flags to set. */
21827 bfd_set_private_flags (stdoutput
, flags
);
21829 /* We have run out flags in the COFF header to encode the
21830 status of ATPCS support, so instead we create a dummy,
21831 empty, debug section called .arm.atpcs. */
21836 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21840 bfd_set_section_flags
21841 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21842 bfd_set_section_size (stdoutput
, sec
, 0);
21843 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21849 /* Record the CPU type as well. */
21850 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21851 mach
= bfd_mach_arm_iWMMXt2
;
21852 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21853 mach
= bfd_mach_arm_iWMMXt
;
21854 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21855 mach
= bfd_mach_arm_XScale
;
21856 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21857 mach
= bfd_mach_arm_ep9312
;
21858 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21859 mach
= bfd_mach_arm_5TE
;
21860 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21862 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21863 mach
= bfd_mach_arm_5T
;
21865 mach
= bfd_mach_arm_5
;
21867 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21869 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21870 mach
= bfd_mach_arm_4T
;
21872 mach
= bfd_mach_arm_4
;
21874 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21875 mach
= bfd_mach_arm_3M
;
21876 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21877 mach
= bfd_mach_arm_3
;
21878 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21879 mach
= bfd_mach_arm_2a
;
21880 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21881 mach
= bfd_mach_arm_2
;
21883 mach
= bfd_mach_arm_unknown
;
21885 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21888 /* Command line processing. */
21891 Invocation line includes a switch not recognized by the base assembler.
21892 See if it's a processor-specific option.
21894 This routine is somewhat complicated by the need for backwards
21895 compatibility (since older releases of gcc can't be changed).
21896 The new options try to make the interface as compatible as
21899 New options (supported) are:
21901 -mcpu=<cpu name> Assemble for selected processor
21902 -march=<architecture name> Assemble for selected architecture
21903 -mfpu=<fpu architecture> Assemble for selected FPU.
21904 -EB/-mbig-endian Big-endian
21905 -EL/-mlittle-endian Little-endian
21906 -k Generate PIC code
21907 -mthumb Start in Thumb mode
21908 -mthumb-interwork Code supports ARM/Thumb interworking
21910 -m[no-]warn-deprecated Warn about deprecated features
21912 For now we will also provide support for:
21914 -mapcs-32 32-bit Program counter
21915 -mapcs-26 26-bit Program counter
21916 -macps-float Floats passed in FP registers
21917 -mapcs-reentrant Reentrant code
21919 (sometime these will probably be replaced with -mapcs=<list of options>
21920 and -matpcs=<list of options>)
21922 The remaining options are only supported for back-wards compatibility.
21923 Cpu variants, the arm part is optional:
21924 -m[arm]1 Currently not supported.
21925 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21926 -m[arm]3 Arm 3 processor
21927 -m[arm]6[xx], Arm 6 processors
21928 -m[arm]7[xx][t][[d]m] Arm 7 processors
21929 -m[arm]8[10] Arm 8 processors
21930 -m[arm]9[20][tdmi] Arm 9 processors
21931 -mstrongarm[110[0]] StrongARM processors
21932 -mxscale XScale processors
21933 -m[arm]v[2345[t[e]]] Arm architectures
21934 -mall All (except the ARM1)
21936 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
21937 -mfpe-old (No float load/store multiples)
21938 -mvfpxd VFP Single precision
21940 -mno-fpu Disable all floating point instructions
21942 The following CPU names are recognized:
21943 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
21944 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
21945 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
21946 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
21947 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
21948 arm10t arm10e, arm1020t, arm1020e, arm10200e,
21949 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
21953 const char * md_shortopts
= "m:k";
21955 #ifdef ARM_BI_ENDIAN
21956 #define OPTION_EB (OPTION_MD_BASE + 0)
21957 #define OPTION_EL (OPTION_MD_BASE + 1)
21959 #if TARGET_BYTES_BIG_ENDIAN
21960 #define OPTION_EB (OPTION_MD_BASE + 0)
21962 #define OPTION_EL (OPTION_MD_BASE + 1)
21965 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
21967 struct option md_longopts
[] =
21970 {"EB", no_argument
, NULL
, OPTION_EB
},
21973 {"EL", no_argument
, NULL
, OPTION_EL
},
21975 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
21976 {NULL
, no_argument
, NULL
, 0}
21979 size_t md_longopts_size
= sizeof (md_longopts
);
21981 struct arm_option_table
21983 char *option
; /* Option name to match. */
21984 char *help
; /* Help information. */
21985 int *var
; /* Variable to change. */
21986 int value
; /* What to change it to. */
21987 char *deprecated
; /* If non-null, print this message. */
21990 struct arm_option_table arm_opts
[] =
21992 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
21993 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
21994 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
21995 &support_interwork
, 1, NULL
},
21996 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
21997 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
21998 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22000 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22001 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22002 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22003 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22006 /* These are recognized by the assembler, but have no affect on code. */
22007 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22008 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22010 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22011 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22012 &warn_on_deprecated
, 0, NULL
},
22013 {NULL
, NULL
, NULL
, 0, NULL
}
22016 struct arm_legacy_option_table
22018 char *option
; /* Option name to match. */
22019 const arm_feature_set
**var
; /* Variable to change. */
22020 const arm_feature_set value
; /* What to change it to. */
22021 char *deprecated
; /* If non-null, print this message. */
22024 const struct arm_legacy_option_table arm_legacy_opts
[] =
22026 /* DON'T add any new processors to this list -- we want the whole list
22027 to go away... Add them to the processors table instead. */
22028 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22029 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22030 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22031 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22032 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22033 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22034 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22035 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22036 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22037 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22038 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22039 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22040 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22041 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22042 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22043 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22044 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22045 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22046 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22047 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22048 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22049 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22050 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22051 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22052 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22053 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22054 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22055 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22056 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22057 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22058 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22059 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22060 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22061 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22062 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22063 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22064 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22065 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22066 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22067 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22068 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22069 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22070 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22071 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22072 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22073 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22074 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22075 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22076 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22077 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22078 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22079 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22080 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22081 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22082 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22083 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22084 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22085 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22086 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22087 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22088 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22089 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22090 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22091 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22092 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22093 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22094 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22095 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22096 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22097 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22098 N_("use -mcpu=strongarm110")},
22099 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22100 N_("use -mcpu=strongarm1100")},
22101 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22102 N_("use -mcpu=strongarm1110")},
22103 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22104 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22105 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22107 /* Architecture variants -- don't add any more to this list either. */
22108 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22109 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22110 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22111 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22112 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22113 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22114 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22115 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22116 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22117 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22118 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22119 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22120 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22121 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22122 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22123 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22124 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22125 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22127 /* Floating point variants -- don't add any more to this list either. */
22128 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22129 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22130 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22131 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22132 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22134 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22137 struct arm_cpu_option_table
22140 const arm_feature_set value
;
22141 /* For some CPUs we assume an FPU unless the user explicitly sets
22143 const arm_feature_set default_fpu
;
22144 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22146 const char *canonical_name
;
22149 /* This list should, at a minimum, contain all the cpu names
22150 recognized by GCC. */
22151 static const struct arm_cpu_option_table arm_cpus
[] =
22153 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22154 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22155 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22156 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22157 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22158 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22159 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22160 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22161 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22162 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22163 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22164 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22165 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22166 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22167 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22168 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22169 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22170 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22171 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22172 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22173 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22174 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22175 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22176 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22177 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22178 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22179 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22180 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22181 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22182 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22183 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22184 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22185 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22186 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22187 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22188 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22189 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22190 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22191 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22192 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22193 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22194 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22195 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22196 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22197 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22198 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22199 /* For V5 or later processors we default to using VFP; but the user
22200 should really set the FPU type explicitly. */
22201 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22202 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22203 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22204 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22205 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22206 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22207 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22208 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22209 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22210 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22211 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22212 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22213 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22214 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22215 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22216 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22217 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22218 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22219 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22220 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22221 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22222 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22223 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22224 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22225 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22226 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22227 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22228 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
22229 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
22230 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22231 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22232 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22233 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22234 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, NULL
},
22235 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22236 | FPU_NEON_EXT_V1
),
22238 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22239 | FPU_NEON_EXT_V1
),
22241 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
22242 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
, NULL
},
22243 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, NULL
},
22244 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
22245 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22246 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22247 /* ??? XSCALE is really an architecture. */
22248 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22249 /* ??? iwmmxt is not a processor. */
22250 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22251 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22252 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22254 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22255 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22258 struct arm_arch_option_table
22261 const arm_feature_set value
;
22262 const arm_feature_set default_fpu
;
22265 /* This list should, at a minimum, contain all the architecture names
22266 recognized by GCC. */
22267 static const struct arm_arch_option_table arm_archs
[] =
22269 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22270 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22271 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22272 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22273 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22274 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22275 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22276 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22277 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22278 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22279 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22280 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22281 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22282 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22283 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22284 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22285 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22286 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22287 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22288 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22289 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22290 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22291 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22292 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22293 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22294 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22295 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22296 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22297 /* The official spelling of the ARMv7 profile variants is the dashed form.
22298 Accept the non-dashed form for compatibility with old toolchains. */
22299 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22300 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22301 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22302 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22303 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22304 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22305 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22306 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22307 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22308 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22309 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22312 /* ISA extensions in the co-processor space. */
22313 struct arm_option_cpu_value_table
22316 const arm_feature_set value
;
22319 static const struct arm_option_cpu_value_table arm_extensions
[] =
22321 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
22322 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
22323 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
22324 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
22325 {NULL
, ARM_ARCH_NONE
}
22328 /* This list should, at a minimum, contain all the fpu names
22329 recognized by GCC. */
22330 static const struct arm_option_cpu_value_table arm_fpus
[] =
22332 {"softfpa", FPU_NONE
},
22333 {"fpe", FPU_ARCH_FPE
},
22334 {"fpe2", FPU_ARCH_FPE
},
22335 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22336 {"fpa", FPU_ARCH_FPA
},
22337 {"fpa10", FPU_ARCH_FPA
},
22338 {"fpa11", FPU_ARCH_FPA
},
22339 {"arm7500fe", FPU_ARCH_FPA
},
22340 {"softvfp", FPU_ARCH_VFP
},
22341 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22342 {"vfp", FPU_ARCH_VFP_V2
},
22343 {"vfp9", FPU_ARCH_VFP_V2
},
22344 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22345 {"vfp10", FPU_ARCH_VFP_V2
},
22346 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22347 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22348 {"vfpv2", FPU_ARCH_VFP_V2
},
22349 {"vfpv3", FPU_ARCH_VFP_V3
},
22350 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22351 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22352 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22353 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22354 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22355 {"arm1020t", FPU_ARCH_VFP_V1
},
22356 {"arm1020e", FPU_ARCH_VFP_V2
},
22357 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22358 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22359 {"maverick", FPU_ARCH_MAVERICK
},
22360 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22361 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22362 {"vfpv4", FPU_ARCH_VFP_V4
},
22363 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22364 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22365 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22366 {NULL
, ARM_ARCH_NONE
}
22369 struct arm_option_value_table
22375 static const struct arm_option_value_table arm_float_abis
[] =
22377 {"hard", ARM_FLOAT_ABI_HARD
},
22378 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22379 {"soft", ARM_FLOAT_ABI_SOFT
},
22384 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22385 static const struct arm_option_value_table arm_eabis
[] =
22387 {"gnu", EF_ARM_EABI_UNKNOWN
},
22388 {"4", EF_ARM_EABI_VER4
},
22389 {"5", EF_ARM_EABI_VER5
},
22394 struct arm_long_option_table
22396 char * option
; /* Substring to match. */
22397 char * help
; /* Help information. */
22398 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22399 char * deprecated
; /* If non-null, print this message. */
22403 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22405 arm_feature_set
*ext_set
= (arm_feature_set
*)
22406 xmalloc (sizeof (arm_feature_set
));
22408 /* Copy the feature set, so that we can modify it. */
22409 *ext_set
= **opt_p
;
22412 while (str
!= NULL
&& *str
!= 0)
22414 const struct arm_option_cpu_value_table
* opt
;
22420 as_bad (_("invalid architectural extension"));
22425 ext
= strchr (str
, '+');
22428 optlen
= ext
- str
;
22430 optlen
= strlen (str
);
22434 as_bad (_("missing architectural extension"));
22438 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22439 if (strncmp (opt
->name
, str
, optlen
) == 0)
22441 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22445 if (opt
->name
== NULL
)
22447 as_bad (_("unknown architectural extension `%s'"), str
);
22458 arm_parse_cpu (char * str
)
22460 const struct arm_cpu_option_table
* opt
;
22461 char * ext
= strchr (str
, '+');
22465 optlen
= ext
- str
;
22467 optlen
= strlen (str
);
22471 as_bad (_("missing cpu name `%s'"), str
);
22475 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22476 if (strncmp (opt
->name
, str
, optlen
) == 0)
22478 mcpu_cpu_opt
= &opt
->value
;
22479 mcpu_fpu_opt
= &opt
->default_fpu
;
22480 if (opt
->canonical_name
)
22481 strcpy (selected_cpu_name
, opt
->canonical_name
);
22486 for (i
= 0; i
< optlen
; i
++)
22487 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22488 selected_cpu_name
[i
] = 0;
22492 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22497 as_bad (_("unknown cpu `%s'"), str
);
22502 arm_parse_arch (char * str
)
22504 const struct arm_arch_option_table
*opt
;
22505 char *ext
= strchr (str
, '+');
22509 optlen
= ext
- str
;
22511 optlen
= strlen (str
);
22515 as_bad (_("missing architecture name `%s'"), str
);
22519 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22520 if (streq (opt
->name
, str
))
22522 march_cpu_opt
= &opt
->value
;
22523 march_fpu_opt
= &opt
->default_fpu
;
22524 strcpy (selected_cpu_name
, opt
->name
);
22527 return arm_parse_extension (ext
, &march_cpu_opt
);
22532 as_bad (_("unknown architecture `%s'\n"), str
);
22537 arm_parse_fpu (char * str
)
22539 const struct arm_option_cpu_value_table
* opt
;
22541 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22542 if (streq (opt
->name
, str
))
22544 mfpu_opt
= &opt
->value
;
22548 as_bad (_("unknown floating point format `%s'\n"), str
);
22553 arm_parse_float_abi (char * str
)
22555 const struct arm_option_value_table
* opt
;
22557 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22558 if (streq (opt
->name
, str
))
22560 mfloat_abi_opt
= opt
->value
;
22564 as_bad (_("unknown floating point abi `%s'\n"), str
);
22570 arm_parse_eabi (char * str
)
22572 const struct arm_option_value_table
*opt
;
22574 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22575 if (streq (opt
->name
, str
))
22577 meabi_flags
= opt
->value
;
22580 as_bad (_("unknown EABI `%s'\n"), str
);
22586 arm_parse_it_mode (char * str
)
22588 bfd_boolean ret
= TRUE
;
22590 if (streq ("arm", str
))
22591 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22592 else if (streq ("thumb", str
))
22593 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22594 else if (streq ("always", str
))
22595 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22596 else if (streq ("never", str
))
22597 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22600 as_bad (_("unknown implicit IT mode `%s', should be "\
22601 "arm, thumb, always, or never."), str
);
22608 struct arm_long_option_table arm_long_opts
[] =
22610 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22611 arm_parse_cpu
, NULL
},
22612 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22613 arm_parse_arch
, NULL
},
22614 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22615 arm_parse_fpu
, NULL
},
22616 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22617 arm_parse_float_abi
, NULL
},
22619 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22620 arm_parse_eabi
, NULL
},
22622 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22623 arm_parse_it_mode
, NULL
},
22624 {NULL
, NULL
, 0, NULL
}
22628 md_parse_option (int c
, char * arg
)
22630 struct arm_option_table
*opt
;
22631 const struct arm_legacy_option_table
*fopt
;
22632 struct arm_long_option_table
*lopt
;
22638 target_big_endian
= 1;
22644 target_big_endian
= 0;
22648 case OPTION_FIX_V4BX
:
22653 /* Listing option. Just ignore these, we don't support additional
22658 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22660 if (c
== opt
->option
[0]
22661 && ((arg
== NULL
&& opt
->option
[1] == 0)
22662 || streq (arg
, opt
->option
+ 1)))
22664 /* If the option is deprecated, tell the user. */
22665 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22666 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22667 arg
? arg
: "", _(opt
->deprecated
));
22669 if (opt
->var
!= NULL
)
22670 *opt
->var
= opt
->value
;
22676 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22678 if (c
== fopt
->option
[0]
22679 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22680 || streq (arg
, fopt
->option
+ 1)))
22682 /* If the option is deprecated, tell the user. */
22683 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22684 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22685 arg
? arg
: "", _(fopt
->deprecated
));
22687 if (fopt
->var
!= NULL
)
22688 *fopt
->var
= &fopt
->value
;
22694 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22696 /* These options are expected to have an argument. */
22697 if (c
== lopt
->option
[0]
22699 && strncmp (arg
, lopt
->option
+ 1,
22700 strlen (lopt
->option
+ 1)) == 0)
22702 /* If the option is deprecated, tell the user. */
22703 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22704 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22705 _(lopt
->deprecated
));
22707 /* Call the sup-option parser. */
22708 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22719 md_show_usage (FILE * fp
)
22721 struct arm_option_table
*opt
;
22722 struct arm_long_option_table
*lopt
;
22724 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22726 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22727 if (opt
->help
!= NULL
)
22728 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22730 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22731 if (lopt
->help
!= NULL
)
22732 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22736 -EB assemble code for a big-endian cpu\n"));
22741 -EL assemble code for a little-endian cpu\n"));
22745 --fix-v4bx Allow BX in ARMv4 code\n"));
22753 arm_feature_set flags
;
22754 } cpu_arch_ver_table
;
22756 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22757 least features first. */
22758 static const cpu_arch_ver_table cpu_arch_ver
[] =
22764 {4, ARM_ARCH_V5TE
},
22765 {5, ARM_ARCH_V5TEJ
},
22769 {11, ARM_ARCH_V6M
},
22770 {8, ARM_ARCH_V6T2
},
22771 {10, ARM_ARCH_V7A
},
22772 {10, ARM_ARCH_V7R
},
22773 {10, ARM_ARCH_V7M
},
22777 /* Set an attribute if it has not already been set by the user. */
22779 aeabi_set_attribute_int (int tag
, int value
)
22782 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22783 || !attributes_set_explicitly
[tag
])
22784 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22788 aeabi_set_attribute_string (int tag
, const char *value
)
22791 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22792 || !attributes_set_explicitly
[tag
])
22793 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22796 /* Set the public EABI object attributes. */
22798 aeabi_set_public_attributes (void)
22801 arm_feature_set flags
;
22802 arm_feature_set tmp
;
22803 const cpu_arch_ver_table
*p
;
22805 /* Choose the architecture based on the capabilities of the requested cpu
22806 (if any) and/or the instructions actually used. */
22807 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22808 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22809 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22810 /*Allow the user to override the reported architecture. */
22813 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22814 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22819 for (p
= cpu_arch_ver
; p
->val
; p
++)
22821 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22824 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22828 /* The table lookup above finds the last architecture to contribute
22829 a new feature. Unfortunately, Tag13 is a subset of the union of
22830 v6T2 and v7-M, so it is never seen as contributing a new feature.
22831 We can not search for the last entry which is entirely used,
22832 because if no CPU is specified we build up only those flags
22833 actually used. Perhaps we should separate out the specified
22834 and implicit cases. Avoid taking this path for -march=all by
22835 checking for contradictory v7-A / v7-M features. */
22837 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
22838 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
22839 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
22842 /* Tag_CPU_name. */
22843 if (selected_cpu_name
[0])
22847 q
= selected_cpu_name
;
22848 if (strncmp (q
, "armv", 4) == 0)
22853 for (i
= 0; q
[i
]; i
++)
22854 q
[i
] = TOUPPER (q
[i
]);
22856 aeabi_set_attribute_string (Tag_CPU_name
, q
);
22859 /* Tag_CPU_arch. */
22860 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22862 /* Tag_CPU_arch_profile. */
22863 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22864 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22865 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22866 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22867 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22868 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22870 /* Tag_ARM_ISA_use. */
22871 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22873 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22875 /* Tag_THUMB_ISA_use. */
22876 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22878 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22879 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22881 /* Tag_VFP_arch. */
22882 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
22883 aeabi_set_attribute_int (Tag_VFP_arch
,
22884 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
22886 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22887 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22888 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
22889 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22890 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22891 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22892 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22893 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22894 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22896 /* Tag_ABI_HardFP_use. */
22897 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
22898 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
22899 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
22901 /* Tag_WMMX_arch. */
22902 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22903 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22904 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22905 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22907 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22908 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22909 aeabi_set_attribute_int
22910 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
22913 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22914 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
22915 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22918 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
22919 aeabi_set_attribute_int (Tag_DIV_use
, 0);
22920 /* Fill this in when gas supports v7a sdiv/udiv.
22921 else if (... v7a with div extension used ...)
22922 aeabi_set_attribute_int (Tag_DIV_use, 2); */
22924 aeabi_set_attribute_int (Tag_DIV_use
, 1);
22927 /* Add the default contents for the .ARM.attributes section. */
22931 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22934 aeabi_set_public_attributes ();
22936 #endif /* OBJ_ELF */
22939 /* Parse a .cpu directive. */
22942 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
22944 const struct arm_cpu_option_table
*opt
;
22948 name
= input_line_pointer
;
22949 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22950 input_line_pointer
++;
22951 saved_char
= *input_line_pointer
;
22952 *input_line_pointer
= 0;
22954 /* Skip the first "all" entry. */
22955 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
22956 if (streq (opt
->name
, name
))
22958 mcpu_cpu_opt
= &opt
->value
;
22959 selected_cpu
= opt
->value
;
22960 if (opt
->canonical_name
)
22961 strcpy (selected_cpu_name
, opt
->canonical_name
);
22965 for (i
= 0; opt
->name
[i
]; i
++)
22966 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22967 selected_cpu_name
[i
] = 0;
22969 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22970 *input_line_pointer
= saved_char
;
22971 demand_empty_rest_of_line ();
22974 as_bad (_("unknown cpu `%s'"), name
);
22975 *input_line_pointer
= saved_char
;
22976 ignore_rest_of_line ();
22980 /* Parse a .arch directive. */
22983 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
22985 const struct arm_arch_option_table
*opt
;
22989 name
= input_line_pointer
;
22990 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22991 input_line_pointer
++;
22992 saved_char
= *input_line_pointer
;
22993 *input_line_pointer
= 0;
22995 /* Skip the first "all" entry. */
22996 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22997 if (streq (opt
->name
, name
))
22999 mcpu_cpu_opt
= &opt
->value
;
23000 selected_cpu
= opt
->value
;
23001 strcpy (selected_cpu_name
, opt
->name
);
23002 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23003 *input_line_pointer
= saved_char
;
23004 demand_empty_rest_of_line ();
23008 as_bad (_("unknown architecture `%s'\n"), name
);
23009 *input_line_pointer
= saved_char
;
23010 ignore_rest_of_line ();
23014 /* Parse a .object_arch directive. */
23017 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23019 const struct arm_arch_option_table
*opt
;
23023 name
= input_line_pointer
;
23024 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23025 input_line_pointer
++;
23026 saved_char
= *input_line_pointer
;
23027 *input_line_pointer
= 0;
23029 /* Skip the first "all" entry. */
23030 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23031 if (streq (opt
->name
, name
))
23033 object_arch
= &opt
->value
;
23034 *input_line_pointer
= saved_char
;
23035 demand_empty_rest_of_line ();
23039 as_bad (_("unknown architecture `%s'\n"), name
);
23040 *input_line_pointer
= saved_char
;
23041 ignore_rest_of_line ();
23044 /* Parse a .fpu directive. */
23047 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23049 const struct arm_option_cpu_value_table
*opt
;
23053 name
= input_line_pointer
;
23054 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23055 input_line_pointer
++;
23056 saved_char
= *input_line_pointer
;
23057 *input_line_pointer
= 0;
23059 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23060 if (streq (opt
->name
, name
))
23062 mfpu_opt
= &opt
->value
;
23063 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23064 *input_line_pointer
= saved_char
;
23065 demand_empty_rest_of_line ();
23069 as_bad (_("unknown floating point format `%s'\n"), name
);
23070 *input_line_pointer
= saved_char
;
23071 ignore_rest_of_line ();
23074 /* Copy symbol information. */
23077 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23079 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23083 /* Given a symbolic attribute NAME, return the proper integer value.
23084 Returns -1 if the attribute is not known. */
23087 arm_convert_symbolic_attribute (const char *name
)
23089 static const struct
23094 attribute_table
[] =
23096 /* When you modify this table you should
23097 also modify the list in doc/c-arm.texi. */
23098 #define T(tag) {#tag, tag}
23099 T (Tag_CPU_raw_name
),
23102 T (Tag_CPU_arch_profile
),
23103 T (Tag_ARM_ISA_use
),
23104 T (Tag_THUMB_ISA_use
),
23108 T (Tag_Advanced_SIMD_arch
),
23109 T (Tag_PCS_config
),
23110 T (Tag_ABI_PCS_R9_use
),
23111 T (Tag_ABI_PCS_RW_data
),
23112 T (Tag_ABI_PCS_RO_data
),
23113 T (Tag_ABI_PCS_GOT_use
),
23114 T (Tag_ABI_PCS_wchar_t
),
23115 T (Tag_ABI_FP_rounding
),
23116 T (Tag_ABI_FP_denormal
),
23117 T (Tag_ABI_FP_exceptions
),
23118 T (Tag_ABI_FP_user_exceptions
),
23119 T (Tag_ABI_FP_number_model
),
23120 T (Tag_ABI_align_needed
),
23121 T (Tag_ABI_align8_needed
),
23122 T (Tag_ABI_align_preserved
),
23123 T (Tag_ABI_align8_preserved
),
23124 T (Tag_ABI_enum_size
),
23125 T (Tag_ABI_HardFP_use
),
23126 T (Tag_ABI_VFP_args
),
23127 T (Tag_ABI_WMMX_args
),
23128 T (Tag_ABI_optimization_goals
),
23129 T (Tag_ABI_FP_optimization_goals
),
23130 T (Tag_compatibility
),
23131 T (Tag_CPU_unaligned_access
),
23132 T (Tag_FP_HP_extension
),
23133 T (Tag_VFP_HP_extension
),
23134 T (Tag_ABI_FP_16bit_format
),
23135 T (Tag_MPextension_use
),
23137 T (Tag_nodefaults
),
23138 T (Tag_also_compatible_with
),
23139 T (Tag_conformance
),
23141 T (Tag_Virtualization_use
),
23142 /* We deliberately do not include Tag_MPextension_use_legacy. */
23150 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23151 if (streq (name
, attribute_table
[i
].name
))
23152 return attribute_table
[i
].tag
;
23158 /* Apply sym value for relocations only in the case that
23159 they are for local symbols and you have the respective
23160 architectural feature for blx and simple switches. */
23162 arm_apply_sym_value (struct fix
* fixP
)
23165 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23166 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
23168 switch (fixP
->fx_r_type
)
23170 case BFD_RELOC_ARM_PCREL_BLX
:
23171 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23172 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23176 case BFD_RELOC_ARM_PCREL_CALL
:
23177 case BFD_RELOC_THUMB_PCREL_BLX
:
23178 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23189 #endif /* OBJ_ELF */