1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 /* Types of processor to assemble for. */
40 #define ARM_1 0x00000001
41 #define ARM_2 0x00000002
42 #define ARM_3 0x00000004
44 #define ARM_6 0x00000008
45 #define ARM_7 ARM_6 /* same core instruction set */
46 #define ARM_8 ARM_6 /* same core instruction set */
47 #define ARM_9 ARM_6 /* same core instruction set */
48 #define ARM_CPU_MASK 0x0000000f
50 /* The following bitmasks control CPU extensions (ARM7 onwards): */
51 #define ARM_LONGMUL 0x00000010 /* allow long multiplies */
52 #define ARM_HALFWORD 0x00000020 /* allow half word loads */
53 #define ARM_THUMB 0x00000040 /* allow BX instruction */
54 #define ARM_EXT_V5 0x00000080 /* allow CLZ etc */
55 #define ARM_EXT_V5E 0x00000200 /* "El Segundo" */
57 /* Architectures are the sum of the base and extensions */
58 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
59 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
60 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5 )
61 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
63 /* Some useful combinations: */
64 #define ARM_ANY 0x00ffffff
65 #define ARM_2UP (ARM_ANY - ARM_1)
66 #define ARM_ALL ARM_2UP /* Not arm1 only */
67 #define ARM_3UP 0x00fffffc
68 #define ARM_6UP 0x00fffff8 /* Includes ARM7 */
70 #define FPU_CORE 0x80000000
71 #define FPU_FPA10 0x40000000
72 #define FPU_FPA11 0x40000000
75 /* Some useful combinations */
76 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY */
77 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core */
82 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
84 #define CPU_DEFAULT ARM_ALL
89 #define FPU_DEFAULT FPU_ALL
92 #define streq(a, b) (strcmp (a, b) == 0)
93 #define skip_whitespace(str) while (* (str) == ' ') ++ (str)
95 static unsigned long cpu_variant
= CPU_DEFAULT
| FPU_DEFAULT
;
96 static int target_oabi
= 0;
98 #if defined OBJ_COFF || defined OBJ_ELF
99 /* Flags stored in private area of BFD structure */
100 static boolean uses_apcs_26
= false;
101 static boolean support_interwork
= false;
102 static boolean uses_apcs_float
= false;
103 static boolean pic_code
= false;
106 /* This array holds the chars that always start a comment. If the
107 pre-processor is disabled, these aren't very useful */
108 CONST
char comment_chars
[] = "@";
110 /* This array holds the chars that only start a comment at the beginning of
111 a line. If the line seems to have the form '# 123 filename'
112 .line and .file directives will appear in the pre-processed output */
113 /* Note that input_file.c hand checks for '#' at the beginning of the
114 first line of the input file. This is because the compiler outputs
115 #NO_APP at the beginning of its output. */
116 /* Also note that comments like this one will always work. */
117 CONST
char line_comment_chars
[] = "#";
120 CONST
char line_separator_chars
[] = ";";
122 CONST
char line_separator_chars
[] = "";
125 /* Chars that can be used to separate mant from exp in floating point nums */
126 CONST
char EXP_CHARS
[] = "eE";
128 /* Chars that mean this number is a floating point constant */
132 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
134 /* Prefix characters that indicate the start of an immediate
136 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
139 symbolS
* GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
142 CONST
int md_reloc_size
= 8; /* Size of relocation record */
144 static int thumb_mode
= 0; /* non-zero if assembling thumb instructions */
146 typedef struct arm_fix
154 unsigned long instruction
;
159 bfd_reloc_code_real_type type
;
169 CONST
char * template;
173 static CONST
struct asm_shift shift
[] =
189 #define NO_SHIFT_RESTRICT 1
190 #define SHIFT_RESTRICT 0
192 #define NUM_FLOAT_VALS 8
194 CONST
char * fp_const
[] =
196 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
199 /* Number of littlenums required to hold an extended precision number */
200 #define MAX_LITTLENUMS 6
202 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
212 #define CP_T_X 0x00008000
213 #define CP_T_Y 0x00400000
214 #define CP_T_Pre 0x01000000
215 #define CP_T_UD 0x00800000
216 #define CP_T_WB 0x00200000
218 #define CONDS_BIT (0x00100000)
219 #define LOAD_BIT (0x00100000)
220 #define TRANS_BIT (0x00200000)
224 CONST
char * template;
228 /* This is to save a hash look-up in the common case */
229 #define COND_ALWAYS 0xe0000000
231 static CONST
struct asm_cond conds
[] =
235 {"cs", 0x20000000}, {"hs", 0x20000000},
236 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
251 /* Warning: If the top bit of the set_bits is set, then the standard
252 instruction bitmask is ignored, and the new bitmask is taken from
256 CONST
char * template; /* Basic flag string */
257 unsigned long set_bits
; /* Bits to set */
260 static CONST
struct asm_flg s_flag
[] =
266 static CONST
struct asm_flg ldr_flags
[] =
270 {"bt", 0x00400000 | TRANS_BIT
},
277 static CONST
struct asm_flg str_flags
[] =
281 {"bt", 0x00400000 | TRANS_BIT
},
286 static CONST
struct asm_flg byte_flag
[] =
292 static CONST
struct asm_flg cmp_flags
[] =
299 static CONST
struct asm_flg ldm_flags
[] =
312 static CONST
struct asm_flg stm_flags
[] =
325 static CONST
struct asm_flg lfm_flags
[] =
332 static CONST
struct asm_flg sfm_flags
[] =
339 static CONST
struct asm_flg round_flags
[] =
347 /* The implementation of the FIX instruction is broken on some assemblers,
348 in that it accepts a precision specifier as well as a rounding specifier,
349 despite the fact that this is meaningless. To be more compatible, we
350 accept it as well, though of course it does not set any bits. */
351 static CONST
struct asm_flg fix_flags
[] =
368 static CONST
struct asm_flg except_flag
[] =
374 static CONST
struct asm_flg cplong_flag
[] =
382 CONST
char * template;
383 unsigned long number
;
386 #define PSR_FIELD_MASK 0x000f0000
388 #define PSR_FLAGS 0x00080000
389 #define PSR_CONTROL 0x00010000 /* Undocumented instruction, its use is discouraged by ARM */
390 #define PSR_ALL 0x00090000
399 static CONST
struct asm_psr psrs
[] =
403 {"cpsr_all", CPSR_ALL
},
405 {"spsr_all", SPSR_ALL
},
408 {"cpsr_flg", CPSR_FLG
},
409 {"spsr_flg", SPSR_FLG
},
412 {"cpsr_c", CPSR_CTL
},
413 {"cpsr_ctl", CPSR_CTL
},
414 {"spsr_c", SPSR_CTL
},
415 {"spsr_ctl", SPSR_CTL
}
418 /* Functions called by parser */
419 /* ARM instructions */
420 static void do_arit
PARAMS ((char *, unsigned long));
421 static void do_cmp
PARAMS ((char *, unsigned long));
422 static void do_mov
PARAMS ((char *, unsigned long));
423 static void do_ldst
PARAMS ((char *, unsigned long));
424 static void do_ldmstm
PARAMS ((char *, unsigned long));
425 static void do_branch
PARAMS ((char *, unsigned long));
426 static void do_swi
PARAMS ((char *, unsigned long));
427 /* Pseudo Op codes */
428 static void do_adr
PARAMS ((char *, unsigned long));
429 static void do_adrl
PARAMS ((char *, unsigned long));
430 static void do_nop
PARAMS ((char *, unsigned long));
432 static void do_mul
PARAMS ((char *, unsigned long));
433 static void do_mla
PARAMS ((char *, unsigned long));
435 static void do_swap
PARAMS ((char *, unsigned long));
437 static void do_msr
PARAMS ((char *, unsigned long));
438 static void do_mrs
PARAMS ((char *, unsigned long));
440 static void do_mull
PARAMS ((char *, unsigned long));
442 static void do_bx
PARAMS ((char *, unsigned long));
445 /* Coprocessor Instructions */
446 static void do_cdp
PARAMS ((char *, unsigned long));
447 static void do_lstc
PARAMS ((char *, unsigned long));
448 static void do_co_reg
PARAMS ((char *, unsigned long));
449 static void do_fp_ctrl
PARAMS ((char *, unsigned long));
450 static void do_fp_ldst
PARAMS ((char *, unsigned long));
451 static void do_fp_ldmstm
PARAMS ((char *, unsigned long));
452 static void do_fp_dyadic
PARAMS ((char *, unsigned long));
453 static void do_fp_monadic
PARAMS ((char *, unsigned long));
454 static void do_fp_cmp
PARAMS ((char *, unsigned long));
455 static void do_fp_from_reg
PARAMS ((char *, unsigned long));
456 static void do_fp_to_reg
PARAMS ((char *, unsigned long));
458 static void fix_new_arm
PARAMS ((fragS
*, int, short, expressionS
*, int, int));
459 static int arm_reg_parse
PARAMS ((char **));
460 static int arm_psr_parse
PARAMS ((char **));
461 static void symbol_locate
PARAMS ((symbolS
*, CONST
char *, segT
, valueT
, fragS
*));
462 static int add_to_lit_pool
PARAMS ((void));
463 static unsigned validate_immediate
PARAMS ((unsigned));
464 static unsigned validate_immediate_twopart
PARAMS ((unsigned int, unsigned int *));
465 static int validate_offset_imm
PARAMS ((unsigned int, int));
466 static void opcode_select
PARAMS ((int));
467 static void end_of_line
PARAMS ((char *));
468 static int reg_required_here
PARAMS ((char **, int));
469 static int psr_required_here
PARAMS ((char **, int, int));
470 static int co_proc_number
PARAMS ((char **));
471 static int cp_opc_expr
PARAMS ((char **, int, int));
472 static int cp_reg_required_here
PARAMS ((char **, int));
473 static int fp_reg_required_here
PARAMS ((char **, int));
474 static int cp_address_offset
PARAMS ((char **));
475 static int cp_address_required_here
PARAMS ((char **));
476 static int my_get_float_expression
PARAMS ((char **));
477 static int skip_past_comma
PARAMS ((char **));
478 static int walk_no_bignums
PARAMS ((symbolS
*));
479 static int negate_data_op
PARAMS ((unsigned long *, unsigned long));
480 static int data_op2
PARAMS ((char **));
481 static int fp_op2
PARAMS ((char **));
482 static long reg_list
PARAMS ((char **));
483 static void thumb_load_store
PARAMS ((char *, int, int));
484 static int decode_shift
PARAMS ((char **, int));
485 static int ldst_extend
PARAMS ((char **, int));
486 static void thumb_add_sub
PARAMS ((char *, int));
487 static void insert_reg
PARAMS ((int));
488 static void thumb_shift
PARAMS ((char *, int));
489 static void thumb_mov_compare
PARAMS ((char *, int));
490 static void set_constant_flonums
PARAMS ((void));
491 static valueT md_chars_to_number
PARAMS ((char *, int));
492 static void insert_reg_alias
PARAMS ((char *, int));
493 static void output_inst
PARAMS ((void));
495 static bfd_reloc_code_real_type arm_parse_reloc
PARAMS ((void));
498 /* ARM instructions take 4bytes in the object file, Thumb instructions
502 /* LONGEST_INST is the longest basic instruction name without conditions or
504 * ARM7M has 4 of length 5
507 #define LONGEST_INST 5
512 CONST
char * template; /* Basic string to match */
513 unsigned long value
; /* Basic instruction code */
515 /* Compulsory suffix that must follow conds. If "", then the
516 instruction is not conditional and must have no suffix. */
517 CONST
char * comp_suffix
;
519 CONST
struct asm_flg
* flags
; /* Bits to toggle if flag 'n' set */
520 unsigned long variants
; /* Which CPU variants this exists for */
521 /* Function to call to parse args */
522 void (* parms
) PARAMS ((char *, unsigned long));
525 static CONST
struct asm_opcode insns
[] =
527 /* ARM Instructions */
528 {"and", 0x00000000, NULL
, s_flag
, ARM_ANY
, do_arit
},
529 {"eor", 0x00200000, NULL
, s_flag
, ARM_ANY
, do_arit
},
530 {"sub", 0x00400000, NULL
, s_flag
, ARM_ANY
, do_arit
},
531 {"rsb", 0x00600000, NULL
, s_flag
, ARM_ANY
, do_arit
},
532 {"add", 0x00800000, NULL
, s_flag
, ARM_ANY
, do_arit
},
533 {"adc", 0x00a00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
534 {"sbc", 0x00c00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
535 {"rsc", 0x00e00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
536 {"orr", 0x01800000, NULL
, s_flag
, ARM_ANY
, do_arit
},
537 {"bic", 0x01c00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
538 {"tst", 0x01000000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
539 {"teq", 0x01200000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
540 {"cmp", 0x01400000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
541 {"cmn", 0x01600000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
542 {"mov", 0x01a00000, NULL
, s_flag
, ARM_ANY
, do_mov
},
543 {"mvn", 0x01e00000, NULL
, s_flag
, ARM_ANY
, do_mov
},
544 {"str", 0x04000000, NULL
, str_flags
, ARM_ANY
, do_ldst
},
545 {"ldr", 0x04100000, NULL
, ldr_flags
, ARM_ANY
, do_ldst
},
546 {"stm", 0x08000000, NULL
, stm_flags
, ARM_ANY
, do_ldmstm
},
547 {"ldm", 0x08100000, NULL
, ldm_flags
, ARM_ANY
, do_ldmstm
},
548 {"swi", 0x0f000000, NULL
, NULL
, ARM_ANY
, do_swi
},
549 {"bl", 0x0bfffffe, NULL
, NULL
, ARM_ANY
, do_branch
},
550 {"b", 0x0afffffe, NULL
, NULL
, ARM_ANY
, do_branch
},
553 {"adr", 0x028f0000, NULL
, NULL
, ARM_ANY
, do_adr
},
554 {"adrl", 0x028f0000, NULL
, NULL
, ARM_ANY
, do_adrl
},
555 {"nop", 0x01a00000, NULL
, NULL
, ARM_ANY
, do_nop
},
557 /* ARM 2 multiplies */
558 {"mul", 0x00000090, NULL
, s_flag
, ARM_2UP
, do_mul
},
559 {"mla", 0x00200090, NULL
, s_flag
, ARM_2UP
, do_mla
},
561 /* ARM 3 - swp instructions */
562 {"swp", 0x01000090, NULL
, byte_flag
, ARM_3UP
, do_swap
},
564 /* ARM 6 Coprocessor instructions */
565 {"mrs", 0x010f0000, NULL
, NULL
, ARM_6UP
, do_mrs
},
566 {"msr", 0x0120f000, NULL
, NULL
, ARM_6UP
, do_msr
},
567 /* ScottB: our code uses 0x0128f000 for msr.
568 NickC: but this is wrong because the bits 16 and 19 are handled
569 by the PSR_xxx defines above. */
571 /* ARM 7M long multiplies - need signed/unsigned flags! */
572 {"smull", 0x00c00090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
573 {"umull", 0x00800090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
574 {"smlal", 0x00e00090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
575 {"umlal", 0x00a00090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
577 /* ARM THUMB interworking */
578 {"bx", 0x012fff10, NULL
, NULL
, ARM_THUMB
, do_bx
},
580 /* Floating point instructions */
581 {"wfs", 0x0e200110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
582 {"rfs", 0x0e300110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
583 {"wfc", 0x0e400110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
584 {"rfc", 0x0e500110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
585 {"ldf", 0x0c100100, "sdep", NULL
, FPU_ALL
, do_fp_ldst
},
586 {"stf", 0x0c000100, "sdep", NULL
, FPU_ALL
, do_fp_ldst
},
587 {"lfm", 0x0c100200, NULL
, lfm_flags
, FPU_MEMMULTI
, do_fp_ldmstm
},
588 {"sfm", 0x0c000200, NULL
, sfm_flags
, FPU_MEMMULTI
, do_fp_ldmstm
},
589 {"mvf", 0x0e008100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
590 {"mnf", 0x0e108100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
591 {"abs", 0x0e208100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
592 {"rnd", 0x0e308100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
593 {"sqt", 0x0e408100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
594 {"log", 0x0e508100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
595 {"lgn", 0x0e608100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
596 {"exp", 0x0e708100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
597 {"sin", 0x0e808100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
598 {"cos", 0x0e908100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
599 {"tan", 0x0ea08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
600 {"asn", 0x0eb08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
601 {"acs", 0x0ec08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
602 {"atn", 0x0ed08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
603 {"urd", 0x0ee08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
604 {"nrm", 0x0ef08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
605 {"adf", 0x0e000100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
606 {"suf", 0x0e200100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
607 {"rsf", 0x0e300100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
608 {"muf", 0x0e100100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
609 {"dvf", 0x0e400100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
610 {"rdf", 0x0e500100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
611 {"pow", 0x0e600100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
612 {"rpw", 0x0e700100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
613 {"rmf", 0x0e800100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
614 {"fml", 0x0e900100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
615 {"fdv", 0x0ea00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
616 {"frd", 0x0eb00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
617 {"pol", 0x0ec00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
618 {"cmf", 0x0e90f110, NULL
, except_flag
, FPU_ALL
, do_fp_cmp
},
619 {"cnf", 0x0eb0f110, NULL
, except_flag
, FPU_ALL
, do_fp_cmp
},
620 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
621 be an optional suffix, but part of the instruction. To be compatible,
623 {"cmfe", 0x0ed0f110, NULL
, NULL
, FPU_ALL
, do_fp_cmp
},
624 {"cnfe", 0x0ef0f110, NULL
, NULL
, FPU_ALL
, do_fp_cmp
},
625 {"flt", 0x0e000110, "sde", round_flags
, FPU_ALL
, do_fp_from_reg
},
626 {"fix", 0x0e100110, NULL
, fix_flags
, FPU_ALL
, do_fp_to_reg
},
628 /* Generic copressor instructions */
629 {"cdp", 0x0e000000, NULL
, NULL
, ARM_2UP
, do_cdp
},
630 {"ldc", 0x0c100000, NULL
, cplong_flag
, ARM_2UP
, do_lstc
},
631 {"stc", 0x0c000000, NULL
, cplong_flag
, ARM_2UP
, do_lstc
},
632 {"mcr", 0x0e000010, NULL
, NULL
, ARM_2UP
, do_co_reg
},
633 {"mrc", 0x0e100010, NULL
, NULL
, ARM_2UP
, do_co_reg
},
636 /* defines for various bits that we will want to toggle */
638 #define INST_IMMEDIATE 0x02000000
639 #define OFFSET_REG 0x02000000
640 #define HWOFFSET_IMM 0x00400000
641 #define SHIFT_BY_REG 0x00000010
642 #define PRE_INDEX 0x01000000
643 #define INDEX_UP 0x00800000
644 #define WRITE_BACK 0x00200000
645 #define LDM_TYPE_2_OR_3 0x00400000
647 #define LITERAL_MASK 0xf000f000
648 #define COND_MASK 0xf0000000
649 #define OPCODE_MASK 0xfe1fffff
650 #define DATA_OP_SHIFT 21
652 /* Codes to distinguish the arithmetic instructions */
664 #define OPCODE_CMP 10
665 #define OPCODE_CMN 11
666 #define OPCODE_ORR 12
667 #define OPCODE_MOV 13
668 #define OPCODE_BIC 14
669 #define OPCODE_MVN 15
671 static void do_t_nop
PARAMS ((char *));
672 static void do_t_arit
PARAMS ((char *));
673 static void do_t_add
PARAMS ((char *));
674 static void do_t_asr
PARAMS ((char *));
675 static void do_t_branch9
PARAMS ((char *));
676 static void do_t_branch12
PARAMS ((char *));
677 static void do_t_branch23
PARAMS ((char *));
678 static void do_t_bx
PARAMS ((char *));
679 static void do_t_compare
PARAMS ((char *));
680 static void do_t_ldmstm
PARAMS ((char *));
681 static void do_t_ldr
PARAMS ((char *));
682 static void do_t_ldrb
PARAMS ((char *));
683 static void do_t_ldrh
PARAMS ((char *));
684 static void do_t_lds
PARAMS ((char *));
685 static void do_t_lsl
PARAMS ((char *));
686 static void do_t_lsr
PARAMS ((char *));
687 static void do_t_mov
PARAMS ((char *));
688 static void do_t_push_pop
PARAMS ((char *));
689 static void do_t_str
PARAMS ((char *));
690 static void do_t_strb
PARAMS ((char *));
691 static void do_t_strh
PARAMS ((char *));
692 static void do_t_sub
PARAMS ((char *));
693 static void do_t_swi
PARAMS ((char *));
694 static void do_t_adr
PARAMS ((char *));
696 #define T_OPCODE_MUL 0x4340
697 #define T_OPCODE_TST 0x4200
698 #define T_OPCODE_CMN 0x42c0
699 #define T_OPCODE_NEG 0x4240
700 #define T_OPCODE_MVN 0x43c0
702 #define T_OPCODE_ADD_R3 0x1800
703 #define T_OPCODE_SUB_R3 0x1a00
704 #define T_OPCODE_ADD_HI 0x4400
705 #define T_OPCODE_ADD_ST 0xb000
706 #define T_OPCODE_SUB_ST 0xb080
707 #define T_OPCODE_ADD_SP 0xa800
708 #define T_OPCODE_ADD_PC 0xa000
709 #define T_OPCODE_ADD_I8 0x3000
710 #define T_OPCODE_SUB_I8 0x3800
711 #define T_OPCODE_ADD_I3 0x1c00
712 #define T_OPCODE_SUB_I3 0x1e00
714 #define T_OPCODE_ASR_R 0x4100
715 #define T_OPCODE_LSL_R 0x4080
716 #define T_OPCODE_LSR_R 0x40c0
717 #define T_OPCODE_ASR_I 0x1000
718 #define T_OPCODE_LSL_I 0x0000
719 #define T_OPCODE_LSR_I 0x0800
721 #define T_OPCODE_MOV_I8 0x2000
722 #define T_OPCODE_CMP_I8 0x2800
723 #define T_OPCODE_CMP_LR 0x4280
724 #define T_OPCODE_MOV_HR 0x4600
725 #define T_OPCODE_CMP_HR 0x4500
727 #define T_OPCODE_LDR_PC 0x4800
728 #define T_OPCODE_LDR_SP 0x9800
729 #define T_OPCODE_STR_SP 0x9000
730 #define T_OPCODE_LDR_IW 0x6800
731 #define T_OPCODE_STR_IW 0x6000
732 #define T_OPCODE_LDR_IH 0x8800
733 #define T_OPCODE_STR_IH 0x8000
734 #define T_OPCODE_LDR_IB 0x7800
735 #define T_OPCODE_STR_IB 0x7000
736 #define T_OPCODE_LDR_RW 0x5800
737 #define T_OPCODE_STR_RW 0x5000
738 #define T_OPCODE_LDR_RH 0x5a00
739 #define T_OPCODE_STR_RH 0x5200
740 #define T_OPCODE_LDR_RB 0x5c00
741 #define T_OPCODE_STR_RB 0x5400
743 #define T_OPCODE_PUSH 0xb400
744 #define T_OPCODE_POP 0xbc00
746 #define T_OPCODE_BRANCH 0xe7fe
748 static int thumb_reg
PARAMS ((char ** str
, int hi_lo
));
750 #define THUMB_SIZE 2 /* Size of thumb instruction */
751 #define THUMB_REG_LO 0x1
752 #define THUMB_REG_HI 0x2
753 #define THUMB_REG_ANY 0x3
755 #define THUMB_H1 0x0080
756 #define THUMB_H2 0x0040
763 #define THUMB_COMPARE 1
766 #define THUMB_STORE 1
768 #define THUMB_PP_PC_LR 0x0100
770 /* These three are used for immediate shifts, do not alter */
772 #define THUMB_HALFWORD 1
777 CONST
char * template; /* Basic string to match */
778 unsigned long value
; /* Basic instruction code */
780 unsigned long variants
; /* Which CPU variants this exists for */
781 void (* parms
) PARAMS ((char *)); /* Function to call to parse args */
784 static CONST
struct thumb_opcode tinsns
[] =
786 {"adc", 0x4140, 2, ARM_THUMB
, do_t_arit
},
787 {"add", 0x0000, 2, ARM_THUMB
, do_t_add
},
788 {"and", 0x4000, 2, ARM_THUMB
, do_t_arit
},
789 {"asr", 0x0000, 2, ARM_THUMB
, do_t_asr
},
790 {"b", T_OPCODE_BRANCH
, 2, ARM_THUMB
, do_t_branch12
},
791 {"beq", 0xd0fe, 2, ARM_THUMB
, do_t_branch9
},
792 {"bne", 0xd1fe, 2, ARM_THUMB
, do_t_branch9
},
793 {"bcs", 0xd2fe, 2, ARM_THUMB
, do_t_branch9
},
794 {"bhs", 0xd2fe, 2, ARM_THUMB
, do_t_branch9
},
795 {"bcc", 0xd3fe, 2, ARM_THUMB
, do_t_branch9
},
796 {"bul", 0xd3fe, 2, ARM_THUMB
, do_t_branch9
},
797 {"blo", 0xd3fe, 2, ARM_THUMB
, do_t_branch9
},
798 {"bmi", 0xd4fe, 2, ARM_THUMB
, do_t_branch9
},
799 {"bpl", 0xd5fe, 2, ARM_THUMB
, do_t_branch9
},
800 {"bvs", 0xd6fe, 2, ARM_THUMB
, do_t_branch9
},
801 {"bvc", 0xd7fe, 2, ARM_THUMB
, do_t_branch9
},
802 {"bhi", 0xd8fe, 2, ARM_THUMB
, do_t_branch9
},
803 {"bls", 0xd9fe, 2, ARM_THUMB
, do_t_branch9
},
804 {"bge", 0xdafe, 2, ARM_THUMB
, do_t_branch9
},
805 {"blt", 0xdbfe, 2, ARM_THUMB
, do_t_branch9
},
806 {"bgt", 0xdcfe, 2, ARM_THUMB
, do_t_branch9
},
807 {"ble", 0xddfe, 2, ARM_THUMB
, do_t_branch9
},
808 {"bic", 0x4380, 2, ARM_THUMB
, do_t_arit
},
809 {"bl", 0xf7fffffe, 4, ARM_THUMB
, do_t_branch23
},
810 {"bx", 0x4700, 2, ARM_THUMB
, do_t_bx
},
811 {"cmn", T_OPCODE_CMN
, 2, ARM_THUMB
, do_t_arit
},
812 {"cmp", 0x0000, 2, ARM_THUMB
, do_t_compare
},
813 {"eor", 0x4040, 2, ARM_THUMB
, do_t_arit
},
814 {"ldmia", 0xc800, 2, ARM_THUMB
, do_t_ldmstm
},
815 {"ldr", 0x0000, 2, ARM_THUMB
, do_t_ldr
},
816 {"ldrb", 0x0000, 2, ARM_THUMB
, do_t_ldrb
},
817 {"ldrh", 0x0000, 2, ARM_THUMB
, do_t_ldrh
},
818 {"ldrsb", 0x5600, 2, ARM_THUMB
, do_t_lds
},
819 {"ldrsh", 0x5e00, 2, ARM_THUMB
, do_t_lds
},
820 {"ldsb", 0x5600, 2, ARM_THUMB
, do_t_lds
},
821 {"ldsh", 0x5e00, 2, ARM_THUMB
, do_t_lds
},
822 {"lsl", 0x0000, 2, ARM_THUMB
, do_t_lsl
},
823 {"lsr", 0x0000, 2, ARM_THUMB
, do_t_lsr
},
824 {"mov", 0x0000, 2, ARM_THUMB
, do_t_mov
},
825 {"mul", T_OPCODE_MUL
, 2, ARM_THUMB
, do_t_arit
},
826 {"mvn", T_OPCODE_MVN
, 2, ARM_THUMB
, do_t_arit
},
827 {"neg", T_OPCODE_NEG
, 2, ARM_THUMB
, do_t_arit
},
828 {"orr", 0x4300, 2, ARM_THUMB
, do_t_arit
},
829 {"pop", 0xbc00, 2, ARM_THUMB
, do_t_push_pop
},
830 {"push", 0xb400, 2, ARM_THUMB
, do_t_push_pop
},
831 {"ror", 0x41c0, 2, ARM_THUMB
, do_t_arit
},
832 {"sbc", 0x4180, 2, ARM_THUMB
, do_t_arit
},
833 {"stmia", 0xc000, 2, ARM_THUMB
, do_t_ldmstm
},
834 {"str", 0x0000, 2, ARM_THUMB
, do_t_str
},
835 {"strb", 0x0000, 2, ARM_THUMB
, do_t_strb
},
836 {"strh", 0x0000, 2, ARM_THUMB
, do_t_strh
},
837 {"swi", 0xdf00, 2, ARM_THUMB
, do_t_swi
},
838 {"sub", 0x0000, 2, ARM_THUMB
, do_t_sub
},
839 {"tst", T_OPCODE_TST
, 2, ARM_THUMB
, do_t_arit
},
841 {"adr", 0x0000, 2, ARM_THUMB
, do_t_adr
},
842 {"nop", 0x46C0, 2, ARM_THUMB
, do_t_nop
}, /* mov r8,r8 */
851 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
852 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
853 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
859 /* These are the standard names; Users can add aliases with .req */
860 static CONST
struct reg_entry reg_table
[] =
862 /* Processor Register Numbers */
863 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
864 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
865 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
866 {"r12", 12}, {"r13", REG_SP
},{"r14", REG_LR
},{"r15", REG_PC
},
867 /* APCS conventions */
868 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
869 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
870 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
871 {"fp", 11}, {"ip", 12}, {"sp", REG_SP
},{"lr", REG_LR
},{"pc", REG_PC
},
873 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
874 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
875 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
876 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
877 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
878 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
879 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
880 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
881 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
882 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
886 #define BAD_ARGS _("Bad arguments to instruction")
887 #define BAD_PC _("r15 not allowed here")
888 #define BAD_FLAGS _("Instruction should not have flags")
889 #define BAD_COND _("Instruction is not conditional")
891 static struct hash_control
* arm_ops_hsh
= NULL
;
892 static struct hash_control
* arm_tops_hsh
= NULL
;
893 static struct hash_control
* arm_cond_hsh
= NULL
;
894 static struct hash_control
* arm_shift_hsh
= NULL
;
895 static struct hash_control
* arm_reg_hsh
= NULL
;
896 static struct hash_control
* arm_psr_hsh
= NULL
;
898 /* This table describes all the machine specific pseudo-ops the assembler
899 has to support. The fields are:
900 pseudo-op name without dot
901 function to call to execute this pseudo-op
902 Integer arg to pass to the function
905 static void s_req
PARAMS ((int));
906 static void s_align
PARAMS ((int));
907 static void s_bss
PARAMS ((int));
908 static void s_even
PARAMS ((int));
909 static void s_ltorg
PARAMS ((int));
910 static void s_arm
PARAMS ((int));
911 static void s_thumb
PARAMS ((int));
912 static void s_code
PARAMS ((int));
913 static void s_force_thumb
PARAMS ((int));
914 static void s_thumb_func
PARAMS ((int));
915 static void s_thumb_set
PARAMS ((int));
916 static void arm_s_text
PARAMS ((int));
917 static void arm_s_data
PARAMS ((int));
919 static void arm_s_section
PARAMS ((int));
920 static void s_arm_elf_cons
PARAMS ((int));
923 static int my_get_expression
PARAMS ((expressionS
*, char **));
925 CONST pseudo_typeS md_pseudo_table
[] =
927 { "req", s_req
, 0 }, /* Never called becasue '.req' does not start line */
929 { "align", s_align
, 0 },
931 { "thumb", s_thumb
, 0 },
932 { "code", s_code
, 0 },
933 { "force_thumb", s_force_thumb
, 0 },
934 { "thumb_func", s_thumb_func
, 0 },
935 { "thumb_set", s_thumb_set
, 0 },
936 { "even", s_even
, 0 },
937 { "ltorg", s_ltorg
, 0 },
938 { "pool", s_ltorg
, 0 },
939 /* Allow for the effect of section changes. */
940 { "text", arm_s_text
, 0 },
941 { "data", arm_s_data
, 0 },
943 { "section", arm_s_section
, 0 },
944 { "section.s", arm_s_section
, 0 },
945 { "sect", arm_s_section
, 0 },
946 { "sect.s", arm_s_section
, 0 },
947 { "word", s_arm_elf_cons
, 4 },
948 { "long", s_arm_elf_cons
, 4 },
952 { "extend", float_cons
, 'x' },
953 { "ldouble", float_cons
, 'x' },
954 { "packed", float_cons
, 'p' },
958 /* Stuff needed to resolve the label ambiguity
968 symbolS
* last_label_seen
;
969 static int label_is_thumb_function_name
= false;
973 #define MAX_LITERAL_POOL_SIZE 1024
975 typedef struct literalS
977 struct expressionS exp
;
978 struct arm_it
* inst
;
981 literalT literals
[MAX_LITERAL_POOL_SIZE
];
982 int next_literal_pool_place
= 0; /* Next free entry in the pool */
983 int lit_pool_num
= 1; /* Next literal pool number */
984 symbolS
* current_poolP
= NULL
;
991 if (current_poolP
== NULL
)
992 current_poolP
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
993 (valueT
) 0, &zero_address_frag
);
995 /* Check if this literal value is already in the pool: */
996 while (lit_count
< next_literal_pool_place
)
998 if (literals
[lit_count
].exp
.X_op
== inst
.reloc
.exp
.X_op
999 && inst
.reloc
.exp
.X_op
== O_constant
1000 && literals
[lit_count
].exp
.X_add_number
== inst
.reloc
.exp
.X_add_number
1001 && literals
[lit_count
].exp
.X_unsigned
== inst
.reloc
.exp
.X_unsigned
)
1006 if (lit_count
== next_literal_pool_place
) /* new entry */
1008 if (next_literal_pool_place
> MAX_LITERAL_POOL_SIZE
)
1010 inst
.error
= _("Literal Pool Overflow");
1014 literals
[next_literal_pool_place
].exp
= inst
.reloc
.exp
;
1015 lit_count
= next_literal_pool_place
++;
1018 inst
.reloc
.exp
.X_op
= O_symbol
;
1019 inst
.reloc
.exp
.X_add_number
= (lit_count
) * 4 - 8;
1020 inst
.reloc
.exp
.X_add_symbol
= current_poolP
;
1025 /* Can't use symbol_new here, so have to create a symbol and then at
1026 a later date assign it a value. Thats what these functions do. */
1028 symbol_locate (symbolP
, name
, segment
, valu
, frag
)
1030 CONST
char * name
; /* It is copied, the caller can modify */
1031 segT segment
; /* Segment identifier (SEG_<something>) */
1032 valueT valu
; /* Symbol value */
1033 fragS
* frag
; /* Associated fragment */
1035 unsigned int name_length
;
1036 char * preserved_copy_of_name
;
1038 name_length
= strlen (name
) + 1; /* +1 for \0 */
1039 obstack_grow (¬es
, name
, name_length
);
1040 preserved_copy_of_name
= obstack_finish (¬es
);
1041 #ifdef STRIP_UNDERSCORE
1042 if (preserved_copy_of_name
[0] == '_')
1043 preserved_copy_of_name
++;
1046 #ifdef tc_canonicalize_symbol_name
1047 preserved_copy_of_name
=
1048 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1051 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1053 S_SET_SEGMENT (symbolP
, segment
);
1054 S_SET_VALUE (symbolP
, valu
);
1055 symbol_clear_list_pointers(symbolP
);
1057 symbol_set_frag (symbolP
, frag
);
1059 /* Link to end of symbol chain. */
1061 extern int symbol_table_frozen
;
1062 if (symbol_table_frozen
)
1066 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
1068 obj_symbol_new_hook (symbolP
);
1070 #ifdef tc_symbol_new_hook
1071 tc_symbol_new_hook (symbolP
);
1075 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1076 #endif /* DEBUG_SYMS */
1079 /* Check that an immediate is valid, and if so, convert it to the right format. */
1082 validate_immediate (val
)
1088 #define rotate_left(v, n) (v << n | v >> (32 - n))
1090 for (i
= 0; i
< 32; i
+= 2)
1091 if ((a
= rotate_left (val
, i
)) <= 0xff)
1092 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const] */
1097 /* Check to see if an immediate can be computed as two seperate immediate
1098 values, added together. We already know that this value cannot be
1099 computed by just one ARM instruction. */
1102 validate_immediate_twopart (val
, highpart
)
1104 unsigned int * highpart
;
1109 for (i
= 0; i
< 32; i
+= 2)
1110 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
1116 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
1118 else if (a
& 0xff0000)
1123 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
1127 assert (a
& 0xff000000);
1129 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
1132 return (a
& 0xff) | (i
<< 7);
1139 validate_offset_imm (val
, hwse
)
1143 if ((hwse
&& val
> 255) || val
> 4095)
1153 as_bad (_("Invalid syntax for .req directive."));
1160 /* We don't support putting frags in the BSS segment, we fake it by
1161 marking in_bss, then looking at s_skip for clues?.. */
1162 subseg_set (bss_section
, 0);
1163 demand_empty_rest_of_line ();
1170 if (!need_pass_2
) /* Never make frag if expect extra pass. */
1171 frag_align (1, 0, 0);
1173 record_alignment (now_seg
, 1);
1175 demand_empty_rest_of_line ();
1185 if (current_poolP
== NULL
)
1188 /* Align pool as you have word accesses */
1189 /* Only make a frag if we have to ... */
1191 frag_align (2, 0, 0);
1193 record_alignment (now_seg
, 2);
1195 sprintf (sym_name
, "$$lit_\002%x", lit_pool_num
++);
1197 symbol_locate (current_poolP
, sym_name
, now_seg
,
1198 (valueT
) frag_now_fix (), frag_now
);
1199 symbol_table_insert (current_poolP
);
1201 ARM_SET_THUMB (current_poolP
, thumb_mode
);
1203 #if defined OBJ_COFF || defined OBJ_ELF
1204 ARM_SET_INTERWORK (current_poolP
, support_interwork
);
1207 while (lit_count
< next_literal_pool_place
)
1208 /* First output the expression in the instruction to the pool */
1209 emit_expr (&(literals
[lit_count
++].exp
), 4); /* .word */
1211 next_literal_pool_place
= 0;
1212 current_poolP
= NULL
;
1216 s_align (unused
) /* Same as s_align_ptwo but align 0 => align 2 */
1220 register long temp_fill
;
1221 long max_alignment
= 15;
1223 temp
= get_absolute_expression ();
1224 if (temp
> max_alignment
)
1225 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
1228 as_bad (_("Alignment negative. 0 assumed."));
1232 if (*input_line_pointer
== ',')
1234 input_line_pointer
++;
1235 temp_fill
= get_absolute_expression ();
1243 /* Only make a frag if we HAVE to. . . */
1244 if (temp
&& !need_pass_2
)
1245 frag_align (temp
, (int) temp_fill
, 0);
1246 demand_empty_rest_of_line ();
1248 record_alignment (now_seg
, temp
);
1252 s_force_thumb (ignore
)
1255 /* If we are not already in thumb mode go into it, EVEN if
1256 the target processor does not support thumb instructions.
1257 This is used by gcc/config/arm/lib1funcs.asm for example
1258 to compile interworking support functions even if the
1259 target processor should not support interworking. */
1265 record_alignment (now_seg
, 1);
1268 demand_empty_rest_of_line ();
1272 s_thumb_func (ignore
)
1275 /* The following label is the name/address of the start of a Thumb function.
1276 We need to know this for the interworking support. */
1278 label_is_thumb_function_name
= true;
1280 demand_empty_rest_of_line ();
1283 /* Perform a .set directive, but also mark the alias as
1284 being a thumb function. */
1290 /* XXX the following is a duplicate of the code for s_set() in read.c
1291 We cannot just call that code as we need to get at the symbol that
1293 register char * name
;
1294 register char delim
;
1295 register char * end_name
;
1296 register symbolS
* symbolP
;
1299 * Especial apologies for the random logic:
1300 * this just grew, and could be parsed much more simply!
1303 name
= input_line_pointer
;
1304 delim
= get_symbol_end ();
1305 end_name
= input_line_pointer
;
1310 if (*input_line_pointer
!= ',')
1313 as_bad (_("Expected comma after name \"%s\""), name
);
1315 ignore_rest_of_line ();
1319 input_line_pointer
++;
1322 if (name
[0] == '.' && name
[1] == '\0')
1324 /* XXX - this should not happen to .thumb_set */
1328 if ((symbolP
= symbol_find (name
)) == NULL
1329 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
1332 /* When doing symbol listings, play games with dummy fragments living
1333 outside the normal fragment chain to record the file and line info
1335 if (listing
& LISTING_SYMBOLS
)
1337 extern struct list_info_struct
* listing_tail
;
1338 fragS
* dummy_frag
= (fragS
*) xmalloc (sizeof(fragS
));
1339 memset (dummy_frag
, 0, sizeof(fragS
));
1340 dummy_frag
->fr_type
= rs_fill
;
1341 dummy_frag
->line
= listing_tail
;
1342 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
1343 dummy_frag
->fr_symbol
= symbolP
;
1347 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
1350 /* "set" symbols are local unless otherwise specified. */
1351 SF_SET_LOCAL (symbolP
);
1352 #endif /* OBJ_COFF */
1353 } /* make a new symbol */
1355 symbol_table_insert (symbolP
);
1360 && S_IS_DEFINED (symbolP
)
1361 && S_GET_SEGMENT (symbolP
) != reg_section
)
1362 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
1364 pseudo_set (symbolP
);
1366 demand_empty_rest_of_line ();
1368 /* XXX Now we come to the Thumb specific bit of code. */
1370 THUMB_SET_FUNC (symbolP
, 1);
1371 ARM_SET_THUMB (symbolP
, 1);
1372 #if defined OBJ_ELF || defined OBJ_COFF
1373 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1377 /* If we change section we must dump the literal pool first. */
1382 if (now_seg
!= text_section
)
1392 if (flag_readonly_data_in_text
)
1394 if (now_seg
!= text_section
)
1397 else if (now_seg
!= data_section
)
1405 arm_s_section (ignore
)
1410 obj_elf_section (ignore
);
1415 opcode_select (width
)
1423 if (! (cpu_variant
& ARM_THUMB
))
1424 as_bad (_("selected processor does not support THUMB opcodes"));
1426 /* No need to force the alignment, since we will have been
1427 coming from ARM mode, which is word-aligned. */
1428 record_alignment (now_seg
, 1);
1435 if ((cpu_variant
& ARM_ANY
) == ARM_THUMB
)
1436 as_bad (_("selected processor does not support ARM opcodes"));
1439 frag_align (2, 0, 0);
1440 record_alignment (now_seg
, 1);
1445 as_bad (_("invalid instruction size selected (%d)"), width
);
1454 demand_empty_rest_of_line ();
1462 demand_empty_rest_of_line ();
1471 temp
= get_absolute_expression ();
1476 opcode_select (temp
);
1480 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
1488 skip_whitespace (str
);
1491 inst
.error
= _("Garbage following instruction");
1495 skip_past_comma (str
)
1501 while ((c
= *p
) == ' ' || c
== ',')
1504 if (c
== ',' && comma
++)
1512 return comma
? SUCCESS
: FAIL
;
1515 /* A standard register must be given at this point.
1516 Shift is the place to put it in inst.instruction.
1517 Restores input start point on err.
1518 Returns the reg#, or FAIL. */
1521 reg_required_here (str
, shift
)
1525 static char buff
[128]; /* XXX */
1527 char * start
= *str
;
1529 if ((reg
= arm_reg_parse (str
)) != FAIL
&& int_register (reg
))
1532 inst
.instruction
|= reg
<< shift
;
1536 /* Restore the start point, we may have got a reg of the wrong class. */
1539 /* In the few cases where we might be able to accept something else
1540 this error can be overridden. */
1541 sprintf (buff
, _("Register expected, not '%.100s'"), start
);
1548 psr_required_here (str
, cpsr
, spsr
)
1554 char * start
= *str
;
1555 psr
= arm_psr_parse (str
);
1557 if (psr
== cpsr
|| psr
== spsr
)
1560 inst
.instruction
|= 1 << 22;
1565 /* In the few cases where we might be able to accept something else
1566 this error can be overridden. */
1567 inst
.error
= _("<psr(f)> expected");
1569 /* Restore the start point. */
1575 co_proc_number (str
)
1578 int processor
, pchar
;
1580 skip_whitespace (* str
);
1582 /* The data sheet seems to imply that just a number on its own is valid
1583 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1585 if (**str
== 'p' || **str
== 'P')
1589 if (pchar
>= '0' && pchar
<= '9')
1591 processor
= pchar
- '0';
1592 if (**str
>= '0' && **str
<= '9')
1594 processor
= processor
* 10 + *(*str
)++ - '0';
1597 inst
.error
= _("Illegal co-processor number");
1604 inst
.error
= _("Bad or missing co-processor number");
1608 inst
.instruction
|= processor
<< 8;
1613 cp_opc_expr (str
, where
, length
)
1620 skip_whitespace (* str
);
1622 memset (&expr
, '\0', sizeof (expr
));
1624 if (my_get_expression (&expr
, str
))
1626 if (expr
.X_op
!= O_constant
)
1628 inst
.error
= _("bad or missing expression");
1632 if ((expr
.X_add_number
& ((1 << length
) - 1)) != expr
.X_add_number
)
1634 inst
.error
= _("immediate co-processor expression too large");
1638 inst
.instruction
|= expr
.X_add_number
<< where
;
1643 cp_reg_required_here (str
, where
)
1648 char * start
= *str
;
1650 if ((reg
= arm_reg_parse (str
)) != FAIL
&& cp_register (reg
))
1653 inst
.instruction
|= reg
<< where
;
1657 /* In the few cases where we might be able to accept something else
1658 this error can be overridden. */
1659 inst
.error
= _("Co-processor register expected");
1661 /* Restore the start point. */
1667 fp_reg_required_here (str
, where
)
1672 char * start
= *str
;
1674 if ((reg
= arm_reg_parse (str
)) != FAIL
&& fp_register (reg
))
1677 inst
.instruction
|= reg
<< where
;
1681 /* In the few cases where we might be able to accept something else
1682 this error can be overridden. */
1683 inst
.error
= _("Floating point register expected");
1685 /* Restore the start point. */
1691 cp_address_offset (str
)
1696 skip_whitespace (* str
);
1698 if (! is_immediate_prefix (**str
))
1700 inst
.error
= _("immediate expression expected");
1706 if (my_get_expression (& inst
.reloc
.exp
, str
))
1709 if (inst
.reloc
.exp
.X_op
== O_constant
)
1711 offset
= inst
.reloc
.exp
.X_add_number
;
1715 inst
.error
= _("co-processor address must be word aligned");
1719 if (offset
> 1023 || offset
< -1023)
1721 inst
.error
= _("offset too large");
1726 inst
.instruction
|= INDEX_UP
;
1730 inst
.instruction
|= offset
>> 2;
1733 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
1739 cp_address_required_here (str
)
1751 skip_whitespace (p
);
1753 if ((reg
= reg_required_here (& p
, 16)) == FAIL
)
1756 skip_whitespace (p
);
1762 if (skip_past_comma (& p
) == SUCCESS
)
1765 write_back
= WRITE_BACK
;
1769 inst
.error
= _("pc may not be used in post-increment");
1773 if (cp_address_offset (& p
) == FAIL
)
1777 pre_inc
= PRE_INDEX
| INDEX_UP
;
1781 /* '['Rn, #expr']'[!] */
1783 if (skip_past_comma (& p
) == FAIL
)
1785 inst
.error
= _("pre-indexed expression expected");
1789 pre_inc
= PRE_INDEX
;
1791 if (cp_address_offset (& p
) == FAIL
)
1794 skip_whitespace (p
);
1798 inst
.error
= _("missing ]");
1802 skip_whitespace (p
);
1808 inst
.error
= _("pc may not be used with write-back");
1813 write_back
= WRITE_BACK
;
1819 if (my_get_expression (&inst
.reloc
.exp
, &p
))
1822 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
1823 inst
.reloc
.exp
.X_add_number
-= 8; /* PC rel adjust */
1824 inst
.reloc
.pc_rel
= 1;
1825 inst
.instruction
|= (REG_PC
<< 16);
1826 pre_inc
= PRE_INDEX
;
1829 inst
.instruction
|= write_back
| pre_inc
;
1837 unsigned long flags
;
1839 /* Do nothing really. */
1840 inst
.instruction
|= flags
; /* This is pointless. */
1848 unsigned long flags
;
1850 /* Only one syntax. */
1851 skip_whitespace (str
);
1853 if (reg_required_here (&str
, 12) == FAIL
)
1855 inst
.error
= BAD_ARGS
;
1859 if (skip_past_comma (&str
) == FAIL
1860 || psr_required_here (& str
, CPSR_ALL
, SPSR_ALL
) == FAIL
)
1862 inst
.error
= _("<psr> expected");
1866 inst
.instruction
|= flags
;
1871 /* Three possible forms: "<psr>, Rm", "<psrf>, Rm", "<psrf>, #expression". */
1875 unsigned long flags
;
1879 skip_whitespace (str
);
1881 if (psr_required_here (&str
, CPSR_ALL
, SPSR_ALL
) == SUCCESS
)
1883 inst
.instruction
|= PSR_ALL
;
1885 /* Sytax should be "<psr>, Rm" */
1886 if (skip_past_comma (&str
) == FAIL
1887 || (reg
= reg_required_here (&str
, 0)) == FAIL
)
1889 inst
.error
= BAD_ARGS
;
1895 if (psr_required_here (& str
, CPSR_FLG
, SPSR_FLG
) == SUCCESS
)
1896 inst
.instruction
|= PSR_FLAGS
;
1897 else if (psr_required_here (& str
, CPSR_CTL
, SPSR_CTL
) == SUCCESS
)
1898 inst
.instruction
|= PSR_CONTROL
;
1901 inst
.error
= BAD_ARGS
;
1905 if (skip_past_comma (&str
) == FAIL
)
1907 inst
.error
= BAD_ARGS
;
1911 /* Syntax could be "<psrf>, rm", "<psrf>, #expression" */
1913 if ((reg
= reg_required_here (& str
, 0)) != FAIL
)
1915 /* Immediate expression. */
1916 else if (is_immediate_prefix (* str
))
1921 if (my_get_expression (& inst
.reloc
.exp
, & str
))
1923 inst
.error
= _("Register or shift expression expected");
1927 if (inst
.reloc
.exp
.X_add_symbol
)
1929 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
1930 inst
.reloc
.pc_rel
= 0;
1934 unsigned value
= validate_immediate (inst
.reloc
.exp
.X_add_number
);
1937 inst
.error
= _("Invalid constant");
1941 inst
.instruction
|= value
;
1944 flags
|= INST_IMMEDIATE
;
1948 inst
.error
= _("Error: unrecognised syntax for second argument to msr instruction");
1954 inst
.instruction
|= flags
;
1959 /* Long Multiply Parser
1960 UMULL RdLo, RdHi, Rm, Rs
1961 SMULL RdLo, RdHi, Rm, Rs
1962 UMLAL RdLo, RdHi, Rm, Rs
1963 SMLAL RdLo, RdHi, Rm, Rs
1966 do_mull (str
, flags
)
1968 unsigned long flags
;
1970 int rdlo
, rdhi
, rm
, rs
;
1972 /* Only one format "rdlo, rdhi, rm, rs" */
1973 skip_whitespace (str
);
1975 if ((rdlo
= reg_required_here (&str
, 12)) == FAIL
)
1977 inst
.error
= BAD_ARGS
;
1981 if (skip_past_comma (&str
) == FAIL
1982 || (rdhi
= reg_required_here (&str
, 16)) == FAIL
)
1984 inst
.error
= BAD_ARGS
;
1988 if (skip_past_comma (&str
) == FAIL
1989 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
1991 inst
.error
= BAD_ARGS
;
1995 /* rdhi, rdlo and rm must all be different */
1996 if (rdlo
== rdhi
|| rdlo
== rm
|| rdhi
== rm
)
1997 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
1999 if (skip_past_comma (&str
) == FAIL
2000 || (rs
= reg_required_here (&str
, 8)) == FAIL
)
2002 inst
.error
= BAD_ARGS
;
2006 if (rdhi
== REG_PC
|| rdhi
== REG_PC
|| rdhi
== REG_PC
|| rdhi
== REG_PC
)
2008 inst
.error
= BAD_PC
;
2012 inst
.instruction
|= flags
;
2020 unsigned long flags
;
2024 /* Only one format "rd, rm, rs" */
2025 skip_whitespace (str
);
2027 if ((rd
= reg_required_here (&str
, 16)) == FAIL
)
2029 inst
.error
= BAD_ARGS
;
2035 inst
.error
= BAD_PC
;
2039 if (skip_past_comma (&str
) == FAIL
2040 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2042 inst
.error
= BAD_ARGS
;
2048 inst
.error
= BAD_PC
;
2053 as_tsktsk (_("rd and rm should be different in mul"));
2055 if (skip_past_comma (&str
) == FAIL
2056 || (rm
= reg_required_here (&str
, 8)) == FAIL
)
2058 inst
.error
= BAD_ARGS
;
2064 inst
.error
= BAD_PC
;
2068 inst
.instruction
|= flags
;
2076 unsigned long flags
;
2080 /* Only one format "rd, rm, rs, rn" */
2081 skip_whitespace (str
);
2083 if ((rd
= reg_required_here (&str
, 16)) == FAIL
)
2085 inst
.error
= BAD_ARGS
;
2091 inst
.error
= BAD_PC
;
2095 if (skip_past_comma (&str
) == FAIL
2096 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2098 inst
.error
= BAD_ARGS
;
2104 inst
.error
= BAD_PC
;
2109 as_tsktsk (_("rd and rm should be different in mla"));
2111 if (skip_past_comma (&str
) == FAIL
2112 || (rd
= reg_required_here (&str
, 8)) == FAIL
2113 || skip_past_comma (&str
) == FAIL
2114 || (rm
= reg_required_here (&str
, 12)) == FAIL
)
2116 inst
.error
= BAD_ARGS
;
2120 if (rd
== REG_PC
|| rm
== REG_PC
)
2122 inst
.error
= BAD_PC
;
2126 inst
.instruction
|= flags
;
2131 /* Returns the index into fp_values of a floating point number, or -1 if
2132 not in the table. */
2134 my_get_float_expression (str
)
2137 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2143 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
2144 /* Look for a raw floating point number */
2145 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
2146 && (is_end_of_line
[(int)(*save_in
)] || *save_in
== '\0'))
2148 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
2150 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
2152 if (words
[j
] != fp_values
[i
][j
])
2156 if (j
== MAX_LITTLENUMS
)
2164 /* Try and parse a more complex expression, this will probably fail
2165 unless the code uses a floating point prefix (eg "0f") */
2166 save_in
= input_line_pointer
;
2167 input_line_pointer
= *str
;
2168 if (expression (&exp
) == absolute_section
2169 && exp
.X_op
== O_big
2170 && exp
.X_add_number
< 0)
2172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2174 if (gen_to_words (words
, 5, (long)15) == 0)
2176 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
2178 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
2180 if (words
[j
] != fp_values
[i
][j
])
2184 if (j
== MAX_LITTLENUMS
)
2186 *str
= input_line_pointer
;
2187 input_line_pointer
= save_in
;
2194 *str
= input_line_pointer
;
2195 input_line_pointer
= save_in
;
2199 /* Return true if anything in the expression is a bignum */
2201 walk_no_bignums (sp
)
2204 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
2207 if (symbol_get_value_expression (sp
)->X_add_symbol
)
2209 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
2210 || (symbol_get_value_expression (sp
)->X_op_symbol
2211 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
2218 my_get_expression (ep
, str
)
2225 save_in
= input_line_pointer
;
2226 input_line_pointer
= *str
;
2227 seg
= expression (ep
);
2230 if (seg
!= absolute_section
2231 && seg
!= text_section
2232 && seg
!= data_section
2233 && seg
!= bss_section
2234 && seg
!= undefined_section
)
2236 inst
.error
= _("bad_segment");
2237 *str
= input_line_pointer
;
2238 input_line_pointer
= save_in
;
2243 /* Get rid of any bignums now, so that we don't generate an error for which
2244 we can't establish a line number later on. Big numbers are never valid
2245 in instructions, which is where this routine is always called. */
2246 if (ep
->X_op
== O_big
2247 || (ep
->X_add_symbol
2248 && (walk_no_bignums (ep
->X_add_symbol
)
2250 && walk_no_bignums (ep
->X_op_symbol
)))))
2252 inst
.error
= _("Invalid constant");
2253 *str
= input_line_pointer
;
2254 input_line_pointer
= save_in
;
2258 *str
= input_line_pointer
;
2259 input_line_pointer
= save_in
;
2263 /* unrestrict should be one if <shift> <register> is permitted for this
2267 decode_shift (str
, unrestrict
)
2271 struct asm_shift
* shft
;
2275 skip_whitespace (* str
);
2277 for (p
= *str
; isalpha (*p
); p
++)
2282 inst
.error
= _("Shift expression expected");
2288 shft
= (struct asm_shift
*) hash_find (arm_shift_hsh
, *str
);
2292 if (!strncmp (*str
, "rrx", 3)
2293 || !strncmp (*str
, "RRX", 3))
2296 inst
.instruction
|= shft
->value
;
2300 skip_whitespace (p
);
2302 if (unrestrict
&& reg_required_here (&p
, 8) != FAIL
)
2304 inst
.instruction
|= shft
->value
| SHIFT_BY_REG
;
2308 else if (is_immediate_prefix (* p
))
2312 if (my_get_expression (&inst
.reloc
.exp
, &p
))
2315 /* Validate some simple #expressions */
2316 if (inst
.reloc
.exp
.X_op
== O_constant
)
2318 unsigned num
= inst
.reloc
.exp
.X_add_number
;
2320 /* Reject operations greater than 32, or lsl #32 */
2321 if (num
> 32 || (num
== 32 && shft
->value
== 0))
2323 inst
.error
= _("Invalid immediate shift");
2327 /* Shifts of zero should be converted to lsl (which is zero)*/
2334 /* Shifts of 32 are encoded as 0, for those shifts that
2339 inst
.instruction
|= (num
<< 7) | shft
->value
;
2344 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
2345 inst
.reloc
.pc_rel
= 0;
2346 inst
.instruction
|= shft
->value
;
2352 inst
.error
= unrestrict
? _("shift requires register or #expression")
2353 : _("shift requires #expression");
2359 inst
.error
= _("Shift expression expected");
2363 /* Do those data_ops which can take a negative immediate constant */
2364 /* by altering the instuction. A bit of a hack really */
2368 by inverting the second operand, and
2371 by negating the second operand.
2374 negate_data_op (instruction
, value
)
2375 unsigned long * instruction
;
2376 unsigned long value
;
2379 unsigned long negated
, inverted
;
2381 negated
= validate_immediate (-value
);
2382 inverted
= validate_immediate (~value
);
2384 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
2388 case OPCODE_SUB
: /* ADD <-> SUB */
2389 new_inst
= OPCODE_ADD
;
2394 new_inst
= OPCODE_SUB
;
2398 case OPCODE_CMP
: /* CMP <-> CMN */
2399 new_inst
= OPCODE_CMN
;
2404 new_inst
= OPCODE_CMP
;
2408 /* Now Inverted ops */
2409 case OPCODE_MOV
: /* MOV <-> MVN */
2410 new_inst
= OPCODE_MVN
;
2415 new_inst
= OPCODE_MOV
;
2419 case OPCODE_AND
: /* AND <-> BIC */
2420 new_inst
= OPCODE_BIC
;
2425 new_inst
= OPCODE_AND
;
2429 case OPCODE_ADC
: /* ADC <-> SBC */
2430 new_inst
= OPCODE_SBC
;
2435 new_inst
= OPCODE_ADC
;
2439 /* We cannot do anything */
2447 *instruction
&= OPCODE_MASK
;
2448 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
2459 skip_whitespace (* str
);
2461 if (reg_required_here (str
, 0) != FAIL
)
2463 if (skip_past_comma (str
) == SUCCESS
)
2464 /* Shift operation on register. */
2465 return decode_shift (str
, NO_SHIFT_RESTRICT
);
2471 /* Immediate expression */
2472 if (is_immediate_prefix (**str
))
2477 if (my_get_expression (&inst
.reloc
.exp
, str
))
2480 if (inst
.reloc
.exp
.X_add_symbol
)
2482 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
2483 inst
.reloc
.pc_rel
= 0;
2487 if (skip_past_comma (str
) == SUCCESS
)
2489 /* #x, y -- ie explicit rotation by Y */
2490 if (my_get_expression (&expr
, str
))
2493 if (expr
.X_op
!= O_constant
)
2495 inst
.error
= _("Constant expression expected");
2499 /* Rotate must be a multiple of 2 */
2500 if (((unsigned) expr
.X_add_number
) > 30
2501 || (expr
.X_add_number
& 1) != 0
2502 || ((unsigned) inst
.reloc
.exp
.X_add_number
) > 255)
2504 inst
.error
= _("Invalid constant");
2507 inst
.instruction
|= INST_IMMEDIATE
;
2508 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
2509 inst
.instruction
|= expr
.X_add_number
<< 7;
2513 /* Implicit rotation, select a suitable one */
2514 value
= validate_immediate (inst
.reloc
.exp
.X_add_number
);
2518 /* Can't be done, perhaps the code reads something like
2519 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok */
2520 if ((value
= negate_data_op (&inst
.instruction
,
2521 inst
.reloc
.exp
.X_add_number
))
2524 inst
.error
= _("Invalid constant");
2529 inst
.instruction
|= value
;
2532 inst
.instruction
|= INST_IMMEDIATE
;
2537 inst
.error
= _("Register or shift expression expected");
2546 skip_whitespace (* str
);
2548 if (fp_reg_required_here (str
, 0) != FAIL
)
2552 /* Immediate expression */
2553 if (*((*str
)++) == '#')
2559 skip_whitespace (* str
);
2561 /* First try and match exact strings, this is to guarantee that
2562 some formats will work even for cross assembly */
2564 for (i
= 0; fp_const
[i
]; i
++)
2566 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
2570 *str
+= strlen (fp_const
[i
]);
2571 if (is_end_of_line
[(int)**str
] || **str
== '\0')
2573 inst
.instruction
|= i
+ 8;
2580 /* Just because we didn't get a match doesn't mean that the
2581 constant isn't valid, just that it is in a format that we
2582 don't automatically recognize. Try parsing it with
2583 the standard expression routines. */
2584 if ((i
= my_get_float_expression (str
)) >= 0)
2586 inst
.instruction
|= i
+ 8;
2590 inst
.error
= _("Invalid floating point immediate expression");
2593 inst
.error
= _("Floating point register or immediate expression expected");
2599 do_arit (str
, flags
)
2601 unsigned long flags
;
2603 skip_whitespace (str
);
2605 if (reg_required_here (&str
, 12) == FAIL
2606 || skip_past_comma (&str
) == FAIL
2607 || reg_required_here (&str
, 16) == FAIL
2608 || skip_past_comma (&str
) == FAIL
2609 || data_op2 (&str
) == FAIL
)
2612 inst
.error
= BAD_ARGS
;
2616 inst
.instruction
|= flags
;
2624 unsigned long flags
;
2626 /* This is a pseudo-op of the form "adr rd, label" to be converted
2627 into a relative address of the form "add rd, pc, #label-.-8" */
2629 skip_whitespace (str
);
2631 if (reg_required_here (&str
, 12) == FAIL
2632 || skip_past_comma (&str
) == FAIL
2633 || my_get_expression (&inst
.reloc
.exp
, &str
))
2636 inst
.error
= BAD_ARGS
;
2639 /* Frag hacking will turn this into a sub instruction if the offset turns
2640 out to be negative. */
2641 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
2642 inst
.reloc
.exp
.X_add_number
-= 8; /* PC relative adjust */
2643 inst
.reloc
.pc_rel
= 1;
2644 inst
.instruction
|= flags
;
2650 do_adrl (str
, flags
)
2652 unsigned long flags
;
2654 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2655 into a relative address of the form:
2656 add rd, pc, #low(label-.-8)"
2657 add rd, rd, #high(label-.-8)" */
2659 skip_whitespace (str
);
2661 if (reg_required_here (& str
, 12) == FAIL
2662 || skip_past_comma (& str
) == FAIL
2663 || my_get_expression (& inst
.reloc
.exp
, & str
))
2666 inst
.error
= BAD_ARGS
;
2672 /* Frag hacking will turn this into a sub instruction if the offset turns
2673 out to be negative. */
2674 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
2675 inst
.reloc
.exp
.X_add_number
-= 8; /* PC relative adjust */
2676 inst
.reloc
.pc_rel
= 1;
2677 inst
.instruction
|= flags
;
2678 inst
.size
= INSN_SIZE
* 2;
2686 unsigned long flags
;
2688 skip_whitespace (str
);
2690 if (reg_required_here (&str
, 16) == FAIL
)
2693 inst
.error
= BAD_ARGS
;
2697 if (skip_past_comma (&str
) == FAIL
2698 || data_op2 (&str
) == FAIL
)
2701 inst
.error
= BAD_ARGS
;
2705 inst
.instruction
|= flags
;
2706 if ((flags
& 0x0000f000) == 0)
2707 inst
.instruction
|= CONDS_BIT
;
2716 unsigned long flags
;
2718 skip_whitespace (str
);
2720 if (reg_required_here (&str
, 12) == FAIL
)
2723 inst
.error
= BAD_ARGS
;
2727 if (skip_past_comma (&str
) == FAIL
2728 || data_op2 (&str
) == FAIL
)
2731 inst
.error
= BAD_ARGS
;
2735 inst
.instruction
|= flags
;
2741 ldst_extend (str
, hwse
)
2752 if (my_get_expression (& inst
.reloc
.exp
, str
))
2755 if (inst
.reloc
.exp
.X_op
== O_constant
)
2757 int value
= inst
.reloc
.exp
.X_add_number
;
2759 if ((hwse
&& (value
< -255 || value
> 255))
2760 || (value
< -4095 || value
> 4095))
2762 inst
.error
= _("address offset too large");
2772 /* Halfword and signextension instructions have the
2773 immediate value split across bits 11..8 and bits 3..0 */
2775 inst
.instruction
|= add
| HWOFFSET_IMM
| ((value
>> 4) << 8) | (value
& 0xF);
2777 inst
.instruction
|= add
| value
;
2783 inst
.instruction
|= HWOFFSET_IMM
;
2784 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
2787 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
2788 inst
.reloc
.pc_rel
= 0;
2793 add
= 0; /* and fall through */
2795 (*str
)++; /* and fall through */
2797 if (reg_required_here (str
, 0) == FAIL
)
2801 inst
.instruction
|= add
;
2804 inst
.instruction
|= add
| OFFSET_REG
;
2805 if (skip_past_comma (str
) == SUCCESS
)
2806 return decode_shift (str
, SHIFT_RESTRICT
);
2814 do_ldst (str
, flags
)
2816 unsigned long flags
;
2823 /* This is not ideal, but it is the simplest way of dealing with the
2824 ARM7T halfword instructions (since they use a different
2825 encoding, but the same mnemonic): */
2826 halfword
= (flags
& 0x80000000) != 0;
2829 /* This is actually a load/store of a halfword, or a
2830 signed-extension load */
2831 if ((cpu_variant
& ARM_HALFWORD
) == 0)
2834 = _("Processor does not support halfwords or signed bytes");
2838 inst
.instruction
= (inst
.instruction
& COND_MASK
)
2839 | (flags
& ~COND_MASK
);
2844 skip_whitespace (str
);
2846 if ((conflict_reg
= reg_required_here (& str
, 12)) == FAIL
)
2849 inst
.error
= BAD_ARGS
;
2853 if (skip_past_comma (& str
) == FAIL
)
2855 inst
.error
= _("Address expected");
2865 skip_whitespace (str
);
2867 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
2870 /* Conflicts can occur on stores as well as loads. */
2871 conflict_reg
= (conflict_reg
== reg
);
2873 skip_whitespace (str
);
2879 if (skip_past_comma (&str
) == SUCCESS
)
2881 /* [Rn],... (post inc) */
2882 if (ldst_extend (&str
, halfword
) == FAIL
)
2885 as_warn (_("%s register same as write-back base"),
2886 (inst
.instruction
& LOAD_BIT
) ? _("destination") : _("source") );
2892 inst
.instruction
|= HWOFFSET_IMM
;
2894 skip_whitespace (str
);
2899 as_warn (_("%s register same as write-back base"),
2900 (inst
.instruction
& LOAD_BIT
) ? _("destination") : _("source") );
2902 inst
.instruction
|= WRITE_BACK
;
2906 if (! (flags
& TRANS_BIT
))
2913 if (skip_past_comma (&str
) == FAIL
)
2915 inst
.error
= _("pre-indexed expression expected");
2920 if (ldst_extend (&str
, halfword
) == FAIL
)
2923 skip_whitespace (str
);
2927 inst
.error
= _("missing ]");
2931 skip_whitespace (str
);
2936 as_warn (_("%s register same as write-back base"),
2937 (inst
.instruction
& LOAD_BIT
) ? _("destination") : _("source") );
2939 inst
.instruction
|= WRITE_BACK
;
2943 else if (*str
== '=')
2945 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
2948 skip_whitespace (str
);
2950 if (my_get_expression (&inst
.reloc
.exp
, &str
))
2953 if (inst
.reloc
.exp
.X_op
!= O_constant
2954 && inst
.reloc
.exp
.X_op
!= O_symbol
)
2956 inst
.error
= _("Constant expression expected");
2960 if (inst
.reloc
.exp
.X_op
== O_constant
2961 && (value
= validate_immediate(inst
.reloc
.exp
.X_add_number
)) != FAIL
)
2963 /* This can be done with a mov instruction */
2964 inst
.instruction
&= LITERAL_MASK
;
2965 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
2966 inst
.instruction
|= (flags
& COND_MASK
) | (value
& 0xfff);
2972 /* Insert into literal pool */
2973 if (add_to_lit_pool () == FAIL
)
2976 inst
.error
= _("literal pool insertion failed");
2980 /* Change the instruction exp to point to the pool */
2983 inst
.instruction
|= HWOFFSET_IMM
;
2984 inst
.reloc
.type
= BFD_RELOC_ARM_HWLITERAL
;
2987 inst
.reloc
.type
= BFD_RELOC_ARM_LITERAL
;
2988 inst
.reloc
.pc_rel
= 1;
2989 inst
.instruction
|= (REG_PC
<< 16);
2995 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3000 inst
.instruction
|= HWOFFSET_IMM
;
3001 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
3004 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
3005 inst
.reloc
.exp
.X_add_number
-= 8; /* PC rel adjust */
3006 inst
.reloc
.pc_rel
= 1;
3007 inst
.instruction
|= (REG_PC
<< 16);
3011 if (pre_inc
&& (flags
& TRANS_BIT
))
3012 inst
.error
= _("Pre-increment instruction with translate");
3014 inst
.instruction
|= flags
| (pre_inc
? PRE_INDEX
: 0);
3027 /* We come back here if we get ranges concatenated by '+' or '|' */
3042 skip_whitespace (str
);
3044 if ((reg
= reg_required_here (& str
, -1)) == FAIL
)
3053 inst
.error
= _("Bad range in register list");
3057 for (i
= cur_reg
+ 1; i
< reg
; i
++)
3059 if (range
& (1 << i
))
3061 (_("Warning: Duplicated register (r%d) in register list"),
3069 if (range
& (1 << reg
))
3070 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3072 else if (reg
<= cur_reg
)
3073 as_tsktsk (_("Warning: Register range not in ascending order"));
3077 } while (skip_past_comma (&str
) != FAIL
3078 || (in_range
= 1, *str
++ == '-'));
3080 skip_whitespace (str
);
3084 inst
.error
= _("Missing `}'");
3092 if (my_get_expression (&expr
, &str
))
3095 if (expr
.X_op
== O_constant
)
3097 if (expr
.X_add_number
3098 != (expr
.X_add_number
& 0x0000ffff))
3100 inst
.error
= _("invalid register mask");
3104 if ((range
& expr
.X_add_number
) != 0)
3106 int regno
= range
& expr
.X_add_number
;
3109 regno
= (1 << regno
) - 1;
3111 (_("Warning: Duplicated register (r%d) in register list"),
3115 range
|= expr
.X_add_number
;
3119 if (inst
.reloc
.type
!= 0)
3121 inst
.error
= _("expression too complex");
3125 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
3126 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
3127 inst
.reloc
.pc_rel
= 0;
3131 skip_whitespace (str
);
3133 if (*str
== '|' || *str
== '+')
3138 } while (another_range
);
3145 do_ldmstm (str
, flags
)
3147 unsigned long flags
;
3152 skip_whitespace (str
);
3154 if ((base_reg
= reg_required_here (&str
, 16)) == FAIL
)
3157 if (base_reg
== REG_PC
)
3159 inst
.error
= _("r15 not allowed as base register");
3163 skip_whitespace (str
);
3167 flags
|= WRITE_BACK
;
3171 if (skip_past_comma (&str
) == FAIL
3172 || (range
= reg_list (&str
)) == FAIL
)
3175 inst
.error
= BAD_ARGS
;
3182 flags
|= LDM_TYPE_2_OR_3
;
3185 inst
.instruction
|= flags
| range
;
3193 unsigned long flags
;
3195 skip_whitespace (str
);
3197 /* Allow optional leading '#'. */
3198 if (is_immediate_prefix (*str
))
3201 if (my_get_expression (& inst
.reloc
.exp
, & str
))
3204 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
3205 inst
.reloc
.pc_rel
= 0;
3206 inst
.instruction
|= flags
;
3214 do_swap (str
, flags
)
3216 unsigned long flags
;
3220 skip_whitespace (str
);
3222 if ((reg
= reg_required_here (&str
, 12)) == FAIL
)
3227 inst
.error
= _("r15 not allowed in swap");
3231 if (skip_past_comma (&str
) == FAIL
3232 || (reg
= reg_required_here (&str
, 0)) == FAIL
)
3235 inst
.error
= BAD_ARGS
;
3241 inst
.error
= _("r15 not allowed in swap");
3245 if (skip_past_comma (&str
) == FAIL
3248 inst
.error
= BAD_ARGS
;
3252 skip_whitespace (str
);
3254 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
3259 inst
.error
= BAD_PC
;
3263 skip_whitespace (str
);
3267 inst
.error
= _("missing ]");
3271 inst
.instruction
|= flags
;
3277 do_branch (str
, flags
)
3279 unsigned long flags
;
3281 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3288 /* ScottB: February 5, 1998 */
3289 /* Check to see of PLT32 reloc required for the instruction. */
3291 /* arm_parse_reloc() works on input_line_pointer.
3292 We actually want to parse the operands to the branch instruction
3293 passed in 'str'. Save the input pointer and restore it later. */
3294 save_in
= input_line_pointer
;
3295 input_line_pointer
= str
;
3296 if (inst
.reloc
.exp
.X_op
== O_symbol
3298 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32
)
3300 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
3301 inst
.reloc
.pc_rel
= 0;
3302 /* Modify str to point to after parsed operands, otherwise
3303 end_of_line() will complain about the (PLT) left in str. */
3304 str
= input_line_pointer
;
3308 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BRANCH
;
3309 inst
.reloc
.pc_rel
= 1;
3311 input_line_pointer
= save_in
;
3314 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BRANCH
;
3315 inst
.reloc
.pc_rel
= 1;
3316 #endif /* OBJ_ELF */
3325 unsigned long flags
;
3329 skip_whitespace (str
);
3331 if ((reg
= reg_required_here (&str
, 0)) == FAIL
)
3333 inst
.error
= BAD_ARGS
;
3338 inst
.error
= BAD_PC
;
3346 unsigned long flags
;
3348 /* Co-processor data operation.
3349 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3350 skip_whitespace (str
);
3352 if (co_proc_number (&str
) == FAIL
)
3355 inst
.error
= BAD_ARGS
;
3359 if (skip_past_comma (&str
) == FAIL
3360 || cp_opc_expr (&str
, 20,4) == FAIL
)
3363 inst
.error
= BAD_ARGS
;
3367 if (skip_past_comma (&str
) == FAIL
3368 || cp_reg_required_here (&str
, 12) == FAIL
)
3371 inst
.error
= BAD_ARGS
;
3375 if (skip_past_comma (&str
) == FAIL
3376 || cp_reg_required_here (&str
, 16) == FAIL
)
3379 inst
.error
= BAD_ARGS
;
3383 if (skip_past_comma (&str
) == FAIL
3384 || cp_reg_required_here (&str
, 0) == FAIL
)
3387 inst
.error
= BAD_ARGS
;
3391 if (skip_past_comma (&str
) == SUCCESS
)
3393 if (cp_opc_expr (&str
, 5, 3) == FAIL
)
3396 inst
.error
= BAD_ARGS
;
3406 do_lstc (str
, flags
)
3408 unsigned long flags
;
3410 /* Co-processor register load/store.
3411 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3413 skip_whitespace (str
);
3415 if (co_proc_number (&str
) == FAIL
)
3418 inst
.error
= BAD_ARGS
;
3422 if (skip_past_comma (&str
) == FAIL
3423 || cp_reg_required_here (&str
, 12) == FAIL
)
3426 inst
.error
= BAD_ARGS
;
3430 if (skip_past_comma (&str
) == FAIL
3431 || cp_address_required_here (&str
) == FAIL
)
3434 inst
.error
= BAD_ARGS
;
3438 inst
.instruction
|= flags
;
3444 do_co_reg (str
, flags
)
3446 unsigned long flags
;
3448 /* Co-processor register transfer.
3449 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3451 skip_whitespace (str
);
3453 if (co_proc_number (&str
) == FAIL
)
3456 inst
.error
= BAD_ARGS
;
3460 if (skip_past_comma (&str
) == FAIL
3461 || cp_opc_expr (&str
, 21, 3) == FAIL
)
3464 inst
.error
= BAD_ARGS
;
3468 if (skip_past_comma (&str
) == FAIL
3469 || reg_required_here (&str
, 12) == FAIL
)
3472 inst
.error
= BAD_ARGS
;
3476 if (skip_past_comma (&str
) == FAIL
3477 || cp_reg_required_here (&str
, 16) == FAIL
)
3480 inst
.error
= BAD_ARGS
;
3484 if (skip_past_comma (&str
) == FAIL
3485 || cp_reg_required_here (&str
, 0) == FAIL
)
3488 inst
.error
= BAD_ARGS
;
3492 if (skip_past_comma (&str
) == SUCCESS
)
3494 if (cp_opc_expr (&str
, 5, 3) == FAIL
)
3497 inst
.error
= BAD_ARGS
;
3503 inst
.error
= BAD_COND
;
3511 do_fp_ctrl (str
, flags
)
3513 unsigned long flags
;
3515 /* FP control registers.
3516 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3518 skip_whitespace (str
);
3520 if (reg_required_here (&str
, 12) == FAIL
)
3523 inst
.error
= BAD_ARGS
;
3532 do_fp_ldst (str
, flags
)
3534 unsigned long flags
;
3536 skip_whitespace (str
);
3538 switch (inst
.suffix
)
3543 inst
.instruction
|= CP_T_X
;
3546 inst
.instruction
|= CP_T_Y
;
3549 inst
.instruction
|= CP_T_X
| CP_T_Y
;
3555 if (fp_reg_required_here (&str
, 12) == FAIL
)
3558 inst
.error
= BAD_ARGS
;
3562 if (skip_past_comma (&str
) == FAIL
3563 || cp_address_required_here (&str
) == FAIL
)
3566 inst
.error
= BAD_ARGS
;
3574 do_fp_ldmstm (str
, flags
)
3576 unsigned long flags
;
3580 skip_whitespace (str
);
3582 if (fp_reg_required_here (&str
, 12) == FAIL
)
3585 inst
.error
= BAD_ARGS
;
3589 /* Get Number of registers to transfer */
3590 if (skip_past_comma (&str
) == FAIL
3591 || my_get_expression (&inst
.reloc
.exp
, &str
))
3594 inst
.error
= _("constant expression expected");
3598 if (inst
.reloc
.exp
.X_op
!= O_constant
)
3600 inst
.error
= _("Constant value required for number of registers");
3604 num_regs
= inst
.reloc
.exp
.X_add_number
;
3606 if (num_regs
< 1 || num_regs
> 4)
3608 inst
.error
= _("number of registers must be in the range [1:4]");
3615 inst
.instruction
|= CP_T_X
;
3618 inst
.instruction
|= CP_T_Y
;
3621 inst
.instruction
|= CP_T_Y
| CP_T_X
;
3635 /* The instruction specified "ea" or "fd", so we can only accept
3636 [Rn]{!}. The instruction does not really support stacking or
3637 unstacking, so we have to emulate these by setting appropriate
3638 bits and offsets. */
3639 if (skip_past_comma (&str
) == FAIL
3643 inst
.error
= BAD_ARGS
;
3648 skip_whitespace (str
);
3650 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
3653 skip_whitespace (str
);
3657 inst
.error
= BAD_ARGS
;
3668 inst
.error
= _("R15 not allowed as base register with write-back");
3675 if (flags
& CP_T_Pre
)
3678 offset
= 3 * num_regs
;
3684 /* Post-increment */
3688 offset
= 3 * num_regs
;
3692 /* No write-back, so convert this into a standard pre-increment
3693 instruction -- aesthetically more pleasing. */
3694 flags
= CP_T_Pre
| CP_T_UD
;
3699 inst
.instruction
|= flags
| offset
;
3701 else if (skip_past_comma (&str
) == FAIL
3702 || cp_address_required_here (&str
) == FAIL
)
3705 inst
.error
= BAD_ARGS
;
3713 do_fp_dyadic (str
, flags
)
3715 unsigned long flags
;
3717 skip_whitespace (str
);
3719 switch (inst
.suffix
)
3724 inst
.instruction
|= 0x00000080;
3727 inst
.instruction
|= 0x00080000;
3733 if (fp_reg_required_here (&str
, 12) == FAIL
)
3736 inst
.error
= BAD_ARGS
;
3740 if (skip_past_comma (&str
) == FAIL
3741 || fp_reg_required_here (&str
, 16) == FAIL
)
3744 inst
.error
= BAD_ARGS
;
3748 if (skip_past_comma (&str
) == FAIL
3749 || fp_op2 (&str
) == FAIL
)
3752 inst
.error
= BAD_ARGS
;
3756 inst
.instruction
|= flags
;
3762 do_fp_monadic (str
, flags
)
3764 unsigned long flags
;
3766 skip_whitespace (str
);
3768 switch (inst
.suffix
)
3773 inst
.instruction
|= 0x00000080;
3776 inst
.instruction
|= 0x00080000;
3782 if (fp_reg_required_here (&str
, 12) == FAIL
)
3785 inst
.error
= BAD_ARGS
;
3789 if (skip_past_comma (&str
) == FAIL
3790 || fp_op2 (&str
) == FAIL
)
3793 inst
.error
= BAD_ARGS
;
3797 inst
.instruction
|= flags
;
3803 do_fp_cmp (str
, flags
)
3805 unsigned long flags
;
3807 skip_whitespace (str
);
3809 if (fp_reg_required_here (&str
, 16) == FAIL
)
3812 inst
.error
= BAD_ARGS
;
3816 if (skip_past_comma (&str
) == FAIL
3817 || fp_op2 (&str
) == FAIL
)
3820 inst
.error
= BAD_ARGS
;
3824 inst
.instruction
|= flags
;
3830 do_fp_from_reg (str
, flags
)
3832 unsigned long flags
;
3834 skip_whitespace (str
);
3836 switch (inst
.suffix
)
3841 inst
.instruction
|= 0x00000080;
3844 inst
.instruction
|= 0x00080000;
3850 if (fp_reg_required_here (&str
, 16) == FAIL
)
3853 inst
.error
= BAD_ARGS
;
3857 if (skip_past_comma (&str
) == FAIL
3858 || reg_required_here (&str
, 12) == FAIL
)
3861 inst
.error
= BAD_ARGS
;
3865 inst
.instruction
|= flags
;
3871 do_fp_to_reg (str
, flags
)
3873 unsigned long flags
;
3875 skip_whitespace (str
);
3877 if (reg_required_here (&str
, 12) == FAIL
)
3880 if (skip_past_comma (&str
) == FAIL
3881 || fp_reg_required_here (&str
, 0) == FAIL
)
3884 inst
.error
= BAD_ARGS
;
3888 inst
.instruction
|= flags
;
3893 /* Thumb specific routines */
3895 /* Parse and validate that a register is of the right form, this saves
3896 repeated checking of this information in many similar cases.
3897 Unlike the 32-bit case we do not insert the register into the opcode
3898 here, since the position is often unknown until the full instruction
3901 thumb_reg (strp
, hi_lo
)
3907 if ((reg
= reg_required_here (strp
, -1)) == FAIL
)
3915 inst
.error
= _("lo register required");
3923 inst
.error
= _("hi register required");
3935 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
3938 thumb_add_sub (str
, subtract
)
3942 int Rd
, Rs
, Rn
= FAIL
;
3944 skip_whitespace (str
);
3946 if ((Rd
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
3947 || skip_past_comma (&str
) == FAIL
)
3950 inst
.error
= BAD_ARGS
;
3954 if (is_immediate_prefix (*str
))
3958 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3963 if ((Rs
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
3966 if (skip_past_comma (&str
) == FAIL
)
3968 /* Two operand format, shuffle the registers and pretend there
3973 else if (is_immediate_prefix (*str
))
3976 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3979 else if ((Rn
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
3983 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
3984 for the latter case, EXPR contains the immediate that was found. */
3987 /* All register format. */
3988 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
3992 inst
.error
= _("dest and source1 must be the same register");
3996 /* Can't do this for SUB */
3999 inst
.error
= _("subtract valid only on lo regs");
4003 inst
.instruction
= (T_OPCODE_ADD_HI
4004 | (Rd
> 7 ? THUMB_H1
: 0)
4005 | (Rn
> 7 ? THUMB_H2
: 0));
4006 inst
.instruction
|= (Rd
& 7) | ((Rn
& 7) << 3);
4010 inst
.instruction
= subtract
? T_OPCODE_SUB_R3
: T_OPCODE_ADD_R3
;
4011 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
4016 /* Immediate expression, now things start to get nasty. */
4018 /* First deal with HI regs, only very restricted cases allowed:
4019 Adjusting SP, and using PC or SP to get an address. */
4020 if ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
4021 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
))
4023 inst
.error
= _("invalid Hi register with immediate");
4027 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4029 /* Value isn't known yet, all we can do is store all the fragments
4030 we know about in the instruction and let the reloc hacking
4032 inst
.instruction
= (subtract
? 0x8000 : 0) | (Rd
<< 4) | Rs
;
4033 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
4037 int offset
= inst
.reloc
.exp
.X_add_number
;
4047 /* Quick check, in case offset is MIN_INT */
4050 inst
.error
= _("immediate value out of range");
4059 if (offset
& ~0x1fc)
4061 inst
.error
= _("invalid immediate value for stack adjust");
4064 inst
.instruction
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
4065 inst
.instruction
|= offset
>> 2;
4067 else if (Rs
== REG_PC
|| Rs
== REG_SP
)
4070 || (offset
& ~0x3fc))
4072 inst
.error
= _("invalid immediate for address calculation");
4075 inst
.instruction
= (Rs
== REG_PC
? T_OPCODE_ADD_PC
4077 inst
.instruction
|= (Rd
<< 8) | (offset
>> 2);
4083 inst
.error
= _("immediate value out of range");
4086 inst
.instruction
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
4087 inst
.instruction
|= (Rd
<< 8) | offset
;
4093 inst
.error
= _("immediate value out of range");
4096 inst
.instruction
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
4097 inst
.instruction
|= Rd
| (Rs
<< 3) | (offset
<< 6);
4105 thumb_shift (str
, shift
)
4109 int Rd
, Rs
, Rn
= FAIL
;
4111 skip_whitespace (str
);
4113 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4114 || skip_past_comma (&str
) == FAIL
)
4117 inst
.error
= BAD_ARGS
;
4121 if (is_immediate_prefix (*str
))
4123 /* Two operand immediate format, set Rs to Rd. */
4126 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4131 if ((Rs
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4134 if (skip_past_comma (&str
) == FAIL
)
4136 /* Two operand format, shuffle the registers and pretend there
4141 else if (is_immediate_prefix (*str
))
4144 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4147 else if ((Rn
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4151 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4152 for the latter case, EXPR contains the immediate that was found. */
4158 inst
.error
= _("source1 and dest must be same register");
4164 case THUMB_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
4165 case THUMB_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
4166 case THUMB_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
4169 inst
.instruction
|= Rd
| (Rn
<< 3);
4175 case THUMB_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
4176 case THUMB_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
4177 case THUMB_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
4180 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4182 /* Value isn't known yet, create a dummy reloc and let reloc
4183 hacking fix it up */
4185 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
4189 unsigned shift_value
= inst
.reloc
.exp
.X_add_number
;
4191 if (shift_value
> 32 || (shift_value
== 32 && shift
== THUMB_LSL
))
4193 inst
.error
= _("Invalid immediate for shift");
4197 /* Shifts of zero are handled by converting to LSL */
4198 if (shift_value
== 0)
4199 inst
.instruction
= T_OPCODE_LSL_I
;
4201 /* Shifts of 32 are encoded as a shift of zero */
4202 if (shift_value
== 32)
4205 inst
.instruction
|= shift_value
<< 6;
4208 inst
.instruction
|= Rd
| (Rs
<< 3);
4214 thumb_mov_compare (str
, move
)
4220 skip_whitespace (str
);
4222 if ((Rd
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
4223 || skip_past_comma (&str
) == FAIL
)
4226 inst
.error
= BAD_ARGS
;
4230 if (is_immediate_prefix (*str
))
4233 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4236 else if ((Rs
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4241 if (Rs
< 8 && Rd
< 8)
4243 if (move
== THUMB_MOVE
)
4244 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4245 since a MOV instruction produces unpredictable results */
4246 inst
.instruction
= T_OPCODE_ADD_I3
;
4248 inst
.instruction
= T_OPCODE_CMP_LR
;
4249 inst
.instruction
|= Rd
| (Rs
<< 3);
4253 if (move
== THUMB_MOVE
)
4254 inst
.instruction
= T_OPCODE_MOV_HR
;
4256 inst
.instruction
= T_OPCODE_CMP_HR
;
4259 inst
.instruction
|= THUMB_H1
;
4262 inst
.instruction
|= THUMB_H2
;
4264 inst
.instruction
|= (Rd
& 7) | ((Rs
& 7) << 3);
4271 inst
.error
= _("only lo regs allowed with immediate");
4275 if (move
== THUMB_MOVE
)
4276 inst
.instruction
= T_OPCODE_MOV_I8
;
4278 inst
.instruction
= T_OPCODE_CMP_I8
;
4280 inst
.instruction
|= Rd
<< 8;
4282 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4283 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
4286 unsigned value
= inst
.reloc
.exp
.X_add_number
;
4290 inst
.error
= _("invalid immediate");
4294 inst
.instruction
|= value
;
4302 thumb_load_store (str
, load_store
, size
)
4307 int Rd
, Rb
, Ro
= FAIL
;
4309 skip_whitespace (str
);
4311 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4312 || skip_past_comma (&str
) == FAIL
)
4315 inst
.error
= BAD_ARGS
;
4322 if ((Rb
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4325 if (skip_past_comma (&str
) != FAIL
)
4327 if (is_immediate_prefix (*str
))
4330 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4333 else if ((Ro
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4338 inst
.reloc
.exp
.X_op
= O_constant
;
4339 inst
.reloc
.exp
.X_add_number
= 0;
4344 inst
.error
= _("expected ']'");
4349 else if (*str
== '=')
4351 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
4354 skip_whitespace (str
);
4356 if (my_get_expression (& inst
.reloc
.exp
, & str
))
4361 if ( inst
.reloc
.exp
.X_op
!= O_constant
4362 && inst
.reloc
.exp
.X_op
!= O_symbol
)
4364 inst
.error
= "Constant expression expected";
4368 if (inst
.reloc
.exp
.X_op
== O_constant
4369 && ((inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0))
4371 /* This can be done with a mov instruction */
4373 inst
.instruction
= T_OPCODE_MOV_I8
| (Rd
<< 8);
4374 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
4378 /* Insert into literal pool */
4379 if (add_to_lit_pool () == FAIL
)
4382 inst
.error
= "literal pool insertion failed";
4386 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4387 inst
.reloc
.pc_rel
= 1;
4388 inst
.instruction
= T_OPCODE_LDR_PC
| (Rd
<< 8);
4389 inst
.reloc
.exp
.X_add_number
+= 4; /* Adjust ARM pipeline offset to Thumb */
4395 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4398 inst
.instruction
= T_OPCODE_LDR_PC
| (Rd
<< 8);
4399 inst
.reloc
.pc_rel
= 1;
4400 inst
.reloc
.exp
.X_add_number
-= 4; /* Pipeline offset */
4401 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4406 if (Rb
== REG_PC
|| Rb
== REG_SP
)
4408 if (size
!= THUMB_WORD
)
4410 inst
.error
= _("byte or halfword not valid for base register");
4413 else if (Rb
== REG_PC
&& load_store
!= THUMB_LOAD
)
4415 inst
.error
= _("R15 based store not allowed");
4418 else if (Ro
!= FAIL
)
4420 inst
.error
= _("Invalid base register for register offset");
4425 inst
.instruction
= T_OPCODE_LDR_PC
;
4426 else if (load_store
== THUMB_LOAD
)
4427 inst
.instruction
= T_OPCODE_LDR_SP
;
4429 inst
.instruction
= T_OPCODE_STR_SP
;
4431 inst
.instruction
|= Rd
<< 8;
4432 if (inst
.reloc
.exp
.X_op
== O_constant
)
4434 unsigned offset
= inst
.reloc
.exp
.X_add_number
;
4436 if (offset
& ~0x3fc)
4438 inst
.error
= _("invalid offset");
4442 inst
.instruction
|= offset
>> 2;
4445 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4449 inst
.error
= _("invalid base register in load/store");
4452 else if (Ro
== FAIL
)
4454 /* Immediate offset */
4455 if (size
== THUMB_WORD
)
4456 inst
.instruction
= (load_store
== THUMB_LOAD
4457 ? T_OPCODE_LDR_IW
: T_OPCODE_STR_IW
);
4458 else if (size
== THUMB_HALFWORD
)
4459 inst
.instruction
= (load_store
== THUMB_LOAD
4460 ? T_OPCODE_LDR_IH
: T_OPCODE_STR_IH
);
4462 inst
.instruction
= (load_store
== THUMB_LOAD
4463 ? T_OPCODE_LDR_IB
: T_OPCODE_STR_IB
);
4465 inst
.instruction
|= Rd
| (Rb
<< 3);
4467 if (inst
.reloc
.exp
.X_op
== O_constant
)
4469 unsigned offset
= inst
.reloc
.exp
.X_add_number
;
4471 if (offset
& ~(0x1f << size
))
4473 inst
.error
= _("Invalid offset");
4476 inst
.instruction
|= (offset
>> size
) << 6;
4479 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4483 /* Register offset */
4484 if (size
== THUMB_WORD
)
4485 inst
.instruction
= (load_store
== THUMB_LOAD
4486 ? T_OPCODE_LDR_RW
: T_OPCODE_STR_RW
);
4487 else if (size
== THUMB_HALFWORD
)
4488 inst
.instruction
= (load_store
== THUMB_LOAD
4489 ? T_OPCODE_LDR_RH
: T_OPCODE_STR_RH
);
4491 inst
.instruction
= (load_store
== THUMB_LOAD
4492 ? T_OPCODE_LDR_RB
: T_OPCODE_STR_RB
);
4494 inst
.instruction
|= Rd
| (Rb
<< 3) | (Ro
<< 6);
4509 /* Handle the Format 4 instructions that do not have equivalents in other
4510 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4518 skip_whitespace (str
);
4520 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4521 || skip_past_comma (&str
) == FAIL
4522 || (Rs
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4524 inst
.error
= BAD_ARGS
;
4528 if (skip_past_comma (&str
) != FAIL
)
4530 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4531 (It isn't allowed for CMP either, but that isn't handled by this
4533 if (inst
.instruction
== T_OPCODE_TST
4534 || inst
.instruction
== T_OPCODE_CMN
4535 || inst
.instruction
== T_OPCODE_NEG
4536 || inst
.instruction
== T_OPCODE_MVN
)
4538 inst
.error
= BAD_ARGS
;
4542 if ((Rn
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4547 inst
.error
= _("dest and source1 one must be the same register");
4553 if (inst
.instruction
== T_OPCODE_MUL
4555 as_tsktsk (_("Rs and Rd must be different in MUL"));
4557 inst
.instruction
|= Rd
| (Rs
<< 3);
4565 thumb_add_sub (str
, 0);
4572 thumb_shift (str
, THUMB_ASR
);
4579 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4581 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
4582 inst
.reloc
.pc_rel
= 1;
4590 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4592 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
4593 inst
.reloc
.pc_rel
= 1;
4597 /* Find the real, Thumb encoded start of a Thumb function. */
4600 find_real_start (symbolP
)
4604 const char * name
= S_GET_NAME (symbolP
);
4605 symbolS
* new_target
;
4607 /* This definiton must agree with the one in gcc/config/arm/thumb.c */
4608 #define STUB_NAME ".real_start_of"
4613 /* Names that start with '.' are local labels, not function entry points.
4614 The compiler may generate BL instructions to these labels because it
4615 needs to perform a branch to a far away location. */
4619 real_start
= malloc (strlen (name
) + strlen (STUB_NAME
) + 1);
4620 sprintf (real_start
, "%s%s", STUB_NAME
, name
);
4622 new_target
= symbol_find (real_start
);
4624 if (new_target
== NULL
)
4626 as_warn ("Failed to find real start of function: %s\n", name
);
4627 new_target
= symbolP
;
4640 if (my_get_expression (& inst
.reloc
.exp
, & str
))
4643 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
4644 inst
.reloc
.pc_rel
= 1;
4647 /* If the destination of the branch is a defined symbol which does not have
4648 the THUMB_FUNC attribute, then we must be calling a function which has
4649 the (interfacearm) attribute. We look for the Thumb entry point to that
4650 function and change the branch to refer to that function instead. */
4651 if ( inst
.reloc
.exp
.X_op
== O_symbol
4652 && inst
.reloc
.exp
.X_add_symbol
!= NULL
4653 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
4654 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
4655 inst
.reloc
.exp
.X_add_symbol
= find_real_start (inst
.reloc
.exp
.X_add_symbol
);
4664 skip_whitespace (str
);
4666 if ((reg
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4669 /* This sets THUMB_H2 from the top bit of reg. */
4670 inst
.instruction
|= reg
<< 3;
4672 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4673 should cause the alignment to be checked once it is known. This is
4674 because BX PC only works if the instruction is word aligned. */
4683 thumb_mov_compare (str
, THUMB_COMPARE
);
4693 skip_whitespace (str
);
4695 if ((Rb
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4699 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4703 if (skip_past_comma (&str
) == FAIL
4704 || (range
= reg_list (&str
)) == FAIL
)
4707 inst
.error
= BAD_ARGS
;
4711 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
4713 /* This really doesn't seem worth it. */
4714 inst
.reloc
.type
= BFD_RELOC_NONE
;
4715 inst
.error
= _("Expression too complex");
4721 inst
.error
= _("only lo-regs valid in load/store multiple");
4725 inst
.instruction
|= (Rb
<< 8) | range
;
4733 thumb_load_store (str
, THUMB_LOAD
, THUMB_WORD
);
4740 thumb_load_store (str
, THUMB_LOAD
, THUMB_BYTE
);
4747 thumb_load_store (str
, THUMB_LOAD
, THUMB_HALFWORD
);
4756 skip_whitespace (str
);
4758 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4759 || skip_past_comma (&str
) == FAIL
4761 || (Rb
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4762 || skip_past_comma (&str
) == FAIL
4763 || (Ro
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4767 inst
.error
= _("Syntax: ldrs[b] Rd, [Rb, Ro]");
4771 inst
.instruction
|= Rd
| (Rb
<< 3) | (Ro
<< 6);
4779 thumb_shift (str
, THUMB_LSL
);
4786 thumb_shift (str
, THUMB_LSR
);
4793 thumb_mov_compare (str
, THUMB_MOVE
);
4802 skip_whitespace (str
);
4804 if ((range
= reg_list (&str
)) == FAIL
)
4807 inst
.error
= BAD_ARGS
;
4811 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
4813 /* This really doesn't seem worth it. */
4814 inst
.reloc
.type
= BFD_RELOC_NONE
;
4815 inst
.error
= _("Expression too complex");
4821 if ((inst
.instruction
== T_OPCODE_PUSH
4822 && (range
& ~0xff) == 1 << REG_LR
)
4823 || (inst
.instruction
== T_OPCODE_POP
4824 && (range
& ~0xff) == 1 << REG_PC
))
4826 inst
.instruction
|= THUMB_PP_PC_LR
;
4831 inst
.error
= _("invalid register list to push/pop instruction");
4836 inst
.instruction
|= range
;
4844 thumb_load_store (str
, THUMB_STORE
, THUMB_WORD
);
4851 thumb_load_store (str
, THUMB_STORE
, THUMB_BYTE
);
4858 thumb_load_store (str
, THUMB_STORE
, THUMB_HALFWORD
);
4865 thumb_add_sub (str
, 1);
4872 skip_whitespace (str
);
4874 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4877 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
4886 /* This is a pseudo-op of the form "adr rd, label" to be converted
4887 into a relative address of the form "add rd, pc, #label-.-4" */
4888 skip_whitespace (str
);
4890 if (reg_required_here (&str
, 4) == FAIL
/* Store Rd in temporary location inside instruction. */
4891 || skip_past_comma (&str
) == FAIL
4892 || my_get_expression (&inst
.reloc
.exp
, &str
))
4895 inst
.error
= BAD_ARGS
;
4899 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
4900 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust */
4901 inst
.reloc
.pc_rel
= 1;
4902 inst
.instruction
|= REG_PC
; /* Rd is already placed into the instruction */
4910 int len
= strlen (reg_table
[entry
].name
) + 2;
4911 char * buf
= (char *) xmalloc (len
);
4912 char * buf2
= (char *) xmalloc (len
);
4915 #ifdef REGISTER_PREFIX
4916 buf
[i
++] = REGISTER_PREFIX
;
4919 strcpy (buf
+ i
, reg_table
[entry
].name
);
4921 for (i
= 0; buf
[i
]; i
++)
4922 buf2
[i
] = islower (buf
[i
]) ? toupper (buf
[i
]) : buf
[i
];
4926 hash_insert (arm_reg_hsh
, buf
, (PTR
) ®_table
[entry
]);
4927 hash_insert (arm_reg_hsh
, buf2
, (PTR
) ®_table
[entry
]);
4931 insert_reg_alias (str
, regnum
)
4935 struct reg_entry
*new =
4936 (struct reg_entry
*)xmalloc (sizeof (struct reg_entry
));
4937 char *name
= xmalloc (strlen (str
) + 1);
4941 new->number
= regnum
;
4943 hash_insert (arm_reg_hsh
, name
, (PTR
) new);
4947 set_constant_flonums ()
4951 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4952 if (atof_ieee ((char *)fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
4961 if ( (arm_ops_hsh
= hash_new ()) == NULL
4962 || (arm_tops_hsh
= hash_new ()) == NULL
4963 || (arm_cond_hsh
= hash_new ()) == NULL
4964 || (arm_shift_hsh
= hash_new ()) == NULL
4965 || (arm_reg_hsh
= hash_new ()) == NULL
4966 || (arm_psr_hsh
= hash_new ()) == NULL
)
4967 as_fatal (_("Virtual memory exhausted"));
4969 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
4970 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
4971 for (i
= 0; i
< sizeof (tinsns
) / sizeof (struct thumb_opcode
); i
++)
4972 hash_insert (arm_tops_hsh
, tinsns
[i
].template, (PTR
) (tinsns
+ i
));
4973 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
4974 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
4975 for (i
= 0; i
< sizeof (shift
) / sizeof (struct asm_shift
); i
++)
4976 hash_insert (arm_shift_hsh
, shift
[i
].template, (PTR
) (shift
+ i
));
4977 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
4978 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
4980 for (i
= 0; reg_table
[i
].name
; i
++)
4983 set_constant_flonums ();
4985 #if defined OBJ_COFF || defined OBJ_ELF
4987 unsigned int flags
= 0;
4989 /* Set the flags in the private structure */
4990 if (uses_apcs_26
) flags
|= F_APCS26
;
4991 if (support_interwork
) flags
|= F_INTERWORK
;
4992 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
4993 if (pic_code
) flags
|= F_PIC
;
4994 if ((cpu_variant
& FPU_ALL
) == FPU_NONE
) flags
|= F_SOFT_FLOAT
;
4996 bfd_set_private_flags (stdoutput
, flags
);
5003 /* Record the CPU type as well */
5004 switch (cpu_variant
& ARM_CPU_MASK
)
5007 mach
= bfd_mach_arm_2
;
5010 case ARM_3
: /* also ARM_250 */
5011 mach
= bfd_mach_arm_2a
;
5015 case ARM_6
| ARM_3
| ARM_2
: /* Actually no CPU type defined */
5016 mach
= bfd_mach_arm_4
;
5019 case ARM_7
: /* also ARM_6 */
5020 mach
= bfd_mach_arm_3
;
5024 /* Catch special cases. */
5025 if (cpu_variant
!= (FPU_DEFAULT
| CPU_DEFAULT
))
5027 if (cpu_variant
& (ARM_EXT_V5
& ARM_THUMB
))
5028 mach
= bfd_mach_arm_5T
;
5029 else if (cpu_variant
& ARM_EXT_V5
)
5030 mach
= bfd_mach_arm_5
;
5031 else if (cpu_variant
& ARM_THUMB
)
5032 mach
= bfd_mach_arm_4T
;
5033 else if ((cpu_variant
& ARM_ARCH_V4
) == ARM_ARCH_V4
)
5034 mach
= bfd_mach_arm_4
;
5035 else if (cpu_variant
& ARM_LONGMUL
)
5036 mach
= bfd_mach_arm_3M
;
5039 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
5043 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5044 for use in the a.out file, and stores them in the array pointed to by buf.
5045 This knows about the endian-ness of the target machine and does
5046 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5047 2 (short) and 4 (long) Floating numbers are put out as a series of
5048 LITTLENUMS (shorts, here at least). */
5050 md_number_to_chars (buf
, val
, n
)
5055 if (target_big_endian
)
5056 number_to_chars_bigendian (buf
, val
, n
);
5058 number_to_chars_littleendian (buf
, val
, n
);
5062 md_chars_to_number (buf
, n
)
5067 unsigned char * where
= (unsigned char *) buf
;
5069 if (target_big_endian
)
5074 result
|= (*where
++ & 255);
5082 result
|= (where
[n
] & 255);
5089 /* Turn a string in input_line_pointer into a floating point constant
5090 of type TYPE, and store the appropriate bytes in *litP. The number
5091 of LITTLENUMS emitted is stored in *sizeP . An error message is
5092 returned, or NULL on OK.
5094 Note that fp constants aren't represent in the normal way on the ARM.
5095 In big endian mode, things are as expected. However, in little endian
5096 mode fp constants are big-endian word-wise, and little-endian byte-wise
5097 within the words. For example, (double) 1.1 in big endian mode is
5098 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5099 the byte sequence 99 99 f1 3f 9a 99 99 99.
5101 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5104 md_atof (type
, litP
, sizeP
)
5110 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5142 return _("Bad call to MD_ATOF()");
5145 t
= atof_ieee (input_line_pointer
, type
, words
);
5147 input_line_pointer
= t
;
5150 if (target_big_endian
)
5152 for (i
= 0; i
< prec
; i
++)
5154 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5160 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5161 8 byte float the order is 1 0 3 2. */
5162 for (i
= 0; i
< prec
; i
+= 2)
5164 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
5165 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
5173 /* The knowledge of the PC's pipeline offset is built into the insns themselves. */
5175 md_pcrel_from (fixP
)
5179 && S_GET_SEGMENT (fixP
->fx_addsy
) == undefined_section
5180 && fixP
->fx_subsy
== NULL
)
5183 if (fixP
->fx_pcrel
&& (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_ADD
))
5185 /* PC relative addressing on the Thumb is slightly odd
5186 as the bottom two bits of the PC are forced to zero
5187 for the calculation. */
5188 return (fixP
->fx_where
+ fixP
->fx_frag
->fr_address
) & ~3;
5191 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5194 /* Round up a section size to the appropriate boundary. */
5196 md_section_align (segment
, size
)
5203 /* Round all sects to multiple of 4 */
5204 return (size
+ 3) & ~3;
5208 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. Otherwise
5209 we have no need to default values of symbols. */
5213 md_undefined_symbol (name
)
5217 if (name
[0] == '_' && name
[1] == 'G'
5218 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
5222 if (symbol_find (name
))
5223 as_bad ("GOT already in the symbol table");
5225 GOT_symbol
= symbol_new (name
, undefined_section
,
5226 (valueT
)0, & zero_address_frag
);
5236 /* arm_reg_parse () := if it looks like a register, return its token and
5237 advance the pointer. */
5241 register char ** ccp
;
5243 char * start
= * ccp
;
5246 struct reg_entry
* reg
;
5248 #ifdef REGISTER_PREFIX
5249 if (*start
!= REGISTER_PREFIX
)
5254 #ifdef OPTIONAL_REGISTER_PREFIX
5255 if (*p
== OPTIONAL_REGISTER_PREFIX
)
5259 if (!isalpha (*p
) || !is_name_beginner (*p
))
5263 while (isalpha (c
) || isdigit (c
) || c
== '_')
5267 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, start
);
5281 register char ** ccp
;
5283 char * start
= * ccp
;
5286 CONST
struct asm_psr
* psr
;
5290 while (isalpha (c
) || c
== '_')
5294 psr
= (CONST
struct asm_psr
*) hash_find (arm_psr_hsh
, start
);
5307 md_apply_fix3 (fixP
, val
, seg
)
5312 offsetT value
= * val
;
5314 unsigned int newimm
;
5317 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5318 arm_fix_data
* arm_data
= (arm_fix_data
*) fixP
->tc_fix_data
;
5320 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
5322 /* Note whether this will delete the relocation. */
5323 #if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
5324 if ((fixP
->fx_addsy
== 0 || symbol_constant_p (fixP
->fx_addsy
))
5327 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
5331 /* If this symbol is in a different section then we need to leave it for
5332 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5333 so we have to undo it's effects here. */
5336 if (fixP
->fx_addsy
!= NULL
5337 && S_IS_DEFINED (fixP
->fx_addsy
)
5338 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
5341 && (fixP
->fx_r_type
== BFD_RELOC_ARM_PCREL_BRANCH
5345 value
+= md_pcrel_from (fixP
);
5349 fixP
->fx_addnumber
= value
; /* Remember value for emit_reloc. */
5351 switch (fixP
->fx_r_type
)
5353 case BFD_RELOC_ARM_IMMEDIATE
:
5354 newimm
= validate_immediate (value
);
5355 temp
= md_chars_to_number (buf
, INSN_SIZE
);
5357 /* If the instruction will fail, see if we can fix things up by
5358 changing the opcode. */
5359 if (newimm
== (unsigned int) FAIL
5360 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
5362 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5363 _("invalid constant (%lx) after fixup"),
5364 (unsigned long) value
);
5368 newimm
|= (temp
& 0xfffff000);
5369 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
5372 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
5374 unsigned int highpart
= 0;
5375 unsigned int newinsn
= 0xe1a00000; /* nop */
5376 newimm
= validate_immediate (value
);
5377 temp
= md_chars_to_number (buf
, INSN_SIZE
);
5379 /* If the instruction will fail, see if we can fix things up by
5380 changing the opcode. */
5381 if (newimm
== (unsigned int) FAIL
5382 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
5384 /* No ? OK - try using two ADD instructions to generate the value. */
5385 newimm
= validate_immediate_twopart (value
, & highpart
);
5387 /* Yes - then make sure that the second instruction is also an add. */
5388 if (newimm
!= (unsigned int) FAIL
)
5390 /* Still No ? Try using a negated value. */
5391 else if (validate_immediate_twopart (- value
, & highpart
) != (unsigned int) FAIL
)
5392 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
5393 /* Otherwise - give up. */
5396 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5397 _("Unable to compute ADRL instructions for PC offset of 0x%x"), value
);
5401 /* Replace the first operand in the 2nd instruction (which is the PC)
5402 with the destination register. We have already added in the PC in the
5403 first instruction and we do not want to do it again. */
5404 newinsn
&= ~ 0xf0000;
5405 newinsn
|= ((newinsn
& 0x0f000) << 4);
5408 newimm
|= (temp
& 0xfffff000);
5409 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
5411 highpart
|= (newinsn
& 0xfffff000);
5412 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
5416 case BFD_RELOC_ARM_OFFSET_IMM
:
5422 if (validate_offset_imm (value
, 0) == FAIL
)
5424 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5425 _("bad immediate value for offset (%ld)"), (long) value
);
5429 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5430 newval
&= 0xff7ff000;
5431 newval
|= value
| (sign
? INDEX_UP
: 0);
5432 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5435 case BFD_RELOC_ARM_OFFSET_IMM8
:
5436 case BFD_RELOC_ARM_HWLITERAL
:
5442 if (validate_offset_imm (value
, 1) == FAIL
)
5444 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
5445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5446 _("invalid literal constant: pool needs to be closer"));
5448 as_bad (_("bad immediate value for half-word offset (%ld)"),
5453 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5454 newval
&= 0xff7ff0f0;
5455 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
5456 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5459 case BFD_RELOC_ARM_LITERAL
:
5465 if (validate_offset_imm (value
, 0) == FAIL
)
5467 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5468 _("invalid literal constant: pool needs to be closer"));
5472 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5473 newval
&= 0xff7ff000;
5474 newval
|= value
| (sign
? INDEX_UP
: 0);
5475 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5478 case BFD_RELOC_ARM_SHIFT_IMM
:
5479 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5480 if (((unsigned long) value
) > 32
5482 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
5484 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5485 _("shift expression is too large"));
5490 newval
&= ~0x60; /* Shifts of zero must be done as lsl */
5491 else if (value
== 32)
5493 newval
&= 0xfffff07f;
5494 newval
|= (value
& 0x1f) << 7;
5495 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5498 case BFD_RELOC_ARM_SWI
:
5499 if (arm_data
->thumb_mode
)
5501 if (((unsigned long) value
) > 0xff)
5502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5503 _("Invalid swi expression"));
5504 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xff00;
5506 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5510 if (((unsigned long) value
) > 0x00ffffff)
5511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5512 _("Invalid swi expression"));
5513 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff000000;
5515 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5519 case BFD_RELOC_ARM_MULTI
:
5520 if (((unsigned long) value
) > 0xffff)
5521 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5522 _("Invalid expression in load/store multiple"));
5523 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
5524 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5527 case BFD_RELOC_ARM_PCREL_BRANCH
:
5528 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5532 value
= fixP
->fx_offset
;
5534 value
= (value
>> 2) & 0x00ffffff;
5535 value
= (value
+ (newval
& 0x00ffffff)) & 0x00ffffff;
5536 newval
= value
| (newval
& 0xff000000);
5537 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5541 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* conditional branch */
5542 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5544 addressT diff
= (newval
& 0xff) << 1;
5549 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
5550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5551 _("Branch out of range"));
5552 newval
= (newval
& 0xff00) | ((value
& 0x1ff) >> 1);
5554 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5557 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* unconditional branch */
5558 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5560 addressT diff
= (newval
& 0x7ff) << 1;
5565 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
5566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5567 _("Branch out of range"));
5568 newval
= (newval
& 0xf800) | ((value
& 0xfff) >> 1);
5570 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5573 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
5578 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5579 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
5580 diff
= ((newval
& 0x7ff) << 12) | ((newval2
& 0x7ff) << 1);
5581 if (diff
& 0x400000)
5584 value
= fixP
->fx_offset
;
5587 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
5588 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5589 _("Branch with link out of range"));
5591 newval
= (newval
& 0xf800) | ((value
& 0x7fffff) >> 12);
5592 newval2
= (newval2
& 0xf800) | ((value
& 0xfff) >> 1);
5593 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5594 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
5599 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
5600 md_number_to_chars (buf
, value
, 1);
5602 else if (!target_oabi
)
5604 value
= fixP
->fx_offset
;
5605 md_number_to_chars (buf
, value
, 1);
5611 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
5612 md_number_to_chars (buf
, value
, 2);
5614 else if (!target_oabi
)
5616 value
= fixP
->fx_offset
;
5617 md_number_to_chars (buf
, value
, 2);
5623 case BFD_RELOC_ARM_GOT32
:
5624 case BFD_RELOC_ARM_GOTOFF
:
5625 md_number_to_chars (buf
, 0, 4);
5631 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
5632 md_number_to_chars (buf
, value
, 4);
5634 else if (!target_oabi
)
5636 value
= fixP
->fx_offset
;
5637 md_number_to_chars (buf
, value
, 4);
5643 case BFD_RELOC_ARM_PLT32
:
5644 /* It appears the instruction is fully prepared at this point. */
5648 case BFD_RELOC_ARM_GOTPC
:
5649 md_number_to_chars (buf
, value
, 4);
5652 case BFD_RELOC_ARM_CP_OFF_IMM
:
5654 if (value
< -1023 || value
> 1023 || (value
& 3))
5655 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5656 _("Illegal value for co-processor offset"));
5659 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff7fff00;
5660 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
5661 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5664 case BFD_RELOC_ARM_THUMB_OFFSET
:
5665 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5666 /* Exactly what ranges, and where the offset is inserted depends on
5667 the type of instruction, we can establish this from the top 4 bits */
5668 switch (newval
>> 12)
5670 case 4: /* PC load */
5671 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5672 forced to zero for these loads, so we will need to round
5673 up the offset if the instruction address is not word
5674 aligned (since the final address produced must be, and
5675 we can only describe word-aligned immediate offsets). */
5677 if ((fixP
->fx_frag
->fr_address
+ fixP
->fx_where
+ value
) & 3)
5678 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5679 _("Invalid offset, target not word aligned (0x%08X)"),
5680 (unsigned int)(fixP
->fx_frag
->fr_address
+ fixP
->fx_where
+ value
));
5682 if ((value
+ 2) & ~0x3fe)
5683 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5684 _("Invalid offset, value too big (0x%08X)"), value
);
5686 /* Round up, since pc will be rounded down. */
5687 newval
|= (value
+ 2) >> 2;
5690 case 9: /* SP load/store */
5692 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5693 _("Invalid offset, value too big (0x%08X)"), value
);
5694 newval
|= value
>> 2;
5697 case 6: /* Word load/store */
5699 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5700 _("Invalid offset, value too big (0x%08X)"), value
);
5701 newval
|= value
<< 4; /* 6 - 2 */
5704 case 7: /* Byte load/store */
5706 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5707 _("Invalid offset, value too big (0x%08X)"), value
);
5708 newval
|= value
<< 6;
5711 case 8: /* Halfword load/store */
5713 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5714 _("Invalid offset, value too big (0x%08X)"), value
);
5715 newval
|= value
<< 5; /* 6 - 1 */
5719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5720 "Unable to process relocation for thumb opcode: %lx",
5721 (unsigned long) newval
);
5724 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5727 case BFD_RELOC_ARM_THUMB_ADD
:
5728 /* This is a complicated relocation, since we use it for all of
5729 the following immediate relocations:
5732 9bit ADD/SUB SP word-aligned
5733 10bit ADD PC/SP word-aligned
5735 The type of instruction being processed is encoded in the
5741 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5743 int rd
= (newval
>> 4) & 0xf;
5744 int rs
= newval
& 0xf;
5745 int subtract
= newval
& 0x8000;
5750 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5751 _("Invalid immediate for stack address calculation"));
5752 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
5753 newval
|= value
>> 2;
5755 else if (rs
== REG_PC
|| rs
== REG_SP
)
5759 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5760 _("Invalid immediate for address calculation (value = 0x%08lX)"),
5761 (unsigned long) value
);
5762 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
5764 newval
|= value
>> 2;
5769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5770 _("Invalid 8bit immediate"));
5771 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
5772 newval
|= (rd
<< 8) | value
;
5777 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5778 _("Invalid 3bit immediate"));
5779 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
5780 newval
|= rd
| (rs
<< 3) | (value
<< 6);
5783 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5786 case BFD_RELOC_ARM_THUMB_IMM
:
5787 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5788 switch (newval
>> 11)
5790 case 0x04: /* 8bit immediate MOV */
5791 case 0x05: /* 8bit immediate CMP */
5792 if (value
< 0 || value
> 255)
5793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5794 _("Invalid immediate: %ld is too large"),
5802 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5805 case BFD_RELOC_ARM_THUMB_SHIFT
:
5806 /* 5bit shift value (0..31) */
5807 if (value
< 0 || value
> 31)
5808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5809 _("Illegal Thumb shift value: %ld"), (long) value
);
5810 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf03f;
5811 newval
|= value
<< 6;
5812 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5815 case BFD_RELOC_VTABLE_INHERIT
:
5816 case BFD_RELOC_VTABLE_ENTRY
:
5820 case BFD_RELOC_NONE
:
5822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5823 _("Bad relocation fixup type (%d)"), fixP
->fx_r_type
);
5829 /* Translate internal representation of relocation info to BFD target
5832 tc_gen_reloc (section
, fixp
)
5837 bfd_reloc_code_real_type code
;
5839 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5841 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5842 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5843 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5845 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
5847 if (fixp
->fx_pcrel
== 0)
5848 reloc
->addend
= fixp
->fx_offset
;
5850 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
5852 reloc
->addend
= fixp
->fx_offset
;
5855 switch (fixp
->fx_r_type
)
5860 code
= BFD_RELOC_8_PCREL
;
5867 code
= BFD_RELOC_16_PCREL
;
5874 code
= BFD_RELOC_32_PCREL
;
5878 case BFD_RELOC_ARM_PCREL_BRANCH
:
5880 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
5881 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
5882 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
5883 case BFD_RELOC_VTABLE_ENTRY
:
5884 case BFD_RELOC_VTABLE_INHERIT
:
5885 code
= fixp
->fx_r_type
;
5888 case BFD_RELOC_ARM_LITERAL
:
5889 case BFD_RELOC_ARM_HWLITERAL
:
5890 /* If this is called then the a literal has been referenced across
5891 a section boundary - possibly due to an implicit dump */
5892 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5893 _("Literal referenced across section boundary (Implicit dump?)"));
5897 case BFD_RELOC_ARM_GOT32
:
5898 case BFD_RELOC_ARM_GOTOFF
:
5899 case BFD_RELOC_ARM_PLT32
:
5900 code
= fixp
->fx_r_type
;
5904 case BFD_RELOC_ARM_IMMEDIATE
:
5905 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5906 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
5910 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
5911 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5912 _("ADRL used for a symbol not defined in the same file"),
5916 case BFD_RELOC_ARM_OFFSET_IMM
:
5917 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5918 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
5925 switch (fixp
->fx_r_type
)
5927 case BFD_RELOC_ARM_IMMEDIATE
: type
= "IMMEDIATE"; break;
5928 case BFD_RELOC_ARM_OFFSET_IMM
: type
= "OFFSET_IMM"; break;
5929 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
5930 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
5931 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
5932 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
5933 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
5934 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
5935 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
5936 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
5937 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
5938 default: type
= _("<unknown>"); break;
5940 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5941 _("Can not represent %s relocation in this object file format (%d)"),
5942 type
, fixp
->fx_pcrel
);
5948 if (code
== BFD_RELOC_32_PCREL
5950 && fixp
->fx_addsy
== GOT_symbol
)
5952 code
= BFD_RELOC_ARM_GOTPC
;
5953 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
5957 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5959 if (reloc
->howto
== NULL
)
5961 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5962 _("Can not represent %s relocation in this object file format"),
5963 bfd_get_reloc_code_name (code
));
5967 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
5968 vtable entry to be used in the relocation's section offset. */
5969 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5970 reloc
->address
= fixp
->fx_offset
;
5976 md_estimate_size_before_relax (fragP
, segtype
)
5980 as_fatal (_("md_estimate_size_before_relax\n"));
5985 output_inst
PARAMS ((void))
5991 as_bad (inst
.error
);
5995 to
= frag_more (inst
.size
);
5997 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
5999 assert (inst
.size
== (2 * THUMB_SIZE
));
6000 md_number_to_chars (to
, inst
.instruction
>> 16, THUMB_SIZE
);
6001 md_number_to_chars (to
+ THUMB_SIZE
, inst
.instruction
, THUMB_SIZE
);
6003 else if (inst
.size
> INSN_SIZE
)
6005 assert (inst
.size
== (2 * INSN_SIZE
));
6006 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
6007 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
6010 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
6012 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
6013 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
6014 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
6029 /* Align the instruction.
6030 This may not be the right thing to do but ... */
6031 /* arm_align (2, 0); */
6032 listing_prev_line (); /* Defined in listing.h */
6034 /* Align the previous label if needed. */
6035 if (last_label_seen
!= NULL
)
6037 symbol_set_frag (last_label_seen
, frag_now
);
6038 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6039 S_SET_SEGMENT (last_label_seen
, now_seg
);
6042 memset (&inst
, '\0', sizeof (inst
));
6043 inst
.reloc
.type
= BFD_RELOC_NONE
;
6045 skip_whitespace (str
);
6047 /* Scan up to the end of the op-code, which must end in white space or
6049 for (start
= p
= str
; *p
!= '\0'; p
++)
6055 as_bad (_("No operator -- statement `%s'\n"), str
);
6061 CONST
struct thumb_opcode
* opcode
;
6065 opcode
= (CONST
struct thumb_opcode
*) hash_find (arm_tops_hsh
, str
);
6070 /* Check that this instruction is supported for this CPU. */
6071 if ((opcode
->variants
& cpu_variant
) == 0)
6073 as_bad (_("selected processor does not support this opcode"));
6077 inst
.instruction
= opcode
->value
;
6078 inst
.size
= opcode
->size
;
6079 (*opcode
->parms
)(p
);
6086 CONST
struct asm_opcode
* opcode
;
6087 unsigned long cond_code
;
6089 inst
.size
= INSN_SIZE
;
6090 /* p now points to the end of the opcode, probably white space, but we
6091 have to break the opcode up in case it contains condionals and flags;
6092 keep trying with progressively smaller basic instructions until one
6093 matches, or we run out of opcode. */
6094 q
= (p
- str
> LONGEST_INST
) ? str
+ LONGEST_INST
: p
;
6095 for (; q
!= str
; q
--)
6099 opcode
= (CONST
struct asm_opcode
*) hash_find (arm_ops_hsh
, str
);
6102 if (opcode
&& opcode
->template)
6104 unsigned long flag_bits
= 0;
6107 /* Check that this instruction is supported for this CPU. */
6108 if ((opcode
->variants
& cpu_variant
) == 0)
6111 inst
.instruction
= opcode
->value
;
6112 if (q
== p
) /* Just a simple opcode. */
6114 if (opcode
->comp_suffix
)
6116 if (*opcode
->comp_suffix
!= '\0')
6117 as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
6118 str
, opcode
->comp_suffix
);
6120 /* Not a conditional instruction. */
6121 (*opcode
->parms
)(q
, 0);
6125 /* A conditional instruction with default condition. */
6126 inst
.instruction
|= COND_ALWAYS
;
6127 (*opcode
->parms
)(q
, 0);
6133 /* Not just a simple opcode. Check if extra is a conditional. */
6137 CONST
struct asm_cond
*cond
;
6141 cond
= (CONST
struct asm_cond
*) hash_find (arm_cond_hsh
, r
);
6145 if (cond
->value
== 0xf0000000)
6147 _("Warning: Use of the 'nv' conditional is deprecated\n"));
6149 cond_code
= cond
->value
;
6153 cond_code
= COND_ALWAYS
;
6156 cond_code
= COND_ALWAYS
;
6159 /* Apply the conditional, or complain it's not allowed. */
6160 if (opcode
->comp_suffix
&& *opcode
->comp_suffix
== '\0')
6162 /* Instruction isn't conditional */
6163 if (cond_code
!= COND_ALWAYS
)
6165 as_bad (_("Opcode `%s' is unconditional\n"), str
);
6170 /* Instruction is conditional: set the condition into it. */
6171 inst
.instruction
|= cond_code
;
6174 /* If there is a compulsory suffix, it should come here, before
6175 any optional flags. */
6176 if (opcode
->comp_suffix
&& *opcode
->comp_suffix
!= '\0')
6178 CONST
char *s
= opcode
->comp_suffix
;
6190 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str
,
6191 opcode
->comp_suffix
);
6198 /* The remainder, if any should now be flags for the instruction;
6199 Scan these checking each one found with the opcode. */
6203 CONST
struct asm_flg
*flag
= opcode
->flags
;
6212 for (flagno
= 0; flag
[flagno
].template; flagno
++)
6214 if (streq (r
, flag
[flagno
].template))
6216 flag_bits
|= flag
[flagno
].set_bits
;
6222 if (! flag
[flagno
].template)
6229 (*opcode
->parms
) (p
, flag_bits
);
6239 /* It wasn't an instruction, but it might be a register alias of the form
6242 skip_whitespace (q
);
6247 if (*q
&& !strncmp (q
, ".req ", 4))
6250 char * copy_of_str
= str
;
6254 skip_whitespace (q
);
6256 for (r
= q
; *r
!= '\0'; r
++)
6266 regnum
= arm_reg_parse (& q
);
6269 reg
= arm_reg_parse (& str
);
6274 insert_reg_alias (str
, regnum
);
6276 as_warn (_("register '%s' does not exist\n"), q
);
6278 else if (regnum
!= FAIL
)
6281 as_warn (_("ignoring redefinition of register alias '%s'"), copy_of_str
);
6283 /* Do not warn about redefinitions to the same alias. */
6286 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6290 as_warn (_("ignoring incomplete .req pseuso op"));
6297 as_bad (_("bad instruction `%s'"), start
);
6302 * Invocation line includes a switch not recognized by the base assembler.
6303 * See if it's a processor-specific option. These are:
6304 * Cpu variants, the arm part is optional:
6305 * -m[arm]1 Currently not supported.
6306 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6307 * -m[arm]3 Arm 3 processor
6308 * -m[arm]6[xx], Arm 6 processors
6309 * -m[arm]7[xx][t][[d]m] Arm 7 processors
6310 * -m[arm]8[10] Arm 8 processors
6311 * -m[arm]9[20][tdmi] Arm 9 processors
6312 * -mstrongarm[110[0]] StrongARM processors
6313 * -m[arm]v[2345] Arm architectures
6314 * -mall All (except the ARM1)
6316 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6317 * -mfpe-old (No float load/store multiples)
6318 * -mno-fpu Disable all floating point instructions
6319 * Run-time endian selection:
6320 * -EB big endian cpu
6321 * -EL little endian cpu
6322 * ARM Procedure Calling Standard:
6323 * -mapcs-32 32 bit APCS
6324 * -mapcs-26 26 bit APCS
6325 * -mapcs-float Pass floats in float regs
6326 * -mapcs-reentrant Position independent code
6327 * -mthumb-interwork Code supports Arm/Thumb interworking
6328 * -moabi Old ELF ABI
6331 CONST
char * md_shortopts
= "m:k";
6332 struct option md_longopts
[] =
6334 #ifdef ARM_BI_ENDIAN
6335 #define OPTION_EB (OPTION_MD_BASE + 0)
6336 {"EB", no_argument
, NULL
, OPTION_EB
},
6337 #define OPTION_EL (OPTION_MD_BASE + 1)
6338 {"EL", no_argument
, NULL
, OPTION_EL
},
6340 #define OPTION_OABI (OPTION_MD_BASE +2)
6341 {"oabi", no_argument
, NULL
, OPTION_OABI
},
6344 {NULL
, no_argument
, NULL
, 0}
6346 size_t md_longopts_size
= sizeof (md_longopts
);
6349 md_parse_option (c
, arg
)
6357 #ifdef ARM_BI_ENDIAN
6359 target_big_endian
= 1;
6362 target_big_endian
= 0;
6370 if (streq (str
, "fpa10"))
6371 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_FPA10
;
6372 else if (streq (str
, "fpa11"))
6373 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_FPA11
;
6374 else if (streq (str
, "fpe-old"))
6375 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_CORE
;
6381 if (streq (str
, "no-fpu"))
6382 cpu_variant
&= ~FPU_ALL
;
6387 if (streq (str
, "oabi"))
6393 /* Limit assembler to generating only Thumb instructions: */
6394 if (streq (str
, "thumb"))
6396 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_THUMB
;
6397 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_NONE
;
6400 else if (streq (str
, "thumb-interwork"))
6402 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_THUMB
| ARM_ARCH_V4
;
6403 #if defined OBJ_COFF || defined OBJ_ELF
6404 support_interwork
= true;
6412 if (streq (str
, "all"))
6414 cpu_variant
= ARM_ALL
| FPU_ALL
;
6417 #if defined OBJ_COFF || defined OBJ_ELF
6418 if (! strncmp (str
, "apcs-", 5))
6420 /* GCC passes on all command line options starting "-mapcs-..."
6421 to us, so we must parse them here. */
6425 if (streq (str
, "32"))
6427 uses_apcs_26
= false;
6430 else if (streq (str
, "26"))
6432 uses_apcs_26
= true;
6435 else if (streq (str
, "frame"))
6437 /* Stack frames are being generated - does not affect
6441 else if (streq (str
, "stack-check"))
6443 /* Stack checking is being performed - does not affect
6444 linkage, but does require that the functions
6445 __rt_stkovf_split_small and __rt_stkovf_split_big be
6446 present in the final link. */
6450 else if (streq (str
, "float"))
6452 /* Floating point arguments are being passed in the floating
6453 point registers. This does affect linking, since this
6454 version of the APCS is incompatible with the version that
6455 passes floating points in the integer registers. */
6457 uses_apcs_float
= true;
6460 else if (streq (str
, "reentrant"))
6462 /* Reentrant code has been generated. This does affect
6463 linking, since there is no point in linking reentrant/
6464 position independent code with absolute position code. */
6469 as_bad (_("Unrecognised APCS switch -m%s"), arg
);
6473 /* Strip off optional "arm" */
6474 if (! strncmp (str
, "arm", 3))
6480 if (streq (str
, "1"))
6481 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_1
;
6487 if (streq (str
, "2"))
6488 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_2
;
6489 else if (streq (str
, "250"))
6490 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_250
;
6496 if (streq (str
, "3"))
6497 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_3
;
6503 switch (strtol (str
, NULL
, 10))
6510 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_6
;
6518 switch (strtol (str
, & str
, 10)) /* Eat the processor name */
6530 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
;
6536 cpu_variant
|= (ARM_THUMB
| ARM_ARCH_V4
);
6540 cpu_variant
|= ARM_LONGMUL
;
6543 case 'f': /* fe => fp enabled cpu. */
6549 case 'c': /* Left over from 710c processor name. */
6550 case 'd': /* Debug */
6551 case 'i': /* Embedded ICE */
6552 /* Included for completeness in ARM processor naming. */
6562 if (streq (str
, "8") || streq (str
, "810"))
6563 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_8
| ARM_ARCH_V4
| ARM_LONGMUL
;
6569 if (streq (str
, "9"))
6570 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_9
| ARM_ARCH_V4
| ARM_LONGMUL
| ARM_THUMB
;
6571 else if (streq (str
, "920"))
6572 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_9
| ARM_ARCH_V4
| ARM_LONGMUL
;
6573 else if (streq (str
, "920t"))
6574 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_9
| ARM_ARCH_V4
| ARM_LONGMUL
| ARM_THUMB
;
6575 else if (streq (str
, "9tdmi"))
6576 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_9
| ARM_ARCH_V4
| ARM_LONGMUL
| ARM_THUMB
;
6583 if (streq (str
, "strongarm")
6584 || streq (str
, "strongarm110")
6585 || streq (str
, "strongarm1100"))
6586 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_8
| ARM_ARCH_V4
| ARM_LONGMUL
;
6592 /* Select variant based on architecture rather than processor */
6598 case 'a': cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_3
; break;
6599 case 0: cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_2
; break;
6600 default: as_bad (_("Invalid architecture variant -m%s"), arg
); break;
6605 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
;
6609 case 'm': cpu_variant
|= ARM_LONGMUL
; break;
6611 default: as_bad (_("Invalid architecture variant -m%s"), arg
); break;
6616 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_ARCH_V4
;
6620 case 't': cpu_variant
|= ARM_THUMB
; break;
6622 default: as_bad (_("Invalid architecture variant -m%s"), arg
); break;
6627 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_ARCH_V5
;
6630 case 't': cpu_variant
|= ARM_THUMB
; break;
6631 case 'e': cpu_variant
|= ARM_EXT_V5E
; break;
6633 default: as_bad (_("Invalid architecture variant -m%s"), arg
); break;
6639 as_bad (_("Invalid architecture variant -m%s"), arg
);
6646 as_bad (_("Invalid processor variant -m%s"), arg
);
6652 #if defined OBJ_ELF || defined OBJ_COFF
6671 ARM Specific Assembler Options:\n\
6672 -m[arm][<processor name>] select processor variant\n\
6673 -m[arm]v[2|2a|3|3m|4|4t|5]select architecture variant\n\
6674 -mthumb only allow Thumb instructions\n\
6675 -mthumb-interwork mark the assembled code as supporting interworking\n\
6676 -mall allow any instruction\n\
6677 -mfpa10, -mfpa11 select floating point architecture\n\
6678 -mfpe-old don't allow floating-point multiple instructions\n\
6679 -mno-fpu don't allow any floating-point instructions.\n"));
6682 -k generate PIC code.\n"));
6683 #if defined OBJ_COFF || defined OBJ_ELF
6686 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n"));
6689 -mapcs-float floating point args are passed in FP regs\n"));
6692 -mapcs-reentrant the code is position independent/reentrant\n"));
6697 -moabi support the old ELF ABI\n"));
6699 #ifdef ARM_BI_ENDIAN
6702 -EB assemble code for a big endian cpu\n\
6703 -EL assemble code for a little endian cpu\n"));
6707 /* We need to be able to fix up arbitrary expressions in some statements.
6708 This is so that we can handle symbols that are an arbitrary distance from
6709 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
6710 which returns part of an address in a form which will be valid for
6711 a data instruction. We do this by pushing the expression into a symbol
6712 in the expr_section, and creating a fix for that. */
6715 fix_new_arm (frag
, where
, size
, exp
, pc_rel
, reloc
)
6724 arm_fix_data
* arm_data
;
6732 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
6736 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
6741 /* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
6742 arm_data
= (arm_fix_data
*) obstack_alloc (& notes
, sizeof (arm_fix_data
));
6743 new_fix
->tc_fix_data
= (PTR
) arm_data
;
6744 arm_data
->thumb_mode
= thumb_mode
;
6750 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6752 cons_fix_new_arm (frag
, where
, size
, exp
)
6758 bfd_reloc_code_real_type type
;
6763 * @@ Should look at CPU word size.
6768 type
= BFD_RELOC_16
;
6772 type
= BFD_RELOC_32
;
6775 type
= BFD_RELOC_64
;
6779 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
6782 /* A good place to do this, although this was probably not intended
6783 for this kind of use. We need to dump the literal pool before
6784 references are made to a null symbol pointer. */
6788 if (current_poolP
== NULL
)
6791 subseg_set (text_section
, 0); /* Put it at the end of text section. */
6793 listing_prev_line ();
6797 arm_start_line_hook ()
6799 last_label_seen
= NULL
;
6803 arm_frob_label (sym
)
6806 last_label_seen
= sym
;
6808 ARM_SET_THUMB (sym
, thumb_mode
);
6810 #if defined OBJ_COFF || defined OBJ_ELF
6811 ARM_SET_INTERWORK (sym
, support_interwork
);
6814 if (label_is_thumb_function_name
)
6816 /* When the address of a Thumb function is taken the bottom
6817 bit of that address should be set. This will allow
6818 interworking between Arm and Thumb functions to work
6821 THUMB_SET_FUNC (sym
, 1);
6823 label_is_thumb_function_name
= false;
6827 /* Adjust the symbol table. This marks Thumb symbols as distinct from
6831 arm_adjust_symtab ()
6836 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
6838 if (ARM_IS_THUMB (sym
))
6840 if (THUMB_IS_FUNC (sym
))
6842 /* Mark the symbol as a Thumb function. */
6843 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
6844 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
6845 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
6847 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
6848 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
6850 as_bad (_("%s: unexpected function type: %d"),
6851 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
6853 else switch (S_GET_STORAGE_CLASS (sym
))
6856 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
6859 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
6862 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
6864 default: /* do nothing */
6869 if (ARM_IS_INTERWORK (sym
))
6870 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
6875 elf_symbol_type
* elf_sym
;
6878 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
6880 if (ARM_IS_THUMB (sym
))
6882 if (THUMB_IS_FUNC (sym
))
6884 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
6885 bind
= ELF_ST_BIND (elf_sym
);
6886 elf_sym
->internal_elf_sym
.st_info
= ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
6896 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
6898 *input_line_pointer
= '/';
6899 input_line_pointer
+= 5;
6900 *input_line_pointer
= 0;
6908 arm_canonicalize_symbol_name (name
)
6913 if (thumb_mode
&& (len
= strlen (name
)) > 5
6914 && streq (name
+ len
- 5, "/data"))
6915 *(name
+ len
- 5) = 0;
6921 arm_validate_fix (fixP
)
6924 /* If the destination of the branch is a defined symbol which does not have
6925 the THUMB_FUNC attribute, then we must be calling a function which has
6926 the (interfacearm) attribute. We look for the Thumb entry point to that
6927 function and change the branch to refer to that function instead. */
6928 if ( fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
6929 && fixP
->fx_addsy
!= NULL
6930 && S_IS_DEFINED (fixP
->fx_addsy
)
6931 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
6933 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
6941 /* Relocations against Thumb function names must be left unadjusted,
6942 so that the linker can use this information to correctly set the
6943 bottom bit of their addresses. The MIPS version of this function
6944 also prevents relocations that are mips-16 specific, but I do not
6945 know why it does this.
6948 There is one other problem that ought to be addressed here, but
6949 which currently is not: Taking the address of a label (rather
6950 than a function) and then later jumping to that address. Such
6951 addresses also ought to have their bottom bit set (assuming that
6952 they reside in Thumb code), but at the moment they will not. */
6955 arm_fix_adjustable (fixP
)
6958 if (fixP
->fx_addsy
== NULL
)
6961 /* Prevent all adjustments to global symbols. */
6962 if (S_IS_EXTERN (fixP
->fx_addsy
))
6965 if (S_IS_WEAK (fixP
->fx_addsy
))
6968 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
6969 && fixP
->fx_subsy
== NULL
)
6972 /* We need the symbol name for the VTABLE entries */
6973 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
6974 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6981 elf32_arm_target_format ()
6983 if (target_big_endian
)
6985 return "elf32-bigarm-oabi";
6987 return "elf32-bigarm";
6990 return "elf32-littlearm-oabi";
6992 return "elf32-littlearm";
6996 armelf_frob_symbol (symp
, puntp
)
7000 elf_frob_symbol (symp
, puntp
);
7004 arm_force_relocation (fixp
)
7007 if ( fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
7008 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
7009 || fixp
->fx_r_type
== BFD_RELOC_ARM_PCREL_BRANCH
7010 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
)
7016 static bfd_reloc_code_real_type
7026 bfd_reloc_code_real_type reloc
;
7030 #define MAP(str,reloc) { str, sizeof (str)-1, reloc }
7031 MAP ("(got)", BFD_RELOC_ARM_GOT32
),
7032 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF
),
7033 /* ScottB: Jan 30, 1998 */
7034 /* Added support for parsing "var(PLT)" branch instructions */
7035 /* generated by GCC for PLT relocs */
7036 MAP ("(plt)", BFD_RELOC_ARM_PLT32
),
7037 { NULL
, 0, BFD_RELOC_UNUSED
}
7041 for (i
= 0, ip
= input_line_pointer
;
7042 i
< sizeof (id
) && (isalnum (*ip
) || ispunct (*ip
));
7044 id
[i
] = tolower (*ip
);
7046 for (i
= 0; reloc_map
[i
].str
; i
++)
7047 if (strncmp (id
, reloc_map
[i
].str
, reloc_map
[i
].len
) == 0)
7050 input_line_pointer
+= reloc_map
[i
].len
;
7052 return reloc_map
[i
].reloc
;
7056 s_arm_elf_cons (nbytes
)
7061 #ifdef md_flush_pending_output
7062 md_flush_pending_output ();
7065 if (is_it_end_of_statement ())
7067 demand_empty_rest_of_line ();
7071 #ifdef md_cons_align
7072 md_cons_align (nbytes
);
7077 bfd_reloc_code_real_type reloc
;
7081 if (exp
.X_op
== O_symbol
7082 && * input_line_pointer
== '('
7083 && (reloc
= arm_parse_reloc()) != BFD_RELOC_UNUSED
)
7085 reloc_howto_type
* howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
7086 int size
= bfd_get_reloc_size (howto
);
7089 as_bad ("%s relocations do not fit in %d bytes", howto
->name
, nbytes
);
7092 register char * p
= frag_more ((int) nbytes
);
7093 int offset
= nbytes
- size
;
7095 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
, size
,
7100 emit_expr (& exp
, (unsigned int) nbytes
);
7102 while (*input_line_pointer
++ == ',');
7104 input_line_pointer
--; /* Put terminator back into stream. */
7105 demand_empty_rest_of_line ();
7108 #endif /* OBJ_ELF */