1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, ARM_EXT2_V8M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
211 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
212 static const arm_feature_set arm_ext_v6t2_v8m
=
213 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
214 /* Instructions shared between ARMv8-A and ARMv8-M. */
215 static const arm_feature_set arm_ext_atomics
=
216 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
217 static const arm_feature_set arm_ext_v8_2
=
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
219 /* FP16 instructions. */
220 static const arm_feature_set arm_ext_fp16
=
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
223 static const arm_feature_set arm_arch_any
= ARM_ANY
;
224 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1, -1);
225 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
226 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
227 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
229 static const arm_feature_set arm_cext_iwmmxt2
=
230 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
231 static const arm_feature_set arm_cext_iwmmxt
=
232 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
233 static const arm_feature_set arm_cext_xscale
=
234 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
235 static const arm_feature_set arm_cext_maverick
=
236 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
237 static const arm_feature_set fpu_fpa_ext_v1
=
238 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
239 static const arm_feature_set fpu_fpa_ext_v2
=
240 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
241 static const arm_feature_set fpu_vfp_ext_v1xd
=
242 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
243 static const arm_feature_set fpu_vfp_ext_v1
=
244 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
245 static const arm_feature_set fpu_vfp_ext_v2
=
246 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
247 static const arm_feature_set fpu_vfp_ext_v3xd
=
248 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
249 static const arm_feature_set fpu_vfp_ext_v3
=
250 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
251 static const arm_feature_set fpu_vfp_ext_d32
=
252 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
253 static const arm_feature_set fpu_neon_ext_v1
=
254 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
255 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
256 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
257 static const arm_feature_set fpu_vfp_fp16
=
258 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
259 static const arm_feature_set fpu_neon_ext_fma
=
260 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
261 static const arm_feature_set fpu_vfp_ext_fma
=
262 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
263 static const arm_feature_set fpu_vfp_ext_armv8
=
264 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
265 static const arm_feature_set fpu_vfp_ext_armv8xd
=
266 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
267 static const arm_feature_set fpu_neon_ext_armv8
=
268 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
269 static const arm_feature_set fpu_crypto_ext_armv8
=
270 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
271 static const arm_feature_set crc_ext_armv8
=
272 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
273 static const arm_feature_set fpu_neon_ext_v8_1
=
274 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
276 static int mfloat_abi_opt
= -1;
277 /* Record user cpu selection for object attributes. */
278 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
279 /* Must be long enough to hold any of the names in arm_cpus. */
280 static char selected_cpu_name
[20];
282 extern FLONUM_TYPE generic_floating_point_number
;
284 /* Return if no cpu was selected on command-line. */
286 no_cpu_selected (void)
288 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
293 static int meabi_flags
= EABI_DEFAULT
;
295 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
298 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
303 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
308 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
309 symbolS
* GOT_symbol
;
312 /* 0: assemble for ARM,
313 1: assemble for Thumb,
314 2: assemble for Thumb even though target CPU does not support thumb
316 static int thumb_mode
= 0;
317 /* A value distinct from the possible values for thumb_mode that we
318 can use to record whether thumb_mode has been copied into the
319 tc_frag_data field of a frag. */
320 #define MODE_RECORDED (1 << 4)
322 /* Specifies the intrinsic IT insn behavior mode. */
323 enum implicit_it_mode
325 IMPLICIT_IT_MODE_NEVER
= 0x00,
326 IMPLICIT_IT_MODE_ARM
= 0x01,
327 IMPLICIT_IT_MODE_THUMB
= 0x02,
328 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
330 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
332 /* If unified_syntax is true, we are processing the new unified
333 ARM/Thumb syntax. Important differences from the old ARM mode:
335 - Immediate operands do not require a # prefix.
336 - Conditional affixes always appear at the end of the
337 instruction. (For backward compatibility, those instructions
338 that formerly had them in the middle, continue to accept them
340 - The IT instruction may appear, and if it does is validated
341 against subsequent conditional affixes. It does not generate
344 Important differences from the old Thumb mode:
346 - Immediate operands do not require a # prefix.
347 - Most of the V6T2 instructions are only available in unified mode.
348 - The .N and .W suffixes are recognized and honored (it is an error
349 if they cannot be honored).
350 - All instructions set the flags if and only if they have an 's' affix.
351 - Conditional affixes may be used. They are validated against
352 preceding IT instructions. Unlike ARM mode, you cannot use a
353 conditional affix except in the scope of an IT instruction. */
355 static bfd_boolean unified_syntax
= FALSE
;
357 /* An immediate operand can start with #, and ld*, st*, pld operands
358 can contain [ and ]. We need to tell APP not to elide whitespace
359 before a [, which can appear as the first operand for pld.
360 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
361 const char arm_symbol_chars
[] = "#[]{}";
376 enum neon_el_type type
;
380 #define NEON_MAX_TYPE_ELS 4
384 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
388 enum it_instruction_type
393 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
394 if inside, should be the last one. */
395 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
396 i.e. BKPT and NOP. */
397 IT_INSN
/* The IT insn has been parsed. */
400 /* The maximum number of operands we need. */
401 #define ARM_IT_MAX_OPERANDS 6
406 unsigned long instruction
;
410 /* "uncond_value" is set to the value in place of the conditional field in
411 unconditional versions of the instruction, or -1 if nothing is
414 struct neon_type vectype
;
415 /* This does not indicate an actual NEON instruction, only that
416 the mnemonic accepts neon-style type suffixes. */
418 /* Set to the opcode if the instruction needs relaxation.
419 Zero if the instruction is not relaxed. */
423 bfd_reloc_code_real_type type
;
428 enum it_instruction_type it_insn_type
;
434 struct neon_type_el vectype
;
435 unsigned present
: 1; /* Operand present. */
436 unsigned isreg
: 1; /* Operand was a register. */
437 unsigned immisreg
: 1; /* .imm field is a second register. */
438 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
439 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
440 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
441 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
442 instructions. This allows us to disambiguate ARM <-> vector insns. */
443 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
444 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
445 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
446 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
447 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
448 unsigned writeback
: 1; /* Operand has trailing ! */
449 unsigned preind
: 1; /* Preindexed address. */
450 unsigned postind
: 1; /* Postindexed address. */
451 unsigned negative
: 1; /* Index register was negated. */
452 unsigned shifted
: 1; /* Shift applied to operation. */
453 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
454 } operands
[ARM_IT_MAX_OPERANDS
];
457 static struct arm_it inst
;
459 #define NUM_FLOAT_VALS 8
461 const char * fp_const
[] =
463 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
466 /* Number of littlenums required to hold an extended precision number. */
467 #define MAX_LITTLENUMS 6
469 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
479 #define CP_T_X 0x00008000
480 #define CP_T_Y 0x00400000
482 #define CONDS_BIT 0x00100000
483 #define LOAD_BIT 0x00100000
485 #define DOUBLE_LOAD_FLAG 0x00000001
489 const char * template_name
;
493 #define COND_ALWAYS 0xE
497 const char * template_name
;
501 struct asm_barrier_opt
503 const char * template_name
;
505 const arm_feature_set arch
;
508 /* The bit that distinguishes CPSR and SPSR. */
509 #define SPSR_BIT (1 << 22)
511 /* The individual PSR flag bits. */
512 #define PSR_c (1 << 16)
513 #define PSR_x (1 << 17)
514 #define PSR_s (1 << 18)
515 #define PSR_f (1 << 19)
520 bfd_reloc_code_real_type reloc
;
525 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
526 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
531 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
534 /* Bits for DEFINED field in neon_typed_alias. */
535 #define NTA_HASTYPE 1
536 #define NTA_HASINDEX 2
538 struct neon_typed_alias
540 unsigned char defined
;
542 struct neon_type_el eltype
;
545 /* ARM register categories. This includes coprocessor numbers and various
546 architecture extensions' registers. */
573 /* Structure for a hash table entry for a register.
574 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
575 information which states whether a vector type or index is specified (for a
576 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
582 unsigned char builtin
;
583 struct neon_typed_alias
* neon
;
586 /* Diagnostics used when we don't get a register of the expected type. */
587 const char * const reg_expected_msgs
[] =
589 N_("ARM register expected"),
590 N_("bad or missing co-processor number"),
591 N_("co-processor register expected"),
592 N_("FPA register expected"),
593 N_("VFP single precision register expected"),
594 N_("VFP/Neon double precision register expected"),
595 N_("Neon quad precision register expected"),
596 N_("VFP single or double precision register expected"),
597 N_("Neon double or quad precision register expected"),
598 N_("VFP single, double or Neon quad precision register expected"),
599 N_("VFP system register expected"),
600 N_("Maverick MVF register expected"),
601 N_("Maverick MVD register expected"),
602 N_("Maverick MVFX register expected"),
603 N_("Maverick MVDX register expected"),
604 N_("Maverick MVAX register expected"),
605 N_("Maverick DSPSC register expected"),
606 N_("iWMMXt data register expected"),
607 N_("iWMMXt control register expected"),
608 N_("iWMMXt scalar register expected"),
609 N_("XScale accumulator register expected"),
612 /* Some well known registers that we refer to directly elsewhere. */
618 /* ARM instructions take 4bytes in the object file, Thumb instructions
624 /* Basic string to match. */
625 const char * template_name
;
627 /* Parameters to instruction. */
628 unsigned int operands
[8];
630 /* Conditional tag - see opcode_lookup. */
631 unsigned int tag
: 4;
633 /* Basic instruction code. */
634 unsigned int avalue
: 28;
636 /* Thumb-format instruction code. */
639 /* Which architecture variant provides this instruction. */
640 const arm_feature_set
* avariant
;
641 const arm_feature_set
* tvariant
;
643 /* Function to call to encode instruction in ARM format. */
644 void (* aencode
) (void);
646 /* Function to call to encode instruction in Thumb format. */
647 void (* tencode
) (void);
650 /* Defines for various bits that we will want to toggle. */
651 #define INST_IMMEDIATE 0x02000000
652 #define OFFSET_REG 0x02000000
653 #define HWOFFSET_IMM 0x00400000
654 #define SHIFT_BY_REG 0x00000010
655 #define PRE_INDEX 0x01000000
656 #define INDEX_UP 0x00800000
657 #define WRITE_BACK 0x00200000
658 #define LDM_TYPE_2_OR_3 0x00400000
659 #define CPSI_MMOD 0x00020000
661 #define LITERAL_MASK 0xf000f000
662 #define OPCODE_MASK 0xfe1fffff
663 #define V4_STR_BIT 0x00000020
664 #define VLDR_VMOV_SAME 0x0040f000
666 #define T2_SUBS_PC_LR 0xf3de8f00
668 #define DATA_OP_SHIFT 21
670 #define T2_OPCODE_MASK 0xfe1fffff
671 #define T2_DATA_OP_SHIFT 21
673 #define A_COND_MASK 0xf0000000
674 #define A_PUSH_POP_OP_MASK 0x0fff0000
676 /* Opcodes for pushing/poping registers to/from the stack. */
677 #define A1_OPCODE_PUSH 0x092d0000
678 #define A2_OPCODE_PUSH 0x052d0004
679 #define A2_OPCODE_POP 0x049d0004
681 /* Codes to distinguish the arithmetic instructions. */
692 #define OPCODE_CMP 10
693 #define OPCODE_CMN 11
694 #define OPCODE_ORR 12
695 #define OPCODE_MOV 13
696 #define OPCODE_BIC 14
697 #define OPCODE_MVN 15
699 #define T2_OPCODE_AND 0
700 #define T2_OPCODE_BIC 1
701 #define T2_OPCODE_ORR 2
702 #define T2_OPCODE_ORN 3
703 #define T2_OPCODE_EOR 4
704 #define T2_OPCODE_ADD 8
705 #define T2_OPCODE_ADC 10
706 #define T2_OPCODE_SBC 11
707 #define T2_OPCODE_SUB 13
708 #define T2_OPCODE_RSB 14
710 #define T_OPCODE_MUL 0x4340
711 #define T_OPCODE_TST 0x4200
712 #define T_OPCODE_CMN 0x42c0
713 #define T_OPCODE_NEG 0x4240
714 #define T_OPCODE_MVN 0x43c0
716 #define T_OPCODE_ADD_R3 0x1800
717 #define T_OPCODE_SUB_R3 0x1a00
718 #define T_OPCODE_ADD_HI 0x4400
719 #define T_OPCODE_ADD_ST 0xb000
720 #define T_OPCODE_SUB_ST 0xb080
721 #define T_OPCODE_ADD_SP 0xa800
722 #define T_OPCODE_ADD_PC 0xa000
723 #define T_OPCODE_ADD_I8 0x3000
724 #define T_OPCODE_SUB_I8 0x3800
725 #define T_OPCODE_ADD_I3 0x1c00
726 #define T_OPCODE_SUB_I3 0x1e00
728 #define T_OPCODE_ASR_R 0x4100
729 #define T_OPCODE_LSL_R 0x4080
730 #define T_OPCODE_LSR_R 0x40c0
731 #define T_OPCODE_ROR_R 0x41c0
732 #define T_OPCODE_ASR_I 0x1000
733 #define T_OPCODE_LSL_I 0x0000
734 #define T_OPCODE_LSR_I 0x0800
736 #define T_OPCODE_MOV_I8 0x2000
737 #define T_OPCODE_CMP_I8 0x2800
738 #define T_OPCODE_CMP_LR 0x4280
739 #define T_OPCODE_MOV_HR 0x4600
740 #define T_OPCODE_CMP_HR 0x4500
742 #define T_OPCODE_LDR_PC 0x4800
743 #define T_OPCODE_LDR_SP 0x9800
744 #define T_OPCODE_STR_SP 0x9000
745 #define T_OPCODE_LDR_IW 0x6800
746 #define T_OPCODE_STR_IW 0x6000
747 #define T_OPCODE_LDR_IH 0x8800
748 #define T_OPCODE_STR_IH 0x8000
749 #define T_OPCODE_LDR_IB 0x7800
750 #define T_OPCODE_STR_IB 0x7000
751 #define T_OPCODE_LDR_RW 0x5800
752 #define T_OPCODE_STR_RW 0x5000
753 #define T_OPCODE_LDR_RH 0x5a00
754 #define T_OPCODE_STR_RH 0x5200
755 #define T_OPCODE_LDR_RB 0x5c00
756 #define T_OPCODE_STR_RB 0x5400
758 #define T_OPCODE_PUSH 0xb400
759 #define T_OPCODE_POP 0xbc00
761 #define T_OPCODE_BRANCH 0xe000
763 #define THUMB_SIZE 2 /* Size of thumb instruction. */
764 #define THUMB_PP_PC_LR 0x0100
765 #define THUMB_LOAD_BIT 0x0800
766 #define THUMB2_LOAD_BIT 0x00100000
768 #define BAD_ARGS _("bad arguments to instruction")
769 #define BAD_SP _("r13 not allowed here")
770 #define BAD_PC _("r15 not allowed here")
771 #define BAD_COND _("instruction cannot be conditional")
772 #define BAD_OVERLAP _("registers may not be the same")
773 #define BAD_HIREG _("lo register required")
774 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
775 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
776 #define BAD_BRANCH _("branch must be last instruction in IT block")
777 #define BAD_NOT_IT _("instruction not allowed in IT block")
778 #define BAD_FPU _("selected FPU does not support instruction")
779 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
780 #define BAD_IT_COND _("incorrect condition in IT block")
781 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
782 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
783 #define BAD_PC_ADDRESSING \
784 _("cannot use register index with PC-relative addressing")
785 #define BAD_PC_WRITEBACK \
786 _("cannot use writeback with PC-relative addressing")
787 #define BAD_RANGE _("branch out of range")
788 #define BAD_FP16 _("selected processor does not support fp16 instruction")
789 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
791 static struct hash_control
* arm_ops_hsh
;
792 static struct hash_control
* arm_cond_hsh
;
793 static struct hash_control
* arm_shift_hsh
;
794 static struct hash_control
* arm_psr_hsh
;
795 static struct hash_control
* arm_v7m_psr_hsh
;
796 static struct hash_control
* arm_reg_hsh
;
797 static struct hash_control
* arm_reloc_hsh
;
798 static struct hash_control
* arm_barrier_opt_hsh
;
800 /* Stuff needed to resolve the label ambiguity
809 symbolS
* last_label_seen
;
810 static int label_is_thumb_function_name
= FALSE
;
812 /* Literal pool structure. Held on a per-section
813 and per-sub-section basis. */
815 #define MAX_LITERAL_POOL_SIZE 1024
816 typedef struct literal_pool
818 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
819 unsigned int next_free_entry
;
825 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
827 struct literal_pool
* next
;
828 unsigned int alignment
;
831 /* Pointer to a linked list of literal pools. */
832 literal_pool
* list_of_pools
= NULL
;
834 typedef enum asmfunc_states
837 WAITING_ASMFUNC_NAME
,
841 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
844 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
846 static struct current_it now_it
;
850 now_it_compatible (int cond
)
852 return (cond
& ~1) == (now_it
.cc
& ~1);
856 conditional_insn (void)
858 return inst
.cond
!= COND_ALWAYS
;
861 static int in_it_block (void);
863 static int handle_it_state (void);
865 static void force_automatic_it_block_close (void);
867 static void it_fsm_post_encode (void);
869 #define set_it_insn_type(type) \
872 inst.it_insn_type = type; \
873 if (handle_it_state () == FAIL) \
878 #define set_it_insn_type_nonvoid(type, failret) \
881 inst.it_insn_type = type; \
882 if (handle_it_state () == FAIL) \
887 #define set_it_insn_type_last() \
890 if (inst.cond == COND_ALWAYS) \
891 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
893 set_it_insn_type (INSIDE_IT_LAST_INSN); \
899 /* This array holds the chars that always start a comment. If the
900 pre-processor is disabled, these aren't very useful. */
901 char arm_comment_chars
[] = "@";
903 /* This array holds the chars that only start a comment at the beginning of
904 a line. If the line seems to have the form '# 123 filename'
905 .line and .file directives will appear in the pre-processed output. */
906 /* Note that input_file.c hand checks for '#' at the beginning of the
907 first line of the input file. This is because the compiler outputs
908 #NO_APP at the beginning of its output. */
909 /* Also note that comments like this one will always work. */
910 const char line_comment_chars
[] = "#";
912 char arm_line_separator_chars
[] = ";";
914 /* Chars that can be used to separate mant
915 from exp in floating point numbers. */
916 const char EXP_CHARS
[] = "eE";
918 /* Chars that mean this number is a floating point constant. */
922 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
924 /* Prefix characters that indicate the start of an immediate
926 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
928 /* Separator character handling. */
930 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
933 skip_past_char (char ** str
, char c
)
935 /* PR gas/14987: Allow for whitespace before the expected character. */
936 skip_whitespace (*str
);
947 #define skip_past_comma(str) skip_past_char (str, ',')
949 /* Arithmetic expressions (possibly involving symbols). */
951 /* Return TRUE if anything in the expression is a bignum. */
954 walk_no_bignums (symbolS
* sp
)
956 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
959 if (symbol_get_value_expression (sp
)->X_add_symbol
)
961 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
962 || (symbol_get_value_expression (sp
)->X_op_symbol
963 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
969 static int in_my_get_expression
= 0;
971 /* Third argument to my_get_expression. */
972 #define GE_NO_PREFIX 0
973 #define GE_IMM_PREFIX 1
974 #define GE_OPT_PREFIX 2
975 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
976 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
977 #define GE_OPT_PREFIX_BIG 3
980 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
985 /* In unified syntax, all prefixes are optional. */
987 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
992 case GE_NO_PREFIX
: break;
994 if (!is_immediate_prefix (**str
))
996 inst
.error
= _("immediate expression requires a # prefix");
1002 case GE_OPT_PREFIX_BIG
:
1003 if (is_immediate_prefix (**str
))
1009 memset (ep
, 0, sizeof (expressionS
));
1011 save_in
= input_line_pointer
;
1012 input_line_pointer
= *str
;
1013 in_my_get_expression
= 1;
1014 seg
= expression (ep
);
1015 in_my_get_expression
= 0;
1017 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1019 /* We found a bad or missing expression in md_operand(). */
1020 *str
= input_line_pointer
;
1021 input_line_pointer
= save_in
;
1022 if (inst
.error
== NULL
)
1023 inst
.error
= (ep
->X_op
== O_absent
1024 ? _("missing expression") :_("bad expression"));
1029 if (seg
!= absolute_section
1030 && seg
!= text_section
1031 && seg
!= data_section
1032 && seg
!= bss_section
1033 && seg
!= undefined_section
)
1035 inst
.error
= _("bad segment");
1036 *str
= input_line_pointer
;
1037 input_line_pointer
= save_in
;
1044 /* Get rid of any bignums now, so that we don't generate an error for which
1045 we can't establish a line number later on. Big numbers are never valid
1046 in instructions, which is where this routine is always called. */
1047 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1048 && (ep
->X_op
== O_big
1049 || (ep
->X_add_symbol
1050 && (walk_no_bignums (ep
->X_add_symbol
)
1052 && walk_no_bignums (ep
->X_op_symbol
))))))
1054 inst
.error
= _("invalid constant");
1055 *str
= input_line_pointer
;
1056 input_line_pointer
= save_in
;
1060 *str
= input_line_pointer
;
1061 input_line_pointer
= save_in
;
1065 /* Turn a string in input_line_pointer into a floating point constant
1066 of type TYPE, and store the appropriate bytes in *LITP. The number
1067 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1068 returned, or NULL on OK.
1070 Note that fp constants aren't represent in the normal way on the ARM.
1071 In big endian mode, things are as expected. However, in little endian
1072 mode fp constants are big-endian word-wise, and little-endian byte-wise
1073 within the words. For example, (double) 1.1 in big endian mode is
1074 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1075 the byte sequence 99 99 f1 3f 9a 99 99 99.
1077 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1080 md_atof (int type
, char * litP
, int * sizeP
)
1083 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1115 return _("Unrecognized or unsupported floating point constant");
1118 t
= atof_ieee (input_line_pointer
, type
, words
);
1120 input_line_pointer
= t
;
1121 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1123 if (target_big_endian
)
1125 for (i
= 0; i
< prec
; i
++)
1127 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1128 litP
+= sizeof (LITTLENUM_TYPE
);
1133 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1134 for (i
= prec
- 1; i
>= 0; i
--)
1136 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1137 litP
+= sizeof (LITTLENUM_TYPE
);
1140 /* For a 4 byte float the order of elements in `words' is 1 0.
1141 For an 8 byte float the order is 1 0 3 2. */
1142 for (i
= 0; i
< prec
; i
+= 2)
1144 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1145 sizeof (LITTLENUM_TYPE
));
1146 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1147 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1148 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1155 /* We handle all bad expressions here, so that we can report the faulty
1156 instruction in the error message. */
1158 md_operand (expressionS
* exp
)
1160 if (in_my_get_expression
)
1161 exp
->X_op
= O_illegal
;
1164 /* Immediate values. */
1166 /* Generic immediate-value read function for use in directives.
1167 Accepts anything that 'expression' can fold to a constant.
1168 *val receives the number. */
1171 immediate_for_directive (int *val
)
1174 exp
.X_op
= O_illegal
;
1176 if (is_immediate_prefix (*input_line_pointer
))
1178 input_line_pointer
++;
1182 if (exp
.X_op
!= O_constant
)
1184 as_bad (_("expected #constant"));
1185 ignore_rest_of_line ();
1188 *val
= exp
.X_add_number
;
1193 /* Register parsing. */
1195 /* Generic register parser. CCP points to what should be the
1196 beginning of a register name. If it is indeed a valid register
1197 name, advance CCP over it and return the reg_entry structure;
1198 otherwise return NULL. Does not issue diagnostics. */
1200 static struct reg_entry
*
1201 arm_reg_parse_multi (char **ccp
)
1205 struct reg_entry
*reg
;
1207 skip_whitespace (start
);
1209 #ifdef REGISTER_PREFIX
1210 if (*start
!= REGISTER_PREFIX
)
1214 #ifdef OPTIONAL_REGISTER_PREFIX
1215 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1220 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1225 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1227 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1237 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1238 enum arm_reg_type type
)
1240 /* Alternative syntaxes are accepted for a few register classes. */
1247 /* Generic coprocessor register names are allowed for these. */
1248 if (reg
&& reg
->type
== REG_TYPE_CN
)
1253 /* For backward compatibility, a bare number is valid here. */
1255 unsigned long processor
= strtoul (start
, ccp
, 10);
1256 if (*ccp
!= start
&& processor
<= 15)
1260 case REG_TYPE_MMXWC
:
1261 /* WC includes WCG. ??? I'm not sure this is true for all
1262 instructions that take WC registers. */
1263 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1274 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1275 return value is the register number or FAIL. */
1278 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1281 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1284 /* Do not allow a scalar (reg+index) to parse as a register. */
1285 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1288 if (reg
&& reg
->type
== type
)
1291 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1298 /* Parse a Neon type specifier. *STR should point at the leading '.'
1299 character. Does no verification at this stage that the type fits the opcode
1306 Can all be legally parsed by this function.
1308 Fills in neon_type struct pointer with parsed information, and updates STR
1309 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1310 type, FAIL if not. */
1313 parse_neon_type (struct neon_type
*type
, char **str
)
1320 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1322 enum neon_el_type thistype
= NT_untyped
;
1323 unsigned thissize
= -1u;
1330 /* Just a size without an explicit type. */
1334 switch (TOLOWER (*ptr
))
1336 case 'i': thistype
= NT_integer
; break;
1337 case 'f': thistype
= NT_float
; break;
1338 case 'p': thistype
= NT_poly
; break;
1339 case 's': thistype
= NT_signed
; break;
1340 case 'u': thistype
= NT_unsigned
; break;
1342 thistype
= NT_float
;
1347 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1353 /* .f is an abbreviation for .f32. */
1354 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1359 thissize
= strtoul (ptr
, &ptr
, 10);
1361 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1364 as_bad (_("bad size %d in type specifier"), thissize
);
1372 type
->el
[type
->elems
].type
= thistype
;
1373 type
->el
[type
->elems
].size
= thissize
;
1378 /* Empty/missing type is not a successful parse. */
1379 if (type
->elems
== 0)
1387 /* Errors may be set multiple times during parsing or bit encoding
1388 (particularly in the Neon bits), but usually the earliest error which is set
1389 will be the most meaningful. Avoid overwriting it with later (cascading)
1390 errors by calling this function. */
1393 first_error (const char *err
)
1399 /* Parse a single type, e.g. ".s32", leading period included. */
1401 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1404 struct neon_type optype
;
1408 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1410 if (optype
.elems
== 1)
1411 *vectype
= optype
.el
[0];
1414 first_error (_("only one type should be specified for operand"));
1420 first_error (_("vector type expected"));
1432 /* Special meanings for indices (which have a range of 0-7), which will fit into
1435 #define NEON_ALL_LANES 15
1436 #define NEON_INTERLEAVE_LANES 14
1438 /* Parse either a register or a scalar, with an optional type. Return the
1439 register number, and optionally fill in the actual type of the register
1440 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1441 type/index information in *TYPEINFO. */
1444 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1445 enum arm_reg_type
*rtype
,
1446 struct neon_typed_alias
*typeinfo
)
1449 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1450 struct neon_typed_alias atype
;
1451 struct neon_type_el parsetype
;
1455 atype
.eltype
.type
= NT_invtype
;
1456 atype
.eltype
.size
= -1;
1458 /* Try alternate syntax for some types of register. Note these are mutually
1459 exclusive with the Neon syntax extensions. */
1462 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1470 /* Undo polymorphism when a set of register types may be accepted. */
1471 if ((type
== REG_TYPE_NDQ
1472 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1473 || (type
== REG_TYPE_VFSD
1474 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1475 || (type
== REG_TYPE_NSDQ
1476 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1477 || reg
->type
== REG_TYPE_NQ
))
1478 || (type
== REG_TYPE_MMXWC
1479 && (reg
->type
== REG_TYPE_MMXWCG
)))
1480 type
= (enum arm_reg_type
) reg
->type
;
1482 if (type
!= reg
->type
)
1488 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1490 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1492 first_error (_("can't redefine type for operand"));
1495 atype
.defined
|= NTA_HASTYPE
;
1496 atype
.eltype
= parsetype
;
1499 if (skip_past_char (&str
, '[') == SUCCESS
)
1501 if (type
!= REG_TYPE_VFD
)
1503 first_error (_("only D registers may be indexed"));
1507 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1509 first_error (_("can't change index for operand"));
1513 atype
.defined
|= NTA_HASINDEX
;
1515 if (skip_past_char (&str
, ']') == SUCCESS
)
1516 atype
.index
= NEON_ALL_LANES
;
1521 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1523 if (exp
.X_op
!= O_constant
)
1525 first_error (_("constant expression required"));
1529 if (skip_past_char (&str
, ']') == FAIL
)
1532 atype
.index
= exp
.X_add_number
;
1547 /* Like arm_reg_parse, but allow allow the following extra features:
1548 - If RTYPE is non-zero, return the (possibly restricted) type of the
1549 register (e.g. Neon double or quad reg when either has been requested).
1550 - If this is a Neon vector type with additional type information, fill
1551 in the struct pointed to by VECTYPE (if non-NULL).
1552 This function will fault on encountering a scalar. */
1555 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1556 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1558 struct neon_typed_alias atype
;
1560 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1565 /* Do not allow regname(... to parse as a register. */
1569 /* Do not allow a scalar (reg+index) to parse as a register. */
1570 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1572 first_error (_("register operand expected, but got scalar"));
1577 *vectype
= atype
.eltype
;
1584 #define NEON_SCALAR_REG(X) ((X) >> 4)
1585 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1587 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1588 have enough information to be able to do a good job bounds-checking. So, we
1589 just do easy checks here, and do further checks later. */
1592 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1596 struct neon_typed_alias atype
;
1598 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1600 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1603 if (atype
.index
== NEON_ALL_LANES
)
1605 first_error (_("scalar must have an index"));
1608 else if (atype
.index
>= 64 / elsize
)
1610 first_error (_("scalar index out of range"));
1615 *type
= atype
.eltype
;
1619 return reg
* 16 + atype
.index
;
1622 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1625 parse_reg_list (char ** strp
)
1627 char * str
= * strp
;
1631 /* We come back here if we get ranges concatenated by '+' or '|'. */
1634 skip_whitespace (str
);
1648 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1650 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1660 first_error (_("bad range in register list"));
1664 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1666 if (range
& (1 << i
))
1668 (_("Warning: duplicated register (r%d) in register list"),
1676 if (range
& (1 << reg
))
1677 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1679 else if (reg
<= cur_reg
)
1680 as_tsktsk (_("Warning: register range not in ascending order"));
1685 while (skip_past_comma (&str
) != FAIL
1686 || (in_range
= 1, *str
++ == '-'));
1689 if (skip_past_char (&str
, '}') == FAIL
)
1691 first_error (_("missing `}'"));
1699 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1702 if (exp
.X_op
== O_constant
)
1704 if (exp
.X_add_number
1705 != (exp
.X_add_number
& 0x0000ffff))
1707 inst
.error
= _("invalid register mask");
1711 if ((range
& exp
.X_add_number
) != 0)
1713 int regno
= range
& exp
.X_add_number
;
1716 regno
= (1 << regno
) - 1;
1718 (_("Warning: duplicated register (r%d) in register list"),
1722 range
|= exp
.X_add_number
;
1726 if (inst
.reloc
.type
!= 0)
1728 inst
.error
= _("expression too complex");
1732 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1733 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1734 inst
.reloc
.pc_rel
= 0;
1738 if (*str
== '|' || *str
== '+')
1744 while (another_range
);
1750 /* Types of registers in a list. */
1759 /* Parse a VFP register list. If the string is invalid return FAIL.
1760 Otherwise return the number of registers, and set PBASE to the first
1761 register. Parses registers of type ETYPE.
1762 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1763 - Q registers can be used to specify pairs of D registers
1764 - { } can be omitted from around a singleton register list
1765 FIXME: This is not implemented, as it would require backtracking in
1768 This could be done (the meaning isn't really ambiguous), but doesn't
1769 fit in well with the current parsing framework.
1770 - 32 D registers may be used (also true for VFPv3).
1771 FIXME: Types are ignored in these register lists, which is probably a
1775 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1780 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1784 unsigned long mask
= 0;
1787 if (skip_past_char (&str
, '{') == FAIL
)
1789 inst
.error
= _("expecting {");
1796 regtype
= REG_TYPE_VFS
;
1801 regtype
= REG_TYPE_VFD
;
1804 case REGLIST_NEON_D
:
1805 regtype
= REG_TYPE_NDQ
;
1809 if (etype
!= REGLIST_VFP_S
)
1811 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1812 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1816 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1819 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1826 base_reg
= max_regs
;
1830 int setmask
= 1, addregs
= 1;
1832 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1834 if (new_base
== FAIL
)
1836 first_error (_(reg_expected_msgs
[regtype
]));
1840 if (new_base
>= max_regs
)
1842 first_error (_("register out of range in list"));
1846 /* Note: a value of 2 * n is returned for the register Q<n>. */
1847 if (regtype
== REG_TYPE_NQ
)
1853 if (new_base
< base_reg
)
1854 base_reg
= new_base
;
1856 if (mask
& (setmask
<< new_base
))
1858 first_error (_("invalid register list"));
1862 if ((mask
>> new_base
) != 0 && ! warned
)
1864 as_tsktsk (_("register list not in ascending order"));
1868 mask
|= setmask
<< new_base
;
1871 if (*str
== '-') /* We have the start of a range expression */
1877 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1880 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1884 if (high_range
>= max_regs
)
1886 first_error (_("register out of range in list"));
1890 if (regtype
== REG_TYPE_NQ
)
1891 high_range
= high_range
+ 1;
1893 if (high_range
<= new_base
)
1895 inst
.error
= _("register range not in ascending order");
1899 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1901 if (mask
& (setmask
<< new_base
))
1903 inst
.error
= _("invalid register list");
1907 mask
|= setmask
<< new_base
;
1912 while (skip_past_comma (&str
) != FAIL
);
1916 /* Sanity check -- should have raised a parse error above. */
1917 if (count
== 0 || count
> max_regs
)
1922 /* Final test -- the registers must be consecutive. */
1924 for (i
= 0; i
< count
; i
++)
1926 if ((mask
& (1u << i
)) == 0)
1928 inst
.error
= _("non-contiguous register range");
1938 /* True if two alias types are the same. */
1941 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1949 if (a
->defined
!= b
->defined
)
1952 if ((a
->defined
& NTA_HASTYPE
) != 0
1953 && (a
->eltype
.type
!= b
->eltype
.type
1954 || a
->eltype
.size
!= b
->eltype
.size
))
1957 if ((a
->defined
& NTA_HASINDEX
) != 0
1958 && (a
->index
!= b
->index
))
1964 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1965 The base register is put in *PBASE.
1966 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1968 The register stride (minus one) is put in bit 4 of the return value.
1969 Bits [6:5] encode the list length (minus one).
1970 The type of the list elements is put in *ELTYPE, if non-NULL. */
1972 #define NEON_LANE(X) ((X) & 0xf)
1973 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1974 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1977 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1978 struct neon_type_el
*eltype
)
1985 int leading_brace
= 0;
1986 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1987 const char *const incr_error
= _("register stride must be 1 or 2");
1988 const char *const type_error
= _("mismatched element/structure types in list");
1989 struct neon_typed_alias firsttype
;
1991 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1996 struct neon_typed_alias atype
;
1997 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2001 first_error (_(reg_expected_msgs
[rtype
]));
2008 if (rtype
== REG_TYPE_NQ
)
2014 else if (reg_incr
== -1)
2016 reg_incr
= getreg
- base_reg
;
2017 if (reg_incr
< 1 || reg_incr
> 2)
2019 first_error (_(incr_error
));
2023 else if (getreg
!= base_reg
+ reg_incr
* count
)
2025 first_error (_(incr_error
));
2029 if (! neon_alias_types_same (&atype
, &firsttype
))
2031 first_error (_(type_error
));
2035 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2039 struct neon_typed_alias htype
;
2040 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2042 lane
= NEON_INTERLEAVE_LANES
;
2043 else if (lane
!= NEON_INTERLEAVE_LANES
)
2045 first_error (_(type_error
));
2050 else if (reg_incr
!= 1)
2052 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2056 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2059 first_error (_(reg_expected_msgs
[rtype
]));
2062 if (! neon_alias_types_same (&htype
, &firsttype
))
2064 first_error (_(type_error
));
2067 count
+= hireg
+ dregs
- getreg
;
2071 /* If we're using Q registers, we can't use [] or [n] syntax. */
2072 if (rtype
== REG_TYPE_NQ
)
2078 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2082 else if (lane
!= atype
.index
)
2084 first_error (_(type_error
));
2088 else if (lane
== -1)
2089 lane
= NEON_INTERLEAVE_LANES
;
2090 else if (lane
!= NEON_INTERLEAVE_LANES
)
2092 first_error (_(type_error
));
2097 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2099 /* No lane set by [x]. We must be interleaving structures. */
2101 lane
= NEON_INTERLEAVE_LANES
;
2104 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2105 || (count
> 1 && reg_incr
== -1))
2107 first_error (_("error parsing element/structure list"));
2111 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2113 first_error (_("expected }"));
2121 *eltype
= firsttype
.eltype
;
2126 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2129 /* Parse an explicit relocation suffix on an expression. This is
2130 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2131 arm_reloc_hsh contains no entries, so this function can only
2132 succeed if there is no () after the word. Returns -1 on error,
2133 BFD_RELOC_UNUSED if there wasn't any suffix. */
2136 parse_reloc (char **str
)
2138 struct reloc_entry
*r
;
2142 return BFD_RELOC_UNUSED
;
2147 while (*q
&& *q
!= ')' && *q
!= ',')
2152 if ((r
= (struct reloc_entry
*)
2153 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2160 /* Directives: register aliases. */
2162 static struct reg_entry
*
2163 insert_reg_alias (char *str
, unsigned number
, int type
)
2165 struct reg_entry
*new_reg
;
2168 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2170 if (new_reg
->builtin
)
2171 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2173 /* Only warn about a redefinition if it's not defined as the
2175 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2176 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2181 name
= xstrdup (str
);
2182 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2184 new_reg
->name
= name
;
2185 new_reg
->number
= number
;
2186 new_reg
->type
= type
;
2187 new_reg
->builtin
= FALSE
;
2188 new_reg
->neon
= NULL
;
2190 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2197 insert_neon_reg_alias (char *str
, int number
, int type
,
2198 struct neon_typed_alias
*atype
)
2200 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2204 first_error (_("attempt to redefine typed alias"));
2210 reg
->neon
= (struct neon_typed_alias
*)
2211 xmalloc (sizeof (struct neon_typed_alias
));
2212 *reg
->neon
= *atype
;
2216 /* Look for the .req directive. This is of the form:
2218 new_register_name .req existing_register_name
2220 If we find one, or if it looks sufficiently like one that we want to
2221 handle any error here, return TRUE. Otherwise return FALSE. */
2224 create_register_alias (char * newname
, char *p
)
2226 struct reg_entry
*old
;
2227 char *oldname
, *nbuf
;
2230 /* The input scrubber ensures that whitespace after the mnemonic is
2231 collapsed to single spaces. */
2233 if (strncmp (oldname
, " .req ", 6) != 0)
2237 if (*oldname
== '\0')
2240 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2243 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2247 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2248 the desired alias name, and p points to its end. If not, then
2249 the desired alias name is in the global original_case_string. */
2250 #ifdef TC_CASE_SENSITIVE
2253 newname
= original_case_string
;
2254 nlen
= strlen (newname
);
2257 nbuf
= (char *) alloca (nlen
+ 1);
2258 memcpy (nbuf
, newname
, nlen
);
2261 /* Create aliases under the new name as stated; an all-lowercase
2262 version of the new name; and an all-uppercase version of the new
2264 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2266 for (p
= nbuf
; *p
; p
++)
2269 if (strncmp (nbuf
, newname
, nlen
))
2271 /* If this attempt to create an additional alias fails, do not bother
2272 trying to create the all-lower case alias. We will fail and issue
2273 a second, duplicate error message. This situation arises when the
2274 programmer does something like:
2277 The second .req creates the "Foo" alias but then fails to create
2278 the artificial FOO alias because it has already been created by the
2280 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2284 for (p
= nbuf
; *p
; p
++)
2287 if (strncmp (nbuf
, newname
, nlen
))
2288 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2294 /* Create a Neon typed/indexed register alias using directives, e.g.:
2299 These typed registers can be used instead of the types specified after the
2300 Neon mnemonic, so long as all operands given have types. Types can also be
2301 specified directly, e.g.:
2302 vadd d0.s32, d1.s32, d2.s32 */
2305 create_neon_reg_alias (char *newname
, char *p
)
2307 enum arm_reg_type basetype
;
2308 struct reg_entry
*basereg
;
2309 struct reg_entry mybasereg
;
2310 struct neon_type ntype
;
2311 struct neon_typed_alias typeinfo
;
2312 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2315 typeinfo
.defined
= 0;
2316 typeinfo
.eltype
.type
= NT_invtype
;
2317 typeinfo
.eltype
.size
= -1;
2318 typeinfo
.index
= -1;
2322 if (strncmp (p
, " .dn ", 5) == 0)
2323 basetype
= REG_TYPE_VFD
;
2324 else if (strncmp (p
, " .qn ", 5) == 0)
2325 basetype
= REG_TYPE_NQ
;
2334 basereg
= arm_reg_parse_multi (&p
);
2336 if (basereg
&& basereg
->type
!= basetype
)
2338 as_bad (_("bad type for register"));
2342 if (basereg
== NULL
)
2345 /* Try parsing as an integer. */
2346 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2347 if (exp
.X_op
!= O_constant
)
2349 as_bad (_("expression must be constant"));
2352 basereg
= &mybasereg
;
2353 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2359 typeinfo
= *basereg
->neon
;
2361 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2363 /* We got a type. */
2364 if (typeinfo
.defined
& NTA_HASTYPE
)
2366 as_bad (_("can't redefine the type of a register alias"));
2370 typeinfo
.defined
|= NTA_HASTYPE
;
2371 if (ntype
.elems
!= 1)
2373 as_bad (_("you must specify a single type only"));
2376 typeinfo
.eltype
= ntype
.el
[0];
2379 if (skip_past_char (&p
, '[') == SUCCESS
)
2382 /* We got a scalar index. */
2384 if (typeinfo
.defined
& NTA_HASINDEX
)
2386 as_bad (_("can't redefine the index of a scalar alias"));
2390 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2392 if (exp
.X_op
!= O_constant
)
2394 as_bad (_("scalar index must be constant"));
2398 typeinfo
.defined
|= NTA_HASINDEX
;
2399 typeinfo
.index
= exp
.X_add_number
;
2401 if (skip_past_char (&p
, ']') == FAIL
)
2403 as_bad (_("expecting ]"));
2408 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2409 the desired alias name, and p points to its end. If not, then
2410 the desired alias name is in the global original_case_string. */
2411 #ifdef TC_CASE_SENSITIVE
2412 namelen
= nameend
- newname
;
2414 newname
= original_case_string
;
2415 namelen
= strlen (newname
);
2418 namebuf
= (char *) alloca (namelen
+ 1);
2419 strncpy (namebuf
, newname
, namelen
);
2420 namebuf
[namelen
] = '\0';
2422 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2423 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2425 /* Insert name in all uppercase. */
2426 for (p
= namebuf
; *p
; p
++)
2429 if (strncmp (namebuf
, newname
, namelen
))
2430 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2431 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2433 /* Insert name in all lowercase. */
2434 for (p
= namebuf
; *p
; p
++)
2437 if (strncmp (namebuf
, newname
, namelen
))
2438 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2439 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2444 /* Should never be called, as .req goes between the alias and the
2445 register name, not at the beginning of the line. */
2448 s_req (int a ATTRIBUTE_UNUSED
)
2450 as_bad (_("invalid syntax for .req directive"));
2454 s_dn (int a ATTRIBUTE_UNUSED
)
2456 as_bad (_("invalid syntax for .dn directive"));
2460 s_qn (int a ATTRIBUTE_UNUSED
)
2462 as_bad (_("invalid syntax for .qn directive"));
2465 /* The .unreq directive deletes an alias which was previously defined
2466 by .req. For example:
2472 s_unreq (int a ATTRIBUTE_UNUSED
)
2477 name
= input_line_pointer
;
2479 while (*input_line_pointer
!= 0
2480 && *input_line_pointer
!= ' '
2481 && *input_line_pointer
!= '\n')
2482 ++input_line_pointer
;
2484 saved_char
= *input_line_pointer
;
2485 *input_line_pointer
= 0;
2488 as_bad (_("invalid syntax for .unreq directive"));
2491 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2495 as_bad (_("unknown register alias '%s'"), name
);
2496 else if (reg
->builtin
)
2497 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2504 hash_delete (arm_reg_hsh
, name
, FALSE
);
2505 free ((char *) reg
->name
);
2510 /* Also locate the all upper case and all lower case versions.
2511 Do not complain if we cannot find one or the other as it
2512 was probably deleted above. */
2514 nbuf
= strdup (name
);
2515 for (p
= nbuf
; *p
; p
++)
2517 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2520 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2521 free ((char *) reg
->name
);
2527 for (p
= nbuf
; *p
; p
++)
2529 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2532 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2533 free ((char *) reg
->name
);
2543 *input_line_pointer
= saved_char
;
2544 demand_empty_rest_of_line ();
2547 /* Directives: Instruction set selection. */
2550 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2551 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2552 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2553 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2555 /* Create a new mapping symbol for the transition to STATE. */
2558 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2561 const char * symname
;
2568 type
= BSF_NO_FLAGS
;
2572 type
= BSF_NO_FLAGS
;
2576 type
= BSF_NO_FLAGS
;
2582 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2583 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2588 THUMB_SET_FUNC (symbolP
, 0);
2589 ARM_SET_THUMB (symbolP
, 0);
2590 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2594 THUMB_SET_FUNC (symbolP
, 1);
2595 ARM_SET_THUMB (symbolP
, 1);
2596 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2604 /* Save the mapping symbols for future reference. Also check that
2605 we do not place two mapping symbols at the same offset within a
2606 frag. We'll handle overlap between frags in
2607 check_mapping_symbols.
2609 If .fill or other data filling directive generates zero sized data,
2610 the mapping symbol for the following code will have the same value
2611 as the one generated for the data filling directive. In this case,
2612 we replace the old symbol with the new one at the same address. */
2615 if (frag
->tc_frag_data
.first_map
!= NULL
)
2617 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2618 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2620 frag
->tc_frag_data
.first_map
= symbolP
;
2622 if (frag
->tc_frag_data
.last_map
!= NULL
)
2624 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2625 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2626 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2628 frag
->tc_frag_data
.last_map
= symbolP
;
2631 /* We must sometimes convert a region marked as code to data during
2632 code alignment, if an odd number of bytes have to be padded. The
2633 code mapping symbol is pushed to an aligned address. */
2636 insert_data_mapping_symbol (enum mstate state
,
2637 valueT value
, fragS
*frag
, offsetT bytes
)
2639 /* If there was already a mapping symbol, remove it. */
2640 if (frag
->tc_frag_data
.last_map
!= NULL
2641 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2643 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2647 know (frag
->tc_frag_data
.first_map
== symp
);
2648 frag
->tc_frag_data
.first_map
= NULL
;
2650 frag
->tc_frag_data
.last_map
= NULL
;
2651 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2654 make_mapping_symbol (MAP_DATA
, value
, frag
);
2655 make_mapping_symbol (state
, value
+ bytes
, frag
);
2658 static void mapping_state_2 (enum mstate state
, int max_chars
);
2660 /* Set the mapping state to STATE. Only call this when about to
2661 emit some STATE bytes to the file. */
2663 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2665 mapping_state (enum mstate state
)
2667 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2669 if (mapstate
== state
)
2670 /* The mapping symbol has already been emitted.
2671 There is nothing else to do. */
2674 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2676 All ARM instructions require 4-byte alignment.
2677 (Almost) all Thumb instructions require 2-byte alignment.
2679 When emitting instructions into any section, mark the section
2682 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2683 but themselves require 2-byte alignment; this applies to some
2684 PC- relative forms. However, these cases will invovle implicit
2685 literal pool generation or an explicit .align >=2, both of
2686 which will cause the section to me marked with sufficient
2687 alignment. Thus, we don't handle those cases here. */
2688 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2690 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2691 /* This case will be evaluated later. */
2694 mapping_state_2 (state
, 0);
2697 /* Same as mapping_state, but MAX_CHARS bytes have already been
2698 allocated. Put the mapping symbol that far back. */
2701 mapping_state_2 (enum mstate state
, int max_chars
)
2703 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2705 if (!SEG_NORMAL (now_seg
))
2708 if (mapstate
== state
)
2709 /* The mapping symbol has already been emitted.
2710 There is nothing else to do. */
2713 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2714 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2716 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2717 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2720 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2723 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2724 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2728 #define mapping_state(x) ((void)0)
2729 #define mapping_state_2(x, y) ((void)0)
2732 /* Find the real, Thumb encoded start of a Thumb function. */
2736 find_real_start (symbolS
* symbolP
)
2739 const char * name
= S_GET_NAME (symbolP
);
2740 symbolS
* new_target
;
2742 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2743 #define STUB_NAME ".real_start_of"
2748 /* The compiler may generate BL instructions to local labels because
2749 it needs to perform a branch to a far away location. These labels
2750 do not have a corresponding ".real_start_of" label. We check
2751 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2752 the ".real_start_of" convention for nonlocal branches. */
2753 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2756 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2757 new_target
= symbol_find (real_start
);
2759 if (new_target
== NULL
)
2761 as_warn (_("Failed to find real start of function: %s\n"), name
);
2762 new_target
= symbolP
;
2770 opcode_select (int width
)
2777 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2778 as_bad (_("selected processor does not support THUMB opcodes"));
2781 /* No need to force the alignment, since we will have been
2782 coming from ARM mode, which is word-aligned. */
2783 record_alignment (now_seg
, 1);
2790 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2791 as_bad (_("selected processor does not support ARM opcodes"));
2796 frag_align (2, 0, 0);
2798 record_alignment (now_seg
, 1);
2803 as_bad (_("invalid instruction size selected (%d)"), width
);
2808 s_arm (int ignore ATTRIBUTE_UNUSED
)
2811 demand_empty_rest_of_line ();
2815 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2818 demand_empty_rest_of_line ();
2822 s_code (int unused ATTRIBUTE_UNUSED
)
2826 temp
= get_absolute_expression ();
2831 opcode_select (temp
);
2835 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2840 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2842 /* If we are not already in thumb mode go into it, EVEN if
2843 the target processor does not support thumb instructions.
2844 This is used by gcc/config/arm/lib1funcs.asm for example
2845 to compile interworking support functions even if the
2846 target processor should not support interworking. */
2850 record_alignment (now_seg
, 1);
2853 demand_empty_rest_of_line ();
2857 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2861 /* The following label is the name/address of the start of a Thumb function.
2862 We need to know this for the interworking support. */
2863 label_is_thumb_function_name
= TRUE
;
2866 /* Perform a .set directive, but also mark the alias as
2867 being a thumb function. */
2870 s_thumb_set (int equiv
)
2872 /* XXX the following is a duplicate of the code for s_set() in read.c
2873 We cannot just call that code as we need to get at the symbol that
2880 /* Especial apologies for the random logic:
2881 This just grew, and could be parsed much more simply!
2883 delim
= get_symbol_name (& name
);
2884 end_name
= input_line_pointer
;
2885 (void) restore_line_pointer (delim
);
2887 if (*input_line_pointer
!= ',')
2890 as_bad (_("expected comma after name \"%s\""), name
);
2892 ignore_rest_of_line ();
2896 input_line_pointer
++;
2899 if (name
[0] == '.' && name
[1] == '\0')
2901 /* XXX - this should not happen to .thumb_set. */
2905 if ((symbolP
= symbol_find (name
)) == NULL
2906 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2909 /* When doing symbol listings, play games with dummy fragments living
2910 outside the normal fragment chain to record the file and line info
2912 if (listing
& LISTING_SYMBOLS
)
2914 extern struct list_info_struct
* listing_tail
;
2915 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2917 memset (dummy_frag
, 0, sizeof (fragS
));
2918 dummy_frag
->fr_type
= rs_fill
;
2919 dummy_frag
->line
= listing_tail
;
2920 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2921 dummy_frag
->fr_symbol
= symbolP
;
2925 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2928 /* "set" symbols are local unless otherwise specified. */
2929 SF_SET_LOCAL (symbolP
);
2930 #endif /* OBJ_COFF */
2931 } /* Make a new symbol. */
2933 symbol_table_insert (symbolP
);
2938 && S_IS_DEFINED (symbolP
)
2939 && S_GET_SEGMENT (symbolP
) != reg_section
)
2940 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2942 pseudo_set (symbolP
);
2944 demand_empty_rest_of_line ();
2946 /* XXX Now we come to the Thumb specific bit of code. */
2948 THUMB_SET_FUNC (symbolP
, 1);
2949 ARM_SET_THUMB (symbolP
, 1);
2950 #if defined OBJ_ELF || defined OBJ_COFF
2951 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2955 /* Directives: Mode selection. */
2957 /* .syntax [unified|divided] - choose the new unified syntax
2958 (same for Arm and Thumb encoding, modulo slight differences in what
2959 can be represented) or the old divergent syntax for each mode. */
2961 s_syntax (int unused ATTRIBUTE_UNUSED
)
2965 delim
= get_symbol_name (& name
);
2967 if (!strcasecmp (name
, "unified"))
2968 unified_syntax
= TRUE
;
2969 else if (!strcasecmp (name
, "divided"))
2970 unified_syntax
= FALSE
;
2973 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2976 (void) restore_line_pointer (delim
);
2977 demand_empty_rest_of_line ();
2980 /* Directives: sectioning and alignment. */
2983 s_bss (int ignore ATTRIBUTE_UNUSED
)
2985 /* We don't support putting frags in the BSS segment, we fake it by
2986 marking in_bss, then looking at s_skip for clues. */
2987 subseg_set (bss_section
, 0);
2988 demand_empty_rest_of_line ();
2990 #ifdef md_elf_section_change_hook
2991 md_elf_section_change_hook ();
2996 s_even (int ignore ATTRIBUTE_UNUSED
)
2998 /* Never make frag if expect extra pass. */
3000 frag_align (1, 0, 0);
3002 record_alignment (now_seg
, 1);
3004 demand_empty_rest_of_line ();
3007 /* Directives: CodeComposer Studio. */
3009 /* .ref (for CodeComposer Studio syntax only). */
3011 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3013 if (codecomposer_syntax
)
3014 ignore_rest_of_line ();
3016 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3019 /* If name is not NULL, then it is used for marking the beginning of a
3020 function, wherease if it is NULL then it means the function end. */
3022 asmfunc_debug (const char * name
)
3024 static const char * last_name
= NULL
;
3028 gas_assert (last_name
== NULL
);
3031 if (debug_type
== DEBUG_STABS
)
3032 stabs_generate_asm_func (name
, name
);
3036 gas_assert (last_name
!= NULL
);
3038 if (debug_type
== DEBUG_STABS
)
3039 stabs_generate_asm_endfunc (last_name
, last_name
);
3046 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3048 if (codecomposer_syntax
)
3050 switch (asmfunc_state
)
3052 case OUTSIDE_ASMFUNC
:
3053 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3056 case WAITING_ASMFUNC_NAME
:
3057 as_bad (_(".asmfunc repeated."));
3060 case WAITING_ENDASMFUNC
:
3061 as_bad (_(".asmfunc without function."));
3064 demand_empty_rest_of_line ();
3067 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3071 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3073 if (codecomposer_syntax
)
3075 switch (asmfunc_state
)
3077 case OUTSIDE_ASMFUNC
:
3078 as_bad (_(".endasmfunc without a .asmfunc."));
3081 case WAITING_ASMFUNC_NAME
:
3082 as_bad (_(".endasmfunc without function."));
3085 case WAITING_ENDASMFUNC
:
3086 asmfunc_state
= OUTSIDE_ASMFUNC
;
3087 asmfunc_debug (NULL
);
3090 demand_empty_rest_of_line ();
3093 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3097 s_ccs_def (int name
)
3099 if (codecomposer_syntax
)
3102 as_bad (_(".def pseudo-op only available with -mccs flag."));
3105 /* Directives: Literal pools. */
3107 static literal_pool
*
3108 find_literal_pool (void)
3110 literal_pool
* pool
;
3112 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3114 if (pool
->section
== now_seg
3115 && pool
->sub_section
== now_subseg
)
3122 static literal_pool
*
3123 find_or_make_literal_pool (void)
3125 /* Next literal pool ID number. */
3126 static unsigned int latest_pool_num
= 1;
3127 literal_pool
* pool
;
3129 pool
= find_literal_pool ();
3133 /* Create a new pool. */
3134 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3138 pool
->next_free_entry
= 0;
3139 pool
->section
= now_seg
;
3140 pool
->sub_section
= now_subseg
;
3141 pool
->next
= list_of_pools
;
3142 pool
->symbol
= NULL
;
3143 pool
->alignment
= 2;
3145 /* Add it to the list. */
3146 list_of_pools
= pool
;
3149 /* New pools, and emptied pools, will have a NULL symbol. */
3150 if (pool
->symbol
== NULL
)
3152 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3153 (valueT
) 0, &zero_address_frag
);
3154 pool
->id
= latest_pool_num
++;
3161 /* Add the literal in the global 'inst'
3162 structure to the relevant literal pool. */
3165 add_to_lit_pool (unsigned int nbytes
)
3167 #define PADDING_SLOT 0x1
3168 #define LIT_ENTRY_SIZE_MASK 0xFF
3169 literal_pool
* pool
;
3170 unsigned int entry
, pool_size
= 0;
3171 bfd_boolean padding_slot_p
= FALSE
;
3177 imm1
= inst
.operands
[1].imm
;
3178 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3179 : inst
.reloc
.exp
.X_unsigned
? 0
3180 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3181 if (target_big_endian
)
3184 imm2
= inst
.operands
[1].imm
;
3188 pool
= find_or_make_literal_pool ();
3190 /* Check if this literal value is already in the pool. */
3191 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3195 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3196 && (inst
.reloc
.exp
.X_op
== O_constant
)
3197 && (pool
->literals
[entry
].X_add_number
3198 == inst
.reloc
.exp
.X_add_number
)
3199 && (pool
->literals
[entry
].X_md
== nbytes
)
3200 && (pool
->literals
[entry
].X_unsigned
3201 == inst
.reloc
.exp
.X_unsigned
))
3204 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3205 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3206 && (pool
->literals
[entry
].X_add_number
3207 == inst
.reloc
.exp
.X_add_number
)
3208 && (pool
->literals
[entry
].X_add_symbol
3209 == inst
.reloc
.exp
.X_add_symbol
)
3210 && (pool
->literals
[entry
].X_op_symbol
3211 == inst
.reloc
.exp
.X_op_symbol
)
3212 && (pool
->literals
[entry
].X_md
== nbytes
))
3215 else if ((nbytes
== 8)
3216 && !(pool_size
& 0x7)
3217 && ((entry
+ 1) != pool
->next_free_entry
)
3218 && (pool
->literals
[entry
].X_op
== O_constant
)
3219 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3220 && (pool
->literals
[entry
].X_unsigned
3221 == inst
.reloc
.exp
.X_unsigned
)
3222 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3223 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3224 && (pool
->literals
[entry
+ 1].X_unsigned
3225 == inst
.reloc
.exp
.X_unsigned
))
3228 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3229 if (padding_slot_p
&& (nbytes
== 4))
3235 /* Do we need to create a new entry? */
3236 if (entry
== pool
->next_free_entry
)
3238 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3240 inst
.error
= _("literal pool overflow");
3246 /* For 8-byte entries, we align to an 8-byte boundary,
3247 and split it into two 4-byte entries, because on 32-bit
3248 host, 8-byte constants are treated as big num, thus
3249 saved in "generic_bignum" which will be overwritten
3250 by later assignments.
3252 We also need to make sure there is enough space for
3255 We also check to make sure the literal operand is a
3257 if (!(inst
.reloc
.exp
.X_op
== O_constant
3258 || inst
.reloc
.exp
.X_op
== O_big
))
3260 inst
.error
= _("invalid type for literal pool");
3263 else if (pool_size
& 0x7)
3265 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3267 inst
.error
= _("literal pool overflow");
3271 pool
->literals
[entry
] = inst
.reloc
.exp
;
3272 pool
->literals
[entry
].X_add_number
= 0;
3273 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3274 pool
->next_free_entry
+= 1;
3277 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3279 inst
.error
= _("literal pool overflow");
3283 pool
->literals
[entry
] = inst
.reloc
.exp
;
3284 pool
->literals
[entry
].X_op
= O_constant
;
3285 pool
->literals
[entry
].X_add_number
= imm1
;
3286 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3287 pool
->literals
[entry
++].X_md
= 4;
3288 pool
->literals
[entry
] = inst
.reloc
.exp
;
3289 pool
->literals
[entry
].X_op
= O_constant
;
3290 pool
->literals
[entry
].X_add_number
= imm2
;
3291 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3292 pool
->literals
[entry
].X_md
= 4;
3293 pool
->alignment
= 3;
3294 pool
->next_free_entry
+= 1;
3298 pool
->literals
[entry
] = inst
.reloc
.exp
;
3299 pool
->literals
[entry
].X_md
= 4;
3303 /* PR ld/12974: Record the location of the first source line to reference
3304 this entry in the literal pool. If it turns out during linking that the
3305 symbol does not exist we will be able to give an accurate line number for
3306 the (first use of the) missing reference. */
3307 if (debug_type
== DEBUG_DWARF2
)
3308 dwarf2_where (pool
->locs
+ entry
);
3310 pool
->next_free_entry
+= 1;
3312 else if (padding_slot_p
)
3314 pool
->literals
[entry
] = inst
.reloc
.exp
;
3315 pool
->literals
[entry
].X_md
= nbytes
;
3318 inst
.reloc
.exp
.X_op
= O_symbol
;
3319 inst
.reloc
.exp
.X_add_number
= pool_size
;
3320 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3326 tc_start_label_without_colon (void)
3328 bfd_boolean ret
= TRUE
;
3330 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3332 const char *label
= input_line_pointer
;
3334 while (!is_end_of_line
[(int) label
[-1]])
3339 as_bad (_("Invalid label '%s'"), label
);
3343 asmfunc_debug (label
);
3345 asmfunc_state
= WAITING_ENDASMFUNC
;
3351 /* Can't use symbol_new here, so have to create a symbol and then at
3352 a later date assign it a value. Thats what these functions do. */
3355 symbol_locate (symbolS
* symbolP
,
3356 const char * name
, /* It is copied, the caller can modify. */
3357 segT segment
, /* Segment identifier (SEG_<something>). */
3358 valueT valu
, /* Symbol value. */
3359 fragS
* frag
) /* Associated fragment. */
3362 char * preserved_copy_of_name
;
3364 name_length
= strlen (name
) + 1; /* +1 for \0. */
3365 obstack_grow (¬es
, name
, name_length
);
3366 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3368 #ifdef tc_canonicalize_symbol_name
3369 preserved_copy_of_name
=
3370 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3373 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3375 S_SET_SEGMENT (symbolP
, segment
);
3376 S_SET_VALUE (symbolP
, valu
);
3377 symbol_clear_list_pointers (symbolP
);
3379 symbol_set_frag (symbolP
, frag
);
3381 /* Link to end of symbol chain. */
3383 extern int symbol_table_frozen
;
3385 if (symbol_table_frozen
)
3389 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3391 obj_symbol_new_hook (symbolP
);
3393 #ifdef tc_symbol_new_hook
3394 tc_symbol_new_hook (symbolP
);
3398 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3399 #endif /* DEBUG_SYMS */
3403 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3406 literal_pool
* pool
;
3409 pool
= find_literal_pool ();
3411 || pool
->symbol
== NULL
3412 || pool
->next_free_entry
== 0)
3415 /* Align pool as you have word accesses.
3416 Only make a frag if we have to. */
3418 frag_align (pool
->alignment
, 0, 0);
3420 record_alignment (now_seg
, 2);
3423 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3424 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3426 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3428 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3429 (valueT
) frag_now_fix (), frag_now
);
3430 symbol_table_insert (pool
->symbol
);
3432 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3434 #if defined OBJ_COFF || defined OBJ_ELF
3435 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3438 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3441 if (debug_type
== DEBUG_DWARF2
)
3442 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3444 /* First output the expression in the instruction to the pool. */
3445 emit_expr (&(pool
->literals
[entry
]),
3446 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3449 /* Mark the pool as empty. */
3450 pool
->next_free_entry
= 0;
3451 pool
->symbol
= NULL
;
3455 /* Forward declarations for functions below, in the MD interface
3457 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3458 static valueT
create_unwind_entry (int);
3459 static void start_unwind_section (const segT
, int);
3460 static void add_unwind_opcode (valueT
, int);
3461 static void flush_pending_unwind (void);
3463 /* Directives: Data. */
3466 s_arm_elf_cons (int nbytes
)
3470 #ifdef md_flush_pending_output
3471 md_flush_pending_output ();
3474 if (is_it_end_of_statement ())
3476 demand_empty_rest_of_line ();
3480 #ifdef md_cons_align
3481 md_cons_align (nbytes
);
3484 mapping_state (MAP_DATA
);
3488 char *base
= input_line_pointer
;
3492 if (exp
.X_op
!= O_symbol
)
3493 emit_expr (&exp
, (unsigned int) nbytes
);
3496 char *before_reloc
= input_line_pointer
;
3497 reloc
= parse_reloc (&input_line_pointer
);
3500 as_bad (_("unrecognized relocation suffix"));
3501 ignore_rest_of_line ();
3504 else if (reloc
== BFD_RELOC_UNUSED
)
3505 emit_expr (&exp
, (unsigned int) nbytes
);
3508 reloc_howto_type
*howto
= (reloc_howto_type
*)
3509 bfd_reloc_type_lookup (stdoutput
,
3510 (bfd_reloc_code_real_type
) reloc
);
3511 int size
= bfd_get_reloc_size (howto
);
3513 if (reloc
== BFD_RELOC_ARM_PLT32
)
3515 as_bad (_("(plt) is only valid on branch targets"));
3516 reloc
= BFD_RELOC_UNUSED
;
3521 as_bad (_("%s relocations do not fit in %d bytes"),
3522 howto
->name
, nbytes
);
3525 /* We've parsed an expression stopping at O_symbol.
3526 But there may be more expression left now that we
3527 have parsed the relocation marker. Parse it again.
3528 XXX Surely there is a cleaner way to do this. */
3529 char *p
= input_line_pointer
;
3531 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3532 memcpy (save_buf
, base
, input_line_pointer
- base
);
3533 memmove (base
+ (input_line_pointer
- before_reloc
),
3534 base
, before_reloc
- base
);
3536 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3538 memcpy (base
, save_buf
, p
- base
);
3540 offset
= nbytes
- size
;
3541 p
= frag_more (nbytes
);
3542 memset (p
, 0, nbytes
);
3543 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3544 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3549 while (*input_line_pointer
++ == ',');
3551 /* Put terminator back into stream. */
3552 input_line_pointer
--;
3553 demand_empty_rest_of_line ();
3556 /* Emit an expression containing a 32-bit thumb instruction.
3557 Implementation based on put_thumb32_insn. */
3560 emit_thumb32_expr (expressionS
* exp
)
3562 expressionS exp_high
= *exp
;
3564 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3565 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3566 exp
->X_add_number
&= 0xffff;
3567 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3570 /* Guess the instruction size based on the opcode. */
3573 thumb_insn_size (int opcode
)
3575 if ((unsigned int) opcode
< 0xe800u
)
3577 else if ((unsigned int) opcode
>= 0xe8000000u
)
3584 emit_insn (expressionS
*exp
, int nbytes
)
3588 if (exp
->X_op
== O_constant
)
3593 size
= thumb_insn_size (exp
->X_add_number
);
3597 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3599 as_bad (_(".inst.n operand too big. "\
3600 "Use .inst.w instead"));
3605 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3606 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3608 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3610 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3611 emit_thumb32_expr (exp
);
3613 emit_expr (exp
, (unsigned int) size
);
3615 it_fsm_post_encode ();
3619 as_bad (_("cannot determine Thumb instruction size. " \
3620 "Use .inst.n/.inst.w instead"));
3623 as_bad (_("constant expression required"));
3628 /* Like s_arm_elf_cons but do not use md_cons_align and
3629 set the mapping state to MAP_ARM/MAP_THUMB. */
3632 s_arm_elf_inst (int nbytes
)
3634 if (is_it_end_of_statement ())
3636 demand_empty_rest_of_line ();
3640 /* Calling mapping_state () here will not change ARM/THUMB,
3641 but will ensure not to be in DATA state. */
3644 mapping_state (MAP_THUMB
);
3649 as_bad (_("width suffixes are invalid in ARM mode"));
3650 ignore_rest_of_line ();
3656 mapping_state (MAP_ARM
);
3665 if (! emit_insn (& exp
, nbytes
))
3667 ignore_rest_of_line ();
3671 while (*input_line_pointer
++ == ',');
3673 /* Put terminator back into stream. */
3674 input_line_pointer
--;
3675 demand_empty_rest_of_line ();
3678 /* Parse a .rel31 directive. */
3681 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3688 if (*input_line_pointer
== '1')
3689 highbit
= 0x80000000;
3690 else if (*input_line_pointer
!= '0')
3691 as_bad (_("expected 0 or 1"));
3693 input_line_pointer
++;
3694 if (*input_line_pointer
!= ',')
3695 as_bad (_("missing comma"));
3696 input_line_pointer
++;
3698 #ifdef md_flush_pending_output
3699 md_flush_pending_output ();
3702 #ifdef md_cons_align
3706 mapping_state (MAP_DATA
);
3711 md_number_to_chars (p
, highbit
, 4);
3712 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3713 BFD_RELOC_ARM_PREL31
);
3715 demand_empty_rest_of_line ();
3718 /* Directives: AEABI stack-unwind tables. */
3720 /* Parse an unwind_fnstart directive. Simply records the current location. */
3723 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3725 demand_empty_rest_of_line ();
3726 if (unwind
.proc_start
)
3728 as_bad (_("duplicate .fnstart directive"));
3732 /* Mark the start of the function. */
3733 unwind
.proc_start
= expr_build_dot ();
3735 /* Reset the rest of the unwind info. */
3736 unwind
.opcode_count
= 0;
3737 unwind
.table_entry
= NULL
;
3738 unwind
.personality_routine
= NULL
;
3739 unwind
.personality_index
= -1;
3740 unwind
.frame_size
= 0;
3741 unwind
.fp_offset
= 0;
3742 unwind
.fp_reg
= REG_SP
;
3744 unwind
.sp_restored
= 0;
3748 /* Parse a handlerdata directive. Creates the exception handling table entry
3749 for the function. */
3752 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3754 demand_empty_rest_of_line ();
3755 if (!unwind
.proc_start
)
3756 as_bad (MISSING_FNSTART
);
3758 if (unwind
.table_entry
)
3759 as_bad (_("duplicate .handlerdata directive"));
3761 create_unwind_entry (1);
3764 /* Parse an unwind_fnend directive. Generates the index table entry. */
3767 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3772 unsigned int marked_pr_dependency
;
3774 demand_empty_rest_of_line ();
3776 if (!unwind
.proc_start
)
3778 as_bad (_(".fnend directive without .fnstart"));
3782 /* Add eh table entry. */
3783 if (unwind
.table_entry
== NULL
)
3784 val
= create_unwind_entry (0);
3788 /* Add index table entry. This is two words. */
3789 start_unwind_section (unwind
.saved_seg
, 1);
3790 frag_align (2, 0, 0);
3791 record_alignment (now_seg
, 2);
3793 ptr
= frag_more (8);
3795 where
= frag_now_fix () - 8;
3797 /* Self relative offset of the function start. */
3798 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3799 BFD_RELOC_ARM_PREL31
);
3801 /* Indicate dependency on EHABI-defined personality routines to the
3802 linker, if it hasn't been done already. */
3803 marked_pr_dependency
3804 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3805 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3806 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3808 static const char *const name
[] =
3810 "__aeabi_unwind_cpp_pr0",
3811 "__aeabi_unwind_cpp_pr1",
3812 "__aeabi_unwind_cpp_pr2"
3814 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3815 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3816 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3817 |= 1 << unwind
.personality_index
;
3821 /* Inline exception table entry. */
3822 md_number_to_chars (ptr
+ 4, val
, 4);
3824 /* Self relative offset of the table entry. */
3825 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3826 BFD_RELOC_ARM_PREL31
);
3828 /* Restore the original section. */
3829 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3831 unwind
.proc_start
= NULL
;
3835 /* Parse an unwind_cantunwind directive. */
3838 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3840 demand_empty_rest_of_line ();
3841 if (!unwind
.proc_start
)
3842 as_bad (MISSING_FNSTART
);
3844 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3845 as_bad (_("personality routine specified for cantunwind frame"));
3847 unwind
.personality_index
= -2;
3851 /* Parse a personalityindex directive. */
3854 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3858 if (!unwind
.proc_start
)
3859 as_bad (MISSING_FNSTART
);
3861 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3862 as_bad (_("duplicate .personalityindex directive"));
3866 if (exp
.X_op
!= O_constant
3867 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3869 as_bad (_("bad personality routine number"));
3870 ignore_rest_of_line ();
3874 unwind
.personality_index
= exp
.X_add_number
;
3876 demand_empty_rest_of_line ();
3880 /* Parse a personality directive. */
3883 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3887 if (!unwind
.proc_start
)
3888 as_bad (MISSING_FNSTART
);
3890 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3891 as_bad (_("duplicate .personality directive"));
3893 c
= get_symbol_name (& name
);
3894 p
= input_line_pointer
;
3896 ++ input_line_pointer
;
3897 unwind
.personality_routine
= symbol_find_or_make (name
);
3899 demand_empty_rest_of_line ();
3903 /* Parse a directive saving core registers. */
3906 s_arm_unwind_save_core (void)
3912 range
= parse_reg_list (&input_line_pointer
);
3915 as_bad (_("expected register list"));
3916 ignore_rest_of_line ();
3920 demand_empty_rest_of_line ();
3922 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3923 into .unwind_save {..., sp...}. We aren't bothered about the value of
3924 ip because it is clobbered by calls. */
3925 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3926 && (range
& 0x3000) == 0x1000)
3928 unwind
.opcode_count
--;
3929 unwind
.sp_restored
= 0;
3930 range
= (range
| 0x2000) & ~0x1000;
3931 unwind
.pending_offset
= 0;
3937 /* See if we can use the short opcodes. These pop a block of up to 8
3938 registers starting with r4, plus maybe r14. */
3939 for (n
= 0; n
< 8; n
++)
3941 /* Break at the first non-saved register. */
3942 if ((range
& (1 << (n
+ 4))) == 0)
3945 /* See if there are any other bits set. */
3946 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3948 /* Use the long form. */
3949 op
= 0x8000 | ((range
>> 4) & 0xfff);
3950 add_unwind_opcode (op
, 2);
3954 /* Use the short form. */
3956 op
= 0xa8; /* Pop r14. */
3958 op
= 0xa0; /* Do not pop r14. */
3960 add_unwind_opcode (op
, 1);
3967 op
= 0xb100 | (range
& 0xf);
3968 add_unwind_opcode (op
, 2);
3971 /* Record the number of bytes pushed. */
3972 for (n
= 0; n
< 16; n
++)
3974 if (range
& (1 << n
))
3975 unwind
.frame_size
+= 4;
3980 /* Parse a directive saving FPA registers. */
3983 s_arm_unwind_save_fpa (int reg
)
3989 /* Get Number of registers to transfer. */
3990 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3993 exp
.X_op
= O_illegal
;
3995 if (exp
.X_op
!= O_constant
)
3997 as_bad (_("expected , <constant>"));
3998 ignore_rest_of_line ();
4002 num_regs
= exp
.X_add_number
;
4004 if (num_regs
< 1 || num_regs
> 4)
4006 as_bad (_("number of registers must be in the range [1:4]"));
4007 ignore_rest_of_line ();
4011 demand_empty_rest_of_line ();
4016 op
= 0xb4 | (num_regs
- 1);
4017 add_unwind_opcode (op
, 1);
4022 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4023 add_unwind_opcode (op
, 2);
4025 unwind
.frame_size
+= num_regs
* 12;
4029 /* Parse a directive saving VFP registers for ARMv6 and above. */
4032 s_arm_unwind_save_vfp_armv6 (void)
4037 int num_vfpv3_regs
= 0;
4038 int num_regs_below_16
;
4040 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4043 as_bad (_("expected register list"));
4044 ignore_rest_of_line ();
4048 demand_empty_rest_of_line ();
4050 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4051 than FSTMX/FLDMX-style ones). */
4053 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4055 num_vfpv3_regs
= count
;
4056 else if (start
+ count
> 16)
4057 num_vfpv3_regs
= start
+ count
- 16;
4059 if (num_vfpv3_regs
> 0)
4061 int start_offset
= start
> 16 ? start
- 16 : 0;
4062 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4063 add_unwind_opcode (op
, 2);
4066 /* Generate opcode for registers numbered in the range 0 .. 15. */
4067 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4068 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4069 if (num_regs_below_16
> 0)
4071 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4072 add_unwind_opcode (op
, 2);
4075 unwind
.frame_size
+= count
* 8;
4079 /* Parse a directive saving VFP registers for pre-ARMv6. */
4082 s_arm_unwind_save_vfp (void)
4088 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4091 as_bad (_("expected register list"));
4092 ignore_rest_of_line ();
4096 demand_empty_rest_of_line ();
4101 op
= 0xb8 | (count
- 1);
4102 add_unwind_opcode (op
, 1);
4107 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4108 add_unwind_opcode (op
, 2);
4110 unwind
.frame_size
+= count
* 8 + 4;
4114 /* Parse a directive saving iWMMXt data registers. */
4117 s_arm_unwind_save_mmxwr (void)
4125 if (*input_line_pointer
== '{')
4126 input_line_pointer
++;
4130 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4134 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4139 as_tsktsk (_("register list not in ascending order"));
4142 if (*input_line_pointer
== '-')
4144 input_line_pointer
++;
4145 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4148 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4151 else if (reg
>= hi_reg
)
4153 as_bad (_("bad register range"));
4156 for (; reg
< hi_reg
; reg
++)
4160 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4162 skip_past_char (&input_line_pointer
, '}');
4164 demand_empty_rest_of_line ();
4166 /* Generate any deferred opcodes because we're going to be looking at
4168 flush_pending_unwind ();
4170 for (i
= 0; i
< 16; i
++)
4172 if (mask
& (1 << i
))
4173 unwind
.frame_size
+= 8;
4176 /* Attempt to combine with a previous opcode. We do this because gcc
4177 likes to output separate unwind directives for a single block of
4179 if (unwind
.opcode_count
> 0)
4181 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4182 if ((i
& 0xf8) == 0xc0)
4185 /* Only merge if the blocks are contiguous. */
4188 if ((mask
& 0xfe00) == (1 << 9))
4190 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4191 unwind
.opcode_count
--;
4194 else if (i
== 6 && unwind
.opcode_count
>= 2)
4196 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4200 op
= 0xffff << (reg
- 1);
4202 && ((mask
& op
) == (1u << (reg
- 1))))
4204 op
= (1 << (reg
+ i
+ 1)) - 1;
4205 op
&= ~((1 << reg
) - 1);
4207 unwind
.opcode_count
-= 2;
4214 /* We want to generate opcodes in the order the registers have been
4215 saved, ie. descending order. */
4216 for (reg
= 15; reg
>= -1; reg
--)
4218 /* Save registers in blocks. */
4220 || !(mask
& (1 << reg
)))
4222 /* We found an unsaved reg. Generate opcodes to save the
4229 op
= 0xc0 | (hi_reg
- 10);
4230 add_unwind_opcode (op
, 1);
4235 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4236 add_unwind_opcode (op
, 2);
4245 ignore_rest_of_line ();
4249 s_arm_unwind_save_mmxwcg (void)
4256 if (*input_line_pointer
== '{')
4257 input_line_pointer
++;
4259 skip_whitespace (input_line_pointer
);
4263 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4267 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4273 as_tsktsk (_("register list not in ascending order"));
4276 if (*input_line_pointer
== '-')
4278 input_line_pointer
++;
4279 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4282 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4285 else if (reg
>= hi_reg
)
4287 as_bad (_("bad register range"));
4290 for (; reg
< hi_reg
; reg
++)
4294 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4296 skip_past_char (&input_line_pointer
, '}');
4298 demand_empty_rest_of_line ();
4300 /* Generate any deferred opcodes because we're going to be looking at
4302 flush_pending_unwind ();
4304 for (reg
= 0; reg
< 16; reg
++)
4306 if (mask
& (1 << reg
))
4307 unwind
.frame_size
+= 4;
4310 add_unwind_opcode (op
, 2);
4313 ignore_rest_of_line ();
4317 /* Parse an unwind_save directive.
4318 If the argument is non-zero, this is a .vsave directive. */
4321 s_arm_unwind_save (int arch_v6
)
4324 struct reg_entry
*reg
;
4325 bfd_boolean had_brace
= FALSE
;
4327 if (!unwind
.proc_start
)
4328 as_bad (MISSING_FNSTART
);
4330 /* Figure out what sort of save we have. */
4331 peek
= input_line_pointer
;
4339 reg
= arm_reg_parse_multi (&peek
);
4343 as_bad (_("register expected"));
4344 ignore_rest_of_line ();
4353 as_bad (_("FPA .unwind_save does not take a register list"));
4354 ignore_rest_of_line ();
4357 input_line_pointer
= peek
;
4358 s_arm_unwind_save_fpa (reg
->number
);
4362 s_arm_unwind_save_core ();
4367 s_arm_unwind_save_vfp_armv6 ();
4369 s_arm_unwind_save_vfp ();
4372 case REG_TYPE_MMXWR
:
4373 s_arm_unwind_save_mmxwr ();
4376 case REG_TYPE_MMXWCG
:
4377 s_arm_unwind_save_mmxwcg ();
4381 as_bad (_(".unwind_save does not support this kind of register"));
4382 ignore_rest_of_line ();
4387 /* Parse an unwind_movsp directive. */
4390 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4396 if (!unwind
.proc_start
)
4397 as_bad (MISSING_FNSTART
);
4399 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4402 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4403 ignore_rest_of_line ();
4407 /* Optional constant. */
4408 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4410 if (immediate_for_directive (&offset
) == FAIL
)
4416 demand_empty_rest_of_line ();
4418 if (reg
== REG_SP
|| reg
== REG_PC
)
4420 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4424 if (unwind
.fp_reg
!= REG_SP
)
4425 as_bad (_("unexpected .unwind_movsp directive"));
4427 /* Generate opcode to restore the value. */
4429 add_unwind_opcode (op
, 1);
4431 /* Record the information for later. */
4432 unwind
.fp_reg
= reg
;
4433 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4434 unwind
.sp_restored
= 1;
4437 /* Parse an unwind_pad directive. */
4440 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4444 if (!unwind
.proc_start
)
4445 as_bad (MISSING_FNSTART
);
4447 if (immediate_for_directive (&offset
) == FAIL
)
4452 as_bad (_("stack increment must be multiple of 4"));
4453 ignore_rest_of_line ();
4457 /* Don't generate any opcodes, just record the details for later. */
4458 unwind
.frame_size
+= offset
;
4459 unwind
.pending_offset
+= offset
;
4461 demand_empty_rest_of_line ();
4464 /* Parse an unwind_setfp directive. */
4467 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4473 if (!unwind
.proc_start
)
4474 as_bad (MISSING_FNSTART
);
4476 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4477 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4480 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4482 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4484 as_bad (_("expected <reg>, <reg>"));
4485 ignore_rest_of_line ();
4489 /* Optional constant. */
4490 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4492 if (immediate_for_directive (&offset
) == FAIL
)
4498 demand_empty_rest_of_line ();
4500 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4502 as_bad (_("register must be either sp or set by a previous"
4503 "unwind_movsp directive"));
4507 /* Don't generate any opcodes, just record the information for later. */
4508 unwind
.fp_reg
= fp_reg
;
4510 if (sp_reg
== REG_SP
)
4511 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4513 unwind
.fp_offset
-= offset
;
4516 /* Parse an unwind_raw directive. */
4519 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4522 /* This is an arbitrary limit. */
4523 unsigned char op
[16];
4526 if (!unwind
.proc_start
)
4527 as_bad (MISSING_FNSTART
);
4530 if (exp
.X_op
== O_constant
4531 && skip_past_comma (&input_line_pointer
) != FAIL
)
4533 unwind
.frame_size
+= exp
.X_add_number
;
4537 exp
.X_op
= O_illegal
;
4539 if (exp
.X_op
!= O_constant
)
4541 as_bad (_("expected <offset>, <opcode>"));
4542 ignore_rest_of_line ();
4548 /* Parse the opcode. */
4553 as_bad (_("unwind opcode too long"));
4554 ignore_rest_of_line ();
4556 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4558 as_bad (_("invalid unwind opcode"));
4559 ignore_rest_of_line ();
4562 op
[count
++] = exp
.X_add_number
;
4564 /* Parse the next byte. */
4565 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4571 /* Add the opcode bytes in reverse order. */
4573 add_unwind_opcode (op
[count
], 1);
4575 demand_empty_rest_of_line ();
4579 /* Parse a .eabi_attribute directive. */
4582 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4584 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4586 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4587 attributes_set_explicitly
[tag
] = 1;
4590 /* Emit a tls fix for the symbol. */
4593 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4597 #ifdef md_flush_pending_output
4598 md_flush_pending_output ();
4601 #ifdef md_cons_align
4605 /* Since we're just labelling the code, there's no need to define a
4608 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4609 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4610 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4611 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4613 #endif /* OBJ_ELF */
4615 static void s_arm_arch (int);
4616 static void s_arm_object_arch (int);
4617 static void s_arm_cpu (int);
4618 static void s_arm_fpu (int);
4619 static void s_arm_arch_extension (int);
4624 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4631 if (exp
.X_op
== O_symbol
)
4632 exp
.X_op
= O_secrel
;
4634 emit_expr (&exp
, 4);
4636 while (*input_line_pointer
++ == ',');
4638 input_line_pointer
--;
4639 demand_empty_rest_of_line ();
4643 /* This table describes all the machine specific pseudo-ops the assembler
4644 has to support. The fields are:
4645 pseudo-op name without dot
4646 function to call to execute this pseudo-op
4647 Integer arg to pass to the function. */
4649 const pseudo_typeS md_pseudo_table
[] =
4651 /* Never called because '.req' does not start a line. */
4652 { "req", s_req
, 0 },
4653 /* Following two are likewise never called. */
4656 { "unreq", s_unreq
, 0 },
4657 { "bss", s_bss
, 0 },
4658 { "align", s_align_ptwo
, 2 },
4659 { "arm", s_arm
, 0 },
4660 { "thumb", s_thumb
, 0 },
4661 { "code", s_code
, 0 },
4662 { "force_thumb", s_force_thumb
, 0 },
4663 { "thumb_func", s_thumb_func
, 0 },
4664 { "thumb_set", s_thumb_set
, 0 },
4665 { "even", s_even
, 0 },
4666 { "ltorg", s_ltorg
, 0 },
4667 { "pool", s_ltorg
, 0 },
4668 { "syntax", s_syntax
, 0 },
4669 { "cpu", s_arm_cpu
, 0 },
4670 { "arch", s_arm_arch
, 0 },
4671 { "object_arch", s_arm_object_arch
, 0 },
4672 { "fpu", s_arm_fpu
, 0 },
4673 { "arch_extension", s_arm_arch_extension
, 0 },
4675 { "word", s_arm_elf_cons
, 4 },
4676 { "long", s_arm_elf_cons
, 4 },
4677 { "inst.n", s_arm_elf_inst
, 2 },
4678 { "inst.w", s_arm_elf_inst
, 4 },
4679 { "inst", s_arm_elf_inst
, 0 },
4680 { "rel31", s_arm_rel31
, 0 },
4681 { "fnstart", s_arm_unwind_fnstart
, 0 },
4682 { "fnend", s_arm_unwind_fnend
, 0 },
4683 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4684 { "personality", s_arm_unwind_personality
, 0 },
4685 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4686 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4687 { "save", s_arm_unwind_save
, 0 },
4688 { "vsave", s_arm_unwind_save
, 1 },
4689 { "movsp", s_arm_unwind_movsp
, 0 },
4690 { "pad", s_arm_unwind_pad
, 0 },
4691 { "setfp", s_arm_unwind_setfp
, 0 },
4692 { "unwind_raw", s_arm_unwind_raw
, 0 },
4693 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4694 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4698 /* These are used for dwarf. */
4702 /* These are used for dwarf2. */
4703 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4704 { "loc", dwarf2_directive_loc
, 0 },
4705 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4707 { "extend", float_cons
, 'x' },
4708 { "ldouble", float_cons
, 'x' },
4709 { "packed", float_cons
, 'p' },
4711 {"secrel32", pe_directive_secrel
, 0},
4714 /* These are for compatibility with CodeComposer Studio. */
4715 {"ref", s_ccs_ref
, 0},
4716 {"def", s_ccs_def
, 0},
4717 {"asmfunc", s_ccs_asmfunc
, 0},
4718 {"endasmfunc", s_ccs_endasmfunc
, 0},
4723 /* Parser functions used exclusively in instruction operands. */
4725 /* Generic immediate-value read function for use in insn parsing.
4726 STR points to the beginning of the immediate (the leading #);
4727 VAL receives the value; if the value is outside [MIN, MAX]
4728 issue an error. PREFIX_OPT is true if the immediate prefix is
4732 parse_immediate (char **str
, int *val
, int min
, int max
,
4733 bfd_boolean prefix_opt
)
4736 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4737 if (exp
.X_op
!= O_constant
)
4739 inst
.error
= _("constant expression required");
4743 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4745 inst
.error
= _("immediate value out of range");
4749 *val
= exp
.X_add_number
;
4753 /* Less-generic immediate-value read function with the possibility of loading a
4754 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4755 instructions. Puts the result directly in inst.operands[i]. */
4758 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4759 bfd_boolean allow_symbol_p
)
4762 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4765 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4767 if (exp_p
->X_op
== O_constant
)
4769 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4770 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4771 O_constant. We have to be careful not to break compilation for
4772 32-bit X_add_number, though. */
4773 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4775 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4776 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4778 inst
.operands
[i
].regisimm
= 1;
4781 else if (exp_p
->X_op
== O_big
4782 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4784 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4786 /* Bignums have their least significant bits in
4787 generic_bignum[0]. Make sure we put 32 bits in imm and
4788 32 bits in reg, in a (hopefully) portable way. */
4789 gas_assert (parts
!= 0);
4791 /* Make sure that the number is not too big.
4792 PR 11972: Bignums can now be sign-extended to the
4793 size of a .octa so check that the out of range bits
4794 are all zero or all one. */
4795 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4797 LITTLENUM_TYPE m
= -1;
4799 if (generic_bignum
[parts
* 2] != 0
4800 && generic_bignum
[parts
* 2] != m
)
4803 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4804 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4808 inst
.operands
[i
].imm
= 0;
4809 for (j
= 0; j
< parts
; j
++, idx
++)
4810 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4811 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4812 inst
.operands
[i
].reg
= 0;
4813 for (j
= 0; j
< parts
; j
++, idx
++)
4814 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4815 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4816 inst
.operands
[i
].regisimm
= 1;
4818 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4826 /* Returns the pseudo-register number of an FPA immediate constant,
4827 or FAIL if there isn't a valid constant here. */
4830 parse_fpa_immediate (char ** str
)
4832 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4838 /* First try and match exact strings, this is to guarantee
4839 that some formats will work even for cross assembly. */
4841 for (i
= 0; fp_const
[i
]; i
++)
4843 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4847 *str
+= strlen (fp_const
[i
]);
4848 if (is_end_of_line
[(unsigned char) **str
])
4854 /* Just because we didn't get a match doesn't mean that the constant
4855 isn't valid, just that it is in a format that we don't
4856 automatically recognize. Try parsing it with the standard
4857 expression routines. */
4859 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4861 /* Look for a raw floating point number. */
4862 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4863 && is_end_of_line
[(unsigned char) *save_in
])
4865 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4867 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4869 if (words
[j
] != fp_values
[i
][j
])
4873 if (j
== MAX_LITTLENUMS
)
4881 /* Try and parse a more complex expression, this will probably fail
4882 unless the code uses a floating point prefix (eg "0f"). */
4883 save_in
= input_line_pointer
;
4884 input_line_pointer
= *str
;
4885 if (expression (&exp
) == absolute_section
4886 && exp
.X_op
== O_big
4887 && exp
.X_add_number
< 0)
4889 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4891 #define X_PRECISION 5
4892 #define E_PRECISION 15L
4893 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4895 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4897 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4899 if (words
[j
] != fp_values
[i
][j
])
4903 if (j
== MAX_LITTLENUMS
)
4905 *str
= input_line_pointer
;
4906 input_line_pointer
= save_in
;
4913 *str
= input_line_pointer
;
4914 input_line_pointer
= save_in
;
4915 inst
.error
= _("invalid FPA immediate expression");
4919 /* Returns 1 if a number has "quarter-precision" float format
4920 0baBbbbbbc defgh000 00000000 00000000. */
4923 is_quarter_float (unsigned imm
)
4925 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4926 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4930 /* Detect the presence of a floating point or integer zero constant,
4934 parse_ifimm_zero (char **in
)
4938 if (!is_immediate_prefix (**in
))
4943 /* Accept #0x0 as a synonym for #0. */
4944 if (strncmp (*in
, "0x", 2) == 0)
4947 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4952 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4953 &generic_floating_point_number
);
4956 && generic_floating_point_number
.sign
== '+'
4957 && (generic_floating_point_number
.low
4958 > generic_floating_point_number
.leader
))
4964 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4965 0baBbbbbbc defgh000 00000000 00000000.
4966 The zero and minus-zero cases need special handling, since they can't be
4967 encoded in the "quarter-precision" float format, but can nonetheless be
4968 loaded as integer constants. */
4971 parse_qfloat_immediate (char **ccp
, int *immed
)
4975 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4976 int found_fpchar
= 0;
4978 skip_past_char (&str
, '#');
4980 /* We must not accidentally parse an integer as a floating-point number. Make
4981 sure that the value we parse is not an integer by checking for special
4982 characters '.' or 'e'.
4983 FIXME: This is a horrible hack, but doing better is tricky because type
4984 information isn't in a very usable state at parse time. */
4986 skip_whitespace (fpnum
);
4988 if (strncmp (fpnum
, "0x", 2) == 0)
4992 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4993 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5003 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5005 unsigned fpword
= 0;
5008 /* Our FP word must be 32 bits (single-precision FP). */
5009 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5011 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5015 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5028 /* Shift operands. */
5031 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5034 struct asm_shift_name
5037 enum shift_kind kind
;
5040 /* Third argument to parse_shift. */
5041 enum parse_shift_mode
5043 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5044 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5045 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5046 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5047 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5050 /* Parse a <shift> specifier on an ARM data processing instruction.
5051 This has three forms:
5053 (LSL|LSR|ASL|ASR|ROR) Rs
5054 (LSL|LSR|ASL|ASR|ROR) #imm
5057 Note that ASL is assimilated to LSL in the instruction encoding, and
5058 RRX to ROR #0 (which cannot be written as such). */
5061 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5063 const struct asm_shift_name
*shift_name
;
5064 enum shift_kind shift
;
5069 for (p
= *str
; ISALPHA (*p
); p
++)
5074 inst
.error
= _("shift expression expected");
5078 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5081 if (shift_name
== NULL
)
5083 inst
.error
= _("shift expression expected");
5087 shift
= shift_name
->kind
;
5091 case NO_SHIFT_RESTRICT
:
5092 case SHIFT_IMMEDIATE
: break;
5094 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5095 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5097 inst
.error
= _("'LSL' or 'ASR' required");
5102 case SHIFT_LSL_IMMEDIATE
:
5103 if (shift
!= SHIFT_LSL
)
5105 inst
.error
= _("'LSL' required");
5110 case SHIFT_ASR_IMMEDIATE
:
5111 if (shift
!= SHIFT_ASR
)
5113 inst
.error
= _("'ASR' required");
5121 if (shift
!= SHIFT_RRX
)
5123 /* Whitespace can appear here if the next thing is a bare digit. */
5124 skip_whitespace (p
);
5126 if (mode
== NO_SHIFT_RESTRICT
5127 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5129 inst
.operands
[i
].imm
= reg
;
5130 inst
.operands
[i
].immisreg
= 1;
5132 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5135 inst
.operands
[i
].shift_kind
= shift
;
5136 inst
.operands
[i
].shifted
= 1;
5141 /* Parse a <shifter_operand> for an ARM data processing instruction:
5144 #<immediate>, <rotate>
5148 where <shift> is defined by parse_shift above, and <rotate> is a
5149 multiple of 2 between 0 and 30. Validation of immediate operands
5150 is deferred to md_apply_fix. */
5153 parse_shifter_operand (char **str
, int i
)
5158 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5160 inst
.operands
[i
].reg
= value
;
5161 inst
.operands
[i
].isreg
= 1;
5163 /* parse_shift will override this if appropriate */
5164 inst
.reloc
.exp
.X_op
= O_constant
;
5165 inst
.reloc
.exp
.X_add_number
= 0;
5167 if (skip_past_comma (str
) == FAIL
)
5170 /* Shift operation on register. */
5171 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5174 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5177 if (skip_past_comma (str
) == SUCCESS
)
5179 /* #x, y -- ie explicit rotation by Y. */
5180 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5183 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5185 inst
.error
= _("constant expression expected");
5189 value
= exp
.X_add_number
;
5190 if (value
< 0 || value
> 30 || value
% 2 != 0)
5192 inst
.error
= _("invalid rotation");
5195 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5197 inst
.error
= _("invalid constant");
5201 /* Encode as specified. */
5202 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5206 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5207 inst
.reloc
.pc_rel
= 0;
5211 /* Group relocation information. Each entry in the table contains the
5212 textual name of the relocation as may appear in assembler source
5213 and must end with a colon.
5214 Along with this textual name are the relocation codes to be used if
5215 the corresponding instruction is an ALU instruction (ADD or SUB only),
5216 an LDR, an LDRS, or an LDC. */
5218 struct group_reloc_table_entry
5229 /* Varieties of non-ALU group relocation. */
5236 static struct group_reloc_table_entry group_reloc_table
[] =
5237 { /* Program counter relative: */
5239 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5244 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5245 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5246 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5247 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5249 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5254 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5255 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5256 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5257 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5259 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5260 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5261 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5262 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5263 /* Section base relative */
5265 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5270 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5271 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5272 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5273 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5275 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5280 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5281 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5282 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5283 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5285 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5286 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5287 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5288 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5289 /* Absolute thumb alu relocations. */
5291 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5296 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5301 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5306 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5311 /* Given the address of a pointer pointing to the textual name of a group
5312 relocation as may appear in assembler source, attempt to find its details
5313 in group_reloc_table. The pointer will be updated to the character after
5314 the trailing colon. On failure, FAIL will be returned; SUCCESS
5315 otherwise. On success, *entry will be updated to point at the relevant
5316 group_reloc_table entry. */
5319 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5322 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5324 int length
= strlen (group_reloc_table
[i
].name
);
5326 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5327 && (*str
)[length
] == ':')
5329 *out
= &group_reloc_table
[i
];
5330 *str
+= (length
+ 1);
5338 /* Parse a <shifter_operand> for an ARM data processing instruction
5339 (as for parse_shifter_operand) where group relocations are allowed:
5342 #<immediate>, <rotate>
5343 #:<group_reloc>:<expression>
5347 where <group_reloc> is one of the strings defined in group_reloc_table.
5348 The hashes are optional.
5350 Everything else is as for parse_shifter_operand. */
5352 static parse_operand_result
5353 parse_shifter_operand_group_reloc (char **str
, int i
)
5355 /* Determine if we have the sequence of characters #: or just :
5356 coming next. If we do, then we check for a group relocation.
5357 If we don't, punt the whole lot to parse_shifter_operand. */
5359 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5360 || (*str
)[0] == ':')
5362 struct group_reloc_table_entry
*entry
;
5364 if ((*str
)[0] == '#')
5369 /* Try to parse a group relocation. Anything else is an error. */
5370 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5372 inst
.error
= _("unknown group relocation");
5373 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5376 /* We now have the group relocation table entry corresponding to
5377 the name in the assembler source. Next, we parse the expression. */
5378 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5379 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5381 /* Record the relocation type (always the ALU variant here). */
5382 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5383 gas_assert (inst
.reloc
.type
!= 0);
5385 return PARSE_OPERAND_SUCCESS
;
5388 return parse_shifter_operand (str
, i
) == SUCCESS
5389 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5391 /* Never reached. */
5394 /* Parse a Neon alignment expression. Information is written to
5395 inst.operands[i]. We assume the initial ':' has been skipped.
5397 align .imm = align << 8, .immisalign=1, .preind=0 */
5398 static parse_operand_result
5399 parse_neon_alignment (char **str
, int i
)
5404 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5406 if (exp
.X_op
!= O_constant
)
5408 inst
.error
= _("alignment must be constant");
5409 return PARSE_OPERAND_FAIL
;
5412 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5413 inst
.operands
[i
].immisalign
= 1;
5414 /* Alignments are not pre-indexes. */
5415 inst
.operands
[i
].preind
= 0;
5418 return PARSE_OPERAND_SUCCESS
;
5421 /* Parse all forms of an ARM address expression. Information is written
5422 to inst.operands[i] and/or inst.reloc.
5424 Preindexed addressing (.preind=1):
5426 [Rn, #offset] .reg=Rn .reloc.exp=offset
5427 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5428 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5429 .shift_kind=shift .reloc.exp=shift_imm
5431 These three may have a trailing ! which causes .writeback to be set also.
5433 Postindexed addressing (.postind=1, .writeback=1):
5435 [Rn], #offset .reg=Rn .reloc.exp=offset
5436 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5437 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5438 .shift_kind=shift .reloc.exp=shift_imm
5440 Unindexed addressing (.preind=0, .postind=0):
5442 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5446 [Rn]{!} shorthand for [Rn,#0]{!}
5447 =immediate .isreg=0 .reloc.exp=immediate
5448 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5450 It is the caller's responsibility to check for addressing modes not
5451 supported by the instruction, and to set inst.reloc.type. */
5453 static parse_operand_result
5454 parse_address_main (char **str
, int i
, int group_relocations
,
5455 group_reloc_type group_type
)
5460 if (skip_past_char (&p
, '[') == FAIL
)
5462 if (skip_past_char (&p
, '=') == FAIL
)
5464 /* Bare address - translate to PC-relative offset. */
5465 inst
.reloc
.pc_rel
= 1;
5466 inst
.operands
[i
].reg
= REG_PC
;
5467 inst
.operands
[i
].isreg
= 1;
5468 inst
.operands
[i
].preind
= 1;
5470 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5471 return PARSE_OPERAND_FAIL
;
5473 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5474 /*allow_symbol_p=*/TRUE
))
5475 return PARSE_OPERAND_FAIL
;
5478 return PARSE_OPERAND_SUCCESS
;
5481 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5482 skip_whitespace (p
);
5484 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5486 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5487 return PARSE_OPERAND_FAIL
;
5489 inst
.operands
[i
].reg
= reg
;
5490 inst
.operands
[i
].isreg
= 1;
5492 if (skip_past_comma (&p
) == SUCCESS
)
5494 inst
.operands
[i
].preind
= 1;
5497 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5499 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5501 inst
.operands
[i
].imm
= reg
;
5502 inst
.operands
[i
].immisreg
= 1;
5504 if (skip_past_comma (&p
) == SUCCESS
)
5505 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5506 return PARSE_OPERAND_FAIL
;
5508 else if (skip_past_char (&p
, ':') == SUCCESS
)
5510 /* FIXME: '@' should be used here, but it's filtered out by generic
5511 code before we get to see it here. This may be subject to
5513 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5515 if (result
!= PARSE_OPERAND_SUCCESS
)
5520 if (inst
.operands
[i
].negative
)
5522 inst
.operands
[i
].negative
= 0;
5526 if (group_relocations
5527 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5529 struct group_reloc_table_entry
*entry
;
5531 /* Skip over the #: or : sequence. */
5537 /* Try to parse a group relocation. Anything else is an
5539 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5541 inst
.error
= _("unknown group relocation");
5542 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5545 /* We now have the group relocation table entry corresponding to
5546 the name in the assembler source. Next, we parse the
5548 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5549 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5551 /* Record the relocation type. */
5555 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5559 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5563 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5570 if (inst
.reloc
.type
== 0)
5572 inst
.error
= _("this group relocation is not allowed on this instruction");
5573 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5579 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5580 return PARSE_OPERAND_FAIL
;
5581 /* If the offset is 0, find out if it's a +0 or -0. */
5582 if (inst
.reloc
.exp
.X_op
== O_constant
5583 && inst
.reloc
.exp
.X_add_number
== 0)
5585 skip_whitespace (q
);
5589 skip_whitespace (q
);
5592 inst
.operands
[i
].negative
= 1;
5597 else if (skip_past_char (&p
, ':') == SUCCESS
)
5599 /* FIXME: '@' should be used here, but it's filtered out by generic code
5600 before we get to see it here. This may be subject to change. */
5601 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5603 if (result
!= PARSE_OPERAND_SUCCESS
)
5607 if (skip_past_char (&p
, ']') == FAIL
)
5609 inst
.error
= _("']' expected");
5610 return PARSE_OPERAND_FAIL
;
5613 if (skip_past_char (&p
, '!') == SUCCESS
)
5614 inst
.operands
[i
].writeback
= 1;
5616 else if (skip_past_comma (&p
) == SUCCESS
)
5618 if (skip_past_char (&p
, '{') == SUCCESS
)
5620 /* [Rn], {expr} - unindexed, with option */
5621 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5622 0, 255, TRUE
) == FAIL
)
5623 return PARSE_OPERAND_FAIL
;
5625 if (skip_past_char (&p
, '}') == FAIL
)
5627 inst
.error
= _("'}' expected at end of 'option' field");
5628 return PARSE_OPERAND_FAIL
;
5630 if (inst
.operands
[i
].preind
)
5632 inst
.error
= _("cannot combine index with option");
5633 return PARSE_OPERAND_FAIL
;
5636 return PARSE_OPERAND_SUCCESS
;
5640 inst
.operands
[i
].postind
= 1;
5641 inst
.operands
[i
].writeback
= 1;
5643 if (inst
.operands
[i
].preind
)
5645 inst
.error
= _("cannot combine pre- and post-indexing");
5646 return PARSE_OPERAND_FAIL
;
5650 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5652 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5654 /* We might be using the immediate for alignment already. If we
5655 are, OR the register number into the low-order bits. */
5656 if (inst
.operands
[i
].immisalign
)
5657 inst
.operands
[i
].imm
|= reg
;
5659 inst
.operands
[i
].imm
= reg
;
5660 inst
.operands
[i
].immisreg
= 1;
5662 if (skip_past_comma (&p
) == SUCCESS
)
5663 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5664 return PARSE_OPERAND_FAIL
;
5669 if (inst
.operands
[i
].negative
)
5671 inst
.operands
[i
].negative
= 0;
5674 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5675 return PARSE_OPERAND_FAIL
;
5676 /* If the offset is 0, find out if it's a +0 or -0. */
5677 if (inst
.reloc
.exp
.X_op
== O_constant
5678 && inst
.reloc
.exp
.X_add_number
== 0)
5680 skip_whitespace (q
);
5684 skip_whitespace (q
);
5687 inst
.operands
[i
].negative
= 1;
5693 /* If at this point neither .preind nor .postind is set, we have a
5694 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5695 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5697 inst
.operands
[i
].preind
= 1;
5698 inst
.reloc
.exp
.X_op
= O_constant
;
5699 inst
.reloc
.exp
.X_add_number
= 0;
5702 return PARSE_OPERAND_SUCCESS
;
5706 parse_address (char **str
, int i
)
5708 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5712 static parse_operand_result
5713 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5715 return parse_address_main (str
, i
, 1, type
);
5718 /* Parse an operand for a MOVW or MOVT instruction. */
5720 parse_half (char **str
)
5725 skip_past_char (&p
, '#');
5726 if (strncasecmp (p
, ":lower16:", 9) == 0)
5727 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5728 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5729 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5731 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5734 skip_whitespace (p
);
5737 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5740 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5742 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5744 inst
.error
= _("constant expression expected");
5747 if (inst
.reloc
.exp
.X_add_number
< 0
5748 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5750 inst
.error
= _("immediate value out of range");
5758 /* Miscellaneous. */
5760 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5761 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5763 parse_psr (char **str
, bfd_boolean lhs
)
5766 unsigned long psr_field
;
5767 const struct asm_psr
*psr
;
5769 bfd_boolean is_apsr
= FALSE
;
5770 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5772 /* PR gas/12698: If the user has specified -march=all then m_profile will
5773 be TRUE, but we want to ignore it in this case as we are building for any
5774 CPU type, including non-m variants. */
5775 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5778 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5779 feature for ease of use and backwards compatibility. */
5781 if (strncasecmp (p
, "SPSR", 4) == 0)
5784 goto unsupported_psr
;
5786 psr_field
= SPSR_BIT
;
5788 else if (strncasecmp (p
, "CPSR", 4) == 0)
5791 goto unsupported_psr
;
5795 else if (strncasecmp (p
, "APSR", 4) == 0)
5797 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5798 and ARMv7-R architecture CPUs. */
5807 while (ISALNUM (*p
) || *p
== '_');
5809 if (strncasecmp (start
, "iapsr", 5) == 0
5810 || strncasecmp (start
, "eapsr", 5) == 0
5811 || strncasecmp (start
, "xpsr", 4) == 0
5812 || strncasecmp (start
, "psr", 3) == 0)
5813 p
= start
+ strcspn (start
, "rR") + 1;
5815 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5821 /* If APSR is being written, a bitfield may be specified. Note that
5822 APSR itself is handled above. */
5823 if (psr
->field
<= 3)
5825 psr_field
= psr
->field
;
5831 /* M-profile MSR instructions have the mask field set to "10", except
5832 *PSR variants which modify APSR, which may use a different mask (and
5833 have been handled already). Do that by setting the PSR_f field
5835 return psr
->field
| (lhs
? PSR_f
: 0);
5838 goto unsupported_psr
;
5844 /* A suffix follows. */
5850 while (ISALNUM (*p
) || *p
== '_');
5854 /* APSR uses a notation for bits, rather than fields. */
5855 unsigned int nzcvq_bits
= 0;
5856 unsigned int g_bit
= 0;
5859 for (bit
= start
; bit
!= p
; bit
++)
5861 switch (TOLOWER (*bit
))
5864 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5868 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5872 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5876 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5880 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5884 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5888 inst
.error
= _("unexpected bit specified after APSR");
5893 if (nzcvq_bits
== 0x1f)
5898 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5900 inst
.error
= _("selected processor does not "
5901 "support DSP extension");
5908 if ((nzcvq_bits
& 0x20) != 0
5909 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5910 || (g_bit
& 0x2) != 0)
5912 inst
.error
= _("bad bitmask specified after APSR");
5918 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5923 psr_field
|= psr
->field
;
5929 goto error
; /* Garbage after "[CS]PSR". */
5931 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5932 is deprecated, but allow it anyway. */
5936 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5939 else if (!m_profile
)
5940 /* These bits are never right for M-profile devices: don't set them
5941 (only code paths which read/write APSR reach here). */
5942 psr_field
|= (PSR_c
| PSR_f
);
5948 inst
.error
= _("selected processor does not support requested special "
5949 "purpose register");
5953 inst
.error
= _("flag for {c}psr instruction expected");
5957 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5958 value suitable for splatting into the AIF field of the instruction. */
5961 parse_cps_flags (char **str
)
5970 case '\0': case ',':
5973 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5974 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5975 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5978 inst
.error
= _("unrecognized CPS flag");
5983 if (saw_a_flag
== 0)
5985 inst
.error
= _("missing CPS flags");
5993 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5994 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5997 parse_endian_specifier (char **str
)
6002 if (strncasecmp (s
, "BE", 2))
6004 else if (strncasecmp (s
, "LE", 2))
6008 inst
.error
= _("valid endian specifiers are be or le");
6012 if (ISALNUM (s
[2]) || s
[2] == '_')
6014 inst
.error
= _("valid endian specifiers are be or le");
6019 return little_endian
;
6022 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6023 value suitable for poking into the rotate field of an sxt or sxta
6024 instruction, or FAIL on error. */
6027 parse_ror (char **str
)
6032 if (strncasecmp (s
, "ROR", 3) == 0)
6036 inst
.error
= _("missing rotation field after comma");
6040 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6045 case 0: *str
= s
; return 0x0;
6046 case 8: *str
= s
; return 0x1;
6047 case 16: *str
= s
; return 0x2;
6048 case 24: *str
= s
; return 0x3;
6051 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6056 /* Parse a conditional code (from conds[] below). The value returned is in the
6057 range 0 .. 14, or FAIL. */
6059 parse_cond (char **str
)
6062 const struct asm_cond
*c
;
6064 /* Condition codes are always 2 characters, so matching up to
6065 3 characters is sufficient. */
6070 while (ISALPHA (*q
) && n
< 3)
6072 cond
[n
] = TOLOWER (*q
);
6077 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6080 inst
.error
= _("condition required");
6088 /* Record a use of the given feature. */
6090 record_feature_use (const arm_feature_set
*feature
)
6093 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6095 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6098 /* If the given feature available in the selected CPU, mark it as used.
6099 Returns TRUE iff feature is available. */
6101 mark_feature_used (const arm_feature_set
*feature
)
6103 /* Ensure the option is valid on the current architecture. */
6104 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6107 /* Add the appropriate architecture feature for the barrier option used.
6109 record_feature_use (feature
);
6114 /* Parse an option for a barrier instruction. Returns the encoding for the
6117 parse_barrier (char **str
)
6120 const struct asm_barrier_opt
*o
;
6123 while (ISALPHA (*q
))
6126 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6131 if (!mark_feature_used (&o
->arch
))
6138 /* Parse the operands of a table branch instruction. Similar to a memory
6141 parse_tb (char **str
)
6146 if (skip_past_char (&p
, '[') == FAIL
)
6148 inst
.error
= _("'[' expected");
6152 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6154 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6157 inst
.operands
[0].reg
= reg
;
6159 if (skip_past_comma (&p
) == FAIL
)
6161 inst
.error
= _("',' expected");
6165 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6167 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6170 inst
.operands
[0].imm
= reg
;
6172 if (skip_past_comma (&p
) == SUCCESS
)
6174 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6176 if (inst
.reloc
.exp
.X_add_number
!= 1)
6178 inst
.error
= _("invalid shift");
6181 inst
.operands
[0].shifted
= 1;
6184 if (skip_past_char (&p
, ']') == FAIL
)
6186 inst
.error
= _("']' expected");
6193 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6194 information on the types the operands can take and how they are encoded.
6195 Up to four operands may be read; this function handles setting the
6196 ".present" field for each read operand itself.
6197 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6198 else returns FAIL. */
6201 parse_neon_mov (char **str
, int *which_operand
)
6203 int i
= *which_operand
, val
;
6204 enum arm_reg_type rtype
;
6206 struct neon_type_el optype
;
6208 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6210 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6211 inst
.operands
[i
].reg
= val
;
6212 inst
.operands
[i
].isscalar
= 1;
6213 inst
.operands
[i
].vectype
= optype
;
6214 inst
.operands
[i
++].present
= 1;
6216 if (skip_past_comma (&ptr
) == FAIL
)
6219 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6222 inst
.operands
[i
].reg
= val
;
6223 inst
.operands
[i
].isreg
= 1;
6224 inst
.operands
[i
].present
= 1;
6226 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6229 /* Cases 0, 1, 2, 3, 5 (D only). */
6230 if (skip_past_comma (&ptr
) == FAIL
)
6233 inst
.operands
[i
].reg
= val
;
6234 inst
.operands
[i
].isreg
= 1;
6235 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6236 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6237 inst
.operands
[i
].isvec
= 1;
6238 inst
.operands
[i
].vectype
= optype
;
6239 inst
.operands
[i
++].present
= 1;
6241 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6243 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6244 Case 13: VMOV <Sd>, <Rm> */
6245 inst
.operands
[i
].reg
= val
;
6246 inst
.operands
[i
].isreg
= 1;
6247 inst
.operands
[i
].present
= 1;
6249 if (rtype
== REG_TYPE_NQ
)
6251 first_error (_("can't use Neon quad register here"));
6254 else if (rtype
!= REG_TYPE_VFS
)
6257 if (skip_past_comma (&ptr
) == FAIL
)
6259 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6261 inst
.operands
[i
].reg
= val
;
6262 inst
.operands
[i
].isreg
= 1;
6263 inst
.operands
[i
].present
= 1;
6266 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6269 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6270 Case 1: VMOV<c><q> <Dd>, <Dm>
6271 Case 8: VMOV.F32 <Sd>, <Sm>
6272 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6274 inst
.operands
[i
].reg
= val
;
6275 inst
.operands
[i
].isreg
= 1;
6276 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6277 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6278 inst
.operands
[i
].isvec
= 1;
6279 inst
.operands
[i
].vectype
= optype
;
6280 inst
.operands
[i
].present
= 1;
6282 if (skip_past_comma (&ptr
) == SUCCESS
)
6287 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6290 inst
.operands
[i
].reg
= val
;
6291 inst
.operands
[i
].isreg
= 1;
6292 inst
.operands
[i
++].present
= 1;
6294 if (skip_past_comma (&ptr
) == FAIL
)
6297 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6300 inst
.operands
[i
].reg
= val
;
6301 inst
.operands
[i
].isreg
= 1;
6302 inst
.operands
[i
].present
= 1;
6305 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6306 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6307 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6308 Case 10: VMOV.F32 <Sd>, #<imm>
6309 Case 11: VMOV.F64 <Dd>, #<imm> */
6310 inst
.operands
[i
].immisfloat
= 1;
6311 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6313 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6314 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6318 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6322 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6325 inst
.operands
[i
].reg
= val
;
6326 inst
.operands
[i
].isreg
= 1;
6327 inst
.operands
[i
++].present
= 1;
6329 if (skip_past_comma (&ptr
) == FAIL
)
6332 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6334 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6335 inst
.operands
[i
].reg
= val
;
6336 inst
.operands
[i
].isscalar
= 1;
6337 inst
.operands
[i
].present
= 1;
6338 inst
.operands
[i
].vectype
= optype
;
6340 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6342 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6343 inst
.operands
[i
].reg
= val
;
6344 inst
.operands
[i
].isreg
= 1;
6345 inst
.operands
[i
++].present
= 1;
6347 if (skip_past_comma (&ptr
) == FAIL
)
6350 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6353 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6357 inst
.operands
[i
].reg
= val
;
6358 inst
.operands
[i
].isreg
= 1;
6359 inst
.operands
[i
].isvec
= 1;
6360 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6361 inst
.operands
[i
].vectype
= optype
;
6362 inst
.operands
[i
].present
= 1;
6364 if (rtype
== REG_TYPE_VFS
)
6368 if (skip_past_comma (&ptr
) == FAIL
)
6370 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6373 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6376 inst
.operands
[i
].reg
= val
;
6377 inst
.operands
[i
].isreg
= 1;
6378 inst
.operands
[i
].isvec
= 1;
6379 inst
.operands
[i
].issingle
= 1;
6380 inst
.operands
[i
].vectype
= optype
;
6381 inst
.operands
[i
].present
= 1;
6384 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6388 inst
.operands
[i
].reg
= val
;
6389 inst
.operands
[i
].isreg
= 1;
6390 inst
.operands
[i
].isvec
= 1;
6391 inst
.operands
[i
].issingle
= 1;
6392 inst
.operands
[i
].vectype
= optype
;
6393 inst
.operands
[i
].present
= 1;
6398 first_error (_("parse error"));
6402 /* Successfully parsed the operands. Update args. */
6408 first_error (_("expected comma"));
6412 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6416 /* Use this macro when the operand constraints are different
6417 for ARM and THUMB (e.g. ldrd). */
6418 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6419 ((arm_operand) | ((thumb_operand) << 16))
6421 /* Matcher codes for parse_operands. */
6422 enum operand_parse_code
6424 OP_stop
, /* end of line */
6426 OP_RR
, /* ARM register */
6427 OP_RRnpc
, /* ARM register, not r15 */
6428 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6429 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6430 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6431 optional trailing ! */
6432 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6433 OP_RCP
, /* Coprocessor number */
6434 OP_RCN
, /* Coprocessor register */
6435 OP_RF
, /* FPA register */
6436 OP_RVS
, /* VFP single precision register */
6437 OP_RVD
, /* VFP double precision register (0..15) */
6438 OP_RND
, /* Neon double precision register (0..31) */
6439 OP_RNQ
, /* Neon quad precision register */
6440 OP_RVSD
, /* VFP single or double precision register */
6441 OP_RNDQ
, /* Neon double or quad precision register */
6442 OP_RNSDQ
, /* Neon single, double or quad precision register */
6443 OP_RNSC
, /* Neon scalar D[X] */
6444 OP_RVC
, /* VFP control register */
6445 OP_RMF
, /* Maverick F register */
6446 OP_RMD
, /* Maverick D register */
6447 OP_RMFX
, /* Maverick FX register */
6448 OP_RMDX
, /* Maverick DX register */
6449 OP_RMAX
, /* Maverick AX register */
6450 OP_RMDS
, /* Maverick DSPSC register */
6451 OP_RIWR
, /* iWMMXt wR register */
6452 OP_RIWC
, /* iWMMXt wC register */
6453 OP_RIWG
, /* iWMMXt wCG register */
6454 OP_RXA
, /* XScale accumulator register */
6456 OP_REGLST
, /* ARM register list */
6457 OP_VRSLST
, /* VFP single-precision register list */
6458 OP_VRDLST
, /* VFP double-precision register list */
6459 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6460 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6461 OP_NSTRLST
, /* Neon element/structure list */
6463 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6464 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6465 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6466 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6467 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6468 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6469 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6470 OP_VMOV
, /* Neon VMOV operands. */
6471 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6472 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6473 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6475 OP_I0
, /* immediate zero */
6476 OP_I7
, /* immediate value 0 .. 7 */
6477 OP_I15
, /* 0 .. 15 */
6478 OP_I16
, /* 1 .. 16 */
6479 OP_I16z
, /* 0 .. 16 */
6480 OP_I31
, /* 0 .. 31 */
6481 OP_I31w
, /* 0 .. 31, optional trailing ! */
6482 OP_I32
, /* 1 .. 32 */
6483 OP_I32z
, /* 0 .. 32 */
6484 OP_I63
, /* 0 .. 63 */
6485 OP_I63s
, /* -64 .. 63 */
6486 OP_I64
, /* 1 .. 64 */
6487 OP_I64z
, /* 0 .. 64 */
6488 OP_I255
, /* 0 .. 255 */
6490 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6491 OP_I7b
, /* 0 .. 7 */
6492 OP_I15b
, /* 0 .. 15 */
6493 OP_I31b
, /* 0 .. 31 */
6495 OP_SH
, /* shifter operand */
6496 OP_SHG
, /* shifter operand with possible group relocation */
6497 OP_ADDR
, /* Memory address expression (any mode) */
6498 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6499 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6500 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6501 OP_EXP
, /* arbitrary expression */
6502 OP_EXPi
, /* same, with optional immediate prefix */
6503 OP_EXPr
, /* same, with optional relocation suffix */
6504 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6506 OP_CPSF
, /* CPS flags */
6507 OP_ENDI
, /* Endianness specifier */
6508 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6509 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6510 OP_COND
, /* conditional code */
6511 OP_TB
, /* Table branch. */
6513 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6515 OP_RRnpc_I0
, /* ARM register or literal 0 */
6516 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6517 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6518 OP_RF_IF
, /* FPA register or immediate */
6519 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6520 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6522 /* Optional operands. */
6523 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6524 OP_oI31b
, /* 0 .. 31 */
6525 OP_oI32b
, /* 1 .. 32 */
6526 OP_oI32z
, /* 0 .. 32 */
6527 OP_oIffffb
, /* 0 .. 65535 */
6528 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6530 OP_oRR
, /* ARM register */
6531 OP_oRRnpc
, /* ARM register, not the PC */
6532 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6533 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6534 OP_oRND
, /* Optional Neon double precision register */
6535 OP_oRNQ
, /* Optional Neon quad precision register */
6536 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6537 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6538 OP_oSHll
, /* LSL immediate */
6539 OP_oSHar
, /* ASR immediate */
6540 OP_oSHllar
, /* LSL or ASR immediate */
6541 OP_oROR
, /* ROR 0/8/16/24 */
6542 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6544 /* Some pre-defined mixed (ARM/THUMB) operands. */
6545 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6546 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6547 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6549 OP_FIRST_OPTIONAL
= OP_oI7b
6552 /* Generic instruction operand parser. This does no encoding and no
6553 semantic validation; it merely squirrels values away in the inst
6554 structure. Returns SUCCESS or FAIL depending on whether the
6555 specified grammar matched. */
6557 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6559 unsigned const int *upat
= pattern
;
6560 char *backtrack_pos
= 0;
6561 const char *backtrack_error
= 0;
6562 int i
, val
= 0, backtrack_index
= 0;
6563 enum arm_reg_type rtype
;
6564 parse_operand_result result
;
6565 unsigned int op_parse_code
;
6567 #define po_char_or_fail(chr) \
6570 if (skip_past_char (&str, chr) == FAIL) \
6575 #define po_reg_or_fail(regtype) \
6578 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6579 & inst.operands[i].vectype); \
6582 first_error (_(reg_expected_msgs[regtype])); \
6585 inst.operands[i].reg = val; \
6586 inst.operands[i].isreg = 1; \
6587 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6588 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6589 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6590 || rtype == REG_TYPE_VFD \
6591 || rtype == REG_TYPE_NQ); \
6595 #define po_reg_or_goto(regtype, label) \
6598 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6599 & inst.operands[i].vectype); \
6603 inst.operands[i].reg = val; \
6604 inst.operands[i].isreg = 1; \
6605 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6606 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6607 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6608 || rtype == REG_TYPE_VFD \
6609 || rtype == REG_TYPE_NQ); \
6613 #define po_imm_or_fail(min, max, popt) \
6616 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6618 inst.operands[i].imm = val; \
6622 #define po_scalar_or_goto(elsz, label) \
6625 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6628 inst.operands[i].reg = val; \
6629 inst.operands[i].isscalar = 1; \
6633 #define po_misc_or_fail(expr) \
6641 #define po_misc_or_fail_no_backtrack(expr) \
6645 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6646 backtrack_pos = 0; \
6647 if (result != PARSE_OPERAND_SUCCESS) \
6652 #define po_barrier_or_imm(str) \
6655 val = parse_barrier (&str); \
6656 if (val == FAIL && ! ISALPHA (*str)) \
6659 /* ISB can only take SY as an option. */ \
6660 || ((inst.instruction & 0xf0) == 0x60 \
6663 inst.error = _("invalid barrier type"); \
6664 backtrack_pos = 0; \
6670 skip_whitespace (str
);
6672 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6674 op_parse_code
= upat
[i
];
6675 if (op_parse_code
>= 1<<16)
6676 op_parse_code
= thumb
? (op_parse_code
>> 16)
6677 : (op_parse_code
& ((1<<16)-1));
6679 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6681 /* Remember where we are in case we need to backtrack. */
6682 gas_assert (!backtrack_pos
);
6683 backtrack_pos
= str
;
6684 backtrack_error
= inst
.error
;
6685 backtrack_index
= i
;
6688 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6689 po_char_or_fail (',');
6691 switch (op_parse_code
)
6699 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6700 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6701 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6702 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6703 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6704 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6706 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6708 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6710 /* Also accept generic coprocessor regs for unknown registers. */
6712 po_reg_or_fail (REG_TYPE_CN
);
6714 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6715 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6716 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6717 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6718 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6719 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6720 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6721 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6722 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6723 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6725 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6727 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6728 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6730 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6732 /* Neon scalar. Using an element size of 8 means that some invalid
6733 scalars are accepted here, so deal with those in later code. */
6734 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6738 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6741 po_imm_or_fail (0, 0, TRUE
);
6746 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6751 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6754 if (parse_ifimm_zero (&str
))
6755 inst
.operands
[i
].imm
= 0;
6759 = _("only floating point zero is allowed as immediate value");
6767 po_scalar_or_goto (8, try_rr
);
6770 po_reg_or_fail (REG_TYPE_RN
);
6776 po_scalar_or_goto (8, try_nsdq
);
6779 po_reg_or_fail (REG_TYPE_NSDQ
);
6785 po_scalar_or_goto (8, try_ndq
);
6788 po_reg_or_fail (REG_TYPE_NDQ
);
6794 po_scalar_or_goto (8, try_vfd
);
6797 po_reg_or_fail (REG_TYPE_VFD
);
6802 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6803 not careful then bad things might happen. */
6804 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6809 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6812 /* There's a possibility of getting a 64-bit immediate here, so
6813 we need special handling. */
6814 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6817 inst
.error
= _("immediate value is out of range");
6825 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6828 po_imm_or_fail (0, 63, TRUE
);
6833 po_char_or_fail ('[');
6834 po_reg_or_fail (REG_TYPE_RN
);
6835 po_char_or_fail (']');
6841 po_reg_or_fail (REG_TYPE_RN
);
6842 if (skip_past_char (&str
, '!') == SUCCESS
)
6843 inst
.operands
[i
].writeback
= 1;
6847 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6848 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6849 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6850 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6851 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6852 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6853 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6854 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6855 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6856 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6857 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6858 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6860 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6862 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6863 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6865 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6866 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6867 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6868 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6870 /* Immediate variants */
6872 po_char_or_fail ('{');
6873 po_imm_or_fail (0, 255, TRUE
);
6874 po_char_or_fail ('}');
6878 /* The expression parser chokes on a trailing !, so we have
6879 to find it first and zap it. */
6882 while (*s
&& *s
!= ',')
6887 inst
.operands
[i
].writeback
= 1;
6889 po_imm_or_fail (0, 31, TRUE
);
6897 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6902 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6907 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6909 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6911 val
= parse_reloc (&str
);
6914 inst
.error
= _("unrecognized relocation suffix");
6917 else if (val
!= BFD_RELOC_UNUSED
)
6919 inst
.operands
[i
].imm
= val
;
6920 inst
.operands
[i
].hasreloc
= 1;
6925 /* Operand for MOVW or MOVT. */
6927 po_misc_or_fail (parse_half (&str
));
6930 /* Register or expression. */
6931 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6932 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6934 /* Register or immediate. */
6935 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6936 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6938 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6940 if (!is_immediate_prefix (*str
))
6943 val
= parse_fpa_immediate (&str
);
6946 /* FPA immediates are encoded as registers 8-15.
6947 parse_fpa_immediate has already applied the offset. */
6948 inst
.operands
[i
].reg
= val
;
6949 inst
.operands
[i
].isreg
= 1;
6952 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6953 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6955 /* Two kinds of register. */
6958 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6960 || (rege
->type
!= REG_TYPE_MMXWR
6961 && rege
->type
!= REG_TYPE_MMXWC
6962 && rege
->type
!= REG_TYPE_MMXWCG
))
6964 inst
.error
= _("iWMMXt data or control register expected");
6967 inst
.operands
[i
].reg
= rege
->number
;
6968 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6974 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6976 || (rege
->type
!= REG_TYPE_MMXWC
6977 && rege
->type
!= REG_TYPE_MMXWCG
))
6979 inst
.error
= _("iWMMXt control register expected");
6982 inst
.operands
[i
].reg
= rege
->number
;
6983 inst
.operands
[i
].isreg
= 1;
6988 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6989 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6990 case OP_oROR
: val
= parse_ror (&str
); break;
6991 case OP_COND
: val
= parse_cond (&str
); break;
6992 case OP_oBARRIER_I15
:
6993 po_barrier_or_imm (str
); break;
6995 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7001 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7002 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7004 inst
.error
= _("Banked registers are not available with this "
7010 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7014 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7017 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7019 if (strncasecmp (str
, "APSR_", 5) == 0)
7026 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7027 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7028 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7029 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7030 default: found
= 16;
7034 inst
.operands
[i
].isvec
= 1;
7035 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7036 inst
.operands
[i
].reg
= REG_PC
;
7043 po_misc_or_fail (parse_tb (&str
));
7046 /* Register lists. */
7048 val
= parse_reg_list (&str
);
7051 inst
.operands
[i
].writeback
= 1;
7057 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7061 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7065 /* Allow Q registers too. */
7066 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7071 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7073 inst
.operands
[i
].issingle
= 1;
7078 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7083 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7084 &inst
.operands
[i
].vectype
);
7087 /* Addressing modes */
7089 po_misc_or_fail (parse_address (&str
, i
));
7093 po_misc_or_fail_no_backtrack (
7094 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7098 po_misc_or_fail_no_backtrack (
7099 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7103 po_misc_or_fail_no_backtrack (
7104 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7108 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7112 po_misc_or_fail_no_backtrack (
7113 parse_shifter_operand_group_reloc (&str
, i
));
7117 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7121 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7125 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7129 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7132 /* Various value-based sanity checks and shared operations. We
7133 do not signal immediate failures for the register constraints;
7134 this allows a syntax error to take precedence. */
7135 switch (op_parse_code
)
7143 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7144 inst
.error
= BAD_PC
;
7149 if (inst
.operands
[i
].isreg
)
7151 if (inst
.operands
[i
].reg
== REG_PC
)
7152 inst
.error
= BAD_PC
;
7153 else if (inst
.operands
[i
].reg
== REG_SP
)
7154 inst
.error
= BAD_SP
;
7159 if (inst
.operands
[i
].isreg
7160 && inst
.operands
[i
].reg
== REG_PC
7161 && (inst
.operands
[i
].writeback
|| thumb
))
7162 inst
.error
= BAD_PC
;
7171 case OP_oBARRIER_I15
:
7180 inst
.operands
[i
].imm
= val
;
7187 /* If we get here, this operand was successfully parsed. */
7188 inst
.operands
[i
].present
= 1;
7192 inst
.error
= BAD_ARGS
;
7197 /* The parse routine should already have set inst.error, but set a
7198 default here just in case. */
7200 inst
.error
= _("syntax error");
7204 /* Do not backtrack over a trailing optional argument that
7205 absorbed some text. We will only fail again, with the
7206 'garbage following instruction' error message, which is
7207 probably less helpful than the current one. */
7208 if (backtrack_index
== i
&& backtrack_pos
!= str
7209 && upat
[i
+1] == OP_stop
)
7212 inst
.error
= _("syntax error");
7216 /* Try again, skipping the optional argument at backtrack_pos. */
7217 str
= backtrack_pos
;
7218 inst
.error
= backtrack_error
;
7219 inst
.operands
[backtrack_index
].present
= 0;
7220 i
= backtrack_index
;
7224 /* Check that we have parsed all the arguments. */
7225 if (*str
!= '\0' && !inst
.error
)
7226 inst
.error
= _("garbage following instruction");
7228 return inst
.error
? FAIL
: SUCCESS
;
7231 #undef po_char_or_fail
7232 #undef po_reg_or_fail
7233 #undef po_reg_or_goto
7234 #undef po_imm_or_fail
7235 #undef po_scalar_or_fail
7236 #undef po_barrier_or_imm
7238 /* Shorthand macro for instruction encoding functions issuing errors. */
7239 #define constraint(expr, err) \
7250 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7251 instructions are unpredictable if these registers are used. This
7252 is the BadReg predicate in ARM's Thumb-2 documentation. */
7253 #define reject_bad_reg(reg) \
7255 if (reg == REG_SP || reg == REG_PC) \
7257 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7262 /* If REG is R13 (the stack pointer), warn that its use is
7264 #define warn_deprecated_sp(reg) \
7266 if (warn_on_deprecated && reg == REG_SP) \
7267 as_tsktsk (_("use of r13 is deprecated")); \
7270 /* Functions for operand encoding. ARM, then Thumb. */
7272 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7274 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7276 The only binary encoding difference is the Coprocessor number. Coprocessor
7277 9 is used for half-precision calculations or conversions. The format of the
7278 instruction is the same as the equivalent Coprocessor 10 instuction that
7279 exists for Single-Precision operation. */
7282 do_scalar_fp16_v82_encode (void)
7284 if (inst
.cond
!= COND_ALWAYS
)
7285 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7286 " the behaviour is UNPREDICTABLE"));
7287 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7290 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7291 mark_feature_used (&arm_ext_fp16
);
7294 /* If VAL can be encoded in the immediate field of an ARM instruction,
7295 return the encoded form. Otherwise, return FAIL. */
7298 encode_arm_immediate (unsigned int val
)
7305 for (i
= 2; i
< 32; i
+= 2)
7306 if ((a
= rotate_left (val
, i
)) <= 0xff)
7307 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7312 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7313 return the encoded form. Otherwise, return FAIL. */
7315 encode_thumb32_immediate (unsigned int val
)
7322 for (i
= 1; i
<= 24; i
++)
7325 if ((val
& ~(0xff << i
)) == 0)
7326 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7330 if (val
== ((a
<< 16) | a
))
7332 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7336 if (val
== ((a
<< 16) | a
))
7337 return 0x200 | (a
>> 8);
7341 /* Encode a VFP SP or DP register number into inst.instruction. */
7344 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7346 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7349 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7352 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7355 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7360 first_error (_("D register out of range for selected VFP version"));
7368 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7372 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7376 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7380 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7384 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7388 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7396 /* Encode a <shift> in an ARM-format instruction. The immediate,
7397 if any, is handled by md_apply_fix. */
7399 encode_arm_shift (int i
)
7401 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7402 inst
.instruction
|= SHIFT_ROR
<< 5;
7405 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7406 if (inst
.operands
[i
].immisreg
)
7408 inst
.instruction
|= SHIFT_BY_REG
;
7409 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7412 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7417 encode_arm_shifter_operand (int i
)
7419 if (inst
.operands
[i
].isreg
)
7421 inst
.instruction
|= inst
.operands
[i
].reg
;
7422 encode_arm_shift (i
);
7426 inst
.instruction
|= INST_IMMEDIATE
;
7427 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7428 inst
.instruction
|= inst
.operands
[i
].imm
;
7432 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7434 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7437 Generate an error if the operand is not a register. */
7438 constraint (!inst
.operands
[i
].isreg
,
7439 _("Instruction does not support =N addresses"));
7441 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7443 if (inst
.operands
[i
].preind
)
7447 inst
.error
= _("instruction does not accept preindexed addressing");
7450 inst
.instruction
|= PRE_INDEX
;
7451 if (inst
.operands
[i
].writeback
)
7452 inst
.instruction
|= WRITE_BACK
;
7455 else if (inst
.operands
[i
].postind
)
7457 gas_assert (inst
.operands
[i
].writeback
);
7459 inst
.instruction
|= WRITE_BACK
;
7461 else /* unindexed - only for coprocessor */
7463 inst
.error
= _("instruction does not accept unindexed addressing");
7467 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7468 && (((inst
.instruction
& 0x000f0000) >> 16)
7469 == ((inst
.instruction
& 0x0000f000) >> 12)))
7470 as_warn ((inst
.instruction
& LOAD_BIT
)
7471 ? _("destination register same as write-back base")
7472 : _("source register same as write-back base"));
7475 /* inst.operands[i] was set up by parse_address. Encode it into an
7476 ARM-format mode 2 load or store instruction. If is_t is true,
7477 reject forms that cannot be used with a T instruction (i.e. not
7480 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7482 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7484 encode_arm_addr_mode_common (i
, is_t
);
7486 if (inst
.operands
[i
].immisreg
)
7488 constraint ((inst
.operands
[i
].imm
== REG_PC
7489 || (is_pc
&& inst
.operands
[i
].writeback
)),
7491 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7492 inst
.instruction
|= inst
.operands
[i
].imm
;
7493 if (!inst
.operands
[i
].negative
)
7494 inst
.instruction
|= INDEX_UP
;
7495 if (inst
.operands
[i
].shifted
)
7497 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7498 inst
.instruction
|= SHIFT_ROR
<< 5;
7501 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7502 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7506 else /* immediate offset in inst.reloc */
7508 if (is_pc
&& !inst
.reloc
.pc_rel
)
7510 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7512 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7513 cannot use PC in addressing.
7514 PC cannot be used in writeback addressing, either. */
7515 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7518 /* Use of PC in str is deprecated for ARMv7. */
7519 if (warn_on_deprecated
7521 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7522 as_tsktsk (_("use of PC in this instruction is deprecated"));
7525 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7527 /* Prefer + for zero encoded value. */
7528 if (!inst
.operands
[i
].negative
)
7529 inst
.instruction
|= INDEX_UP
;
7530 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7535 /* inst.operands[i] was set up by parse_address. Encode it into an
7536 ARM-format mode 3 load or store instruction. Reject forms that
7537 cannot be used with such instructions. If is_t is true, reject
7538 forms that cannot be used with a T instruction (i.e. not
7541 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7543 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7545 inst
.error
= _("instruction does not accept scaled register index");
7549 encode_arm_addr_mode_common (i
, is_t
);
7551 if (inst
.operands
[i
].immisreg
)
7553 constraint ((inst
.operands
[i
].imm
== REG_PC
7554 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7556 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7558 inst
.instruction
|= inst
.operands
[i
].imm
;
7559 if (!inst
.operands
[i
].negative
)
7560 inst
.instruction
|= INDEX_UP
;
7562 else /* immediate offset in inst.reloc */
7564 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7565 && inst
.operands
[i
].writeback
),
7567 inst
.instruction
|= HWOFFSET_IMM
;
7568 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7570 /* Prefer + for zero encoded value. */
7571 if (!inst
.operands
[i
].negative
)
7572 inst
.instruction
|= INDEX_UP
;
7574 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7579 /* Write immediate bits [7:0] to the following locations:
7581 |28/24|23 19|18 16|15 4|3 0|
7582 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7584 This function is used by VMOV/VMVN/VORR/VBIC. */
7587 neon_write_immbits (unsigned immbits
)
7589 inst
.instruction
|= immbits
& 0xf;
7590 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7591 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7594 /* Invert low-order SIZE bits of XHI:XLO. */
7597 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7599 unsigned immlo
= xlo
? *xlo
: 0;
7600 unsigned immhi
= xhi
? *xhi
: 0;
7605 immlo
= (~immlo
) & 0xff;
7609 immlo
= (~immlo
) & 0xffff;
7613 immhi
= (~immhi
) & 0xffffffff;
7617 immlo
= (~immlo
) & 0xffffffff;
7631 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7635 neon_bits_same_in_bytes (unsigned imm
)
7637 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7638 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7639 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7640 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7643 /* For immediate of above form, return 0bABCD. */
7646 neon_squash_bits (unsigned imm
)
7648 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7649 | ((imm
& 0x01000000) >> 21);
7652 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7655 neon_qfloat_bits (unsigned imm
)
7657 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7660 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7661 the instruction. *OP is passed as the initial value of the op field, and
7662 may be set to a different value depending on the constant (i.e.
7663 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7664 MVN). If the immediate looks like a repeated pattern then also
7665 try smaller element sizes. */
7668 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7669 unsigned *immbits
, int *op
, int size
,
7670 enum neon_el_type type
)
7672 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7674 if (type
== NT_float
&& !float_p
)
7677 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7679 if (size
!= 32 || *op
== 1)
7681 *immbits
= neon_qfloat_bits (immlo
);
7687 if (neon_bits_same_in_bytes (immhi
)
7688 && neon_bits_same_in_bytes (immlo
))
7692 *immbits
= (neon_squash_bits (immhi
) << 4)
7693 | neon_squash_bits (immlo
);
7704 if (immlo
== (immlo
& 0x000000ff))
7709 else if (immlo
== (immlo
& 0x0000ff00))
7711 *immbits
= immlo
>> 8;
7714 else if (immlo
== (immlo
& 0x00ff0000))
7716 *immbits
= immlo
>> 16;
7719 else if (immlo
== (immlo
& 0xff000000))
7721 *immbits
= immlo
>> 24;
7724 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7726 *immbits
= (immlo
>> 8) & 0xff;
7729 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7731 *immbits
= (immlo
>> 16) & 0xff;
7735 if ((immlo
& 0xffff) != (immlo
>> 16))
7742 if (immlo
== (immlo
& 0x000000ff))
7747 else if (immlo
== (immlo
& 0x0000ff00))
7749 *immbits
= immlo
>> 8;
7753 if ((immlo
& 0xff) != (immlo
>> 8))
7758 if (immlo
== (immlo
& 0x000000ff))
7760 /* Don't allow MVN with 8-bit immediate. */
7770 #if defined BFD_HOST_64_BIT
7771 /* Returns TRUE if double precision value V may be cast
7772 to single precision without loss of accuracy. */
7775 is_double_a_single (bfd_int64_t v
)
7777 int exp
= (int)((v
>> 52) & 0x7FF);
7778 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7780 return (exp
== 0 || exp
== 0x7FF
7781 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7782 && (mantissa
& 0x1FFFFFFFl
) == 0;
7785 /* Returns a double precision value casted to single precision
7786 (ignoring the least significant bits in exponent and mantissa). */
7789 double_to_single (bfd_int64_t v
)
7791 int sign
= (int) ((v
>> 63) & 1l);
7792 int exp
= (int) ((v
>> 52) & 0x7FF);
7793 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7799 exp
= exp
- 1023 + 127;
7808 /* No denormalized numbers. */
7814 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7816 #endif /* BFD_HOST_64_BIT */
7825 static void do_vfp_nsyn_opcode (const char *);
7827 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7828 Determine whether it can be performed with a move instruction; if
7829 it can, convert inst.instruction to that move instruction and
7830 return TRUE; if it can't, convert inst.instruction to a literal-pool
7831 load and return FALSE. If this is not a valid thing to do in the
7832 current context, set inst.error and return TRUE.
7834 inst.operands[i] describes the destination register. */
7837 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7840 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7841 bfd_boolean arm_p
= (t
== CONST_ARM
);
7844 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7848 if ((inst
.instruction
& tbit
) == 0)
7850 inst
.error
= _("invalid pseudo operation");
7854 if (inst
.reloc
.exp
.X_op
!= O_constant
7855 && inst
.reloc
.exp
.X_op
!= O_symbol
7856 && inst
.reloc
.exp
.X_op
!= O_big
)
7858 inst
.error
= _("constant expression expected");
7862 if (inst
.reloc
.exp
.X_op
== O_constant
7863 || inst
.reloc
.exp
.X_op
== O_big
)
7865 #if defined BFD_HOST_64_BIT
7870 if (inst
.reloc
.exp
.X_op
== O_big
)
7872 LITTLENUM_TYPE w
[X_PRECISION
];
7875 if (inst
.reloc
.exp
.X_add_number
== -1)
7877 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7879 /* FIXME: Should we check words w[2..5] ? */
7884 #if defined BFD_HOST_64_BIT
7886 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7887 << LITTLENUM_NUMBER_OF_BITS
)
7888 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7889 << LITTLENUM_NUMBER_OF_BITS
)
7890 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7891 << LITTLENUM_NUMBER_OF_BITS
)
7892 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7894 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7895 | (l
[0] & LITTLENUM_MASK
);
7899 v
= inst
.reloc
.exp
.X_add_number
;
7901 if (!inst
.operands
[i
].issingle
)
7905 /* This can be encoded only for a low register. */
7906 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7908 /* This can be done with a mov(1) instruction. */
7909 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7910 inst
.instruction
|= v
;
7914 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7915 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7917 /* Check if on thumb2 it can be done with a mov.w, mvn or
7918 movw instruction. */
7919 unsigned int newimm
;
7920 bfd_boolean isNegated
;
7922 newimm
= encode_thumb32_immediate (v
);
7923 if (newimm
!= (unsigned int) FAIL
)
7927 newimm
= encode_thumb32_immediate (~v
);
7928 if (newimm
!= (unsigned int) FAIL
)
7932 /* The number can be loaded with a mov.w or mvn
7934 if (newimm
!= (unsigned int) FAIL
7935 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7937 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7938 | (inst
.operands
[i
].reg
<< 8));
7939 /* Change to MOVN. */
7940 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7941 inst
.instruction
|= (newimm
& 0x800) << 15;
7942 inst
.instruction
|= (newimm
& 0x700) << 4;
7943 inst
.instruction
|= (newimm
& 0x0ff);
7946 /* The number can be loaded with a movw instruction. */
7947 else if ((v
& ~0xFFFF) == 0
7948 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7950 int imm
= v
& 0xFFFF;
7952 inst
.instruction
= 0xf2400000; /* MOVW. */
7953 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7954 inst
.instruction
|= (imm
& 0xf000) << 4;
7955 inst
.instruction
|= (imm
& 0x0800) << 15;
7956 inst
.instruction
|= (imm
& 0x0700) << 4;
7957 inst
.instruction
|= (imm
& 0x00ff);
7964 int value
= encode_arm_immediate (v
);
7968 /* This can be done with a mov instruction. */
7969 inst
.instruction
&= LITERAL_MASK
;
7970 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7971 inst
.instruction
|= value
& 0xfff;
7975 value
= encode_arm_immediate (~ v
);
7978 /* This can be done with a mvn instruction. */
7979 inst
.instruction
&= LITERAL_MASK
;
7980 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7981 inst
.instruction
|= value
& 0xfff;
7985 else if (t
== CONST_VEC
)
7988 unsigned immbits
= 0;
7989 unsigned immlo
= inst
.operands
[1].imm
;
7990 unsigned immhi
= inst
.operands
[1].regisimm
7991 ? inst
.operands
[1].reg
7992 : inst
.reloc
.exp
.X_unsigned
7994 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7995 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7996 &op
, 64, NT_invtype
);
8000 neon_invert_size (&immlo
, &immhi
, 64);
8002 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8003 &op
, 64, NT_invtype
);
8008 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8014 /* Fill other bits in vmov encoding for both thumb and arm. */
8016 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8018 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8019 neon_write_immbits (immbits
);
8027 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8028 if (inst
.operands
[i
].issingle
8029 && is_quarter_float (inst
.operands
[1].imm
)
8030 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8032 inst
.operands
[1].imm
=
8033 neon_qfloat_bits (v
);
8034 do_vfp_nsyn_opcode ("fconsts");
8038 /* If our host does not support a 64-bit type then we cannot perform
8039 the following optimization. This mean that there will be a
8040 discrepancy between the output produced by an assembler built for
8041 a 32-bit-only host and the output produced from a 64-bit host, but
8042 this cannot be helped. */
8043 #if defined BFD_HOST_64_BIT
8044 else if (!inst
.operands
[1].issingle
8045 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8047 if (is_double_a_single (v
)
8048 && is_quarter_float (double_to_single (v
)))
8050 inst
.operands
[1].imm
=
8051 neon_qfloat_bits (double_to_single (v
));
8052 do_vfp_nsyn_opcode ("fconstd");
8060 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8061 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8064 inst
.operands
[1].reg
= REG_PC
;
8065 inst
.operands
[1].isreg
= 1;
8066 inst
.operands
[1].preind
= 1;
8067 inst
.reloc
.pc_rel
= 1;
8068 inst
.reloc
.type
= (thumb_p
8069 ? BFD_RELOC_ARM_THUMB_OFFSET
8071 ? BFD_RELOC_ARM_HWLITERAL
8072 : BFD_RELOC_ARM_LITERAL
));
8076 /* inst.operands[i] was set up by parse_address. Encode it into an
8077 ARM-format instruction. Reject all forms which cannot be encoded
8078 into a coprocessor load/store instruction. If wb_ok is false,
8079 reject use of writeback; if unind_ok is false, reject use of
8080 unindexed addressing. If reloc_override is not 0, use it instead
8081 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8082 (in which case it is preserved). */
8085 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8087 if (!inst
.operands
[i
].isreg
)
8090 if (! inst
.operands
[0].isvec
)
8092 inst
.error
= _("invalid co-processor operand");
8095 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8099 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8101 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8103 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8105 gas_assert (!inst
.operands
[i
].writeback
);
8108 inst
.error
= _("instruction does not support unindexed addressing");
8111 inst
.instruction
|= inst
.operands
[i
].imm
;
8112 inst
.instruction
|= INDEX_UP
;
8116 if (inst
.operands
[i
].preind
)
8117 inst
.instruction
|= PRE_INDEX
;
8119 if (inst
.operands
[i
].writeback
)
8121 if (inst
.operands
[i
].reg
== REG_PC
)
8123 inst
.error
= _("pc may not be used with write-back");
8128 inst
.error
= _("instruction does not support writeback");
8131 inst
.instruction
|= WRITE_BACK
;
8135 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8136 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8137 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8138 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8141 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8143 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8146 /* Prefer + for zero encoded value. */
8147 if (!inst
.operands
[i
].negative
)
8148 inst
.instruction
|= INDEX_UP
;
8153 /* Functions for instruction encoding, sorted by sub-architecture.
8154 First some generics; their names are taken from the conventional
8155 bit positions for register arguments in ARM format instructions. */
8165 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8171 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8172 inst
.instruction
|= inst
.operands
[1].reg
;
8178 inst
.instruction
|= inst
.operands
[0].reg
;
8179 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8185 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8186 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8192 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8193 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8199 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8200 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8204 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8206 if (ARM_CPU_IS_ANY (cpu_variant
))
8208 as_tsktsk ("%s", msg
);
8211 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8223 unsigned Rn
= inst
.operands
[2].reg
;
8224 /* Enforce restrictions on SWP instruction. */
8225 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8227 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8228 _("Rn must not overlap other operands"));
8230 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8232 if (!check_obsolete (&arm_ext_v8
,
8233 _("swp{b} use is obsoleted for ARMv8 and later"))
8234 && warn_on_deprecated
8235 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8236 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8239 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8240 inst
.instruction
|= inst
.operands
[1].reg
;
8241 inst
.instruction
|= Rn
<< 16;
8247 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8248 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8249 inst
.instruction
|= inst
.operands
[2].reg
;
8255 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8256 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8257 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8258 || inst
.reloc
.exp
.X_add_number
!= 0),
8260 inst
.instruction
|= inst
.operands
[0].reg
;
8261 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8262 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8268 inst
.instruction
|= inst
.operands
[0].imm
;
8274 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8275 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8278 /* ARM instructions, in alphabetical order by function name (except
8279 that wrapper functions appear immediately after the function they
8282 /* This is a pseudo-op of the form "adr rd, label" to be converted
8283 into a relative address of the form "add rd, pc, #label-.-8". */
8288 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8290 /* Frag hacking will turn this into a sub instruction if the offset turns
8291 out to be negative. */
8292 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8293 inst
.reloc
.pc_rel
= 1;
8294 inst
.reloc
.exp
.X_add_number
-= 8;
8297 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8298 into a relative address of the form:
8299 add rd, pc, #low(label-.-8)"
8300 add rd, rd, #high(label-.-8)" */
8305 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8307 /* Frag hacking will turn this into a sub instruction if the offset turns
8308 out to be negative. */
8309 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8310 inst
.reloc
.pc_rel
= 1;
8311 inst
.size
= INSN_SIZE
* 2;
8312 inst
.reloc
.exp
.X_add_number
-= 8;
8318 if (!inst
.operands
[1].present
)
8319 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8320 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8321 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8322 encode_arm_shifter_operand (2);
8328 if (inst
.operands
[0].present
)
8329 inst
.instruction
|= inst
.operands
[0].imm
;
8331 inst
.instruction
|= 0xf;
8337 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8338 constraint (msb
> 32, _("bit-field extends past end of register"));
8339 /* The instruction encoding stores the LSB and MSB,
8340 not the LSB and width. */
8341 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8342 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8343 inst
.instruction
|= (msb
- 1) << 16;
8351 /* #0 in second position is alternative syntax for bfc, which is
8352 the same instruction but with REG_PC in the Rm field. */
8353 if (!inst
.operands
[1].isreg
)
8354 inst
.operands
[1].reg
= REG_PC
;
8356 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8357 constraint (msb
> 32, _("bit-field extends past end of register"));
8358 /* The instruction encoding stores the LSB and MSB,
8359 not the LSB and width. */
8360 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8361 inst
.instruction
|= inst
.operands
[1].reg
;
8362 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8363 inst
.instruction
|= (msb
- 1) << 16;
8369 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8370 _("bit-field extends past end of register"));
8371 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8372 inst
.instruction
|= inst
.operands
[1].reg
;
8373 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8374 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8377 /* ARM V5 breakpoint instruction (argument parse)
8378 BKPT <16 bit unsigned immediate>
8379 Instruction is not conditional.
8380 The bit pattern given in insns[] has the COND_ALWAYS condition,
8381 and it is an error if the caller tried to override that. */
8386 /* Top 12 of 16 bits to bits 19:8. */
8387 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8389 /* Bottom 4 of 16 bits to bits 3:0. */
8390 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8394 encode_branch (int default_reloc
)
8396 if (inst
.operands
[0].hasreloc
)
8398 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8399 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8400 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8401 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8402 ? BFD_RELOC_ARM_PLT32
8403 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8406 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8407 inst
.reloc
.pc_rel
= 1;
8414 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8415 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8418 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8425 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8427 if (inst
.cond
== COND_ALWAYS
)
8428 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8430 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8434 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8437 /* ARM V5 branch-link-exchange instruction (argument parse)
8438 BLX <target_addr> ie BLX(1)
8439 BLX{<condition>} <Rm> ie BLX(2)
8440 Unfortunately, there are two different opcodes for this mnemonic.
8441 So, the insns[].value is not used, and the code here zaps values
8442 into inst.instruction.
8443 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8448 if (inst
.operands
[0].isreg
)
8450 /* Arg is a register; the opcode provided by insns[] is correct.
8451 It is not illegal to do "blx pc", just useless. */
8452 if (inst
.operands
[0].reg
== REG_PC
)
8453 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8455 inst
.instruction
|= inst
.operands
[0].reg
;
8459 /* Arg is an address; this instruction cannot be executed
8460 conditionally, and the opcode must be adjusted.
8461 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8462 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8463 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8464 inst
.instruction
= 0xfa000000;
8465 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8472 bfd_boolean want_reloc
;
8474 if (inst
.operands
[0].reg
== REG_PC
)
8475 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8477 inst
.instruction
|= inst
.operands
[0].reg
;
8478 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8479 it is for ARMv4t or earlier. */
8480 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8481 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8485 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8490 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8494 /* ARM v5TEJ. Jump to Jazelle code. */
8499 if (inst
.operands
[0].reg
== REG_PC
)
8500 as_tsktsk (_("use of r15 in bxj is not really useful"));
8502 inst
.instruction
|= inst
.operands
[0].reg
;
8505 /* Co-processor data operation:
8506 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8507 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8511 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8512 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8513 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8514 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8515 inst
.instruction
|= inst
.operands
[4].reg
;
8516 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8522 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8523 encode_arm_shifter_operand (1);
8526 /* Transfer between coprocessor and ARM registers.
8527 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8532 No special properties. */
8534 struct deprecated_coproc_regs_s
8541 arm_feature_set deprecated
;
8542 arm_feature_set obsoleted
;
8543 const char *dep_msg
;
8544 const char *obs_msg
;
8547 #define DEPR_ACCESS_V8 \
8548 N_("This coprocessor register access is deprecated in ARMv8")
8550 /* Table of all deprecated coprocessor registers. */
8551 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8553 {15, 0, 7, 10, 5, /* CP15DMB. */
8554 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8555 DEPR_ACCESS_V8
, NULL
},
8556 {15, 0, 7, 10, 4, /* CP15DSB. */
8557 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8558 DEPR_ACCESS_V8
, NULL
},
8559 {15, 0, 7, 5, 4, /* CP15ISB. */
8560 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8561 DEPR_ACCESS_V8
, NULL
},
8562 {14, 6, 1, 0, 0, /* TEEHBR. */
8563 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8564 DEPR_ACCESS_V8
, NULL
},
8565 {14, 6, 0, 0, 0, /* TEECR. */
8566 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8567 DEPR_ACCESS_V8
, NULL
},
8570 #undef DEPR_ACCESS_V8
8572 static const size_t deprecated_coproc_reg_count
=
8573 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8581 Rd
= inst
.operands
[2].reg
;
8584 if (inst
.instruction
== 0xee000010
8585 || inst
.instruction
== 0xfe000010)
8587 reject_bad_reg (Rd
);
8590 constraint (Rd
== REG_SP
, BAD_SP
);
8595 if (inst
.instruction
== 0xe000010)
8596 constraint (Rd
== REG_PC
, BAD_PC
);
8599 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8601 const struct deprecated_coproc_regs_s
*r
=
8602 deprecated_coproc_regs
+ i
;
8604 if (inst
.operands
[0].reg
== r
->cp
8605 && inst
.operands
[1].imm
== r
->opc1
8606 && inst
.operands
[3].reg
== r
->crn
8607 && inst
.operands
[4].reg
== r
->crm
8608 && inst
.operands
[5].imm
== r
->opc2
)
8610 if (! ARM_CPU_IS_ANY (cpu_variant
)
8611 && warn_on_deprecated
8612 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8613 as_tsktsk ("%s", r
->dep_msg
);
8617 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8618 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8619 inst
.instruction
|= Rd
<< 12;
8620 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8621 inst
.instruction
|= inst
.operands
[4].reg
;
8622 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8625 /* Transfer between coprocessor register and pair of ARM registers.
8626 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8631 Two XScale instructions are special cases of these:
8633 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8634 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8636 Result unpredictable if Rd or Rn is R15. */
8643 Rd
= inst
.operands
[2].reg
;
8644 Rn
= inst
.operands
[3].reg
;
8648 reject_bad_reg (Rd
);
8649 reject_bad_reg (Rn
);
8653 constraint (Rd
== REG_PC
, BAD_PC
);
8654 constraint (Rn
== REG_PC
, BAD_PC
);
8657 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8658 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8659 inst
.instruction
|= Rd
<< 12;
8660 inst
.instruction
|= Rn
<< 16;
8661 inst
.instruction
|= inst
.operands
[4].reg
;
8667 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8668 if (inst
.operands
[1].present
)
8670 inst
.instruction
|= CPSI_MMOD
;
8671 inst
.instruction
|= inst
.operands
[1].imm
;
8678 inst
.instruction
|= inst
.operands
[0].imm
;
8684 unsigned Rd
, Rn
, Rm
;
8686 Rd
= inst
.operands
[0].reg
;
8687 Rn
= (inst
.operands
[1].present
8688 ? inst
.operands
[1].reg
: Rd
);
8689 Rm
= inst
.operands
[2].reg
;
8691 constraint ((Rd
== REG_PC
), BAD_PC
);
8692 constraint ((Rn
== REG_PC
), BAD_PC
);
8693 constraint ((Rm
== REG_PC
), BAD_PC
);
8695 inst
.instruction
|= Rd
<< 16;
8696 inst
.instruction
|= Rn
<< 0;
8697 inst
.instruction
|= Rm
<< 8;
8703 /* There is no IT instruction in ARM mode. We
8704 process it to do the validation as if in
8705 thumb mode, just in case the code gets
8706 assembled for thumb using the unified syntax. */
8711 set_it_insn_type (IT_INSN
);
8712 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8713 now_it
.cc
= inst
.operands
[0].imm
;
8717 /* If there is only one register in the register list,
8718 then return its register number. Otherwise return -1. */
8720 only_one_reg_in_list (int range
)
8722 int i
= ffs (range
) - 1;
8723 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8727 encode_ldmstm(int from_push_pop_mnem
)
8729 int base_reg
= inst
.operands
[0].reg
;
8730 int range
= inst
.operands
[1].imm
;
8733 inst
.instruction
|= base_reg
<< 16;
8734 inst
.instruction
|= range
;
8736 if (inst
.operands
[1].writeback
)
8737 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8739 if (inst
.operands
[0].writeback
)
8741 inst
.instruction
|= WRITE_BACK
;
8742 /* Check for unpredictable uses of writeback. */
8743 if (inst
.instruction
& LOAD_BIT
)
8745 /* Not allowed in LDM type 2. */
8746 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8747 && ((range
& (1 << REG_PC
)) == 0))
8748 as_warn (_("writeback of base register is UNPREDICTABLE"));
8749 /* Only allowed if base reg not in list for other types. */
8750 else if (range
& (1 << base_reg
))
8751 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8755 /* Not allowed for type 2. */
8756 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8757 as_warn (_("writeback of base register is UNPREDICTABLE"));
8758 /* Only allowed if base reg not in list, or first in list. */
8759 else if ((range
& (1 << base_reg
))
8760 && (range
& ((1 << base_reg
) - 1)))
8761 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8765 /* If PUSH/POP has only one register, then use the A2 encoding. */
8766 one_reg
= only_one_reg_in_list (range
);
8767 if (from_push_pop_mnem
&& one_reg
>= 0)
8769 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8771 inst
.instruction
&= A_COND_MASK
;
8772 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8773 inst
.instruction
|= one_reg
<< 12;
8780 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8783 /* ARMv5TE load-consecutive (argument parse)
8792 constraint (inst
.operands
[0].reg
% 2 != 0,
8793 _("first transfer register must be even"));
8794 constraint (inst
.operands
[1].present
8795 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8796 _("can only transfer two consecutive registers"));
8797 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8798 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8800 if (!inst
.operands
[1].present
)
8801 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8803 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8804 register and the first register written; we have to diagnose
8805 overlap between the base and the second register written here. */
8807 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8808 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8809 as_warn (_("base register written back, and overlaps "
8810 "second transfer register"));
8812 if (!(inst
.instruction
& V4_STR_BIT
))
8814 /* For an index-register load, the index register must not overlap the
8815 destination (even if not write-back). */
8816 if (inst
.operands
[2].immisreg
8817 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8818 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8819 as_warn (_("index register overlaps transfer register"));
8821 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8822 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8828 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8829 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8830 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8831 || inst
.operands
[1].negative
8832 /* This can arise if the programmer has written
8834 or if they have mistakenly used a register name as the last
8837 It is very difficult to distinguish between these two cases
8838 because "rX" might actually be a label. ie the register
8839 name has been occluded by a symbol of the same name. So we
8840 just generate a general 'bad addressing mode' type error
8841 message and leave it up to the programmer to discover the
8842 true cause and fix their mistake. */
8843 || (inst
.operands
[1].reg
== REG_PC
),
8846 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8847 || inst
.reloc
.exp
.X_add_number
!= 0,
8848 _("offset must be zero in ARM encoding"));
8850 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8852 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8853 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8854 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8860 constraint (inst
.operands
[0].reg
% 2 != 0,
8861 _("even register required"));
8862 constraint (inst
.operands
[1].present
8863 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8864 _("can only load two consecutive registers"));
8865 /* If op 1 were present and equal to PC, this function wouldn't
8866 have been called in the first place. */
8867 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8869 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8870 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8873 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8874 which is not a multiple of four is UNPREDICTABLE. */
8876 check_ldr_r15_aligned (void)
8878 constraint (!(inst
.operands
[1].immisreg
)
8879 && (inst
.operands
[0].reg
== REG_PC
8880 && inst
.operands
[1].reg
== REG_PC
8881 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8882 _("ldr to register 15 must be 4-byte alligned"));
8888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8889 if (!inst
.operands
[1].isreg
)
8890 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8892 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8893 check_ldr_r15_aligned ();
8899 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8901 if (inst
.operands
[1].preind
)
8903 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8904 || inst
.reloc
.exp
.X_add_number
!= 0,
8905 _("this instruction requires a post-indexed address"));
8907 inst
.operands
[1].preind
= 0;
8908 inst
.operands
[1].postind
= 1;
8909 inst
.operands
[1].writeback
= 1;
8911 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8912 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8915 /* Halfword and signed-byte load/store operations. */
8920 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8921 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8922 if (!inst
.operands
[1].isreg
)
8923 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8925 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8931 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8933 if (inst
.operands
[1].preind
)
8935 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8936 || inst
.reloc
.exp
.X_add_number
!= 0,
8937 _("this instruction requires a post-indexed address"));
8939 inst
.operands
[1].preind
= 0;
8940 inst
.operands
[1].postind
= 1;
8941 inst
.operands
[1].writeback
= 1;
8943 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8944 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8947 /* Co-processor register load/store.
8948 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8952 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8953 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8954 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8960 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8961 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8962 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8963 && !(inst
.instruction
& 0x00400000))
8964 as_tsktsk (_("Rd and Rm should be different in mla"));
8966 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8967 inst
.instruction
|= inst
.operands
[1].reg
;
8968 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8969 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8975 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8976 encode_arm_shifter_operand (1);
8979 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8986 top
= (inst
.instruction
& 0x00400000) != 0;
8987 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8988 _(":lower16: not allowed this instruction"));
8989 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8990 _(":upper16: not allowed instruction"));
8991 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8992 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8994 imm
= inst
.reloc
.exp
.X_add_number
;
8995 /* The value is in two pieces: 0:11, 16:19. */
8996 inst
.instruction
|= (imm
& 0x00000fff);
8997 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9002 do_vfp_nsyn_mrs (void)
9004 if (inst
.operands
[0].isvec
)
9006 if (inst
.operands
[1].reg
!= 1)
9007 first_error (_("operand 1 must be FPSCR"));
9008 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9009 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9010 do_vfp_nsyn_opcode ("fmstat");
9012 else if (inst
.operands
[1].isvec
)
9013 do_vfp_nsyn_opcode ("fmrx");
9021 do_vfp_nsyn_msr (void)
9023 if (inst
.operands
[0].isvec
)
9024 do_vfp_nsyn_opcode ("fmxr");
9034 unsigned Rt
= inst
.operands
[0].reg
;
9036 if (thumb_mode
&& Rt
== REG_SP
)
9038 inst
.error
= BAD_SP
;
9042 /* APSR_ sets isvec. All other refs to PC are illegal. */
9043 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9045 inst
.error
= BAD_PC
;
9049 /* If we get through parsing the register name, we just insert the number
9050 generated into the instruction without further validation. */
9051 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9052 inst
.instruction
|= (Rt
<< 12);
9058 unsigned Rt
= inst
.operands
[1].reg
;
9061 reject_bad_reg (Rt
);
9062 else if (Rt
== REG_PC
)
9064 inst
.error
= BAD_PC
;
9068 /* If we get through parsing the register name, we just insert the number
9069 generated into the instruction without further validation. */
9070 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9071 inst
.instruction
|= (Rt
<< 12);
9079 if (do_vfp_nsyn_mrs () == SUCCESS
)
9082 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9083 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9085 if (inst
.operands
[1].isreg
)
9087 br
= inst
.operands
[1].reg
;
9088 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9089 as_bad (_("bad register for mrs"));
9093 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9094 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9096 _("'APSR', 'CPSR' or 'SPSR' expected"));
9097 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9100 inst
.instruction
|= br
;
9103 /* Two possible forms:
9104 "{C|S}PSR_<field>, Rm",
9105 "{C|S}PSR_f, #expression". */
9110 if (do_vfp_nsyn_msr () == SUCCESS
)
9113 inst
.instruction
|= inst
.operands
[0].imm
;
9114 if (inst
.operands
[1].isreg
)
9115 inst
.instruction
|= inst
.operands
[1].reg
;
9118 inst
.instruction
|= INST_IMMEDIATE
;
9119 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9120 inst
.reloc
.pc_rel
= 0;
9127 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9129 if (!inst
.operands
[2].present
)
9130 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9131 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9132 inst
.instruction
|= inst
.operands
[1].reg
;
9133 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9135 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9136 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9137 as_tsktsk (_("Rd and Rm should be different in mul"));
9140 /* Long Multiply Parser
9141 UMULL RdLo, RdHi, Rm, Rs
9142 SMULL RdLo, RdHi, Rm, Rs
9143 UMLAL RdLo, RdHi, Rm, Rs
9144 SMLAL RdLo, RdHi, Rm, Rs. */
9149 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9150 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9151 inst
.instruction
|= inst
.operands
[2].reg
;
9152 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9154 /* rdhi and rdlo must be different. */
9155 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9156 as_tsktsk (_("rdhi and rdlo must be different"));
9158 /* rdhi, rdlo and rm must all be different before armv6. */
9159 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9160 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9161 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9162 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9168 if (inst
.operands
[0].present
9169 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9171 /* Architectural NOP hints are CPSR sets with no bits selected. */
9172 inst
.instruction
&= 0xf0000000;
9173 inst
.instruction
|= 0x0320f000;
9174 if (inst
.operands
[0].present
)
9175 inst
.instruction
|= inst
.operands
[0].imm
;
9179 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9180 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9181 Condition defaults to COND_ALWAYS.
9182 Error if Rd, Rn or Rm are R15. */
9187 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9188 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9189 inst
.instruction
|= inst
.operands
[2].reg
;
9190 if (inst
.operands
[3].present
)
9191 encode_arm_shift (3);
9194 /* ARM V6 PKHTB (Argument Parse). */
9199 if (!inst
.operands
[3].present
)
9201 /* If the shift specifier is omitted, turn the instruction
9202 into pkhbt rd, rm, rn. */
9203 inst
.instruction
&= 0xfff00010;
9204 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9205 inst
.instruction
|= inst
.operands
[1].reg
;
9206 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9210 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9211 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9212 inst
.instruction
|= inst
.operands
[2].reg
;
9213 encode_arm_shift (3);
9217 /* ARMv5TE: Preload-Cache
9218 MP Extensions: Preload for write
9222 Syntactically, like LDR with B=1, W=0, L=1. */
9227 constraint (!inst
.operands
[0].isreg
,
9228 _("'[' expected after PLD mnemonic"));
9229 constraint (inst
.operands
[0].postind
,
9230 _("post-indexed expression used in preload instruction"));
9231 constraint (inst
.operands
[0].writeback
,
9232 _("writeback used in preload instruction"));
9233 constraint (!inst
.operands
[0].preind
,
9234 _("unindexed addressing used in preload instruction"));
9235 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9238 /* ARMv7: PLI <addr_mode> */
9242 constraint (!inst
.operands
[0].isreg
,
9243 _("'[' expected after PLI mnemonic"));
9244 constraint (inst
.operands
[0].postind
,
9245 _("post-indexed expression used in preload instruction"));
9246 constraint (inst
.operands
[0].writeback
,
9247 _("writeback used in preload instruction"));
9248 constraint (!inst
.operands
[0].preind
,
9249 _("unindexed addressing used in preload instruction"));
9250 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9251 inst
.instruction
&= ~PRE_INDEX
;
9257 constraint (inst
.operands
[0].writeback
,
9258 _("push/pop do not support {reglist}^"));
9259 inst
.operands
[1] = inst
.operands
[0];
9260 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9261 inst
.operands
[0].isreg
= 1;
9262 inst
.operands
[0].writeback
= 1;
9263 inst
.operands
[0].reg
= REG_SP
;
9264 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9267 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9268 word at the specified address and the following word
9270 Unconditionally executed.
9271 Error if Rn is R15. */
9276 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9277 if (inst
.operands
[0].writeback
)
9278 inst
.instruction
|= WRITE_BACK
;
9281 /* ARM V6 ssat (argument parse). */
9286 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9287 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9288 inst
.instruction
|= inst
.operands
[2].reg
;
9290 if (inst
.operands
[3].present
)
9291 encode_arm_shift (3);
9294 /* ARM V6 usat (argument parse). */
9299 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9300 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9301 inst
.instruction
|= inst
.operands
[2].reg
;
9303 if (inst
.operands
[3].present
)
9304 encode_arm_shift (3);
9307 /* ARM V6 ssat16 (argument parse). */
9312 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9313 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9314 inst
.instruction
|= inst
.operands
[2].reg
;
9320 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9321 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9322 inst
.instruction
|= inst
.operands
[2].reg
;
9325 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9326 preserving the other bits.
9328 setend <endian_specifier>, where <endian_specifier> is either
9334 if (warn_on_deprecated
9335 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9336 as_tsktsk (_("setend use is deprecated for ARMv8"));
9338 if (inst
.operands
[0].imm
)
9339 inst
.instruction
|= 0x200;
9345 unsigned int Rm
= (inst
.operands
[1].present
9346 ? inst
.operands
[1].reg
9347 : inst
.operands
[0].reg
);
9349 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9350 inst
.instruction
|= Rm
;
9351 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9353 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9354 inst
.instruction
|= SHIFT_BY_REG
;
9355 /* PR 12854: Error on extraneous shifts. */
9356 constraint (inst
.operands
[2].shifted
,
9357 _("extraneous shift as part of operand to shift insn"));
9360 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9366 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9367 inst
.reloc
.pc_rel
= 0;
9373 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9374 inst
.reloc
.pc_rel
= 0;
9380 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9381 inst
.reloc
.pc_rel
= 0;
9387 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9388 _("selected processor does not support SETPAN instruction"));
9390 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9396 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9397 _("selected processor does not support SETPAN instruction"));
9399 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9402 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9403 SMLAxy{cond} Rd,Rm,Rs,Rn
9404 SMLAWy{cond} Rd,Rm,Rs,Rn
9405 Error if any register is R15. */
9410 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9411 inst
.instruction
|= inst
.operands
[1].reg
;
9412 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9413 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9416 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9417 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9418 Error if any register is R15.
9419 Warning if Rdlo == Rdhi. */
9424 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9425 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9426 inst
.instruction
|= inst
.operands
[2].reg
;
9427 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9429 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9430 as_tsktsk (_("rdhi and rdlo must be different"));
9433 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9434 SMULxy{cond} Rd,Rm,Rs
9435 Error if any register is R15. */
9440 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9441 inst
.instruction
|= inst
.operands
[1].reg
;
9442 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9445 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9446 the same for both ARM and Thumb-2. */
9453 if (inst
.operands
[0].present
)
9455 reg
= inst
.operands
[0].reg
;
9456 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9461 inst
.instruction
|= reg
<< 16;
9462 inst
.instruction
|= inst
.operands
[1].imm
;
9463 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9464 inst
.instruction
|= WRITE_BACK
;
9467 /* ARM V6 strex (argument parse). */
9472 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9473 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9474 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9475 || inst
.operands
[2].negative
9476 /* See comment in do_ldrex(). */
9477 || (inst
.operands
[2].reg
== REG_PC
),
9480 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9481 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9483 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9484 || inst
.reloc
.exp
.X_add_number
!= 0,
9485 _("offset must be zero in ARM encoding"));
9487 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9488 inst
.instruction
|= inst
.operands
[1].reg
;
9489 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9490 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9496 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9497 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9498 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9499 || inst
.operands
[2].negative
,
9502 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9503 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9511 constraint (inst
.operands
[1].reg
% 2 != 0,
9512 _("even register required"));
9513 constraint (inst
.operands
[2].present
9514 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9515 _("can only store two consecutive registers"));
9516 /* If op 2 were present and equal to PC, this function wouldn't
9517 have been called in the first place. */
9518 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9520 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9521 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9522 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9525 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9526 inst
.instruction
|= inst
.operands
[1].reg
;
9527 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9534 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9535 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9543 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9544 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9549 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9550 extends it to 32-bits, and adds the result to a value in another
9551 register. You can specify a rotation by 0, 8, 16, or 24 bits
9552 before extracting the 16-bit value.
9553 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9554 Condition defaults to COND_ALWAYS.
9555 Error if any register uses R15. */
9560 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9561 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9562 inst
.instruction
|= inst
.operands
[2].reg
;
9563 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9568 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9569 Condition defaults to COND_ALWAYS.
9570 Error if any register uses R15. */
9575 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9576 inst
.instruction
|= inst
.operands
[1].reg
;
9577 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9580 /* VFP instructions. In a logical order: SP variant first, monad
9581 before dyad, arithmetic then move then load/store. */
9584 do_vfp_sp_monadic (void)
9586 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9587 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9591 do_vfp_sp_dyadic (void)
9593 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9594 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9595 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9599 do_vfp_sp_compare_z (void)
9601 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9605 do_vfp_dp_sp_cvt (void)
9607 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9608 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9612 do_vfp_sp_dp_cvt (void)
9614 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9615 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9619 do_vfp_reg_from_sp (void)
9621 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9622 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9626 do_vfp_reg2_from_sp2 (void)
9628 constraint (inst
.operands
[2].imm
!= 2,
9629 _("only two consecutive VFP SP registers allowed here"));
9630 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9631 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9632 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9636 do_vfp_sp_from_reg (void)
9638 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9639 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9643 do_vfp_sp2_from_reg2 (void)
9645 constraint (inst
.operands
[0].imm
!= 2,
9646 _("only two consecutive VFP SP registers allowed here"));
9647 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9648 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9649 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9653 do_vfp_sp_ldst (void)
9655 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9656 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9660 do_vfp_dp_ldst (void)
9662 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9663 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9668 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9670 if (inst
.operands
[0].writeback
)
9671 inst
.instruction
|= WRITE_BACK
;
9673 constraint (ldstm_type
!= VFP_LDSTMIA
,
9674 _("this addressing mode requires base-register writeback"));
9675 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9676 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9677 inst
.instruction
|= inst
.operands
[1].imm
;
9681 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9685 if (inst
.operands
[0].writeback
)
9686 inst
.instruction
|= WRITE_BACK
;
9688 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9689 _("this addressing mode requires base-register writeback"));
9691 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9692 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9694 count
= inst
.operands
[1].imm
<< 1;
9695 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9698 inst
.instruction
|= count
;
9702 do_vfp_sp_ldstmia (void)
9704 vfp_sp_ldstm (VFP_LDSTMIA
);
9708 do_vfp_sp_ldstmdb (void)
9710 vfp_sp_ldstm (VFP_LDSTMDB
);
9714 do_vfp_dp_ldstmia (void)
9716 vfp_dp_ldstm (VFP_LDSTMIA
);
9720 do_vfp_dp_ldstmdb (void)
9722 vfp_dp_ldstm (VFP_LDSTMDB
);
9726 do_vfp_xp_ldstmia (void)
9728 vfp_dp_ldstm (VFP_LDSTMIAX
);
9732 do_vfp_xp_ldstmdb (void)
9734 vfp_dp_ldstm (VFP_LDSTMDBX
);
9738 do_vfp_dp_rd_rm (void)
9740 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9741 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9745 do_vfp_dp_rn_rd (void)
9747 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9748 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9752 do_vfp_dp_rd_rn (void)
9754 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9755 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9759 do_vfp_dp_rd_rn_rm (void)
9761 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9762 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9763 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9769 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9773 do_vfp_dp_rm_rd_rn (void)
9775 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9776 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9777 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9780 /* VFPv3 instructions. */
9782 do_vfp_sp_const (void)
9784 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9785 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9786 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9790 do_vfp_dp_const (void)
9792 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9793 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9794 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9798 vfp_conv (int srcsize
)
9800 int immbits
= srcsize
- inst
.operands
[1].imm
;
9802 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9804 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9805 i.e. immbits must be in range 0 - 16. */
9806 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9809 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9811 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9812 i.e. immbits must be in range 0 - 31. */
9813 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9817 inst
.instruction
|= (immbits
& 1) << 5;
9818 inst
.instruction
|= (immbits
>> 1);
9822 do_vfp_sp_conv_16 (void)
9824 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9829 do_vfp_dp_conv_16 (void)
9831 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9836 do_vfp_sp_conv_32 (void)
9838 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9843 do_vfp_dp_conv_32 (void)
9845 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9849 /* FPA instructions. Also in a logical order. */
9854 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9855 inst
.instruction
|= inst
.operands
[1].reg
;
9859 do_fpa_ldmstm (void)
9861 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9862 switch (inst
.operands
[1].imm
)
9864 case 1: inst
.instruction
|= CP_T_X
; break;
9865 case 2: inst
.instruction
|= CP_T_Y
; break;
9866 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9871 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9873 /* The instruction specified "ea" or "fd", so we can only accept
9874 [Rn]{!}. The instruction does not really support stacking or
9875 unstacking, so we have to emulate these by setting appropriate
9876 bits and offsets. */
9877 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9878 || inst
.reloc
.exp
.X_add_number
!= 0,
9879 _("this instruction does not support indexing"));
9881 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9882 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9884 if (!(inst
.instruction
& INDEX_UP
))
9885 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9887 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9889 inst
.operands
[2].preind
= 0;
9890 inst
.operands
[2].postind
= 1;
9894 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9897 /* iWMMXt instructions: strictly in alphabetical order. */
9900 do_iwmmxt_tandorc (void)
9902 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9906 do_iwmmxt_textrc (void)
9908 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9909 inst
.instruction
|= inst
.operands
[1].imm
;
9913 do_iwmmxt_textrm (void)
9915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9916 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9917 inst
.instruction
|= inst
.operands
[2].imm
;
9921 do_iwmmxt_tinsr (void)
9923 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9924 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9925 inst
.instruction
|= inst
.operands
[2].imm
;
9929 do_iwmmxt_tmia (void)
9931 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9932 inst
.instruction
|= inst
.operands
[1].reg
;
9933 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9937 do_iwmmxt_waligni (void)
9939 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9940 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9941 inst
.instruction
|= inst
.operands
[2].reg
;
9942 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9946 do_iwmmxt_wmerge (void)
9948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9949 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9950 inst
.instruction
|= inst
.operands
[2].reg
;
9951 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9955 do_iwmmxt_wmov (void)
9957 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9958 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9959 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9960 inst
.instruction
|= inst
.operands
[1].reg
;
9964 do_iwmmxt_wldstbh (void)
9967 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9969 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9971 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9972 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9976 do_iwmmxt_wldstw (void)
9978 /* RIWR_RIWC clears .isreg for a control register. */
9979 if (!inst
.operands
[0].isreg
)
9981 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9982 inst
.instruction
|= 0xf0000000;
9985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9986 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9990 do_iwmmxt_wldstd (void)
9992 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9993 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9994 && inst
.operands
[1].immisreg
)
9996 inst
.instruction
&= ~0x1a000ff;
9997 inst
.instruction
|= (0xfU
<< 28);
9998 if (inst
.operands
[1].preind
)
9999 inst
.instruction
|= PRE_INDEX
;
10000 if (!inst
.operands
[1].negative
)
10001 inst
.instruction
|= INDEX_UP
;
10002 if (inst
.operands
[1].writeback
)
10003 inst
.instruction
|= WRITE_BACK
;
10004 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10005 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10006 inst
.instruction
|= inst
.operands
[1].imm
;
10009 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10013 do_iwmmxt_wshufh (void)
10015 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10016 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10017 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10018 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10022 do_iwmmxt_wzero (void)
10024 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10025 inst
.instruction
|= inst
.operands
[0].reg
;
10026 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10027 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10031 do_iwmmxt_wrwrwr_or_imm5 (void)
10033 if (inst
.operands
[2].isreg
)
10036 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10037 _("immediate operand requires iWMMXt2"));
10039 if (inst
.operands
[2].imm
== 0)
10041 switch ((inst
.instruction
>> 20) & 0xf)
10047 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10048 inst
.operands
[2].imm
= 16;
10049 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10055 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10056 inst
.operands
[2].imm
= 32;
10057 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10064 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10066 wrn
= (inst
.instruction
>> 16) & 0xf;
10067 inst
.instruction
&= 0xff0fff0f;
10068 inst
.instruction
|= wrn
;
10069 /* Bail out here; the instruction is now assembled. */
10074 /* Map 32 -> 0, etc. */
10075 inst
.operands
[2].imm
&= 0x1f;
10076 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10080 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10081 operations first, then control, shift, and load/store. */
10083 /* Insns like "foo X,Y,Z". */
10086 do_mav_triple (void)
10088 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10089 inst
.instruction
|= inst
.operands
[1].reg
;
10090 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10093 /* Insns like "foo W,X,Y,Z".
10094 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10099 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10100 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10101 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10102 inst
.instruction
|= inst
.operands
[3].reg
;
10105 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10107 do_mav_dspsc (void)
10109 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10112 /* Maverick shift immediate instructions.
10113 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10114 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10117 do_mav_shift (void)
10119 int imm
= inst
.operands
[2].imm
;
10121 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10122 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10124 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10125 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10126 Bit 4 should be 0. */
10127 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10129 inst
.instruction
|= imm
;
10132 /* XScale instructions. Also sorted arithmetic before move. */
10134 /* Xscale multiply-accumulate (argument parse)
10137 MIAxycc acc0,Rm,Rs. */
10142 inst
.instruction
|= inst
.operands
[1].reg
;
10143 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10146 /* Xscale move-accumulator-register (argument parse)
10148 MARcc acc0,RdLo,RdHi. */
10153 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10154 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10157 /* Xscale move-register-accumulator (argument parse)
10159 MRAcc RdLo,RdHi,acc0. */
10164 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10165 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10166 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10169 /* Encoding functions relevant only to Thumb. */
10171 /* inst.operands[i] is a shifted-register operand; encode
10172 it into inst.instruction in the format used by Thumb32. */
10175 encode_thumb32_shifted_operand (int i
)
10177 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10178 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10180 constraint (inst
.operands
[i
].immisreg
,
10181 _("shift by register not allowed in thumb mode"));
10182 inst
.instruction
|= inst
.operands
[i
].reg
;
10183 if (shift
== SHIFT_RRX
)
10184 inst
.instruction
|= SHIFT_ROR
<< 4;
10187 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10188 _("expression too complex"));
10190 constraint (value
> 32
10191 || (value
== 32 && (shift
== SHIFT_LSL
10192 || shift
== SHIFT_ROR
)),
10193 _("shift expression is too large"));
10197 else if (value
== 32)
10200 inst
.instruction
|= shift
<< 4;
10201 inst
.instruction
|= (value
& 0x1c) << 10;
10202 inst
.instruction
|= (value
& 0x03) << 6;
10207 /* inst.operands[i] was set up by parse_address. Encode it into a
10208 Thumb32 format load or store instruction. Reject forms that cannot
10209 be used with such instructions. If is_t is true, reject forms that
10210 cannot be used with a T instruction; if is_d is true, reject forms
10211 that cannot be used with a D instruction. If it is a store insn,
10212 reject PC in Rn. */
10215 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10217 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10219 constraint (!inst
.operands
[i
].isreg
,
10220 _("Instruction does not support =N addresses"));
10222 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10223 if (inst
.operands
[i
].immisreg
)
10225 constraint (is_pc
, BAD_PC_ADDRESSING
);
10226 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10227 constraint (inst
.operands
[i
].negative
,
10228 _("Thumb does not support negative register indexing"));
10229 constraint (inst
.operands
[i
].postind
,
10230 _("Thumb does not support register post-indexing"));
10231 constraint (inst
.operands
[i
].writeback
,
10232 _("Thumb does not support register indexing with writeback"));
10233 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10234 _("Thumb supports only LSL in shifted register indexing"));
10236 inst
.instruction
|= inst
.operands
[i
].imm
;
10237 if (inst
.operands
[i
].shifted
)
10239 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10240 _("expression too complex"));
10241 constraint (inst
.reloc
.exp
.X_add_number
< 0
10242 || inst
.reloc
.exp
.X_add_number
> 3,
10243 _("shift out of range"));
10244 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10246 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10248 else if (inst
.operands
[i
].preind
)
10250 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10251 constraint (is_t
&& inst
.operands
[i
].writeback
,
10252 _("cannot use writeback with this instruction"));
10253 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10254 BAD_PC_ADDRESSING
);
10258 inst
.instruction
|= 0x01000000;
10259 if (inst
.operands
[i
].writeback
)
10260 inst
.instruction
|= 0x00200000;
10264 inst
.instruction
|= 0x00000c00;
10265 if (inst
.operands
[i
].writeback
)
10266 inst
.instruction
|= 0x00000100;
10268 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10270 else if (inst
.operands
[i
].postind
)
10272 gas_assert (inst
.operands
[i
].writeback
);
10273 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10274 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10277 inst
.instruction
|= 0x00200000;
10279 inst
.instruction
|= 0x00000900;
10280 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10282 else /* unindexed - only for coprocessor */
10283 inst
.error
= _("instruction does not accept unindexed addressing");
10286 /* Table of Thumb instructions which exist in both 16- and 32-bit
10287 encodings (the latter only in post-V6T2 cores). The index is the
10288 value used in the insns table below. When there is more than one
10289 possible 16-bit encoding for the instruction, this table always
10291 Also contains several pseudo-instructions used during relaxation. */
10292 #define T16_32_TAB \
10293 X(_adc, 4140, eb400000), \
10294 X(_adcs, 4140, eb500000), \
10295 X(_add, 1c00, eb000000), \
10296 X(_adds, 1c00, eb100000), \
10297 X(_addi, 0000, f1000000), \
10298 X(_addis, 0000, f1100000), \
10299 X(_add_pc,000f, f20f0000), \
10300 X(_add_sp,000d, f10d0000), \
10301 X(_adr, 000f, f20f0000), \
10302 X(_and, 4000, ea000000), \
10303 X(_ands, 4000, ea100000), \
10304 X(_asr, 1000, fa40f000), \
10305 X(_asrs, 1000, fa50f000), \
10306 X(_b, e000, f000b000), \
10307 X(_bcond, d000, f0008000), \
10308 X(_bic, 4380, ea200000), \
10309 X(_bics, 4380, ea300000), \
10310 X(_cmn, 42c0, eb100f00), \
10311 X(_cmp, 2800, ebb00f00), \
10312 X(_cpsie, b660, f3af8400), \
10313 X(_cpsid, b670, f3af8600), \
10314 X(_cpy, 4600, ea4f0000), \
10315 X(_dec_sp,80dd, f1ad0d00), \
10316 X(_eor, 4040, ea800000), \
10317 X(_eors, 4040, ea900000), \
10318 X(_inc_sp,00dd, f10d0d00), \
10319 X(_ldmia, c800, e8900000), \
10320 X(_ldr, 6800, f8500000), \
10321 X(_ldrb, 7800, f8100000), \
10322 X(_ldrh, 8800, f8300000), \
10323 X(_ldrsb, 5600, f9100000), \
10324 X(_ldrsh, 5e00, f9300000), \
10325 X(_ldr_pc,4800, f85f0000), \
10326 X(_ldr_pc2,4800, f85f0000), \
10327 X(_ldr_sp,9800, f85d0000), \
10328 X(_lsl, 0000, fa00f000), \
10329 X(_lsls, 0000, fa10f000), \
10330 X(_lsr, 0800, fa20f000), \
10331 X(_lsrs, 0800, fa30f000), \
10332 X(_mov, 2000, ea4f0000), \
10333 X(_movs, 2000, ea5f0000), \
10334 X(_mul, 4340, fb00f000), \
10335 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10336 X(_mvn, 43c0, ea6f0000), \
10337 X(_mvns, 43c0, ea7f0000), \
10338 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10339 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10340 X(_orr, 4300, ea400000), \
10341 X(_orrs, 4300, ea500000), \
10342 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10343 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10344 X(_rev, ba00, fa90f080), \
10345 X(_rev16, ba40, fa90f090), \
10346 X(_revsh, bac0, fa90f0b0), \
10347 X(_ror, 41c0, fa60f000), \
10348 X(_rors, 41c0, fa70f000), \
10349 X(_sbc, 4180, eb600000), \
10350 X(_sbcs, 4180, eb700000), \
10351 X(_stmia, c000, e8800000), \
10352 X(_str, 6000, f8400000), \
10353 X(_strb, 7000, f8000000), \
10354 X(_strh, 8000, f8200000), \
10355 X(_str_sp,9000, f84d0000), \
10356 X(_sub, 1e00, eba00000), \
10357 X(_subs, 1e00, ebb00000), \
10358 X(_subi, 8000, f1a00000), \
10359 X(_subis, 8000, f1b00000), \
10360 X(_sxtb, b240, fa4ff080), \
10361 X(_sxth, b200, fa0ff080), \
10362 X(_tst, 4200, ea100f00), \
10363 X(_uxtb, b2c0, fa5ff080), \
10364 X(_uxth, b280, fa1ff080), \
10365 X(_nop, bf00, f3af8000), \
10366 X(_yield, bf10, f3af8001), \
10367 X(_wfe, bf20, f3af8002), \
10368 X(_wfi, bf30, f3af8003), \
10369 X(_sev, bf40, f3af8004), \
10370 X(_sevl, bf50, f3af8005), \
10371 X(_udf, de00, f7f0a000)
10373 /* To catch errors in encoding functions, the codes are all offset by
10374 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10375 as 16-bit instructions. */
10376 #define X(a,b,c) T_MNEM##a
10377 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10380 #define X(a,b,c) 0x##b
10381 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10382 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10385 #define X(a,b,c) 0x##c
10386 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10387 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10388 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10392 /* Thumb instruction encoders, in alphabetical order. */
10394 /* ADDW or SUBW. */
10397 do_t_add_sub_w (void)
10401 Rd
= inst
.operands
[0].reg
;
10402 Rn
= inst
.operands
[1].reg
;
10404 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10405 is the SP-{plus,minus}-immediate form of the instruction. */
10407 constraint (Rd
== REG_PC
, BAD_PC
);
10409 reject_bad_reg (Rd
);
10411 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10412 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10415 /* Parse an add or subtract instruction. We get here with inst.instruction
10416 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10419 do_t_add_sub (void)
10423 Rd
= inst
.operands
[0].reg
;
10424 Rs
= (inst
.operands
[1].present
10425 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10426 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10429 set_it_insn_type_last ();
10431 if (unified_syntax
)
10434 bfd_boolean narrow
;
10437 flags
= (inst
.instruction
== T_MNEM_adds
10438 || inst
.instruction
== T_MNEM_subs
);
10440 narrow
= !in_it_block ();
10442 narrow
= in_it_block ();
10443 if (!inst
.operands
[2].isreg
)
10447 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10449 add
= (inst
.instruction
== T_MNEM_add
10450 || inst
.instruction
== T_MNEM_adds
);
10452 if (inst
.size_req
!= 4)
10454 /* Attempt to use a narrow opcode, with relaxation if
10456 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10457 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10458 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10459 opcode
= T_MNEM_add_sp
;
10460 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10461 opcode
= T_MNEM_add_pc
;
10462 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10465 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10467 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10471 inst
.instruction
= THUMB_OP16(opcode
);
10472 inst
.instruction
|= (Rd
<< 4) | Rs
;
10473 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10474 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10475 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10476 if (inst
.size_req
!= 2)
10477 inst
.relax
= opcode
;
10480 constraint (inst
.size_req
== 2, BAD_HIREG
);
10482 if (inst
.size_req
== 4
10483 || (inst
.size_req
!= 2 && !opcode
))
10487 constraint (add
, BAD_PC
);
10488 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10489 _("only SUBS PC, LR, #const allowed"));
10490 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10491 _("expression too complex"));
10492 constraint (inst
.reloc
.exp
.X_add_number
< 0
10493 || inst
.reloc
.exp
.X_add_number
> 0xff,
10494 _("immediate value out of range"));
10495 inst
.instruction
= T2_SUBS_PC_LR
10496 | inst
.reloc
.exp
.X_add_number
;
10497 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10500 else if (Rs
== REG_PC
)
10502 /* Always use addw/subw. */
10503 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10504 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10508 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10509 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10512 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10514 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10516 inst
.instruction
|= Rd
<< 8;
10517 inst
.instruction
|= Rs
<< 16;
10522 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10523 unsigned int shift
= inst
.operands
[2].shift_kind
;
10525 Rn
= inst
.operands
[2].reg
;
10526 /* See if we can do this with a 16-bit instruction. */
10527 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10529 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10534 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10535 || inst
.instruction
== T_MNEM_add
)
10537 : T_OPCODE_SUB_R3
);
10538 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10542 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10544 /* Thumb-1 cores (except v6-M) require at least one high
10545 register in a narrow non flag setting add. */
10546 if (Rd
> 7 || Rn
> 7
10547 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10548 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10555 inst
.instruction
= T_OPCODE_ADD_HI
;
10556 inst
.instruction
|= (Rd
& 8) << 4;
10557 inst
.instruction
|= (Rd
& 7);
10558 inst
.instruction
|= Rn
<< 3;
10564 constraint (Rd
== REG_PC
, BAD_PC
);
10565 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10566 constraint (Rs
== REG_PC
, BAD_PC
);
10567 reject_bad_reg (Rn
);
10569 /* If we get here, it can't be done in 16 bits. */
10570 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10571 _("shift must be constant"));
10572 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10573 inst
.instruction
|= Rd
<< 8;
10574 inst
.instruction
|= Rs
<< 16;
10575 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10576 _("shift value over 3 not allowed in thumb mode"));
10577 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10578 _("only LSL shift allowed in thumb mode"));
10579 encode_thumb32_shifted_operand (2);
10584 constraint (inst
.instruction
== T_MNEM_adds
10585 || inst
.instruction
== T_MNEM_subs
,
10588 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10590 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10591 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10594 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10595 ? 0x0000 : 0x8000);
10596 inst
.instruction
|= (Rd
<< 4) | Rs
;
10597 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10601 Rn
= inst
.operands
[2].reg
;
10602 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10604 /* We now have Rd, Rs, and Rn set to registers. */
10605 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10607 /* Can't do this for SUB. */
10608 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10609 inst
.instruction
= T_OPCODE_ADD_HI
;
10610 inst
.instruction
|= (Rd
& 8) << 4;
10611 inst
.instruction
|= (Rd
& 7);
10613 inst
.instruction
|= Rn
<< 3;
10615 inst
.instruction
|= Rs
<< 3;
10617 constraint (1, _("dest must overlap one source register"));
10621 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10622 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10623 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10633 Rd
= inst
.operands
[0].reg
;
10634 reject_bad_reg (Rd
);
10636 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10638 /* Defer to section relaxation. */
10639 inst
.relax
= inst
.instruction
;
10640 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10641 inst
.instruction
|= Rd
<< 4;
10643 else if (unified_syntax
&& inst
.size_req
!= 2)
10645 /* Generate a 32-bit opcode. */
10646 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10647 inst
.instruction
|= Rd
<< 8;
10648 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10649 inst
.reloc
.pc_rel
= 1;
10653 /* Generate a 16-bit opcode. */
10654 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10655 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10656 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10657 inst
.reloc
.pc_rel
= 1;
10659 inst
.instruction
|= Rd
<< 4;
10663 /* Arithmetic instructions for which there is just one 16-bit
10664 instruction encoding, and it allows only two low registers.
10665 For maximal compatibility with ARM syntax, we allow three register
10666 operands even when Thumb-32 instructions are not available, as long
10667 as the first two are identical. For instance, both "sbc r0,r1" and
10668 "sbc r0,r0,r1" are allowed. */
10674 Rd
= inst
.operands
[0].reg
;
10675 Rs
= (inst
.operands
[1].present
10676 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10677 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10678 Rn
= inst
.operands
[2].reg
;
10680 reject_bad_reg (Rd
);
10681 reject_bad_reg (Rs
);
10682 if (inst
.operands
[2].isreg
)
10683 reject_bad_reg (Rn
);
10685 if (unified_syntax
)
10687 if (!inst
.operands
[2].isreg
)
10689 /* For an immediate, we always generate a 32-bit opcode;
10690 section relaxation will shrink it later if possible. */
10691 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10692 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10693 inst
.instruction
|= Rd
<< 8;
10694 inst
.instruction
|= Rs
<< 16;
10695 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10699 bfd_boolean narrow
;
10701 /* See if we can do this with a 16-bit instruction. */
10702 if (THUMB_SETS_FLAGS (inst
.instruction
))
10703 narrow
= !in_it_block ();
10705 narrow
= in_it_block ();
10707 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10709 if (inst
.operands
[2].shifted
)
10711 if (inst
.size_req
== 4)
10717 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10718 inst
.instruction
|= Rd
;
10719 inst
.instruction
|= Rn
<< 3;
10723 /* If we get here, it can't be done in 16 bits. */
10724 constraint (inst
.operands
[2].shifted
10725 && inst
.operands
[2].immisreg
,
10726 _("shift must be constant"));
10727 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10728 inst
.instruction
|= Rd
<< 8;
10729 inst
.instruction
|= Rs
<< 16;
10730 encode_thumb32_shifted_operand (2);
10735 /* On its face this is a lie - the instruction does set the
10736 flags. However, the only supported mnemonic in this mode
10737 says it doesn't. */
10738 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10740 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10741 _("unshifted register required"));
10742 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10743 constraint (Rd
!= Rs
,
10744 _("dest and source1 must be the same register"));
10746 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10747 inst
.instruction
|= Rd
;
10748 inst
.instruction
|= Rn
<< 3;
10752 /* Similarly, but for instructions where the arithmetic operation is
10753 commutative, so we can allow either of them to be different from
10754 the destination operand in a 16-bit instruction. For instance, all
10755 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10762 Rd
= inst
.operands
[0].reg
;
10763 Rs
= (inst
.operands
[1].present
10764 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10765 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10766 Rn
= inst
.operands
[2].reg
;
10768 reject_bad_reg (Rd
);
10769 reject_bad_reg (Rs
);
10770 if (inst
.operands
[2].isreg
)
10771 reject_bad_reg (Rn
);
10773 if (unified_syntax
)
10775 if (!inst
.operands
[2].isreg
)
10777 /* For an immediate, we always generate a 32-bit opcode;
10778 section relaxation will shrink it later if possible. */
10779 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10780 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10781 inst
.instruction
|= Rd
<< 8;
10782 inst
.instruction
|= Rs
<< 16;
10783 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10787 bfd_boolean narrow
;
10789 /* See if we can do this with a 16-bit instruction. */
10790 if (THUMB_SETS_FLAGS (inst
.instruction
))
10791 narrow
= !in_it_block ();
10793 narrow
= in_it_block ();
10795 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10797 if (inst
.operands
[2].shifted
)
10799 if (inst
.size_req
== 4)
10806 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10807 inst
.instruction
|= Rd
;
10808 inst
.instruction
|= Rn
<< 3;
10813 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10814 inst
.instruction
|= Rd
;
10815 inst
.instruction
|= Rs
<< 3;
10820 /* If we get here, it can't be done in 16 bits. */
10821 constraint (inst
.operands
[2].shifted
10822 && inst
.operands
[2].immisreg
,
10823 _("shift must be constant"));
10824 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10825 inst
.instruction
|= Rd
<< 8;
10826 inst
.instruction
|= Rs
<< 16;
10827 encode_thumb32_shifted_operand (2);
10832 /* On its face this is a lie - the instruction does set the
10833 flags. However, the only supported mnemonic in this mode
10834 says it doesn't. */
10835 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10837 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10838 _("unshifted register required"));
10839 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10841 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10842 inst
.instruction
|= Rd
;
10845 inst
.instruction
|= Rn
<< 3;
10847 inst
.instruction
|= Rs
<< 3;
10849 constraint (1, _("dest must overlap one source register"));
10857 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10858 constraint (msb
> 32, _("bit-field extends past end of register"));
10859 /* The instruction encoding stores the LSB and MSB,
10860 not the LSB and width. */
10861 Rd
= inst
.operands
[0].reg
;
10862 reject_bad_reg (Rd
);
10863 inst
.instruction
|= Rd
<< 8;
10864 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10865 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10866 inst
.instruction
|= msb
- 1;
10875 Rd
= inst
.operands
[0].reg
;
10876 reject_bad_reg (Rd
);
10878 /* #0 in second position is alternative syntax for bfc, which is
10879 the same instruction but with REG_PC in the Rm field. */
10880 if (!inst
.operands
[1].isreg
)
10884 Rn
= inst
.operands
[1].reg
;
10885 reject_bad_reg (Rn
);
10888 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10889 constraint (msb
> 32, _("bit-field extends past end of register"));
10890 /* The instruction encoding stores the LSB and MSB,
10891 not the LSB and width. */
10892 inst
.instruction
|= Rd
<< 8;
10893 inst
.instruction
|= Rn
<< 16;
10894 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10895 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10896 inst
.instruction
|= msb
- 1;
10904 Rd
= inst
.operands
[0].reg
;
10905 Rn
= inst
.operands
[1].reg
;
10907 reject_bad_reg (Rd
);
10908 reject_bad_reg (Rn
);
10910 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10911 _("bit-field extends past end of register"));
10912 inst
.instruction
|= Rd
<< 8;
10913 inst
.instruction
|= Rn
<< 16;
10914 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10915 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10916 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10919 /* ARM V5 Thumb BLX (argument parse)
10920 BLX <target_addr> which is BLX(1)
10921 BLX <Rm> which is BLX(2)
10922 Unfortunately, there are two different opcodes for this mnemonic.
10923 So, the insns[].value is not used, and the code here zaps values
10924 into inst.instruction.
10926 ??? How to take advantage of the additional two bits of displacement
10927 available in Thumb32 mode? Need new relocation? */
10932 set_it_insn_type_last ();
10934 if (inst
.operands
[0].isreg
)
10936 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10937 /* We have a register, so this is BLX(2). */
10938 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10942 /* No register. This must be BLX(1). */
10943 inst
.instruction
= 0xf000e800;
10944 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10956 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10958 if (in_it_block ())
10960 /* Conditional branches inside IT blocks are encoded as unconditional
10962 cond
= COND_ALWAYS
;
10967 if (cond
!= COND_ALWAYS
)
10968 opcode
= T_MNEM_bcond
;
10970 opcode
= inst
.instruction
;
10973 && (inst
.size_req
== 4
10974 || (inst
.size_req
!= 2
10975 && (inst
.operands
[0].hasreloc
10976 || inst
.reloc
.exp
.X_op
== O_constant
))))
10978 inst
.instruction
= THUMB_OP32(opcode
);
10979 if (cond
== COND_ALWAYS
)
10980 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10983 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
10984 _("selected architecture does not support "
10985 "wide conditional branch instruction"));
10987 gas_assert (cond
!= 0xF);
10988 inst
.instruction
|= cond
<< 22;
10989 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10994 inst
.instruction
= THUMB_OP16(opcode
);
10995 if (cond
== COND_ALWAYS
)
10996 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10999 inst
.instruction
|= cond
<< 8;
11000 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11002 /* Allow section relaxation. */
11003 if (unified_syntax
&& inst
.size_req
!= 2)
11004 inst
.relax
= opcode
;
11006 inst
.reloc
.type
= reloc
;
11007 inst
.reloc
.pc_rel
= 1;
11010 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11011 between the two is the maximum immediate allowed - which is passed in
11014 do_t_bkpt_hlt1 (int range
)
11016 constraint (inst
.cond
!= COND_ALWAYS
,
11017 _("instruction is always unconditional"));
11018 if (inst
.operands
[0].present
)
11020 constraint (inst
.operands
[0].imm
> range
,
11021 _("immediate value out of range"));
11022 inst
.instruction
|= inst
.operands
[0].imm
;
11025 set_it_insn_type (NEUTRAL_IT_INSN
);
11031 do_t_bkpt_hlt1 (63);
11037 do_t_bkpt_hlt1 (255);
11041 do_t_branch23 (void)
11043 set_it_insn_type_last ();
11044 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11046 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11047 this file. We used to simply ignore the PLT reloc type here --
11048 the branch encoding is now needed to deal with TLSCALL relocs.
11049 So if we see a PLT reloc now, put it back to how it used to be to
11050 keep the preexisting behaviour. */
11051 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11052 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11054 #if defined(OBJ_COFF)
11055 /* If the destination of the branch is a defined symbol which does not have
11056 the THUMB_FUNC attribute, then we must be calling a function which has
11057 the (interfacearm) attribute. We look for the Thumb entry point to that
11058 function and change the branch to refer to that function instead. */
11059 if ( inst
.reloc
.exp
.X_op
== O_symbol
11060 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11061 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11062 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11063 inst
.reloc
.exp
.X_add_symbol
=
11064 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11071 set_it_insn_type_last ();
11072 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11073 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11074 should cause the alignment to be checked once it is known. This is
11075 because BX PC only works if the instruction is word aligned. */
11083 set_it_insn_type_last ();
11084 Rm
= inst
.operands
[0].reg
;
11085 reject_bad_reg (Rm
);
11086 inst
.instruction
|= Rm
<< 16;
11095 Rd
= inst
.operands
[0].reg
;
11096 Rm
= inst
.operands
[1].reg
;
11098 reject_bad_reg (Rd
);
11099 reject_bad_reg (Rm
);
11101 inst
.instruction
|= Rd
<< 8;
11102 inst
.instruction
|= Rm
<< 16;
11103 inst
.instruction
|= Rm
;
11109 set_it_insn_type (OUTSIDE_IT_INSN
);
11110 inst
.instruction
|= inst
.operands
[0].imm
;
11116 set_it_insn_type (OUTSIDE_IT_INSN
);
11118 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11119 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11121 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11122 inst
.instruction
= 0xf3af8000;
11123 inst
.instruction
|= imod
<< 9;
11124 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11125 if (inst
.operands
[1].present
)
11126 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11130 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11131 && (inst
.operands
[0].imm
& 4),
11132 _("selected processor does not support 'A' form "
11133 "of this instruction"));
11134 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11135 _("Thumb does not support the 2-argument "
11136 "form of this instruction"));
11137 inst
.instruction
|= inst
.operands
[0].imm
;
11141 /* THUMB CPY instruction (argument parse). */
11146 if (inst
.size_req
== 4)
11148 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11149 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11150 inst
.instruction
|= inst
.operands
[1].reg
;
11154 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11155 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11156 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11163 set_it_insn_type (OUTSIDE_IT_INSN
);
11164 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11165 inst
.instruction
|= inst
.operands
[0].reg
;
11166 inst
.reloc
.pc_rel
= 1;
11167 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11173 inst
.instruction
|= inst
.operands
[0].imm
;
11179 unsigned Rd
, Rn
, Rm
;
11181 Rd
= inst
.operands
[0].reg
;
11182 Rn
= (inst
.operands
[1].present
11183 ? inst
.operands
[1].reg
: Rd
);
11184 Rm
= inst
.operands
[2].reg
;
11186 reject_bad_reg (Rd
);
11187 reject_bad_reg (Rn
);
11188 reject_bad_reg (Rm
);
11190 inst
.instruction
|= Rd
<< 8;
11191 inst
.instruction
|= Rn
<< 16;
11192 inst
.instruction
|= Rm
;
11198 if (unified_syntax
&& inst
.size_req
== 4)
11199 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11201 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11207 unsigned int cond
= inst
.operands
[0].imm
;
11209 set_it_insn_type (IT_INSN
);
11210 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11212 now_it
.warn_deprecated
= FALSE
;
11214 /* If the condition is a negative condition, invert the mask. */
11215 if ((cond
& 0x1) == 0x0)
11217 unsigned int mask
= inst
.instruction
& 0x000f;
11219 if ((mask
& 0x7) == 0)
11221 /* No conversion needed. */
11222 now_it
.block_length
= 1;
11224 else if ((mask
& 0x3) == 0)
11227 now_it
.block_length
= 2;
11229 else if ((mask
& 0x1) == 0)
11232 now_it
.block_length
= 3;
11237 now_it
.block_length
= 4;
11240 inst
.instruction
&= 0xfff0;
11241 inst
.instruction
|= mask
;
11244 inst
.instruction
|= cond
<< 4;
11247 /* Helper function used for both push/pop and ldm/stm. */
11249 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11253 load
= (inst
.instruction
& (1 << 20)) != 0;
11255 if (mask
& (1 << 13))
11256 inst
.error
= _("SP not allowed in register list");
11258 if ((mask
& (1 << base
)) != 0
11260 inst
.error
= _("having the base register in the register list when "
11261 "using write back is UNPREDICTABLE");
11265 if (mask
& (1 << 15))
11267 if (mask
& (1 << 14))
11268 inst
.error
= _("LR and PC should not both be in register list");
11270 set_it_insn_type_last ();
11275 if (mask
& (1 << 15))
11276 inst
.error
= _("PC not allowed in register list");
11279 if ((mask
& (mask
- 1)) == 0)
11281 /* Single register transfers implemented as str/ldr. */
11284 if (inst
.instruction
& (1 << 23))
11285 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11287 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11291 if (inst
.instruction
& (1 << 23))
11292 inst
.instruction
= 0x00800000; /* ia -> [base] */
11294 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11297 inst
.instruction
|= 0xf8400000;
11299 inst
.instruction
|= 0x00100000;
11301 mask
= ffs (mask
) - 1;
11304 else if (writeback
)
11305 inst
.instruction
|= WRITE_BACK
;
11307 inst
.instruction
|= mask
;
11308 inst
.instruction
|= base
<< 16;
11314 /* This really doesn't seem worth it. */
11315 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11316 _("expression too complex"));
11317 constraint (inst
.operands
[1].writeback
,
11318 _("Thumb load/store multiple does not support {reglist}^"));
11320 if (unified_syntax
)
11322 bfd_boolean narrow
;
11326 /* See if we can use a 16-bit instruction. */
11327 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11328 && inst
.size_req
!= 4
11329 && !(inst
.operands
[1].imm
& ~0xff))
11331 mask
= 1 << inst
.operands
[0].reg
;
11333 if (inst
.operands
[0].reg
<= 7)
11335 if (inst
.instruction
== T_MNEM_stmia
11336 ? inst
.operands
[0].writeback
11337 : (inst
.operands
[0].writeback
11338 == !(inst
.operands
[1].imm
& mask
)))
11340 if (inst
.instruction
== T_MNEM_stmia
11341 && (inst
.operands
[1].imm
& mask
)
11342 && (inst
.operands
[1].imm
& (mask
- 1)))
11343 as_warn (_("value stored for r%d is UNKNOWN"),
11344 inst
.operands
[0].reg
);
11346 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11347 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11348 inst
.instruction
|= inst
.operands
[1].imm
;
11351 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11353 /* This means 1 register in reg list one of 3 situations:
11354 1. Instruction is stmia, but without writeback.
11355 2. lmdia without writeback, but with Rn not in
11357 3. ldmia with writeback, but with Rn in reglist.
11358 Case 3 is UNPREDICTABLE behaviour, so we handle
11359 case 1 and 2 which can be converted into a 16-bit
11360 str or ldr. The SP cases are handled below. */
11361 unsigned long opcode
;
11362 /* First, record an error for Case 3. */
11363 if (inst
.operands
[1].imm
& mask
11364 && inst
.operands
[0].writeback
)
11366 _("having the base register in the register list when "
11367 "using write back is UNPREDICTABLE");
11369 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11371 inst
.instruction
= THUMB_OP16 (opcode
);
11372 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11373 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11377 else if (inst
.operands
[0] .reg
== REG_SP
)
11379 if (inst
.operands
[0].writeback
)
11382 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11383 ? T_MNEM_push
: T_MNEM_pop
);
11384 inst
.instruction
|= inst
.operands
[1].imm
;
11387 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11390 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11391 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11392 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11400 if (inst
.instruction
< 0xffff)
11401 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11403 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11404 inst
.operands
[0].writeback
);
11409 constraint (inst
.operands
[0].reg
> 7
11410 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11411 constraint (inst
.instruction
!= T_MNEM_ldmia
11412 && inst
.instruction
!= T_MNEM_stmia
,
11413 _("Thumb-2 instruction only valid in unified syntax"));
11414 if (inst
.instruction
== T_MNEM_stmia
)
11416 if (!inst
.operands
[0].writeback
)
11417 as_warn (_("this instruction will write back the base register"));
11418 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11419 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11420 as_warn (_("value stored for r%d is UNKNOWN"),
11421 inst
.operands
[0].reg
);
11425 if (!inst
.operands
[0].writeback
11426 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11427 as_warn (_("this instruction will write back the base register"));
11428 else if (inst
.operands
[0].writeback
11429 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11430 as_warn (_("this instruction will not write back the base register"));
11433 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11434 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11435 inst
.instruction
|= inst
.operands
[1].imm
;
11442 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11443 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11444 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11445 || inst
.operands
[1].negative
,
11448 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11450 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11451 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11452 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11458 if (!inst
.operands
[1].present
)
11460 constraint (inst
.operands
[0].reg
== REG_LR
,
11461 _("r14 not allowed as first register "
11462 "when second register is omitted"));
11463 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11465 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11468 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11469 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11470 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11476 unsigned long opcode
;
11479 if (inst
.operands
[0].isreg
11480 && !inst
.operands
[0].preind
11481 && inst
.operands
[0].reg
== REG_PC
)
11482 set_it_insn_type_last ();
11484 opcode
= inst
.instruction
;
11485 if (unified_syntax
)
11487 if (!inst
.operands
[1].isreg
)
11489 if (opcode
<= 0xffff)
11490 inst
.instruction
= THUMB_OP32 (opcode
);
11491 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11494 if (inst
.operands
[1].isreg
11495 && !inst
.operands
[1].writeback
11496 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11497 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11498 && opcode
<= 0xffff
11499 && inst
.size_req
!= 4)
11501 /* Insn may have a 16-bit form. */
11502 Rn
= inst
.operands
[1].reg
;
11503 if (inst
.operands
[1].immisreg
)
11505 inst
.instruction
= THUMB_OP16 (opcode
);
11507 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11509 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11510 reject_bad_reg (inst
.operands
[1].imm
);
11512 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11513 && opcode
!= T_MNEM_ldrsb
)
11514 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11515 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11522 if (inst
.reloc
.pc_rel
)
11523 opcode
= T_MNEM_ldr_pc2
;
11525 opcode
= T_MNEM_ldr_pc
;
11529 if (opcode
== T_MNEM_ldr
)
11530 opcode
= T_MNEM_ldr_sp
;
11532 opcode
= T_MNEM_str_sp
;
11534 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11538 inst
.instruction
= inst
.operands
[0].reg
;
11539 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11541 inst
.instruction
|= THUMB_OP16 (opcode
);
11542 if (inst
.size_req
== 2)
11543 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11545 inst
.relax
= opcode
;
11549 /* Definitely a 32-bit variant. */
11551 /* Warning for Erratum 752419. */
11552 if (opcode
== T_MNEM_ldr
11553 && inst
.operands
[0].reg
== REG_SP
11554 && inst
.operands
[1].writeback
== 1
11555 && !inst
.operands
[1].immisreg
)
11557 if (no_cpu_selected ()
11558 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11559 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11560 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11561 as_warn (_("This instruction may be unpredictable "
11562 "if executed on M-profile cores "
11563 "with interrupts enabled."));
11566 /* Do some validations regarding addressing modes. */
11567 if (inst
.operands
[1].immisreg
)
11568 reject_bad_reg (inst
.operands
[1].imm
);
11570 constraint (inst
.operands
[1].writeback
== 1
11571 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11574 inst
.instruction
= THUMB_OP32 (opcode
);
11575 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11576 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11577 check_ldr_r15_aligned ();
11581 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11583 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11585 /* Only [Rn,Rm] is acceptable. */
11586 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11587 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11588 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11589 || inst
.operands
[1].negative
,
11590 _("Thumb does not support this addressing mode"));
11591 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11595 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11596 if (!inst
.operands
[1].isreg
)
11597 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11600 constraint (!inst
.operands
[1].preind
11601 || inst
.operands
[1].shifted
11602 || inst
.operands
[1].writeback
,
11603 _("Thumb does not support this addressing mode"));
11604 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11606 constraint (inst
.instruction
& 0x0600,
11607 _("byte or halfword not valid for base register"));
11608 constraint (inst
.operands
[1].reg
== REG_PC
11609 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11610 _("r15 based store not allowed"));
11611 constraint (inst
.operands
[1].immisreg
,
11612 _("invalid base register for register offset"));
11614 if (inst
.operands
[1].reg
== REG_PC
)
11615 inst
.instruction
= T_OPCODE_LDR_PC
;
11616 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11617 inst
.instruction
= T_OPCODE_LDR_SP
;
11619 inst
.instruction
= T_OPCODE_STR_SP
;
11621 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11622 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11626 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11627 if (!inst
.operands
[1].immisreg
)
11629 /* Immediate offset. */
11630 inst
.instruction
|= inst
.operands
[0].reg
;
11631 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11632 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11636 /* Register offset. */
11637 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11638 constraint (inst
.operands
[1].negative
,
11639 _("Thumb does not support this addressing mode"));
11642 switch (inst
.instruction
)
11644 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11645 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11646 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11647 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11648 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11649 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11650 case 0x5600 /* ldrsb */:
11651 case 0x5e00 /* ldrsh */: break;
11655 inst
.instruction
|= inst
.operands
[0].reg
;
11656 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11657 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11663 if (!inst
.operands
[1].present
)
11665 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11666 constraint (inst
.operands
[0].reg
== REG_LR
,
11667 _("r14 not allowed here"));
11668 constraint (inst
.operands
[0].reg
== REG_R12
,
11669 _("r12 not allowed here"));
11672 if (inst
.operands
[2].writeback
11673 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11674 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11675 as_warn (_("base register written back, and overlaps "
11676 "one of transfer registers"));
11678 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11679 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11680 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11686 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11687 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11693 unsigned Rd
, Rn
, Rm
, Ra
;
11695 Rd
= inst
.operands
[0].reg
;
11696 Rn
= inst
.operands
[1].reg
;
11697 Rm
= inst
.operands
[2].reg
;
11698 Ra
= inst
.operands
[3].reg
;
11700 reject_bad_reg (Rd
);
11701 reject_bad_reg (Rn
);
11702 reject_bad_reg (Rm
);
11703 reject_bad_reg (Ra
);
11705 inst
.instruction
|= Rd
<< 8;
11706 inst
.instruction
|= Rn
<< 16;
11707 inst
.instruction
|= Rm
;
11708 inst
.instruction
|= Ra
<< 12;
11714 unsigned RdLo
, RdHi
, Rn
, Rm
;
11716 RdLo
= inst
.operands
[0].reg
;
11717 RdHi
= inst
.operands
[1].reg
;
11718 Rn
= inst
.operands
[2].reg
;
11719 Rm
= inst
.operands
[3].reg
;
11721 reject_bad_reg (RdLo
);
11722 reject_bad_reg (RdHi
);
11723 reject_bad_reg (Rn
);
11724 reject_bad_reg (Rm
);
11726 inst
.instruction
|= RdLo
<< 12;
11727 inst
.instruction
|= RdHi
<< 8;
11728 inst
.instruction
|= Rn
<< 16;
11729 inst
.instruction
|= Rm
;
11733 do_t_mov_cmp (void)
11737 Rn
= inst
.operands
[0].reg
;
11738 Rm
= inst
.operands
[1].reg
;
11741 set_it_insn_type_last ();
11743 if (unified_syntax
)
11745 int r0off
= (inst
.instruction
== T_MNEM_mov
11746 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11747 unsigned long opcode
;
11748 bfd_boolean narrow
;
11749 bfd_boolean low_regs
;
11751 low_regs
= (Rn
<= 7 && Rm
<= 7);
11752 opcode
= inst
.instruction
;
11753 if (in_it_block ())
11754 narrow
= opcode
!= T_MNEM_movs
;
11756 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11757 if (inst
.size_req
== 4
11758 || inst
.operands
[1].shifted
)
11761 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11762 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11763 && !inst
.operands
[1].shifted
11767 inst
.instruction
= T2_SUBS_PC_LR
;
11771 if (opcode
== T_MNEM_cmp
)
11773 constraint (Rn
== REG_PC
, BAD_PC
);
11776 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11778 warn_deprecated_sp (Rm
);
11779 /* R15 was documented as a valid choice for Rm in ARMv6,
11780 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11781 tools reject R15, so we do too. */
11782 constraint (Rm
== REG_PC
, BAD_PC
);
11785 reject_bad_reg (Rm
);
11787 else if (opcode
== T_MNEM_mov
11788 || opcode
== T_MNEM_movs
)
11790 if (inst
.operands
[1].isreg
)
11792 if (opcode
== T_MNEM_movs
)
11794 reject_bad_reg (Rn
);
11795 reject_bad_reg (Rm
);
11799 /* This is mov.n. */
11800 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11801 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11803 as_tsktsk (_("Use of r%u as a source register is "
11804 "deprecated when r%u is the destination "
11805 "register."), Rm
, Rn
);
11810 /* This is mov.w. */
11811 constraint (Rn
== REG_PC
, BAD_PC
);
11812 constraint (Rm
== REG_PC
, BAD_PC
);
11813 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11817 reject_bad_reg (Rn
);
11820 if (!inst
.operands
[1].isreg
)
11822 /* Immediate operand. */
11823 if (!in_it_block () && opcode
== T_MNEM_mov
)
11825 if (low_regs
&& narrow
)
11827 inst
.instruction
= THUMB_OP16 (opcode
);
11828 inst
.instruction
|= Rn
<< 8;
11829 if (inst
.size_req
== 2)
11831 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11832 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11833 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11836 inst
.relax
= opcode
;
11840 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11841 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11842 inst
.instruction
|= Rn
<< r0off
;
11843 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11846 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11847 && (inst
.instruction
== T_MNEM_mov
11848 || inst
.instruction
== T_MNEM_movs
))
11850 /* Register shifts are encoded as separate shift instructions. */
11851 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11853 if (in_it_block ())
11858 if (inst
.size_req
== 4)
11861 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11867 switch (inst
.operands
[1].shift_kind
)
11870 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11873 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11876 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11879 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11885 inst
.instruction
= opcode
;
11888 inst
.instruction
|= Rn
;
11889 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11894 inst
.instruction
|= CONDS_BIT
;
11896 inst
.instruction
|= Rn
<< 8;
11897 inst
.instruction
|= Rm
<< 16;
11898 inst
.instruction
|= inst
.operands
[1].imm
;
11903 /* Some mov with immediate shift have narrow variants.
11904 Register shifts are handled above. */
11905 if (low_regs
&& inst
.operands
[1].shifted
11906 && (inst
.instruction
== T_MNEM_mov
11907 || inst
.instruction
== T_MNEM_movs
))
11909 if (in_it_block ())
11910 narrow
= (inst
.instruction
== T_MNEM_mov
);
11912 narrow
= (inst
.instruction
== T_MNEM_movs
);
11917 switch (inst
.operands
[1].shift_kind
)
11919 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11920 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11921 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11922 default: narrow
= FALSE
; break;
11928 inst
.instruction
|= Rn
;
11929 inst
.instruction
|= Rm
<< 3;
11930 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11934 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11935 inst
.instruction
|= Rn
<< r0off
;
11936 encode_thumb32_shifted_operand (1);
11940 switch (inst
.instruction
)
11943 /* In v4t or v5t a move of two lowregs produces unpredictable
11944 results. Don't allow this. */
11947 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11948 "MOV Rd, Rs with two low registers is not "
11949 "permitted on this architecture");
11950 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11954 inst
.instruction
= T_OPCODE_MOV_HR
;
11955 inst
.instruction
|= (Rn
& 0x8) << 4;
11956 inst
.instruction
|= (Rn
& 0x7);
11957 inst
.instruction
|= Rm
<< 3;
11961 /* We know we have low registers at this point.
11962 Generate LSLS Rd, Rs, #0. */
11963 inst
.instruction
= T_OPCODE_LSL_I
;
11964 inst
.instruction
|= Rn
;
11965 inst
.instruction
|= Rm
<< 3;
11971 inst
.instruction
= T_OPCODE_CMP_LR
;
11972 inst
.instruction
|= Rn
;
11973 inst
.instruction
|= Rm
<< 3;
11977 inst
.instruction
= T_OPCODE_CMP_HR
;
11978 inst
.instruction
|= (Rn
& 0x8) << 4;
11979 inst
.instruction
|= (Rn
& 0x7);
11980 inst
.instruction
|= Rm
<< 3;
11987 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11989 /* PR 10443: Do not silently ignore shifted operands. */
11990 constraint (inst
.operands
[1].shifted
,
11991 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11993 if (inst
.operands
[1].isreg
)
11995 if (Rn
< 8 && Rm
< 8)
11997 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11998 since a MOV instruction produces unpredictable results. */
11999 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12000 inst
.instruction
= T_OPCODE_ADD_I3
;
12002 inst
.instruction
= T_OPCODE_CMP_LR
;
12004 inst
.instruction
|= Rn
;
12005 inst
.instruction
|= Rm
<< 3;
12009 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12010 inst
.instruction
= T_OPCODE_MOV_HR
;
12012 inst
.instruction
= T_OPCODE_CMP_HR
;
12018 constraint (Rn
> 7,
12019 _("only lo regs allowed with immediate"));
12020 inst
.instruction
|= Rn
<< 8;
12021 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12032 top
= (inst
.instruction
& 0x00800000) != 0;
12033 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12035 constraint (top
, _(":lower16: not allowed this instruction"));
12036 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12038 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12040 constraint (!top
, _(":upper16: not allowed this instruction"));
12041 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12044 Rd
= inst
.operands
[0].reg
;
12045 reject_bad_reg (Rd
);
12047 inst
.instruction
|= Rd
<< 8;
12048 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12050 imm
= inst
.reloc
.exp
.X_add_number
;
12051 inst
.instruction
|= (imm
& 0xf000) << 4;
12052 inst
.instruction
|= (imm
& 0x0800) << 15;
12053 inst
.instruction
|= (imm
& 0x0700) << 4;
12054 inst
.instruction
|= (imm
& 0x00ff);
12059 do_t_mvn_tst (void)
12063 Rn
= inst
.operands
[0].reg
;
12064 Rm
= inst
.operands
[1].reg
;
12066 if (inst
.instruction
== T_MNEM_cmp
12067 || inst
.instruction
== T_MNEM_cmn
)
12068 constraint (Rn
== REG_PC
, BAD_PC
);
12070 reject_bad_reg (Rn
);
12071 reject_bad_reg (Rm
);
12073 if (unified_syntax
)
12075 int r0off
= (inst
.instruction
== T_MNEM_mvn
12076 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12077 bfd_boolean narrow
;
12079 if (inst
.size_req
== 4
12080 || inst
.instruction
> 0xffff
12081 || inst
.operands
[1].shifted
12082 || Rn
> 7 || Rm
> 7)
12084 else if (inst
.instruction
== T_MNEM_cmn
12085 || inst
.instruction
== T_MNEM_tst
)
12087 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12088 narrow
= !in_it_block ();
12090 narrow
= in_it_block ();
12092 if (!inst
.operands
[1].isreg
)
12094 /* For an immediate, we always generate a 32-bit opcode;
12095 section relaxation will shrink it later if possible. */
12096 if (inst
.instruction
< 0xffff)
12097 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12098 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12099 inst
.instruction
|= Rn
<< r0off
;
12100 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12104 /* See if we can do this with a 16-bit instruction. */
12107 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12108 inst
.instruction
|= Rn
;
12109 inst
.instruction
|= Rm
<< 3;
12113 constraint (inst
.operands
[1].shifted
12114 && inst
.operands
[1].immisreg
,
12115 _("shift must be constant"));
12116 if (inst
.instruction
< 0xffff)
12117 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12118 inst
.instruction
|= Rn
<< r0off
;
12119 encode_thumb32_shifted_operand (1);
12125 constraint (inst
.instruction
> 0xffff
12126 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12127 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12128 _("unshifted register required"));
12129 constraint (Rn
> 7 || Rm
> 7,
12132 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12133 inst
.instruction
|= Rn
;
12134 inst
.instruction
|= Rm
<< 3;
12143 if (do_vfp_nsyn_mrs () == SUCCESS
)
12146 Rd
= inst
.operands
[0].reg
;
12147 reject_bad_reg (Rd
);
12148 inst
.instruction
|= Rd
<< 8;
12150 if (inst
.operands
[1].isreg
)
12152 unsigned br
= inst
.operands
[1].reg
;
12153 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12154 as_bad (_("bad register for mrs"));
12156 inst
.instruction
|= br
& (0xf << 16);
12157 inst
.instruction
|= (br
& 0x300) >> 4;
12158 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12162 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12164 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12166 /* PR gas/12698: The constraint is only applied for m_profile.
12167 If the user has specified -march=all, we want to ignore it as
12168 we are building for any CPU type, including non-m variants. */
12169 bfd_boolean m_profile
=
12170 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12171 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12172 "not support requested special purpose register"));
12175 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12177 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12178 _("'APSR', 'CPSR' or 'SPSR' expected"));
12180 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12181 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12182 inst
.instruction
|= 0xf0000;
12192 if (do_vfp_nsyn_msr () == SUCCESS
)
12195 constraint (!inst
.operands
[1].isreg
,
12196 _("Thumb encoding does not support an immediate here"));
12198 if (inst
.operands
[0].isreg
)
12199 flags
= (int)(inst
.operands
[0].reg
);
12201 flags
= inst
.operands
[0].imm
;
12203 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12205 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12207 /* PR gas/12698: The constraint is only applied for m_profile.
12208 If the user has specified -march=all, we want to ignore it as
12209 we are building for any CPU type, including non-m variants. */
12210 bfd_boolean m_profile
=
12211 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12212 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12213 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12214 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12215 && bits
!= PSR_f
)) && m_profile
,
12216 _("selected processor does not support requested special "
12217 "purpose register"));
12220 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12221 "requested special purpose register"));
12223 Rn
= inst
.operands
[1].reg
;
12224 reject_bad_reg (Rn
);
12226 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12227 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12228 inst
.instruction
|= (flags
& 0x300) >> 4;
12229 inst
.instruction
|= (flags
& 0xff);
12230 inst
.instruction
|= Rn
<< 16;
12236 bfd_boolean narrow
;
12237 unsigned Rd
, Rn
, Rm
;
12239 if (!inst
.operands
[2].present
)
12240 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12242 Rd
= inst
.operands
[0].reg
;
12243 Rn
= inst
.operands
[1].reg
;
12244 Rm
= inst
.operands
[2].reg
;
12246 if (unified_syntax
)
12248 if (inst
.size_req
== 4
12254 else if (inst
.instruction
== T_MNEM_muls
)
12255 narrow
= !in_it_block ();
12257 narrow
= in_it_block ();
12261 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12262 constraint (Rn
> 7 || Rm
> 7,
12269 /* 16-bit MULS/Conditional MUL. */
12270 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12271 inst
.instruction
|= Rd
;
12274 inst
.instruction
|= Rm
<< 3;
12276 inst
.instruction
|= Rn
<< 3;
12278 constraint (1, _("dest must overlap one source register"));
12282 constraint (inst
.instruction
!= T_MNEM_mul
,
12283 _("Thumb-2 MUL must not set flags"));
12285 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12286 inst
.instruction
|= Rd
<< 8;
12287 inst
.instruction
|= Rn
<< 16;
12288 inst
.instruction
|= Rm
<< 0;
12290 reject_bad_reg (Rd
);
12291 reject_bad_reg (Rn
);
12292 reject_bad_reg (Rm
);
12299 unsigned RdLo
, RdHi
, Rn
, Rm
;
12301 RdLo
= inst
.operands
[0].reg
;
12302 RdHi
= inst
.operands
[1].reg
;
12303 Rn
= inst
.operands
[2].reg
;
12304 Rm
= inst
.operands
[3].reg
;
12306 reject_bad_reg (RdLo
);
12307 reject_bad_reg (RdHi
);
12308 reject_bad_reg (Rn
);
12309 reject_bad_reg (Rm
);
12311 inst
.instruction
|= RdLo
<< 12;
12312 inst
.instruction
|= RdHi
<< 8;
12313 inst
.instruction
|= Rn
<< 16;
12314 inst
.instruction
|= Rm
;
12317 as_tsktsk (_("rdhi and rdlo must be different"));
12323 set_it_insn_type (NEUTRAL_IT_INSN
);
12325 if (unified_syntax
)
12327 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12329 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12330 inst
.instruction
|= inst
.operands
[0].imm
;
12334 /* PR9722: Check for Thumb2 availability before
12335 generating a thumb2 nop instruction. */
12336 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12338 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12339 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12342 inst
.instruction
= 0x46c0;
12347 constraint (inst
.operands
[0].present
,
12348 _("Thumb does not support NOP with hints"));
12349 inst
.instruction
= 0x46c0;
12356 if (unified_syntax
)
12358 bfd_boolean narrow
;
12360 if (THUMB_SETS_FLAGS (inst
.instruction
))
12361 narrow
= !in_it_block ();
12363 narrow
= in_it_block ();
12364 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12366 if (inst
.size_req
== 4)
12371 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12372 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12373 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12377 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12378 inst
.instruction
|= inst
.operands
[0].reg
;
12379 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12384 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12386 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12388 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12389 inst
.instruction
|= inst
.operands
[0].reg
;
12390 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12399 Rd
= inst
.operands
[0].reg
;
12400 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12402 reject_bad_reg (Rd
);
12403 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12404 reject_bad_reg (Rn
);
12406 inst
.instruction
|= Rd
<< 8;
12407 inst
.instruction
|= Rn
<< 16;
12409 if (!inst
.operands
[2].isreg
)
12411 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12412 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12418 Rm
= inst
.operands
[2].reg
;
12419 reject_bad_reg (Rm
);
12421 constraint (inst
.operands
[2].shifted
12422 && inst
.operands
[2].immisreg
,
12423 _("shift must be constant"));
12424 encode_thumb32_shifted_operand (2);
12431 unsigned Rd
, Rn
, Rm
;
12433 Rd
= inst
.operands
[0].reg
;
12434 Rn
= inst
.operands
[1].reg
;
12435 Rm
= inst
.operands
[2].reg
;
12437 reject_bad_reg (Rd
);
12438 reject_bad_reg (Rn
);
12439 reject_bad_reg (Rm
);
12441 inst
.instruction
|= Rd
<< 8;
12442 inst
.instruction
|= Rn
<< 16;
12443 inst
.instruction
|= Rm
;
12444 if (inst
.operands
[3].present
)
12446 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12447 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12448 _("expression too complex"));
12449 inst
.instruction
|= (val
& 0x1c) << 10;
12450 inst
.instruction
|= (val
& 0x03) << 6;
12457 if (!inst
.operands
[3].present
)
12461 inst
.instruction
&= ~0x00000020;
12463 /* PR 10168. Swap the Rm and Rn registers. */
12464 Rtmp
= inst
.operands
[1].reg
;
12465 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12466 inst
.operands
[2].reg
= Rtmp
;
12474 if (inst
.operands
[0].immisreg
)
12475 reject_bad_reg (inst
.operands
[0].imm
);
12477 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12481 do_t_push_pop (void)
12485 constraint (inst
.operands
[0].writeback
,
12486 _("push/pop do not support {reglist}^"));
12487 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12488 _("expression too complex"));
12490 mask
= inst
.operands
[0].imm
;
12491 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12492 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12493 else if (inst
.size_req
!= 4
12494 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12495 ? REG_LR
: REG_PC
)))
12497 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12498 inst
.instruction
|= THUMB_PP_PC_LR
;
12499 inst
.instruction
|= mask
& 0xff;
12501 else if (unified_syntax
)
12503 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12504 encode_thumb2_ldmstm (13, mask
, TRUE
);
12508 inst
.error
= _("invalid register list to push/pop instruction");
12518 Rd
= inst
.operands
[0].reg
;
12519 Rm
= inst
.operands
[1].reg
;
12521 reject_bad_reg (Rd
);
12522 reject_bad_reg (Rm
);
12524 inst
.instruction
|= Rd
<< 8;
12525 inst
.instruction
|= Rm
<< 16;
12526 inst
.instruction
|= Rm
;
12534 Rd
= inst
.operands
[0].reg
;
12535 Rm
= inst
.operands
[1].reg
;
12537 reject_bad_reg (Rd
);
12538 reject_bad_reg (Rm
);
12540 if (Rd
<= 7 && Rm
<= 7
12541 && inst
.size_req
!= 4)
12543 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12544 inst
.instruction
|= Rd
;
12545 inst
.instruction
|= Rm
<< 3;
12547 else if (unified_syntax
)
12549 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12550 inst
.instruction
|= Rd
<< 8;
12551 inst
.instruction
|= Rm
<< 16;
12552 inst
.instruction
|= Rm
;
12555 inst
.error
= BAD_HIREG
;
12563 Rd
= inst
.operands
[0].reg
;
12564 Rm
= inst
.operands
[1].reg
;
12566 reject_bad_reg (Rd
);
12567 reject_bad_reg (Rm
);
12569 inst
.instruction
|= Rd
<< 8;
12570 inst
.instruction
|= Rm
;
12578 Rd
= inst
.operands
[0].reg
;
12579 Rs
= (inst
.operands
[1].present
12580 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12581 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12583 reject_bad_reg (Rd
);
12584 reject_bad_reg (Rs
);
12585 if (inst
.operands
[2].isreg
)
12586 reject_bad_reg (inst
.operands
[2].reg
);
12588 inst
.instruction
|= Rd
<< 8;
12589 inst
.instruction
|= Rs
<< 16;
12590 if (!inst
.operands
[2].isreg
)
12592 bfd_boolean narrow
;
12594 if ((inst
.instruction
& 0x00100000) != 0)
12595 narrow
= !in_it_block ();
12597 narrow
= in_it_block ();
12599 if (Rd
> 7 || Rs
> 7)
12602 if (inst
.size_req
== 4 || !unified_syntax
)
12605 if (inst
.reloc
.exp
.X_op
!= O_constant
12606 || inst
.reloc
.exp
.X_add_number
!= 0)
12609 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12610 relaxation, but it doesn't seem worth the hassle. */
12613 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12614 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12615 inst
.instruction
|= Rs
<< 3;
12616 inst
.instruction
|= Rd
;
12620 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12621 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12625 encode_thumb32_shifted_operand (2);
12631 if (warn_on_deprecated
12632 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12633 as_tsktsk (_("setend use is deprecated for ARMv8"));
12635 set_it_insn_type (OUTSIDE_IT_INSN
);
12636 if (inst
.operands
[0].imm
)
12637 inst
.instruction
|= 0x8;
12643 if (!inst
.operands
[1].present
)
12644 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12646 if (unified_syntax
)
12648 bfd_boolean narrow
;
12651 switch (inst
.instruction
)
12654 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12656 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12658 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12660 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12664 if (THUMB_SETS_FLAGS (inst
.instruction
))
12665 narrow
= !in_it_block ();
12667 narrow
= in_it_block ();
12668 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12670 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12672 if (inst
.operands
[2].isreg
12673 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12674 || inst
.operands
[2].reg
> 7))
12676 if (inst
.size_req
== 4)
12679 reject_bad_reg (inst
.operands
[0].reg
);
12680 reject_bad_reg (inst
.operands
[1].reg
);
12684 if (inst
.operands
[2].isreg
)
12686 reject_bad_reg (inst
.operands
[2].reg
);
12687 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12688 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12689 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12690 inst
.instruction
|= inst
.operands
[2].reg
;
12692 /* PR 12854: Error on extraneous shifts. */
12693 constraint (inst
.operands
[2].shifted
,
12694 _("extraneous shift as part of operand to shift insn"));
12698 inst
.operands
[1].shifted
= 1;
12699 inst
.operands
[1].shift_kind
= shift_kind
;
12700 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12701 ? T_MNEM_movs
: T_MNEM_mov
);
12702 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12703 encode_thumb32_shifted_operand (1);
12704 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12705 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12710 if (inst
.operands
[2].isreg
)
12712 switch (shift_kind
)
12714 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12715 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12716 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12717 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12721 inst
.instruction
|= inst
.operands
[0].reg
;
12722 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12724 /* PR 12854: Error on extraneous shifts. */
12725 constraint (inst
.operands
[2].shifted
,
12726 _("extraneous shift as part of operand to shift insn"));
12730 switch (shift_kind
)
12732 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12733 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12734 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12737 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12738 inst
.instruction
|= inst
.operands
[0].reg
;
12739 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12745 constraint (inst
.operands
[0].reg
> 7
12746 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12747 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12749 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12751 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12752 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12753 _("source1 and dest must be same register"));
12755 switch (inst
.instruction
)
12757 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12758 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12759 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12760 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12764 inst
.instruction
|= inst
.operands
[0].reg
;
12765 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12767 /* PR 12854: Error on extraneous shifts. */
12768 constraint (inst
.operands
[2].shifted
,
12769 _("extraneous shift as part of operand to shift insn"));
12773 switch (inst
.instruction
)
12775 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12776 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12777 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12778 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12781 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12782 inst
.instruction
|= inst
.operands
[0].reg
;
12783 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12791 unsigned Rd
, Rn
, Rm
;
12793 Rd
= inst
.operands
[0].reg
;
12794 Rn
= inst
.operands
[1].reg
;
12795 Rm
= inst
.operands
[2].reg
;
12797 reject_bad_reg (Rd
);
12798 reject_bad_reg (Rn
);
12799 reject_bad_reg (Rm
);
12801 inst
.instruction
|= Rd
<< 8;
12802 inst
.instruction
|= Rn
<< 16;
12803 inst
.instruction
|= Rm
;
12809 unsigned Rd
, Rn
, Rm
;
12811 Rd
= inst
.operands
[0].reg
;
12812 Rm
= inst
.operands
[1].reg
;
12813 Rn
= inst
.operands
[2].reg
;
12815 reject_bad_reg (Rd
);
12816 reject_bad_reg (Rn
);
12817 reject_bad_reg (Rm
);
12819 inst
.instruction
|= Rd
<< 8;
12820 inst
.instruction
|= Rn
<< 16;
12821 inst
.instruction
|= Rm
;
12827 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12828 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12829 _("SMC is not permitted on this architecture"));
12830 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12831 _("expression too complex"));
12832 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12833 inst
.instruction
|= (value
& 0xf000) >> 12;
12834 inst
.instruction
|= (value
& 0x0ff0);
12835 inst
.instruction
|= (value
& 0x000f) << 16;
12836 /* PR gas/15623: SMC instructions must be last in an IT block. */
12837 set_it_insn_type_last ();
12843 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12845 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12846 inst
.instruction
|= (value
& 0x0fff);
12847 inst
.instruction
|= (value
& 0xf000) << 4;
12851 do_t_ssat_usat (int bias
)
12855 Rd
= inst
.operands
[0].reg
;
12856 Rn
= inst
.operands
[2].reg
;
12858 reject_bad_reg (Rd
);
12859 reject_bad_reg (Rn
);
12861 inst
.instruction
|= Rd
<< 8;
12862 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12863 inst
.instruction
|= Rn
<< 16;
12865 if (inst
.operands
[3].present
)
12867 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12869 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12871 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12872 _("expression too complex"));
12874 if (shift_amount
!= 0)
12876 constraint (shift_amount
> 31,
12877 _("shift expression is too large"));
12879 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12880 inst
.instruction
|= 0x00200000; /* sh bit. */
12882 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12883 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12891 do_t_ssat_usat (1);
12899 Rd
= inst
.operands
[0].reg
;
12900 Rn
= inst
.operands
[2].reg
;
12902 reject_bad_reg (Rd
);
12903 reject_bad_reg (Rn
);
12905 inst
.instruction
|= Rd
<< 8;
12906 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12907 inst
.instruction
|= Rn
<< 16;
12913 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12914 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12915 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12916 || inst
.operands
[2].negative
,
12919 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12921 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12922 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12923 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12924 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12930 if (!inst
.operands
[2].present
)
12931 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12933 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12934 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12935 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12938 inst
.instruction
|= inst
.operands
[0].reg
;
12939 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12940 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12941 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12947 unsigned Rd
, Rn
, Rm
;
12949 Rd
= inst
.operands
[0].reg
;
12950 Rn
= inst
.operands
[1].reg
;
12951 Rm
= inst
.operands
[2].reg
;
12953 reject_bad_reg (Rd
);
12954 reject_bad_reg (Rn
);
12955 reject_bad_reg (Rm
);
12957 inst
.instruction
|= Rd
<< 8;
12958 inst
.instruction
|= Rn
<< 16;
12959 inst
.instruction
|= Rm
;
12960 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12968 Rd
= inst
.operands
[0].reg
;
12969 Rm
= inst
.operands
[1].reg
;
12971 reject_bad_reg (Rd
);
12972 reject_bad_reg (Rm
);
12974 if (inst
.instruction
<= 0xffff
12975 && inst
.size_req
!= 4
12976 && Rd
<= 7 && Rm
<= 7
12977 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12979 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12980 inst
.instruction
|= Rd
;
12981 inst
.instruction
|= Rm
<< 3;
12983 else if (unified_syntax
)
12985 if (inst
.instruction
<= 0xffff)
12986 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12987 inst
.instruction
|= Rd
<< 8;
12988 inst
.instruction
|= Rm
;
12989 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12993 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12994 _("Thumb encoding does not support rotation"));
12995 constraint (1, BAD_HIREG
);
13002 /* We have to do the following check manually as ARM_EXT_OS only applies
13004 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13006 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13007 /* This only applies to the v6m howver, not later architectures. */
13008 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13009 as_bad (_("SVC is not permitted on this architecture"));
13010 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13013 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13022 half
= (inst
.instruction
& 0x10) != 0;
13023 set_it_insn_type_last ();
13024 constraint (inst
.operands
[0].immisreg
,
13025 _("instruction requires register index"));
13027 Rn
= inst
.operands
[0].reg
;
13028 Rm
= inst
.operands
[0].imm
;
13030 constraint (Rn
== REG_SP
, BAD_SP
);
13031 reject_bad_reg (Rm
);
13033 constraint (!half
&& inst
.operands
[0].shifted
,
13034 _("instruction does not allow shifted index"));
13035 inst
.instruction
|= (Rn
<< 16) | Rm
;
13041 if (!inst
.operands
[0].present
)
13042 inst
.operands
[0].imm
= 0;
13044 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13046 constraint (inst
.size_req
== 2,
13047 _("immediate value out of range"));
13048 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13049 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13050 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13054 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13055 inst
.instruction
|= inst
.operands
[0].imm
;
13058 set_it_insn_type (NEUTRAL_IT_INSN
);
13065 do_t_ssat_usat (0);
13073 Rd
= inst
.operands
[0].reg
;
13074 Rn
= inst
.operands
[2].reg
;
13076 reject_bad_reg (Rd
);
13077 reject_bad_reg (Rn
);
13079 inst
.instruction
|= Rd
<< 8;
13080 inst
.instruction
|= inst
.operands
[1].imm
;
13081 inst
.instruction
|= Rn
<< 16;
13084 /* Neon instruction encoder helpers. */
13086 /* Encodings for the different types for various Neon opcodes. */
13088 /* An "invalid" code for the following tables. */
13091 struct neon_tab_entry
13094 unsigned float_or_poly
;
13095 unsigned scalar_or_imm
;
13098 /* Map overloaded Neon opcodes to their respective encodings. */
13099 #define NEON_ENC_TAB \
13100 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13101 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13102 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13103 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13104 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13105 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13106 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13107 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13108 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13109 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13110 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13111 /* Register variants of the following two instructions are encoded as
13112 vcge / vcgt with the operands reversed. */ \
13113 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13114 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13115 X(vfma, N_INV, 0x0000c10, N_INV), \
13116 X(vfms, N_INV, 0x0200c10, N_INV), \
13117 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13118 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13119 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13120 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13121 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13122 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13123 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13124 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13125 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13126 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13127 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13128 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13129 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13130 X(vshl, 0x0000400, N_INV, 0x0800510), \
13131 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13132 X(vand, 0x0000110, N_INV, 0x0800030), \
13133 X(vbic, 0x0100110, N_INV, 0x0800030), \
13134 X(veor, 0x1000110, N_INV, N_INV), \
13135 X(vorn, 0x0300110, N_INV, 0x0800010), \
13136 X(vorr, 0x0200110, N_INV, 0x0800010), \
13137 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13138 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13139 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13140 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13141 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13142 X(vst1, 0x0000000, 0x0800000, N_INV), \
13143 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13144 X(vst2, 0x0000100, 0x0800100, N_INV), \
13145 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13146 X(vst3, 0x0000200, 0x0800200, N_INV), \
13147 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13148 X(vst4, 0x0000300, 0x0800300, N_INV), \
13149 X(vmovn, 0x1b20200, N_INV, N_INV), \
13150 X(vtrn, 0x1b20080, N_INV, N_INV), \
13151 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13152 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13153 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13154 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13155 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13156 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13157 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13158 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13159 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13160 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13161 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13162 X(vseleq, 0xe000a00, N_INV, N_INV), \
13163 X(vselvs, 0xe100a00, N_INV, N_INV), \
13164 X(vselge, 0xe200a00, N_INV, N_INV), \
13165 X(vselgt, 0xe300a00, N_INV, N_INV), \
13166 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13167 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13168 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13169 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13170 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13171 X(aes, 0x3b00300, N_INV, N_INV), \
13172 X(sha3op, 0x2000c00, N_INV, N_INV), \
13173 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13174 X(sha2op, 0x3ba0380, N_INV, N_INV)
13178 #define X(OPC,I,F,S) N_MNEM_##OPC
13183 static const struct neon_tab_entry neon_enc_tab
[] =
13185 #define X(OPC,I,F,S) { (I), (F), (S) }
13190 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13191 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13192 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13193 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13194 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13195 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13196 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13197 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13198 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13199 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13200 #define NEON_ENC_SINGLE_(X) \
13201 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13202 #define NEON_ENC_DOUBLE_(X) \
13203 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13204 #define NEON_ENC_FPV8_(X) \
13205 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13207 #define NEON_ENCODE(type, inst) \
13210 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13211 inst.is_neon = 1; \
13215 #define check_neon_suffixes \
13218 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13220 as_bad (_("invalid neon suffix for non neon instruction")); \
13226 /* Define shapes for instruction operands. The following mnemonic characters
13227 are used in this table:
13229 F - VFP S<n> register
13230 D - Neon D<n> register
13231 Q - Neon Q<n> register
13235 L - D<n> register list
13237 This table is used to generate various data:
13238 - enumerations of the form NS_DDR to be used as arguments to
13240 - a table classifying shapes into single, double, quad, mixed.
13241 - a table used to drive neon_select_shape. */
13243 #define NEON_SHAPE_DEF \
13244 X(3, (D, D, D), DOUBLE), \
13245 X(3, (Q, Q, Q), QUAD), \
13246 X(3, (D, D, I), DOUBLE), \
13247 X(3, (Q, Q, I), QUAD), \
13248 X(3, (D, D, S), DOUBLE), \
13249 X(3, (Q, Q, S), QUAD), \
13250 X(2, (D, D), DOUBLE), \
13251 X(2, (Q, Q), QUAD), \
13252 X(2, (D, S), DOUBLE), \
13253 X(2, (Q, S), QUAD), \
13254 X(2, (D, R), DOUBLE), \
13255 X(2, (Q, R), QUAD), \
13256 X(2, (D, I), DOUBLE), \
13257 X(2, (Q, I), QUAD), \
13258 X(3, (D, L, D), DOUBLE), \
13259 X(2, (D, Q), MIXED), \
13260 X(2, (Q, D), MIXED), \
13261 X(3, (D, Q, I), MIXED), \
13262 X(3, (Q, D, I), MIXED), \
13263 X(3, (Q, D, D), MIXED), \
13264 X(3, (D, Q, Q), MIXED), \
13265 X(3, (Q, Q, D), MIXED), \
13266 X(3, (Q, D, S), MIXED), \
13267 X(3, (D, Q, S), MIXED), \
13268 X(4, (D, D, D, I), DOUBLE), \
13269 X(4, (Q, Q, Q, I), QUAD), \
13270 X(2, (F, F), SINGLE), \
13271 X(3, (F, F, F), SINGLE), \
13272 X(2, (F, I), SINGLE), \
13273 X(2, (F, D), MIXED), \
13274 X(2, (D, F), MIXED), \
13275 X(3, (F, F, I), MIXED), \
13276 X(4, (R, R, F, F), SINGLE), \
13277 X(4, (F, F, R, R), SINGLE), \
13278 X(3, (D, R, R), DOUBLE), \
13279 X(3, (R, R, D), DOUBLE), \
13280 X(2, (S, R), SINGLE), \
13281 X(2, (R, S), SINGLE), \
13282 X(2, (F, R), SINGLE), \
13283 X(2, (R, F), SINGLE), \
13284 /* Half float shape supported so far. */\
13285 X (2, (H, D), MIXED), \
13286 X (2, (D, H), MIXED), \
13287 X (2, (H, F), MIXED), \
13288 X (2, (F, H), MIXED), \
13289 X (2, (H, H), HALF), \
13290 X (2, (H, R), HALF), \
13291 X (2, (R, H), HALF), \
13292 X (2, (H, I), HALF), \
13293 X (3, (H, H, H), HALF), \
13294 X (3, (H, F, I), MIXED), \
13295 X (3, (F, H, I), MIXED)
13297 #define S2(A,B) NS_##A##B
13298 #define S3(A,B,C) NS_##A##B##C
13299 #define S4(A,B,C,D) NS_##A##B##C##D
13301 #define X(N, L, C) S##N L
13314 enum neon_shape_class
13323 #define X(N, L, C) SC_##C
13325 static enum neon_shape_class neon_shape_class
[] =
13344 /* Register widths of above. */
13345 static unsigned neon_shape_el_size
[] =
13357 struct neon_shape_info
13360 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13363 #define S2(A,B) { SE_##A, SE_##B }
13364 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13365 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13367 #define X(N, L, C) { N, S##N L }
13369 static struct neon_shape_info neon_shape_tab
[] =
13379 /* Bit masks used in type checking given instructions.
13380 'N_EQK' means the type must be the same as (or based on in some way) the key
13381 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13382 set, various other bits can be set as well in order to modify the meaning of
13383 the type constraint. */
13385 enum neon_type_mask
13409 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13410 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13411 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13412 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13413 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13414 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13415 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13416 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13417 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13418 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13419 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13421 N_MAX_NONSPECIAL
= N_P64
13424 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13426 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13427 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13428 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13429 #define N_SUF_32 (N_SU_32 | N_F32)
13430 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13431 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13432 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13434 /* Pass this as the first type argument to neon_check_type to ignore types
13436 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13438 /* Select a "shape" for the current instruction (describing register types or
13439 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13440 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13441 function of operand parsing, so this function doesn't need to be called.
13442 Shapes should be listed in order of decreasing length. */
13444 static enum neon_shape
13445 neon_select_shape (enum neon_shape shape
, ...)
13448 enum neon_shape first_shape
= shape
;
13450 /* Fix missing optional operands. FIXME: we don't know at this point how
13451 many arguments we should have, so this makes the assumption that we have
13452 > 1. This is true of all current Neon opcodes, I think, but may not be
13453 true in the future. */
13454 if (!inst
.operands
[1].present
)
13455 inst
.operands
[1] = inst
.operands
[0];
13457 va_start (ap
, shape
);
13459 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13464 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13466 if (!inst
.operands
[j
].present
)
13472 switch (neon_shape_tab
[shape
].el
[j
])
13474 /* If a .f16, .16, .u16, .s16 type specifier is given over
13475 a VFP single precision register operand, it's essentially
13476 means only half of the register is used.
13478 If the type specifier is given after the mnemonics, the
13479 information is stored in inst.vectype. If the type specifier
13480 is given after register operand, the information is stored
13481 in inst.operands[].vectype.
13483 When there is only one type specifier, and all the register
13484 operands are the same type of hardware register, the type
13485 specifier applies to all register operands.
13487 If no type specifier is given, the shape is inferred from
13488 operand information.
13491 vadd.f16 s0, s1, s2: NS_HHH
13492 vabs.f16 s0, s1: NS_HH
13493 vmov.f16 s0, r1: NS_HR
13494 vmov.f16 r0, s1: NS_RH
13495 vcvt.f16 r0, s1: NS_RH
13496 vcvt.f16.s32 s2, s2, #29: NS_HFI
13497 vcvt.f16.s32 s2, s2: NS_HF
13500 if (!(inst
.operands
[j
].isreg
13501 && inst
.operands
[j
].isvec
13502 && inst
.operands
[j
].issingle
13503 && !inst
.operands
[j
].isquad
13504 && ((inst
.vectype
.elems
== 1
13505 && inst
.vectype
.el
[0].size
== 16)
13506 || (inst
.vectype
.elems
> 1
13507 && inst
.vectype
.el
[j
].size
== 16)
13508 || (inst
.vectype
.elems
== 0
13509 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13510 && inst
.operands
[j
].vectype
.size
== 16))))
13515 if (!(inst
.operands
[j
].isreg
13516 && inst
.operands
[j
].isvec
13517 && inst
.operands
[j
].issingle
13518 && !inst
.operands
[j
].isquad
13519 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13520 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13521 || (inst
.vectype
.elems
== 0
13522 && (inst
.operands
[j
].vectype
.size
== 32
13523 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13528 if (!(inst
.operands
[j
].isreg
13529 && inst
.operands
[j
].isvec
13530 && !inst
.operands
[j
].isquad
13531 && !inst
.operands
[j
].issingle
))
13536 if (!(inst
.operands
[j
].isreg
13537 && !inst
.operands
[j
].isvec
))
13542 if (!(inst
.operands
[j
].isreg
13543 && inst
.operands
[j
].isvec
13544 && inst
.operands
[j
].isquad
13545 && !inst
.operands
[j
].issingle
))
13550 if (!(!inst
.operands
[j
].isreg
13551 && !inst
.operands
[j
].isscalar
))
13556 if (!(!inst
.operands
[j
].isreg
13557 && inst
.operands
[j
].isscalar
))
13567 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13568 /* We've matched all the entries in the shape table, and we don't
13569 have any left over operands which have not been matched. */
13575 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13576 first_error (_("invalid instruction shape"));
13581 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13582 means the Q bit should be set). */
13585 neon_quad (enum neon_shape shape
)
13587 return neon_shape_class
[shape
] == SC_QUAD
;
13591 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13594 /* Allow modification to be made to types which are constrained to be
13595 based on the key element, based on bits set alongside N_EQK. */
13596 if ((typebits
& N_EQK
) != 0)
13598 if ((typebits
& N_HLF
) != 0)
13600 else if ((typebits
& N_DBL
) != 0)
13602 if ((typebits
& N_SGN
) != 0)
13603 *g_type
= NT_signed
;
13604 else if ((typebits
& N_UNS
) != 0)
13605 *g_type
= NT_unsigned
;
13606 else if ((typebits
& N_INT
) != 0)
13607 *g_type
= NT_integer
;
13608 else if ((typebits
& N_FLT
) != 0)
13609 *g_type
= NT_float
;
13610 else if ((typebits
& N_SIZ
) != 0)
13611 *g_type
= NT_untyped
;
13615 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13616 operand type, i.e. the single type specified in a Neon instruction when it
13617 is the only one given. */
13619 static struct neon_type_el
13620 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13622 struct neon_type_el dest
= *key
;
13624 gas_assert ((thisarg
& N_EQK
) != 0);
13626 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13631 /* Convert Neon type and size into compact bitmask representation. */
13633 static enum neon_type_mask
13634 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13641 case 8: return N_8
;
13642 case 16: return N_16
;
13643 case 32: return N_32
;
13644 case 64: return N_64
;
13652 case 8: return N_I8
;
13653 case 16: return N_I16
;
13654 case 32: return N_I32
;
13655 case 64: return N_I64
;
13663 case 16: return N_F16
;
13664 case 32: return N_F32
;
13665 case 64: return N_F64
;
13673 case 8: return N_P8
;
13674 case 16: return N_P16
;
13675 case 64: return N_P64
;
13683 case 8: return N_S8
;
13684 case 16: return N_S16
;
13685 case 32: return N_S32
;
13686 case 64: return N_S64
;
13694 case 8: return N_U8
;
13695 case 16: return N_U16
;
13696 case 32: return N_U32
;
13697 case 64: return N_U64
;
13708 /* Convert compact Neon bitmask type representation to a type and size. Only
13709 handles the case where a single bit is set in the mask. */
13712 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13713 enum neon_type_mask mask
)
13715 if ((mask
& N_EQK
) != 0)
13718 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13720 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13722 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13724 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13729 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13731 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13732 *type
= NT_unsigned
;
13733 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13734 *type
= NT_integer
;
13735 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13736 *type
= NT_untyped
;
13737 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13739 else if ((mask
& (N_F_ALL
)) != 0)
13747 /* Modify a bitmask of allowed types. This is only needed for type
13751 modify_types_allowed (unsigned allowed
, unsigned mods
)
13754 enum neon_el_type type
;
13760 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13762 if (el_type_of_type_chk (&type
, &size
,
13763 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13765 neon_modify_type_size (mods
, &type
, &size
);
13766 destmask
|= type_chk_of_el_type (type
, size
);
13773 /* Check type and return type classification.
13774 The manual states (paraphrase): If one datatype is given, it indicates the
13776 - the second operand, if there is one
13777 - the operand, if there is no second operand
13778 - the result, if there are no operands.
13779 This isn't quite good enough though, so we use a concept of a "key" datatype
13780 which is set on a per-instruction basis, which is the one which matters when
13781 only one data type is written.
13782 Note: this function has side-effects (e.g. filling in missing operands). All
13783 Neon instructions should call it before performing bit encoding. */
13785 static struct neon_type_el
13786 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13789 unsigned i
, pass
, key_el
= 0;
13790 unsigned types
[NEON_MAX_TYPE_ELS
];
13791 enum neon_el_type k_type
= NT_invtype
;
13792 unsigned k_size
= -1u;
13793 struct neon_type_el badtype
= {NT_invtype
, -1};
13794 unsigned key_allowed
= 0;
13796 /* Optional registers in Neon instructions are always (not) in operand 1.
13797 Fill in the missing operand here, if it was omitted. */
13798 if (els
> 1 && !inst
.operands
[1].present
)
13799 inst
.operands
[1] = inst
.operands
[0];
13801 /* Suck up all the varargs. */
13803 for (i
= 0; i
< els
; i
++)
13805 unsigned thisarg
= va_arg (ap
, unsigned);
13806 if (thisarg
== N_IGNORE_TYPE
)
13811 types
[i
] = thisarg
;
13812 if ((thisarg
& N_KEY
) != 0)
13817 if (inst
.vectype
.elems
> 0)
13818 for (i
= 0; i
< els
; i
++)
13819 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13821 first_error (_("types specified in both the mnemonic and operands"));
13825 /* Duplicate inst.vectype elements here as necessary.
13826 FIXME: No idea if this is exactly the same as the ARM assembler,
13827 particularly when an insn takes one register and one non-register
13829 if (inst
.vectype
.elems
== 1 && els
> 1)
13832 inst
.vectype
.elems
= els
;
13833 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13834 for (j
= 0; j
< els
; j
++)
13836 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13839 else if (inst
.vectype
.elems
== 0 && els
> 0)
13842 /* No types were given after the mnemonic, so look for types specified
13843 after each operand. We allow some flexibility here; as long as the
13844 "key" operand has a type, we can infer the others. */
13845 for (j
= 0; j
< els
; j
++)
13846 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13847 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13849 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13851 for (j
= 0; j
< els
; j
++)
13852 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13853 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13858 first_error (_("operand types can't be inferred"));
13862 else if (inst
.vectype
.elems
!= els
)
13864 first_error (_("type specifier has the wrong number of parts"));
13868 for (pass
= 0; pass
< 2; pass
++)
13870 for (i
= 0; i
< els
; i
++)
13872 unsigned thisarg
= types
[i
];
13873 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13874 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13875 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13876 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13878 /* Decay more-specific signed & unsigned types to sign-insensitive
13879 integer types if sign-specific variants are unavailable. */
13880 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13881 && (types_allowed
& N_SU_ALL
) == 0)
13882 g_type
= NT_integer
;
13884 /* If only untyped args are allowed, decay any more specific types to
13885 them. Some instructions only care about signs for some element
13886 sizes, so handle that properly. */
13887 if (((types_allowed
& N_UNT
) == 0)
13888 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13889 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13890 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13891 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13892 g_type
= NT_untyped
;
13896 if ((thisarg
& N_KEY
) != 0)
13900 key_allowed
= thisarg
& ~N_KEY
;
13905 if ((thisarg
& N_VFP
) != 0)
13907 enum neon_shape_el regshape
;
13908 unsigned regwidth
, match
;
13910 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13913 first_error (_("invalid instruction shape"));
13916 regshape
= neon_shape_tab
[ns
].el
[i
];
13917 regwidth
= neon_shape_el_size
[regshape
];
13919 /* In VFP mode, operands must match register widths. If we
13920 have a key operand, use its width, else use the width of
13921 the current operand. */
13927 /* FP16 will use a single precision register. */
13928 if (regwidth
== 32 && match
== 16)
13930 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13934 inst
.error
= _(BAD_FP16
);
13939 if (regwidth
!= match
)
13941 first_error (_("operand size must match register width"));
13946 if ((thisarg
& N_EQK
) == 0)
13948 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13950 if ((given_type
& types_allowed
) == 0)
13952 first_error (_("bad type in Neon instruction"));
13958 enum neon_el_type mod_k_type
= k_type
;
13959 unsigned mod_k_size
= k_size
;
13960 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13961 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13963 first_error (_("inconsistent types in Neon instruction"));
13971 return inst
.vectype
.el
[key_el
];
13974 /* Neon-style VFP instruction forwarding. */
13976 /* Thumb VFP instructions have 0xE in the condition field. */
13979 do_vfp_cond_or_thumb (void)
13984 inst
.instruction
|= 0xe0000000;
13986 inst
.instruction
|= inst
.cond
<< 28;
13989 /* Look up and encode a simple mnemonic, for use as a helper function for the
13990 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13991 etc. It is assumed that operand parsing has already been done, and that the
13992 operands are in the form expected by the given opcode (this isn't necessarily
13993 the same as the form in which they were parsed, hence some massaging must
13994 take place before this function is called).
13995 Checks current arch version against that in the looked-up opcode. */
13998 do_vfp_nsyn_opcode (const char *opname
)
14000 const struct asm_opcode
*opcode
;
14002 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14007 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14008 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14015 inst
.instruction
= opcode
->tvalue
;
14016 opcode
->tencode ();
14020 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14021 opcode
->aencode ();
14026 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14028 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14030 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14033 do_vfp_nsyn_opcode ("fadds");
14035 do_vfp_nsyn_opcode ("fsubs");
14037 /* ARMv8.2 fp16 instruction. */
14039 do_scalar_fp16_v82_encode ();
14044 do_vfp_nsyn_opcode ("faddd");
14046 do_vfp_nsyn_opcode ("fsubd");
14050 /* Check operand types to see if this is a VFP instruction, and if so call
14054 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14056 enum neon_shape rs
;
14057 struct neon_type_el et
;
14062 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14063 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14067 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14068 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14069 N_F_ALL
| N_KEY
| N_VFP
);
14076 if (et
.type
!= NT_invtype
)
14087 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14089 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14091 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14094 do_vfp_nsyn_opcode ("fmacs");
14096 do_vfp_nsyn_opcode ("fnmacs");
14098 /* ARMv8.2 fp16 instruction. */
14100 do_scalar_fp16_v82_encode ();
14105 do_vfp_nsyn_opcode ("fmacd");
14107 do_vfp_nsyn_opcode ("fnmacd");
14112 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14114 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14116 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14119 do_vfp_nsyn_opcode ("ffmas");
14121 do_vfp_nsyn_opcode ("ffnmas");
14123 /* ARMv8.2 fp16 instruction. */
14125 do_scalar_fp16_v82_encode ();
14130 do_vfp_nsyn_opcode ("ffmad");
14132 do_vfp_nsyn_opcode ("ffnmad");
14137 do_vfp_nsyn_mul (enum neon_shape rs
)
14139 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14141 do_vfp_nsyn_opcode ("fmuls");
14143 /* ARMv8.2 fp16 instruction. */
14145 do_scalar_fp16_v82_encode ();
14148 do_vfp_nsyn_opcode ("fmuld");
14152 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14154 int is_neg
= (inst
.instruction
& 0x80) != 0;
14155 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14157 if (rs
== NS_FF
|| rs
== NS_HH
)
14160 do_vfp_nsyn_opcode ("fnegs");
14162 do_vfp_nsyn_opcode ("fabss");
14164 /* ARMv8.2 fp16 instruction. */
14166 do_scalar_fp16_v82_encode ();
14171 do_vfp_nsyn_opcode ("fnegd");
14173 do_vfp_nsyn_opcode ("fabsd");
14177 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14178 insns belong to Neon, and are handled elsewhere. */
14181 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14183 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14187 do_vfp_nsyn_opcode ("fldmdbs");
14189 do_vfp_nsyn_opcode ("fldmias");
14194 do_vfp_nsyn_opcode ("fstmdbs");
14196 do_vfp_nsyn_opcode ("fstmias");
14201 do_vfp_nsyn_sqrt (void)
14203 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14204 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14206 if (rs
== NS_FF
|| rs
== NS_HH
)
14208 do_vfp_nsyn_opcode ("fsqrts");
14210 /* ARMv8.2 fp16 instruction. */
14212 do_scalar_fp16_v82_encode ();
14215 do_vfp_nsyn_opcode ("fsqrtd");
14219 do_vfp_nsyn_div (void)
14221 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14222 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14223 N_F_ALL
| N_KEY
| N_VFP
);
14225 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14227 do_vfp_nsyn_opcode ("fdivs");
14229 /* ARMv8.2 fp16 instruction. */
14231 do_scalar_fp16_v82_encode ();
14234 do_vfp_nsyn_opcode ("fdivd");
14238 do_vfp_nsyn_nmul (void)
14240 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14241 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14242 N_F_ALL
| N_KEY
| N_VFP
);
14244 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14246 NEON_ENCODE (SINGLE
, inst
);
14247 do_vfp_sp_dyadic ();
14249 /* ARMv8.2 fp16 instruction. */
14251 do_scalar_fp16_v82_encode ();
14255 NEON_ENCODE (DOUBLE
, inst
);
14256 do_vfp_dp_rd_rn_rm ();
14258 do_vfp_cond_or_thumb ();
14263 do_vfp_nsyn_cmp (void)
14265 enum neon_shape rs
;
14266 if (inst
.operands
[1].isreg
)
14268 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14269 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14271 if (rs
== NS_FF
|| rs
== NS_HH
)
14273 NEON_ENCODE (SINGLE
, inst
);
14274 do_vfp_sp_monadic ();
14278 NEON_ENCODE (DOUBLE
, inst
);
14279 do_vfp_dp_rd_rm ();
14284 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14285 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14287 switch (inst
.instruction
& 0x0fffffff)
14290 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14293 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14299 if (rs
== NS_FI
|| rs
== NS_HI
)
14301 NEON_ENCODE (SINGLE
, inst
);
14302 do_vfp_sp_compare_z ();
14306 NEON_ENCODE (DOUBLE
, inst
);
14310 do_vfp_cond_or_thumb ();
14312 /* ARMv8.2 fp16 instruction. */
14313 if (rs
== NS_HI
|| rs
== NS_HH
)
14314 do_scalar_fp16_v82_encode ();
14318 nsyn_insert_sp (void)
14320 inst
.operands
[1] = inst
.operands
[0];
14321 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14322 inst
.operands
[0].reg
= REG_SP
;
14323 inst
.operands
[0].isreg
= 1;
14324 inst
.operands
[0].writeback
= 1;
14325 inst
.operands
[0].present
= 1;
14329 do_vfp_nsyn_push (void)
14332 if (inst
.operands
[1].issingle
)
14333 do_vfp_nsyn_opcode ("fstmdbs");
14335 do_vfp_nsyn_opcode ("fstmdbd");
14339 do_vfp_nsyn_pop (void)
14342 if (inst
.operands
[1].issingle
)
14343 do_vfp_nsyn_opcode ("fldmias");
14345 do_vfp_nsyn_opcode ("fldmiad");
14348 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14349 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14352 neon_dp_fixup (struct arm_it
* insn
)
14354 unsigned int i
= insn
->instruction
;
14359 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14370 insn
->instruction
= i
;
14373 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14377 neon_logbits (unsigned x
)
14379 return ffs (x
) - 4;
14382 #define LOW4(R) ((R) & 0xf)
14383 #define HI1(R) (((R) >> 4) & 1)
14385 /* Encode insns with bit pattern:
14387 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14388 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14390 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14391 different meaning for some instruction. */
14394 neon_three_same (int isquad
, int ubit
, int size
)
14396 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14397 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14398 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14399 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14400 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14401 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14402 inst
.instruction
|= (isquad
!= 0) << 6;
14403 inst
.instruction
|= (ubit
!= 0) << 24;
14405 inst
.instruction
|= neon_logbits (size
) << 20;
14407 neon_dp_fixup (&inst
);
14410 /* Encode instructions of the form:
14412 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14413 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14415 Don't write size if SIZE == -1. */
14418 neon_two_same (int qbit
, int ubit
, int size
)
14420 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14421 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14422 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14423 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14424 inst
.instruction
|= (qbit
!= 0) << 6;
14425 inst
.instruction
|= (ubit
!= 0) << 24;
14428 inst
.instruction
|= neon_logbits (size
) << 18;
14430 neon_dp_fixup (&inst
);
14433 /* Neon instruction encoders, in approximate order of appearance. */
14436 do_neon_dyadic_i_su (void)
14438 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14439 struct neon_type_el et
= neon_check_type (3, rs
,
14440 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14441 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14445 do_neon_dyadic_i64_su (void)
14447 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14448 struct neon_type_el et
= neon_check_type (3, rs
,
14449 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14450 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14454 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14457 unsigned size
= et
.size
>> 3;
14458 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14459 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14460 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14461 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14462 inst
.instruction
|= (isquad
!= 0) << 6;
14463 inst
.instruction
|= immbits
<< 16;
14464 inst
.instruction
|= (size
>> 3) << 7;
14465 inst
.instruction
|= (size
& 0x7) << 19;
14467 inst
.instruction
|= (uval
!= 0) << 24;
14469 neon_dp_fixup (&inst
);
14473 do_neon_shl_imm (void)
14475 if (!inst
.operands
[2].isreg
)
14477 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14478 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14479 int imm
= inst
.operands
[2].imm
;
14481 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14482 _("immediate out of range for shift"));
14483 NEON_ENCODE (IMMED
, inst
);
14484 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14488 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14489 struct neon_type_el et
= neon_check_type (3, rs
,
14490 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14493 /* VSHL/VQSHL 3-register variants have syntax such as:
14495 whereas other 3-register operations encoded by neon_three_same have
14498 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14500 tmp
= inst
.operands
[2].reg
;
14501 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14502 inst
.operands
[1].reg
= tmp
;
14503 NEON_ENCODE (INTEGER
, inst
);
14504 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14509 do_neon_qshl_imm (void)
14511 if (!inst
.operands
[2].isreg
)
14513 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14514 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14515 int imm
= inst
.operands
[2].imm
;
14517 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14518 _("immediate out of range for shift"));
14519 NEON_ENCODE (IMMED
, inst
);
14520 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14524 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14525 struct neon_type_el et
= neon_check_type (3, rs
,
14526 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14529 /* See note in do_neon_shl_imm. */
14530 tmp
= inst
.operands
[2].reg
;
14531 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14532 inst
.operands
[1].reg
= tmp
;
14533 NEON_ENCODE (INTEGER
, inst
);
14534 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14539 do_neon_rshl (void)
14541 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14542 struct neon_type_el et
= neon_check_type (3, rs
,
14543 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14546 tmp
= inst
.operands
[2].reg
;
14547 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14548 inst
.operands
[1].reg
= tmp
;
14549 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14553 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14555 /* Handle .I8 pseudo-instructions. */
14558 /* Unfortunately, this will make everything apart from zero out-of-range.
14559 FIXME is this the intended semantics? There doesn't seem much point in
14560 accepting .I8 if so. */
14561 immediate
|= immediate
<< 8;
14567 if (immediate
== (immediate
& 0x000000ff))
14569 *immbits
= immediate
;
14572 else if (immediate
== (immediate
& 0x0000ff00))
14574 *immbits
= immediate
>> 8;
14577 else if (immediate
== (immediate
& 0x00ff0000))
14579 *immbits
= immediate
>> 16;
14582 else if (immediate
== (immediate
& 0xff000000))
14584 *immbits
= immediate
>> 24;
14587 if ((immediate
& 0xffff) != (immediate
>> 16))
14588 goto bad_immediate
;
14589 immediate
&= 0xffff;
14592 if (immediate
== (immediate
& 0x000000ff))
14594 *immbits
= immediate
;
14597 else if (immediate
== (immediate
& 0x0000ff00))
14599 *immbits
= immediate
>> 8;
14604 first_error (_("immediate value out of range"));
14609 do_neon_logic (void)
14611 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14613 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14614 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14615 /* U bit and size field were set as part of the bitmask. */
14616 NEON_ENCODE (INTEGER
, inst
);
14617 neon_three_same (neon_quad (rs
), 0, -1);
14621 const int three_ops_form
= (inst
.operands
[2].present
14622 && !inst
.operands
[2].isreg
);
14623 const int immoperand
= (three_ops_form
? 2 : 1);
14624 enum neon_shape rs
= (three_ops_form
14625 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14626 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14627 struct neon_type_el et
= neon_check_type (2, rs
,
14628 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14629 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14633 if (et
.type
== NT_invtype
)
14636 if (three_ops_form
)
14637 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14638 _("first and second operands shall be the same register"));
14640 NEON_ENCODE (IMMED
, inst
);
14642 immbits
= inst
.operands
[immoperand
].imm
;
14645 /* .i64 is a pseudo-op, so the immediate must be a repeating
14647 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14648 inst
.operands
[immoperand
].reg
: 0))
14650 /* Set immbits to an invalid constant. */
14651 immbits
= 0xdeadbeef;
14658 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14662 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14666 /* Pseudo-instruction for VBIC. */
14667 neon_invert_size (&immbits
, 0, et
.size
);
14668 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14672 /* Pseudo-instruction for VORR. */
14673 neon_invert_size (&immbits
, 0, et
.size
);
14674 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14684 inst
.instruction
|= neon_quad (rs
) << 6;
14685 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14686 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14687 inst
.instruction
|= cmode
<< 8;
14688 neon_write_immbits (immbits
);
14690 neon_dp_fixup (&inst
);
14695 do_neon_bitfield (void)
14697 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14698 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14699 neon_three_same (neon_quad (rs
), 0, -1);
14703 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14706 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14707 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14709 if (et
.type
== NT_float
)
14711 NEON_ENCODE (FLOAT
, inst
);
14712 neon_three_same (neon_quad (rs
), 0, -1);
14716 NEON_ENCODE (INTEGER
, inst
);
14717 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14722 do_neon_dyadic_if_su (void)
14724 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14728 do_neon_dyadic_if_su_d (void)
14730 /* This version only allow D registers, but that constraint is enforced during
14731 operand parsing so we don't need to do anything extra here. */
14732 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14736 do_neon_dyadic_if_i_d (void)
14738 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14739 affected if we specify unsigned args. */
14740 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14743 enum vfp_or_neon_is_neon_bits
14746 NEON_CHECK_ARCH
= 2,
14747 NEON_CHECK_ARCH8
= 4
14750 /* Call this function if an instruction which may have belonged to the VFP or
14751 Neon instruction sets, but turned out to be a Neon instruction (due to the
14752 operand types involved, etc.). We have to check and/or fix-up a couple of
14755 - Make sure the user hasn't attempted to make a Neon instruction
14757 - Alter the value in the condition code field if necessary.
14758 - Make sure that the arch supports Neon instructions.
14760 Which of these operations take place depends on bits from enum
14761 vfp_or_neon_is_neon_bits.
14763 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14764 current instruction's condition is COND_ALWAYS, the condition field is
14765 changed to inst.uncond_value. This is necessary because instructions shared
14766 between VFP and Neon may be conditional for the VFP variants only, and the
14767 unconditional Neon version must have, e.g., 0xF in the condition field. */
14770 vfp_or_neon_is_neon (unsigned check
)
14772 /* Conditions are always legal in Thumb mode (IT blocks). */
14773 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14775 if (inst
.cond
!= COND_ALWAYS
)
14777 first_error (_(BAD_COND
));
14780 if (inst
.uncond_value
!= -1)
14781 inst
.instruction
|= inst
.uncond_value
<< 28;
14784 if ((check
& NEON_CHECK_ARCH
)
14785 && !mark_feature_used (&fpu_neon_ext_v1
))
14787 first_error (_(BAD_FPU
));
14791 if ((check
& NEON_CHECK_ARCH8
)
14792 && !mark_feature_used (&fpu_neon_ext_armv8
))
14794 first_error (_(BAD_FPU
));
14802 do_neon_addsub_if_i (void)
14804 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14807 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14810 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14811 affected if we specify unsigned args. */
14812 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14815 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14817 V<op> A,B (A is operand 0, B is operand 2)
14822 so handle that case specially. */
14825 neon_exchange_operands (void)
14827 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14828 if (inst
.operands
[1].present
)
14830 /* Swap operands[1] and operands[2]. */
14831 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14832 inst
.operands
[1] = inst
.operands
[2];
14833 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14837 inst
.operands
[1] = inst
.operands
[2];
14838 inst
.operands
[2] = inst
.operands
[0];
14843 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14845 if (inst
.operands
[2].isreg
)
14848 neon_exchange_operands ();
14849 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14853 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14854 struct neon_type_el et
= neon_check_type (2, rs
,
14855 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14857 NEON_ENCODE (IMMED
, inst
);
14858 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14859 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14860 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14861 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14862 inst
.instruction
|= neon_quad (rs
) << 6;
14863 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14864 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14866 neon_dp_fixup (&inst
);
14873 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14877 do_neon_cmp_inv (void)
14879 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14885 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14888 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14889 scalars, which are encoded in 5 bits, M : Rm.
14890 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14891 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14895 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14897 unsigned regno
= NEON_SCALAR_REG (scalar
);
14898 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14903 if (regno
> 7 || elno
> 3)
14905 return regno
| (elno
<< 3);
14908 if (regno
> 15 || elno
> 1)
14910 return regno
| (elno
<< 4);
14914 first_error (_("scalar out of range for multiply instruction"));
14920 /* Encode multiply / multiply-accumulate scalar instructions. */
14923 neon_mul_mac (struct neon_type_el et
, int ubit
)
14927 /* Give a more helpful error message if we have an invalid type. */
14928 if (et
.type
== NT_invtype
)
14931 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14932 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14933 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14934 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14935 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14936 inst
.instruction
|= LOW4 (scalar
);
14937 inst
.instruction
|= HI1 (scalar
) << 5;
14938 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14939 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14940 inst
.instruction
|= (ubit
!= 0) << 24;
14942 neon_dp_fixup (&inst
);
14946 do_neon_mac_maybe_scalar (void)
14948 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14951 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14954 if (inst
.operands
[2].isscalar
)
14956 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14957 struct neon_type_el et
= neon_check_type (3, rs
,
14958 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14959 NEON_ENCODE (SCALAR
, inst
);
14960 neon_mul_mac (et
, neon_quad (rs
));
14964 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14965 affected if we specify unsigned args. */
14966 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14971 do_neon_fmac (void)
14973 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14976 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14979 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14985 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14986 struct neon_type_el et
= neon_check_type (3, rs
,
14987 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14988 neon_three_same (neon_quad (rs
), 0, et
.size
);
14991 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14992 same types as the MAC equivalents. The polynomial type for this instruction
14993 is encoded the same as the integer type. */
14998 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15001 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15004 if (inst
.operands
[2].isscalar
)
15005 do_neon_mac_maybe_scalar ();
15007 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
15011 do_neon_qdmulh (void)
15013 if (inst
.operands
[2].isscalar
)
15015 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15016 struct neon_type_el et
= neon_check_type (3, rs
,
15017 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15018 NEON_ENCODE (SCALAR
, inst
);
15019 neon_mul_mac (et
, neon_quad (rs
));
15023 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15024 struct neon_type_el et
= neon_check_type (3, rs
,
15025 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15026 NEON_ENCODE (INTEGER
, inst
);
15027 /* The U bit (rounding) comes from bit mask. */
15028 neon_three_same (neon_quad (rs
), 0, et
.size
);
15033 do_neon_qrdmlah (void)
15035 /* Check we're on the correct architecture. */
15036 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15038 _("instruction form not available on this architecture.");
15039 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15041 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15042 record_feature_use (&fpu_neon_ext_v8_1
);
15045 if (inst
.operands
[2].isscalar
)
15047 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15048 struct neon_type_el et
= neon_check_type (3, rs
,
15049 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15050 NEON_ENCODE (SCALAR
, inst
);
15051 neon_mul_mac (et
, neon_quad (rs
));
15055 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15056 struct neon_type_el et
= neon_check_type (3, rs
,
15057 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15058 NEON_ENCODE (INTEGER
, inst
);
15059 /* The U bit (rounding) comes from bit mask. */
15060 neon_three_same (neon_quad (rs
), 0, et
.size
);
15065 do_neon_fcmp_absolute (void)
15067 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15068 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
15069 /* Size field comes from bit mask. */
15070 neon_three_same (neon_quad (rs
), 1, -1);
15074 do_neon_fcmp_absolute_inv (void)
15076 neon_exchange_operands ();
15077 do_neon_fcmp_absolute ();
15081 do_neon_step (void)
15083 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15084 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
15085 neon_three_same (neon_quad (rs
), 0, -1);
15089 do_neon_abs_neg (void)
15091 enum neon_shape rs
;
15092 struct neon_type_el et
;
15094 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15097 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15100 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15101 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
15103 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15104 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15105 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15106 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15107 inst
.instruction
|= neon_quad (rs
) << 6;
15108 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15109 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15111 neon_dp_fixup (&inst
);
15117 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15118 struct neon_type_el et
= neon_check_type (2, rs
,
15119 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15120 int imm
= inst
.operands
[2].imm
;
15121 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15122 _("immediate out of range for insert"));
15123 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15129 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15130 struct neon_type_el et
= neon_check_type (2, rs
,
15131 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15132 int imm
= inst
.operands
[2].imm
;
15133 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15134 _("immediate out of range for insert"));
15135 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15139 do_neon_qshlu_imm (void)
15141 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15142 struct neon_type_el et
= neon_check_type (2, rs
,
15143 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15144 int imm
= inst
.operands
[2].imm
;
15145 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15146 _("immediate out of range for shift"));
15147 /* Only encodes the 'U present' variant of the instruction.
15148 In this case, signed types have OP (bit 8) set to 0.
15149 Unsigned types have OP set to 1. */
15150 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15151 /* The rest of the bits are the same as other immediate shifts. */
15152 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15156 do_neon_qmovn (void)
15158 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15159 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15160 /* Saturating move where operands can be signed or unsigned, and the
15161 destination has the same signedness. */
15162 NEON_ENCODE (INTEGER
, inst
);
15163 if (et
.type
== NT_unsigned
)
15164 inst
.instruction
|= 0xc0;
15166 inst
.instruction
|= 0x80;
15167 neon_two_same (0, 1, et
.size
/ 2);
15171 do_neon_qmovun (void)
15173 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15174 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15175 /* Saturating move with unsigned results. Operands must be signed. */
15176 NEON_ENCODE (INTEGER
, inst
);
15177 neon_two_same (0, 1, et
.size
/ 2);
15181 do_neon_rshift_sat_narrow (void)
15183 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15184 or unsigned. If operands are unsigned, results must also be unsigned. */
15185 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15186 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15187 int imm
= inst
.operands
[2].imm
;
15188 /* This gets the bounds check, size encoding and immediate bits calculation
15192 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15193 VQMOVN.I<size> <Dd>, <Qm>. */
15196 inst
.operands
[2].present
= 0;
15197 inst
.instruction
= N_MNEM_vqmovn
;
15202 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15203 _("immediate out of range"));
15204 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15208 do_neon_rshift_sat_narrow_u (void)
15210 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15211 or unsigned. If operands are unsigned, results must also be unsigned. */
15212 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15213 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15214 int imm
= inst
.operands
[2].imm
;
15215 /* This gets the bounds check, size encoding and immediate bits calculation
15219 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15220 VQMOVUN.I<size> <Dd>, <Qm>. */
15223 inst
.operands
[2].present
= 0;
15224 inst
.instruction
= N_MNEM_vqmovun
;
15229 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15230 _("immediate out of range"));
15231 /* FIXME: The manual is kind of unclear about what value U should have in
15232 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15234 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15238 do_neon_movn (void)
15240 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15241 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15242 NEON_ENCODE (INTEGER
, inst
);
15243 neon_two_same (0, 1, et
.size
/ 2);
15247 do_neon_rshift_narrow (void)
15249 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15250 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15251 int imm
= inst
.operands
[2].imm
;
15252 /* This gets the bounds check, size encoding and immediate bits calculation
15256 /* If immediate is zero then we are a pseudo-instruction for
15257 VMOVN.I<size> <Dd>, <Qm> */
15260 inst
.operands
[2].present
= 0;
15261 inst
.instruction
= N_MNEM_vmovn
;
15266 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15267 _("immediate out of range for narrowing operation"));
15268 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15272 do_neon_shll (void)
15274 /* FIXME: Type checking when lengthening. */
15275 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15276 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15277 unsigned imm
= inst
.operands
[2].imm
;
15279 if (imm
== et
.size
)
15281 /* Maximum shift variant. */
15282 NEON_ENCODE (INTEGER
, inst
);
15283 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15284 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15285 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15286 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15287 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15289 neon_dp_fixup (&inst
);
15293 /* A more-specific type check for non-max versions. */
15294 et
= neon_check_type (2, NS_QDI
,
15295 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15296 NEON_ENCODE (IMMED
, inst
);
15297 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15301 /* Check the various types for the VCVT instruction, and return which version
15302 the current instruction is. */
15304 #define CVT_FLAVOUR_VAR \
15305 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15306 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15307 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15308 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15309 /* Half-precision conversions. */ \
15310 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15311 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15312 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15313 Compared with single/double precision variants, only the co-processor \
15314 field is different, so the encoding flow is reused here. */ \
15315 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15316 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15317 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15318 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15319 /* VFP instructions. */ \
15320 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15321 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15322 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15323 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15324 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15325 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15326 /* VFP instructions with bitshift. */ \
15327 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15328 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15329 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15330 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15331 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15332 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15333 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15334 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15336 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15337 neon_cvt_flavour_##C,
15339 /* The different types of conversions we can do. */
15340 enum neon_cvt_flavour
15343 neon_cvt_flavour_invalid
,
15344 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15349 static enum neon_cvt_flavour
15350 get_neon_cvt_flavour (enum neon_shape rs
)
15352 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15353 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15354 if (et.type != NT_invtype) \
15356 inst.error = NULL; \
15357 return (neon_cvt_flavour_##C); \
15360 struct neon_type_el et
;
15361 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15362 || rs
== NS_FF
) ? N_VFP
: 0;
15363 /* The instruction versions which take an immediate take one register
15364 argument, which is extended to the width of the full register. Thus the
15365 "source" and "destination" registers must have the same width. Hack that
15366 here by making the size equal to the key (wider, in this case) operand. */
15367 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15371 return neon_cvt_flavour_invalid
;
15386 /* Neon-syntax VFP conversions. */
15389 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15391 const char *opname
= 0;
15393 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15394 || rs
== NS_FHI
|| rs
== NS_HFI
)
15396 /* Conversions with immediate bitshift. */
15397 const char *enc
[] =
15399 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15405 if (flavour
< (int) ARRAY_SIZE (enc
))
15407 opname
= enc
[flavour
];
15408 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15409 _("operands 0 and 1 must be the same register"));
15410 inst
.operands
[1] = inst
.operands
[2];
15411 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15416 /* Conversions without bitshift. */
15417 const char *enc
[] =
15419 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15425 if (flavour
< (int) ARRAY_SIZE (enc
))
15426 opname
= enc
[flavour
];
15430 do_vfp_nsyn_opcode (opname
);
15432 /* ARMv8.2 fp16 VCVT instruction. */
15433 if (flavour
== neon_cvt_flavour_s32_f16
15434 || flavour
== neon_cvt_flavour_u32_f16
15435 || flavour
== neon_cvt_flavour_f16_u32
15436 || flavour
== neon_cvt_flavour_f16_s32
)
15437 do_scalar_fp16_v82_encode ();
15441 do_vfp_nsyn_cvtz (void)
15443 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15444 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15445 const char *enc
[] =
15447 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15453 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15454 do_vfp_nsyn_opcode (enc
[flavour
]);
15458 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15459 enum neon_cvt_mode mode
)
15464 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15465 D register operands. */
15466 if (flavour
== neon_cvt_flavour_s32_f64
15467 || flavour
== neon_cvt_flavour_u32_f64
)
15468 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15471 if (flavour
== neon_cvt_flavour_s32_f16
15472 || flavour
== neon_cvt_flavour_u32_f16
)
15473 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15476 set_it_insn_type (OUTSIDE_IT_INSN
);
15480 case neon_cvt_flavour_s32_f64
:
15484 case neon_cvt_flavour_s32_f32
:
15488 case neon_cvt_flavour_s32_f16
:
15492 case neon_cvt_flavour_u32_f64
:
15496 case neon_cvt_flavour_u32_f32
:
15500 case neon_cvt_flavour_u32_f16
:
15505 first_error (_("invalid instruction shape"));
15511 case neon_cvt_mode_a
: rm
= 0; break;
15512 case neon_cvt_mode_n
: rm
= 1; break;
15513 case neon_cvt_mode_p
: rm
= 2; break;
15514 case neon_cvt_mode_m
: rm
= 3; break;
15515 default: first_error (_("invalid rounding mode")); return;
15518 NEON_ENCODE (FPV8
, inst
);
15519 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15520 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15521 inst
.instruction
|= sz
<< 8;
15523 /* ARMv8.2 fp16 VCVT instruction. */
15524 if (flavour
== neon_cvt_flavour_s32_f16
15525 ||flavour
== neon_cvt_flavour_u32_f16
)
15526 do_scalar_fp16_v82_encode ();
15527 inst
.instruction
|= op
<< 7;
15528 inst
.instruction
|= rm
<< 16;
15529 inst
.instruction
|= 0xf0000000;
15530 inst
.is_neon
= TRUE
;
15534 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15536 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15537 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15538 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15540 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15542 /* PR11109: Handle round-to-zero for VCVT conversions. */
15543 if (mode
== neon_cvt_mode_z
15544 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15545 && (flavour
== neon_cvt_flavour_s32_f32
15546 || flavour
== neon_cvt_flavour_u32_f32
15547 || flavour
== neon_cvt_flavour_s32_f64
15548 || flavour
== neon_cvt_flavour_u32_f64
)
15549 && (rs
== NS_FD
|| rs
== NS_FF
))
15551 do_vfp_nsyn_cvtz ();
15555 /* ARMv8.2 fp16 VCVT conversions. */
15556 if (mode
== neon_cvt_mode_z
15557 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15558 && (flavour
== neon_cvt_flavour_s32_f16
15559 || flavour
== neon_cvt_flavour_u32_f16
)
15562 do_vfp_nsyn_cvtz ();
15563 do_scalar_fp16_v82_encode ();
15567 /* VFP rather than Neon conversions. */
15568 if (flavour
>= neon_cvt_flavour_first_fp
)
15570 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15571 do_vfp_nsyn_cvt (rs
, flavour
);
15573 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15584 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15586 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15589 /* Fixed-point conversion with #0 immediate is encoded as an
15590 integer conversion. */
15591 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15593 immbits
= 32 - inst
.operands
[2].imm
;
15594 NEON_ENCODE (IMMED
, inst
);
15595 if (flavour
!= neon_cvt_flavour_invalid
)
15596 inst
.instruction
|= enctab
[flavour
];
15597 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15598 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15599 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15600 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15601 inst
.instruction
|= neon_quad (rs
) << 6;
15602 inst
.instruction
|= 1 << 21;
15603 inst
.instruction
|= immbits
<< 16;
15605 neon_dp_fixup (&inst
);
15611 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15613 NEON_ENCODE (FLOAT
, inst
);
15614 set_it_insn_type (OUTSIDE_IT_INSN
);
15616 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15619 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15620 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15621 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15622 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15623 inst
.instruction
|= neon_quad (rs
) << 6;
15624 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
15625 inst
.instruction
|= mode
<< 8;
15627 inst
.instruction
|= 0xfc000000;
15629 inst
.instruction
|= 0xf0000000;
15635 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
15637 NEON_ENCODE (INTEGER
, inst
);
15639 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15642 if (flavour
!= neon_cvt_flavour_invalid
)
15643 inst
.instruction
|= enctab
[flavour
];
15645 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15646 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15647 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15648 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15649 inst
.instruction
|= neon_quad (rs
) << 6;
15650 inst
.instruction
|= 2 << 18;
15652 neon_dp_fixup (&inst
);
15657 /* Half-precision conversions for Advanced SIMD -- neon. */
15662 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15664 as_bad (_("operand size must match register width"));
15669 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15671 as_bad (_("operand size must match register width"));
15676 inst
.instruction
= 0x3b60600;
15678 inst
.instruction
= 0x3b60700;
15680 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15681 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15682 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15683 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15684 neon_dp_fixup (&inst
);
15688 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15689 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15690 do_vfp_nsyn_cvt (rs
, flavour
);
15692 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15697 do_neon_cvtr (void)
15699 do_neon_cvt_1 (neon_cvt_mode_x
);
15705 do_neon_cvt_1 (neon_cvt_mode_z
);
15709 do_neon_cvta (void)
15711 do_neon_cvt_1 (neon_cvt_mode_a
);
15715 do_neon_cvtn (void)
15717 do_neon_cvt_1 (neon_cvt_mode_n
);
15721 do_neon_cvtp (void)
15723 do_neon_cvt_1 (neon_cvt_mode_p
);
15727 do_neon_cvtm (void)
15729 do_neon_cvt_1 (neon_cvt_mode_m
);
15733 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15736 mark_feature_used (&fpu_vfp_ext_armv8
);
15738 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15739 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15740 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15741 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15742 inst
.instruction
|= to
? 0x10000 : 0;
15743 inst
.instruction
|= t
? 0x80 : 0;
15744 inst
.instruction
|= is_double
? 0x100 : 0;
15745 do_vfp_cond_or_thumb ();
15749 do_neon_cvttb_1 (bfd_boolean t
)
15751 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15752 NS_DF
, NS_DH
, NS_NULL
);
15756 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15759 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15761 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15764 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15766 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15768 /* The VCVTB and VCVTT instructions with D-register operands
15769 don't work for SP only targets. */
15770 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15774 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15776 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15778 /* The VCVTB and VCVTT instructions with D-register operands
15779 don't work for SP only targets. */
15780 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15784 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15791 do_neon_cvtb (void)
15793 do_neon_cvttb_1 (FALSE
);
15798 do_neon_cvtt (void)
15800 do_neon_cvttb_1 (TRUE
);
15804 neon_move_immediate (void)
15806 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15807 struct neon_type_el et
= neon_check_type (2, rs
,
15808 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15809 unsigned immlo
, immhi
= 0, immbits
;
15810 int op
, cmode
, float_p
;
15812 constraint (et
.type
== NT_invtype
,
15813 _("operand size must be specified for immediate VMOV"));
15815 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15816 op
= (inst
.instruction
& (1 << 5)) != 0;
15818 immlo
= inst
.operands
[1].imm
;
15819 if (inst
.operands
[1].regisimm
)
15820 immhi
= inst
.operands
[1].reg
;
15822 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15823 _("immediate has bits set outside the operand size"));
15825 float_p
= inst
.operands
[1].immisfloat
;
15827 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15828 et
.size
, et
.type
)) == FAIL
)
15830 /* Invert relevant bits only. */
15831 neon_invert_size (&immlo
, &immhi
, et
.size
);
15832 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15833 with one or the other; those cases are caught by
15834 neon_cmode_for_move_imm. */
15836 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15837 &op
, et
.size
, et
.type
)) == FAIL
)
15839 first_error (_("immediate out of range"));
15844 inst
.instruction
&= ~(1 << 5);
15845 inst
.instruction
|= op
<< 5;
15847 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15848 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15849 inst
.instruction
|= neon_quad (rs
) << 6;
15850 inst
.instruction
|= cmode
<< 8;
15852 neon_write_immbits (immbits
);
15858 if (inst
.operands
[1].isreg
)
15860 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15862 NEON_ENCODE (INTEGER
, inst
);
15863 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15864 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15865 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15866 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15867 inst
.instruction
|= neon_quad (rs
) << 6;
15871 NEON_ENCODE (IMMED
, inst
);
15872 neon_move_immediate ();
15875 neon_dp_fixup (&inst
);
15878 /* Encode instructions of form:
15880 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15881 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15884 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15886 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15887 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15888 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15889 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15890 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15891 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15892 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15893 inst
.instruction
|= neon_logbits (size
) << 20;
15895 neon_dp_fixup (&inst
);
15899 do_neon_dyadic_long (void)
15901 /* FIXME: Type checking for lengthening op. */
15902 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15903 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15904 neon_mixed_length (et
, et
.size
);
15908 do_neon_abal (void)
15910 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15911 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15912 neon_mixed_length (et
, et
.size
);
15916 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15918 if (inst
.operands
[2].isscalar
)
15920 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15921 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15922 NEON_ENCODE (SCALAR
, inst
);
15923 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15927 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15928 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15929 NEON_ENCODE (INTEGER
, inst
);
15930 neon_mixed_length (et
, et
.size
);
15935 do_neon_mac_maybe_scalar_long (void)
15937 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15941 do_neon_dyadic_wide (void)
15943 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15944 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15945 neon_mixed_length (et
, et
.size
);
15949 do_neon_dyadic_narrow (void)
15951 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15952 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15953 /* Operand sign is unimportant, and the U bit is part of the opcode,
15954 so force the operand type to integer. */
15955 et
.type
= NT_integer
;
15956 neon_mixed_length (et
, et
.size
/ 2);
15960 do_neon_mul_sat_scalar_long (void)
15962 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15966 do_neon_vmull (void)
15968 if (inst
.operands
[2].isscalar
)
15969 do_neon_mac_maybe_scalar_long ();
15972 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15973 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15975 if (et
.type
== NT_poly
)
15976 NEON_ENCODE (POLY
, inst
);
15978 NEON_ENCODE (INTEGER
, inst
);
15980 /* For polynomial encoding the U bit must be zero, and the size must
15981 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15982 obviously, as 0b10). */
15985 /* Check we're on the correct architecture. */
15986 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15988 _("Instruction form not available on this architecture.");
15993 neon_mixed_length (et
, et
.size
);
16000 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16001 struct neon_type_el et
= neon_check_type (3, rs
,
16002 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16003 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16005 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16006 _("shift out of range"));
16007 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16008 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16009 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16010 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16011 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16012 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16013 inst
.instruction
|= neon_quad (rs
) << 6;
16014 inst
.instruction
|= imm
<< 8;
16016 neon_dp_fixup (&inst
);
16022 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16023 struct neon_type_el et
= neon_check_type (2, rs
,
16024 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16025 unsigned op
= (inst
.instruction
>> 7) & 3;
16026 /* N (width of reversed regions) is encoded as part of the bitmask. We
16027 extract it here to check the elements to be reversed are smaller.
16028 Otherwise we'd get a reserved instruction. */
16029 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16030 gas_assert (elsize
!= 0);
16031 constraint (et
.size
>= elsize
,
16032 _("elements must be smaller than reversal region"));
16033 neon_two_same (neon_quad (rs
), 1, et
.size
);
16039 if (inst
.operands
[1].isscalar
)
16041 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16042 struct neon_type_el et
= neon_check_type (2, rs
,
16043 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16044 unsigned sizebits
= et
.size
>> 3;
16045 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16046 int logsize
= neon_logbits (et
.size
);
16047 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16049 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16052 NEON_ENCODE (SCALAR
, inst
);
16053 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16054 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16055 inst
.instruction
|= LOW4 (dm
);
16056 inst
.instruction
|= HI1 (dm
) << 5;
16057 inst
.instruction
|= neon_quad (rs
) << 6;
16058 inst
.instruction
|= x
<< 17;
16059 inst
.instruction
|= sizebits
<< 16;
16061 neon_dp_fixup (&inst
);
16065 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16066 struct neon_type_el et
= neon_check_type (2, rs
,
16067 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16068 /* Duplicate ARM register to lanes of vector. */
16069 NEON_ENCODE (ARMREG
, inst
);
16072 case 8: inst
.instruction
|= 0x400000; break;
16073 case 16: inst
.instruction
|= 0x000020; break;
16074 case 32: inst
.instruction
|= 0x000000; break;
16077 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16078 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16079 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16080 inst
.instruction
|= neon_quad (rs
) << 21;
16081 /* The encoding for this instruction is identical for the ARM and Thumb
16082 variants, except for the condition field. */
16083 do_vfp_cond_or_thumb ();
16087 /* VMOV has particularly many variations. It can be one of:
16088 0. VMOV<c><q> <Qd>, <Qm>
16089 1. VMOV<c><q> <Dd>, <Dm>
16090 (Register operations, which are VORR with Rm = Rn.)
16091 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16092 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16094 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16095 (ARM register to scalar.)
16096 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16097 (Two ARM registers to vector.)
16098 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16099 (Scalar to ARM register.)
16100 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16101 (Vector to two ARM registers.)
16102 8. VMOV.F32 <Sd>, <Sm>
16103 9. VMOV.F64 <Dd>, <Dm>
16104 (VFP register moves.)
16105 10. VMOV.F32 <Sd>, #imm
16106 11. VMOV.F64 <Dd>, #imm
16107 (VFP float immediate load.)
16108 12. VMOV <Rd>, <Sm>
16109 (VFP single to ARM reg.)
16110 13. VMOV <Sd>, <Rm>
16111 (ARM reg to VFP single.)
16112 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16113 (Two ARM regs to two VFP singles.)
16114 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16115 (Two VFP singles to two ARM regs.)
16117 These cases can be disambiguated using neon_select_shape, except cases 1/9
16118 and 3/11 which depend on the operand type too.
16120 All the encoded bits are hardcoded by this function.
16122 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16123 Cases 5, 7 may be used with VFPv2 and above.
16125 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16126 can specify a type where it doesn't make sense to, and is ignored). */
16131 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16132 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16133 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16134 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16135 struct neon_type_el et
;
16136 const char *ldconst
= 0;
16140 case NS_DD
: /* case 1/9. */
16141 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16142 /* It is not an error here if no type is given. */
16144 if (et
.type
== NT_float
&& et
.size
== 64)
16146 do_vfp_nsyn_opcode ("fcpyd");
16149 /* fall through. */
16151 case NS_QQ
: /* case 0/1. */
16153 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16155 /* The architecture manual I have doesn't explicitly state which
16156 value the U bit should have for register->register moves, but
16157 the equivalent VORR instruction has U = 0, so do that. */
16158 inst
.instruction
= 0x0200110;
16159 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16160 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16161 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16162 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16163 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16164 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16165 inst
.instruction
|= neon_quad (rs
) << 6;
16167 neon_dp_fixup (&inst
);
16171 case NS_DI
: /* case 3/11. */
16172 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16174 if (et
.type
== NT_float
&& et
.size
== 64)
16176 /* case 11 (fconstd). */
16177 ldconst
= "fconstd";
16178 goto encode_fconstd
;
16180 /* fall through. */
16182 case NS_QI
: /* case 2/3. */
16183 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16185 inst
.instruction
= 0x0800010;
16186 neon_move_immediate ();
16187 neon_dp_fixup (&inst
);
16190 case NS_SR
: /* case 4. */
16192 unsigned bcdebits
= 0;
16194 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16195 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16197 /* .<size> is optional here, defaulting to .32. */
16198 if (inst
.vectype
.elems
== 0
16199 && inst
.operands
[0].vectype
.type
== NT_invtype
16200 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16202 inst
.vectype
.el
[0].type
= NT_untyped
;
16203 inst
.vectype
.el
[0].size
= 32;
16204 inst
.vectype
.elems
= 1;
16207 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16208 logsize
= neon_logbits (et
.size
);
16210 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16212 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16213 && et
.size
!= 32, _(BAD_FPU
));
16214 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16215 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16219 case 8: bcdebits
= 0x8; break;
16220 case 16: bcdebits
= 0x1; break;
16221 case 32: bcdebits
= 0x0; break;
16225 bcdebits
|= x
<< logsize
;
16227 inst
.instruction
= 0xe000b10;
16228 do_vfp_cond_or_thumb ();
16229 inst
.instruction
|= LOW4 (dn
) << 16;
16230 inst
.instruction
|= HI1 (dn
) << 7;
16231 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16232 inst
.instruction
|= (bcdebits
& 3) << 5;
16233 inst
.instruction
|= (bcdebits
>> 2) << 21;
16237 case NS_DRR
: /* case 5 (fmdrr). */
16238 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16241 inst
.instruction
= 0xc400b10;
16242 do_vfp_cond_or_thumb ();
16243 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16244 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16245 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16246 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16249 case NS_RS
: /* case 6. */
16252 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16253 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16254 unsigned abcdebits
= 0;
16256 /* .<dt> is optional here, defaulting to .32. */
16257 if (inst
.vectype
.elems
== 0
16258 && inst
.operands
[0].vectype
.type
== NT_invtype
16259 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16261 inst
.vectype
.el
[0].type
= NT_untyped
;
16262 inst
.vectype
.el
[0].size
= 32;
16263 inst
.vectype
.elems
= 1;
16266 et
= neon_check_type (2, NS_NULL
,
16267 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16268 logsize
= neon_logbits (et
.size
);
16270 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16272 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16273 && et
.size
!= 32, _(BAD_FPU
));
16274 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16275 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16279 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16280 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16281 case 32: abcdebits
= 0x00; break;
16285 abcdebits
|= x
<< logsize
;
16286 inst
.instruction
= 0xe100b10;
16287 do_vfp_cond_or_thumb ();
16288 inst
.instruction
|= LOW4 (dn
) << 16;
16289 inst
.instruction
|= HI1 (dn
) << 7;
16290 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16291 inst
.instruction
|= (abcdebits
& 3) << 5;
16292 inst
.instruction
|= (abcdebits
>> 2) << 21;
16296 case NS_RRD
: /* case 7 (fmrrd). */
16297 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16300 inst
.instruction
= 0xc500b10;
16301 do_vfp_cond_or_thumb ();
16302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16303 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16304 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16305 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16308 case NS_FF
: /* case 8 (fcpys). */
16309 do_vfp_nsyn_opcode ("fcpys");
16313 case NS_FI
: /* case 10 (fconsts). */
16314 ldconst
= "fconsts";
16316 if (is_quarter_float (inst
.operands
[1].imm
))
16318 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16319 do_vfp_nsyn_opcode (ldconst
);
16321 /* ARMv8.2 fp16 vmov.f16 instruction. */
16323 do_scalar_fp16_v82_encode ();
16326 first_error (_("immediate out of range"));
16330 case NS_RF
: /* case 12 (fmrs). */
16331 do_vfp_nsyn_opcode ("fmrs");
16332 /* ARMv8.2 fp16 vmov.f16 instruction. */
16334 do_scalar_fp16_v82_encode ();
16338 case NS_FR
: /* case 13 (fmsr). */
16339 do_vfp_nsyn_opcode ("fmsr");
16340 /* ARMv8.2 fp16 vmov.f16 instruction. */
16342 do_scalar_fp16_v82_encode ();
16345 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16346 (one of which is a list), but we have parsed four. Do some fiddling to
16347 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16349 case NS_RRFF
: /* case 14 (fmrrs). */
16350 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16351 _("VFP registers must be adjacent"));
16352 inst
.operands
[2].imm
= 2;
16353 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16354 do_vfp_nsyn_opcode ("fmrrs");
16357 case NS_FFRR
: /* case 15 (fmsrr). */
16358 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16359 _("VFP registers must be adjacent"));
16360 inst
.operands
[1] = inst
.operands
[2];
16361 inst
.operands
[2] = inst
.operands
[3];
16362 inst
.operands
[0].imm
= 2;
16363 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16364 do_vfp_nsyn_opcode ("fmsrr");
16368 /* neon_select_shape has determined that the instruction
16369 shape is wrong and has already set the error message. */
16378 do_neon_rshift_round_imm (void)
16380 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16381 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16382 int imm
= inst
.operands
[2].imm
;
16384 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16387 inst
.operands
[2].present
= 0;
16392 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16393 _("immediate out of range for shift"));
16394 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16399 do_neon_movhf (void)
16401 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16402 constraint (rs
!= NS_HH
, _("invalid suffix"));
16404 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16407 do_vfp_sp_monadic ();
16410 inst
.instruction
|= 0xf0000000;
16414 do_neon_movl (void)
16416 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16417 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16418 unsigned sizebits
= et
.size
>> 3;
16419 inst
.instruction
|= sizebits
<< 19;
16420 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16426 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16427 struct neon_type_el et
= neon_check_type (2, rs
,
16428 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16429 NEON_ENCODE (INTEGER
, inst
);
16430 neon_two_same (neon_quad (rs
), 1, et
.size
);
16434 do_neon_zip_uzp (void)
16436 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16437 struct neon_type_el et
= neon_check_type (2, rs
,
16438 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16439 if (rs
== NS_DD
&& et
.size
== 32)
16441 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16442 inst
.instruction
= N_MNEM_vtrn
;
16446 neon_two_same (neon_quad (rs
), 1, et
.size
);
16450 do_neon_sat_abs_neg (void)
16452 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16453 struct neon_type_el et
= neon_check_type (2, rs
,
16454 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16455 neon_two_same (neon_quad (rs
), 1, et
.size
);
16459 do_neon_pair_long (void)
16461 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16462 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16463 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16464 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16465 neon_two_same (neon_quad (rs
), 1, et
.size
);
16469 do_neon_recip_est (void)
16471 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16472 struct neon_type_el et
= neon_check_type (2, rs
,
16473 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
16474 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16475 neon_two_same (neon_quad (rs
), 1, et
.size
);
16481 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16482 struct neon_type_el et
= neon_check_type (2, rs
,
16483 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16484 neon_two_same (neon_quad (rs
), 1, et
.size
);
16490 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16491 struct neon_type_el et
= neon_check_type (2, rs
,
16492 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16493 neon_two_same (neon_quad (rs
), 1, et
.size
);
16499 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16500 struct neon_type_el et
= neon_check_type (2, rs
,
16501 N_EQK
| N_INT
, N_8
| N_KEY
);
16502 neon_two_same (neon_quad (rs
), 1, et
.size
);
16508 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16509 neon_two_same (neon_quad (rs
), 1, -1);
16513 do_neon_tbl_tbx (void)
16515 unsigned listlenbits
;
16516 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16518 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16520 first_error (_("bad list length for table lookup"));
16524 listlenbits
= inst
.operands
[1].imm
- 1;
16525 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16526 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16527 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16528 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16529 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16530 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16531 inst
.instruction
|= listlenbits
<< 8;
16533 neon_dp_fixup (&inst
);
16537 do_neon_ldm_stm (void)
16539 /* P, U and L bits are part of bitmask. */
16540 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16541 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16543 if (inst
.operands
[1].issingle
)
16545 do_vfp_nsyn_ldm_stm (is_dbmode
);
16549 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16550 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16552 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16553 _("register list must contain at least 1 and at most 16 "
16556 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16557 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16558 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16559 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16561 inst
.instruction
|= offsetbits
;
16563 do_vfp_cond_or_thumb ();
16567 do_neon_ldr_str (void)
16569 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16571 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16572 And is UNPREDICTABLE in thumb mode. */
16574 && inst
.operands
[1].reg
== REG_PC
16575 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16578 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16579 else if (warn_on_deprecated
)
16580 as_tsktsk (_("Use of PC here is deprecated"));
16583 if (inst
.operands
[0].issingle
)
16586 do_vfp_nsyn_opcode ("flds");
16588 do_vfp_nsyn_opcode ("fsts");
16590 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16591 if (inst
.vectype
.el
[0].size
== 16)
16592 do_scalar_fp16_v82_encode ();
16597 do_vfp_nsyn_opcode ("fldd");
16599 do_vfp_nsyn_opcode ("fstd");
16603 /* "interleave" version also handles non-interleaving register VLD1/VST1
16607 do_neon_ld_st_interleave (void)
16609 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16610 N_8
| N_16
| N_32
| N_64
);
16611 unsigned alignbits
= 0;
16613 /* The bits in this table go:
16614 0: register stride of one (0) or two (1)
16615 1,2: register list length, minus one (1, 2, 3, 4).
16616 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16617 We use -1 for invalid entries. */
16618 const int typetable
[] =
16620 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16621 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16622 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16623 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16627 if (et
.type
== NT_invtype
)
16630 if (inst
.operands
[1].immisalign
)
16631 switch (inst
.operands
[1].imm
>> 8)
16633 case 64: alignbits
= 1; break;
16635 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16636 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16637 goto bad_alignment
;
16641 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16642 goto bad_alignment
;
16647 first_error (_("bad alignment"));
16651 inst
.instruction
|= alignbits
<< 4;
16652 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16654 /* Bits [4:6] of the immediate in a list specifier encode register stride
16655 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16656 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16657 up the right value for "type" in a table based on this value and the given
16658 list style, then stick it back. */
16659 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16660 | (((inst
.instruction
>> 8) & 3) << 3);
16662 typebits
= typetable
[idx
];
16664 constraint (typebits
== -1, _("bad list type for instruction"));
16665 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16666 _("bad element type for instruction"));
16668 inst
.instruction
&= ~0xf00;
16669 inst
.instruction
|= typebits
<< 8;
16672 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16673 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16674 otherwise. The variable arguments are a list of pairs of legal (size, align)
16675 values, terminated with -1. */
16678 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
16681 int result
= FAIL
, thissize
, thisalign
;
16683 if (!inst
.operands
[1].immisalign
)
16689 va_start (ap
, do_align
);
16693 thissize
= va_arg (ap
, int);
16694 if (thissize
== -1)
16696 thisalign
= va_arg (ap
, int);
16698 if (size
== thissize
&& align
== thisalign
)
16701 while (result
!= SUCCESS
);
16705 if (result
== SUCCESS
)
16708 first_error (_("unsupported alignment for instruction"));
16714 do_neon_ld_st_lane (void)
16716 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16717 int align_good
, do_align
= 0;
16718 int logsize
= neon_logbits (et
.size
);
16719 int align
= inst
.operands
[1].imm
>> 8;
16720 int n
= (inst
.instruction
>> 8) & 3;
16721 int max_el
= 64 / et
.size
;
16723 if (et
.type
== NT_invtype
)
16726 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16727 _("bad list length"));
16728 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16729 _("scalar index out of range"));
16730 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16732 _("stride of 2 unavailable when element size is 8"));
16736 case 0: /* VLD1 / VST1. */
16737 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16739 if (align_good
== FAIL
)
16743 unsigned alignbits
= 0;
16746 case 16: alignbits
= 0x1; break;
16747 case 32: alignbits
= 0x3; break;
16750 inst
.instruction
|= alignbits
<< 4;
16754 case 1: /* VLD2 / VST2. */
16755 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16757 if (align_good
== FAIL
)
16760 inst
.instruction
|= 1 << 4;
16763 case 2: /* VLD3 / VST3. */
16764 constraint (inst
.operands
[1].immisalign
,
16765 _("can't use alignment with this instruction"));
16768 case 3: /* VLD4 / VST4. */
16769 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16770 16, 64, 32, 64, 32, 128, -1);
16771 if (align_good
== FAIL
)
16775 unsigned alignbits
= 0;
16778 case 8: alignbits
= 0x1; break;
16779 case 16: alignbits
= 0x1; break;
16780 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16783 inst
.instruction
|= alignbits
<< 4;
16790 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16791 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16792 inst
.instruction
|= 1 << (4 + logsize
);
16794 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16795 inst
.instruction
|= logsize
<< 10;
16798 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16801 do_neon_ld_dup (void)
16803 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16804 int align_good
, do_align
= 0;
16806 if (et
.type
== NT_invtype
)
16809 switch ((inst
.instruction
>> 8) & 3)
16811 case 0: /* VLD1. */
16812 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16813 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16814 &do_align
, 16, 16, 32, 32, -1);
16815 if (align_good
== FAIL
)
16817 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16820 case 2: inst
.instruction
|= 1 << 5; break;
16821 default: first_error (_("bad list length")); return;
16823 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16826 case 1: /* VLD2. */
16827 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16828 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16829 if (align_good
== FAIL
)
16831 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16832 _("bad list length"));
16833 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16834 inst
.instruction
|= 1 << 5;
16835 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16838 case 2: /* VLD3. */
16839 constraint (inst
.operands
[1].immisalign
,
16840 _("can't use alignment with this instruction"));
16841 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16842 _("bad list length"));
16843 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16844 inst
.instruction
|= 1 << 5;
16845 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16848 case 3: /* VLD4. */
16850 int align
= inst
.operands
[1].imm
>> 8;
16851 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16852 16, 64, 32, 64, 32, 128, -1);
16853 if (align_good
== FAIL
)
16855 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16856 _("bad list length"));
16857 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16858 inst
.instruction
|= 1 << 5;
16859 if (et
.size
== 32 && align
== 128)
16860 inst
.instruction
|= 0x3 << 6;
16862 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16869 inst
.instruction
|= do_align
<< 4;
16872 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16873 apart from bits [11:4]. */
16876 do_neon_ldx_stx (void)
16878 if (inst
.operands
[1].isreg
)
16879 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16881 switch (NEON_LANE (inst
.operands
[0].imm
))
16883 case NEON_INTERLEAVE_LANES
:
16884 NEON_ENCODE (INTERLV
, inst
);
16885 do_neon_ld_st_interleave ();
16888 case NEON_ALL_LANES
:
16889 NEON_ENCODE (DUP
, inst
);
16890 if (inst
.instruction
== N_INV
)
16892 first_error ("only loads support such operands");
16899 NEON_ENCODE (LANE
, inst
);
16900 do_neon_ld_st_lane ();
16903 /* L bit comes from bit mask. */
16904 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16905 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16906 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16908 if (inst
.operands
[1].postind
)
16910 int postreg
= inst
.operands
[1].imm
& 0xf;
16911 constraint (!inst
.operands
[1].immisreg
,
16912 _("post-index must be a register"));
16913 constraint (postreg
== 0xd || postreg
== 0xf,
16914 _("bad register for post-index"));
16915 inst
.instruction
|= postreg
;
16919 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16920 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16921 || inst
.reloc
.exp
.X_add_number
!= 0,
16924 if (inst
.operands
[1].writeback
)
16926 inst
.instruction
|= 0xd;
16929 inst
.instruction
|= 0xf;
16933 inst
.instruction
|= 0xf9000000;
16935 inst
.instruction
|= 0xf4000000;
16940 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16942 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16943 D register operands. */
16944 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16945 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16948 NEON_ENCODE (FPV8
, inst
);
16950 if (rs
== NS_FFF
|| rs
== NS_HHH
)
16952 do_vfp_sp_dyadic ();
16954 /* ARMv8.2 fp16 instruction. */
16956 do_scalar_fp16_v82_encode ();
16959 do_vfp_dp_rd_rn_rm ();
16962 inst
.instruction
|= 0x100;
16964 inst
.instruction
|= 0xf0000000;
16970 set_it_insn_type (OUTSIDE_IT_INSN
);
16972 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16973 first_error (_("invalid instruction shape"));
16979 set_it_insn_type (OUTSIDE_IT_INSN
);
16981 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16984 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16987 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16991 do_vrint_1 (enum neon_cvt_mode mode
)
16993 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16994 struct neon_type_el et
;
16999 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17000 D register operands. */
17001 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17002 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17005 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17007 if (et
.type
!= NT_invtype
)
17009 /* VFP encodings. */
17010 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17011 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17012 set_it_insn_type (OUTSIDE_IT_INSN
);
17014 NEON_ENCODE (FPV8
, inst
);
17015 if (rs
== NS_FF
|| rs
== NS_HH
)
17016 do_vfp_sp_monadic ();
17018 do_vfp_dp_rd_rm ();
17022 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17023 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17024 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17025 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17026 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17027 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17028 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17032 inst
.instruction
|= (rs
== NS_DD
) << 8;
17033 do_vfp_cond_or_thumb ();
17035 /* ARMv8.2 fp16 vrint instruction. */
17037 do_scalar_fp16_v82_encode ();
17041 /* Neon encodings (or something broken...). */
17043 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
17045 if (et
.type
== NT_invtype
)
17048 set_it_insn_type (OUTSIDE_IT_INSN
);
17049 NEON_ENCODE (FLOAT
, inst
);
17051 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17054 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17055 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17056 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17057 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17058 inst
.instruction
|= neon_quad (rs
) << 6;
17061 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17062 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17063 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17064 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17065 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17066 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17067 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17072 inst
.instruction
|= 0xfc000000;
17074 inst
.instruction
|= 0xf0000000;
17081 do_vrint_1 (neon_cvt_mode_x
);
17087 do_vrint_1 (neon_cvt_mode_z
);
17093 do_vrint_1 (neon_cvt_mode_r
);
17099 do_vrint_1 (neon_cvt_mode_a
);
17105 do_vrint_1 (neon_cvt_mode_n
);
17111 do_vrint_1 (neon_cvt_mode_p
);
17117 do_vrint_1 (neon_cvt_mode_m
);
17120 /* Crypto v1 instructions. */
17122 do_crypto_2op_1 (unsigned elttype
, int op
)
17124 set_it_insn_type (OUTSIDE_IT_INSN
);
17126 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17132 NEON_ENCODE (INTEGER
, inst
);
17133 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17134 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17135 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17136 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17138 inst
.instruction
|= op
<< 6;
17141 inst
.instruction
|= 0xfc000000;
17143 inst
.instruction
|= 0xf0000000;
17147 do_crypto_3op_1 (int u
, int op
)
17149 set_it_insn_type (OUTSIDE_IT_INSN
);
17151 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17152 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17157 NEON_ENCODE (INTEGER
, inst
);
17158 neon_three_same (1, u
, 8 << op
);
17164 do_crypto_2op_1 (N_8
, 0);
17170 do_crypto_2op_1 (N_8
, 1);
17176 do_crypto_2op_1 (N_8
, 2);
17182 do_crypto_2op_1 (N_8
, 3);
17188 do_crypto_3op_1 (0, 0);
17194 do_crypto_3op_1 (0, 1);
17200 do_crypto_3op_1 (0, 2);
17206 do_crypto_3op_1 (0, 3);
17212 do_crypto_3op_1 (1, 0);
17218 do_crypto_3op_1 (1, 1);
17222 do_sha256su1 (void)
17224 do_crypto_3op_1 (1, 2);
17230 do_crypto_2op_1 (N_32
, -1);
17236 do_crypto_2op_1 (N_32
, 0);
17240 do_sha256su0 (void)
17242 do_crypto_2op_1 (N_32
, 1);
17246 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17248 unsigned int Rd
= inst
.operands
[0].reg
;
17249 unsigned int Rn
= inst
.operands
[1].reg
;
17250 unsigned int Rm
= inst
.operands
[2].reg
;
17252 set_it_insn_type (OUTSIDE_IT_INSN
);
17253 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17254 inst
.instruction
|= LOW4 (Rn
) << 16;
17255 inst
.instruction
|= LOW4 (Rm
);
17256 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17257 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17259 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17260 as_warn (UNPRED_REG ("r15"));
17261 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17262 as_warn (UNPRED_REG ("r13"));
17302 /* Overall per-instruction processing. */
17304 /* We need to be able to fix up arbitrary expressions in some statements.
17305 This is so that we can handle symbols that are an arbitrary distance from
17306 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17307 which returns part of an address in a form which will be valid for
17308 a data instruction. We do this by pushing the expression into a symbol
17309 in the expr_section, and creating a fix for that. */
17312 fix_new_arm (fragS
* frag
,
17326 /* Create an absolute valued symbol, so we have something to
17327 refer to in the object file. Unfortunately for us, gas's
17328 generic expression parsing will already have folded out
17329 any use of .set foo/.type foo %function that may have
17330 been used to set type information of the target location,
17331 that's being specified symbolically. We have to presume
17332 the user knows what they are doing. */
17336 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17338 symbol
= symbol_find_or_make (name
);
17339 S_SET_SEGMENT (symbol
, absolute_section
);
17340 symbol_set_frag (symbol
, &zero_address_frag
);
17341 S_SET_VALUE (symbol
, exp
->X_add_number
);
17342 exp
->X_op
= O_symbol
;
17343 exp
->X_add_symbol
= symbol
;
17344 exp
->X_add_number
= 0;
17350 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17351 (enum bfd_reloc_code_real
) reloc
);
17355 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17356 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17360 /* Mark whether the fix is to a THUMB instruction, or an ARM
17362 new_fix
->tc_fix_data
= thumb_mode
;
17365 /* Create a frg for an instruction requiring relaxation. */
17367 output_relax_insn (void)
17373 /* The size of the instruction is unknown, so tie the debug info to the
17374 start of the instruction. */
17375 dwarf2_emit_insn (0);
17377 switch (inst
.reloc
.exp
.X_op
)
17380 sym
= inst
.reloc
.exp
.X_add_symbol
;
17381 offset
= inst
.reloc
.exp
.X_add_number
;
17385 offset
= inst
.reloc
.exp
.X_add_number
;
17388 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17392 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17393 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17394 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17397 /* Write a 32-bit thumb instruction to buf. */
17399 put_thumb32_insn (char * buf
, unsigned long insn
)
17401 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17402 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17406 output_inst (const char * str
)
17412 as_bad ("%s -- `%s'", inst
.error
, str
);
17417 output_relax_insn ();
17420 if (inst
.size
== 0)
17423 to
= frag_more (inst
.size
);
17424 /* PR 9814: Record the thumb mode into the current frag so that we know
17425 what type of NOP padding to use, if necessary. We override any previous
17426 setting so that if the mode has changed then the NOPS that we use will
17427 match the encoding of the last instruction in the frag. */
17428 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17430 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17432 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17433 put_thumb32_insn (to
, inst
.instruction
);
17435 else if (inst
.size
> INSN_SIZE
)
17437 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17438 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17439 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17442 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17444 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17445 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17446 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17449 dwarf2_emit_insn (inst
.size
);
17453 output_it_inst (int cond
, int mask
, char * to
)
17455 unsigned long instruction
= 0xbf00;
17458 instruction
|= mask
;
17459 instruction
|= cond
<< 4;
17463 to
= frag_more (2);
17465 dwarf2_emit_insn (2);
17469 md_number_to_chars (to
, instruction
, 2);
17474 /* Tag values used in struct asm_opcode's tag field. */
17477 OT_unconditional
, /* Instruction cannot be conditionalized.
17478 The ARM condition field is still 0xE. */
17479 OT_unconditionalF
, /* Instruction cannot be conditionalized
17480 and carries 0xF in its ARM condition field. */
17481 OT_csuffix
, /* Instruction takes a conditional suffix. */
17482 OT_csuffixF
, /* Some forms of the instruction take a conditional
17483 suffix, others place 0xF where the condition field
17485 OT_cinfix3
, /* Instruction takes a conditional infix,
17486 beginning at character index 3. (In
17487 unified mode, it becomes a suffix.) */
17488 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17489 tsts, cmps, cmns, and teqs. */
17490 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17491 character index 3, even in unified mode. Used for
17492 legacy instructions where suffix and infix forms
17493 may be ambiguous. */
17494 OT_csuf_or_in3
, /* Instruction takes either a conditional
17495 suffix or an infix at character index 3. */
17496 OT_odd_infix_unc
, /* This is the unconditional variant of an
17497 instruction that takes a conditional infix
17498 at an unusual position. In unified mode,
17499 this variant will accept a suffix. */
17500 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17501 are the conditional variants of instructions that
17502 take conditional infixes in unusual positions.
17503 The infix appears at character index
17504 (tag - OT_odd_infix_0). These are not accepted
17505 in unified mode. */
17508 /* Subroutine of md_assemble, responsible for looking up the primary
17509 opcode from the mnemonic the user wrote. STR points to the
17510 beginning of the mnemonic.
17512 This is not simply a hash table lookup, because of conditional
17513 variants. Most instructions have conditional variants, which are
17514 expressed with a _conditional affix_ to the mnemonic. If we were
17515 to encode each conditional variant as a literal string in the opcode
17516 table, it would have approximately 20,000 entries.
17518 Most mnemonics take this affix as a suffix, and in unified syntax,
17519 'most' is upgraded to 'all'. However, in the divided syntax, some
17520 instructions take the affix as an infix, notably the s-variants of
17521 the arithmetic instructions. Of those instructions, all but six
17522 have the infix appear after the third character of the mnemonic.
17524 Accordingly, the algorithm for looking up primary opcodes given
17527 1. Look up the identifier in the opcode table.
17528 If we find a match, go to step U.
17530 2. Look up the last two characters of the identifier in the
17531 conditions table. If we find a match, look up the first N-2
17532 characters of the identifier in the opcode table. If we
17533 find a match, go to step CE.
17535 3. Look up the fourth and fifth characters of the identifier in
17536 the conditions table. If we find a match, extract those
17537 characters from the identifier, and look up the remaining
17538 characters in the opcode table. If we find a match, go
17543 U. Examine the tag field of the opcode structure, in case this is
17544 one of the six instructions with its conditional infix in an
17545 unusual place. If it is, the tag tells us where to find the
17546 infix; look it up in the conditions table and set inst.cond
17547 accordingly. Otherwise, this is an unconditional instruction.
17548 Again set inst.cond accordingly. Return the opcode structure.
17550 CE. Examine the tag field to make sure this is an instruction that
17551 should receive a conditional suffix. If it is not, fail.
17552 Otherwise, set inst.cond from the suffix we already looked up,
17553 and return the opcode structure.
17555 CM. Examine the tag field to make sure this is an instruction that
17556 should receive a conditional infix after the third character.
17557 If it is not, fail. Otherwise, undo the edits to the current
17558 line of input and proceed as for case CE. */
17560 static const struct asm_opcode
*
17561 opcode_lookup (char **str
)
17565 const struct asm_opcode
*opcode
;
17566 const struct asm_cond
*cond
;
17569 /* Scan up to the end of the mnemonic, which must end in white space,
17570 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17571 for (base
= end
= *str
; *end
!= '\0'; end
++)
17572 if (*end
== ' ' || *end
== '.')
17578 /* Handle a possible width suffix and/or Neon type suffix. */
17583 /* The .w and .n suffixes are only valid if the unified syntax is in
17585 if (unified_syntax
&& end
[1] == 'w')
17587 else if (unified_syntax
&& end
[1] == 'n')
17592 inst
.vectype
.elems
= 0;
17594 *str
= end
+ offset
;
17596 if (end
[offset
] == '.')
17598 /* See if we have a Neon type suffix (possible in either unified or
17599 non-unified ARM syntax mode). */
17600 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17603 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17609 /* Look for unaffixed or special-case affixed mnemonic. */
17610 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17615 if (opcode
->tag
< OT_odd_infix_0
)
17617 inst
.cond
= COND_ALWAYS
;
17621 if (warn_on_deprecated
&& unified_syntax
)
17622 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17623 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17624 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17627 inst
.cond
= cond
->value
;
17631 /* Cannot have a conditional suffix on a mnemonic of less than two
17633 if (end
- base
< 3)
17636 /* Look for suffixed mnemonic. */
17638 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17639 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17641 if (opcode
&& cond
)
17644 switch (opcode
->tag
)
17646 case OT_cinfix3_legacy
:
17647 /* Ignore conditional suffixes matched on infix only mnemonics. */
17651 case OT_cinfix3_deprecated
:
17652 case OT_odd_infix_unc
:
17653 if (!unified_syntax
)
17655 /* else fall through */
17659 case OT_csuf_or_in3
:
17660 inst
.cond
= cond
->value
;
17663 case OT_unconditional
:
17664 case OT_unconditionalF
:
17666 inst
.cond
= cond
->value
;
17669 /* Delayed diagnostic. */
17670 inst
.error
= BAD_COND
;
17671 inst
.cond
= COND_ALWAYS
;
17680 /* Cannot have a usual-position infix on a mnemonic of less than
17681 six characters (five would be a suffix). */
17682 if (end
- base
< 6)
17685 /* Look for infixed mnemonic in the usual position. */
17687 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17691 memcpy (save
, affix
, 2);
17692 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17693 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17695 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17696 memcpy (affix
, save
, 2);
17699 && (opcode
->tag
== OT_cinfix3
17700 || opcode
->tag
== OT_cinfix3_deprecated
17701 || opcode
->tag
== OT_csuf_or_in3
17702 || opcode
->tag
== OT_cinfix3_legacy
))
17705 if (warn_on_deprecated
&& unified_syntax
17706 && (opcode
->tag
== OT_cinfix3
17707 || opcode
->tag
== OT_cinfix3_deprecated
))
17708 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17710 inst
.cond
= cond
->value
;
17717 /* This function generates an initial IT instruction, leaving its block
17718 virtually open for the new instructions. Eventually,
17719 the mask will be updated by now_it_add_mask () each time
17720 a new instruction needs to be included in the IT block.
17721 Finally, the block is closed with close_automatic_it_block ().
17722 The block closure can be requested either from md_assemble (),
17723 a tencode (), or due to a label hook. */
17726 new_automatic_it_block (int cond
)
17728 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17729 now_it
.mask
= 0x18;
17731 now_it
.block_length
= 1;
17732 mapping_state (MAP_THUMB
);
17733 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17734 now_it
.warn_deprecated
= FALSE
;
17735 now_it
.insn_cond
= TRUE
;
17738 /* Close an automatic IT block.
17739 See comments in new_automatic_it_block (). */
17742 close_automatic_it_block (void)
17744 now_it
.mask
= 0x10;
17745 now_it
.block_length
= 0;
17748 /* Update the mask of the current automatically-generated IT
17749 instruction. See comments in new_automatic_it_block (). */
17752 now_it_add_mask (int cond
)
17754 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17755 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17756 | ((bitvalue) << (nbit)))
17757 const int resulting_bit
= (cond
& 1);
17759 now_it
.mask
&= 0xf;
17760 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17762 (5 - now_it
.block_length
));
17763 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17765 ((5 - now_it
.block_length
) - 1) );
17766 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17769 #undef SET_BIT_VALUE
17772 /* The IT blocks handling machinery is accessed through the these functions:
17773 it_fsm_pre_encode () from md_assemble ()
17774 set_it_insn_type () optional, from the tencode functions
17775 set_it_insn_type_last () ditto
17776 in_it_block () ditto
17777 it_fsm_post_encode () from md_assemble ()
17778 force_automatic_it_block_close () from label habdling functions
17781 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17782 initializing the IT insn type with a generic initial value depending
17783 on the inst.condition.
17784 2) During the tencode function, two things may happen:
17785 a) The tencode function overrides the IT insn type by
17786 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17787 b) The tencode function queries the IT block state by
17788 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17790 Both set_it_insn_type and in_it_block run the internal FSM state
17791 handling function (handle_it_state), because: a) setting the IT insn
17792 type may incur in an invalid state (exiting the function),
17793 and b) querying the state requires the FSM to be updated.
17794 Specifically we want to avoid creating an IT block for conditional
17795 branches, so it_fsm_pre_encode is actually a guess and we can't
17796 determine whether an IT block is required until the tencode () routine
17797 has decided what type of instruction this actually it.
17798 Because of this, if set_it_insn_type and in_it_block have to be used,
17799 set_it_insn_type has to be called first.
17801 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17802 determines the insn IT type depending on the inst.cond code.
17803 When a tencode () routine encodes an instruction that can be
17804 either outside an IT block, or, in the case of being inside, has to be
17805 the last one, set_it_insn_type_last () will determine the proper
17806 IT instruction type based on the inst.cond code. Otherwise,
17807 set_it_insn_type can be called for overriding that logic or
17808 for covering other cases.
17810 Calling handle_it_state () may not transition the IT block state to
17811 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17812 still queried. Instead, if the FSM determines that the state should
17813 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17814 after the tencode () function: that's what it_fsm_post_encode () does.
17816 Since in_it_block () calls the state handling function to get an
17817 updated state, an error may occur (due to invalid insns combination).
17818 In that case, inst.error is set.
17819 Therefore, inst.error has to be checked after the execution of
17820 the tencode () routine.
17822 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17823 any pending state change (if any) that didn't take place in
17824 handle_it_state () as explained above. */
17827 it_fsm_pre_encode (void)
17829 if (inst
.cond
!= COND_ALWAYS
)
17830 inst
.it_insn_type
= INSIDE_IT_INSN
;
17832 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17834 now_it
.state_handled
= 0;
17837 /* IT state FSM handling function. */
17840 handle_it_state (void)
17842 now_it
.state_handled
= 1;
17843 now_it
.insn_cond
= FALSE
;
17845 switch (now_it
.state
)
17847 case OUTSIDE_IT_BLOCK
:
17848 switch (inst
.it_insn_type
)
17850 case OUTSIDE_IT_INSN
:
17853 case INSIDE_IT_INSN
:
17854 case INSIDE_IT_LAST_INSN
:
17855 if (thumb_mode
== 0)
17858 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17859 as_tsktsk (_("Warning: conditional outside an IT block"\
17864 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17865 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
17867 /* Automatically generate the IT instruction. */
17868 new_automatic_it_block (inst
.cond
);
17869 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17870 close_automatic_it_block ();
17874 inst
.error
= BAD_OUT_IT
;
17880 case IF_INSIDE_IT_LAST_INSN
:
17881 case NEUTRAL_IT_INSN
:
17885 now_it
.state
= MANUAL_IT_BLOCK
;
17886 now_it
.block_length
= 0;
17891 case AUTOMATIC_IT_BLOCK
:
17892 /* Three things may happen now:
17893 a) We should increment current it block size;
17894 b) We should close current it block (closing insn or 4 insns);
17895 c) We should close current it block and start a new one (due
17896 to incompatible conditions or
17897 4 insns-length block reached). */
17899 switch (inst
.it_insn_type
)
17901 case OUTSIDE_IT_INSN
:
17902 /* The closure of the block shall happen immediatelly,
17903 so any in_it_block () call reports the block as closed. */
17904 force_automatic_it_block_close ();
17907 case INSIDE_IT_INSN
:
17908 case INSIDE_IT_LAST_INSN
:
17909 case IF_INSIDE_IT_LAST_INSN
:
17910 now_it
.block_length
++;
17912 if (now_it
.block_length
> 4
17913 || !now_it_compatible (inst
.cond
))
17915 force_automatic_it_block_close ();
17916 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17917 new_automatic_it_block (inst
.cond
);
17921 now_it
.insn_cond
= TRUE
;
17922 now_it_add_mask (inst
.cond
);
17925 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17926 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17927 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17928 close_automatic_it_block ();
17931 case NEUTRAL_IT_INSN
:
17932 now_it
.block_length
++;
17933 now_it
.insn_cond
= TRUE
;
17935 if (now_it
.block_length
> 4)
17936 force_automatic_it_block_close ();
17938 now_it_add_mask (now_it
.cc
& 1);
17942 close_automatic_it_block ();
17943 now_it
.state
= MANUAL_IT_BLOCK
;
17948 case MANUAL_IT_BLOCK
:
17950 /* Check conditional suffixes. */
17951 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17954 now_it
.mask
&= 0x1f;
17955 is_last
= (now_it
.mask
== 0x10);
17956 now_it
.insn_cond
= TRUE
;
17958 switch (inst
.it_insn_type
)
17960 case OUTSIDE_IT_INSN
:
17961 inst
.error
= BAD_NOT_IT
;
17964 case INSIDE_IT_INSN
:
17965 if (cond
!= inst
.cond
)
17967 inst
.error
= BAD_IT_COND
;
17972 case INSIDE_IT_LAST_INSN
:
17973 case IF_INSIDE_IT_LAST_INSN
:
17974 if (cond
!= inst
.cond
)
17976 inst
.error
= BAD_IT_COND
;
17981 inst
.error
= BAD_BRANCH
;
17986 case NEUTRAL_IT_INSN
:
17987 /* The BKPT instruction is unconditional even in an IT block. */
17991 inst
.error
= BAD_IT_IT
;
18001 struct depr_insn_mask
18003 unsigned long pattern
;
18004 unsigned long mask
;
18005 const char* description
;
18008 /* List of 16-bit instruction patterns deprecated in an IT block in
18010 static const struct depr_insn_mask depr_it_insns
[] = {
18011 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18012 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18013 { 0xa000, 0xb800, N_("ADR") },
18014 { 0x4800, 0xf800, N_("Literal loads") },
18015 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18016 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18017 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18018 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18019 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18024 it_fsm_post_encode (void)
18028 if (!now_it
.state_handled
)
18029 handle_it_state ();
18031 if (now_it
.insn_cond
18032 && !now_it
.warn_deprecated
18033 && warn_on_deprecated
18034 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18036 if (inst
.instruction
>= 0x10000)
18038 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18039 "deprecated in ARMv8"));
18040 now_it
.warn_deprecated
= TRUE
;
18044 const struct depr_insn_mask
*p
= depr_it_insns
;
18046 while (p
->mask
!= 0)
18048 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18050 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18051 "of the following class are deprecated in ARMv8: "
18052 "%s"), p
->description
);
18053 now_it
.warn_deprecated
= TRUE
;
18061 if (now_it
.block_length
> 1)
18063 as_tsktsk (_("IT blocks containing more than one conditional "
18064 "instruction are deprecated in ARMv8"));
18065 now_it
.warn_deprecated
= TRUE
;
18069 is_last
= (now_it
.mask
== 0x10);
18072 now_it
.state
= OUTSIDE_IT_BLOCK
;
18078 force_automatic_it_block_close (void)
18080 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18082 close_automatic_it_block ();
18083 now_it
.state
= OUTSIDE_IT_BLOCK
;
18091 if (!now_it
.state_handled
)
18092 handle_it_state ();
18094 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18097 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18098 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18099 here, hence the "known" in the function name. */
18102 known_t32_only_insn (const struct asm_opcode
*opcode
)
18104 /* Original Thumb-1 wide instruction. */
18105 if (opcode
->tencode
== do_t_blx
18106 || opcode
->tencode
== do_t_branch23
18107 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18108 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18111 /* Wide-only instruction added to ARMv8-M. */
18112 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m
)
18113 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18114 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18115 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18121 /* Whether wide instruction variant can be used if available for a valid OPCODE
18125 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18127 if (known_t32_only_insn (opcode
))
18130 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18131 of variant T3 of B.W is checked in do_t_branch. */
18132 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18133 && opcode
->tencode
== do_t_branch
)
18136 /* Wide instruction variants of all instructions with narrow *and* wide
18137 variants become available with ARMv6t2. Other opcodes are either
18138 narrow-only or wide-only and are thus available if OPCODE is valid. */
18139 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18142 /* OPCODE with narrow only instruction variant or wide variant not
18148 md_assemble (char *str
)
18151 const struct asm_opcode
* opcode
;
18153 /* Align the previous label if needed. */
18154 if (last_label_seen
!= NULL
)
18156 symbol_set_frag (last_label_seen
, frag_now
);
18157 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18158 S_SET_SEGMENT (last_label_seen
, now_seg
);
18161 memset (&inst
, '\0', sizeof (inst
));
18162 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18164 opcode
= opcode_lookup (&p
);
18167 /* It wasn't an instruction, but it might be a register alias of
18168 the form alias .req reg, or a Neon .dn/.qn directive. */
18169 if (! create_register_alias (str
, p
)
18170 && ! create_neon_reg_alias (str
, p
))
18171 as_bad (_("bad instruction `%s'"), str
);
18176 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18177 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18179 /* The value which unconditional instructions should have in place of the
18180 condition field. */
18181 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18185 arm_feature_set variant
;
18187 variant
= cpu_variant
;
18188 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18189 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18190 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18191 /* Check that this instruction is supported for this CPU. */
18192 if (!opcode
->tvariant
18193 || (thumb_mode
== 1
18194 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18196 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18199 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18200 && opcode
->tencode
!= do_t_branch
)
18202 as_bad (_("Thumb does not support conditional execution"));
18206 /* Two things are addressed here:
18207 1) Implicit require narrow instructions on Thumb-1.
18208 This avoids relaxation accidentally introducing Thumb-2
18210 2) Reject wide instructions in non Thumb-2 cores.
18212 Only instructions with narrow and wide variants need to be handled
18213 but selecting all non wide-only instructions is easier. */
18214 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18215 && !t32_insn_ok (variant
, opcode
))
18217 if (inst
.size_req
== 0)
18219 else if (inst
.size_req
== 4)
18221 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18222 as_bad (_("selected processor does not support 32bit wide "
18223 "variant of instruction `%s'"), str
);
18225 as_bad (_("selected processor does not support `%s' in "
18226 "Thumb-2 mode"), str
);
18231 inst
.instruction
= opcode
->tvalue
;
18233 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18235 /* Prepare the it_insn_type for those encodings that don't set
18237 it_fsm_pre_encode ();
18239 opcode
->tencode ();
18241 it_fsm_post_encode ();
18244 if (!(inst
.error
|| inst
.relax
))
18246 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18247 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18248 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18250 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18255 /* Something has gone badly wrong if we try to relax a fixed size
18257 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18259 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18260 *opcode
->tvariant
);
18261 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18262 set those bits when Thumb-2 32-bit instructions are seen. The impact
18263 of relaxable instructions will be considered later after we finish all
18265 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18266 variant
= arm_arch_none
;
18268 variant
= cpu_variant
;
18269 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18270 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18273 check_neon_suffixes
;
18277 mapping_state (MAP_THUMB
);
18280 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18284 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18285 is_bx
= (opcode
->aencode
== do_bx
);
18287 /* Check that this instruction is supported for this CPU. */
18288 if (!(is_bx
&& fix_v4bx
)
18289 && !(opcode
->avariant
&&
18290 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18292 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18297 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18301 inst
.instruction
= opcode
->avalue
;
18302 if (opcode
->tag
== OT_unconditionalF
)
18303 inst
.instruction
|= 0xFU
<< 28;
18305 inst
.instruction
|= inst
.cond
<< 28;
18306 inst
.size
= INSN_SIZE
;
18307 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18309 it_fsm_pre_encode ();
18310 opcode
->aencode ();
18311 it_fsm_post_encode ();
18313 /* Arm mode bx is marked as both v4T and v5 because it's still required
18314 on a hypothetical non-thumb v5 core. */
18316 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18318 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18319 *opcode
->avariant
);
18321 check_neon_suffixes
;
18325 mapping_state (MAP_ARM
);
18330 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18338 check_it_blocks_finished (void)
18343 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18344 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18345 == MANUAL_IT_BLOCK
)
18347 as_warn (_("section '%s' finished with an open IT block."),
18351 if (now_it
.state
== MANUAL_IT_BLOCK
)
18352 as_warn (_("file finished with an open IT block."));
18356 /* Various frobbings of labels and their addresses. */
18359 arm_start_line_hook (void)
18361 last_label_seen
= NULL
;
18365 arm_frob_label (symbolS
* sym
)
18367 last_label_seen
= sym
;
18369 ARM_SET_THUMB (sym
, thumb_mode
);
18371 #if defined OBJ_COFF || defined OBJ_ELF
18372 ARM_SET_INTERWORK (sym
, support_interwork
);
18375 force_automatic_it_block_close ();
18377 /* Note - do not allow local symbols (.Lxxx) to be labelled
18378 as Thumb functions. This is because these labels, whilst
18379 they exist inside Thumb code, are not the entry points for
18380 possible ARM->Thumb calls. Also, these labels can be used
18381 as part of a computed goto or switch statement. eg gcc
18382 can generate code that looks like this:
18384 ldr r2, [pc, .Laaa]
18394 The first instruction loads the address of the jump table.
18395 The second instruction converts a table index into a byte offset.
18396 The third instruction gets the jump address out of the table.
18397 The fourth instruction performs the jump.
18399 If the address stored at .Laaa is that of a symbol which has the
18400 Thumb_Func bit set, then the linker will arrange for this address
18401 to have the bottom bit set, which in turn would mean that the
18402 address computation performed by the third instruction would end
18403 up with the bottom bit set. Since the ARM is capable of unaligned
18404 word loads, the instruction would then load the incorrect address
18405 out of the jump table, and chaos would ensue. */
18406 if (label_is_thumb_function_name
18407 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18408 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18410 /* When the address of a Thumb function is taken the bottom
18411 bit of that address should be set. This will allow
18412 interworking between Arm and Thumb functions to work
18415 THUMB_SET_FUNC (sym
, 1);
18417 label_is_thumb_function_name
= FALSE
;
18420 dwarf2_emit_label (sym
);
18424 arm_data_in_code (void)
18426 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18428 *input_line_pointer
= '/';
18429 input_line_pointer
+= 5;
18430 *input_line_pointer
= 0;
18438 arm_canonicalize_symbol_name (char * name
)
18442 if (thumb_mode
&& (len
= strlen (name
)) > 5
18443 && streq (name
+ len
- 5, "/data"))
18444 *(name
+ len
- 5) = 0;
18449 /* Table of all register names defined by default. The user can
18450 define additional names with .req. Note that all register names
18451 should appear in both upper and lowercase variants. Some registers
18452 also have mixed-case names. */
18454 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18455 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18456 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18457 #define REGSET(p,t) \
18458 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18459 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18460 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18461 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18462 #define REGSETH(p,t) \
18463 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18464 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18465 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18466 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18467 #define REGSET2(p,t) \
18468 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18469 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18470 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18471 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18472 #define SPLRBANK(base,bank,t) \
18473 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18474 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18475 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18476 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18477 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18478 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18480 static const struct reg_entry reg_names
[] =
18482 /* ARM integer registers. */
18483 REGSET(r
, RN
), REGSET(R
, RN
),
18485 /* ATPCS synonyms. */
18486 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18487 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18488 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18490 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18491 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18492 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18494 /* Well-known aliases. */
18495 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18496 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18498 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18499 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18501 /* Coprocessor numbers. */
18502 REGSET(p
, CP
), REGSET(P
, CP
),
18504 /* Coprocessor register numbers. The "cr" variants are for backward
18506 REGSET(c
, CN
), REGSET(C
, CN
),
18507 REGSET(cr
, CN
), REGSET(CR
, CN
),
18509 /* ARM banked registers. */
18510 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18511 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18512 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18513 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18514 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18515 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18516 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18518 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18519 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18520 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18521 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18522 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18523 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18524 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18525 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18527 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18528 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18529 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18530 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18531 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18532 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18533 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18534 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18535 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18537 /* FPA registers. */
18538 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18539 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18541 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18542 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18544 /* VFP SP registers. */
18545 REGSET(s
,VFS
), REGSET(S
,VFS
),
18546 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18548 /* VFP DP Registers. */
18549 REGSET(d
,VFD
), REGSET(D
,VFD
),
18550 /* Extra Neon DP registers. */
18551 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18553 /* Neon QP registers. */
18554 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18556 /* VFP control registers. */
18557 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18558 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18559 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18560 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18561 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18562 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18564 /* Maverick DSP coprocessor registers. */
18565 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18566 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18568 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18569 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18570 REGDEF(dspsc
,0,DSPSC
),
18572 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18573 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18574 REGDEF(DSPSC
,0,DSPSC
),
18576 /* iWMMXt data registers - p0, c0-15. */
18577 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18579 /* iWMMXt control registers - p1, c0-3. */
18580 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18581 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18582 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18583 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18585 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18586 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18587 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18588 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18589 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18591 /* XScale accumulator registers. */
18592 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18598 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18599 within psr_required_here. */
18600 static const struct asm_psr psrs
[] =
18602 /* Backward compatibility notation. Note that "all" is no longer
18603 truly all possible PSR bits. */
18604 {"all", PSR_c
| PSR_f
},
18608 /* Individual flags. */
18614 /* Combinations of flags. */
18615 {"fs", PSR_f
| PSR_s
},
18616 {"fx", PSR_f
| PSR_x
},
18617 {"fc", PSR_f
| PSR_c
},
18618 {"sf", PSR_s
| PSR_f
},
18619 {"sx", PSR_s
| PSR_x
},
18620 {"sc", PSR_s
| PSR_c
},
18621 {"xf", PSR_x
| PSR_f
},
18622 {"xs", PSR_x
| PSR_s
},
18623 {"xc", PSR_x
| PSR_c
},
18624 {"cf", PSR_c
| PSR_f
},
18625 {"cs", PSR_c
| PSR_s
},
18626 {"cx", PSR_c
| PSR_x
},
18627 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18628 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18629 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18630 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18631 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18632 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18633 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18634 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18635 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18636 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18637 {"scf", PSR_s
| PSR_c
| PSR_f
},
18638 {"scx", PSR_s
| PSR_c
| PSR_x
},
18639 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18640 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18641 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18642 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18643 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18644 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18645 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18646 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18647 {"csf", PSR_c
| PSR_s
| PSR_f
},
18648 {"csx", PSR_c
| PSR_s
| PSR_x
},
18649 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18650 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18651 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18652 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18653 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18654 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18655 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18656 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18657 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18658 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18659 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18660 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18661 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18662 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18663 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18664 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18665 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18666 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18667 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18668 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18669 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18670 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18671 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18672 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18673 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18674 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18677 /* Table of V7M psr names. */
18678 static const struct asm_psr v7m_psrs
[] =
18680 {"apsr", 0 }, {"APSR", 0 },
18681 {"iapsr", 1 }, {"IAPSR", 1 },
18682 {"eapsr", 2 }, {"EAPSR", 2 },
18683 {"psr", 3 }, {"PSR", 3 },
18684 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18685 {"ipsr", 5 }, {"IPSR", 5 },
18686 {"epsr", 6 }, {"EPSR", 6 },
18687 {"iepsr", 7 }, {"IEPSR", 7 },
18688 {"msp", 8 }, {"MSP", 8 },
18689 {"psp", 9 }, {"PSP", 9 },
18690 {"primask", 16}, {"PRIMASK", 16},
18691 {"basepri", 17}, {"BASEPRI", 17},
18692 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18693 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18694 {"faultmask", 19}, {"FAULTMASK", 19},
18695 {"control", 20}, {"CONTROL", 20}
18698 /* Table of all shift-in-operand names. */
18699 static const struct asm_shift_name shift_names
[] =
18701 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18702 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18703 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18704 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18705 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18706 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18709 /* Table of all explicit relocation names. */
18711 static struct reloc_entry reloc_names
[] =
18713 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18714 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18715 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18716 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18717 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18718 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18719 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18720 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18721 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18722 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18723 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18724 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18725 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18726 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18727 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18728 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18729 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18730 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18734 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18735 static const struct asm_cond conds
[] =
18739 {"cs", 0x2}, {"hs", 0x2},
18740 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18754 #define UL_BARRIER(L,U,CODE,FEAT) \
18755 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18756 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18758 static struct asm_barrier_opt barrier_opt_names
[] =
18760 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18761 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18762 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18763 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18764 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18765 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18766 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18767 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18768 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18769 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18770 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18771 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18772 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18773 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18774 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18775 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18780 /* Table of ARM-format instructions. */
18782 /* Macros for gluing together operand strings. N.B. In all cases
18783 other than OPS0, the trailing OP_stop comes from default
18784 zero-initialization of the unspecified elements of the array. */
18785 #define OPS0() { OP_stop, }
18786 #define OPS1(a) { OP_##a, }
18787 #define OPS2(a,b) { OP_##a,OP_##b, }
18788 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18789 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18790 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18791 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18793 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18794 This is useful when mixing operands for ARM and THUMB, i.e. using the
18795 MIX_ARM_THUMB_OPERANDS macro.
18796 In order to use these macros, prefix the number of operands with _
18798 #define OPS_1(a) { a, }
18799 #define OPS_2(a,b) { a,b, }
18800 #define OPS_3(a,b,c) { a,b,c, }
18801 #define OPS_4(a,b,c,d) { a,b,c,d, }
18802 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18803 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18805 /* These macros abstract out the exact format of the mnemonic table and
18806 save some repeated characters. */
18808 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18809 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18810 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18811 THUMB_VARIANT, do_##ae, do_##te }
18813 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18814 a T_MNEM_xyz enumerator. */
18815 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18816 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18817 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18818 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18820 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18821 infix after the third character. */
18822 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18823 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18824 THUMB_VARIANT, do_##ae, do_##te }
18825 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18826 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18827 THUMB_VARIANT, do_##ae, do_##te }
18828 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18829 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18830 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18831 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18832 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18833 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18834 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18835 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18837 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18838 field is still 0xE. Many of the Thumb variants can be executed
18839 conditionally, so this is checked separately. */
18840 #define TUE(mnem, op, top, nops, ops, ae, te) \
18841 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18842 THUMB_VARIANT, do_##ae, do_##te }
18844 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18845 Used by mnemonics that have very minimal differences in the encoding for
18846 ARM and Thumb variants and can be handled in a common function. */
18847 #define TUEc(mnem, op, top, nops, ops, en) \
18848 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18849 THUMB_VARIANT, do_##en, do_##en }
18851 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18852 condition code field. */
18853 #define TUF(mnem, op, top, nops, ops, ae, te) \
18854 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18855 THUMB_VARIANT, do_##ae, do_##te }
18857 /* ARM-only variants of all the above. */
18858 #define CE(mnem, op, nops, ops, ae) \
18859 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18861 #define C3(mnem, op, nops, ops, ae) \
18862 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18864 /* Legacy mnemonics that always have conditional infix after the third
18866 #define CL(mnem, op, nops, ops, ae) \
18867 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18868 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18870 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18871 #define cCE(mnem, op, nops, ops, ae) \
18872 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18874 /* Legacy coprocessor instructions where conditional infix and conditional
18875 suffix are ambiguous. For consistency this includes all FPA instructions,
18876 not just the potentially ambiguous ones. */
18877 #define cCL(mnem, op, nops, ops, ae) \
18878 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18879 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18881 /* Coprocessor, takes either a suffix or a position-3 infix
18882 (for an FPA corner case). */
18883 #define C3E(mnem, op, nops, ops, ae) \
18884 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18885 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18887 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18888 { m1 #m2 m3, OPS##nops ops, \
18889 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18890 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18892 #define CM(m1, m2, op, nops, ops, ae) \
18893 xCM_ (m1, , m2, op, nops, ops, ae), \
18894 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18895 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18896 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18897 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18898 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18899 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18900 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18901 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18902 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18903 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18904 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18905 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18906 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18907 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18908 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18909 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18910 xCM_ (m1, le, m2, op, nops, ops, ae), \
18911 xCM_ (m1, al, m2, op, nops, ops, ae)
18913 #define UE(mnem, op, nops, ops, ae) \
18914 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18916 #define UF(mnem, op, nops, ops, ae) \
18917 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18919 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18920 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18921 use the same encoding function for each. */
18922 #define NUF(mnem, op, nops, ops, enc) \
18923 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18924 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18926 /* Neon data processing, version which indirects through neon_enc_tab for
18927 the various overloaded versions of opcodes. */
18928 #define nUF(mnem, op, nops, ops, enc) \
18929 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18930 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18932 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18934 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18935 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18936 THUMB_VARIANT, do_##enc, do_##enc }
18938 #define NCE(mnem, op, nops, ops, enc) \
18939 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18941 #define NCEF(mnem, op, nops, ops, enc) \
18942 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18944 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18945 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18946 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18947 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18949 #define nCE(mnem, op, nops, ops, enc) \
18950 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18952 #define nCEF(mnem, op, nops, ops, enc) \
18953 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18957 static const struct asm_opcode insns
[] =
18959 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18960 #define THUMB_VARIANT & arm_ext_v4t
18961 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18962 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18963 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18964 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18965 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18966 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18967 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18968 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18969 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18970 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18971 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18972 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18973 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18974 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18975 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18976 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18978 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18979 for setting PSR flag bits. They are obsolete in V6 and do not
18980 have Thumb equivalents. */
18981 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18982 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18983 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18984 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18985 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18986 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18987 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18988 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18989 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18991 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18992 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
18993 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18994 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18996 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18997 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18998 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19000 OP_ADDRGLDR
),ldst
, t_ldst
),
19001 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19003 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19004 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19005 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19006 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19007 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19008 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19010 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19011 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19012 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19013 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19016 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19017 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19018 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19019 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19021 /* Thumb-compatibility pseudo ops. */
19022 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19023 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19024 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19025 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19026 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19027 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19028 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19029 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19030 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19031 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19032 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19033 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19035 /* These may simplify to neg. */
19036 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19037 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19039 #undef THUMB_VARIANT
19040 #define THUMB_VARIANT & arm_ext_v6
19042 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19044 /* V1 instructions with no Thumb analogue prior to V6T2. */
19045 #undef THUMB_VARIANT
19046 #define THUMB_VARIANT & arm_ext_v6t2
19048 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19049 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19050 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19052 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19053 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19054 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19055 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19057 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19058 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19060 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19061 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19063 /* V1 instructions with no Thumb analogue at all. */
19064 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19065 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19067 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19068 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19069 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19070 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19071 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19072 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19073 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19074 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19077 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19078 #undef THUMB_VARIANT
19079 #define THUMB_VARIANT & arm_ext_v4t
19081 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19082 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19084 #undef THUMB_VARIANT
19085 #define THUMB_VARIANT & arm_ext_v6t2
19087 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19088 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19090 /* Generic coprocessor instructions. */
19091 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19092 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19093 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19094 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19095 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19096 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19097 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19100 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19102 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19103 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19106 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19107 #undef THUMB_VARIANT
19108 #define THUMB_VARIANT & arm_ext_msr
19110 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19111 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19114 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19115 #undef THUMB_VARIANT
19116 #define THUMB_VARIANT & arm_ext_v6t2
19118 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19119 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19120 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19121 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19122 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19123 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19124 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19125 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19128 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19129 #undef THUMB_VARIANT
19130 #define THUMB_VARIANT & arm_ext_v4t
19132 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19133 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19134 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19135 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19136 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19137 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19140 #define ARM_VARIANT & arm_ext_v4t_5
19142 /* ARM Architecture 4T. */
19143 /* Note: bx (and blx) are required on V5, even if the processor does
19144 not support Thumb. */
19145 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19148 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19149 #undef THUMB_VARIANT
19150 #define THUMB_VARIANT & arm_ext_v5t
19152 /* Note: blx has 2 variants; the .value coded here is for
19153 BLX(2). Only this variant has conditional execution. */
19154 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19155 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19157 #undef THUMB_VARIANT
19158 #define THUMB_VARIANT & arm_ext_v6t2
19160 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19161 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19162 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19163 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19164 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19165 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19166 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19167 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19170 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19171 #undef THUMB_VARIANT
19172 #define THUMB_VARIANT & arm_ext_v5exp
19174 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19175 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19176 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19177 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19179 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19180 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19182 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19183 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19184 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19185 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19187 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19188 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19189 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19190 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19192 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19193 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19195 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19196 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19197 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19198 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19201 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19202 #undef THUMB_VARIANT
19203 #define THUMB_VARIANT & arm_ext_v6t2
19205 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19206 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19208 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19209 ADDRGLDRS
), ldrd
, t_ldstd
),
19211 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19212 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19215 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19217 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19220 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19221 #undef THUMB_VARIANT
19222 #define THUMB_VARIANT & arm_ext_v6
19224 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19225 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19226 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19227 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19228 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19229 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19230 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19231 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19232 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19233 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19235 #undef THUMB_VARIANT
19236 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19238 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19239 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19241 #undef THUMB_VARIANT
19242 #define THUMB_VARIANT & arm_ext_v6t2
19244 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19245 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19247 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19248 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19250 /* ARM V6 not included in V7M. */
19251 #undef THUMB_VARIANT
19252 #define THUMB_VARIANT & arm_ext_v6_notm
19253 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19254 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19255 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19256 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19257 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19258 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19259 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19260 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19261 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19262 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19263 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19264 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19265 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19266 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19267 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19268 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19269 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19270 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19271 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19273 /* ARM V6 not included in V7M (eg. integer SIMD). */
19274 #undef THUMB_VARIANT
19275 #define THUMB_VARIANT & arm_ext_v6_dsp
19276 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19277 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19278 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19279 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19280 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19281 /* Old name for QASX. */
19282 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19283 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19284 /* Old name for QSAX. */
19285 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19286 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19287 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19288 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19289 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19290 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19291 /* Old name for SASX. */
19292 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19293 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19294 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19295 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19296 /* Old name for SHASX. */
19297 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19298 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19299 /* Old name for SHSAX. */
19300 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19301 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19302 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19303 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19304 /* Old name for SSAX. */
19305 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19306 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19307 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19308 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19309 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19310 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19311 /* Old name for UASX. */
19312 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19313 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19314 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19315 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19316 /* Old name for UHASX. */
19317 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19318 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19319 /* Old name for UHSAX. */
19320 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19321 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19322 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19323 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19324 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19325 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19326 /* Old name for UQASX. */
19327 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19328 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19329 /* Old name for UQSAX. */
19330 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19331 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19332 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19333 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19334 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19335 /* Old name for USAX. */
19336 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19337 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19338 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19339 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19340 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19341 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19342 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19343 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19344 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19345 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19346 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19347 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19348 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19349 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19350 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19351 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19352 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19353 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19354 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19355 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19356 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19357 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19358 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19359 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19360 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19361 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19362 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19363 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19364 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19365 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19366 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19367 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19368 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19369 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19372 #define ARM_VARIANT & arm_ext_v6k
19373 #undef THUMB_VARIANT
19374 #define THUMB_VARIANT & arm_ext_v6k
19376 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19377 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19378 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19379 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19381 #undef THUMB_VARIANT
19382 #define THUMB_VARIANT & arm_ext_v6_notm
19383 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19385 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19386 RRnpcb
), strexd
, t_strexd
),
19388 #undef THUMB_VARIANT
19389 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19390 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19392 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19394 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19396 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19398 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19401 #define ARM_VARIANT & arm_ext_sec
19402 #undef THUMB_VARIANT
19403 #define THUMB_VARIANT & arm_ext_sec
19405 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19408 #define ARM_VARIANT & arm_ext_virt
19409 #undef THUMB_VARIANT
19410 #define THUMB_VARIANT & arm_ext_virt
19412 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19413 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19416 #define ARM_VARIANT & arm_ext_pan
19417 #undef THUMB_VARIANT
19418 #define THUMB_VARIANT & arm_ext_pan
19420 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19423 #define ARM_VARIANT & arm_ext_v6t2
19424 #undef THUMB_VARIANT
19425 #define THUMB_VARIANT & arm_ext_v6t2
19427 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19428 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19429 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19430 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19432 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19433 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19435 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19436 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19437 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19438 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19440 #undef THUMB_VARIANT
19441 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19442 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19443 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19445 /* Thumb-only instructions. */
19447 #define ARM_VARIANT NULL
19448 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19449 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19451 /* ARM does not really have an IT instruction, so always allow it.
19452 The opcode is copied from Thumb in order to allow warnings in
19453 -mimplicit-it=[never | arm] modes. */
19455 #define ARM_VARIANT & arm_ext_v1
19456 #undef THUMB_VARIANT
19457 #define THUMB_VARIANT & arm_ext_v6t2
19459 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19460 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19461 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19462 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19463 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19464 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19465 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19466 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19467 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19468 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19469 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19470 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19471 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19472 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19473 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19474 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19475 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19476 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19478 /* Thumb2 only instructions. */
19480 #define ARM_VARIANT NULL
19482 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19483 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19484 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19485 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19486 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19487 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19489 /* Hardware division instructions. */
19491 #define ARM_VARIANT & arm_ext_adiv
19492 #undef THUMB_VARIANT
19493 #define THUMB_VARIANT & arm_ext_div
19495 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19496 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19498 /* ARM V6M/V7 instructions. */
19500 #define ARM_VARIANT & arm_ext_barrier
19501 #undef THUMB_VARIANT
19502 #define THUMB_VARIANT & arm_ext_barrier
19504 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19505 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19506 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19508 /* ARM V7 instructions. */
19510 #define ARM_VARIANT & arm_ext_v7
19511 #undef THUMB_VARIANT
19512 #define THUMB_VARIANT & arm_ext_v7
19514 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19515 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19518 #define ARM_VARIANT & arm_ext_mp
19519 #undef THUMB_VARIANT
19520 #define THUMB_VARIANT & arm_ext_mp
19522 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19524 /* AArchv8 instructions. */
19526 #define ARM_VARIANT & arm_ext_v8
19528 /* Instructions shared between armv8-a and armv8-m. */
19529 #undef THUMB_VARIANT
19530 #define THUMB_VARIANT & arm_ext_atomics
19532 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19533 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19534 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19535 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19536 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19537 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19538 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19539 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19540 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19541 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19543 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19545 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19547 #undef THUMB_VARIANT
19548 #define THUMB_VARIANT & arm_ext_v8
19550 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19551 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19552 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19554 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19556 /* ARMv8 T32 only. */
19558 #define ARM_VARIANT NULL
19559 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19560 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19561 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19563 /* FP for ARMv8. */
19565 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19566 #undef THUMB_VARIANT
19567 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19569 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19570 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19571 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19572 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19573 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19574 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19575 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19576 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19577 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19578 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19579 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19580 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19581 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19582 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19583 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19584 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19585 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19587 /* Crypto v1 extensions. */
19589 #define ARM_VARIANT & fpu_crypto_ext_armv8
19590 #undef THUMB_VARIANT
19591 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19593 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19594 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19595 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19596 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19597 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19598 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19599 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19600 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19601 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19602 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19603 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19604 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19605 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19606 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19609 #define ARM_VARIANT & crc_ext_armv8
19610 #undef THUMB_VARIANT
19611 #define THUMB_VARIANT & crc_ext_armv8
19612 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19613 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19614 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19615 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19616 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19617 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19619 /* ARMv8.2 RAS extension. */
19621 #define ARM_VARIANT & arm_ext_v8_2
19622 #undef THUMB_VARIANT
19623 #define THUMB_VARIANT & arm_ext_v8_2
19624 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19627 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19628 #undef THUMB_VARIANT
19629 #define THUMB_VARIANT NULL
19631 cCE("wfs", e200110
, 1, (RR
), rd
),
19632 cCE("rfs", e300110
, 1, (RR
), rd
),
19633 cCE("wfc", e400110
, 1, (RR
), rd
),
19634 cCE("rfc", e500110
, 1, (RR
), rd
),
19636 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19637 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19638 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19639 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19641 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19642 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19643 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19644 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19646 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19647 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19648 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19649 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19650 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19651 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19652 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19653 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19654 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19655 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19656 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19657 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19659 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19660 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19661 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19662 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19663 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19664 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19665 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19666 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19667 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19668 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19669 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19670 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19672 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19673 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19674 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19675 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19676 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19677 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19678 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19679 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19680 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19681 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19682 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19683 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19685 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19686 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19687 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19688 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19689 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19690 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19691 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19692 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19693 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19694 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19695 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19696 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19698 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19699 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19700 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19701 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19702 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19703 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19704 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19705 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19706 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19707 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19708 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19709 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19711 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19712 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19713 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19714 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19715 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19716 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19717 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19718 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19719 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19720 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19721 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19722 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19724 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19725 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19726 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19727 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19728 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19729 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19730 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19731 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19732 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19733 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19734 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19735 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19737 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19738 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19739 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19740 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19741 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19742 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19743 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19744 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19745 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19746 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19747 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19748 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19750 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19751 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19752 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19753 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19754 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19755 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19756 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19757 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19758 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19759 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19760 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19761 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19763 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19764 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19765 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19766 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19767 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19768 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19769 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19770 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19771 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19772 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19773 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19774 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19776 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19777 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19778 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19779 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19780 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19781 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19782 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19783 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19784 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19785 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19786 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19787 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19789 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19790 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19791 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19792 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19793 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19794 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19795 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19796 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19797 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19798 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19799 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19800 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19802 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19803 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19804 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19805 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19806 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19807 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19808 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19809 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19810 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19811 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19812 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19813 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19815 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19816 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19817 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19818 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19819 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19820 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19821 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19822 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19823 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19824 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19825 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19826 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19828 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19829 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19830 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19831 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19832 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19833 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19834 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19835 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19836 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19837 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19838 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19839 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19841 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19842 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19843 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19844 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19845 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19846 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19847 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19848 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19849 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19850 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19851 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19852 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19854 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19855 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19856 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19857 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19858 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19859 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19860 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19861 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19862 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19863 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19864 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19865 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19867 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19868 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19869 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19870 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19871 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19872 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19873 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19874 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19875 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19876 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19877 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19878 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19880 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19881 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19882 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19883 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19884 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19885 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19886 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19887 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19888 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19889 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19890 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19891 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19893 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19894 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19895 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19896 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19897 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19898 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19899 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19900 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19901 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19902 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19903 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19904 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19906 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19907 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19908 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19909 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19910 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19911 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19912 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19913 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19914 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19915 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19916 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19917 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19919 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19920 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19921 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19922 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19923 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19924 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19925 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19926 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19927 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19928 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19929 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19930 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19932 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19933 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19934 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19935 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19936 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19937 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19938 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19939 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19940 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19941 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19942 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19943 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19945 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19946 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19947 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19948 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19949 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19950 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19951 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19952 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19953 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19954 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19955 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19956 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19958 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19959 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19960 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19961 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19962 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19963 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19964 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19965 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19966 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19967 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19968 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19969 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19971 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19972 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19973 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19974 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19975 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19976 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19977 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19978 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19979 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19980 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19981 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19982 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19984 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19985 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19986 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19987 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19988 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19989 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19990 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19991 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19992 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19993 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19994 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19995 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19997 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19998 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19999 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20000 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20001 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20002 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20003 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20004 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20005 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20006 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20007 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20008 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20010 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20011 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20012 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20013 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20014 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20015 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20016 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20017 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20018 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20019 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20020 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20021 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20023 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20024 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20025 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20026 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20028 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20029 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20030 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20031 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20032 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20033 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20034 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20035 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20036 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20037 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20038 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20039 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20041 /* The implementation of the FIX instruction is broken on some
20042 assemblers, in that it accepts a precision specifier as well as a
20043 rounding specifier, despite the fact that this is meaningless.
20044 To be more compatible, we accept it as well, though of course it
20045 does not set any bits. */
20046 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20047 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20048 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20049 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20050 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20051 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20052 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20053 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20054 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20055 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20056 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20057 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20058 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20060 /* Instructions that were new with the real FPA, call them V2. */
20062 #define ARM_VARIANT & fpu_fpa_ext_v2
20064 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20065 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20066 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20067 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20068 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20069 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20072 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20074 /* Moves and type conversions. */
20075 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20076 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20077 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20078 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20079 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20080 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20081 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20082 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20083 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20084 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20085 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20086 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20087 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20088 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20090 /* Memory operations. */
20091 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20092 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20093 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20094 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20095 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20096 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20097 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20098 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20099 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20100 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20101 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20102 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20103 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20104 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20105 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20106 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20107 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20108 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20110 /* Monadic operations. */
20111 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20112 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20113 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20115 /* Dyadic operations. */
20116 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20117 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20118 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20119 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20120 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20121 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20122 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20123 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20124 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20127 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20128 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20129 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20130 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20132 /* Double precision load/store are still present on single precision
20133 implementations. */
20134 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20135 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20136 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20137 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20138 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20139 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20140 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20141 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20142 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20143 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20146 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20148 /* Moves and type conversions. */
20149 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20150 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20151 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20152 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20153 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20154 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20155 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20156 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20157 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20158 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20159 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20160 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20161 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20163 /* Monadic operations. */
20164 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20165 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20166 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20168 /* Dyadic operations. */
20169 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20170 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20171 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20172 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20173 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20174 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20175 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20176 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20177 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20180 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20181 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20182 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20183 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20186 #define ARM_VARIANT & fpu_vfp_ext_v2
20188 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20189 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20190 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20191 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20193 /* Instructions which may belong to either the Neon or VFP instruction sets.
20194 Individual encoder functions perform additional architecture checks. */
20196 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20197 #undef THUMB_VARIANT
20198 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20200 /* These mnemonics are unique to VFP. */
20201 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20202 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20203 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20204 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20205 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20206 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20207 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20208 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20209 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20210 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20212 /* Mnemonics shared by Neon and VFP. */
20213 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20214 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20215 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20217 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20218 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20220 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20221 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20223 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20224 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20225 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20226 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20227 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20228 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20229 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20230 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20232 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20233 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20234 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20235 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20238 /* NOTE: All VMOV encoding is special-cased! */
20239 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20240 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20243 #define ARM_VARIANT & arm_ext_fp16
20244 #undef THUMB_VARIANT
20245 #define THUMB_VARIANT & arm_ext_fp16
20246 /* New instructions added from v8.2, allowing the extraction and insertion of
20247 the upper 16 bits of a 32-bit vector register. */
20248 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20249 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20251 #undef THUMB_VARIANT
20252 #define THUMB_VARIANT & fpu_neon_ext_v1
20254 #define ARM_VARIANT & fpu_neon_ext_v1
20256 /* Data processing with three registers of the same length. */
20257 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20258 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20259 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20260 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20261 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20262 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20263 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20264 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20265 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20266 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20267 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20268 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20269 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20270 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20271 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20272 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20273 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20274 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20275 /* If not immediate, fall back to neon_dyadic_i64_su.
20276 shl_imm should accept I8 I16 I32 I64,
20277 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20278 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20279 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20280 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20281 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20282 /* Logic ops, types optional & ignored. */
20283 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20284 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20285 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20286 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20287 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20288 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20289 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20290 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20291 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20292 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20293 /* Bitfield ops, untyped. */
20294 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20295 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20296 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20297 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20298 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20299 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20300 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
20301 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20302 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20303 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20304 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20305 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20306 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20307 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20308 back to neon_dyadic_if_su. */
20309 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20310 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20311 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20312 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20313 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20314 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20315 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20316 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20317 /* Comparison. Type I8 I16 I32 F32. */
20318 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20319 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20320 /* As above, D registers only. */
20321 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20322 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20323 /* Int and float variants, signedness unimportant. */
20324 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20325 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20326 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20327 /* Add/sub take types I8 I16 I32 I64 F32. */
20328 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20329 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20330 /* vtst takes sizes 8, 16, 32. */
20331 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20332 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20333 /* VMUL takes I8 I16 I32 F32 P8. */
20334 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20335 /* VQD{R}MULH takes S16 S32. */
20336 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20337 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20338 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20339 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20340 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20341 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20342 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20343 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20344 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20345 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20346 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20347 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20348 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20349 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20350 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20351 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20352 /* ARM v8.1 extension. */
20353 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20354 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20355 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20356 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20358 /* Two address, int/float. Types S8 S16 S32 F32. */
20359 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20360 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20362 /* Data processing with two registers and a shift amount. */
20363 /* Right shifts, and variants with rounding.
20364 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20365 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20366 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20367 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20368 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20369 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20370 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20371 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20372 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20373 /* Shift and insert. Sizes accepted 8 16 32 64. */
20374 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20375 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20376 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20377 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20378 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20379 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20380 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20381 /* Right shift immediate, saturating & narrowing, with rounding variants.
20382 Types accepted S16 S32 S64 U16 U32 U64. */
20383 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20384 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20385 /* As above, unsigned. Types accepted S16 S32 S64. */
20386 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20387 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20388 /* Right shift narrowing. Types accepted I16 I32 I64. */
20389 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20390 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20391 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20392 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20393 /* CVT with optional immediate for fixed-point variant. */
20394 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20396 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20397 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20399 /* Data processing, three registers of different lengths. */
20400 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20401 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20402 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20403 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20404 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20405 /* If not scalar, fall back to neon_dyadic_long.
20406 Vector types as above, scalar types S16 S32 U16 U32. */
20407 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20408 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20409 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20410 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20411 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20412 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20413 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20414 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20415 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20416 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20417 /* Saturating doubling multiplies. Types S16 S32. */
20418 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20419 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20420 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20421 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20422 S16 S32 U16 U32. */
20423 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20425 /* Extract. Size 8. */
20426 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20427 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20429 /* Two registers, miscellaneous. */
20430 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20431 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20432 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20433 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20434 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20435 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20436 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20437 /* Vector replicate. Sizes 8 16 32. */
20438 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20439 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20440 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20441 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20442 /* VMOVN. Types I16 I32 I64. */
20443 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20444 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20445 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20446 /* VQMOVUN. Types S16 S32 S64. */
20447 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20448 /* VZIP / VUZP. Sizes 8 16 32. */
20449 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20450 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20451 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20452 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20453 /* VQABS / VQNEG. Types S8 S16 S32. */
20454 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20455 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20456 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20457 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20458 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20459 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20460 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20461 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20462 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20463 /* Reciprocal estimates. Types U32 F32. */
20464 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20465 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20466 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20467 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20468 /* VCLS. Types S8 S16 S32. */
20469 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20470 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20471 /* VCLZ. Types I8 I16 I32. */
20472 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20473 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20474 /* VCNT. Size 8. */
20475 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20476 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20477 /* Two address, untyped. */
20478 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20479 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20480 /* VTRN. Sizes 8 16 32. */
20481 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20482 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20484 /* Table lookup. Size 8. */
20485 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20486 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20488 #undef THUMB_VARIANT
20489 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20491 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20493 /* Neon element/structure load/store. */
20494 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20495 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20496 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20497 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20498 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20499 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20500 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20501 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20503 #undef THUMB_VARIANT
20504 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20506 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20507 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20508 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20509 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20510 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20511 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20512 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20513 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20514 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20515 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20517 #undef THUMB_VARIANT
20518 #define THUMB_VARIANT & fpu_vfp_ext_v3
20520 #define ARM_VARIANT & fpu_vfp_ext_v3
20522 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20523 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20524 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20525 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20526 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20527 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20528 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20529 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20530 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20533 #define ARM_VARIANT & fpu_vfp_ext_fma
20534 #undef THUMB_VARIANT
20535 #define THUMB_VARIANT & fpu_vfp_ext_fma
20536 /* Mnemonics shared by Neon and VFP. These are included in the
20537 VFP FMA variant; NEON and VFP FMA always includes the NEON
20538 FMA instructions. */
20539 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20540 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20541 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20542 the v form should always be used. */
20543 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20544 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20545 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20546 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20547 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20548 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20550 #undef THUMB_VARIANT
20552 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20554 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20555 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20556 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20557 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20558 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20559 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20560 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20561 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20564 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20566 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20567 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20568 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20569 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20570 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20571 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20572 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20573 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20574 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20575 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20576 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20577 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20578 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20579 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20580 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20581 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20582 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20583 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20584 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20585 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20586 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20587 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20588 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20589 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20590 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20591 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20592 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20593 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20594 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20595 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20596 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20597 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20598 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20599 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20600 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20601 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20602 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20603 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20604 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20605 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20606 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20607 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20608 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20609 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20610 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20611 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20612 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20613 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20614 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20615 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20616 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20617 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20618 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20619 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20620 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20621 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20622 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20623 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20624 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20625 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20626 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20627 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20628 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20629 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20630 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20631 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20632 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20633 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20634 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20635 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20636 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20637 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20638 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20639 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20640 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20641 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20642 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20643 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20644 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20645 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20646 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20647 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20648 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20649 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20650 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20651 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20652 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20653 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20654 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20655 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20656 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20657 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20658 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20659 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20660 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20661 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20662 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20663 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20664 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20665 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20666 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20667 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20668 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20669 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20670 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20671 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20672 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20673 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20674 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20675 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20676 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20677 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20678 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20679 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20680 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20681 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20682 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20683 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20684 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20685 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20686 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20687 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20688 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20689 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20690 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20691 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20692 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20693 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20694 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20695 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20696 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20697 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20698 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20699 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20700 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20701 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20702 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20703 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20704 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20705 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20706 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20707 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20708 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20709 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20710 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20711 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20712 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20713 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20714 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20715 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20716 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20717 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20718 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20719 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20720 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20721 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20722 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20723 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20724 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20725 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20726 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20727 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20730 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20732 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20733 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20734 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20735 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20736 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20737 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20738 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20739 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20740 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20741 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20742 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20743 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20744 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20745 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20746 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20747 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20748 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20749 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20750 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20751 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20752 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20753 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20754 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20755 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20756 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20757 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20758 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20759 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20760 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20761 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20762 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20763 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20764 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20765 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20766 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20767 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20768 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20769 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20770 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20771 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20772 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20773 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20774 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20775 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20776 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20777 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20778 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20779 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20780 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20781 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20782 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20783 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20784 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20785 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20786 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20787 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20788 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20791 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20793 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20794 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20795 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20796 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20797 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20798 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20799 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20800 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20801 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20802 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20803 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20804 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20805 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20806 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20807 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20808 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20809 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20810 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20811 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20812 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20813 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20814 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20815 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20816 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20817 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20818 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20819 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20820 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20821 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20822 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20823 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20824 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20825 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20826 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20827 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20828 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20829 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20830 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20831 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20832 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20833 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20834 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20835 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20836 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20837 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20838 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20839 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20840 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20841 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20842 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20843 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20844 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20845 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20846 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20847 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20848 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20849 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20850 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20851 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20852 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20853 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20854 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20855 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20856 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20857 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20858 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20859 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20860 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20861 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20862 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20863 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20864 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20865 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20866 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20867 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20868 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20871 #define ARM_VARIANT NULL
20872 #undef THUMB_VARIANT
20873 #define THUMB_VARIANT & arm_ext_v8m
20874 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
20875 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
20878 #undef THUMB_VARIANT
20904 /* MD interface: bits in the object file. */
20906 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20907 for use in the a.out file, and stores them in the array pointed to by buf.
20908 This knows about the endian-ness of the target machine and does
20909 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20910 2 (short) and 4 (long) Floating numbers are put out as a series of
20911 LITTLENUMS (shorts, here at least). */
20914 md_number_to_chars (char * buf
, valueT val
, int n
)
20916 if (target_big_endian
)
20917 number_to_chars_bigendian (buf
, val
, n
);
20919 number_to_chars_littleendian (buf
, val
, n
);
20923 md_chars_to_number (char * buf
, int n
)
20926 unsigned char * where
= (unsigned char *) buf
;
20928 if (target_big_endian
)
20933 result
|= (*where
++ & 255);
20941 result
|= (where
[n
] & 255);
20948 /* MD interface: Sections. */
20950 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20951 that an rs_machine_dependent frag may reach. */
20954 arm_frag_max_var (fragS
*fragp
)
20956 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20957 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20959 Note that we generate relaxable instructions even for cases that don't
20960 really need it, like an immediate that's a trivial constant. So we're
20961 overestimating the instruction size for some of those cases. Rather
20962 than putting more intelligence here, it would probably be better to
20963 avoid generating a relaxation frag in the first place when it can be
20964 determined up front that a short instruction will suffice. */
20966 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20970 /* Estimate the size of a frag before relaxing. Assume everything fits in
20974 md_estimate_size_before_relax (fragS
* fragp
,
20975 segT segtype ATTRIBUTE_UNUSED
)
20981 /* Convert a machine dependent frag. */
20984 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20986 unsigned long insn
;
20987 unsigned long old_op
;
20995 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20997 old_op
= bfd_get_16(abfd
, buf
);
20998 if (fragp
->fr_symbol
)
21000 exp
.X_op
= O_symbol
;
21001 exp
.X_add_symbol
= fragp
->fr_symbol
;
21005 exp
.X_op
= O_constant
;
21007 exp
.X_add_number
= fragp
->fr_offset
;
21008 opcode
= fragp
->fr_subtype
;
21011 case T_MNEM_ldr_pc
:
21012 case T_MNEM_ldr_pc2
:
21013 case T_MNEM_ldr_sp
:
21014 case T_MNEM_str_sp
:
21021 if (fragp
->fr_var
== 4)
21023 insn
= THUMB_OP32 (opcode
);
21024 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21026 insn
|= (old_op
& 0x700) << 4;
21030 insn
|= (old_op
& 7) << 12;
21031 insn
|= (old_op
& 0x38) << 13;
21033 insn
|= 0x00000c00;
21034 put_thumb32_insn (buf
, insn
);
21035 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21039 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21041 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21044 if (fragp
->fr_var
== 4)
21046 insn
= THUMB_OP32 (opcode
);
21047 insn
|= (old_op
& 0xf0) << 4;
21048 put_thumb32_insn (buf
, insn
);
21049 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21053 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21054 exp
.X_add_number
-= 4;
21062 if (fragp
->fr_var
== 4)
21064 int r0off
= (opcode
== T_MNEM_mov
21065 || opcode
== T_MNEM_movs
) ? 0 : 8;
21066 insn
= THUMB_OP32 (opcode
);
21067 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21068 insn
|= (old_op
& 0x700) << r0off
;
21069 put_thumb32_insn (buf
, insn
);
21070 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21074 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21079 if (fragp
->fr_var
== 4)
21081 insn
= THUMB_OP32(opcode
);
21082 put_thumb32_insn (buf
, insn
);
21083 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21086 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21090 if (fragp
->fr_var
== 4)
21092 insn
= THUMB_OP32(opcode
);
21093 insn
|= (old_op
& 0xf00) << 14;
21094 put_thumb32_insn (buf
, insn
);
21095 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21098 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21101 case T_MNEM_add_sp
:
21102 case T_MNEM_add_pc
:
21103 case T_MNEM_inc_sp
:
21104 case T_MNEM_dec_sp
:
21105 if (fragp
->fr_var
== 4)
21107 /* ??? Choose between add and addw. */
21108 insn
= THUMB_OP32 (opcode
);
21109 insn
|= (old_op
& 0xf0) << 4;
21110 put_thumb32_insn (buf
, insn
);
21111 if (opcode
== T_MNEM_add_pc
)
21112 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21114 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21117 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21125 if (fragp
->fr_var
== 4)
21127 insn
= THUMB_OP32 (opcode
);
21128 insn
|= (old_op
& 0xf0) << 4;
21129 insn
|= (old_op
& 0xf) << 16;
21130 put_thumb32_insn (buf
, insn
);
21131 if (insn
& (1 << 20))
21132 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21134 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21137 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21143 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21144 (enum bfd_reloc_code_real
) reloc_type
);
21145 fixp
->fx_file
= fragp
->fr_file
;
21146 fixp
->fx_line
= fragp
->fr_line
;
21147 fragp
->fr_fix
+= fragp
->fr_var
;
21149 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21150 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21151 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21152 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21155 /* Return the size of a relaxable immediate operand instruction.
21156 SHIFT and SIZE specify the form of the allowable immediate. */
21158 relax_immediate (fragS
*fragp
, int size
, int shift
)
21164 /* ??? Should be able to do better than this. */
21165 if (fragp
->fr_symbol
)
21168 low
= (1 << shift
) - 1;
21169 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21170 offset
= fragp
->fr_offset
;
21171 /* Force misaligned offsets to 32-bit variant. */
21174 if (offset
& ~mask
)
21179 /* Get the address of a symbol during relaxation. */
21181 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21187 sym
= fragp
->fr_symbol
;
21188 sym_frag
= symbol_get_frag (sym
);
21189 know (S_GET_SEGMENT (sym
) != absolute_section
21190 || sym_frag
== &zero_address_frag
);
21191 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21193 /* If frag has yet to be reached on this pass, assume it will
21194 move by STRETCH just as we did. If this is not so, it will
21195 be because some frag between grows, and that will force
21199 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21203 /* Adjust stretch for any alignment frag. Note that if have
21204 been expanding the earlier code, the symbol may be
21205 defined in what appears to be an earlier frag. FIXME:
21206 This doesn't handle the fr_subtype field, which specifies
21207 a maximum number of bytes to skip when doing an
21209 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21211 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21214 stretch
= - ((- stretch
)
21215 & ~ ((1 << (int) f
->fr_offset
) - 1));
21217 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21229 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21232 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21237 /* Assume worst case for symbols not known to be in the same section. */
21238 if (fragp
->fr_symbol
== NULL
21239 || !S_IS_DEFINED (fragp
->fr_symbol
)
21240 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21241 || S_IS_WEAK (fragp
->fr_symbol
))
21244 val
= relaxed_symbol_addr (fragp
, stretch
);
21245 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21246 addr
= (addr
+ 4) & ~3;
21247 /* Force misaligned targets to 32-bit variant. */
21251 if (val
< 0 || val
> 1020)
21256 /* Return the size of a relaxable add/sub immediate instruction. */
21258 relax_addsub (fragS
*fragp
, asection
*sec
)
21263 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21264 op
= bfd_get_16(sec
->owner
, buf
);
21265 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21266 return relax_immediate (fragp
, 8, 0);
21268 return relax_immediate (fragp
, 3, 0);
21271 /* Return TRUE iff the definition of symbol S could be pre-empted
21272 (overridden) at link or load time. */
21274 symbol_preemptible (symbolS
*s
)
21276 /* Weak symbols can always be pre-empted. */
21280 /* Non-global symbols cannot be pre-empted. */
21281 if (! S_IS_EXTERNAL (s
))
21285 /* In ELF, a global symbol can be marked protected, or private. In that
21286 case it can't be pre-empted (other definitions in the same link unit
21287 would violate the ODR). */
21288 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21292 /* Other global symbols might be pre-empted. */
21296 /* Return the size of a relaxable branch instruction. BITS is the
21297 size of the offset field in the narrow instruction. */
21300 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21306 /* Assume worst case for symbols not known to be in the same section. */
21307 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21308 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21309 || S_IS_WEAK (fragp
->fr_symbol
))
21313 /* A branch to a function in ARM state will require interworking. */
21314 if (S_IS_DEFINED (fragp
->fr_symbol
)
21315 && ARM_IS_FUNC (fragp
->fr_symbol
))
21319 if (symbol_preemptible (fragp
->fr_symbol
))
21322 val
= relaxed_symbol_addr (fragp
, stretch
);
21323 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21326 /* Offset is a signed value *2 */
21328 if (val
>= limit
|| val
< -limit
)
21334 /* Relax a machine dependent frag. This returns the amount by which
21335 the current size of the frag should change. */
21338 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21343 oldsize
= fragp
->fr_var
;
21344 switch (fragp
->fr_subtype
)
21346 case T_MNEM_ldr_pc2
:
21347 newsize
= relax_adr (fragp
, sec
, stretch
);
21349 case T_MNEM_ldr_pc
:
21350 case T_MNEM_ldr_sp
:
21351 case T_MNEM_str_sp
:
21352 newsize
= relax_immediate (fragp
, 8, 2);
21356 newsize
= relax_immediate (fragp
, 5, 2);
21360 newsize
= relax_immediate (fragp
, 5, 1);
21364 newsize
= relax_immediate (fragp
, 5, 0);
21367 newsize
= relax_adr (fragp
, sec
, stretch
);
21373 newsize
= relax_immediate (fragp
, 8, 0);
21376 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21379 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21381 case T_MNEM_add_sp
:
21382 case T_MNEM_add_pc
:
21383 newsize
= relax_immediate (fragp
, 8, 2);
21385 case T_MNEM_inc_sp
:
21386 case T_MNEM_dec_sp
:
21387 newsize
= relax_immediate (fragp
, 7, 2);
21393 newsize
= relax_addsub (fragp
, sec
);
21399 fragp
->fr_var
= newsize
;
21400 /* Freeze wide instructions that are at or before the same location as
21401 in the previous pass. This avoids infinite loops.
21402 Don't freeze them unconditionally because targets may be artificially
21403 misaligned by the expansion of preceding frags. */
21404 if (stretch
<= 0 && newsize
> 2)
21406 md_convert_frag (sec
->owner
, sec
, fragp
);
21410 return newsize
- oldsize
;
21413 /* Round up a section size to the appropriate boundary. */
21416 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21419 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21420 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21422 /* For a.out, force the section size to be aligned. If we don't do
21423 this, BFD will align it for us, but it will not write out the
21424 final bytes of the section. This may be a bug in BFD, but it is
21425 easier to fix it here since that is how the other a.out targets
21429 align
= bfd_get_section_alignment (stdoutput
, segment
);
21430 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21437 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21438 of an rs_align_code fragment. */
21441 arm_handle_align (fragS
* fragP
)
21443 static char const arm_noop
[2][2][4] =
21446 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21447 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21450 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21451 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21454 static char const thumb_noop
[2][2][2] =
21457 {0xc0, 0x46}, /* LE */
21458 {0x46, 0xc0}, /* BE */
21461 {0x00, 0xbf}, /* LE */
21462 {0xbf, 0x00} /* BE */
21465 static char const wide_thumb_noop
[2][4] =
21466 { /* Wide Thumb-2 */
21467 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21468 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21471 unsigned bytes
, fix
, noop_size
;
21474 const char *narrow_noop
= NULL
;
21479 if (fragP
->fr_type
!= rs_align_code
)
21482 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21483 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21486 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21487 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21489 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21491 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21493 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21494 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21496 narrow_noop
= thumb_noop
[1][target_big_endian
];
21497 noop
= wide_thumb_noop
[target_big_endian
];
21500 noop
= thumb_noop
[0][target_big_endian
];
21508 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21509 ? selected_cpu
: arm_arch_none
,
21511 [target_big_endian
];
21518 fragP
->fr_var
= noop_size
;
21520 if (bytes
& (noop_size
- 1))
21522 fix
= bytes
& (noop_size
- 1);
21524 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21526 memset (p
, 0, fix
);
21533 if (bytes
& noop_size
)
21535 /* Insert a narrow noop. */
21536 memcpy (p
, narrow_noop
, noop_size
);
21538 bytes
-= noop_size
;
21542 /* Use wide noops for the remainder */
21546 while (bytes
>= noop_size
)
21548 memcpy (p
, noop
, noop_size
);
21550 bytes
-= noop_size
;
21554 fragP
->fr_fix
+= fix
;
21557 /* Called from md_do_align. Used to create an alignment
21558 frag in a code section. */
21561 arm_frag_align_code (int n
, int max
)
21565 /* We assume that there will never be a requirement
21566 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21567 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21572 _("alignments greater than %d bytes not supported in .text sections."),
21573 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21574 as_fatal ("%s", err_msg
);
21577 p
= frag_var (rs_align_code
,
21578 MAX_MEM_FOR_RS_ALIGN_CODE
,
21580 (relax_substateT
) max
,
21587 /* Perform target specific initialisation of a frag.
21588 Note - despite the name this initialisation is not done when the frag
21589 is created, but only when its type is assigned. A frag can be created
21590 and used a long time before its type is set, so beware of assuming that
21591 this initialisationis performed first. */
21595 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21597 /* Record whether this frag is in an ARM or a THUMB area. */
21598 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21601 #else /* OBJ_ELF is defined. */
21603 arm_init_frag (fragS
* fragP
, int max_chars
)
21605 int frag_thumb_mode
;
21607 /* If the current ARM vs THUMB mode has not already
21608 been recorded into this frag then do so now. */
21609 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21610 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21612 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21614 /* Record a mapping symbol for alignment frags. We will delete this
21615 later if the alignment ends up empty. */
21616 switch (fragP
->fr_type
)
21619 case rs_align_test
:
21621 mapping_state_2 (MAP_DATA
, max_chars
);
21623 case rs_align_code
:
21624 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21631 /* When we change sections we need to issue a new mapping symbol. */
21634 arm_elf_change_section (void)
21636 /* Link an unlinked unwind index table section to the .text section. */
21637 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21638 && elf_linked_to_section (now_seg
) == NULL
)
21639 elf_linked_to_section (now_seg
) = text_section
;
21643 arm_elf_section_type (const char * str
, size_t len
)
21645 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21646 return SHT_ARM_EXIDX
;
21651 /* Code to deal with unwinding tables. */
21653 static void add_unwind_adjustsp (offsetT
);
21655 /* Generate any deferred unwind frame offset. */
21658 flush_pending_unwind (void)
21662 offset
= unwind
.pending_offset
;
21663 unwind
.pending_offset
= 0;
21665 add_unwind_adjustsp (offset
);
21668 /* Add an opcode to this list for this function. Two-byte opcodes should
21669 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21673 add_unwind_opcode (valueT op
, int length
)
21675 /* Add any deferred stack adjustment. */
21676 if (unwind
.pending_offset
)
21677 flush_pending_unwind ();
21679 unwind
.sp_restored
= 0;
21681 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21683 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21684 if (unwind
.opcodes
)
21685 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21686 unwind
.opcode_alloc
);
21688 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21693 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21695 unwind
.opcode_count
++;
21699 /* Add unwind opcodes to adjust the stack pointer. */
21702 add_unwind_adjustsp (offsetT offset
)
21706 if (offset
> 0x200)
21708 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21713 /* Long form: 0xb2, uleb128. */
21714 /* This might not fit in a word so add the individual bytes,
21715 remembering the list is built in reverse order. */
21716 o
= (valueT
) ((offset
- 0x204) >> 2);
21718 add_unwind_opcode (0, 1);
21720 /* Calculate the uleb128 encoding of the offset. */
21724 bytes
[n
] = o
& 0x7f;
21730 /* Add the insn. */
21732 add_unwind_opcode (bytes
[n
- 1], 1);
21733 add_unwind_opcode (0xb2, 1);
21735 else if (offset
> 0x100)
21737 /* Two short opcodes. */
21738 add_unwind_opcode (0x3f, 1);
21739 op
= (offset
- 0x104) >> 2;
21740 add_unwind_opcode (op
, 1);
21742 else if (offset
> 0)
21744 /* Short opcode. */
21745 op
= (offset
- 4) >> 2;
21746 add_unwind_opcode (op
, 1);
21748 else if (offset
< 0)
21751 while (offset
> 0x100)
21753 add_unwind_opcode (0x7f, 1);
21756 op
= ((offset
- 4) >> 2) | 0x40;
21757 add_unwind_opcode (op
, 1);
21761 /* Finish the list of unwind opcodes for this function. */
21763 finish_unwind_opcodes (void)
21767 if (unwind
.fp_used
)
21769 /* Adjust sp as necessary. */
21770 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21771 flush_pending_unwind ();
21773 /* After restoring sp from the frame pointer. */
21774 op
= 0x90 | unwind
.fp_reg
;
21775 add_unwind_opcode (op
, 1);
21778 flush_pending_unwind ();
21782 /* Start an exception table entry. If idx is nonzero this is an index table
21786 start_unwind_section (const segT text_seg
, int idx
)
21788 const char * text_name
;
21789 const char * prefix
;
21790 const char * prefix_once
;
21791 const char * group_name
;
21795 size_t sec_name_len
;
21802 prefix
= ELF_STRING_ARM_unwind
;
21803 prefix_once
= ELF_STRING_ARM_unwind_once
;
21804 type
= SHT_ARM_EXIDX
;
21808 prefix
= ELF_STRING_ARM_unwind_info
;
21809 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21810 type
= SHT_PROGBITS
;
21813 text_name
= segment_name (text_seg
);
21814 if (streq (text_name
, ".text"))
21817 if (strncmp (text_name
, ".gnu.linkonce.t.",
21818 strlen (".gnu.linkonce.t.")) == 0)
21820 prefix
= prefix_once
;
21821 text_name
+= strlen (".gnu.linkonce.t.");
21824 prefix_len
= strlen (prefix
);
21825 text_len
= strlen (text_name
);
21826 sec_name_len
= prefix_len
+ text_len
;
21827 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21828 memcpy (sec_name
, prefix
, prefix_len
);
21829 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21830 sec_name
[prefix_len
+ text_len
] = '\0';
21836 /* Handle COMDAT group. */
21837 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21839 group_name
= elf_group_name (text_seg
);
21840 if (group_name
== NULL
)
21842 as_bad (_("Group section `%s' has no group signature"),
21843 segment_name (text_seg
));
21844 ignore_rest_of_line ();
21847 flags
|= SHF_GROUP
;
21851 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21853 /* Set the section link for index tables. */
21855 elf_linked_to_section (now_seg
) = text_seg
;
21859 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21860 personality routine data. Returns zero, or the index table value for
21861 an inline entry. */
21864 create_unwind_entry (int have_data
)
21869 /* The current word of data. */
21871 /* The number of bytes left in this word. */
21874 finish_unwind_opcodes ();
21876 /* Remember the current text section. */
21877 unwind
.saved_seg
= now_seg
;
21878 unwind
.saved_subseg
= now_subseg
;
21880 start_unwind_section (now_seg
, 0);
21882 if (unwind
.personality_routine
== NULL
)
21884 if (unwind
.personality_index
== -2)
21887 as_bad (_("handlerdata in cantunwind frame"));
21888 return 1; /* EXIDX_CANTUNWIND. */
21891 /* Use a default personality routine if none is specified. */
21892 if (unwind
.personality_index
== -1)
21894 if (unwind
.opcode_count
> 3)
21895 unwind
.personality_index
= 1;
21897 unwind
.personality_index
= 0;
21900 /* Space for the personality routine entry. */
21901 if (unwind
.personality_index
== 0)
21903 if (unwind
.opcode_count
> 3)
21904 as_bad (_("too many unwind opcodes for personality routine 0"));
21908 /* All the data is inline in the index table. */
21911 while (unwind
.opcode_count
> 0)
21913 unwind
.opcode_count
--;
21914 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21918 /* Pad with "finish" opcodes. */
21920 data
= (data
<< 8) | 0xb0;
21927 /* We get two opcodes "free" in the first word. */
21928 size
= unwind
.opcode_count
- 2;
21932 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21933 if (unwind
.personality_index
!= -1)
21935 as_bad (_("attempt to recreate an unwind entry"));
21939 /* An extra byte is required for the opcode count. */
21940 size
= unwind
.opcode_count
+ 1;
21943 size
= (size
+ 3) >> 2;
21945 as_bad (_("too many unwind opcodes"));
21947 frag_align (2, 0, 0);
21948 record_alignment (now_seg
, 2);
21949 unwind
.table_entry
= expr_build_dot ();
21951 /* Allocate the table entry. */
21952 ptr
= frag_more ((size
<< 2) + 4);
21953 /* PR 13449: Zero the table entries in case some of them are not used. */
21954 memset (ptr
, 0, (size
<< 2) + 4);
21955 where
= frag_now_fix () - ((size
<< 2) + 4);
21957 switch (unwind
.personality_index
)
21960 /* ??? Should this be a PLT generating relocation? */
21961 /* Custom personality routine. */
21962 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21963 BFD_RELOC_ARM_PREL31
);
21968 /* Set the first byte to the number of additional words. */
21969 data
= size
> 0 ? size
- 1 : 0;
21973 /* ABI defined personality routines. */
21975 /* Three opcodes bytes are packed into the first word. */
21982 /* The size and first two opcode bytes go in the first word. */
21983 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21988 /* Should never happen. */
21992 /* Pack the opcodes into words (MSB first), reversing the list at the same
21994 while (unwind
.opcode_count
> 0)
21998 md_number_to_chars (ptr
, data
, 4);
22003 unwind
.opcode_count
--;
22005 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22008 /* Finish off the last word. */
22011 /* Pad with "finish" opcodes. */
22013 data
= (data
<< 8) | 0xb0;
22015 md_number_to_chars (ptr
, data
, 4);
22020 /* Add an empty descriptor if there is no user-specified data. */
22021 ptr
= frag_more (4);
22022 md_number_to_chars (ptr
, 0, 4);
22029 /* Initialize the DWARF-2 unwind information for this procedure. */
22032 tc_arm_frame_initial_instructions (void)
22034 cfi_add_CFA_def_cfa (REG_SP
, 0);
22036 #endif /* OBJ_ELF */
22038 /* Convert REGNAME to a DWARF-2 register number. */
22041 tc_arm_regname_to_dw2regnum (char *regname
)
22043 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22047 /* PR 16694: Allow VFP registers as well. */
22048 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22052 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22061 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22065 exp
.X_op
= O_secrel
;
22066 exp
.X_add_symbol
= symbol
;
22067 exp
.X_add_number
= 0;
22068 emit_expr (&exp
, size
);
22072 /* MD interface: Symbol and relocation handling. */
22074 /* Return the address within the segment that a PC-relative fixup is
22075 relative to. For ARM, PC-relative fixups applied to instructions
22076 are generally relative to the location of the fixup plus 8 bytes.
22077 Thumb branches are offset by 4, and Thumb loads relative to PC
22078 require special handling. */
22081 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22083 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22085 /* If this is pc-relative and we are going to emit a relocation
22086 then we just want to put out any pipeline compensation that the linker
22087 will need. Otherwise we want to use the calculated base.
22088 For WinCE we skip the bias for externals as well, since this
22089 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22091 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22092 || (arm_force_relocation (fixP
)
22094 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22100 switch (fixP
->fx_r_type
)
22102 /* PC relative addressing on the Thumb is slightly odd as the
22103 bottom two bits of the PC are forced to zero for the
22104 calculation. This happens *after* application of the
22105 pipeline offset. However, Thumb adrl already adjusts for
22106 this, so we need not do it again. */
22107 case BFD_RELOC_ARM_THUMB_ADD
:
22110 case BFD_RELOC_ARM_THUMB_OFFSET
:
22111 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22112 case BFD_RELOC_ARM_T32_ADD_PC12
:
22113 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22114 return (base
+ 4) & ~3;
22116 /* Thumb branches are simply offset by +4. */
22117 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22118 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22119 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22120 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22121 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22124 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22126 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22127 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22128 && ARM_IS_FUNC (fixP
->fx_addsy
)
22129 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22130 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22133 /* BLX is like branches above, but forces the low two bits of PC to
22135 case BFD_RELOC_THUMB_PCREL_BLX
:
22137 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22138 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22139 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22140 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22141 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22142 return (base
+ 4) & ~3;
22144 /* ARM mode branches are offset by +8. However, the Windows CE
22145 loader expects the relocation not to take this into account. */
22146 case BFD_RELOC_ARM_PCREL_BLX
:
22148 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22149 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22150 && ARM_IS_FUNC (fixP
->fx_addsy
)
22151 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22152 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22155 case BFD_RELOC_ARM_PCREL_CALL
:
22157 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22158 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22159 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22160 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22161 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22164 case BFD_RELOC_ARM_PCREL_BRANCH
:
22165 case BFD_RELOC_ARM_PCREL_JUMP
:
22166 case BFD_RELOC_ARM_PLT32
:
22168 /* When handling fixups immediately, because we have already
22169 discovered the value of a symbol, or the address of the frag involved
22170 we must account for the offset by +8, as the OS loader will never see the reloc.
22171 see fixup_segment() in write.c
22172 The S_IS_EXTERNAL test handles the case of global symbols.
22173 Those need the calculated base, not just the pipe compensation the linker will need. */
22175 && fixP
->fx_addsy
!= NULL
22176 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22177 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22185 /* ARM mode loads relative to PC are also offset by +8. Unlike
22186 branches, the Windows CE loader *does* expect the relocation
22187 to take this into account. */
22188 case BFD_RELOC_ARM_OFFSET_IMM
:
22189 case BFD_RELOC_ARM_OFFSET_IMM8
:
22190 case BFD_RELOC_ARM_HWLITERAL
:
22191 case BFD_RELOC_ARM_LITERAL
:
22192 case BFD_RELOC_ARM_CP_OFF_IMM
:
22196 /* Other PC-relative relocations are un-offset. */
22202 static bfd_boolean flag_warn_syms
= TRUE
;
22205 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22207 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22208 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22209 does mean that the resulting code might be very confusing to the reader.
22210 Also this warning can be triggered if the user omits an operand before
22211 an immediate address, eg:
22215 GAS treats this as an assignment of the value of the symbol foo to a
22216 symbol LDR, and so (without this code) it will not issue any kind of
22217 warning or error message.
22219 Note - ARM instructions are case-insensitive but the strings in the hash
22220 table are all stored in lower case, so we must first ensure that name is
22222 if (flag_warn_syms
&& arm_ops_hsh
)
22224 char * nbuf
= strdup (name
);
22227 for (p
= nbuf
; *p
; p
++)
22229 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22231 static struct hash_control
* already_warned
= NULL
;
22233 if (already_warned
== NULL
)
22234 already_warned
= hash_new ();
22235 /* Only warn about the symbol once. To keep the code
22236 simple we let hash_insert do the lookup for us. */
22237 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22238 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22247 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22248 Otherwise we have no need to default values of symbols. */
22251 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22254 if (name
[0] == '_' && name
[1] == 'G'
22255 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22259 if (symbol_find (name
))
22260 as_bad (_("GOT already in the symbol table"));
22262 GOT_symbol
= symbol_new (name
, undefined_section
,
22263 (valueT
) 0, & zero_address_frag
);
22273 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22274 computed as two separate immediate values, added together. We
22275 already know that this value cannot be computed by just one ARM
22278 static unsigned int
22279 validate_immediate_twopart (unsigned int val
,
22280 unsigned int * highpart
)
22285 for (i
= 0; i
< 32; i
+= 2)
22286 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22292 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22294 else if (a
& 0xff0000)
22296 if (a
& 0xff000000)
22298 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22302 gas_assert (a
& 0xff000000);
22303 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22306 return (a
& 0xff) | (i
<< 7);
22313 validate_offset_imm (unsigned int val
, int hwse
)
22315 if ((hwse
&& val
> 255) || val
> 4095)
22320 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22321 negative immediate constant by altering the instruction. A bit of
22326 by inverting the second operand, and
22329 by negating the second operand. */
22332 negate_data_op (unsigned long * instruction
,
22333 unsigned long value
)
22336 unsigned long negated
, inverted
;
22338 negated
= encode_arm_immediate (-value
);
22339 inverted
= encode_arm_immediate (~value
);
22341 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22344 /* First negates. */
22345 case OPCODE_SUB
: /* ADD <-> SUB */
22346 new_inst
= OPCODE_ADD
;
22351 new_inst
= OPCODE_SUB
;
22355 case OPCODE_CMP
: /* CMP <-> CMN */
22356 new_inst
= OPCODE_CMN
;
22361 new_inst
= OPCODE_CMP
;
22365 /* Now Inverted ops. */
22366 case OPCODE_MOV
: /* MOV <-> MVN */
22367 new_inst
= OPCODE_MVN
;
22372 new_inst
= OPCODE_MOV
;
22376 case OPCODE_AND
: /* AND <-> BIC */
22377 new_inst
= OPCODE_BIC
;
22382 new_inst
= OPCODE_AND
;
22386 case OPCODE_ADC
: /* ADC <-> SBC */
22387 new_inst
= OPCODE_SBC
;
22392 new_inst
= OPCODE_ADC
;
22396 /* We cannot do anything. */
22401 if (value
== (unsigned) FAIL
)
22404 *instruction
&= OPCODE_MASK
;
22405 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22409 /* Like negate_data_op, but for Thumb-2. */
22411 static unsigned int
22412 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22416 unsigned int negated
, inverted
;
22418 negated
= encode_thumb32_immediate (-value
);
22419 inverted
= encode_thumb32_immediate (~value
);
22421 rd
= (*instruction
>> 8) & 0xf;
22422 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22425 /* ADD <-> SUB. Includes CMP <-> CMN. */
22426 case T2_OPCODE_SUB
:
22427 new_inst
= T2_OPCODE_ADD
;
22431 case T2_OPCODE_ADD
:
22432 new_inst
= T2_OPCODE_SUB
;
22436 /* ORR <-> ORN. Includes MOV <-> MVN. */
22437 case T2_OPCODE_ORR
:
22438 new_inst
= T2_OPCODE_ORN
;
22442 case T2_OPCODE_ORN
:
22443 new_inst
= T2_OPCODE_ORR
;
22447 /* AND <-> BIC. TST has no inverted equivalent. */
22448 case T2_OPCODE_AND
:
22449 new_inst
= T2_OPCODE_BIC
;
22456 case T2_OPCODE_BIC
:
22457 new_inst
= T2_OPCODE_AND
;
22462 case T2_OPCODE_ADC
:
22463 new_inst
= T2_OPCODE_SBC
;
22467 case T2_OPCODE_SBC
:
22468 new_inst
= T2_OPCODE_ADC
;
22472 /* We cannot do anything. */
22477 if (value
== (unsigned int)FAIL
)
22480 *instruction
&= T2_OPCODE_MASK
;
22481 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22485 /* Read a 32-bit thumb instruction from buf. */
22486 static unsigned long
22487 get_thumb32_insn (char * buf
)
22489 unsigned long insn
;
22490 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22491 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22497 /* We usually want to set the low bit on the address of thumb function
22498 symbols. In particular .word foo - . should have the low bit set.
22499 Generic code tries to fold the difference of two symbols to
22500 a constant. Prevent this and force a relocation when the first symbols
22501 is a thumb function. */
22504 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22506 if (op
== O_subtract
22507 && l
->X_op
== O_symbol
22508 && r
->X_op
== O_symbol
22509 && THUMB_IS_FUNC (l
->X_add_symbol
))
22511 l
->X_op
= O_subtract
;
22512 l
->X_op_symbol
= r
->X_add_symbol
;
22513 l
->X_add_number
-= r
->X_add_number
;
22517 /* Process as normal. */
22521 /* Encode Thumb2 unconditional branches and calls. The encoding
22522 for the 2 are identical for the immediate values. */
22525 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22527 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22530 addressT S
, I1
, I2
, lo
, hi
;
22532 S
= (value
>> 24) & 0x01;
22533 I1
= (value
>> 23) & 0x01;
22534 I2
= (value
>> 22) & 0x01;
22535 hi
= (value
>> 12) & 0x3ff;
22536 lo
= (value
>> 1) & 0x7ff;
22537 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22538 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22539 newval
|= (S
<< 10) | hi
;
22540 newval2
&= ~T2I1I2MASK
;
22541 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22542 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22543 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22547 md_apply_fix (fixS
* fixP
,
22551 offsetT value
= * valP
;
22553 unsigned int newimm
;
22554 unsigned long temp
;
22556 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22558 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22560 /* Note whether this will delete the relocation. */
22562 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22565 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22566 consistency with the behaviour on 32-bit hosts. Remember value
22568 value
&= 0xffffffff;
22569 value
^= 0x80000000;
22570 value
-= 0x80000000;
22573 fixP
->fx_addnumber
= value
;
22575 /* Same treatment for fixP->fx_offset. */
22576 fixP
->fx_offset
&= 0xffffffff;
22577 fixP
->fx_offset
^= 0x80000000;
22578 fixP
->fx_offset
-= 0x80000000;
22580 switch (fixP
->fx_r_type
)
22582 case BFD_RELOC_NONE
:
22583 /* This will need to go in the object file. */
22587 case BFD_RELOC_ARM_IMMEDIATE
:
22588 /* We claim that this fixup has been processed here,
22589 even if in fact we generate an error because we do
22590 not have a reloc for it, so tc_gen_reloc will reject it. */
22593 if (fixP
->fx_addsy
)
22595 const char *msg
= 0;
22597 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22598 msg
= _("undefined symbol %s used as an immediate value");
22599 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22600 msg
= _("symbol %s is in a different section");
22601 else if (S_IS_WEAK (fixP
->fx_addsy
))
22602 msg
= _("symbol %s is weak and may be overridden later");
22606 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22607 msg
, S_GET_NAME (fixP
->fx_addsy
));
22612 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22614 /* If the offset is negative, we should use encoding A2 for ADR. */
22615 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22616 newimm
= negate_data_op (&temp
, value
);
22619 newimm
= encode_arm_immediate (value
);
22621 /* If the instruction will fail, see if we can fix things up by
22622 changing the opcode. */
22623 if (newimm
== (unsigned int) FAIL
)
22624 newimm
= negate_data_op (&temp
, value
);
22627 if (newimm
== (unsigned int) FAIL
)
22629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22630 _("invalid constant (%lx) after fixup"),
22631 (unsigned long) value
);
22635 newimm
|= (temp
& 0xfffff000);
22636 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22639 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22641 unsigned int highpart
= 0;
22642 unsigned int newinsn
= 0xe1a00000; /* nop. */
22644 if (fixP
->fx_addsy
)
22646 const char *msg
= 0;
22648 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22649 msg
= _("undefined symbol %s used as an immediate value");
22650 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22651 msg
= _("symbol %s is in a different section");
22652 else if (S_IS_WEAK (fixP
->fx_addsy
))
22653 msg
= _("symbol %s is weak and may be overridden later");
22657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22658 msg
, S_GET_NAME (fixP
->fx_addsy
));
22663 newimm
= encode_arm_immediate (value
);
22664 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22666 /* If the instruction will fail, see if we can fix things up by
22667 changing the opcode. */
22668 if (newimm
== (unsigned int) FAIL
22669 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22671 /* No ? OK - try using two ADD instructions to generate
22673 newimm
= validate_immediate_twopart (value
, & highpart
);
22675 /* Yes - then make sure that the second instruction is
22677 if (newimm
!= (unsigned int) FAIL
)
22679 /* Still No ? Try using a negated value. */
22680 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22681 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22682 /* Otherwise - give up. */
22685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22686 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22691 /* Replace the first operand in the 2nd instruction (which
22692 is the PC) with the destination register. We have
22693 already added in the PC in the first instruction and we
22694 do not want to do it again. */
22695 newinsn
&= ~ 0xf0000;
22696 newinsn
|= ((newinsn
& 0x0f000) << 4);
22699 newimm
|= (temp
& 0xfffff000);
22700 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22702 highpart
|= (newinsn
& 0xfffff000);
22703 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22707 case BFD_RELOC_ARM_OFFSET_IMM
:
22708 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22711 case BFD_RELOC_ARM_LITERAL
:
22717 if (validate_offset_imm (value
, 0) == FAIL
)
22719 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22720 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22721 _("invalid literal constant: pool needs to be closer"));
22723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22724 _("bad immediate value for offset (%ld)"),
22729 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22731 newval
&= 0xfffff000;
22734 newval
&= 0xff7ff000;
22735 newval
|= value
| (sign
? INDEX_UP
: 0);
22737 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22740 case BFD_RELOC_ARM_OFFSET_IMM8
:
22741 case BFD_RELOC_ARM_HWLITERAL
:
22747 if (validate_offset_imm (value
, 1) == FAIL
)
22749 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22750 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22751 _("invalid literal constant: pool needs to be closer"));
22753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22754 _("bad immediate value for 8-bit offset (%ld)"),
22759 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22761 newval
&= 0xfffff0f0;
22764 newval
&= 0xff7ff0f0;
22765 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22767 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22770 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22771 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22772 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22773 _("bad immediate value for offset (%ld)"), (long) value
);
22776 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22778 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22781 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22782 /* This is a complicated relocation used for all varieties of Thumb32
22783 load/store instruction with immediate offset:
22785 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22786 *4, optional writeback(W)
22787 (doubleword load/store)
22789 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22790 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22791 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22792 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22793 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22795 Uppercase letters indicate bits that are already encoded at
22796 this point. Lowercase letters are our problem. For the
22797 second block of instructions, the secondary opcode nybble
22798 (bits 8..11) is present, and bit 23 is zero, even if this is
22799 a PC-relative operation. */
22800 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22802 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22804 if ((newval
& 0xf0000000) == 0xe0000000)
22806 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22808 newval
|= (1 << 23);
22811 if (value
% 4 != 0)
22813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22814 _("offset not a multiple of 4"));
22820 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22821 _("offset out of range"));
22826 else if ((newval
& 0x000f0000) == 0x000f0000)
22828 /* PC-relative, 12-bit offset. */
22830 newval
|= (1 << 23);
22835 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22836 _("offset out of range"));
22841 else if ((newval
& 0x00000100) == 0x00000100)
22843 /* Writeback: 8-bit, +/- offset. */
22845 newval
|= (1 << 9);
22850 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22851 _("offset out of range"));
22856 else if ((newval
& 0x00000f00) == 0x00000e00)
22858 /* T-instruction: positive 8-bit offset. */
22859 if (value
< 0 || value
> 0xff)
22861 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22862 _("offset out of range"));
22870 /* Positive 12-bit or negative 8-bit offset. */
22874 newval
|= (1 << 23);
22884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22885 _("offset out of range"));
22892 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22893 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22896 case BFD_RELOC_ARM_SHIFT_IMM
:
22897 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22898 if (((unsigned long) value
) > 32
22900 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22903 _("shift expression is too large"));
22908 /* Shifts of zero must be done as lsl. */
22910 else if (value
== 32)
22912 newval
&= 0xfffff07f;
22913 newval
|= (value
& 0x1f) << 7;
22914 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22917 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22918 case BFD_RELOC_ARM_T32_ADD_IMM
:
22919 case BFD_RELOC_ARM_T32_IMM12
:
22920 case BFD_RELOC_ARM_T32_ADD_PC12
:
22921 /* We claim that this fixup has been processed here,
22922 even if in fact we generate an error because we do
22923 not have a reloc for it, so tc_gen_reloc will reject it. */
22927 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22929 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22930 _("undefined symbol %s used as an immediate value"),
22931 S_GET_NAME (fixP
->fx_addsy
));
22935 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22937 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22940 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22941 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22943 newimm
= encode_thumb32_immediate (value
);
22944 if (newimm
== (unsigned int) FAIL
)
22945 newimm
= thumb32_negate_data_op (&newval
, value
);
22947 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22948 && newimm
== (unsigned int) FAIL
)
22950 /* Turn add/sum into addw/subw. */
22951 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22952 newval
= (newval
& 0xfeffffff) | 0x02000000;
22953 /* No flat 12-bit imm encoding for addsw/subsw. */
22954 if ((newval
& 0x00100000) == 0)
22956 /* 12 bit immediate for addw/subw. */
22960 newval
^= 0x00a00000;
22963 newimm
= (unsigned int) FAIL
;
22969 if (newimm
== (unsigned int)FAIL
)
22971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22972 _("invalid constant (%lx) after fixup"),
22973 (unsigned long) value
);
22977 newval
|= (newimm
& 0x800) << 15;
22978 newval
|= (newimm
& 0x700) << 4;
22979 newval
|= (newimm
& 0x0ff);
22981 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22982 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22985 case BFD_RELOC_ARM_SMC
:
22986 if (((unsigned long) value
) > 0xffff)
22987 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22988 _("invalid smc expression"));
22989 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22990 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22991 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22994 case BFD_RELOC_ARM_HVC
:
22995 if (((unsigned long) value
) > 0xffff)
22996 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22997 _("invalid hvc expression"));
22998 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22999 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23000 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23003 case BFD_RELOC_ARM_SWI
:
23004 if (fixP
->tc_fix_data
!= 0)
23006 if (((unsigned long) value
) > 0xff)
23007 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23008 _("invalid swi expression"));
23009 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23011 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23015 if (((unsigned long) value
) > 0x00ffffff)
23016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23017 _("invalid swi expression"));
23018 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23020 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23024 case BFD_RELOC_ARM_MULTI
:
23025 if (((unsigned long) value
) > 0xffff)
23026 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23027 _("invalid expression in load/store multiple"));
23028 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23029 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23033 case BFD_RELOC_ARM_PCREL_CALL
:
23035 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23037 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23038 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23039 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23040 /* Flip the bl to blx. This is a simple flip
23041 bit here because we generate PCREL_CALL for
23042 unconditional bls. */
23044 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23045 newval
= newval
| 0x10000000;
23046 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23052 goto arm_branch_common
;
23054 case BFD_RELOC_ARM_PCREL_JUMP
:
23055 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23057 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23058 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23059 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23061 /* This would map to a bl<cond>, b<cond>,
23062 b<always> to a Thumb function. We
23063 need to force a relocation for this particular
23065 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23069 case BFD_RELOC_ARM_PLT32
:
23071 case BFD_RELOC_ARM_PCREL_BRANCH
:
23073 goto arm_branch_common
;
23075 case BFD_RELOC_ARM_PCREL_BLX
:
23078 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23080 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23081 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23082 && ARM_IS_FUNC (fixP
->fx_addsy
))
23084 /* Flip the blx to a bl and warn. */
23085 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23086 newval
= 0xeb000000;
23087 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23088 _("blx to '%s' an ARM ISA state function changed to bl"),
23090 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23096 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23097 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23101 /* We are going to store value (shifted right by two) in the
23102 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23103 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23104 also be be clear. */
23106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23107 _("misaligned branch destination"));
23108 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23109 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23110 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23112 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23114 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23115 newval
|= (value
>> 2) & 0x00ffffff;
23116 /* Set the H bit on BLX instructions. */
23120 newval
|= 0x01000000;
23122 newval
&= ~0x01000000;
23124 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23128 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23129 /* CBZ can only branch forward. */
23131 /* Attempts to use CBZ to branch to the next instruction
23132 (which, strictly speaking, are prohibited) will be turned into
23135 FIXME: It may be better to remove the instruction completely and
23136 perform relaxation. */
23139 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23140 newval
= 0xbf00; /* NOP encoding T1 */
23141 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23146 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23148 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23150 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23151 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23152 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23157 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23158 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23159 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23161 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23163 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23164 newval
|= (value
& 0x1ff) >> 1;
23165 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23169 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23170 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23171 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23173 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23175 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23176 newval
|= (value
& 0xfff) >> 1;
23177 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23181 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23183 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23184 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23185 && ARM_IS_FUNC (fixP
->fx_addsy
)
23186 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23188 /* Force a relocation for a branch 20 bits wide. */
23191 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23192 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23193 _("conditional branch out of range"));
23195 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23198 addressT S
, J1
, J2
, lo
, hi
;
23200 S
= (value
& 0x00100000) >> 20;
23201 J2
= (value
& 0x00080000) >> 19;
23202 J1
= (value
& 0x00040000) >> 18;
23203 hi
= (value
& 0x0003f000) >> 12;
23204 lo
= (value
& 0x00000ffe) >> 1;
23206 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23207 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23208 newval
|= (S
<< 10) | hi
;
23209 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23210 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23211 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23215 case BFD_RELOC_THUMB_PCREL_BLX
:
23216 /* If there is a blx from a thumb state function to
23217 another thumb function flip this to a bl and warn
23221 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23222 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23223 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23225 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23226 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23227 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23229 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23230 newval
= newval
| 0x1000;
23231 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23232 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23237 goto thumb_bl_common
;
23239 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23240 /* A bl from Thumb state ISA to an internal ARM state function
23241 is converted to a blx. */
23243 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23244 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23245 && ARM_IS_FUNC (fixP
->fx_addsy
)
23246 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23248 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23249 newval
= newval
& ~0x1000;
23250 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23251 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23257 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23258 /* For a BLX instruction, make sure that the relocation is rounded up
23259 to a word boundary. This follows the semantics of the instruction
23260 which specifies that bit 1 of the target address will come from bit
23261 1 of the base address. */
23262 value
= (value
+ 3) & ~ 3;
23265 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23266 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23267 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23270 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23272 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23274 else if ((value
& ~0x1ffffff)
23275 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23276 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23277 _("Thumb2 branch out of range"));
23280 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23281 encode_thumb2_b_bl_offset (buf
, value
);
23285 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23286 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23287 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23289 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23290 encode_thumb2_b_bl_offset (buf
, value
);
23295 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23300 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23301 md_number_to_chars (buf
, value
, 2);
23305 case BFD_RELOC_ARM_TLS_CALL
:
23306 case BFD_RELOC_ARM_THM_TLS_CALL
:
23307 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23308 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23309 case BFD_RELOC_ARM_TLS_GOTDESC
:
23310 case BFD_RELOC_ARM_TLS_GD32
:
23311 case BFD_RELOC_ARM_TLS_LE32
:
23312 case BFD_RELOC_ARM_TLS_IE32
:
23313 case BFD_RELOC_ARM_TLS_LDM32
:
23314 case BFD_RELOC_ARM_TLS_LDO32
:
23315 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23318 case BFD_RELOC_ARM_GOT32
:
23319 case BFD_RELOC_ARM_GOTOFF
:
23322 case BFD_RELOC_ARM_GOT_PREL
:
23323 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23324 md_number_to_chars (buf
, value
, 4);
23327 case BFD_RELOC_ARM_TARGET2
:
23328 /* TARGET2 is not partial-inplace, so we need to write the
23329 addend here for REL targets, because it won't be written out
23330 during reloc processing later. */
23331 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23332 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23336 case BFD_RELOC_RVA
:
23338 case BFD_RELOC_ARM_TARGET1
:
23339 case BFD_RELOC_ARM_ROSEGREL32
:
23340 case BFD_RELOC_ARM_SBREL32
:
23341 case BFD_RELOC_32_PCREL
:
23343 case BFD_RELOC_32_SECREL
:
23345 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23347 /* For WinCE we only do this for pcrel fixups. */
23348 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23350 md_number_to_chars (buf
, value
, 4);
23354 case BFD_RELOC_ARM_PREL31
:
23355 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23357 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23358 if ((value
^ (value
>> 1)) & 0x40000000)
23360 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23361 _("rel31 relocation overflow"));
23363 newval
|= value
& 0x7fffffff;
23364 md_number_to_chars (buf
, newval
, 4);
23369 case BFD_RELOC_ARM_CP_OFF_IMM
:
23370 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23371 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23372 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23374 newval
= get_thumb32_insn (buf
);
23375 if ((newval
& 0x0f200f00) == 0x0d000900)
23377 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23378 has permitted values that are multiples of 2, in the range 0
23380 if (value
< -510 || value
> 510 || (value
& 1))
23381 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23382 _("co-processor offset out of range"));
23384 else if (value
< -1023 || value
> 1023 || (value
& 3))
23385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23386 _("co-processor offset out of range"));
23391 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23392 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23393 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23395 newval
= get_thumb32_insn (buf
);
23397 newval
&= 0xffffff00;
23400 newval
&= 0xff7fff00;
23401 if ((newval
& 0x0f200f00) == 0x0d000900)
23403 /* This is a fp16 vstr/vldr.
23405 It requires the immediate offset in the instruction is shifted
23406 left by 1 to be a half-word offset.
23408 Here, left shift by 1 first, and later right shift by 2
23409 should get the right offset. */
23412 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23414 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23415 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23416 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23418 put_thumb32_insn (buf
, newval
);
23421 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23422 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23423 if (value
< -255 || value
> 255)
23424 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23425 _("co-processor offset out of range"));
23427 goto cp_off_common
;
23429 case BFD_RELOC_ARM_THUMB_OFFSET
:
23430 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23431 /* Exactly what ranges, and where the offset is inserted depends
23432 on the type of instruction, we can establish this from the
23434 switch (newval
>> 12)
23436 case 4: /* PC load. */
23437 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23438 forced to zero for these loads; md_pcrel_from has already
23439 compensated for this. */
23441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23442 _("invalid offset, target not word aligned (0x%08lX)"),
23443 (((unsigned long) fixP
->fx_frag
->fr_address
23444 + (unsigned long) fixP
->fx_where
) & ~3)
23445 + (unsigned long) value
);
23447 if (value
& ~0x3fc)
23448 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23449 _("invalid offset, value too big (0x%08lX)"),
23452 newval
|= value
>> 2;
23455 case 9: /* SP load/store. */
23456 if (value
& ~0x3fc)
23457 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23458 _("invalid offset, value too big (0x%08lX)"),
23460 newval
|= value
>> 2;
23463 case 6: /* Word load/store. */
23465 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23466 _("invalid offset, value too big (0x%08lX)"),
23468 newval
|= value
<< 4; /* 6 - 2. */
23471 case 7: /* Byte load/store. */
23473 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23474 _("invalid offset, value too big (0x%08lX)"),
23476 newval
|= value
<< 6;
23479 case 8: /* Halfword load/store. */
23481 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23482 _("invalid offset, value too big (0x%08lX)"),
23484 newval
|= value
<< 5; /* 6 - 1. */
23488 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23489 "Unable to process relocation for thumb opcode: %lx",
23490 (unsigned long) newval
);
23493 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23496 case BFD_RELOC_ARM_THUMB_ADD
:
23497 /* This is a complicated relocation, since we use it for all of
23498 the following immediate relocations:
23502 9bit ADD/SUB SP word-aligned
23503 10bit ADD PC/SP word-aligned
23505 The type of instruction being processed is encoded in the
23512 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23514 int rd
= (newval
>> 4) & 0xf;
23515 int rs
= newval
& 0xf;
23516 int subtract
= !!(newval
& 0x8000);
23518 /* Check for HI regs, only very restricted cases allowed:
23519 Adjusting SP, and using PC or SP to get an address. */
23520 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23521 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23522 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23523 _("invalid Hi register with immediate"));
23525 /* If value is negative, choose the opposite instruction. */
23529 subtract
= !subtract
;
23531 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23532 _("immediate value out of range"));
23537 if (value
& ~0x1fc)
23538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23539 _("invalid immediate for stack address calculation"));
23540 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23541 newval
|= value
>> 2;
23543 else if (rs
== REG_PC
|| rs
== REG_SP
)
23545 /* PR gas/18541. If the addition is for a defined symbol
23546 within range of an ADR instruction then accept it. */
23549 && fixP
->fx_addsy
!= NULL
)
23553 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23554 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23555 || S_IS_WEAK (fixP
->fx_addsy
))
23557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23558 _("address calculation needs a strongly defined nearby symbol"));
23562 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23564 /* Round up to the next 4-byte boundary. */
23569 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23573 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23574 _("symbol too far away"));
23584 if (subtract
|| value
& ~0x3fc)
23585 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23586 _("invalid immediate for address calculation (value = 0x%08lX)"),
23587 (unsigned long) (subtract
? - value
: value
));
23588 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23590 newval
|= value
>> 2;
23595 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23596 _("immediate value out of range"));
23597 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23598 newval
|= (rd
<< 8) | value
;
23603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23604 _("immediate value out of range"));
23605 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23606 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23609 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23612 case BFD_RELOC_ARM_THUMB_IMM
:
23613 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23614 if (value
< 0 || value
> 255)
23615 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23616 _("invalid immediate: %ld is out of range"),
23619 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23622 case BFD_RELOC_ARM_THUMB_SHIFT
:
23623 /* 5bit shift value (0..32). LSL cannot take 32. */
23624 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23625 temp
= newval
& 0xf800;
23626 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23628 _("invalid shift value: %ld"), (long) value
);
23629 /* Shifts of zero must be encoded as LSL. */
23631 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23632 /* Shifts of 32 are encoded as zero. */
23633 else if (value
== 32)
23635 newval
|= value
<< 6;
23636 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23639 case BFD_RELOC_VTABLE_INHERIT
:
23640 case BFD_RELOC_VTABLE_ENTRY
:
23644 case BFD_RELOC_ARM_MOVW
:
23645 case BFD_RELOC_ARM_MOVT
:
23646 case BFD_RELOC_ARM_THUMB_MOVW
:
23647 case BFD_RELOC_ARM_THUMB_MOVT
:
23648 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23650 /* REL format relocations are limited to a 16-bit addend. */
23651 if (!fixP
->fx_done
)
23653 if (value
< -0x8000 || value
> 0x7fff)
23654 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23655 _("offset out of range"));
23657 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23658 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23663 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23664 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23666 newval
= get_thumb32_insn (buf
);
23667 newval
&= 0xfbf08f00;
23668 newval
|= (value
& 0xf000) << 4;
23669 newval
|= (value
& 0x0800) << 15;
23670 newval
|= (value
& 0x0700) << 4;
23671 newval
|= (value
& 0x00ff);
23672 put_thumb32_insn (buf
, newval
);
23676 newval
= md_chars_to_number (buf
, 4);
23677 newval
&= 0xfff0f000;
23678 newval
|= value
& 0x0fff;
23679 newval
|= (value
& 0xf000) << 4;
23680 md_number_to_chars (buf
, newval
, 4);
23685 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23686 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23687 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23688 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23689 gas_assert (!fixP
->fx_done
);
23692 bfd_boolean is_mov
;
23693 bfd_vma encoded_addend
= value
;
23695 /* Check that addend can be encoded in instruction. */
23696 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
23697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23698 _("the offset 0x%08lX is not representable"),
23699 (unsigned long) encoded_addend
);
23701 /* Extract the instruction. */
23702 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
23703 is_mov
= (insn
& 0xf800) == 0x2000;
23708 if (!seg
->use_rela_p
)
23709 insn
|= encoded_addend
;
23715 /* Extract the instruction. */
23716 /* Encoding is the following
23721 /* The following conditions must be true :
23726 rd
= (insn
>> 4) & 0xf;
23728 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
23729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23730 _("Unable to process relocation for thumb opcode: %lx"),
23731 (unsigned long) insn
);
23733 /* Encode as ADD immediate8 thumb 1 code. */
23734 insn
= 0x3000 | (rd
<< 8);
23736 /* Place the encoded addend into the first 8 bits of the
23738 if (!seg
->use_rela_p
)
23739 insn
|= encoded_addend
;
23742 /* Update the instruction. */
23743 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
23747 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23748 case BFD_RELOC_ARM_ALU_PC_G0
:
23749 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23750 case BFD_RELOC_ARM_ALU_PC_G1
:
23751 case BFD_RELOC_ARM_ALU_PC_G2
:
23752 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23753 case BFD_RELOC_ARM_ALU_SB_G0
:
23754 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23755 case BFD_RELOC_ARM_ALU_SB_G1
:
23756 case BFD_RELOC_ARM_ALU_SB_G2
:
23757 gas_assert (!fixP
->fx_done
);
23758 if (!seg
->use_rela_p
)
23761 bfd_vma encoded_addend
;
23762 bfd_vma addend_abs
= abs (value
);
23764 /* Check that the absolute value of the addend can be
23765 expressed as an 8-bit constant plus a rotation. */
23766 encoded_addend
= encode_arm_immediate (addend_abs
);
23767 if (encoded_addend
== (unsigned int) FAIL
)
23768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23769 _("the offset 0x%08lX is not representable"),
23770 (unsigned long) addend_abs
);
23772 /* Extract the instruction. */
23773 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23775 /* If the addend is positive, use an ADD instruction.
23776 Otherwise use a SUB. Take care not to destroy the S bit. */
23777 insn
&= 0xff1fffff;
23783 /* Place the encoded addend into the first 12 bits of the
23785 insn
&= 0xfffff000;
23786 insn
|= encoded_addend
;
23788 /* Update the instruction. */
23789 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23793 case BFD_RELOC_ARM_LDR_PC_G0
:
23794 case BFD_RELOC_ARM_LDR_PC_G1
:
23795 case BFD_RELOC_ARM_LDR_PC_G2
:
23796 case BFD_RELOC_ARM_LDR_SB_G0
:
23797 case BFD_RELOC_ARM_LDR_SB_G1
:
23798 case BFD_RELOC_ARM_LDR_SB_G2
:
23799 gas_assert (!fixP
->fx_done
);
23800 if (!seg
->use_rela_p
)
23803 bfd_vma addend_abs
= abs (value
);
23805 /* Check that the absolute value of the addend can be
23806 encoded in 12 bits. */
23807 if (addend_abs
>= 0x1000)
23808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23809 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23810 (unsigned long) addend_abs
);
23812 /* Extract the instruction. */
23813 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23815 /* If the addend is negative, clear bit 23 of the instruction.
23816 Otherwise set it. */
23818 insn
&= ~(1 << 23);
23822 /* Place the absolute value of the addend into the first 12 bits
23823 of the instruction. */
23824 insn
&= 0xfffff000;
23825 insn
|= addend_abs
;
23827 /* Update the instruction. */
23828 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23832 case BFD_RELOC_ARM_LDRS_PC_G0
:
23833 case BFD_RELOC_ARM_LDRS_PC_G1
:
23834 case BFD_RELOC_ARM_LDRS_PC_G2
:
23835 case BFD_RELOC_ARM_LDRS_SB_G0
:
23836 case BFD_RELOC_ARM_LDRS_SB_G1
:
23837 case BFD_RELOC_ARM_LDRS_SB_G2
:
23838 gas_assert (!fixP
->fx_done
);
23839 if (!seg
->use_rela_p
)
23842 bfd_vma addend_abs
= abs (value
);
23844 /* Check that the absolute value of the addend can be
23845 encoded in 8 bits. */
23846 if (addend_abs
>= 0x100)
23847 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23848 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23849 (unsigned long) addend_abs
);
23851 /* Extract the instruction. */
23852 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23854 /* If the addend is negative, clear bit 23 of the instruction.
23855 Otherwise set it. */
23857 insn
&= ~(1 << 23);
23861 /* Place the first four bits of the absolute value of the addend
23862 into the first 4 bits of the instruction, and the remaining
23863 four into bits 8 .. 11. */
23864 insn
&= 0xfffff0f0;
23865 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23867 /* Update the instruction. */
23868 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23872 case BFD_RELOC_ARM_LDC_PC_G0
:
23873 case BFD_RELOC_ARM_LDC_PC_G1
:
23874 case BFD_RELOC_ARM_LDC_PC_G2
:
23875 case BFD_RELOC_ARM_LDC_SB_G0
:
23876 case BFD_RELOC_ARM_LDC_SB_G1
:
23877 case BFD_RELOC_ARM_LDC_SB_G2
:
23878 gas_assert (!fixP
->fx_done
);
23879 if (!seg
->use_rela_p
)
23882 bfd_vma addend_abs
= abs (value
);
23884 /* Check that the absolute value of the addend is a multiple of
23885 four and, when divided by four, fits in 8 bits. */
23886 if (addend_abs
& 0x3)
23887 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23888 _("bad offset 0x%08lX (must be word-aligned)"),
23889 (unsigned long) addend_abs
);
23891 if ((addend_abs
>> 2) > 0xff)
23892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23893 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23894 (unsigned long) addend_abs
);
23896 /* Extract the instruction. */
23897 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23899 /* If the addend is negative, clear bit 23 of the instruction.
23900 Otherwise set it. */
23902 insn
&= ~(1 << 23);
23906 /* Place the addend (divided by four) into the first eight
23907 bits of the instruction. */
23908 insn
&= 0xfffffff0;
23909 insn
|= addend_abs
>> 2;
23911 /* Update the instruction. */
23912 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23916 case BFD_RELOC_ARM_V4BX
:
23917 /* This will need to go in the object file. */
23921 case BFD_RELOC_UNUSED
:
23923 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23924 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23928 /* Translate internal representation of relocation info to BFD target
23932 tc_gen_reloc (asection
*section
, fixS
*fixp
)
23935 bfd_reloc_code_real_type code
;
23937 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
23939 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
23940 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
23941 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
23943 if (fixp
->fx_pcrel
)
23945 if (section
->use_rela_p
)
23946 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
23948 fixp
->fx_offset
= reloc
->address
;
23950 reloc
->addend
= fixp
->fx_offset
;
23952 switch (fixp
->fx_r_type
)
23955 if (fixp
->fx_pcrel
)
23957 code
= BFD_RELOC_8_PCREL
;
23962 if (fixp
->fx_pcrel
)
23964 code
= BFD_RELOC_16_PCREL
;
23969 if (fixp
->fx_pcrel
)
23971 code
= BFD_RELOC_32_PCREL
;
23975 case BFD_RELOC_ARM_MOVW
:
23976 if (fixp
->fx_pcrel
)
23978 code
= BFD_RELOC_ARM_MOVW_PCREL
;
23982 case BFD_RELOC_ARM_MOVT
:
23983 if (fixp
->fx_pcrel
)
23985 code
= BFD_RELOC_ARM_MOVT_PCREL
;
23989 case BFD_RELOC_ARM_THUMB_MOVW
:
23990 if (fixp
->fx_pcrel
)
23992 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
23996 case BFD_RELOC_ARM_THUMB_MOVT
:
23997 if (fixp
->fx_pcrel
)
23999 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24003 case BFD_RELOC_NONE
:
24004 case BFD_RELOC_ARM_PCREL_BRANCH
:
24005 case BFD_RELOC_ARM_PCREL_BLX
:
24006 case BFD_RELOC_RVA
:
24007 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24008 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24009 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24010 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24011 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24012 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24013 case BFD_RELOC_VTABLE_ENTRY
:
24014 case BFD_RELOC_VTABLE_INHERIT
:
24016 case BFD_RELOC_32_SECREL
:
24018 code
= fixp
->fx_r_type
;
24021 case BFD_RELOC_THUMB_PCREL_BLX
:
24023 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24024 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24027 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24030 case BFD_RELOC_ARM_LITERAL
:
24031 case BFD_RELOC_ARM_HWLITERAL
:
24032 /* If this is called then the a literal has
24033 been referenced across a section boundary. */
24034 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24035 _("literal referenced across section boundary"));
24039 case BFD_RELOC_ARM_TLS_CALL
:
24040 case BFD_RELOC_ARM_THM_TLS_CALL
:
24041 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24042 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24043 case BFD_RELOC_ARM_GOT32
:
24044 case BFD_RELOC_ARM_GOTOFF
:
24045 case BFD_RELOC_ARM_GOT_PREL
:
24046 case BFD_RELOC_ARM_PLT32
:
24047 case BFD_RELOC_ARM_TARGET1
:
24048 case BFD_RELOC_ARM_ROSEGREL32
:
24049 case BFD_RELOC_ARM_SBREL32
:
24050 case BFD_RELOC_ARM_PREL31
:
24051 case BFD_RELOC_ARM_TARGET2
:
24052 case BFD_RELOC_ARM_TLS_LDO32
:
24053 case BFD_RELOC_ARM_PCREL_CALL
:
24054 case BFD_RELOC_ARM_PCREL_JUMP
:
24055 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24056 case BFD_RELOC_ARM_ALU_PC_G0
:
24057 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24058 case BFD_RELOC_ARM_ALU_PC_G1
:
24059 case BFD_RELOC_ARM_ALU_PC_G2
:
24060 case BFD_RELOC_ARM_LDR_PC_G0
:
24061 case BFD_RELOC_ARM_LDR_PC_G1
:
24062 case BFD_RELOC_ARM_LDR_PC_G2
:
24063 case BFD_RELOC_ARM_LDRS_PC_G0
:
24064 case BFD_RELOC_ARM_LDRS_PC_G1
:
24065 case BFD_RELOC_ARM_LDRS_PC_G2
:
24066 case BFD_RELOC_ARM_LDC_PC_G0
:
24067 case BFD_RELOC_ARM_LDC_PC_G1
:
24068 case BFD_RELOC_ARM_LDC_PC_G2
:
24069 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24070 case BFD_RELOC_ARM_ALU_SB_G0
:
24071 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24072 case BFD_RELOC_ARM_ALU_SB_G1
:
24073 case BFD_RELOC_ARM_ALU_SB_G2
:
24074 case BFD_RELOC_ARM_LDR_SB_G0
:
24075 case BFD_RELOC_ARM_LDR_SB_G1
:
24076 case BFD_RELOC_ARM_LDR_SB_G2
:
24077 case BFD_RELOC_ARM_LDRS_SB_G0
:
24078 case BFD_RELOC_ARM_LDRS_SB_G1
:
24079 case BFD_RELOC_ARM_LDRS_SB_G2
:
24080 case BFD_RELOC_ARM_LDC_SB_G0
:
24081 case BFD_RELOC_ARM_LDC_SB_G1
:
24082 case BFD_RELOC_ARM_LDC_SB_G2
:
24083 case BFD_RELOC_ARM_V4BX
:
24084 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24085 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24086 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24087 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24088 code
= fixp
->fx_r_type
;
24091 case BFD_RELOC_ARM_TLS_GOTDESC
:
24092 case BFD_RELOC_ARM_TLS_GD32
:
24093 case BFD_RELOC_ARM_TLS_LE32
:
24094 case BFD_RELOC_ARM_TLS_IE32
:
24095 case BFD_RELOC_ARM_TLS_LDM32
:
24096 /* BFD will include the symbol's address in the addend.
24097 But we don't want that, so subtract it out again here. */
24098 if (!S_IS_COMMON (fixp
->fx_addsy
))
24099 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24100 code
= fixp
->fx_r_type
;
24104 case BFD_RELOC_ARM_IMMEDIATE
:
24105 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24106 _("internal relocation (type: IMMEDIATE) not fixed up"));
24109 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24110 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24111 _("ADRL used for a symbol not defined in the same file"));
24114 case BFD_RELOC_ARM_OFFSET_IMM
:
24115 if (section
->use_rela_p
)
24117 code
= fixp
->fx_r_type
;
24121 if (fixp
->fx_addsy
!= NULL
24122 && !S_IS_DEFINED (fixp
->fx_addsy
)
24123 && S_IS_LOCAL (fixp
->fx_addsy
))
24125 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24126 _("undefined local label `%s'"),
24127 S_GET_NAME (fixp
->fx_addsy
));
24131 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24132 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24139 switch (fixp
->fx_r_type
)
24141 case BFD_RELOC_NONE
: type
= "NONE"; break;
24142 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24143 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24144 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24145 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24146 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24147 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24148 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24149 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24150 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24151 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24152 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24153 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24154 default: type
= _("<unknown>"); break;
24156 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24157 _("cannot represent %s relocation in this object file format"),
24164 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24166 && fixp
->fx_addsy
== GOT_symbol
)
24168 code
= BFD_RELOC_ARM_GOTPC
;
24169 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24173 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24175 if (reloc
->howto
== NULL
)
24177 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24178 _("cannot represent %s relocation in this object file format"),
24179 bfd_get_reloc_code_name (code
));
24183 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24184 vtable entry to be used in the relocation's section offset. */
24185 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24186 reloc
->address
= fixp
->fx_offset
;
24191 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24194 cons_fix_new_arm (fragS
* frag
,
24198 bfd_reloc_code_real_type reloc
)
24203 FIXME: @@ Should look at CPU word size. */
24207 reloc
= BFD_RELOC_8
;
24210 reloc
= BFD_RELOC_16
;
24214 reloc
= BFD_RELOC_32
;
24217 reloc
= BFD_RELOC_64
;
24222 if (exp
->X_op
== O_secrel
)
24224 exp
->X_op
= O_symbol
;
24225 reloc
= BFD_RELOC_32_SECREL
;
24229 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24232 #if defined (OBJ_COFF)
24234 arm_validate_fix (fixS
* fixP
)
24236 /* If the destination of the branch is a defined symbol which does not have
24237 the THUMB_FUNC attribute, then we must be calling a function which has
24238 the (interfacearm) attribute. We look for the Thumb entry point to that
24239 function and change the branch to refer to that function instead. */
24240 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24241 && fixP
->fx_addsy
!= NULL
24242 && S_IS_DEFINED (fixP
->fx_addsy
)
24243 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24245 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24252 arm_force_relocation (struct fix
* fixp
)
24254 #if defined (OBJ_COFF) && defined (TE_PE)
24255 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24259 /* In case we have a call or a branch to a function in ARM ISA mode from
24260 a thumb function or vice-versa force the relocation. These relocations
24261 are cleared off for some cores that might have blx and simple transformations
24265 switch (fixp
->fx_r_type
)
24267 case BFD_RELOC_ARM_PCREL_JUMP
:
24268 case BFD_RELOC_ARM_PCREL_CALL
:
24269 case BFD_RELOC_THUMB_PCREL_BLX
:
24270 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24274 case BFD_RELOC_ARM_PCREL_BLX
:
24275 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24276 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24277 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24278 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24287 /* Resolve these relocations even if the symbol is extern or weak.
24288 Technically this is probably wrong due to symbol preemption.
24289 In practice these relocations do not have enough range to be useful
24290 at dynamic link time, and some code (e.g. in the Linux kernel)
24291 expects these references to be resolved. */
24292 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24293 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24294 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24295 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24296 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24297 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24298 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24299 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24300 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24301 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24302 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24303 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24304 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24305 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24308 /* Always leave these relocations for the linker. */
24309 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24310 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24311 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24314 /* Always generate relocations against function symbols. */
24315 if (fixp
->fx_r_type
== BFD_RELOC_32
24317 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24320 return generic_force_reloc (fixp
);
24323 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24324 /* Relocations against function names must be left unadjusted,
24325 so that the linker can use this information to generate interworking
24326 stubs. The MIPS version of this function
24327 also prevents relocations that are mips-16 specific, but I do not
24328 know why it does this.
24331 There is one other problem that ought to be addressed here, but
24332 which currently is not: Taking the address of a label (rather
24333 than a function) and then later jumping to that address. Such
24334 addresses also ought to have their bottom bit set (assuming that
24335 they reside in Thumb code), but at the moment they will not. */
24338 arm_fix_adjustable (fixS
* fixP
)
24340 if (fixP
->fx_addsy
== NULL
)
24343 /* Preserve relocations against symbols with function type. */
24344 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24347 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24348 && fixP
->fx_subsy
== NULL
)
24351 /* We need the symbol name for the VTABLE entries. */
24352 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24353 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24356 /* Don't allow symbols to be discarded on GOT related relocs. */
24357 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24358 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24359 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24360 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24361 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24362 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24363 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24364 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24365 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24366 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24367 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24368 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24369 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24370 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24373 /* Similarly for group relocations. */
24374 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24375 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24376 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24379 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24380 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24381 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24382 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24383 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24384 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24385 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24386 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24387 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24390 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24391 offsets, so keep these symbols. */
24392 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24393 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24398 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24402 elf32_arm_target_format (void)
24405 return (target_big_endian
24406 ? "elf32-bigarm-symbian"
24407 : "elf32-littlearm-symbian");
24408 #elif defined (TE_VXWORKS)
24409 return (target_big_endian
24410 ? "elf32-bigarm-vxworks"
24411 : "elf32-littlearm-vxworks");
24412 #elif defined (TE_NACL)
24413 return (target_big_endian
24414 ? "elf32-bigarm-nacl"
24415 : "elf32-littlearm-nacl");
24417 if (target_big_endian
)
24418 return "elf32-bigarm";
24420 return "elf32-littlearm";
24425 armelf_frob_symbol (symbolS
* symp
,
24428 elf_frob_symbol (symp
, puntp
);
24432 /* MD interface: Finalization. */
24437 literal_pool
* pool
;
24439 /* Ensure that all the IT blocks are properly closed. */
24440 check_it_blocks_finished ();
24442 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24444 /* Put it at the end of the relevant section. */
24445 subseg_set (pool
->section
, pool
->sub_section
);
24447 arm_elf_change_section ();
24454 /* Remove any excess mapping symbols generated for alignment frags in
24455 SEC. We may have created a mapping symbol before a zero byte
24456 alignment; remove it if there's a mapping symbol after the
24459 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24460 void *dummy ATTRIBUTE_UNUSED
)
24462 segment_info_type
*seginfo
= seg_info (sec
);
24465 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24468 for (fragp
= seginfo
->frchainP
->frch_root
;
24470 fragp
= fragp
->fr_next
)
24472 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24473 fragS
*next
= fragp
->fr_next
;
24475 /* Variable-sized frags have been converted to fixed size by
24476 this point. But if this was variable-sized to start with,
24477 there will be a fixed-size frag after it. So don't handle
24479 if (sym
== NULL
|| next
== NULL
)
24482 if (S_GET_VALUE (sym
) < next
->fr_address
)
24483 /* Not at the end of this frag. */
24485 know (S_GET_VALUE (sym
) == next
->fr_address
);
24489 if (next
->tc_frag_data
.first_map
!= NULL
)
24491 /* Next frag starts with a mapping symbol. Discard this
24493 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24497 if (next
->fr_next
== NULL
)
24499 /* This mapping symbol is at the end of the section. Discard
24501 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24502 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24506 /* As long as we have empty frags without any mapping symbols,
24508 /* If the next frag is non-empty and does not start with a
24509 mapping symbol, then this mapping symbol is required. */
24510 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24513 next
= next
->fr_next
;
24515 while (next
!= NULL
);
24520 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24524 arm_adjust_symtab (void)
24529 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24531 if (ARM_IS_THUMB (sym
))
24533 if (THUMB_IS_FUNC (sym
))
24535 /* Mark the symbol as a Thumb function. */
24536 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24537 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24538 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24540 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24541 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24543 as_bad (_("%s: unexpected function type: %d"),
24544 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24546 else switch (S_GET_STORAGE_CLASS (sym
))
24549 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24552 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24555 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24563 if (ARM_IS_INTERWORK (sym
))
24564 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24571 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24573 if (ARM_IS_THUMB (sym
))
24575 elf_symbol_type
* elf_sym
;
24577 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24578 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24580 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24581 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24583 /* If it's a .thumb_func, declare it as so,
24584 otherwise tag label as .code 16. */
24585 if (THUMB_IS_FUNC (sym
))
24586 elf_sym
->internal_elf_sym
.st_target_internal
24587 = ST_BRANCH_TO_THUMB
;
24588 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24589 elf_sym
->internal_elf_sym
.st_info
=
24590 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24595 /* Remove any overlapping mapping symbols generated by alignment frags. */
24596 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24597 /* Now do generic ELF adjustments. */
24598 elf_adjust_symtab ();
24602 /* MD interface: Initialization. */
24605 set_constant_flonums (void)
24609 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24610 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24614 /* Auto-select Thumb mode if it's the only available instruction set for the
24615 given architecture. */
24618 autoselect_thumb_from_cpu_variant (void)
24620 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24621 opcode_select (16);
24630 if ( (arm_ops_hsh
= hash_new ()) == NULL
24631 || (arm_cond_hsh
= hash_new ()) == NULL
24632 || (arm_shift_hsh
= hash_new ()) == NULL
24633 || (arm_psr_hsh
= hash_new ()) == NULL
24634 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24635 || (arm_reg_hsh
= hash_new ()) == NULL
24636 || (arm_reloc_hsh
= hash_new ()) == NULL
24637 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24638 as_fatal (_("virtual memory exhausted"));
24640 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24641 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24642 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24643 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24644 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24645 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24646 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24647 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24648 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24649 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24650 (void *) (v7m_psrs
+ i
));
24651 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24652 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24654 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24656 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24657 (void *) (barrier_opt_names
+ i
));
24659 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24661 struct reloc_entry
* entry
= reloc_names
+ i
;
24663 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24664 /* This makes encode_branch() use the EABI versions of this relocation. */
24665 entry
->reloc
= BFD_RELOC_UNUSED
;
24667 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24671 set_constant_flonums ();
24673 /* Set the cpu variant based on the command-line options. We prefer
24674 -mcpu= over -march= if both are set (as for GCC); and we prefer
24675 -mfpu= over any other way of setting the floating point unit.
24676 Use of legacy options with new options are faulted. */
24679 if (mcpu_cpu_opt
|| march_cpu_opt
)
24680 as_bad (_("use of old and new-style options to set CPU type"));
24682 mcpu_cpu_opt
= legacy_cpu
;
24684 else if (!mcpu_cpu_opt
)
24685 mcpu_cpu_opt
= march_cpu_opt
;
24690 as_bad (_("use of old and new-style options to set FPU type"));
24692 mfpu_opt
= legacy_fpu
;
24694 else if (!mfpu_opt
)
24696 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24697 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24698 /* Some environments specify a default FPU. If they don't, infer it
24699 from the processor. */
24701 mfpu_opt
= mcpu_fpu_opt
;
24703 mfpu_opt
= march_fpu_opt
;
24705 mfpu_opt
= &fpu_default
;
24711 if (mcpu_cpu_opt
!= NULL
)
24712 mfpu_opt
= &fpu_default
;
24713 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24714 mfpu_opt
= &fpu_arch_vfp_v2
;
24716 mfpu_opt
= &fpu_arch_fpa
;
24722 mcpu_cpu_opt
= &cpu_default
;
24723 selected_cpu
= cpu_default
;
24725 else if (no_cpu_selected ())
24726 selected_cpu
= cpu_default
;
24729 selected_cpu
= *mcpu_cpu_opt
;
24731 mcpu_cpu_opt
= &arm_arch_any
;
24734 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24736 autoselect_thumb_from_cpu_variant ();
24738 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24740 #if defined OBJ_COFF || defined OBJ_ELF
24742 unsigned int flags
= 0;
24744 #if defined OBJ_ELF
24745 flags
= meabi_flags
;
24747 switch (meabi_flags
)
24749 case EF_ARM_EABI_UNKNOWN
:
24751 /* Set the flags in the private structure. */
24752 if (uses_apcs_26
) flags
|= F_APCS26
;
24753 if (support_interwork
) flags
|= F_INTERWORK
;
24754 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24755 if (pic_code
) flags
|= F_PIC
;
24756 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24757 flags
|= F_SOFT_FLOAT
;
24759 switch (mfloat_abi_opt
)
24761 case ARM_FLOAT_ABI_SOFT
:
24762 case ARM_FLOAT_ABI_SOFTFP
:
24763 flags
|= F_SOFT_FLOAT
;
24766 case ARM_FLOAT_ABI_HARD
:
24767 if (flags
& F_SOFT_FLOAT
)
24768 as_bad (_("hard-float conflicts with specified fpu"));
24772 /* Using pure-endian doubles (even if soft-float). */
24773 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24774 flags
|= F_VFP_FLOAT
;
24776 #if defined OBJ_ELF
24777 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24778 flags
|= EF_ARM_MAVERICK_FLOAT
;
24781 case EF_ARM_EABI_VER4
:
24782 case EF_ARM_EABI_VER5
:
24783 /* No additional flags to set. */
24790 bfd_set_private_flags (stdoutput
, flags
);
24792 /* We have run out flags in the COFF header to encode the
24793 status of ATPCS support, so instead we create a dummy,
24794 empty, debug section called .arm.atpcs. */
24799 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24803 bfd_set_section_flags
24804 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24805 bfd_set_section_size (stdoutput
, sec
, 0);
24806 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24812 /* Record the CPU type as well. */
24813 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24814 mach
= bfd_mach_arm_iWMMXt2
;
24815 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24816 mach
= bfd_mach_arm_iWMMXt
;
24817 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24818 mach
= bfd_mach_arm_XScale
;
24819 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24820 mach
= bfd_mach_arm_ep9312
;
24821 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24822 mach
= bfd_mach_arm_5TE
;
24823 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24825 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24826 mach
= bfd_mach_arm_5T
;
24828 mach
= bfd_mach_arm_5
;
24830 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24832 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24833 mach
= bfd_mach_arm_4T
;
24835 mach
= bfd_mach_arm_4
;
24837 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24838 mach
= bfd_mach_arm_3M
;
24839 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24840 mach
= bfd_mach_arm_3
;
24841 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24842 mach
= bfd_mach_arm_2a
;
24843 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24844 mach
= bfd_mach_arm_2
;
24846 mach
= bfd_mach_arm_unknown
;
24848 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24851 /* Command line processing. */
24854 Invocation line includes a switch not recognized by the base assembler.
24855 See if it's a processor-specific option.
24857 This routine is somewhat complicated by the need for backwards
24858 compatibility (since older releases of gcc can't be changed).
24859 The new options try to make the interface as compatible as
24862 New options (supported) are:
24864 -mcpu=<cpu name> Assemble for selected processor
24865 -march=<architecture name> Assemble for selected architecture
24866 -mfpu=<fpu architecture> Assemble for selected FPU.
24867 -EB/-mbig-endian Big-endian
24868 -EL/-mlittle-endian Little-endian
24869 -k Generate PIC code
24870 -mthumb Start in Thumb mode
24871 -mthumb-interwork Code supports ARM/Thumb interworking
24873 -m[no-]warn-deprecated Warn about deprecated features
24874 -m[no-]warn-syms Warn when symbols match instructions
24876 For now we will also provide support for:
24878 -mapcs-32 32-bit Program counter
24879 -mapcs-26 26-bit Program counter
24880 -macps-float Floats passed in FP registers
24881 -mapcs-reentrant Reentrant code
24883 (sometime these will probably be replaced with -mapcs=<list of options>
24884 and -matpcs=<list of options>)
24886 The remaining options are only supported for back-wards compatibility.
24887 Cpu variants, the arm part is optional:
24888 -m[arm]1 Currently not supported.
24889 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24890 -m[arm]3 Arm 3 processor
24891 -m[arm]6[xx], Arm 6 processors
24892 -m[arm]7[xx][t][[d]m] Arm 7 processors
24893 -m[arm]8[10] Arm 8 processors
24894 -m[arm]9[20][tdmi] Arm 9 processors
24895 -mstrongarm[110[0]] StrongARM processors
24896 -mxscale XScale processors
24897 -m[arm]v[2345[t[e]]] Arm architectures
24898 -mall All (except the ARM1)
24900 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24901 -mfpe-old (No float load/store multiples)
24902 -mvfpxd VFP Single precision
24904 -mno-fpu Disable all floating point instructions
24906 The following CPU names are recognized:
24907 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24908 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24909 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24910 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24911 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24912 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24913 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24917 const char * md_shortopts
= "m:k";
24919 #ifdef ARM_BI_ENDIAN
24920 #define OPTION_EB (OPTION_MD_BASE + 0)
24921 #define OPTION_EL (OPTION_MD_BASE + 1)
24923 #if TARGET_BYTES_BIG_ENDIAN
24924 #define OPTION_EB (OPTION_MD_BASE + 0)
24926 #define OPTION_EL (OPTION_MD_BASE + 1)
24929 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24931 struct option md_longopts
[] =
24934 {"EB", no_argument
, NULL
, OPTION_EB
},
24937 {"EL", no_argument
, NULL
, OPTION_EL
},
24939 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
24940 {NULL
, no_argument
, NULL
, 0}
24944 size_t md_longopts_size
= sizeof (md_longopts
);
24946 struct arm_option_table
24948 const char *option
; /* Option name to match. */
24949 const char *help
; /* Help information. */
24950 int *var
; /* Variable to change. */
24951 int value
; /* What to change it to. */
24952 const char *deprecated
; /* If non-null, print this message. */
24955 struct arm_option_table arm_opts
[] =
24957 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
24958 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
24959 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24960 &support_interwork
, 1, NULL
},
24961 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
24962 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
24963 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
24965 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
24966 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
24967 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
24968 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
24971 /* These are recognized by the assembler, but have no affect on code. */
24972 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
24973 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
24975 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
24976 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24977 &warn_on_deprecated
, 0, NULL
},
24978 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
24979 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
24980 {NULL
, NULL
, NULL
, 0, NULL
}
24983 struct arm_legacy_option_table
24985 const char *option
; /* Option name to match. */
24986 const arm_feature_set
**var
; /* Variable to change. */
24987 const arm_feature_set value
; /* What to change it to. */
24988 const char *deprecated
; /* If non-null, print this message. */
24991 const struct arm_legacy_option_table arm_legacy_opts
[] =
24993 /* DON'T add any new processors to this list -- we want the whole list
24994 to go away... Add them to the processors table instead. */
24995 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24996 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24997 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24998 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24999 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25000 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25001 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25002 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25003 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25004 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25005 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25006 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25007 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25008 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25009 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25010 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25011 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25012 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25013 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25014 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25015 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25016 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25017 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25018 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25019 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25020 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25021 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25022 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25023 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25024 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25025 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25026 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25027 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25028 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25029 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25030 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25031 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25032 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25033 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25034 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25035 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25036 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25037 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25038 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25039 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25040 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25041 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25042 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25043 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25044 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25045 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25046 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25047 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25048 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25049 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25050 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25051 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25052 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25053 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25054 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25055 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25056 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25057 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25058 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25059 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25060 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25061 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25062 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25063 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25064 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25065 N_("use -mcpu=strongarm110")},
25066 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25067 N_("use -mcpu=strongarm1100")},
25068 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25069 N_("use -mcpu=strongarm1110")},
25070 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25071 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25072 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25074 /* Architecture variants -- don't add any more to this list either. */
25075 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25076 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25077 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25078 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25079 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25080 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25081 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25082 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25083 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25084 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25085 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25086 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25087 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25088 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25089 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25090 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25091 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25092 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25094 /* Floating point variants -- don't add any more to this list either. */
25095 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25096 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25097 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25098 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25099 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25101 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25104 struct arm_cpu_option_table
25108 const arm_feature_set value
;
25109 /* For some CPUs we assume an FPU unless the user explicitly sets
25111 const arm_feature_set default_fpu
;
25112 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25114 const char *canonical_name
;
25117 /* This list should, at a minimum, contain all the cpu names
25118 recognized by GCC. */
25119 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25120 static const struct arm_cpu_option_table arm_cpus
[] =
25122 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25123 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25124 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25125 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25126 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25127 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25128 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25129 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25130 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25131 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25132 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25133 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25134 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25135 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25136 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25137 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25138 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25139 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25140 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25141 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25142 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25143 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25144 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25145 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25146 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25147 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25148 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25149 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25150 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25151 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25152 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25153 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25154 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25155 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25156 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25157 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25158 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25159 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25160 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25161 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25162 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25163 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25164 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25165 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25166 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25167 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25168 /* For V5 or later processors we default to using VFP; but the user
25169 should really set the FPU type explicitly. */
25170 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25171 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25172 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25173 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25174 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25175 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25176 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25177 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25178 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25179 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25180 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25181 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25182 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25183 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25184 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25185 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25186 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25187 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25188 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25189 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25191 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25192 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25193 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25194 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25195 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25196 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25197 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25198 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25199 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25201 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25202 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25203 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25204 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25205 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25206 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25207 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25208 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25209 FPU_NONE
, "Cortex-A5"),
25210 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25212 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25213 ARM_FEATURE_COPROC (FPU_VFP_V3
25214 | FPU_NEON_EXT_V1
),
25216 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25217 ARM_FEATURE_COPROC (FPU_VFP_V3
25218 | FPU_NEON_EXT_V1
),
25220 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25222 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25224 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25226 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25228 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25230 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25232 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25234 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25236 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25237 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25239 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25240 FPU_NONE
, "Cortex-R5"),
25241 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25242 FPU_ARCH_VFP_V3D16
,
25244 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25245 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25246 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25247 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25248 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25249 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25250 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25253 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25257 /* ??? XSCALE is really an architecture. */
25258 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25259 /* ??? iwmmxt is not a processor. */
25260 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25261 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25262 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25264 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25265 FPU_ARCH_MAVERICK
, "ARM920T"),
25266 /* Marvell processors. */
25267 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25269 ARM_EXT2_V6T2_V8M
),
25270 FPU_ARCH_VFP_V3D16
, NULL
),
25271 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25273 ARM_EXT2_V6T2_V8M
),
25274 FPU_ARCH_NEON_VFP_V4
, NULL
),
25275 /* APM X-Gene family. */
25276 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25278 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25281 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25285 struct arm_arch_option_table
25289 const arm_feature_set value
;
25290 const arm_feature_set default_fpu
;
25293 /* This list should, at a minimum, contain all the architecture names
25294 recognized by GCC. */
25295 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25296 static const struct arm_arch_option_table arm_archs
[] =
25298 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25299 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25300 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25301 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25302 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25303 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25304 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25305 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25306 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25307 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25308 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25309 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25310 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25311 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25312 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25313 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25314 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25315 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25316 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25317 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25318 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25319 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25320 kept to preserve existing behaviour. */
25321 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25322 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25323 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25324 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25325 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25326 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25327 kept to preserve existing behaviour. */
25328 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25329 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25330 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25331 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25332 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25333 /* The official spelling of the ARMv7 profile variants is the dashed form.
25334 Accept the non-dashed form for compatibility with old toolchains. */
25335 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25336 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25337 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25338 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25339 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25340 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25341 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25342 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25343 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25344 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25345 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25346 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25347 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25348 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25349 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25350 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25351 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25353 #undef ARM_ARCH_OPT
25355 /* ISA extensions in the co-processor and main instruction set space. */
25356 struct arm_option_extension_value_table
25360 const arm_feature_set merge_value
;
25361 const arm_feature_set clear_value
;
25362 const arm_feature_set allowed_archs
;
25365 /* The following table must be in alphabetical order with a NULL last entry.
25367 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
25368 static const struct arm_option_extension_value_table arm_extensions
[] =
25370 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25371 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25372 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25373 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25374 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25375 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25376 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25377 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25378 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25380 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25381 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25382 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
25383 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25384 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
25385 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25386 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
25387 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25388 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
25389 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25390 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25391 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
25392 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25393 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25394 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25395 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25396 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25397 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25398 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25399 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25400 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25401 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25402 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25403 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
25404 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25405 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25406 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25407 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25409 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25410 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25411 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25412 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
25413 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25417 /* ISA floating-point and Advanced SIMD extensions. */
25418 struct arm_option_fpu_value_table
25421 const arm_feature_set value
;
25424 /* This list should, at a minimum, contain all the fpu names
25425 recognized by GCC. */
25426 static const struct arm_option_fpu_value_table arm_fpus
[] =
25428 {"softfpa", FPU_NONE
},
25429 {"fpe", FPU_ARCH_FPE
},
25430 {"fpe2", FPU_ARCH_FPE
},
25431 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25432 {"fpa", FPU_ARCH_FPA
},
25433 {"fpa10", FPU_ARCH_FPA
},
25434 {"fpa11", FPU_ARCH_FPA
},
25435 {"arm7500fe", FPU_ARCH_FPA
},
25436 {"softvfp", FPU_ARCH_VFP
},
25437 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25438 {"vfp", FPU_ARCH_VFP_V2
},
25439 {"vfp9", FPU_ARCH_VFP_V2
},
25440 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25441 {"vfp10", FPU_ARCH_VFP_V2
},
25442 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25443 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25444 {"vfpv2", FPU_ARCH_VFP_V2
},
25445 {"vfpv3", FPU_ARCH_VFP_V3
},
25446 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25447 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25448 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25449 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25450 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25451 {"arm1020t", FPU_ARCH_VFP_V1
},
25452 {"arm1020e", FPU_ARCH_VFP_V2
},
25453 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25454 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25455 {"maverick", FPU_ARCH_MAVERICK
},
25456 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25457 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25458 {"vfpv4", FPU_ARCH_VFP_V4
},
25459 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25460 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25461 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25462 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25463 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25464 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25465 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25466 {"crypto-neon-fp-armv8",
25467 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25468 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25469 {"crypto-neon-fp-armv8.1",
25470 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25471 {NULL
, ARM_ARCH_NONE
}
25474 struct arm_option_value_table
25480 static const struct arm_option_value_table arm_float_abis
[] =
25482 {"hard", ARM_FLOAT_ABI_HARD
},
25483 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25484 {"soft", ARM_FLOAT_ABI_SOFT
},
25489 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25490 static const struct arm_option_value_table arm_eabis
[] =
25492 {"gnu", EF_ARM_EABI_UNKNOWN
},
25493 {"4", EF_ARM_EABI_VER4
},
25494 {"5", EF_ARM_EABI_VER5
},
25499 struct arm_long_option_table
25501 const char * option
; /* Substring to match. */
25502 const char * help
; /* Help information. */
25503 int (* func
) (char * subopt
); /* Function to decode sub-option. */
25504 const char * deprecated
; /* If non-null, print this message. */
25508 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
25510 arm_feature_set
*ext_set
= (arm_feature_set
*)
25511 xmalloc (sizeof (arm_feature_set
));
25513 /* We insist on extensions being specified in alphabetical order, and with
25514 extensions being added before being removed. We achieve this by having
25515 the global ARM_EXTENSIONS table in alphabetical order, and using the
25516 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25517 or removing it (0) and only allowing it to change in the order
25519 const struct arm_option_extension_value_table
* opt
= NULL
;
25520 int adding_value
= -1;
25522 /* Copy the feature set, so that we can modify it. */
25523 *ext_set
= **opt_p
;
25526 while (str
!= NULL
&& *str
!= 0)
25533 as_bad (_("invalid architectural extension"));
25538 ext
= strchr (str
, '+');
25543 len
= strlen (str
);
25545 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25547 if (adding_value
!= 0)
25550 opt
= arm_extensions
;
25558 if (adding_value
== -1)
25561 opt
= arm_extensions
;
25563 else if (adding_value
!= 1)
25565 as_bad (_("must specify extensions to add before specifying "
25566 "those to remove"));
25573 as_bad (_("missing architectural extension"));
25577 gas_assert (adding_value
!= -1);
25578 gas_assert (opt
!= NULL
);
25580 /* Scan over the options table trying to find an exact match. */
25581 for (; opt
->name
!= NULL
; opt
++)
25582 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25584 /* Check we can apply the extension to this architecture. */
25585 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
25587 as_bad (_("extension does not apply to the base architecture"));
25591 /* Add or remove the extension. */
25593 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25595 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25600 if (opt
->name
== NULL
)
25602 /* Did we fail to find an extension because it wasn't specified in
25603 alphabetical order, or because it does not exist? */
25605 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25606 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25609 if (opt
->name
== NULL
)
25610 as_bad (_("unknown architectural extension `%s'"), str
);
25612 as_bad (_("architectural extensions must be specified in "
25613 "alphabetical order"));
25619 /* We should skip the extension we've just matched the next time
25631 arm_parse_cpu (char *str
)
25633 const struct arm_cpu_option_table
*opt
;
25634 char *ext
= strchr (str
, '+');
25640 len
= strlen (str
);
25644 as_bad (_("missing cpu name `%s'"), str
);
25648 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25649 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25651 mcpu_cpu_opt
= &opt
->value
;
25652 mcpu_fpu_opt
= &opt
->default_fpu
;
25653 if (opt
->canonical_name
)
25655 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25656 strcpy (selected_cpu_name
, opt
->canonical_name
);
25662 if (len
>= sizeof selected_cpu_name
)
25663 len
= (sizeof selected_cpu_name
) - 1;
25665 for (i
= 0; i
< len
; i
++)
25666 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25667 selected_cpu_name
[i
] = 0;
25671 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25676 as_bad (_("unknown cpu `%s'"), str
);
25681 arm_parse_arch (char *str
)
25683 const struct arm_arch_option_table
*opt
;
25684 char *ext
= strchr (str
, '+');
25690 len
= strlen (str
);
25694 as_bad (_("missing architecture name `%s'"), str
);
25698 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25699 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25701 march_cpu_opt
= &opt
->value
;
25702 march_fpu_opt
= &opt
->default_fpu
;
25703 strcpy (selected_cpu_name
, opt
->name
);
25706 return arm_parse_extension (ext
, &march_cpu_opt
);
25711 as_bad (_("unknown architecture `%s'\n"), str
);
25716 arm_parse_fpu (char * str
)
25718 const struct arm_option_fpu_value_table
* opt
;
25720 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25721 if (streq (opt
->name
, str
))
25723 mfpu_opt
= &opt
->value
;
25727 as_bad (_("unknown floating point format `%s'\n"), str
);
25732 arm_parse_float_abi (char * str
)
25734 const struct arm_option_value_table
* opt
;
25736 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25737 if (streq (opt
->name
, str
))
25739 mfloat_abi_opt
= opt
->value
;
25743 as_bad (_("unknown floating point abi `%s'\n"), str
);
25749 arm_parse_eabi (char * str
)
25751 const struct arm_option_value_table
*opt
;
25753 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25754 if (streq (opt
->name
, str
))
25756 meabi_flags
= opt
->value
;
25759 as_bad (_("unknown EABI `%s'\n"), str
);
25765 arm_parse_it_mode (char * str
)
25767 bfd_boolean ret
= TRUE
;
25769 if (streq ("arm", str
))
25770 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25771 else if (streq ("thumb", str
))
25772 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25773 else if (streq ("always", str
))
25774 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25775 else if (streq ("never", str
))
25776 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25779 as_bad (_("unknown implicit IT mode `%s', should be "\
25780 "arm, thumb, always, or never."), str
);
25788 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
25790 codecomposer_syntax
= TRUE
;
25791 arm_comment_chars
[0] = ';';
25792 arm_line_separator_chars
[0] = 0;
25796 struct arm_long_option_table arm_long_opts
[] =
25798 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25799 arm_parse_cpu
, NULL
},
25800 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25801 arm_parse_arch
, NULL
},
25802 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25803 arm_parse_fpu
, NULL
},
25804 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25805 arm_parse_float_abi
, NULL
},
25807 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25808 arm_parse_eabi
, NULL
},
25810 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25811 arm_parse_it_mode
, NULL
},
25812 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25813 arm_ccs_mode
, NULL
},
25814 {NULL
, NULL
, 0, NULL
}
25818 md_parse_option (int c
, char * arg
)
25820 struct arm_option_table
*opt
;
25821 const struct arm_legacy_option_table
*fopt
;
25822 struct arm_long_option_table
*lopt
;
25828 target_big_endian
= 1;
25834 target_big_endian
= 0;
25838 case OPTION_FIX_V4BX
:
25843 /* Listing option. Just ignore these, we don't support additional
25848 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25850 if (c
== opt
->option
[0]
25851 && ((arg
== NULL
&& opt
->option
[1] == 0)
25852 || streq (arg
, opt
->option
+ 1)))
25854 /* If the option is deprecated, tell the user. */
25855 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25856 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25857 arg
? arg
: "", _(opt
->deprecated
));
25859 if (opt
->var
!= NULL
)
25860 *opt
->var
= opt
->value
;
25866 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25868 if (c
== fopt
->option
[0]
25869 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25870 || streq (arg
, fopt
->option
+ 1)))
25872 /* If the option is deprecated, tell the user. */
25873 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25874 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25875 arg
? arg
: "", _(fopt
->deprecated
));
25877 if (fopt
->var
!= NULL
)
25878 *fopt
->var
= &fopt
->value
;
25884 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25886 /* These options are expected to have an argument. */
25887 if (c
== lopt
->option
[0]
25889 && strncmp (arg
, lopt
->option
+ 1,
25890 strlen (lopt
->option
+ 1)) == 0)
25892 /* If the option is deprecated, tell the user. */
25893 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25894 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25895 _(lopt
->deprecated
));
25897 /* Call the sup-option parser. */
25898 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25909 md_show_usage (FILE * fp
)
25911 struct arm_option_table
*opt
;
25912 struct arm_long_option_table
*lopt
;
25914 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25916 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25917 if (opt
->help
!= NULL
)
25918 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25920 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25921 if (lopt
->help
!= NULL
)
25922 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25926 -EB assemble code for a big-endian cpu\n"));
25931 -EL assemble code for a little-endian cpu\n"));
25935 --fix-v4bx Allow BX in ARMv4 code\n"));
25943 arm_feature_set flags
;
25944 } cpu_arch_ver_table
;
25946 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
25947 must be sorted least features first but some reordering is needed, eg. for
25948 Thumb-2 instructions to be detected as coming from ARMv6T2. */
25949 static const cpu_arch_ver_table cpu_arch_ver
[] =
25955 {4, ARM_ARCH_V5TE
},
25956 {5, ARM_ARCH_V5TEJ
},
25960 {11, ARM_ARCH_V6M
},
25961 {12, ARM_ARCH_V6SM
},
25962 {8, ARM_ARCH_V6T2
},
25963 {10, ARM_ARCH_V7VE
},
25964 {10, ARM_ARCH_V7R
},
25965 {10, ARM_ARCH_V7M
},
25966 {14, ARM_ARCH_V8A
},
25967 {16, ARM_ARCH_V8M_BASE
},
25968 {17, ARM_ARCH_V8M_MAIN
},
25972 /* Set an attribute if it has not already been set by the user. */
25974 aeabi_set_attribute_int (int tag
, int value
)
25977 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25978 || !attributes_set_explicitly
[tag
])
25979 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
25983 aeabi_set_attribute_string (int tag
, const char *value
)
25986 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25987 || !attributes_set_explicitly
[tag
])
25988 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
25991 /* Set the public EABI object attributes. */
25993 aeabi_set_public_attributes (void)
25998 int fp16_optional
= 0;
25999 arm_feature_set flags
;
26000 arm_feature_set tmp
;
26001 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26002 const cpu_arch_ver_table
*p
;
26004 /* Choose the architecture based on the capabilities of the requested cpu
26005 (if any) and/or the instructions actually used. */
26006 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26007 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26008 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26010 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26011 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26013 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26014 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26016 selected_cpu
= flags
;
26018 /* Allow the user to override the reported architecture. */
26021 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26022 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26025 /* We need to make sure that the attributes do not identify us as v6S-M
26026 when the only v6S-M feature in use is the Operating System Extensions. */
26027 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26028 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26029 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26033 for (p
= cpu_arch_ver
; p
->val
; p
++)
26035 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26038 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26042 /* The table lookup above finds the last architecture to contribute
26043 a new feature. Unfortunately, Tag13 is a subset of the union of
26044 v6T2 and v7-M, so it is never seen as contributing a new feature.
26045 We can not search for the last entry which is entirely used,
26046 because if no CPU is specified we build up only those flags
26047 actually used. Perhaps we should separate out the specified
26048 and implicit cases. Avoid taking this path for -march=all by
26049 checking for contradictory v7-A / v7-M features. */
26050 if (arch
== TAG_CPU_ARCH_V7
26051 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26052 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26053 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26054 arch
= TAG_CPU_ARCH_V7E_M
;
26056 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26057 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26058 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26060 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26061 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26062 ARMv8-M, -march=all must be detected as ARMv8-A. */
26063 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26064 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26065 arch
= TAG_CPU_ARCH_V8
;
26067 /* Tag_CPU_name. */
26068 if (selected_cpu_name
[0])
26072 q
= selected_cpu_name
;
26073 if (strncmp (q
, "armv", 4) == 0)
26078 for (i
= 0; q
[i
]; i
++)
26079 q
[i
] = TOUPPER (q
[i
]);
26081 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26084 /* Tag_CPU_arch. */
26085 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26087 /* Tag_CPU_arch_profile. */
26088 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26089 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26090 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26091 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
)))
26093 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26095 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26100 if (profile
!= '\0')
26101 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26103 /* Tag_ARM_ISA_use. */
26104 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26106 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26108 /* Tag_THUMB_ISA_use. */
26109 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26114 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26115 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26117 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26121 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26124 /* Tag_VFP_arch. */
26125 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26126 aeabi_set_attribute_int (Tag_VFP_arch
,
26127 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26129 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26130 aeabi_set_attribute_int (Tag_VFP_arch
,
26131 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26133 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26136 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26138 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26140 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26143 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26144 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26145 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26146 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26147 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26149 /* Tag_ABI_HardFP_use. */
26150 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26151 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26152 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26154 /* Tag_WMMX_arch. */
26155 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26156 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26157 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26158 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26160 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26161 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26162 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26163 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26164 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26165 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26167 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26169 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26173 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26178 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26179 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26180 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26184 We set Tag_DIV_use to two when integer divide instructions have been used
26185 in ARM state, or when Thumb integer divide instructions have been used,
26186 but we have no architecture profile set, nor have we any ARM instructions.
26188 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26189 by the base architecture.
26191 For new architectures we will have to check these tests. */
26192 gas_assert (arch
<= TAG_CPU_ARCH_V8
26193 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26194 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26195 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26196 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26197 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26198 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26199 || (profile
== '\0'
26200 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26201 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26202 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26204 /* Tag_MP_extension_use. */
26205 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26206 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26208 /* Tag Virtualization_use. */
26209 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26211 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26214 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26217 /* Add the default contents for the .ARM.attributes section. */
26221 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26224 aeabi_set_public_attributes ();
26226 #endif /* OBJ_ELF */
26229 /* Parse a .cpu directive. */
26232 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26234 const struct arm_cpu_option_table
*opt
;
26238 name
= input_line_pointer
;
26239 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26240 input_line_pointer
++;
26241 saved_char
= *input_line_pointer
;
26242 *input_line_pointer
= 0;
26244 /* Skip the first "all" entry. */
26245 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26246 if (streq (opt
->name
, name
))
26248 mcpu_cpu_opt
= &opt
->value
;
26249 selected_cpu
= opt
->value
;
26250 if (opt
->canonical_name
)
26251 strcpy (selected_cpu_name
, opt
->canonical_name
);
26255 for (i
= 0; opt
->name
[i
]; i
++)
26256 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26258 selected_cpu_name
[i
] = 0;
26260 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26261 *input_line_pointer
= saved_char
;
26262 demand_empty_rest_of_line ();
26265 as_bad (_("unknown cpu `%s'"), name
);
26266 *input_line_pointer
= saved_char
;
26267 ignore_rest_of_line ();
26271 /* Parse a .arch directive. */
26274 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26276 const struct arm_arch_option_table
*opt
;
26280 name
= input_line_pointer
;
26281 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26282 input_line_pointer
++;
26283 saved_char
= *input_line_pointer
;
26284 *input_line_pointer
= 0;
26286 /* Skip the first "all" entry. */
26287 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26288 if (streq (opt
->name
, name
))
26290 mcpu_cpu_opt
= &opt
->value
;
26291 selected_cpu
= opt
->value
;
26292 strcpy (selected_cpu_name
, opt
->name
);
26293 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26294 *input_line_pointer
= saved_char
;
26295 demand_empty_rest_of_line ();
26299 as_bad (_("unknown architecture `%s'\n"), name
);
26300 *input_line_pointer
= saved_char
;
26301 ignore_rest_of_line ();
26305 /* Parse a .object_arch directive. */
26308 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26310 const struct arm_arch_option_table
*opt
;
26314 name
= input_line_pointer
;
26315 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26316 input_line_pointer
++;
26317 saved_char
= *input_line_pointer
;
26318 *input_line_pointer
= 0;
26320 /* Skip the first "all" entry. */
26321 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26322 if (streq (opt
->name
, name
))
26324 object_arch
= &opt
->value
;
26325 *input_line_pointer
= saved_char
;
26326 demand_empty_rest_of_line ();
26330 as_bad (_("unknown architecture `%s'\n"), name
);
26331 *input_line_pointer
= saved_char
;
26332 ignore_rest_of_line ();
26335 /* Parse a .arch_extension directive. */
26338 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26340 const struct arm_option_extension_value_table
*opt
;
26343 int adding_value
= 1;
26345 name
= input_line_pointer
;
26346 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26347 input_line_pointer
++;
26348 saved_char
= *input_line_pointer
;
26349 *input_line_pointer
= 0;
26351 if (strlen (name
) >= 2
26352 && strncmp (name
, "no", 2) == 0)
26358 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26359 if (streq (opt
->name
, name
))
26361 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
26363 as_bad (_("architectural extension `%s' is not allowed for the "
26364 "current base architecture"), name
);
26369 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26372 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26374 mcpu_cpu_opt
= &selected_cpu
;
26375 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26376 *input_line_pointer
= saved_char
;
26377 demand_empty_rest_of_line ();
26381 if (opt
->name
== NULL
)
26382 as_bad (_("unknown architecture extension `%s'\n"), name
);
26384 *input_line_pointer
= saved_char
;
26385 ignore_rest_of_line ();
26388 /* Parse a .fpu directive. */
26391 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26393 const struct arm_option_fpu_value_table
*opt
;
26397 name
= input_line_pointer
;
26398 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26399 input_line_pointer
++;
26400 saved_char
= *input_line_pointer
;
26401 *input_line_pointer
= 0;
26403 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26404 if (streq (opt
->name
, name
))
26406 mfpu_opt
= &opt
->value
;
26407 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26408 *input_line_pointer
= saved_char
;
26409 demand_empty_rest_of_line ();
26413 as_bad (_("unknown floating point format `%s'\n"), name
);
26414 *input_line_pointer
= saved_char
;
26415 ignore_rest_of_line ();
26418 /* Copy symbol information. */
26421 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26423 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26427 /* Given a symbolic attribute NAME, return the proper integer value.
26428 Returns -1 if the attribute is not known. */
26431 arm_convert_symbolic_attribute (const char *name
)
26433 static const struct
26438 attribute_table
[] =
26440 /* When you modify this table you should
26441 also modify the list in doc/c-arm.texi. */
26442 #define T(tag) {#tag, tag}
26443 T (Tag_CPU_raw_name
),
26446 T (Tag_CPU_arch_profile
),
26447 T (Tag_ARM_ISA_use
),
26448 T (Tag_THUMB_ISA_use
),
26452 T (Tag_Advanced_SIMD_arch
),
26453 T (Tag_PCS_config
),
26454 T (Tag_ABI_PCS_R9_use
),
26455 T (Tag_ABI_PCS_RW_data
),
26456 T (Tag_ABI_PCS_RO_data
),
26457 T (Tag_ABI_PCS_GOT_use
),
26458 T (Tag_ABI_PCS_wchar_t
),
26459 T (Tag_ABI_FP_rounding
),
26460 T (Tag_ABI_FP_denormal
),
26461 T (Tag_ABI_FP_exceptions
),
26462 T (Tag_ABI_FP_user_exceptions
),
26463 T (Tag_ABI_FP_number_model
),
26464 T (Tag_ABI_align_needed
),
26465 T (Tag_ABI_align8_needed
),
26466 T (Tag_ABI_align_preserved
),
26467 T (Tag_ABI_align8_preserved
),
26468 T (Tag_ABI_enum_size
),
26469 T (Tag_ABI_HardFP_use
),
26470 T (Tag_ABI_VFP_args
),
26471 T (Tag_ABI_WMMX_args
),
26472 T (Tag_ABI_optimization_goals
),
26473 T (Tag_ABI_FP_optimization_goals
),
26474 T (Tag_compatibility
),
26475 T (Tag_CPU_unaligned_access
),
26476 T (Tag_FP_HP_extension
),
26477 T (Tag_VFP_HP_extension
),
26478 T (Tag_ABI_FP_16bit_format
),
26479 T (Tag_MPextension_use
),
26481 T (Tag_nodefaults
),
26482 T (Tag_also_compatible_with
),
26483 T (Tag_conformance
),
26485 T (Tag_Virtualization_use
),
26486 /* We deliberately do not include Tag_MPextension_use_legacy. */
26494 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26495 if (streq (name
, attribute_table
[i
].name
))
26496 return attribute_table
[i
].tag
;
26502 /* Apply sym value for relocations only in the case that they are for
26503 local symbols in the same segment as the fixup and you have the
26504 respective architectural feature for blx and simple switches. */
26506 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26509 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26510 /* PR 17444: If the local symbol is in a different section then a reloc
26511 will always be generated for it, so applying the symbol value now
26512 will result in a double offset being stored in the relocation. */
26513 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26514 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26516 switch (fixP
->fx_r_type
)
26518 case BFD_RELOC_ARM_PCREL_BLX
:
26519 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26520 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26524 case BFD_RELOC_ARM_PCREL_CALL
:
26525 case BFD_RELOC_THUMB_PCREL_BLX
:
26526 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26537 #endif /* OBJ_ELF */