1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
167 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
170 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
173 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
174 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
175 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
176 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
177 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
178 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
179 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
180 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v4t_5
=
182 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
184 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
185 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
186 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
187 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
188 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
190 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
191 static const arm_feature_set arm_ext_v6_notm
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
193 static const arm_feature_set arm_ext_v6_dsp
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
195 static const arm_feature_set arm_ext_barrier
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
197 static const arm_feature_set arm_ext_msr
=
198 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
199 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
200 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
201 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
202 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
204 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
206 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
207 static const arm_feature_set arm_ext_m
=
208 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
,
209 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
210 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
211 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
212 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
213 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
214 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
215 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
216 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
217 static const arm_feature_set arm_ext_v8m_main
=
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
219 /* Instructions in ARMv8-M only found in M profile architectures. */
220 static const arm_feature_set arm_ext_v8m_m_only
=
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
222 static const arm_feature_set arm_ext_v6t2_v8m
=
223 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
224 /* Instructions shared between ARMv8-A and ARMv8-M. */
225 static const arm_feature_set arm_ext_atomics
=
226 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
228 /* DSP instructions Tag_DSP_extension refers to. */
229 static const arm_feature_set arm_ext_dsp
=
230 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
232 static const arm_feature_set arm_ext_ras
=
233 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
234 /* FP16 instructions. */
235 static const arm_feature_set arm_ext_fp16
=
236 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
237 static const arm_feature_set arm_ext_v8_3
=
238 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
240 static const arm_feature_set arm_arch_any
= ARM_ANY
;
241 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
242 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
243 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
245 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
248 static const arm_feature_set arm_cext_iwmmxt2
=
249 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
250 static const arm_feature_set arm_cext_iwmmxt
=
251 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
252 static const arm_feature_set arm_cext_xscale
=
253 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
254 static const arm_feature_set arm_cext_maverick
=
255 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
256 static const arm_feature_set fpu_fpa_ext_v1
=
257 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
258 static const arm_feature_set fpu_fpa_ext_v2
=
259 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
260 static const arm_feature_set fpu_vfp_ext_v1xd
=
261 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
262 static const arm_feature_set fpu_vfp_ext_v1
=
263 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
264 static const arm_feature_set fpu_vfp_ext_v2
=
265 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
266 static const arm_feature_set fpu_vfp_ext_v3xd
=
267 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
268 static const arm_feature_set fpu_vfp_ext_v3
=
269 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
270 static const arm_feature_set fpu_vfp_ext_d32
=
271 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
272 static const arm_feature_set fpu_neon_ext_v1
=
273 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
274 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
275 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
277 static const arm_feature_set fpu_vfp_fp16
=
278 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
279 static const arm_feature_set fpu_neon_ext_fma
=
280 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
282 static const arm_feature_set fpu_vfp_ext_fma
=
283 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
284 static const arm_feature_set fpu_vfp_ext_armv8
=
285 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
286 static const arm_feature_set fpu_vfp_ext_armv8xd
=
287 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
288 static const arm_feature_set fpu_neon_ext_armv8
=
289 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
290 static const arm_feature_set fpu_crypto_ext_armv8
=
291 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
292 static const arm_feature_set crc_ext_armv8
=
293 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
294 static const arm_feature_set fpu_neon_ext_v8_1
=
295 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
297 static int mfloat_abi_opt
= -1;
298 /* Record user cpu selection for object attributes. */
299 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
300 /* Must be long enough to hold any of the names in arm_cpus. */
301 static char selected_cpu_name
[20];
303 extern FLONUM_TYPE generic_floating_point_number
;
305 /* Return if no cpu was selected on command-line. */
307 no_cpu_selected (void)
309 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
314 static int meabi_flags
= EABI_DEFAULT
;
316 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
319 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
324 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
329 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
330 symbolS
* GOT_symbol
;
333 /* 0: assemble for ARM,
334 1: assemble for Thumb,
335 2: assemble for Thumb even though target CPU does not support thumb
337 static int thumb_mode
= 0;
338 /* A value distinct from the possible values for thumb_mode that we
339 can use to record whether thumb_mode has been copied into the
340 tc_frag_data field of a frag. */
341 #define MODE_RECORDED (1 << 4)
343 /* Specifies the intrinsic IT insn behavior mode. */
344 enum implicit_it_mode
346 IMPLICIT_IT_MODE_NEVER
= 0x00,
347 IMPLICIT_IT_MODE_ARM
= 0x01,
348 IMPLICIT_IT_MODE_THUMB
= 0x02,
349 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
351 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
353 /* If unified_syntax is true, we are processing the new unified
354 ARM/Thumb syntax. Important differences from the old ARM mode:
356 - Immediate operands do not require a # prefix.
357 - Conditional affixes always appear at the end of the
358 instruction. (For backward compatibility, those instructions
359 that formerly had them in the middle, continue to accept them
361 - The IT instruction may appear, and if it does is validated
362 against subsequent conditional affixes. It does not generate
365 Important differences from the old Thumb mode:
367 - Immediate operands do not require a # prefix.
368 - Most of the V6T2 instructions are only available in unified mode.
369 - The .N and .W suffixes are recognized and honored (it is an error
370 if they cannot be honored).
371 - All instructions set the flags if and only if they have an 's' affix.
372 - Conditional affixes may be used. They are validated against
373 preceding IT instructions. Unlike ARM mode, you cannot use a
374 conditional affix except in the scope of an IT instruction. */
376 static bfd_boolean unified_syntax
= FALSE
;
378 /* An immediate operand can start with #, and ld*, st*, pld operands
379 can contain [ and ]. We need to tell APP not to elide whitespace
380 before a [, which can appear as the first operand for pld.
381 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
382 const char arm_symbol_chars
[] = "#[]{}";
397 enum neon_el_type type
;
401 #define NEON_MAX_TYPE_ELS 4
405 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
409 enum it_instruction_type
414 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
415 if inside, should be the last one. */
416 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
417 i.e. BKPT and NOP. */
418 IT_INSN
/* The IT insn has been parsed. */
421 /* The maximum number of operands we need. */
422 #define ARM_IT_MAX_OPERANDS 6
427 unsigned long instruction
;
431 /* "uncond_value" is set to the value in place of the conditional field in
432 unconditional versions of the instruction, or -1 if nothing is
435 struct neon_type vectype
;
436 /* This does not indicate an actual NEON instruction, only that
437 the mnemonic accepts neon-style type suffixes. */
439 /* Set to the opcode if the instruction needs relaxation.
440 Zero if the instruction is not relaxed. */
444 bfd_reloc_code_real_type type
;
449 enum it_instruction_type it_insn_type
;
455 struct neon_type_el vectype
;
456 unsigned present
: 1; /* Operand present. */
457 unsigned isreg
: 1; /* Operand was a register. */
458 unsigned immisreg
: 1; /* .imm field is a second register. */
459 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
460 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
461 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
462 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
463 instructions. This allows us to disambiguate ARM <-> vector insns. */
464 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
465 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
466 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
467 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
468 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
469 unsigned writeback
: 1; /* Operand has trailing ! */
470 unsigned preind
: 1; /* Preindexed address. */
471 unsigned postind
: 1; /* Postindexed address. */
472 unsigned negative
: 1; /* Index register was negated. */
473 unsigned shifted
: 1; /* Shift applied to operation. */
474 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
475 } operands
[ARM_IT_MAX_OPERANDS
];
478 static struct arm_it inst
;
480 #define NUM_FLOAT_VALS 8
482 const char * fp_const
[] =
484 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
487 /* Number of littlenums required to hold an extended precision number. */
488 #define MAX_LITTLENUMS 6
490 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
500 #define CP_T_X 0x00008000
501 #define CP_T_Y 0x00400000
503 #define CONDS_BIT 0x00100000
504 #define LOAD_BIT 0x00100000
506 #define DOUBLE_LOAD_FLAG 0x00000001
510 const char * template_name
;
514 #define COND_ALWAYS 0xE
518 const char * template_name
;
522 struct asm_barrier_opt
524 const char * template_name
;
526 const arm_feature_set arch
;
529 /* The bit that distinguishes CPSR and SPSR. */
530 #define SPSR_BIT (1 << 22)
532 /* The individual PSR flag bits. */
533 #define PSR_c (1 << 16)
534 #define PSR_x (1 << 17)
535 #define PSR_s (1 << 18)
536 #define PSR_f (1 << 19)
541 bfd_reloc_code_real_type reloc
;
546 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
547 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
552 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
555 /* Bits for DEFINED field in neon_typed_alias. */
556 #define NTA_HASTYPE 1
557 #define NTA_HASINDEX 2
559 struct neon_typed_alias
561 unsigned char defined
;
563 struct neon_type_el eltype
;
566 /* ARM register categories. This includes coprocessor numbers and various
567 architecture extensions' registers. */
594 /* Structure for a hash table entry for a register.
595 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
596 information which states whether a vector type or index is specified (for a
597 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
603 unsigned char builtin
;
604 struct neon_typed_alias
* neon
;
607 /* Diagnostics used when we don't get a register of the expected type. */
608 const char * const reg_expected_msgs
[] =
610 N_("ARM register expected"),
611 N_("bad or missing co-processor number"),
612 N_("co-processor register expected"),
613 N_("FPA register expected"),
614 N_("VFP single precision register expected"),
615 N_("VFP/Neon double precision register expected"),
616 N_("Neon quad precision register expected"),
617 N_("VFP single or double precision register expected"),
618 N_("Neon double or quad precision register expected"),
619 N_("VFP single, double or Neon quad precision register expected"),
620 N_("VFP system register expected"),
621 N_("Maverick MVF register expected"),
622 N_("Maverick MVD register expected"),
623 N_("Maverick MVFX register expected"),
624 N_("Maverick MVDX register expected"),
625 N_("Maverick MVAX register expected"),
626 N_("Maverick DSPSC register expected"),
627 N_("iWMMXt data register expected"),
628 N_("iWMMXt control register expected"),
629 N_("iWMMXt scalar register expected"),
630 N_("XScale accumulator register expected"),
633 /* Some well known registers that we refer to directly elsewhere. */
639 /* ARM instructions take 4bytes in the object file, Thumb instructions
645 /* Basic string to match. */
646 const char * template_name
;
648 /* Parameters to instruction. */
649 unsigned int operands
[8];
651 /* Conditional tag - see opcode_lookup. */
652 unsigned int tag
: 4;
654 /* Basic instruction code. */
655 unsigned int avalue
: 28;
657 /* Thumb-format instruction code. */
660 /* Which architecture variant provides this instruction. */
661 const arm_feature_set
* avariant
;
662 const arm_feature_set
* tvariant
;
664 /* Function to call to encode instruction in ARM format. */
665 void (* aencode
) (void);
667 /* Function to call to encode instruction in Thumb format. */
668 void (* tencode
) (void);
671 /* Defines for various bits that we will want to toggle. */
672 #define INST_IMMEDIATE 0x02000000
673 #define OFFSET_REG 0x02000000
674 #define HWOFFSET_IMM 0x00400000
675 #define SHIFT_BY_REG 0x00000010
676 #define PRE_INDEX 0x01000000
677 #define INDEX_UP 0x00800000
678 #define WRITE_BACK 0x00200000
679 #define LDM_TYPE_2_OR_3 0x00400000
680 #define CPSI_MMOD 0x00020000
682 #define LITERAL_MASK 0xf000f000
683 #define OPCODE_MASK 0xfe1fffff
684 #define V4_STR_BIT 0x00000020
685 #define VLDR_VMOV_SAME 0x0040f000
687 #define T2_SUBS_PC_LR 0xf3de8f00
689 #define DATA_OP_SHIFT 21
690 #define SBIT_SHIFT 20
692 #define T2_OPCODE_MASK 0xfe1fffff
693 #define T2_DATA_OP_SHIFT 21
694 #define T2_SBIT_SHIFT 20
696 #define A_COND_MASK 0xf0000000
697 #define A_PUSH_POP_OP_MASK 0x0fff0000
699 /* Opcodes for pushing/poping registers to/from the stack. */
700 #define A1_OPCODE_PUSH 0x092d0000
701 #define A2_OPCODE_PUSH 0x052d0004
702 #define A2_OPCODE_POP 0x049d0004
704 /* Codes to distinguish the arithmetic instructions. */
715 #define OPCODE_CMP 10
716 #define OPCODE_CMN 11
717 #define OPCODE_ORR 12
718 #define OPCODE_MOV 13
719 #define OPCODE_BIC 14
720 #define OPCODE_MVN 15
722 #define T2_OPCODE_AND 0
723 #define T2_OPCODE_BIC 1
724 #define T2_OPCODE_ORR 2
725 #define T2_OPCODE_ORN 3
726 #define T2_OPCODE_EOR 4
727 #define T2_OPCODE_ADD 8
728 #define T2_OPCODE_ADC 10
729 #define T2_OPCODE_SBC 11
730 #define T2_OPCODE_SUB 13
731 #define T2_OPCODE_RSB 14
733 #define T_OPCODE_MUL 0x4340
734 #define T_OPCODE_TST 0x4200
735 #define T_OPCODE_CMN 0x42c0
736 #define T_OPCODE_NEG 0x4240
737 #define T_OPCODE_MVN 0x43c0
739 #define T_OPCODE_ADD_R3 0x1800
740 #define T_OPCODE_SUB_R3 0x1a00
741 #define T_OPCODE_ADD_HI 0x4400
742 #define T_OPCODE_ADD_ST 0xb000
743 #define T_OPCODE_SUB_ST 0xb080
744 #define T_OPCODE_ADD_SP 0xa800
745 #define T_OPCODE_ADD_PC 0xa000
746 #define T_OPCODE_ADD_I8 0x3000
747 #define T_OPCODE_SUB_I8 0x3800
748 #define T_OPCODE_ADD_I3 0x1c00
749 #define T_OPCODE_SUB_I3 0x1e00
751 #define T_OPCODE_ASR_R 0x4100
752 #define T_OPCODE_LSL_R 0x4080
753 #define T_OPCODE_LSR_R 0x40c0
754 #define T_OPCODE_ROR_R 0x41c0
755 #define T_OPCODE_ASR_I 0x1000
756 #define T_OPCODE_LSL_I 0x0000
757 #define T_OPCODE_LSR_I 0x0800
759 #define T_OPCODE_MOV_I8 0x2000
760 #define T_OPCODE_CMP_I8 0x2800
761 #define T_OPCODE_CMP_LR 0x4280
762 #define T_OPCODE_MOV_HR 0x4600
763 #define T_OPCODE_CMP_HR 0x4500
765 #define T_OPCODE_LDR_PC 0x4800
766 #define T_OPCODE_LDR_SP 0x9800
767 #define T_OPCODE_STR_SP 0x9000
768 #define T_OPCODE_LDR_IW 0x6800
769 #define T_OPCODE_STR_IW 0x6000
770 #define T_OPCODE_LDR_IH 0x8800
771 #define T_OPCODE_STR_IH 0x8000
772 #define T_OPCODE_LDR_IB 0x7800
773 #define T_OPCODE_STR_IB 0x7000
774 #define T_OPCODE_LDR_RW 0x5800
775 #define T_OPCODE_STR_RW 0x5000
776 #define T_OPCODE_LDR_RH 0x5a00
777 #define T_OPCODE_STR_RH 0x5200
778 #define T_OPCODE_LDR_RB 0x5c00
779 #define T_OPCODE_STR_RB 0x5400
781 #define T_OPCODE_PUSH 0xb400
782 #define T_OPCODE_POP 0xbc00
784 #define T_OPCODE_BRANCH 0xe000
786 #define THUMB_SIZE 2 /* Size of thumb instruction. */
787 #define THUMB_PP_PC_LR 0x0100
788 #define THUMB_LOAD_BIT 0x0800
789 #define THUMB2_LOAD_BIT 0x00100000
791 #define BAD_ARGS _("bad arguments to instruction")
792 #define BAD_SP _("r13 not allowed here")
793 #define BAD_PC _("r15 not allowed here")
794 #define BAD_COND _("instruction cannot be conditional")
795 #define BAD_OVERLAP _("registers may not be the same")
796 #define BAD_HIREG _("lo register required")
797 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
798 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
799 #define BAD_BRANCH _("branch must be last instruction in IT block")
800 #define BAD_NOT_IT _("instruction not allowed in IT block")
801 #define BAD_FPU _("selected FPU does not support instruction")
802 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
803 #define BAD_IT_COND _("incorrect condition in IT block")
804 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
805 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
806 #define BAD_PC_ADDRESSING \
807 _("cannot use register index with PC-relative addressing")
808 #define BAD_PC_WRITEBACK \
809 _("cannot use writeback with PC-relative addressing")
810 #define BAD_RANGE _("branch out of range")
811 #define BAD_FP16 _("selected processor does not support fp16 instruction")
812 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
813 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
815 static struct hash_control
* arm_ops_hsh
;
816 static struct hash_control
* arm_cond_hsh
;
817 static struct hash_control
* arm_shift_hsh
;
818 static struct hash_control
* arm_psr_hsh
;
819 static struct hash_control
* arm_v7m_psr_hsh
;
820 static struct hash_control
* arm_reg_hsh
;
821 static struct hash_control
* arm_reloc_hsh
;
822 static struct hash_control
* arm_barrier_opt_hsh
;
824 /* Stuff needed to resolve the label ambiguity
833 symbolS
* last_label_seen
;
834 static int label_is_thumb_function_name
= FALSE
;
836 /* Literal pool structure. Held on a per-section
837 and per-sub-section basis. */
839 #define MAX_LITERAL_POOL_SIZE 1024
840 typedef struct literal_pool
842 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
843 unsigned int next_free_entry
;
849 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
851 struct literal_pool
* next
;
852 unsigned int alignment
;
855 /* Pointer to a linked list of literal pools. */
856 literal_pool
* list_of_pools
= NULL
;
858 typedef enum asmfunc_states
861 WAITING_ASMFUNC_NAME
,
865 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
868 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
870 static struct current_it now_it
;
874 now_it_compatible (int cond
)
876 return (cond
& ~1) == (now_it
.cc
& ~1);
880 conditional_insn (void)
882 return inst
.cond
!= COND_ALWAYS
;
885 static int in_it_block (void);
887 static int handle_it_state (void);
889 static void force_automatic_it_block_close (void);
891 static void it_fsm_post_encode (void);
893 #define set_it_insn_type(type) \
896 inst.it_insn_type = type; \
897 if (handle_it_state () == FAIL) \
902 #define set_it_insn_type_nonvoid(type, failret) \
905 inst.it_insn_type = type; \
906 if (handle_it_state () == FAIL) \
911 #define set_it_insn_type_last() \
914 if (inst.cond == COND_ALWAYS) \
915 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
917 set_it_insn_type (INSIDE_IT_LAST_INSN); \
923 /* This array holds the chars that always start a comment. If the
924 pre-processor is disabled, these aren't very useful. */
925 char arm_comment_chars
[] = "@";
927 /* This array holds the chars that only start a comment at the beginning of
928 a line. If the line seems to have the form '# 123 filename'
929 .line and .file directives will appear in the pre-processed output. */
930 /* Note that input_file.c hand checks for '#' at the beginning of the
931 first line of the input file. This is because the compiler outputs
932 #NO_APP at the beginning of its output. */
933 /* Also note that comments like this one will always work. */
934 const char line_comment_chars
[] = "#";
936 char arm_line_separator_chars
[] = ";";
938 /* Chars that can be used to separate mant
939 from exp in floating point numbers. */
940 const char EXP_CHARS
[] = "eE";
942 /* Chars that mean this number is a floating point constant. */
946 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
948 /* Prefix characters that indicate the start of an immediate
950 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
952 /* Separator character handling. */
954 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
957 skip_past_char (char ** str
, char c
)
959 /* PR gas/14987: Allow for whitespace before the expected character. */
960 skip_whitespace (*str
);
971 #define skip_past_comma(str) skip_past_char (str, ',')
973 /* Arithmetic expressions (possibly involving symbols). */
975 /* Return TRUE if anything in the expression is a bignum. */
978 walk_no_bignums (symbolS
* sp
)
980 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
983 if (symbol_get_value_expression (sp
)->X_add_symbol
)
985 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
986 || (symbol_get_value_expression (sp
)->X_op_symbol
987 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
993 static int in_my_get_expression
= 0;
995 /* Third argument to my_get_expression. */
996 #define GE_NO_PREFIX 0
997 #define GE_IMM_PREFIX 1
998 #define GE_OPT_PREFIX 2
999 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1000 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1001 #define GE_OPT_PREFIX_BIG 3
1004 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1009 /* In unified syntax, all prefixes are optional. */
1011 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1014 switch (prefix_mode
)
1016 case GE_NO_PREFIX
: break;
1018 if (!is_immediate_prefix (**str
))
1020 inst
.error
= _("immediate expression requires a # prefix");
1026 case GE_OPT_PREFIX_BIG
:
1027 if (is_immediate_prefix (**str
))
1033 memset (ep
, 0, sizeof (expressionS
));
1035 save_in
= input_line_pointer
;
1036 input_line_pointer
= *str
;
1037 in_my_get_expression
= 1;
1038 seg
= expression (ep
);
1039 in_my_get_expression
= 0;
1041 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1043 /* We found a bad or missing expression in md_operand(). */
1044 *str
= input_line_pointer
;
1045 input_line_pointer
= save_in
;
1046 if (inst
.error
== NULL
)
1047 inst
.error
= (ep
->X_op
== O_absent
1048 ? _("missing expression") :_("bad expression"));
1053 if (seg
!= absolute_section
1054 && seg
!= text_section
1055 && seg
!= data_section
1056 && seg
!= bss_section
1057 && seg
!= undefined_section
)
1059 inst
.error
= _("bad segment");
1060 *str
= input_line_pointer
;
1061 input_line_pointer
= save_in
;
1068 /* Get rid of any bignums now, so that we don't generate an error for which
1069 we can't establish a line number later on. Big numbers are never valid
1070 in instructions, which is where this routine is always called. */
1071 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1072 && (ep
->X_op
== O_big
1073 || (ep
->X_add_symbol
1074 && (walk_no_bignums (ep
->X_add_symbol
)
1076 && walk_no_bignums (ep
->X_op_symbol
))))))
1078 inst
.error
= _("invalid constant");
1079 *str
= input_line_pointer
;
1080 input_line_pointer
= save_in
;
1084 *str
= input_line_pointer
;
1085 input_line_pointer
= save_in
;
1089 /* Turn a string in input_line_pointer into a floating point constant
1090 of type TYPE, and store the appropriate bytes in *LITP. The number
1091 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1092 returned, or NULL on OK.
1094 Note that fp constants aren't represent in the normal way on the ARM.
1095 In big endian mode, things are as expected. However, in little endian
1096 mode fp constants are big-endian word-wise, and little-endian byte-wise
1097 within the words. For example, (double) 1.1 in big endian mode is
1098 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1099 the byte sequence 99 99 f1 3f 9a 99 99 99.
1101 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1104 md_atof (int type
, char * litP
, int * sizeP
)
1107 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1139 return _("Unrecognized or unsupported floating point constant");
1142 t
= atof_ieee (input_line_pointer
, type
, words
);
1144 input_line_pointer
= t
;
1145 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1147 if (target_big_endian
)
1149 for (i
= 0; i
< prec
; i
++)
1151 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1152 litP
+= sizeof (LITTLENUM_TYPE
);
1157 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1158 for (i
= prec
- 1; i
>= 0; i
--)
1160 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1161 litP
+= sizeof (LITTLENUM_TYPE
);
1164 /* For a 4 byte float the order of elements in `words' is 1 0.
1165 For an 8 byte float the order is 1 0 3 2. */
1166 for (i
= 0; i
< prec
; i
+= 2)
1168 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1169 sizeof (LITTLENUM_TYPE
));
1170 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1171 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1172 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1179 /* We handle all bad expressions here, so that we can report the faulty
1180 instruction in the error message. */
1182 md_operand (expressionS
* exp
)
1184 if (in_my_get_expression
)
1185 exp
->X_op
= O_illegal
;
1188 /* Immediate values. */
1190 /* Generic immediate-value read function for use in directives.
1191 Accepts anything that 'expression' can fold to a constant.
1192 *val receives the number. */
1195 immediate_for_directive (int *val
)
1198 exp
.X_op
= O_illegal
;
1200 if (is_immediate_prefix (*input_line_pointer
))
1202 input_line_pointer
++;
1206 if (exp
.X_op
!= O_constant
)
1208 as_bad (_("expected #constant"));
1209 ignore_rest_of_line ();
1212 *val
= exp
.X_add_number
;
1217 /* Register parsing. */
1219 /* Generic register parser. CCP points to what should be the
1220 beginning of a register name. If it is indeed a valid register
1221 name, advance CCP over it and return the reg_entry structure;
1222 otherwise return NULL. Does not issue diagnostics. */
1224 static struct reg_entry
*
1225 arm_reg_parse_multi (char **ccp
)
1229 struct reg_entry
*reg
;
1231 skip_whitespace (start
);
1233 #ifdef REGISTER_PREFIX
1234 if (*start
!= REGISTER_PREFIX
)
1238 #ifdef OPTIONAL_REGISTER_PREFIX
1239 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1244 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1249 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1251 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1261 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1262 enum arm_reg_type type
)
1264 /* Alternative syntaxes are accepted for a few register classes. */
1271 /* Generic coprocessor register names are allowed for these. */
1272 if (reg
&& reg
->type
== REG_TYPE_CN
)
1277 /* For backward compatibility, a bare number is valid here. */
1279 unsigned long processor
= strtoul (start
, ccp
, 10);
1280 if (*ccp
!= start
&& processor
<= 15)
1285 case REG_TYPE_MMXWC
:
1286 /* WC includes WCG. ??? I'm not sure this is true for all
1287 instructions that take WC registers. */
1288 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1299 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1300 return value is the register number or FAIL. */
1303 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1306 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1309 /* Do not allow a scalar (reg+index) to parse as a register. */
1310 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1313 if (reg
&& reg
->type
== type
)
1316 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1323 /* Parse a Neon type specifier. *STR should point at the leading '.'
1324 character. Does no verification at this stage that the type fits the opcode
1331 Can all be legally parsed by this function.
1333 Fills in neon_type struct pointer with parsed information, and updates STR
1334 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1335 type, FAIL if not. */
1338 parse_neon_type (struct neon_type
*type
, char **str
)
1345 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1347 enum neon_el_type thistype
= NT_untyped
;
1348 unsigned thissize
= -1u;
1355 /* Just a size without an explicit type. */
1359 switch (TOLOWER (*ptr
))
1361 case 'i': thistype
= NT_integer
; break;
1362 case 'f': thistype
= NT_float
; break;
1363 case 'p': thistype
= NT_poly
; break;
1364 case 's': thistype
= NT_signed
; break;
1365 case 'u': thistype
= NT_unsigned
; break;
1367 thistype
= NT_float
;
1372 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1378 /* .f is an abbreviation for .f32. */
1379 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1384 thissize
= strtoul (ptr
, &ptr
, 10);
1386 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1389 as_bad (_("bad size %d in type specifier"), thissize
);
1397 type
->el
[type
->elems
].type
= thistype
;
1398 type
->el
[type
->elems
].size
= thissize
;
1403 /* Empty/missing type is not a successful parse. */
1404 if (type
->elems
== 0)
1412 /* Errors may be set multiple times during parsing or bit encoding
1413 (particularly in the Neon bits), but usually the earliest error which is set
1414 will be the most meaningful. Avoid overwriting it with later (cascading)
1415 errors by calling this function. */
1418 first_error (const char *err
)
1424 /* Parse a single type, e.g. ".s32", leading period included. */
1426 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1429 struct neon_type optype
;
1433 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1435 if (optype
.elems
== 1)
1436 *vectype
= optype
.el
[0];
1439 first_error (_("only one type should be specified for operand"));
1445 first_error (_("vector type expected"));
1457 /* Special meanings for indices (which have a range of 0-7), which will fit into
1460 #define NEON_ALL_LANES 15
1461 #define NEON_INTERLEAVE_LANES 14
1463 /* Parse either a register or a scalar, with an optional type. Return the
1464 register number, and optionally fill in the actual type of the register
1465 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1466 type/index information in *TYPEINFO. */
1469 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1470 enum arm_reg_type
*rtype
,
1471 struct neon_typed_alias
*typeinfo
)
1474 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1475 struct neon_typed_alias atype
;
1476 struct neon_type_el parsetype
;
1480 atype
.eltype
.type
= NT_invtype
;
1481 atype
.eltype
.size
= -1;
1483 /* Try alternate syntax for some types of register. Note these are mutually
1484 exclusive with the Neon syntax extensions. */
1487 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1495 /* Undo polymorphism when a set of register types may be accepted. */
1496 if ((type
== REG_TYPE_NDQ
1497 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1498 || (type
== REG_TYPE_VFSD
1499 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1500 || (type
== REG_TYPE_NSDQ
1501 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1502 || reg
->type
== REG_TYPE_NQ
))
1503 || (type
== REG_TYPE_MMXWC
1504 && (reg
->type
== REG_TYPE_MMXWCG
)))
1505 type
= (enum arm_reg_type
) reg
->type
;
1507 if (type
!= reg
->type
)
1513 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1515 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1517 first_error (_("can't redefine type for operand"));
1520 atype
.defined
|= NTA_HASTYPE
;
1521 atype
.eltype
= parsetype
;
1524 if (skip_past_char (&str
, '[') == SUCCESS
)
1526 if (type
!= REG_TYPE_VFD
)
1528 first_error (_("only D registers may be indexed"));
1532 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1534 first_error (_("can't change index for operand"));
1538 atype
.defined
|= NTA_HASINDEX
;
1540 if (skip_past_char (&str
, ']') == SUCCESS
)
1541 atype
.index
= NEON_ALL_LANES
;
1546 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1548 if (exp
.X_op
!= O_constant
)
1550 first_error (_("constant expression required"));
1554 if (skip_past_char (&str
, ']') == FAIL
)
1557 atype
.index
= exp
.X_add_number
;
1572 /* Like arm_reg_parse, but allow allow the following extra features:
1573 - If RTYPE is non-zero, return the (possibly restricted) type of the
1574 register (e.g. Neon double or quad reg when either has been requested).
1575 - If this is a Neon vector type with additional type information, fill
1576 in the struct pointed to by VECTYPE (if non-NULL).
1577 This function will fault on encountering a scalar. */
1580 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1581 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1583 struct neon_typed_alias atype
;
1585 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1590 /* Do not allow regname(... to parse as a register. */
1594 /* Do not allow a scalar (reg+index) to parse as a register. */
1595 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1597 first_error (_("register operand expected, but got scalar"));
1602 *vectype
= atype
.eltype
;
1609 #define NEON_SCALAR_REG(X) ((X) >> 4)
1610 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1612 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1613 have enough information to be able to do a good job bounds-checking. So, we
1614 just do easy checks here, and do further checks later. */
1617 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1621 struct neon_typed_alias atype
;
1623 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1625 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1628 if (atype
.index
== NEON_ALL_LANES
)
1630 first_error (_("scalar must have an index"));
1633 else if (atype
.index
>= 64 / elsize
)
1635 first_error (_("scalar index out of range"));
1640 *type
= atype
.eltype
;
1644 return reg
* 16 + atype
.index
;
1647 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1650 parse_reg_list (char ** strp
)
1652 char * str
= * strp
;
1656 /* We come back here if we get ranges concatenated by '+' or '|'. */
1659 skip_whitespace (str
);
1673 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1675 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1685 first_error (_("bad range in register list"));
1689 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1691 if (range
& (1 << i
))
1693 (_("Warning: duplicated register (r%d) in register list"),
1701 if (range
& (1 << reg
))
1702 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1704 else if (reg
<= cur_reg
)
1705 as_tsktsk (_("Warning: register range not in ascending order"));
1710 while (skip_past_comma (&str
) != FAIL
1711 || (in_range
= 1, *str
++ == '-'));
1714 if (skip_past_char (&str
, '}') == FAIL
)
1716 first_error (_("missing `}'"));
1724 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1727 if (exp
.X_op
== O_constant
)
1729 if (exp
.X_add_number
1730 != (exp
.X_add_number
& 0x0000ffff))
1732 inst
.error
= _("invalid register mask");
1736 if ((range
& exp
.X_add_number
) != 0)
1738 int regno
= range
& exp
.X_add_number
;
1741 regno
= (1 << regno
) - 1;
1743 (_("Warning: duplicated register (r%d) in register list"),
1747 range
|= exp
.X_add_number
;
1751 if (inst
.reloc
.type
!= 0)
1753 inst
.error
= _("expression too complex");
1757 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1758 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1759 inst
.reloc
.pc_rel
= 0;
1763 if (*str
== '|' || *str
== '+')
1769 while (another_range
);
1775 /* Types of registers in a list. */
1784 /* Parse a VFP register list. If the string is invalid return FAIL.
1785 Otherwise return the number of registers, and set PBASE to the first
1786 register. Parses registers of type ETYPE.
1787 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1788 - Q registers can be used to specify pairs of D registers
1789 - { } can be omitted from around a singleton register list
1790 FIXME: This is not implemented, as it would require backtracking in
1793 This could be done (the meaning isn't really ambiguous), but doesn't
1794 fit in well with the current parsing framework.
1795 - 32 D registers may be used (also true for VFPv3).
1796 FIXME: Types are ignored in these register lists, which is probably a
1800 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1805 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1809 unsigned long mask
= 0;
1812 if (skip_past_char (&str
, '{') == FAIL
)
1814 inst
.error
= _("expecting {");
1821 regtype
= REG_TYPE_VFS
;
1826 regtype
= REG_TYPE_VFD
;
1829 case REGLIST_NEON_D
:
1830 regtype
= REG_TYPE_NDQ
;
1834 if (etype
!= REGLIST_VFP_S
)
1836 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1837 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1841 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1844 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1851 base_reg
= max_regs
;
1855 int setmask
= 1, addregs
= 1;
1857 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1859 if (new_base
== FAIL
)
1861 first_error (_(reg_expected_msgs
[regtype
]));
1865 if (new_base
>= max_regs
)
1867 first_error (_("register out of range in list"));
1871 /* Note: a value of 2 * n is returned for the register Q<n>. */
1872 if (regtype
== REG_TYPE_NQ
)
1878 if (new_base
< base_reg
)
1879 base_reg
= new_base
;
1881 if (mask
& (setmask
<< new_base
))
1883 first_error (_("invalid register list"));
1887 if ((mask
>> new_base
) != 0 && ! warned
)
1889 as_tsktsk (_("register list not in ascending order"));
1893 mask
|= setmask
<< new_base
;
1896 if (*str
== '-') /* We have the start of a range expression */
1902 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1905 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1909 if (high_range
>= max_regs
)
1911 first_error (_("register out of range in list"));
1915 if (regtype
== REG_TYPE_NQ
)
1916 high_range
= high_range
+ 1;
1918 if (high_range
<= new_base
)
1920 inst
.error
= _("register range not in ascending order");
1924 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1926 if (mask
& (setmask
<< new_base
))
1928 inst
.error
= _("invalid register list");
1932 mask
|= setmask
<< new_base
;
1937 while (skip_past_comma (&str
) != FAIL
);
1941 /* Sanity check -- should have raised a parse error above. */
1942 if (count
== 0 || count
> max_regs
)
1947 /* Final test -- the registers must be consecutive. */
1949 for (i
= 0; i
< count
; i
++)
1951 if ((mask
& (1u << i
)) == 0)
1953 inst
.error
= _("non-contiguous register range");
1963 /* True if two alias types are the same. */
1966 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1974 if (a
->defined
!= b
->defined
)
1977 if ((a
->defined
& NTA_HASTYPE
) != 0
1978 && (a
->eltype
.type
!= b
->eltype
.type
1979 || a
->eltype
.size
!= b
->eltype
.size
))
1982 if ((a
->defined
& NTA_HASINDEX
) != 0
1983 && (a
->index
!= b
->index
))
1989 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1990 The base register is put in *PBASE.
1991 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1993 The register stride (minus one) is put in bit 4 of the return value.
1994 Bits [6:5] encode the list length (minus one).
1995 The type of the list elements is put in *ELTYPE, if non-NULL. */
1997 #define NEON_LANE(X) ((X) & 0xf)
1998 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1999 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2002 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2003 struct neon_type_el
*eltype
)
2010 int leading_brace
= 0;
2011 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2012 const char *const incr_error
= _("register stride must be 1 or 2");
2013 const char *const type_error
= _("mismatched element/structure types in list");
2014 struct neon_typed_alias firsttype
;
2015 firsttype
.defined
= 0;
2016 firsttype
.eltype
.type
= NT_invtype
;
2017 firsttype
.eltype
.size
= -1;
2018 firsttype
.index
= -1;
2020 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2025 struct neon_typed_alias atype
;
2026 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2030 first_error (_(reg_expected_msgs
[rtype
]));
2037 if (rtype
== REG_TYPE_NQ
)
2043 else if (reg_incr
== -1)
2045 reg_incr
= getreg
- base_reg
;
2046 if (reg_incr
< 1 || reg_incr
> 2)
2048 first_error (_(incr_error
));
2052 else if (getreg
!= base_reg
+ reg_incr
* count
)
2054 first_error (_(incr_error
));
2058 if (! neon_alias_types_same (&atype
, &firsttype
))
2060 first_error (_(type_error
));
2064 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2068 struct neon_typed_alias htype
;
2069 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2071 lane
= NEON_INTERLEAVE_LANES
;
2072 else if (lane
!= NEON_INTERLEAVE_LANES
)
2074 first_error (_(type_error
));
2079 else if (reg_incr
!= 1)
2081 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2085 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2088 first_error (_(reg_expected_msgs
[rtype
]));
2091 if (! neon_alias_types_same (&htype
, &firsttype
))
2093 first_error (_(type_error
));
2096 count
+= hireg
+ dregs
- getreg
;
2100 /* If we're using Q registers, we can't use [] or [n] syntax. */
2101 if (rtype
== REG_TYPE_NQ
)
2107 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2111 else if (lane
!= atype
.index
)
2113 first_error (_(type_error
));
2117 else if (lane
== -1)
2118 lane
= NEON_INTERLEAVE_LANES
;
2119 else if (lane
!= NEON_INTERLEAVE_LANES
)
2121 first_error (_(type_error
));
2126 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2128 /* No lane set by [x]. We must be interleaving structures. */
2130 lane
= NEON_INTERLEAVE_LANES
;
2133 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2134 || (count
> 1 && reg_incr
== -1))
2136 first_error (_("error parsing element/structure list"));
2140 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2142 first_error (_("expected }"));
2150 *eltype
= firsttype
.eltype
;
2155 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2158 /* Parse an explicit relocation suffix on an expression. This is
2159 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2160 arm_reloc_hsh contains no entries, so this function can only
2161 succeed if there is no () after the word. Returns -1 on error,
2162 BFD_RELOC_UNUSED if there wasn't any suffix. */
2165 parse_reloc (char **str
)
2167 struct reloc_entry
*r
;
2171 return BFD_RELOC_UNUSED
;
2176 while (*q
&& *q
!= ')' && *q
!= ',')
2181 if ((r
= (struct reloc_entry
*)
2182 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2189 /* Directives: register aliases. */
2191 static struct reg_entry
*
2192 insert_reg_alias (char *str
, unsigned number
, int type
)
2194 struct reg_entry
*new_reg
;
2197 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2199 if (new_reg
->builtin
)
2200 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2202 /* Only warn about a redefinition if it's not defined as the
2204 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2205 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2210 name
= xstrdup (str
);
2211 new_reg
= XNEW (struct reg_entry
);
2213 new_reg
->name
= name
;
2214 new_reg
->number
= number
;
2215 new_reg
->type
= type
;
2216 new_reg
->builtin
= FALSE
;
2217 new_reg
->neon
= NULL
;
2219 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2226 insert_neon_reg_alias (char *str
, int number
, int type
,
2227 struct neon_typed_alias
*atype
)
2229 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2233 first_error (_("attempt to redefine typed alias"));
2239 reg
->neon
= XNEW (struct neon_typed_alias
);
2240 *reg
->neon
= *atype
;
2244 /* Look for the .req directive. This is of the form:
2246 new_register_name .req existing_register_name
2248 If we find one, or if it looks sufficiently like one that we want to
2249 handle any error here, return TRUE. Otherwise return FALSE. */
2252 create_register_alias (char * newname
, char *p
)
2254 struct reg_entry
*old
;
2255 char *oldname
, *nbuf
;
2258 /* The input scrubber ensures that whitespace after the mnemonic is
2259 collapsed to single spaces. */
2261 if (strncmp (oldname
, " .req ", 6) != 0)
2265 if (*oldname
== '\0')
2268 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2271 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2275 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2276 the desired alias name, and p points to its end. If not, then
2277 the desired alias name is in the global original_case_string. */
2278 #ifdef TC_CASE_SENSITIVE
2281 newname
= original_case_string
;
2282 nlen
= strlen (newname
);
2285 nbuf
= xmemdup0 (newname
, nlen
);
2287 /* Create aliases under the new name as stated; an all-lowercase
2288 version of the new name; and an all-uppercase version of the new
2290 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2292 for (p
= nbuf
; *p
; p
++)
2295 if (strncmp (nbuf
, newname
, nlen
))
2297 /* If this attempt to create an additional alias fails, do not bother
2298 trying to create the all-lower case alias. We will fail and issue
2299 a second, duplicate error message. This situation arises when the
2300 programmer does something like:
2303 The second .req creates the "Foo" alias but then fails to create
2304 the artificial FOO alias because it has already been created by the
2306 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2313 for (p
= nbuf
; *p
; p
++)
2316 if (strncmp (nbuf
, newname
, nlen
))
2317 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2324 /* Create a Neon typed/indexed register alias using directives, e.g.:
2329 These typed registers can be used instead of the types specified after the
2330 Neon mnemonic, so long as all operands given have types. Types can also be
2331 specified directly, e.g.:
2332 vadd d0.s32, d1.s32, d2.s32 */
2335 create_neon_reg_alias (char *newname
, char *p
)
2337 enum arm_reg_type basetype
;
2338 struct reg_entry
*basereg
;
2339 struct reg_entry mybasereg
;
2340 struct neon_type ntype
;
2341 struct neon_typed_alias typeinfo
;
2342 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2345 typeinfo
.defined
= 0;
2346 typeinfo
.eltype
.type
= NT_invtype
;
2347 typeinfo
.eltype
.size
= -1;
2348 typeinfo
.index
= -1;
2352 if (strncmp (p
, " .dn ", 5) == 0)
2353 basetype
= REG_TYPE_VFD
;
2354 else if (strncmp (p
, " .qn ", 5) == 0)
2355 basetype
= REG_TYPE_NQ
;
2364 basereg
= arm_reg_parse_multi (&p
);
2366 if (basereg
&& basereg
->type
!= basetype
)
2368 as_bad (_("bad type for register"));
2372 if (basereg
== NULL
)
2375 /* Try parsing as an integer. */
2376 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2377 if (exp
.X_op
!= O_constant
)
2379 as_bad (_("expression must be constant"));
2382 basereg
= &mybasereg
;
2383 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2389 typeinfo
= *basereg
->neon
;
2391 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2393 /* We got a type. */
2394 if (typeinfo
.defined
& NTA_HASTYPE
)
2396 as_bad (_("can't redefine the type of a register alias"));
2400 typeinfo
.defined
|= NTA_HASTYPE
;
2401 if (ntype
.elems
!= 1)
2403 as_bad (_("you must specify a single type only"));
2406 typeinfo
.eltype
= ntype
.el
[0];
2409 if (skip_past_char (&p
, '[') == SUCCESS
)
2412 /* We got a scalar index. */
2414 if (typeinfo
.defined
& NTA_HASINDEX
)
2416 as_bad (_("can't redefine the index of a scalar alias"));
2420 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2422 if (exp
.X_op
!= O_constant
)
2424 as_bad (_("scalar index must be constant"));
2428 typeinfo
.defined
|= NTA_HASINDEX
;
2429 typeinfo
.index
= exp
.X_add_number
;
2431 if (skip_past_char (&p
, ']') == FAIL
)
2433 as_bad (_("expecting ]"));
2438 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2439 the desired alias name, and p points to its end. If not, then
2440 the desired alias name is in the global original_case_string. */
2441 #ifdef TC_CASE_SENSITIVE
2442 namelen
= nameend
- newname
;
2444 newname
= original_case_string
;
2445 namelen
= strlen (newname
);
2448 namebuf
= xmemdup0 (newname
, namelen
);
2450 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2451 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2453 /* Insert name in all uppercase. */
2454 for (p
= namebuf
; *p
; p
++)
2457 if (strncmp (namebuf
, newname
, namelen
))
2458 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2459 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2461 /* Insert name in all lowercase. */
2462 for (p
= namebuf
; *p
; p
++)
2465 if (strncmp (namebuf
, newname
, namelen
))
2466 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2467 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2473 /* Should never be called, as .req goes between the alias and the
2474 register name, not at the beginning of the line. */
2477 s_req (int a ATTRIBUTE_UNUSED
)
2479 as_bad (_("invalid syntax for .req directive"));
2483 s_dn (int a ATTRIBUTE_UNUSED
)
2485 as_bad (_("invalid syntax for .dn directive"));
2489 s_qn (int a ATTRIBUTE_UNUSED
)
2491 as_bad (_("invalid syntax for .qn directive"));
2494 /* The .unreq directive deletes an alias which was previously defined
2495 by .req. For example:
2501 s_unreq (int a ATTRIBUTE_UNUSED
)
2506 name
= input_line_pointer
;
2508 while (*input_line_pointer
!= 0
2509 && *input_line_pointer
!= ' '
2510 && *input_line_pointer
!= '\n')
2511 ++input_line_pointer
;
2513 saved_char
= *input_line_pointer
;
2514 *input_line_pointer
= 0;
2517 as_bad (_("invalid syntax for .unreq directive"));
2520 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2524 as_bad (_("unknown register alias '%s'"), name
);
2525 else if (reg
->builtin
)
2526 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2533 hash_delete (arm_reg_hsh
, name
, FALSE
);
2534 free ((char *) reg
->name
);
2539 /* Also locate the all upper case and all lower case versions.
2540 Do not complain if we cannot find one or the other as it
2541 was probably deleted above. */
2543 nbuf
= strdup (name
);
2544 for (p
= nbuf
; *p
; p
++)
2546 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2549 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2550 free ((char *) reg
->name
);
2556 for (p
= nbuf
; *p
; p
++)
2558 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2561 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2562 free ((char *) reg
->name
);
2572 *input_line_pointer
= saved_char
;
2573 demand_empty_rest_of_line ();
2576 /* Directives: Instruction set selection. */
2579 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2580 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2581 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2582 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2584 /* Create a new mapping symbol for the transition to STATE. */
2587 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2590 const char * symname
;
2597 type
= BSF_NO_FLAGS
;
2601 type
= BSF_NO_FLAGS
;
2605 type
= BSF_NO_FLAGS
;
2611 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2612 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2617 THUMB_SET_FUNC (symbolP
, 0);
2618 ARM_SET_THUMB (symbolP
, 0);
2619 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2623 THUMB_SET_FUNC (symbolP
, 1);
2624 ARM_SET_THUMB (symbolP
, 1);
2625 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2633 /* Save the mapping symbols for future reference. Also check that
2634 we do not place two mapping symbols at the same offset within a
2635 frag. We'll handle overlap between frags in
2636 check_mapping_symbols.
2638 If .fill or other data filling directive generates zero sized data,
2639 the mapping symbol for the following code will have the same value
2640 as the one generated for the data filling directive. In this case,
2641 we replace the old symbol with the new one at the same address. */
2644 if (frag
->tc_frag_data
.first_map
!= NULL
)
2646 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2647 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2649 frag
->tc_frag_data
.first_map
= symbolP
;
2651 if (frag
->tc_frag_data
.last_map
!= NULL
)
2653 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2654 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2655 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2657 frag
->tc_frag_data
.last_map
= symbolP
;
2660 /* We must sometimes convert a region marked as code to data during
2661 code alignment, if an odd number of bytes have to be padded. The
2662 code mapping symbol is pushed to an aligned address. */
2665 insert_data_mapping_symbol (enum mstate state
,
2666 valueT value
, fragS
*frag
, offsetT bytes
)
2668 /* If there was already a mapping symbol, remove it. */
2669 if (frag
->tc_frag_data
.last_map
!= NULL
2670 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2672 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2676 know (frag
->tc_frag_data
.first_map
== symp
);
2677 frag
->tc_frag_data
.first_map
= NULL
;
2679 frag
->tc_frag_data
.last_map
= NULL
;
2680 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2683 make_mapping_symbol (MAP_DATA
, value
, frag
);
2684 make_mapping_symbol (state
, value
+ bytes
, frag
);
2687 static void mapping_state_2 (enum mstate state
, int max_chars
);
2689 /* Set the mapping state to STATE. Only call this when about to
2690 emit some STATE bytes to the file. */
2692 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2694 mapping_state (enum mstate state
)
2696 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2698 if (mapstate
== state
)
2699 /* The mapping symbol has already been emitted.
2700 There is nothing else to do. */
2703 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2705 All ARM instructions require 4-byte alignment.
2706 (Almost) all Thumb instructions require 2-byte alignment.
2708 When emitting instructions into any section, mark the section
2711 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2712 but themselves require 2-byte alignment; this applies to some
2713 PC- relative forms. However, these cases will involve implicit
2714 literal pool generation or an explicit .align >=2, both of
2715 which will cause the section to me marked with sufficient
2716 alignment. Thus, we don't handle those cases here. */
2717 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2719 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2720 /* This case will be evaluated later. */
2723 mapping_state_2 (state
, 0);
2726 /* Same as mapping_state, but MAX_CHARS bytes have already been
2727 allocated. Put the mapping symbol that far back. */
2730 mapping_state_2 (enum mstate state
, int max_chars
)
2732 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2734 if (!SEG_NORMAL (now_seg
))
2737 if (mapstate
== state
)
2738 /* The mapping symbol has already been emitted.
2739 There is nothing else to do. */
2742 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2743 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2745 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2746 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2749 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2752 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2753 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2757 #define mapping_state(x) ((void)0)
2758 #define mapping_state_2(x, y) ((void)0)
2761 /* Find the real, Thumb encoded start of a Thumb function. */
2765 find_real_start (symbolS
* symbolP
)
2768 const char * name
= S_GET_NAME (symbolP
);
2769 symbolS
* new_target
;
2771 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2772 #define STUB_NAME ".real_start_of"
2777 /* The compiler may generate BL instructions to local labels because
2778 it needs to perform a branch to a far away location. These labels
2779 do not have a corresponding ".real_start_of" label. We check
2780 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2781 the ".real_start_of" convention for nonlocal branches. */
2782 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2785 real_start
= concat (STUB_NAME
, name
, NULL
);
2786 new_target
= symbol_find (real_start
);
2789 if (new_target
== NULL
)
2791 as_warn (_("Failed to find real start of function: %s\n"), name
);
2792 new_target
= symbolP
;
2800 opcode_select (int width
)
2807 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2808 as_bad (_("selected processor does not support THUMB opcodes"));
2811 /* No need to force the alignment, since we will have been
2812 coming from ARM mode, which is word-aligned. */
2813 record_alignment (now_seg
, 1);
2820 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2821 as_bad (_("selected processor does not support ARM opcodes"));
2826 frag_align (2, 0, 0);
2828 record_alignment (now_seg
, 1);
2833 as_bad (_("invalid instruction size selected (%d)"), width
);
2838 s_arm (int ignore ATTRIBUTE_UNUSED
)
2841 demand_empty_rest_of_line ();
2845 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2848 demand_empty_rest_of_line ();
2852 s_code (int unused ATTRIBUTE_UNUSED
)
2856 temp
= get_absolute_expression ();
2861 opcode_select (temp
);
2865 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2870 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2872 /* If we are not already in thumb mode go into it, EVEN if
2873 the target processor does not support thumb instructions.
2874 This is used by gcc/config/arm/lib1funcs.asm for example
2875 to compile interworking support functions even if the
2876 target processor should not support interworking. */
2880 record_alignment (now_seg
, 1);
2883 demand_empty_rest_of_line ();
2887 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2891 /* The following label is the name/address of the start of a Thumb function.
2892 We need to know this for the interworking support. */
2893 label_is_thumb_function_name
= TRUE
;
2896 /* Perform a .set directive, but also mark the alias as
2897 being a thumb function. */
2900 s_thumb_set (int equiv
)
2902 /* XXX the following is a duplicate of the code for s_set() in read.c
2903 We cannot just call that code as we need to get at the symbol that
2910 /* Especial apologies for the random logic:
2911 This just grew, and could be parsed much more simply!
2913 delim
= get_symbol_name (& name
);
2914 end_name
= input_line_pointer
;
2915 (void) restore_line_pointer (delim
);
2917 if (*input_line_pointer
!= ',')
2920 as_bad (_("expected comma after name \"%s\""), name
);
2922 ignore_rest_of_line ();
2926 input_line_pointer
++;
2929 if (name
[0] == '.' && name
[1] == '\0')
2931 /* XXX - this should not happen to .thumb_set. */
2935 if ((symbolP
= symbol_find (name
)) == NULL
2936 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2939 /* When doing symbol listings, play games with dummy fragments living
2940 outside the normal fragment chain to record the file and line info
2942 if (listing
& LISTING_SYMBOLS
)
2944 extern struct list_info_struct
* listing_tail
;
2945 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2947 memset (dummy_frag
, 0, sizeof (fragS
));
2948 dummy_frag
->fr_type
= rs_fill
;
2949 dummy_frag
->line
= listing_tail
;
2950 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2951 dummy_frag
->fr_symbol
= symbolP
;
2955 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2958 /* "set" symbols are local unless otherwise specified. */
2959 SF_SET_LOCAL (symbolP
);
2960 #endif /* OBJ_COFF */
2961 } /* Make a new symbol. */
2963 symbol_table_insert (symbolP
);
2968 && S_IS_DEFINED (symbolP
)
2969 && S_GET_SEGMENT (symbolP
) != reg_section
)
2970 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2972 pseudo_set (symbolP
);
2974 demand_empty_rest_of_line ();
2976 /* XXX Now we come to the Thumb specific bit of code. */
2978 THUMB_SET_FUNC (symbolP
, 1);
2979 ARM_SET_THUMB (symbolP
, 1);
2980 #if defined OBJ_ELF || defined OBJ_COFF
2981 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2985 /* Directives: Mode selection. */
2987 /* .syntax [unified|divided] - choose the new unified syntax
2988 (same for Arm and Thumb encoding, modulo slight differences in what
2989 can be represented) or the old divergent syntax for each mode. */
2991 s_syntax (int unused ATTRIBUTE_UNUSED
)
2995 delim
= get_symbol_name (& name
);
2997 if (!strcasecmp (name
, "unified"))
2998 unified_syntax
= TRUE
;
2999 else if (!strcasecmp (name
, "divided"))
3000 unified_syntax
= FALSE
;
3003 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3006 (void) restore_line_pointer (delim
);
3007 demand_empty_rest_of_line ();
3010 /* Directives: sectioning and alignment. */
3013 s_bss (int ignore ATTRIBUTE_UNUSED
)
3015 /* We don't support putting frags in the BSS segment, we fake it by
3016 marking in_bss, then looking at s_skip for clues. */
3017 subseg_set (bss_section
, 0);
3018 demand_empty_rest_of_line ();
3020 #ifdef md_elf_section_change_hook
3021 md_elf_section_change_hook ();
3026 s_even (int ignore ATTRIBUTE_UNUSED
)
3028 /* Never make frag if expect extra pass. */
3030 frag_align (1, 0, 0);
3032 record_alignment (now_seg
, 1);
3034 demand_empty_rest_of_line ();
3037 /* Directives: CodeComposer Studio. */
3039 /* .ref (for CodeComposer Studio syntax only). */
3041 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3043 if (codecomposer_syntax
)
3044 ignore_rest_of_line ();
3046 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3049 /* If name is not NULL, then it is used for marking the beginning of a
3050 function, whereas if it is NULL then it means the function end. */
3052 asmfunc_debug (const char * name
)
3054 static const char * last_name
= NULL
;
3058 gas_assert (last_name
== NULL
);
3061 if (debug_type
== DEBUG_STABS
)
3062 stabs_generate_asm_func (name
, name
);
3066 gas_assert (last_name
!= NULL
);
3068 if (debug_type
== DEBUG_STABS
)
3069 stabs_generate_asm_endfunc (last_name
, last_name
);
3076 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3078 if (codecomposer_syntax
)
3080 switch (asmfunc_state
)
3082 case OUTSIDE_ASMFUNC
:
3083 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3086 case WAITING_ASMFUNC_NAME
:
3087 as_bad (_(".asmfunc repeated."));
3090 case WAITING_ENDASMFUNC
:
3091 as_bad (_(".asmfunc without function."));
3094 demand_empty_rest_of_line ();
3097 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3101 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3103 if (codecomposer_syntax
)
3105 switch (asmfunc_state
)
3107 case OUTSIDE_ASMFUNC
:
3108 as_bad (_(".endasmfunc without a .asmfunc."));
3111 case WAITING_ASMFUNC_NAME
:
3112 as_bad (_(".endasmfunc without function."));
3115 case WAITING_ENDASMFUNC
:
3116 asmfunc_state
= OUTSIDE_ASMFUNC
;
3117 asmfunc_debug (NULL
);
3120 demand_empty_rest_of_line ();
3123 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3127 s_ccs_def (int name
)
3129 if (codecomposer_syntax
)
3132 as_bad (_(".def pseudo-op only available with -mccs flag."));
3135 /* Directives: Literal pools. */
3137 static literal_pool
*
3138 find_literal_pool (void)
3140 literal_pool
* pool
;
3142 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3144 if (pool
->section
== now_seg
3145 && pool
->sub_section
== now_subseg
)
3152 static literal_pool
*
3153 find_or_make_literal_pool (void)
3155 /* Next literal pool ID number. */
3156 static unsigned int latest_pool_num
= 1;
3157 literal_pool
* pool
;
3159 pool
= find_literal_pool ();
3163 /* Create a new pool. */
3164 pool
= XNEW (literal_pool
);
3168 pool
->next_free_entry
= 0;
3169 pool
->section
= now_seg
;
3170 pool
->sub_section
= now_subseg
;
3171 pool
->next
= list_of_pools
;
3172 pool
->symbol
= NULL
;
3173 pool
->alignment
= 2;
3175 /* Add it to the list. */
3176 list_of_pools
= pool
;
3179 /* New pools, and emptied pools, will have a NULL symbol. */
3180 if (pool
->symbol
== NULL
)
3182 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3183 (valueT
) 0, &zero_address_frag
);
3184 pool
->id
= latest_pool_num
++;
3191 /* Add the literal in the global 'inst'
3192 structure to the relevant literal pool. */
3195 add_to_lit_pool (unsigned int nbytes
)
3197 #define PADDING_SLOT 0x1
3198 #define LIT_ENTRY_SIZE_MASK 0xFF
3199 literal_pool
* pool
;
3200 unsigned int entry
, pool_size
= 0;
3201 bfd_boolean padding_slot_p
= FALSE
;
3207 imm1
= inst
.operands
[1].imm
;
3208 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3209 : inst
.reloc
.exp
.X_unsigned
? 0
3210 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3211 if (target_big_endian
)
3214 imm2
= inst
.operands
[1].imm
;
3218 pool
= find_or_make_literal_pool ();
3220 /* Check if this literal value is already in the pool. */
3221 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3225 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3226 && (inst
.reloc
.exp
.X_op
== O_constant
)
3227 && (pool
->literals
[entry
].X_add_number
3228 == inst
.reloc
.exp
.X_add_number
)
3229 && (pool
->literals
[entry
].X_md
== nbytes
)
3230 && (pool
->literals
[entry
].X_unsigned
3231 == inst
.reloc
.exp
.X_unsigned
))
3234 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3235 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3236 && (pool
->literals
[entry
].X_add_number
3237 == inst
.reloc
.exp
.X_add_number
)
3238 && (pool
->literals
[entry
].X_add_symbol
3239 == inst
.reloc
.exp
.X_add_symbol
)
3240 && (pool
->literals
[entry
].X_op_symbol
3241 == inst
.reloc
.exp
.X_op_symbol
)
3242 && (pool
->literals
[entry
].X_md
== nbytes
))
3245 else if ((nbytes
== 8)
3246 && !(pool_size
& 0x7)
3247 && ((entry
+ 1) != pool
->next_free_entry
)
3248 && (pool
->literals
[entry
].X_op
== O_constant
)
3249 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3250 && (pool
->literals
[entry
].X_unsigned
3251 == inst
.reloc
.exp
.X_unsigned
)
3252 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3253 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3254 && (pool
->literals
[entry
+ 1].X_unsigned
3255 == inst
.reloc
.exp
.X_unsigned
))
3258 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3259 if (padding_slot_p
&& (nbytes
== 4))
3265 /* Do we need to create a new entry? */
3266 if (entry
== pool
->next_free_entry
)
3268 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3270 inst
.error
= _("literal pool overflow");
3276 /* For 8-byte entries, we align to an 8-byte boundary,
3277 and split it into two 4-byte entries, because on 32-bit
3278 host, 8-byte constants are treated as big num, thus
3279 saved in "generic_bignum" which will be overwritten
3280 by later assignments.
3282 We also need to make sure there is enough space for
3285 We also check to make sure the literal operand is a
3287 if (!(inst
.reloc
.exp
.X_op
== O_constant
3288 || inst
.reloc
.exp
.X_op
== O_big
))
3290 inst
.error
= _("invalid type for literal pool");
3293 else if (pool_size
& 0x7)
3295 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3297 inst
.error
= _("literal pool overflow");
3301 pool
->literals
[entry
] = inst
.reloc
.exp
;
3302 pool
->literals
[entry
].X_op
= O_constant
;
3303 pool
->literals
[entry
].X_add_number
= 0;
3304 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3305 pool
->next_free_entry
+= 1;
3308 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3310 inst
.error
= _("literal pool overflow");
3314 pool
->literals
[entry
] = inst
.reloc
.exp
;
3315 pool
->literals
[entry
].X_op
= O_constant
;
3316 pool
->literals
[entry
].X_add_number
= imm1
;
3317 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3318 pool
->literals
[entry
++].X_md
= 4;
3319 pool
->literals
[entry
] = inst
.reloc
.exp
;
3320 pool
->literals
[entry
].X_op
= O_constant
;
3321 pool
->literals
[entry
].X_add_number
= imm2
;
3322 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3323 pool
->literals
[entry
].X_md
= 4;
3324 pool
->alignment
= 3;
3325 pool
->next_free_entry
+= 1;
3329 pool
->literals
[entry
] = inst
.reloc
.exp
;
3330 pool
->literals
[entry
].X_md
= 4;
3334 /* PR ld/12974: Record the location of the first source line to reference
3335 this entry in the literal pool. If it turns out during linking that the
3336 symbol does not exist we will be able to give an accurate line number for
3337 the (first use of the) missing reference. */
3338 if (debug_type
== DEBUG_DWARF2
)
3339 dwarf2_where (pool
->locs
+ entry
);
3341 pool
->next_free_entry
+= 1;
3343 else if (padding_slot_p
)
3345 pool
->literals
[entry
] = inst
.reloc
.exp
;
3346 pool
->literals
[entry
].X_md
= nbytes
;
3349 inst
.reloc
.exp
.X_op
= O_symbol
;
3350 inst
.reloc
.exp
.X_add_number
= pool_size
;
3351 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3357 tc_start_label_without_colon (void)
3359 bfd_boolean ret
= TRUE
;
3361 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3363 const char *label
= input_line_pointer
;
3365 while (!is_end_of_line
[(int) label
[-1]])
3370 as_bad (_("Invalid label '%s'"), label
);
3374 asmfunc_debug (label
);
3376 asmfunc_state
= WAITING_ENDASMFUNC
;
3382 /* Can't use symbol_new here, so have to create a symbol and then at
3383 a later date assign it a value. That's what these functions do. */
3386 symbol_locate (symbolS
* symbolP
,
3387 const char * name
, /* It is copied, the caller can modify. */
3388 segT segment
, /* Segment identifier (SEG_<something>). */
3389 valueT valu
, /* Symbol value. */
3390 fragS
* frag
) /* Associated fragment. */
3393 char * preserved_copy_of_name
;
3395 name_length
= strlen (name
) + 1; /* +1 for \0. */
3396 obstack_grow (¬es
, name
, name_length
);
3397 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3399 #ifdef tc_canonicalize_symbol_name
3400 preserved_copy_of_name
=
3401 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3404 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3406 S_SET_SEGMENT (symbolP
, segment
);
3407 S_SET_VALUE (symbolP
, valu
);
3408 symbol_clear_list_pointers (symbolP
);
3410 symbol_set_frag (symbolP
, frag
);
3412 /* Link to end of symbol chain. */
3414 extern int symbol_table_frozen
;
3416 if (symbol_table_frozen
)
3420 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3422 obj_symbol_new_hook (symbolP
);
3424 #ifdef tc_symbol_new_hook
3425 tc_symbol_new_hook (symbolP
);
3429 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3430 #endif /* DEBUG_SYMS */
3434 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3437 literal_pool
* pool
;
3440 pool
= find_literal_pool ();
3442 || pool
->symbol
== NULL
3443 || pool
->next_free_entry
== 0)
3446 /* Align pool as you have word accesses.
3447 Only make a frag if we have to. */
3449 frag_align (pool
->alignment
, 0, 0);
3451 record_alignment (now_seg
, 2);
3454 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3455 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3457 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3459 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3460 (valueT
) frag_now_fix (), frag_now
);
3461 symbol_table_insert (pool
->symbol
);
3463 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3465 #if defined OBJ_COFF || defined OBJ_ELF
3466 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3469 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3472 if (debug_type
== DEBUG_DWARF2
)
3473 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3475 /* First output the expression in the instruction to the pool. */
3476 emit_expr (&(pool
->literals
[entry
]),
3477 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3480 /* Mark the pool as empty. */
3481 pool
->next_free_entry
= 0;
3482 pool
->symbol
= NULL
;
3486 /* Forward declarations for functions below, in the MD interface
3488 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3489 static valueT
create_unwind_entry (int);
3490 static void start_unwind_section (const segT
, int);
3491 static void add_unwind_opcode (valueT
, int);
3492 static void flush_pending_unwind (void);
3494 /* Directives: Data. */
3497 s_arm_elf_cons (int nbytes
)
3501 #ifdef md_flush_pending_output
3502 md_flush_pending_output ();
3505 if (is_it_end_of_statement ())
3507 demand_empty_rest_of_line ();
3511 #ifdef md_cons_align
3512 md_cons_align (nbytes
);
3515 mapping_state (MAP_DATA
);
3519 char *base
= input_line_pointer
;
3523 if (exp
.X_op
!= O_symbol
)
3524 emit_expr (&exp
, (unsigned int) nbytes
);
3527 char *before_reloc
= input_line_pointer
;
3528 reloc
= parse_reloc (&input_line_pointer
);
3531 as_bad (_("unrecognized relocation suffix"));
3532 ignore_rest_of_line ();
3535 else if (reloc
== BFD_RELOC_UNUSED
)
3536 emit_expr (&exp
, (unsigned int) nbytes
);
3539 reloc_howto_type
*howto
= (reloc_howto_type
*)
3540 bfd_reloc_type_lookup (stdoutput
,
3541 (bfd_reloc_code_real_type
) reloc
);
3542 int size
= bfd_get_reloc_size (howto
);
3544 if (reloc
== BFD_RELOC_ARM_PLT32
)
3546 as_bad (_("(plt) is only valid on branch targets"));
3547 reloc
= BFD_RELOC_UNUSED
;
3552 as_bad (_("%s relocations do not fit in %d bytes"),
3553 howto
->name
, nbytes
);
3556 /* We've parsed an expression stopping at O_symbol.
3557 But there may be more expression left now that we
3558 have parsed the relocation marker. Parse it again.
3559 XXX Surely there is a cleaner way to do this. */
3560 char *p
= input_line_pointer
;
3562 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3564 memcpy (save_buf
, base
, input_line_pointer
- base
);
3565 memmove (base
+ (input_line_pointer
- before_reloc
),
3566 base
, before_reloc
- base
);
3568 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3570 memcpy (base
, save_buf
, p
- base
);
3572 offset
= nbytes
- size
;
3573 p
= frag_more (nbytes
);
3574 memset (p
, 0, nbytes
);
3575 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3576 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3582 while (*input_line_pointer
++ == ',');
3584 /* Put terminator back into stream. */
3585 input_line_pointer
--;
3586 demand_empty_rest_of_line ();
3589 /* Emit an expression containing a 32-bit thumb instruction.
3590 Implementation based on put_thumb32_insn. */
3593 emit_thumb32_expr (expressionS
* exp
)
3595 expressionS exp_high
= *exp
;
3597 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3598 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3599 exp
->X_add_number
&= 0xffff;
3600 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3603 /* Guess the instruction size based on the opcode. */
3606 thumb_insn_size (int opcode
)
3608 if ((unsigned int) opcode
< 0xe800u
)
3610 else if ((unsigned int) opcode
>= 0xe8000000u
)
3617 emit_insn (expressionS
*exp
, int nbytes
)
3621 if (exp
->X_op
== O_constant
)
3626 size
= thumb_insn_size (exp
->X_add_number
);
3630 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3632 as_bad (_(".inst.n operand too big. "\
3633 "Use .inst.w instead"));
3638 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3639 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3641 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3643 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3644 emit_thumb32_expr (exp
);
3646 emit_expr (exp
, (unsigned int) size
);
3648 it_fsm_post_encode ();
3652 as_bad (_("cannot determine Thumb instruction size. " \
3653 "Use .inst.n/.inst.w instead"));
3656 as_bad (_("constant expression required"));
3661 /* Like s_arm_elf_cons but do not use md_cons_align and
3662 set the mapping state to MAP_ARM/MAP_THUMB. */
3665 s_arm_elf_inst (int nbytes
)
3667 if (is_it_end_of_statement ())
3669 demand_empty_rest_of_line ();
3673 /* Calling mapping_state () here will not change ARM/THUMB,
3674 but will ensure not to be in DATA state. */
3677 mapping_state (MAP_THUMB
);
3682 as_bad (_("width suffixes are invalid in ARM mode"));
3683 ignore_rest_of_line ();
3689 mapping_state (MAP_ARM
);
3698 if (! emit_insn (& exp
, nbytes
))
3700 ignore_rest_of_line ();
3704 while (*input_line_pointer
++ == ',');
3706 /* Put terminator back into stream. */
3707 input_line_pointer
--;
3708 demand_empty_rest_of_line ();
3711 /* Parse a .rel31 directive. */
3714 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3721 if (*input_line_pointer
== '1')
3722 highbit
= 0x80000000;
3723 else if (*input_line_pointer
!= '0')
3724 as_bad (_("expected 0 or 1"));
3726 input_line_pointer
++;
3727 if (*input_line_pointer
!= ',')
3728 as_bad (_("missing comma"));
3729 input_line_pointer
++;
3731 #ifdef md_flush_pending_output
3732 md_flush_pending_output ();
3735 #ifdef md_cons_align
3739 mapping_state (MAP_DATA
);
3744 md_number_to_chars (p
, highbit
, 4);
3745 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3746 BFD_RELOC_ARM_PREL31
);
3748 demand_empty_rest_of_line ();
3751 /* Directives: AEABI stack-unwind tables. */
3753 /* Parse an unwind_fnstart directive. Simply records the current location. */
3756 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3758 demand_empty_rest_of_line ();
3759 if (unwind
.proc_start
)
3761 as_bad (_("duplicate .fnstart directive"));
3765 /* Mark the start of the function. */
3766 unwind
.proc_start
= expr_build_dot ();
3768 /* Reset the rest of the unwind info. */
3769 unwind
.opcode_count
= 0;
3770 unwind
.table_entry
= NULL
;
3771 unwind
.personality_routine
= NULL
;
3772 unwind
.personality_index
= -1;
3773 unwind
.frame_size
= 0;
3774 unwind
.fp_offset
= 0;
3775 unwind
.fp_reg
= REG_SP
;
3777 unwind
.sp_restored
= 0;
3781 /* Parse a handlerdata directive. Creates the exception handling table entry
3782 for the function. */
3785 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3787 demand_empty_rest_of_line ();
3788 if (!unwind
.proc_start
)
3789 as_bad (MISSING_FNSTART
);
3791 if (unwind
.table_entry
)
3792 as_bad (_("duplicate .handlerdata directive"));
3794 create_unwind_entry (1);
3797 /* Parse an unwind_fnend directive. Generates the index table entry. */
3800 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3805 unsigned int marked_pr_dependency
;
3807 demand_empty_rest_of_line ();
3809 if (!unwind
.proc_start
)
3811 as_bad (_(".fnend directive without .fnstart"));
3815 /* Add eh table entry. */
3816 if (unwind
.table_entry
== NULL
)
3817 val
= create_unwind_entry (0);
3821 /* Add index table entry. This is two words. */
3822 start_unwind_section (unwind
.saved_seg
, 1);
3823 frag_align (2, 0, 0);
3824 record_alignment (now_seg
, 2);
3826 ptr
= frag_more (8);
3828 where
= frag_now_fix () - 8;
3830 /* Self relative offset of the function start. */
3831 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3832 BFD_RELOC_ARM_PREL31
);
3834 /* Indicate dependency on EHABI-defined personality routines to the
3835 linker, if it hasn't been done already. */
3836 marked_pr_dependency
3837 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3838 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3839 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3841 static const char *const name
[] =
3843 "__aeabi_unwind_cpp_pr0",
3844 "__aeabi_unwind_cpp_pr1",
3845 "__aeabi_unwind_cpp_pr2"
3847 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3848 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3849 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3850 |= 1 << unwind
.personality_index
;
3854 /* Inline exception table entry. */
3855 md_number_to_chars (ptr
+ 4, val
, 4);
3857 /* Self relative offset of the table entry. */
3858 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3859 BFD_RELOC_ARM_PREL31
);
3861 /* Restore the original section. */
3862 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3864 unwind
.proc_start
= NULL
;
3868 /* Parse an unwind_cantunwind directive. */
3871 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3873 demand_empty_rest_of_line ();
3874 if (!unwind
.proc_start
)
3875 as_bad (MISSING_FNSTART
);
3877 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3878 as_bad (_("personality routine specified for cantunwind frame"));
3880 unwind
.personality_index
= -2;
3884 /* Parse a personalityindex directive. */
3887 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3891 if (!unwind
.proc_start
)
3892 as_bad (MISSING_FNSTART
);
3894 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3895 as_bad (_("duplicate .personalityindex directive"));
3899 if (exp
.X_op
!= O_constant
3900 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3902 as_bad (_("bad personality routine number"));
3903 ignore_rest_of_line ();
3907 unwind
.personality_index
= exp
.X_add_number
;
3909 demand_empty_rest_of_line ();
3913 /* Parse a personality directive. */
3916 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3920 if (!unwind
.proc_start
)
3921 as_bad (MISSING_FNSTART
);
3923 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3924 as_bad (_("duplicate .personality directive"));
3926 c
= get_symbol_name (& name
);
3927 p
= input_line_pointer
;
3929 ++ input_line_pointer
;
3930 unwind
.personality_routine
= symbol_find_or_make (name
);
3932 demand_empty_rest_of_line ();
3936 /* Parse a directive saving core registers. */
3939 s_arm_unwind_save_core (void)
3945 range
= parse_reg_list (&input_line_pointer
);
3948 as_bad (_("expected register list"));
3949 ignore_rest_of_line ();
3953 demand_empty_rest_of_line ();
3955 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3956 into .unwind_save {..., sp...}. We aren't bothered about the value of
3957 ip because it is clobbered by calls. */
3958 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3959 && (range
& 0x3000) == 0x1000)
3961 unwind
.opcode_count
--;
3962 unwind
.sp_restored
= 0;
3963 range
= (range
| 0x2000) & ~0x1000;
3964 unwind
.pending_offset
= 0;
3970 /* See if we can use the short opcodes. These pop a block of up to 8
3971 registers starting with r4, plus maybe r14. */
3972 for (n
= 0; n
< 8; n
++)
3974 /* Break at the first non-saved register. */
3975 if ((range
& (1 << (n
+ 4))) == 0)
3978 /* See if there are any other bits set. */
3979 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3981 /* Use the long form. */
3982 op
= 0x8000 | ((range
>> 4) & 0xfff);
3983 add_unwind_opcode (op
, 2);
3987 /* Use the short form. */
3989 op
= 0xa8; /* Pop r14. */
3991 op
= 0xa0; /* Do not pop r14. */
3993 add_unwind_opcode (op
, 1);
4000 op
= 0xb100 | (range
& 0xf);
4001 add_unwind_opcode (op
, 2);
4004 /* Record the number of bytes pushed. */
4005 for (n
= 0; n
< 16; n
++)
4007 if (range
& (1 << n
))
4008 unwind
.frame_size
+= 4;
4013 /* Parse a directive saving FPA registers. */
4016 s_arm_unwind_save_fpa (int reg
)
4022 /* Get Number of registers to transfer. */
4023 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4026 exp
.X_op
= O_illegal
;
4028 if (exp
.X_op
!= O_constant
)
4030 as_bad (_("expected , <constant>"));
4031 ignore_rest_of_line ();
4035 num_regs
= exp
.X_add_number
;
4037 if (num_regs
< 1 || num_regs
> 4)
4039 as_bad (_("number of registers must be in the range [1:4]"));
4040 ignore_rest_of_line ();
4044 demand_empty_rest_of_line ();
4049 op
= 0xb4 | (num_regs
- 1);
4050 add_unwind_opcode (op
, 1);
4055 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4056 add_unwind_opcode (op
, 2);
4058 unwind
.frame_size
+= num_regs
* 12;
4062 /* Parse a directive saving VFP registers for ARMv6 and above. */
4065 s_arm_unwind_save_vfp_armv6 (void)
4070 int num_vfpv3_regs
= 0;
4071 int num_regs_below_16
;
4073 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4076 as_bad (_("expected register list"));
4077 ignore_rest_of_line ();
4081 demand_empty_rest_of_line ();
4083 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4084 than FSTMX/FLDMX-style ones). */
4086 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4088 num_vfpv3_regs
= count
;
4089 else if (start
+ count
> 16)
4090 num_vfpv3_regs
= start
+ count
- 16;
4092 if (num_vfpv3_regs
> 0)
4094 int start_offset
= start
> 16 ? start
- 16 : 0;
4095 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4096 add_unwind_opcode (op
, 2);
4099 /* Generate opcode for registers numbered in the range 0 .. 15. */
4100 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4101 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4102 if (num_regs_below_16
> 0)
4104 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4105 add_unwind_opcode (op
, 2);
4108 unwind
.frame_size
+= count
* 8;
4112 /* Parse a directive saving VFP registers for pre-ARMv6. */
4115 s_arm_unwind_save_vfp (void)
4121 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4124 as_bad (_("expected register list"));
4125 ignore_rest_of_line ();
4129 demand_empty_rest_of_line ();
4134 op
= 0xb8 | (count
- 1);
4135 add_unwind_opcode (op
, 1);
4140 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4141 add_unwind_opcode (op
, 2);
4143 unwind
.frame_size
+= count
* 8 + 4;
4147 /* Parse a directive saving iWMMXt data registers. */
4150 s_arm_unwind_save_mmxwr (void)
4158 if (*input_line_pointer
== '{')
4159 input_line_pointer
++;
4163 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4167 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4172 as_tsktsk (_("register list not in ascending order"));
4175 if (*input_line_pointer
== '-')
4177 input_line_pointer
++;
4178 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4181 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4184 else if (reg
>= hi_reg
)
4186 as_bad (_("bad register range"));
4189 for (; reg
< hi_reg
; reg
++)
4193 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4195 skip_past_char (&input_line_pointer
, '}');
4197 demand_empty_rest_of_line ();
4199 /* Generate any deferred opcodes because we're going to be looking at
4201 flush_pending_unwind ();
4203 for (i
= 0; i
< 16; i
++)
4205 if (mask
& (1 << i
))
4206 unwind
.frame_size
+= 8;
4209 /* Attempt to combine with a previous opcode. We do this because gcc
4210 likes to output separate unwind directives for a single block of
4212 if (unwind
.opcode_count
> 0)
4214 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4215 if ((i
& 0xf8) == 0xc0)
4218 /* Only merge if the blocks are contiguous. */
4221 if ((mask
& 0xfe00) == (1 << 9))
4223 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4224 unwind
.opcode_count
--;
4227 else if (i
== 6 && unwind
.opcode_count
>= 2)
4229 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4233 op
= 0xffff << (reg
- 1);
4235 && ((mask
& op
) == (1u << (reg
- 1))))
4237 op
= (1 << (reg
+ i
+ 1)) - 1;
4238 op
&= ~((1 << reg
) - 1);
4240 unwind
.opcode_count
-= 2;
4247 /* We want to generate opcodes in the order the registers have been
4248 saved, ie. descending order. */
4249 for (reg
= 15; reg
>= -1; reg
--)
4251 /* Save registers in blocks. */
4253 || !(mask
& (1 << reg
)))
4255 /* We found an unsaved reg. Generate opcodes to save the
4262 op
= 0xc0 | (hi_reg
- 10);
4263 add_unwind_opcode (op
, 1);
4268 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4269 add_unwind_opcode (op
, 2);
4278 ignore_rest_of_line ();
4282 s_arm_unwind_save_mmxwcg (void)
4289 if (*input_line_pointer
== '{')
4290 input_line_pointer
++;
4292 skip_whitespace (input_line_pointer
);
4296 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4300 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4306 as_tsktsk (_("register list not in ascending order"));
4309 if (*input_line_pointer
== '-')
4311 input_line_pointer
++;
4312 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4315 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4318 else if (reg
>= hi_reg
)
4320 as_bad (_("bad register range"));
4323 for (; reg
< hi_reg
; reg
++)
4327 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4329 skip_past_char (&input_line_pointer
, '}');
4331 demand_empty_rest_of_line ();
4333 /* Generate any deferred opcodes because we're going to be looking at
4335 flush_pending_unwind ();
4337 for (reg
= 0; reg
< 16; reg
++)
4339 if (mask
& (1 << reg
))
4340 unwind
.frame_size
+= 4;
4343 add_unwind_opcode (op
, 2);
4346 ignore_rest_of_line ();
4350 /* Parse an unwind_save directive.
4351 If the argument is non-zero, this is a .vsave directive. */
4354 s_arm_unwind_save (int arch_v6
)
4357 struct reg_entry
*reg
;
4358 bfd_boolean had_brace
= FALSE
;
4360 if (!unwind
.proc_start
)
4361 as_bad (MISSING_FNSTART
);
4363 /* Figure out what sort of save we have. */
4364 peek
= input_line_pointer
;
4372 reg
= arm_reg_parse_multi (&peek
);
4376 as_bad (_("register expected"));
4377 ignore_rest_of_line ();
4386 as_bad (_("FPA .unwind_save does not take a register list"));
4387 ignore_rest_of_line ();
4390 input_line_pointer
= peek
;
4391 s_arm_unwind_save_fpa (reg
->number
);
4395 s_arm_unwind_save_core ();
4400 s_arm_unwind_save_vfp_armv6 ();
4402 s_arm_unwind_save_vfp ();
4405 case REG_TYPE_MMXWR
:
4406 s_arm_unwind_save_mmxwr ();
4409 case REG_TYPE_MMXWCG
:
4410 s_arm_unwind_save_mmxwcg ();
4414 as_bad (_(".unwind_save does not support this kind of register"));
4415 ignore_rest_of_line ();
4420 /* Parse an unwind_movsp directive. */
4423 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4429 if (!unwind
.proc_start
)
4430 as_bad (MISSING_FNSTART
);
4432 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4435 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4436 ignore_rest_of_line ();
4440 /* Optional constant. */
4441 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4443 if (immediate_for_directive (&offset
) == FAIL
)
4449 demand_empty_rest_of_line ();
4451 if (reg
== REG_SP
|| reg
== REG_PC
)
4453 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4457 if (unwind
.fp_reg
!= REG_SP
)
4458 as_bad (_("unexpected .unwind_movsp directive"));
4460 /* Generate opcode to restore the value. */
4462 add_unwind_opcode (op
, 1);
4464 /* Record the information for later. */
4465 unwind
.fp_reg
= reg
;
4466 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4467 unwind
.sp_restored
= 1;
4470 /* Parse an unwind_pad directive. */
4473 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4477 if (!unwind
.proc_start
)
4478 as_bad (MISSING_FNSTART
);
4480 if (immediate_for_directive (&offset
) == FAIL
)
4485 as_bad (_("stack increment must be multiple of 4"));
4486 ignore_rest_of_line ();
4490 /* Don't generate any opcodes, just record the details for later. */
4491 unwind
.frame_size
+= offset
;
4492 unwind
.pending_offset
+= offset
;
4494 demand_empty_rest_of_line ();
4497 /* Parse an unwind_setfp directive. */
4500 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4506 if (!unwind
.proc_start
)
4507 as_bad (MISSING_FNSTART
);
4509 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4510 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4513 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4515 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4517 as_bad (_("expected <reg>, <reg>"));
4518 ignore_rest_of_line ();
4522 /* Optional constant. */
4523 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4525 if (immediate_for_directive (&offset
) == FAIL
)
4531 demand_empty_rest_of_line ();
4533 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4535 as_bad (_("register must be either sp or set by a previous"
4536 "unwind_movsp directive"));
4540 /* Don't generate any opcodes, just record the information for later. */
4541 unwind
.fp_reg
= fp_reg
;
4543 if (sp_reg
== REG_SP
)
4544 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4546 unwind
.fp_offset
-= offset
;
4549 /* Parse an unwind_raw directive. */
4552 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4555 /* This is an arbitrary limit. */
4556 unsigned char op
[16];
4559 if (!unwind
.proc_start
)
4560 as_bad (MISSING_FNSTART
);
4563 if (exp
.X_op
== O_constant
4564 && skip_past_comma (&input_line_pointer
) != FAIL
)
4566 unwind
.frame_size
+= exp
.X_add_number
;
4570 exp
.X_op
= O_illegal
;
4572 if (exp
.X_op
!= O_constant
)
4574 as_bad (_("expected <offset>, <opcode>"));
4575 ignore_rest_of_line ();
4581 /* Parse the opcode. */
4586 as_bad (_("unwind opcode too long"));
4587 ignore_rest_of_line ();
4589 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4591 as_bad (_("invalid unwind opcode"));
4592 ignore_rest_of_line ();
4595 op
[count
++] = exp
.X_add_number
;
4597 /* Parse the next byte. */
4598 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4604 /* Add the opcode bytes in reverse order. */
4606 add_unwind_opcode (op
[count
], 1);
4608 demand_empty_rest_of_line ();
4612 /* Parse a .eabi_attribute directive. */
4615 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4617 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4619 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4620 attributes_set_explicitly
[tag
] = 1;
4623 /* Emit a tls fix for the symbol. */
4626 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4630 #ifdef md_flush_pending_output
4631 md_flush_pending_output ();
4634 #ifdef md_cons_align
4638 /* Since we're just labelling the code, there's no need to define a
4641 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4642 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4643 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4644 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4646 #endif /* OBJ_ELF */
4648 static void s_arm_arch (int);
4649 static void s_arm_object_arch (int);
4650 static void s_arm_cpu (int);
4651 static void s_arm_fpu (int);
4652 static void s_arm_arch_extension (int);
4657 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4664 if (exp
.X_op
== O_symbol
)
4665 exp
.X_op
= O_secrel
;
4667 emit_expr (&exp
, 4);
4669 while (*input_line_pointer
++ == ',');
4671 input_line_pointer
--;
4672 demand_empty_rest_of_line ();
4676 /* This table describes all the machine specific pseudo-ops the assembler
4677 has to support. The fields are:
4678 pseudo-op name without dot
4679 function to call to execute this pseudo-op
4680 Integer arg to pass to the function. */
4682 const pseudo_typeS md_pseudo_table
[] =
4684 /* Never called because '.req' does not start a line. */
4685 { "req", s_req
, 0 },
4686 /* Following two are likewise never called. */
4689 { "unreq", s_unreq
, 0 },
4690 { "bss", s_bss
, 0 },
4691 { "align", s_align_ptwo
, 2 },
4692 { "arm", s_arm
, 0 },
4693 { "thumb", s_thumb
, 0 },
4694 { "code", s_code
, 0 },
4695 { "force_thumb", s_force_thumb
, 0 },
4696 { "thumb_func", s_thumb_func
, 0 },
4697 { "thumb_set", s_thumb_set
, 0 },
4698 { "even", s_even
, 0 },
4699 { "ltorg", s_ltorg
, 0 },
4700 { "pool", s_ltorg
, 0 },
4701 { "syntax", s_syntax
, 0 },
4702 { "cpu", s_arm_cpu
, 0 },
4703 { "arch", s_arm_arch
, 0 },
4704 { "object_arch", s_arm_object_arch
, 0 },
4705 { "fpu", s_arm_fpu
, 0 },
4706 { "arch_extension", s_arm_arch_extension
, 0 },
4708 { "word", s_arm_elf_cons
, 4 },
4709 { "long", s_arm_elf_cons
, 4 },
4710 { "inst.n", s_arm_elf_inst
, 2 },
4711 { "inst.w", s_arm_elf_inst
, 4 },
4712 { "inst", s_arm_elf_inst
, 0 },
4713 { "rel31", s_arm_rel31
, 0 },
4714 { "fnstart", s_arm_unwind_fnstart
, 0 },
4715 { "fnend", s_arm_unwind_fnend
, 0 },
4716 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4717 { "personality", s_arm_unwind_personality
, 0 },
4718 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4719 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4720 { "save", s_arm_unwind_save
, 0 },
4721 { "vsave", s_arm_unwind_save
, 1 },
4722 { "movsp", s_arm_unwind_movsp
, 0 },
4723 { "pad", s_arm_unwind_pad
, 0 },
4724 { "setfp", s_arm_unwind_setfp
, 0 },
4725 { "unwind_raw", s_arm_unwind_raw
, 0 },
4726 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4727 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4731 /* These are used for dwarf. */
4735 /* These are used for dwarf2. */
4736 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4737 { "loc", dwarf2_directive_loc
, 0 },
4738 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4740 { "extend", float_cons
, 'x' },
4741 { "ldouble", float_cons
, 'x' },
4742 { "packed", float_cons
, 'p' },
4744 {"secrel32", pe_directive_secrel
, 0},
4747 /* These are for compatibility with CodeComposer Studio. */
4748 {"ref", s_ccs_ref
, 0},
4749 {"def", s_ccs_def
, 0},
4750 {"asmfunc", s_ccs_asmfunc
, 0},
4751 {"endasmfunc", s_ccs_endasmfunc
, 0},
4756 /* Parser functions used exclusively in instruction operands. */
4758 /* Generic immediate-value read function for use in insn parsing.
4759 STR points to the beginning of the immediate (the leading #);
4760 VAL receives the value; if the value is outside [MIN, MAX]
4761 issue an error. PREFIX_OPT is true if the immediate prefix is
4765 parse_immediate (char **str
, int *val
, int min
, int max
,
4766 bfd_boolean prefix_opt
)
4769 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4770 if (exp
.X_op
!= O_constant
)
4772 inst
.error
= _("constant expression required");
4776 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4778 inst
.error
= _("immediate value out of range");
4782 *val
= exp
.X_add_number
;
4786 /* Less-generic immediate-value read function with the possibility of loading a
4787 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4788 instructions. Puts the result directly in inst.operands[i]. */
4791 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4792 bfd_boolean allow_symbol_p
)
4795 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4798 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4800 if (exp_p
->X_op
== O_constant
)
4802 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4803 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4804 O_constant. We have to be careful not to break compilation for
4805 32-bit X_add_number, though. */
4806 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4808 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4809 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4811 inst
.operands
[i
].regisimm
= 1;
4814 else if (exp_p
->X_op
== O_big
4815 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4817 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4819 /* Bignums have their least significant bits in
4820 generic_bignum[0]. Make sure we put 32 bits in imm and
4821 32 bits in reg, in a (hopefully) portable way. */
4822 gas_assert (parts
!= 0);
4824 /* Make sure that the number is not too big.
4825 PR 11972: Bignums can now be sign-extended to the
4826 size of a .octa so check that the out of range bits
4827 are all zero or all one. */
4828 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4830 LITTLENUM_TYPE m
= -1;
4832 if (generic_bignum
[parts
* 2] != 0
4833 && generic_bignum
[parts
* 2] != m
)
4836 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4837 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4841 inst
.operands
[i
].imm
= 0;
4842 for (j
= 0; j
< parts
; j
++, idx
++)
4843 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4844 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4845 inst
.operands
[i
].reg
= 0;
4846 for (j
= 0; j
< parts
; j
++, idx
++)
4847 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4848 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4849 inst
.operands
[i
].regisimm
= 1;
4851 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4859 /* Returns the pseudo-register number of an FPA immediate constant,
4860 or FAIL if there isn't a valid constant here. */
4863 parse_fpa_immediate (char ** str
)
4865 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4871 /* First try and match exact strings, this is to guarantee
4872 that some formats will work even for cross assembly. */
4874 for (i
= 0; fp_const
[i
]; i
++)
4876 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4880 *str
+= strlen (fp_const
[i
]);
4881 if (is_end_of_line
[(unsigned char) **str
])
4887 /* Just because we didn't get a match doesn't mean that the constant
4888 isn't valid, just that it is in a format that we don't
4889 automatically recognize. Try parsing it with the standard
4890 expression routines. */
4892 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4894 /* Look for a raw floating point number. */
4895 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4896 && is_end_of_line
[(unsigned char) *save_in
])
4898 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4900 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4902 if (words
[j
] != fp_values
[i
][j
])
4906 if (j
== MAX_LITTLENUMS
)
4914 /* Try and parse a more complex expression, this will probably fail
4915 unless the code uses a floating point prefix (eg "0f"). */
4916 save_in
= input_line_pointer
;
4917 input_line_pointer
= *str
;
4918 if (expression (&exp
) == absolute_section
4919 && exp
.X_op
== O_big
4920 && exp
.X_add_number
< 0)
4922 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4924 #define X_PRECISION 5
4925 #define E_PRECISION 15L
4926 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4928 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4930 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4932 if (words
[j
] != fp_values
[i
][j
])
4936 if (j
== MAX_LITTLENUMS
)
4938 *str
= input_line_pointer
;
4939 input_line_pointer
= save_in
;
4946 *str
= input_line_pointer
;
4947 input_line_pointer
= save_in
;
4948 inst
.error
= _("invalid FPA immediate expression");
4952 /* Returns 1 if a number has "quarter-precision" float format
4953 0baBbbbbbc defgh000 00000000 00000000. */
4956 is_quarter_float (unsigned imm
)
4958 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4959 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4963 /* Detect the presence of a floating point or integer zero constant,
4967 parse_ifimm_zero (char **in
)
4971 if (!is_immediate_prefix (**in
))
4973 /* In unified syntax, all prefixes are optional. */
4974 if (!unified_syntax
)
4980 /* Accept #0x0 as a synonym for #0. */
4981 if (strncmp (*in
, "0x", 2) == 0)
4984 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4989 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4990 &generic_floating_point_number
);
4993 && generic_floating_point_number
.sign
== '+'
4994 && (generic_floating_point_number
.low
4995 > generic_floating_point_number
.leader
))
5001 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5002 0baBbbbbbc defgh000 00000000 00000000.
5003 The zero and minus-zero cases need special handling, since they can't be
5004 encoded in the "quarter-precision" float format, but can nonetheless be
5005 loaded as integer constants. */
5008 parse_qfloat_immediate (char **ccp
, int *immed
)
5012 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5013 int found_fpchar
= 0;
5015 skip_past_char (&str
, '#');
5017 /* We must not accidentally parse an integer as a floating-point number. Make
5018 sure that the value we parse is not an integer by checking for special
5019 characters '.' or 'e'.
5020 FIXME: This is a horrible hack, but doing better is tricky because type
5021 information isn't in a very usable state at parse time. */
5023 skip_whitespace (fpnum
);
5025 if (strncmp (fpnum
, "0x", 2) == 0)
5029 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5030 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5040 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5042 unsigned fpword
= 0;
5045 /* Our FP word must be 32 bits (single-precision FP). */
5046 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5048 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5052 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5065 /* Shift operands. */
5068 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5071 struct asm_shift_name
5074 enum shift_kind kind
;
5077 /* Third argument to parse_shift. */
5078 enum parse_shift_mode
5080 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5081 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5082 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5083 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5084 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5087 /* Parse a <shift> specifier on an ARM data processing instruction.
5088 This has three forms:
5090 (LSL|LSR|ASL|ASR|ROR) Rs
5091 (LSL|LSR|ASL|ASR|ROR) #imm
5094 Note that ASL is assimilated to LSL in the instruction encoding, and
5095 RRX to ROR #0 (which cannot be written as such). */
5098 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5100 const struct asm_shift_name
*shift_name
;
5101 enum shift_kind shift
;
5106 for (p
= *str
; ISALPHA (*p
); p
++)
5111 inst
.error
= _("shift expression expected");
5115 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5118 if (shift_name
== NULL
)
5120 inst
.error
= _("shift expression expected");
5124 shift
= shift_name
->kind
;
5128 case NO_SHIFT_RESTRICT
:
5129 case SHIFT_IMMEDIATE
: break;
5131 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5132 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5134 inst
.error
= _("'LSL' or 'ASR' required");
5139 case SHIFT_LSL_IMMEDIATE
:
5140 if (shift
!= SHIFT_LSL
)
5142 inst
.error
= _("'LSL' required");
5147 case SHIFT_ASR_IMMEDIATE
:
5148 if (shift
!= SHIFT_ASR
)
5150 inst
.error
= _("'ASR' required");
5158 if (shift
!= SHIFT_RRX
)
5160 /* Whitespace can appear here if the next thing is a bare digit. */
5161 skip_whitespace (p
);
5163 if (mode
== NO_SHIFT_RESTRICT
5164 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5166 inst
.operands
[i
].imm
= reg
;
5167 inst
.operands
[i
].immisreg
= 1;
5169 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5172 inst
.operands
[i
].shift_kind
= shift
;
5173 inst
.operands
[i
].shifted
= 1;
5178 /* Parse a <shifter_operand> for an ARM data processing instruction:
5181 #<immediate>, <rotate>
5185 where <shift> is defined by parse_shift above, and <rotate> is a
5186 multiple of 2 between 0 and 30. Validation of immediate operands
5187 is deferred to md_apply_fix. */
5190 parse_shifter_operand (char **str
, int i
)
5195 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5197 inst
.operands
[i
].reg
= value
;
5198 inst
.operands
[i
].isreg
= 1;
5200 /* parse_shift will override this if appropriate */
5201 inst
.reloc
.exp
.X_op
= O_constant
;
5202 inst
.reloc
.exp
.X_add_number
= 0;
5204 if (skip_past_comma (str
) == FAIL
)
5207 /* Shift operation on register. */
5208 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5211 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5214 if (skip_past_comma (str
) == SUCCESS
)
5216 /* #x, y -- ie explicit rotation by Y. */
5217 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5220 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5222 inst
.error
= _("constant expression expected");
5226 value
= exp
.X_add_number
;
5227 if (value
< 0 || value
> 30 || value
% 2 != 0)
5229 inst
.error
= _("invalid rotation");
5232 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5234 inst
.error
= _("invalid constant");
5238 /* Encode as specified. */
5239 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5243 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5244 inst
.reloc
.pc_rel
= 0;
5248 /* Group relocation information. Each entry in the table contains the
5249 textual name of the relocation as may appear in assembler source
5250 and must end with a colon.
5251 Along with this textual name are the relocation codes to be used if
5252 the corresponding instruction is an ALU instruction (ADD or SUB only),
5253 an LDR, an LDRS, or an LDC. */
5255 struct group_reloc_table_entry
5266 /* Varieties of non-ALU group relocation. */
5273 static struct group_reloc_table_entry group_reloc_table
[] =
5274 { /* Program counter relative: */
5276 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5281 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5282 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5283 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5284 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5286 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5291 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5292 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5293 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5294 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5296 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5297 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5298 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5299 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5300 /* Section base relative */
5302 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5307 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5308 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5309 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5310 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5312 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5317 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5318 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5319 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5320 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5322 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5323 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5324 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5325 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5326 /* Absolute thumb alu relocations. */
5328 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5333 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5338 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5343 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5348 /* Given the address of a pointer pointing to the textual name of a group
5349 relocation as may appear in assembler source, attempt to find its details
5350 in group_reloc_table. The pointer will be updated to the character after
5351 the trailing colon. On failure, FAIL will be returned; SUCCESS
5352 otherwise. On success, *entry will be updated to point at the relevant
5353 group_reloc_table entry. */
5356 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5359 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5361 int length
= strlen (group_reloc_table
[i
].name
);
5363 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5364 && (*str
)[length
] == ':')
5366 *out
= &group_reloc_table
[i
];
5367 *str
+= (length
+ 1);
5375 /* Parse a <shifter_operand> for an ARM data processing instruction
5376 (as for parse_shifter_operand) where group relocations are allowed:
5379 #<immediate>, <rotate>
5380 #:<group_reloc>:<expression>
5384 where <group_reloc> is one of the strings defined in group_reloc_table.
5385 The hashes are optional.
5387 Everything else is as for parse_shifter_operand. */
5389 static parse_operand_result
5390 parse_shifter_operand_group_reloc (char **str
, int i
)
5392 /* Determine if we have the sequence of characters #: or just :
5393 coming next. If we do, then we check for a group relocation.
5394 If we don't, punt the whole lot to parse_shifter_operand. */
5396 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5397 || (*str
)[0] == ':')
5399 struct group_reloc_table_entry
*entry
;
5401 if ((*str
)[0] == '#')
5406 /* Try to parse a group relocation. Anything else is an error. */
5407 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5409 inst
.error
= _("unknown group relocation");
5410 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5413 /* We now have the group relocation table entry corresponding to
5414 the name in the assembler source. Next, we parse the expression. */
5415 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5416 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5418 /* Record the relocation type (always the ALU variant here). */
5419 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5420 gas_assert (inst
.reloc
.type
!= 0);
5422 return PARSE_OPERAND_SUCCESS
;
5425 return parse_shifter_operand (str
, i
) == SUCCESS
5426 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5428 /* Never reached. */
5431 /* Parse a Neon alignment expression. Information is written to
5432 inst.operands[i]. We assume the initial ':' has been skipped.
5434 align .imm = align << 8, .immisalign=1, .preind=0 */
5435 static parse_operand_result
5436 parse_neon_alignment (char **str
, int i
)
5441 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5443 if (exp
.X_op
!= O_constant
)
5445 inst
.error
= _("alignment must be constant");
5446 return PARSE_OPERAND_FAIL
;
5449 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5450 inst
.operands
[i
].immisalign
= 1;
5451 /* Alignments are not pre-indexes. */
5452 inst
.operands
[i
].preind
= 0;
5455 return PARSE_OPERAND_SUCCESS
;
5458 /* Parse all forms of an ARM address expression. Information is written
5459 to inst.operands[i] and/or inst.reloc.
5461 Preindexed addressing (.preind=1):
5463 [Rn, #offset] .reg=Rn .reloc.exp=offset
5464 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5465 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5466 .shift_kind=shift .reloc.exp=shift_imm
5468 These three may have a trailing ! which causes .writeback to be set also.
5470 Postindexed addressing (.postind=1, .writeback=1):
5472 [Rn], #offset .reg=Rn .reloc.exp=offset
5473 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5474 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5475 .shift_kind=shift .reloc.exp=shift_imm
5477 Unindexed addressing (.preind=0, .postind=0):
5479 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5483 [Rn]{!} shorthand for [Rn,#0]{!}
5484 =immediate .isreg=0 .reloc.exp=immediate
5485 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5487 It is the caller's responsibility to check for addressing modes not
5488 supported by the instruction, and to set inst.reloc.type. */
5490 static parse_operand_result
5491 parse_address_main (char **str
, int i
, int group_relocations
,
5492 group_reloc_type group_type
)
5497 if (skip_past_char (&p
, '[') == FAIL
)
5499 if (skip_past_char (&p
, '=') == FAIL
)
5501 /* Bare address - translate to PC-relative offset. */
5502 inst
.reloc
.pc_rel
= 1;
5503 inst
.operands
[i
].reg
= REG_PC
;
5504 inst
.operands
[i
].isreg
= 1;
5505 inst
.operands
[i
].preind
= 1;
5507 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5508 return PARSE_OPERAND_FAIL
;
5510 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5511 /*allow_symbol_p=*/TRUE
))
5512 return PARSE_OPERAND_FAIL
;
5515 return PARSE_OPERAND_SUCCESS
;
5518 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5519 skip_whitespace (p
);
5521 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5523 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5524 return PARSE_OPERAND_FAIL
;
5526 inst
.operands
[i
].reg
= reg
;
5527 inst
.operands
[i
].isreg
= 1;
5529 if (skip_past_comma (&p
) == SUCCESS
)
5531 inst
.operands
[i
].preind
= 1;
5534 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5536 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5538 inst
.operands
[i
].imm
= reg
;
5539 inst
.operands
[i
].immisreg
= 1;
5541 if (skip_past_comma (&p
) == SUCCESS
)
5542 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5543 return PARSE_OPERAND_FAIL
;
5545 else if (skip_past_char (&p
, ':') == SUCCESS
)
5547 /* FIXME: '@' should be used here, but it's filtered out by generic
5548 code before we get to see it here. This may be subject to
5550 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5552 if (result
!= PARSE_OPERAND_SUCCESS
)
5557 if (inst
.operands
[i
].negative
)
5559 inst
.operands
[i
].negative
= 0;
5563 if (group_relocations
5564 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5566 struct group_reloc_table_entry
*entry
;
5568 /* Skip over the #: or : sequence. */
5574 /* Try to parse a group relocation. Anything else is an
5576 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5578 inst
.error
= _("unknown group relocation");
5579 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5582 /* We now have the group relocation table entry corresponding to
5583 the name in the assembler source. Next, we parse the
5585 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5586 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5588 /* Record the relocation type. */
5592 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5596 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5600 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5607 if (inst
.reloc
.type
== 0)
5609 inst
.error
= _("this group relocation is not allowed on this instruction");
5610 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5616 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5617 return PARSE_OPERAND_FAIL
;
5618 /* If the offset is 0, find out if it's a +0 or -0. */
5619 if (inst
.reloc
.exp
.X_op
== O_constant
5620 && inst
.reloc
.exp
.X_add_number
== 0)
5622 skip_whitespace (q
);
5626 skip_whitespace (q
);
5629 inst
.operands
[i
].negative
= 1;
5634 else if (skip_past_char (&p
, ':') == SUCCESS
)
5636 /* FIXME: '@' should be used here, but it's filtered out by generic code
5637 before we get to see it here. This may be subject to change. */
5638 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5640 if (result
!= PARSE_OPERAND_SUCCESS
)
5644 if (skip_past_char (&p
, ']') == FAIL
)
5646 inst
.error
= _("']' expected");
5647 return PARSE_OPERAND_FAIL
;
5650 if (skip_past_char (&p
, '!') == SUCCESS
)
5651 inst
.operands
[i
].writeback
= 1;
5653 else if (skip_past_comma (&p
) == SUCCESS
)
5655 if (skip_past_char (&p
, '{') == SUCCESS
)
5657 /* [Rn], {expr} - unindexed, with option */
5658 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5659 0, 255, TRUE
) == FAIL
)
5660 return PARSE_OPERAND_FAIL
;
5662 if (skip_past_char (&p
, '}') == FAIL
)
5664 inst
.error
= _("'}' expected at end of 'option' field");
5665 return PARSE_OPERAND_FAIL
;
5667 if (inst
.operands
[i
].preind
)
5669 inst
.error
= _("cannot combine index with option");
5670 return PARSE_OPERAND_FAIL
;
5673 return PARSE_OPERAND_SUCCESS
;
5677 inst
.operands
[i
].postind
= 1;
5678 inst
.operands
[i
].writeback
= 1;
5680 if (inst
.operands
[i
].preind
)
5682 inst
.error
= _("cannot combine pre- and post-indexing");
5683 return PARSE_OPERAND_FAIL
;
5687 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5689 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5691 /* We might be using the immediate for alignment already. If we
5692 are, OR the register number into the low-order bits. */
5693 if (inst
.operands
[i
].immisalign
)
5694 inst
.operands
[i
].imm
|= reg
;
5696 inst
.operands
[i
].imm
= reg
;
5697 inst
.operands
[i
].immisreg
= 1;
5699 if (skip_past_comma (&p
) == SUCCESS
)
5700 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5701 return PARSE_OPERAND_FAIL
;
5706 if (inst
.operands
[i
].negative
)
5708 inst
.operands
[i
].negative
= 0;
5711 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5712 return PARSE_OPERAND_FAIL
;
5713 /* If the offset is 0, find out if it's a +0 or -0. */
5714 if (inst
.reloc
.exp
.X_op
== O_constant
5715 && inst
.reloc
.exp
.X_add_number
== 0)
5717 skip_whitespace (q
);
5721 skip_whitespace (q
);
5724 inst
.operands
[i
].negative
= 1;
5730 /* If at this point neither .preind nor .postind is set, we have a
5731 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5732 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5734 inst
.operands
[i
].preind
= 1;
5735 inst
.reloc
.exp
.X_op
= O_constant
;
5736 inst
.reloc
.exp
.X_add_number
= 0;
5739 return PARSE_OPERAND_SUCCESS
;
5743 parse_address (char **str
, int i
)
5745 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5749 static parse_operand_result
5750 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5752 return parse_address_main (str
, i
, 1, type
);
5755 /* Parse an operand for a MOVW or MOVT instruction. */
5757 parse_half (char **str
)
5762 skip_past_char (&p
, '#');
5763 if (strncasecmp (p
, ":lower16:", 9) == 0)
5764 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5765 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5766 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5768 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5771 skip_whitespace (p
);
5774 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5777 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5779 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5781 inst
.error
= _("constant expression expected");
5784 if (inst
.reloc
.exp
.X_add_number
< 0
5785 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5787 inst
.error
= _("immediate value out of range");
5795 /* Miscellaneous. */
5797 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5798 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5800 parse_psr (char **str
, bfd_boolean lhs
)
5803 unsigned long psr_field
;
5804 const struct asm_psr
*psr
;
5806 bfd_boolean is_apsr
= FALSE
;
5807 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5809 /* PR gas/12698: If the user has specified -march=all then m_profile will
5810 be TRUE, but we want to ignore it in this case as we are building for any
5811 CPU type, including non-m variants. */
5812 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5815 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5816 feature for ease of use and backwards compatibility. */
5818 if (strncasecmp (p
, "SPSR", 4) == 0)
5821 goto unsupported_psr
;
5823 psr_field
= SPSR_BIT
;
5825 else if (strncasecmp (p
, "CPSR", 4) == 0)
5828 goto unsupported_psr
;
5832 else if (strncasecmp (p
, "APSR", 4) == 0)
5834 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5835 and ARMv7-R architecture CPUs. */
5844 while (ISALNUM (*p
) || *p
== '_');
5846 if (strncasecmp (start
, "iapsr", 5) == 0
5847 || strncasecmp (start
, "eapsr", 5) == 0
5848 || strncasecmp (start
, "xpsr", 4) == 0
5849 || strncasecmp (start
, "psr", 3) == 0)
5850 p
= start
+ strcspn (start
, "rR") + 1;
5852 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5858 /* If APSR is being written, a bitfield may be specified. Note that
5859 APSR itself is handled above. */
5860 if (psr
->field
<= 3)
5862 psr_field
= psr
->field
;
5868 /* M-profile MSR instructions have the mask field set to "10", except
5869 *PSR variants which modify APSR, which may use a different mask (and
5870 have been handled already). Do that by setting the PSR_f field
5872 return psr
->field
| (lhs
? PSR_f
: 0);
5875 goto unsupported_psr
;
5881 /* A suffix follows. */
5887 while (ISALNUM (*p
) || *p
== '_');
5891 /* APSR uses a notation for bits, rather than fields. */
5892 unsigned int nzcvq_bits
= 0;
5893 unsigned int g_bit
= 0;
5896 for (bit
= start
; bit
!= p
; bit
++)
5898 switch (TOLOWER (*bit
))
5901 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5905 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5909 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5913 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5917 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5921 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5925 inst
.error
= _("unexpected bit specified after APSR");
5930 if (nzcvq_bits
== 0x1f)
5935 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5937 inst
.error
= _("selected processor does not "
5938 "support DSP extension");
5945 if ((nzcvq_bits
& 0x20) != 0
5946 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5947 || (g_bit
& 0x2) != 0)
5949 inst
.error
= _("bad bitmask specified after APSR");
5955 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5960 psr_field
|= psr
->field
;
5966 goto error
; /* Garbage after "[CS]PSR". */
5968 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5969 is deprecated, but allow it anyway. */
5973 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5976 else if (!m_profile
)
5977 /* These bits are never right for M-profile devices: don't set them
5978 (only code paths which read/write APSR reach here). */
5979 psr_field
|= (PSR_c
| PSR_f
);
5985 inst
.error
= _("selected processor does not support requested special "
5986 "purpose register");
5990 inst
.error
= _("flag for {c}psr instruction expected");
5994 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5995 value suitable for splatting into the AIF field of the instruction. */
5998 parse_cps_flags (char **str
)
6007 case '\0': case ',':
6010 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6011 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6012 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6015 inst
.error
= _("unrecognized CPS flag");
6020 if (saw_a_flag
== 0)
6022 inst
.error
= _("missing CPS flags");
6030 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6031 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6034 parse_endian_specifier (char **str
)
6039 if (strncasecmp (s
, "BE", 2))
6041 else if (strncasecmp (s
, "LE", 2))
6045 inst
.error
= _("valid endian specifiers are be or le");
6049 if (ISALNUM (s
[2]) || s
[2] == '_')
6051 inst
.error
= _("valid endian specifiers are be or le");
6056 return little_endian
;
6059 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6060 value suitable for poking into the rotate field of an sxt or sxta
6061 instruction, or FAIL on error. */
6064 parse_ror (char **str
)
6069 if (strncasecmp (s
, "ROR", 3) == 0)
6073 inst
.error
= _("missing rotation field after comma");
6077 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6082 case 0: *str
= s
; return 0x0;
6083 case 8: *str
= s
; return 0x1;
6084 case 16: *str
= s
; return 0x2;
6085 case 24: *str
= s
; return 0x3;
6088 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6093 /* Parse a conditional code (from conds[] below). The value returned is in the
6094 range 0 .. 14, or FAIL. */
6096 parse_cond (char **str
)
6099 const struct asm_cond
*c
;
6101 /* Condition codes are always 2 characters, so matching up to
6102 3 characters is sufficient. */
6107 while (ISALPHA (*q
) && n
< 3)
6109 cond
[n
] = TOLOWER (*q
);
6114 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6117 inst
.error
= _("condition required");
6125 /* Record a use of the given feature. */
6127 record_feature_use (const arm_feature_set
*feature
)
6130 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6132 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6135 /* If the given feature available in the selected CPU, mark it as used.
6136 Returns TRUE iff feature is available. */
6138 mark_feature_used (const arm_feature_set
*feature
)
6140 /* Ensure the option is valid on the current architecture. */
6141 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6144 /* Add the appropriate architecture feature for the barrier option used.
6146 record_feature_use (feature
);
6151 /* Parse an option for a barrier instruction. Returns the encoding for the
6154 parse_barrier (char **str
)
6157 const struct asm_barrier_opt
*o
;
6160 while (ISALPHA (*q
))
6163 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6168 if (!mark_feature_used (&o
->arch
))
6175 /* Parse the operands of a table branch instruction. Similar to a memory
6178 parse_tb (char **str
)
6183 if (skip_past_char (&p
, '[') == FAIL
)
6185 inst
.error
= _("'[' expected");
6189 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6191 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6194 inst
.operands
[0].reg
= reg
;
6196 if (skip_past_comma (&p
) == FAIL
)
6198 inst
.error
= _("',' expected");
6202 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6204 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6207 inst
.operands
[0].imm
= reg
;
6209 if (skip_past_comma (&p
) == SUCCESS
)
6211 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6213 if (inst
.reloc
.exp
.X_add_number
!= 1)
6215 inst
.error
= _("invalid shift");
6218 inst
.operands
[0].shifted
= 1;
6221 if (skip_past_char (&p
, ']') == FAIL
)
6223 inst
.error
= _("']' expected");
6230 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6231 information on the types the operands can take and how they are encoded.
6232 Up to four operands may be read; this function handles setting the
6233 ".present" field for each read operand itself.
6234 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6235 else returns FAIL. */
6238 parse_neon_mov (char **str
, int *which_operand
)
6240 int i
= *which_operand
, val
;
6241 enum arm_reg_type rtype
;
6243 struct neon_type_el optype
;
6245 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6247 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6248 inst
.operands
[i
].reg
= val
;
6249 inst
.operands
[i
].isscalar
= 1;
6250 inst
.operands
[i
].vectype
= optype
;
6251 inst
.operands
[i
++].present
= 1;
6253 if (skip_past_comma (&ptr
) == FAIL
)
6256 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6259 inst
.operands
[i
].reg
= val
;
6260 inst
.operands
[i
].isreg
= 1;
6261 inst
.operands
[i
].present
= 1;
6263 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6266 /* Cases 0, 1, 2, 3, 5 (D only). */
6267 if (skip_past_comma (&ptr
) == FAIL
)
6270 inst
.operands
[i
].reg
= val
;
6271 inst
.operands
[i
].isreg
= 1;
6272 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6273 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6274 inst
.operands
[i
].isvec
= 1;
6275 inst
.operands
[i
].vectype
= optype
;
6276 inst
.operands
[i
++].present
= 1;
6278 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6280 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6281 Case 13: VMOV <Sd>, <Rm> */
6282 inst
.operands
[i
].reg
= val
;
6283 inst
.operands
[i
].isreg
= 1;
6284 inst
.operands
[i
].present
= 1;
6286 if (rtype
== REG_TYPE_NQ
)
6288 first_error (_("can't use Neon quad register here"));
6291 else if (rtype
!= REG_TYPE_VFS
)
6294 if (skip_past_comma (&ptr
) == FAIL
)
6296 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6298 inst
.operands
[i
].reg
= val
;
6299 inst
.operands
[i
].isreg
= 1;
6300 inst
.operands
[i
].present
= 1;
6303 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6306 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6307 Case 1: VMOV<c><q> <Dd>, <Dm>
6308 Case 8: VMOV.F32 <Sd>, <Sm>
6309 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6311 inst
.operands
[i
].reg
= val
;
6312 inst
.operands
[i
].isreg
= 1;
6313 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6314 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6315 inst
.operands
[i
].isvec
= 1;
6316 inst
.operands
[i
].vectype
= optype
;
6317 inst
.operands
[i
].present
= 1;
6319 if (skip_past_comma (&ptr
) == SUCCESS
)
6324 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6327 inst
.operands
[i
].reg
= val
;
6328 inst
.operands
[i
].isreg
= 1;
6329 inst
.operands
[i
++].present
= 1;
6331 if (skip_past_comma (&ptr
) == FAIL
)
6334 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6337 inst
.operands
[i
].reg
= val
;
6338 inst
.operands
[i
].isreg
= 1;
6339 inst
.operands
[i
].present
= 1;
6342 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6343 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6344 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6345 Case 10: VMOV.F32 <Sd>, #<imm>
6346 Case 11: VMOV.F64 <Dd>, #<imm> */
6347 inst
.operands
[i
].immisfloat
= 1;
6348 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6350 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6351 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6355 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6359 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6362 inst
.operands
[i
].reg
= val
;
6363 inst
.operands
[i
].isreg
= 1;
6364 inst
.operands
[i
++].present
= 1;
6366 if (skip_past_comma (&ptr
) == FAIL
)
6369 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6371 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6372 inst
.operands
[i
].reg
= val
;
6373 inst
.operands
[i
].isscalar
= 1;
6374 inst
.operands
[i
].present
= 1;
6375 inst
.operands
[i
].vectype
= optype
;
6377 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6379 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6380 inst
.operands
[i
].reg
= val
;
6381 inst
.operands
[i
].isreg
= 1;
6382 inst
.operands
[i
++].present
= 1;
6384 if (skip_past_comma (&ptr
) == FAIL
)
6387 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6390 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6394 inst
.operands
[i
].reg
= val
;
6395 inst
.operands
[i
].isreg
= 1;
6396 inst
.operands
[i
].isvec
= 1;
6397 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6398 inst
.operands
[i
].vectype
= optype
;
6399 inst
.operands
[i
].present
= 1;
6401 if (rtype
== REG_TYPE_VFS
)
6405 if (skip_past_comma (&ptr
) == FAIL
)
6407 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6410 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6413 inst
.operands
[i
].reg
= val
;
6414 inst
.operands
[i
].isreg
= 1;
6415 inst
.operands
[i
].isvec
= 1;
6416 inst
.operands
[i
].issingle
= 1;
6417 inst
.operands
[i
].vectype
= optype
;
6418 inst
.operands
[i
].present
= 1;
6421 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6425 inst
.operands
[i
].reg
= val
;
6426 inst
.operands
[i
].isreg
= 1;
6427 inst
.operands
[i
].isvec
= 1;
6428 inst
.operands
[i
].issingle
= 1;
6429 inst
.operands
[i
].vectype
= optype
;
6430 inst
.operands
[i
].present
= 1;
6435 first_error (_("parse error"));
6439 /* Successfully parsed the operands. Update args. */
6445 first_error (_("expected comma"));
6449 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6453 /* Use this macro when the operand constraints are different
6454 for ARM and THUMB (e.g. ldrd). */
6455 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6456 ((arm_operand) | ((thumb_operand) << 16))
6458 /* Matcher codes for parse_operands. */
6459 enum operand_parse_code
6461 OP_stop
, /* end of line */
6463 OP_RR
, /* ARM register */
6464 OP_RRnpc
, /* ARM register, not r15 */
6465 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6466 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6467 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6468 optional trailing ! */
6469 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6470 OP_RCP
, /* Coprocessor number */
6471 OP_RCN
, /* Coprocessor register */
6472 OP_RF
, /* FPA register */
6473 OP_RVS
, /* VFP single precision register */
6474 OP_RVD
, /* VFP double precision register (0..15) */
6475 OP_RND
, /* Neon double precision register (0..31) */
6476 OP_RNQ
, /* Neon quad precision register */
6477 OP_RVSD
, /* VFP single or double precision register */
6478 OP_RNDQ
, /* Neon double or quad precision register */
6479 OP_RNSDQ
, /* Neon single, double or quad precision register */
6480 OP_RNSC
, /* Neon scalar D[X] */
6481 OP_RVC
, /* VFP control register */
6482 OP_RMF
, /* Maverick F register */
6483 OP_RMD
, /* Maverick D register */
6484 OP_RMFX
, /* Maverick FX register */
6485 OP_RMDX
, /* Maverick DX register */
6486 OP_RMAX
, /* Maverick AX register */
6487 OP_RMDS
, /* Maverick DSPSC register */
6488 OP_RIWR
, /* iWMMXt wR register */
6489 OP_RIWC
, /* iWMMXt wC register */
6490 OP_RIWG
, /* iWMMXt wCG register */
6491 OP_RXA
, /* XScale accumulator register */
6493 OP_REGLST
, /* ARM register list */
6494 OP_VRSLST
, /* VFP single-precision register list */
6495 OP_VRDLST
, /* VFP double-precision register list */
6496 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6497 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6498 OP_NSTRLST
, /* Neon element/structure list */
6500 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6501 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6502 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6503 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6504 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6505 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6506 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6507 OP_VMOV
, /* Neon VMOV operands. */
6508 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6509 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6510 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6512 OP_I0
, /* immediate zero */
6513 OP_I7
, /* immediate value 0 .. 7 */
6514 OP_I15
, /* 0 .. 15 */
6515 OP_I16
, /* 1 .. 16 */
6516 OP_I16z
, /* 0 .. 16 */
6517 OP_I31
, /* 0 .. 31 */
6518 OP_I31w
, /* 0 .. 31, optional trailing ! */
6519 OP_I32
, /* 1 .. 32 */
6520 OP_I32z
, /* 0 .. 32 */
6521 OP_I63
, /* 0 .. 63 */
6522 OP_I63s
, /* -64 .. 63 */
6523 OP_I64
, /* 1 .. 64 */
6524 OP_I64z
, /* 0 .. 64 */
6525 OP_I255
, /* 0 .. 255 */
6527 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6528 OP_I7b
, /* 0 .. 7 */
6529 OP_I15b
, /* 0 .. 15 */
6530 OP_I31b
, /* 0 .. 31 */
6532 OP_SH
, /* shifter operand */
6533 OP_SHG
, /* shifter operand with possible group relocation */
6534 OP_ADDR
, /* Memory address expression (any mode) */
6535 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6536 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6537 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6538 OP_EXP
, /* arbitrary expression */
6539 OP_EXPi
, /* same, with optional immediate prefix */
6540 OP_EXPr
, /* same, with optional relocation suffix */
6541 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6542 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6543 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6545 OP_CPSF
, /* CPS flags */
6546 OP_ENDI
, /* Endianness specifier */
6547 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6548 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6549 OP_COND
, /* conditional code */
6550 OP_TB
, /* Table branch. */
6552 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6554 OP_RRnpc_I0
, /* ARM register or literal 0 */
6555 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6556 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6557 OP_RF_IF
, /* FPA register or immediate */
6558 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6559 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6561 /* Optional operands. */
6562 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6563 OP_oI31b
, /* 0 .. 31 */
6564 OP_oI32b
, /* 1 .. 32 */
6565 OP_oI32z
, /* 0 .. 32 */
6566 OP_oIffffb
, /* 0 .. 65535 */
6567 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6569 OP_oRR
, /* ARM register */
6570 OP_oRRnpc
, /* ARM register, not the PC */
6571 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6572 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6573 OP_oRND
, /* Optional Neon double precision register */
6574 OP_oRNQ
, /* Optional Neon quad precision register */
6575 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6576 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6577 OP_oSHll
, /* LSL immediate */
6578 OP_oSHar
, /* ASR immediate */
6579 OP_oSHllar
, /* LSL or ASR immediate */
6580 OP_oROR
, /* ROR 0/8/16/24 */
6581 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6583 /* Some pre-defined mixed (ARM/THUMB) operands. */
6584 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6585 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6586 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6588 OP_FIRST_OPTIONAL
= OP_oI7b
6591 /* Generic instruction operand parser. This does no encoding and no
6592 semantic validation; it merely squirrels values away in the inst
6593 structure. Returns SUCCESS or FAIL depending on whether the
6594 specified grammar matched. */
6596 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6598 unsigned const int *upat
= pattern
;
6599 char *backtrack_pos
= 0;
6600 const char *backtrack_error
= 0;
6601 int i
, val
= 0, backtrack_index
= 0;
6602 enum arm_reg_type rtype
;
6603 parse_operand_result result
;
6604 unsigned int op_parse_code
;
6606 #define po_char_or_fail(chr) \
6609 if (skip_past_char (&str, chr) == FAIL) \
6614 #define po_reg_or_fail(regtype) \
6617 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6618 & inst.operands[i].vectype); \
6621 first_error (_(reg_expected_msgs[regtype])); \
6624 inst.operands[i].reg = val; \
6625 inst.operands[i].isreg = 1; \
6626 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6627 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6628 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6629 || rtype == REG_TYPE_VFD \
6630 || rtype == REG_TYPE_NQ); \
6634 #define po_reg_or_goto(regtype, label) \
6637 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6638 & inst.operands[i].vectype); \
6642 inst.operands[i].reg = val; \
6643 inst.operands[i].isreg = 1; \
6644 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6645 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6646 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6647 || rtype == REG_TYPE_VFD \
6648 || rtype == REG_TYPE_NQ); \
6652 #define po_imm_or_fail(min, max, popt) \
6655 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6657 inst.operands[i].imm = val; \
6661 #define po_scalar_or_goto(elsz, label) \
6664 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6667 inst.operands[i].reg = val; \
6668 inst.operands[i].isscalar = 1; \
6672 #define po_misc_or_fail(expr) \
6680 #define po_misc_or_fail_no_backtrack(expr) \
6684 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6685 backtrack_pos = 0; \
6686 if (result != PARSE_OPERAND_SUCCESS) \
6691 #define po_barrier_or_imm(str) \
6694 val = parse_barrier (&str); \
6695 if (val == FAIL && ! ISALPHA (*str)) \
6698 /* ISB can only take SY as an option. */ \
6699 || ((inst.instruction & 0xf0) == 0x60 \
6702 inst.error = _("invalid barrier type"); \
6703 backtrack_pos = 0; \
6709 skip_whitespace (str
);
6711 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6713 op_parse_code
= upat
[i
];
6714 if (op_parse_code
>= 1<<16)
6715 op_parse_code
= thumb
? (op_parse_code
>> 16)
6716 : (op_parse_code
& ((1<<16)-1));
6718 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6720 /* Remember where we are in case we need to backtrack. */
6721 gas_assert (!backtrack_pos
);
6722 backtrack_pos
= str
;
6723 backtrack_error
= inst
.error
;
6724 backtrack_index
= i
;
6727 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6728 po_char_or_fail (',');
6730 switch (op_parse_code
)
6738 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6739 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6740 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6741 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6742 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6743 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6745 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6747 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6749 /* Also accept generic coprocessor regs for unknown registers. */
6751 po_reg_or_fail (REG_TYPE_CN
);
6753 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6754 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6755 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6756 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6757 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6758 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6759 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6760 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6761 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6762 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6764 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6766 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6767 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6769 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6771 /* Neon scalar. Using an element size of 8 means that some invalid
6772 scalars are accepted here, so deal with those in later code. */
6773 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6777 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6780 po_imm_or_fail (0, 0, TRUE
);
6785 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6790 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6793 if (parse_ifimm_zero (&str
))
6794 inst
.operands
[i
].imm
= 0;
6798 = _("only floating point zero is allowed as immediate value");
6806 po_scalar_or_goto (8, try_rr
);
6809 po_reg_or_fail (REG_TYPE_RN
);
6815 po_scalar_or_goto (8, try_nsdq
);
6818 po_reg_or_fail (REG_TYPE_NSDQ
);
6824 po_scalar_or_goto (8, try_ndq
);
6827 po_reg_or_fail (REG_TYPE_NDQ
);
6833 po_scalar_or_goto (8, try_vfd
);
6836 po_reg_or_fail (REG_TYPE_VFD
);
6841 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6842 not careful then bad things might happen. */
6843 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6848 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6851 /* There's a possibility of getting a 64-bit immediate here, so
6852 we need special handling. */
6853 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6856 inst
.error
= _("immediate value is out of range");
6864 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6867 po_imm_or_fail (0, 63, TRUE
);
6872 po_char_or_fail ('[');
6873 po_reg_or_fail (REG_TYPE_RN
);
6874 po_char_or_fail (']');
6880 po_reg_or_fail (REG_TYPE_RN
);
6881 if (skip_past_char (&str
, '!') == SUCCESS
)
6882 inst
.operands
[i
].writeback
= 1;
6886 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6887 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6888 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6889 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6890 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6891 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6892 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6893 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6894 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6895 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6896 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6897 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6899 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6901 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6902 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6904 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6905 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6906 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6907 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6909 /* Immediate variants */
6911 po_char_or_fail ('{');
6912 po_imm_or_fail (0, 255, TRUE
);
6913 po_char_or_fail ('}');
6917 /* The expression parser chokes on a trailing !, so we have
6918 to find it first and zap it. */
6921 while (*s
&& *s
!= ',')
6926 inst
.operands
[i
].writeback
= 1;
6928 po_imm_or_fail (0, 31, TRUE
);
6936 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6941 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6946 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6948 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6950 val
= parse_reloc (&str
);
6953 inst
.error
= _("unrecognized relocation suffix");
6956 else if (val
!= BFD_RELOC_UNUSED
)
6958 inst
.operands
[i
].imm
= val
;
6959 inst
.operands
[i
].hasreloc
= 1;
6964 /* Operand for MOVW or MOVT. */
6966 po_misc_or_fail (parse_half (&str
));
6969 /* Register or expression. */
6970 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6971 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6973 /* Register or immediate. */
6974 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6975 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6977 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6979 if (!is_immediate_prefix (*str
))
6982 val
= parse_fpa_immediate (&str
);
6985 /* FPA immediates are encoded as registers 8-15.
6986 parse_fpa_immediate has already applied the offset. */
6987 inst
.operands
[i
].reg
= val
;
6988 inst
.operands
[i
].isreg
= 1;
6991 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6992 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6994 /* Two kinds of register. */
6997 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6999 || (rege
->type
!= REG_TYPE_MMXWR
7000 && rege
->type
!= REG_TYPE_MMXWC
7001 && rege
->type
!= REG_TYPE_MMXWCG
))
7003 inst
.error
= _("iWMMXt data or control register expected");
7006 inst
.operands
[i
].reg
= rege
->number
;
7007 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7013 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7015 || (rege
->type
!= REG_TYPE_MMXWC
7016 && rege
->type
!= REG_TYPE_MMXWCG
))
7018 inst
.error
= _("iWMMXt control register expected");
7021 inst
.operands
[i
].reg
= rege
->number
;
7022 inst
.operands
[i
].isreg
= 1;
7027 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7028 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7029 case OP_oROR
: val
= parse_ror (&str
); break;
7030 case OP_COND
: val
= parse_cond (&str
); break;
7031 case OP_oBARRIER_I15
:
7032 po_barrier_or_imm (str
); break;
7034 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7040 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7041 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7043 inst
.error
= _("Banked registers are not available with this "
7049 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7053 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7056 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7058 if (strncasecmp (str
, "APSR_", 5) == 0)
7065 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7066 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7067 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7068 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7069 default: found
= 16;
7073 inst
.operands
[i
].isvec
= 1;
7074 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7075 inst
.operands
[i
].reg
= REG_PC
;
7082 po_misc_or_fail (parse_tb (&str
));
7085 /* Register lists. */
7087 val
= parse_reg_list (&str
);
7090 inst
.operands
[i
].writeback
= 1;
7096 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7100 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7104 /* Allow Q registers too. */
7105 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7110 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7112 inst
.operands
[i
].issingle
= 1;
7117 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7122 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7123 &inst
.operands
[i
].vectype
);
7126 /* Addressing modes */
7128 po_misc_or_fail (parse_address (&str
, i
));
7132 po_misc_or_fail_no_backtrack (
7133 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7137 po_misc_or_fail_no_backtrack (
7138 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7142 po_misc_or_fail_no_backtrack (
7143 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7147 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7151 po_misc_or_fail_no_backtrack (
7152 parse_shifter_operand_group_reloc (&str
, i
));
7156 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7160 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7164 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7168 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7171 /* Various value-based sanity checks and shared operations. We
7172 do not signal immediate failures for the register constraints;
7173 this allows a syntax error to take precedence. */
7174 switch (op_parse_code
)
7182 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7183 inst
.error
= BAD_PC
;
7188 if (inst
.operands
[i
].isreg
)
7190 if (inst
.operands
[i
].reg
== REG_PC
)
7191 inst
.error
= BAD_PC
;
7192 else if (inst
.operands
[i
].reg
== REG_SP
)
7193 inst
.error
= BAD_SP
;
7198 if (inst
.operands
[i
].isreg
7199 && inst
.operands
[i
].reg
== REG_PC
7200 && (inst
.operands
[i
].writeback
|| thumb
))
7201 inst
.error
= BAD_PC
;
7210 case OP_oBARRIER_I15
:
7219 inst
.operands
[i
].imm
= val
;
7226 /* If we get here, this operand was successfully parsed. */
7227 inst
.operands
[i
].present
= 1;
7231 inst
.error
= BAD_ARGS
;
7236 /* The parse routine should already have set inst.error, but set a
7237 default here just in case. */
7239 inst
.error
= _("syntax error");
7243 /* Do not backtrack over a trailing optional argument that
7244 absorbed some text. We will only fail again, with the
7245 'garbage following instruction' error message, which is
7246 probably less helpful than the current one. */
7247 if (backtrack_index
== i
&& backtrack_pos
!= str
7248 && upat
[i
+1] == OP_stop
)
7251 inst
.error
= _("syntax error");
7255 /* Try again, skipping the optional argument at backtrack_pos. */
7256 str
= backtrack_pos
;
7257 inst
.error
= backtrack_error
;
7258 inst
.operands
[backtrack_index
].present
= 0;
7259 i
= backtrack_index
;
7263 /* Check that we have parsed all the arguments. */
7264 if (*str
!= '\0' && !inst
.error
)
7265 inst
.error
= _("garbage following instruction");
7267 return inst
.error
? FAIL
: SUCCESS
;
7270 #undef po_char_or_fail
7271 #undef po_reg_or_fail
7272 #undef po_reg_or_goto
7273 #undef po_imm_or_fail
7274 #undef po_scalar_or_fail
7275 #undef po_barrier_or_imm
7277 /* Shorthand macro for instruction encoding functions issuing errors. */
7278 #define constraint(expr, err) \
7289 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7290 instructions are unpredictable if these registers are used. This
7291 is the BadReg predicate in ARM's Thumb-2 documentation. */
7292 #define reject_bad_reg(reg) \
7294 if (reg == REG_SP || reg == REG_PC) \
7296 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7301 /* If REG is R13 (the stack pointer), warn that its use is
7303 #define warn_deprecated_sp(reg) \
7305 if (warn_on_deprecated && reg == REG_SP) \
7306 as_tsktsk (_("use of r13 is deprecated")); \
7309 /* Functions for operand encoding. ARM, then Thumb. */
7311 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7313 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7315 The only binary encoding difference is the Coprocessor number. Coprocessor
7316 9 is used for half-precision calculations or conversions. The format of the
7317 instruction is the same as the equivalent Coprocessor 10 instruction that
7318 exists for Single-Precision operation. */
7321 do_scalar_fp16_v82_encode (void)
7323 if (inst
.cond
!= COND_ALWAYS
)
7324 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7325 " the behaviour is UNPREDICTABLE"));
7326 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7329 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7330 mark_feature_used (&arm_ext_fp16
);
7333 /* If VAL can be encoded in the immediate field of an ARM instruction,
7334 return the encoded form. Otherwise, return FAIL. */
7337 encode_arm_immediate (unsigned int val
)
7344 for (i
= 2; i
< 32; i
+= 2)
7345 if ((a
= rotate_left (val
, i
)) <= 0xff)
7346 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7351 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7352 return the encoded form. Otherwise, return FAIL. */
7354 encode_thumb32_immediate (unsigned int val
)
7361 for (i
= 1; i
<= 24; i
++)
7364 if ((val
& ~(0xff << i
)) == 0)
7365 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7369 if (val
== ((a
<< 16) | a
))
7371 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7375 if (val
== ((a
<< 16) | a
))
7376 return 0x200 | (a
>> 8);
7380 /* Encode a VFP SP or DP register number into inst.instruction. */
7383 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7385 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7388 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7391 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7394 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7399 first_error (_("D register out of range for selected VFP version"));
7407 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7411 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7415 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7419 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7423 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7427 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7435 /* Encode a <shift> in an ARM-format instruction. The immediate,
7436 if any, is handled by md_apply_fix. */
7438 encode_arm_shift (int i
)
7440 /* register-shifted register. */
7441 if (inst
.operands
[i
].immisreg
)
7444 for (op_index
= 0; op_index
<= i
; ++op_index
)
7446 /* Check the operand only when it's presented. In pre-UAL syntax,
7447 if the destination register is the same as the first operand, two
7448 register form of the instruction can be used. */
7449 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7450 && inst
.operands
[op_index
].reg
== REG_PC
)
7451 as_warn (UNPRED_REG ("r15"));
7454 if (inst
.operands
[i
].imm
== REG_PC
)
7455 as_warn (UNPRED_REG ("r15"));
7458 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7459 inst
.instruction
|= SHIFT_ROR
<< 5;
7462 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7463 if (inst
.operands
[i
].immisreg
)
7465 inst
.instruction
|= SHIFT_BY_REG
;
7466 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7469 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7474 encode_arm_shifter_operand (int i
)
7476 if (inst
.operands
[i
].isreg
)
7478 inst
.instruction
|= inst
.operands
[i
].reg
;
7479 encode_arm_shift (i
);
7483 inst
.instruction
|= INST_IMMEDIATE
;
7484 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7485 inst
.instruction
|= inst
.operands
[i
].imm
;
7489 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7491 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7494 Generate an error if the operand is not a register. */
7495 constraint (!inst
.operands
[i
].isreg
,
7496 _("Instruction does not support =N addresses"));
7498 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7500 if (inst
.operands
[i
].preind
)
7504 inst
.error
= _("instruction does not accept preindexed addressing");
7507 inst
.instruction
|= PRE_INDEX
;
7508 if (inst
.operands
[i
].writeback
)
7509 inst
.instruction
|= WRITE_BACK
;
7512 else if (inst
.operands
[i
].postind
)
7514 gas_assert (inst
.operands
[i
].writeback
);
7516 inst
.instruction
|= WRITE_BACK
;
7518 else /* unindexed - only for coprocessor */
7520 inst
.error
= _("instruction does not accept unindexed addressing");
7524 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7525 && (((inst
.instruction
& 0x000f0000) >> 16)
7526 == ((inst
.instruction
& 0x0000f000) >> 12)))
7527 as_warn ((inst
.instruction
& LOAD_BIT
)
7528 ? _("destination register same as write-back base")
7529 : _("source register same as write-back base"));
7532 /* inst.operands[i] was set up by parse_address. Encode it into an
7533 ARM-format mode 2 load or store instruction. If is_t is true,
7534 reject forms that cannot be used with a T instruction (i.e. not
7537 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7539 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7541 encode_arm_addr_mode_common (i
, is_t
);
7543 if (inst
.operands
[i
].immisreg
)
7545 constraint ((inst
.operands
[i
].imm
== REG_PC
7546 || (is_pc
&& inst
.operands
[i
].writeback
)),
7548 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7549 inst
.instruction
|= inst
.operands
[i
].imm
;
7550 if (!inst
.operands
[i
].negative
)
7551 inst
.instruction
|= INDEX_UP
;
7552 if (inst
.operands
[i
].shifted
)
7554 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7555 inst
.instruction
|= SHIFT_ROR
<< 5;
7558 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7559 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7563 else /* immediate offset in inst.reloc */
7565 if (is_pc
&& !inst
.reloc
.pc_rel
)
7567 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7569 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7570 cannot use PC in addressing.
7571 PC cannot be used in writeback addressing, either. */
7572 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7575 /* Use of PC in str is deprecated for ARMv7. */
7576 if (warn_on_deprecated
7578 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7579 as_tsktsk (_("use of PC in this instruction is deprecated"));
7582 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7584 /* Prefer + for zero encoded value. */
7585 if (!inst
.operands
[i
].negative
)
7586 inst
.instruction
|= INDEX_UP
;
7587 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7592 /* inst.operands[i] was set up by parse_address. Encode it into an
7593 ARM-format mode 3 load or store instruction. Reject forms that
7594 cannot be used with such instructions. If is_t is true, reject
7595 forms that cannot be used with a T instruction (i.e. not
7598 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7600 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7602 inst
.error
= _("instruction does not accept scaled register index");
7606 encode_arm_addr_mode_common (i
, is_t
);
7608 if (inst
.operands
[i
].immisreg
)
7610 constraint ((inst
.operands
[i
].imm
== REG_PC
7611 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7613 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7615 inst
.instruction
|= inst
.operands
[i
].imm
;
7616 if (!inst
.operands
[i
].negative
)
7617 inst
.instruction
|= INDEX_UP
;
7619 else /* immediate offset in inst.reloc */
7621 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7622 && inst
.operands
[i
].writeback
),
7624 inst
.instruction
|= HWOFFSET_IMM
;
7625 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7627 /* Prefer + for zero encoded value. */
7628 if (!inst
.operands
[i
].negative
)
7629 inst
.instruction
|= INDEX_UP
;
7631 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7636 /* Write immediate bits [7:0] to the following locations:
7638 |28/24|23 19|18 16|15 4|3 0|
7639 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7641 This function is used by VMOV/VMVN/VORR/VBIC. */
7644 neon_write_immbits (unsigned immbits
)
7646 inst
.instruction
|= immbits
& 0xf;
7647 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7648 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7651 /* Invert low-order SIZE bits of XHI:XLO. */
7654 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7656 unsigned immlo
= xlo
? *xlo
: 0;
7657 unsigned immhi
= xhi
? *xhi
: 0;
7662 immlo
= (~immlo
) & 0xff;
7666 immlo
= (~immlo
) & 0xffff;
7670 immhi
= (~immhi
) & 0xffffffff;
7674 immlo
= (~immlo
) & 0xffffffff;
7688 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7692 neon_bits_same_in_bytes (unsigned imm
)
7694 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7695 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7696 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7697 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7700 /* For immediate of above form, return 0bABCD. */
7703 neon_squash_bits (unsigned imm
)
7705 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7706 | ((imm
& 0x01000000) >> 21);
7709 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7712 neon_qfloat_bits (unsigned imm
)
7714 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7717 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7718 the instruction. *OP is passed as the initial value of the op field, and
7719 may be set to a different value depending on the constant (i.e.
7720 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7721 MVN). If the immediate looks like a repeated pattern then also
7722 try smaller element sizes. */
7725 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7726 unsigned *immbits
, int *op
, int size
,
7727 enum neon_el_type type
)
7729 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7731 if (type
== NT_float
&& !float_p
)
7734 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7736 if (size
!= 32 || *op
== 1)
7738 *immbits
= neon_qfloat_bits (immlo
);
7744 if (neon_bits_same_in_bytes (immhi
)
7745 && neon_bits_same_in_bytes (immlo
))
7749 *immbits
= (neon_squash_bits (immhi
) << 4)
7750 | neon_squash_bits (immlo
);
7761 if (immlo
== (immlo
& 0x000000ff))
7766 else if (immlo
== (immlo
& 0x0000ff00))
7768 *immbits
= immlo
>> 8;
7771 else if (immlo
== (immlo
& 0x00ff0000))
7773 *immbits
= immlo
>> 16;
7776 else if (immlo
== (immlo
& 0xff000000))
7778 *immbits
= immlo
>> 24;
7781 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7783 *immbits
= (immlo
>> 8) & 0xff;
7786 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7788 *immbits
= (immlo
>> 16) & 0xff;
7792 if ((immlo
& 0xffff) != (immlo
>> 16))
7799 if (immlo
== (immlo
& 0x000000ff))
7804 else if (immlo
== (immlo
& 0x0000ff00))
7806 *immbits
= immlo
>> 8;
7810 if ((immlo
& 0xff) != (immlo
>> 8))
7815 if (immlo
== (immlo
& 0x000000ff))
7817 /* Don't allow MVN with 8-bit immediate. */
7827 #if defined BFD_HOST_64_BIT
7828 /* Returns TRUE if double precision value V may be cast
7829 to single precision without loss of accuracy. */
7832 is_double_a_single (bfd_int64_t v
)
7834 int exp
= (int)((v
>> 52) & 0x7FF);
7835 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7837 return (exp
== 0 || exp
== 0x7FF
7838 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7839 && (mantissa
& 0x1FFFFFFFl
) == 0;
7842 /* Returns a double precision value casted to single precision
7843 (ignoring the least significant bits in exponent and mantissa). */
7846 double_to_single (bfd_int64_t v
)
7848 int sign
= (int) ((v
>> 63) & 1l);
7849 int exp
= (int) ((v
>> 52) & 0x7FF);
7850 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7856 exp
= exp
- 1023 + 127;
7865 /* No denormalized numbers. */
7871 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7873 #endif /* BFD_HOST_64_BIT */
7882 static void do_vfp_nsyn_opcode (const char *);
7884 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7885 Determine whether it can be performed with a move instruction; if
7886 it can, convert inst.instruction to that move instruction and
7887 return TRUE; if it can't, convert inst.instruction to a literal-pool
7888 load and return FALSE. If this is not a valid thing to do in the
7889 current context, set inst.error and return TRUE.
7891 inst.operands[i] describes the destination register. */
7894 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7897 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7898 bfd_boolean arm_p
= (t
== CONST_ARM
);
7901 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7905 if ((inst
.instruction
& tbit
) == 0)
7907 inst
.error
= _("invalid pseudo operation");
7911 if (inst
.reloc
.exp
.X_op
!= O_constant
7912 && inst
.reloc
.exp
.X_op
!= O_symbol
7913 && inst
.reloc
.exp
.X_op
!= O_big
)
7915 inst
.error
= _("constant expression expected");
7919 if (inst
.reloc
.exp
.X_op
== O_constant
7920 || inst
.reloc
.exp
.X_op
== O_big
)
7922 #if defined BFD_HOST_64_BIT
7927 if (inst
.reloc
.exp
.X_op
== O_big
)
7929 LITTLENUM_TYPE w
[X_PRECISION
];
7932 if (inst
.reloc
.exp
.X_add_number
== -1)
7934 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7936 /* FIXME: Should we check words w[2..5] ? */
7941 #if defined BFD_HOST_64_BIT
7943 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7944 << LITTLENUM_NUMBER_OF_BITS
)
7945 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7946 << LITTLENUM_NUMBER_OF_BITS
)
7947 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7948 << LITTLENUM_NUMBER_OF_BITS
)
7949 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7951 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7952 | (l
[0] & LITTLENUM_MASK
);
7956 v
= inst
.reloc
.exp
.X_add_number
;
7958 if (!inst
.operands
[i
].issingle
)
7962 /* This can be encoded only for a low register. */
7963 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7965 /* This can be done with a mov(1) instruction. */
7966 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7967 inst
.instruction
|= v
;
7971 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7972 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7974 /* Check if on thumb2 it can be done with a mov.w, mvn or
7975 movw instruction. */
7976 unsigned int newimm
;
7977 bfd_boolean isNegated
;
7979 newimm
= encode_thumb32_immediate (v
);
7980 if (newimm
!= (unsigned int) FAIL
)
7984 newimm
= encode_thumb32_immediate (~v
);
7985 if (newimm
!= (unsigned int) FAIL
)
7989 /* The number can be loaded with a mov.w or mvn
7991 if (newimm
!= (unsigned int) FAIL
7992 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7994 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7995 | (inst
.operands
[i
].reg
<< 8));
7996 /* Change to MOVN. */
7997 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7998 inst
.instruction
|= (newimm
& 0x800) << 15;
7999 inst
.instruction
|= (newimm
& 0x700) << 4;
8000 inst
.instruction
|= (newimm
& 0x0ff);
8003 /* The number can be loaded with a movw instruction. */
8004 else if ((v
& ~0xFFFF) == 0
8005 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8007 int imm
= v
& 0xFFFF;
8009 inst
.instruction
= 0xf2400000; /* MOVW. */
8010 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8011 inst
.instruction
|= (imm
& 0xf000) << 4;
8012 inst
.instruction
|= (imm
& 0x0800) << 15;
8013 inst
.instruction
|= (imm
& 0x0700) << 4;
8014 inst
.instruction
|= (imm
& 0x00ff);
8021 int value
= encode_arm_immediate (v
);
8025 /* This can be done with a mov instruction. */
8026 inst
.instruction
&= LITERAL_MASK
;
8027 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8028 inst
.instruction
|= value
& 0xfff;
8032 value
= encode_arm_immediate (~ v
);
8035 /* This can be done with a mvn instruction. */
8036 inst
.instruction
&= LITERAL_MASK
;
8037 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8038 inst
.instruction
|= value
& 0xfff;
8042 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8045 unsigned immbits
= 0;
8046 unsigned immlo
= inst
.operands
[1].imm
;
8047 unsigned immhi
= inst
.operands
[1].regisimm
8048 ? inst
.operands
[1].reg
8049 : inst
.reloc
.exp
.X_unsigned
8051 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8052 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8053 &op
, 64, NT_invtype
);
8057 neon_invert_size (&immlo
, &immhi
, 64);
8059 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8060 &op
, 64, NT_invtype
);
8065 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8071 /* Fill other bits in vmov encoding for both thumb and arm. */
8073 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8075 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8076 neon_write_immbits (immbits
);
8084 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8085 if (inst
.operands
[i
].issingle
8086 && is_quarter_float (inst
.operands
[1].imm
)
8087 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8089 inst
.operands
[1].imm
=
8090 neon_qfloat_bits (v
);
8091 do_vfp_nsyn_opcode ("fconsts");
8095 /* If our host does not support a 64-bit type then we cannot perform
8096 the following optimization. This mean that there will be a
8097 discrepancy between the output produced by an assembler built for
8098 a 32-bit-only host and the output produced from a 64-bit host, but
8099 this cannot be helped. */
8100 #if defined BFD_HOST_64_BIT
8101 else if (!inst
.operands
[1].issingle
8102 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8104 if (is_double_a_single (v
)
8105 && is_quarter_float (double_to_single (v
)))
8107 inst
.operands
[1].imm
=
8108 neon_qfloat_bits (double_to_single (v
));
8109 do_vfp_nsyn_opcode ("fconstd");
8117 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8118 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8121 inst
.operands
[1].reg
= REG_PC
;
8122 inst
.operands
[1].isreg
= 1;
8123 inst
.operands
[1].preind
= 1;
8124 inst
.reloc
.pc_rel
= 1;
8125 inst
.reloc
.type
= (thumb_p
8126 ? BFD_RELOC_ARM_THUMB_OFFSET
8128 ? BFD_RELOC_ARM_HWLITERAL
8129 : BFD_RELOC_ARM_LITERAL
));
8133 /* inst.operands[i] was set up by parse_address. Encode it into an
8134 ARM-format instruction. Reject all forms which cannot be encoded
8135 into a coprocessor load/store instruction. If wb_ok is false,
8136 reject use of writeback; if unind_ok is false, reject use of
8137 unindexed addressing. If reloc_override is not 0, use it instead
8138 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8139 (in which case it is preserved). */
8142 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8144 if (!inst
.operands
[i
].isreg
)
8147 if (! inst
.operands
[0].isvec
)
8149 inst
.error
= _("invalid co-processor operand");
8152 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8156 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8158 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8160 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8162 gas_assert (!inst
.operands
[i
].writeback
);
8165 inst
.error
= _("instruction does not support unindexed addressing");
8168 inst
.instruction
|= inst
.operands
[i
].imm
;
8169 inst
.instruction
|= INDEX_UP
;
8173 if (inst
.operands
[i
].preind
)
8174 inst
.instruction
|= PRE_INDEX
;
8176 if (inst
.operands
[i
].writeback
)
8178 if (inst
.operands
[i
].reg
== REG_PC
)
8180 inst
.error
= _("pc may not be used with write-back");
8185 inst
.error
= _("instruction does not support writeback");
8188 inst
.instruction
|= WRITE_BACK
;
8192 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8193 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8194 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8195 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8198 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8200 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8203 /* Prefer + for zero encoded value. */
8204 if (!inst
.operands
[i
].negative
)
8205 inst
.instruction
|= INDEX_UP
;
8210 /* Functions for instruction encoding, sorted by sub-architecture.
8211 First some generics; their names are taken from the conventional
8212 bit positions for register arguments in ARM format instructions. */
8222 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8228 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8234 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8235 inst
.instruction
|= inst
.operands
[1].reg
;
8241 inst
.instruction
|= inst
.operands
[0].reg
;
8242 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8248 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8249 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8255 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8256 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8262 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8263 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8267 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8269 if (ARM_CPU_IS_ANY (cpu_variant
))
8271 as_tsktsk ("%s", msg
);
8274 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8286 unsigned Rn
= inst
.operands
[2].reg
;
8287 /* Enforce restrictions on SWP instruction. */
8288 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8290 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8291 _("Rn must not overlap other operands"));
8293 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8295 if (!check_obsolete (&arm_ext_v8
,
8296 _("swp{b} use is obsoleted for ARMv8 and later"))
8297 && warn_on_deprecated
8298 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8299 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8303 inst
.instruction
|= inst
.operands
[1].reg
;
8304 inst
.instruction
|= Rn
<< 16;
8310 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8311 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8312 inst
.instruction
|= inst
.operands
[2].reg
;
8318 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8319 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8320 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8321 || inst
.reloc
.exp
.X_add_number
!= 0),
8323 inst
.instruction
|= inst
.operands
[0].reg
;
8324 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8325 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8331 inst
.instruction
|= inst
.operands
[0].imm
;
8337 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8338 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8341 /* ARM instructions, in alphabetical order by function name (except
8342 that wrapper functions appear immediately after the function they
8345 /* This is a pseudo-op of the form "adr rd, label" to be converted
8346 into a relative address of the form "add rd, pc, #label-.-8". */
8351 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8353 /* Frag hacking will turn this into a sub instruction if the offset turns
8354 out to be negative. */
8355 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8356 inst
.reloc
.pc_rel
= 1;
8357 inst
.reloc
.exp
.X_add_number
-= 8;
8360 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8361 into a relative address of the form:
8362 add rd, pc, #low(label-.-8)"
8363 add rd, rd, #high(label-.-8)" */
8368 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8370 /* Frag hacking will turn this into a sub instruction if the offset turns
8371 out to be negative. */
8372 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8373 inst
.reloc
.pc_rel
= 1;
8374 inst
.size
= INSN_SIZE
* 2;
8375 inst
.reloc
.exp
.X_add_number
-= 8;
8381 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8382 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8384 if (!inst
.operands
[1].present
)
8385 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8387 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8388 encode_arm_shifter_operand (2);
8394 if (inst
.operands
[0].present
)
8395 inst
.instruction
|= inst
.operands
[0].imm
;
8397 inst
.instruction
|= 0xf;
8403 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8404 constraint (msb
> 32, _("bit-field extends past end of register"));
8405 /* The instruction encoding stores the LSB and MSB,
8406 not the LSB and width. */
8407 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8408 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8409 inst
.instruction
|= (msb
- 1) << 16;
8417 /* #0 in second position is alternative syntax for bfc, which is
8418 the same instruction but with REG_PC in the Rm field. */
8419 if (!inst
.operands
[1].isreg
)
8420 inst
.operands
[1].reg
= REG_PC
;
8422 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8423 constraint (msb
> 32, _("bit-field extends past end of register"));
8424 /* The instruction encoding stores the LSB and MSB,
8425 not the LSB and width. */
8426 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8427 inst
.instruction
|= inst
.operands
[1].reg
;
8428 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8429 inst
.instruction
|= (msb
- 1) << 16;
8435 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8436 _("bit-field extends past end of register"));
8437 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8438 inst
.instruction
|= inst
.operands
[1].reg
;
8439 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8440 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8443 /* ARM V5 breakpoint instruction (argument parse)
8444 BKPT <16 bit unsigned immediate>
8445 Instruction is not conditional.
8446 The bit pattern given in insns[] has the COND_ALWAYS condition,
8447 and it is an error if the caller tried to override that. */
8452 /* Top 12 of 16 bits to bits 19:8. */
8453 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8455 /* Bottom 4 of 16 bits to bits 3:0. */
8456 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8460 encode_branch (int default_reloc
)
8462 if (inst
.operands
[0].hasreloc
)
8464 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8465 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8466 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8467 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8468 ? BFD_RELOC_ARM_PLT32
8469 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8472 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8473 inst
.reloc
.pc_rel
= 1;
8480 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8481 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8484 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8491 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8493 if (inst
.cond
== COND_ALWAYS
)
8494 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8496 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8500 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8503 /* ARM V5 branch-link-exchange instruction (argument parse)
8504 BLX <target_addr> ie BLX(1)
8505 BLX{<condition>} <Rm> ie BLX(2)
8506 Unfortunately, there are two different opcodes for this mnemonic.
8507 So, the insns[].value is not used, and the code here zaps values
8508 into inst.instruction.
8509 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8514 if (inst
.operands
[0].isreg
)
8516 /* Arg is a register; the opcode provided by insns[] is correct.
8517 It is not illegal to do "blx pc", just useless. */
8518 if (inst
.operands
[0].reg
== REG_PC
)
8519 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8521 inst
.instruction
|= inst
.operands
[0].reg
;
8525 /* Arg is an address; this instruction cannot be executed
8526 conditionally, and the opcode must be adjusted.
8527 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8528 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8529 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8530 inst
.instruction
= 0xfa000000;
8531 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8538 bfd_boolean want_reloc
;
8540 if (inst
.operands
[0].reg
== REG_PC
)
8541 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8543 inst
.instruction
|= inst
.operands
[0].reg
;
8544 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8545 it is for ARMv4t or earlier. */
8546 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8547 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8551 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8556 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8560 /* ARM v5TEJ. Jump to Jazelle code. */
8565 if (inst
.operands
[0].reg
== REG_PC
)
8566 as_tsktsk (_("use of r15 in bxj is not really useful"));
8568 inst
.instruction
|= inst
.operands
[0].reg
;
8571 /* Co-processor data operation:
8572 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8573 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8577 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8578 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8579 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8580 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8581 inst
.instruction
|= inst
.operands
[4].reg
;
8582 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8588 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8589 encode_arm_shifter_operand (1);
8592 /* Transfer between coprocessor and ARM registers.
8593 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8598 No special properties. */
8600 struct deprecated_coproc_regs_s
8607 arm_feature_set deprecated
;
8608 arm_feature_set obsoleted
;
8609 const char *dep_msg
;
8610 const char *obs_msg
;
8613 #define DEPR_ACCESS_V8 \
8614 N_("This coprocessor register access is deprecated in ARMv8")
8616 /* Table of all deprecated coprocessor registers. */
8617 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8619 {15, 0, 7, 10, 5, /* CP15DMB. */
8620 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8621 DEPR_ACCESS_V8
, NULL
},
8622 {15, 0, 7, 10, 4, /* CP15DSB. */
8623 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8624 DEPR_ACCESS_V8
, NULL
},
8625 {15, 0, 7, 5, 4, /* CP15ISB. */
8626 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8627 DEPR_ACCESS_V8
, NULL
},
8628 {14, 6, 1, 0, 0, /* TEEHBR. */
8629 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8630 DEPR_ACCESS_V8
, NULL
},
8631 {14, 6, 0, 0, 0, /* TEECR. */
8632 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8633 DEPR_ACCESS_V8
, NULL
},
8636 #undef DEPR_ACCESS_V8
8638 static const size_t deprecated_coproc_reg_count
=
8639 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8647 Rd
= inst
.operands
[2].reg
;
8650 if (inst
.instruction
== 0xee000010
8651 || inst
.instruction
== 0xfe000010)
8653 reject_bad_reg (Rd
);
8656 constraint (Rd
== REG_SP
, BAD_SP
);
8661 if (inst
.instruction
== 0xe000010)
8662 constraint (Rd
== REG_PC
, BAD_PC
);
8665 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8667 const struct deprecated_coproc_regs_s
*r
=
8668 deprecated_coproc_regs
+ i
;
8670 if (inst
.operands
[0].reg
== r
->cp
8671 && inst
.operands
[1].imm
== r
->opc1
8672 && inst
.operands
[3].reg
== r
->crn
8673 && inst
.operands
[4].reg
== r
->crm
8674 && inst
.operands
[5].imm
== r
->opc2
)
8676 if (! ARM_CPU_IS_ANY (cpu_variant
)
8677 && warn_on_deprecated
8678 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8679 as_tsktsk ("%s", r
->dep_msg
);
8683 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8684 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8685 inst
.instruction
|= Rd
<< 12;
8686 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8687 inst
.instruction
|= inst
.operands
[4].reg
;
8688 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8691 /* Transfer between coprocessor register and pair of ARM registers.
8692 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8697 Two XScale instructions are special cases of these:
8699 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8700 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8702 Result unpredictable if Rd or Rn is R15. */
8709 Rd
= inst
.operands
[2].reg
;
8710 Rn
= inst
.operands
[3].reg
;
8714 reject_bad_reg (Rd
);
8715 reject_bad_reg (Rn
);
8719 constraint (Rd
== REG_PC
, BAD_PC
);
8720 constraint (Rn
== REG_PC
, BAD_PC
);
8723 /* Only check the MRRC{2} variants. */
8724 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8726 /* If Rd == Rn, error that the operation is
8727 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8728 constraint (Rd
== Rn
, BAD_OVERLAP
);
8731 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8732 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8733 inst
.instruction
|= Rd
<< 12;
8734 inst
.instruction
|= Rn
<< 16;
8735 inst
.instruction
|= inst
.operands
[4].reg
;
8741 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8742 if (inst
.operands
[1].present
)
8744 inst
.instruction
|= CPSI_MMOD
;
8745 inst
.instruction
|= inst
.operands
[1].imm
;
8752 inst
.instruction
|= inst
.operands
[0].imm
;
8758 unsigned Rd
, Rn
, Rm
;
8760 Rd
= inst
.operands
[0].reg
;
8761 Rn
= (inst
.operands
[1].present
8762 ? inst
.operands
[1].reg
: Rd
);
8763 Rm
= inst
.operands
[2].reg
;
8765 constraint ((Rd
== REG_PC
), BAD_PC
);
8766 constraint ((Rn
== REG_PC
), BAD_PC
);
8767 constraint ((Rm
== REG_PC
), BAD_PC
);
8769 inst
.instruction
|= Rd
<< 16;
8770 inst
.instruction
|= Rn
<< 0;
8771 inst
.instruction
|= Rm
<< 8;
8777 /* There is no IT instruction in ARM mode. We
8778 process it to do the validation as if in
8779 thumb mode, just in case the code gets
8780 assembled for thumb using the unified syntax. */
8785 set_it_insn_type (IT_INSN
);
8786 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8787 now_it
.cc
= inst
.operands
[0].imm
;
8791 /* If there is only one register in the register list,
8792 then return its register number. Otherwise return -1. */
8794 only_one_reg_in_list (int range
)
8796 int i
= ffs (range
) - 1;
8797 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8801 encode_ldmstm(int from_push_pop_mnem
)
8803 int base_reg
= inst
.operands
[0].reg
;
8804 int range
= inst
.operands
[1].imm
;
8807 inst
.instruction
|= base_reg
<< 16;
8808 inst
.instruction
|= range
;
8810 if (inst
.operands
[1].writeback
)
8811 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8813 if (inst
.operands
[0].writeback
)
8815 inst
.instruction
|= WRITE_BACK
;
8816 /* Check for unpredictable uses of writeback. */
8817 if (inst
.instruction
& LOAD_BIT
)
8819 /* Not allowed in LDM type 2. */
8820 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8821 && ((range
& (1 << REG_PC
)) == 0))
8822 as_warn (_("writeback of base register is UNPREDICTABLE"));
8823 /* Only allowed if base reg not in list for other types. */
8824 else if (range
& (1 << base_reg
))
8825 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8829 /* Not allowed for type 2. */
8830 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8831 as_warn (_("writeback of base register is UNPREDICTABLE"));
8832 /* Only allowed if base reg not in list, or first in list. */
8833 else if ((range
& (1 << base_reg
))
8834 && (range
& ((1 << base_reg
) - 1)))
8835 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8839 /* If PUSH/POP has only one register, then use the A2 encoding. */
8840 one_reg
= only_one_reg_in_list (range
);
8841 if (from_push_pop_mnem
&& one_reg
>= 0)
8843 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8845 inst
.instruction
&= A_COND_MASK
;
8846 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8847 inst
.instruction
|= one_reg
<< 12;
8854 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8857 /* ARMv5TE load-consecutive (argument parse)
8866 constraint (inst
.operands
[0].reg
% 2 != 0,
8867 _("first transfer register must be even"));
8868 constraint (inst
.operands
[1].present
8869 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8870 _("can only transfer two consecutive registers"));
8871 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8872 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8874 if (!inst
.operands
[1].present
)
8875 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8877 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8878 register and the first register written; we have to diagnose
8879 overlap between the base and the second register written here. */
8881 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8882 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8883 as_warn (_("base register written back, and overlaps "
8884 "second transfer register"));
8886 if (!(inst
.instruction
& V4_STR_BIT
))
8888 /* For an index-register load, the index register must not overlap the
8889 destination (even if not write-back). */
8890 if (inst
.operands
[2].immisreg
8891 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8892 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8893 as_warn (_("index register overlaps transfer register"));
8895 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8896 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8902 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8903 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8904 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8905 || inst
.operands
[1].negative
8906 /* This can arise if the programmer has written
8908 or if they have mistakenly used a register name as the last
8911 It is very difficult to distinguish between these two cases
8912 because "rX" might actually be a label. ie the register
8913 name has been occluded by a symbol of the same name. So we
8914 just generate a general 'bad addressing mode' type error
8915 message and leave it up to the programmer to discover the
8916 true cause and fix their mistake. */
8917 || (inst
.operands
[1].reg
== REG_PC
),
8920 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8921 || inst
.reloc
.exp
.X_add_number
!= 0,
8922 _("offset must be zero in ARM encoding"));
8924 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8927 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8928 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8934 constraint (inst
.operands
[0].reg
% 2 != 0,
8935 _("even register required"));
8936 constraint (inst
.operands
[1].present
8937 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8938 _("can only load two consecutive registers"));
8939 /* If op 1 were present and equal to PC, this function wouldn't
8940 have been called in the first place. */
8941 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8943 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8944 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8947 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8948 which is not a multiple of four is UNPREDICTABLE. */
8950 check_ldr_r15_aligned (void)
8952 constraint (!(inst
.operands
[1].immisreg
)
8953 && (inst
.operands
[0].reg
== REG_PC
8954 && inst
.operands
[1].reg
== REG_PC
8955 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8956 _("ldr to register 15 must be 4-byte alligned"));
8962 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8963 if (!inst
.operands
[1].isreg
)
8964 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8966 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8967 check_ldr_r15_aligned ();
8973 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8975 if (inst
.operands
[1].preind
)
8977 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8978 || inst
.reloc
.exp
.X_add_number
!= 0,
8979 _("this instruction requires a post-indexed address"));
8981 inst
.operands
[1].preind
= 0;
8982 inst
.operands
[1].postind
= 1;
8983 inst
.operands
[1].writeback
= 1;
8985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8986 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8989 /* Halfword and signed-byte load/store operations. */
8994 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8995 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8996 if (!inst
.operands
[1].isreg
)
8997 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8999 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9005 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9007 if (inst
.operands
[1].preind
)
9009 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9010 || inst
.reloc
.exp
.X_add_number
!= 0,
9011 _("this instruction requires a post-indexed address"));
9013 inst
.operands
[1].preind
= 0;
9014 inst
.operands
[1].postind
= 1;
9015 inst
.operands
[1].writeback
= 1;
9017 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9018 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9021 /* Co-processor register load/store.
9022 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9026 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9027 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9028 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9034 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9035 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9036 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9037 && !(inst
.instruction
& 0x00400000))
9038 as_tsktsk (_("Rd and Rm should be different in mla"));
9040 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9041 inst
.instruction
|= inst
.operands
[1].reg
;
9042 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9043 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9049 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9050 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9052 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9053 encode_arm_shifter_operand (1);
9056 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9063 top
= (inst
.instruction
& 0x00400000) != 0;
9064 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9065 _(":lower16: not allowed in this instruction"));
9066 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9067 _(":upper16: not allowed in this instruction"));
9068 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9069 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9071 imm
= inst
.reloc
.exp
.X_add_number
;
9072 /* The value is in two pieces: 0:11, 16:19. */
9073 inst
.instruction
|= (imm
& 0x00000fff);
9074 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9079 do_vfp_nsyn_mrs (void)
9081 if (inst
.operands
[0].isvec
)
9083 if (inst
.operands
[1].reg
!= 1)
9084 first_error (_("operand 1 must be FPSCR"));
9085 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9086 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9087 do_vfp_nsyn_opcode ("fmstat");
9089 else if (inst
.operands
[1].isvec
)
9090 do_vfp_nsyn_opcode ("fmrx");
9098 do_vfp_nsyn_msr (void)
9100 if (inst
.operands
[0].isvec
)
9101 do_vfp_nsyn_opcode ("fmxr");
9111 unsigned Rt
= inst
.operands
[0].reg
;
9113 if (thumb_mode
&& Rt
== REG_SP
)
9115 inst
.error
= BAD_SP
;
9119 /* APSR_ sets isvec. All other refs to PC are illegal. */
9120 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9122 inst
.error
= BAD_PC
;
9126 /* If we get through parsing the register name, we just insert the number
9127 generated into the instruction without further validation. */
9128 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9129 inst
.instruction
|= (Rt
<< 12);
9135 unsigned Rt
= inst
.operands
[1].reg
;
9138 reject_bad_reg (Rt
);
9139 else if (Rt
== REG_PC
)
9141 inst
.error
= BAD_PC
;
9145 /* If we get through parsing the register name, we just insert the number
9146 generated into the instruction without further validation. */
9147 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9148 inst
.instruction
|= (Rt
<< 12);
9156 if (do_vfp_nsyn_mrs () == SUCCESS
)
9159 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9160 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9162 if (inst
.operands
[1].isreg
)
9164 br
= inst
.operands
[1].reg
;
9165 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9166 as_bad (_("bad register for mrs"));
9170 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9171 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9173 _("'APSR', 'CPSR' or 'SPSR' expected"));
9174 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9177 inst
.instruction
|= br
;
9180 /* Two possible forms:
9181 "{C|S}PSR_<field>, Rm",
9182 "{C|S}PSR_f, #expression". */
9187 if (do_vfp_nsyn_msr () == SUCCESS
)
9190 inst
.instruction
|= inst
.operands
[0].imm
;
9191 if (inst
.operands
[1].isreg
)
9192 inst
.instruction
|= inst
.operands
[1].reg
;
9195 inst
.instruction
|= INST_IMMEDIATE
;
9196 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9197 inst
.reloc
.pc_rel
= 0;
9204 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9206 if (!inst
.operands
[2].present
)
9207 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9208 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9209 inst
.instruction
|= inst
.operands
[1].reg
;
9210 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9212 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9213 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9214 as_tsktsk (_("Rd and Rm should be different in mul"));
9217 /* Long Multiply Parser
9218 UMULL RdLo, RdHi, Rm, Rs
9219 SMULL RdLo, RdHi, Rm, Rs
9220 UMLAL RdLo, RdHi, Rm, Rs
9221 SMLAL RdLo, RdHi, Rm, Rs. */
9226 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9227 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9228 inst
.instruction
|= inst
.operands
[2].reg
;
9229 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9231 /* rdhi and rdlo must be different. */
9232 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9233 as_tsktsk (_("rdhi and rdlo must be different"));
9235 /* rdhi, rdlo and rm must all be different before armv6. */
9236 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9237 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9238 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9239 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9245 if (inst
.operands
[0].present
9246 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9248 /* Architectural NOP hints are CPSR sets with no bits selected. */
9249 inst
.instruction
&= 0xf0000000;
9250 inst
.instruction
|= 0x0320f000;
9251 if (inst
.operands
[0].present
)
9252 inst
.instruction
|= inst
.operands
[0].imm
;
9256 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9257 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9258 Condition defaults to COND_ALWAYS.
9259 Error if Rd, Rn or Rm are R15. */
9264 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9265 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9266 inst
.instruction
|= inst
.operands
[2].reg
;
9267 if (inst
.operands
[3].present
)
9268 encode_arm_shift (3);
9271 /* ARM V6 PKHTB (Argument Parse). */
9276 if (!inst
.operands
[3].present
)
9278 /* If the shift specifier is omitted, turn the instruction
9279 into pkhbt rd, rm, rn. */
9280 inst
.instruction
&= 0xfff00010;
9281 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9282 inst
.instruction
|= inst
.operands
[1].reg
;
9283 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9287 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9288 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9289 inst
.instruction
|= inst
.operands
[2].reg
;
9290 encode_arm_shift (3);
9294 /* ARMv5TE: Preload-Cache
9295 MP Extensions: Preload for write
9299 Syntactically, like LDR with B=1, W=0, L=1. */
9304 constraint (!inst
.operands
[0].isreg
,
9305 _("'[' expected after PLD mnemonic"));
9306 constraint (inst
.operands
[0].postind
,
9307 _("post-indexed expression used in preload instruction"));
9308 constraint (inst
.operands
[0].writeback
,
9309 _("writeback used in preload instruction"));
9310 constraint (!inst
.operands
[0].preind
,
9311 _("unindexed addressing used in preload instruction"));
9312 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9315 /* ARMv7: PLI <addr_mode> */
9319 constraint (!inst
.operands
[0].isreg
,
9320 _("'[' expected after PLI mnemonic"));
9321 constraint (inst
.operands
[0].postind
,
9322 _("post-indexed expression used in preload instruction"));
9323 constraint (inst
.operands
[0].writeback
,
9324 _("writeback used in preload instruction"));
9325 constraint (!inst
.operands
[0].preind
,
9326 _("unindexed addressing used in preload instruction"));
9327 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9328 inst
.instruction
&= ~PRE_INDEX
;
9334 constraint (inst
.operands
[0].writeback
,
9335 _("push/pop do not support {reglist}^"));
9336 inst
.operands
[1] = inst
.operands
[0];
9337 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9338 inst
.operands
[0].isreg
= 1;
9339 inst
.operands
[0].writeback
= 1;
9340 inst
.operands
[0].reg
= REG_SP
;
9341 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9344 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9345 word at the specified address and the following word
9347 Unconditionally executed.
9348 Error if Rn is R15. */
9353 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9354 if (inst
.operands
[0].writeback
)
9355 inst
.instruction
|= WRITE_BACK
;
9358 /* ARM V6 ssat (argument parse). */
9363 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9364 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9365 inst
.instruction
|= inst
.operands
[2].reg
;
9367 if (inst
.operands
[3].present
)
9368 encode_arm_shift (3);
9371 /* ARM V6 usat (argument parse). */
9376 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9377 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9378 inst
.instruction
|= inst
.operands
[2].reg
;
9380 if (inst
.operands
[3].present
)
9381 encode_arm_shift (3);
9384 /* ARM V6 ssat16 (argument parse). */
9389 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9390 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9391 inst
.instruction
|= inst
.operands
[2].reg
;
9397 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9398 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9399 inst
.instruction
|= inst
.operands
[2].reg
;
9402 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9403 preserving the other bits.
9405 setend <endian_specifier>, where <endian_specifier> is either
9411 if (warn_on_deprecated
9412 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9413 as_tsktsk (_("setend use is deprecated for ARMv8"));
9415 if (inst
.operands
[0].imm
)
9416 inst
.instruction
|= 0x200;
9422 unsigned int Rm
= (inst
.operands
[1].present
9423 ? inst
.operands
[1].reg
9424 : inst
.operands
[0].reg
);
9426 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9427 inst
.instruction
|= Rm
;
9428 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9430 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9431 inst
.instruction
|= SHIFT_BY_REG
;
9432 /* PR 12854: Error on extraneous shifts. */
9433 constraint (inst
.operands
[2].shifted
,
9434 _("extraneous shift as part of operand to shift insn"));
9437 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9443 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9444 inst
.reloc
.pc_rel
= 0;
9450 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9451 inst
.reloc
.pc_rel
= 0;
9457 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9458 inst
.reloc
.pc_rel
= 0;
9464 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9465 _("selected processor does not support SETPAN instruction"));
9467 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9473 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9474 _("selected processor does not support SETPAN instruction"));
9476 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9479 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9480 SMLAxy{cond} Rd,Rm,Rs,Rn
9481 SMLAWy{cond} Rd,Rm,Rs,Rn
9482 Error if any register is R15. */
9487 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9488 inst
.instruction
|= inst
.operands
[1].reg
;
9489 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9490 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9493 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9494 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9495 Error if any register is R15.
9496 Warning if Rdlo == Rdhi. */
9501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9502 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9503 inst
.instruction
|= inst
.operands
[2].reg
;
9504 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9506 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9507 as_tsktsk (_("rdhi and rdlo must be different"));
9510 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9511 SMULxy{cond} Rd,Rm,Rs
9512 Error if any register is R15. */
9517 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9518 inst
.instruction
|= inst
.operands
[1].reg
;
9519 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9522 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9523 the same for both ARM and Thumb-2. */
9530 if (inst
.operands
[0].present
)
9532 reg
= inst
.operands
[0].reg
;
9533 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9538 inst
.instruction
|= reg
<< 16;
9539 inst
.instruction
|= inst
.operands
[1].imm
;
9540 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9541 inst
.instruction
|= WRITE_BACK
;
9544 /* ARM V6 strex (argument parse). */
9549 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9550 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9551 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9552 || inst
.operands
[2].negative
9553 /* See comment in do_ldrex(). */
9554 || (inst
.operands
[2].reg
== REG_PC
),
9557 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9558 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9560 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9561 || inst
.reloc
.exp
.X_add_number
!= 0,
9562 _("offset must be zero in ARM encoding"));
9564 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9565 inst
.instruction
|= inst
.operands
[1].reg
;
9566 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9567 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9573 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9574 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9575 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9576 || inst
.operands
[2].negative
,
9579 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9580 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9588 constraint (inst
.operands
[1].reg
% 2 != 0,
9589 _("even register required"));
9590 constraint (inst
.operands
[2].present
9591 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9592 _("can only store two consecutive registers"));
9593 /* If op 2 were present and equal to PC, this function wouldn't
9594 have been called in the first place. */
9595 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9597 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9598 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9599 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9602 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9603 inst
.instruction
|= inst
.operands
[1].reg
;
9604 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9611 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9612 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9620 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9621 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9626 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9627 extends it to 32-bits, and adds the result to a value in another
9628 register. You can specify a rotation by 0, 8, 16, or 24 bits
9629 before extracting the 16-bit value.
9630 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9631 Condition defaults to COND_ALWAYS.
9632 Error if any register uses R15. */
9637 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9638 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9639 inst
.instruction
|= inst
.operands
[2].reg
;
9640 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9645 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9646 Condition defaults to COND_ALWAYS.
9647 Error if any register uses R15. */
9652 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9653 inst
.instruction
|= inst
.operands
[1].reg
;
9654 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9657 /* VFP instructions. In a logical order: SP variant first, monad
9658 before dyad, arithmetic then move then load/store. */
9661 do_vfp_sp_monadic (void)
9663 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9664 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9668 do_vfp_sp_dyadic (void)
9670 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9671 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9672 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9676 do_vfp_sp_compare_z (void)
9678 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9682 do_vfp_dp_sp_cvt (void)
9684 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9685 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9689 do_vfp_sp_dp_cvt (void)
9691 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9692 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9696 do_vfp_reg_from_sp (void)
9698 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9699 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9703 do_vfp_reg2_from_sp2 (void)
9705 constraint (inst
.operands
[2].imm
!= 2,
9706 _("only two consecutive VFP SP registers allowed here"));
9707 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9708 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9709 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9713 do_vfp_sp_from_reg (void)
9715 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9716 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9720 do_vfp_sp2_from_reg2 (void)
9722 constraint (inst
.operands
[0].imm
!= 2,
9723 _("only two consecutive VFP SP registers allowed here"));
9724 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9725 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9726 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9730 do_vfp_sp_ldst (void)
9732 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9733 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9737 do_vfp_dp_ldst (void)
9739 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9740 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9745 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9747 if (inst
.operands
[0].writeback
)
9748 inst
.instruction
|= WRITE_BACK
;
9750 constraint (ldstm_type
!= VFP_LDSTMIA
,
9751 _("this addressing mode requires base-register writeback"));
9752 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9753 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9754 inst
.instruction
|= inst
.operands
[1].imm
;
9758 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9762 if (inst
.operands
[0].writeback
)
9763 inst
.instruction
|= WRITE_BACK
;
9765 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9766 _("this addressing mode requires base-register writeback"));
9768 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9769 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9771 count
= inst
.operands
[1].imm
<< 1;
9772 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9775 inst
.instruction
|= count
;
9779 do_vfp_sp_ldstmia (void)
9781 vfp_sp_ldstm (VFP_LDSTMIA
);
9785 do_vfp_sp_ldstmdb (void)
9787 vfp_sp_ldstm (VFP_LDSTMDB
);
9791 do_vfp_dp_ldstmia (void)
9793 vfp_dp_ldstm (VFP_LDSTMIA
);
9797 do_vfp_dp_ldstmdb (void)
9799 vfp_dp_ldstm (VFP_LDSTMDB
);
9803 do_vfp_xp_ldstmia (void)
9805 vfp_dp_ldstm (VFP_LDSTMIAX
);
9809 do_vfp_xp_ldstmdb (void)
9811 vfp_dp_ldstm (VFP_LDSTMDBX
);
9815 do_vfp_dp_rd_rm (void)
9817 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9818 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9822 do_vfp_dp_rn_rd (void)
9824 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9825 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9829 do_vfp_dp_rd_rn (void)
9831 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9832 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9836 do_vfp_dp_rd_rn_rm (void)
9838 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9839 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9840 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9846 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9850 do_vfp_dp_rm_rd_rn (void)
9852 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9853 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9854 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9857 /* VFPv3 instructions. */
9859 do_vfp_sp_const (void)
9861 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9862 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9863 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9867 do_vfp_dp_const (void)
9869 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9870 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9871 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9875 vfp_conv (int srcsize
)
9877 int immbits
= srcsize
- inst
.operands
[1].imm
;
9879 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9881 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9882 i.e. immbits must be in range 0 - 16. */
9883 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9886 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9888 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9889 i.e. immbits must be in range 0 - 31. */
9890 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9894 inst
.instruction
|= (immbits
& 1) << 5;
9895 inst
.instruction
|= (immbits
>> 1);
9899 do_vfp_sp_conv_16 (void)
9901 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9906 do_vfp_dp_conv_16 (void)
9908 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9913 do_vfp_sp_conv_32 (void)
9915 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9920 do_vfp_dp_conv_32 (void)
9922 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9926 /* FPA instructions. Also in a logical order. */
9931 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9932 inst
.instruction
|= inst
.operands
[1].reg
;
9936 do_fpa_ldmstm (void)
9938 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9939 switch (inst
.operands
[1].imm
)
9941 case 1: inst
.instruction
|= CP_T_X
; break;
9942 case 2: inst
.instruction
|= CP_T_Y
; break;
9943 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9948 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9950 /* The instruction specified "ea" or "fd", so we can only accept
9951 [Rn]{!}. The instruction does not really support stacking or
9952 unstacking, so we have to emulate these by setting appropriate
9953 bits and offsets. */
9954 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9955 || inst
.reloc
.exp
.X_add_number
!= 0,
9956 _("this instruction does not support indexing"));
9958 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9959 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9961 if (!(inst
.instruction
& INDEX_UP
))
9962 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9964 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9966 inst
.operands
[2].preind
= 0;
9967 inst
.operands
[2].postind
= 1;
9971 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9974 /* iWMMXt instructions: strictly in alphabetical order. */
9977 do_iwmmxt_tandorc (void)
9979 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9983 do_iwmmxt_textrc (void)
9985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9986 inst
.instruction
|= inst
.operands
[1].imm
;
9990 do_iwmmxt_textrm (void)
9992 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9993 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9994 inst
.instruction
|= inst
.operands
[2].imm
;
9998 do_iwmmxt_tinsr (void)
10000 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10001 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10002 inst
.instruction
|= inst
.operands
[2].imm
;
10006 do_iwmmxt_tmia (void)
10008 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10009 inst
.instruction
|= inst
.operands
[1].reg
;
10010 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10014 do_iwmmxt_waligni (void)
10016 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10017 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10018 inst
.instruction
|= inst
.operands
[2].reg
;
10019 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10023 do_iwmmxt_wmerge (void)
10025 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10026 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10027 inst
.instruction
|= inst
.operands
[2].reg
;
10028 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10032 do_iwmmxt_wmov (void)
10034 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10035 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10036 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10037 inst
.instruction
|= inst
.operands
[1].reg
;
10041 do_iwmmxt_wldstbh (void)
10044 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10046 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10048 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10049 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10053 do_iwmmxt_wldstw (void)
10055 /* RIWR_RIWC clears .isreg for a control register. */
10056 if (!inst
.operands
[0].isreg
)
10058 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10059 inst
.instruction
|= 0xf0000000;
10062 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10063 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10067 do_iwmmxt_wldstd (void)
10069 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10070 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10071 && inst
.operands
[1].immisreg
)
10073 inst
.instruction
&= ~0x1a000ff;
10074 inst
.instruction
|= (0xfU
<< 28);
10075 if (inst
.operands
[1].preind
)
10076 inst
.instruction
|= PRE_INDEX
;
10077 if (!inst
.operands
[1].negative
)
10078 inst
.instruction
|= INDEX_UP
;
10079 if (inst
.operands
[1].writeback
)
10080 inst
.instruction
|= WRITE_BACK
;
10081 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10082 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10083 inst
.instruction
|= inst
.operands
[1].imm
;
10086 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10090 do_iwmmxt_wshufh (void)
10092 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10093 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10094 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10095 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10099 do_iwmmxt_wzero (void)
10101 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10102 inst
.instruction
|= inst
.operands
[0].reg
;
10103 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10104 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10108 do_iwmmxt_wrwrwr_or_imm5 (void)
10110 if (inst
.operands
[2].isreg
)
10113 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10114 _("immediate operand requires iWMMXt2"));
10116 if (inst
.operands
[2].imm
== 0)
10118 switch ((inst
.instruction
>> 20) & 0xf)
10124 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10125 inst
.operands
[2].imm
= 16;
10126 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10132 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10133 inst
.operands
[2].imm
= 32;
10134 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10141 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10143 wrn
= (inst
.instruction
>> 16) & 0xf;
10144 inst
.instruction
&= 0xff0fff0f;
10145 inst
.instruction
|= wrn
;
10146 /* Bail out here; the instruction is now assembled. */
10151 /* Map 32 -> 0, etc. */
10152 inst
.operands
[2].imm
&= 0x1f;
10153 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10157 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10158 operations first, then control, shift, and load/store. */
10160 /* Insns like "foo X,Y,Z". */
10163 do_mav_triple (void)
10165 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10166 inst
.instruction
|= inst
.operands
[1].reg
;
10167 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10170 /* Insns like "foo W,X,Y,Z".
10171 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10176 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10177 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10178 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10179 inst
.instruction
|= inst
.operands
[3].reg
;
10182 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10184 do_mav_dspsc (void)
10186 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10189 /* Maverick shift immediate instructions.
10190 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10191 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10194 do_mav_shift (void)
10196 int imm
= inst
.operands
[2].imm
;
10198 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10199 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10201 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10202 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10203 Bit 4 should be 0. */
10204 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10206 inst
.instruction
|= imm
;
10209 /* XScale instructions. Also sorted arithmetic before move. */
10211 /* Xscale multiply-accumulate (argument parse)
10214 MIAxycc acc0,Rm,Rs. */
10219 inst
.instruction
|= inst
.operands
[1].reg
;
10220 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10223 /* Xscale move-accumulator-register (argument parse)
10225 MARcc acc0,RdLo,RdHi. */
10230 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10231 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10234 /* Xscale move-register-accumulator (argument parse)
10236 MRAcc RdLo,RdHi,acc0. */
10241 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10242 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10243 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10246 /* Encoding functions relevant only to Thumb. */
10248 /* inst.operands[i] is a shifted-register operand; encode
10249 it into inst.instruction in the format used by Thumb32. */
10252 encode_thumb32_shifted_operand (int i
)
10254 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10255 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10257 constraint (inst
.operands
[i
].immisreg
,
10258 _("shift by register not allowed in thumb mode"));
10259 inst
.instruction
|= inst
.operands
[i
].reg
;
10260 if (shift
== SHIFT_RRX
)
10261 inst
.instruction
|= SHIFT_ROR
<< 4;
10264 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10265 _("expression too complex"));
10267 constraint (value
> 32
10268 || (value
== 32 && (shift
== SHIFT_LSL
10269 || shift
== SHIFT_ROR
)),
10270 _("shift expression is too large"));
10274 else if (value
== 32)
10277 inst
.instruction
|= shift
<< 4;
10278 inst
.instruction
|= (value
& 0x1c) << 10;
10279 inst
.instruction
|= (value
& 0x03) << 6;
10284 /* inst.operands[i] was set up by parse_address. Encode it into a
10285 Thumb32 format load or store instruction. Reject forms that cannot
10286 be used with such instructions. If is_t is true, reject forms that
10287 cannot be used with a T instruction; if is_d is true, reject forms
10288 that cannot be used with a D instruction. If it is a store insn,
10289 reject PC in Rn. */
10292 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10294 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10296 constraint (!inst
.operands
[i
].isreg
,
10297 _("Instruction does not support =N addresses"));
10299 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10300 if (inst
.operands
[i
].immisreg
)
10302 constraint (is_pc
, BAD_PC_ADDRESSING
);
10303 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10304 constraint (inst
.operands
[i
].negative
,
10305 _("Thumb does not support negative register indexing"));
10306 constraint (inst
.operands
[i
].postind
,
10307 _("Thumb does not support register post-indexing"));
10308 constraint (inst
.operands
[i
].writeback
,
10309 _("Thumb does not support register indexing with writeback"));
10310 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10311 _("Thumb supports only LSL in shifted register indexing"));
10313 inst
.instruction
|= inst
.operands
[i
].imm
;
10314 if (inst
.operands
[i
].shifted
)
10316 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10317 _("expression too complex"));
10318 constraint (inst
.reloc
.exp
.X_add_number
< 0
10319 || inst
.reloc
.exp
.X_add_number
> 3,
10320 _("shift out of range"));
10321 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10323 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10325 else if (inst
.operands
[i
].preind
)
10327 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10328 constraint (is_t
&& inst
.operands
[i
].writeback
,
10329 _("cannot use writeback with this instruction"));
10330 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10331 BAD_PC_ADDRESSING
);
10335 inst
.instruction
|= 0x01000000;
10336 if (inst
.operands
[i
].writeback
)
10337 inst
.instruction
|= 0x00200000;
10341 inst
.instruction
|= 0x00000c00;
10342 if (inst
.operands
[i
].writeback
)
10343 inst
.instruction
|= 0x00000100;
10345 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10347 else if (inst
.operands
[i
].postind
)
10349 gas_assert (inst
.operands
[i
].writeback
);
10350 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10351 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10354 inst
.instruction
|= 0x00200000;
10356 inst
.instruction
|= 0x00000900;
10357 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10359 else /* unindexed - only for coprocessor */
10360 inst
.error
= _("instruction does not accept unindexed addressing");
10363 /* Table of Thumb instructions which exist in both 16- and 32-bit
10364 encodings (the latter only in post-V6T2 cores). The index is the
10365 value used in the insns table below. When there is more than one
10366 possible 16-bit encoding for the instruction, this table always
10368 Also contains several pseudo-instructions used during relaxation. */
10369 #define T16_32_TAB \
10370 X(_adc, 4140, eb400000), \
10371 X(_adcs, 4140, eb500000), \
10372 X(_add, 1c00, eb000000), \
10373 X(_adds, 1c00, eb100000), \
10374 X(_addi, 0000, f1000000), \
10375 X(_addis, 0000, f1100000), \
10376 X(_add_pc,000f, f20f0000), \
10377 X(_add_sp,000d, f10d0000), \
10378 X(_adr, 000f, f20f0000), \
10379 X(_and, 4000, ea000000), \
10380 X(_ands, 4000, ea100000), \
10381 X(_asr, 1000, fa40f000), \
10382 X(_asrs, 1000, fa50f000), \
10383 X(_b, e000, f000b000), \
10384 X(_bcond, d000, f0008000), \
10385 X(_bic, 4380, ea200000), \
10386 X(_bics, 4380, ea300000), \
10387 X(_cmn, 42c0, eb100f00), \
10388 X(_cmp, 2800, ebb00f00), \
10389 X(_cpsie, b660, f3af8400), \
10390 X(_cpsid, b670, f3af8600), \
10391 X(_cpy, 4600, ea4f0000), \
10392 X(_dec_sp,80dd, f1ad0d00), \
10393 X(_eor, 4040, ea800000), \
10394 X(_eors, 4040, ea900000), \
10395 X(_inc_sp,00dd, f10d0d00), \
10396 X(_ldmia, c800, e8900000), \
10397 X(_ldr, 6800, f8500000), \
10398 X(_ldrb, 7800, f8100000), \
10399 X(_ldrh, 8800, f8300000), \
10400 X(_ldrsb, 5600, f9100000), \
10401 X(_ldrsh, 5e00, f9300000), \
10402 X(_ldr_pc,4800, f85f0000), \
10403 X(_ldr_pc2,4800, f85f0000), \
10404 X(_ldr_sp,9800, f85d0000), \
10405 X(_lsl, 0000, fa00f000), \
10406 X(_lsls, 0000, fa10f000), \
10407 X(_lsr, 0800, fa20f000), \
10408 X(_lsrs, 0800, fa30f000), \
10409 X(_mov, 2000, ea4f0000), \
10410 X(_movs, 2000, ea5f0000), \
10411 X(_mul, 4340, fb00f000), \
10412 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10413 X(_mvn, 43c0, ea6f0000), \
10414 X(_mvns, 43c0, ea7f0000), \
10415 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10416 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10417 X(_orr, 4300, ea400000), \
10418 X(_orrs, 4300, ea500000), \
10419 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10420 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10421 X(_rev, ba00, fa90f080), \
10422 X(_rev16, ba40, fa90f090), \
10423 X(_revsh, bac0, fa90f0b0), \
10424 X(_ror, 41c0, fa60f000), \
10425 X(_rors, 41c0, fa70f000), \
10426 X(_sbc, 4180, eb600000), \
10427 X(_sbcs, 4180, eb700000), \
10428 X(_stmia, c000, e8800000), \
10429 X(_str, 6000, f8400000), \
10430 X(_strb, 7000, f8000000), \
10431 X(_strh, 8000, f8200000), \
10432 X(_str_sp,9000, f84d0000), \
10433 X(_sub, 1e00, eba00000), \
10434 X(_subs, 1e00, ebb00000), \
10435 X(_subi, 8000, f1a00000), \
10436 X(_subis, 8000, f1b00000), \
10437 X(_sxtb, b240, fa4ff080), \
10438 X(_sxth, b200, fa0ff080), \
10439 X(_tst, 4200, ea100f00), \
10440 X(_uxtb, b2c0, fa5ff080), \
10441 X(_uxth, b280, fa1ff080), \
10442 X(_nop, bf00, f3af8000), \
10443 X(_yield, bf10, f3af8001), \
10444 X(_wfe, bf20, f3af8002), \
10445 X(_wfi, bf30, f3af8003), \
10446 X(_sev, bf40, f3af8004), \
10447 X(_sevl, bf50, f3af8005), \
10448 X(_udf, de00, f7f0a000)
10450 /* To catch errors in encoding functions, the codes are all offset by
10451 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10452 as 16-bit instructions. */
10453 #define X(a,b,c) T_MNEM##a
10454 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10457 #define X(a,b,c) 0x##b
10458 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10459 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10462 #define X(a,b,c) 0x##c
10463 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10464 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10465 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10469 /* Thumb instruction encoders, in alphabetical order. */
10471 /* ADDW or SUBW. */
10474 do_t_add_sub_w (void)
10478 Rd
= inst
.operands
[0].reg
;
10479 Rn
= inst
.operands
[1].reg
;
10481 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10482 is the SP-{plus,minus}-immediate form of the instruction. */
10484 constraint (Rd
== REG_PC
, BAD_PC
);
10486 reject_bad_reg (Rd
);
10488 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10489 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10492 /* Parse an add or subtract instruction. We get here with inst.instruction
10493 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10496 do_t_add_sub (void)
10500 Rd
= inst
.operands
[0].reg
;
10501 Rs
= (inst
.operands
[1].present
10502 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10503 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10506 set_it_insn_type_last ();
10508 if (unified_syntax
)
10511 bfd_boolean narrow
;
10514 flags
= (inst
.instruction
== T_MNEM_adds
10515 || inst
.instruction
== T_MNEM_subs
);
10517 narrow
= !in_it_block ();
10519 narrow
= in_it_block ();
10520 if (!inst
.operands
[2].isreg
)
10524 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10526 add
= (inst
.instruction
== T_MNEM_add
10527 || inst
.instruction
== T_MNEM_adds
);
10529 if (inst
.size_req
!= 4)
10531 /* Attempt to use a narrow opcode, with relaxation if
10533 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10534 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10535 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10536 opcode
= T_MNEM_add_sp
;
10537 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10538 opcode
= T_MNEM_add_pc
;
10539 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10542 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10544 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10548 inst
.instruction
= THUMB_OP16(opcode
);
10549 inst
.instruction
|= (Rd
<< 4) | Rs
;
10550 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10551 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10553 if (inst
.size_req
== 2)
10554 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10556 inst
.relax
= opcode
;
10560 constraint (inst
.size_req
== 2, BAD_HIREG
);
10562 if (inst
.size_req
== 4
10563 || (inst
.size_req
!= 2 && !opcode
))
10565 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10566 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10567 THUMB1_RELOC_ONLY
);
10570 constraint (add
, BAD_PC
);
10571 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10572 _("only SUBS PC, LR, #const allowed"));
10573 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10574 _("expression too complex"));
10575 constraint (inst
.reloc
.exp
.X_add_number
< 0
10576 || inst
.reloc
.exp
.X_add_number
> 0xff,
10577 _("immediate value out of range"));
10578 inst
.instruction
= T2_SUBS_PC_LR
10579 | inst
.reloc
.exp
.X_add_number
;
10580 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10583 else if (Rs
== REG_PC
)
10585 /* Always use addw/subw. */
10586 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10587 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10591 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10592 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10595 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10597 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10599 inst
.instruction
|= Rd
<< 8;
10600 inst
.instruction
|= Rs
<< 16;
10605 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10606 unsigned int shift
= inst
.operands
[2].shift_kind
;
10608 Rn
= inst
.operands
[2].reg
;
10609 /* See if we can do this with a 16-bit instruction. */
10610 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10612 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10617 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10618 || inst
.instruction
== T_MNEM_add
)
10620 : T_OPCODE_SUB_R3
);
10621 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10625 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10627 /* Thumb-1 cores (except v6-M) require at least one high
10628 register in a narrow non flag setting add. */
10629 if (Rd
> 7 || Rn
> 7
10630 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10631 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10638 inst
.instruction
= T_OPCODE_ADD_HI
;
10639 inst
.instruction
|= (Rd
& 8) << 4;
10640 inst
.instruction
|= (Rd
& 7);
10641 inst
.instruction
|= Rn
<< 3;
10647 constraint (Rd
== REG_PC
, BAD_PC
);
10648 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10649 constraint (Rs
== REG_PC
, BAD_PC
);
10650 reject_bad_reg (Rn
);
10652 /* If we get here, it can't be done in 16 bits. */
10653 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10654 _("shift must be constant"));
10655 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10656 inst
.instruction
|= Rd
<< 8;
10657 inst
.instruction
|= Rs
<< 16;
10658 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10659 _("shift value over 3 not allowed in thumb mode"));
10660 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10661 _("only LSL shift allowed in thumb mode"));
10662 encode_thumb32_shifted_operand (2);
10667 constraint (inst
.instruction
== T_MNEM_adds
10668 || inst
.instruction
== T_MNEM_subs
,
10671 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10673 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10674 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10677 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10678 ? 0x0000 : 0x8000);
10679 inst
.instruction
|= (Rd
<< 4) | Rs
;
10680 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10684 Rn
= inst
.operands
[2].reg
;
10685 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10687 /* We now have Rd, Rs, and Rn set to registers. */
10688 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10690 /* Can't do this for SUB. */
10691 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10692 inst
.instruction
= T_OPCODE_ADD_HI
;
10693 inst
.instruction
|= (Rd
& 8) << 4;
10694 inst
.instruction
|= (Rd
& 7);
10696 inst
.instruction
|= Rn
<< 3;
10698 inst
.instruction
|= Rs
<< 3;
10700 constraint (1, _("dest must overlap one source register"));
10704 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10705 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10706 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10716 Rd
= inst
.operands
[0].reg
;
10717 reject_bad_reg (Rd
);
10719 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10721 /* Defer to section relaxation. */
10722 inst
.relax
= inst
.instruction
;
10723 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10724 inst
.instruction
|= Rd
<< 4;
10726 else if (unified_syntax
&& inst
.size_req
!= 2)
10728 /* Generate a 32-bit opcode. */
10729 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10730 inst
.instruction
|= Rd
<< 8;
10731 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10732 inst
.reloc
.pc_rel
= 1;
10736 /* Generate a 16-bit opcode. */
10737 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10738 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10739 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10740 inst
.reloc
.pc_rel
= 1;
10742 inst
.instruction
|= Rd
<< 4;
10746 /* Arithmetic instructions for which there is just one 16-bit
10747 instruction encoding, and it allows only two low registers.
10748 For maximal compatibility with ARM syntax, we allow three register
10749 operands even when Thumb-32 instructions are not available, as long
10750 as the first two are identical. For instance, both "sbc r0,r1" and
10751 "sbc r0,r0,r1" are allowed. */
10757 Rd
= inst
.operands
[0].reg
;
10758 Rs
= (inst
.operands
[1].present
10759 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10760 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10761 Rn
= inst
.operands
[2].reg
;
10763 reject_bad_reg (Rd
);
10764 reject_bad_reg (Rs
);
10765 if (inst
.operands
[2].isreg
)
10766 reject_bad_reg (Rn
);
10768 if (unified_syntax
)
10770 if (!inst
.operands
[2].isreg
)
10772 /* For an immediate, we always generate a 32-bit opcode;
10773 section relaxation will shrink it later if possible. */
10774 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10775 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10776 inst
.instruction
|= Rd
<< 8;
10777 inst
.instruction
|= Rs
<< 16;
10778 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10782 bfd_boolean narrow
;
10784 /* See if we can do this with a 16-bit instruction. */
10785 if (THUMB_SETS_FLAGS (inst
.instruction
))
10786 narrow
= !in_it_block ();
10788 narrow
= in_it_block ();
10790 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10792 if (inst
.operands
[2].shifted
)
10794 if (inst
.size_req
== 4)
10800 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10801 inst
.instruction
|= Rd
;
10802 inst
.instruction
|= Rn
<< 3;
10806 /* If we get here, it can't be done in 16 bits. */
10807 constraint (inst
.operands
[2].shifted
10808 && inst
.operands
[2].immisreg
,
10809 _("shift must be constant"));
10810 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10811 inst
.instruction
|= Rd
<< 8;
10812 inst
.instruction
|= Rs
<< 16;
10813 encode_thumb32_shifted_operand (2);
10818 /* On its face this is a lie - the instruction does set the
10819 flags. However, the only supported mnemonic in this mode
10820 says it doesn't. */
10821 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10823 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10824 _("unshifted register required"));
10825 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10826 constraint (Rd
!= Rs
,
10827 _("dest and source1 must be the same register"));
10829 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10830 inst
.instruction
|= Rd
;
10831 inst
.instruction
|= Rn
<< 3;
10835 /* Similarly, but for instructions where the arithmetic operation is
10836 commutative, so we can allow either of them to be different from
10837 the destination operand in a 16-bit instruction. For instance, all
10838 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10845 Rd
= inst
.operands
[0].reg
;
10846 Rs
= (inst
.operands
[1].present
10847 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10848 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10849 Rn
= inst
.operands
[2].reg
;
10851 reject_bad_reg (Rd
);
10852 reject_bad_reg (Rs
);
10853 if (inst
.operands
[2].isreg
)
10854 reject_bad_reg (Rn
);
10856 if (unified_syntax
)
10858 if (!inst
.operands
[2].isreg
)
10860 /* For an immediate, we always generate a 32-bit opcode;
10861 section relaxation will shrink it later if possible. */
10862 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10863 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10864 inst
.instruction
|= Rd
<< 8;
10865 inst
.instruction
|= Rs
<< 16;
10866 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10870 bfd_boolean narrow
;
10872 /* See if we can do this with a 16-bit instruction. */
10873 if (THUMB_SETS_FLAGS (inst
.instruction
))
10874 narrow
= !in_it_block ();
10876 narrow
= in_it_block ();
10878 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10880 if (inst
.operands
[2].shifted
)
10882 if (inst
.size_req
== 4)
10889 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10890 inst
.instruction
|= Rd
;
10891 inst
.instruction
|= Rn
<< 3;
10896 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10897 inst
.instruction
|= Rd
;
10898 inst
.instruction
|= Rs
<< 3;
10903 /* If we get here, it can't be done in 16 bits. */
10904 constraint (inst
.operands
[2].shifted
10905 && inst
.operands
[2].immisreg
,
10906 _("shift must be constant"));
10907 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10908 inst
.instruction
|= Rd
<< 8;
10909 inst
.instruction
|= Rs
<< 16;
10910 encode_thumb32_shifted_operand (2);
10915 /* On its face this is a lie - the instruction does set the
10916 flags. However, the only supported mnemonic in this mode
10917 says it doesn't. */
10918 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10920 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10921 _("unshifted register required"));
10922 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10924 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10925 inst
.instruction
|= Rd
;
10928 inst
.instruction
|= Rn
<< 3;
10930 inst
.instruction
|= Rs
<< 3;
10932 constraint (1, _("dest must overlap one source register"));
10940 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10941 constraint (msb
> 32, _("bit-field extends past end of register"));
10942 /* The instruction encoding stores the LSB and MSB,
10943 not the LSB and width. */
10944 Rd
= inst
.operands
[0].reg
;
10945 reject_bad_reg (Rd
);
10946 inst
.instruction
|= Rd
<< 8;
10947 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10948 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10949 inst
.instruction
|= msb
- 1;
10958 Rd
= inst
.operands
[0].reg
;
10959 reject_bad_reg (Rd
);
10961 /* #0 in second position is alternative syntax for bfc, which is
10962 the same instruction but with REG_PC in the Rm field. */
10963 if (!inst
.operands
[1].isreg
)
10967 Rn
= inst
.operands
[1].reg
;
10968 reject_bad_reg (Rn
);
10971 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10972 constraint (msb
> 32, _("bit-field extends past end of register"));
10973 /* The instruction encoding stores the LSB and MSB,
10974 not the LSB and width. */
10975 inst
.instruction
|= Rd
<< 8;
10976 inst
.instruction
|= Rn
<< 16;
10977 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10978 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10979 inst
.instruction
|= msb
- 1;
10987 Rd
= inst
.operands
[0].reg
;
10988 Rn
= inst
.operands
[1].reg
;
10990 reject_bad_reg (Rd
);
10991 reject_bad_reg (Rn
);
10993 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10994 _("bit-field extends past end of register"));
10995 inst
.instruction
|= Rd
<< 8;
10996 inst
.instruction
|= Rn
<< 16;
10997 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10998 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10999 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11002 /* ARM V5 Thumb BLX (argument parse)
11003 BLX <target_addr> which is BLX(1)
11004 BLX <Rm> which is BLX(2)
11005 Unfortunately, there are two different opcodes for this mnemonic.
11006 So, the insns[].value is not used, and the code here zaps values
11007 into inst.instruction.
11009 ??? How to take advantage of the additional two bits of displacement
11010 available in Thumb32 mode? Need new relocation? */
11015 set_it_insn_type_last ();
11017 if (inst
.operands
[0].isreg
)
11019 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11020 /* We have a register, so this is BLX(2). */
11021 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11025 /* No register. This must be BLX(1). */
11026 inst
.instruction
= 0xf000e800;
11027 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11036 bfd_reloc_code_real_type reloc
;
11039 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11041 if (in_it_block ())
11043 /* Conditional branches inside IT blocks are encoded as unconditional
11045 cond
= COND_ALWAYS
;
11050 if (cond
!= COND_ALWAYS
)
11051 opcode
= T_MNEM_bcond
;
11053 opcode
= inst
.instruction
;
11056 && (inst
.size_req
== 4
11057 || (inst
.size_req
!= 2
11058 && (inst
.operands
[0].hasreloc
11059 || inst
.reloc
.exp
.X_op
== O_constant
))))
11061 inst
.instruction
= THUMB_OP32(opcode
);
11062 if (cond
== COND_ALWAYS
)
11063 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11066 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11067 _("selected architecture does not support "
11068 "wide conditional branch instruction"));
11070 gas_assert (cond
!= 0xF);
11071 inst
.instruction
|= cond
<< 22;
11072 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11077 inst
.instruction
= THUMB_OP16(opcode
);
11078 if (cond
== COND_ALWAYS
)
11079 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11082 inst
.instruction
|= cond
<< 8;
11083 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11085 /* Allow section relaxation. */
11086 if (unified_syntax
&& inst
.size_req
!= 2)
11087 inst
.relax
= opcode
;
11089 inst
.reloc
.type
= reloc
;
11090 inst
.reloc
.pc_rel
= 1;
11093 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11094 between the two is the maximum immediate allowed - which is passed in
11097 do_t_bkpt_hlt1 (int range
)
11099 constraint (inst
.cond
!= COND_ALWAYS
,
11100 _("instruction is always unconditional"));
11101 if (inst
.operands
[0].present
)
11103 constraint (inst
.operands
[0].imm
> range
,
11104 _("immediate value out of range"));
11105 inst
.instruction
|= inst
.operands
[0].imm
;
11108 set_it_insn_type (NEUTRAL_IT_INSN
);
11114 do_t_bkpt_hlt1 (63);
11120 do_t_bkpt_hlt1 (255);
11124 do_t_branch23 (void)
11126 set_it_insn_type_last ();
11127 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11129 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11130 this file. We used to simply ignore the PLT reloc type here --
11131 the branch encoding is now needed to deal with TLSCALL relocs.
11132 So if we see a PLT reloc now, put it back to how it used to be to
11133 keep the preexisting behaviour. */
11134 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11135 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11137 #if defined(OBJ_COFF)
11138 /* If the destination of the branch is a defined symbol which does not have
11139 the THUMB_FUNC attribute, then we must be calling a function which has
11140 the (interfacearm) attribute. We look for the Thumb entry point to that
11141 function and change the branch to refer to that function instead. */
11142 if ( inst
.reloc
.exp
.X_op
== O_symbol
11143 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11144 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11145 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11146 inst
.reloc
.exp
.X_add_symbol
=
11147 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11154 set_it_insn_type_last ();
11155 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11156 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11157 should cause the alignment to be checked once it is known. This is
11158 because BX PC only works if the instruction is word aligned. */
11166 set_it_insn_type_last ();
11167 Rm
= inst
.operands
[0].reg
;
11168 reject_bad_reg (Rm
);
11169 inst
.instruction
|= Rm
<< 16;
11178 Rd
= inst
.operands
[0].reg
;
11179 Rm
= inst
.operands
[1].reg
;
11181 reject_bad_reg (Rd
);
11182 reject_bad_reg (Rm
);
11184 inst
.instruction
|= Rd
<< 8;
11185 inst
.instruction
|= Rm
<< 16;
11186 inst
.instruction
|= Rm
;
11192 set_it_insn_type (OUTSIDE_IT_INSN
);
11193 inst
.instruction
|= inst
.operands
[0].imm
;
11199 set_it_insn_type (OUTSIDE_IT_INSN
);
11201 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11202 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11204 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11205 inst
.instruction
= 0xf3af8000;
11206 inst
.instruction
|= imod
<< 9;
11207 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11208 if (inst
.operands
[1].present
)
11209 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11213 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11214 && (inst
.operands
[0].imm
& 4),
11215 _("selected processor does not support 'A' form "
11216 "of this instruction"));
11217 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11218 _("Thumb does not support the 2-argument "
11219 "form of this instruction"));
11220 inst
.instruction
|= inst
.operands
[0].imm
;
11224 /* THUMB CPY instruction (argument parse). */
11229 if (inst
.size_req
== 4)
11231 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11232 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11233 inst
.instruction
|= inst
.operands
[1].reg
;
11237 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11238 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11239 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11246 set_it_insn_type (OUTSIDE_IT_INSN
);
11247 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11248 inst
.instruction
|= inst
.operands
[0].reg
;
11249 inst
.reloc
.pc_rel
= 1;
11250 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11256 inst
.instruction
|= inst
.operands
[0].imm
;
11262 unsigned Rd
, Rn
, Rm
;
11264 Rd
= inst
.operands
[0].reg
;
11265 Rn
= (inst
.operands
[1].present
11266 ? inst
.operands
[1].reg
: Rd
);
11267 Rm
= inst
.operands
[2].reg
;
11269 reject_bad_reg (Rd
);
11270 reject_bad_reg (Rn
);
11271 reject_bad_reg (Rm
);
11273 inst
.instruction
|= Rd
<< 8;
11274 inst
.instruction
|= Rn
<< 16;
11275 inst
.instruction
|= Rm
;
11281 if (unified_syntax
&& inst
.size_req
== 4)
11282 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11284 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11290 unsigned int cond
= inst
.operands
[0].imm
;
11292 set_it_insn_type (IT_INSN
);
11293 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11295 now_it
.warn_deprecated
= FALSE
;
11297 /* If the condition is a negative condition, invert the mask. */
11298 if ((cond
& 0x1) == 0x0)
11300 unsigned int mask
= inst
.instruction
& 0x000f;
11302 if ((mask
& 0x7) == 0)
11304 /* No conversion needed. */
11305 now_it
.block_length
= 1;
11307 else if ((mask
& 0x3) == 0)
11310 now_it
.block_length
= 2;
11312 else if ((mask
& 0x1) == 0)
11315 now_it
.block_length
= 3;
11320 now_it
.block_length
= 4;
11323 inst
.instruction
&= 0xfff0;
11324 inst
.instruction
|= mask
;
11327 inst
.instruction
|= cond
<< 4;
11330 /* Helper function used for both push/pop and ldm/stm. */
11332 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11336 load
= (inst
.instruction
& (1 << 20)) != 0;
11338 if (mask
& (1 << 13))
11339 inst
.error
= _("SP not allowed in register list");
11341 if ((mask
& (1 << base
)) != 0
11343 inst
.error
= _("having the base register in the register list when "
11344 "using write back is UNPREDICTABLE");
11348 if (mask
& (1 << 15))
11350 if (mask
& (1 << 14))
11351 inst
.error
= _("LR and PC should not both be in register list");
11353 set_it_insn_type_last ();
11358 if (mask
& (1 << 15))
11359 inst
.error
= _("PC not allowed in register list");
11362 if ((mask
& (mask
- 1)) == 0)
11364 /* Single register transfers implemented as str/ldr. */
11367 if (inst
.instruction
& (1 << 23))
11368 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11370 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11374 if (inst
.instruction
& (1 << 23))
11375 inst
.instruction
= 0x00800000; /* ia -> [base] */
11377 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11380 inst
.instruction
|= 0xf8400000;
11382 inst
.instruction
|= 0x00100000;
11384 mask
= ffs (mask
) - 1;
11387 else if (writeback
)
11388 inst
.instruction
|= WRITE_BACK
;
11390 inst
.instruction
|= mask
;
11391 inst
.instruction
|= base
<< 16;
11397 /* This really doesn't seem worth it. */
11398 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11399 _("expression too complex"));
11400 constraint (inst
.operands
[1].writeback
,
11401 _("Thumb load/store multiple does not support {reglist}^"));
11403 if (unified_syntax
)
11405 bfd_boolean narrow
;
11409 /* See if we can use a 16-bit instruction. */
11410 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11411 && inst
.size_req
!= 4
11412 && !(inst
.operands
[1].imm
& ~0xff))
11414 mask
= 1 << inst
.operands
[0].reg
;
11416 if (inst
.operands
[0].reg
<= 7)
11418 if (inst
.instruction
== T_MNEM_stmia
11419 ? inst
.operands
[0].writeback
11420 : (inst
.operands
[0].writeback
11421 == !(inst
.operands
[1].imm
& mask
)))
11423 if (inst
.instruction
== T_MNEM_stmia
11424 && (inst
.operands
[1].imm
& mask
)
11425 && (inst
.operands
[1].imm
& (mask
- 1)))
11426 as_warn (_("value stored for r%d is UNKNOWN"),
11427 inst
.operands
[0].reg
);
11429 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11430 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11431 inst
.instruction
|= inst
.operands
[1].imm
;
11434 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11436 /* This means 1 register in reg list one of 3 situations:
11437 1. Instruction is stmia, but without writeback.
11438 2. lmdia without writeback, but with Rn not in
11440 3. ldmia with writeback, but with Rn in reglist.
11441 Case 3 is UNPREDICTABLE behaviour, so we handle
11442 case 1 and 2 which can be converted into a 16-bit
11443 str or ldr. The SP cases are handled below. */
11444 unsigned long opcode
;
11445 /* First, record an error for Case 3. */
11446 if (inst
.operands
[1].imm
& mask
11447 && inst
.operands
[0].writeback
)
11449 _("having the base register in the register list when "
11450 "using write back is UNPREDICTABLE");
11452 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11454 inst
.instruction
= THUMB_OP16 (opcode
);
11455 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11456 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11460 else if (inst
.operands
[0] .reg
== REG_SP
)
11462 if (inst
.operands
[0].writeback
)
11465 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11466 ? T_MNEM_push
: T_MNEM_pop
);
11467 inst
.instruction
|= inst
.operands
[1].imm
;
11470 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11473 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11474 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11475 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11483 if (inst
.instruction
< 0xffff)
11484 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11486 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11487 inst
.operands
[0].writeback
);
11492 constraint (inst
.operands
[0].reg
> 7
11493 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11494 constraint (inst
.instruction
!= T_MNEM_ldmia
11495 && inst
.instruction
!= T_MNEM_stmia
,
11496 _("Thumb-2 instruction only valid in unified syntax"));
11497 if (inst
.instruction
== T_MNEM_stmia
)
11499 if (!inst
.operands
[0].writeback
)
11500 as_warn (_("this instruction will write back the base register"));
11501 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11502 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11503 as_warn (_("value stored for r%d is UNKNOWN"),
11504 inst
.operands
[0].reg
);
11508 if (!inst
.operands
[0].writeback
11509 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11510 as_warn (_("this instruction will write back the base register"));
11511 else if (inst
.operands
[0].writeback
11512 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11513 as_warn (_("this instruction will not write back the base register"));
11516 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11517 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11518 inst
.instruction
|= inst
.operands
[1].imm
;
11525 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11526 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11527 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11528 || inst
.operands
[1].negative
,
11531 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11533 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11534 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11535 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11541 if (!inst
.operands
[1].present
)
11543 constraint (inst
.operands
[0].reg
== REG_LR
,
11544 _("r14 not allowed as first register "
11545 "when second register is omitted"));
11546 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11548 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11551 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11552 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11553 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11559 unsigned long opcode
;
11562 if (inst
.operands
[0].isreg
11563 && !inst
.operands
[0].preind
11564 && inst
.operands
[0].reg
== REG_PC
)
11565 set_it_insn_type_last ();
11567 opcode
= inst
.instruction
;
11568 if (unified_syntax
)
11570 if (!inst
.operands
[1].isreg
)
11572 if (opcode
<= 0xffff)
11573 inst
.instruction
= THUMB_OP32 (opcode
);
11574 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11577 if (inst
.operands
[1].isreg
11578 && !inst
.operands
[1].writeback
11579 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11580 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11581 && opcode
<= 0xffff
11582 && inst
.size_req
!= 4)
11584 /* Insn may have a 16-bit form. */
11585 Rn
= inst
.operands
[1].reg
;
11586 if (inst
.operands
[1].immisreg
)
11588 inst
.instruction
= THUMB_OP16 (opcode
);
11590 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11592 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11593 reject_bad_reg (inst
.operands
[1].imm
);
11595 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11596 && opcode
!= T_MNEM_ldrsb
)
11597 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11598 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11605 if (inst
.reloc
.pc_rel
)
11606 opcode
= T_MNEM_ldr_pc2
;
11608 opcode
= T_MNEM_ldr_pc
;
11612 if (opcode
== T_MNEM_ldr
)
11613 opcode
= T_MNEM_ldr_sp
;
11615 opcode
= T_MNEM_str_sp
;
11617 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11621 inst
.instruction
= inst
.operands
[0].reg
;
11622 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11624 inst
.instruction
|= THUMB_OP16 (opcode
);
11625 if (inst
.size_req
== 2)
11626 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11628 inst
.relax
= opcode
;
11632 /* Definitely a 32-bit variant. */
11634 /* Warning for Erratum 752419. */
11635 if (opcode
== T_MNEM_ldr
11636 && inst
.operands
[0].reg
== REG_SP
11637 && inst
.operands
[1].writeback
== 1
11638 && !inst
.operands
[1].immisreg
)
11640 if (no_cpu_selected ()
11641 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11642 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11643 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11644 as_warn (_("This instruction may be unpredictable "
11645 "if executed on M-profile cores "
11646 "with interrupts enabled."));
11649 /* Do some validations regarding addressing modes. */
11650 if (inst
.operands
[1].immisreg
)
11651 reject_bad_reg (inst
.operands
[1].imm
);
11653 constraint (inst
.operands
[1].writeback
== 1
11654 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11657 inst
.instruction
= THUMB_OP32 (opcode
);
11658 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11659 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11660 check_ldr_r15_aligned ();
11664 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11666 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11668 /* Only [Rn,Rm] is acceptable. */
11669 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11670 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11671 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11672 || inst
.operands
[1].negative
,
11673 _("Thumb does not support this addressing mode"));
11674 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11678 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11679 if (!inst
.operands
[1].isreg
)
11680 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11683 constraint (!inst
.operands
[1].preind
11684 || inst
.operands
[1].shifted
11685 || inst
.operands
[1].writeback
,
11686 _("Thumb does not support this addressing mode"));
11687 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11689 constraint (inst
.instruction
& 0x0600,
11690 _("byte or halfword not valid for base register"));
11691 constraint (inst
.operands
[1].reg
== REG_PC
11692 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11693 _("r15 based store not allowed"));
11694 constraint (inst
.operands
[1].immisreg
,
11695 _("invalid base register for register offset"));
11697 if (inst
.operands
[1].reg
== REG_PC
)
11698 inst
.instruction
= T_OPCODE_LDR_PC
;
11699 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11700 inst
.instruction
= T_OPCODE_LDR_SP
;
11702 inst
.instruction
= T_OPCODE_STR_SP
;
11704 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11705 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11709 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11710 if (!inst
.operands
[1].immisreg
)
11712 /* Immediate offset. */
11713 inst
.instruction
|= inst
.operands
[0].reg
;
11714 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11715 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11719 /* Register offset. */
11720 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11721 constraint (inst
.operands
[1].negative
,
11722 _("Thumb does not support this addressing mode"));
11725 switch (inst
.instruction
)
11727 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11728 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11729 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11730 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11731 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11732 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11733 case 0x5600 /* ldrsb */:
11734 case 0x5e00 /* ldrsh */: break;
11738 inst
.instruction
|= inst
.operands
[0].reg
;
11739 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11740 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11746 if (!inst
.operands
[1].present
)
11748 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11749 constraint (inst
.operands
[0].reg
== REG_LR
,
11750 _("r14 not allowed here"));
11751 constraint (inst
.operands
[0].reg
== REG_R12
,
11752 _("r12 not allowed here"));
11755 if (inst
.operands
[2].writeback
11756 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11757 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11758 as_warn (_("base register written back, and overlaps "
11759 "one of transfer registers"));
11761 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11762 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11763 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11769 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11770 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11776 unsigned Rd
, Rn
, Rm
, Ra
;
11778 Rd
= inst
.operands
[0].reg
;
11779 Rn
= inst
.operands
[1].reg
;
11780 Rm
= inst
.operands
[2].reg
;
11781 Ra
= inst
.operands
[3].reg
;
11783 reject_bad_reg (Rd
);
11784 reject_bad_reg (Rn
);
11785 reject_bad_reg (Rm
);
11786 reject_bad_reg (Ra
);
11788 inst
.instruction
|= Rd
<< 8;
11789 inst
.instruction
|= Rn
<< 16;
11790 inst
.instruction
|= Rm
;
11791 inst
.instruction
|= Ra
<< 12;
11797 unsigned RdLo
, RdHi
, Rn
, Rm
;
11799 RdLo
= inst
.operands
[0].reg
;
11800 RdHi
= inst
.operands
[1].reg
;
11801 Rn
= inst
.operands
[2].reg
;
11802 Rm
= inst
.operands
[3].reg
;
11804 reject_bad_reg (RdLo
);
11805 reject_bad_reg (RdHi
);
11806 reject_bad_reg (Rn
);
11807 reject_bad_reg (Rm
);
11809 inst
.instruction
|= RdLo
<< 12;
11810 inst
.instruction
|= RdHi
<< 8;
11811 inst
.instruction
|= Rn
<< 16;
11812 inst
.instruction
|= Rm
;
11816 do_t_mov_cmp (void)
11820 Rn
= inst
.operands
[0].reg
;
11821 Rm
= inst
.operands
[1].reg
;
11824 set_it_insn_type_last ();
11826 if (unified_syntax
)
11828 int r0off
= (inst
.instruction
== T_MNEM_mov
11829 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11830 unsigned long opcode
;
11831 bfd_boolean narrow
;
11832 bfd_boolean low_regs
;
11834 low_regs
= (Rn
<= 7 && Rm
<= 7);
11835 opcode
= inst
.instruction
;
11836 if (in_it_block ())
11837 narrow
= opcode
!= T_MNEM_movs
;
11839 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11840 if (inst
.size_req
== 4
11841 || inst
.operands
[1].shifted
)
11844 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11845 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11846 && !inst
.operands
[1].shifted
11850 inst
.instruction
= T2_SUBS_PC_LR
;
11854 if (opcode
== T_MNEM_cmp
)
11856 constraint (Rn
== REG_PC
, BAD_PC
);
11859 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11861 warn_deprecated_sp (Rm
);
11862 /* R15 was documented as a valid choice for Rm in ARMv6,
11863 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11864 tools reject R15, so we do too. */
11865 constraint (Rm
== REG_PC
, BAD_PC
);
11868 reject_bad_reg (Rm
);
11870 else if (opcode
== T_MNEM_mov
11871 || opcode
== T_MNEM_movs
)
11873 if (inst
.operands
[1].isreg
)
11875 if (opcode
== T_MNEM_movs
)
11877 reject_bad_reg (Rn
);
11878 reject_bad_reg (Rm
);
11882 /* This is mov.n. */
11883 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11884 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11886 as_tsktsk (_("Use of r%u as a source register is "
11887 "deprecated when r%u is the destination "
11888 "register."), Rm
, Rn
);
11893 /* This is mov.w. */
11894 constraint (Rn
== REG_PC
, BAD_PC
);
11895 constraint (Rm
== REG_PC
, BAD_PC
);
11896 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11900 reject_bad_reg (Rn
);
11903 if (!inst
.operands
[1].isreg
)
11905 /* Immediate operand. */
11906 if (!in_it_block () && opcode
== T_MNEM_mov
)
11908 if (low_regs
&& narrow
)
11910 inst
.instruction
= THUMB_OP16 (opcode
);
11911 inst
.instruction
|= Rn
<< 8;
11912 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11913 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11915 if (inst
.size_req
== 2)
11916 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11918 inst
.relax
= opcode
;
11923 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11924 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11925 THUMB1_RELOC_ONLY
);
11927 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11928 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11929 inst
.instruction
|= Rn
<< r0off
;
11930 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11933 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11934 && (inst
.instruction
== T_MNEM_mov
11935 || inst
.instruction
== T_MNEM_movs
))
11937 /* Register shifts are encoded as separate shift instructions. */
11938 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11940 if (in_it_block ())
11945 if (inst
.size_req
== 4)
11948 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11954 switch (inst
.operands
[1].shift_kind
)
11957 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11960 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11963 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11966 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11972 inst
.instruction
= opcode
;
11975 inst
.instruction
|= Rn
;
11976 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11981 inst
.instruction
|= CONDS_BIT
;
11983 inst
.instruction
|= Rn
<< 8;
11984 inst
.instruction
|= Rm
<< 16;
11985 inst
.instruction
|= inst
.operands
[1].imm
;
11990 /* Some mov with immediate shift have narrow variants.
11991 Register shifts are handled above. */
11992 if (low_regs
&& inst
.operands
[1].shifted
11993 && (inst
.instruction
== T_MNEM_mov
11994 || inst
.instruction
== T_MNEM_movs
))
11996 if (in_it_block ())
11997 narrow
= (inst
.instruction
== T_MNEM_mov
);
11999 narrow
= (inst
.instruction
== T_MNEM_movs
);
12004 switch (inst
.operands
[1].shift_kind
)
12006 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12007 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12008 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12009 default: narrow
= FALSE
; break;
12015 inst
.instruction
|= Rn
;
12016 inst
.instruction
|= Rm
<< 3;
12017 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12021 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12022 inst
.instruction
|= Rn
<< r0off
;
12023 encode_thumb32_shifted_operand (1);
12027 switch (inst
.instruction
)
12030 /* In v4t or v5t a move of two lowregs produces unpredictable
12031 results. Don't allow this. */
12034 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12035 "MOV Rd, Rs with two low registers is not "
12036 "permitted on this architecture");
12037 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12041 inst
.instruction
= T_OPCODE_MOV_HR
;
12042 inst
.instruction
|= (Rn
& 0x8) << 4;
12043 inst
.instruction
|= (Rn
& 0x7);
12044 inst
.instruction
|= Rm
<< 3;
12048 /* We know we have low registers at this point.
12049 Generate LSLS Rd, Rs, #0. */
12050 inst
.instruction
= T_OPCODE_LSL_I
;
12051 inst
.instruction
|= Rn
;
12052 inst
.instruction
|= Rm
<< 3;
12058 inst
.instruction
= T_OPCODE_CMP_LR
;
12059 inst
.instruction
|= Rn
;
12060 inst
.instruction
|= Rm
<< 3;
12064 inst
.instruction
= T_OPCODE_CMP_HR
;
12065 inst
.instruction
|= (Rn
& 0x8) << 4;
12066 inst
.instruction
|= (Rn
& 0x7);
12067 inst
.instruction
|= Rm
<< 3;
12074 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12076 /* PR 10443: Do not silently ignore shifted operands. */
12077 constraint (inst
.operands
[1].shifted
,
12078 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12080 if (inst
.operands
[1].isreg
)
12082 if (Rn
< 8 && Rm
< 8)
12084 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12085 since a MOV instruction produces unpredictable results. */
12086 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12087 inst
.instruction
= T_OPCODE_ADD_I3
;
12089 inst
.instruction
= T_OPCODE_CMP_LR
;
12091 inst
.instruction
|= Rn
;
12092 inst
.instruction
|= Rm
<< 3;
12096 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12097 inst
.instruction
= T_OPCODE_MOV_HR
;
12099 inst
.instruction
= T_OPCODE_CMP_HR
;
12105 constraint (Rn
> 7,
12106 _("only lo regs allowed with immediate"));
12107 inst
.instruction
|= Rn
<< 8;
12108 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12119 top
= (inst
.instruction
& 0x00800000) != 0;
12120 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12122 constraint (top
, _(":lower16: not allowed in this instruction"));
12123 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12125 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12127 constraint (!top
, _(":upper16: not allowed in this instruction"));
12128 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12131 Rd
= inst
.operands
[0].reg
;
12132 reject_bad_reg (Rd
);
12134 inst
.instruction
|= Rd
<< 8;
12135 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12137 imm
= inst
.reloc
.exp
.X_add_number
;
12138 inst
.instruction
|= (imm
& 0xf000) << 4;
12139 inst
.instruction
|= (imm
& 0x0800) << 15;
12140 inst
.instruction
|= (imm
& 0x0700) << 4;
12141 inst
.instruction
|= (imm
& 0x00ff);
12146 do_t_mvn_tst (void)
12150 Rn
= inst
.operands
[0].reg
;
12151 Rm
= inst
.operands
[1].reg
;
12153 if (inst
.instruction
== T_MNEM_cmp
12154 || inst
.instruction
== T_MNEM_cmn
)
12155 constraint (Rn
== REG_PC
, BAD_PC
);
12157 reject_bad_reg (Rn
);
12158 reject_bad_reg (Rm
);
12160 if (unified_syntax
)
12162 int r0off
= (inst
.instruction
== T_MNEM_mvn
12163 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12164 bfd_boolean narrow
;
12166 if (inst
.size_req
== 4
12167 || inst
.instruction
> 0xffff
12168 || inst
.operands
[1].shifted
12169 || Rn
> 7 || Rm
> 7)
12171 else if (inst
.instruction
== T_MNEM_cmn
12172 || inst
.instruction
== T_MNEM_tst
)
12174 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12175 narrow
= !in_it_block ();
12177 narrow
= in_it_block ();
12179 if (!inst
.operands
[1].isreg
)
12181 /* For an immediate, we always generate a 32-bit opcode;
12182 section relaxation will shrink it later if possible. */
12183 if (inst
.instruction
< 0xffff)
12184 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12185 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12186 inst
.instruction
|= Rn
<< r0off
;
12187 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12191 /* See if we can do this with a 16-bit instruction. */
12194 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12195 inst
.instruction
|= Rn
;
12196 inst
.instruction
|= Rm
<< 3;
12200 constraint (inst
.operands
[1].shifted
12201 && inst
.operands
[1].immisreg
,
12202 _("shift must be constant"));
12203 if (inst
.instruction
< 0xffff)
12204 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12205 inst
.instruction
|= Rn
<< r0off
;
12206 encode_thumb32_shifted_operand (1);
12212 constraint (inst
.instruction
> 0xffff
12213 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12214 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12215 _("unshifted register required"));
12216 constraint (Rn
> 7 || Rm
> 7,
12219 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12220 inst
.instruction
|= Rn
;
12221 inst
.instruction
|= Rm
<< 3;
12230 if (do_vfp_nsyn_mrs () == SUCCESS
)
12233 Rd
= inst
.operands
[0].reg
;
12234 reject_bad_reg (Rd
);
12235 inst
.instruction
|= Rd
<< 8;
12237 if (inst
.operands
[1].isreg
)
12239 unsigned br
= inst
.operands
[1].reg
;
12240 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12241 as_bad (_("bad register for mrs"));
12243 inst
.instruction
|= br
& (0xf << 16);
12244 inst
.instruction
|= (br
& 0x300) >> 4;
12245 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12249 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12251 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12253 /* PR gas/12698: The constraint is only applied for m_profile.
12254 If the user has specified -march=all, we want to ignore it as
12255 we are building for any CPU type, including non-m variants. */
12256 bfd_boolean m_profile
=
12257 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12258 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12259 "not support requested special purpose register"));
12262 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12264 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12265 _("'APSR', 'CPSR' or 'SPSR' expected"));
12267 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12268 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12269 inst
.instruction
|= 0xf0000;
12279 if (do_vfp_nsyn_msr () == SUCCESS
)
12282 constraint (!inst
.operands
[1].isreg
,
12283 _("Thumb encoding does not support an immediate here"));
12285 if (inst
.operands
[0].isreg
)
12286 flags
= (int)(inst
.operands
[0].reg
);
12288 flags
= inst
.operands
[0].imm
;
12290 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12292 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12294 /* PR gas/12698: The constraint is only applied for m_profile.
12295 If the user has specified -march=all, we want to ignore it as
12296 we are building for any CPU type, including non-m variants. */
12297 bfd_boolean m_profile
=
12298 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12299 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12300 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12301 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12302 && bits
!= PSR_f
)) && m_profile
,
12303 _("selected processor does not support requested special "
12304 "purpose register"));
12307 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12308 "requested special purpose register"));
12310 Rn
= inst
.operands
[1].reg
;
12311 reject_bad_reg (Rn
);
12313 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12314 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12315 inst
.instruction
|= (flags
& 0x300) >> 4;
12316 inst
.instruction
|= (flags
& 0xff);
12317 inst
.instruction
|= Rn
<< 16;
12323 bfd_boolean narrow
;
12324 unsigned Rd
, Rn
, Rm
;
12326 if (!inst
.operands
[2].present
)
12327 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12329 Rd
= inst
.operands
[0].reg
;
12330 Rn
= inst
.operands
[1].reg
;
12331 Rm
= inst
.operands
[2].reg
;
12333 if (unified_syntax
)
12335 if (inst
.size_req
== 4
12341 else if (inst
.instruction
== T_MNEM_muls
)
12342 narrow
= !in_it_block ();
12344 narrow
= in_it_block ();
12348 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12349 constraint (Rn
> 7 || Rm
> 7,
12356 /* 16-bit MULS/Conditional MUL. */
12357 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12358 inst
.instruction
|= Rd
;
12361 inst
.instruction
|= Rm
<< 3;
12363 inst
.instruction
|= Rn
<< 3;
12365 constraint (1, _("dest must overlap one source register"));
12369 constraint (inst
.instruction
!= T_MNEM_mul
,
12370 _("Thumb-2 MUL must not set flags"));
12372 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12373 inst
.instruction
|= Rd
<< 8;
12374 inst
.instruction
|= Rn
<< 16;
12375 inst
.instruction
|= Rm
<< 0;
12377 reject_bad_reg (Rd
);
12378 reject_bad_reg (Rn
);
12379 reject_bad_reg (Rm
);
12386 unsigned RdLo
, RdHi
, Rn
, Rm
;
12388 RdLo
= inst
.operands
[0].reg
;
12389 RdHi
= inst
.operands
[1].reg
;
12390 Rn
= inst
.operands
[2].reg
;
12391 Rm
= inst
.operands
[3].reg
;
12393 reject_bad_reg (RdLo
);
12394 reject_bad_reg (RdHi
);
12395 reject_bad_reg (Rn
);
12396 reject_bad_reg (Rm
);
12398 inst
.instruction
|= RdLo
<< 12;
12399 inst
.instruction
|= RdHi
<< 8;
12400 inst
.instruction
|= Rn
<< 16;
12401 inst
.instruction
|= Rm
;
12404 as_tsktsk (_("rdhi and rdlo must be different"));
12410 set_it_insn_type (NEUTRAL_IT_INSN
);
12412 if (unified_syntax
)
12414 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12416 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12417 inst
.instruction
|= inst
.operands
[0].imm
;
12421 /* PR9722: Check for Thumb2 availability before
12422 generating a thumb2 nop instruction. */
12423 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12425 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12426 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12429 inst
.instruction
= 0x46c0;
12434 constraint (inst
.operands
[0].present
,
12435 _("Thumb does not support NOP with hints"));
12436 inst
.instruction
= 0x46c0;
12443 if (unified_syntax
)
12445 bfd_boolean narrow
;
12447 if (THUMB_SETS_FLAGS (inst
.instruction
))
12448 narrow
= !in_it_block ();
12450 narrow
= in_it_block ();
12451 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12453 if (inst
.size_req
== 4)
12458 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12459 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12460 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12464 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12465 inst
.instruction
|= inst
.operands
[0].reg
;
12466 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12471 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12473 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12475 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12476 inst
.instruction
|= inst
.operands
[0].reg
;
12477 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12486 Rd
= inst
.operands
[0].reg
;
12487 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12489 reject_bad_reg (Rd
);
12490 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12491 reject_bad_reg (Rn
);
12493 inst
.instruction
|= Rd
<< 8;
12494 inst
.instruction
|= Rn
<< 16;
12496 if (!inst
.operands
[2].isreg
)
12498 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12499 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12505 Rm
= inst
.operands
[2].reg
;
12506 reject_bad_reg (Rm
);
12508 constraint (inst
.operands
[2].shifted
12509 && inst
.operands
[2].immisreg
,
12510 _("shift must be constant"));
12511 encode_thumb32_shifted_operand (2);
12518 unsigned Rd
, Rn
, Rm
;
12520 Rd
= inst
.operands
[0].reg
;
12521 Rn
= inst
.operands
[1].reg
;
12522 Rm
= inst
.operands
[2].reg
;
12524 reject_bad_reg (Rd
);
12525 reject_bad_reg (Rn
);
12526 reject_bad_reg (Rm
);
12528 inst
.instruction
|= Rd
<< 8;
12529 inst
.instruction
|= Rn
<< 16;
12530 inst
.instruction
|= Rm
;
12531 if (inst
.operands
[3].present
)
12533 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12534 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12535 _("expression too complex"));
12536 inst
.instruction
|= (val
& 0x1c) << 10;
12537 inst
.instruction
|= (val
& 0x03) << 6;
12544 if (!inst
.operands
[3].present
)
12548 inst
.instruction
&= ~0x00000020;
12550 /* PR 10168. Swap the Rm and Rn registers. */
12551 Rtmp
= inst
.operands
[1].reg
;
12552 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12553 inst
.operands
[2].reg
= Rtmp
;
12561 if (inst
.operands
[0].immisreg
)
12562 reject_bad_reg (inst
.operands
[0].imm
);
12564 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12568 do_t_push_pop (void)
12572 constraint (inst
.operands
[0].writeback
,
12573 _("push/pop do not support {reglist}^"));
12574 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12575 _("expression too complex"));
12577 mask
= inst
.operands
[0].imm
;
12578 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12579 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12580 else if (inst
.size_req
!= 4
12581 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12582 ? REG_LR
: REG_PC
)))
12584 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12585 inst
.instruction
|= THUMB_PP_PC_LR
;
12586 inst
.instruction
|= mask
& 0xff;
12588 else if (unified_syntax
)
12590 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12591 encode_thumb2_ldmstm (13, mask
, TRUE
);
12595 inst
.error
= _("invalid register list to push/pop instruction");
12605 Rd
= inst
.operands
[0].reg
;
12606 Rm
= inst
.operands
[1].reg
;
12608 reject_bad_reg (Rd
);
12609 reject_bad_reg (Rm
);
12611 inst
.instruction
|= Rd
<< 8;
12612 inst
.instruction
|= Rm
<< 16;
12613 inst
.instruction
|= Rm
;
12621 Rd
= inst
.operands
[0].reg
;
12622 Rm
= inst
.operands
[1].reg
;
12624 reject_bad_reg (Rd
);
12625 reject_bad_reg (Rm
);
12627 if (Rd
<= 7 && Rm
<= 7
12628 && inst
.size_req
!= 4)
12630 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12631 inst
.instruction
|= Rd
;
12632 inst
.instruction
|= Rm
<< 3;
12634 else if (unified_syntax
)
12636 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12637 inst
.instruction
|= Rd
<< 8;
12638 inst
.instruction
|= Rm
<< 16;
12639 inst
.instruction
|= Rm
;
12642 inst
.error
= BAD_HIREG
;
12650 Rd
= inst
.operands
[0].reg
;
12651 Rm
= inst
.operands
[1].reg
;
12653 reject_bad_reg (Rd
);
12654 reject_bad_reg (Rm
);
12656 inst
.instruction
|= Rd
<< 8;
12657 inst
.instruction
|= Rm
;
12665 Rd
= inst
.operands
[0].reg
;
12666 Rs
= (inst
.operands
[1].present
12667 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12668 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12670 reject_bad_reg (Rd
);
12671 reject_bad_reg (Rs
);
12672 if (inst
.operands
[2].isreg
)
12673 reject_bad_reg (inst
.operands
[2].reg
);
12675 inst
.instruction
|= Rd
<< 8;
12676 inst
.instruction
|= Rs
<< 16;
12677 if (!inst
.operands
[2].isreg
)
12679 bfd_boolean narrow
;
12681 if ((inst
.instruction
& 0x00100000) != 0)
12682 narrow
= !in_it_block ();
12684 narrow
= in_it_block ();
12686 if (Rd
> 7 || Rs
> 7)
12689 if (inst
.size_req
== 4 || !unified_syntax
)
12692 if (inst
.reloc
.exp
.X_op
!= O_constant
12693 || inst
.reloc
.exp
.X_add_number
!= 0)
12696 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12697 relaxation, but it doesn't seem worth the hassle. */
12700 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12701 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12702 inst
.instruction
|= Rs
<< 3;
12703 inst
.instruction
|= Rd
;
12707 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12708 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12712 encode_thumb32_shifted_operand (2);
12718 if (warn_on_deprecated
12719 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12720 as_tsktsk (_("setend use is deprecated for ARMv8"));
12722 set_it_insn_type (OUTSIDE_IT_INSN
);
12723 if (inst
.operands
[0].imm
)
12724 inst
.instruction
|= 0x8;
12730 if (!inst
.operands
[1].present
)
12731 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12733 if (unified_syntax
)
12735 bfd_boolean narrow
;
12738 switch (inst
.instruction
)
12741 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12743 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12745 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12747 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12751 if (THUMB_SETS_FLAGS (inst
.instruction
))
12752 narrow
= !in_it_block ();
12754 narrow
= in_it_block ();
12755 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12757 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12759 if (inst
.operands
[2].isreg
12760 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12761 || inst
.operands
[2].reg
> 7))
12763 if (inst
.size_req
== 4)
12766 reject_bad_reg (inst
.operands
[0].reg
);
12767 reject_bad_reg (inst
.operands
[1].reg
);
12771 if (inst
.operands
[2].isreg
)
12773 reject_bad_reg (inst
.operands
[2].reg
);
12774 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12775 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12776 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12777 inst
.instruction
|= inst
.operands
[2].reg
;
12779 /* PR 12854: Error on extraneous shifts. */
12780 constraint (inst
.operands
[2].shifted
,
12781 _("extraneous shift as part of operand to shift insn"));
12785 inst
.operands
[1].shifted
= 1;
12786 inst
.operands
[1].shift_kind
= shift_kind
;
12787 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12788 ? T_MNEM_movs
: T_MNEM_mov
);
12789 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12790 encode_thumb32_shifted_operand (1);
12791 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12792 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12797 if (inst
.operands
[2].isreg
)
12799 switch (shift_kind
)
12801 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12802 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12803 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12804 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12808 inst
.instruction
|= inst
.operands
[0].reg
;
12809 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12811 /* PR 12854: Error on extraneous shifts. */
12812 constraint (inst
.operands
[2].shifted
,
12813 _("extraneous shift as part of operand to shift insn"));
12817 switch (shift_kind
)
12819 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12820 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12821 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12824 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12825 inst
.instruction
|= inst
.operands
[0].reg
;
12826 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12832 constraint (inst
.operands
[0].reg
> 7
12833 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12834 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12836 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12838 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12839 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12840 _("source1 and dest must be same register"));
12842 switch (inst
.instruction
)
12844 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12845 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12846 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12847 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12851 inst
.instruction
|= inst
.operands
[0].reg
;
12852 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12854 /* PR 12854: Error on extraneous shifts. */
12855 constraint (inst
.operands
[2].shifted
,
12856 _("extraneous shift as part of operand to shift insn"));
12860 switch (inst
.instruction
)
12862 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12863 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12864 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12865 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12868 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12869 inst
.instruction
|= inst
.operands
[0].reg
;
12870 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12878 unsigned Rd
, Rn
, Rm
;
12880 Rd
= inst
.operands
[0].reg
;
12881 Rn
= inst
.operands
[1].reg
;
12882 Rm
= inst
.operands
[2].reg
;
12884 reject_bad_reg (Rd
);
12885 reject_bad_reg (Rn
);
12886 reject_bad_reg (Rm
);
12888 inst
.instruction
|= Rd
<< 8;
12889 inst
.instruction
|= Rn
<< 16;
12890 inst
.instruction
|= Rm
;
12896 unsigned Rd
, Rn
, Rm
;
12898 Rd
= inst
.operands
[0].reg
;
12899 Rm
= inst
.operands
[1].reg
;
12900 Rn
= inst
.operands
[2].reg
;
12902 reject_bad_reg (Rd
);
12903 reject_bad_reg (Rn
);
12904 reject_bad_reg (Rm
);
12906 inst
.instruction
|= Rd
<< 8;
12907 inst
.instruction
|= Rn
<< 16;
12908 inst
.instruction
|= Rm
;
12914 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12915 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12916 _("SMC is not permitted on this architecture"));
12917 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12918 _("expression too complex"));
12919 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12920 inst
.instruction
|= (value
& 0xf000) >> 12;
12921 inst
.instruction
|= (value
& 0x0ff0);
12922 inst
.instruction
|= (value
& 0x000f) << 16;
12923 /* PR gas/15623: SMC instructions must be last in an IT block. */
12924 set_it_insn_type_last ();
12930 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12932 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12933 inst
.instruction
|= (value
& 0x0fff);
12934 inst
.instruction
|= (value
& 0xf000) << 4;
12938 do_t_ssat_usat (int bias
)
12942 Rd
= inst
.operands
[0].reg
;
12943 Rn
= inst
.operands
[2].reg
;
12945 reject_bad_reg (Rd
);
12946 reject_bad_reg (Rn
);
12948 inst
.instruction
|= Rd
<< 8;
12949 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12950 inst
.instruction
|= Rn
<< 16;
12952 if (inst
.operands
[3].present
)
12954 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12956 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12958 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12959 _("expression too complex"));
12961 if (shift_amount
!= 0)
12963 constraint (shift_amount
> 31,
12964 _("shift expression is too large"));
12966 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12967 inst
.instruction
|= 0x00200000; /* sh bit. */
12969 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12970 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12978 do_t_ssat_usat (1);
12986 Rd
= inst
.operands
[0].reg
;
12987 Rn
= inst
.operands
[2].reg
;
12989 reject_bad_reg (Rd
);
12990 reject_bad_reg (Rn
);
12992 inst
.instruction
|= Rd
<< 8;
12993 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12994 inst
.instruction
|= Rn
<< 16;
13000 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13001 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13002 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13003 || inst
.operands
[2].negative
,
13006 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13008 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13009 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13010 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13011 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13017 if (!inst
.operands
[2].present
)
13018 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13020 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13021 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13022 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13025 inst
.instruction
|= inst
.operands
[0].reg
;
13026 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13027 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13028 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13034 unsigned Rd
, Rn
, Rm
;
13036 Rd
= inst
.operands
[0].reg
;
13037 Rn
= inst
.operands
[1].reg
;
13038 Rm
= inst
.operands
[2].reg
;
13040 reject_bad_reg (Rd
);
13041 reject_bad_reg (Rn
);
13042 reject_bad_reg (Rm
);
13044 inst
.instruction
|= Rd
<< 8;
13045 inst
.instruction
|= Rn
<< 16;
13046 inst
.instruction
|= Rm
;
13047 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13055 Rd
= inst
.operands
[0].reg
;
13056 Rm
= inst
.operands
[1].reg
;
13058 reject_bad_reg (Rd
);
13059 reject_bad_reg (Rm
);
13061 if (inst
.instruction
<= 0xffff
13062 && inst
.size_req
!= 4
13063 && Rd
<= 7 && Rm
<= 7
13064 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13066 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13067 inst
.instruction
|= Rd
;
13068 inst
.instruction
|= Rm
<< 3;
13070 else if (unified_syntax
)
13072 if (inst
.instruction
<= 0xffff)
13073 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13074 inst
.instruction
|= Rd
<< 8;
13075 inst
.instruction
|= Rm
;
13076 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13080 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13081 _("Thumb encoding does not support rotation"));
13082 constraint (1, BAD_HIREG
);
13089 /* We have to do the following check manually as ARM_EXT_OS only applies
13091 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13093 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13094 /* This only applies to the v6m however, not later architectures. */
13095 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13096 as_bad (_("SVC is not permitted on this architecture"));
13097 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13100 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13109 half
= (inst
.instruction
& 0x10) != 0;
13110 set_it_insn_type_last ();
13111 constraint (inst
.operands
[0].immisreg
,
13112 _("instruction requires register index"));
13114 Rn
= inst
.operands
[0].reg
;
13115 Rm
= inst
.operands
[0].imm
;
13117 constraint (Rn
== REG_SP
, BAD_SP
);
13118 reject_bad_reg (Rm
);
13120 constraint (!half
&& inst
.operands
[0].shifted
,
13121 _("instruction does not allow shifted index"));
13122 inst
.instruction
|= (Rn
<< 16) | Rm
;
13128 if (!inst
.operands
[0].present
)
13129 inst
.operands
[0].imm
= 0;
13131 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13133 constraint (inst
.size_req
== 2,
13134 _("immediate value out of range"));
13135 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13136 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13137 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13141 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13142 inst
.instruction
|= inst
.operands
[0].imm
;
13145 set_it_insn_type (NEUTRAL_IT_INSN
);
13152 do_t_ssat_usat (0);
13160 Rd
= inst
.operands
[0].reg
;
13161 Rn
= inst
.operands
[2].reg
;
13163 reject_bad_reg (Rd
);
13164 reject_bad_reg (Rn
);
13166 inst
.instruction
|= Rd
<< 8;
13167 inst
.instruction
|= inst
.operands
[1].imm
;
13168 inst
.instruction
|= Rn
<< 16;
13171 /* Neon instruction encoder helpers. */
13173 /* Encodings for the different types for various Neon opcodes. */
13175 /* An "invalid" code for the following tables. */
13178 struct neon_tab_entry
13181 unsigned float_or_poly
;
13182 unsigned scalar_or_imm
;
13185 /* Map overloaded Neon opcodes to their respective encodings. */
13186 #define NEON_ENC_TAB \
13187 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13188 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13189 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13190 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13191 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13192 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13193 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13194 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13195 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13196 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13197 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13198 /* Register variants of the following two instructions are encoded as
13199 vcge / vcgt with the operands reversed. */ \
13200 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13201 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13202 X(vfma, N_INV, 0x0000c10, N_INV), \
13203 X(vfms, N_INV, 0x0200c10, N_INV), \
13204 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13205 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13206 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13207 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13208 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13209 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13210 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13211 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13212 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13213 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13214 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13215 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13216 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13217 X(vshl, 0x0000400, N_INV, 0x0800510), \
13218 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13219 X(vand, 0x0000110, N_INV, 0x0800030), \
13220 X(vbic, 0x0100110, N_INV, 0x0800030), \
13221 X(veor, 0x1000110, N_INV, N_INV), \
13222 X(vorn, 0x0300110, N_INV, 0x0800010), \
13223 X(vorr, 0x0200110, N_INV, 0x0800010), \
13224 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13225 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13226 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13227 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13228 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13229 X(vst1, 0x0000000, 0x0800000, N_INV), \
13230 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13231 X(vst2, 0x0000100, 0x0800100, N_INV), \
13232 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13233 X(vst3, 0x0000200, 0x0800200, N_INV), \
13234 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13235 X(vst4, 0x0000300, 0x0800300, N_INV), \
13236 X(vmovn, 0x1b20200, N_INV, N_INV), \
13237 X(vtrn, 0x1b20080, N_INV, N_INV), \
13238 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13239 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13240 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13241 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13242 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13243 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13244 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13245 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13246 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13247 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13248 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13249 X(vseleq, 0xe000a00, N_INV, N_INV), \
13250 X(vselvs, 0xe100a00, N_INV, N_INV), \
13251 X(vselge, 0xe200a00, N_INV, N_INV), \
13252 X(vselgt, 0xe300a00, N_INV, N_INV), \
13253 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13254 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13255 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13256 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13257 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13258 X(aes, 0x3b00300, N_INV, N_INV), \
13259 X(sha3op, 0x2000c00, N_INV, N_INV), \
13260 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13261 X(sha2op, 0x3ba0380, N_INV, N_INV)
13265 #define X(OPC,I,F,S) N_MNEM_##OPC
13270 static const struct neon_tab_entry neon_enc_tab
[] =
13272 #define X(OPC,I,F,S) { (I), (F), (S) }
13277 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13278 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13279 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13280 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13281 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13282 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13283 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13284 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13285 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13286 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13287 #define NEON_ENC_SINGLE_(X) \
13288 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13289 #define NEON_ENC_DOUBLE_(X) \
13290 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13291 #define NEON_ENC_FPV8_(X) \
13292 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13294 #define NEON_ENCODE(type, inst) \
13297 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13298 inst.is_neon = 1; \
13302 #define check_neon_suffixes \
13305 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13307 as_bad (_("invalid neon suffix for non neon instruction")); \
13313 /* Define shapes for instruction operands. The following mnemonic characters
13314 are used in this table:
13316 F - VFP S<n> register
13317 D - Neon D<n> register
13318 Q - Neon Q<n> register
13322 L - D<n> register list
13324 This table is used to generate various data:
13325 - enumerations of the form NS_DDR to be used as arguments to
13327 - a table classifying shapes into single, double, quad, mixed.
13328 - a table used to drive neon_select_shape. */
13330 #define NEON_SHAPE_DEF \
13331 X(3, (D, D, D), DOUBLE), \
13332 X(3, (Q, Q, Q), QUAD), \
13333 X(3, (D, D, I), DOUBLE), \
13334 X(3, (Q, Q, I), QUAD), \
13335 X(3, (D, D, S), DOUBLE), \
13336 X(3, (Q, Q, S), QUAD), \
13337 X(2, (D, D), DOUBLE), \
13338 X(2, (Q, Q), QUAD), \
13339 X(2, (D, S), DOUBLE), \
13340 X(2, (Q, S), QUAD), \
13341 X(2, (D, R), DOUBLE), \
13342 X(2, (Q, R), QUAD), \
13343 X(2, (D, I), DOUBLE), \
13344 X(2, (Q, I), QUAD), \
13345 X(3, (D, L, D), DOUBLE), \
13346 X(2, (D, Q), MIXED), \
13347 X(2, (Q, D), MIXED), \
13348 X(3, (D, Q, I), MIXED), \
13349 X(3, (Q, D, I), MIXED), \
13350 X(3, (Q, D, D), MIXED), \
13351 X(3, (D, Q, Q), MIXED), \
13352 X(3, (Q, Q, D), MIXED), \
13353 X(3, (Q, D, S), MIXED), \
13354 X(3, (D, Q, S), MIXED), \
13355 X(4, (D, D, D, I), DOUBLE), \
13356 X(4, (Q, Q, Q, I), QUAD), \
13357 X(4, (D, D, S, I), DOUBLE), \
13358 X(4, (Q, Q, S, I), QUAD), \
13359 X(2, (F, F), SINGLE), \
13360 X(3, (F, F, F), SINGLE), \
13361 X(2, (F, I), SINGLE), \
13362 X(2, (F, D), MIXED), \
13363 X(2, (D, F), MIXED), \
13364 X(3, (F, F, I), MIXED), \
13365 X(4, (R, R, F, F), SINGLE), \
13366 X(4, (F, F, R, R), SINGLE), \
13367 X(3, (D, R, R), DOUBLE), \
13368 X(3, (R, R, D), DOUBLE), \
13369 X(2, (S, R), SINGLE), \
13370 X(2, (R, S), SINGLE), \
13371 X(2, (F, R), SINGLE), \
13372 X(2, (R, F), SINGLE), \
13373 /* Half float shape supported so far. */\
13374 X (2, (H, D), MIXED), \
13375 X (2, (D, H), MIXED), \
13376 X (2, (H, F), MIXED), \
13377 X (2, (F, H), MIXED), \
13378 X (2, (H, H), HALF), \
13379 X (2, (H, R), HALF), \
13380 X (2, (R, H), HALF), \
13381 X (2, (H, I), HALF), \
13382 X (3, (H, H, H), HALF), \
13383 X (3, (H, F, I), MIXED), \
13384 X (3, (F, H, I), MIXED)
13386 #define S2(A,B) NS_##A##B
13387 #define S3(A,B,C) NS_##A##B##C
13388 #define S4(A,B,C,D) NS_##A##B##C##D
13390 #define X(N, L, C) S##N L
13403 enum neon_shape_class
13412 #define X(N, L, C) SC_##C
13414 static enum neon_shape_class neon_shape_class
[] =
13433 /* Register widths of above. */
13434 static unsigned neon_shape_el_size
[] =
13446 struct neon_shape_info
13449 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13452 #define S2(A,B) { SE_##A, SE_##B }
13453 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13454 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13456 #define X(N, L, C) { N, S##N L }
13458 static struct neon_shape_info neon_shape_tab
[] =
13468 /* Bit masks used in type checking given instructions.
13469 'N_EQK' means the type must be the same as (or based on in some way) the key
13470 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13471 set, various other bits can be set as well in order to modify the meaning of
13472 the type constraint. */
13474 enum neon_type_mask
13498 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13499 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13500 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13501 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13502 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13503 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13504 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13505 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13506 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13507 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13508 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13510 N_MAX_NONSPECIAL
= N_P64
13513 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13515 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13516 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13517 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13518 #define N_S_32 (N_S8 | N_S16 | N_S32)
13519 #define N_F_16_32 (N_F16 | N_F32)
13520 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13521 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13522 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13523 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13525 /* Pass this as the first type argument to neon_check_type to ignore types
13527 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13529 /* Select a "shape" for the current instruction (describing register types or
13530 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13531 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13532 function of operand parsing, so this function doesn't need to be called.
13533 Shapes should be listed in order of decreasing length. */
13535 static enum neon_shape
13536 neon_select_shape (enum neon_shape shape
, ...)
13539 enum neon_shape first_shape
= shape
;
13541 /* Fix missing optional operands. FIXME: we don't know at this point how
13542 many arguments we should have, so this makes the assumption that we have
13543 > 1. This is true of all current Neon opcodes, I think, but may not be
13544 true in the future. */
13545 if (!inst
.operands
[1].present
)
13546 inst
.operands
[1] = inst
.operands
[0];
13548 va_start (ap
, shape
);
13550 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13555 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13557 if (!inst
.operands
[j
].present
)
13563 switch (neon_shape_tab
[shape
].el
[j
])
13565 /* If a .f16, .16, .u16, .s16 type specifier is given over
13566 a VFP single precision register operand, it's essentially
13567 means only half of the register is used.
13569 If the type specifier is given after the mnemonics, the
13570 information is stored in inst.vectype. If the type specifier
13571 is given after register operand, the information is stored
13572 in inst.operands[].vectype.
13574 When there is only one type specifier, and all the register
13575 operands are the same type of hardware register, the type
13576 specifier applies to all register operands.
13578 If no type specifier is given, the shape is inferred from
13579 operand information.
13582 vadd.f16 s0, s1, s2: NS_HHH
13583 vabs.f16 s0, s1: NS_HH
13584 vmov.f16 s0, r1: NS_HR
13585 vmov.f16 r0, s1: NS_RH
13586 vcvt.f16 r0, s1: NS_RH
13587 vcvt.f16.s32 s2, s2, #29: NS_HFI
13588 vcvt.f16.s32 s2, s2: NS_HF
13591 if (!(inst
.operands
[j
].isreg
13592 && inst
.operands
[j
].isvec
13593 && inst
.operands
[j
].issingle
13594 && !inst
.operands
[j
].isquad
13595 && ((inst
.vectype
.elems
== 1
13596 && inst
.vectype
.el
[0].size
== 16)
13597 || (inst
.vectype
.elems
> 1
13598 && inst
.vectype
.el
[j
].size
== 16)
13599 || (inst
.vectype
.elems
== 0
13600 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13601 && inst
.operands
[j
].vectype
.size
== 16))))
13606 if (!(inst
.operands
[j
].isreg
13607 && inst
.operands
[j
].isvec
13608 && inst
.operands
[j
].issingle
13609 && !inst
.operands
[j
].isquad
13610 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13611 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13612 || (inst
.vectype
.elems
== 0
13613 && (inst
.operands
[j
].vectype
.size
== 32
13614 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13619 if (!(inst
.operands
[j
].isreg
13620 && inst
.operands
[j
].isvec
13621 && !inst
.operands
[j
].isquad
13622 && !inst
.operands
[j
].issingle
))
13627 if (!(inst
.operands
[j
].isreg
13628 && !inst
.operands
[j
].isvec
))
13633 if (!(inst
.operands
[j
].isreg
13634 && inst
.operands
[j
].isvec
13635 && inst
.operands
[j
].isquad
13636 && !inst
.operands
[j
].issingle
))
13641 if (!(!inst
.operands
[j
].isreg
13642 && !inst
.operands
[j
].isscalar
))
13647 if (!(!inst
.operands
[j
].isreg
13648 && inst
.operands
[j
].isscalar
))
13658 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13659 /* We've matched all the entries in the shape table, and we don't
13660 have any left over operands which have not been matched. */
13666 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13667 first_error (_("invalid instruction shape"));
13672 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13673 means the Q bit should be set). */
13676 neon_quad (enum neon_shape shape
)
13678 return neon_shape_class
[shape
] == SC_QUAD
;
13682 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13685 /* Allow modification to be made to types which are constrained to be
13686 based on the key element, based on bits set alongside N_EQK. */
13687 if ((typebits
& N_EQK
) != 0)
13689 if ((typebits
& N_HLF
) != 0)
13691 else if ((typebits
& N_DBL
) != 0)
13693 if ((typebits
& N_SGN
) != 0)
13694 *g_type
= NT_signed
;
13695 else if ((typebits
& N_UNS
) != 0)
13696 *g_type
= NT_unsigned
;
13697 else if ((typebits
& N_INT
) != 0)
13698 *g_type
= NT_integer
;
13699 else if ((typebits
& N_FLT
) != 0)
13700 *g_type
= NT_float
;
13701 else if ((typebits
& N_SIZ
) != 0)
13702 *g_type
= NT_untyped
;
13706 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13707 operand type, i.e. the single type specified in a Neon instruction when it
13708 is the only one given. */
13710 static struct neon_type_el
13711 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13713 struct neon_type_el dest
= *key
;
13715 gas_assert ((thisarg
& N_EQK
) != 0);
13717 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13722 /* Convert Neon type and size into compact bitmask representation. */
13724 static enum neon_type_mask
13725 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13732 case 8: return N_8
;
13733 case 16: return N_16
;
13734 case 32: return N_32
;
13735 case 64: return N_64
;
13743 case 8: return N_I8
;
13744 case 16: return N_I16
;
13745 case 32: return N_I32
;
13746 case 64: return N_I64
;
13754 case 16: return N_F16
;
13755 case 32: return N_F32
;
13756 case 64: return N_F64
;
13764 case 8: return N_P8
;
13765 case 16: return N_P16
;
13766 case 64: return N_P64
;
13774 case 8: return N_S8
;
13775 case 16: return N_S16
;
13776 case 32: return N_S32
;
13777 case 64: return N_S64
;
13785 case 8: return N_U8
;
13786 case 16: return N_U16
;
13787 case 32: return N_U32
;
13788 case 64: return N_U64
;
13799 /* Convert compact Neon bitmask type representation to a type and size. Only
13800 handles the case where a single bit is set in the mask. */
13803 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13804 enum neon_type_mask mask
)
13806 if ((mask
& N_EQK
) != 0)
13809 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13811 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13813 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13815 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13820 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13822 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13823 *type
= NT_unsigned
;
13824 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13825 *type
= NT_integer
;
13826 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13827 *type
= NT_untyped
;
13828 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13830 else if ((mask
& (N_F_ALL
)) != 0)
13838 /* Modify a bitmask of allowed types. This is only needed for type
13842 modify_types_allowed (unsigned allowed
, unsigned mods
)
13845 enum neon_el_type type
;
13851 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13853 if (el_type_of_type_chk (&type
, &size
,
13854 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13856 neon_modify_type_size (mods
, &type
, &size
);
13857 destmask
|= type_chk_of_el_type (type
, size
);
13864 /* Check type and return type classification.
13865 The manual states (paraphrase): If one datatype is given, it indicates the
13867 - the second operand, if there is one
13868 - the operand, if there is no second operand
13869 - the result, if there are no operands.
13870 This isn't quite good enough though, so we use a concept of a "key" datatype
13871 which is set on a per-instruction basis, which is the one which matters when
13872 only one data type is written.
13873 Note: this function has side-effects (e.g. filling in missing operands). All
13874 Neon instructions should call it before performing bit encoding. */
13876 static struct neon_type_el
13877 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13880 unsigned i
, pass
, key_el
= 0;
13881 unsigned types
[NEON_MAX_TYPE_ELS
];
13882 enum neon_el_type k_type
= NT_invtype
;
13883 unsigned k_size
= -1u;
13884 struct neon_type_el badtype
= {NT_invtype
, -1};
13885 unsigned key_allowed
= 0;
13887 /* Optional registers in Neon instructions are always (not) in operand 1.
13888 Fill in the missing operand here, if it was omitted. */
13889 if (els
> 1 && !inst
.operands
[1].present
)
13890 inst
.operands
[1] = inst
.operands
[0];
13892 /* Suck up all the varargs. */
13894 for (i
= 0; i
< els
; i
++)
13896 unsigned thisarg
= va_arg (ap
, unsigned);
13897 if (thisarg
== N_IGNORE_TYPE
)
13902 types
[i
] = thisarg
;
13903 if ((thisarg
& N_KEY
) != 0)
13908 if (inst
.vectype
.elems
> 0)
13909 for (i
= 0; i
< els
; i
++)
13910 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13912 first_error (_("types specified in both the mnemonic and operands"));
13916 /* Duplicate inst.vectype elements here as necessary.
13917 FIXME: No idea if this is exactly the same as the ARM assembler,
13918 particularly when an insn takes one register and one non-register
13920 if (inst
.vectype
.elems
== 1 && els
> 1)
13923 inst
.vectype
.elems
= els
;
13924 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13925 for (j
= 0; j
< els
; j
++)
13927 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13930 else if (inst
.vectype
.elems
== 0 && els
> 0)
13933 /* No types were given after the mnemonic, so look for types specified
13934 after each operand. We allow some flexibility here; as long as the
13935 "key" operand has a type, we can infer the others. */
13936 for (j
= 0; j
< els
; j
++)
13937 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13938 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13940 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13942 for (j
= 0; j
< els
; j
++)
13943 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13944 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13949 first_error (_("operand types can't be inferred"));
13953 else if (inst
.vectype
.elems
!= els
)
13955 first_error (_("type specifier has the wrong number of parts"));
13959 for (pass
= 0; pass
< 2; pass
++)
13961 for (i
= 0; i
< els
; i
++)
13963 unsigned thisarg
= types
[i
];
13964 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13965 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13966 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13967 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13969 /* Decay more-specific signed & unsigned types to sign-insensitive
13970 integer types if sign-specific variants are unavailable. */
13971 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13972 && (types_allowed
& N_SU_ALL
) == 0)
13973 g_type
= NT_integer
;
13975 /* If only untyped args are allowed, decay any more specific types to
13976 them. Some instructions only care about signs for some element
13977 sizes, so handle that properly. */
13978 if (((types_allowed
& N_UNT
) == 0)
13979 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13980 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13981 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13982 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13983 g_type
= NT_untyped
;
13987 if ((thisarg
& N_KEY
) != 0)
13991 key_allowed
= thisarg
& ~N_KEY
;
13993 /* Check architecture constraint on FP16 extension. */
13995 && k_type
== NT_float
13996 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13998 inst
.error
= _(BAD_FP16
);
14005 if ((thisarg
& N_VFP
) != 0)
14007 enum neon_shape_el regshape
;
14008 unsigned regwidth
, match
;
14010 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14013 first_error (_("invalid instruction shape"));
14016 regshape
= neon_shape_tab
[ns
].el
[i
];
14017 regwidth
= neon_shape_el_size
[regshape
];
14019 /* In VFP mode, operands must match register widths. If we
14020 have a key operand, use its width, else use the width of
14021 the current operand. */
14027 /* FP16 will use a single precision register. */
14028 if (regwidth
== 32 && match
== 16)
14030 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14034 inst
.error
= _(BAD_FP16
);
14039 if (regwidth
!= match
)
14041 first_error (_("operand size must match register width"));
14046 if ((thisarg
& N_EQK
) == 0)
14048 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14050 if ((given_type
& types_allowed
) == 0)
14052 first_error (_("bad type in Neon instruction"));
14058 enum neon_el_type mod_k_type
= k_type
;
14059 unsigned mod_k_size
= k_size
;
14060 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14061 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14063 first_error (_("inconsistent types in Neon instruction"));
14071 return inst
.vectype
.el
[key_el
];
14074 /* Neon-style VFP instruction forwarding. */
14076 /* Thumb VFP instructions have 0xE in the condition field. */
14079 do_vfp_cond_or_thumb (void)
14084 inst
.instruction
|= 0xe0000000;
14086 inst
.instruction
|= inst
.cond
<< 28;
14089 /* Look up and encode a simple mnemonic, for use as a helper function for the
14090 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14091 etc. It is assumed that operand parsing has already been done, and that the
14092 operands are in the form expected by the given opcode (this isn't necessarily
14093 the same as the form in which they were parsed, hence some massaging must
14094 take place before this function is called).
14095 Checks current arch version against that in the looked-up opcode. */
14098 do_vfp_nsyn_opcode (const char *opname
)
14100 const struct asm_opcode
*opcode
;
14102 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14107 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14108 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14115 inst
.instruction
= opcode
->tvalue
;
14116 opcode
->tencode ();
14120 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14121 opcode
->aencode ();
14126 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14128 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14130 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14133 do_vfp_nsyn_opcode ("fadds");
14135 do_vfp_nsyn_opcode ("fsubs");
14137 /* ARMv8.2 fp16 instruction. */
14139 do_scalar_fp16_v82_encode ();
14144 do_vfp_nsyn_opcode ("faddd");
14146 do_vfp_nsyn_opcode ("fsubd");
14150 /* Check operand types to see if this is a VFP instruction, and if so call
14154 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14156 enum neon_shape rs
;
14157 struct neon_type_el et
;
14162 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14163 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14167 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14168 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14169 N_F_ALL
| N_KEY
| N_VFP
);
14176 if (et
.type
!= NT_invtype
)
14187 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14189 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14191 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14194 do_vfp_nsyn_opcode ("fmacs");
14196 do_vfp_nsyn_opcode ("fnmacs");
14198 /* ARMv8.2 fp16 instruction. */
14200 do_scalar_fp16_v82_encode ();
14205 do_vfp_nsyn_opcode ("fmacd");
14207 do_vfp_nsyn_opcode ("fnmacd");
14212 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14214 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14216 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14219 do_vfp_nsyn_opcode ("ffmas");
14221 do_vfp_nsyn_opcode ("ffnmas");
14223 /* ARMv8.2 fp16 instruction. */
14225 do_scalar_fp16_v82_encode ();
14230 do_vfp_nsyn_opcode ("ffmad");
14232 do_vfp_nsyn_opcode ("ffnmad");
14237 do_vfp_nsyn_mul (enum neon_shape rs
)
14239 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14241 do_vfp_nsyn_opcode ("fmuls");
14243 /* ARMv8.2 fp16 instruction. */
14245 do_scalar_fp16_v82_encode ();
14248 do_vfp_nsyn_opcode ("fmuld");
14252 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14254 int is_neg
= (inst
.instruction
& 0x80) != 0;
14255 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14257 if (rs
== NS_FF
|| rs
== NS_HH
)
14260 do_vfp_nsyn_opcode ("fnegs");
14262 do_vfp_nsyn_opcode ("fabss");
14264 /* ARMv8.2 fp16 instruction. */
14266 do_scalar_fp16_v82_encode ();
14271 do_vfp_nsyn_opcode ("fnegd");
14273 do_vfp_nsyn_opcode ("fabsd");
14277 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14278 insns belong to Neon, and are handled elsewhere. */
14281 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14283 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14287 do_vfp_nsyn_opcode ("fldmdbs");
14289 do_vfp_nsyn_opcode ("fldmias");
14294 do_vfp_nsyn_opcode ("fstmdbs");
14296 do_vfp_nsyn_opcode ("fstmias");
14301 do_vfp_nsyn_sqrt (void)
14303 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14304 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14306 if (rs
== NS_FF
|| rs
== NS_HH
)
14308 do_vfp_nsyn_opcode ("fsqrts");
14310 /* ARMv8.2 fp16 instruction. */
14312 do_scalar_fp16_v82_encode ();
14315 do_vfp_nsyn_opcode ("fsqrtd");
14319 do_vfp_nsyn_div (void)
14321 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14322 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14323 N_F_ALL
| N_KEY
| N_VFP
);
14325 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14327 do_vfp_nsyn_opcode ("fdivs");
14329 /* ARMv8.2 fp16 instruction. */
14331 do_scalar_fp16_v82_encode ();
14334 do_vfp_nsyn_opcode ("fdivd");
14338 do_vfp_nsyn_nmul (void)
14340 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14341 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14342 N_F_ALL
| N_KEY
| N_VFP
);
14344 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14346 NEON_ENCODE (SINGLE
, inst
);
14347 do_vfp_sp_dyadic ();
14349 /* ARMv8.2 fp16 instruction. */
14351 do_scalar_fp16_v82_encode ();
14355 NEON_ENCODE (DOUBLE
, inst
);
14356 do_vfp_dp_rd_rn_rm ();
14358 do_vfp_cond_or_thumb ();
14363 do_vfp_nsyn_cmp (void)
14365 enum neon_shape rs
;
14366 if (inst
.operands
[1].isreg
)
14368 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14369 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14371 if (rs
== NS_FF
|| rs
== NS_HH
)
14373 NEON_ENCODE (SINGLE
, inst
);
14374 do_vfp_sp_monadic ();
14378 NEON_ENCODE (DOUBLE
, inst
);
14379 do_vfp_dp_rd_rm ();
14384 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14385 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14387 switch (inst
.instruction
& 0x0fffffff)
14390 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14393 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14399 if (rs
== NS_FI
|| rs
== NS_HI
)
14401 NEON_ENCODE (SINGLE
, inst
);
14402 do_vfp_sp_compare_z ();
14406 NEON_ENCODE (DOUBLE
, inst
);
14410 do_vfp_cond_or_thumb ();
14412 /* ARMv8.2 fp16 instruction. */
14413 if (rs
== NS_HI
|| rs
== NS_HH
)
14414 do_scalar_fp16_v82_encode ();
14418 nsyn_insert_sp (void)
14420 inst
.operands
[1] = inst
.operands
[0];
14421 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14422 inst
.operands
[0].reg
= REG_SP
;
14423 inst
.operands
[0].isreg
= 1;
14424 inst
.operands
[0].writeback
= 1;
14425 inst
.operands
[0].present
= 1;
14429 do_vfp_nsyn_push (void)
14433 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14434 _("register list must contain at least 1 and at most 16 "
14437 if (inst
.operands
[1].issingle
)
14438 do_vfp_nsyn_opcode ("fstmdbs");
14440 do_vfp_nsyn_opcode ("fstmdbd");
14444 do_vfp_nsyn_pop (void)
14448 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14449 _("register list must contain at least 1 and at most 16 "
14452 if (inst
.operands
[1].issingle
)
14453 do_vfp_nsyn_opcode ("fldmias");
14455 do_vfp_nsyn_opcode ("fldmiad");
14458 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14459 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14462 neon_dp_fixup (struct arm_it
* insn
)
14464 unsigned int i
= insn
->instruction
;
14469 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14480 insn
->instruction
= i
;
14483 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14487 neon_logbits (unsigned x
)
14489 return ffs (x
) - 4;
14492 #define LOW4(R) ((R) & 0xf)
14493 #define HI1(R) (((R) >> 4) & 1)
14495 /* Encode insns with bit pattern:
14497 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14498 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14500 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14501 different meaning for some instruction. */
14504 neon_three_same (int isquad
, int ubit
, int size
)
14506 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14507 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14508 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14509 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14510 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14511 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14512 inst
.instruction
|= (isquad
!= 0) << 6;
14513 inst
.instruction
|= (ubit
!= 0) << 24;
14515 inst
.instruction
|= neon_logbits (size
) << 20;
14517 neon_dp_fixup (&inst
);
14520 /* Encode instructions of the form:
14522 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14523 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14525 Don't write size if SIZE == -1. */
14528 neon_two_same (int qbit
, int ubit
, int size
)
14530 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14531 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14532 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14533 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14534 inst
.instruction
|= (qbit
!= 0) << 6;
14535 inst
.instruction
|= (ubit
!= 0) << 24;
14538 inst
.instruction
|= neon_logbits (size
) << 18;
14540 neon_dp_fixup (&inst
);
14543 /* Neon instruction encoders, in approximate order of appearance. */
14546 do_neon_dyadic_i_su (void)
14548 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14549 struct neon_type_el et
= neon_check_type (3, rs
,
14550 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14551 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14555 do_neon_dyadic_i64_su (void)
14557 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14558 struct neon_type_el et
= neon_check_type (3, rs
,
14559 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14560 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14564 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14567 unsigned size
= et
.size
>> 3;
14568 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14569 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14570 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14571 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14572 inst
.instruction
|= (isquad
!= 0) << 6;
14573 inst
.instruction
|= immbits
<< 16;
14574 inst
.instruction
|= (size
>> 3) << 7;
14575 inst
.instruction
|= (size
& 0x7) << 19;
14577 inst
.instruction
|= (uval
!= 0) << 24;
14579 neon_dp_fixup (&inst
);
14583 do_neon_shl_imm (void)
14585 if (!inst
.operands
[2].isreg
)
14587 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14588 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14589 int imm
= inst
.operands
[2].imm
;
14591 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14592 _("immediate out of range for shift"));
14593 NEON_ENCODE (IMMED
, inst
);
14594 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14598 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14599 struct neon_type_el et
= neon_check_type (3, rs
,
14600 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14603 /* VSHL/VQSHL 3-register variants have syntax such as:
14605 whereas other 3-register operations encoded by neon_three_same have
14608 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14610 tmp
= inst
.operands
[2].reg
;
14611 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14612 inst
.operands
[1].reg
= tmp
;
14613 NEON_ENCODE (INTEGER
, inst
);
14614 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14619 do_neon_qshl_imm (void)
14621 if (!inst
.operands
[2].isreg
)
14623 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14624 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14625 int imm
= inst
.operands
[2].imm
;
14627 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14628 _("immediate out of range for shift"));
14629 NEON_ENCODE (IMMED
, inst
);
14630 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14634 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14635 struct neon_type_el et
= neon_check_type (3, rs
,
14636 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14639 /* See note in do_neon_shl_imm. */
14640 tmp
= inst
.operands
[2].reg
;
14641 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14642 inst
.operands
[1].reg
= tmp
;
14643 NEON_ENCODE (INTEGER
, inst
);
14644 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14649 do_neon_rshl (void)
14651 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14652 struct neon_type_el et
= neon_check_type (3, rs
,
14653 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14656 tmp
= inst
.operands
[2].reg
;
14657 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14658 inst
.operands
[1].reg
= tmp
;
14659 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14663 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14665 /* Handle .I8 pseudo-instructions. */
14668 /* Unfortunately, this will make everything apart from zero out-of-range.
14669 FIXME is this the intended semantics? There doesn't seem much point in
14670 accepting .I8 if so. */
14671 immediate
|= immediate
<< 8;
14677 if (immediate
== (immediate
& 0x000000ff))
14679 *immbits
= immediate
;
14682 else if (immediate
== (immediate
& 0x0000ff00))
14684 *immbits
= immediate
>> 8;
14687 else if (immediate
== (immediate
& 0x00ff0000))
14689 *immbits
= immediate
>> 16;
14692 else if (immediate
== (immediate
& 0xff000000))
14694 *immbits
= immediate
>> 24;
14697 if ((immediate
& 0xffff) != (immediate
>> 16))
14698 goto bad_immediate
;
14699 immediate
&= 0xffff;
14702 if (immediate
== (immediate
& 0x000000ff))
14704 *immbits
= immediate
;
14707 else if (immediate
== (immediate
& 0x0000ff00))
14709 *immbits
= immediate
>> 8;
14714 first_error (_("immediate value out of range"));
14719 do_neon_logic (void)
14721 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14723 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14724 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14725 /* U bit and size field were set as part of the bitmask. */
14726 NEON_ENCODE (INTEGER
, inst
);
14727 neon_three_same (neon_quad (rs
), 0, -1);
14731 const int three_ops_form
= (inst
.operands
[2].present
14732 && !inst
.operands
[2].isreg
);
14733 const int immoperand
= (three_ops_form
? 2 : 1);
14734 enum neon_shape rs
= (three_ops_form
14735 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14736 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14737 struct neon_type_el et
= neon_check_type (2, rs
,
14738 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14739 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14743 if (et
.type
== NT_invtype
)
14746 if (three_ops_form
)
14747 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14748 _("first and second operands shall be the same register"));
14750 NEON_ENCODE (IMMED
, inst
);
14752 immbits
= inst
.operands
[immoperand
].imm
;
14755 /* .i64 is a pseudo-op, so the immediate must be a repeating
14757 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14758 inst
.operands
[immoperand
].reg
: 0))
14760 /* Set immbits to an invalid constant. */
14761 immbits
= 0xdeadbeef;
14768 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14772 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14776 /* Pseudo-instruction for VBIC. */
14777 neon_invert_size (&immbits
, 0, et
.size
);
14778 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14782 /* Pseudo-instruction for VORR. */
14783 neon_invert_size (&immbits
, 0, et
.size
);
14784 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14794 inst
.instruction
|= neon_quad (rs
) << 6;
14795 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14796 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14797 inst
.instruction
|= cmode
<< 8;
14798 neon_write_immbits (immbits
);
14800 neon_dp_fixup (&inst
);
14805 do_neon_bitfield (void)
14807 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14808 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14809 neon_three_same (neon_quad (rs
), 0, -1);
14813 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14816 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14817 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14819 if (et
.type
== NT_float
)
14821 NEON_ENCODE (FLOAT
, inst
);
14822 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14826 NEON_ENCODE (INTEGER
, inst
);
14827 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14832 do_neon_dyadic_if_su (void)
14834 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14838 do_neon_dyadic_if_su_d (void)
14840 /* This version only allow D registers, but that constraint is enforced during
14841 operand parsing so we don't need to do anything extra here. */
14842 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14846 do_neon_dyadic_if_i_d (void)
14848 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14849 affected if we specify unsigned args. */
14850 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14853 enum vfp_or_neon_is_neon_bits
14856 NEON_CHECK_ARCH
= 2,
14857 NEON_CHECK_ARCH8
= 4
14860 /* Call this function if an instruction which may have belonged to the VFP or
14861 Neon instruction sets, but turned out to be a Neon instruction (due to the
14862 operand types involved, etc.). We have to check and/or fix-up a couple of
14865 - Make sure the user hasn't attempted to make a Neon instruction
14867 - Alter the value in the condition code field if necessary.
14868 - Make sure that the arch supports Neon instructions.
14870 Which of these operations take place depends on bits from enum
14871 vfp_or_neon_is_neon_bits.
14873 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14874 current instruction's condition is COND_ALWAYS, the condition field is
14875 changed to inst.uncond_value. This is necessary because instructions shared
14876 between VFP and Neon may be conditional for the VFP variants only, and the
14877 unconditional Neon version must have, e.g., 0xF in the condition field. */
14880 vfp_or_neon_is_neon (unsigned check
)
14882 /* Conditions are always legal in Thumb mode (IT blocks). */
14883 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14885 if (inst
.cond
!= COND_ALWAYS
)
14887 first_error (_(BAD_COND
));
14890 if (inst
.uncond_value
!= -1)
14891 inst
.instruction
|= inst
.uncond_value
<< 28;
14894 if ((check
& NEON_CHECK_ARCH
)
14895 && !mark_feature_used (&fpu_neon_ext_v1
))
14897 first_error (_(BAD_FPU
));
14901 if ((check
& NEON_CHECK_ARCH8
)
14902 && !mark_feature_used (&fpu_neon_ext_armv8
))
14904 first_error (_(BAD_FPU
));
14912 do_neon_addsub_if_i (void)
14914 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14917 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14920 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14921 affected if we specify unsigned args. */
14922 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14925 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14927 V<op> A,B (A is operand 0, B is operand 2)
14932 so handle that case specially. */
14935 neon_exchange_operands (void)
14937 if (inst
.operands
[1].present
)
14939 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14941 /* Swap operands[1] and operands[2]. */
14942 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14943 inst
.operands
[1] = inst
.operands
[2];
14944 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14949 inst
.operands
[1] = inst
.operands
[2];
14950 inst
.operands
[2] = inst
.operands
[0];
14955 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14957 if (inst
.operands
[2].isreg
)
14960 neon_exchange_operands ();
14961 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14965 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14966 struct neon_type_el et
= neon_check_type (2, rs
,
14967 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14969 NEON_ENCODE (IMMED
, inst
);
14970 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14971 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14972 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14973 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14974 inst
.instruction
|= neon_quad (rs
) << 6;
14975 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14976 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14978 neon_dp_fixup (&inst
);
14985 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
14989 do_neon_cmp_inv (void)
14991 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
14997 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15000 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15001 scalars, which are encoded in 5 bits, M : Rm.
15002 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15003 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15007 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15009 unsigned regno
= NEON_SCALAR_REG (scalar
);
15010 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15015 if (regno
> 7 || elno
> 3)
15017 return regno
| (elno
<< 3);
15020 if (regno
> 15 || elno
> 1)
15022 return regno
| (elno
<< 4);
15026 first_error (_("scalar out of range for multiply instruction"));
15032 /* Encode multiply / multiply-accumulate scalar instructions. */
15035 neon_mul_mac (struct neon_type_el et
, int ubit
)
15039 /* Give a more helpful error message if we have an invalid type. */
15040 if (et
.type
== NT_invtype
)
15043 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15044 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15045 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15046 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15047 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15048 inst
.instruction
|= LOW4 (scalar
);
15049 inst
.instruction
|= HI1 (scalar
) << 5;
15050 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15051 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15052 inst
.instruction
|= (ubit
!= 0) << 24;
15054 neon_dp_fixup (&inst
);
15058 do_neon_mac_maybe_scalar (void)
15060 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15063 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15066 if (inst
.operands
[2].isscalar
)
15068 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15069 struct neon_type_el et
= neon_check_type (3, rs
,
15070 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15071 NEON_ENCODE (SCALAR
, inst
);
15072 neon_mul_mac (et
, neon_quad (rs
));
15076 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15077 affected if we specify unsigned args. */
15078 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15083 do_neon_fmac (void)
15085 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15088 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15091 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15097 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15098 struct neon_type_el et
= neon_check_type (3, rs
,
15099 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15100 neon_three_same (neon_quad (rs
), 0, et
.size
);
15103 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15104 same types as the MAC equivalents. The polynomial type for this instruction
15105 is encoded the same as the integer type. */
15110 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15113 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15116 if (inst
.operands
[2].isscalar
)
15117 do_neon_mac_maybe_scalar ();
15119 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15123 do_neon_qdmulh (void)
15125 if (inst
.operands
[2].isscalar
)
15127 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15128 struct neon_type_el et
= neon_check_type (3, rs
,
15129 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15130 NEON_ENCODE (SCALAR
, inst
);
15131 neon_mul_mac (et
, neon_quad (rs
));
15135 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15136 struct neon_type_el et
= neon_check_type (3, rs
,
15137 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15138 NEON_ENCODE (INTEGER
, inst
);
15139 /* The U bit (rounding) comes from bit mask. */
15140 neon_three_same (neon_quad (rs
), 0, et
.size
);
15145 do_neon_qrdmlah (void)
15147 /* Check we're on the correct architecture. */
15148 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15150 _("instruction form not available on this architecture.");
15151 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15153 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15154 record_feature_use (&fpu_neon_ext_v8_1
);
15157 if (inst
.operands
[2].isscalar
)
15159 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15160 struct neon_type_el et
= neon_check_type (3, rs
,
15161 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15162 NEON_ENCODE (SCALAR
, inst
);
15163 neon_mul_mac (et
, neon_quad (rs
));
15167 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15168 struct neon_type_el et
= neon_check_type (3, rs
,
15169 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15170 NEON_ENCODE (INTEGER
, inst
);
15171 /* The U bit (rounding) comes from bit mask. */
15172 neon_three_same (neon_quad (rs
), 0, et
.size
);
15177 do_neon_fcmp_absolute (void)
15179 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15180 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15181 N_F_16_32
| N_KEY
);
15182 /* Size field comes from bit mask. */
15183 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15187 do_neon_fcmp_absolute_inv (void)
15189 neon_exchange_operands ();
15190 do_neon_fcmp_absolute ();
15194 do_neon_step (void)
15196 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15197 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15198 N_F_16_32
| N_KEY
);
15199 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15203 do_neon_abs_neg (void)
15205 enum neon_shape rs
;
15206 struct neon_type_el et
;
15208 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15211 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15214 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15215 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15217 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15218 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15219 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15220 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15221 inst
.instruction
|= neon_quad (rs
) << 6;
15222 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15223 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15225 neon_dp_fixup (&inst
);
15231 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15232 struct neon_type_el et
= neon_check_type (2, rs
,
15233 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15234 int imm
= inst
.operands
[2].imm
;
15235 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15236 _("immediate out of range for insert"));
15237 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15243 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15244 struct neon_type_el et
= neon_check_type (2, rs
,
15245 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15246 int imm
= inst
.operands
[2].imm
;
15247 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15248 _("immediate out of range for insert"));
15249 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15253 do_neon_qshlu_imm (void)
15255 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15256 struct neon_type_el et
= neon_check_type (2, rs
,
15257 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15258 int imm
= inst
.operands
[2].imm
;
15259 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15260 _("immediate out of range for shift"));
15261 /* Only encodes the 'U present' variant of the instruction.
15262 In this case, signed types have OP (bit 8) set to 0.
15263 Unsigned types have OP set to 1. */
15264 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15265 /* The rest of the bits are the same as other immediate shifts. */
15266 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15270 do_neon_qmovn (void)
15272 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15273 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15274 /* Saturating move where operands can be signed or unsigned, and the
15275 destination has the same signedness. */
15276 NEON_ENCODE (INTEGER
, inst
);
15277 if (et
.type
== NT_unsigned
)
15278 inst
.instruction
|= 0xc0;
15280 inst
.instruction
|= 0x80;
15281 neon_two_same (0, 1, et
.size
/ 2);
15285 do_neon_qmovun (void)
15287 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15288 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15289 /* Saturating move with unsigned results. Operands must be signed. */
15290 NEON_ENCODE (INTEGER
, inst
);
15291 neon_two_same (0, 1, et
.size
/ 2);
15295 do_neon_rshift_sat_narrow (void)
15297 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15298 or unsigned. If operands are unsigned, results must also be unsigned. */
15299 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15300 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15301 int imm
= inst
.operands
[2].imm
;
15302 /* This gets the bounds check, size encoding and immediate bits calculation
15306 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15307 VQMOVN.I<size> <Dd>, <Qm>. */
15310 inst
.operands
[2].present
= 0;
15311 inst
.instruction
= N_MNEM_vqmovn
;
15316 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15317 _("immediate out of range"));
15318 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15322 do_neon_rshift_sat_narrow_u (void)
15324 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15325 or unsigned. If operands are unsigned, results must also be unsigned. */
15326 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15327 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15328 int imm
= inst
.operands
[2].imm
;
15329 /* This gets the bounds check, size encoding and immediate bits calculation
15333 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15334 VQMOVUN.I<size> <Dd>, <Qm>. */
15337 inst
.operands
[2].present
= 0;
15338 inst
.instruction
= N_MNEM_vqmovun
;
15343 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15344 _("immediate out of range"));
15345 /* FIXME: The manual is kind of unclear about what value U should have in
15346 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15348 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15352 do_neon_movn (void)
15354 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15355 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15356 NEON_ENCODE (INTEGER
, inst
);
15357 neon_two_same (0, 1, et
.size
/ 2);
15361 do_neon_rshift_narrow (void)
15363 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15364 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15365 int imm
= inst
.operands
[2].imm
;
15366 /* This gets the bounds check, size encoding and immediate bits calculation
15370 /* If immediate is zero then we are a pseudo-instruction for
15371 VMOVN.I<size> <Dd>, <Qm> */
15374 inst
.operands
[2].present
= 0;
15375 inst
.instruction
= N_MNEM_vmovn
;
15380 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15381 _("immediate out of range for narrowing operation"));
15382 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15386 do_neon_shll (void)
15388 /* FIXME: Type checking when lengthening. */
15389 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15390 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15391 unsigned imm
= inst
.operands
[2].imm
;
15393 if (imm
== et
.size
)
15395 /* Maximum shift variant. */
15396 NEON_ENCODE (INTEGER
, inst
);
15397 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15398 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15399 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15400 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15401 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15403 neon_dp_fixup (&inst
);
15407 /* A more-specific type check for non-max versions. */
15408 et
= neon_check_type (2, NS_QDI
,
15409 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15410 NEON_ENCODE (IMMED
, inst
);
15411 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15415 /* Check the various types for the VCVT instruction, and return which version
15416 the current instruction is. */
15418 #define CVT_FLAVOUR_VAR \
15419 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15420 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15421 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15422 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15423 /* Half-precision conversions. */ \
15424 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15425 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15426 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15427 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15428 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15429 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15430 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15431 Compared with single/double precision variants, only the co-processor \
15432 field is different, so the encoding flow is reused here. */ \
15433 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15434 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15435 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15436 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15437 /* VFP instructions. */ \
15438 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15439 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15440 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15441 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15442 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15443 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15444 /* VFP instructions with bitshift. */ \
15445 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15446 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15447 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15448 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15449 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15450 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15451 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15452 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15454 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15455 neon_cvt_flavour_##C,
15457 /* The different types of conversions we can do. */
15458 enum neon_cvt_flavour
15461 neon_cvt_flavour_invalid
,
15462 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15467 static enum neon_cvt_flavour
15468 get_neon_cvt_flavour (enum neon_shape rs
)
15470 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15471 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15472 if (et.type != NT_invtype) \
15474 inst.error = NULL; \
15475 return (neon_cvt_flavour_##C); \
15478 struct neon_type_el et
;
15479 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15480 || rs
== NS_FF
) ? N_VFP
: 0;
15481 /* The instruction versions which take an immediate take one register
15482 argument, which is extended to the width of the full register. Thus the
15483 "source" and "destination" registers must have the same width. Hack that
15484 here by making the size equal to the key (wider, in this case) operand. */
15485 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15489 return neon_cvt_flavour_invalid
;
15504 /* Neon-syntax VFP conversions. */
15507 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15509 const char *opname
= 0;
15511 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15512 || rs
== NS_FHI
|| rs
== NS_HFI
)
15514 /* Conversions with immediate bitshift. */
15515 const char *enc
[] =
15517 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15523 if (flavour
< (int) ARRAY_SIZE (enc
))
15525 opname
= enc
[flavour
];
15526 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15527 _("operands 0 and 1 must be the same register"));
15528 inst
.operands
[1] = inst
.operands
[2];
15529 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15534 /* Conversions without bitshift. */
15535 const char *enc
[] =
15537 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15543 if (flavour
< (int) ARRAY_SIZE (enc
))
15544 opname
= enc
[flavour
];
15548 do_vfp_nsyn_opcode (opname
);
15550 /* ARMv8.2 fp16 VCVT instruction. */
15551 if (flavour
== neon_cvt_flavour_s32_f16
15552 || flavour
== neon_cvt_flavour_u32_f16
15553 || flavour
== neon_cvt_flavour_f16_u32
15554 || flavour
== neon_cvt_flavour_f16_s32
)
15555 do_scalar_fp16_v82_encode ();
15559 do_vfp_nsyn_cvtz (void)
15561 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15562 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15563 const char *enc
[] =
15565 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15571 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15572 do_vfp_nsyn_opcode (enc
[flavour
]);
15576 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15577 enum neon_cvt_mode mode
)
15582 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15583 D register operands. */
15584 if (flavour
== neon_cvt_flavour_s32_f64
15585 || flavour
== neon_cvt_flavour_u32_f64
)
15586 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15589 if (flavour
== neon_cvt_flavour_s32_f16
15590 || flavour
== neon_cvt_flavour_u32_f16
)
15591 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15594 set_it_insn_type (OUTSIDE_IT_INSN
);
15598 case neon_cvt_flavour_s32_f64
:
15602 case neon_cvt_flavour_s32_f32
:
15606 case neon_cvt_flavour_s32_f16
:
15610 case neon_cvt_flavour_u32_f64
:
15614 case neon_cvt_flavour_u32_f32
:
15618 case neon_cvt_flavour_u32_f16
:
15623 first_error (_("invalid instruction shape"));
15629 case neon_cvt_mode_a
: rm
= 0; break;
15630 case neon_cvt_mode_n
: rm
= 1; break;
15631 case neon_cvt_mode_p
: rm
= 2; break;
15632 case neon_cvt_mode_m
: rm
= 3; break;
15633 default: first_error (_("invalid rounding mode")); return;
15636 NEON_ENCODE (FPV8
, inst
);
15637 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15638 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15639 inst
.instruction
|= sz
<< 8;
15641 /* ARMv8.2 fp16 VCVT instruction. */
15642 if (flavour
== neon_cvt_flavour_s32_f16
15643 ||flavour
== neon_cvt_flavour_u32_f16
)
15644 do_scalar_fp16_v82_encode ();
15645 inst
.instruction
|= op
<< 7;
15646 inst
.instruction
|= rm
<< 16;
15647 inst
.instruction
|= 0xf0000000;
15648 inst
.is_neon
= TRUE
;
15652 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15654 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15655 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15656 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15658 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15660 if (flavour
== neon_cvt_flavour_invalid
)
15663 /* PR11109: Handle round-to-zero for VCVT conversions. */
15664 if (mode
== neon_cvt_mode_z
15665 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15666 && (flavour
== neon_cvt_flavour_s16_f16
15667 || flavour
== neon_cvt_flavour_u16_f16
15668 || flavour
== neon_cvt_flavour_s32_f32
15669 || flavour
== neon_cvt_flavour_u32_f32
15670 || flavour
== neon_cvt_flavour_s32_f64
15671 || flavour
== neon_cvt_flavour_u32_f64
)
15672 && (rs
== NS_FD
|| rs
== NS_FF
))
15674 do_vfp_nsyn_cvtz ();
15678 /* ARMv8.2 fp16 VCVT conversions. */
15679 if (mode
== neon_cvt_mode_z
15680 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15681 && (flavour
== neon_cvt_flavour_s32_f16
15682 || flavour
== neon_cvt_flavour_u32_f16
)
15685 do_vfp_nsyn_cvtz ();
15686 do_scalar_fp16_v82_encode ();
15690 /* VFP rather than Neon conversions. */
15691 if (flavour
>= neon_cvt_flavour_first_fp
)
15693 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15694 do_vfp_nsyn_cvt (rs
, flavour
);
15696 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15707 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15708 0x0000100, 0x1000100, 0x0, 0x1000000};
15710 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15713 /* Fixed-point conversion with #0 immediate is encoded as an
15714 integer conversion. */
15715 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15717 NEON_ENCODE (IMMED
, inst
);
15718 if (flavour
!= neon_cvt_flavour_invalid
)
15719 inst
.instruction
|= enctab
[flavour
];
15720 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15721 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15722 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15723 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15724 inst
.instruction
|= neon_quad (rs
) << 6;
15725 inst
.instruction
|= 1 << 21;
15726 if (flavour
< neon_cvt_flavour_s16_f16
)
15728 inst
.instruction
|= 1 << 21;
15729 immbits
= 32 - inst
.operands
[2].imm
;
15730 inst
.instruction
|= immbits
<< 16;
15734 inst
.instruction
|= 3 << 20;
15735 immbits
= 16 - inst
.operands
[2].imm
;
15736 inst
.instruction
|= immbits
<< 16;
15737 inst
.instruction
&= ~(1 << 9);
15740 neon_dp_fixup (&inst
);
15746 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15748 NEON_ENCODE (FLOAT
, inst
);
15749 set_it_insn_type (OUTSIDE_IT_INSN
);
15751 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15754 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15755 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15756 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15757 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15758 inst
.instruction
|= neon_quad (rs
) << 6;
15759 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15760 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15761 inst
.instruction
|= mode
<< 8;
15762 if (flavour
== neon_cvt_flavour_u16_f16
15763 || flavour
== neon_cvt_flavour_s16_f16
)
15764 /* Mask off the original size bits and reencode them. */
15765 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15768 inst
.instruction
|= 0xfc000000;
15770 inst
.instruction
|= 0xf0000000;
15776 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15777 0x100, 0x180, 0x0, 0x080};
15779 NEON_ENCODE (INTEGER
, inst
);
15781 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15784 if (flavour
!= neon_cvt_flavour_invalid
)
15785 inst
.instruction
|= enctab
[flavour
];
15787 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15788 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15789 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15790 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15791 inst
.instruction
|= neon_quad (rs
) << 6;
15792 if (flavour
>= neon_cvt_flavour_s16_f16
15793 && flavour
<= neon_cvt_flavour_f16_u16
)
15794 /* Half precision. */
15795 inst
.instruction
|= 1 << 18;
15797 inst
.instruction
|= 2 << 18;
15799 neon_dp_fixup (&inst
);
15804 /* Half-precision conversions for Advanced SIMD -- neon. */
15809 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15811 as_bad (_("operand size must match register width"));
15816 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15818 as_bad (_("operand size must match register width"));
15823 inst
.instruction
= 0x3b60600;
15825 inst
.instruction
= 0x3b60700;
15827 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15828 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15829 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15830 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15831 neon_dp_fixup (&inst
);
15835 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15836 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15837 do_vfp_nsyn_cvt (rs
, flavour
);
15839 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15844 do_neon_cvtr (void)
15846 do_neon_cvt_1 (neon_cvt_mode_x
);
15852 do_neon_cvt_1 (neon_cvt_mode_z
);
15856 do_neon_cvta (void)
15858 do_neon_cvt_1 (neon_cvt_mode_a
);
15862 do_neon_cvtn (void)
15864 do_neon_cvt_1 (neon_cvt_mode_n
);
15868 do_neon_cvtp (void)
15870 do_neon_cvt_1 (neon_cvt_mode_p
);
15874 do_neon_cvtm (void)
15876 do_neon_cvt_1 (neon_cvt_mode_m
);
15880 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15883 mark_feature_used (&fpu_vfp_ext_armv8
);
15885 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15886 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15887 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15888 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15889 inst
.instruction
|= to
? 0x10000 : 0;
15890 inst
.instruction
|= t
? 0x80 : 0;
15891 inst
.instruction
|= is_double
? 0x100 : 0;
15892 do_vfp_cond_or_thumb ();
15896 do_neon_cvttb_1 (bfd_boolean t
)
15898 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15899 NS_DF
, NS_DH
, NS_NULL
);
15903 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15906 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15908 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15911 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15913 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15915 /* The VCVTB and VCVTT instructions with D-register operands
15916 don't work for SP only targets. */
15917 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15921 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15923 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15925 /* The VCVTB and VCVTT instructions with D-register operands
15926 don't work for SP only targets. */
15927 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15931 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15938 do_neon_cvtb (void)
15940 do_neon_cvttb_1 (FALSE
);
15945 do_neon_cvtt (void)
15947 do_neon_cvttb_1 (TRUE
);
15951 neon_move_immediate (void)
15953 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15954 struct neon_type_el et
= neon_check_type (2, rs
,
15955 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15956 unsigned immlo
, immhi
= 0, immbits
;
15957 int op
, cmode
, float_p
;
15959 constraint (et
.type
== NT_invtype
,
15960 _("operand size must be specified for immediate VMOV"));
15962 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15963 op
= (inst
.instruction
& (1 << 5)) != 0;
15965 immlo
= inst
.operands
[1].imm
;
15966 if (inst
.operands
[1].regisimm
)
15967 immhi
= inst
.operands
[1].reg
;
15969 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15970 _("immediate has bits set outside the operand size"));
15972 float_p
= inst
.operands
[1].immisfloat
;
15974 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15975 et
.size
, et
.type
)) == FAIL
)
15977 /* Invert relevant bits only. */
15978 neon_invert_size (&immlo
, &immhi
, et
.size
);
15979 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15980 with one or the other; those cases are caught by
15981 neon_cmode_for_move_imm. */
15983 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15984 &op
, et
.size
, et
.type
)) == FAIL
)
15986 first_error (_("immediate out of range"));
15991 inst
.instruction
&= ~(1 << 5);
15992 inst
.instruction
|= op
<< 5;
15994 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15995 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15996 inst
.instruction
|= neon_quad (rs
) << 6;
15997 inst
.instruction
|= cmode
<< 8;
15999 neon_write_immbits (immbits
);
16005 if (inst
.operands
[1].isreg
)
16007 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16009 NEON_ENCODE (INTEGER
, inst
);
16010 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16011 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16012 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16013 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16014 inst
.instruction
|= neon_quad (rs
) << 6;
16018 NEON_ENCODE (IMMED
, inst
);
16019 neon_move_immediate ();
16022 neon_dp_fixup (&inst
);
16025 /* Encode instructions of form:
16027 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16028 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16031 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16033 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16034 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16035 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16036 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16037 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16038 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16039 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16040 inst
.instruction
|= neon_logbits (size
) << 20;
16042 neon_dp_fixup (&inst
);
16046 do_neon_dyadic_long (void)
16048 /* FIXME: Type checking for lengthening op. */
16049 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16050 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16051 neon_mixed_length (et
, et
.size
);
16055 do_neon_abal (void)
16057 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16058 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16059 neon_mixed_length (et
, et
.size
);
16063 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16065 if (inst
.operands
[2].isscalar
)
16067 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16068 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16069 NEON_ENCODE (SCALAR
, inst
);
16070 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16074 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16075 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16076 NEON_ENCODE (INTEGER
, inst
);
16077 neon_mixed_length (et
, et
.size
);
16082 do_neon_mac_maybe_scalar_long (void)
16084 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16088 do_neon_dyadic_wide (void)
16090 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16091 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16092 neon_mixed_length (et
, et
.size
);
16096 do_neon_dyadic_narrow (void)
16098 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16099 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16100 /* Operand sign is unimportant, and the U bit is part of the opcode,
16101 so force the operand type to integer. */
16102 et
.type
= NT_integer
;
16103 neon_mixed_length (et
, et
.size
/ 2);
16107 do_neon_mul_sat_scalar_long (void)
16109 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16113 do_neon_vmull (void)
16115 if (inst
.operands
[2].isscalar
)
16116 do_neon_mac_maybe_scalar_long ();
16119 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16120 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16122 if (et
.type
== NT_poly
)
16123 NEON_ENCODE (POLY
, inst
);
16125 NEON_ENCODE (INTEGER
, inst
);
16127 /* For polynomial encoding the U bit must be zero, and the size must
16128 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16129 obviously, as 0b10). */
16132 /* Check we're on the correct architecture. */
16133 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16135 _("Instruction form not available on this architecture.");
16140 neon_mixed_length (et
, et
.size
);
16147 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16148 struct neon_type_el et
= neon_check_type (3, rs
,
16149 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16150 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16152 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16153 _("shift out of range"));
16154 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16155 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16156 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16157 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16158 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16159 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16160 inst
.instruction
|= neon_quad (rs
) << 6;
16161 inst
.instruction
|= imm
<< 8;
16163 neon_dp_fixup (&inst
);
16169 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16170 struct neon_type_el et
= neon_check_type (2, rs
,
16171 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16172 unsigned op
= (inst
.instruction
>> 7) & 3;
16173 /* N (width of reversed regions) is encoded as part of the bitmask. We
16174 extract it here to check the elements to be reversed are smaller.
16175 Otherwise we'd get a reserved instruction. */
16176 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16177 gas_assert (elsize
!= 0);
16178 constraint (et
.size
>= elsize
,
16179 _("elements must be smaller than reversal region"));
16180 neon_two_same (neon_quad (rs
), 1, et
.size
);
16186 if (inst
.operands
[1].isscalar
)
16188 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16189 struct neon_type_el et
= neon_check_type (2, rs
,
16190 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16191 unsigned sizebits
= et
.size
>> 3;
16192 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16193 int logsize
= neon_logbits (et
.size
);
16194 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16196 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16199 NEON_ENCODE (SCALAR
, inst
);
16200 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16201 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16202 inst
.instruction
|= LOW4 (dm
);
16203 inst
.instruction
|= HI1 (dm
) << 5;
16204 inst
.instruction
|= neon_quad (rs
) << 6;
16205 inst
.instruction
|= x
<< 17;
16206 inst
.instruction
|= sizebits
<< 16;
16208 neon_dp_fixup (&inst
);
16212 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16213 struct neon_type_el et
= neon_check_type (2, rs
,
16214 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16215 /* Duplicate ARM register to lanes of vector. */
16216 NEON_ENCODE (ARMREG
, inst
);
16219 case 8: inst
.instruction
|= 0x400000; break;
16220 case 16: inst
.instruction
|= 0x000020; break;
16221 case 32: inst
.instruction
|= 0x000000; break;
16224 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16225 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16226 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16227 inst
.instruction
|= neon_quad (rs
) << 21;
16228 /* The encoding for this instruction is identical for the ARM and Thumb
16229 variants, except for the condition field. */
16230 do_vfp_cond_or_thumb ();
16234 /* VMOV has particularly many variations. It can be one of:
16235 0. VMOV<c><q> <Qd>, <Qm>
16236 1. VMOV<c><q> <Dd>, <Dm>
16237 (Register operations, which are VORR with Rm = Rn.)
16238 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16239 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16241 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16242 (ARM register to scalar.)
16243 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16244 (Two ARM registers to vector.)
16245 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16246 (Scalar to ARM register.)
16247 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16248 (Vector to two ARM registers.)
16249 8. VMOV.F32 <Sd>, <Sm>
16250 9. VMOV.F64 <Dd>, <Dm>
16251 (VFP register moves.)
16252 10. VMOV.F32 <Sd>, #imm
16253 11. VMOV.F64 <Dd>, #imm
16254 (VFP float immediate load.)
16255 12. VMOV <Rd>, <Sm>
16256 (VFP single to ARM reg.)
16257 13. VMOV <Sd>, <Rm>
16258 (ARM reg to VFP single.)
16259 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16260 (Two ARM regs to two VFP singles.)
16261 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16262 (Two VFP singles to two ARM regs.)
16264 These cases can be disambiguated using neon_select_shape, except cases 1/9
16265 and 3/11 which depend on the operand type too.
16267 All the encoded bits are hardcoded by this function.
16269 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16270 Cases 5, 7 may be used with VFPv2 and above.
16272 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16273 can specify a type where it doesn't make sense to, and is ignored). */
16278 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16279 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16280 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16281 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16282 struct neon_type_el et
;
16283 const char *ldconst
= 0;
16287 case NS_DD
: /* case 1/9. */
16288 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16289 /* It is not an error here if no type is given. */
16291 if (et
.type
== NT_float
&& et
.size
== 64)
16293 do_vfp_nsyn_opcode ("fcpyd");
16296 /* fall through. */
16298 case NS_QQ
: /* case 0/1. */
16300 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16302 /* The architecture manual I have doesn't explicitly state which
16303 value the U bit should have for register->register moves, but
16304 the equivalent VORR instruction has U = 0, so do that. */
16305 inst
.instruction
= 0x0200110;
16306 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16307 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16308 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16309 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16310 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16311 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16312 inst
.instruction
|= neon_quad (rs
) << 6;
16314 neon_dp_fixup (&inst
);
16318 case NS_DI
: /* case 3/11. */
16319 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16321 if (et
.type
== NT_float
&& et
.size
== 64)
16323 /* case 11 (fconstd). */
16324 ldconst
= "fconstd";
16325 goto encode_fconstd
;
16327 /* fall through. */
16329 case NS_QI
: /* case 2/3. */
16330 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16332 inst
.instruction
= 0x0800010;
16333 neon_move_immediate ();
16334 neon_dp_fixup (&inst
);
16337 case NS_SR
: /* case 4. */
16339 unsigned bcdebits
= 0;
16341 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16342 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16344 /* .<size> is optional here, defaulting to .32. */
16345 if (inst
.vectype
.elems
== 0
16346 && inst
.operands
[0].vectype
.type
== NT_invtype
16347 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16349 inst
.vectype
.el
[0].type
= NT_untyped
;
16350 inst
.vectype
.el
[0].size
= 32;
16351 inst
.vectype
.elems
= 1;
16354 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16355 logsize
= neon_logbits (et
.size
);
16357 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16359 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16360 && et
.size
!= 32, _(BAD_FPU
));
16361 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16362 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16366 case 8: bcdebits
= 0x8; break;
16367 case 16: bcdebits
= 0x1; break;
16368 case 32: bcdebits
= 0x0; break;
16372 bcdebits
|= x
<< logsize
;
16374 inst
.instruction
= 0xe000b10;
16375 do_vfp_cond_or_thumb ();
16376 inst
.instruction
|= LOW4 (dn
) << 16;
16377 inst
.instruction
|= HI1 (dn
) << 7;
16378 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16379 inst
.instruction
|= (bcdebits
& 3) << 5;
16380 inst
.instruction
|= (bcdebits
>> 2) << 21;
16384 case NS_DRR
: /* case 5 (fmdrr). */
16385 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16388 inst
.instruction
= 0xc400b10;
16389 do_vfp_cond_or_thumb ();
16390 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16391 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16392 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16393 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16396 case NS_RS
: /* case 6. */
16399 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16400 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16401 unsigned abcdebits
= 0;
16403 /* .<dt> is optional here, defaulting to .32. */
16404 if (inst
.vectype
.elems
== 0
16405 && inst
.operands
[0].vectype
.type
== NT_invtype
16406 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16408 inst
.vectype
.el
[0].type
= NT_untyped
;
16409 inst
.vectype
.el
[0].size
= 32;
16410 inst
.vectype
.elems
= 1;
16413 et
= neon_check_type (2, NS_NULL
,
16414 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16415 logsize
= neon_logbits (et
.size
);
16417 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16419 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16420 && et
.size
!= 32, _(BAD_FPU
));
16421 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16422 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16426 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16427 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16428 case 32: abcdebits
= 0x00; break;
16432 abcdebits
|= x
<< logsize
;
16433 inst
.instruction
= 0xe100b10;
16434 do_vfp_cond_or_thumb ();
16435 inst
.instruction
|= LOW4 (dn
) << 16;
16436 inst
.instruction
|= HI1 (dn
) << 7;
16437 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16438 inst
.instruction
|= (abcdebits
& 3) << 5;
16439 inst
.instruction
|= (abcdebits
>> 2) << 21;
16443 case NS_RRD
: /* case 7 (fmrrd). */
16444 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16447 inst
.instruction
= 0xc500b10;
16448 do_vfp_cond_or_thumb ();
16449 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16450 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16451 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16452 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16455 case NS_FF
: /* case 8 (fcpys). */
16456 do_vfp_nsyn_opcode ("fcpys");
16460 case NS_FI
: /* case 10 (fconsts). */
16461 ldconst
= "fconsts";
16463 if (is_quarter_float (inst
.operands
[1].imm
))
16465 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16466 do_vfp_nsyn_opcode (ldconst
);
16468 /* ARMv8.2 fp16 vmov.f16 instruction. */
16470 do_scalar_fp16_v82_encode ();
16473 first_error (_("immediate out of range"));
16477 case NS_RF
: /* case 12 (fmrs). */
16478 do_vfp_nsyn_opcode ("fmrs");
16479 /* ARMv8.2 fp16 vmov.f16 instruction. */
16481 do_scalar_fp16_v82_encode ();
16485 case NS_FR
: /* case 13 (fmsr). */
16486 do_vfp_nsyn_opcode ("fmsr");
16487 /* ARMv8.2 fp16 vmov.f16 instruction. */
16489 do_scalar_fp16_v82_encode ();
16492 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16493 (one of which is a list), but we have parsed four. Do some fiddling to
16494 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16496 case NS_RRFF
: /* case 14 (fmrrs). */
16497 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16498 _("VFP registers must be adjacent"));
16499 inst
.operands
[2].imm
= 2;
16500 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16501 do_vfp_nsyn_opcode ("fmrrs");
16504 case NS_FFRR
: /* case 15 (fmsrr). */
16505 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16506 _("VFP registers must be adjacent"));
16507 inst
.operands
[1] = inst
.operands
[2];
16508 inst
.operands
[2] = inst
.operands
[3];
16509 inst
.operands
[0].imm
= 2;
16510 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16511 do_vfp_nsyn_opcode ("fmsrr");
16515 /* neon_select_shape has determined that the instruction
16516 shape is wrong and has already set the error message. */
16525 do_neon_rshift_round_imm (void)
16527 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16528 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16529 int imm
= inst
.operands
[2].imm
;
16531 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16534 inst
.operands
[2].present
= 0;
16539 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16540 _("immediate out of range for shift"));
16541 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16546 do_neon_movhf (void)
16548 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16549 constraint (rs
!= NS_HH
, _("invalid suffix"));
16551 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16554 do_vfp_sp_monadic ();
16557 inst
.instruction
|= 0xf0000000;
16561 do_neon_movl (void)
16563 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16564 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16565 unsigned sizebits
= et
.size
>> 3;
16566 inst
.instruction
|= sizebits
<< 19;
16567 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16573 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16574 struct neon_type_el et
= neon_check_type (2, rs
,
16575 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16576 NEON_ENCODE (INTEGER
, inst
);
16577 neon_two_same (neon_quad (rs
), 1, et
.size
);
16581 do_neon_zip_uzp (void)
16583 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16584 struct neon_type_el et
= neon_check_type (2, rs
,
16585 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16586 if (rs
== NS_DD
&& et
.size
== 32)
16588 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16589 inst
.instruction
= N_MNEM_vtrn
;
16593 neon_two_same (neon_quad (rs
), 1, et
.size
);
16597 do_neon_sat_abs_neg (void)
16599 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16600 struct neon_type_el et
= neon_check_type (2, rs
,
16601 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16602 neon_two_same (neon_quad (rs
), 1, et
.size
);
16606 do_neon_pair_long (void)
16608 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16609 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16610 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16611 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16612 neon_two_same (neon_quad (rs
), 1, et
.size
);
16616 do_neon_recip_est (void)
16618 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16619 struct neon_type_el et
= neon_check_type (2, rs
,
16620 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16621 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16622 neon_two_same (neon_quad (rs
), 1, et
.size
);
16628 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16629 struct neon_type_el et
= neon_check_type (2, rs
,
16630 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16631 neon_two_same (neon_quad (rs
), 1, et
.size
);
16637 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16638 struct neon_type_el et
= neon_check_type (2, rs
,
16639 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16640 neon_two_same (neon_quad (rs
), 1, et
.size
);
16646 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16647 struct neon_type_el et
= neon_check_type (2, rs
,
16648 N_EQK
| N_INT
, N_8
| N_KEY
);
16649 neon_two_same (neon_quad (rs
), 1, et
.size
);
16655 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16656 neon_two_same (neon_quad (rs
), 1, -1);
16660 do_neon_tbl_tbx (void)
16662 unsigned listlenbits
;
16663 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16665 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16667 first_error (_("bad list length for table lookup"));
16671 listlenbits
= inst
.operands
[1].imm
- 1;
16672 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16673 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16674 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16675 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16676 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16677 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16678 inst
.instruction
|= listlenbits
<< 8;
16680 neon_dp_fixup (&inst
);
16684 do_neon_ldm_stm (void)
16686 /* P, U and L bits are part of bitmask. */
16687 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16688 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16690 if (inst
.operands
[1].issingle
)
16692 do_vfp_nsyn_ldm_stm (is_dbmode
);
16696 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16697 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16699 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16700 _("register list must contain at least 1 and at most 16 "
16703 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16704 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16705 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16706 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16708 inst
.instruction
|= offsetbits
;
16710 do_vfp_cond_or_thumb ();
16714 do_neon_ldr_str (void)
16716 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16718 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16719 And is UNPREDICTABLE in thumb mode. */
16721 && inst
.operands
[1].reg
== REG_PC
16722 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16725 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16726 else if (warn_on_deprecated
)
16727 as_tsktsk (_("Use of PC here is deprecated"));
16730 if (inst
.operands
[0].issingle
)
16733 do_vfp_nsyn_opcode ("flds");
16735 do_vfp_nsyn_opcode ("fsts");
16737 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16738 if (inst
.vectype
.el
[0].size
== 16)
16739 do_scalar_fp16_v82_encode ();
16744 do_vfp_nsyn_opcode ("fldd");
16746 do_vfp_nsyn_opcode ("fstd");
16750 /* "interleave" version also handles non-interleaving register VLD1/VST1
16754 do_neon_ld_st_interleave (void)
16756 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16757 N_8
| N_16
| N_32
| N_64
);
16758 unsigned alignbits
= 0;
16760 /* The bits in this table go:
16761 0: register stride of one (0) or two (1)
16762 1,2: register list length, minus one (1, 2, 3, 4).
16763 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16764 We use -1 for invalid entries. */
16765 const int typetable
[] =
16767 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16768 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16769 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16770 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16774 if (et
.type
== NT_invtype
)
16777 if (inst
.operands
[1].immisalign
)
16778 switch (inst
.operands
[1].imm
>> 8)
16780 case 64: alignbits
= 1; break;
16782 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16783 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16784 goto bad_alignment
;
16788 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16789 goto bad_alignment
;
16794 first_error (_("bad alignment"));
16798 inst
.instruction
|= alignbits
<< 4;
16799 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16801 /* Bits [4:6] of the immediate in a list specifier encode register stride
16802 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16803 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16804 up the right value for "type" in a table based on this value and the given
16805 list style, then stick it back. */
16806 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16807 | (((inst
.instruction
>> 8) & 3) << 3);
16809 typebits
= typetable
[idx
];
16811 constraint (typebits
== -1, _("bad list type for instruction"));
16812 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16813 _("bad element type for instruction"));
16815 inst
.instruction
&= ~0xf00;
16816 inst
.instruction
|= typebits
<< 8;
16819 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16820 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16821 otherwise. The variable arguments are a list of pairs of legal (size, align)
16822 values, terminated with -1. */
16825 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16828 int result
= FAIL
, thissize
, thisalign
;
16830 if (!inst
.operands
[1].immisalign
)
16836 va_start (ap
, do_alignment
);
16840 thissize
= va_arg (ap
, int);
16841 if (thissize
== -1)
16843 thisalign
= va_arg (ap
, int);
16845 if (size
== thissize
&& align
== thisalign
)
16848 while (result
!= SUCCESS
);
16852 if (result
== SUCCESS
)
16855 first_error (_("unsupported alignment for instruction"));
16861 do_neon_ld_st_lane (void)
16863 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16864 int align_good
, do_alignment
= 0;
16865 int logsize
= neon_logbits (et
.size
);
16866 int align
= inst
.operands
[1].imm
>> 8;
16867 int n
= (inst
.instruction
>> 8) & 3;
16868 int max_el
= 64 / et
.size
;
16870 if (et
.type
== NT_invtype
)
16873 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16874 _("bad list length"));
16875 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16876 _("scalar index out of range"));
16877 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16879 _("stride of 2 unavailable when element size is 8"));
16883 case 0: /* VLD1 / VST1. */
16884 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16886 if (align_good
== FAIL
)
16890 unsigned alignbits
= 0;
16893 case 16: alignbits
= 0x1; break;
16894 case 32: alignbits
= 0x3; break;
16897 inst
.instruction
|= alignbits
<< 4;
16901 case 1: /* VLD2 / VST2. */
16902 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16903 16, 32, 32, 64, -1);
16904 if (align_good
== FAIL
)
16907 inst
.instruction
|= 1 << 4;
16910 case 2: /* VLD3 / VST3. */
16911 constraint (inst
.operands
[1].immisalign
,
16912 _("can't use alignment with this instruction"));
16915 case 3: /* VLD4 / VST4. */
16916 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16917 16, 64, 32, 64, 32, 128, -1);
16918 if (align_good
== FAIL
)
16922 unsigned alignbits
= 0;
16925 case 8: alignbits
= 0x1; break;
16926 case 16: alignbits
= 0x1; break;
16927 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16930 inst
.instruction
|= alignbits
<< 4;
16937 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16938 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16939 inst
.instruction
|= 1 << (4 + logsize
);
16941 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16942 inst
.instruction
|= logsize
<< 10;
16945 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16948 do_neon_ld_dup (void)
16950 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16951 int align_good
, do_alignment
= 0;
16953 if (et
.type
== NT_invtype
)
16956 switch ((inst
.instruction
>> 8) & 3)
16958 case 0: /* VLD1. */
16959 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16960 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16961 &do_alignment
, 16, 16, 32, 32, -1);
16962 if (align_good
== FAIL
)
16964 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16967 case 2: inst
.instruction
|= 1 << 5; break;
16968 default: first_error (_("bad list length")); return;
16970 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16973 case 1: /* VLD2. */
16974 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16975 &do_alignment
, 8, 16, 16, 32, 32, 64,
16977 if (align_good
== FAIL
)
16979 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16980 _("bad list length"));
16981 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16982 inst
.instruction
|= 1 << 5;
16983 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16986 case 2: /* VLD3. */
16987 constraint (inst
.operands
[1].immisalign
,
16988 _("can't use alignment with this instruction"));
16989 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16990 _("bad list length"));
16991 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16992 inst
.instruction
|= 1 << 5;
16993 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16996 case 3: /* VLD4. */
16998 int align
= inst
.operands
[1].imm
>> 8;
16999 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17000 16, 64, 32, 64, 32, 128, -1);
17001 if (align_good
== FAIL
)
17003 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17004 _("bad list length"));
17005 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17006 inst
.instruction
|= 1 << 5;
17007 if (et
.size
== 32 && align
== 128)
17008 inst
.instruction
|= 0x3 << 6;
17010 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17017 inst
.instruction
|= do_alignment
<< 4;
17020 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17021 apart from bits [11:4]. */
17024 do_neon_ldx_stx (void)
17026 if (inst
.operands
[1].isreg
)
17027 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17029 switch (NEON_LANE (inst
.operands
[0].imm
))
17031 case NEON_INTERLEAVE_LANES
:
17032 NEON_ENCODE (INTERLV
, inst
);
17033 do_neon_ld_st_interleave ();
17036 case NEON_ALL_LANES
:
17037 NEON_ENCODE (DUP
, inst
);
17038 if (inst
.instruction
== N_INV
)
17040 first_error ("only loads support such operands");
17047 NEON_ENCODE (LANE
, inst
);
17048 do_neon_ld_st_lane ();
17051 /* L bit comes from bit mask. */
17052 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17053 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17054 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17056 if (inst
.operands
[1].postind
)
17058 int postreg
= inst
.operands
[1].imm
& 0xf;
17059 constraint (!inst
.operands
[1].immisreg
,
17060 _("post-index must be a register"));
17061 constraint (postreg
== 0xd || postreg
== 0xf,
17062 _("bad register for post-index"));
17063 inst
.instruction
|= postreg
;
17067 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17068 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17069 || inst
.reloc
.exp
.X_add_number
!= 0,
17072 if (inst
.operands
[1].writeback
)
17074 inst
.instruction
|= 0xd;
17077 inst
.instruction
|= 0xf;
17081 inst
.instruction
|= 0xf9000000;
17083 inst
.instruction
|= 0xf4000000;
17088 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17090 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17091 D register operands. */
17092 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17093 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17096 NEON_ENCODE (FPV8
, inst
);
17098 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17100 do_vfp_sp_dyadic ();
17102 /* ARMv8.2 fp16 instruction. */
17104 do_scalar_fp16_v82_encode ();
17107 do_vfp_dp_rd_rn_rm ();
17110 inst
.instruction
|= 0x100;
17112 inst
.instruction
|= 0xf0000000;
17118 set_it_insn_type (OUTSIDE_IT_INSN
);
17120 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17121 first_error (_("invalid instruction shape"));
17127 set_it_insn_type (OUTSIDE_IT_INSN
);
17129 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17132 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17135 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17139 do_vrint_1 (enum neon_cvt_mode mode
)
17141 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17142 struct neon_type_el et
;
17147 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17148 D register operands. */
17149 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17150 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17153 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17155 if (et
.type
!= NT_invtype
)
17157 /* VFP encodings. */
17158 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17159 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17160 set_it_insn_type (OUTSIDE_IT_INSN
);
17162 NEON_ENCODE (FPV8
, inst
);
17163 if (rs
== NS_FF
|| rs
== NS_HH
)
17164 do_vfp_sp_monadic ();
17166 do_vfp_dp_rd_rm ();
17170 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17171 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17172 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17173 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17174 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17175 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17176 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17180 inst
.instruction
|= (rs
== NS_DD
) << 8;
17181 do_vfp_cond_or_thumb ();
17183 /* ARMv8.2 fp16 vrint instruction. */
17185 do_scalar_fp16_v82_encode ();
17189 /* Neon encodings (or something broken...). */
17191 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17193 if (et
.type
== NT_invtype
)
17196 set_it_insn_type (OUTSIDE_IT_INSN
);
17197 NEON_ENCODE (FLOAT
, inst
);
17199 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17202 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17203 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17204 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17205 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17206 inst
.instruction
|= neon_quad (rs
) << 6;
17207 /* Mask off the original size bits and reencode them. */
17208 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17209 | neon_logbits (et
.size
) << 18);
17213 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17214 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17215 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17216 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17217 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17218 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17219 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17224 inst
.instruction
|= 0xfc000000;
17226 inst
.instruction
|= 0xf0000000;
17233 do_vrint_1 (neon_cvt_mode_x
);
17239 do_vrint_1 (neon_cvt_mode_z
);
17245 do_vrint_1 (neon_cvt_mode_r
);
17251 do_vrint_1 (neon_cvt_mode_a
);
17257 do_vrint_1 (neon_cvt_mode_n
);
17263 do_vrint_1 (neon_cvt_mode_p
);
17269 do_vrint_1 (neon_cvt_mode_m
);
17273 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17275 unsigned regno
= NEON_SCALAR_REG (opnd
);
17276 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17278 if (elsize
== 16 && elno
< 2 && regno
< 16)
17279 return regno
| (elno
<< 4);
17280 else if (elsize
== 32 && elno
== 0)
17283 first_error (_("scalar out of range"));
17290 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17292 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17293 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17294 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17295 _("immediate out of range"));
17297 if (inst
.operands
[2].isscalar
)
17299 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17300 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17301 N_KEY
| N_F16
| N_F32
).size
;
17302 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17304 inst
.instruction
= 0xfe000800;
17305 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17306 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17307 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17308 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17309 inst
.instruction
|= LOW4 (m
);
17310 inst
.instruction
|= HI1 (m
) << 5;
17311 inst
.instruction
|= neon_quad (rs
) << 6;
17312 inst
.instruction
|= rot
<< 20;
17313 inst
.instruction
|= (size
== 32) << 23;
17317 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17318 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17319 N_KEY
| N_F16
| N_F32
).size
;
17320 neon_three_same (neon_quad (rs
), 0, -1);
17321 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17322 inst
.instruction
|= 0xfc200800;
17323 inst
.instruction
|= rot
<< 23;
17324 inst
.instruction
|= (size
== 32) << 20;
17331 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17333 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17334 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17335 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17336 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17337 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17338 N_KEY
| N_F16
| N_F32
).size
;
17339 neon_three_same (neon_quad (rs
), 0, -1);
17340 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17341 inst
.instruction
|= 0xfc800800;
17342 inst
.instruction
|= (rot
== 270) << 24;
17343 inst
.instruction
|= (size
== 32) << 20;
17346 /* Crypto v1 instructions. */
17348 do_crypto_2op_1 (unsigned elttype
, int op
)
17350 set_it_insn_type (OUTSIDE_IT_INSN
);
17352 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17358 NEON_ENCODE (INTEGER
, inst
);
17359 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17360 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17361 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17362 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17364 inst
.instruction
|= op
<< 6;
17367 inst
.instruction
|= 0xfc000000;
17369 inst
.instruction
|= 0xf0000000;
17373 do_crypto_3op_1 (int u
, int op
)
17375 set_it_insn_type (OUTSIDE_IT_INSN
);
17377 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17378 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17383 NEON_ENCODE (INTEGER
, inst
);
17384 neon_three_same (1, u
, 8 << op
);
17390 do_crypto_2op_1 (N_8
, 0);
17396 do_crypto_2op_1 (N_8
, 1);
17402 do_crypto_2op_1 (N_8
, 2);
17408 do_crypto_2op_1 (N_8
, 3);
17414 do_crypto_3op_1 (0, 0);
17420 do_crypto_3op_1 (0, 1);
17426 do_crypto_3op_1 (0, 2);
17432 do_crypto_3op_1 (0, 3);
17438 do_crypto_3op_1 (1, 0);
17444 do_crypto_3op_1 (1, 1);
17448 do_sha256su1 (void)
17450 do_crypto_3op_1 (1, 2);
17456 do_crypto_2op_1 (N_32
, -1);
17462 do_crypto_2op_1 (N_32
, 0);
17466 do_sha256su0 (void)
17468 do_crypto_2op_1 (N_32
, 1);
17472 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17474 unsigned int Rd
= inst
.operands
[0].reg
;
17475 unsigned int Rn
= inst
.operands
[1].reg
;
17476 unsigned int Rm
= inst
.operands
[2].reg
;
17478 set_it_insn_type (OUTSIDE_IT_INSN
);
17479 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17480 inst
.instruction
|= LOW4 (Rn
) << 16;
17481 inst
.instruction
|= LOW4 (Rm
);
17482 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17483 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17485 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17486 as_warn (UNPRED_REG ("r15"));
17487 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17488 as_warn (UNPRED_REG ("r13"));
17530 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17532 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17533 do_vfp_sp_dp_cvt ();
17534 do_vfp_cond_or_thumb ();
17538 /* Overall per-instruction processing. */
17540 /* We need to be able to fix up arbitrary expressions in some statements.
17541 This is so that we can handle symbols that are an arbitrary distance from
17542 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17543 which returns part of an address in a form which will be valid for
17544 a data instruction. We do this by pushing the expression into a symbol
17545 in the expr_section, and creating a fix for that. */
17548 fix_new_arm (fragS
* frag
,
17562 /* Create an absolute valued symbol, so we have something to
17563 refer to in the object file. Unfortunately for us, gas's
17564 generic expression parsing will already have folded out
17565 any use of .set foo/.type foo %function that may have
17566 been used to set type information of the target location,
17567 that's being specified symbolically. We have to presume
17568 the user knows what they are doing. */
17572 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17574 symbol
= symbol_find_or_make (name
);
17575 S_SET_SEGMENT (symbol
, absolute_section
);
17576 symbol_set_frag (symbol
, &zero_address_frag
);
17577 S_SET_VALUE (symbol
, exp
->X_add_number
);
17578 exp
->X_op
= O_symbol
;
17579 exp
->X_add_symbol
= symbol
;
17580 exp
->X_add_number
= 0;
17586 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17587 (enum bfd_reloc_code_real
) reloc
);
17591 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17592 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17596 /* Mark whether the fix is to a THUMB instruction, or an ARM
17598 new_fix
->tc_fix_data
= thumb_mode
;
17601 /* Create a frg for an instruction requiring relaxation. */
17603 output_relax_insn (void)
17609 /* The size of the instruction is unknown, so tie the debug info to the
17610 start of the instruction. */
17611 dwarf2_emit_insn (0);
17613 switch (inst
.reloc
.exp
.X_op
)
17616 sym
= inst
.reloc
.exp
.X_add_symbol
;
17617 offset
= inst
.reloc
.exp
.X_add_number
;
17621 offset
= inst
.reloc
.exp
.X_add_number
;
17624 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17628 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17629 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17630 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17633 /* Write a 32-bit thumb instruction to buf. */
17635 put_thumb32_insn (char * buf
, unsigned long insn
)
17637 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17638 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17642 output_inst (const char * str
)
17648 as_bad ("%s -- `%s'", inst
.error
, str
);
17653 output_relax_insn ();
17656 if (inst
.size
== 0)
17659 to
= frag_more (inst
.size
);
17660 /* PR 9814: Record the thumb mode into the current frag so that we know
17661 what type of NOP padding to use, if necessary. We override any previous
17662 setting so that if the mode has changed then the NOPS that we use will
17663 match the encoding of the last instruction in the frag. */
17664 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17666 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17668 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17669 put_thumb32_insn (to
, inst
.instruction
);
17671 else if (inst
.size
> INSN_SIZE
)
17673 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17674 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17675 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17678 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17680 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17681 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17682 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17685 dwarf2_emit_insn (inst
.size
);
17689 output_it_inst (int cond
, int mask
, char * to
)
17691 unsigned long instruction
= 0xbf00;
17694 instruction
|= mask
;
17695 instruction
|= cond
<< 4;
17699 to
= frag_more (2);
17701 dwarf2_emit_insn (2);
17705 md_number_to_chars (to
, instruction
, 2);
17710 /* Tag values used in struct asm_opcode's tag field. */
17713 OT_unconditional
, /* Instruction cannot be conditionalized.
17714 The ARM condition field is still 0xE. */
17715 OT_unconditionalF
, /* Instruction cannot be conditionalized
17716 and carries 0xF in its ARM condition field. */
17717 OT_csuffix
, /* Instruction takes a conditional suffix. */
17718 OT_csuffixF
, /* Some forms of the instruction take a conditional
17719 suffix, others place 0xF where the condition field
17721 OT_cinfix3
, /* Instruction takes a conditional infix,
17722 beginning at character index 3. (In
17723 unified mode, it becomes a suffix.) */
17724 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17725 tsts, cmps, cmns, and teqs. */
17726 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17727 character index 3, even in unified mode. Used for
17728 legacy instructions where suffix and infix forms
17729 may be ambiguous. */
17730 OT_csuf_or_in3
, /* Instruction takes either a conditional
17731 suffix or an infix at character index 3. */
17732 OT_odd_infix_unc
, /* This is the unconditional variant of an
17733 instruction that takes a conditional infix
17734 at an unusual position. In unified mode,
17735 this variant will accept a suffix. */
17736 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17737 are the conditional variants of instructions that
17738 take conditional infixes in unusual positions.
17739 The infix appears at character index
17740 (tag - OT_odd_infix_0). These are not accepted
17741 in unified mode. */
17744 /* Subroutine of md_assemble, responsible for looking up the primary
17745 opcode from the mnemonic the user wrote. STR points to the
17746 beginning of the mnemonic.
17748 This is not simply a hash table lookup, because of conditional
17749 variants. Most instructions have conditional variants, which are
17750 expressed with a _conditional affix_ to the mnemonic. If we were
17751 to encode each conditional variant as a literal string in the opcode
17752 table, it would have approximately 20,000 entries.
17754 Most mnemonics take this affix as a suffix, and in unified syntax,
17755 'most' is upgraded to 'all'. However, in the divided syntax, some
17756 instructions take the affix as an infix, notably the s-variants of
17757 the arithmetic instructions. Of those instructions, all but six
17758 have the infix appear after the third character of the mnemonic.
17760 Accordingly, the algorithm for looking up primary opcodes given
17763 1. Look up the identifier in the opcode table.
17764 If we find a match, go to step U.
17766 2. Look up the last two characters of the identifier in the
17767 conditions table. If we find a match, look up the first N-2
17768 characters of the identifier in the opcode table. If we
17769 find a match, go to step CE.
17771 3. Look up the fourth and fifth characters of the identifier in
17772 the conditions table. If we find a match, extract those
17773 characters from the identifier, and look up the remaining
17774 characters in the opcode table. If we find a match, go
17779 U. Examine the tag field of the opcode structure, in case this is
17780 one of the six instructions with its conditional infix in an
17781 unusual place. If it is, the tag tells us where to find the
17782 infix; look it up in the conditions table and set inst.cond
17783 accordingly. Otherwise, this is an unconditional instruction.
17784 Again set inst.cond accordingly. Return the opcode structure.
17786 CE. Examine the tag field to make sure this is an instruction that
17787 should receive a conditional suffix. If it is not, fail.
17788 Otherwise, set inst.cond from the suffix we already looked up,
17789 and return the opcode structure.
17791 CM. Examine the tag field to make sure this is an instruction that
17792 should receive a conditional infix after the third character.
17793 If it is not, fail. Otherwise, undo the edits to the current
17794 line of input and proceed as for case CE. */
17796 static const struct asm_opcode
*
17797 opcode_lookup (char **str
)
17801 const struct asm_opcode
*opcode
;
17802 const struct asm_cond
*cond
;
17805 /* Scan up to the end of the mnemonic, which must end in white space,
17806 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17807 for (base
= end
= *str
; *end
!= '\0'; end
++)
17808 if (*end
== ' ' || *end
== '.')
17814 /* Handle a possible width suffix and/or Neon type suffix. */
17819 /* The .w and .n suffixes are only valid if the unified syntax is in
17821 if (unified_syntax
&& end
[1] == 'w')
17823 else if (unified_syntax
&& end
[1] == 'n')
17828 inst
.vectype
.elems
= 0;
17830 *str
= end
+ offset
;
17832 if (end
[offset
] == '.')
17834 /* See if we have a Neon type suffix (possible in either unified or
17835 non-unified ARM syntax mode). */
17836 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17839 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17845 /* Look for unaffixed or special-case affixed mnemonic. */
17846 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17851 if (opcode
->tag
< OT_odd_infix_0
)
17853 inst
.cond
= COND_ALWAYS
;
17857 if (warn_on_deprecated
&& unified_syntax
)
17858 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17859 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17860 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17863 inst
.cond
= cond
->value
;
17867 /* Cannot have a conditional suffix on a mnemonic of less than two
17869 if (end
- base
< 3)
17872 /* Look for suffixed mnemonic. */
17874 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17875 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17877 if (opcode
&& cond
)
17880 switch (opcode
->tag
)
17882 case OT_cinfix3_legacy
:
17883 /* Ignore conditional suffixes matched on infix only mnemonics. */
17887 case OT_cinfix3_deprecated
:
17888 case OT_odd_infix_unc
:
17889 if (!unified_syntax
)
17891 /* Fall through. */
17895 case OT_csuf_or_in3
:
17896 inst
.cond
= cond
->value
;
17899 case OT_unconditional
:
17900 case OT_unconditionalF
:
17902 inst
.cond
= cond
->value
;
17905 /* Delayed diagnostic. */
17906 inst
.error
= BAD_COND
;
17907 inst
.cond
= COND_ALWAYS
;
17916 /* Cannot have a usual-position infix on a mnemonic of less than
17917 six characters (five would be a suffix). */
17918 if (end
- base
< 6)
17921 /* Look for infixed mnemonic in the usual position. */
17923 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17927 memcpy (save
, affix
, 2);
17928 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17929 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17931 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17932 memcpy (affix
, save
, 2);
17935 && (opcode
->tag
== OT_cinfix3
17936 || opcode
->tag
== OT_cinfix3_deprecated
17937 || opcode
->tag
== OT_csuf_or_in3
17938 || opcode
->tag
== OT_cinfix3_legacy
))
17941 if (warn_on_deprecated
&& unified_syntax
17942 && (opcode
->tag
== OT_cinfix3
17943 || opcode
->tag
== OT_cinfix3_deprecated
))
17944 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17946 inst
.cond
= cond
->value
;
17953 /* This function generates an initial IT instruction, leaving its block
17954 virtually open for the new instructions. Eventually,
17955 the mask will be updated by now_it_add_mask () each time
17956 a new instruction needs to be included in the IT block.
17957 Finally, the block is closed with close_automatic_it_block ().
17958 The block closure can be requested either from md_assemble (),
17959 a tencode (), or due to a label hook. */
17962 new_automatic_it_block (int cond
)
17964 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17965 now_it
.mask
= 0x18;
17967 now_it
.block_length
= 1;
17968 mapping_state (MAP_THUMB
);
17969 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17970 now_it
.warn_deprecated
= FALSE
;
17971 now_it
.insn_cond
= TRUE
;
17974 /* Close an automatic IT block.
17975 See comments in new_automatic_it_block (). */
17978 close_automatic_it_block (void)
17980 now_it
.mask
= 0x10;
17981 now_it
.block_length
= 0;
17984 /* Update the mask of the current automatically-generated IT
17985 instruction. See comments in new_automatic_it_block (). */
17988 now_it_add_mask (int cond
)
17990 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17991 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17992 | ((bitvalue) << (nbit)))
17993 const int resulting_bit
= (cond
& 1);
17995 now_it
.mask
&= 0xf;
17996 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17998 (5 - now_it
.block_length
));
17999 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18001 ((5 - now_it
.block_length
) - 1) );
18002 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18005 #undef SET_BIT_VALUE
18008 /* The IT blocks handling machinery is accessed through the these functions:
18009 it_fsm_pre_encode () from md_assemble ()
18010 set_it_insn_type () optional, from the tencode functions
18011 set_it_insn_type_last () ditto
18012 in_it_block () ditto
18013 it_fsm_post_encode () from md_assemble ()
18014 force_automatic_it_block_close () from label handling functions
18017 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18018 initializing the IT insn type with a generic initial value depending
18019 on the inst.condition.
18020 2) During the tencode function, two things may happen:
18021 a) The tencode function overrides the IT insn type by
18022 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18023 b) The tencode function queries the IT block state by
18024 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18026 Both set_it_insn_type and in_it_block run the internal FSM state
18027 handling function (handle_it_state), because: a) setting the IT insn
18028 type may incur in an invalid state (exiting the function),
18029 and b) querying the state requires the FSM to be updated.
18030 Specifically we want to avoid creating an IT block for conditional
18031 branches, so it_fsm_pre_encode is actually a guess and we can't
18032 determine whether an IT block is required until the tencode () routine
18033 has decided what type of instruction this actually it.
18034 Because of this, if set_it_insn_type and in_it_block have to be used,
18035 set_it_insn_type has to be called first.
18037 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18038 determines the insn IT type depending on the inst.cond code.
18039 When a tencode () routine encodes an instruction that can be
18040 either outside an IT block, or, in the case of being inside, has to be
18041 the last one, set_it_insn_type_last () will determine the proper
18042 IT instruction type based on the inst.cond code. Otherwise,
18043 set_it_insn_type can be called for overriding that logic or
18044 for covering other cases.
18046 Calling handle_it_state () may not transition the IT block state to
18047 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18048 still queried. Instead, if the FSM determines that the state should
18049 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18050 after the tencode () function: that's what it_fsm_post_encode () does.
18052 Since in_it_block () calls the state handling function to get an
18053 updated state, an error may occur (due to invalid insns combination).
18054 In that case, inst.error is set.
18055 Therefore, inst.error has to be checked after the execution of
18056 the tencode () routine.
18058 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18059 any pending state change (if any) that didn't take place in
18060 handle_it_state () as explained above. */
18063 it_fsm_pre_encode (void)
18065 if (inst
.cond
!= COND_ALWAYS
)
18066 inst
.it_insn_type
= INSIDE_IT_INSN
;
18068 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18070 now_it
.state_handled
= 0;
18073 /* IT state FSM handling function. */
18076 handle_it_state (void)
18078 now_it
.state_handled
= 1;
18079 now_it
.insn_cond
= FALSE
;
18081 switch (now_it
.state
)
18083 case OUTSIDE_IT_BLOCK
:
18084 switch (inst
.it_insn_type
)
18086 case OUTSIDE_IT_INSN
:
18089 case INSIDE_IT_INSN
:
18090 case INSIDE_IT_LAST_INSN
:
18091 if (thumb_mode
== 0)
18094 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18095 as_tsktsk (_("Warning: conditional outside an IT block"\
18100 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18101 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18103 /* Automatically generate the IT instruction. */
18104 new_automatic_it_block (inst
.cond
);
18105 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18106 close_automatic_it_block ();
18110 inst
.error
= BAD_OUT_IT
;
18116 case IF_INSIDE_IT_LAST_INSN
:
18117 case NEUTRAL_IT_INSN
:
18121 now_it
.state
= MANUAL_IT_BLOCK
;
18122 now_it
.block_length
= 0;
18127 case AUTOMATIC_IT_BLOCK
:
18128 /* Three things may happen now:
18129 a) We should increment current it block size;
18130 b) We should close current it block (closing insn or 4 insns);
18131 c) We should close current it block and start a new one (due
18132 to incompatible conditions or
18133 4 insns-length block reached). */
18135 switch (inst
.it_insn_type
)
18137 case OUTSIDE_IT_INSN
:
18138 /* The closure of the block shall happen immediately,
18139 so any in_it_block () call reports the block as closed. */
18140 force_automatic_it_block_close ();
18143 case INSIDE_IT_INSN
:
18144 case INSIDE_IT_LAST_INSN
:
18145 case IF_INSIDE_IT_LAST_INSN
:
18146 now_it
.block_length
++;
18148 if (now_it
.block_length
> 4
18149 || !now_it_compatible (inst
.cond
))
18151 force_automatic_it_block_close ();
18152 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18153 new_automatic_it_block (inst
.cond
);
18157 now_it
.insn_cond
= TRUE
;
18158 now_it_add_mask (inst
.cond
);
18161 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18162 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18163 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18164 close_automatic_it_block ();
18167 case NEUTRAL_IT_INSN
:
18168 now_it
.block_length
++;
18169 now_it
.insn_cond
= TRUE
;
18171 if (now_it
.block_length
> 4)
18172 force_automatic_it_block_close ();
18174 now_it_add_mask (now_it
.cc
& 1);
18178 close_automatic_it_block ();
18179 now_it
.state
= MANUAL_IT_BLOCK
;
18184 case MANUAL_IT_BLOCK
:
18186 /* Check conditional suffixes. */
18187 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18190 now_it
.mask
&= 0x1f;
18191 is_last
= (now_it
.mask
== 0x10);
18192 now_it
.insn_cond
= TRUE
;
18194 switch (inst
.it_insn_type
)
18196 case OUTSIDE_IT_INSN
:
18197 inst
.error
= BAD_NOT_IT
;
18200 case INSIDE_IT_INSN
:
18201 if (cond
!= inst
.cond
)
18203 inst
.error
= BAD_IT_COND
;
18208 case INSIDE_IT_LAST_INSN
:
18209 case IF_INSIDE_IT_LAST_INSN
:
18210 if (cond
!= inst
.cond
)
18212 inst
.error
= BAD_IT_COND
;
18217 inst
.error
= BAD_BRANCH
;
18222 case NEUTRAL_IT_INSN
:
18223 /* The BKPT instruction is unconditional even in an IT block. */
18227 inst
.error
= BAD_IT_IT
;
18237 struct depr_insn_mask
18239 unsigned long pattern
;
18240 unsigned long mask
;
18241 const char* description
;
18244 /* List of 16-bit instruction patterns deprecated in an IT block in
18246 static const struct depr_insn_mask depr_it_insns
[] = {
18247 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18248 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18249 { 0xa000, 0xb800, N_("ADR") },
18250 { 0x4800, 0xf800, N_("Literal loads") },
18251 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18252 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18253 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18254 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18255 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18260 it_fsm_post_encode (void)
18264 if (!now_it
.state_handled
)
18265 handle_it_state ();
18267 if (now_it
.insn_cond
18268 && !now_it
.warn_deprecated
18269 && warn_on_deprecated
18270 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18272 if (inst
.instruction
>= 0x10000)
18274 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18275 "deprecated in ARMv8"));
18276 now_it
.warn_deprecated
= TRUE
;
18280 const struct depr_insn_mask
*p
= depr_it_insns
;
18282 while (p
->mask
!= 0)
18284 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18286 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18287 "of the following class are deprecated in ARMv8: "
18288 "%s"), p
->description
);
18289 now_it
.warn_deprecated
= TRUE
;
18297 if (now_it
.block_length
> 1)
18299 as_tsktsk (_("IT blocks containing more than one conditional "
18300 "instruction are deprecated in ARMv8"));
18301 now_it
.warn_deprecated
= TRUE
;
18305 is_last
= (now_it
.mask
== 0x10);
18308 now_it
.state
= OUTSIDE_IT_BLOCK
;
18314 force_automatic_it_block_close (void)
18316 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18318 close_automatic_it_block ();
18319 now_it
.state
= OUTSIDE_IT_BLOCK
;
18327 if (!now_it
.state_handled
)
18328 handle_it_state ();
18330 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18333 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18334 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18335 here, hence the "known" in the function name. */
18338 known_t32_only_insn (const struct asm_opcode
*opcode
)
18340 /* Original Thumb-1 wide instruction. */
18341 if (opcode
->tencode
== do_t_blx
18342 || opcode
->tencode
== do_t_branch23
18343 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18344 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18347 /* Wide-only instruction added to ARMv8-M Baseline. */
18348 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18349 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18350 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18351 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18357 /* Whether wide instruction variant can be used if available for a valid OPCODE
18361 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18363 if (known_t32_only_insn (opcode
))
18366 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18367 of variant T3 of B.W is checked in do_t_branch. */
18368 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18369 && opcode
->tencode
== do_t_branch
)
18372 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18373 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18374 && opcode
->tencode
== do_t_mov_cmp
18375 /* Make sure CMP instruction is not affected. */
18376 && opcode
->aencode
== do_mov
)
18379 /* Wide instruction variants of all instructions with narrow *and* wide
18380 variants become available with ARMv6t2. Other opcodes are either
18381 narrow-only or wide-only and are thus available if OPCODE is valid. */
18382 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18385 /* OPCODE with narrow only instruction variant or wide variant not
18391 md_assemble (char *str
)
18394 const struct asm_opcode
* opcode
;
18396 /* Align the previous label if needed. */
18397 if (last_label_seen
!= NULL
)
18399 symbol_set_frag (last_label_seen
, frag_now
);
18400 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18401 S_SET_SEGMENT (last_label_seen
, now_seg
);
18404 memset (&inst
, '\0', sizeof (inst
));
18405 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18407 opcode
= opcode_lookup (&p
);
18410 /* It wasn't an instruction, but it might be a register alias of
18411 the form alias .req reg, or a Neon .dn/.qn directive. */
18412 if (! create_register_alias (str
, p
)
18413 && ! create_neon_reg_alias (str
, p
))
18414 as_bad (_("bad instruction `%s'"), str
);
18419 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18420 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18422 /* The value which unconditional instructions should have in place of the
18423 condition field. */
18424 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18428 arm_feature_set variant
;
18430 variant
= cpu_variant
;
18431 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18432 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18433 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18434 /* Check that this instruction is supported for this CPU. */
18435 if (!opcode
->tvariant
18436 || (thumb_mode
== 1
18437 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18439 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18442 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18443 && opcode
->tencode
!= do_t_branch
)
18445 as_bad (_("Thumb does not support conditional execution"));
18449 /* Two things are addressed here:
18450 1) Implicit require narrow instructions on Thumb-1.
18451 This avoids relaxation accidentally introducing Thumb-2
18453 2) Reject wide instructions in non Thumb-2 cores.
18455 Only instructions with narrow and wide variants need to be handled
18456 but selecting all non wide-only instructions is easier. */
18457 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18458 && !t32_insn_ok (variant
, opcode
))
18460 if (inst
.size_req
== 0)
18462 else if (inst
.size_req
== 4)
18464 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18465 as_bad (_("selected processor does not support 32bit wide "
18466 "variant of instruction `%s'"), str
);
18468 as_bad (_("selected processor does not support `%s' in "
18469 "Thumb-2 mode"), str
);
18474 inst
.instruction
= opcode
->tvalue
;
18476 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18478 /* Prepare the it_insn_type for those encodings that don't set
18480 it_fsm_pre_encode ();
18482 opcode
->tencode ();
18484 it_fsm_post_encode ();
18487 if (!(inst
.error
|| inst
.relax
))
18489 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18490 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18491 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18493 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18498 /* Something has gone badly wrong if we try to relax a fixed size
18500 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18502 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18503 *opcode
->tvariant
);
18504 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18505 set those bits when Thumb-2 32-bit instructions are seen. The impact
18506 of relaxable instructions will be considered later after we finish all
18508 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18509 variant
= arm_arch_none
;
18511 variant
= cpu_variant
;
18512 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18513 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18516 check_neon_suffixes
;
18520 mapping_state (MAP_THUMB
);
18523 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18527 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18528 is_bx
= (opcode
->aencode
== do_bx
);
18530 /* Check that this instruction is supported for this CPU. */
18531 if (!(is_bx
&& fix_v4bx
)
18532 && !(opcode
->avariant
&&
18533 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18535 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18540 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18544 inst
.instruction
= opcode
->avalue
;
18545 if (opcode
->tag
== OT_unconditionalF
)
18546 inst
.instruction
|= 0xFU
<< 28;
18548 inst
.instruction
|= inst
.cond
<< 28;
18549 inst
.size
= INSN_SIZE
;
18550 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18552 it_fsm_pre_encode ();
18553 opcode
->aencode ();
18554 it_fsm_post_encode ();
18556 /* Arm mode bx is marked as both v4T and v5 because it's still required
18557 on a hypothetical non-thumb v5 core. */
18559 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18561 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18562 *opcode
->avariant
);
18564 check_neon_suffixes
;
18568 mapping_state (MAP_ARM
);
18573 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18581 check_it_blocks_finished (void)
18586 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18587 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18588 == MANUAL_IT_BLOCK
)
18590 as_warn (_("section '%s' finished with an open IT block."),
18594 if (now_it
.state
== MANUAL_IT_BLOCK
)
18595 as_warn (_("file finished with an open IT block."));
18599 /* Various frobbings of labels and their addresses. */
18602 arm_start_line_hook (void)
18604 last_label_seen
= NULL
;
18608 arm_frob_label (symbolS
* sym
)
18610 last_label_seen
= sym
;
18612 ARM_SET_THUMB (sym
, thumb_mode
);
18614 #if defined OBJ_COFF || defined OBJ_ELF
18615 ARM_SET_INTERWORK (sym
, support_interwork
);
18618 force_automatic_it_block_close ();
18620 /* Note - do not allow local symbols (.Lxxx) to be labelled
18621 as Thumb functions. This is because these labels, whilst
18622 they exist inside Thumb code, are not the entry points for
18623 possible ARM->Thumb calls. Also, these labels can be used
18624 as part of a computed goto or switch statement. eg gcc
18625 can generate code that looks like this:
18627 ldr r2, [pc, .Laaa]
18637 The first instruction loads the address of the jump table.
18638 The second instruction converts a table index into a byte offset.
18639 The third instruction gets the jump address out of the table.
18640 The fourth instruction performs the jump.
18642 If the address stored at .Laaa is that of a symbol which has the
18643 Thumb_Func bit set, then the linker will arrange for this address
18644 to have the bottom bit set, which in turn would mean that the
18645 address computation performed by the third instruction would end
18646 up with the bottom bit set. Since the ARM is capable of unaligned
18647 word loads, the instruction would then load the incorrect address
18648 out of the jump table, and chaos would ensue. */
18649 if (label_is_thumb_function_name
18650 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18651 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18653 /* When the address of a Thumb function is taken the bottom
18654 bit of that address should be set. This will allow
18655 interworking between Arm and Thumb functions to work
18658 THUMB_SET_FUNC (sym
, 1);
18660 label_is_thumb_function_name
= FALSE
;
18663 dwarf2_emit_label (sym
);
18667 arm_data_in_code (void)
18669 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18671 *input_line_pointer
= '/';
18672 input_line_pointer
+= 5;
18673 *input_line_pointer
= 0;
18681 arm_canonicalize_symbol_name (char * name
)
18685 if (thumb_mode
&& (len
= strlen (name
)) > 5
18686 && streq (name
+ len
- 5, "/data"))
18687 *(name
+ len
- 5) = 0;
18692 /* Table of all register names defined by default. The user can
18693 define additional names with .req. Note that all register names
18694 should appear in both upper and lowercase variants. Some registers
18695 also have mixed-case names. */
18697 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18698 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18699 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18700 #define REGSET(p,t) \
18701 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18702 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18703 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18704 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18705 #define REGSETH(p,t) \
18706 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18707 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18708 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18709 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18710 #define REGSET2(p,t) \
18711 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18712 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18713 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18714 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18715 #define SPLRBANK(base,bank,t) \
18716 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18717 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18718 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18719 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18720 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18721 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18723 static const struct reg_entry reg_names
[] =
18725 /* ARM integer registers. */
18726 REGSET(r
, RN
), REGSET(R
, RN
),
18728 /* ATPCS synonyms. */
18729 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18730 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18731 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18733 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18734 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18735 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18737 /* Well-known aliases. */
18738 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18739 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18741 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18742 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18744 /* Coprocessor numbers. */
18745 REGSET(p
, CP
), REGSET(P
, CP
),
18747 /* Coprocessor register numbers. The "cr" variants are for backward
18749 REGSET(c
, CN
), REGSET(C
, CN
),
18750 REGSET(cr
, CN
), REGSET(CR
, CN
),
18752 /* ARM banked registers. */
18753 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18754 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18755 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18756 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18757 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18758 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18759 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18761 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18762 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18763 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18764 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18765 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18766 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18767 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18768 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18770 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18771 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18772 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18773 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18774 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18775 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18776 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18777 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18778 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18780 /* FPA registers. */
18781 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18782 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18784 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18785 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18787 /* VFP SP registers. */
18788 REGSET(s
,VFS
), REGSET(S
,VFS
),
18789 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18791 /* VFP DP Registers. */
18792 REGSET(d
,VFD
), REGSET(D
,VFD
),
18793 /* Extra Neon DP registers. */
18794 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18796 /* Neon QP registers. */
18797 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18799 /* VFP control registers. */
18800 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18801 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18802 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18803 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18804 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18805 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18807 /* Maverick DSP coprocessor registers. */
18808 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18809 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18811 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18812 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18813 REGDEF(dspsc
,0,DSPSC
),
18815 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18816 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18817 REGDEF(DSPSC
,0,DSPSC
),
18819 /* iWMMXt data registers - p0, c0-15. */
18820 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18822 /* iWMMXt control registers - p1, c0-3. */
18823 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18824 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18825 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18826 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18828 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18829 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18830 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18831 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18832 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18834 /* XScale accumulator registers. */
18835 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18841 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18842 within psr_required_here. */
18843 static const struct asm_psr psrs
[] =
18845 /* Backward compatibility notation. Note that "all" is no longer
18846 truly all possible PSR bits. */
18847 {"all", PSR_c
| PSR_f
},
18851 /* Individual flags. */
18857 /* Combinations of flags. */
18858 {"fs", PSR_f
| PSR_s
},
18859 {"fx", PSR_f
| PSR_x
},
18860 {"fc", PSR_f
| PSR_c
},
18861 {"sf", PSR_s
| PSR_f
},
18862 {"sx", PSR_s
| PSR_x
},
18863 {"sc", PSR_s
| PSR_c
},
18864 {"xf", PSR_x
| PSR_f
},
18865 {"xs", PSR_x
| PSR_s
},
18866 {"xc", PSR_x
| PSR_c
},
18867 {"cf", PSR_c
| PSR_f
},
18868 {"cs", PSR_c
| PSR_s
},
18869 {"cx", PSR_c
| PSR_x
},
18870 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18871 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18872 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18873 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18874 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18875 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18876 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18877 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18878 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18879 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18880 {"scf", PSR_s
| PSR_c
| PSR_f
},
18881 {"scx", PSR_s
| PSR_c
| PSR_x
},
18882 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18883 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18884 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18885 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18886 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18887 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18888 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18889 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18890 {"csf", PSR_c
| PSR_s
| PSR_f
},
18891 {"csx", PSR_c
| PSR_s
| PSR_x
},
18892 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18893 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18894 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18895 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18896 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18897 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18898 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18899 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18900 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18901 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18902 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18903 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18904 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18905 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18906 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18907 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18908 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18909 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18910 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18911 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18912 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18913 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18914 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18915 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18916 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18917 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18920 /* Table of V7M psr names. */
18921 static const struct asm_psr v7m_psrs
[] =
18923 {"apsr", 0x0 }, {"APSR", 0x0 },
18924 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
18925 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
18926 {"psr", 0x3 }, {"PSR", 0x3 },
18927 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
18928 {"ipsr", 0x5 }, {"IPSR", 0x5 },
18929 {"epsr", 0x6 }, {"EPSR", 0x6 },
18930 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
18931 {"msp", 0x8 }, {"MSP", 0x8 },
18932 {"psp", 0x9 }, {"PSP", 0x9 },
18933 {"msplim", 0xa }, {"MSPLIM", 0xa },
18934 {"psplim", 0xb }, {"PSPLIM", 0xb },
18935 {"primask", 0x10}, {"PRIMASK", 0x10},
18936 {"basepri", 0x11}, {"BASEPRI", 0x11},
18937 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
18938 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
18939 {"control", 0x14}, {"CONTROL", 0x14},
18940 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
18941 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
18942 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
18943 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
18944 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
18945 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
18946 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
18947 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
18948 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
18951 /* Table of all shift-in-operand names. */
18952 static const struct asm_shift_name shift_names
[] =
18954 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18955 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18956 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18957 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18958 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18959 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18962 /* Table of all explicit relocation names. */
18964 static struct reloc_entry reloc_names
[] =
18966 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18967 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18968 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18969 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18970 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18971 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18972 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18973 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18974 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18975 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18976 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18977 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18978 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18979 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18980 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18981 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18982 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18983 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18987 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18988 static const struct asm_cond conds
[] =
18992 {"cs", 0x2}, {"hs", 0x2},
18993 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19007 #define UL_BARRIER(L,U,CODE,FEAT) \
19008 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19009 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19011 static struct asm_barrier_opt barrier_opt_names
[] =
19013 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19014 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19015 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19016 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19017 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19018 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19019 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19020 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19021 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19022 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19023 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19024 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19025 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19026 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19027 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19028 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19033 /* Table of ARM-format instructions. */
19035 /* Macros for gluing together operand strings. N.B. In all cases
19036 other than OPS0, the trailing OP_stop comes from default
19037 zero-initialization of the unspecified elements of the array. */
19038 #define OPS0() { OP_stop, }
19039 #define OPS1(a) { OP_##a, }
19040 #define OPS2(a,b) { OP_##a,OP_##b, }
19041 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19042 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19043 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19044 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19046 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19047 This is useful when mixing operands for ARM and THUMB, i.e. using the
19048 MIX_ARM_THUMB_OPERANDS macro.
19049 In order to use these macros, prefix the number of operands with _
19051 #define OPS_1(a) { a, }
19052 #define OPS_2(a,b) { a,b, }
19053 #define OPS_3(a,b,c) { a,b,c, }
19054 #define OPS_4(a,b,c,d) { a,b,c,d, }
19055 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19056 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19058 /* These macros abstract out the exact format of the mnemonic table and
19059 save some repeated characters. */
19061 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19062 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19063 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19064 THUMB_VARIANT, do_##ae, do_##te }
19066 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19067 a T_MNEM_xyz enumerator. */
19068 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19069 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19070 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19071 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19073 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19074 infix after the third character. */
19075 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19076 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19077 THUMB_VARIANT, do_##ae, do_##te }
19078 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19079 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19080 THUMB_VARIANT, do_##ae, do_##te }
19081 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19082 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19083 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19084 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19085 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19086 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19087 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19088 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19090 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19091 field is still 0xE. Many of the Thumb variants can be executed
19092 conditionally, so this is checked separately. */
19093 #define TUE(mnem, op, top, nops, ops, ae, te) \
19094 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19095 THUMB_VARIANT, do_##ae, do_##te }
19097 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19098 Used by mnemonics that have very minimal differences in the encoding for
19099 ARM and Thumb variants and can be handled in a common function. */
19100 #define TUEc(mnem, op, top, nops, ops, en) \
19101 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19102 THUMB_VARIANT, do_##en, do_##en }
19104 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19105 condition code field. */
19106 #define TUF(mnem, op, top, nops, ops, ae, te) \
19107 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19108 THUMB_VARIANT, do_##ae, do_##te }
19110 /* ARM-only variants of all the above. */
19111 #define CE(mnem, op, nops, ops, ae) \
19112 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19114 #define C3(mnem, op, nops, ops, ae) \
19115 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19117 /* Legacy mnemonics that always have conditional infix after the third
19119 #define CL(mnem, op, nops, ops, ae) \
19120 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19121 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19123 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19124 #define cCE(mnem, op, nops, ops, ae) \
19125 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19127 /* Legacy coprocessor instructions where conditional infix and conditional
19128 suffix are ambiguous. For consistency this includes all FPA instructions,
19129 not just the potentially ambiguous ones. */
19130 #define cCL(mnem, op, nops, ops, ae) \
19131 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19132 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19134 /* Coprocessor, takes either a suffix or a position-3 infix
19135 (for an FPA corner case). */
19136 #define C3E(mnem, op, nops, ops, ae) \
19137 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19138 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19140 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19141 { m1 #m2 m3, OPS##nops ops, \
19142 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19143 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19145 #define CM(m1, m2, op, nops, ops, ae) \
19146 xCM_ (m1, , m2, op, nops, ops, ae), \
19147 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19148 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19149 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19150 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19151 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19152 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19153 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19154 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19155 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19156 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19157 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19158 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19159 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19160 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19161 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19162 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19163 xCM_ (m1, le, m2, op, nops, ops, ae), \
19164 xCM_ (m1, al, m2, op, nops, ops, ae)
19166 #define UE(mnem, op, nops, ops, ae) \
19167 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19169 #define UF(mnem, op, nops, ops, ae) \
19170 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19172 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19173 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19174 use the same encoding function for each. */
19175 #define NUF(mnem, op, nops, ops, enc) \
19176 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19177 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19179 /* Neon data processing, version which indirects through neon_enc_tab for
19180 the various overloaded versions of opcodes. */
19181 #define nUF(mnem, op, nops, ops, enc) \
19182 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19183 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19185 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19187 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19188 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19189 THUMB_VARIANT, do_##enc, do_##enc }
19191 #define NCE(mnem, op, nops, ops, enc) \
19192 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19194 #define NCEF(mnem, op, nops, ops, enc) \
19195 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19197 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19198 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19199 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19200 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19202 #define nCE(mnem, op, nops, ops, enc) \
19203 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19205 #define nCEF(mnem, op, nops, ops, enc) \
19206 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19210 static const struct asm_opcode insns
[] =
19212 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19213 #define THUMB_VARIANT & arm_ext_v4t
19214 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19215 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19216 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19217 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19218 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19219 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19220 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19221 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19222 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19223 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19224 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19225 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19226 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19227 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19228 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19229 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19231 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19232 for setting PSR flag bits. They are obsolete in V6 and do not
19233 have Thumb equivalents. */
19234 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19235 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19236 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19237 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19238 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19239 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19240 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19241 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19242 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19244 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19245 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19246 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19247 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19249 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19250 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19251 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19253 OP_ADDRGLDR
),ldst
, t_ldst
),
19254 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19256 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19257 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19258 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19259 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19260 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19261 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19263 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19264 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19265 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19266 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19269 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19270 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19271 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19272 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19274 /* Thumb-compatibility pseudo ops. */
19275 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19276 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19277 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19278 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19279 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19280 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19281 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19282 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19283 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19284 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19285 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19286 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19288 /* These may simplify to neg. */
19289 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19290 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19292 #undef THUMB_VARIANT
19293 #define THUMB_VARIANT & arm_ext_v6
19295 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19297 /* V1 instructions with no Thumb analogue prior to V6T2. */
19298 #undef THUMB_VARIANT
19299 #define THUMB_VARIANT & arm_ext_v6t2
19301 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19302 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19303 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19305 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19306 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19307 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19308 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19310 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19311 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19313 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19314 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19316 /* V1 instructions with no Thumb analogue at all. */
19317 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19318 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19320 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19321 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19322 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19323 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19324 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19325 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19326 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19327 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19330 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19331 #undef THUMB_VARIANT
19332 #define THUMB_VARIANT & arm_ext_v4t
19334 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19335 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19337 #undef THUMB_VARIANT
19338 #define THUMB_VARIANT & arm_ext_v6t2
19340 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19341 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19343 /* Generic coprocessor instructions. */
19344 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19345 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19346 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19347 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19348 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19349 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19350 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19353 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19355 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19356 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19359 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19360 #undef THUMB_VARIANT
19361 #define THUMB_VARIANT & arm_ext_msr
19363 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19364 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19367 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19368 #undef THUMB_VARIANT
19369 #define THUMB_VARIANT & arm_ext_v6t2
19371 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19372 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19373 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19374 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19375 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19376 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19377 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19378 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19381 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19382 #undef THUMB_VARIANT
19383 #define THUMB_VARIANT & arm_ext_v4t
19385 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19386 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19387 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19388 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19389 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19390 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19393 #define ARM_VARIANT & arm_ext_v4t_5
19395 /* ARM Architecture 4T. */
19396 /* Note: bx (and blx) are required on V5, even if the processor does
19397 not support Thumb. */
19398 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19401 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19402 #undef THUMB_VARIANT
19403 #define THUMB_VARIANT & arm_ext_v5t
19405 /* Note: blx has 2 variants; the .value coded here is for
19406 BLX(2). Only this variant has conditional execution. */
19407 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19408 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19410 #undef THUMB_VARIANT
19411 #define THUMB_VARIANT & arm_ext_v6t2
19413 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19414 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19415 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19416 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19417 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19418 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19419 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19420 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19423 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19424 #undef THUMB_VARIANT
19425 #define THUMB_VARIANT & arm_ext_v5exp
19427 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19428 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19429 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19430 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19432 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19433 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19435 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19436 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19437 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19438 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19440 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19441 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19442 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19443 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19445 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19446 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19448 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19449 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19450 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19451 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19454 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19455 #undef THUMB_VARIANT
19456 #define THUMB_VARIANT & arm_ext_v6t2
19458 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19459 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19461 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19462 ADDRGLDRS
), ldrd
, t_ldstd
),
19464 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19465 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19468 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19470 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19473 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19474 #undef THUMB_VARIANT
19475 #define THUMB_VARIANT & arm_ext_v6
19477 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19478 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19479 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19480 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19481 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19482 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19483 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19484 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19485 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19486 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19488 #undef THUMB_VARIANT
19489 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19491 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19492 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19494 #undef THUMB_VARIANT
19495 #define THUMB_VARIANT & arm_ext_v6t2
19497 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19498 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19500 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19501 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19503 /* ARM V6 not included in V7M. */
19504 #undef THUMB_VARIANT
19505 #define THUMB_VARIANT & arm_ext_v6_notm
19506 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19507 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19508 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19509 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19510 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19511 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19512 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19513 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19514 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19515 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19516 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19517 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19518 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19519 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19520 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19521 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19522 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19523 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19524 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19526 /* ARM V6 not included in V7M (eg. integer SIMD). */
19527 #undef THUMB_VARIANT
19528 #define THUMB_VARIANT & arm_ext_v6_dsp
19529 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19530 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19531 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19532 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19533 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19534 /* Old name for QASX. */
19535 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19536 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19537 /* Old name for QSAX. */
19538 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19539 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19540 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19541 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19542 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19543 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19544 /* Old name for SASX. */
19545 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19546 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19547 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19548 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19549 /* Old name for SHASX. */
19550 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19551 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19552 /* Old name for SHSAX. */
19553 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19554 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19555 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19556 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19557 /* Old name for SSAX. */
19558 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19559 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19560 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19561 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19562 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19563 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19564 /* Old name for UASX. */
19565 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19566 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19567 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19568 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19569 /* Old name for UHASX. */
19570 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19571 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19572 /* Old name for UHSAX. */
19573 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19574 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19575 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19576 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19577 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19578 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19579 /* Old name for UQASX. */
19580 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19581 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19582 /* Old name for UQSAX. */
19583 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19584 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19585 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19586 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19587 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19588 /* Old name for USAX. */
19589 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19590 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19591 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19592 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19593 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19594 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19595 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19596 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19597 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19598 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19599 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19600 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19601 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19602 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19603 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19604 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19605 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19606 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19607 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19608 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19609 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19610 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19611 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19612 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19613 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19614 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19615 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19616 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19617 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19618 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19619 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19620 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19621 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19622 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19625 #define ARM_VARIANT & arm_ext_v6k
19626 #undef THUMB_VARIANT
19627 #define THUMB_VARIANT & arm_ext_v6k
19629 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19630 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19631 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19632 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19634 #undef THUMB_VARIANT
19635 #define THUMB_VARIANT & arm_ext_v6_notm
19636 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19638 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19639 RRnpcb
), strexd
, t_strexd
),
19641 #undef THUMB_VARIANT
19642 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19643 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19645 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19647 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19649 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19651 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19654 #define ARM_VARIANT & arm_ext_sec
19655 #undef THUMB_VARIANT
19656 #define THUMB_VARIANT & arm_ext_sec
19658 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19661 #define ARM_VARIANT & arm_ext_virt
19662 #undef THUMB_VARIANT
19663 #define THUMB_VARIANT & arm_ext_virt
19665 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19666 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19669 #define ARM_VARIANT & arm_ext_pan
19670 #undef THUMB_VARIANT
19671 #define THUMB_VARIANT & arm_ext_pan
19673 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19676 #define ARM_VARIANT & arm_ext_v6t2
19677 #undef THUMB_VARIANT
19678 #define THUMB_VARIANT & arm_ext_v6t2
19680 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19681 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19682 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19683 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19685 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19686 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19688 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19689 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19690 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19691 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19693 #undef THUMB_VARIANT
19694 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19695 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19696 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19698 /* Thumb-only instructions. */
19700 #define ARM_VARIANT NULL
19701 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19702 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19704 /* ARM does not really have an IT instruction, so always allow it.
19705 The opcode is copied from Thumb in order to allow warnings in
19706 -mimplicit-it=[never | arm] modes. */
19708 #define ARM_VARIANT & arm_ext_v1
19709 #undef THUMB_VARIANT
19710 #define THUMB_VARIANT & arm_ext_v6t2
19712 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19713 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19714 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19715 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19716 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19717 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19718 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19719 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19720 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19721 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19722 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19723 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19724 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19725 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19726 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19727 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19728 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19729 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19731 /* Thumb2 only instructions. */
19733 #define ARM_VARIANT NULL
19735 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19736 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19737 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19738 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19739 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19740 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19742 /* Hardware division instructions. */
19744 #define ARM_VARIANT & arm_ext_adiv
19745 #undef THUMB_VARIANT
19746 #define THUMB_VARIANT & arm_ext_div
19748 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19749 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19751 /* ARM V6M/V7 instructions. */
19753 #define ARM_VARIANT & arm_ext_barrier
19754 #undef THUMB_VARIANT
19755 #define THUMB_VARIANT & arm_ext_barrier
19757 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19758 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19759 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19761 /* ARM V7 instructions. */
19763 #define ARM_VARIANT & arm_ext_v7
19764 #undef THUMB_VARIANT
19765 #define THUMB_VARIANT & arm_ext_v7
19767 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19768 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19771 #define ARM_VARIANT & arm_ext_mp
19772 #undef THUMB_VARIANT
19773 #define THUMB_VARIANT & arm_ext_mp
19775 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19777 /* AArchv8 instructions. */
19779 #define ARM_VARIANT & arm_ext_v8
19781 /* Instructions shared between armv8-a and armv8-m. */
19782 #undef THUMB_VARIANT
19783 #define THUMB_VARIANT & arm_ext_atomics
19785 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19786 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19787 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19788 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19789 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19790 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19791 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19792 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19793 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19794 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19796 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19798 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19800 #undef THUMB_VARIANT
19801 #define THUMB_VARIANT & arm_ext_v8
19803 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19804 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19805 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19807 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19809 /* ARMv8 T32 only. */
19811 #define ARM_VARIANT NULL
19812 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19813 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19814 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19816 /* FP for ARMv8. */
19818 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19819 #undef THUMB_VARIANT
19820 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19822 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19823 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19824 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19825 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19826 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19827 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19828 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19829 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19830 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19831 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19832 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19833 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19834 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19835 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19836 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19837 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19838 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19840 /* Crypto v1 extensions. */
19842 #define ARM_VARIANT & fpu_crypto_ext_armv8
19843 #undef THUMB_VARIANT
19844 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19846 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19847 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19848 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19849 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19850 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19851 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19852 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19853 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19854 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19855 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19856 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19857 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19858 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19859 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19862 #define ARM_VARIANT & crc_ext_armv8
19863 #undef THUMB_VARIANT
19864 #define THUMB_VARIANT & crc_ext_armv8
19865 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19866 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19867 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19868 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19869 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19870 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19872 /* ARMv8.2 RAS extension. */
19874 #define ARM_VARIANT & arm_ext_ras
19875 #undef THUMB_VARIANT
19876 #define THUMB_VARIANT & arm_ext_ras
19877 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19880 #define ARM_VARIANT & arm_ext_v8_3
19881 #undef THUMB_VARIANT
19882 #define THUMB_VARIANT & arm_ext_v8_3
19883 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
19884 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
19885 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
19888 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19889 #undef THUMB_VARIANT
19890 #define THUMB_VARIANT NULL
19892 cCE("wfs", e200110
, 1, (RR
), rd
),
19893 cCE("rfs", e300110
, 1, (RR
), rd
),
19894 cCE("wfc", e400110
, 1, (RR
), rd
),
19895 cCE("rfc", e500110
, 1, (RR
), rd
),
19897 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19898 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19899 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19900 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19902 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19903 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19904 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19905 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19907 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19908 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19909 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19910 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19911 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19912 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19913 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19914 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19915 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19916 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19917 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19918 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19920 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19921 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19922 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19923 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19924 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19925 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19926 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19927 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19928 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19929 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19930 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19931 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19933 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19934 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19935 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19936 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19937 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19938 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19939 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19940 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19941 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19942 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19943 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19944 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19946 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19947 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19948 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19949 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19950 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19951 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19952 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19953 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19954 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19955 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19956 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19957 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19959 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19960 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19961 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19962 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19963 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19964 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19965 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19966 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19967 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19968 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19969 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19970 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19972 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19973 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19974 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19975 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19976 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19977 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19978 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19979 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19980 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19981 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19982 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19983 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19985 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19986 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19987 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19988 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19989 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19990 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19991 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19992 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19993 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19994 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19995 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19996 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19998 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19999 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20000 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20001 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20002 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20003 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20004 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20005 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20006 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20007 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20008 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20009 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20011 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20012 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20013 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20014 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20015 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20016 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20017 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20018 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20019 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20020 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20021 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20022 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20024 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20025 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20026 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20027 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20028 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20029 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20030 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20031 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20032 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20033 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20034 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20035 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20037 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20038 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20039 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20040 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20041 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20042 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20043 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20044 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20045 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20046 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20047 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20048 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20050 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20051 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20052 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20053 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20054 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20055 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20056 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20057 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20058 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20059 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20060 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20061 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20063 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20064 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20065 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20066 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20067 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20068 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20069 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20070 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20071 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20072 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20073 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20074 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20076 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20077 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20078 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20079 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20080 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20081 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20082 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20083 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20084 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20085 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20086 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20087 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20089 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20090 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20091 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20092 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20093 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20094 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20095 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20096 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20097 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20098 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20099 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20100 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20102 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20103 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20104 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20105 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20106 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20107 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20108 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20109 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20110 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20111 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20112 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20113 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20115 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20116 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20117 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20118 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20119 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20120 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20121 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20122 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20123 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20124 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20125 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20126 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20128 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20129 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20130 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20131 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20132 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20133 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20134 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20135 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20136 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20137 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20138 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20139 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20141 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20142 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20143 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20144 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20145 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20146 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20147 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20148 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20149 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20150 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20151 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20152 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20154 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20155 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20156 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20157 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20158 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20159 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20160 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20161 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20162 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20163 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20164 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20165 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20167 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20168 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20169 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20170 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20171 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20172 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20173 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20174 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20175 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20176 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20177 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20178 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20180 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20181 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20182 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20183 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20184 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20185 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20186 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20187 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20188 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20189 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20190 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20191 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20193 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20194 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20195 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20196 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20197 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20198 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20199 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20200 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20201 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20202 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20203 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20204 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20206 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20207 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20208 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20209 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20210 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20211 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20212 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20213 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20214 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20215 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20216 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20217 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20219 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20220 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20221 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20222 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20223 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20224 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20225 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20226 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20227 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20228 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20229 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20230 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20232 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20233 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20234 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20235 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20236 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20237 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20238 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20239 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20240 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20241 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20242 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20243 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20245 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20246 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20247 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20248 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20249 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20250 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20251 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20252 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20253 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20254 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20255 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20256 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20258 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20259 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20260 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20261 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20262 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20263 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20264 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20265 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20266 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20267 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20268 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20269 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20271 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20272 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20273 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20274 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20275 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20276 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20277 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20278 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20279 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20280 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20281 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20282 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20284 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20285 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20286 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20287 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20289 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20290 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20291 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20292 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20293 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20294 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20295 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20296 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20297 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20298 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20299 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20300 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20302 /* The implementation of the FIX instruction is broken on some
20303 assemblers, in that it accepts a precision specifier as well as a
20304 rounding specifier, despite the fact that this is meaningless.
20305 To be more compatible, we accept it as well, though of course it
20306 does not set any bits. */
20307 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20308 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20309 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20310 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20311 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20312 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20313 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20314 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20315 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20316 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20317 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20318 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20319 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20321 /* Instructions that were new with the real FPA, call them V2. */
20323 #define ARM_VARIANT & fpu_fpa_ext_v2
20325 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20326 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20327 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20328 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20329 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20330 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20333 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20335 /* Moves and type conversions. */
20336 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20337 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20338 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20339 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20340 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20341 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20342 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20343 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20344 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20345 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20346 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20347 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20348 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20349 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20351 /* Memory operations. */
20352 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20353 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20354 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20355 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20356 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20357 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20358 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20359 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20360 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20361 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20362 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20363 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20364 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20365 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20366 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20367 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20368 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20369 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20371 /* Monadic operations. */
20372 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20373 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20374 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20376 /* Dyadic operations. */
20377 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20378 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20379 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20380 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20381 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20382 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20383 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20384 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20385 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20388 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20389 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20390 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20391 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20393 /* Double precision load/store are still present on single precision
20394 implementations. */
20395 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20396 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20397 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20398 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20399 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20400 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20401 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20402 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20403 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20404 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20407 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20409 /* Moves and type conversions. */
20410 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20411 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20412 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20413 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20414 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20415 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20416 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20417 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20418 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20419 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20420 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20421 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20422 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20424 /* Monadic operations. */
20425 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20426 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20427 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20429 /* Dyadic operations. */
20430 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20431 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20432 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20433 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20434 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20435 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20436 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20437 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20438 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20441 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20442 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20443 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20444 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20447 #define ARM_VARIANT & fpu_vfp_ext_v2
20449 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20450 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20451 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20452 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20454 /* Instructions which may belong to either the Neon or VFP instruction sets.
20455 Individual encoder functions perform additional architecture checks. */
20457 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20458 #undef THUMB_VARIANT
20459 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20461 /* These mnemonics are unique to VFP. */
20462 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20463 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20464 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20465 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20466 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20467 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20468 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20469 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20470 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20471 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20473 /* Mnemonics shared by Neon and VFP. */
20474 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20475 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20476 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20478 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20479 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20481 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20482 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20484 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20485 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20486 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20487 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20488 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20489 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20490 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20491 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20493 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20494 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20495 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20496 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20499 /* NOTE: All VMOV encoding is special-cased! */
20500 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20501 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20504 #define ARM_VARIANT & arm_ext_fp16
20505 #undef THUMB_VARIANT
20506 #define THUMB_VARIANT & arm_ext_fp16
20507 /* New instructions added from v8.2, allowing the extraction and insertion of
20508 the upper 16 bits of a 32-bit vector register. */
20509 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20510 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20512 #undef THUMB_VARIANT
20513 #define THUMB_VARIANT & fpu_neon_ext_v1
20515 #define ARM_VARIANT & fpu_neon_ext_v1
20517 /* Data processing with three registers of the same length. */
20518 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20519 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20520 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20521 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20522 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20523 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20524 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20525 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20526 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20527 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20528 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20529 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20530 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20531 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20532 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20533 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20534 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20535 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20536 /* If not immediate, fall back to neon_dyadic_i64_su.
20537 shl_imm should accept I8 I16 I32 I64,
20538 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20539 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20540 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20541 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20542 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20543 /* Logic ops, types optional & ignored. */
20544 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20545 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20546 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20547 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20548 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20549 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20550 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20551 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20552 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20553 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20554 /* Bitfield ops, untyped. */
20555 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20556 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20557 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20558 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20559 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20560 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20561 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20562 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20563 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20564 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20565 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20566 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20567 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20568 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20569 back to neon_dyadic_if_su. */
20570 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20571 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20572 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20573 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20574 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20575 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20576 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20577 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20578 /* Comparison. Type I8 I16 I32 F32. */
20579 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20580 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20581 /* As above, D registers only. */
20582 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20583 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20584 /* Int and float variants, signedness unimportant. */
20585 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20586 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20587 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20588 /* Add/sub take types I8 I16 I32 I64 F32. */
20589 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20590 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20591 /* vtst takes sizes 8, 16, 32. */
20592 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20593 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20594 /* VMUL takes I8 I16 I32 F32 P8. */
20595 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20596 /* VQD{R}MULH takes S16 S32. */
20597 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20598 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20599 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20600 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20601 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20602 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20603 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20604 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20605 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20606 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20607 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20608 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20609 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20610 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20611 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20612 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20613 /* ARM v8.1 extension. */
20614 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20615 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20616 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20617 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20619 /* Two address, int/float. Types S8 S16 S32 F32. */
20620 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20621 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20623 /* Data processing with two registers and a shift amount. */
20624 /* Right shifts, and variants with rounding.
20625 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20626 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20627 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20628 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20629 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20630 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20631 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20632 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20633 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20634 /* Shift and insert. Sizes accepted 8 16 32 64. */
20635 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20636 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20637 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20638 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20639 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20640 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20641 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20642 /* Right shift immediate, saturating & narrowing, with rounding variants.
20643 Types accepted S16 S32 S64 U16 U32 U64. */
20644 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20645 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20646 /* As above, unsigned. Types accepted S16 S32 S64. */
20647 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20648 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20649 /* Right shift narrowing. Types accepted I16 I32 I64. */
20650 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20651 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20652 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20653 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20654 /* CVT with optional immediate for fixed-point variant. */
20655 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20657 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20658 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20660 /* Data processing, three registers of different lengths. */
20661 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20662 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20663 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20664 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20665 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20666 /* If not scalar, fall back to neon_dyadic_long.
20667 Vector types as above, scalar types S16 S32 U16 U32. */
20668 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20669 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20670 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20671 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20672 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20673 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20674 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20675 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20676 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20677 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20678 /* Saturating doubling multiplies. Types S16 S32. */
20679 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20680 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20681 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20682 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20683 S16 S32 U16 U32. */
20684 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20686 /* Extract. Size 8. */
20687 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20688 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20690 /* Two registers, miscellaneous. */
20691 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20692 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20693 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20694 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20695 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20696 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20697 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20698 /* Vector replicate. Sizes 8 16 32. */
20699 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20700 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20701 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20702 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20703 /* VMOVN. Types I16 I32 I64. */
20704 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20705 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20706 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20707 /* VQMOVUN. Types S16 S32 S64. */
20708 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20709 /* VZIP / VUZP. Sizes 8 16 32. */
20710 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20711 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20712 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20713 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20714 /* VQABS / VQNEG. Types S8 S16 S32. */
20715 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20716 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20717 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20718 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20719 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20720 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20721 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20722 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20723 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20724 /* Reciprocal estimates. Types U32 F16 F32. */
20725 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20726 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20727 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20728 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20729 /* VCLS. Types S8 S16 S32. */
20730 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20731 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20732 /* VCLZ. Types I8 I16 I32. */
20733 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20734 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20735 /* VCNT. Size 8. */
20736 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20737 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20738 /* Two address, untyped. */
20739 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20740 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20741 /* VTRN. Sizes 8 16 32. */
20742 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20743 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20745 /* Table lookup. Size 8. */
20746 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20747 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20749 #undef THUMB_VARIANT
20750 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20752 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20754 /* Neon element/structure load/store. */
20755 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20756 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20757 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20758 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20759 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20760 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20761 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20762 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20764 #undef THUMB_VARIANT
20765 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20767 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20768 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20769 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20770 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20771 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20772 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20773 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20774 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20775 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20776 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20778 #undef THUMB_VARIANT
20779 #define THUMB_VARIANT & fpu_vfp_ext_v3
20781 #define ARM_VARIANT & fpu_vfp_ext_v3
20783 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20784 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20785 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20786 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20787 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20788 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20789 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20790 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20791 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20794 #define ARM_VARIANT & fpu_vfp_ext_fma
20795 #undef THUMB_VARIANT
20796 #define THUMB_VARIANT & fpu_vfp_ext_fma
20797 /* Mnemonics shared by Neon and VFP. These are included in the
20798 VFP FMA variant; NEON and VFP FMA always includes the NEON
20799 FMA instructions. */
20800 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20801 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20802 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20803 the v form should always be used. */
20804 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20805 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20806 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20807 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20808 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20809 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20811 #undef THUMB_VARIANT
20813 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20815 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20816 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20817 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20818 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20819 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20820 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20821 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20822 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20825 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20827 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20828 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20829 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20830 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20831 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20832 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20833 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20834 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20835 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20836 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20837 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20838 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20839 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20840 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20841 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20842 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20843 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20844 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20845 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20846 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20847 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20848 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20849 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20850 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20851 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20852 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20853 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20854 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20855 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20856 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20857 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20858 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20859 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20860 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20861 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20862 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20863 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20864 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20865 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20866 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20867 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20868 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20869 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20870 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20871 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20872 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20873 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20874 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20875 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20876 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20877 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20878 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20879 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20880 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20881 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20882 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20883 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20884 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20885 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20886 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20887 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20888 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20889 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20890 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20891 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20892 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20893 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20894 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20895 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20896 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20897 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20898 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20899 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20900 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20901 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20902 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20903 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20904 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20905 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20906 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20907 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20908 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20909 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20910 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20911 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20912 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20913 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20914 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20915 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20916 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20917 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20918 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20919 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20920 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20921 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20922 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20923 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20924 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20925 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20926 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20927 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20928 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20929 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20930 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20931 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20932 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20933 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20934 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20935 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20936 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20937 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20938 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20939 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20940 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20941 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20942 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20943 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20944 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20945 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20946 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20947 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20948 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20949 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20950 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20951 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20952 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20953 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20954 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20955 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20956 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20957 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20958 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20959 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20960 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20961 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20962 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20963 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20964 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20965 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20966 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20967 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20968 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20969 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20970 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20971 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20972 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20973 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20974 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20975 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20976 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20977 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20978 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20979 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20980 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20981 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20982 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20983 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20984 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20985 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20986 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20987 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20988 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20991 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20993 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20994 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20995 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20996 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20997 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20998 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20999 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21000 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21001 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21002 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21003 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21004 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21005 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21006 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21007 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21008 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21009 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21010 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21011 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21012 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21013 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21014 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21015 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21016 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21017 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21018 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21019 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21020 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21021 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21022 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21023 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21024 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21025 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21026 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21027 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21028 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21029 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21030 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21031 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21032 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21033 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21034 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21035 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21036 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21037 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21038 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21039 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21040 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21041 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21042 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21043 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21044 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21045 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21046 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21047 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21048 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21049 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21052 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21054 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21055 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21056 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21057 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21058 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21059 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21060 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21061 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21062 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21063 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21064 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21065 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21066 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21067 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21068 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21069 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21070 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21071 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21072 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21073 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21074 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21075 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21076 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21077 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21078 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21079 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21080 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21081 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21082 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21083 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21084 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21085 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21086 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21087 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21088 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21089 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21090 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21091 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21092 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21093 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21094 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21095 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21096 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21097 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21098 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21099 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21100 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21101 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21102 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21103 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21104 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21105 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21106 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21107 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21108 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21109 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21110 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21111 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21112 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21113 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21114 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21115 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21116 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21117 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21118 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21119 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21120 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21121 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21122 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21123 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21124 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21125 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21126 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21127 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21128 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21129 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21131 /* ARMv8-M instructions. */
21133 #define ARM_VARIANT NULL
21134 #undef THUMB_VARIANT
21135 #define THUMB_VARIANT & arm_ext_v8m
21136 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21137 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21138 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21139 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21140 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21141 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21142 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21144 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21145 instructions behave as nop if no VFP is present. */
21146 #undef THUMB_VARIANT
21147 #define THUMB_VARIANT & arm_ext_v8m_main
21148 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21149 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21152 #undef THUMB_VARIANT
21178 /* MD interface: bits in the object file. */
21180 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21181 for use in the a.out file, and stores them in the array pointed to by buf.
21182 This knows about the endian-ness of the target machine and does
21183 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21184 2 (short) and 4 (long) Floating numbers are put out as a series of
21185 LITTLENUMS (shorts, here at least). */
21188 md_number_to_chars (char * buf
, valueT val
, int n
)
21190 if (target_big_endian
)
21191 number_to_chars_bigendian (buf
, val
, n
);
21193 number_to_chars_littleendian (buf
, val
, n
);
21197 md_chars_to_number (char * buf
, int n
)
21200 unsigned char * where
= (unsigned char *) buf
;
21202 if (target_big_endian
)
21207 result
|= (*where
++ & 255);
21215 result
|= (where
[n
] & 255);
21222 /* MD interface: Sections. */
21224 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21225 that an rs_machine_dependent frag may reach. */
21228 arm_frag_max_var (fragS
*fragp
)
21230 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21231 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21233 Note that we generate relaxable instructions even for cases that don't
21234 really need it, like an immediate that's a trivial constant. So we're
21235 overestimating the instruction size for some of those cases. Rather
21236 than putting more intelligence here, it would probably be better to
21237 avoid generating a relaxation frag in the first place when it can be
21238 determined up front that a short instruction will suffice. */
21240 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21244 /* Estimate the size of a frag before relaxing. Assume everything fits in
21248 md_estimate_size_before_relax (fragS
* fragp
,
21249 segT segtype ATTRIBUTE_UNUSED
)
21255 /* Convert a machine dependent frag. */
21258 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21260 unsigned long insn
;
21261 unsigned long old_op
;
21269 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21271 old_op
= bfd_get_16(abfd
, buf
);
21272 if (fragp
->fr_symbol
)
21274 exp
.X_op
= O_symbol
;
21275 exp
.X_add_symbol
= fragp
->fr_symbol
;
21279 exp
.X_op
= O_constant
;
21281 exp
.X_add_number
= fragp
->fr_offset
;
21282 opcode
= fragp
->fr_subtype
;
21285 case T_MNEM_ldr_pc
:
21286 case T_MNEM_ldr_pc2
:
21287 case T_MNEM_ldr_sp
:
21288 case T_MNEM_str_sp
:
21295 if (fragp
->fr_var
== 4)
21297 insn
= THUMB_OP32 (opcode
);
21298 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21300 insn
|= (old_op
& 0x700) << 4;
21304 insn
|= (old_op
& 7) << 12;
21305 insn
|= (old_op
& 0x38) << 13;
21307 insn
|= 0x00000c00;
21308 put_thumb32_insn (buf
, insn
);
21309 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21313 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21315 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21318 if (fragp
->fr_var
== 4)
21320 insn
= THUMB_OP32 (opcode
);
21321 insn
|= (old_op
& 0xf0) << 4;
21322 put_thumb32_insn (buf
, insn
);
21323 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21327 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21328 exp
.X_add_number
-= 4;
21336 if (fragp
->fr_var
== 4)
21338 int r0off
= (opcode
== T_MNEM_mov
21339 || opcode
== T_MNEM_movs
) ? 0 : 8;
21340 insn
= THUMB_OP32 (opcode
);
21341 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21342 insn
|= (old_op
& 0x700) << r0off
;
21343 put_thumb32_insn (buf
, insn
);
21344 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21348 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21353 if (fragp
->fr_var
== 4)
21355 insn
= THUMB_OP32(opcode
);
21356 put_thumb32_insn (buf
, insn
);
21357 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21360 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21364 if (fragp
->fr_var
== 4)
21366 insn
= THUMB_OP32(opcode
);
21367 insn
|= (old_op
& 0xf00) << 14;
21368 put_thumb32_insn (buf
, insn
);
21369 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21372 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21375 case T_MNEM_add_sp
:
21376 case T_MNEM_add_pc
:
21377 case T_MNEM_inc_sp
:
21378 case T_MNEM_dec_sp
:
21379 if (fragp
->fr_var
== 4)
21381 /* ??? Choose between add and addw. */
21382 insn
= THUMB_OP32 (opcode
);
21383 insn
|= (old_op
& 0xf0) << 4;
21384 put_thumb32_insn (buf
, insn
);
21385 if (opcode
== T_MNEM_add_pc
)
21386 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21388 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21391 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21399 if (fragp
->fr_var
== 4)
21401 insn
= THUMB_OP32 (opcode
);
21402 insn
|= (old_op
& 0xf0) << 4;
21403 insn
|= (old_op
& 0xf) << 16;
21404 put_thumb32_insn (buf
, insn
);
21405 if (insn
& (1 << 20))
21406 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21408 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21411 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21417 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21418 (enum bfd_reloc_code_real
) reloc_type
);
21419 fixp
->fx_file
= fragp
->fr_file
;
21420 fixp
->fx_line
= fragp
->fr_line
;
21421 fragp
->fr_fix
+= fragp
->fr_var
;
21423 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21424 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21425 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21426 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21429 /* Return the size of a relaxable immediate operand instruction.
21430 SHIFT and SIZE specify the form of the allowable immediate. */
21432 relax_immediate (fragS
*fragp
, int size
, int shift
)
21438 /* ??? Should be able to do better than this. */
21439 if (fragp
->fr_symbol
)
21442 low
= (1 << shift
) - 1;
21443 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21444 offset
= fragp
->fr_offset
;
21445 /* Force misaligned offsets to 32-bit variant. */
21448 if (offset
& ~mask
)
21453 /* Get the address of a symbol during relaxation. */
21455 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21461 sym
= fragp
->fr_symbol
;
21462 sym_frag
= symbol_get_frag (sym
);
21463 know (S_GET_SEGMENT (sym
) != absolute_section
21464 || sym_frag
== &zero_address_frag
);
21465 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21467 /* If frag has yet to be reached on this pass, assume it will
21468 move by STRETCH just as we did. If this is not so, it will
21469 be because some frag between grows, and that will force
21473 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21477 /* Adjust stretch for any alignment frag. Note that if have
21478 been expanding the earlier code, the symbol may be
21479 defined in what appears to be an earlier frag. FIXME:
21480 This doesn't handle the fr_subtype field, which specifies
21481 a maximum number of bytes to skip when doing an
21483 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21485 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21488 stretch
= - ((- stretch
)
21489 & ~ ((1 << (int) f
->fr_offset
) - 1));
21491 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21503 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21506 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21511 /* Assume worst case for symbols not known to be in the same section. */
21512 if (fragp
->fr_symbol
== NULL
21513 || !S_IS_DEFINED (fragp
->fr_symbol
)
21514 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21515 || S_IS_WEAK (fragp
->fr_symbol
))
21518 val
= relaxed_symbol_addr (fragp
, stretch
);
21519 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21520 addr
= (addr
+ 4) & ~3;
21521 /* Force misaligned targets to 32-bit variant. */
21525 if (val
< 0 || val
> 1020)
21530 /* Return the size of a relaxable add/sub immediate instruction. */
21532 relax_addsub (fragS
*fragp
, asection
*sec
)
21537 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21538 op
= bfd_get_16(sec
->owner
, buf
);
21539 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21540 return relax_immediate (fragp
, 8, 0);
21542 return relax_immediate (fragp
, 3, 0);
21545 /* Return TRUE iff the definition of symbol S could be pre-empted
21546 (overridden) at link or load time. */
21548 symbol_preemptible (symbolS
*s
)
21550 /* Weak symbols can always be pre-empted. */
21554 /* Non-global symbols cannot be pre-empted. */
21555 if (! S_IS_EXTERNAL (s
))
21559 /* In ELF, a global symbol can be marked protected, or private. In that
21560 case it can't be pre-empted (other definitions in the same link unit
21561 would violate the ODR). */
21562 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21566 /* Other global symbols might be pre-empted. */
21570 /* Return the size of a relaxable branch instruction. BITS is the
21571 size of the offset field in the narrow instruction. */
21574 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21580 /* Assume worst case for symbols not known to be in the same section. */
21581 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21582 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21583 || S_IS_WEAK (fragp
->fr_symbol
))
21587 /* A branch to a function in ARM state will require interworking. */
21588 if (S_IS_DEFINED (fragp
->fr_symbol
)
21589 && ARM_IS_FUNC (fragp
->fr_symbol
))
21593 if (symbol_preemptible (fragp
->fr_symbol
))
21596 val
= relaxed_symbol_addr (fragp
, stretch
);
21597 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21600 /* Offset is a signed value *2 */
21602 if (val
>= limit
|| val
< -limit
)
21608 /* Relax a machine dependent frag. This returns the amount by which
21609 the current size of the frag should change. */
21612 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21617 oldsize
= fragp
->fr_var
;
21618 switch (fragp
->fr_subtype
)
21620 case T_MNEM_ldr_pc2
:
21621 newsize
= relax_adr (fragp
, sec
, stretch
);
21623 case T_MNEM_ldr_pc
:
21624 case T_MNEM_ldr_sp
:
21625 case T_MNEM_str_sp
:
21626 newsize
= relax_immediate (fragp
, 8, 2);
21630 newsize
= relax_immediate (fragp
, 5, 2);
21634 newsize
= relax_immediate (fragp
, 5, 1);
21638 newsize
= relax_immediate (fragp
, 5, 0);
21641 newsize
= relax_adr (fragp
, sec
, stretch
);
21647 newsize
= relax_immediate (fragp
, 8, 0);
21650 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21653 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21655 case T_MNEM_add_sp
:
21656 case T_MNEM_add_pc
:
21657 newsize
= relax_immediate (fragp
, 8, 2);
21659 case T_MNEM_inc_sp
:
21660 case T_MNEM_dec_sp
:
21661 newsize
= relax_immediate (fragp
, 7, 2);
21667 newsize
= relax_addsub (fragp
, sec
);
21673 fragp
->fr_var
= newsize
;
21674 /* Freeze wide instructions that are at or before the same location as
21675 in the previous pass. This avoids infinite loops.
21676 Don't freeze them unconditionally because targets may be artificially
21677 misaligned by the expansion of preceding frags. */
21678 if (stretch
<= 0 && newsize
> 2)
21680 md_convert_frag (sec
->owner
, sec
, fragp
);
21684 return newsize
- oldsize
;
21687 /* Round up a section size to the appropriate boundary. */
21690 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21693 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21694 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21696 /* For a.out, force the section size to be aligned. If we don't do
21697 this, BFD will align it for us, but it will not write out the
21698 final bytes of the section. This may be a bug in BFD, but it is
21699 easier to fix it here since that is how the other a.out targets
21703 align
= bfd_get_section_alignment (stdoutput
, segment
);
21704 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21711 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21712 of an rs_align_code fragment. */
21715 arm_handle_align (fragS
* fragP
)
21717 static unsigned char const arm_noop
[2][2][4] =
21720 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21721 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21724 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21725 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21728 static unsigned char const thumb_noop
[2][2][2] =
21731 {0xc0, 0x46}, /* LE */
21732 {0x46, 0xc0}, /* BE */
21735 {0x00, 0xbf}, /* LE */
21736 {0xbf, 0x00} /* BE */
21739 static unsigned char const wide_thumb_noop
[2][4] =
21740 { /* Wide Thumb-2 */
21741 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21742 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21745 unsigned bytes
, fix
, noop_size
;
21747 const unsigned char * noop
;
21748 const unsigned char *narrow_noop
= NULL
;
21753 if (fragP
->fr_type
!= rs_align_code
)
21756 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21757 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21760 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21761 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21763 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21765 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21767 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21768 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21770 narrow_noop
= thumb_noop
[1][target_big_endian
];
21771 noop
= wide_thumb_noop
[target_big_endian
];
21774 noop
= thumb_noop
[0][target_big_endian
];
21782 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21783 ? selected_cpu
: arm_arch_none
,
21785 [target_big_endian
];
21792 fragP
->fr_var
= noop_size
;
21794 if (bytes
& (noop_size
- 1))
21796 fix
= bytes
& (noop_size
- 1);
21798 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21800 memset (p
, 0, fix
);
21807 if (bytes
& noop_size
)
21809 /* Insert a narrow noop. */
21810 memcpy (p
, narrow_noop
, noop_size
);
21812 bytes
-= noop_size
;
21816 /* Use wide noops for the remainder */
21820 while (bytes
>= noop_size
)
21822 memcpy (p
, noop
, noop_size
);
21824 bytes
-= noop_size
;
21828 fragP
->fr_fix
+= fix
;
21831 /* Called from md_do_align. Used to create an alignment
21832 frag in a code section. */
21835 arm_frag_align_code (int n
, int max
)
21839 /* We assume that there will never be a requirement
21840 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21841 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21846 _("alignments greater than %d bytes not supported in .text sections."),
21847 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21848 as_fatal ("%s", err_msg
);
21851 p
= frag_var (rs_align_code
,
21852 MAX_MEM_FOR_RS_ALIGN_CODE
,
21854 (relax_substateT
) max
,
21861 /* Perform target specific initialisation of a frag.
21862 Note - despite the name this initialisation is not done when the frag
21863 is created, but only when its type is assigned. A frag can be created
21864 and used a long time before its type is set, so beware of assuming that
21865 this initialisation is performed first. */
21869 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21871 /* Record whether this frag is in an ARM or a THUMB area. */
21872 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21875 #else /* OBJ_ELF is defined. */
21877 arm_init_frag (fragS
* fragP
, int max_chars
)
21879 int frag_thumb_mode
;
21881 /* If the current ARM vs THUMB mode has not already
21882 been recorded into this frag then do so now. */
21883 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21884 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21886 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21888 /* Record a mapping symbol for alignment frags. We will delete this
21889 later if the alignment ends up empty. */
21890 switch (fragP
->fr_type
)
21893 case rs_align_test
:
21895 mapping_state_2 (MAP_DATA
, max_chars
);
21897 case rs_align_code
:
21898 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21905 /* When we change sections we need to issue a new mapping symbol. */
21908 arm_elf_change_section (void)
21910 /* Link an unlinked unwind index table section to the .text section. */
21911 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21912 && elf_linked_to_section (now_seg
) == NULL
)
21913 elf_linked_to_section (now_seg
) = text_section
;
21917 arm_elf_section_type (const char * str
, size_t len
)
21919 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21920 return SHT_ARM_EXIDX
;
21925 /* Code to deal with unwinding tables. */
21927 static void add_unwind_adjustsp (offsetT
);
21929 /* Generate any deferred unwind frame offset. */
21932 flush_pending_unwind (void)
21936 offset
= unwind
.pending_offset
;
21937 unwind
.pending_offset
= 0;
21939 add_unwind_adjustsp (offset
);
21942 /* Add an opcode to this list for this function. Two-byte opcodes should
21943 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21947 add_unwind_opcode (valueT op
, int length
)
21949 /* Add any deferred stack adjustment. */
21950 if (unwind
.pending_offset
)
21951 flush_pending_unwind ();
21953 unwind
.sp_restored
= 0;
21955 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21957 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21958 if (unwind
.opcodes
)
21959 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21960 unwind
.opcode_alloc
);
21962 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21967 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21969 unwind
.opcode_count
++;
21973 /* Add unwind opcodes to adjust the stack pointer. */
21976 add_unwind_adjustsp (offsetT offset
)
21980 if (offset
> 0x200)
21982 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21987 /* Long form: 0xb2, uleb128. */
21988 /* This might not fit in a word so add the individual bytes,
21989 remembering the list is built in reverse order. */
21990 o
= (valueT
) ((offset
- 0x204) >> 2);
21992 add_unwind_opcode (0, 1);
21994 /* Calculate the uleb128 encoding of the offset. */
21998 bytes
[n
] = o
& 0x7f;
22004 /* Add the insn. */
22006 add_unwind_opcode (bytes
[n
- 1], 1);
22007 add_unwind_opcode (0xb2, 1);
22009 else if (offset
> 0x100)
22011 /* Two short opcodes. */
22012 add_unwind_opcode (0x3f, 1);
22013 op
= (offset
- 0x104) >> 2;
22014 add_unwind_opcode (op
, 1);
22016 else if (offset
> 0)
22018 /* Short opcode. */
22019 op
= (offset
- 4) >> 2;
22020 add_unwind_opcode (op
, 1);
22022 else if (offset
< 0)
22025 while (offset
> 0x100)
22027 add_unwind_opcode (0x7f, 1);
22030 op
= ((offset
- 4) >> 2) | 0x40;
22031 add_unwind_opcode (op
, 1);
22035 /* Finish the list of unwind opcodes for this function. */
22037 finish_unwind_opcodes (void)
22041 if (unwind
.fp_used
)
22043 /* Adjust sp as necessary. */
22044 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22045 flush_pending_unwind ();
22047 /* After restoring sp from the frame pointer. */
22048 op
= 0x90 | unwind
.fp_reg
;
22049 add_unwind_opcode (op
, 1);
22052 flush_pending_unwind ();
22056 /* Start an exception table entry. If idx is nonzero this is an index table
22060 start_unwind_section (const segT text_seg
, int idx
)
22062 const char * text_name
;
22063 const char * prefix
;
22064 const char * prefix_once
;
22065 const char * group_name
;
22073 prefix
= ELF_STRING_ARM_unwind
;
22074 prefix_once
= ELF_STRING_ARM_unwind_once
;
22075 type
= SHT_ARM_EXIDX
;
22079 prefix
= ELF_STRING_ARM_unwind_info
;
22080 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22081 type
= SHT_PROGBITS
;
22084 text_name
= segment_name (text_seg
);
22085 if (streq (text_name
, ".text"))
22088 if (strncmp (text_name
, ".gnu.linkonce.t.",
22089 strlen (".gnu.linkonce.t.")) == 0)
22091 prefix
= prefix_once
;
22092 text_name
+= strlen (".gnu.linkonce.t.");
22095 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22101 /* Handle COMDAT group. */
22102 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22104 group_name
= elf_group_name (text_seg
);
22105 if (group_name
== NULL
)
22107 as_bad (_("Group section `%s' has no group signature"),
22108 segment_name (text_seg
));
22109 ignore_rest_of_line ();
22112 flags
|= SHF_GROUP
;
22116 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22119 /* Set the section link for index tables. */
22121 elf_linked_to_section (now_seg
) = text_seg
;
22125 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22126 personality routine data. Returns zero, or the index table value for
22127 an inline entry. */
22130 create_unwind_entry (int have_data
)
22135 /* The current word of data. */
22137 /* The number of bytes left in this word. */
22140 finish_unwind_opcodes ();
22142 /* Remember the current text section. */
22143 unwind
.saved_seg
= now_seg
;
22144 unwind
.saved_subseg
= now_subseg
;
22146 start_unwind_section (now_seg
, 0);
22148 if (unwind
.personality_routine
== NULL
)
22150 if (unwind
.personality_index
== -2)
22153 as_bad (_("handlerdata in cantunwind frame"));
22154 return 1; /* EXIDX_CANTUNWIND. */
22157 /* Use a default personality routine if none is specified. */
22158 if (unwind
.personality_index
== -1)
22160 if (unwind
.opcode_count
> 3)
22161 unwind
.personality_index
= 1;
22163 unwind
.personality_index
= 0;
22166 /* Space for the personality routine entry. */
22167 if (unwind
.personality_index
== 0)
22169 if (unwind
.opcode_count
> 3)
22170 as_bad (_("too many unwind opcodes for personality routine 0"));
22174 /* All the data is inline in the index table. */
22177 while (unwind
.opcode_count
> 0)
22179 unwind
.opcode_count
--;
22180 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22184 /* Pad with "finish" opcodes. */
22186 data
= (data
<< 8) | 0xb0;
22193 /* We get two opcodes "free" in the first word. */
22194 size
= unwind
.opcode_count
- 2;
22198 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22199 if (unwind
.personality_index
!= -1)
22201 as_bad (_("attempt to recreate an unwind entry"));
22205 /* An extra byte is required for the opcode count. */
22206 size
= unwind
.opcode_count
+ 1;
22209 size
= (size
+ 3) >> 2;
22211 as_bad (_("too many unwind opcodes"));
22213 frag_align (2, 0, 0);
22214 record_alignment (now_seg
, 2);
22215 unwind
.table_entry
= expr_build_dot ();
22217 /* Allocate the table entry. */
22218 ptr
= frag_more ((size
<< 2) + 4);
22219 /* PR 13449: Zero the table entries in case some of them are not used. */
22220 memset (ptr
, 0, (size
<< 2) + 4);
22221 where
= frag_now_fix () - ((size
<< 2) + 4);
22223 switch (unwind
.personality_index
)
22226 /* ??? Should this be a PLT generating relocation? */
22227 /* Custom personality routine. */
22228 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22229 BFD_RELOC_ARM_PREL31
);
22234 /* Set the first byte to the number of additional words. */
22235 data
= size
> 0 ? size
- 1 : 0;
22239 /* ABI defined personality routines. */
22241 /* Three opcodes bytes are packed into the first word. */
22248 /* The size and first two opcode bytes go in the first word. */
22249 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22254 /* Should never happen. */
22258 /* Pack the opcodes into words (MSB first), reversing the list at the same
22260 while (unwind
.opcode_count
> 0)
22264 md_number_to_chars (ptr
, data
, 4);
22269 unwind
.opcode_count
--;
22271 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22274 /* Finish off the last word. */
22277 /* Pad with "finish" opcodes. */
22279 data
= (data
<< 8) | 0xb0;
22281 md_number_to_chars (ptr
, data
, 4);
22286 /* Add an empty descriptor if there is no user-specified data. */
22287 ptr
= frag_more (4);
22288 md_number_to_chars (ptr
, 0, 4);
22295 /* Initialize the DWARF-2 unwind information for this procedure. */
22298 tc_arm_frame_initial_instructions (void)
22300 cfi_add_CFA_def_cfa (REG_SP
, 0);
22302 #endif /* OBJ_ELF */
22304 /* Convert REGNAME to a DWARF-2 register number. */
22307 tc_arm_regname_to_dw2regnum (char *regname
)
22309 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22313 /* PR 16694: Allow VFP registers as well. */
22314 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22318 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22327 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22331 exp
.X_op
= O_secrel
;
22332 exp
.X_add_symbol
= symbol
;
22333 exp
.X_add_number
= 0;
22334 emit_expr (&exp
, size
);
22338 /* MD interface: Symbol and relocation handling. */
22340 /* Return the address within the segment that a PC-relative fixup is
22341 relative to. For ARM, PC-relative fixups applied to instructions
22342 are generally relative to the location of the fixup plus 8 bytes.
22343 Thumb branches are offset by 4, and Thumb loads relative to PC
22344 require special handling. */
22347 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22349 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22351 /* If this is pc-relative and we are going to emit a relocation
22352 then we just want to put out any pipeline compensation that the linker
22353 will need. Otherwise we want to use the calculated base.
22354 For WinCE we skip the bias for externals as well, since this
22355 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22357 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22358 || (arm_force_relocation (fixP
)
22360 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22366 switch (fixP
->fx_r_type
)
22368 /* PC relative addressing on the Thumb is slightly odd as the
22369 bottom two bits of the PC are forced to zero for the
22370 calculation. This happens *after* application of the
22371 pipeline offset. However, Thumb adrl already adjusts for
22372 this, so we need not do it again. */
22373 case BFD_RELOC_ARM_THUMB_ADD
:
22376 case BFD_RELOC_ARM_THUMB_OFFSET
:
22377 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22378 case BFD_RELOC_ARM_T32_ADD_PC12
:
22379 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22380 return (base
+ 4) & ~3;
22382 /* Thumb branches are simply offset by +4. */
22383 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22384 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22385 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22386 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22387 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22390 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22392 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22393 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22394 && ARM_IS_FUNC (fixP
->fx_addsy
)
22395 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22396 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22399 /* BLX is like branches above, but forces the low two bits of PC to
22401 case BFD_RELOC_THUMB_PCREL_BLX
:
22403 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22404 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22405 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22406 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22407 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22408 return (base
+ 4) & ~3;
22410 /* ARM mode branches are offset by +8. However, the Windows CE
22411 loader expects the relocation not to take this into account. */
22412 case BFD_RELOC_ARM_PCREL_BLX
:
22414 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22415 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22416 && ARM_IS_FUNC (fixP
->fx_addsy
)
22417 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22418 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22421 case BFD_RELOC_ARM_PCREL_CALL
:
22423 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22424 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22425 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22426 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22427 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22430 case BFD_RELOC_ARM_PCREL_BRANCH
:
22431 case BFD_RELOC_ARM_PCREL_JUMP
:
22432 case BFD_RELOC_ARM_PLT32
:
22434 /* When handling fixups immediately, because we have already
22435 discovered the value of a symbol, or the address of the frag involved
22436 we must account for the offset by +8, as the OS loader will never see the reloc.
22437 see fixup_segment() in write.c
22438 The S_IS_EXTERNAL test handles the case of global symbols.
22439 Those need the calculated base, not just the pipe compensation the linker will need. */
22441 && fixP
->fx_addsy
!= NULL
22442 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22443 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22451 /* ARM mode loads relative to PC are also offset by +8. Unlike
22452 branches, the Windows CE loader *does* expect the relocation
22453 to take this into account. */
22454 case BFD_RELOC_ARM_OFFSET_IMM
:
22455 case BFD_RELOC_ARM_OFFSET_IMM8
:
22456 case BFD_RELOC_ARM_HWLITERAL
:
22457 case BFD_RELOC_ARM_LITERAL
:
22458 case BFD_RELOC_ARM_CP_OFF_IMM
:
22462 /* Other PC-relative relocations are un-offset. */
22468 static bfd_boolean flag_warn_syms
= TRUE
;
22471 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22473 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22474 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22475 does mean that the resulting code might be very confusing to the reader.
22476 Also this warning can be triggered if the user omits an operand before
22477 an immediate address, eg:
22481 GAS treats this as an assignment of the value of the symbol foo to a
22482 symbol LDR, and so (without this code) it will not issue any kind of
22483 warning or error message.
22485 Note - ARM instructions are case-insensitive but the strings in the hash
22486 table are all stored in lower case, so we must first ensure that name is
22488 if (flag_warn_syms
&& arm_ops_hsh
)
22490 char * nbuf
= strdup (name
);
22493 for (p
= nbuf
; *p
; p
++)
22495 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22497 static struct hash_control
* already_warned
= NULL
;
22499 if (already_warned
== NULL
)
22500 already_warned
= hash_new ();
22501 /* Only warn about the symbol once. To keep the code
22502 simple we let hash_insert do the lookup for us. */
22503 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22504 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22513 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22514 Otherwise we have no need to default values of symbols. */
22517 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22520 if (name
[0] == '_' && name
[1] == 'G'
22521 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22525 if (symbol_find (name
))
22526 as_bad (_("GOT already in the symbol table"));
22528 GOT_symbol
= symbol_new (name
, undefined_section
,
22529 (valueT
) 0, & zero_address_frag
);
22539 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22540 computed as two separate immediate values, added together. We
22541 already know that this value cannot be computed by just one ARM
22544 static unsigned int
22545 validate_immediate_twopart (unsigned int val
,
22546 unsigned int * highpart
)
22551 for (i
= 0; i
< 32; i
+= 2)
22552 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22558 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22560 else if (a
& 0xff0000)
22562 if (a
& 0xff000000)
22564 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22568 gas_assert (a
& 0xff000000);
22569 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22572 return (a
& 0xff) | (i
<< 7);
22579 validate_offset_imm (unsigned int val
, int hwse
)
22581 if ((hwse
&& val
> 255) || val
> 4095)
22586 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22587 negative immediate constant by altering the instruction. A bit of
22592 by inverting the second operand, and
22595 by negating the second operand. */
22598 negate_data_op (unsigned long * instruction
,
22599 unsigned long value
)
22602 unsigned long negated
, inverted
;
22604 negated
= encode_arm_immediate (-value
);
22605 inverted
= encode_arm_immediate (~value
);
22607 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22610 /* First negates. */
22611 case OPCODE_SUB
: /* ADD <-> SUB */
22612 new_inst
= OPCODE_ADD
;
22617 new_inst
= OPCODE_SUB
;
22621 case OPCODE_CMP
: /* CMP <-> CMN */
22622 new_inst
= OPCODE_CMN
;
22627 new_inst
= OPCODE_CMP
;
22631 /* Now Inverted ops. */
22632 case OPCODE_MOV
: /* MOV <-> MVN */
22633 new_inst
= OPCODE_MVN
;
22638 new_inst
= OPCODE_MOV
;
22642 case OPCODE_AND
: /* AND <-> BIC */
22643 new_inst
= OPCODE_BIC
;
22648 new_inst
= OPCODE_AND
;
22652 case OPCODE_ADC
: /* ADC <-> SBC */
22653 new_inst
= OPCODE_SBC
;
22658 new_inst
= OPCODE_ADC
;
22662 /* We cannot do anything. */
22667 if (value
== (unsigned) FAIL
)
22670 *instruction
&= OPCODE_MASK
;
22671 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22675 /* Like negate_data_op, but for Thumb-2. */
22677 static unsigned int
22678 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22682 unsigned int negated
, inverted
;
22684 negated
= encode_thumb32_immediate (-value
);
22685 inverted
= encode_thumb32_immediate (~value
);
22687 rd
= (*instruction
>> 8) & 0xf;
22688 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22691 /* ADD <-> SUB. Includes CMP <-> CMN. */
22692 case T2_OPCODE_SUB
:
22693 new_inst
= T2_OPCODE_ADD
;
22697 case T2_OPCODE_ADD
:
22698 new_inst
= T2_OPCODE_SUB
;
22702 /* ORR <-> ORN. Includes MOV <-> MVN. */
22703 case T2_OPCODE_ORR
:
22704 new_inst
= T2_OPCODE_ORN
;
22708 case T2_OPCODE_ORN
:
22709 new_inst
= T2_OPCODE_ORR
;
22713 /* AND <-> BIC. TST has no inverted equivalent. */
22714 case T2_OPCODE_AND
:
22715 new_inst
= T2_OPCODE_BIC
;
22722 case T2_OPCODE_BIC
:
22723 new_inst
= T2_OPCODE_AND
;
22728 case T2_OPCODE_ADC
:
22729 new_inst
= T2_OPCODE_SBC
;
22733 case T2_OPCODE_SBC
:
22734 new_inst
= T2_OPCODE_ADC
;
22738 /* We cannot do anything. */
22743 if (value
== (unsigned int)FAIL
)
22746 *instruction
&= T2_OPCODE_MASK
;
22747 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22751 /* Read a 32-bit thumb instruction from buf. */
22752 static unsigned long
22753 get_thumb32_insn (char * buf
)
22755 unsigned long insn
;
22756 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22757 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22763 /* We usually want to set the low bit on the address of thumb function
22764 symbols. In particular .word foo - . should have the low bit set.
22765 Generic code tries to fold the difference of two symbols to
22766 a constant. Prevent this and force a relocation when the first symbols
22767 is a thumb function. */
22770 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22772 if (op
== O_subtract
22773 && l
->X_op
== O_symbol
22774 && r
->X_op
== O_symbol
22775 && THUMB_IS_FUNC (l
->X_add_symbol
))
22777 l
->X_op
= O_subtract
;
22778 l
->X_op_symbol
= r
->X_add_symbol
;
22779 l
->X_add_number
-= r
->X_add_number
;
22783 /* Process as normal. */
22787 /* Encode Thumb2 unconditional branches and calls. The encoding
22788 for the 2 are identical for the immediate values. */
22791 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22793 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22796 addressT S
, I1
, I2
, lo
, hi
;
22798 S
= (value
>> 24) & 0x01;
22799 I1
= (value
>> 23) & 0x01;
22800 I2
= (value
>> 22) & 0x01;
22801 hi
= (value
>> 12) & 0x3ff;
22802 lo
= (value
>> 1) & 0x7ff;
22803 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22804 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22805 newval
|= (S
<< 10) | hi
;
22806 newval2
&= ~T2I1I2MASK
;
22807 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22808 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22809 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22813 md_apply_fix (fixS
* fixP
,
22817 offsetT value
= * valP
;
22819 unsigned int newimm
;
22820 unsigned long temp
;
22822 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22824 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22826 /* Note whether this will delete the relocation. */
22828 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22831 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22832 consistency with the behaviour on 32-bit hosts. Remember value
22834 value
&= 0xffffffff;
22835 value
^= 0x80000000;
22836 value
-= 0x80000000;
22839 fixP
->fx_addnumber
= value
;
22841 /* Same treatment for fixP->fx_offset. */
22842 fixP
->fx_offset
&= 0xffffffff;
22843 fixP
->fx_offset
^= 0x80000000;
22844 fixP
->fx_offset
-= 0x80000000;
22846 switch (fixP
->fx_r_type
)
22848 case BFD_RELOC_NONE
:
22849 /* This will need to go in the object file. */
22853 case BFD_RELOC_ARM_IMMEDIATE
:
22854 /* We claim that this fixup has been processed here,
22855 even if in fact we generate an error because we do
22856 not have a reloc for it, so tc_gen_reloc will reject it. */
22859 if (fixP
->fx_addsy
)
22861 const char *msg
= 0;
22863 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22864 msg
= _("undefined symbol %s used as an immediate value");
22865 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22866 msg
= _("symbol %s is in a different section");
22867 else if (S_IS_WEAK (fixP
->fx_addsy
))
22868 msg
= _("symbol %s is weak and may be overridden later");
22872 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22873 msg
, S_GET_NAME (fixP
->fx_addsy
));
22878 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22880 /* If the offset is negative, we should use encoding A2 for ADR. */
22881 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22882 newimm
= negate_data_op (&temp
, value
);
22885 newimm
= encode_arm_immediate (value
);
22887 /* If the instruction will fail, see if we can fix things up by
22888 changing the opcode. */
22889 if (newimm
== (unsigned int) FAIL
)
22890 newimm
= negate_data_op (&temp
, value
);
22891 /* MOV accepts both ARM modified immediate (A1 encoding) and
22892 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
22893 When disassembling, MOV is preferred when there is no encoding
22895 if (newimm
== (unsigned int) FAIL
22896 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
22897 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
22898 && !((temp
>> SBIT_SHIFT
) & 0x1)
22899 && value
>= 0 && value
<= 0xffff)
22901 /* Clear bits[23:20] to change encoding from A1 to A2. */
22902 temp
&= 0xff0fffff;
22903 /* Encoding high 4bits imm. Code below will encode the remaining
22905 temp
|= (value
& 0x0000f000) << 4;
22906 newimm
= value
& 0x00000fff;
22910 if (newimm
== (unsigned int) FAIL
)
22912 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22913 _("invalid constant (%lx) after fixup"),
22914 (unsigned long) value
);
22918 newimm
|= (temp
& 0xfffff000);
22919 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22922 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22924 unsigned int highpart
= 0;
22925 unsigned int newinsn
= 0xe1a00000; /* nop. */
22927 if (fixP
->fx_addsy
)
22929 const char *msg
= 0;
22931 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22932 msg
= _("undefined symbol %s used as an immediate value");
22933 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22934 msg
= _("symbol %s is in a different section");
22935 else if (S_IS_WEAK (fixP
->fx_addsy
))
22936 msg
= _("symbol %s is weak and may be overridden later");
22940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22941 msg
, S_GET_NAME (fixP
->fx_addsy
));
22946 newimm
= encode_arm_immediate (value
);
22947 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22949 /* If the instruction will fail, see if we can fix things up by
22950 changing the opcode. */
22951 if (newimm
== (unsigned int) FAIL
22952 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22954 /* No ? OK - try using two ADD instructions to generate
22956 newimm
= validate_immediate_twopart (value
, & highpart
);
22958 /* Yes - then make sure that the second instruction is
22960 if (newimm
!= (unsigned int) FAIL
)
22962 /* Still No ? Try using a negated value. */
22963 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22964 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22965 /* Otherwise - give up. */
22968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22969 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22974 /* Replace the first operand in the 2nd instruction (which
22975 is the PC) with the destination register. We have
22976 already added in the PC in the first instruction and we
22977 do not want to do it again. */
22978 newinsn
&= ~ 0xf0000;
22979 newinsn
|= ((newinsn
& 0x0f000) << 4);
22982 newimm
|= (temp
& 0xfffff000);
22983 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22985 highpart
|= (newinsn
& 0xfffff000);
22986 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22990 case BFD_RELOC_ARM_OFFSET_IMM
:
22991 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22993 /* Fall through. */
22995 case BFD_RELOC_ARM_LITERAL
:
23001 if (validate_offset_imm (value
, 0) == FAIL
)
23003 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23005 _("invalid literal constant: pool needs to be closer"));
23007 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23008 _("bad immediate value for offset (%ld)"),
23013 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23015 newval
&= 0xfffff000;
23018 newval
&= 0xff7ff000;
23019 newval
|= value
| (sign
? INDEX_UP
: 0);
23021 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23024 case BFD_RELOC_ARM_OFFSET_IMM8
:
23025 case BFD_RELOC_ARM_HWLITERAL
:
23031 if (validate_offset_imm (value
, 1) == FAIL
)
23033 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23034 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23035 _("invalid literal constant: pool needs to be closer"));
23037 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23038 _("bad immediate value for 8-bit offset (%ld)"),
23043 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23045 newval
&= 0xfffff0f0;
23048 newval
&= 0xff7ff0f0;
23049 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23051 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23054 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23055 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23056 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23057 _("bad immediate value for offset (%ld)"), (long) value
);
23060 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23062 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23065 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23066 /* This is a complicated relocation used for all varieties of Thumb32
23067 load/store instruction with immediate offset:
23069 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23070 *4, optional writeback(W)
23071 (doubleword load/store)
23073 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23074 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23075 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23076 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23077 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23079 Uppercase letters indicate bits that are already encoded at
23080 this point. Lowercase letters are our problem. For the
23081 second block of instructions, the secondary opcode nybble
23082 (bits 8..11) is present, and bit 23 is zero, even if this is
23083 a PC-relative operation. */
23084 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23086 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23088 if ((newval
& 0xf0000000) == 0xe0000000)
23090 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23092 newval
|= (1 << 23);
23095 if (value
% 4 != 0)
23097 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23098 _("offset not a multiple of 4"));
23104 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23105 _("offset out of range"));
23110 else if ((newval
& 0x000f0000) == 0x000f0000)
23112 /* PC-relative, 12-bit offset. */
23114 newval
|= (1 << 23);
23119 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23120 _("offset out of range"));
23125 else if ((newval
& 0x00000100) == 0x00000100)
23127 /* Writeback: 8-bit, +/- offset. */
23129 newval
|= (1 << 9);
23134 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23135 _("offset out of range"));
23140 else if ((newval
& 0x00000f00) == 0x00000e00)
23142 /* T-instruction: positive 8-bit offset. */
23143 if (value
< 0 || value
> 0xff)
23145 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23146 _("offset out of range"));
23154 /* Positive 12-bit or negative 8-bit offset. */
23158 newval
|= (1 << 23);
23168 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23169 _("offset out of range"));
23176 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23177 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23180 case BFD_RELOC_ARM_SHIFT_IMM
:
23181 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23182 if (((unsigned long) value
) > 32
23184 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23186 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23187 _("shift expression is too large"));
23192 /* Shifts of zero must be done as lsl. */
23194 else if (value
== 32)
23196 newval
&= 0xfffff07f;
23197 newval
|= (value
& 0x1f) << 7;
23198 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23201 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23202 case BFD_RELOC_ARM_T32_ADD_IMM
:
23203 case BFD_RELOC_ARM_T32_IMM12
:
23204 case BFD_RELOC_ARM_T32_ADD_PC12
:
23205 /* We claim that this fixup has been processed here,
23206 even if in fact we generate an error because we do
23207 not have a reloc for it, so tc_gen_reloc will reject it. */
23211 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23213 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23214 _("undefined symbol %s used as an immediate value"),
23215 S_GET_NAME (fixP
->fx_addsy
));
23219 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23221 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23224 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23225 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23226 Thumb2 modified immediate encoding (T2). */
23227 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23228 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23230 newimm
= encode_thumb32_immediate (value
);
23231 if (newimm
== (unsigned int) FAIL
)
23232 newimm
= thumb32_negate_data_op (&newval
, value
);
23234 if (newimm
== (unsigned int) FAIL
)
23236 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23238 /* Turn add/sum into addw/subw. */
23239 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23240 newval
= (newval
& 0xfeffffff) | 0x02000000;
23241 /* No flat 12-bit imm encoding for addsw/subsw. */
23242 if ((newval
& 0x00100000) == 0)
23244 /* 12 bit immediate for addw/subw. */
23248 newval
^= 0x00a00000;
23251 newimm
= (unsigned int) FAIL
;
23258 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23259 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23260 disassembling, MOV is preferred when there is no encoding
23262 NOTE: MOV is using ORR opcode under Thumb 2 mode. */
23263 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23264 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23265 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23266 && value
>= 0 && value
<=0xffff)
23268 /* Toggle bit[25] to change encoding from T2 to T3. */
23270 /* Clear bits[19:16]. */
23271 newval
&= 0xfff0ffff;
23272 /* Encoding high 4bits imm. Code below will encode the
23273 remaining low 12bits. */
23274 newval
|= (value
& 0x0000f000) << 4;
23275 newimm
= value
& 0x00000fff;
23280 if (newimm
== (unsigned int)FAIL
)
23282 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23283 _("invalid constant (%lx) after fixup"),
23284 (unsigned long) value
);
23288 newval
|= (newimm
& 0x800) << 15;
23289 newval
|= (newimm
& 0x700) << 4;
23290 newval
|= (newimm
& 0x0ff);
23292 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23293 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23296 case BFD_RELOC_ARM_SMC
:
23297 if (((unsigned long) value
) > 0xffff)
23298 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23299 _("invalid smc expression"));
23300 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23301 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23302 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23305 case BFD_RELOC_ARM_HVC
:
23306 if (((unsigned long) value
) > 0xffff)
23307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23308 _("invalid hvc expression"));
23309 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23310 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23311 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23314 case BFD_RELOC_ARM_SWI
:
23315 if (fixP
->tc_fix_data
!= 0)
23317 if (((unsigned long) value
) > 0xff)
23318 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23319 _("invalid swi expression"));
23320 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23322 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23326 if (((unsigned long) value
) > 0x00ffffff)
23327 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23328 _("invalid swi expression"));
23329 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23331 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23335 case BFD_RELOC_ARM_MULTI
:
23336 if (((unsigned long) value
) > 0xffff)
23337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23338 _("invalid expression in load/store multiple"));
23339 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23340 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23344 case BFD_RELOC_ARM_PCREL_CALL
:
23346 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23348 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23349 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23350 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23351 /* Flip the bl to blx. This is a simple flip
23352 bit here because we generate PCREL_CALL for
23353 unconditional bls. */
23355 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23356 newval
= newval
| 0x10000000;
23357 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23363 goto arm_branch_common
;
23365 case BFD_RELOC_ARM_PCREL_JUMP
:
23366 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23368 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23369 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23370 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23372 /* This would map to a bl<cond>, b<cond>,
23373 b<always> to a Thumb function. We
23374 need to force a relocation for this particular
23376 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23379 /* Fall through. */
23381 case BFD_RELOC_ARM_PLT32
:
23383 case BFD_RELOC_ARM_PCREL_BRANCH
:
23385 goto arm_branch_common
;
23387 case BFD_RELOC_ARM_PCREL_BLX
:
23390 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23392 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23393 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23394 && ARM_IS_FUNC (fixP
->fx_addsy
))
23396 /* Flip the blx to a bl and warn. */
23397 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23398 newval
= 0xeb000000;
23399 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23400 _("blx to '%s' an ARM ISA state function changed to bl"),
23402 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23408 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23409 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23413 /* We are going to store value (shifted right by two) in the
23414 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23415 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23416 also be be clear. */
23418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23419 _("misaligned branch destination"));
23420 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23421 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23422 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23424 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23426 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23427 newval
|= (value
>> 2) & 0x00ffffff;
23428 /* Set the H bit on BLX instructions. */
23432 newval
|= 0x01000000;
23434 newval
&= ~0x01000000;
23436 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23440 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23441 /* CBZ can only branch forward. */
23443 /* Attempts to use CBZ to branch to the next instruction
23444 (which, strictly speaking, are prohibited) will be turned into
23447 FIXME: It may be better to remove the instruction completely and
23448 perform relaxation. */
23451 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23452 newval
= 0xbf00; /* NOP encoding T1 */
23453 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23458 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23460 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23462 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23463 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23464 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23469 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23470 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23471 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23473 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23475 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23476 newval
|= (value
& 0x1ff) >> 1;
23477 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23481 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23482 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23485 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23487 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23488 newval
|= (value
& 0xfff) >> 1;
23489 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23493 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23495 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23496 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23497 && ARM_IS_FUNC (fixP
->fx_addsy
)
23498 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23500 /* Force a relocation for a branch 20 bits wide. */
23503 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23504 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23505 _("conditional branch out of range"));
23507 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23510 addressT S
, J1
, J2
, lo
, hi
;
23512 S
= (value
& 0x00100000) >> 20;
23513 J2
= (value
& 0x00080000) >> 19;
23514 J1
= (value
& 0x00040000) >> 18;
23515 hi
= (value
& 0x0003f000) >> 12;
23516 lo
= (value
& 0x00000ffe) >> 1;
23518 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23519 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23520 newval
|= (S
<< 10) | hi
;
23521 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23522 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23523 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23527 case BFD_RELOC_THUMB_PCREL_BLX
:
23528 /* If there is a blx from a thumb state function to
23529 another thumb function flip this to a bl and warn
23533 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23534 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23535 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23537 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23538 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23539 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23541 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23542 newval
= newval
| 0x1000;
23543 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23544 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23549 goto thumb_bl_common
;
23551 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23552 /* A bl from Thumb state ISA to an internal ARM state function
23553 is converted to a blx. */
23555 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23556 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23557 && ARM_IS_FUNC (fixP
->fx_addsy
)
23558 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23560 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23561 newval
= newval
& ~0x1000;
23562 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23563 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23569 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23570 /* For a BLX instruction, make sure that the relocation is rounded up
23571 to a word boundary. This follows the semantics of the instruction
23572 which specifies that bit 1 of the target address will come from bit
23573 1 of the base address. */
23574 value
= (value
+ 3) & ~ 3;
23577 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23578 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23579 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23582 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23584 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23585 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23586 else if ((value
& ~0x1ffffff)
23587 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23588 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23589 _("Thumb2 branch out of range"));
23592 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23593 encode_thumb2_b_bl_offset (buf
, value
);
23597 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23598 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23601 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23602 encode_thumb2_b_bl_offset (buf
, value
);
23607 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23612 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23613 md_number_to_chars (buf
, value
, 2);
23617 case BFD_RELOC_ARM_TLS_CALL
:
23618 case BFD_RELOC_ARM_THM_TLS_CALL
:
23619 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23620 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23621 case BFD_RELOC_ARM_TLS_GOTDESC
:
23622 case BFD_RELOC_ARM_TLS_GD32
:
23623 case BFD_RELOC_ARM_TLS_LE32
:
23624 case BFD_RELOC_ARM_TLS_IE32
:
23625 case BFD_RELOC_ARM_TLS_LDM32
:
23626 case BFD_RELOC_ARM_TLS_LDO32
:
23627 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23630 case BFD_RELOC_ARM_GOT32
:
23631 case BFD_RELOC_ARM_GOTOFF
:
23634 case BFD_RELOC_ARM_GOT_PREL
:
23635 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23636 md_number_to_chars (buf
, value
, 4);
23639 case BFD_RELOC_ARM_TARGET2
:
23640 /* TARGET2 is not partial-inplace, so we need to write the
23641 addend here for REL targets, because it won't be written out
23642 during reloc processing later. */
23643 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23644 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23648 case BFD_RELOC_RVA
:
23650 case BFD_RELOC_ARM_TARGET1
:
23651 case BFD_RELOC_ARM_ROSEGREL32
:
23652 case BFD_RELOC_ARM_SBREL32
:
23653 case BFD_RELOC_32_PCREL
:
23655 case BFD_RELOC_32_SECREL
:
23657 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23659 /* For WinCE we only do this for pcrel fixups. */
23660 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23662 md_number_to_chars (buf
, value
, 4);
23666 case BFD_RELOC_ARM_PREL31
:
23667 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23669 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23670 if ((value
^ (value
>> 1)) & 0x40000000)
23672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23673 _("rel31 relocation overflow"));
23675 newval
|= value
& 0x7fffffff;
23676 md_number_to_chars (buf
, newval
, 4);
23681 case BFD_RELOC_ARM_CP_OFF_IMM
:
23682 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23683 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23684 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23686 newval
= get_thumb32_insn (buf
);
23687 if ((newval
& 0x0f200f00) == 0x0d000900)
23689 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23690 has permitted values that are multiples of 2, in the range 0
23692 if (value
< -510 || value
> 510 || (value
& 1))
23693 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23694 _("co-processor offset out of range"));
23696 else if (value
< -1023 || value
> 1023 || (value
& 3))
23697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23698 _("co-processor offset out of range"));
23703 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23704 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23705 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23707 newval
= get_thumb32_insn (buf
);
23709 newval
&= 0xffffff00;
23712 newval
&= 0xff7fff00;
23713 if ((newval
& 0x0f200f00) == 0x0d000900)
23715 /* This is a fp16 vstr/vldr.
23717 It requires the immediate offset in the instruction is shifted
23718 left by 1 to be a half-word offset.
23720 Here, left shift by 1 first, and later right shift by 2
23721 should get the right offset. */
23724 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23726 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23727 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23728 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23730 put_thumb32_insn (buf
, newval
);
23733 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23734 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23735 if (value
< -255 || value
> 255)
23736 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23737 _("co-processor offset out of range"));
23739 goto cp_off_common
;
23741 case BFD_RELOC_ARM_THUMB_OFFSET
:
23742 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23743 /* Exactly what ranges, and where the offset is inserted depends
23744 on the type of instruction, we can establish this from the
23746 switch (newval
>> 12)
23748 case 4: /* PC load. */
23749 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23750 forced to zero for these loads; md_pcrel_from has already
23751 compensated for this. */
23753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23754 _("invalid offset, target not word aligned (0x%08lX)"),
23755 (((unsigned long) fixP
->fx_frag
->fr_address
23756 + (unsigned long) fixP
->fx_where
) & ~3)
23757 + (unsigned long) value
);
23759 if (value
& ~0x3fc)
23760 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23761 _("invalid offset, value too big (0x%08lX)"),
23764 newval
|= value
>> 2;
23767 case 9: /* SP load/store. */
23768 if (value
& ~0x3fc)
23769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23770 _("invalid offset, value too big (0x%08lX)"),
23772 newval
|= value
>> 2;
23775 case 6: /* Word load/store. */
23777 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23778 _("invalid offset, value too big (0x%08lX)"),
23780 newval
|= value
<< 4; /* 6 - 2. */
23783 case 7: /* Byte load/store. */
23785 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23786 _("invalid offset, value too big (0x%08lX)"),
23788 newval
|= value
<< 6;
23791 case 8: /* Halfword load/store. */
23793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23794 _("invalid offset, value too big (0x%08lX)"),
23796 newval
|= value
<< 5; /* 6 - 1. */
23800 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23801 "Unable to process relocation for thumb opcode: %lx",
23802 (unsigned long) newval
);
23805 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23808 case BFD_RELOC_ARM_THUMB_ADD
:
23809 /* This is a complicated relocation, since we use it for all of
23810 the following immediate relocations:
23814 9bit ADD/SUB SP word-aligned
23815 10bit ADD PC/SP word-aligned
23817 The type of instruction being processed is encoded in the
23824 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23826 int rd
= (newval
>> 4) & 0xf;
23827 int rs
= newval
& 0xf;
23828 int subtract
= !!(newval
& 0x8000);
23830 /* Check for HI regs, only very restricted cases allowed:
23831 Adjusting SP, and using PC or SP to get an address. */
23832 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23833 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23835 _("invalid Hi register with immediate"));
23837 /* If value is negative, choose the opposite instruction. */
23841 subtract
= !subtract
;
23843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23844 _("immediate value out of range"));
23849 if (value
& ~0x1fc)
23850 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23851 _("invalid immediate for stack address calculation"));
23852 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23853 newval
|= value
>> 2;
23855 else if (rs
== REG_PC
|| rs
== REG_SP
)
23857 /* PR gas/18541. If the addition is for a defined symbol
23858 within range of an ADR instruction then accept it. */
23861 && fixP
->fx_addsy
!= NULL
)
23865 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23866 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23867 || S_IS_WEAK (fixP
->fx_addsy
))
23869 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23870 _("address calculation needs a strongly defined nearby symbol"));
23874 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23876 /* Round up to the next 4-byte boundary. */
23881 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23886 _("symbol too far away"));
23896 if (subtract
|| value
& ~0x3fc)
23897 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23898 _("invalid immediate for address calculation (value = 0x%08lX)"),
23899 (unsigned long) (subtract
? - value
: value
));
23900 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23902 newval
|= value
>> 2;
23907 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23908 _("immediate value out of range"));
23909 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23910 newval
|= (rd
<< 8) | value
;
23915 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23916 _("immediate value out of range"));
23917 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23918 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23921 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23924 case BFD_RELOC_ARM_THUMB_IMM
:
23925 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23926 if (value
< 0 || value
> 255)
23927 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23928 _("invalid immediate: %ld is out of range"),
23931 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23934 case BFD_RELOC_ARM_THUMB_SHIFT
:
23935 /* 5bit shift value (0..32). LSL cannot take 32. */
23936 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23937 temp
= newval
& 0xf800;
23938 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23939 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23940 _("invalid shift value: %ld"), (long) value
);
23941 /* Shifts of zero must be encoded as LSL. */
23943 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23944 /* Shifts of 32 are encoded as zero. */
23945 else if (value
== 32)
23947 newval
|= value
<< 6;
23948 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23951 case BFD_RELOC_VTABLE_INHERIT
:
23952 case BFD_RELOC_VTABLE_ENTRY
:
23956 case BFD_RELOC_ARM_MOVW
:
23957 case BFD_RELOC_ARM_MOVT
:
23958 case BFD_RELOC_ARM_THUMB_MOVW
:
23959 case BFD_RELOC_ARM_THUMB_MOVT
:
23960 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23962 /* REL format relocations are limited to a 16-bit addend. */
23963 if (!fixP
->fx_done
)
23965 if (value
< -0x8000 || value
> 0x7fff)
23966 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23967 _("offset out of range"));
23969 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23970 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23975 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23976 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23978 newval
= get_thumb32_insn (buf
);
23979 newval
&= 0xfbf08f00;
23980 newval
|= (value
& 0xf000) << 4;
23981 newval
|= (value
& 0x0800) << 15;
23982 newval
|= (value
& 0x0700) << 4;
23983 newval
|= (value
& 0x00ff);
23984 put_thumb32_insn (buf
, newval
);
23988 newval
= md_chars_to_number (buf
, 4);
23989 newval
&= 0xfff0f000;
23990 newval
|= value
& 0x0fff;
23991 newval
|= (value
& 0xf000) << 4;
23992 md_number_to_chars (buf
, newval
, 4);
23997 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23998 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23999 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24000 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24001 gas_assert (!fixP
->fx_done
);
24004 bfd_boolean is_mov
;
24005 bfd_vma encoded_addend
= value
;
24007 /* Check that addend can be encoded in instruction. */
24008 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24009 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24010 _("the offset 0x%08lX is not representable"),
24011 (unsigned long) encoded_addend
);
24013 /* Extract the instruction. */
24014 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24015 is_mov
= (insn
& 0xf800) == 0x2000;
24020 if (!seg
->use_rela_p
)
24021 insn
|= encoded_addend
;
24027 /* Extract the instruction. */
24028 /* Encoding is the following
24033 /* The following conditions must be true :
24038 rd
= (insn
>> 4) & 0xf;
24040 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24041 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24042 _("Unable to process relocation for thumb opcode: %lx"),
24043 (unsigned long) insn
);
24045 /* Encode as ADD immediate8 thumb 1 code. */
24046 insn
= 0x3000 | (rd
<< 8);
24048 /* Place the encoded addend into the first 8 bits of the
24050 if (!seg
->use_rela_p
)
24051 insn
|= encoded_addend
;
24054 /* Update the instruction. */
24055 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24059 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24060 case BFD_RELOC_ARM_ALU_PC_G0
:
24061 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24062 case BFD_RELOC_ARM_ALU_PC_G1
:
24063 case BFD_RELOC_ARM_ALU_PC_G2
:
24064 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24065 case BFD_RELOC_ARM_ALU_SB_G0
:
24066 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24067 case BFD_RELOC_ARM_ALU_SB_G1
:
24068 case BFD_RELOC_ARM_ALU_SB_G2
:
24069 gas_assert (!fixP
->fx_done
);
24070 if (!seg
->use_rela_p
)
24073 bfd_vma encoded_addend
;
24074 bfd_vma addend_abs
= abs (value
);
24076 /* Check that the absolute value of the addend can be
24077 expressed as an 8-bit constant plus a rotation. */
24078 encoded_addend
= encode_arm_immediate (addend_abs
);
24079 if (encoded_addend
== (unsigned int) FAIL
)
24080 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24081 _("the offset 0x%08lX is not representable"),
24082 (unsigned long) addend_abs
);
24084 /* Extract the instruction. */
24085 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24087 /* If the addend is positive, use an ADD instruction.
24088 Otherwise use a SUB. Take care not to destroy the S bit. */
24089 insn
&= 0xff1fffff;
24095 /* Place the encoded addend into the first 12 bits of the
24097 insn
&= 0xfffff000;
24098 insn
|= encoded_addend
;
24100 /* Update the instruction. */
24101 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24105 case BFD_RELOC_ARM_LDR_PC_G0
:
24106 case BFD_RELOC_ARM_LDR_PC_G1
:
24107 case BFD_RELOC_ARM_LDR_PC_G2
:
24108 case BFD_RELOC_ARM_LDR_SB_G0
:
24109 case BFD_RELOC_ARM_LDR_SB_G1
:
24110 case BFD_RELOC_ARM_LDR_SB_G2
:
24111 gas_assert (!fixP
->fx_done
);
24112 if (!seg
->use_rela_p
)
24115 bfd_vma addend_abs
= abs (value
);
24117 /* Check that the absolute value of the addend can be
24118 encoded in 12 bits. */
24119 if (addend_abs
>= 0x1000)
24120 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24121 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24122 (unsigned long) addend_abs
);
24124 /* Extract the instruction. */
24125 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24127 /* If the addend is negative, clear bit 23 of the instruction.
24128 Otherwise set it. */
24130 insn
&= ~(1 << 23);
24134 /* Place the absolute value of the addend into the first 12 bits
24135 of the instruction. */
24136 insn
&= 0xfffff000;
24137 insn
|= addend_abs
;
24139 /* Update the instruction. */
24140 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24144 case BFD_RELOC_ARM_LDRS_PC_G0
:
24145 case BFD_RELOC_ARM_LDRS_PC_G1
:
24146 case BFD_RELOC_ARM_LDRS_PC_G2
:
24147 case BFD_RELOC_ARM_LDRS_SB_G0
:
24148 case BFD_RELOC_ARM_LDRS_SB_G1
:
24149 case BFD_RELOC_ARM_LDRS_SB_G2
:
24150 gas_assert (!fixP
->fx_done
);
24151 if (!seg
->use_rela_p
)
24154 bfd_vma addend_abs
= abs (value
);
24156 /* Check that the absolute value of the addend can be
24157 encoded in 8 bits. */
24158 if (addend_abs
>= 0x100)
24159 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24160 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24161 (unsigned long) addend_abs
);
24163 /* Extract the instruction. */
24164 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24166 /* If the addend is negative, clear bit 23 of the instruction.
24167 Otherwise set it. */
24169 insn
&= ~(1 << 23);
24173 /* Place the first four bits of the absolute value of the addend
24174 into the first 4 bits of the instruction, and the remaining
24175 four into bits 8 .. 11. */
24176 insn
&= 0xfffff0f0;
24177 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24179 /* Update the instruction. */
24180 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24184 case BFD_RELOC_ARM_LDC_PC_G0
:
24185 case BFD_RELOC_ARM_LDC_PC_G1
:
24186 case BFD_RELOC_ARM_LDC_PC_G2
:
24187 case BFD_RELOC_ARM_LDC_SB_G0
:
24188 case BFD_RELOC_ARM_LDC_SB_G1
:
24189 case BFD_RELOC_ARM_LDC_SB_G2
:
24190 gas_assert (!fixP
->fx_done
);
24191 if (!seg
->use_rela_p
)
24194 bfd_vma addend_abs
= abs (value
);
24196 /* Check that the absolute value of the addend is a multiple of
24197 four and, when divided by four, fits in 8 bits. */
24198 if (addend_abs
& 0x3)
24199 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24200 _("bad offset 0x%08lX (must be word-aligned)"),
24201 (unsigned long) addend_abs
);
24203 if ((addend_abs
>> 2) > 0xff)
24204 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24205 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24206 (unsigned long) addend_abs
);
24208 /* Extract the instruction. */
24209 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24211 /* If the addend is negative, clear bit 23 of the instruction.
24212 Otherwise set it. */
24214 insn
&= ~(1 << 23);
24218 /* Place the addend (divided by four) into the first eight
24219 bits of the instruction. */
24220 insn
&= 0xfffffff0;
24221 insn
|= addend_abs
>> 2;
24223 /* Update the instruction. */
24224 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24228 case BFD_RELOC_ARM_V4BX
:
24229 /* This will need to go in the object file. */
24233 case BFD_RELOC_UNUSED
:
24235 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24236 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24240 /* Translate internal representation of relocation info to BFD target
24244 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24247 bfd_reloc_code_real_type code
;
24249 reloc
= XNEW (arelent
);
24251 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24252 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24253 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24255 if (fixp
->fx_pcrel
)
24257 if (section
->use_rela_p
)
24258 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24260 fixp
->fx_offset
= reloc
->address
;
24262 reloc
->addend
= fixp
->fx_offset
;
24264 switch (fixp
->fx_r_type
)
24267 if (fixp
->fx_pcrel
)
24269 code
= BFD_RELOC_8_PCREL
;
24272 /* Fall through. */
24275 if (fixp
->fx_pcrel
)
24277 code
= BFD_RELOC_16_PCREL
;
24280 /* Fall through. */
24283 if (fixp
->fx_pcrel
)
24285 code
= BFD_RELOC_32_PCREL
;
24288 /* Fall through. */
24290 case BFD_RELOC_ARM_MOVW
:
24291 if (fixp
->fx_pcrel
)
24293 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24296 /* Fall through. */
24298 case BFD_RELOC_ARM_MOVT
:
24299 if (fixp
->fx_pcrel
)
24301 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24304 /* Fall through. */
24306 case BFD_RELOC_ARM_THUMB_MOVW
:
24307 if (fixp
->fx_pcrel
)
24309 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24312 /* Fall through. */
24314 case BFD_RELOC_ARM_THUMB_MOVT
:
24315 if (fixp
->fx_pcrel
)
24317 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24320 /* Fall through. */
24322 case BFD_RELOC_NONE
:
24323 case BFD_RELOC_ARM_PCREL_BRANCH
:
24324 case BFD_RELOC_ARM_PCREL_BLX
:
24325 case BFD_RELOC_RVA
:
24326 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24327 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24328 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24329 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24330 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24331 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24332 case BFD_RELOC_VTABLE_ENTRY
:
24333 case BFD_RELOC_VTABLE_INHERIT
:
24335 case BFD_RELOC_32_SECREL
:
24337 code
= fixp
->fx_r_type
;
24340 case BFD_RELOC_THUMB_PCREL_BLX
:
24342 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24343 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24346 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24349 case BFD_RELOC_ARM_LITERAL
:
24350 case BFD_RELOC_ARM_HWLITERAL
:
24351 /* If this is called then the a literal has
24352 been referenced across a section boundary. */
24353 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24354 _("literal referenced across section boundary"));
24358 case BFD_RELOC_ARM_TLS_CALL
:
24359 case BFD_RELOC_ARM_THM_TLS_CALL
:
24360 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24361 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24362 case BFD_RELOC_ARM_GOT32
:
24363 case BFD_RELOC_ARM_GOTOFF
:
24364 case BFD_RELOC_ARM_GOT_PREL
:
24365 case BFD_RELOC_ARM_PLT32
:
24366 case BFD_RELOC_ARM_TARGET1
:
24367 case BFD_RELOC_ARM_ROSEGREL32
:
24368 case BFD_RELOC_ARM_SBREL32
:
24369 case BFD_RELOC_ARM_PREL31
:
24370 case BFD_RELOC_ARM_TARGET2
:
24371 case BFD_RELOC_ARM_TLS_LDO32
:
24372 case BFD_RELOC_ARM_PCREL_CALL
:
24373 case BFD_RELOC_ARM_PCREL_JUMP
:
24374 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24375 case BFD_RELOC_ARM_ALU_PC_G0
:
24376 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24377 case BFD_RELOC_ARM_ALU_PC_G1
:
24378 case BFD_RELOC_ARM_ALU_PC_G2
:
24379 case BFD_RELOC_ARM_LDR_PC_G0
:
24380 case BFD_RELOC_ARM_LDR_PC_G1
:
24381 case BFD_RELOC_ARM_LDR_PC_G2
:
24382 case BFD_RELOC_ARM_LDRS_PC_G0
:
24383 case BFD_RELOC_ARM_LDRS_PC_G1
:
24384 case BFD_RELOC_ARM_LDRS_PC_G2
:
24385 case BFD_RELOC_ARM_LDC_PC_G0
:
24386 case BFD_RELOC_ARM_LDC_PC_G1
:
24387 case BFD_RELOC_ARM_LDC_PC_G2
:
24388 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24389 case BFD_RELOC_ARM_ALU_SB_G0
:
24390 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24391 case BFD_RELOC_ARM_ALU_SB_G1
:
24392 case BFD_RELOC_ARM_ALU_SB_G2
:
24393 case BFD_RELOC_ARM_LDR_SB_G0
:
24394 case BFD_RELOC_ARM_LDR_SB_G1
:
24395 case BFD_RELOC_ARM_LDR_SB_G2
:
24396 case BFD_RELOC_ARM_LDRS_SB_G0
:
24397 case BFD_RELOC_ARM_LDRS_SB_G1
:
24398 case BFD_RELOC_ARM_LDRS_SB_G2
:
24399 case BFD_RELOC_ARM_LDC_SB_G0
:
24400 case BFD_RELOC_ARM_LDC_SB_G1
:
24401 case BFD_RELOC_ARM_LDC_SB_G2
:
24402 case BFD_RELOC_ARM_V4BX
:
24403 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24404 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24405 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24406 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24407 code
= fixp
->fx_r_type
;
24410 case BFD_RELOC_ARM_TLS_GOTDESC
:
24411 case BFD_RELOC_ARM_TLS_GD32
:
24412 case BFD_RELOC_ARM_TLS_LE32
:
24413 case BFD_RELOC_ARM_TLS_IE32
:
24414 case BFD_RELOC_ARM_TLS_LDM32
:
24415 /* BFD will include the symbol's address in the addend.
24416 But we don't want that, so subtract it out again here. */
24417 if (!S_IS_COMMON (fixp
->fx_addsy
))
24418 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24419 code
= fixp
->fx_r_type
;
24423 case BFD_RELOC_ARM_IMMEDIATE
:
24424 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24425 _("internal relocation (type: IMMEDIATE) not fixed up"));
24428 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24429 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24430 _("ADRL used for a symbol not defined in the same file"));
24433 case BFD_RELOC_ARM_OFFSET_IMM
:
24434 if (section
->use_rela_p
)
24436 code
= fixp
->fx_r_type
;
24440 if (fixp
->fx_addsy
!= NULL
24441 && !S_IS_DEFINED (fixp
->fx_addsy
)
24442 && S_IS_LOCAL (fixp
->fx_addsy
))
24444 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24445 _("undefined local label `%s'"),
24446 S_GET_NAME (fixp
->fx_addsy
));
24450 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24451 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24458 switch (fixp
->fx_r_type
)
24460 case BFD_RELOC_NONE
: type
= "NONE"; break;
24461 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24462 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24463 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24464 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24465 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24466 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24467 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24468 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24469 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24470 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24471 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24472 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24473 default: type
= _("<unknown>"); break;
24475 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24476 _("cannot represent %s relocation in this object file format"),
24483 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24485 && fixp
->fx_addsy
== GOT_symbol
)
24487 code
= BFD_RELOC_ARM_GOTPC
;
24488 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24492 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24494 if (reloc
->howto
== NULL
)
24496 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24497 _("cannot represent %s relocation in this object file format"),
24498 bfd_get_reloc_code_name (code
));
24502 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24503 vtable entry to be used in the relocation's section offset. */
24504 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24505 reloc
->address
= fixp
->fx_offset
;
24510 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24513 cons_fix_new_arm (fragS
* frag
,
24517 bfd_reloc_code_real_type reloc
)
24522 FIXME: @@ Should look at CPU word size. */
24526 reloc
= BFD_RELOC_8
;
24529 reloc
= BFD_RELOC_16
;
24533 reloc
= BFD_RELOC_32
;
24536 reloc
= BFD_RELOC_64
;
24541 if (exp
->X_op
== O_secrel
)
24543 exp
->X_op
= O_symbol
;
24544 reloc
= BFD_RELOC_32_SECREL
;
24548 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24551 #if defined (OBJ_COFF)
24553 arm_validate_fix (fixS
* fixP
)
24555 /* If the destination of the branch is a defined symbol which does not have
24556 the THUMB_FUNC attribute, then we must be calling a function which has
24557 the (interfacearm) attribute. We look for the Thumb entry point to that
24558 function and change the branch to refer to that function instead. */
24559 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24560 && fixP
->fx_addsy
!= NULL
24561 && S_IS_DEFINED (fixP
->fx_addsy
)
24562 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24564 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24571 arm_force_relocation (struct fix
* fixp
)
24573 #if defined (OBJ_COFF) && defined (TE_PE)
24574 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24578 /* In case we have a call or a branch to a function in ARM ISA mode from
24579 a thumb function or vice-versa force the relocation. These relocations
24580 are cleared off for some cores that might have blx and simple transformations
24584 switch (fixp
->fx_r_type
)
24586 case BFD_RELOC_ARM_PCREL_JUMP
:
24587 case BFD_RELOC_ARM_PCREL_CALL
:
24588 case BFD_RELOC_THUMB_PCREL_BLX
:
24589 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24593 case BFD_RELOC_ARM_PCREL_BLX
:
24594 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24595 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24596 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24597 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24606 /* Resolve these relocations even if the symbol is extern or weak.
24607 Technically this is probably wrong due to symbol preemption.
24608 In practice these relocations do not have enough range to be useful
24609 at dynamic link time, and some code (e.g. in the Linux kernel)
24610 expects these references to be resolved. */
24611 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24612 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24613 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24614 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24615 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24616 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24617 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24618 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24619 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24620 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24621 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24622 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24623 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24624 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24627 /* Always leave these relocations for the linker. */
24628 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24629 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24630 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24633 /* Always generate relocations against function symbols. */
24634 if (fixp
->fx_r_type
== BFD_RELOC_32
24636 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24639 return generic_force_reloc (fixp
);
24642 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24643 /* Relocations against function names must be left unadjusted,
24644 so that the linker can use this information to generate interworking
24645 stubs. The MIPS version of this function
24646 also prevents relocations that are mips-16 specific, but I do not
24647 know why it does this.
24650 There is one other problem that ought to be addressed here, but
24651 which currently is not: Taking the address of a label (rather
24652 than a function) and then later jumping to that address. Such
24653 addresses also ought to have their bottom bit set (assuming that
24654 they reside in Thumb code), but at the moment they will not. */
24657 arm_fix_adjustable (fixS
* fixP
)
24659 if (fixP
->fx_addsy
== NULL
)
24662 /* Preserve relocations against symbols with function type. */
24663 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24666 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24667 && fixP
->fx_subsy
== NULL
)
24670 /* We need the symbol name for the VTABLE entries. */
24671 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24672 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24675 /* Don't allow symbols to be discarded on GOT related relocs. */
24676 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24677 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24678 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24679 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24680 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24681 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24682 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24683 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24684 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24685 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24686 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24687 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24688 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24689 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24692 /* Similarly for group relocations. */
24693 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24694 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24695 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24698 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24699 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24700 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24701 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24702 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24703 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24704 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24705 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24706 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24709 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24710 offsets, so keep these symbols. */
24711 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24712 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24717 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24721 elf32_arm_target_format (void)
24724 return (target_big_endian
24725 ? "elf32-bigarm-symbian"
24726 : "elf32-littlearm-symbian");
24727 #elif defined (TE_VXWORKS)
24728 return (target_big_endian
24729 ? "elf32-bigarm-vxworks"
24730 : "elf32-littlearm-vxworks");
24731 #elif defined (TE_NACL)
24732 return (target_big_endian
24733 ? "elf32-bigarm-nacl"
24734 : "elf32-littlearm-nacl");
24736 if (target_big_endian
)
24737 return "elf32-bigarm";
24739 return "elf32-littlearm";
24744 armelf_frob_symbol (symbolS
* symp
,
24747 elf_frob_symbol (symp
, puntp
);
24751 /* MD interface: Finalization. */
24756 literal_pool
* pool
;
24758 /* Ensure that all the IT blocks are properly closed. */
24759 check_it_blocks_finished ();
24761 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24763 /* Put it at the end of the relevant section. */
24764 subseg_set (pool
->section
, pool
->sub_section
);
24766 arm_elf_change_section ();
24773 /* Remove any excess mapping symbols generated for alignment frags in
24774 SEC. We may have created a mapping symbol before a zero byte
24775 alignment; remove it if there's a mapping symbol after the
24778 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24779 void *dummy ATTRIBUTE_UNUSED
)
24781 segment_info_type
*seginfo
= seg_info (sec
);
24784 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24787 for (fragp
= seginfo
->frchainP
->frch_root
;
24789 fragp
= fragp
->fr_next
)
24791 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24792 fragS
*next
= fragp
->fr_next
;
24794 /* Variable-sized frags have been converted to fixed size by
24795 this point. But if this was variable-sized to start with,
24796 there will be a fixed-size frag after it. So don't handle
24798 if (sym
== NULL
|| next
== NULL
)
24801 if (S_GET_VALUE (sym
) < next
->fr_address
)
24802 /* Not at the end of this frag. */
24804 know (S_GET_VALUE (sym
) == next
->fr_address
);
24808 if (next
->tc_frag_data
.first_map
!= NULL
)
24810 /* Next frag starts with a mapping symbol. Discard this
24812 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24816 if (next
->fr_next
== NULL
)
24818 /* This mapping symbol is at the end of the section. Discard
24820 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24821 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24825 /* As long as we have empty frags without any mapping symbols,
24827 /* If the next frag is non-empty and does not start with a
24828 mapping symbol, then this mapping symbol is required. */
24829 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24832 next
= next
->fr_next
;
24834 while (next
!= NULL
);
24839 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24843 arm_adjust_symtab (void)
24848 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24850 if (ARM_IS_THUMB (sym
))
24852 if (THUMB_IS_FUNC (sym
))
24854 /* Mark the symbol as a Thumb function. */
24855 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24856 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24857 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24859 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24860 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24862 as_bad (_("%s: unexpected function type: %d"),
24863 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24865 else switch (S_GET_STORAGE_CLASS (sym
))
24868 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24871 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24874 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24882 if (ARM_IS_INTERWORK (sym
))
24883 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24890 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24892 if (ARM_IS_THUMB (sym
))
24894 elf_symbol_type
* elf_sym
;
24896 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24897 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24899 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24900 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24902 /* If it's a .thumb_func, declare it as so,
24903 otherwise tag label as .code 16. */
24904 if (THUMB_IS_FUNC (sym
))
24905 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
24906 ST_BRANCH_TO_THUMB
);
24907 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24908 elf_sym
->internal_elf_sym
.st_info
=
24909 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24914 /* Remove any overlapping mapping symbols generated by alignment frags. */
24915 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24916 /* Now do generic ELF adjustments. */
24917 elf_adjust_symtab ();
24921 /* MD interface: Initialization. */
24924 set_constant_flonums (void)
24928 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24929 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24933 /* Auto-select Thumb mode if it's the only available instruction set for the
24934 given architecture. */
24937 autoselect_thumb_from_cpu_variant (void)
24939 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24940 opcode_select (16);
24949 if ( (arm_ops_hsh
= hash_new ()) == NULL
24950 || (arm_cond_hsh
= hash_new ()) == NULL
24951 || (arm_shift_hsh
= hash_new ()) == NULL
24952 || (arm_psr_hsh
= hash_new ()) == NULL
24953 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24954 || (arm_reg_hsh
= hash_new ()) == NULL
24955 || (arm_reloc_hsh
= hash_new ()) == NULL
24956 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24957 as_fatal (_("virtual memory exhausted"));
24959 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24960 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24961 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24962 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24963 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24964 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24965 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24966 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24967 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24968 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24969 (void *) (v7m_psrs
+ i
));
24970 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24971 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24973 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24975 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24976 (void *) (barrier_opt_names
+ i
));
24978 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24980 struct reloc_entry
* entry
= reloc_names
+ i
;
24982 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24983 /* This makes encode_branch() use the EABI versions of this relocation. */
24984 entry
->reloc
= BFD_RELOC_UNUSED
;
24986 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24990 set_constant_flonums ();
24992 /* Set the cpu variant based on the command-line options. We prefer
24993 -mcpu= over -march= if both are set (as for GCC); and we prefer
24994 -mfpu= over any other way of setting the floating point unit.
24995 Use of legacy options with new options are faulted. */
24998 if (mcpu_cpu_opt
|| march_cpu_opt
)
24999 as_bad (_("use of old and new-style options to set CPU type"));
25001 mcpu_cpu_opt
= legacy_cpu
;
25003 else if (!mcpu_cpu_opt
)
25004 mcpu_cpu_opt
= march_cpu_opt
;
25009 as_bad (_("use of old and new-style options to set FPU type"));
25011 mfpu_opt
= legacy_fpu
;
25013 else if (!mfpu_opt
)
25015 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25016 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25017 /* Some environments specify a default FPU. If they don't, infer it
25018 from the processor. */
25020 mfpu_opt
= mcpu_fpu_opt
;
25022 mfpu_opt
= march_fpu_opt
;
25024 mfpu_opt
= &fpu_default
;
25030 if (mcpu_cpu_opt
!= NULL
)
25031 mfpu_opt
= &fpu_default
;
25032 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
25033 mfpu_opt
= &fpu_arch_vfp_v2
;
25035 mfpu_opt
= &fpu_arch_fpa
;
25041 mcpu_cpu_opt
= &cpu_default
;
25042 selected_cpu
= cpu_default
;
25045 selected_cpu
= *mcpu_cpu_opt
;
25048 selected_cpu
= *mcpu_cpu_opt
;
25050 mcpu_cpu_opt
= &arm_arch_any
;
25053 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25055 autoselect_thumb_from_cpu_variant ();
25057 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25059 #if defined OBJ_COFF || defined OBJ_ELF
25061 unsigned int flags
= 0;
25063 #if defined OBJ_ELF
25064 flags
= meabi_flags
;
25066 switch (meabi_flags
)
25068 case EF_ARM_EABI_UNKNOWN
:
25070 /* Set the flags in the private structure. */
25071 if (uses_apcs_26
) flags
|= F_APCS26
;
25072 if (support_interwork
) flags
|= F_INTERWORK
;
25073 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25074 if (pic_code
) flags
|= F_PIC
;
25075 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25076 flags
|= F_SOFT_FLOAT
;
25078 switch (mfloat_abi_opt
)
25080 case ARM_FLOAT_ABI_SOFT
:
25081 case ARM_FLOAT_ABI_SOFTFP
:
25082 flags
|= F_SOFT_FLOAT
;
25085 case ARM_FLOAT_ABI_HARD
:
25086 if (flags
& F_SOFT_FLOAT
)
25087 as_bad (_("hard-float conflicts with specified fpu"));
25091 /* Using pure-endian doubles (even if soft-float). */
25092 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25093 flags
|= F_VFP_FLOAT
;
25095 #if defined OBJ_ELF
25096 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25097 flags
|= EF_ARM_MAVERICK_FLOAT
;
25100 case EF_ARM_EABI_VER4
:
25101 case EF_ARM_EABI_VER5
:
25102 /* No additional flags to set. */
25109 bfd_set_private_flags (stdoutput
, flags
);
25111 /* We have run out flags in the COFF header to encode the
25112 status of ATPCS support, so instead we create a dummy,
25113 empty, debug section called .arm.atpcs. */
25118 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25122 bfd_set_section_flags
25123 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25124 bfd_set_section_size (stdoutput
, sec
, 0);
25125 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25131 /* Record the CPU type as well. */
25132 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25133 mach
= bfd_mach_arm_iWMMXt2
;
25134 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25135 mach
= bfd_mach_arm_iWMMXt
;
25136 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25137 mach
= bfd_mach_arm_XScale
;
25138 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25139 mach
= bfd_mach_arm_ep9312
;
25140 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25141 mach
= bfd_mach_arm_5TE
;
25142 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25144 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25145 mach
= bfd_mach_arm_5T
;
25147 mach
= bfd_mach_arm_5
;
25149 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25151 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25152 mach
= bfd_mach_arm_4T
;
25154 mach
= bfd_mach_arm_4
;
25156 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25157 mach
= bfd_mach_arm_3M
;
25158 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25159 mach
= bfd_mach_arm_3
;
25160 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25161 mach
= bfd_mach_arm_2a
;
25162 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25163 mach
= bfd_mach_arm_2
;
25165 mach
= bfd_mach_arm_unknown
;
25167 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25170 /* Command line processing. */
25173 Invocation line includes a switch not recognized by the base assembler.
25174 See if it's a processor-specific option.
25176 This routine is somewhat complicated by the need for backwards
25177 compatibility (since older releases of gcc can't be changed).
25178 The new options try to make the interface as compatible as
25181 New options (supported) are:
25183 -mcpu=<cpu name> Assemble for selected processor
25184 -march=<architecture name> Assemble for selected architecture
25185 -mfpu=<fpu architecture> Assemble for selected FPU.
25186 -EB/-mbig-endian Big-endian
25187 -EL/-mlittle-endian Little-endian
25188 -k Generate PIC code
25189 -mthumb Start in Thumb mode
25190 -mthumb-interwork Code supports ARM/Thumb interworking
25192 -m[no-]warn-deprecated Warn about deprecated features
25193 -m[no-]warn-syms Warn when symbols match instructions
25195 For now we will also provide support for:
25197 -mapcs-32 32-bit Program counter
25198 -mapcs-26 26-bit Program counter
25199 -macps-float Floats passed in FP registers
25200 -mapcs-reentrant Reentrant code
25202 (sometime these will probably be replaced with -mapcs=<list of options>
25203 and -matpcs=<list of options>)
25205 The remaining options are only supported for back-wards compatibility.
25206 Cpu variants, the arm part is optional:
25207 -m[arm]1 Currently not supported.
25208 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25209 -m[arm]3 Arm 3 processor
25210 -m[arm]6[xx], Arm 6 processors
25211 -m[arm]7[xx][t][[d]m] Arm 7 processors
25212 -m[arm]8[10] Arm 8 processors
25213 -m[arm]9[20][tdmi] Arm 9 processors
25214 -mstrongarm[110[0]] StrongARM processors
25215 -mxscale XScale processors
25216 -m[arm]v[2345[t[e]]] Arm architectures
25217 -mall All (except the ARM1)
25219 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25220 -mfpe-old (No float load/store multiples)
25221 -mvfpxd VFP Single precision
25223 -mno-fpu Disable all floating point instructions
25225 The following CPU names are recognized:
25226 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25227 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25228 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25229 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25230 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25231 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25232 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25236 const char * md_shortopts
= "m:k";
25238 #ifdef ARM_BI_ENDIAN
25239 #define OPTION_EB (OPTION_MD_BASE + 0)
25240 #define OPTION_EL (OPTION_MD_BASE + 1)
25242 #if TARGET_BYTES_BIG_ENDIAN
25243 #define OPTION_EB (OPTION_MD_BASE + 0)
25245 #define OPTION_EL (OPTION_MD_BASE + 1)
25248 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25250 struct option md_longopts
[] =
25253 {"EB", no_argument
, NULL
, OPTION_EB
},
25256 {"EL", no_argument
, NULL
, OPTION_EL
},
25258 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25259 {NULL
, no_argument
, NULL
, 0}
25263 size_t md_longopts_size
= sizeof (md_longopts
);
25265 struct arm_option_table
25267 const char *option
; /* Option name to match. */
25268 const char *help
; /* Help information. */
25269 int *var
; /* Variable to change. */
25270 int value
; /* What to change it to. */
25271 const char *deprecated
; /* If non-null, print this message. */
25274 struct arm_option_table arm_opts
[] =
25276 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25277 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25278 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25279 &support_interwork
, 1, NULL
},
25280 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25281 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25282 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25284 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25285 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25286 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25287 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25290 /* These are recognized by the assembler, but have no affect on code. */
25291 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25292 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25294 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25295 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25296 &warn_on_deprecated
, 0, NULL
},
25297 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25298 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25299 {NULL
, NULL
, NULL
, 0, NULL
}
25302 struct arm_legacy_option_table
25304 const char *option
; /* Option name to match. */
25305 const arm_feature_set
**var
; /* Variable to change. */
25306 const arm_feature_set value
; /* What to change it to. */
25307 const char *deprecated
; /* If non-null, print this message. */
25310 const struct arm_legacy_option_table arm_legacy_opts
[] =
25312 /* DON'T add any new processors to this list -- we want the whole list
25313 to go away... Add them to the processors table instead. */
25314 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25315 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25316 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25317 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25318 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25319 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25320 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25321 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25322 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25323 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25324 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25325 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25326 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25327 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25328 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25329 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25330 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25331 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25332 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25333 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25334 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25335 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25336 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25337 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25338 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25339 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25340 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25341 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25342 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25343 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25344 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25345 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25346 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25347 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25348 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25349 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25350 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25351 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25352 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25353 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25354 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25355 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25356 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25357 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25358 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25359 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25360 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25361 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25362 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25363 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25364 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25365 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25366 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25367 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25368 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25369 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25370 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25371 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25372 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25373 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25374 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25375 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25376 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25377 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25378 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25379 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25380 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25381 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25382 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25383 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25384 N_("use -mcpu=strongarm110")},
25385 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25386 N_("use -mcpu=strongarm1100")},
25387 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25388 N_("use -mcpu=strongarm1110")},
25389 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25390 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25391 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25393 /* Architecture variants -- don't add any more to this list either. */
25394 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25395 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25396 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25397 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25398 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25399 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25400 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25401 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25402 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25403 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25404 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25405 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25406 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25407 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25408 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25409 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25410 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25411 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25413 /* Floating point variants -- don't add any more to this list either. */
25414 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25415 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25416 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25417 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25418 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25420 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25423 struct arm_cpu_option_table
25427 const arm_feature_set value
;
25428 /* For some CPUs we assume an FPU unless the user explicitly sets
25430 const arm_feature_set default_fpu
;
25431 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25433 const char *canonical_name
;
25436 /* This list should, at a minimum, contain all the cpu names
25437 recognized by GCC. */
25438 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25439 static const struct arm_cpu_option_table arm_cpus
[] =
25441 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25442 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25443 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25444 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25445 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25446 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25447 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25448 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25449 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25450 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25451 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25452 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25453 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25454 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25455 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25456 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25457 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25458 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25459 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25460 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25461 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25462 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25463 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25464 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25465 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25466 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25467 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25468 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25469 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25470 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25471 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25472 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25473 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25474 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25475 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25476 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25477 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25478 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25479 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25480 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25481 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25482 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25483 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25484 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25485 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25486 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25487 /* For V5 or later processors we default to using VFP; but the user
25488 should really set the FPU type explicitly. */
25489 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25490 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25491 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25492 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25493 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25494 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25495 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25496 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25497 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25498 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25499 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25500 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25501 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25502 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25503 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25504 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25505 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25506 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25507 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25508 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25510 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25511 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25512 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25513 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25514 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25515 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25516 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25517 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25518 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25520 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25521 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25522 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25523 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25524 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25525 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25526 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25527 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25528 FPU_NONE
, "Cortex-A5"),
25529 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25531 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25532 ARM_FEATURE_COPROC (FPU_VFP_V3
25533 | FPU_NEON_EXT_V1
),
25535 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25536 ARM_FEATURE_COPROC (FPU_VFP_V3
25537 | FPU_NEON_EXT_V1
),
25539 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25541 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25543 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25545 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25547 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25549 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25551 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25553 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25555 ARM_CPU_OPT ("cortex-a73", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25557 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25558 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25560 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25561 FPU_NONE
, "Cortex-R5"),
25562 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25563 FPU_ARCH_VFP_V3D16
,
25565 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV
,
25566 FPU_ARCH_VFP_V3D16
,
25568 ARM_CPU_OPT ("cortex-m33", ARM_ARCH_V8M_MAIN_DSP
,
25569 FPU_NONE
, "Cortex-M33"),
25570 ARM_CPU_OPT ("cortex-m23", ARM_ARCH_V8M_BASE
,
25571 FPU_NONE
, "Cortex-M23"),
25572 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25573 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25574 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25575 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25576 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25577 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25578 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25581 ARM_CPU_OPT ("falkor", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25584 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25588 /* ??? XSCALE is really an architecture. */
25589 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25590 /* ??? iwmmxt is not a processor. */
25591 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25592 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25593 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25595 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25596 FPU_ARCH_MAVERICK
, "ARM920T"),
25597 /* Marvell processors. */
25598 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25600 ARM_EXT2_V6T2_V8M
),
25601 FPU_ARCH_VFP_V3D16
, NULL
),
25602 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25604 ARM_EXT2_V6T2_V8M
),
25605 FPU_ARCH_NEON_VFP_V4
, NULL
),
25606 /* APM X-Gene family. */
25607 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25609 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A_CRC
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25612 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25616 struct arm_arch_option_table
25620 const arm_feature_set value
;
25621 const arm_feature_set default_fpu
;
25624 /* This list should, at a minimum, contain all the architecture names
25625 recognized by GCC. */
25626 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25627 static const struct arm_arch_option_table arm_archs
[] =
25629 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25630 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25631 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25632 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25633 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25634 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25635 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25636 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25637 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25638 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25639 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25640 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25641 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25642 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25643 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25644 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25645 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25646 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25647 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25648 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25649 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25650 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25651 kept to preserve existing behaviour. */
25652 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25653 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25654 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25655 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25656 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25657 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25658 kept to preserve existing behaviour. */
25659 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25660 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25661 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25662 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25663 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25664 /* The official spelling of the ARMv7 profile variants is the dashed form.
25665 Accept the non-dashed form for compatibility with old toolchains. */
25666 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25667 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25668 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25669 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25670 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25671 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25672 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25673 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25674 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25675 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25676 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25677 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25678 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25679 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
25680 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25681 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25682 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25683 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25685 #undef ARM_ARCH_OPT
25687 /* ISA extensions in the co-processor and main instruction set space. */
25688 struct arm_option_extension_value_table
25692 const arm_feature_set merge_value
;
25693 const arm_feature_set clear_value
;
25694 /* List of architectures for which an extension is available. ARM_ARCH_NONE
25695 indicates that an extension is available for all architectures while
25696 ARM_ANY marks an empty entry. */
25697 const arm_feature_set allowed_archs
[2];
25700 /* The following table must be in alphabetical order with a NULL last entry.
25702 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
25703 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
25704 static const struct arm_option_extension_value_table arm_extensions
[] =
25706 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25707 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25708 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25709 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25710 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25711 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25712 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25713 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
25714 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25715 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25716 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25717 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25719 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25720 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25721 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25722 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25723 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25724 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
25725 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25726 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
25727 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25728 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
25729 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25730 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25731 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25732 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25733 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25734 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25735 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25736 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25737 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25738 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25739 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
25740 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
25741 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25742 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25743 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25744 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25745 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25746 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25747 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
25748 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25749 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25750 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25751 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25752 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25754 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25755 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25756 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25757 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
25758 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
25762 /* ISA floating-point and Advanced SIMD extensions. */
25763 struct arm_option_fpu_value_table
25766 const arm_feature_set value
;
25769 /* This list should, at a minimum, contain all the fpu names
25770 recognized by GCC. */
25771 static const struct arm_option_fpu_value_table arm_fpus
[] =
25773 {"softfpa", FPU_NONE
},
25774 {"fpe", FPU_ARCH_FPE
},
25775 {"fpe2", FPU_ARCH_FPE
},
25776 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25777 {"fpa", FPU_ARCH_FPA
},
25778 {"fpa10", FPU_ARCH_FPA
},
25779 {"fpa11", FPU_ARCH_FPA
},
25780 {"arm7500fe", FPU_ARCH_FPA
},
25781 {"softvfp", FPU_ARCH_VFP
},
25782 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25783 {"vfp", FPU_ARCH_VFP_V2
},
25784 {"vfp9", FPU_ARCH_VFP_V2
},
25785 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
25786 {"vfp10", FPU_ARCH_VFP_V2
},
25787 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25788 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25789 {"vfpv2", FPU_ARCH_VFP_V2
},
25790 {"vfpv3", FPU_ARCH_VFP_V3
},
25791 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25792 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25793 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25794 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25795 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25796 {"arm1020t", FPU_ARCH_VFP_V1
},
25797 {"arm1020e", FPU_ARCH_VFP_V2
},
25798 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
25799 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25800 {"maverick", FPU_ARCH_MAVERICK
},
25801 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25802 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25803 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25804 {"vfpv4", FPU_ARCH_VFP_V4
},
25805 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25806 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25807 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25808 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25809 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25810 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25811 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25812 {"crypto-neon-fp-armv8",
25813 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25814 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25815 {"crypto-neon-fp-armv8.1",
25816 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25817 {NULL
, ARM_ARCH_NONE
}
25820 struct arm_option_value_table
25826 static const struct arm_option_value_table arm_float_abis
[] =
25828 {"hard", ARM_FLOAT_ABI_HARD
},
25829 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25830 {"soft", ARM_FLOAT_ABI_SOFT
},
25835 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25836 static const struct arm_option_value_table arm_eabis
[] =
25838 {"gnu", EF_ARM_EABI_UNKNOWN
},
25839 {"4", EF_ARM_EABI_VER4
},
25840 {"5", EF_ARM_EABI_VER5
},
25845 struct arm_long_option_table
25847 const char * option
; /* Substring to match. */
25848 const char * help
; /* Help information. */
25849 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
25850 const char * deprecated
; /* If non-null, print this message. */
25854 arm_parse_extension (const char *str
, const arm_feature_set
**opt_p
)
25856 arm_feature_set
*ext_set
= XNEW (arm_feature_set
);
25858 /* We insist on extensions being specified in alphabetical order, and with
25859 extensions being added before being removed. We achieve this by having
25860 the global ARM_EXTENSIONS table in alphabetical order, and using the
25861 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25862 or removing it (0) and only allowing it to change in the order
25864 const struct arm_option_extension_value_table
* opt
= NULL
;
25865 const arm_feature_set arm_any
= ARM_ANY
;
25866 int adding_value
= -1;
25868 /* Copy the feature set, so that we can modify it. */
25869 *ext_set
= **opt_p
;
25872 while (str
!= NULL
&& *str
!= 0)
25879 as_bad (_("invalid architectural extension"));
25884 ext
= strchr (str
, '+');
25889 len
= strlen (str
);
25891 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25893 if (adding_value
!= 0)
25896 opt
= arm_extensions
;
25904 if (adding_value
== -1)
25907 opt
= arm_extensions
;
25909 else if (adding_value
!= 1)
25911 as_bad (_("must specify extensions to add before specifying "
25912 "those to remove"));
25919 as_bad (_("missing architectural extension"));
25923 gas_assert (adding_value
!= -1);
25924 gas_assert (opt
!= NULL
);
25926 /* Scan over the options table trying to find an exact match. */
25927 for (; opt
->name
!= NULL
; opt
++)
25928 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25930 int i
, nb_allowed_archs
=
25931 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
25932 /* Check we can apply the extension to this architecture. */
25933 for (i
= 0; i
< nb_allowed_archs
; i
++)
25936 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
25938 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *ext_set
))
25941 if (i
== nb_allowed_archs
)
25943 as_bad (_("extension does not apply to the base architecture"));
25947 /* Add or remove the extension. */
25949 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25951 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25956 if (opt
->name
== NULL
)
25958 /* Did we fail to find an extension because it wasn't specified in
25959 alphabetical order, or because it does not exist? */
25961 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25962 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25965 if (opt
->name
== NULL
)
25966 as_bad (_("unknown architectural extension `%s'"), str
);
25968 as_bad (_("architectural extensions must be specified in "
25969 "alphabetical order"));
25975 /* We should skip the extension we've just matched the next time
25987 arm_parse_cpu (const char *str
)
25989 const struct arm_cpu_option_table
*opt
;
25990 const char *ext
= strchr (str
, '+');
25996 len
= strlen (str
);
26000 as_bad (_("missing cpu name `%s'"), str
);
26004 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26005 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26007 mcpu_cpu_opt
= &opt
->value
;
26008 mcpu_fpu_opt
= &opt
->default_fpu
;
26009 if (opt
->canonical_name
)
26011 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26012 strcpy (selected_cpu_name
, opt
->canonical_name
);
26018 if (len
>= sizeof selected_cpu_name
)
26019 len
= (sizeof selected_cpu_name
) - 1;
26021 for (i
= 0; i
< len
; i
++)
26022 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26023 selected_cpu_name
[i
] = 0;
26027 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
26032 as_bad (_("unknown cpu `%s'"), str
);
26037 arm_parse_arch (const char *str
)
26039 const struct arm_arch_option_table
*opt
;
26040 const char *ext
= strchr (str
, '+');
26046 len
= strlen (str
);
26050 as_bad (_("missing architecture name `%s'"), str
);
26054 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26055 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26057 march_cpu_opt
= &opt
->value
;
26058 march_fpu_opt
= &opt
->default_fpu
;
26059 strcpy (selected_cpu_name
, opt
->name
);
26062 return arm_parse_extension (ext
, &march_cpu_opt
);
26067 as_bad (_("unknown architecture `%s'\n"), str
);
26072 arm_parse_fpu (const char * str
)
26074 const struct arm_option_fpu_value_table
* opt
;
26076 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26077 if (streq (opt
->name
, str
))
26079 mfpu_opt
= &opt
->value
;
26083 as_bad (_("unknown floating point format `%s'\n"), str
);
26088 arm_parse_float_abi (const char * str
)
26090 const struct arm_option_value_table
* opt
;
26092 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26093 if (streq (opt
->name
, str
))
26095 mfloat_abi_opt
= opt
->value
;
26099 as_bad (_("unknown floating point abi `%s'\n"), str
);
26105 arm_parse_eabi (const char * str
)
26107 const struct arm_option_value_table
*opt
;
26109 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26110 if (streq (opt
->name
, str
))
26112 meabi_flags
= opt
->value
;
26115 as_bad (_("unknown EABI `%s'\n"), str
);
26121 arm_parse_it_mode (const char * str
)
26123 bfd_boolean ret
= TRUE
;
26125 if (streq ("arm", str
))
26126 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26127 else if (streq ("thumb", str
))
26128 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26129 else if (streq ("always", str
))
26130 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26131 else if (streq ("never", str
))
26132 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26135 as_bad (_("unknown implicit IT mode `%s', should be "\
26136 "arm, thumb, always, or never."), str
);
26144 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26146 codecomposer_syntax
= TRUE
;
26147 arm_comment_chars
[0] = ';';
26148 arm_line_separator_chars
[0] = 0;
26152 struct arm_long_option_table arm_long_opts
[] =
26154 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26155 arm_parse_cpu
, NULL
},
26156 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26157 arm_parse_arch
, NULL
},
26158 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26159 arm_parse_fpu
, NULL
},
26160 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26161 arm_parse_float_abi
, NULL
},
26163 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26164 arm_parse_eabi
, NULL
},
26166 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26167 arm_parse_it_mode
, NULL
},
26168 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26169 arm_ccs_mode
, NULL
},
26170 {NULL
, NULL
, 0, NULL
}
26174 md_parse_option (int c
, const char * arg
)
26176 struct arm_option_table
*opt
;
26177 const struct arm_legacy_option_table
*fopt
;
26178 struct arm_long_option_table
*lopt
;
26184 target_big_endian
= 1;
26190 target_big_endian
= 0;
26194 case OPTION_FIX_V4BX
:
26199 /* Listing option. Just ignore these, we don't support additional
26204 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26206 if (c
== opt
->option
[0]
26207 && ((arg
== NULL
&& opt
->option
[1] == 0)
26208 || streq (arg
, opt
->option
+ 1)))
26210 /* If the option is deprecated, tell the user. */
26211 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26212 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26213 arg
? arg
: "", _(opt
->deprecated
));
26215 if (opt
->var
!= NULL
)
26216 *opt
->var
= opt
->value
;
26222 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26224 if (c
== fopt
->option
[0]
26225 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26226 || streq (arg
, fopt
->option
+ 1)))
26228 /* If the option is deprecated, tell the user. */
26229 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26230 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26231 arg
? arg
: "", _(fopt
->deprecated
));
26233 if (fopt
->var
!= NULL
)
26234 *fopt
->var
= &fopt
->value
;
26240 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26242 /* These options are expected to have an argument. */
26243 if (c
== lopt
->option
[0]
26245 && strncmp (arg
, lopt
->option
+ 1,
26246 strlen (lopt
->option
+ 1)) == 0)
26248 /* If the option is deprecated, tell the user. */
26249 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26250 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26251 _(lopt
->deprecated
));
26253 /* Call the sup-option parser. */
26254 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26265 md_show_usage (FILE * fp
)
26267 struct arm_option_table
*opt
;
26268 struct arm_long_option_table
*lopt
;
26270 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26272 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26273 if (opt
->help
!= NULL
)
26274 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26276 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26277 if (lopt
->help
!= NULL
)
26278 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26282 -EB assemble code for a big-endian cpu\n"));
26287 -EL assemble code for a little-endian cpu\n"));
26291 --fix-v4bx Allow BX in ARMv4 code\n"));
26299 arm_feature_set flags
;
26300 } cpu_arch_ver_table
;
26302 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26303 must be sorted least features first but some reordering is needed, eg. for
26304 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26305 static const cpu_arch_ver_table cpu_arch_ver
[] =
26311 {4, ARM_ARCH_V5TE
},
26312 {5, ARM_ARCH_V5TEJ
},
26316 {11, ARM_ARCH_V6M
},
26317 {12, ARM_ARCH_V6SM
},
26318 {8, ARM_ARCH_V6T2
},
26319 {10, ARM_ARCH_V7VE
},
26320 {10, ARM_ARCH_V7R
},
26321 {10, ARM_ARCH_V7M
},
26322 {14, ARM_ARCH_V8A
},
26323 {16, ARM_ARCH_V8M_BASE
},
26324 {17, ARM_ARCH_V8M_MAIN
},
26328 /* Set an attribute if it has not already been set by the user. */
26330 aeabi_set_attribute_int (int tag
, int value
)
26333 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26334 || !attributes_set_explicitly
[tag
])
26335 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26339 aeabi_set_attribute_string (int tag
, const char *value
)
26342 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26343 || !attributes_set_explicitly
[tag
])
26344 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26347 /* Set the public EABI object attributes. */
26349 aeabi_set_public_attributes (void)
26354 int fp16_optional
= 0;
26355 arm_feature_set arm_arch
= ARM_ARCH_NONE
;
26356 arm_feature_set flags
;
26357 arm_feature_set tmp
;
26358 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26359 const cpu_arch_ver_table
*p
;
26361 /* Choose the architecture based on the capabilities of the requested cpu
26362 (if any) and/or the instructions actually used. */
26363 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26364 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26365 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26367 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26368 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26370 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26371 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26373 selected_cpu
= flags
;
26375 /* Allow the user to override the reported architecture. */
26378 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26379 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26382 /* We need to make sure that the attributes do not identify us as v6S-M
26383 when the only v6S-M feature in use is the Operating System Extensions. */
26384 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26385 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26386 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26390 for (p
= cpu_arch_ver
; p
->val
; p
++)
26392 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26395 arm_arch
= p
->flags
;
26396 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26400 /* The table lookup above finds the last architecture to contribute
26401 a new feature. Unfortunately, Tag13 is a subset of the union of
26402 v6T2 and v7-M, so it is never seen as contributing a new feature.
26403 We can not search for the last entry which is entirely used,
26404 because if no CPU is specified we build up only those flags
26405 actually used. Perhaps we should separate out the specified
26406 and implicit cases. Avoid taking this path for -march=all by
26407 checking for contradictory v7-A / v7-M features. */
26408 if (arch
== TAG_CPU_ARCH_V7
26409 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26410 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26411 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26413 arch
= TAG_CPU_ARCH_V7E_M
;
26414 arm_arch
= (arm_feature_set
) ARM_ARCH_V7EM
;
26417 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26418 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26420 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26421 arm_arch
= (arm_feature_set
) ARM_ARCH_V8M_MAIN
;
26424 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26425 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26426 ARMv8-M, -march=all must be detected as ARMv8-A. */
26427 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26428 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26430 arch
= TAG_CPU_ARCH_V8
;
26431 arm_arch
= (arm_feature_set
) ARM_ARCH_V8A
;
26434 /* Tag_CPU_name. */
26435 if (selected_cpu_name
[0])
26439 q
= selected_cpu_name
;
26440 if (strncmp (q
, "armv", 4) == 0)
26445 for (i
= 0; q
[i
]; i
++)
26446 q
[i
] = TOUPPER (q
[i
]);
26448 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26451 /* Tag_CPU_arch. */
26452 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26454 /* Tag_CPU_arch_profile. */
26455 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26456 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26457 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26458 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
)))
26460 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26462 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26467 if (profile
!= '\0')
26468 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26470 /* Tag_DSP_extension. */
26471 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_dsp
))
26473 arm_feature_set ext
;
26475 /* DSP instructions not in architecture. */
26476 ARM_CLEAR_FEATURE (ext
, flags
, arm_arch
);
26477 if (ARM_CPU_HAS_FEATURE (ext
, arm_ext_dsp
))
26478 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26481 /* Tag_ARM_ISA_use. */
26482 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26484 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26486 /* Tag_THUMB_ISA_use. */
26487 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26492 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26493 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26495 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26499 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26502 /* Tag_VFP_arch. */
26503 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26504 aeabi_set_attribute_int (Tag_VFP_arch
,
26505 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26507 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26508 aeabi_set_attribute_int (Tag_VFP_arch
,
26509 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26511 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26514 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26516 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26518 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26521 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26522 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26523 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26524 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26525 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26527 /* Tag_ABI_HardFP_use. */
26528 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26529 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26530 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26532 /* Tag_WMMX_arch. */
26533 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26534 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26535 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26536 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26538 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26539 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26540 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26541 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26542 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26543 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26545 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26547 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26551 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26556 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26557 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26558 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26562 We set Tag_DIV_use to two when integer divide instructions have been used
26563 in ARM state, or when Thumb integer divide instructions have been used,
26564 but we have no architecture profile set, nor have we any ARM instructions.
26566 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26567 by the base architecture.
26569 For new architectures we will have to check these tests. */
26570 gas_assert (arch
<= TAG_CPU_ARCH_V8
26571 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26572 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26573 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26574 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26575 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26576 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26577 || (profile
== '\0'
26578 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26579 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26580 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26582 /* Tag_MP_extension_use. */
26583 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26584 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26586 /* Tag Virtualization_use. */
26587 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26589 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26592 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26595 /* Add the default contents for the .ARM.attributes section. */
26599 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26602 aeabi_set_public_attributes ();
26604 #endif /* OBJ_ELF */
26607 /* Parse a .cpu directive. */
26610 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26612 const struct arm_cpu_option_table
*opt
;
26616 name
= input_line_pointer
;
26617 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26618 input_line_pointer
++;
26619 saved_char
= *input_line_pointer
;
26620 *input_line_pointer
= 0;
26622 /* Skip the first "all" entry. */
26623 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26624 if (streq (opt
->name
, name
))
26626 mcpu_cpu_opt
= &opt
->value
;
26627 selected_cpu
= opt
->value
;
26628 if (opt
->canonical_name
)
26629 strcpy (selected_cpu_name
, opt
->canonical_name
);
26633 for (i
= 0; opt
->name
[i
]; i
++)
26634 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26636 selected_cpu_name
[i
] = 0;
26638 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26639 *input_line_pointer
= saved_char
;
26640 demand_empty_rest_of_line ();
26643 as_bad (_("unknown cpu `%s'"), name
);
26644 *input_line_pointer
= saved_char
;
26645 ignore_rest_of_line ();
26649 /* Parse a .arch directive. */
26652 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26654 const struct arm_arch_option_table
*opt
;
26658 name
= input_line_pointer
;
26659 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26660 input_line_pointer
++;
26661 saved_char
= *input_line_pointer
;
26662 *input_line_pointer
= 0;
26664 /* Skip the first "all" entry. */
26665 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26666 if (streq (opt
->name
, name
))
26668 mcpu_cpu_opt
= &opt
->value
;
26669 selected_cpu
= opt
->value
;
26670 strcpy (selected_cpu_name
, opt
->name
);
26671 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26672 *input_line_pointer
= saved_char
;
26673 demand_empty_rest_of_line ();
26677 as_bad (_("unknown architecture `%s'\n"), name
);
26678 *input_line_pointer
= saved_char
;
26679 ignore_rest_of_line ();
26683 /* Parse a .object_arch directive. */
26686 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26688 const struct arm_arch_option_table
*opt
;
26692 name
= input_line_pointer
;
26693 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26694 input_line_pointer
++;
26695 saved_char
= *input_line_pointer
;
26696 *input_line_pointer
= 0;
26698 /* Skip the first "all" entry. */
26699 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26700 if (streq (opt
->name
, name
))
26702 object_arch
= &opt
->value
;
26703 *input_line_pointer
= saved_char
;
26704 demand_empty_rest_of_line ();
26708 as_bad (_("unknown architecture `%s'\n"), name
);
26709 *input_line_pointer
= saved_char
;
26710 ignore_rest_of_line ();
26713 /* Parse a .arch_extension directive. */
26716 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26718 const struct arm_option_extension_value_table
*opt
;
26719 const arm_feature_set arm_any
= ARM_ANY
;
26722 int adding_value
= 1;
26724 name
= input_line_pointer
;
26725 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26726 input_line_pointer
++;
26727 saved_char
= *input_line_pointer
;
26728 *input_line_pointer
= 0;
26730 if (strlen (name
) >= 2
26731 && strncmp (name
, "no", 2) == 0)
26737 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26738 if (streq (opt
->name
, name
))
26740 int i
, nb_allowed_archs
=
26741 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
26742 for (i
= 0; i
< nb_allowed_archs
; i
++)
26745 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26747 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
26751 if (i
== nb_allowed_archs
)
26753 as_bad (_("architectural extension `%s' is not allowed for the "
26754 "current base architecture"), name
);
26759 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26762 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26764 mcpu_cpu_opt
= &selected_cpu
;
26765 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26766 *input_line_pointer
= saved_char
;
26767 demand_empty_rest_of_line ();
26771 if (opt
->name
== NULL
)
26772 as_bad (_("unknown architecture extension `%s'\n"), name
);
26774 *input_line_pointer
= saved_char
;
26775 ignore_rest_of_line ();
26778 /* Parse a .fpu directive. */
26781 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26783 const struct arm_option_fpu_value_table
*opt
;
26787 name
= input_line_pointer
;
26788 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26789 input_line_pointer
++;
26790 saved_char
= *input_line_pointer
;
26791 *input_line_pointer
= 0;
26793 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26794 if (streq (opt
->name
, name
))
26796 mfpu_opt
= &opt
->value
;
26797 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26798 *input_line_pointer
= saved_char
;
26799 demand_empty_rest_of_line ();
26803 as_bad (_("unknown floating point format `%s'\n"), name
);
26804 *input_line_pointer
= saved_char
;
26805 ignore_rest_of_line ();
26808 /* Copy symbol information. */
26811 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26813 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26817 /* Given a symbolic attribute NAME, return the proper integer value.
26818 Returns -1 if the attribute is not known. */
26821 arm_convert_symbolic_attribute (const char *name
)
26823 static const struct
26828 attribute_table
[] =
26830 /* When you modify this table you should
26831 also modify the list in doc/c-arm.texi. */
26832 #define T(tag) {#tag, tag}
26833 T (Tag_CPU_raw_name
),
26836 T (Tag_CPU_arch_profile
),
26837 T (Tag_ARM_ISA_use
),
26838 T (Tag_THUMB_ISA_use
),
26842 T (Tag_Advanced_SIMD_arch
),
26843 T (Tag_PCS_config
),
26844 T (Tag_ABI_PCS_R9_use
),
26845 T (Tag_ABI_PCS_RW_data
),
26846 T (Tag_ABI_PCS_RO_data
),
26847 T (Tag_ABI_PCS_GOT_use
),
26848 T (Tag_ABI_PCS_wchar_t
),
26849 T (Tag_ABI_FP_rounding
),
26850 T (Tag_ABI_FP_denormal
),
26851 T (Tag_ABI_FP_exceptions
),
26852 T (Tag_ABI_FP_user_exceptions
),
26853 T (Tag_ABI_FP_number_model
),
26854 T (Tag_ABI_align_needed
),
26855 T (Tag_ABI_align8_needed
),
26856 T (Tag_ABI_align_preserved
),
26857 T (Tag_ABI_align8_preserved
),
26858 T (Tag_ABI_enum_size
),
26859 T (Tag_ABI_HardFP_use
),
26860 T (Tag_ABI_VFP_args
),
26861 T (Tag_ABI_WMMX_args
),
26862 T (Tag_ABI_optimization_goals
),
26863 T (Tag_ABI_FP_optimization_goals
),
26864 T (Tag_compatibility
),
26865 T (Tag_CPU_unaligned_access
),
26866 T (Tag_FP_HP_extension
),
26867 T (Tag_VFP_HP_extension
),
26868 T (Tag_ABI_FP_16bit_format
),
26869 T (Tag_MPextension_use
),
26871 T (Tag_nodefaults
),
26872 T (Tag_also_compatible_with
),
26873 T (Tag_conformance
),
26875 T (Tag_Virtualization_use
),
26876 T (Tag_DSP_extension
),
26877 /* We deliberately do not include Tag_MPextension_use_legacy. */
26885 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26886 if (streq (name
, attribute_table
[i
].name
))
26887 return attribute_table
[i
].tag
;
26893 /* Apply sym value for relocations only in the case that they are for
26894 local symbols in the same segment as the fixup and you have the
26895 respective architectural feature for blx and simple switches. */
26897 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26900 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26901 /* PR 17444: If the local symbol is in a different section then a reloc
26902 will always be generated for it, so applying the symbol value now
26903 will result in a double offset being stored in the relocation. */
26904 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26905 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26907 switch (fixP
->fx_r_type
)
26909 case BFD_RELOC_ARM_PCREL_BLX
:
26910 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26911 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26915 case BFD_RELOC_ARM_PCREL_CALL
:
26916 case BFD_RELOC_THUMB_PCREL_BLX
:
26917 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26928 #endif /* OBJ_ELF */