1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1012 /* Toggle value[pos]. */
1013 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1017 /* This array holds the chars that always start a comment. If the
1018 pre-processor is disabled, these aren't very useful. */
1019 char arm_comment_chars
[] = "@";
1021 /* This array holds the chars that only start a comment at the beginning of
1022 a line. If the line seems to have the form '# 123 filename'
1023 .line and .file directives will appear in the pre-processed output. */
1024 /* Note that input_file.c hand checks for '#' at the beginning of the
1025 first line of the input file. This is because the compiler outputs
1026 #NO_APP at the beginning of its output. */
1027 /* Also note that comments like this one will always work. */
1028 const char line_comment_chars
[] = "#";
1030 char arm_line_separator_chars
[] = ";";
1032 /* Chars that can be used to separate mant
1033 from exp in floating point numbers. */
1034 const char EXP_CHARS
[] = "eE";
1036 /* Chars that mean this number is a floating point constant. */
1037 /* As in 0f12.456 */
1038 /* or 0d1.2345e12 */
1040 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1042 /* Prefix characters that indicate the start of an immediate
1044 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1046 /* Separator character handling. */
1048 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1051 skip_past_char (char ** str
, char c
)
1053 /* PR gas/14987: Allow for whitespace before the expected character. */
1054 skip_whitespace (*str
);
1065 #define skip_past_comma(str) skip_past_char (str, ',')
1067 /* Arithmetic expressions (possibly involving symbols). */
1069 /* Return TRUE if anything in the expression is a bignum. */
1072 walk_no_bignums (symbolS
* sp
)
1074 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1077 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1079 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1080 || (symbol_get_value_expression (sp
)->X_op_symbol
1081 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1087 static bfd_boolean in_my_get_expression
= FALSE
;
1089 /* Third argument to my_get_expression. */
1090 #define GE_NO_PREFIX 0
1091 #define GE_IMM_PREFIX 1
1092 #define GE_OPT_PREFIX 2
1093 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1094 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1095 #define GE_OPT_PREFIX_BIG 3
1098 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1102 /* In unified syntax, all prefixes are optional. */
1104 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1107 switch (prefix_mode
)
1109 case GE_NO_PREFIX
: break;
1111 if (!is_immediate_prefix (**str
))
1113 inst
.error
= _("immediate expression requires a # prefix");
1119 case GE_OPT_PREFIX_BIG
:
1120 if (is_immediate_prefix (**str
))
1127 memset (ep
, 0, sizeof (expressionS
));
1129 save_in
= input_line_pointer
;
1130 input_line_pointer
= *str
;
1131 in_my_get_expression
= TRUE
;
1133 in_my_get_expression
= FALSE
;
1135 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1137 /* We found a bad or missing expression in md_operand(). */
1138 *str
= input_line_pointer
;
1139 input_line_pointer
= save_in
;
1140 if (inst
.error
== NULL
)
1141 inst
.error
= (ep
->X_op
== O_absent
1142 ? _("missing expression") :_("bad expression"));
1146 /* Get rid of any bignums now, so that we don't generate an error for which
1147 we can't establish a line number later on. Big numbers are never valid
1148 in instructions, which is where this routine is always called. */
1149 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1150 && (ep
->X_op
== O_big
1151 || (ep
->X_add_symbol
1152 && (walk_no_bignums (ep
->X_add_symbol
)
1154 && walk_no_bignums (ep
->X_op_symbol
))))))
1156 inst
.error
= _("invalid constant");
1157 *str
= input_line_pointer
;
1158 input_line_pointer
= save_in
;
1162 *str
= input_line_pointer
;
1163 input_line_pointer
= save_in
;
1167 /* Turn a string in input_line_pointer into a floating point constant
1168 of type TYPE, and store the appropriate bytes in *LITP. The number
1169 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1170 returned, or NULL on OK.
1172 Note that fp constants aren't represent in the normal way on the ARM.
1173 In big endian mode, things are as expected. However, in little endian
1174 mode fp constants are big-endian word-wise, and little-endian byte-wise
1175 within the words. For example, (double) 1.1 in big endian mode is
1176 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1177 the byte sequence 99 99 f1 3f 9a 99 99 99.
1179 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1182 md_atof (int type
, char * litP
, int * sizeP
)
1185 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1217 return _("Unrecognized or unsupported floating point constant");
1220 t
= atof_ieee (input_line_pointer
, type
, words
);
1222 input_line_pointer
= t
;
1223 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1225 if (target_big_endian
)
1227 for (i
= 0; i
< prec
; i
++)
1229 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1230 litP
+= sizeof (LITTLENUM_TYPE
);
1235 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1236 for (i
= prec
- 1; i
>= 0; i
--)
1238 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1239 litP
+= sizeof (LITTLENUM_TYPE
);
1242 /* For a 4 byte float the order of elements in `words' is 1 0.
1243 For an 8 byte float the order is 1 0 3 2. */
1244 for (i
= 0; i
< prec
; i
+= 2)
1246 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1247 sizeof (LITTLENUM_TYPE
));
1248 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1249 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1250 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1257 /* We handle all bad expressions here, so that we can report the faulty
1258 instruction in the error message. */
1261 md_operand (expressionS
* exp
)
1263 if (in_my_get_expression
)
1264 exp
->X_op
= O_illegal
;
1267 /* Immediate values. */
1270 /* Generic immediate-value read function for use in directives.
1271 Accepts anything that 'expression' can fold to a constant.
1272 *val receives the number. */
1275 immediate_for_directive (int *val
)
1278 exp
.X_op
= O_illegal
;
1280 if (is_immediate_prefix (*input_line_pointer
))
1282 input_line_pointer
++;
1286 if (exp
.X_op
!= O_constant
)
1288 as_bad (_("expected #constant"));
1289 ignore_rest_of_line ();
1292 *val
= exp
.X_add_number
;
1297 /* Register parsing. */
1299 /* Generic register parser. CCP points to what should be the
1300 beginning of a register name. If it is indeed a valid register
1301 name, advance CCP over it and return the reg_entry structure;
1302 otherwise return NULL. Does not issue diagnostics. */
1304 static struct reg_entry
*
1305 arm_reg_parse_multi (char **ccp
)
1309 struct reg_entry
*reg
;
1311 skip_whitespace (start
);
1313 #ifdef REGISTER_PREFIX
1314 if (*start
!= REGISTER_PREFIX
)
1318 #ifdef OPTIONAL_REGISTER_PREFIX
1319 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1324 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1329 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1331 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1341 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1342 enum arm_reg_type type
)
1344 /* Alternative syntaxes are accepted for a few register classes. */
1351 /* Generic coprocessor register names are allowed for these. */
1352 if (reg
&& reg
->type
== REG_TYPE_CN
)
1357 /* For backward compatibility, a bare number is valid here. */
1359 unsigned long processor
= strtoul (start
, ccp
, 10);
1360 if (*ccp
!= start
&& processor
<= 15)
1365 case REG_TYPE_MMXWC
:
1366 /* WC includes WCG. ??? I'm not sure this is true for all
1367 instructions that take WC registers. */
1368 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1379 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1380 return value is the register number or FAIL. */
1383 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1386 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1389 /* Do not allow a scalar (reg+index) to parse as a register. */
1390 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1393 if (reg
&& reg
->type
== type
)
1396 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1403 /* Parse a Neon type specifier. *STR should point at the leading '.'
1404 character. Does no verification at this stage that the type fits the opcode
1411 Can all be legally parsed by this function.
1413 Fills in neon_type struct pointer with parsed information, and updates STR
1414 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1415 type, FAIL if not. */
1418 parse_neon_type (struct neon_type
*type
, char **str
)
1425 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1427 enum neon_el_type thistype
= NT_untyped
;
1428 unsigned thissize
= -1u;
1435 /* Just a size without an explicit type. */
1439 switch (TOLOWER (*ptr
))
1441 case 'i': thistype
= NT_integer
; break;
1442 case 'f': thistype
= NT_float
; break;
1443 case 'p': thistype
= NT_poly
; break;
1444 case 's': thistype
= NT_signed
; break;
1445 case 'u': thistype
= NT_unsigned
; break;
1447 thistype
= NT_float
;
1452 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1458 /* .f is an abbreviation for .f32. */
1459 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1464 thissize
= strtoul (ptr
, &ptr
, 10);
1466 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1469 as_bad (_("bad size %d in type specifier"), thissize
);
1477 type
->el
[type
->elems
].type
= thistype
;
1478 type
->el
[type
->elems
].size
= thissize
;
1483 /* Empty/missing type is not a successful parse. */
1484 if (type
->elems
== 0)
1492 /* Errors may be set multiple times during parsing or bit encoding
1493 (particularly in the Neon bits), but usually the earliest error which is set
1494 will be the most meaningful. Avoid overwriting it with later (cascading)
1495 errors by calling this function. */
1498 first_error (const char *err
)
1504 /* Parse a single type, e.g. ".s32", leading period included. */
1506 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1509 struct neon_type optype
;
1513 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1515 if (optype
.elems
== 1)
1516 *vectype
= optype
.el
[0];
1519 first_error (_("only one type should be specified for operand"));
1525 first_error (_("vector type expected"));
1537 /* Special meanings for indices (which have a range of 0-7), which will fit into
1540 #define NEON_ALL_LANES 15
1541 #define NEON_INTERLEAVE_LANES 14
1543 /* Record a use of the given feature. */
1545 record_feature_use (const arm_feature_set
*feature
)
1548 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1550 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1553 /* If the given feature available in the selected CPU, mark it as used.
1554 Returns TRUE iff feature is available. */
1556 mark_feature_used (const arm_feature_set
*feature
)
1559 /* Do not support the use of MVE only instructions when in auto-detection or
1561 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1562 && ARM_CPU_IS_ANY (cpu_variant
))
1564 first_error (BAD_MVE_AUTO
);
1567 /* Ensure the option is valid on the current architecture. */
1568 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1571 /* Add the appropriate architecture feature for the barrier option used.
1573 record_feature_use (feature
);
1578 /* Parse either a register or a scalar, with an optional type. Return the
1579 register number, and optionally fill in the actual type of the register
1580 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1581 type/index information in *TYPEINFO. */
1584 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1585 enum arm_reg_type
*rtype
,
1586 struct neon_typed_alias
*typeinfo
)
1589 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1590 struct neon_typed_alias atype
;
1591 struct neon_type_el parsetype
;
1595 atype
.eltype
.type
= NT_invtype
;
1596 atype
.eltype
.size
= -1;
1598 /* Try alternate syntax for some types of register. Note these are mutually
1599 exclusive with the Neon syntax extensions. */
1602 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1610 /* Undo polymorphism when a set of register types may be accepted. */
1611 if ((type
== REG_TYPE_NDQ
1612 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1613 || (type
== REG_TYPE_VFSD
1614 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1615 || (type
== REG_TYPE_NSDQ
1616 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1617 || reg
->type
== REG_TYPE_NQ
))
1618 || (type
== REG_TYPE_NSD
1619 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1620 || (type
== REG_TYPE_MMXWC
1621 && (reg
->type
== REG_TYPE_MMXWCG
)))
1622 type
= (enum arm_reg_type
) reg
->type
;
1624 if (type
== REG_TYPE_MQ
)
1626 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1629 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1632 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1634 first_error (_("expected MVE register [q0..q7]"));
1639 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1640 && (type
== REG_TYPE_NQ
))
1644 if (type
!= reg
->type
)
1650 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1652 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1654 first_error (_("can't redefine type for operand"));
1657 atype
.defined
|= NTA_HASTYPE
;
1658 atype
.eltype
= parsetype
;
1661 if (skip_past_char (&str
, '[') == SUCCESS
)
1663 if (type
!= REG_TYPE_VFD
1664 && !(type
== REG_TYPE_VFS
1665 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1666 && !(type
== REG_TYPE_NQ
1667 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1669 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1670 first_error (_("only D and Q registers may be indexed"));
1672 first_error (_("only D registers may be indexed"));
1676 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1678 first_error (_("can't change index for operand"));
1682 atype
.defined
|= NTA_HASINDEX
;
1684 if (skip_past_char (&str
, ']') == SUCCESS
)
1685 atype
.index
= NEON_ALL_LANES
;
1690 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1692 if (exp
.X_op
!= O_constant
)
1694 first_error (_("constant expression required"));
1698 if (skip_past_char (&str
, ']') == FAIL
)
1701 atype
.index
= exp
.X_add_number
;
1716 /* Like arm_reg_parse, but also allow the following extra features:
1717 - If RTYPE is non-zero, return the (possibly restricted) type of the
1718 register (e.g. Neon double or quad reg when either has been requested).
1719 - If this is a Neon vector type with additional type information, fill
1720 in the struct pointed to by VECTYPE (if non-NULL).
1721 This function will fault on encountering a scalar. */
1724 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1725 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1727 struct neon_typed_alias atype
;
1729 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1734 /* Do not allow regname(... to parse as a register. */
1738 /* Do not allow a scalar (reg+index) to parse as a register. */
1739 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1741 first_error (_("register operand expected, but got scalar"));
1746 *vectype
= atype
.eltype
;
1753 #define NEON_SCALAR_REG(X) ((X) >> 4)
1754 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1756 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1757 have enough information to be able to do a good job bounds-checking. So, we
1758 just do easy checks here, and do further checks later. */
1761 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1762 arm_reg_type reg_type
)
1766 struct neon_typed_alias atype
;
1769 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1787 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1790 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1792 first_error (_("scalar must have an index"));
1795 else if (atype
.index
>= reg_size
/ elsize
)
1797 first_error (_("scalar index out of range"));
1802 *type
= atype
.eltype
;
1806 return reg
* 16 + atype
.index
;
1809 /* Types of registers in a list. */
1822 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1825 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1831 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1833 /* We come back here if we get ranges concatenated by '+' or '|'. */
1836 skip_whitespace (str
);
1849 const char apsr_str
[] = "apsr";
1850 int apsr_str_len
= strlen (apsr_str
);
1852 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1853 if (etype
== REGLIST_CLRM
)
1855 if (reg
== REG_SP
|| reg
== REG_PC
)
1857 else if (reg
== FAIL
1858 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1859 && !ISALPHA (*(str
+ apsr_str_len
)))
1862 str
+= apsr_str_len
;
1867 first_error (_("r0-r12, lr or APSR expected"));
1871 else /* etype == REGLIST_RN. */
1875 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1886 first_error (_("bad range in register list"));
1890 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1892 if (range
& (1 << i
))
1894 (_("Warning: duplicated register (r%d) in register list"),
1902 if (range
& (1 << reg
))
1903 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1905 else if (reg
<= cur_reg
)
1906 as_tsktsk (_("Warning: register range not in ascending order"));
1911 while (skip_past_comma (&str
) != FAIL
1912 || (in_range
= 1, *str
++ == '-'));
1915 if (skip_past_char (&str
, '}') == FAIL
)
1917 first_error (_("missing `}'"));
1921 else if (etype
== REGLIST_RN
)
1925 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1928 if (exp
.X_op
== O_constant
)
1930 if (exp
.X_add_number
1931 != (exp
.X_add_number
& 0x0000ffff))
1933 inst
.error
= _("invalid register mask");
1937 if ((range
& exp
.X_add_number
) != 0)
1939 int regno
= range
& exp
.X_add_number
;
1942 regno
= (1 << regno
) - 1;
1944 (_("Warning: duplicated register (r%d) in register list"),
1948 range
|= exp
.X_add_number
;
1952 if (inst
.relocs
[0].type
!= 0)
1954 inst
.error
= _("expression too complex");
1958 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1959 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1960 inst
.relocs
[0].pc_rel
= 0;
1964 if (*str
== '|' || *str
== '+')
1970 while (another_range
);
1976 /* Parse a VFP register list. If the string is invalid return FAIL.
1977 Otherwise return the number of registers, and set PBASE to the first
1978 register. Parses registers of type ETYPE.
1979 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1980 - Q registers can be used to specify pairs of D registers
1981 - { } can be omitted from around a singleton register list
1982 FIXME: This is not implemented, as it would require backtracking in
1985 This could be done (the meaning isn't really ambiguous), but doesn't
1986 fit in well with the current parsing framework.
1987 - 32 D registers may be used (also true for VFPv3).
1988 FIXME: Types are ignored in these register lists, which is probably a
1992 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1993 bfd_boolean
*partial_match
)
1998 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2002 unsigned long mask
= 0;
2004 bfd_boolean vpr_seen
= FALSE
;
2005 bfd_boolean expect_vpr
=
2006 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2008 if (skip_past_char (&str
, '{') == FAIL
)
2010 inst
.error
= _("expecting {");
2017 case REGLIST_VFP_S_VPR
:
2018 regtype
= REG_TYPE_VFS
;
2023 case REGLIST_VFP_D_VPR
:
2024 regtype
= REG_TYPE_VFD
;
2027 case REGLIST_NEON_D
:
2028 regtype
= REG_TYPE_NDQ
;
2035 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2037 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2038 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2042 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2045 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2052 base_reg
= max_regs
;
2053 *partial_match
= FALSE
;
2057 int setmask
= 1, addregs
= 1;
2058 const char vpr_str
[] = "vpr";
2059 int vpr_str_len
= strlen (vpr_str
);
2061 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2065 if (new_base
== FAIL
2066 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2067 && !ISALPHA (*(str
+ vpr_str_len
))
2073 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2077 first_error (_("VPR expected last"));
2080 else if (new_base
== FAIL
)
2082 if (regtype
== REG_TYPE_VFS
)
2083 first_error (_("VFP single precision register or VPR "
2085 else /* regtype == REG_TYPE_VFD. */
2086 first_error (_("VFP/Neon double precision register or VPR "
2091 else if (new_base
== FAIL
)
2093 first_error (_(reg_expected_msgs
[regtype
]));
2097 *partial_match
= TRUE
;
2101 if (new_base
>= max_regs
)
2103 first_error (_("register out of range in list"));
2107 /* Note: a value of 2 * n is returned for the register Q<n>. */
2108 if (regtype
== REG_TYPE_NQ
)
2114 if (new_base
< base_reg
)
2115 base_reg
= new_base
;
2117 if (mask
& (setmask
<< new_base
))
2119 first_error (_("invalid register list"));
2123 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2125 as_tsktsk (_("register list not in ascending order"));
2129 mask
|= setmask
<< new_base
;
2132 if (*str
== '-') /* We have the start of a range expression */
2138 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2141 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2145 if (high_range
>= max_regs
)
2147 first_error (_("register out of range in list"));
2151 if (regtype
== REG_TYPE_NQ
)
2152 high_range
= high_range
+ 1;
2154 if (high_range
<= new_base
)
2156 inst
.error
= _("register range not in ascending order");
2160 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2162 if (mask
& (setmask
<< new_base
))
2164 inst
.error
= _("invalid register list");
2168 mask
|= setmask
<< new_base
;
2173 while (skip_past_comma (&str
) != FAIL
);
2177 /* Sanity check -- should have raised a parse error above. */
2178 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2183 if (expect_vpr
&& !vpr_seen
)
2185 first_error (_("VPR expected last"));
2189 /* Final test -- the registers must be consecutive. */
2191 for (i
= 0; i
< count
; i
++)
2193 if ((mask
& (1u << i
)) == 0)
2195 inst
.error
= _("non-contiguous register range");
2205 /* True if two alias types are the same. */
2208 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2216 if (a
->defined
!= b
->defined
)
2219 if ((a
->defined
& NTA_HASTYPE
) != 0
2220 && (a
->eltype
.type
!= b
->eltype
.type
2221 || a
->eltype
.size
!= b
->eltype
.size
))
2224 if ((a
->defined
& NTA_HASINDEX
) != 0
2225 && (a
->index
!= b
->index
))
2231 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2232 The base register is put in *PBASE.
2233 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2235 The register stride (minus one) is put in bit 4 of the return value.
2236 Bits [6:5] encode the list length (minus one).
2237 The type of the list elements is put in *ELTYPE, if non-NULL. */
2239 #define NEON_LANE(X) ((X) & 0xf)
2240 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2241 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2244 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2246 struct neon_type_el
*eltype
)
2253 int leading_brace
= 0;
2254 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2255 const char *const incr_error
= mve
? _("register stride must be 1") :
2256 _("register stride must be 1 or 2");
2257 const char *const type_error
= _("mismatched element/structure types in list");
2258 struct neon_typed_alias firsttype
;
2259 firsttype
.defined
= 0;
2260 firsttype
.eltype
.type
= NT_invtype
;
2261 firsttype
.eltype
.size
= -1;
2262 firsttype
.index
= -1;
2264 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2269 struct neon_typed_alias atype
;
2271 rtype
= REG_TYPE_MQ
;
2272 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2276 first_error (_(reg_expected_msgs
[rtype
]));
2283 if (rtype
== REG_TYPE_NQ
)
2289 else if (reg_incr
== -1)
2291 reg_incr
= getreg
- base_reg
;
2292 if (reg_incr
< 1 || reg_incr
> 2)
2294 first_error (_(incr_error
));
2298 else if (getreg
!= base_reg
+ reg_incr
* count
)
2300 first_error (_(incr_error
));
2304 if (! neon_alias_types_same (&atype
, &firsttype
))
2306 first_error (_(type_error
));
2310 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2314 struct neon_typed_alias htype
;
2315 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2317 lane
= NEON_INTERLEAVE_LANES
;
2318 else if (lane
!= NEON_INTERLEAVE_LANES
)
2320 first_error (_(type_error
));
2325 else if (reg_incr
!= 1)
2327 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2331 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2334 first_error (_(reg_expected_msgs
[rtype
]));
2337 if (! neon_alias_types_same (&htype
, &firsttype
))
2339 first_error (_(type_error
));
2342 count
+= hireg
+ dregs
- getreg
;
2346 /* If we're using Q registers, we can't use [] or [n] syntax. */
2347 if (rtype
== REG_TYPE_NQ
)
2353 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2357 else if (lane
!= atype
.index
)
2359 first_error (_(type_error
));
2363 else if (lane
== -1)
2364 lane
= NEON_INTERLEAVE_LANES
;
2365 else if (lane
!= NEON_INTERLEAVE_LANES
)
2367 first_error (_(type_error
));
2372 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2374 /* No lane set by [x]. We must be interleaving structures. */
2376 lane
= NEON_INTERLEAVE_LANES
;
2379 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2380 || (count
> 1 && reg_incr
== -1))
2382 first_error (_("error parsing element/structure list"));
2386 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2388 first_error (_("expected }"));
2396 *eltype
= firsttype
.eltype
;
2401 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2404 /* Parse an explicit relocation suffix on an expression. This is
2405 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2406 arm_reloc_hsh contains no entries, so this function can only
2407 succeed if there is no () after the word. Returns -1 on error,
2408 BFD_RELOC_UNUSED if there wasn't any suffix. */
2411 parse_reloc (char **str
)
2413 struct reloc_entry
*r
;
2417 return BFD_RELOC_UNUSED
;
2422 while (*q
&& *q
!= ')' && *q
!= ',')
2427 if ((r
= (struct reloc_entry
*)
2428 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2435 /* Directives: register aliases. */
2437 static struct reg_entry
*
2438 insert_reg_alias (char *str
, unsigned number
, int type
)
2440 struct reg_entry
*new_reg
;
2443 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2445 if (new_reg
->builtin
)
2446 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2448 /* Only warn about a redefinition if it's not defined as the
2450 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2451 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2456 name
= xstrdup (str
);
2457 new_reg
= XNEW (struct reg_entry
);
2459 new_reg
->name
= name
;
2460 new_reg
->number
= number
;
2461 new_reg
->type
= type
;
2462 new_reg
->builtin
= FALSE
;
2463 new_reg
->neon
= NULL
;
2465 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2472 insert_neon_reg_alias (char *str
, int number
, int type
,
2473 struct neon_typed_alias
*atype
)
2475 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2479 first_error (_("attempt to redefine typed alias"));
2485 reg
->neon
= XNEW (struct neon_typed_alias
);
2486 *reg
->neon
= *atype
;
2490 /* Look for the .req directive. This is of the form:
2492 new_register_name .req existing_register_name
2494 If we find one, or if it looks sufficiently like one that we want to
2495 handle any error here, return TRUE. Otherwise return FALSE. */
2498 create_register_alias (char * newname
, char *p
)
2500 struct reg_entry
*old
;
2501 char *oldname
, *nbuf
;
2504 /* The input scrubber ensures that whitespace after the mnemonic is
2505 collapsed to single spaces. */
2507 if (strncmp (oldname
, " .req ", 6) != 0)
2511 if (*oldname
== '\0')
2514 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2517 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2521 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2522 the desired alias name, and p points to its end. If not, then
2523 the desired alias name is in the global original_case_string. */
2524 #ifdef TC_CASE_SENSITIVE
2527 newname
= original_case_string
;
2528 nlen
= strlen (newname
);
2531 nbuf
= xmemdup0 (newname
, nlen
);
2533 /* Create aliases under the new name as stated; an all-lowercase
2534 version of the new name; and an all-uppercase version of the new
2536 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2538 for (p
= nbuf
; *p
; p
++)
2541 if (strncmp (nbuf
, newname
, nlen
))
2543 /* If this attempt to create an additional alias fails, do not bother
2544 trying to create the all-lower case alias. We will fail and issue
2545 a second, duplicate error message. This situation arises when the
2546 programmer does something like:
2549 The second .req creates the "Foo" alias but then fails to create
2550 the artificial FOO alias because it has already been created by the
2552 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2559 for (p
= nbuf
; *p
; p
++)
2562 if (strncmp (nbuf
, newname
, nlen
))
2563 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2570 /* Create a Neon typed/indexed register alias using directives, e.g.:
2575 These typed registers can be used instead of the types specified after the
2576 Neon mnemonic, so long as all operands given have types. Types can also be
2577 specified directly, e.g.:
2578 vadd d0.s32, d1.s32, d2.s32 */
2581 create_neon_reg_alias (char *newname
, char *p
)
2583 enum arm_reg_type basetype
;
2584 struct reg_entry
*basereg
;
2585 struct reg_entry mybasereg
;
2586 struct neon_type ntype
;
2587 struct neon_typed_alias typeinfo
;
2588 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2591 typeinfo
.defined
= 0;
2592 typeinfo
.eltype
.type
= NT_invtype
;
2593 typeinfo
.eltype
.size
= -1;
2594 typeinfo
.index
= -1;
2598 if (strncmp (p
, " .dn ", 5) == 0)
2599 basetype
= REG_TYPE_VFD
;
2600 else if (strncmp (p
, " .qn ", 5) == 0)
2601 basetype
= REG_TYPE_NQ
;
2610 basereg
= arm_reg_parse_multi (&p
);
2612 if (basereg
&& basereg
->type
!= basetype
)
2614 as_bad (_("bad type for register"));
2618 if (basereg
== NULL
)
2621 /* Try parsing as an integer. */
2622 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2623 if (exp
.X_op
!= O_constant
)
2625 as_bad (_("expression must be constant"));
2628 basereg
= &mybasereg
;
2629 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2635 typeinfo
= *basereg
->neon
;
2637 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2639 /* We got a type. */
2640 if (typeinfo
.defined
& NTA_HASTYPE
)
2642 as_bad (_("can't redefine the type of a register alias"));
2646 typeinfo
.defined
|= NTA_HASTYPE
;
2647 if (ntype
.elems
!= 1)
2649 as_bad (_("you must specify a single type only"));
2652 typeinfo
.eltype
= ntype
.el
[0];
2655 if (skip_past_char (&p
, '[') == SUCCESS
)
2658 /* We got a scalar index. */
2660 if (typeinfo
.defined
& NTA_HASINDEX
)
2662 as_bad (_("can't redefine the index of a scalar alias"));
2666 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2668 if (exp
.X_op
!= O_constant
)
2670 as_bad (_("scalar index must be constant"));
2674 typeinfo
.defined
|= NTA_HASINDEX
;
2675 typeinfo
.index
= exp
.X_add_number
;
2677 if (skip_past_char (&p
, ']') == FAIL
)
2679 as_bad (_("expecting ]"));
2684 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2685 the desired alias name, and p points to its end. If not, then
2686 the desired alias name is in the global original_case_string. */
2687 #ifdef TC_CASE_SENSITIVE
2688 namelen
= nameend
- newname
;
2690 newname
= original_case_string
;
2691 namelen
= strlen (newname
);
2694 namebuf
= xmemdup0 (newname
, namelen
);
2696 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2697 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2699 /* Insert name in all uppercase. */
2700 for (p
= namebuf
; *p
; p
++)
2703 if (strncmp (namebuf
, newname
, namelen
))
2704 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2705 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2707 /* Insert name in all lowercase. */
2708 for (p
= namebuf
; *p
; p
++)
2711 if (strncmp (namebuf
, newname
, namelen
))
2712 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2713 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2719 /* Should never be called, as .req goes between the alias and the
2720 register name, not at the beginning of the line. */
2723 s_req (int a ATTRIBUTE_UNUSED
)
2725 as_bad (_("invalid syntax for .req directive"));
2729 s_dn (int a ATTRIBUTE_UNUSED
)
2731 as_bad (_("invalid syntax for .dn directive"));
2735 s_qn (int a ATTRIBUTE_UNUSED
)
2737 as_bad (_("invalid syntax for .qn directive"));
2740 /* The .unreq directive deletes an alias which was previously defined
2741 by .req. For example:
2747 s_unreq (int a ATTRIBUTE_UNUSED
)
2752 name
= input_line_pointer
;
2754 while (*input_line_pointer
!= 0
2755 && *input_line_pointer
!= ' '
2756 && *input_line_pointer
!= '\n')
2757 ++input_line_pointer
;
2759 saved_char
= *input_line_pointer
;
2760 *input_line_pointer
= 0;
2763 as_bad (_("invalid syntax for .unreq directive"));
2766 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2770 as_bad (_("unknown register alias '%s'"), name
);
2771 else if (reg
->builtin
)
2772 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2779 hash_delete (arm_reg_hsh
, name
, FALSE
);
2780 free ((char *) reg
->name
);
2785 /* Also locate the all upper case and all lower case versions.
2786 Do not complain if we cannot find one or the other as it
2787 was probably deleted above. */
2789 nbuf
= strdup (name
);
2790 for (p
= nbuf
; *p
; p
++)
2792 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2795 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2796 free ((char *) reg
->name
);
2802 for (p
= nbuf
; *p
; p
++)
2804 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2807 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2808 free ((char *) reg
->name
);
2818 *input_line_pointer
= saved_char
;
2819 demand_empty_rest_of_line ();
2822 /* Directives: Instruction set selection. */
2825 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2826 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2827 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2828 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2830 /* Create a new mapping symbol for the transition to STATE. */
2833 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2836 const char * symname
;
2843 type
= BSF_NO_FLAGS
;
2847 type
= BSF_NO_FLAGS
;
2851 type
= BSF_NO_FLAGS
;
2857 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2858 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2863 THUMB_SET_FUNC (symbolP
, 0);
2864 ARM_SET_THUMB (symbolP
, 0);
2865 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2869 THUMB_SET_FUNC (symbolP
, 1);
2870 ARM_SET_THUMB (symbolP
, 1);
2871 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2879 /* Save the mapping symbols for future reference. Also check that
2880 we do not place two mapping symbols at the same offset within a
2881 frag. We'll handle overlap between frags in
2882 check_mapping_symbols.
2884 If .fill or other data filling directive generates zero sized data,
2885 the mapping symbol for the following code will have the same value
2886 as the one generated for the data filling directive. In this case,
2887 we replace the old symbol with the new one at the same address. */
2890 if (frag
->tc_frag_data
.first_map
!= NULL
)
2892 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2893 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2895 frag
->tc_frag_data
.first_map
= symbolP
;
2897 if (frag
->tc_frag_data
.last_map
!= NULL
)
2899 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2900 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2901 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2903 frag
->tc_frag_data
.last_map
= symbolP
;
2906 /* We must sometimes convert a region marked as code to data during
2907 code alignment, if an odd number of bytes have to be padded. The
2908 code mapping symbol is pushed to an aligned address. */
2911 insert_data_mapping_symbol (enum mstate state
,
2912 valueT value
, fragS
*frag
, offsetT bytes
)
2914 /* If there was already a mapping symbol, remove it. */
2915 if (frag
->tc_frag_data
.last_map
!= NULL
2916 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2918 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2922 know (frag
->tc_frag_data
.first_map
== symp
);
2923 frag
->tc_frag_data
.first_map
= NULL
;
2925 frag
->tc_frag_data
.last_map
= NULL
;
2926 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2929 make_mapping_symbol (MAP_DATA
, value
, frag
);
2930 make_mapping_symbol (state
, value
+ bytes
, frag
);
2933 static void mapping_state_2 (enum mstate state
, int max_chars
);
2935 /* Set the mapping state to STATE. Only call this when about to
2936 emit some STATE bytes to the file. */
2938 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2940 mapping_state (enum mstate state
)
2942 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2944 if (mapstate
== state
)
2945 /* The mapping symbol has already been emitted.
2946 There is nothing else to do. */
2949 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2951 All ARM instructions require 4-byte alignment.
2952 (Almost) all Thumb instructions require 2-byte alignment.
2954 When emitting instructions into any section, mark the section
2957 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2958 but themselves require 2-byte alignment; this applies to some
2959 PC- relative forms. However, these cases will involve implicit
2960 literal pool generation or an explicit .align >=2, both of
2961 which will cause the section to me marked with sufficient
2962 alignment. Thus, we don't handle those cases here. */
2963 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2965 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2966 /* This case will be evaluated later. */
2969 mapping_state_2 (state
, 0);
2972 /* Same as mapping_state, but MAX_CHARS bytes have already been
2973 allocated. Put the mapping symbol that far back. */
2976 mapping_state_2 (enum mstate state
, int max_chars
)
2978 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2980 if (!SEG_NORMAL (now_seg
))
2983 if (mapstate
== state
)
2984 /* The mapping symbol has already been emitted.
2985 There is nothing else to do. */
2988 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2989 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2991 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2992 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2995 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2998 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2999 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3003 #define mapping_state(x) ((void)0)
3004 #define mapping_state_2(x, y) ((void)0)
3007 /* Find the real, Thumb encoded start of a Thumb function. */
3011 find_real_start (symbolS
* symbolP
)
3014 const char * name
= S_GET_NAME (symbolP
);
3015 symbolS
* new_target
;
3017 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3018 #define STUB_NAME ".real_start_of"
3023 /* The compiler may generate BL instructions to local labels because
3024 it needs to perform a branch to a far away location. These labels
3025 do not have a corresponding ".real_start_of" label. We check
3026 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3027 the ".real_start_of" convention for nonlocal branches. */
3028 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3031 real_start
= concat (STUB_NAME
, name
, NULL
);
3032 new_target
= symbol_find (real_start
);
3035 if (new_target
== NULL
)
3037 as_warn (_("Failed to find real start of function: %s\n"), name
);
3038 new_target
= symbolP
;
3046 opcode_select (int width
)
3053 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3054 as_bad (_("selected processor does not support THUMB opcodes"));
3057 /* No need to force the alignment, since we will have been
3058 coming from ARM mode, which is word-aligned. */
3059 record_alignment (now_seg
, 1);
3066 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3067 as_bad (_("selected processor does not support ARM opcodes"));
3072 frag_align (2, 0, 0);
3074 record_alignment (now_seg
, 1);
3079 as_bad (_("invalid instruction size selected (%d)"), width
);
3084 s_arm (int ignore ATTRIBUTE_UNUSED
)
3087 demand_empty_rest_of_line ();
3091 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3094 demand_empty_rest_of_line ();
3098 s_code (int unused ATTRIBUTE_UNUSED
)
3102 temp
= get_absolute_expression ();
3107 opcode_select (temp
);
3111 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3116 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3118 /* If we are not already in thumb mode go into it, EVEN if
3119 the target processor does not support thumb instructions.
3120 This is used by gcc/config/arm/lib1funcs.asm for example
3121 to compile interworking support functions even if the
3122 target processor should not support interworking. */
3126 record_alignment (now_seg
, 1);
3129 demand_empty_rest_of_line ();
3133 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3137 /* The following label is the name/address of the start of a Thumb function.
3138 We need to know this for the interworking support. */
3139 label_is_thumb_function_name
= TRUE
;
3142 /* Perform a .set directive, but also mark the alias as
3143 being a thumb function. */
3146 s_thumb_set (int equiv
)
3148 /* XXX the following is a duplicate of the code for s_set() in read.c
3149 We cannot just call that code as we need to get at the symbol that
3156 /* Especial apologies for the random logic:
3157 This just grew, and could be parsed much more simply!
3159 delim
= get_symbol_name (& name
);
3160 end_name
= input_line_pointer
;
3161 (void) restore_line_pointer (delim
);
3163 if (*input_line_pointer
!= ',')
3166 as_bad (_("expected comma after name \"%s\""), name
);
3168 ignore_rest_of_line ();
3172 input_line_pointer
++;
3175 if (name
[0] == '.' && name
[1] == '\0')
3177 /* XXX - this should not happen to .thumb_set. */
3181 if ((symbolP
= symbol_find (name
)) == NULL
3182 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3185 /* When doing symbol listings, play games with dummy fragments living
3186 outside the normal fragment chain to record the file and line info
3188 if (listing
& LISTING_SYMBOLS
)
3190 extern struct list_info_struct
* listing_tail
;
3191 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3193 memset (dummy_frag
, 0, sizeof (fragS
));
3194 dummy_frag
->fr_type
= rs_fill
;
3195 dummy_frag
->line
= listing_tail
;
3196 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3197 dummy_frag
->fr_symbol
= symbolP
;
3201 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3204 /* "set" symbols are local unless otherwise specified. */
3205 SF_SET_LOCAL (symbolP
);
3206 #endif /* OBJ_COFF */
3207 } /* Make a new symbol. */
3209 symbol_table_insert (symbolP
);
3214 && S_IS_DEFINED (symbolP
)
3215 && S_GET_SEGMENT (symbolP
) != reg_section
)
3216 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3218 pseudo_set (symbolP
);
3220 demand_empty_rest_of_line ();
3222 /* XXX Now we come to the Thumb specific bit of code. */
3224 THUMB_SET_FUNC (symbolP
, 1);
3225 ARM_SET_THUMB (symbolP
, 1);
3226 #if defined OBJ_ELF || defined OBJ_COFF
3227 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3231 /* Directives: Mode selection. */
3233 /* .syntax [unified|divided] - choose the new unified syntax
3234 (same for Arm and Thumb encoding, modulo slight differences in what
3235 can be represented) or the old divergent syntax for each mode. */
3237 s_syntax (int unused ATTRIBUTE_UNUSED
)
3241 delim
= get_symbol_name (& name
);
3243 if (!strcasecmp (name
, "unified"))
3244 unified_syntax
= TRUE
;
3245 else if (!strcasecmp (name
, "divided"))
3246 unified_syntax
= FALSE
;
3249 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3252 (void) restore_line_pointer (delim
);
3253 demand_empty_rest_of_line ();
3256 /* Directives: sectioning and alignment. */
3259 s_bss (int ignore ATTRIBUTE_UNUSED
)
3261 /* We don't support putting frags in the BSS segment, we fake it by
3262 marking in_bss, then looking at s_skip for clues. */
3263 subseg_set (bss_section
, 0);
3264 demand_empty_rest_of_line ();
3266 #ifdef md_elf_section_change_hook
3267 md_elf_section_change_hook ();
3272 s_even (int ignore ATTRIBUTE_UNUSED
)
3274 /* Never make frag if expect extra pass. */
3276 frag_align (1, 0, 0);
3278 record_alignment (now_seg
, 1);
3280 demand_empty_rest_of_line ();
3283 /* Directives: CodeComposer Studio. */
3285 /* .ref (for CodeComposer Studio syntax only). */
3287 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3289 if (codecomposer_syntax
)
3290 ignore_rest_of_line ();
3292 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3295 /* If name is not NULL, then it is used for marking the beginning of a
3296 function, whereas if it is NULL then it means the function end. */
3298 asmfunc_debug (const char * name
)
3300 static const char * last_name
= NULL
;
3304 gas_assert (last_name
== NULL
);
3307 if (debug_type
== DEBUG_STABS
)
3308 stabs_generate_asm_func (name
, name
);
3312 gas_assert (last_name
!= NULL
);
3314 if (debug_type
== DEBUG_STABS
)
3315 stabs_generate_asm_endfunc (last_name
, last_name
);
3322 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3324 if (codecomposer_syntax
)
3326 switch (asmfunc_state
)
3328 case OUTSIDE_ASMFUNC
:
3329 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3332 case WAITING_ASMFUNC_NAME
:
3333 as_bad (_(".asmfunc repeated."));
3336 case WAITING_ENDASMFUNC
:
3337 as_bad (_(".asmfunc without function."));
3340 demand_empty_rest_of_line ();
3343 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3347 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3349 if (codecomposer_syntax
)
3351 switch (asmfunc_state
)
3353 case OUTSIDE_ASMFUNC
:
3354 as_bad (_(".endasmfunc without a .asmfunc."));
3357 case WAITING_ASMFUNC_NAME
:
3358 as_bad (_(".endasmfunc without function."));
3361 case WAITING_ENDASMFUNC
:
3362 asmfunc_state
= OUTSIDE_ASMFUNC
;
3363 asmfunc_debug (NULL
);
3366 demand_empty_rest_of_line ();
3369 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3373 s_ccs_def (int name
)
3375 if (codecomposer_syntax
)
3378 as_bad (_(".def pseudo-op only available with -mccs flag."));
3381 /* Directives: Literal pools. */
3383 static literal_pool
*
3384 find_literal_pool (void)
3386 literal_pool
* pool
;
3388 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3390 if (pool
->section
== now_seg
3391 && pool
->sub_section
== now_subseg
)
3398 static literal_pool
*
3399 find_or_make_literal_pool (void)
3401 /* Next literal pool ID number. */
3402 static unsigned int latest_pool_num
= 1;
3403 literal_pool
* pool
;
3405 pool
= find_literal_pool ();
3409 /* Create a new pool. */
3410 pool
= XNEW (literal_pool
);
3414 pool
->next_free_entry
= 0;
3415 pool
->section
= now_seg
;
3416 pool
->sub_section
= now_subseg
;
3417 pool
->next
= list_of_pools
;
3418 pool
->symbol
= NULL
;
3419 pool
->alignment
= 2;
3421 /* Add it to the list. */
3422 list_of_pools
= pool
;
3425 /* New pools, and emptied pools, will have a NULL symbol. */
3426 if (pool
->symbol
== NULL
)
3428 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3429 (valueT
) 0, &zero_address_frag
);
3430 pool
->id
= latest_pool_num
++;
3437 /* Add the literal in the global 'inst'
3438 structure to the relevant literal pool. */
3441 add_to_lit_pool (unsigned int nbytes
)
3443 #define PADDING_SLOT 0x1
3444 #define LIT_ENTRY_SIZE_MASK 0xFF
3445 literal_pool
* pool
;
3446 unsigned int entry
, pool_size
= 0;
3447 bfd_boolean padding_slot_p
= FALSE
;
3453 imm1
= inst
.operands
[1].imm
;
3454 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3455 : inst
.relocs
[0].exp
.X_unsigned
? 0
3456 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3457 if (target_big_endian
)
3460 imm2
= inst
.operands
[1].imm
;
3464 pool
= find_or_make_literal_pool ();
3466 /* Check if this literal value is already in the pool. */
3467 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3471 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3472 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3473 && (pool
->literals
[entry
].X_add_number
3474 == inst
.relocs
[0].exp
.X_add_number
)
3475 && (pool
->literals
[entry
].X_md
== nbytes
)
3476 && (pool
->literals
[entry
].X_unsigned
3477 == inst
.relocs
[0].exp
.X_unsigned
))
3480 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3481 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3482 && (pool
->literals
[entry
].X_add_number
3483 == inst
.relocs
[0].exp
.X_add_number
)
3484 && (pool
->literals
[entry
].X_add_symbol
3485 == inst
.relocs
[0].exp
.X_add_symbol
)
3486 && (pool
->literals
[entry
].X_op_symbol
3487 == inst
.relocs
[0].exp
.X_op_symbol
)
3488 && (pool
->literals
[entry
].X_md
== nbytes
))
3491 else if ((nbytes
== 8)
3492 && !(pool_size
& 0x7)
3493 && ((entry
+ 1) != pool
->next_free_entry
)
3494 && (pool
->literals
[entry
].X_op
== O_constant
)
3495 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3496 && (pool
->literals
[entry
].X_unsigned
3497 == inst
.relocs
[0].exp
.X_unsigned
)
3498 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3499 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3500 && (pool
->literals
[entry
+ 1].X_unsigned
3501 == inst
.relocs
[0].exp
.X_unsigned
))
3504 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3505 if (padding_slot_p
&& (nbytes
== 4))
3511 /* Do we need to create a new entry? */
3512 if (entry
== pool
->next_free_entry
)
3514 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3516 inst
.error
= _("literal pool overflow");
3522 /* For 8-byte entries, we align to an 8-byte boundary,
3523 and split it into two 4-byte entries, because on 32-bit
3524 host, 8-byte constants are treated as big num, thus
3525 saved in "generic_bignum" which will be overwritten
3526 by later assignments.
3528 We also need to make sure there is enough space for
3531 We also check to make sure the literal operand is a
3533 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3534 || inst
.relocs
[0].exp
.X_op
== O_big
))
3536 inst
.error
= _("invalid type for literal pool");
3539 else if (pool_size
& 0x7)
3541 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3543 inst
.error
= _("literal pool overflow");
3547 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3548 pool
->literals
[entry
].X_op
= O_constant
;
3549 pool
->literals
[entry
].X_add_number
= 0;
3550 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3551 pool
->next_free_entry
+= 1;
3554 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3556 inst
.error
= _("literal pool overflow");
3560 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3561 pool
->literals
[entry
].X_op
= O_constant
;
3562 pool
->literals
[entry
].X_add_number
= imm1
;
3563 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3564 pool
->literals
[entry
++].X_md
= 4;
3565 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3566 pool
->literals
[entry
].X_op
= O_constant
;
3567 pool
->literals
[entry
].X_add_number
= imm2
;
3568 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3569 pool
->literals
[entry
].X_md
= 4;
3570 pool
->alignment
= 3;
3571 pool
->next_free_entry
+= 1;
3575 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3576 pool
->literals
[entry
].X_md
= 4;
3580 /* PR ld/12974: Record the location of the first source line to reference
3581 this entry in the literal pool. If it turns out during linking that the
3582 symbol does not exist we will be able to give an accurate line number for
3583 the (first use of the) missing reference. */
3584 if (debug_type
== DEBUG_DWARF2
)
3585 dwarf2_where (pool
->locs
+ entry
);
3587 pool
->next_free_entry
+= 1;
3589 else if (padding_slot_p
)
3591 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3592 pool
->literals
[entry
].X_md
= nbytes
;
3595 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3596 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3597 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3603 tc_start_label_without_colon (void)
3605 bfd_boolean ret
= TRUE
;
3607 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3609 const char *label
= input_line_pointer
;
3611 while (!is_end_of_line
[(int) label
[-1]])
3616 as_bad (_("Invalid label '%s'"), label
);
3620 asmfunc_debug (label
);
3622 asmfunc_state
= WAITING_ENDASMFUNC
;
3628 /* Can't use symbol_new here, so have to create a symbol and then at
3629 a later date assign it a value. That's what these functions do. */
3632 symbol_locate (symbolS
* symbolP
,
3633 const char * name
, /* It is copied, the caller can modify. */
3634 segT segment
, /* Segment identifier (SEG_<something>). */
3635 valueT valu
, /* Symbol value. */
3636 fragS
* frag
) /* Associated fragment. */
3639 char * preserved_copy_of_name
;
3641 name_length
= strlen (name
) + 1; /* +1 for \0. */
3642 obstack_grow (¬es
, name
, name_length
);
3643 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3645 #ifdef tc_canonicalize_symbol_name
3646 preserved_copy_of_name
=
3647 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3650 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3652 S_SET_SEGMENT (symbolP
, segment
);
3653 S_SET_VALUE (symbolP
, valu
);
3654 symbol_clear_list_pointers (symbolP
);
3656 symbol_set_frag (symbolP
, frag
);
3658 /* Link to end of symbol chain. */
3660 extern int symbol_table_frozen
;
3662 if (symbol_table_frozen
)
3666 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3668 obj_symbol_new_hook (symbolP
);
3670 #ifdef tc_symbol_new_hook
3671 tc_symbol_new_hook (symbolP
);
3675 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3676 #endif /* DEBUG_SYMS */
3680 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3683 literal_pool
* pool
;
3686 pool
= find_literal_pool ();
3688 || pool
->symbol
== NULL
3689 || pool
->next_free_entry
== 0)
3692 /* Align pool as you have word accesses.
3693 Only make a frag if we have to. */
3695 frag_align (pool
->alignment
, 0, 0);
3697 record_alignment (now_seg
, 2);
3700 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3701 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3703 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3705 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3706 (valueT
) frag_now_fix (), frag_now
);
3707 symbol_table_insert (pool
->symbol
);
3709 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3711 #if defined OBJ_COFF || defined OBJ_ELF
3712 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3715 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3718 if (debug_type
== DEBUG_DWARF2
)
3719 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3721 /* First output the expression in the instruction to the pool. */
3722 emit_expr (&(pool
->literals
[entry
]),
3723 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3726 /* Mark the pool as empty. */
3727 pool
->next_free_entry
= 0;
3728 pool
->symbol
= NULL
;
3732 /* Forward declarations for functions below, in the MD interface
3734 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3735 static valueT
create_unwind_entry (int);
3736 static void start_unwind_section (const segT
, int);
3737 static void add_unwind_opcode (valueT
, int);
3738 static void flush_pending_unwind (void);
3740 /* Directives: Data. */
3743 s_arm_elf_cons (int nbytes
)
3747 #ifdef md_flush_pending_output
3748 md_flush_pending_output ();
3751 if (is_it_end_of_statement ())
3753 demand_empty_rest_of_line ();
3757 #ifdef md_cons_align
3758 md_cons_align (nbytes
);
3761 mapping_state (MAP_DATA
);
3765 char *base
= input_line_pointer
;
3769 if (exp
.X_op
!= O_symbol
)
3770 emit_expr (&exp
, (unsigned int) nbytes
);
3773 char *before_reloc
= input_line_pointer
;
3774 reloc
= parse_reloc (&input_line_pointer
);
3777 as_bad (_("unrecognized relocation suffix"));
3778 ignore_rest_of_line ();
3781 else if (reloc
== BFD_RELOC_UNUSED
)
3782 emit_expr (&exp
, (unsigned int) nbytes
);
3785 reloc_howto_type
*howto
= (reloc_howto_type
*)
3786 bfd_reloc_type_lookup (stdoutput
,
3787 (bfd_reloc_code_real_type
) reloc
);
3788 int size
= bfd_get_reloc_size (howto
);
3790 if (reloc
== BFD_RELOC_ARM_PLT32
)
3792 as_bad (_("(plt) is only valid on branch targets"));
3793 reloc
= BFD_RELOC_UNUSED
;
3798 as_bad (ngettext ("%s relocations do not fit in %d byte",
3799 "%s relocations do not fit in %d bytes",
3801 howto
->name
, nbytes
);
3804 /* We've parsed an expression stopping at O_symbol.
3805 But there may be more expression left now that we
3806 have parsed the relocation marker. Parse it again.
3807 XXX Surely there is a cleaner way to do this. */
3808 char *p
= input_line_pointer
;
3810 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3812 memcpy (save_buf
, base
, input_line_pointer
- base
);
3813 memmove (base
+ (input_line_pointer
- before_reloc
),
3814 base
, before_reloc
- base
);
3816 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3818 memcpy (base
, save_buf
, p
- base
);
3820 offset
= nbytes
- size
;
3821 p
= frag_more (nbytes
);
3822 memset (p
, 0, nbytes
);
3823 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3824 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3830 while (*input_line_pointer
++ == ',');
3832 /* Put terminator back into stream. */
3833 input_line_pointer
--;
3834 demand_empty_rest_of_line ();
3837 /* Emit an expression containing a 32-bit thumb instruction.
3838 Implementation based on put_thumb32_insn. */
3841 emit_thumb32_expr (expressionS
* exp
)
3843 expressionS exp_high
= *exp
;
3845 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3846 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3847 exp
->X_add_number
&= 0xffff;
3848 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3851 /* Guess the instruction size based on the opcode. */
3854 thumb_insn_size (int opcode
)
3856 if ((unsigned int) opcode
< 0xe800u
)
3858 else if ((unsigned int) opcode
>= 0xe8000000u
)
3865 emit_insn (expressionS
*exp
, int nbytes
)
3869 if (exp
->X_op
== O_constant
)
3874 size
= thumb_insn_size (exp
->X_add_number
);
3878 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3880 as_bad (_(".inst.n operand too big. "\
3881 "Use .inst.w instead"));
3886 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3887 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3889 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3891 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3892 emit_thumb32_expr (exp
);
3894 emit_expr (exp
, (unsigned int) size
);
3896 it_fsm_post_encode ();
3900 as_bad (_("cannot determine Thumb instruction size. " \
3901 "Use .inst.n/.inst.w instead"));
3904 as_bad (_("constant expression required"));
3909 /* Like s_arm_elf_cons but do not use md_cons_align and
3910 set the mapping state to MAP_ARM/MAP_THUMB. */
3913 s_arm_elf_inst (int nbytes
)
3915 if (is_it_end_of_statement ())
3917 demand_empty_rest_of_line ();
3921 /* Calling mapping_state () here will not change ARM/THUMB,
3922 but will ensure not to be in DATA state. */
3925 mapping_state (MAP_THUMB
);
3930 as_bad (_("width suffixes are invalid in ARM mode"));
3931 ignore_rest_of_line ();
3937 mapping_state (MAP_ARM
);
3946 if (! emit_insn (& exp
, nbytes
))
3948 ignore_rest_of_line ();
3952 while (*input_line_pointer
++ == ',');
3954 /* Put terminator back into stream. */
3955 input_line_pointer
--;
3956 demand_empty_rest_of_line ();
3959 /* Parse a .rel31 directive. */
3962 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3969 if (*input_line_pointer
== '1')
3970 highbit
= 0x80000000;
3971 else if (*input_line_pointer
!= '0')
3972 as_bad (_("expected 0 or 1"));
3974 input_line_pointer
++;
3975 if (*input_line_pointer
!= ',')
3976 as_bad (_("missing comma"));
3977 input_line_pointer
++;
3979 #ifdef md_flush_pending_output
3980 md_flush_pending_output ();
3983 #ifdef md_cons_align
3987 mapping_state (MAP_DATA
);
3992 md_number_to_chars (p
, highbit
, 4);
3993 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3994 BFD_RELOC_ARM_PREL31
);
3996 demand_empty_rest_of_line ();
3999 /* Directives: AEABI stack-unwind tables. */
4001 /* Parse an unwind_fnstart directive. Simply records the current location. */
4004 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4006 demand_empty_rest_of_line ();
4007 if (unwind
.proc_start
)
4009 as_bad (_("duplicate .fnstart directive"));
4013 /* Mark the start of the function. */
4014 unwind
.proc_start
= expr_build_dot ();
4016 /* Reset the rest of the unwind info. */
4017 unwind
.opcode_count
= 0;
4018 unwind
.table_entry
= NULL
;
4019 unwind
.personality_routine
= NULL
;
4020 unwind
.personality_index
= -1;
4021 unwind
.frame_size
= 0;
4022 unwind
.fp_offset
= 0;
4023 unwind
.fp_reg
= REG_SP
;
4025 unwind
.sp_restored
= 0;
4029 /* Parse a handlerdata directive. Creates the exception handling table entry
4030 for the function. */
4033 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4035 demand_empty_rest_of_line ();
4036 if (!unwind
.proc_start
)
4037 as_bad (MISSING_FNSTART
);
4039 if (unwind
.table_entry
)
4040 as_bad (_("duplicate .handlerdata directive"));
4042 create_unwind_entry (1);
4045 /* Parse an unwind_fnend directive. Generates the index table entry. */
4048 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4053 unsigned int marked_pr_dependency
;
4055 demand_empty_rest_of_line ();
4057 if (!unwind
.proc_start
)
4059 as_bad (_(".fnend directive without .fnstart"));
4063 /* Add eh table entry. */
4064 if (unwind
.table_entry
== NULL
)
4065 val
= create_unwind_entry (0);
4069 /* Add index table entry. This is two words. */
4070 start_unwind_section (unwind
.saved_seg
, 1);
4071 frag_align (2, 0, 0);
4072 record_alignment (now_seg
, 2);
4074 ptr
= frag_more (8);
4076 where
= frag_now_fix () - 8;
4078 /* Self relative offset of the function start. */
4079 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4080 BFD_RELOC_ARM_PREL31
);
4082 /* Indicate dependency on EHABI-defined personality routines to the
4083 linker, if it hasn't been done already. */
4084 marked_pr_dependency
4085 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4086 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4087 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4089 static const char *const name
[] =
4091 "__aeabi_unwind_cpp_pr0",
4092 "__aeabi_unwind_cpp_pr1",
4093 "__aeabi_unwind_cpp_pr2"
4095 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4096 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4097 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4098 |= 1 << unwind
.personality_index
;
4102 /* Inline exception table entry. */
4103 md_number_to_chars (ptr
+ 4, val
, 4);
4105 /* Self relative offset of the table entry. */
4106 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4107 BFD_RELOC_ARM_PREL31
);
4109 /* Restore the original section. */
4110 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4112 unwind
.proc_start
= NULL
;
4116 /* Parse an unwind_cantunwind directive. */
4119 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4121 demand_empty_rest_of_line ();
4122 if (!unwind
.proc_start
)
4123 as_bad (MISSING_FNSTART
);
4125 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4126 as_bad (_("personality routine specified for cantunwind frame"));
4128 unwind
.personality_index
= -2;
4132 /* Parse a personalityindex directive. */
4135 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4139 if (!unwind
.proc_start
)
4140 as_bad (MISSING_FNSTART
);
4142 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4143 as_bad (_("duplicate .personalityindex directive"));
4147 if (exp
.X_op
!= O_constant
4148 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4150 as_bad (_("bad personality routine number"));
4151 ignore_rest_of_line ();
4155 unwind
.personality_index
= exp
.X_add_number
;
4157 demand_empty_rest_of_line ();
4161 /* Parse a personality directive. */
4164 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4168 if (!unwind
.proc_start
)
4169 as_bad (MISSING_FNSTART
);
4171 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4172 as_bad (_("duplicate .personality directive"));
4174 c
= get_symbol_name (& name
);
4175 p
= input_line_pointer
;
4177 ++ input_line_pointer
;
4178 unwind
.personality_routine
= symbol_find_or_make (name
);
4180 demand_empty_rest_of_line ();
4184 /* Parse a directive saving core registers. */
4187 s_arm_unwind_save_core (void)
4193 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4196 as_bad (_("expected register list"));
4197 ignore_rest_of_line ();
4201 demand_empty_rest_of_line ();
4203 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4204 into .unwind_save {..., sp...}. We aren't bothered about the value of
4205 ip because it is clobbered by calls. */
4206 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4207 && (range
& 0x3000) == 0x1000)
4209 unwind
.opcode_count
--;
4210 unwind
.sp_restored
= 0;
4211 range
= (range
| 0x2000) & ~0x1000;
4212 unwind
.pending_offset
= 0;
4218 /* See if we can use the short opcodes. These pop a block of up to 8
4219 registers starting with r4, plus maybe r14. */
4220 for (n
= 0; n
< 8; n
++)
4222 /* Break at the first non-saved register. */
4223 if ((range
& (1 << (n
+ 4))) == 0)
4226 /* See if there are any other bits set. */
4227 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4229 /* Use the long form. */
4230 op
= 0x8000 | ((range
>> 4) & 0xfff);
4231 add_unwind_opcode (op
, 2);
4235 /* Use the short form. */
4237 op
= 0xa8; /* Pop r14. */
4239 op
= 0xa0; /* Do not pop r14. */
4241 add_unwind_opcode (op
, 1);
4248 op
= 0xb100 | (range
& 0xf);
4249 add_unwind_opcode (op
, 2);
4252 /* Record the number of bytes pushed. */
4253 for (n
= 0; n
< 16; n
++)
4255 if (range
& (1 << n
))
4256 unwind
.frame_size
+= 4;
4261 /* Parse a directive saving FPA registers. */
4264 s_arm_unwind_save_fpa (int reg
)
4270 /* Get Number of registers to transfer. */
4271 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4274 exp
.X_op
= O_illegal
;
4276 if (exp
.X_op
!= O_constant
)
4278 as_bad (_("expected , <constant>"));
4279 ignore_rest_of_line ();
4283 num_regs
= exp
.X_add_number
;
4285 if (num_regs
< 1 || num_regs
> 4)
4287 as_bad (_("number of registers must be in the range [1:4]"));
4288 ignore_rest_of_line ();
4292 demand_empty_rest_of_line ();
4297 op
= 0xb4 | (num_regs
- 1);
4298 add_unwind_opcode (op
, 1);
4303 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4304 add_unwind_opcode (op
, 2);
4306 unwind
.frame_size
+= num_regs
* 12;
4310 /* Parse a directive saving VFP registers for ARMv6 and above. */
4313 s_arm_unwind_save_vfp_armv6 (void)
4318 int num_vfpv3_regs
= 0;
4319 int num_regs_below_16
;
4320 bfd_boolean partial_match
;
4322 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4326 as_bad (_("expected register list"));
4327 ignore_rest_of_line ();
4331 demand_empty_rest_of_line ();
4333 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4334 than FSTMX/FLDMX-style ones). */
4336 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4338 num_vfpv3_regs
= count
;
4339 else if (start
+ count
> 16)
4340 num_vfpv3_regs
= start
+ count
- 16;
4342 if (num_vfpv3_regs
> 0)
4344 int start_offset
= start
> 16 ? start
- 16 : 0;
4345 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4346 add_unwind_opcode (op
, 2);
4349 /* Generate opcode for registers numbered in the range 0 .. 15. */
4350 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4351 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4352 if (num_regs_below_16
> 0)
4354 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4355 add_unwind_opcode (op
, 2);
4358 unwind
.frame_size
+= count
* 8;
4362 /* Parse a directive saving VFP registers for pre-ARMv6. */
4365 s_arm_unwind_save_vfp (void)
4370 bfd_boolean partial_match
;
4372 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4376 as_bad (_("expected register list"));
4377 ignore_rest_of_line ();
4381 demand_empty_rest_of_line ();
4386 op
= 0xb8 | (count
- 1);
4387 add_unwind_opcode (op
, 1);
4392 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4393 add_unwind_opcode (op
, 2);
4395 unwind
.frame_size
+= count
* 8 + 4;
4399 /* Parse a directive saving iWMMXt data registers. */
4402 s_arm_unwind_save_mmxwr (void)
4410 if (*input_line_pointer
== '{')
4411 input_line_pointer
++;
4415 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4419 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4424 as_tsktsk (_("register list not in ascending order"));
4427 if (*input_line_pointer
== '-')
4429 input_line_pointer
++;
4430 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4433 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4436 else if (reg
>= hi_reg
)
4438 as_bad (_("bad register range"));
4441 for (; reg
< hi_reg
; reg
++)
4445 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4447 skip_past_char (&input_line_pointer
, '}');
4449 demand_empty_rest_of_line ();
4451 /* Generate any deferred opcodes because we're going to be looking at
4453 flush_pending_unwind ();
4455 for (i
= 0; i
< 16; i
++)
4457 if (mask
& (1 << i
))
4458 unwind
.frame_size
+= 8;
4461 /* Attempt to combine with a previous opcode. We do this because gcc
4462 likes to output separate unwind directives for a single block of
4464 if (unwind
.opcode_count
> 0)
4466 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4467 if ((i
& 0xf8) == 0xc0)
4470 /* Only merge if the blocks are contiguous. */
4473 if ((mask
& 0xfe00) == (1 << 9))
4475 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4476 unwind
.opcode_count
--;
4479 else if (i
== 6 && unwind
.opcode_count
>= 2)
4481 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4485 op
= 0xffff << (reg
- 1);
4487 && ((mask
& op
) == (1u << (reg
- 1))))
4489 op
= (1 << (reg
+ i
+ 1)) - 1;
4490 op
&= ~((1 << reg
) - 1);
4492 unwind
.opcode_count
-= 2;
4499 /* We want to generate opcodes in the order the registers have been
4500 saved, ie. descending order. */
4501 for (reg
= 15; reg
>= -1; reg
--)
4503 /* Save registers in blocks. */
4505 || !(mask
& (1 << reg
)))
4507 /* We found an unsaved reg. Generate opcodes to save the
4514 op
= 0xc0 | (hi_reg
- 10);
4515 add_unwind_opcode (op
, 1);
4520 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4521 add_unwind_opcode (op
, 2);
4530 ignore_rest_of_line ();
4534 s_arm_unwind_save_mmxwcg (void)
4541 if (*input_line_pointer
== '{')
4542 input_line_pointer
++;
4544 skip_whitespace (input_line_pointer
);
4548 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4552 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4558 as_tsktsk (_("register list not in ascending order"));
4561 if (*input_line_pointer
== '-')
4563 input_line_pointer
++;
4564 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4567 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4570 else if (reg
>= hi_reg
)
4572 as_bad (_("bad register range"));
4575 for (; reg
< hi_reg
; reg
++)
4579 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4581 skip_past_char (&input_line_pointer
, '}');
4583 demand_empty_rest_of_line ();
4585 /* Generate any deferred opcodes because we're going to be looking at
4587 flush_pending_unwind ();
4589 for (reg
= 0; reg
< 16; reg
++)
4591 if (mask
& (1 << reg
))
4592 unwind
.frame_size
+= 4;
4595 add_unwind_opcode (op
, 2);
4598 ignore_rest_of_line ();
4602 /* Parse an unwind_save directive.
4603 If the argument is non-zero, this is a .vsave directive. */
4606 s_arm_unwind_save (int arch_v6
)
4609 struct reg_entry
*reg
;
4610 bfd_boolean had_brace
= FALSE
;
4612 if (!unwind
.proc_start
)
4613 as_bad (MISSING_FNSTART
);
4615 /* Figure out what sort of save we have. */
4616 peek
= input_line_pointer
;
4624 reg
= arm_reg_parse_multi (&peek
);
4628 as_bad (_("register expected"));
4629 ignore_rest_of_line ();
4638 as_bad (_("FPA .unwind_save does not take a register list"));
4639 ignore_rest_of_line ();
4642 input_line_pointer
= peek
;
4643 s_arm_unwind_save_fpa (reg
->number
);
4647 s_arm_unwind_save_core ();
4652 s_arm_unwind_save_vfp_armv6 ();
4654 s_arm_unwind_save_vfp ();
4657 case REG_TYPE_MMXWR
:
4658 s_arm_unwind_save_mmxwr ();
4661 case REG_TYPE_MMXWCG
:
4662 s_arm_unwind_save_mmxwcg ();
4666 as_bad (_(".unwind_save does not support this kind of register"));
4667 ignore_rest_of_line ();
4672 /* Parse an unwind_movsp directive. */
4675 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4681 if (!unwind
.proc_start
)
4682 as_bad (MISSING_FNSTART
);
4684 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4687 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4688 ignore_rest_of_line ();
4692 /* Optional constant. */
4693 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4695 if (immediate_for_directive (&offset
) == FAIL
)
4701 demand_empty_rest_of_line ();
4703 if (reg
== REG_SP
|| reg
== REG_PC
)
4705 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4709 if (unwind
.fp_reg
!= REG_SP
)
4710 as_bad (_("unexpected .unwind_movsp directive"));
4712 /* Generate opcode to restore the value. */
4714 add_unwind_opcode (op
, 1);
4716 /* Record the information for later. */
4717 unwind
.fp_reg
= reg
;
4718 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4719 unwind
.sp_restored
= 1;
4722 /* Parse an unwind_pad directive. */
4725 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4729 if (!unwind
.proc_start
)
4730 as_bad (MISSING_FNSTART
);
4732 if (immediate_for_directive (&offset
) == FAIL
)
4737 as_bad (_("stack increment must be multiple of 4"));
4738 ignore_rest_of_line ();
4742 /* Don't generate any opcodes, just record the details for later. */
4743 unwind
.frame_size
+= offset
;
4744 unwind
.pending_offset
+= offset
;
4746 demand_empty_rest_of_line ();
4749 /* Parse an unwind_setfp directive. */
4752 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4758 if (!unwind
.proc_start
)
4759 as_bad (MISSING_FNSTART
);
4761 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4762 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4765 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4767 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4769 as_bad (_("expected <reg>, <reg>"));
4770 ignore_rest_of_line ();
4774 /* Optional constant. */
4775 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4777 if (immediate_for_directive (&offset
) == FAIL
)
4783 demand_empty_rest_of_line ();
4785 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4787 as_bad (_("register must be either sp or set by a previous"
4788 "unwind_movsp directive"));
4792 /* Don't generate any opcodes, just record the information for later. */
4793 unwind
.fp_reg
= fp_reg
;
4795 if (sp_reg
== REG_SP
)
4796 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4798 unwind
.fp_offset
-= offset
;
4801 /* Parse an unwind_raw directive. */
4804 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4807 /* This is an arbitrary limit. */
4808 unsigned char op
[16];
4811 if (!unwind
.proc_start
)
4812 as_bad (MISSING_FNSTART
);
4815 if (exp
.X_op
== O_constant
4816 && skip_past_comma (&input_line_pointer
) != FAIL
)
4818 unwind
.frame_size
+= exp
.X_add_number
;
4822 exp
.X_op
= O_illegal
;
4824 if (exp
.X_op
!= O_constant
)
4826 as_bad (_("expected <offset>, <opcode>"));
4827 ignore_rest_of_line ();
4833 /* Parse the opcode. */
4838 as_bad (_("unwind opcode too long"));
4839 ignore_rest_of_line ();
4841 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4843 as_bad (_("invalid unwind opcode"));
4844 ignore_rest_of_line ();
4847 op
[count
++] = exp
.X_add_number
;
4849 /* Parse the next byte. */
4850 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4856 /* Add the opcode bytes in reverse order. */
4858 add_unwind_opcode (op
[count
], 1);
4860 demand_empty_rest_of_line ();
4864 /* Parse a .eabi_attribute directive. */
4867 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4869 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4871 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4872 attributes_set_explicitly
[tag
] = 1;
4875 /* Emit a tls fix for the symbol. */
4878 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4882 #ifdef md_flush_pending_output
4883 md_flush_pending_output ();
4886 #ifdef md_cons_align
4890 /* Since we're just labelling the code, there's no need to define a
4893 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4894 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4895 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4896 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4898 #endif /* OBJ_ELF */
4900 static void s_arm_arch (int);
4901 static void s_arm_object_arch (int);
4902 static void s_arm_cpu (int);
4903 static void s_arm_fpu (int);
4904 static void s_arm_arch_extension (int);
4909 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4916 if (exp
.X_op
== O_symbol
)
4917 exp
.X_op
= O_secrel
;
4919 emit_expr (&exp
, 4);
4921 while (*input_line_pointer
++ == ',');
4923 input_line_pointer
--;
4924 demand_empty_rest_of_line ();
4928 /* This table describes all the machine specific pseudo-ops the assembler
4929 has to support. The fields are:
4930 pseudo-op name without dot
4931 function to call to execute this pseudo-op
4932 Integer arg to pass to the function. */
4934 const pseudo_typeS md_pseudo_table
[] =
4936 /* Never called because '.req' does not start a line. */
4937 { "req", s_req
, 0 },
4938 /* Following two are likewise never called. */
4941 { "unreq", s_unreq
, 0 },
4942 { "bss", s_bss
, 0 },
4943 { "align", s_align_ptwo
, 2 },
4944 { "arm", s_arm
, 0 },
4945 { "thumb", s_thumb
, 0 },
4946 { "code", s_code
, 0 },
4947 { "force_thumb", s_force_thumb
, 0 },
4948 { "thumb_func", s_thumb_func
, 0 },
4949 { "thumb_set", s_thumb_set
, 0 },
4950 { "even", s_even
, 0 },
4951 { "ltorg", s_ltorg
, 0 },
4952 { "pool", s_ltorg
, 0 },
4953 { "syntax", s_syntax
, 0 },
4954 { "cpu", s_arm_cpu
, 0 },
4955 { "arch", s_arm_arch
, 0 },
4956 { "object_arch", s_arm_object_arch
, 0 },
4957 { "fpu", s_arm_fpu
, 0 },
4958 { "arch_extension", s_arm_arch_extension
, 0 },
4960 { "word", s_arm_elf_cons
, 4 },
4961 { "long", s_arm_elf_cons
, 4 },
4962 { "inst.n", s_arm_elf_inst
, 2 },
4963 { "inst.w", s_arm_elf_inst
, 4 },
4964 { "inst", s_arm_elf_inst
, 0 },
4965 { "rel31", s_arm_rel31
, 0 },
4966 { "fnstart", s_arm_unwind_fnstart
, 0 },
4967 { "fnend", s_arm_unwind_fnend
, 0 },
4968 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4969 { "personality", s_arm_unwind_personality
, 0 },
4970 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4971 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4972 { "save", s_arm_unwind_save
, 0 },
4973 { "vsave", s_arm_unwind_save
, 1 },
4974 { "movsp", s_arm_unwind_movsp
, 0 },
4975 { "pad", s_arm_unwind_pad
, 0 },
4976 { "setfp", s_arm_unwind_setfp
, 0 },
4977 { "unwind_raw", s_arm_unwind_raw
, 0 },
4978 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4979 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4983 /* These are used for dwarf. */
4987 /* These are used for dwarf2. */
4988 { "file", dwarf2_directive_file
, 0 },
4989 { "loc", dwarf2_directive_loc
, 0 },
4990 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4992 { "extend", float_cons
, 'x' },
4993 { "ldouble", float_cons
, 'x' },
4994 { "packed", float_cons
, 'p' },
4996 {"secrel32", pe_directive_secrel
, 0},
4999 /* These are for compatibility with CodeComposer Studio. */
5000 {"ref", s_ccs_ref
, 0},
5001 {"def", s_ccs_def
, 0},
5002 {"asmfunc", s_ccs_asmfunc
, 0},
5003 {"endasmfunc", s_ccs_endasmfunc
, 0},
5008 /* Parser functions used exclusively in instruction operands. */
5010 /* Generic immediate-value read function for use in insn parsing.
5011 STR points to the beginning of the immediate (the leading #);
5012 VAL receives the value; if the value is outside [MIN, MAX]
5013 issue an error. PREFIX_OPT is true if the immediate prefix is
5017 parse_immediate (char **str
, int *val
, int min
, int max
,
5018 bfd_boolean prefix_opt
)
5022 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5023 if (exp
.X_op
!= O_constant
)
5025 inst
.error
= _("constant expression required");
5029 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5031 inst
.error
= _("immediate value out of range");
5035 *val
= exp
.X_add_number
;
5039 /* Less-generic immediate-value read function with the possibility of loading a
5040 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5041 instructions. Puts the result directly in inst.operands[i]. */
5044 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5045 bfd_boolean allow_symbol_p
)
5048 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5051 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5053 if (exp_p
->X_op
== O_constant
)
5055 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5056 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5057 O_constant. We have to be careful not to break compilation for
5058 32-bit X_add_number, though. */
5059 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5061 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5062 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5064 inst
.operands
[i
].regisimm
= 1;
5067 else if (exp_p
->X_op
== O_big
5068 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5070 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5072 /* Bignums have their least significant bits in
5073 generic_bignum[0]. Make sure we put 32 bits in imm and
5074 32 bits in reg, in a (hopefully) portable way. */
5075 gas_assert (parts
!= 0);
5077 /* Make sure that the number is not too big.
5078 PR 11972: Bignums can now be sign-extended to the
5079 size of a .octa so check that the out of range bits
5080 are all zero or all one. */
5081 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5083 LITTLENUM_TYPE m
= -1;
5085 if (generic_bignum
[parts
* 2] != 0
5086 && generic_bignum
[parts
* 2] != m
)
5089 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5090 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5094 inst
.operands
[i
].imm
= 0;
5095 for (j
= 0; j
< parts
; j
++, idx
++)
5096 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5097 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5098 inst
.operands
[i
].reg
= 0;
5099 for (j
= 0; j
< parts
; j
++, idx
++)
5100 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5101 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5102 inst
.operands
[i
].regisimm
= 1;
5104 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5112 /* Returns the pseudo-register number of an FPA immediate constant,
5113 or FAIL if there isn't a valid constant here. */
5116 parse_fpa_immediate (char ** str
)
5118 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5124 /* First try and match exact strings, this is to guarantee
5125 that some formats will work even for cross assembly. */
5127 for (i
= 0; fp_const
[i
]; i
++)
5129 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5133 *str
+= strlen (fp_const
[i
]);
5134 if (is_end_of_line
[(unsigned char) **str
])
5140 /* Just because we didn't get a match doesn't mean that the constant
5141 isn't valid, just that it is in a format that we don't
5142 automatically recognize. Try parsing it with the standard
5143 expression routines. */
5145 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5147 /* Look for a raw floating point number. */
5148 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5149 && is_end_of_line
[(unsigned char) *save_in
])
5151 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5153 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5155 if (words
[j
] != fp_values
[i
][j
])
5159 if (j
== MAX_LITTLENUMS
)
5167 /* Try and parse a more complex expression, this will probably fail
5168 unless the code uses a floating point prefix (eg "0f"). */
5169 save_in
= input_line_pointer
;
5170 input_line_pointer
= *str
;
5171 if (expression (&exp
) == absolute_section
5172 && exp
.X_op
== O_big
5173 && exp
.X_add_number
< 0)
5175 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5177 #define X_PRECISION 5
5178 #define E_PRECISION 15L
5179 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5181 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5183 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5185 if (words
[j
] != fp_values
[i
][j
])
5189 if (j
== MAX_LITTLENUMS
)
5191 *str
= input_line_pointer
;
5192 input_line_pointer
= save_in
;
5199 *str
= input_line_pointer
;
5200 input_line_pointer
= save_in
;
5201 inst
.error
= _("invalid FPA immediate expression");
5205 /* Returns 1 if a number has "quarter-precision" float format
5206 0baBbbbbbc defgh000 00000000 00000000. */
5209 is_quarter_float (unsigned imm
)
5211 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5212 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5216 /* Detect the presence of a floating point or integer zero constant,
5220 parse_ifimm_zero (char **in
)
5224 if (!is_immediate_prefix (**in
))
5226 /* In unified syntax, all prefixes are optional. */
5227 if (!unified_syntax
)
5233 /* Accept #0x0 as a synonym for #0. */
5234 if (strncmp (*in
, "0x", 2) == 0)
5237 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5242 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5243 &generic_floating_point_number
);
5246 && generic_floating_point_number
.sign
== '+'
5247 && (generic_floating_point_number
.low
5248 > generic_floating_point_number
.leader
))
5254 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5255 0baBbbbbbc defgh000 00000000 00000000.
5256 The zero and minus-zero cases need special handling, since they can't be
5257 encoded in the "quarter-precision" float format, but can nonetheless be
5258 loaded as integer constants. */
5261 parse_qfloat_immediate (char **ccp
, int *immed
)
5265 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5266 int found_fpchar
= 0;
5268 skip_past_char (&str
, '#');
5270 /* We must not accidentally parse an integer as a floating-point number. Make
5271 sure that the value we parse is not an integer by checking for special
5272 characters '.' or 'e'.
5273 FIXME: This is a horrible hack, but doing better is tricky because type
5274 information isn't in a very usable state at parse time. */
5276 skip_whitespace (fpnum
);
5278 if (strncmp (fpnum
, "0x", 2) == 0)
5282 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5283 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5293 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5295 unsigned fpword
= 0;
5298 /* Our FP word must be 32 bits (single-precision FP). */
5299 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5301 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5305 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5318 /* Shift operands. */
5321 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5324 struct asm_shift_name
5327 enum shift_kind kind
;
5330 /* Third argument to parse_shift. */
5331 enum parse_shift_mode
5333 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5334 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5335 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5336 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5337 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5338 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5341 /* Parse a <shift> specifier on an ARM data processing instruction.
5342 This has three forms:
5344 (LSL|LSR|ASL|ASR|ROR) Rs
5345 (LSL|LSR|ASL|ASR|ROR) #imm
5348 Note that ASL is assimilated to LSL in the instruction encoding, and
5349 RRX to ROR #0 (which cannot be written as such). */
5352 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5354 const struct asm_shift_name
*shift_name
;
5355 enum shift_kind shift
;
5360 for (p
= *str
; ISALPHA (*p
); p
++)
5365 inst
.error
= _("shift expression expected");
5369 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5372 if (shift_name
== NULL
)
5374 inst
.error
= _("shift expression expected");
5378 shift
= shift_name
->kind
;
5382 case NO_SHIFT_RESTRICT
:
5383 case SHIFT_IMMEDIATE
:
5384 if (shift
== SHIFT_UXTW
)
5386 inst
.error
= _("'UXTW' not allowed here");
5391 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5392 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5394 inst
.error
= _("'LSL' or 'ASR' required");
5399 case SHIFT_LSL_IMMEDIATE
:
5400 if (shift
!= SHIFT_LSL
)
5402 inst
.error
= _("'LSL' required");
5407 case SHIFT_ASR_IMMEDIATE
:
5408 if (shift
!= SHIFT_ASR
)
5410 inst
.error
= _("'ASR' required");
5414 case SHIFT_UXTW_IMMEDIATE
:
5415 if (shift
!= SHIFT_UXTW
)
5417 inst
.error
= _("'UXTW' required");
5425 if (shift
!= SHIFT_RRX
)
5427 /* Whitespace can appear here if the next thing is a bare digit. */
5428 skip_whitespace (p
);
5430 if (mode
== NO_SHIFT_RESTRICT
5431 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5433 inst
.operands
[i
].imm
= reg
;
5434 inst
.operands
[i
].immisreg
= 1;
5436 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5439 inst
.operands
[i
].shift_kind
= shift
;
5440 inst
.operands
[i
].shifted
= 1;
5445 /* Parse a <shifter_operand> for an ARM data processing instruction:
5448 #<immediate>, <rotate>
5452 where <shift> is defined by parse_shift above, and <rotate> is a
5453 multiple of 2 between 0 and 30. Validation of immediate operands
5454 is deferred to md_apply_fix. */
5457 parse_shifter_operand (char **str
, int i
)
5462 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5464 inst
.operands
[i
].reg
= value
;
5465 inst
.operands
[i
].isreg
= 1;
5467 /* parse_shift will override this if appropriate */
5468 inst
.relocs
[0].exp
.X_op
= O_constant
;
5469 inst
.relocs
[0].exp
.X_add_number
= 0;
5471 if (skip_past_comma (str
) == FAIL
)
5474 /* Shift operation on register. */
5475 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5478 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5481 if (skip_past_comma (str
) == SUCCESS
)
5483 /* #x, y -- ie explicit rotation by Y. */
5484 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5487 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5489 inst
.error
= _("constant expression expected");
5493 value
= exp
.X_add_number
;
5494 if (value
< 0 || value
> 30 || value
% 2 != 0)
5496 inst
.error
= _("invalid rotation");
5499 if (inst
.relocs
[0].exp
.X_add_number
< 0
5500 || inst
.relocs
[0].exp
.X_add_number
> 255)
5502 inst
.error
= _("invalid constant");
5506 /* Encode as specified. */
5507 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5511 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5512 inst
.relocs
[0].pc_rel
= 0;
5516 /* Group relocation information. Each entry in the table contains the
5517 textual name of the relocation as may appear in assembler source
5518 and must end with a colon.
5519 Along with this textual name are the relocation codes to be used if
5520 the corresponding instruction is an ALU instruction (ADD or SUB only),
5521 an LDR, an LDRS, or an LDC. */
5523 struct group_reloc_table_entry
5534 /* Varieties of non-ALU group relocation. */
5542 static struct group_reloc_table_entry group_reloc_table
[] =
5543 { /* Program counter relative: */
5545 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5550 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5551 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5552 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5553 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5555 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5560 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5561 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5562 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5563 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5565 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5566 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5567 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5568 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5569 /* Section base relative */
5571 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5576 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5577 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5578 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5579 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5581 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5586 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5587 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5588 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5589 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5591 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5592 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5593 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5594 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5595 /* Absolute thumb alu relocations. */
5597 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5602 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5607 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5612 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5617 /* Given the address of a pointer pointing to the textual name of a group
5618 relocation as may appear in assembler source, attempt to find its details
5619 in group_reloc_table. The pointer will be updated to the character after
5620 the trailing colon. On failure, FAIL will be returned; SUCCESS
5621 otherwise. On success, *entry will be updated to point at the relevant
5622 group_reloc_table entry. */
5625 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5628 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5630 int length
= strlen (group_reloc_table
[i
].name
);
5632 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5633 && (*str
)[length
] == ':')
5635 *out
= &group_reloc_table
[i
];
5636 *str
+= (length
+ 1);
5644 /* Parse a <shifter_operand> for an ARM data processing instruction
5645 (as for parse_shifter_operand) where group relocations are allowed:
5648 #<immediate>, <rotate>
5649 #:<group_reloc>:<expression>
5653 where <group_reloc> is one of the strings defined in group_reloc_table.
5654 The hashes are optional.
5656 Everything else is as for parse_shifter_operand. */
5658 static parse_operand_result
5659 parse_shifter_operand_group_reloc (char **str
, int i
)
5661 /* Determine if we have the sequence of characters #: or just :
5662 coming next. If we do, then we check for a group relocation.
5663 If we don't, punt the whole lot to parse_shifter_operand. */
5665 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5666 || (*str
)[0] == ':')
5668 struct group_reloc_table_entry
*entry
;
5670 if ((*str
)[0] == '#')
5675 /* Try to parse a group relocation. Anything else is an error. */
5676 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5678 inst
.error
= _("unknown group relocation");
5679 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5682 /* We now have the group relocation table entry corresponding to
5683 the name in the assembler source. Next, we parse the expression. */
5684 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5685 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5687 /* Record the relocation type (always the ALU variant here). */
5688 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5689 gas_assert (inst
.relocs
[0].type
!= 0);
5691 return PARSE_OPERAND_SUCCESS
;
5694 return parse_shifter_operand (str
, i
) == SUCCESS
5695 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5697 /* Never reached. */
5700 /* Parse a Neon alignment expression. Information is written to
5701 inst.operands[i]. We assume the initial ':' has been skipped.
5703 align .imm = align << 8, .immisalign=1, .preind=0 */
5704 static parse_operand_result
5705 parse_neon_alignment (char **str
, int i
)
5710 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5712 if (exp
.X_op
!= O_constant
)
5714 inst
.error
= _("alignment must be constant");
5715 return PARSE_OPERAND_FAIL
;
5718 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5719 inst
.operands
[i
].immisalign
= 1;
5720 /* Alignments are not pre-indexes. */
5721 inst
.operands
[i
].preind
= 0;
5724 return PARSE_OPERAND_SUCCESS
;
5727 /* Parse all forms of an ARM address expression. Information is written
5728 to inst.operands[i] and/or inst.relocs[0].
5730 Preindexed addressing (.preind=1):
5732 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5733 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5734 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5735 .shift_kind=shift .relocs[0].exp=shift_imm
5737 These three may have a trailing ! which causes .writeback to be set also.
5739 Postindexed addressing (.postind=1, .writeback=1):
5741 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5742 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5743 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5744 .shift_kind=shift .relocs[0].exp=shift_imm
5746 Unindexed addressing (.preind=0, .postind=0):
5748 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5752 [Rn]{!} shorthand for [Rn,#0]{!}
5753 =immediate .isreg=0 .relocs[0].exp=immediate
5754 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5756 It is the caller's responsibility to check for addressing modes not
5757 supported by the instruction, and to set inst.relocs[0].type. */
5759 static parse_operand_result
5760 parse_address_main (char **str
, int i
, int group_relocations
,
5761 group_reloc_type group_type
)
5766 if (skip_past_char (&p
, '[') == FAIL
)
5768 if (skip_past_char (&p
, '=') == FAIL
)
5770 /* Bare address - translate to PC-relative offset. */
5771 inst
.relocs
[0].pc_rel
= 1;
5772 inst
.operands
[i
].reg
= REG_PC
;
5773 inst
.operands
[i
].isreg
= 1;
5774 inst
.operands
[i
].preind
= 1;
5776 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5777 return PARSE_OPERAND_FAIL
;
5779 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5780 /*allow_symbol_p=*/TRUE
))
5781 return PARSE_OPERAND_FAIL
;
5784 return PARSE_OPERAND_SUCCESS
;
5787 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5788 skip_whitespace (p
);
5790 if (group_type
== GROUP_MVE
)
5792 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5793 struct neon_type_el et
;
5794 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5796 inst
.operands
[i
].isquad
= 1;
5798 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5800 inst
.error
= BAD_ADDR_MODE
;
5801 return PARSE_OPERAND_FAIL
;
5804 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5806 if (group_type
== GROUP_MVE
)
5807 inst
.error
= BAD_ADDR_MODE
;
5809 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5810 return PARSE_OPERAND_FAIL
;
5812 inst
.operands
[i
].reg
= reg
;
5813 inst
.operands
[i
].isreg
= 1;
5815 if (skip_past_comma (&p
) == SUCCESS
)
5817 inst
.operands
[i
].preind
= 1;
5820 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5822 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5823 struct neon_type_el et
;
5824 if (group_type
== GROUP_MVE
5825 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5827 inst
.operands
[i
].immisreg
= 2;
5828 inst
.operands
[i
].imm
= reg
;
5830 if (skip_past_comma (&p
) == SUCCESS
)
5832 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5834 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5835 inst
.relocs
[0].exp
.X_add_number
= 0;
5838 return PARSE_OPERAND_FAIL
;
5841 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5843 inst
.operands
[i
].imm
= reg
;
5844 inst
.operands
[i
].immisreg
= 1;
5846 if (skip_past_comma (&p
) == SUCCESS
)
5847 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5848 return PARSE_OPERAND_FAIL
;
5850 else if (skip_past_char (&p
, ':') == SUCCESS
)
5852 /* FIXME: '@' should be used here, but it's filtered out by generic
5853 code before we get to see it here. This may be subject to
5855 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5857 if (result
!= PARSE_OPERAND_SUCCESS
)
5862 if (inst
.operands
[i
].negative
)
5864 inst
.operands
[i
].negative
= 0;
5868 if (group_relocations
5869 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5871 struct group_reloc_table_entry
*entry
;
5873 /* Skip over the #: or : sequence. */
5879 /* Try to parse a group relocation. Anything else is an
5881 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5883 inst
.error
= _("unknown group relocation");
5884 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5887 /* We now have the group relocation table entry corresponding to
5888 the name in the assembler source. Next, we parse the
5890 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5891 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5893 /* Record the relocation type. */
5898 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5903 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5908 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5915 if (inst
.relocs
[0].type
== 0)
5917 inst
.error
= _("this group relocation is not allowed on this instruction");
5918 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5925 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5926 return PARSE_OPERAND_FAIL
;
5927 /* If the offset is 0, find out if it's a +0 or -0. */
5928 if (inst
.relocs
[0].exp
.X_op
== O_constant
5929 && inst
.relocs
[0].exp
.X_add_number
== 0)
5931 skip_whitespace (q
);
5935 skip_whitespace (q
);
5938 inst
.operands
[i
].negative
= 1;
5943 else if (skip_past_char (&p
, ':') == SUCCESS
)
5945 /* FIXME: '@' should be used here, but it's filtered out by generic code
5946 before we get to see it here. This may be subject to change. */
5947 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5949 if (result
!= PARSE_OPERAND_SUCCESS
)
5953 if (skip_past_char (&p
, ']') == FAIL
)
5955 inst
.error
= _("']' expected");
5956 return PARSE_OPERAND_FAIL
;
5959 if (skip_past_char (&p
, '!') == SUCCESS
)
5960 inst
.operands
[i
].writeback
= 1;
5962 else if (skip_past_comma (&p
) == SUCCESS
)
5964 if (skip_past_char (&p
, '{') == SUCCESS
)
5966 /* [Rn], {expr} - unindexed, with option */
5967 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5968 0, 255, TRUE
) == FAIL
)
5969 return PARSE_OPERAND_FAIL
;
5971 if (skip_past_char (&p
, '}') == FAIL
)
5973 inst
.error
= _("'}' expected at end of 'option' field");
5974 return PARSE_OPERAND_FAIL
;
5976 if (inst
.operands
[i
].preind
)
5978 inst
.error
= _("cannot combine index with option");
5979 return PARSE_OPERAND_FAIL
;
5982 return PARSE_OPERAND_SUCCESS
;
5986 inst
.operands
[i
].postind
= 1;
5987 inst
.operands
[i
].writeback
= 1;
5989 if (inst
.operands
[i
].preind
)
5991 inst
.error
= _("cannot combine pre- and post-indexing");
5992 return PARSE_OPERAND_FAIL
;
5996 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5998 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5999 struct neon_type_el et
;
6000 if (group_type
== GROUP_MVE
6001 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6003 inst
.operands
[i
].immisreg
= 2;
6004 inst
.operands
[i
].imm
= reg
;
6006 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6008 /* We might be using the immediate for alignment already. If we
6009 are, OR the register number into the low-order bits. */
6010 if (inst
.operands
[i
].immisalign
)
6011 inst
.operands
[i
].imm
|= reg
;
6013 inst
.operands
[i
].imm
= reg
;
6014 inst
.operands
[i
].immisreg
= 1;
6016 if (skip_past_comma (&p
) == SUCCESS
)
6017 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6018 return PARSE_OPERAND_FAIL
;
6024 if (inst
.operands
[i
].negative
)
6026 inst
.operands
[i
].negative
= 0;
6029 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6030 return PARSE_OPERAND_FAIL
;
6031 /* If the offset is 0, find out if it's a +0 or -0. */
6032 if (inst
.relocs
[0].exp
.X_op
== O_constant
6033 && inst
.relocs
[0].exp
.X_add_number
== 0)
6035 skip_whitespace (q
);
6039 skip_whitespace (q
);
6042 inst
.operands
[i
].negative
= 1;
6048 /* If at this point neither .preind nor .postind is set, we have a
6049 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6050 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6052 inst
.operands
[i
].preind
= 1;
6053 inst
.relocs
[0].exp
.X_op
= O_constant
;
6054 inst
.relocs
[0].exp
.X_add_number
= 0;
6057 return PARSE_OPERAND_SUCCESS
;
6061 parse_address (char **str
, int i
)
6063 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6067 static parse_operand_result
6068 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6070 return parse_address_main (str
, i
, 1, type
);
6073 /* Parse an operand for a MOVW or MOVT instruction. */
6075 parse_half (char **str
)
6080 skip_past_char (&p
, '#');
6081 if (strncasecmp (p
, ":lower16:", 9) == 0)
6082 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6083 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6084 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6086 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6089 skip_whitespace (p
);
6092 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6095 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6097 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6099 inst
.error
= _("constant expression expected");
6102 if (inst
.relocs
[0].exp
.X_add_number
< 0
6103 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6105 inst
.error
= _("immediate value out of range");
6113 /* Miscellaneous. */
6115 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6116 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6118 parse_psr (char **str
, bfd_boolean lhs
)
6121 unsigned long psr_field
;
6122 const struct asm_psr
*psr
;
6124 bfd_boolean is_apsr
= FALSE
;
6125 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6127 /* PR gas/12698: If the user has specified -march=all then m_profile will
6128 be TRUE, but we want to ignore it in this case as we are building for any
6129 CPU type, including non-m variants. */
6130 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6133 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6134 feature for ease of use and backwards compatibility. */
6136 if (strncasecmp (p
, "SPSR", 4) == 0)
6139 goto unsupported_psr
;
6141 psr_field
= SPSR_BIT
;
6143 else if (strncasecmp (p
, "CPSR", 4) == 0)
6146 goto unsupported_psr
;
6150 else if (strncasecmp (p
, "APSR", 4) == 0)
6152 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6153 and ARMv7-R architecture CPUs. */
6162 while (ISALNUM (*p
) || *p
== '_');
6164 if (strncasecmp (start
, "iapsr", 5) == 0
6165 || strncasecmp (start
, "eapsr", 5) == 0
6166 || strncasecmp (start
, "xpsr", 4) == 0
6167 || strncasecmp (start
, "psr", 3) == 0)
6168 p
= start
+ strcspn (start
, "rR") + 1;
6170 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6176 /* If APSR is being written, a bitfield may be specified. Note that
6177 APSR itself is handled above. */
6178 if (psr
->field
<= 3)
6180 psr_field
= psr
->field
;
6186 /* M-profile MSR instructions have the mask field set to "10", except
6187 *PSR variants which modify APSR, which may use a different mask (and
6188 have been handled already). Do that by setting the PSR_f field
6190 return psr
->field
| (lhs
? PSR_f
: 0);
6193 goto unsupported_psr
;
6199 /* A suffix follows. */
6205 while (ISALNUM (*p
) || *p
== '_');
6209 /* APSR uses a notation for bits, rather than fields. */
6210 unsigned int nzcvq_bits
= 0;
6211 unsigned int g_bit
= 0;
6214 for (bit
= start
; bit
!= p
; bit
++)
6216 switch (TOLOWER (*bit
))
6219 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6223 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6227 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6231 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6235 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6239 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6243 inst
.error
= _("unexpected bit specified after APSR");
6248 if (nzcvq_bits
== 0x1f)
6253 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6255 inst
.error
= _("selected processor does not "
6256 "support DSP extension");
6263 if ((nzcvq_bits
& 0x20) != 0
6264 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6265 || (g_bit
& 0x2) != 0)
6267 inst
.error
= _("bad bitmask specified after APSR");
6273 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6278 psr_field
|= psr
->field
;
6284 goto error
; /* Garbage after "[CS]PSR". */
6286 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6287 is deprecated, but allow it anyway. */
6291 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6294 else if (!m_profile
)
6295 /* These bits are never right for M-profile devices: don't set them
6296 (only code paths which read/write APSR reach here). */
6297 psr_field
|= (PSR_c
| PSR_f
);
6303 inst
.error
= _("selected processor does not support requested special "
6304 "purpose register");
6308 inst
.error
= _("flag for {c}psr instruction expected");
6313 parse_sys_vldr_vstr (char **str
)
6322 {"FPSCR", 0x1, 0x0},
6323 {"FPSCR_nzcvqc", 0x2, 0x0},
6326 {"FPCXTNS", 0x6, 0x1},
6327 {"FPCXTS", 0x7, 0x1}
6329 char *op_end
= strchr (*str
, ',');
6330 size_t op_strlen
= op_end
- *str
;
6332 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6334 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6336 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6345 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6346 value suitable for splatting into the AIF field of the instruction. */
6349 parse_cps_flags (char **str
)
6358 case '\0': case ',':
6361 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6362 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6363 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6366 inst
.error
= _("unrecognized CPS flag");
6371 if (saw_a_flag
== 0)
6373 inst
.error
= _("missing CPS flags");
6381 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6382 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6385 parse_endian_specifier (char **str
)
6390 if (strncasecmp (s
, "BE", 2))
6392 else if (strncasecmp (s
, "LE", 2))
6396 inst
.error
= _("valid endian specifiers are be or le");
6400 if (ISALNUM (s
[2]) || s
[2] == '_')
6402 inst
.error
= _("valid endian specifiers are be or le");
6407 return little_endian
;
6410 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6411 value suitable for poking into the rotate field of an sxt or sxta
6412 instruction, or FAIL on error. */
6415 parse_ror (char **str
)
6420 if (strncasecmp (s
, "ROR", 3) == 0)
6424 inst
.error
= _("missing rotation field after comma");
6428 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6433 case 0: *str
= s
; return 0x0;
6434 case 8: *str
= s
; return 0x1;
6435 case 16: *str
= s
; return 0x2;
6436 case 24: *str
= s
; return 0x3;
6439 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6444 /* Parse a conditional code (from conds[] below). The value returned is in the
6445 range 0 .. 14, or FAIL. */
6447 parse_cond (char **str
)
6450 const struct asm_cond
*c
;
6452 /* Condition codes are always 2 characters, so matching up to
6453 3 characters is sufficient. */
6458 while (ISALPHA (*q
) && n
< 3)
6460 cond
[n
] = TOLOWER (*q
);
6465 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6468 inst
.error
= _("condition required");
6476 /* Parse an option for a barrier instruction. Returns the encoding for the
6479 parse_barrier (char **str
)
6482 const struct asm_barrier_opt
*o
;
6485 while (ISALPHA (*q
))
6488 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6493 if (!mark_feature_used (&o
->arch
))
6500 /* Parse the operands of a table branch instruction. Similar to a memory
6503 parse_tb (char **str
)
6508 if (skip_past_char (&p
, '[') == FAIL
)
6510 inst
.error
= _("'[' expected");
6514 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6516 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6519 inst
.operands
[0].reg
= reg
;
6521 if (skip_past_comma (&p
) == FAIL
)
6523 inst
.error
= _("',' expected");
6527 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6529 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6532 inst
.operands
[0].imm
= reg
;
6534 if (skip_past_comma (&p
) == SUCCESS
)
6536 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6538 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6540 inst
.error
= _("invalid shift");
6543 inst
.operands
[0].shifted
= 1;
6546 if (skip_past_char (&p
, ']') == FAIL
)
6548 inst
.error
= _("']' expected");
6555 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6556 information on the types the operands can take and how they are encoded.
6557 Up to four operands may be read; this function handles setting the
6558 ".present" field for each read operand itself.
6559 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6560 else returns FAIL. */
6563 parse_neon_mov (char **str
, int *which_operand
)
6565 int i
= *which_operand
, val
;
6566 enum arm_reg_type rtype
;
6568 struct neon_type_el optype
;
6570 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6572 /* Cases 17 or 19. */
6573 inst
.operands
[i
].reg
= val
;
6574 inst
.operands
[i
].isvec
= 1;
6575 inst
.operands
[i
].isscalar
= 2;
6576 inst
.operands
[i
].vectype
= optype
;
6577 inst
.operands
[i
++].present
= 1;
6579 if (skip_past_comma (&ptr
) == FAIL
)
6582 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6584 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6585 inst
.operands
[i
].reg
= val
;
6586 inst
.operands
[i
].isreg
= 1;
6587 inst
.operands
[i
].present
= 1;
6589 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6591 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6592 inst
.operands
[i
].reg
= val
;
6593 inst
.operands
[i
].isvec
= 1;
6594 inst
.operands
[i
].isscalar
= 2;
6595 inst
.operands
[i
].vectype
= optype
;
6596 inst
.operands
[i
++].present
= 1;
6598 if (skip_past_comma (&ptr
) == FAIL
)
6601 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6604 inst
.operands
[i
].reg
= val
;
6605 inst
.operands
[i
].isreg
= 1;
6606 inst
.operands
[i
++].present
= 1;
6608 if (skip_past_comma (&ptr
) == FAIL
)
6611 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6614 inst
.operands
[i
].reg
= val
;
6615 inst
.operands
[i
].isreg
= 1;
6616 inst
.operands
[i
].present
= 1;
6620 first_error (_("expected ARM or MVE vector register"));
6624 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6626 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6627 inst
.operands
[i
].reg
= val
;
6628 inst
.operands
[i
].isscalar
= 1;
6629 inst
.operands
[i
].vectype
= optype
;
6630 inst
.operands
[i
++].present
= 1;
6632 if (skip_past_comma (&ptr
) == FAIL
)
6635 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6638 inst
.operands
[i
].reg
= val
;
6639 inst
.operands
[i
].isreg
= 1;
6640 inst
.operands
[i
].present
= 1;
6642 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6644 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6647 /* Cases 0, 1, 2, 3, 5 (D only). */
6648 if (skip_past_comma (&ptr
) == FAIL
)
6651 inst
.operands
[i
].reg
= val
;
6652 inst
.operands
[i
].isreg
= 1;
6653 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6654 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6655 inst
.operands
[i
].isvec
= 1;
6656 inst
.operands
[i
].vectype
= optype
;
6657 inst
.operands
[i
++].present
= 1;
6659 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6661 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6662 Case 13: VMOV <Sd>, <Rm> */
6663 inst
.operands
[i
].reg
= val
;
6664 inst
.operands
[i
].isreg
= 1;
6665 inst
.operands
[i
].present
= 1;
6667 if (rtype
== REG_TYPE_NQ
)
6669 first_error (_("can't use Neon quad register here"));
6672 else if (rtype
!= REG_TYPE_VFS
)
6675 if (skip_past_comma (&ptr
) == FAIL
)
6677 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6679 inst
.operands
[i
].reg
= val
;
6680 inst
.operands
[i
].isreg
= 1;
6681 inst
.operands
[i
].present
= 1;
6684 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6687 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6688 Case 1: VMOV<c><q> <Dd>, <Dm>
6689 Case 8: VMOV.F32 <Sd>, <Sm>
6690 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6692 inst
.operands
[i
].reg
= val
;
6693 inst
.operands
[i
].isreg
= 1;
6694 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6695 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6696 inst
.operands
[i
].isvec
= 1;
6697 inst
.operands
[i
].vectype
= optype
;
6698 inst
.operands
[i
].present
= 1;
6700 if (skip_past_comma (&ptr
) == SUCCESS
)
6705 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6708 inst
.operands
[i
].reg
= val
;
6709 inst
.operands
[i
].isreg
= 1;
6710 inst
.operands
[i
++].present
= 1;
6712 if (skip_past_comma (&ptr
) == FAIL
)
6715 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6718 inst
.operands
[i
].reg
= val
;
6719 inst
.operands
[i
].isreg
= 1;
6720 inst
.operands
[i
].present
= 1;
6723 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6724 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6725 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6726 Case 10: VMOV.F32 <Sd>, #<imm>
6727 Case 11: VMOV.F64 <Dd>, #<imm> */
6728 inst
.operands
[i
].immisfloat
= 1;
6729 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6731 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6732 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6736 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6740 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6742 /* Cases 6, 7, 16, 18. */
6743 inst
.operands
[i
].reg
= val
;
6744 inst
.operands
[i
].isreg
= 1;
6745 inst
.operands
[i
++].present
= 1;
6747 if (skip_past_comma (&ptr
) == FAIL
)
6750 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6752 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6753 inst
.operands
[i
].reg
= val
;
6754 inst
.operands
[i
].isscalar
= 2;
6755 inst
.operands
[i
].present
= 1;
6756 inst
.operands
[i
].vectype
= optype
;
6758 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6760 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6761 inst
.operands
[i
].reg
= val
;
6762 inst
.operands
[i
].isscalar
= 1;
6763 inst
.operands
[i
].present
= 1;
6764 inst
.operands
[i
].vectype
= optype
;
6766 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6768 inst
.operands
[i
].reg
= val
;
6769 inst
.operands
[i
].isreg
= 1;
6770 inst
.operands
[i
++].present
= 1;
6772 if (skip_past_comma (&ptr
) == FAIL
)
6775 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6778 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6780 inst
.operands
[i
].reg
= val
;
6781 inst
.operands
[i
].isreg
= 1;
6782 inst
.operands
[i
].isvec
= 1;
6783 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6784 inst
.operands
[i
].vectype
= optype
;
6785 inst
.operands
[i
].present
= 1;
6787 if (rtype
== REG_TYPE_VFS
)
6791 if (skip_past_comma (&ptr
) == FAIL
)
6793 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6796 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6799 inst
.operands
[i
].reg
= val
;
6800 inst
.operands
[i
].isreg
= 1;
6801 inst
.operands
[i
].isvec
= 1;
6802 inst
.operands
[i
].issingle
= 1;
6803 inst
.operands
[i
].vectype
= optype
;
6804 inst
.operands
[i
].present
= 1;
6809 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6812 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6813 inst
.operands
[i
].reg
= val
;
6814 inst
.operands
[i
].isvec
= 1;
6815 inst
.operands
[i
].isscalar
= 2;
6816 inst
.operands
[i
].vectype
= optype
;
6817 inst
.operands
[i
++].present
= 1;
6819 if (skip_past_comma (&ptr
) == FAIL
)
6822 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6825 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6828 inst
.operands
[i
].reg
= val
;
6829 inst
.operands
[i
].isvec
= 1;
6830 inst
.operands
[i
].isscalar
= 2;
6831 inst
.operands
[i
].vectype
= optype
;
6832 inst
.operands
[i
].present
= 1;
6836 first_error (_("VFP single, double or MVE vector register"
6842 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6846 inst
.operands
[i
].reg
= val
;
6847 inst
.operands
[i
].isreg
= 1;
6848 inst
.operands
[i
].isvec
= 1;
6849 inst
.operands
[i
].issingle
= 1;
6850 inst
.operands
[i
].vectype
= optype
;
6851 inst
.operands
[i
].present
= 1;
6856 first_error (_("parse error"));
6860 /* Successfully parsed the operands. Update args. */
6866 first_error (_("expected comma"));
6870 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6874 /* Use this macro when the operand constraints are different
6875 for ARM and THUMB (e.g. ldrd). */
6876 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6877 ((arm_operand) | ((thumb_operand) << 16))
6879 /* Matcher codes for parse_operands. */
6880 enum operand_parse_code
6882 OP_stop
, /* end of line */
6884 OP_RR
, /* ARM register */
6885 OP_RRnpc
, /* ARM register, not r15 */
6886 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6887 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6888 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6889 optional trailing ! */
6890 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6891 OP_RCP
, /* Coprocessor number */
6892 OP_RCN
, /* Coprocessor register */
6893 OP_RF
, /* FPA register */
6894 OP_RVS
, /* VFP single precision register */
6895 OP_RVD
, /* VFP double precision register (0..15) */
6896 OP_RND
, /* Neon double precision register (0..31) */
6897 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6898 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6900 OP_RNQ
, /* Neon quad precision register */
6901 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6902 OP_RVSD
, /* VFP single or double precision register */
6903 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6904 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6905 OP_RNSD
, /* Neon single or double precision register */
6906 OP_RNDQ
, /* Neon double or quad precision register */
6907 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6908 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6909 OP_RNSDQ
, /* Neon single, double or quad precision register */
6910 OP_RNSC
, /* Neon scalar D[X] */
6911 OP_RVC
, /* VFP control register */
6912 OP_RMF
, /* Maverick F register */
6913 OP_RMD
, /* Maverick D register */
6914 OP_RMFX
, /* Maverick FX register */
6915 OP_RMDX
, /* Maverick DX register */
6916 OP_RMAX
, /* Maverick AX register */
6917 OP_RMDS
, /* Maverick DSPSC register */
6918 OP_RIWR
, /* iWMMXt wR register */
6919 OP_RIWC
, /* iWMMXt wC register */
6920 OP_RIWG
, /* iWMMXt wCG register */
6921 OP_RXA
, /* XScale accumulator register */
6923 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6925 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6927 OP_RMQ
, /* MVE vector register. */
6928 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6929 OP_RMQRR
, /* MVE vector or ARM register. */
6931 /* New operands for Armv8.1-M Mainline. */
6932 OP_LR
, /* ARM LR register */
6933 OP_RRe
, /* ARM register, only even numbered. */
6934 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6935 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6936 OP_RR_ZR
, /* ARM register or ZR but no PC */
6938 OP_REGLST
, /* ARM register list */
6939 OP_CLRMLST
, /* CLRM register list */
6940 OP_VRSLST
, /* VFP single-precision register list */
6941 OP_VRDLST
, /* VFP double-precision register list */
6942 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6943 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6944 OP_NSTRLST
, /* Neon element/structure list */
6945 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6946 OP_MSTRLST2
, /* MVE vector list with two elements. */
6947 OP_MSTRLST4
, /* MVE vector list with four elements. */
6949 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6950 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6951 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6952 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
6954 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6955 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6956 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6957 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6959 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
6960 scalar, or ARM register. */
6961 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6962 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
6963 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
6965 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
6966 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6967 OP_VMOV
, /* Neon VMOV operands. */
6968 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6969 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6971 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6972 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
6974 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6975 OP_VLDR
, /* VLDR operand. */
6977 OP_I0
, /* immediate zero */
6978 OP_I7
, /* immediate value 0 .. 7 */
6979 OP_I15
, /* 0 .. 15 */
6980 OP_I16
, /* 1 .. 16 */
6981 OP_I16z
, /* 0 .. 16 */
6982 OP_I31
, /* 0 .. 31 */
6983 OP_I31w
, /* 0 .. 31, optional trailing ! */
6984 OP_I32
, /* 1 .. 32 */
6985 OP_I32z
, /* 0 .. 32 */
6986 OP_I63
, /* 0 .. 63 */
6987 OP_I63s
, /* -64 .. 63 */
6988 OP_I64
, /* 1 .. 64 */
6989 OP_I64z
, /* 0 .. 64 */
6990 OP_I255
, /* 0 .. 255 */
6992 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6993 OP_I7b
, /* 0 .. 7 */
6994 OP_I15b
, /* 0 .. 15 */
6995 OP_I31b
, /* 0 .. 31 */
6997 OP_SH
, /* shifter operand */
6998 OP_SHG
, /* shifter operand with possible group relocation */
6999 OP_ADDR
, /* Memory address expression (any mode) */
7000 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7001 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7002 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7003 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7004 OP_EXP
, /* arbitrary expression */
7005 OP_EXPi
, /* same, with optional immediate prefix */
7006 OP_EXPr
, /* same, with optional relocation suffix */
7007 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7008 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7009 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7010 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7012 OP_CPSF
, /* CPS flags */
7013 OP_ENDI
, /* Endianness specifier */
7014 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7015 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7016 OP_COND
, /* conditional code */
7017 OP_TB
, /* Table branch. */
7019 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7021 OP_RRnpc_I0
, /* ARM register or literal 0 */
7022 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7023 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7024 OP_RF_IF
, /* FPA register or immediate */
7025 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7026 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7028 /* Optional operands. */
7029 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7030 OP_oI31b
, /* 0 .. 31 */
7031 OP_oI32b
, /* 1 .. 32 */
7032 OP_oI32z
, /* 0 .. 32 */
7033 OP_oIffffb
, /* 0 .. 65535 */
7034 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7036 OP_oRR
, /* ARM register */
7037 OP_oLR
, /* ARM LR register */
7038 OP_oRRnpc
, /* ARM register, not the PC */
7039 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7040 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7041 OP_oRND
, /* Optional Neon double precision register */
7042 OP_oRNQ
, /* Optional Neon quad precision register */
7043 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7044 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7045 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7046 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7048 OP_oSHll
, /* LSL immediate */
7049 OP_oSHar
, /* ASR immediate */
7050 OP_oSHllar
, /* LSL or ASR immediate */
7051 OP_oROR
, /* ROR 0/8/16/24 */
7052 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7054 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7056 /* Some pre-defined mixed (ARM/THUMB) operands. */
7057 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7058 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7059 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7061 OP_FIRST_OPTIONAL
= OP_oI7b
7064 /* Generic instruction operand parser. This does no encoding and no
7065 semantic validation; it merely squirrels values away in the inst
7066 structure. Returns SUCCESS or FAIL depending on whether the
7067 specified grammar matched. */
7069 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7071 unsigned const int *upat
= pattern
;
7072 char *backtrack_pos
= 0;
7073 const char *backtrack_error
= 0;
7074 int i
, val
= 0, backtrack_index
= 0;
7075 enum arm_reg_type rtype
;
7076 parse_operand_result result
;
7077 unsigned int op_parse_code
;
7078 bfd_boolean partial_match
;
7080 #define po_char_or_fail(chr) \
7083 if (skip_past_char (&str, chr) == FAIL) \
7088 #define po_reg_or_fail(regtype) \
7091 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7092 & inst.operands[i].vectype); \
7095 first_error (_(reg_expected_msgs[regtype])); \
7098 inst.operands[i].reg = val; \
7099 inst.operands[i].isreg = 1; \
7100 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7101 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7102 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7103 || rtype == REG_TYPE_VFD \
7104 || rtype == REG_TYPE_NQ); \
7105 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7109 #define po_reg_or_goto(regtype, label) \
7112 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7113 & inst.operands[i].vectype); \
7117 inst.operands[i].reg = val; \
7118 inst.operands[i].isreg = 1; \
7119 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7120 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7121 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7122 || rtype == REG_TYPE_VFD \
7123 || rtype == REG_TYPE_NQ); \
7124 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7128 #define po_imm_or_fail(min, max, popt) \
7131 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7133 inst.operands[i].imm = val; \
7137 #define po_scalar_or_goto(elsz, label, reg_type) \
7140 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7144 inst.operands[i].reg = val; \
7145 inst.operands[i].isscalar = 1; \
7149 #define po_misc_or_fail(expr) \
7157 #define po_misc_or_fail_no_backtrack(expr) \
7161 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7162 backtrack_pos = 0; \
7163 if (result != PARSE_OPERAND_SUCCESS) \
7168 #define po_barrier_or_imm(str) \
7171 val = parse_barrier (&str); \
7172 if (val == FAIL && ! ISALPHA (*str)) \
7175 /* ISB can only take SY as an option. */ \
7176 || ((inst.instruction & 0xf0) == 0x60 \
7179 inst.error = _("invalid barrier type"); \
7180 backtrack_pos = 0; \
7186 skip_whitespace (str
);
7188 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7190 op_parse_code
= upat
[i
];
7191 if (op_parse_code
>= 1<<16)
7192 op_parse_code
= thumb
? (op_parse_code
>> 16)
7193 : (op_parse_code
& ((1<<16)-1));
7195 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7197 /* Remember where we are in case we need to backtrack. */
7198 backtrack_pos
= str
;
7199 backtrack_error
= inst
.error
;
7200 backtrack_index
= i
;
7203 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7204 po_char_or_fail (',');
7206 switch (op_parse_code
)
7218 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7219 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7220 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7221 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7222 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7223 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7226 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7230 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7233 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7235 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7237 /* Also accept generic coprocessor regs for unknown registers. */
7239 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7241 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7242 existing register with a value of 0, this seems like the
7243 best way to parse P0. */
7245 if (strncasecmp (str
, "P0", 2) == 0)
7248 inst
.operands
[i
].isreg
= 1;
7249 inst
.operands
[i
].reg
= 13;
7254 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7255 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7256 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7257 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7258 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7259 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7260 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7261 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7262 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7263 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7266 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7269 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7270 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7272 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7277 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7281 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7283 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7286 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7288 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7291 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7293 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7298 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7301 po_reg_or_fail (REG_TYPE_NSDQ
);
7305 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7309 po_reg_or_fail (REG_TYPE_MQ
);
7311 /* Neon scalar. Using an element size of 8 means that some invalid
7312 scalars are accepted here, so deal with those in later code. */
7313 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7317 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7320 po_imm_or_fail (0, 0, TRUE
);
7325 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7329 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7334 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7337 if (parse_ifimm_zero (&str
))
7338 inst
.operands
[i
].imm
= 0;
7342 = _("only floating point zero is allowed as immediate value");
7350 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7353 po_reg_or_fail (REG_TYPE_RN
);
7357 case OP_RNSDQ_RNSC_MQ_RR
:
7358 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7361 case OP_RNSDQ_RNSC_MQ
:
7362 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7367 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7371 po_reg_or_fail (REG_TYPE_NSDQ
);
7378 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7381 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7384 po_reg_or_fail (REG_TYPE_NSD
);
7388 case OP_RNDQMQ_RNSC_RR
:
7389 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7392 case OP_RNDQ_RNSC_RR
:
7393 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7395 case OP_RNDQMQ_RNSC
:
7396 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7401 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7404 po_reg_or_fail (REG_TYPE_NDQ
);
7410 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7413 po_reg_or_fail (REG_TYPE_VFD
);
7418 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7419 not careful then bad things might happen. */
7420 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7423 case OP_RNDQMQ_Ibig
:
7424 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7429 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7432 /* There's a possibility of getting a 64-bit immediate here, so
7433 we need special handling. */
7434 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7437 inst
.error
= _("immediate value is out of range");
7443 case OP_RNDQMQ_I63b_RR
:
7444 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7447 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7452 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7455 po_imm_or_fail (0, 63, TRUE
);
7460 po_char_or_fail ('[');
7461 po_reg_or_fail (REG_TYPE_RN
);
7462 po_char_or_fail (']');
7468 po_reg_or_fail (REG_TYPE_RN
);
7469 if (skip_past_char (&str
, '!') == SUCCESS
)
7470 inst
.operands
[i
].writeback
= 1;
7474 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7475 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7476 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7477 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7478 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7479 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7480 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7481 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7482 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7483 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7484 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7485 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7487 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7489 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7490 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7492 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7493 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7494 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7495 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7497 /* Immediate variants */
7499 po_char_or_fail ('{');
7500 po_imm_or_fail (0, 255, TRUE
);
7501 po_char_or_fail ('}');
7505 /* The expression parser chokes on a trailing !, so we have
7506 to find it first and zap it. */
7509 while (*s
&& *s
!= ',')
7514 inst
.operands
[i
].writeback
= 1;
7516 po_imm_or_fail (0, 31, TRUE
);
7524 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7529 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7534 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7536 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7538 val
= parse_reloc (&str
);
7541 inst
.error
= _("unrecognized relocation suffix");
7544 else if (val
!= BFD_RELOC_UNUSED
)
7546 inst
.operands
[i
].imm
= val
;
7547 inst
.operands
[i
].hasreloc
= 1;
7553 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7555 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7557 inst
.operands
[i
].hasreloc
= 1;
7559 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7561 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7562 inst
.operands
[i
].hasreloc
= 0;
7566 /* Operand for MOVW or MOVT. */
7568 po_misc_or_fail (parse_half (&str
));
7571 /* Register or expression. */
7572 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7573 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7575 /* Register or immediate. */
7576 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7577 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7579 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7580 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7582 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7584 if (!is_immediate_prefix (*str
))
7587 val
= parse_fpa_immediate (&str
);
7590 /* FPA immediates are encoded as registers 8-15.
7591 parse_fpa_immediate has already applied the offset. */
7592 inst
.operands
[i
].reg
= val
;
7593 inst
.operands
[i
].isreg
= 1;
7596 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7597 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7599 /* Two kinds of register. */
7602 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7604 || (rege
->type
!= REG_TYPE_MMXWR
7605 && rege
->type
!= REG_TYPE_MMXWC
7606 && rege
->type
!= REG_TYPE_MMXWCG
))
7608 inst
.error
= _("iWMMXt data or control register expected");
7611 inst
.operands
[i
].reg
= rege
->number
;
7612 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7618 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7620 || (rege
->type
!= REG_TYPE_MMXWC
7621 && rege
->type
!= REG_TYPE_MMXWCG
))
7623 inst
.error
= _("iWMMXt control register expected");
7626 inst
.operands
[i
].reg
= rege
->number
;
7627 inst
.operands
[i
].isreg
= 1;
7632 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7633 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7634 case OP_oROR
: val
= parse_ror (&str
); break;
7636 case OP_COND
: val
= parse_cond (&str
); break;
7637 case OP_oBARRIER_I15
:
7638 po_barrier_or_imm (str
); break;
7640 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7646 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7647 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7649 inst
.error
= _("Banked registers are not available with this "
7655 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7659 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7662 val
= parse_sys_vldr_vstr (&str
);
7666 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7669 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7671 if (strncasecmp (str
, "APSR_", 5) == 0)
7678 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7679 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7680 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7681 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7682 default: found
= 16;
7686 inst
.operands
[i
].isvec
= 1;
7687 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7688 inst
.operands
[i
].reg
= REG_PC
;
7695 po_misc_or_fail (parse_tb (&str
));
7698 /* Register lists. */
7700 val
= parse_reg_list (&str
, REGLIST_RN
);
7703 inst
.operands
[i
].writeback
= 1;
7709 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7713 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7718 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7723 /* Allow Q registers too. */
7724 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7725 REGLIST_NEON_D
, &partial_match
);
7729 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7730 REGLIST_VFP_S
, &partial_match
);
7731 inst
.operands
[i
].issingle
= 1;
7736 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7737 REGLIST_VFP_D_VPR
, &partial_match
);
7738 if (val
== FAIL
&& !partial_match
)
7741 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7742 REGLIST_VFP_S_VPR
, &partial_match
);
7743 inst
.operands
[i
].issingle
= 1;
7748 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7749 REGLIST_NEON_D
, &partial_match
);
7754 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7755 1, &inst
.operands
[i
].vectype
);
7756 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7760 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7761 0, &inst
.operands
[i
].vectype
);
7764 /* Addressing modes */
7766 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7770 po_misc_or_fail (parse_address (&str
, i
));
7774 po_misc_or_fail_no_backtrack (
7775 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7779 po_misc_or_fail_no_backtrack (
7780 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7784 po_misc_or_fail_no_backtrack (
7785 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7789 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7793 po_misc_or_fail_no_backtrack (
7794 parse_shifter_operand_group_reloc (&str
, i
));
7798 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7802 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7806 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7811 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7816 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7819 po_reg_or_fail (REG_TYPE_ZR
);
7823 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7826 /* Various value-based sanity checks and shared operations. We
7827 do not signal immediate failures for the register constraints;
7828 this allows a syntax error to take precedence. */
7829 switch (op_parse_code
)
7837 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7838 inst
.error
= BAD_PC
;
7843 case OP_RRnpcsp_I32
:
7844 if (inst
.operands
[i
].isreg
)
7846 if (inst
.operands
[i
].reg
== REG_PC
)
7847 inst
.error
= BAD_PC
;
7848 else if (inst
.operands
[i
].reg
== REG_SP
7849 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7850 relaxed since ARMv8-A. */
7851 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7854 inst
.error
= BAD_SP
;
7860 if (inst
.operands
[i
].isreg
7861 && inst
.operands
[i
].reg
== REG_PC
7862 && (inst
.operands
[i
].writeback
|| thumb
))
7863 inst
.error
= BAD_PC
;
7868 if (inst
.operands
[i
].isreg
)
7878 case OP_oBARRIER_I15
:
7891 inst
.operands
[i
].imm
= val
;
7896 if (inst
.operands
[i
].reg
!= REG_LR
)
7897 inst
.error
= _("operand must be LR register");
7903 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7904 inst
.error
= BAD_PC
;
7908 if (inst
.operands
[i
].isreg
7909 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7910 inst
.error
= BAD_ODD
;
7914 if (inst
.operands
[i
].isreg
)
7916 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7917 inst
.error
= BAD_EVEN
;
7918 else if (inst
.operands
[i
].reg
== REG_SP
)
7919 as_tsktsk (MVE_BAD_SP
);
7920 else if (inst
.operands
[i
].reg
== REG_PC
)
7921 inst
.error
= BAD_PC
;
7929 /* If we get here, this operand was successfully parsed. */
7930 inst
.operands
[i
].present
= 1;
7934 inst
.error
= BAD_ARGS
;
7939 /* The parse routine should already have set inst.error, but set a
7940 default here just in case. */
7942 inst
.error
= BAD_SYNTAX
;
7946 /* Do not backtrack over a trailing optional argument that
7947 absorbed some text. We will only fail again, with the
7948 'garbage following instruction' error message, which is
7949 probably less helpful than the current one. */
7950 if (backtrack_index
== i
&& backtrack_pos
!= str
7951 && upat
[i
+1] == OP_stop
)
7954 inst
.error
= BAD_SYNTAX
;
7958 /* Try again, skipping the optional argument at backtrack_pos. */
7959 str
= backtrack_pos
;
7960 inst
.error
= backtrack_error
;
7961 inst
.operands
[backtrack_index
].present
= 0;
7962 i
= backtrack_index
;
7966 /* Check that we have parsed all the arguments. */
7967 if (*str
!= '\0' && !inst
.error
)
7968 inst
.error
= _("garbage following instruction");
7970 return inst
.error
? FAIL
: SUCCESS
;
7973 #undef po_char_or_fail
7974 #undef po_reg_or_fail
7975 #undef po_reg_or_goto
7976 #undef po_imm_or_fail
7977 #undef po_scalar_or_fail
7978 #undef po_barrier_or_imm
7980 /* Shorthand macro for instruction encoding functions issuing errors. */
7981 #define constraint(expr, err) \
7992 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7993 instructions are unpredictable if these registers are used. This
7994 is the BadReg predicate in ARM's Thumb-2 documentation.
7996 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7997 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7998 #define reject_bad_reg(reg) \
8000 if (reg == REG_PC) \
8002 inst.error = BAD_PC; \
8005 else if (reg == REG_SP \
8006 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8008 inst.error = BAD_SP; \
8013 /* If REG is R13 (the stack pointer), warn that its use is
8015 #define warn_deprecated_sp(reg) \
8017 if (warn_on_deprecated && reg == REG_SP) \
8018 as_tsktsk (_("use of r13 is deprecated")); \
8021 /* Functions for operand encoding. ARM, then Thumb. */
8023 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8025 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8027 The only binary encoding difference is the Coprocessor number. Coprocessor
8028 9 is used for half-precision calculations or conversions. The format of the
8029 instruction is the same as the equivalent Coprocessor 10 instruction that
8030 exists for Single-Precision operation. */
8033 do_scalar_fp16_v82_encode (void)
8035 if (inst
.cond
< COND_ALWAYS
)
8036 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8037 " the behaviour is UNPREDICTABLE"));
8038 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8041 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8042 mark_feature_used (&arm_ext_fp16
);
8045 /* If VAL can be encoded in the immediate field of an ARM instruction,
8046 return the encoded form. Otherwise, return FAIL. */
8049 encode_arm_immediate (unsigned int val
)
8056 for (i
= 2; i
< 32; i
+= 2)
8057 if ((a
= rotate_left (val
, i
)) <= 0xff)
8058 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8063 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8064 return the encoded form. Otherwise, return FAIL. */
8066 encode_thumb32_immediate (unsigned int val
)
8073 for (i
= 1; i
<= 24; i
++)
8076 if ((val
& ~(0xff << i
)) == 0)
8077 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8081 if (val
== ((a
<< 16) | a
))
8083 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8087 if (val
== ((a
<< 16) | a
))
8088 return 0x200 | (a
>> 8);
8092 /* Encode a VFP SP or DP register number into inst.instruction. */
8095 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8097 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8100 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8103 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8106 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8111 first_error (_("D register out of range for selected VFP version"));
8119 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8123 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8127 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8131 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8135 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8139 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8147 /* Encode a <shift> in an ARM-format instruction. The immediate,
8148 if any, is handled by md_apply_fix. */
8150 encode_arm_shift (int i
)
8152 /* register-shifted register. */
8153 if (inst
.operands
[i
].immisreg
)
8156 for (op_index
= 0; op_index
<= i
; ++op_index
)
8158 /* Check the operand only when it's presented. In pre-UAL syntax,
8159 if the destination register is the same as the first operand, two
8160 register form of the instruction can be used. */
8161 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8162 && inst
.operands
[op_index
].reg
== REG_PC
)
8163 as_warn (UNPRED_REG ("r15"));
8166 if (inst
.operands
[i
].imm
== REG_PC
)
8167 as_warn (UNPRED_REG ("r15"));
8170 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8171 inst
.instruction
|= SHIFT_ROR
<< 5;
8174 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8175 if (inst
.operands
[i
].immisreg
)
8177 inst
.instruction
|= SHIFT_BY_REG
;
8178 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8181 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8186 encode_arm_shifter_operand (int i
)
8188 if (inst
.operands
[i
].isreg
)
8190 inst
.instruction
|= inst
.operands
[i
].reg
;
8191 encode_arm_shift (i
);
8195 inst
.instruction
|= INST_IMMEDIATE
;
8196 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8197 inst
.instruction
|= inst
.operands
[i
].imm
;
8201 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8203 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8206 Generate an error if the operand is not a register. */
8207 constraint (!inst
.operands
[i
].isreg
,
8208 _("Instruction does not support =N addresses"));
8210 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8212 if (inst
.operands
[i
].preind
)
8216 inst
.error
= _("instruction does not accept preindexed addressing");
8219 inst
.instruction
|= PRE_INDEX
;
8220 if (inst
.operands
[i
].writeback
)
8221 inst
.instruction
|= WRITE_BACK
;
8224 else if (inst
.operands
[i
].postind
)
8226 gas_assert (inst
.operands
[i
].writeback
);
8228 inst
.instruction
|= WRITE_BACK
;
8230 else /* unindexed - only for coprocessor */
8232 inst
.error
= _("instruction does not accept unindexed addressing");
8236 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8237 && (((inst
.instruction
& 0x000f0000) >> 16)
8238 == ((inst
.instruction
& 0x0000f000) >> 12)))
8239 as_warn ((inst
.instruction
& LOAD_BIT
)
8240 ? _("destination register same as write-back base")
8241 : _("source register same as write-back base"));
8244 /* inst.operands[i] was set up by parse_address. Encode it into an
8245 ARM-format mode 2 load or store instruction. If is_t is true,
8246 reject forms that cannot be used with a T instruction (i.e. not
8249 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8251 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8253 encode_arm_addr_mode_common (i
, is_t
);
8255 if (inst
.operands
[i
].immisreg
)
8257 constraint ((inst
.operands
[i
].imm
== REG_PC
8258 || (is_pc
&& inst
.operands
[i
].writeback
)),
8260 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8261 inst
.instruction
|= inst
.operands
[i
].imm
;
8262 if (!inst
.operands
[i
].negative
)
8263 inst
.instruction
|= INDEX_UP
;
8264 if (inst
.operands
[i
].shifted
)
8266 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8267 inst
.instruction
|= SHIFT_ROR
<< 5;
8270 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8271 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8275 else /* immediate offset in inst.relocs[0] */
8277 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8279 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8281 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8282 cannot use PC in addressing.
8283 PC cannot be used in writeback addressing, either. */
8284 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8287 /* Use of PC in str is deprecated for ARMv7. */
8288 if (warn_on_deprecated
8290 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8291 as_tsktsk (_("use of PC in this instruction is deprecated"));
8294 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8296 /* Prefer + for zero encoded value. */
8297 if (!inst
.operands
[i
].negative
)
8298 inst
.instruction
|= INDEX_UP
;
8299 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8304 /* inst.operands[i] was set up by parse_address. Encode it into an
8305 ARM-format mode 3 load or store instruction. Reject forms that
8306 cannot be used with such instructions. If is_t is true, reject
8307 forms that cannot be used with a T instruction (i.e. not
8310 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8312 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8314 inst
.error
= _("instruction does not accept scaled register index");
8318 encode_arm_addr_mode_common (i
, is_t
);
8320 if (inst
.operands
[i
].immisreg
)
8322 constraint ((inst
.operands
[i
].imm
== REG_PC
8323 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8325 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8327 inst
.instruction
|= inst
.operands
[i
].imm
;
8328 if (!inst
.operands
[i
].negative
)
8329 inst
.instruction
|= INDEX_UP
;
8331 else /* immediate offset in inst.relocs[0] */
8333 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8334 && inst
.operands
[i
].writeback
),
8336 inst
.instruction
|= HWOFFSET_IMM
;
8337 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8339 /* Prefer + for zero encoded value. */
8340 if (!inst
.operands
[i
].negative
)
8341 inst
.instruction
|= INDEX_UP
;
8343 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8348 /* Write immediate bits [7:0] to the following locations:
8350 |28/24|23 19|18 16|15 4|3 0|
8351 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8353 This function is used by VMOV/VMVN/VORR/VBIC. */
8356 neon_write_immbits (unsigned immbits
)
8358 inst
.instruction
|= immbits
& 0xf;
8359 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8360 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8363 /* Invert low-order SIZE bits of XHI:XLO. */
8366 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8368 unsigned immlo
= xlo
? *xlo
: 0;
8369 unsigned immhi
= xhi
? *xhi
: 0;
8374 immlo
= (~immlo
) & 0xff;
8378 immlo
= (~immlo
) & 0xffff;
8382 immhi
= (~immhi
) & 0xffffffff;
8386 immlo
= (~immlo
) & 0xffffffff;
8400 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8404 neon_bits_same_in_bytes (unsigned imm
)
8406 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8407 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8408 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8409 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8412 /* For immediate of above form, return 0bABCD. */
8415 neon_squash_bits (unsigned imm
)
8417 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8418 | ((imm
& 0x01000000) >> 21);
8421 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8424 neon_qfloat_bits (unsigned imm
)
8426 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8429 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8430 the instruction. *OP is passed as the initial value of the op field, and
8431 may be set to a different value depending on the constant (i.e.
8432 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8433 MVN). If the immediate looks like a repeated pattern then also
8434 try smaller element sizes. */
8437 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8438 unsigned *immbits
, int *op
, int size
,
8439 enum neon_el_type type
)
8441 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8443 if (type
== NT_float
&& !float_p
)
8446 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8448 if (size
!= 32 || *op
== 1)
8450 *immbits
= neon_qfloat_bits (immlo
);
8456 if (neon_bits_same_in_bytes (immhi
)
8457 && neon_bits_same_in_bytes (immlo
))
8461 *immbits
= (neon_squash_bits (immhi
) << 4)
8462 | neon_squash_bits (immlo
);
8473 if (immlo
== (immlo
& 0x000000ff))
8478 else if (immlo
== (immlo
& 0x0000ff00))
8480 *immbits
= immlo
>> 8;
8483 else if (immlo
== (immlo
& 0x00ff0000))
8485 *immbits
= immlo
>> 16;
8488 else if (immlo
== (immlo
& 0xff000000))
8490 *immbits
= immlo
>> 24;
8493 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8495 *immbits
= (immlo
>> 8) & 0xff;
8498 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8500 *immbits
= (immlo
>> 16) & 0xff;
8504 if ((immlo
& 0xffff) != (immlo
>> 16))
8511 if (immlo
== (immlo
& 0x000000ff))
8516 else if (immlo
== (immlo
& 0x0000ff00))
8518 *immbits
= immlo
>> 8;
8522 if ((immlo
& 0xff) != (immlo
>> 8))
8527 if (immlo
== (immlo
& 0x000000ff))
8529 /* Don't allow MVN with 8-bit immediate. */
8539 #if defined BFD_HOST_64_BIT
8540 /* Returns TRUE if double precision value V may be cast
8541 to single precision without loss of accuracy. */
8544 is_double_a_single (bfd_int64_t v
)
8546 int exp
= (int)((v
>> 52) & 0x7FF);
8547 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8549 return (exp
== 0 || exp
== 0x7FF
8550 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8551 && (mantissa
& 0x1FFFFFFFl
) == 0;
8554 /* Returns a double precision value casted to single precision
8555 (ignoring the least significant bits in exponent and mantissa). */
8558 double_to_single (bfd_int64_t v
)
8560 int sign
= (int) ((v
>> 63) & 1l);
8561 int exp
= (int) ((v
>> 52) & 0x7FF);
8562 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8568 exp
= exp
- 1023 + 127;
8577 /* No denormalized numbers. */
8583 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8585 #endif /* BFD_HOST_64_BIT */
8594 static void do_vfp_nsyn_opcode (const char *);
8596 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8597 Determine whether it can be performed with a move instruction; if
8598 it can, convert inst.instruction to that move instruction and
8599 return TRUE; if it can't, convert inst.instruction to a literal-pool
8600 load and return FALSE. If this is not a valid thing to do in the
8601 current context, set inst.error and return TRUE.
8603 inst.operands[i] describes the destination register. */
8606 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8609 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8610 bfd_boolean arm_p
= (t
== CONST_ARM
);
8613 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8617 if ((inst
.instruction
& tbit
) == 0)
8619 inst
.error
= _("invalid pseudo operation");
8623 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8624 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8625 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8627 inst
.error
= _("constant expression expected");
8631 if (inst
.relocs
[0].exp
.X_op
== O_constant
8632 || inst
.relocs
[0].exp
.X_op
== O_big
)
8634 #if defined BFD_HOST_64_BIT
8639 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8641 LITTLENUM_TYPE w
[X_PRECISION
];
8644 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8646 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8648 /* FIXME: Should we check words w[2..5] ? */
8653 #if defined BFD_HOST_64_BIT
8655 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8656 << LITTLENUM_NUMBER_OF_BITS
)
8657 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8658 << LITTLENUM_NUMBER_OF_BITS
)
8659 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8660 << LITTLENUM_NUMBER_OF_BITS
)
8661 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8663 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8664 | (l
[0] & LITTLENUM_MASK
);
8668 v
= inst
.relocs
[0].exp
.X_add_number
;
8670 if (!inst
.operands
[i
].issingle
)
8674 /* LDR should not use lead in a flag-setting instruction being
8675 chosen so we do not check whether movs can be used. */
8677 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8678 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8679 && inst
.operands
[i
].reg
!= 13
8680 && inst
.operands
[i
].reg
!= 15)
8682 /* Check if on thumb2 it can be done with a mov.w, mvn or
8683 movw instruction. */
8684 unsigned int newimm
;
8685 bfd_boolean isNegated
;
8687 newimm
= encode_thumb32_immediate (v
);
8688 if (newimm
!= (unsigned int) FAIL
)
8692 newimm
= encode_thumb32_immediate (~v
);
8693 if (newimm
!= (unsigned int) FAIL
)
8697 /* The number can be loaded with a mov.w or mvn
8699 if (newimm
!= (unsigned int) FAIL
8700 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8702 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8703 | (inst
.operands
[i
].reg
<< 8));
8704 /* Change to MOVN. */
8705 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8706 inst
.instruction
|= (newimm
& 0x800) << 15;
8707 inst
.instruction
|= (newimm
& 0x700) << 4;
8708 inst
.instruction
|= (newimm
& 0x0ff);
8711 /* The number can be loaded with a movw instruction. */
8712 else if ((v
& ~0xFFFF) == 0
8713 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8715 int imm
= v
& 0xFFFF;
8717 inst
.instruction
= 0xf2400000; /* MOVW. */
8718 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8719 inst
.instruction
|= (imm
& 0xf000) << 4;
8720 inst
.instruction
|= (imm
& 0x0800) << 15;
8721 inst
.instruction
|= (imm
& 0x0700) << 4;
8722 inst
.instruction
|= (imm
& 0x00ff);
8723 /* In case this replacement is being done on Armv8-M
8724 Baseline we need to make sure to disable the
8725 instruction size check, as otherwise GAS will reject
8726 the use of this T32 instruction. */
8734 int value
= encode_arm_immediate (v
);
8738 /* This can be done with a mov instruction. */
8739 inst
.instruction
&= LITERAL_MASK
;
8740 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8741 inst
.instruction
|= value
& 0xfff;
8745 value
= encode_arm_immediate (~ v
);
8748 /* This can be done with a mvn instruction. */
8749 inst
.instruction
&= LITERAL_MASK
;
8750 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8751 inst
.instruction
|= value
& 0xfff;
8755 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8758 unsigned immbits
= 0;
8759 unsigned immlo
= inst
.operands
[1].imm
;
8760 unsigned immhi
= inst
.operands
[1].regisimm
8761 ? inst
.operands
[1].reg
8762 : inst
.relocs
[0].exp
.X_unsigned
8764 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8765 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8766 &op
, 64, NT_invtype
);
8770 neon_invert_size (&immlo
, &immhi
, 64);
8772 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8773 &op
, 64, NT_invtype
);
8778 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8784 /* Fill other bits in vmov encoding for both thumb and arm. */
8786 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8788 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8789 neon_write_immbits (immbits
);
8797 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8798 if (inst
.operands
[i
].issingle
8799 && is_quarter_float (inst
.operands
[1].imm
)
8800 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8802 inst
.operands
[1].imm
=
8803 neon_qfloat_bits (v
);
8804 do_vfp_nsyn_opcode ("fconsts");
8808 /* If our host does not support a 64-bit type then we cannot perform
8809 the following optimization. This mean that there will be a
8810 discrepancy between the output produced by an assembler built for
8811 a 32-bit-only host and the output produced from a 64-bit host, but
8812 this cannot be helped. */
8813 #if defined BFD_HOST_64_BIT
8814 else if (!inst
.operands
[1].issingle
8815 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8817 if (is_double_a_single (v
)
8818 && is_quarter_float (double_to_single (v
)))
8820 inst
.operands
[1].imm
=
8821 neon_qfloat_bits (double_to_single (v
));
8822 do_vfp_nsyn_opcode ("fconstd");
8830 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8831 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8834 inst
.operands
[1].reg
= REG_PC
;
8835 inst
.operands
[1].isreg
= 1;
8836 inst
.operands
[1].preind
= 1;
8837 inst
.relocs
[0].pc_rel
= 1;
8838 inst
.relocs
[0].type
= (thumb_p
8839 ? BFD_RELOC_ARM_THUMB_OFFSET
8841 ? BFD_RELOC_ARM_HWLITERAL
8842 : BFD_RELOC_ARM_LITERAL
));
8846 /* inst.operands[i] was set up by parse_address. Encode it into an
8847 ARM-format instruction. Reject all forms which cannot be encoded
8848 into a coprocessor load/store instruction. If wb_ok is false,
8849 reject use of writeback; if unind_ok is false, reject use of
8850 unindexed addressing. If reloc_override is not 0, use it instead
8851 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8852 (in which case it is preserved). */
8855 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8857 if (!inst
.operands
[i
].isreg
)
8860 if (! inst
.operands
[0].isvec
)
8862 inst
.error
= _("invalid co-processor operand");
8865 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8869 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8871 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8873 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8875 gas_assert (!inst
.operands
[i
].writeback
);
8878 inst
.error
= _("instruction does not support unindexed addressing");
8881 inst
.instruction
|= inst
.operands
[i
].imm
;
8882 inst
.instruction
|= INDEX_UP
;
8886 if (inst
.operands
[i
].preind
)
8887 inst
.instruction
|= PRE_INDEX
;
8889 if (inst
.operands
[i
].writeback
)
8891 if (inst
.operands
[i
].reg
== REG_PC
)
8893 inst
.error
= _("pc may not be used with write-back");
8898 inst
.error
= _("instruction does not support writeback");
8901 inst
.instruction
|= WRITE_BACK
;
8905 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8906 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8907 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8908 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8911 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8913 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8916 /* Prefer + for zero encoded value. */
8917 if (!inst
.operands
[i
].negative
)
8918 inst
.instruction
|= INDEX_UP
;
8923 /* Functions for instruction encoding, sorted by sub-architecture.
8924 First some generics; their names are taken from the conventional
8925 bit positions for register arguments in ARM format instructions. */
8935 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8941 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8947 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8948 inst
.instruction
|= inst
.operands
[1].reg
;
8954 inst
.instruction
|= inst
.operands
[0].reg
;
8955 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8961 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8962 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8968 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8969 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8975 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8976 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8980 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8982 if (ARM_CPU_IS_ANY (cpu_variant
))
8984 as_tsktsk ("%s", msg
);
8987 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8999 unsigned Rn
= inst
.operands
[2].reg
;
9000 /* Enforce restrictions on SWP instruction. */
9001 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9003 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9004 _("Rn must not overlap other operands"));
9006 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9008 if (!check_obsolete (&arm_ext_v8
,
9009 _("swp{b} use is obsoleted for ARMv8 and later"))
9010 && warn_on_deprecated
9011 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9012 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9015 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9016 inst
.instruction
|= inst
.operands
[1].reg
;
9017 inst
.instruction
|= Rn
<< 16;
9023 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9024 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9025 inst
.instruction
|= inst
.operands
[2].reg
;
9031 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9032 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9033 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9034 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9036 inst
.instruction
|= inst
.operands
[0].reg
;
9037 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9038 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9044 inst
.instruction
|= inst
.operands
[0].imm
;
9050 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9051 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9054 /* ARM instructions, in alphabetical order by function name (except
9055 that wrapper functions appear immediately after the function they
9058 /* This is a pseudo-op of the form "adr rd, label" to be converted
9059 into a relative address of the form "add rd, pc, #label-.-8". */
9064 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9066 /* Frag hacking will turn this into a sub instruction if the offset turns
9067 out to be negative. */
9068 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9069 inst
.relocs
[0].pc_rel
= 1;
9070 inst
.relocs
[0].exp
.X_add_number
-= 8;
9072 if (support_interwork
9073 && inst
.relocs
[0].exp
.X_op
== O_symbol
9074 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9075 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9076 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9077 inst
.relocs
[0].exp
.X_add_number
|= 1;
9080 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9081 into a relative address of the form:
9082 add rd, pc, #low(label-.-8)"
9083 add rd, rd, #high(label-.-8)" */
9088 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9090 /* Frag hacking will turn this into a sub instruction if the offset turns
9091 out to be negative. */
9092 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9093 inst
.relocs
[0].pc_rel
= 1;
9094 inst
.size
= INSN_SIZE
* 2;
9095 inst
.relocs
[0].exp
.X_add_number
-= 8;
9097 if (support_interwork
9098 && inst
.relocs
[0].exp
.X_op
== O_symbol
9099 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9100 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9101 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9102 inst
.relocs
[0].exp
.X_add_number
|= 1;
9108 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9109 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9111 if (!inst
.operands
[1].present
)
9112 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9113 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9114 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9115 encode_arm_shifter_operand (2);
9121 if (inst
.operands
[0].present
)
9122 inst
.instruction
|= inst
.operands
[0].imm
;
9124 inst
.instruction
|= 0xf;
9130 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9131 constraint (msb
> 32, _("bit-field extends past end of register"));
9132 /* The instruction encoding stores the LSB and MSB,
9133 not the LSB and width. */
9134 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9135 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9136 inst
.instruction
|= (msb
- 1) << 16;
9144 /* #0 in second position is alternative syntax for bfc, which is
9145 the same instruction but with REG_PC in the Rm field. */
9146 if (!inst
.operands
[1].isreg
)
9147 inst
.operands
[1].reg
= REG_PC
;
9149 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9150 constraint (msb
> 32, _("bit-field extends past end of register"));
9151 /* The instruction encoding stores the LSB and MSB,
9152 not the LSB and width. */
9153 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9154 inst
.instruction
|= inst
.operands
[1].reg
;
9155 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9156 inst
.instruction
|= (msb
- 1) << 16;
9162 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9163 _("bit-field extends past end of register"));
9164 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9165 inst
.instruction
|= inst
.operands
[1].reg
;
9166 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9167 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9170 /* ARM V5 breakpoint instruction (argument parse)
9171 BKPT <16 bit unsigned immediate>
9172 Instruction is not conditional.
9173 The bit pattern given in insns[] has the COND_ALWAYS condition,
9174 and it is an error if the caller tried to override that. */
9179 /* Top 12 of 16 bits to bits 19:8. */
9180 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9182 /* Bottom 4 of 16 bits to bits 3:0. */
9183 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9187 encode_branch (int default_reloc
)
9189 if (inst
.operands
[0].hasreloc
)
9191 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9192 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9193 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9194 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9195 ? BFD_RELOC_ARM_PLT32
9196 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9199 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9200 inst
.relocs
[0].pc_rel
= 1;
9207 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9208 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9211 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9218 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9220 if (inst
.cond
== COND_ALWAYS
)
9221 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9223 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9227 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9230 /* ARM V5 branch-link-exchange instruction (argument parse)
9231 BLX <target_addr> ie BLX(1)
9232 BLX{<condition>} <Rm> ie BLX(2)
9233 Unfortunately, there are two different opcodes for this mnemonic.
9234 So, the insns[].value is not used, and the code here zaps values
9235 into inst.instruction.
9236 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9241 if (inst
.operands
[0].isreg
)
9243 /* Arg is a register; the opcode provided by insns[] is correct.
9244 It is not illegal to do "blx pc", just useless. */
9245 if (inst
.operands
[0].reg
== REG_PC
)
9246 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9248 inst
.instruction
|= inst
.operands
[0].reg
;
9252 /* Arg is an address; this instruction cannot be executed
9253 conditionally, and the opcode must be adjusted.
9254 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9255 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9256 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9257 inst
.instruction
= 0xfa000000;
9258 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9265 bfd_boolean want_reloc
;
9267 if (inst
.operands
[0].reg
== REG_PC
)
9268 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9270 inst
.instruction
|= inst
.operands
[0].reg
;
9271 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9272 it is for ARMv4t or earlier. */
9273 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9274 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9275 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9279 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9284 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9288 /* ARM v5TEJ. Jump to Jazelle code. */
9293 if (inst
.operands
[0].reg
== REG_PC
)
9294 as_tsktsk (_("use of r15 in bxj is not really useful"));
9296 inst
.instruction
|= inst
.operands
[0].reg
;
9299 /* Co-processor data operation:
9300 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9301 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9305 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9306 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9307 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9308 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9309 inst
.instruction
|= inst
.operands
[4].reg
;
9310 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9316 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9317 encode_arm_shifter_operand (1);
9320 /* Transfer between coprocessor and ARM registers.
9321 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9326 No special properties. */
9328 struct deprecated_coproc_regs_s
9335 arm_feature_set deprecated
;
9336 arm_feature_set obsoleted
;
9337 const char *dep_msg
;
9338 const char *obs_msg
;
9341 #define DEPR_ACCESS_V8 \
9342 N_("This coprocessor register access is deprecated in ARMv8")
9344 /* Table of all deprecated coprocessor registers. */
9345 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9347 {15, 0, 7, 10, 5, /* CP15DMB. */
9348 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9349 DEPR_ACCESS_V8
, NULL
},
9350 {15, 0, 7, 10, 4, /* CP15DSB. */
9351 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9352 DEPR_ACCESS_V8
, NULL
},
9353 {15, 0, 7, 5, 4, /* CP15ISB. */
9354 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9355 DEPR_ACCESS_V8
, NULL
},
9356 {14, 6, 1, 0, 0, /* TEEHBR. */
9357 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9358 DEPR_ACCESS_V8
, NULL
},
9359 {14, 6, 0, 0, 0, /* TEECR. */
9360 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9361 DEPR_ACCESS_V8
, NULL
},
9364 #undef DEPR_ACCESS_V8
9366 static const size_t deprecated_coproc_reg_count
=
9367 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9375 Rd
= inst
.operands
[2].reg
;
9378 if (inst
.instruction
== 0xee000010
9379 || inst
.instruction
== 0xfe000010)
9381 reject_bad_reg (Rd
);
9382 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9384 constraint (Rd
== REG_SP
, BAD_SP
);
9389 if (inst
.instruction
== 0xe000010)
9390 constraint (Rd
== REG_PC
, BAD_PC
);
9393 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9395 const struct deprecated_coproc_regs_s
*r
=
9396 deprecated_coproc_regs
+ i
;
9398 if (inst
.operands
[0].reg
== r
->cp
9399 && inst
.operands
[1].imm
== r
->opc1
9400 && inst
.operands
[3].reg
== r
->crn
9401 && inst
.operands
[4].reg
== r
->crm
9402 && inst
.operands
[5].imm
== r
->opc2
)
9404 if (! ARM_CPU_IS_ANY (cpu_variant
)
9405 && warn_on_deprecated
9406 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9407 as_tsktsk ("%s", r
->dep_msg
);
9411 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9412 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9413 inst
.instruction
|= Rd
<< 12;
9414 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9415 inst
.instruction
|= inst
.operands
[4].reg
;
9416 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9419 /* Transfer between coprocessor register and pair of ARM registers.
9420 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9425 Two XScale instructions are special cases of these:
9427 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9428 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9430 Result unpredictable if Rd or Rn is R15. */
9437 Rd
= inst
.operands
[2].reg
;
9438 Rn
= inst
.operands
[3].reg
;
9442 reject_bad_reg (Rd
);
9443 reject_bad_reg (Rn
);
9447 constraint (Rd
== REG_PC
, BAD_PC
);
9448 constraint (Rn
== REG_PC
, BAD_PC
);
9451 /* Only check the MRRC{2} variants. */
9452 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9454 /* If Rd == Rn, error that the operation is
9455 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9456 constraint (Rd
== Rn
, BAD_OVERLAP
);
9459 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9460 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9461 inst
.instruction
|= Rd
<< 12;
9462 inst
.instruction
|= Rn
<< 16;
9463 inst
.instruction
|= inst
.operands
[4].reg
;
9469 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9470 if (inst
.operands
[1].present
)
9472 inst
.instruction
|= CPSI_MMOD
;
9473 inst
.instruction
|= inst
.operands
[1].imm
;
9480 inst
.instruction
|= inst
.operands
[0].imm
;
9486 unsigned Rd
, Rn
, Rm
;
9488 Rd
= inst
.operands
[0].reg
;
9489 Rn
= (inst
.operands
[1].present
9490 ? inst
.operands
[1].reg
: Rd
);
9491 Rm
= inst
.operands
[2].reg
;
9493 constraint ((Rd
== REG_PC
), BAD_PC
);
9494 constraint ((Rn
== REG_PC
), BAD_PC
);
9495 constraint ((Rm
== REG_PC
), BAD_PC
);
9497 inst
.instruction
|= Rd
<< 16;
9498 inst
.instruction
|= Rn
<< 0;
9499 inst
.instruction
|= Rm
<< 8;
9505 /* There is no IT instruction in ARM mode. We
9506 process it to do the validation as if in
9507 thumb mode, just in case the code gets
9508 assembled for thumb using the unified syntax. */
9513 set_pred_insn_type (IT_INSN
);
9514 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9515 now_pred
.cc
= inst
.operands
[0].imm
;
9519 /* If there is only one register in the register list,
9520 then return its register number. Otherwise return -1. */
9522 only_one_reg_in_list (int range
)
9524 int i
= ffs (range
) - 1;
9525 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9529 encode_ldmstm(int from_push_pop_mnem
)
9531 int base_reg
= inst
.operands
[0].reg
;
9532 int range
= inst
.operands
[1].imm
;
9535 inst
.instruction
|= base_reg
<< 16;
9536 inst
.instruction
|= range
;
9538 if (inst
.operands
[1].writeback
)
9539 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9541 if (inst
.operands
[0].writeback
)
9543 inst
.instruction
|= WRITE_BACK
;
9544 /* Check for unpredictable uses of writeback. */
9545 if (inst
.instruction
& LOAD_BIT
)
9547 /* Not allowed in LDM type 2. */
9548 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9549 && ((range
& (1 << REG_PC
)) == 0))
9550 as_warn (_("writeback of base register is UNPREDICTABLE"));
9551 /* Only allowed if base reg not in list for other types. */
9552 else if (range
& (1 << base_reg
))
9553 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9557 /* Not allowed for type 2. */
9558 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9559 as_warn (_("writeback of base register is UNPREDICTABLE"));
9560 /* Only allowed if base reg not in list, or first in list. */
9561 else if ((range
& (1 << base_reg
))
9562 && (range
& ((1 << base_reg
) - 1)))
9563 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9567 /* If PUSH/POP has only one register, then use the A2 encoding. */
9568 one_reg
= only_one_reg_in_list (range
);
9569 if (from_push_pop_mnem
&& one_reg
>= 0)
9571 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9573 if (is_push
&& one_reg
== 13 /* SP */)
9574 /* PR 22483: The A2 encoding cannot be used when
9575 pushing the stack pointer as this is UNPREDICTABLE. */
9578 inst
.instruction
&= A_COND_MASK
;
9579 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9580 inst
.instruction
|= one_reg
<< 12;
9587 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9590 /* ARMv5TE load-consecutive (argument parse)
9599 constraint (inst
.operands
[0].reg
% 2 != 0,
9600 _("first transfer register must be even"));
9601 constraint (inst
.operands
[1].present
9602 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9603 _("can only transfer two consecutive registers"));
9604 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9605 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9607 if (!inst
.operands
[1].present
)
9608 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9610 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9611 register and the first register written; we have to diagnose
9612 overlap between the base and the second register written here. */
9614 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9615 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9616 as_warn (_("base register written back, and overlaps "
9617 "second transfer register"));
9619 if (!(inst
.instruction
& V4_STR_BIT
))
9621 /* For an index-register load, the index register must not overlap the
9622 destination (even if not write-back). */
9623 if (inst
.operands
[2].immisreg
9624 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9625 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9626 as_warn (_("index register overlaps transfer register"));
9628 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9629 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9635 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9636 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9637 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9638 || inst
.operands
[1].negative
9639 /* This can arise if the programmer has written
9641 or if they have mistakenly used a register name as the last
9644 It is very difficult to distinguish between these two cases
9645 because "rX" might actually be a label. ie the register
9646 name has been occluded by a symbol of the same name. So we
9647 just generate a general 'bad addressing mode' type error
9648 message and leave it up to the programmer to discover the
9649 true cause and fix their mistake. */
9650 || (inst
.operands
[1].reg
== REG_PC
),
9653 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9654 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9655 _("offset must be zero in ARM encoding"));
9657 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9659 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9660 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9661 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9667 constraint (inst
.operands
[0].reg
% 2 != 0,
9668 _("even register required"));
9669 constraint (inst
.operands
[1].present
9670 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9671 _("can only load two consecutive registers"));
9672 /* If op 1 were present and equal to PC, this function wouldn't
9673 have been called in the first place. */
9674 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9676 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9677 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9680 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9681 which is not a multiple of four is UNPREDICTABLE. */
9683 check_ldr_r15_aligned (void)
9685 constraint (!(inst
.operands
[1].immisreg
)
9686 && (inst
.operands
[0].reg
== REG_PC
9687 && inst
.operands
[1].reg
== REG_PC
9688 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9689 _("ldr to register 15 must be 4-byte aligned"));
9695 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9696 if (!inst
.operands
[1].isreg
)
9697 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9699 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9700 check_ldr_r15_aligned ();
9706 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9708 if (inst
.operands
[1].preind
)
9710 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9711 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9712 _("this instruction requires a post-indexed address"));
9714 inst
.operands
[1].preind
= 0;
9715 inst
.operands
[1].postind
= 1;
9716 inst
.operands
[1].writeback
= 1;
9718 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9719 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9722 /* Halfword and signed-byte load/store operations. */
9727 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9728 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9729 if (!inst
.operands
[1].isreg
)
9730 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9732 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9738 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9740 if (inst
.operands
[1].preind
)
9742 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9743 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9744 _("this instruction requires a post-indexed address"));
9746 inst
.operands
[1].preind
= 0;
9747 inst
.operands
[1].postind
= 1;
9748 inst
.operands
[1].writeback
= 1;
9750 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9751 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9754 /* Co-processor register load/store.
9755 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9759 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9760 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9761 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9767 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9768 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9769 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9770 && !(inst
.instruction
& 0x00400000))
9771 as_tsktsk (_("Rd and Rm should be different in mla"));
9773 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9774 inst
.instruction
|= inst
.operands
[1].reg
;
9775 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9776 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9782 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9783 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9785 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9786 encode_arm_shifter_operand (1);
9789 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9796 top
= (inst
.instruction
& 0x00400000) != 0;
9797 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9798 _(":lower16: not allowed in this instruction"));
9799 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9800 _(":upper16: not allowed in this instruction"));
9801 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9802 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9804 imm
= inst
.relocs
[0].exp
.X_add_number
;
9805 /* The value is in two pieces: 0:11, 16:19. */
9806 inst
.instruction
|= (imm
& 0x00000fff);
9807 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9812 do_vfp_nsyn_mrs (void)
9814 if (inst
.operands
[0].isvec
)
9816 if (inst
.operands
[1].reg
!= 1)
9817 first_error (_("operand 1 must be FPSCR"));
9818 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9819 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9820 do_vfp_nsyn_opcode ("fmstat");
9822 else if (inst
.operands
[1].isvec
)
9823 do_vfp_nsyn_opcode ("fmrx");
9831 do_vfp_nsyn_msr (void)
9833 if (inst
.operands
[0].isvec
)
9834 do_vfp_nsyn_opcode ("fmxr");
9844 unsigned Rt
= inst
.operands
[0].reg
;
9846 if (thumb_mode
&& Rt
== REG_SP
)
9848 inst
.error
= BAD_SP
;
9852 switch (inst
.operands
[1].reg
)
9854 /* MVFR2 is only valid for Armv8-A. */
9856 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9860 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
9861 case 1: /* fpscr. */
9862 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9863 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9867 case 14: /* fpcxt_ns. */
9868 case 15: /* fpcxt_s. */
9869 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
9870 _("selected processor does not support instruction"));
9873 case 2: /* fpscr_nzcvqc. */
9876 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
9877 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9878 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9879 _("selected processor does not support instruction"));
9880 if (inst
.operands
[0].reg
!= 2
9881 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
9882 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
9889 /* APSR_ sets isvec. All other refs to PC are illegal. */
9890 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9892 inst
.error
= BAD_PC
;
9896 /* If we get through parsing the register name, we just insert the number
9897 generated into the instruction without further validation. */
9898 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9899 inst
.instruction
|= (Rt
<< 12);
9905 unsigned Rt
= inst
.operands
[1].reg
;
9908 reject_bad_reg (Rt
);
9909 else if (Rt
== REG_PC
)
9911 inst
.error
= BAD_PC
;
9915 switch (inst
.operands
[0].reg
)
9917 /* MVFR2 is only valid for Armv8-A. */
9919 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9923 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
9925 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9926 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9930 case 14: /* fpcxt_ns. */
9931 case 15: /* fpcxt_s. */
9932 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
9933 _("selected processor does not support instruction"));
9936 case 2: /* fpscr_nzcvqc. */
9939 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
9940 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9941 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9942 _("selected processor does not support instruction"));
9943 if (inst
.operands
[0].reg
!= 2
9944 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
9945 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
9952 /* If we get through parsing the register name, we just insert the number
9953 generated into the instruction without further validation. */
9954 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9955 inst
.instruction
|= (Rt
<< 12);
9963 if (do_vfp_nsyn_mrs () == SUCCESS
)
9966 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9967 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9969 if (inst
.operands
[1].isreg
)
9971 br
= inst
.operands
[1].reg
;
9972 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9973 as_bad (_("bad register for mrs"));
9977 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9978 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9980 _("'APSR', 'CPSR' or 'SPSR' expected"));
9981 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9984 inst
.instruction
|= br
;
9987 /* Two possible forms:
9988 "{C|S}PSR_<field>, Rm",
9989 "{C|S}PSR_f, #expression". */
9994 if (do_vfp_nsyn_msr () == SUCCESS
)
9997 inst
.instruction
|= inst
.operands
[0].imm
;
9998 if (inst
.operands
[1].isreg
)
9999 inst
.instruction
|= inst
.operands
[1].reg
;
10002 inst
.instruction
|= INST_IMMEDIATE
;
10003 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10004 inst
.relocs
[0].pc_rel
= 0;
10011 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10013 if (!inst
.operands
[2].present
)
10014 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10015 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10016 inst
.instruction
|= inst
.operands
[1].reg
;
10017 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10019 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10020 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10021 as_tsktsk (_("Rd and Rm should be different in mul"));
10024 /* Long Multiply Parser
10025 UMULL RdLo, RdHi, Rm, Rs
10026 SMULL RdLo, RdHi, Rm, Rs
10027 UMLAL RdLo, RdHi, Rm, Rs
10028 SMLAL RdLo, RdHi, Rm, Rs. */
10033 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10034 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10035 inst
.instruction
|= inst
.operands
[2].reg
;
10036 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10038 /* rdhi and rdlo must be different. */
10039 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10040 as_tsktsk (_("rdhi and rdlo must be different"));
10042 /* rdhi, rdlo and rm must all be different before armv6. */
10043 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10044 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10045 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10046 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10052 if (inst
.operands
[0].present
10053 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10055 /* Architectural NOP hints are CPSR sets with no bits selected. */
10056 inst
.instruction
&= 0xf0000000;
10057 inst
.instruction
|= 0x0320f000;
10058 if (inst
.operands
[0].present
)
10059 inst
.instruction
|= inst
.operands
[0].imm
;
10063 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10064 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10065 Condition defaults to COND_ALWAYS.
10066 Error if Rd, Rn or Rm are R15. */
10071 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10072 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10073 inst
.instruction
|= inst
.operands
[2].reg
;
10074 if (inst
.operands
[3].present
)
10075 encode_arm_shift (3);
10078 /* ARM V6 PKHTB (Argument Parse). */
10083 if (!inst
.operands
[3].present
)
10085 /* If the shift specifier is omitted, turn the instruction
10086 into pkhbt rd, rm, rn. */
10087 inst
.instruction
&= 0xfff00010;
10088 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10089 inst
.instruction
|= inst
.operands
[1].reg
;
10090 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10094 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10095 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10096 inst
.instruction
|= inst
.operands
[2].reg
;
10097 encode_arm_shift (3);
10101 /* ARMv5TE: Preload-Cache
10102 MP Extensions: Preload for write
10106 Syntactically, like LDR with B=1, W=0, L=1. */
10111 constraint (!inst
.operands
[0].isreg
,
10112 _("'[' expected after PLD mnemonic"));
10113 constraint (inst
.operands
[0].postind
,
10114 _("post-indexed expression used in preload instruction"));
10115 constraint (inst
.operands
[0].writeback
,
10116 _("writeback used in preload instruction"));
10117 constraint (!inst
.operands
[0].preind
,
10118 _("unindexed addressing used in preload instruction"));
10119 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10122 /* ARMv7: PLI <addr_mode> */
10126 constraint (!inst
.operands
[0].isreg
,
10127 _("'[' expected after PLI mnemonic"));
10128 constraint (inst
.operands
[0].postind
,
10129 _("post-indexed expression used in preload instruction"));
10130 constraint (inst
.operands
[0].writeback
,
10131 _("writeback used in preload instruction"));
10132 constraint (!inst
.operands
[0].preind
,
10133 _("unindexed addressing used in preload instruction"));
10134 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10135 inst
.instruction
&= ~PRE_INDEX
;
10141 constraint (inst
.operands
[0].writeback
,
10142 _("push/pop do not support {reglist}^"));
10143 inst
.operands
[1] = inst
.operands
[0];
10144 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10145 inst
.operands
[0].isreg
= 1;
10146 inst
.operands
[0].writeback
= 1;
10147 inst
.operands
[0].reg
= REG_SP
;
10148 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10151 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10152 word at the specified address and the following word
10154 Unconditionally executed.
10155 Error if Rn is R15. */
10160 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10161 if (inst
.operands
[0].writeback
)
10162 inst
.instruction
|= WRITE_BACK
;
10165 /* ARM V6 ssat (argument parse). */
10170 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10171 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10172 inst
.instruction
|= inst
.operands
[2].reg
;
10174 if (inst
.operands
[3].present
)
10175 encode_arm_shift (3);
10178 /* ARM V6 usat (argument parse). */
10183 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10184 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10185 inst
.instruction
|= inst
.operands
[2].reg
;
10187 if (inst
.operands
[3].present
)
10188 encode_arm_shift (3);
10191 /* ARM V6 ssat16 (argument parse). */
10196 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10197 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10198 inst
.instruction
|= inst
.operands
[2].reg
;
10204 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10205 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10206 inst
.instruction
|= inst
.operands
[2].reg
;
10209 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10210 preserving the other bits.
10212 setend <endian_specifier>, where <endian_specifier> is either
10218 if (warn_on_deprecated
10219 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10220 as_tsktsk (_("setend use is deprecated for ARMv8"));
10222 if (inst
.operands
[0].imm
)
10223 inst
.instruction
|= 0x200;
10229 unsigned int Rm
= (inst
.operands
[1].present
10230 ? inst
.operands
[1].reg
10231 : inst
.operands
[0].reg
);
10233 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10234 inst
.instruction
|= Rm
;
10235 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10237 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10238 inst
.instruction
|= SHIFT_BY_REG
;
10239 /* PR 12854: Error on extraneous shifts. */
10240 constraint (inst
.operands
[2].shifted
,
10241 _("extraneous shift as part of operand to shift insn"));
10244 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10250 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10251 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10253 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10254 inst
.relocs
[0].pc_rel
= 0;
10260 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10261 inst
.relocs
[0].pc_rel
= 0;
10267 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10268 inst
.relocs
[0].pc_rel
= 0;
10274 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10275 _("selected processor does not support SETPAN instruction"));
10277 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10283 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10284 _("selected processor does not support SETPAN instruction"));
10286 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10289 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10290 SMLAxy{cond} Rd,Rm,Rs,Rn
10291 SMLAWy{cond} Rd,Rm,Rs,Rn
10292 Error if any register is R15. */
10297 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10298 inst
.instruction
|= inst
.operands
[1].reg
;
10299 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10300 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10303 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10304 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10305 Error if any register is R15.
10306 Warning if Rdlo == Rdhi. */
10311 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10312 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10313 inst
.instruction
|= inst
.operands
[2].reg
;
10314 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10316 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10317 as_tsktsk (_("rdhi and rdlo must be different"));
10320 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10321 SMULxy{cond} Rd,Rm,Rs
10322 Error if any register is R15. */
10327 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10328 inst
.instruction
|= inst
.operands
[1].reg
;
10329 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10332 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10333 the same for both ARM and Thumb-2. */
10340 if (inst
.operands
[0].present
)
10342 reg
= inst
.operands
[0].reg
;
10343 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10348 inst
.instruction
|= reg
<< 16;
10349 inst
.instruction
|= inst
.operands
[1].imm
;
10350 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10351 inst
.instruction
|= WRITE_BACK
;
10354 /* ARM V6 strex (argument parse). */
10359 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10360 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10361 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10362 || inst
.operands
[2].negative
10363 /* See comment in do_ldrex(). */
10364 || (inst
.operands
[2].reg
== REG_PC
),
10367 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10368 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10370 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10371 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10372 _("offset must be zero in ARM encoding"));
10374 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10375 inst
.instruction
|= inst
.operands
[1].reg
;
10376 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10377 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10381 do_t_strexbh (void)
10383 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10384 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10385 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10386 || inst
.operands
[2].negative
,
10389 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10390 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10398 constraint (inst
.operands
[1].reg
% 2 != 0,
10399 _("even register required"));
10400 constraint (inst
.operands
[2].present
10401 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10402 _("can only store two consecutive registers"));
10403 /* If op 2 were present and equal to PC, this function wouldn't
10404 have been called in the first place. */
10405 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10407 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10408 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10409 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10412 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10413 inst
.instruction
|= inst
.operands
[1].reg
;
10414 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10421 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10422 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10430 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10431 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10436 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10437 extends it to 32-bits, and adds the result to a value in another
10438 register. You can specify a rotation by 0, 8, 16, or 24 bits
10439 before extracting the 16-bit value.
10440 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10441 Condition defaults to COND_ALWAYS.
10442 Error if any register uses R15. */
10447 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10448 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10449 inst
.instruction
|= inst
.operands
[2].reg
;
10450 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10455 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10456 Condition defaults to COND_ALWAYS.
10457 Error if any register uses R15. */
10462 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10463 inst
.instruction
|= inst
.operands
[1].reg
;
10464 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10467 /* VFP instructions. In a logical order: SP variant first, monad
10468 before dyad, arithmetic then move then load/store. */
10471 do_vfp_sp_monadic (void)
10473 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10474 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10477 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10478 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10482 do_vfp_sp_dyadic (void)
10484 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10485 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10486 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10490 do_vfp_sp_compare_z (void)
10492 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10496 do_vfp_dp_sp_cvt (void)
10498 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10499 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10503 do_vfp_sp_dp_cvt (void)
10505 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10506 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10510 do_vfp_reg_from_sp (void)
10512 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10513 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10516 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10517 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10521 do_vfp_reg2_from_sp2 (void)
10523 constraint (inst
.operands
[2].imm
!= 2,
10524 _("only two consecutive VFP SP registers allowed here"));
10525 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10526 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10527 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10531 do_vfp_sp_from_reg (void)
10533 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10534 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10537 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10538 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10542 do_vfp_sp2_from_reg2 (void)
10544 constraint (inst
.operands
[0].imm
!= 2,
10545 _("only two consecutive VFP SP registers allowed here"));
10546 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10547 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10548 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10552 do_vfp_sp_ldst (void)
10554 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10555 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10559 do_vfp_dp_ldst (void)
10561 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10562 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10567 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10569 if (inst
.operands
[0].writeback
)
10570 inst
.instruction
|= WRITE_BACK
;
10572 constraint (ldstm_type
!= VFP_LDSTMIA
,
10573 _("this addressing mode requires base-register writeback"));
10574 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10575 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10576 inst
.instruction
|= inst
.operands
[1].imm
;
10580 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10584 if (inst
.operands
[0].writeback
)
10585 inst
.instruction
|= WRITE_BACK
;
10587 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10588 _("this addressing mode requires base-register writeback"));
10590 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10591 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10593 count
= inst
.operands
[1].imm
<< 1;
10594 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10597 inst
.instruction
|= count
;
10601 do_vfp_sp_ldstmia (void)
10603 vfp_sp_ldstm (VFP_LDSTMIA
);
10607 do_vfp_sp_ldstmdb (void)
10609 vfp_sp_ldstm (VFP_LDSTMDB
);
10613 do_vfp_dp_ldstmia (void)
10615 vfp_dp_ldstm (VFP_LDSTMIA
);
10619 do_vfp_dp_ldstmdb (void)
10621 vfp_dp_ldstm (VFP_LDSTMDB
);
10625 do_vfp_xp_ldstmia (void)
10627 vfp_dp_ldstm (VFP_LDSTMIAX
);
10631 do_vfp_xp_ldstmdb (void)
10633 vfp_dp_ldstm (VFP_LDSTMDBX
);
10637 do_vfp_dp_rd_rm (void)
10639 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10640 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10643 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10644 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10648 do_vfp_dp_rn_rd (void)
10650 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10651 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10655 do_vfp_dp_rd_rn (void)
10657 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10658 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10662 do_vfp_dp_rd_rn_rm (void)
10664 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10665 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10668 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10669 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10670 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10674 do_vfp_dp_rd (void)
10676 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10680 do_vfp_dp_rm_rd_rn (void)
10682 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10683 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10686 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10687 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10688 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10691 /* VFPv3 instructions. */
10693 do_vfp_sp_const (void)
10695 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10696 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10697 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10701 do_vfp_dp_const (void)
10703 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10704 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10705 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10709 vfp_conv (int srcsize
)
10711 int immbits
= srcsize
- inst
.operands
[1].imm
;
10713 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10715 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10716 i.e. immbits must be in range 0 - 16. */
10717 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10720 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10722 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10723 i.e. immbits must be in range 0 - 31. */
10724 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10728 inst
.instruction
|= (immbits
& 1) << 5;
10729 inst
.instruction
|= (immbits
>> 1);
10733 do_vfp_sp_conv_16 (void)
10735 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10740 do_vfp_dp_conv_16 (void)
10742 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10747 do_vfp_sp_conv_32 (void)
10749 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10754 do_vfp_dp_conv_32 (void)
10756 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10760 /* FPA instructions. Also in a logical order. */
10765 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10766 inst
.instruction
|= inst
.operands
[1].reg
;
10770 do_fpa_ldmstm (void)
10772 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10773 switch (inst
.operands
[1].imm
)
10775 case 1: inst
.instruction
|= CP_T_X
; break;
10776 case 2: inst
.instruction
|= CP_T_Y
; break;
10777 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10782 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10784 /* The instruction specified "ea" or "fd", so we can only accept
10785 [Rn]{!}. The instruction does not really support stacking or
10786 unstacking, so we have to emulate these by setting appropriate
10787 bits and offsets. */
10788 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10789 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10790 _("this instruction does not support indexing"));
10792 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10793 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10795 if (!(inst
.instruction
& INDEX_UP
))
10796 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10798 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10800 inst
.operands
[2].preind
= 0;
10801 inst
.operands
[2].postind
= 1;
10805 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10808 /* iWMMXt instructions: strictly in alphabetical order. */
10811 do_iwmmxt_tandorc (void)
10813 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10817 do_iwmmxt_textrc (void)
10819 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10820 inst
.instruction
|= inst
.operands
[1].imm
;
10824 do_iwmmxt_textrm (void)
10826 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10827 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10828 inst
.instruction
|= inst
.operands
[2].imm
;
10832 do_iwmmxt_tinsr (void)
10834 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10835 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10836 inst
.instruction
|= inst
.operands
[2].imm
;
10840 do_iwmmxt_tmia (void)
10842 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10843 inst
.instruction
|= inst
.operands
[1].reg
;
10844 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10848 do_iwmmxt_waligni (void)
10850 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10851 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10852 inst
.instruction
|= inst
.operands
[2].reg
;
10853 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10857 do_iwmmxt_wmerge (void)
10859 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10860 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10861 inst
.instruction
|= inst
.operands
[2].reg
;
10862 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10866 do_iwmmxt_wmov (void)
10868 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10869 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10870 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10871 inst
.instruction
|= inst
.operands
[1].reg
;
10875 do_iwmmxt_wldstbh (void)
10878 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10880 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10882 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10883 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10887 do_iwmmxt_wldstw (void)
10889 /* RIWR_RIWC clears .isreg for a control register. */
10890 if (!inst
.operands
[0].isreg
)
10892 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10893 inst
.instruction
|= 0xf0000000;
10896 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10897 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10901 do_iwmmxt_wldstd (void)
10903 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10904 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10905 && inst
.operands
[1].immisreg
)
10907 inst
.instruction
&= ~0x1a000ff;
10908 inst
.instruction
|= (0xfU
<< 28);
10909 if (inst
.operands
[1].preind
)
10910 inst
.instruction
|= PRE_INDEX
;
10911 if (!inst
.operands
[1].negative
)
10912 inst
.instruction
|= INDEX_UP
;
10913 if (inst
.operands
[1].writeback
)
10914 inst
.instruction
|= WRITE_BACK
;
10915 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10916 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10917 inst
.instruction
|= inst
.operands
[1].imm
;
10920 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10924 do_iwmmxt_wshufh (void)
10926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10927 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10928 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10929 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10933 do_iwmmxt_wzero (void)
10935 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10936 inst
.instruction
|= inst
.operands
[0].reg
;
10937 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10938 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10942 do_iwmmxt_wrwrwr_or_imm5 (void)
10944 if (inst
.operands
[2].isreg
)
10947 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10948 _("immediate operand requires iWMMXt2"));
10950 if (inst
.operands
[2].imm
== 0)
10952 switch ((inst
.instruction
>> 20) & 0xf)
10958 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10959 inst
.operands
[2].imm
= 16;
10960 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10966 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10967 inst
.operands
[2].imm
= 32;
10968 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10975 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10977 wrn
= (inst
.instruction
>> 16) & 0xf;
10978 inst
.instruction
&= 0xff0fff0f;
10979 inst
.instruction
|= wrn
;
10980 /* Bail out here; the instruction is now assembled. */
10985 /* Map 32 -> 0, etc. */
10986 inst
.operands
[2].imm
&= 0x1f;
10987 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10991 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10992 operations first, then control, shift, and load/store. */
10994 /* Insns like "foo X,Y,Z". */
10997 do_mav_triple (void)
10999 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11000 inst
.instruction
|= inst
.operands
[1].reg
;
11001 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11004 /* Insns like "foo W,X,Y,Z".
11005 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11010 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11011 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11012 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11013 inst
.instruction
|= inst
.operands
[3].reg
;
11016 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11018 do_mav_dspsc (void)
11020 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11023 /* Maverick shift immediate instructions.
11024 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11025 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11028 do_mav_shift (void)
11030 int imm
= inst
.operands
[2].imm
;
11032 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11033 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11035 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11036 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11037 Bit 4 should be 0. */
11038 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11040 inst
.instruction
|= imm
;
11043 /* XScale instructions. Also sorted arithmetic before move. */
11045 /* Xscale multiply-accumulate (argument parse)
11048 MIAxycc acc0,Rm,Rs. */
11053 inst
.instruction
|= inst
.operands
[1].reg
;
11054 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11057 /* Xscale move-accumulator-register (argument parse)
11059 MARcc acc0,RdLo,RdHi. */
11064 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11065 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11068 /* Xscale move-register-accumulator (argument parse)
11070 MRAcc RdLo,RdHi,acc0. */
11075 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11076 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11077 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11080 /* Encoding functions relevant only to Thumb. */
11082 /* inst.operands[i] is a shifted-register operand; encode
11083 it into inst.instruction in the format used by Thumb32. */
11086 encode_thumb32_shifted_operand (int i
)
11088 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11089 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11091 constraint (inst
.operands
[i
].immisreg
,
11092 _("shift by register not allowed in thumb mode"));
11093 inst
.instruction
|= inst
.operands
[i
].reg
;
11094 if (shift
== SHIFT_RRX
)
11095 inst
.instruction
|= SHIFT_ROR
<< 4;
11098 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11099 _("expression too complex"));
11101 constraint (value
> 32
11102 || (value
== 32 && (shift
== SHIFT_LSL
11103 || shift
== SHIFT_ROR
)),
11104 _("shift expression is too large"));
11108 else if (value
== 32)
11111 inst
.instruction
|= shift
<< 4;
11112 inst
.instruction
|= (value
& 0x1c) << 10;
11113 inst
.instruction
|= (value
& 0x03) << 6;
11118 /* inst.operands[i] was set up by parse_address. Encode it into a
11119 Thumb32 format load or store instruction. Reject forms that cannot
11120 be used with such instructions. If is_t is true, reject forms that
11121 cannot be used with a T instruction; if is_d is true, reject forms
11122 that cannot be used with a D instruction. If it is a store insn,
11123 reject PC in Rn. */
11126 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11128 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11130 constraint (!inst
.operands
[i
].isreg
,
11131 _("Instruction does not support =N addresses"));
11133 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11134 if (inst
.operands
[i
].immisreg
)
11136 constraint (is_pc
, BAD_PC_ADDRESSING
);
11137 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11138 constraint (inst
.operands
[i
].negative
,
11139 _("Thumb does not support negative register indexing"));
11140 constraint (inst
.operands
[i
].postind
,
11141 _("Thumb does not support register post-indexing"));
11142 constraint (inst
.operands
[i
].writeback
,
11143 _("Thumb does not support register indexing with writeback"));
11144 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11145 _("Thumb supports only LSL in shifted register indexing"));
11147 inst
.instruction
|= inst
.operands
[i
].imm
;
11148 if (inst
.operands
[i
].shifted
)
11150 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11151 _("expression too complex"));
11152 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11153 || inst
.relocs
[0].exp
.X_add_number
> 3,
11154 _("shift out of range"));
11155 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11157 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11159 else if (inst
.operands
[i
].preind
)
11161 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11162 constraint (is_t
&& inst
.operands
[i
].writeback
,
11163 _("cannot use writeback with this instruction"));
11164 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11165 BAD_PC_ADDRESSING
);
11169 inst
.instruction
|= 0x01000000;
11170 if (inst
.operands
[i
].writeback
)
11171 inst
.instruction
|= 0x00200000;
11175 inst
.instruction
|= 0x00000c00;
11176 if (inst
.operands
[i
].writeback
)
11177 inst
.instruction
|= 0x00000100;
11179 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11181 else if (inst
.operands
[i
].postind
)
11183 gas_assert (inst
.operands
[i
].writeback
);
11184 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11185 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11188 inst
.instruction
|= 0x00200000;
11190 inst
.instruction
|= 0x00000900;
11191 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11193 else /* unindexed - only for coprocessor */
11194 inst
.error
= _("instruction does not accept unindexed addressing");
11197 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11198 encodings (the latter only in post-V6T2 cores). The index is the
11199 value used in the insns table below. When there is more than one
11200 possible 16-bit encoding for the instruction, this table always
11202 Also contains several pseudo-instructions used during relaxation. */
11203 #define T16_32_TAB \
11204 X(_adc, 4140, eb400000), \
11205 X(_adcs, 4140, eb500000), \
11206 X(_add, 1c00, eb000000), \
11207 X(_adds, 1c00, eb100000), \
11208 X(_addi, 0000, f1000000), \
11209 X(_addis, 0000, f1100000), \
11210 X(_add_pc,000f, f20f0000), \
11211 X(_add_sp,000d, f10d0000), \
11212 X(_adr, 000f, f20f0000), \
11213 X(_and, 4000, ea000000), \
11214 X(_ands, 4000, ea100000), \
11215 X(_asr, 1000, fa40f000), \
11216 X(_asrs, 1000, fa50f000), \
11217 X(_b, e000, f000b000), \
11218 X(_bcond, d000, f0008000), \
11219 X(_bf, 0000, f040e001), \
11220 X(_bfcsel,0000, f000e001), \
11221 X(_bfx, 0000, f060e001), \
11222 X(_bfl, 0000, f000c001), \
11223 X(_bflx, 0000, f070e001), \
11224 X(_bic, 4380, ea200000), \
11225 X(_bics, 4380, ea300000), \
11226 X(_cinc, 0000, ea509000), \
11227 X(_cinv, 0000, ea50a000), \
11228 X(_cmn, 42c0, eb100f00), \
11229 X(_cmp, 2800, ebb00f00), \
11230 X(_cneg, 0000, ea50b000), \
11231 X(_cpsie, b660, f3af8400), \
11232 X(_cpsid, b670, f3af8600), \
11233 X(_cpy, 4600, ea4f0000), \
11234 X(_csel, 0000, ea508000), \
11235 X(_cset, 0000, ea5f900f), \
11236 X(_csetm, 0000, ea5fa00f), \
11237 X(_csinc, 0000, ea509000), \
11238 X(_csinv, 0000, ea50a000), \
11239 X(_csneg, 0000, ea50b000), \
11240 X(_dec_sp,80dd, f1ad0d00), \
11241 X(_dls, 0000, f040e001), \
11242 X(_dlstp, 0000, f000e001), \
11243 X(_eor, 4040, ea800000), \
11244 X(_eors, 4040, ea900000), \
11245 X(_inc_sp,00dd, f10d0d00), \
11246 X(_lctp, 0000, f00fe001), \
11247 X(_ldmia, c800, e8900000), \
11248 X(_ldr, 6800, f8500000), \
11249 X(_ldrb, 7800, f8100000), \
11250 X(_ldrh, 8800, f8300000), \
11251 X(_ldrsb, 5600, f9100000), \
11252 X(_ldrsh, 5e00, f9300000), \
11253 X(_ldr_pc,4800, f85f0000), \
11254 X(_ldr_pc2,4800, f85f0000), \
11255 X(_ldr_sp,9800, f85d0000), \
11256 X(_le, 0000, f00fc001), \
11257 X(_letp, 0000, f01fc001), \
11258 X(_lsl, 0000, fa00f000), \
11259 X(_lsls, 0000, fa10f000), \
11260 X(_lsr, 0800, fa20f000), \
11261 X(_lsrs, 0800, fa30f000), \
11262 X(_mov, 2000, ea4f0000), \
11263 X(_movs, 2000, ea5f0000), \
11264 X(_mul, 4340, fb00f000), \
11265 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11266 X(_mvn, 43c0, ea6f0000), \
11267 X(_mvns, 43c0, ea7f0000), \
11268 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11269 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11270 X(_orr, 4300, ea400000), \
11271 X(_orrs, 4300, ea500000), \
11272 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11273 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11274 X(_rev, ba00, fa90f080), \
11275 X(_rev16, ba40, fa90f090), \
11276 X(_revsh, bac0, fa90f0b0), \
11277 X(_ror, 41c0, fa60f000), \
11278 X(_rors, 41c0, fa70f000), \
11279 X(_sbc, 4180, eb600000), \
11280 X(_sbcs, 4180, eb700000), \
11281 X(_stmia, c000, e8800000), \
11282 X(_str, 6000, f8400000), \
11283 X(_strb, 7000, f8000000), \
11284 X(_strh, 8000, f8200000), \
11285 X(_str_sp,9000, f84d0000), \
11286 X(_sub, 1e00, eba00000), \
11287 X(_subs, 1e00, ebb00000), \
11288 X(_subi, 8000, f1a00000), \
11289 X(_subis, 8000, f1b00000), \
11290 X(_sxtb, b240, fa4ff080), \
11291 X(_sxth, b200, fa0ff080), \
11292 X(_tst, 4200, ea100f00), \
11293 X(_uxtb, b2c0, fa5ff080), \
11294 X(_uxth, b280, fa1ff080), \
11295 X(_nop, bf00, f3af8000), \
11296 X(_yield, bf10, f3af8001), \
11297 X(_wfe, bf20, f3af8002), \
11298 X(_wfi, bf30, f3af8003), \
11299 X(_wls, 0000, f040c001), \
11300 X(_wlstp, 0000, f000c001), \
11301 X(_sev, bf40, f3af8004), \
11302 X(_sevl, bf50, f3af8005), \
11303 X(_udf, de00, f7f0a000)
11305 /* To catch errors in encoding functions, the codes are all offset by
11306 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11307 as 16-bit instructions. */
11308 #define X(a,b,c) T_MNEM##a
11309 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11312 #define X(a,b,c) 0x##b
11313 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11314 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11317 #define X(a,b,c) 0x##c
11318 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11319 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11320 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11324 /* Thumb instruction encoders, in alphabetical order. */
11326 /* ADDW or SUBW. */
11329 do_t_add_sub_w (void)
11333 Rd
= inst
.operands
[0].reg
;
11334 Rn
= inst
.operands
[1].reg
;
11336 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11337 is the SP-{plus,minus}-immediate form of the instruction. */
11339 constraint (Rd
== REG_PC
, BAD_PC
);
11341 reject_bad_reg (Rd
);
11343 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11344 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11347 /* Parse an add or subtract instruction. We get here with inst.instruction
11348 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11351 do_t_add_sub (void)
11355 Rd
= inst
.operands
[0].reg
;
11356 Rs
= (inst
.operands
[1].present
11357 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11358 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11361 set_pred_insn_type_last ();
11363 if (unified_syntax
)
11366 bfd_boolean narrow
;
11369 flags
= (inst
.instruction
== T_MNEM_adds
11370 || inst
.instruction
== T_MNEM_subs
);
11372 narrow
= !in_pred_block ();
11374 narrow
= in_pred_block ();
11375 if (!inst
.operands
[2].isreg
)
11379 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11380 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11382 add
= (inst
.instruction
== T_MNEM_add
11383 || inst
.instruction
== T_MNEM_adds
);
11385 if (inst
.size_req
!= 4)
11387 /* Attempt to use a narrow opcode, with relaxation if
11389 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11390 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11391 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11392 opcode
= T_MNEM_add_sp
;
11393 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11394 opcode
= T_MNEM_add_pc
;
11395 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11398 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11400 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11404 inst
.instruction
= THUMB_OP16(opcode
);
11405 inst
.instruction
|= (Rd
<< 4) | Rs
;
11406 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11407 || (inst
.relocs
[0].type
11408 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11410 if (inst
.size_req
== 2)
11411 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11413 inst
.relax
= opcode
;
11417 constraint (inst
.size_req
== 2, BAD_HIREG
);
11419 if (inst
.size_req
== 4
11420 || (inst
.size_req
!= 2 && !opcode
))
11422 constraint ((inst
.relocs
[0].type
11423 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11424 && (inst
.relocs
[0].type
11425 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11426 THUMB1_RELOC_ONLY
);
11429 constraint (add
, BAD_PC
);
11430 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11431 _("only SUBS PC, LR, #const allowed"));
11432 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11433 _("expression too complex"));
11434 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11435 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11436 _("immediate value out of range"));
11437 inst
.instruction
= T2_SUBS_PC_LR
11438 | inst
.relocs
[0].exp
.X_add_number
;
11439 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11442 else if (Rs
== REG_PC
)
11444 /* Always use addw/subw. */
11445 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11446 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11450 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11451 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11454 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11456 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11458 inst
.instruction
|= Rd
<< 8;
11459 inst
.instruction
|= Rs
<< 16;
11464 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11465 unsigned int shift
= inst
.operands
[2].shift_kind
;
11467 Rn
= inst
.operands
[2].reg
;
11468 /* See if we can do this with a 16-bit instruction. */
11469 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11471 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11476 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11477 || inst
.instruction
== T_MNEM_add
)
11479 : T_OPCODE_SUB_R3
);
11480 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11484 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11486 /* Thumb-1 cores (except v6-M) require at least one high
11487 register in a narrow non flag setting add. */
11488 if (Rd
> 7 || Rn
> 7
11489 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11490 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11497 inst
.instruction
= T_OPCODE_ADD_HI
;
11498 inst
.instruction
|= (Rd
& 8) << 4;
11499 inst
.instruction
|= (Rd
& 7);
11500 inst
.instruction
|= Rn
<< 3;
11506 constraint (Rd
== REG_PC
, BAD_PC
);
11507 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11508 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11509 constraint (Rs
== REG_PC
, BAD_PC
);
11510 reject_bad_reg (Rn
);
11512 /* If we get here, it can't be done in 16 bits. */
11513 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11514 _("shift must be constant"));
11515 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11516 inst
.instruction
|= Rd
<< 8;
11517 inst
.instruction
|= Rs
<< 16;
11518 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11519 _("shift value over 3 not allowed in thumb mode"));
11520 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11521 _("only LSL shift allowed in thumb mode"));
11522 encode_thumb32_shifted_operand (2);
11527 constraint (inst
.instruction
== T_MNEM_adds
11528 || inst
.instruction
== T_MNEM_subs
,
11531 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11533 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11534 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11537 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11538 ? 0x0000 : 0x8000);
11539 inst
.instruction
|= (Rd
<< 4) | Rs
;
11540 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11544 Rn
= inst
.operands
[2].reg
;
11545 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11547 /* We now have Rd, Rs, and Rn set to registers. */
11548 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11550 /* Can't do this for SUB. */
11551 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11552 inst
.instruction
= T_OPCODE_ADD_HI
;
11553 inst
.instruction
|= (Rd
& 8) << 4;
11554 inst
.instruction
|= (Rd
& 7);
11556 inst
.instruction
|= Rn
<< 3;
11558 inst
.instruction
|= Rs
<< 3;
11560 constraint (1, _("dest must overlap one source register"));
11564 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11565 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11566 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11576 Rd
= inst
.operands
[0].reg
;
11577 reject_bad_reg (Rd
);
11579 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11581 /* Defer to section relaxation. */
11582 inst
.relax
= inst
.instruction
;
11583 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11584 inst
.instruction
|= Rd
<< 4;
11586 else if (unified_syntax
&& inst
.size_req
!= 2)
11588 /* Generate a 32-bit opcode. */
11589 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11590 inst
.instruction
|= Rd
<< 8;
11591 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11592 inst
.relocs
[0].pc_rel
= 1;
11596 /* Generate a 16-bit opcode. */
11597 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11598 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11599 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11600 inst
.relocs
[0].pc_rel
= 1;
11601 inst
.instruction
|= Rd
<< 4;
11604 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11605 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11606 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11607 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11608 inst
.relocs
[0].exp
.X_add_number
+= 1;
11611 /* Arithmetic instructions for which there is just one 16-bit
11612 instruction encoding, and it allows only two low registers.
11613 For maximal compatibility with ARM syntax, we allow three register
11614 operands even when Thumb-32 instructions are not available, as long
11615 as the first two are identical. For instance, both "sbc r0,r1" and
11616 "sbc r0,r0,r1" are allowed. */
11622 Rd
= inst
.operands
[0].reg
;
11623 Rs
= (inst
.operands
[1].present
11624 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11625 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11626 Rn
= inst
.operands
[2].reg
;
11628 reject_bad_reg (Rd
);
11629 reject_bad_reg (Rs
);
11630 if (inst
.operands
[2].isreg
)
11631 reject_bad_reg (Rn
);
11633 if (unified_syntax
)
11635 if (!inst
.operands
[2].isreg
)
11637 /* For an immediate, we always generate a 32-bit opcode;
11638 section relaxation will shrink it later if possible. */
11639 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11640 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11641 inst
.instruction
|= Rd
<< 8;
11642 inst
.instruction
|= Rs
<< 16;
11643 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11647 bfd_boolean narrow
;
11649 /* See if we can do this with a 16-bit instruction. */
11650 if (THUMB_SETS_FLAGS (inst
.instruction
))
11651 narrow
= !in_pred_block ();
11653 narrow
= in_pred_block ();
11655 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11657 if (inst
.operands
[2].shifted
)
11659 if (inst
.size_req
== 4)
11665 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11666 inst
.instruction
|= Rd
;
11667 inst
.instruction
|= Rn
<< 3;
11671 /* If we get here, it can't be done in 16 bits. */
11672 constraint (inst
.operands
[2].shifted
11673 && inst
.operands
[2].immisreg
,
11674 _("shift must be constant"));
11675 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11676 inst
.instruction
|= Rd
<< 8;
11677 inst
.instruction
|= Rs
<< 16;
11678 encode_thumb32_shifted_operand (2);
11683 /* On its face this is a lie - the instruction does set the
11684 flags. However, the only supported mnemonic in this mode
11685 says it doesn't. */
11686 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11688 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11689 _("unshifted register required"));
11690 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11691 constraint (Rd
!= Rs
,
11692 _("dest and source1 must be the same register"));
11694 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11695 inst
.instruction
|= Rd
;
11696 inst
.instruction
|= Rn
<< 3;
11700 /* Similarly, but for instructions where the arithmetic operation is
11701 commutative, so we can allow either of them to be different from
11702 the destination operand in a 16-bit instruction. For instance, all
11703 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11710 Rd
= inst
.operands
[0].reg
;
11711 Rs
= (inst
.operands
[1].present
11712 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11713 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11714 Rn
= inst
.operands
[2].reg
;
11716 reject_bad_reg (Rd
);
11717 reject_bad_reg (Rs
);
11718 if (inst
.operands
[2].isreg
)
11719 reject_bad_reg (Rn
);
11721 if (unified_syntax
)
11723 if (!inst
.operands
[2].isreg
)
11725 /* For an immediate, we always generate a 32-bit opcode;
11726 section relaxation will shrink it later if possible. */
11727 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11728 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11729 inst
.instruction
|= Rd
<< 8;
11730 inst
.instruction
|= Rs
<< 16;
11731 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11735 bfd_boolean narrow
;
11737 /* See if we can do this with a 16-bit instruction. */
11738 if (THUMB_SETS_FLAGS (inst
.instruction
))
11739 narrow
= !in_pred_block ();
11741 narrow
= in_pred_block ();
11743 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11745 if (inst
.operands
[2].shifted
)
11747 if (inst
.size_req
== 4)
11754 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11755 inst
.instruction
|= Rd
;
11756 inst
.instruction
|= Rn
<< 3;
11761 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11762 inst
.instruction
|= Rd
;
11763 inst
.instruction
|= Rs
<< 3;
11768 /* If we get here, it can't be done in 16 bits. */
11769 constraint (inst
.operands
[2].shifted
11770 && inst
.operands
[2].immisreg
,
11771 _("shift must be constant"));
11772 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11773 inst
.instruction
|= Rd
<< 8;
11774 inst
.instruction
|= Rs
<< 16;
11775 encode_thumb32_shifted_operand (2);
11780 /* On its face this is a lie - the instruction does set the
11781 flags. However, the only supported mnemonic in this mode
11782 says it doesn't. */
11783 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11785 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11786 _("unshifted register required"));
11787 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11789 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11790 inst
.instruction
|= Rd
;
11793 inst
.instruction
|= Rn
<< 3;
11795 inst
.instruction
|= Rs
<< 3;
11797 constraint (1, _("dest must overlap one source register"));
11805 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11806 constraint (msb
> 32, _("bit-field extends past end of register"));
11807 /* The instruction encoding stores the LSB and MSB,
11808 not the LSB and width. */
11809 Rd
= inst
.operands
[0].reg
;
11810 reject_bad_reg (Rd
);
11811 inst
.instruction
|= Rd
<< 8;
11812 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11813 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11814 inst
.instruction
|= msb
- 1;
11823 Rd
= inst
.operands
[0].reg
;
11824 reject_bad_reg (Rd
);
11826 /* #0 in second position is alternative syntax for bfc, which is
11827 the same instruction but with REG_PC in the Rm field. */
11828 if (!inst
.operands
[1].isreg
)
11832 Rn
= inst
.operands
[1].reg
;
11833 reject_bad_reg (Rn
);
11836 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11837 constraint (msb
> 32, _("bit-field extends past end of register"));
11838 /* The instruction encoding stores the LSB and MSB,
11839 not the LSB and width. */
11840 inst
.instruction
|= Rd
<< 8;
11841 inst
.instruction
|= Rn
<< 16;
11842 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11843 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11844 inst
.instruction
|= msb
- 1;
11852 Rd
= inst
.operands
[0].reg
;
11853 Rn
= inst
.operands
[1].reg
;
11855 reject_bad_reg (Rd
);
11856 reject_bad_reg (Rn
);
11858 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11859 _("bit-field extends past end of register"));
11860 inst
.instruction
|= Rd
<< 8;
11861 inst
.instruction
|= Rn
<< 16;
11862 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11863 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11864 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11867 /* ARM V5 Thumb BLX (argument parse)
11868 BLX <target_addr> which is BLX(1)
11869 BLX <Rm> which is BLX(2)
11870 Unfortunately, there are two different opcodes for this mnemonic.
11871 So, the insns[].value is not used, and the code here zaps values
11872 into inst.instruction.
11874 ??? How to take advantage of the additional two bits of displacement
11875 available in Thumb32 mode? Need new relocation? */
11880 set_pred_insn_type_last ();
11882 if (inst
.operands
[0].isreg
)
11884 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11885 /* We have a register, so this is BLX(2). */
11886 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11890 /* No register. This must be BLX(1). */
11891 inst
.instruction
= 0xf000e800;
11892 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11901 bfd_reloc_code_real_type reloc
;
11904 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11906 if (in_pred_block ())
11908 /* Conditional branches inside IT blocks are encoded as unconditional
11910 cond
= COND_ALWAYS
;
11915 if (cond
!= COND_ALWAYS
)
11916 opcode
= T_MNEM_bcond
;
11918 opcode
= inst
.instruction
;
11921 && (inst
.size_req
== 4
11922 || (inst
.size_req
!= 2
11923 && (inst
.operands
[0].hasreloc
11924 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11926 inst
.instruction
= THUMB_OP32(opcode
);
11927 if (cond
== COND_ALWAYS
)
11928 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11931 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11932 _("selected architecture does not support "
11933 "wide conditional branch instruction"));
11935 gas_assert (cond
!= 0xF);
11936 inst
.instruction
|= cond
<< 22;
11937 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11942 inst
.instruction
= THUMB_OP16(opcode
);
11943 if (cond
== COND_ALWAYS
)
11944 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11947 inst
.instruction
|= cond
<< 8;
11948 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11950 /* Allow section relaxation. */
11951 if (unified_syntax
&& inst
.size_req
!= 2)
11952 inst
.relax
= opcode
;
11954 inst
.relocs
[0].type
= reloc
;
11955 inst
.relocs
[0].pc_rel
= 1;
11958 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11959 between the two is the maximum immediate allowed - which is passed in
11962 do_t_bkpt_hlt1 (int range
)
11964 constraint (inst
.cond
!= COND_ALWAYS
,
11965 _("instruction is always unconditional"));
11966 if (inst
.operands
[0].present
)
11968 constraint (inst
.operands
[0].imm
> range
,
11969 _("immediate value out of range"));
11970 inst
.instruction
|= inst
.operands
[0].imm
;
11973 set_pred_insn_type (NEUTRAL_IT_INSN
);
11979 do_t_bkpt_hlt1 (63);
11985 do_t_bkpt_hlt1 (255);
11989 do_t_branch23 (void)
11991 set_pred_insn_type_last ();
11992 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11994 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11995 this file. We used to simply ignore the PLT reloc type here --
11996 the branch encoding is now needed to deal with TLSCALL relocs.
11997 So if we see a PLT reloc now, put it back to how it used to be to
11998 keep the preexisting behaviour. */
11999 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12000 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12002 #if defined(OBJ_COFF)
12003 /* If the destination of the branch is a defined symbol which does not have
12004 the THUMB_FUNC attribute, then we must be calling a function which has
12005 the (interfacearm) attribute. We look for the Thumb entry point to that
12006 function and change the branch to refer to that function instead. */
12007 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12008 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12009 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12010 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12011 inst
.relocs
[0].exp
.X_add_symbol
12012 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12019 set_pred_insn_type_last ();
12020 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12021 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12022 should cause the alignment to be checked once it is known. This is
12023 because BX PC only works if the instruction is word aligned. */
12031 set_pred_insn_type_last ();
12032 Rm
= inst
.operands
[0].reg
;
12033 reject_bad_reg (Rm
);
12034 inst
.instruction
|= Rm
<< 16;
12043 Rd
= inst
.operands
[0].reg
;
12044 Rm
= inst
.operands
[1].reg
;
12046 reject_bad_reg (Rd
);
12047 reject_bad_reg (Rm
);
12049 inst
.instruction
|= Rd
<< 8;
12050 inst
.instruction
|= Rm
<< 16;
12051 inst
.instruction
|= Rm
;
12054 /* For the Armv8.1-M conditional instructions. */
12058 unsigned Rd
, Rn
, Rm
;
12061 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12063 Rd
= inst
.operands
[0].reg
;
12064 switch (inst
.instruction
)
12070 Rn
= inst
.operands
[1].reg
;
12071 Rm
= inst
.operands
[2].reg
;
12072 cond
= inst
.operands
[3].imm
;
12073 constraint (Rn
== REG_SP
, BAD_SP
);
12074 constraint (Rm
== REG_SP
, BAD_SP
);
12080 Rn
= inst
.operands
[1].reg
;
12081 cond
= inst
.operands
[2].imm
;
12082 /* Invert the last bit to invert the cond. */
12083 cond
= TOGGLE_BIT (cond
, 0);
12084 constraint (Rn
== REG_SP
, BAD_SP
);
12090 cond
= inst
.operands
[1].imm
;
12091 /* Invert the last bit to invert the cond. */
12092 cond
= TOGGLE_BIT (cond
, 0);
12100 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12101 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12102 inst
.instruction
|= Rd
<< 8;
12103 inst
.instruction
|= Rn
<< 16;
12104 inst
.instruction
|= Rm
;
12105 inst
.instruction
|= cond
<< 4;
12111 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12117 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12118 inst
.instruction
|= inst
.operands
[0].imm
;
12124 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12126 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12127 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12129 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12130 inst
.instruction
= 0xf3af8000;
12131 inst
.instruction
|= imod
<< 9;
12132 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12133 if (inst
.operands
[1].present
)
12134 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12138 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12139 && (inst
.operands
[0].imm
& 4),
12140 _("selected processor does not support 'A' form "
12141 "of this instruction"));
12142 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12143 _("Thumb does not support the 2-argument "
12144 "form of this instruction"));
12145 inst
.instruction
|= inst
.operands
[0].imm
;
12149 /* THUMB CPY instruction (argument parse). */
12154 if (inst
.size_req
== 4)
12156 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12157 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12158 inst
.instruction
|= inst
.operands
[1].reg
;
12162 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12163 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12164 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12171 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12172 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12173 inst
.instruction
|= inst
.operands
[0].reg
;
12174 inst
.relocs
[0].pc_rel
= 1;
12175 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12181 inst
.instruction
|= inst
.operands
[0].imm
;
12187 unsigned Rd
, Rn
, Rm
;
12189 Rd
= inst
.operands
[0].reg
;
12190 Rn
= (inst
.operands
[1].present
12191 ? inst
.operands
[1].reg
: Rd
);
12192 Rm
= inst
.operands
[2].reg
;
12194 reject_bad_reg (Rd
);
12195 reject_bad_reg (Rn
);
12196 reject_bad_reg (Rm
);
12198 inst
.instruction
|= Rd
<< 8;
12199 inst
.instruction
|= Rn
<< 16;
12200 inst
.instruction
|= Rm
;
12206 if (unified_syntax
&& inst
.size_req
== 4)
12207 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12209 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12215 unsigned int cond
= inst
.operands
[0].imm
;
12217 set_pred_insn_type (IT_INSN
);
12218 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12219 now_pred
.cc
= cond
;
12220 now_pred
.warn_deprecated
= FALSE
;
12221 now_pred
.type
= SCALAR_PRED
;
12223 /* If the condition is a negative condition, invert the mask. */
12224 if ((cond
& 0x1) == 0x0)
12226 unsigned int mask
= inst
.instruction
& 0x000f;
12228 if ((mask
& 0x7) == 0)
12230 /* No conversion needed. */
12231 now_pred
.block_length
= 1;
12233 else if ((mask
& 0x3) == 0)
12236 now_pred
.block_length
= 2;
12238 else if ((mask
& 0x1) == 0)
12241 now_pred
.block_length
= 3;
12246 now_pred
.block_length
= 4;
12249 inst
.instruction
&= 0xfff0;
12250 inst
.instruction
|= mask
;
12253 inst
.instruction
|= cond
<< 4;
12256 /* Helper function used for both push/pop and ldm/stm. */
12258 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12259 bfd_boolean writeback
)
12261 bfd_boolean load
, store
;
12263 gas_assert (base
!= -1 || !do_io
);
12264 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12265 store
= do_io
&& !load
;
12267 if (mask
& (1 << 13))
12268 inst
.error
= _("SP not allowed in register list");
12270 if (do_io
&& (mask
& (1 << base
)) != 0
12272 inst
.error
= _("having the base register in the register list when "
12273 "using write back is UNPREDICTABLE");
12277 if (mask
& (1 << 15))
12279 if (mask
& (1 << 14))
12280 inst
.error
= _("LR and PC should not both be in register list");
12282 set_pred_insn_type_last ();
12287 if (mask
& (1 << 15))
12288 inst
.error
= _("PC not allowed in register list");
12291 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12293 /* Single register transfers implemented as str/ldr. */
12296 if (inst
.instruction
& (1 << 23))
12297 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12299 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12303 if (inst
.instruction
& (1 << 23))
12304 inst
.instruction
= 0x00800000; /* ia -> [base] */
12306 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12309 inst
.instruction
|= 0xf8400000;
12311 inst
.instruction
|= 0x00100000;
12313 mask
= ffs (mask
) - 1;
12316 else if (writeback
)
12317 inst
.instruction
|= WRITE_BACK
;
12319 inst
.instruction
|= mask
;
12321 inst
.instruction
|= base
<< 16;
12327 /* This really doesn't seem worth it. */
12328 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12329 _("expression too complex"));
12330 constraint (inst
.operands
[1].writeback
,
12331 _("Thumb load/store multiple does not support {reglist}^"));
12333 if (unified_syntax
)
12335 bfd_boolean narrow
;
12339 /* See if we can use a 16-bit instruction. */
12340 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12341 && inst
.size_req
!= 4
12342 && !(inst
.operands
[1].imm
& ~0xff))
12344 mask
= 1 << inst
.operands
[0].reg
;
12346 if (inst
.operands
[0].reg
<= 7)
12348 if (inst
.instruction
== T_MNEM_stmia
12349 ? inst
.operands
[0].writeback
12350 : (inst
.operands
[0].writeback
12351 == !(inst
.operands
[1].imm
& mask
)))
12353 if (inst
.instruction
== T_MNEM_stmia
12354 && (inst
.operands
[1].imm
& mask
)
12355 && (inst
.operands
[1].imm
& (mask
- 1)))
12356 as_warn (_("value stored for r%d is UNKNOWN"),
12357 inst
.operands
[0].reg
);
12359 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12360 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12361 inst
.instruction
|= inst
.operands
[1].imm
;
12364 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12366 /* This means 1 register in reg list one of 3 situations:
12367 1. Instruction is stmia, but without writeback.
12368 2. lmdia without writeback, but with Rn not in
12370 3. ldmia with writeback, but with Rn in reglist.
12371 Case 3 is UNPREDICTABLE behaviour, so we handle
12372 case 1 and 2 which can be converted into a 16-bit
12373 str or ldr. The SP cases are handled below. */
12374 unsigned long opcode
;
12375 /* First, record an error for Case 3. */
12376 if (inst
.operands
[1].imm
& mask
12377 && inst
.operands
[0].writeback
)
12379 _("having the base register in the register list when "
12380 "using write back is UNPREDICTABLE");
12382 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12384 inst
.instruction
= THUMB_OP16 (opcode
);
12385 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12386 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12390 else if (inst
.operands
[0] .reg
== REG_SP
)
12392 if (inst
.operands
[0].writeback
)
12395 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12396 ? T_MNEM_push
: T_MNEM_pop
);
12397 inst
.instruction
|= inst
.operands
[1].imm
;
12400 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12403 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12404 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12405 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12413 if (inst
.instruction
< 0xffff)
12414 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12416 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12417 inst
.operands
[1].imm
,
12418 inst
.operands
[0].writeback
);
12423 constraint (inst
.operands
[0].reg
> 7
12424 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12425 constraint (inst
.instruction
!= T_MNEM_ldmia
12426 && inst
.instruction
!= T_MNEM_stmia
,
12427 _("Thumb-2 instruction only valid in unified syntax"));
12428 if (inst
.instruction
== T_MNEM_stmia
)
12430 if (!inst
.operands
[0].writeback
)
12431 as_warn (_("this instruction will write back the base register"));
12432 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12433 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12434 as_warn (_("value stored for r%d is UNKNOWN"),
12435 inst
.operands
[0].reg
);
12439 if (!inst
.operands
[0].writeback
12440 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12441 as_warn (_("this instruction will write back the base register"));
12442 else if (inst
.operands
[0].writeback
12443 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12444 as_warn (_("this instruction will not write back the base register"));
12447 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12448 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12449 inst
.instruction
|= inst
.operands
[1].imm
;
12456 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12457 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12458 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12459 || inst
.operands
[1].negative
,
12462 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12464 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12465 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12466 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12472 if (!inst
.operands
[1].present
)
12474 constraint (inst
.operands
[0].reg
== REG_LR
,
12475 _("r14 not allowed as first register "
12476 "when second register is omitted"));
12477 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12479 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12482 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12483 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12484 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12490 unsigned long opcode
;
12493 if (inst
.operands
[0].isreg
12494 && !inst
.operands
[0].preind
12495 && inst
.operands
[0].reg
== REG_PC
)
12496 set_pred_insn_type_last ();
12498 opcode
= inst
.instruction
;
12499 if (unified_syntax
)
12501 if (!inst
.operands
[1].isreg
)
12503 if (opcode
<= 0xffff)
12504 inst
.instruction
= THUMB_OP32 (opcode
);
12505 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12508 if (inst
.operands
[1].isreg
12509 && !inst
.operands
[1].writeback
12510 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12511 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12512 && opcode
<= 0xffff
12513 && inst
.size_req
!= 4)
12515 /* Insn may have a 16-bit form. */
12516 Rn
= inst
.operands
[1].reg
;
12517 if (inst
.operands
[1].immisreg
)
12519 inst
.instruction
= THUMB_OP16 (opcode
);
12521 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12523 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12524 reject_bad_reg (inst
.operands
[1].imm
);
12526 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12527 && opcode
!= T_MNEM_ldrsb
)
12528 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12529 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12536 if (inst
.relocs
[0].pc_rel
)
12537 opcode
= T_MNEM_ldr_pc2
;
12539 opcode
= T_MNEM_ldr_pc
;
12543 if (opcode
== T_MNEM_ldr
)
12544 opcode
= T_MNEM_ldr_sp
;
12546 opcode
= T_MNEM_str_sp
;
12548 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12552 inst
.instruction
= inst
.operands
[0].reg
;
12553 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12555 inst
.instruction
|= THUMB_OP16 (opcode
);
12556 if (inst
.size_req
== 2)
12557 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12559 inst
.relax
= opcode
;
12563 /* Definitely a 32-bit variant. */
12565 /* Warning for Erratum 752419. */
12566 if (opcode
== T_MNEM_ldr
12567 && inst
.operands
[0].reg
== REG_SP
12568 && inst
.operands
[1].writeback
== 1
12569 && !inst
.operands
[1].immisreg
)
12571 if (no_cpu_selected ()
12572 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12573 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12574 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12575 as_warn (_("This instruction may be unpredictable "
12576 "if executed on M-profile cores "
12577 "with interrupts enabled."));
12580 /* Do some validations regarding addressing modes. */
12581 if (inst
.operands
[1].immisreg
)
12582 reject_bad_reg (inst
.operands
[1].imm
);
12584 constraint (inst
.operands
[1].writeback
== 1
12585 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12588 inst
.instruction
= THUMB_OP32 (opcode
);
12589 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12590 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12591 check_ldr_r15_aligned ();
12595 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12597 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12599 /* Only [Rn,Rm] is acceptable. */
12600 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12601 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12602 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12603 || inst
.operands
[1].negative
,
12604 _("Thumb does not support this addressing mode"));
12605 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12609 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12610 if (!inst
.operands
[1].isreg
)
12611 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12614 constraint (!inst
.operands
[1].preind
12615 || inst
.operands
[1].shifted
12616 || inst
.operands
[1].writeback
,
12617 _("Thumb does not support this addressing mode"));
12618 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12620 constraint (inst
.instruction
& 0x0600,
12621 _("byte or halfword not valid for base register"));
12622 constraint (inst
.operands
[1].reg
== REG_PC
12623 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12624 _("r15 based store not allowed"));
12625 constraint (inst
.operands
[1].immisreg
,
12626 _("invalid base register for register offset"));
12628 if (inst
.operands
[1].reg
== REG_PC
)
12629 inst
.instruction
= T_OPCODE_LDR_PC
;
12630 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12631 inst
.instruction
= T_OPCODE_LDR_SP
;
12633 inst
.instruction
= T_OPCODE_STR_SP
;
12635 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12636 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12640 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12641 if (!inst
.operands
[1].immisreg
)
12643 /* Immediate offset. */
12644 inst
.instruction
|= inst
.operands
[0].reg
;
12645 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12646 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12650 /* Register offset. */
12651 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12652 constraint (inst
.operands
[1].negative
,
12653 _("Thumb does not support this addressing mode"));
12656 switch (inst
.instruction
)
12658 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12659 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12660 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12661 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12662 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12663 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12664 case 0x5600 /* ldrsb */:
12665 case 0x5e00 /* ldrsh */: break;
12669 inst
.instruction
|= inst
.operands
[0].reg
;
12670 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12671 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12677 if (!inst
.operands
[1].present
)
12679 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12680 constraint (inst
.operands
[0].reg
== REG_LR
,
12681 _("r14 not allowed here"));
12682 constraint (inst
.operands
[0].reg
== REG_R12
,
12683 _("r12 not allowed here"));
12686 if (inst
.operands
[2].writeback
12687 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12688 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12689 as_warn (_("base register written back, and overlaps "
12690 "one of transfer registers"));
12692 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12693 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12694 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12700 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12701 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12707 unsigned Rd
, Rn
, Rm
, Ra
;
12709 Rd
= inst
.operands
[0].reg
;
12710 Rn
= inst
.operands
[1].reg
;
12711 Rm
= inst
.operands
[2].reg
;
12712 Ra
= inst
.operands
[3].reg
;
12714 reject_bad_reg (Rd
);
12715 reject_bad_reg (Rn
);
12716 reject_bad_reg (Rm
);
12717 reject_bad_reg (Ra
);
12719 inst
.instruction
|= Rd
<< 8;
12720 inst
.instruction
|= Rn
<< 16;
12721 inst
.instruction
|= Rm
;
12722 inst
.instruction
|= Ra
<< 12;
12728 unsigned RdLo
, RdHi
, Rn
, Rm
;
12730 RdLo
= inst
.operands
[0].reg
;
12731 RdHi
= inst
.operands
[1].reg
;
12732 Rn
= inst
.operands
[2].reg
;
12733 Rm
= inst
.operands
[3].reg
;
12735 reject_bad_reg (RdLo
);
12736 reject_bad_reg (RdHi
);
12737 reject_bad_reg (Rn
);
12738 reject_bad_reg (Rm
);
12740 inst
.instruction
|= RdLo
<< 12;
12741 inst
.instruction
|= RdHi
<< 8;
12742 inst
.instruction
|= Rn
<< 16;
12743 inst
.instruction
|= Rm
;
12747 do_t_mov_cmp (void)
12751 Rn
= inst
.operands
[0].reg
;
12752 Rm
= inst
.operands
[1].reg
;
12755 set_pred_insn_type_last ();
12757 if (unified_syntax
)
12759 int r0off
= (inst
.instruction
== T_MNEM_mov
12760 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12761 unsigned long opcode
;
12762 bfd_boolean narrow
;
12763 bfd_boolean low_regs
;
12765 low_regs
= (Rn
<= 7 && Rm
<= 7);
12766 opcode
= inst
.instruction
;
12767 if (in_pred_block ())
12768 narrow
= opcode
!= T_MNEM_movs
;
12770 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12771 if (inst
.size_req
== 4
12772 || inst
.operands
[1].shifted
)
12775 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12776 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12777 && !inst
.operands
[1].shifted
12781 inst
.instruction
= T2_SUBS_PC_LR
;
12785 if (opcode
== T_MNEM_cmp
)
12787 constraint (Rn
== REG_PC
, BAD_PC
);
12790 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12792 warn_deprecated_sp (Rm
);
12793 /* R15 was documented as a valid choice for Rm in ARMv6,
12794 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12795 tools reject R15, so we do too. */
12796 constraint (Rm
== REG_PC
, BAD_PC
);
12799 reject_bad_reg (Rm
);
12801 else if (opcode
== T_MNEM_mov
12802 || opcode
== T_MNEM_movs
)
12804 if (inst
.operands
[1].isreg
)
12806 if (opcode
== T_MNEM_movs
)
12808 reject_bad_reg (Rn
);
12809 reject_bad_reg (Rm
);
12813 /* This is mov.n. */
12814 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12815 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12817 as_tsktsk (_("Use of r%u as a source register is "
12818 "deprecated when r%u is the destination "
12819 "register."), Rm
, Rn
);
12824 /* This is mov.w. */
12825 constraint (Rn
== REG_PC
, BAD_PC
);
12826 constraint (Rm
== REG_PC
, BAD_PC
);
12827 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12828 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12832 reject_bad_reg (Rn
);
12835 if (!inst
.operands
[1].isreg
)
12837 /* Immediate operand. */
12838 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12840 if (low_regs
&& narrow
)
12842 inst
.instruction
= THUMB_OP16 (opcode
);
12843 inst
.instruction
|= Rn
<< 8;
12844 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12845 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12847 if (inst
.size_req
== 2)
12848 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12850 inst
.relax
= opcode
;
12855 constraint ((inst
.relocs
[0].type
12856 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12857 && (inst
.relocs
[0].type
12858 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12859 THUMB1_RELOC_ONLY
);
12861 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12862 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12863 inst
.instruction
|= Rn
<< r0off
;
12864 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12867 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12868 && (inst
.instruction
== T_MNEM_mov
12869 || inst
.instruction
== T_MNEM_movs
))
12871 /* Register shifts are encoded as separate shift instructions. */
12872 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12874 if (in_pred_block ())
12879 if (inst
.size_req
== 4)
12882 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12888 switch (inst
.operands
[1].shift_kind
)
12891 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12894 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12897 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12900 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12906 inst
.instruction
= opcode
;
12909 inst
.instruction
|= Rn
;
12910 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12915 inst
.instruction
|= CONDS_BIT
;
12917 inst
.instruction
|= Rn
<< 8;
12918 inst
.instruction
|= Rm
<< 16;
12919 inst
.instruction
|= inst
.operands
[1].imm
;
12924 /* Some mov with immediate shift have narrow variants.
12925 Register shifts are handled above. */
12926 if (low_regs
&& inst
.operands
[1].shifted
12927 && (inst
.instruction
== T_MNEM_mov
12928 || inst
.instruction
== T_MNEM_movs
))
12930 if (in_pred_block ())
12931 narrow
= (inst
.instruction
== T_MNEM_mov
);
12933 narrow
= (inst
.instruction
== T_MNEM_movs
);
12938 switch (inst
.operands
[1].shift_kind
)
12940 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12941 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12942 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12943 default: narrow
= FALSE
; break;
12949 inst
.instruction
|= Rn
;
12950 inst
.instruction
|= Rm
<< 3;
12951 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12955 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12956 inst
.instruction
|= Rn
<< r0off
;
12957 encode_thumb32_shifted_operand (1);
12961 switch (inst
.instruction
)
12964 /* In v4t or v5t a move of two lowregs produces unpredictable
12965 results. Don't allow this. */
12968 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12969 "MOV Rd, Rs with two low registers is not "
12970 "permitted on this architecture");
12971 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12975 inst
.instruction
= T_OPCODE_MOV_HR
;
12976 inst
.instruction
|= (Rn
& 0x8) << 4;
12977 inst
.instruction
|= (Rn
& 0x7);
12978 inst
.instruction
|= Rm
<< 3;
12982 /* We know we have low registers at this point.
12983 Generate LSLS Rd, Rs, #0. */
12984 inst
.instruction
= T_OPCODE_LSL_I
;
12985 inst
.instruction
|= Rn
;
12986 inst
.instruction
|= Rm
<< 3;
12992 inst
.instruction
= T_OPCODE_CMP_LR
;
12993 inst
.instruction
|= Rn
;
12994 inst
.instruction
|= Rm
<< 3;
12998 inst
.instruction
= T_OPCODE_CMP_HR
;
12999 inst
.instruction
|= (Rn
& 0x8) << 4;
13000 inst
.instruction
|= (Rn
& 0x7);
13001 inst
.instruction
|= Rm
<< 3;
13008 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13010 /* PR 10443: Do not silently ignore shifted operands. */
13011 constraint (inst
.operands
[1].shifted
,
13012 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13014 if (inst
.operands
[1].isreg
)
13016 if (Rn
< 8 && Rm
< 8)
13018 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13019 since a MOV instruction produces unpredictable results. */
13020 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13021 inst
.instruction
= T_OPCODE_ADD_I3
;
13023 inst
.instruction
= T_OPCODE_CMP_LR
;
13025 inst
.instruction
|= Rn
;
13026 inst
.instruction
|= Rm
<< 3;
13030 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13031 inst
.instruction
= T_OPCODE_MOV_HR
;
13033 inst
.instruction
= T_OPCODE_CMP_HR
;
13039 constraint (Rn
> 7,
13040 _("only lo regs allowed with immediate"));
13041 inst
.instruction
|= Rn
<< 8;
13042 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13053 top
= (inst
.instruction
& 0x00800000) != 0;
13054 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13056 constraint (top
, _(":lower16: not allowed in this instruction"));
13057 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13059 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13061 constraint (!top
, _(":upper16: not allowed in this instruction"));
13062 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13065 Rd
= inst
.operands
[0].reg
;
13066 reject_bad_reg (Rd
);
13068 inst
.instruction
|= Rd
<< 8;
13069 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13071 imm
= inst
.relocs
[0].exp
.X_add_number
;
13072 inst
.instruction
|= (imm
& 0xf000) << 4;
13073 inst
.instruction
|= (imm
& 0x0800) << 15;
13074 inst
.instruction
|= (imm
& 0x0700) << 4;
13075 inst
.instruction
|= (imm
& 0x00ff);
13080 do_t_mvn_tst (void)
13084 Rn
= inst
.operands
[0].reg
;
13085 Rm
= inst
.operands
[1].reg
;
13087 if (inst
.instruction
== T_MNEM_cmp
13088 || inst
.instruction
== T_MNEM_cmn
)
13089 constraint (Rn
== REG_PC
, BAD_PC
);
13091 reject_bad_reg (Rn
);
13092 reject_bad_reg (Rm
);
13094 if (unified_syntax
)
13096 int r0off
= (inst
.instruction
== T_MNEM_mvn
13097 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13098 bfd_boolean narrow
;
13100 if (inst
.size_req
== 4
13101 || inst
.instruction
> 0xffff
13102 || inst
.operands
[1].shifted
13103 || Rn
> 7 || Rm
> 7)
13105 else if (inst
.instruction
== T_MNEM_cmn
13106 || inst
.instruction
== T_MNEM_tst
)
13108 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13109 narrow
= !in_pred_block ();
13111 narrow
= in_pred_block ();
13113 if (!inst
.operands
[1].isreg
)
13115 /* For an immediate, we always generate a 32-bit opcode;
13116 section relaxation will shrink it later if possible. */
13117 if (inst
.instruction
< 0xffff)
13118 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13119 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13120 inst
.instruction
|= Rn
<< r0off
;
13121 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13125 /* See if we can do this with a 16-bit instruction. */
13128 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13129 inst
.instruction
|= Rn
;
13130 inst
.instruction
|= Rm
<< 3;
13134 constraint (inst
.operands
[1].shifted
13135 && inst
.operands
[1].immisreg
,
13136 _("shift must be constant"));
13137 if (inst
.instruction
< 0xffff)
13138 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13139 inst
.instruction
|= Rn
<< r0off
;
13140 encode_thumb32_shifted_operand (1);
13146 constraint (inst
.instruction
> 0xffff
13147 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13148 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13149 _("unshifted register required"));
13150 constraint (Rn
> 7 || Rm
> 7,
13153 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13154 inst
.instruction
|= Rn
;
13155 inst
.instruction
|= Rm
<< 3;
13164 if (do_vfp_nsyn_mrs () == SUCCESS
)
13167 Rd
= inst
.operands
[0].reg
;
13168 reject_bad_reg (Rd
);
13169 inst
.instruction
|= Rd
<< 8;
13171 if (inst
.operands
[1].isreg
)
13173 unsigned br
= inst
.operands
[1].reg
;
13174 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13175 as_bad (_("bad register for mrs"));
13177 inst
.instruction
|= br
& (0xf << 16);
13178 inst
.instruction
|= (br
& 0x300) >> 4;
13179 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13183 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13185 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13187 /* PR gas/12698: The constraint is only applied for m_profile.
13188 If the user has specified -march=all, we want to ignore it as
13189 we are building for any CPU type, including non-m variants. */
13190 bfd_boolean m_profile
=
13191 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13192 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13193 "not support requested special purpose register"));
13196 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13198 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13199 _("'APSR', 'CPSR' or 'SPSR' expected"));
13201 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13202 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13203 inst
.instruction
|= 0xf0000;
13213 if (do_vfp_nsyn_msr () == SUCCESS
)
13216 constraint (!inst
.operands
[1].isreg
,
13217 _("Thumb encoding does not support an immediate here"));
13219 if (inst
.operands
[0].isreg
)
13220 flags
= (int)(inst
.operands
[0].reg
);
13222 flags
= inst
.operands
[0].imm
;
13224 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13226 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13228 /* PR gas/12698: The constraint is only applied for m_profile.
13229 If the user has specified -march=all, we want to ignore it as
13230 we are building for any CPU type, including non-m variants. */
13231 bfd_boolean m_profile
=
13232 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13233 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13234 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13235 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13236 && bits
!= PSR_f
)) && m_profile
,
13237 _("selected processor does not support requested special "
13238 "purpose register"));
13241 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13242 "requested special purpose register"));
13244 Rn
= inst
.operands
[1].reg
;
13245 reject_bad_reg (Rn
);
13247 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13248 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13249 inst
.instruction
|= (flags
& 0x300) >> 4;
13250 inst
.instruction
|= (flags
& 0xff);
13251 inst
.instruction
|= Rn
<< 16;
13257 bfd_boolean narrow
;
13258 unsigned Rd
, Rn
, Rm
;
13260 if (!inst
.operands
[2].present
)
13261 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13263 Rd
= inst
.operands
[0].reg
;
13264 Rn
= inst
.operands
[1].reg
;
13265 Rm
= inst
.operands
[2].reg
;
13267 if (unified_syntax
)
13269 if (inst
.size_req
== 4
13275 else if (inst
.instruction
== T_MNEM_muls
)
13276 narrow
= !in_pred_block ();
13278 narrow
= in_pred_block ();
13282 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13283 constraint (Rn
> 7 || Rm
> 7,
13290 /* 16-bit MULS/Conditional MUL. */
13291 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13292 inst
.instruction
|= Rd
;
13295 inst
.instruction
|= Rm
<< 3;
13297 inst
.instruction
|= Rn
<< 3;
13299 constraint (1, _("dest must overlap one source register"));
13303 constraint (inst
.instruction
!= T_MNEM_mul
,
13304 _("Thumb-2 MUL must not set flags"));
13306 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13307 inst
.instruction
|= Rd
<< 8;
13308 inst
.instruction
|= Rn
<< 16;
13309 inst
.instruction
|= Rm
<< 0;
13311 reject_bad_reg (Rd
);
13312 reject_bad_reg (Rn
);
13313 reject_bad_reg (Rm
);
13320 unsigned RdLo
, RdHi
, Rn
, Rm
;
13322 RdLo
= inst
.operands
[0].reg
;
13323 RdHi
= inst
.operands
[1].reg
;
13324 Rn
= inst
.operands
[2].reg
;
13325 Rm
= inst
.operands
[3].reg
;
13327 reject_bad_reg (RdLo
);
13328 reject_bad_reg (RdHi
);
13329 reject_bad_reg (Rn
);
13330 reject_bad_reg (Rm
);
13332 inst
.instruction
|= RdLo
<< 12;
13333 inst
.instruction
|= RdHi
<< 8;
13334 inst
.instruction
|= Rn
<< 16;
13335 inst
.instruction
|= Rm
;
13338 as_tsktsk (_("rdhi and rdlo must be different"));
13344 set_pred_insn_type (NEUTRAL_IT_INSN
);
13346 if (unified_syntax
)
13348 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13350 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13351 inst
.instruction
|= inst
.operands
[0].imm
;
13355 /* PR9722: Check for Thumb2 availability before
13356 generating a thumb2 nop instruction. */
13357 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13359 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13360 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13363 inst
.instruction
= 0x46c0;
13368 constraint (inst
.operands
[0].present
,
13369 _("Thumb does not support NOP with hints"));
13370 inst
.instruction
= 0x46c0;
13377 if (unified_syntax
)
13379 bfd_boolean narrow
;
13381 if (THUMB_SETS_FLAGS (inst
.instruction
))
13382 narrow
= !in_pred_block ();
13384 narrow
= in_pred_block ();
13385 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13387 if (inst
.size_req
== 4)
13392 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13393 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13394 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13398 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13399 inst
.instruction
|= inst
.operands
[0].reg
;
13400 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13405 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13407 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13409 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13410 inst
.instruction
|= inst
.operands
[0].reg
;
13411 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13420 Rd
= inst
.operands
[0].reg
;
13421 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13423 reject_bad_reg (Rd
);
13424 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13425 reject_bad_reg (Rn
);
13427 inst
.instruction
|= Rd
<< 8;
13428 inst
.instruction
|= Rn
<< 16;
13430 if (!inst
.operands
[2].isreg
)
13432 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13433 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13439 Rm
= inst
.operands
[2].reg
;
13440 reject_bad_reg (Rm
);
13442 constraint (inst
.operands
[2].shifted
13443 && inst
.operands
[2].immisreg
,
13444 _("shift must be constant"));
13445 encode_thumb32_shifted_operand (2);
13452 unsigned Rd
, Rn
, Rm
;
13454 Rd
= inst
.operands
[0].reg
;
13455 Rn
= inst
.operands
[1].reg
;
13456 Rm
= inst
.operands
[2].reg
;
13458 reject_bad_reg (Rd
);
13459 reject_bad_reg (Rn
);
13460 reject_bad_reg (Rm
);
13462 inst
.instruction
|= Rd
<< 8;
13463 inst
.instruction
|= Rn
<< 16;
13464 inst
.instruction
|= Rm
;
13465 if (inst
.operands
[3].present
)
13467 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13468 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13469 _("expression too complex"));
13470 inst
.instruction
|= (val
& 0x1c) << 10;
13471 inst
.instruction
|= (val
& 0x03) << 6;
13478 if (!inst
.operands
[3].present
)
13482 inst
.instruction
&= ~0x00000020;
13484 /* PR 10168. Swap the Rm and Rn registers. */
13485 Rtmp
= inst
.operands
[1].reg
;
13486 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13487 inst
.operands
[2].reg
= Rtmp
;
13495 if (inst
.operands
[0].immisreg
)
13496 reject_bad_reg (inst
.operands
[0].imm
);
13498 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13502 do_t_push_pop (void)
13506 constraint (inst
.operands
[0].writeback
,
13507 _("push/pop do not support {reglist}^"));
13508 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13509 _("expression too complex"));
13511 mask
= inst
.operands
[0].imm
;
13512 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13513 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13514 else if (inst
.size_req
!= 4
13515 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13516 ? REG_LR
: REG_PC
)))
13518 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13519 inst
.instruction
|= THUMB_PP_PC_LR
;
13520 inst
.instruction
|= mask
& 0xff;
13522 else if (unified_syntax
)
13524 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13525 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13529 inst
.error
= _("invalid register list to push/pop instruction");
13537 if (unified_syntax
)
13538 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13541 inst
.error
= _("invalid register list to push/pop instruction");
13547 do_t_vscclrm (void)
13549 if (inst
.operands
[0].issingle
)
13551 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13552 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13553 inst
.instruction
|= inst
.operands
[0].imm
;
13557 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13558 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13559 inst
.instruction
|= 1 << 8;
13560 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13569 Rd
= inst
.operands
[0].reg
;
13570 Rm
= inst
.operands
[1].reg
;
13572 reject_bad_reg (Rd
);
13573 reject_bad_reg (Rm
);
13575 inst
.instruction
|= Rd
<< 8;
13576 inst
.instruction
|= Rm
<< 16;
13577 inst
.instruction
|= Rm
;
13585 Rd
= inst
.operands
[0].reg
;
13586 Rm
= inst
.operands
[1].reg
;
13588 reject_bad_reg (Rd
);
13589 reject_bad_reg (Rm
);
13591 if (Rd
<= 7 && Rm
<= 7
13592 && inst
.size_req
!= 4)
13594 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13595 inst
.instruction
|= Rd
;
13596 inst
.instruction
|= Rm
<< 3;
13598 else if (unified_syntax
)
13600 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13601 inst
.instruction
|= Rd
<< 8;
13602 inst
.instruction
|= Rm
<< 16;
13603 inst
.instruction
|= Rm
;
13606 inst
.error
= BAD_HIREG
;
13614 Rd
= inst
.operands
[0].reg
;
13615 Rm
= inst
.operands
[1].reg
;
13617 reject_bad_reg (Rd
);
13618 reject_bad_reg (Rm
);
13620 inst
.instruction
|= Rd
<< 8;
13621 inst
.instruction
|= Rm
;
13629 Rd
= inst
.operands
[0].reg
;
13630 Rs
= (inst
.operands
[1].present
13631 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13632 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13634 reject_bad_reg (Rd
);
13635 reject_bad_reg (Rs
);
13636 if (inst
.operands
[2].isreg
)
13637 reject_bad_reg (inst
.operands
[2].reg
);
13639 inst
.instruction
|= Rd
<< 8;
13640 inst
.instruction
|= Rs
<< 16;
13641 if (!inst
.operands
[2].isreg
)
13643 bfd_boolean narrow
;
13645 if ((inst
.instruction
& 0x00100000) != 0)
13646 narrow
= !in_pred_block ();
13648 narrow
= in_pred_block ();
13650 if (Rd
> 7 || Rs
> 7)
13653 if (inst
.size_req
== 4 || !unified_syntax
)
13656 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13657 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13660 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13661 relaxation, but it doesn't seem worth the hassle. */
13664 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13665 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13666 inst
.instruction
|= Rs
<< 3;
13667 inst
.instruction
|= Rd
;
13671 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13672 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13676 encode_thumb32_shifted_operand (2);
13682 if (warn_on_deprecated
13683 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13684 as_tsktsk (_("setend use is deprecated for ARMv8"));
13686 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13687 if (inst
.operands
[0].imm
)
13688 inst
.instruction
|= 0x8;
13694 if (!inst
.operands
[1].present
)
13695 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13697 if (unified_syntax
)
13699 bfd_boolean narrow
;
13702 switch (inst
.instruction
)
13705 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13707 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13709 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13711 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13715 if (THUMB_SETS_FLAGS (inst
.instruction
))
13716 narrow
= !in_pred_block ();
13718 narrow
= in_pred_block ();
13719 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13721 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13723 if (inst
.operands
[2].isreg
13724 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13725 || inst
.operands
[2].reg
> 7))
13727 if (inst
.size_req
== 4)
13730 reject_bad_reg (inst
.operands
[0].reg
);
13731 reject_bad_reg (inst
.operands
[1].reg
);
13735 if (inst
.operands
[2].isreg
)
13737 reject_bad_reg (inst
.operands
[2].reg
);
13738 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13739 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13740 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13741 inst
.instruction
|= inst
.operands
[2].reg
;
13743 /* PR 12854: Error on extraneous shifts. */
13744 constraint (inst
.operands
[2].shifted
,
13745 _("extraneous shift as part of operand to shift insn"));
13749 inst
.operands
[1].shifted
= 1;
13750 inst
.operands
[1].shift_kind
= shift_kind
;
13751 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13752 ? T_MNEM_movs
: T_MNEM_mov
);
13753 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13754 encode_thumb32_shifted_operand (1);
13755 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13756 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13761 if (inst
.operands
[2].isreg
)
13763 switch (shift_kind
)
13765 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13766 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13767 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13768 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13772 inst
.instruction
|= inst
.operands
[0].reg
;
13773 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13775 /* PR 12854: Error on extraneous shifts. */
13776 constraint (inst
.operands
[2].shifted
,
13777 _("extraneous shift as part of operand to shift insn"));
13781 switch (shift_kind
)
13783 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13784 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13785 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13788 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13789 inst
.instruction
|= inst
.operands
[0].reg
;
13790 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13796 constraint (inst
.operands
[0].reg
> 7
13797 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13798 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13800 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13802 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13803 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13804 _("source1 and dest must be same register"));
13806 switch (inst
.instruction
)
13808 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13809 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13810 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13811 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13815 inst
.instruction
|= inst
.operands
[0].reg
;
13816 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13818 /* PR 12854: Error on extraneous shifts. */
13819 constraint (inst
.operands
[2].shifted
,
13820 _("extraneous shift as part of operand to shift insn"));
13824 switch (inst
.instruction
)
13826 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13827 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13828 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13829 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13832 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13833 inst
.instruction
|= inst
.operands
[0].reg
;
13834 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13842 unsigned Rd
, Rn
, Rm
;
13844 Rd
= inst
.operands
[0].reg
;
13845 Rn
= inst
.operands
[1].reg
;
13846 Rm
= inst
.operands
[2].reg
;
13848 reject_bad_reg (Rd
);
13849 reject_bad_reg (Rn
);
13850 reject_bad_reg (Rm
);
13852 inst
.instruction
|= Rd
<< 8;
13853 inst
.instruction
|= Rn
<< 16;
13854 inst
.instruction
|= Rm
;
13860 unsigned Rd
, Rn
, Rm
;
13862 Rd
= inst
.operands
[0].reg
;
13863 Rm
= inst
.operands
[1].reg
;
13864 Rn
= inst
.operands
[2].reg
;
13866 reject_bad_reg (Rd
);
13867 reject_bad_reg (Rn
);
13868 reject_bad_reg (Rm
);
13870 inst
.instruction
|= Rd
<< 8;
13871 inst
.instruction
|= Rn
<< 16;
13872 inst
.instruction
|= Rm
;
13878 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13879 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13880 _("SMC is not permitted on this architecture"));
13881 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13882 _("expression too complex"));
13883 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
13885 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13886 inst
.instruction
|= (value
& 0x000f) << 16;
13888 /* PR gas/15623: SMC instructions must be last in an IT block. */
13889 set_pred_insn_type_last ();
13895 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13897 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13898 inst
.instruction
|= (value
& 0x0fff);
13899 inst
.instruction
|= (value
& 0xf000) << 4;
13903 do_t_ssat_usat (int bias
)
13907 Rd
= inst
.operands
[0].reg
;
13908 Rn
= inst
.operands
[2].reg
;
13910 reject_bad_reg (Rd
);
13911 reject_bad_reg (Rn
);
13913 inst
.instruction
|= Rd
<< 8;
13914 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13915 inst
.instruction
|= Rn
<< 16;
13917 if (inst
.operands
[3].present
)
13919 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13921 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13923 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13924 _("expression too complex"));
13926 if (shift_amount
!= 0)
13928 constraint (shift_amount
> 31,
13929 _("shift expression is too large"));
13931 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13932 inst
.instruction
|= 0x00200000; /* sh bit. */
13934 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13935 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13943 do_t_ssat_usat (1);
13951 Rd
= inst
.operands
[0].reg
;
13952 Rn
= inst
.operands
[2].reg
;
13954 reject_bad_reg (Rd
);
13955 reject_bad_reg (Rn
);
13957 inst
.instruction
|= Rd
<< 8;
13958 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13959 inst
.instruction
|= Rn
<< 16;
13965 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13966 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13967 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13968 || inst
.operands
[2].negative
,
13971 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13973 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13974 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13975 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13976 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13982 if (!inst
.operands
[2].present
)
13983 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13985 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13986 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13987 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13990 inst
.instruction
|= inst
.operands
[0].reg
;
13991 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13992 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13993 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13999 unsigned Rd
, Rn
, Rm
;
14001 Rd
= inst
.operands
[0].reg
;
14002 Rn
= inst
.operands
[1].reg
;
14003 Rm
= inst
.operands
[2].reg
;
14005 reject_bad_reg (Rd
);
14006 reject_bad_reg (Rn
);
14007 reject_bad_reg (Rm
);
14009 inst
.instruction
|= Rd
<< 8;
14010 inst
.instruction
|= Rn
<< 16;
14011 inst
.instruction
|= Rm
;
14012 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14020 Rd
= inst
.operands
[0].reg
;
14021 Rm
= inst
.operands
[1].reg
;
14023 reject_bad_reg (Rd
);
14024 reject_bad_reg (Rm
);
14026 if (inst
.instruction
<= 0xffff
14027 && inst
.size_req
!= 4
14028 && Rd
<= 7 && Rm
<= 7
14029 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14031 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14032 inst
.instruction
|= Rd
;
14033 inst
.instruction
|= Rm
<< 3;
14035 else if (unified_syntax
)
14037 if (inst
.instruction
<= 0xffff)
14038 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14039 inst
.instruction
|= Rd
<< 8;
14040 inst
.instruction
|= Rm
;
14041 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14045 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14046 _("Thumb encoding does not support rotation"));
14047 constraint (1, BAD_HIREG
);
14054 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14063 half
= (inst
.instruction
& 0x10) != 0;
14064 set_pred_insn_type_last ();
14065 constraint (inst
.operands
[0].immisreg
,
14066 _("instruction requires register index"));
14068 Rn
= inst
.operands
[0].reg
;
14069 Rm
= inst
.operands
[0].imm
;
14071 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14072 constraint (Rn
== REG_SP
, BAD_SP
);
14073 reject_bad_reg (Rm
);
14075 constraint (!half
&& inst
.operands
[0].shifted
,
14076 _("instruction does not allow shifted index"));
14077 inst
.instruction
|= (Rn
<< 16) | Rm
;
14083 if (!inst
.operands
[0].present
)
14084 inst
.operands
[0].imm
= 0;
14086 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14088 constraint (inst
.size_req
== 2,
14089 _("immediate value out of range"));
14090 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14091 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14092 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14096 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14097 inst
.instruction
|= inst
.operands
[0].imm
;
14100 set_pred_insn_type (NEUTRAL_IT_INSN
);
14107 do_t_ssat_usat (0);
14115 Rd
= inst
.operands
[0].reg
;
14116 Rn
= inst
.operands
[2].reg
;
14118 reject_bad_reg (Rd
);
14119 reject_bad_reg (Rn
);
14121 inst
.instruction
|= Rd
<< 8;
14122 inst
.instruction
|= inst
.operands
[1].imm
;
14123 inst
.instruction
|= Rn
<< 16;
14126 /* Checking the range of the branch offset (VAL) with NBITS bits
14127 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14129 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14131 gas_assert (nbits
> 0 && nbits
<= 32);
14134 int cmp
= (1 << (nbits
- 1));
14135 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14140 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14146 /* For branches in Armv8.1-M Mainline. */
14148 do_t_branch_future (void)
14150 unsigned long insn
= inst
.instruction
;
14152 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14153 if (inst
.operands
[0].hasreloc
== 0)
14155 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14156 as_bad (BAD_BRANCH_OFF
);
14158 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14162 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14163 inst
.relocs
[0].pc_rel
= 1;
14169 if (inst
.operands
[1].hasreloc
== 0)
14171 int val
= inst
.operands
[1].imm
;
14172 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14173 as_bad (BAD_BRANCH_OFF
);
14175 int immA
= (val
& 0x0001f000) >> 12;
14176 int immB
= (val
& 0x00000ffc) >> 2;
14177 int immC
= (val
& 0x00000002) >> 1;
14178 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14182 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14183 inst
.relocs
[1].pc_rel
= 1;
14188 if (inst
.operands
[1].hasreloc
== 0)
14190 int val
= inst
.operands
[1].imm
;
14191 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14192 as_bad (BAD_BRANCH_OFF
);
14194 int immA
= (val
& 0x0007f000) >> 12;
14195 int immB
= (val
& 0x00000ffc) >> 2;
14196 int immC
= (val
& 0x00000002) >> 1;
14197 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14201 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14202 inst
.relocs
[1].pc_rel
= 1;
14206 case T_MNEM_bfcsel
:
14208 if (inst
.operands
[1].hasreloc
== 0)
14210 int val
= inst
.operands
[1].imm
;
14211 int immA
= (val
& 0x00001000) >> 12;
14212 int immB
= (val
& 0x00000ffc) >> 2;
14213 int immC
= (val
& 0x00000002) >> 1;
14214 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14218 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14219 inst
.relocs
[1].pc_rel
= 1;
14223 if (inst
.operands
[2].hasreloc
== 0)
14225 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14226 int val2
= inst
.operands
[2].imm
;
14227 int val0
= inst
.operands
[0].imm
& 0x1f;
14228 int diff
= val2
- val0
;
14230 inst
.instruction
|= 1 << 17; /* T bit. */
14231 else if (diff
!= 2)
14232 as_bad (_("out of range label-relative fixup value"));
14236 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14237 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14238 inst
.relocs
[2].pc_rel
= 1;
14242 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14243 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14248 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14255 /* Helper function for do_t_loloop to handle relocations. */
14257 v8_1_loop_reloc (int is_le
)
14259 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14261 int value
= inst
.relocs
[0].exp
.X_add_number
;
14262 value
= (is_le
) ? -value
: value
;
14264 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14265 as_bad (BAD_BRANCH_OFF
);
14269 immh
= (value
& 0x00000ffc) >> 2;
14270 imml
= (value
& 0x00000002) >> 1;
14272 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14276 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14277 inst
.relocs
[0].pc_rel
= 1;
14281 /* For shifts in MVE. */
14283 do_mve_scalar_shift (void)
14285 if (!inst
.operands
[2].present
)
14287 inst
.operands
[2] = inst
.operands
[1];
14288 inst
.operands
[1].reg
= 0xf;
14291 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14292 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14294 if (inst
.operands
[2].isreg
)
14296 /* Assuming Rm is already checked not to be 11x1. */
14297 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14298 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14299 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14303 /* Assuming imm is already checked as [1,32]. */
14304 unsigned int value
= inst
.operands
[2].imm
;
14305 inst
.instruction
|= (value
& 0x1c) << 10;
14306 inst
.instruction
|= (value
& 0x03) << 6;
14307 /* Change last 4 bits from 0xd to 0xf. */
14308 inst
.instruction
|= 0x2;
14312 /* MVE instruction encoder helpers. */
14313 #define M_MNEM_vabav 0xee800f01
14314 #define M_MNEM_vmladav 0xeef00e00
14315 #define M_MNEM_vmladava 0xeef00e20
14316 #define M_MNEM_vmladavx 0xeef01e00
14317 #define M_MNEM_vmladavax 0xeef01e20
14318 #define M_MNEM_vmlsdav 0xeef00e01
14319 #define M_MNEM_vmlsdava 0xeef00e21
14320 #define M_MNEM_vmlsdavx 0xeef01e01
14321 #define M_MNEM_vmlsdavax 0xeef01e21
14322 #define M_MNEM_vmullt 0xee011e00
14323 #define M_MNEM_vmullb 0xee010e00
14324 #define M_MNEM_vst20 0xfc801e00
14325 #define M_MNEM_vst21 0xfc801e20
14326 #define M_MNEM_vst40 0xfc801e01
14327 #define M_MNEM_vst41 0xfc801e21
14328 #define M_MNEM_vst42 0xfc801e41
14329 #define M_MNEM_vst43 0xfc801e61
14330 #define M_MNEM_vld20 0xfc901e00
14331 #define M_MNEM_vld21 0xfc901e20
14332 #define M_MNEM_vld40 0xfc901e01
14333 #define M_MNEM_vld41 0xfc901e21
14334 #define M_MNEM_vld42 0xfc901e41
14335 #define M_MNEM_vld43 0xfc901e61
14336 #define M_MNEM_vstrb 0xec000e00
14337 #define M_MNEM_vstrh 0xec000e10
14338 #define M_MNEM_vstrw 0xec000e40
14339 #define M_MNEM_vstrd 0xec000e50
14340 #define M_MNEM_vldrb 0xec100e00
14341 #define M_MNEM_vldrh 0xec100e10
14342 #define M_MNEM_vldrw 0xec100e40
14343 #define M_MNEM_vldrd 0xec100e50
14344 #define M_MNEM_vmovlt 0xeea01f40
14345 #define M_MNEM_vmovlb 0xeea00f40
14346 #define M_MNEM_vmovnt 0xfe311e81
14347 #define M_MNEM_vmovnb 0xfe310e81
14348 #define M_MNEM_vadc 0xee300f00
14349 #define M_MNEM_vadci 0xee301f00
14350 #define M_MNEM_vbrsr 0xfe011e60
14351 #define M_MNEM_vaddlv 0xee890f00
14352 #define M_MNEM_vaddlva 0xee890f20
14353 #define M_MNEM_vaddv 0xeef10f00
14354 #define M_MNEM_vaddva 0xeef10f20
14355 #define M_MNEM_vddup 0xee011f6e
14356 #define M_MNEM_vdwdup 0xee011f60
14357 #define M_MNEM_vidup 0xee010f6e
14358 #define M_MNEM_viwdup 0xee010f60
14359 #define M_MNEM_vmaxv 0xeee20f00
14360 #define M_MNEM_vmaxav 0xeee00f00
14361 #define M_MNEM_vminv 0xeee20f80
14362 #define M_MNEM_vminav 0xeee00f80
14363 #define M_MNEM_vmlaldav 0xee800e00
14364 #define M_MNEM_vmlaldava 0xee800e20
14365 #define M_MNEM_vmlaldavx 0xee801e00
14366 #define M_MNEM_vmlaldavax 0xee801e20
14367 #define M_MNEM_vmlsldav 0xee800e01
14368 #define M_MNEM_vmlsldava 0xee800e21
14369 #define M_MNEM_vmlsldavx 0xee801e01
14370 #define M_MNEM_vmlsldavax 0xee801e21
14371 #define M_MNEM_vrmlaldavhx 0xee801f00
14372 #define M_MNEM_vrmlaldavhax 0xee801f20
14373 #define M_MNEM_vrmlsldavh 0xfe800e01
14374 #define M_MNEM_vrmlsldavha 0xfe800e21
14375 #define M_MNEM_vrmlsldavhx 0xfe801e01
14376 #define M_MNEM_vrmlsldavhax 0xfe801e21
14377 #define M_MNEM_vqmovnt 0xee331e01
14378 #define M_MNEM_vqmovnb 0xee330e01
14379 #define M_MNEM_vqmovunt 0xee311e81
14380 #define M_MNEM_vqmovunb 0xee310e81
14381 #define M_MNEM_vshrnt 0xee801fc1
14382 #define M_MNEM_vshrnb 0xee800fc1
14383 #define M_MNEM_vrshrnt 0xfe801fc1
14384 #define M_MNEM_vqshrnt 0xee801f40
14385 #define M_MNEM_vqshrnb 0xee800f40
14386 #define M_MNEM_vqshrunt 0xee801fc0
14387 #define M_MNEM_vqshrunb 0xee800fc0
14388 #define M_MNEM_vrshrnb 0xfe800fc1
14389 #define M_MNEM_vqrshrnt 0xee801f41
14390 #define M_MNEM_vqrshrnb 0xee800f41
14391 #define M_MNEM_vqrshrunt 0xfe801fc0
14392 #define M_MNEM_vqrshrunb 0xfe800fc0
14394 /* Neon instruction encoder helpers. */
14396 /* Encodings for the different types for various Neon opcodes. */
14398 /* An "invalid" code for the following tables. */
14401 struct neon_tab_entry
14404 unsigned float_or_poly
;
14405 unsigned scalar_or_imm
;
14408 /* Map overloaded Neon opcodes to their respective encodings. */
14409 #define NEON_ENC_TAB \
14410 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14411 X(vabdl, 0x0800700, N_INV, N_INV), \
14412 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14413 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14414 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14415 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14416 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14417 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14418 X(vaddl, 0x0800000, N_INV, N_INV), \
14419 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14420 X(vsubl, 0x0800200, N_INV, N_INV), \
14421 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14422 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14423 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14424 /* Register variants of the following two instructions are encoded as
14425 vcge / vcgt with the operands reversed. */ \
14426 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14427 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14428 X(vfma, N_INV, 0x0000c10, N_INV), \
14429 X(vfms, N_INV, 0x0200c10, N_INV), \
14430 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14431 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14432 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14433 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14434 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14435 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14436 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14437 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14438 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14439 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14440 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14441 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14442 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14443 X(vshl, 0x0000400, N_INV, 0x0800510), \
14444 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14445 X(vand, 0x0000110, N_INV, 0x0800030), \
14446 X(vbic, 0x0100110, N_INV, 0x0800030), \
14447 X(veor, 0x1000110, N_INV, N_INV), \
14448 X(vorn, 0x0300110, N_INV, 0x0800010), \
14449 X(vorr, 0x0200110, N_INV, 0x0800010), \
14450 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14451 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14452 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14453 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14454 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14455 X(vst1, 0x0000000, 0x0800000, N_INV), \
14456 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14457 X(vst2, 0x0000100, 0x0800100, N_INV), \
14458 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14459 X(vst3, 0x0000200, 0x0800200, N_INV), \
14460 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14461 X(vst4, 0x0000300, 0x0800300, N_INV), \
14462 X(vmovn, 0x1b20200, N_INV, N_INV), \
14463 X(vtrn, 0x1b20080, N_INV, N_INV), \
14464 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14465 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14466 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14467 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14468 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14469 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14470 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14471 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14472 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14473 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14474 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14475 X(vseleq, 0xe000a00, N_INV, N_INV), \
14476 X(vselvs, 0xe100a00, N_INV, N_INV), \
14477 X(vselge, 0xe200a00, N_INV, N_INV), \
14478 X(vselgt, 0xe300a00, N_INV, N_INV), \
14479 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14480 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14481 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14482 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14483 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14484 X(aes, 0x3b00300, N_INV, N_INV), \
14485 X(sha3op, 0x2000c00, N_INV, N_INV), \
14486 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14487 X(sha2op, 0x3ba0380, N_INV, N_INV)
14491 #define X(OPC,I,F,S) N_MNEM_##OPC
14496 static const struct neon_tab_entry neon_enc_tab
[] =
14498 #define X(OPC,I,F,S) { (I), (F), (S) }
14503 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14504 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14505 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14506 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14507 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14508 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14509 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14510 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14511 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14512 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14513 #define NEON_ENC_SINGLE_(X) \
14514 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14515 #define NEON_ENC_DOUBLE_(X) \
14516 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14517 #define NEON_ENC_FPV8_(X) \
14518 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14520 #define NEON_ENCODE(type, inst) \
14523 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14524 inst.is_neon = 1; \
14528 #define check_neon_suffixes \
14531 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14533 as_bad (_("invalid neon suffix for non neon instruction")); \
14539 /* Define shapes for instruction operands. The following mnemonic characters
14540 are used in this table:
14542 F - VFP S<n> register
14543 D - Neon D<n> register
14544 Q - Neon Q<n> register
14548 L - D<n> register list
14550 This table is used to generate various data:
14551 - enumerations of the form NS_DDR to be used as arguments to
14553 - a table classifying shapes into single, double, quad, mixed.
14554 - a table used to drive neon_select_shape. */
14556 #define NEON_SHAPE_DEF \
14557 X(4, (R, R, Q, Q), QUAD), \
14558 X(4, (Q, R, R, I), QUAD), \
14559 X(4, (R, R, S, S), QUAD), \
14560 X(4, (S, S, R, R), QUAD), \
14561 X(3, (Q, R, I), QUAD), \
14562 X(3, (I, Q, Q), QUAD), \
14563 X(3, (I, Q, R), QUAD), \
14564 X(3, (R, Q, Q), QUAD), \
14565 X(3, (D, D, D), DOUBLE), \
14566 X(3, (Q, Q, Q), QUAD), \
14567 X(3, (D, D, I), DOUBLE), \
14568 X(3, (Q, Q, I), QUAD), \
14569 X(3, (D, D, S), DOUBLE), \
14570 X(3, (Q, Q, S), QUAD), \
14571 X(3, (Q, Q, R), QUAD), \
14572 X(3, (R, R, Q), QUAD), \
14573 X(2, (R, Q), QUAD), \
14574 X(2, (D, D), DOUBLE), \
14575 X(2, (Q, Q), QUAD), \
14576 X(2, (D, S), DOUBLE), \
14577 X(2, (Q, S), QUAD), \
14578 X(2, (D, R), DOUBLE), \
14579 X(2, (Q, R), QUAD), \
14580 X(2, (D, I), DOUBLE), \
14581 X(2, (Q, I), QUAD), \
14582 X(3, (D, L, D), DOUBLE), \
14583 X(2, (D, Q), MIXED), \
14584 X(2, (Q, D), MIXED), \
14585 X(3, (D, Q, I), MIXED), \
14586 X(3, (Q, D, I), MIXED), \
14587 X(3, (Q, D, D), MIXED), \
14588 X(3, (D, Q, Q), MIXED), \
14589 X(3, (Q, Q, D), MIXED), \
14590 X(3, (Q, D, S), MIXED), \
14591 X(3, (D, Q, S), MIXED), \
14592 X(4, (D, D, D, I), DOUBLE), \
14593 X(4, (Q, Q, Q, I), QUAD), \
14594 X(4, (D, D, S, I), DOUBLE), \
14595 X(4, (Q, Q, S, I), QUAD), \
14596 X(2, (F, F), SINGLE), \
14597 X(3, (F, F, F), SINGLE), \
14598 X(2, (F, I), SINGLE), \
14599 X(2, (F, D), MIXED), \
14600 X(2, (D, F), MIXED), \
14601 X(3, (F, F, I), MIXED), \
14602 X(4, (R, R, F, F), SINGLE), \
14603 X(4, (F, F, R, R), SINGLE), \
14604 X(3, (D, R, R), DOUBLE), \
14605 X(3, (R, R, D), DOUBLE), \
14606 X(2, (S, R), SINGLE), \
14607 X(2, (R, S), SINGLE), \
14608 X(2, (F, R), SINGLE), \
14609 X(2, (R, F), SINGLE), \
14610 /* Used for MVE tail predicated loop instructions. */\
14611 X(2, (R, R), QUAD), \
14612 /* Half float shape supported so far. */\
14613 X (2, (H, D), MIXED), \
14614 X (2, (D, H), MIXED), \
14615 X (2, (H, F), MIXED), \
14616 X (2, (F, H), MIXED), \
14617 X (2, (H, H), HALF), \
14618 X (2, (H, R), HALF), \
14619 X (2, (R, H), HALF), \
14620 X (2, (H, I), HALF), \
14621 X (3, (H, H, H), HALF), \
14622 X (3, (H, F, I), MIXED), \
14623 X (3, (F, H, I), MIXED), \
14624 X (3, (D, H, H), MIXED), \
14625 X (3, (D, H, S), MIXED)
14627 #define S2(A,B) NS_##A##B
14628 #define S3(A,B,C) NS_##A##B##C
14629 #define S4(A,B,C,D) NS_##A##B##C##D
14631 #define X(N, L, C) S##N L
14644 enum neon_shape_class
14653 #define X(N, L, C) SC_##C
14655 static enum neon_shape_class neon_shape_class
[] =
14674 /* Register widths of above. */
14675 static unsigned neon_shape_el_size
[] =
14687 struct neon_shape_info
14690 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14693 #define S2(A,B) { SE_##A, SE_##B }
14694 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14695 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14697 #define X(N, L, C) { N, S##N L }
14699 static struct neon_shape_info neon_shape_tab
[] =
14709 /* Bit masks used in type checking given instructions.
14710 'N_EQK' means the type must be the same as (or based on in some way) the key
14711 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14712 set, various other bits can be set as well in order to modify the meaning of
14713 the type constraint. */
14715 enum neon_type_mask
14739 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14740 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14741 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14742 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14743 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14744 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14745 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14746 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14747 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14748 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14749 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14751 N_MAX_NONSPECIAL
= N_P64
14754 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14756 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14757 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14758 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14759 #define N_S_32 (N_S8 | N_S16 | N_S32)
14760 #define N_F_16_32 (N_F16 | N_F32)
14761 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14762 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14763 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14764 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14765 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14766 #define N_F_MVE (N_F16 | N_F32)
14767 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14769 /* Pass this as the first type argument to neon_check_type to ignore types
14771 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14773 /* Select a "shape" for the current instruction (describing register types or
14774 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14775 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14776 function of operand parsing, so this function doesn't need to be called.
14777 Shapes should be listed in order of decreasing length. */
14779 static enum neon_shape
14780 neon_select_shape (enum neon_shape shape
, ...)
14783 enum neon_shape first_shape
= shape
;
14785 /* Fix missing optional operands. FIXME: we don't know at this point how
14786 many arguments we should have, so this makes the assumption that we have
14787 > 1. This is true of all current Neon opcodes, I think, but may not be
14788 true in the future. */
14789 if (!inst
.operands
[1].present
)
14790 inst
.operands
[1] = inst
.operands
[0];
14792 va_start (ap
, shape
);
14794 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14799 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14801 if (!inst
.operands
[j
].present
)
14807 switch (neon_shape_tab
[shape
].el
[j
])
14809 /* If a .f16, .16, .u16, .s16 type specifier is given over
14810 a VFP single precision register operand, it's essentially
14811 means only half of the register is used.
14813 If the type specifier is given after the mnemonics, the
14814 information is stored in inst.vectype. If the type specifier
14815 is given after register operand, the information is stored
14816 in inst.operands[].vectype.
14818 When there is only one type specifier, and all the register
14819 operands are the same type of hardware register, the type
14820 specifier applies to all register operands.
14822 If no type specifier is given, the shape is inferred from
14823 operand information.
14826 vadd.f16 s0, s1, s2: NS_HHH
14827 vabs.f16 s0, s1: NS_HH
14828 vmov.f16 s0, r1: NS_HR
14829 vmov.f16 r0, s1: NS_RH
14830 vcvt.f16 r0, s1: NS_RH
14831 vcvt.f16.s32 s2, s2, #29: NS_HFI
14832 vcvt.f16.s32 s2, s2: NS_HF
14835 if (!(inst
.operands
[j
].isreg
14836 && inst
.operands
[j
].isvec
14837 && inst
.operands
[j
].issingle
14838 && !inst
.operands
[j
].isquad
14839 && ((inst
.vectype
.elems
== 1
14840 && inst
.vectype
.el
[0].size
== 16)
14841 || (inst
.vectype
.elems
> 1
14842 && inst
.vectype
.el
[j
].size
== 16)
14843 || (inst
.vectype
.elems
== 0
14844 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14845 && inst
.operands
[j
].vectype
.size
== 16))))
14850 if (!(inst
.operands
[j
].isreg
14851 && inst
.operands
[j
].isvec
14852 && inst
.operands
[j
].issingle
14853 && !inst
.operands
[j
].isquad
14854 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14855 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14856 || (inst
.vectype
.elems
== 0
14857 && (inst
.operands
[j
].vectype
.size
== 32
14858 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14863 if (!(inst
.operands
[j
].isreg
14864 && inst
.operands
[j
].isvec
14865 && !inst
.operands
[j
].isquad
14866 && !inst
.operands
[j
].issingle
))
14871 if (!(inst
.operands
[j
].isreg
14872 && !inst
.operands
[j
].isvec
))
14877 if (!(inst
.operands
[j
].isreg
14878 && inst
.operands
[j
].isvec
14879 && inst
.operands
[j
].isquad
14880 && !inst
.operands
[j
].issingle
))
14885 if (!(!inst
.operands
[j
].isreg
14886 && !inst
.operands
[j
].isscalar
))
14891 if (!(!inst
.operands
[j
].isreg
14892 && inst
.operands
[j
].isscalar
))
14902 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14903 /* We've matched all the entries in the shape table, and we don't
14904 have any left over operands which have not been matched. */
14910 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14911 first_error (_("invalid instruction shape"));
14916 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14917 means the Q bit should be set). */
14920 neon_quad (enum neon_shape shape
)
14922 return neon_shape_class
[shape
] == SC_QUAD
;
14926 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14929 /* Allow modification to be made to types which are constrained to be
14930 based on the key element, based on bits set alongside N_EQK. */
14931 if ((typebits
& N_EQK
) != 0)
14933 if ((typebits
& N_HLF
) != 0)
14935 else if ((typebits
& N_DBL
) != 0)
14937 if ((typebits
& N_SGN
) != 0)
14938 *g_type
= NT_signed
;
14939 else if ((typebits
& N_UNS
) != 0)
14940 *g_type
= NT_unsigned
;
14941 else if ((typebits
& N_INT
) != 0)
14942 *g_type
= NT_integer
;
14943 else if ((typebits
& N_FLT
) != 0)
14944 *g_type
= NT_float
;
14945 else if ((typebits
& N_SIZ
) != 0)
14946 *g_type
= NT_untyped
;
14950 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14951 operand type, i.e. the single type specified in a Neon instruction when it
14952 is the only one given. */
14954 static struct neon_type_el
14955 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14957 struct neon_type_el dest
= *key
;
14959 gas_assert ((thisarg
& N_EQK
) != 0);
14961 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14966 /* Convert Neon type and size into compact bitmask representation. */
14968 static enum neon_type_mask
14969 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14976 case 8: return N_8
;
14977 case 16: return N_16
;
14978 case 32: return N_32
;
14979 case 64: return N_64
;
14987 case 8: return N_I8
;
14988 case 16: return N_I16
;
14989 case 32: return N_I32
;
14990 case 64: return N_I64
;
14998 case 16: return N_F16
;
14999 case 32: return N_F32
;
15000 case 64: return N_F64
;
15008 case 8: return N_P8
;
15009 case 16: return N_P16
;
15010 case 64: return N_P64
;
15018 case 8: return N_S8
;
15019 case 16: return N_S16
;
15020 case 32: return N_S32
;
15021 case 64: return N_S64
;
15029 case 8: return N_U8
;
15030 case 16: return N_U16
;
15031 case 32: return N_U32
;
15032 case 64: return N_U64
;
15043 /* Convert compact Neon bitmask type representation to a type and size. Only
15044 handles the case where a single bit is set in the mask. */
15047 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15048 enum neon_type_mask mask
)
15050 if ((mask
& N_EQK
) != 0)
15053 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15055 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
15057 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15059 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15064 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15066 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15067 *type
= NT_unsigned
;
15068 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15069 *type
= NT_integer
;
15070 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15071 *type
= NT_untyped
;
15072 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15074 else if ((mask
& (N_F_ALL
)) != 0)
15082 /* Modify a bitmask of allowed types. This is only needed for type
15086 modify_types_allowed (unsigned allowed
, unsigned mods
)
15089 enum neon_el_type type
;
15095 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15097 if (el_type_of_type_chk (&type
, &size
,
15098 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15100 neon_modify_type_size (mods
, &type
, &size
);
15101 destmask
|= type_chk_of_el_type (type
, size
);
15108 /* Check type and return type classification.
15109 The manual states (paraphrase): If one datatype is given, it indicates the
15111 - the second operand, if there is one
15112 - the operand, if there is no second operand
15113 - the result, if there are no operands.
15114 This isn't quite good enough though, so we use a concept of a "key" datatype
15115 which is set on a per-instruction basis, which is the one which matters when
15116 only one data type is written.
15117 Note: this function has side-effects (e.g. filling in missing operands). All
15118 Neon instructions should call it before performing bit encoding. */
15120 static struct neon_type_el
15121 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15124 unsigned i
, pass
, key_el
= 0;
15125 unsigned types
[NEON_MAX_TYPE_ELS
];
15126 enum neon_el_type k_type
= NT_invtype
;
15127 unsigned k_size
= -1u;
15128 struct neon_type_el badtype
= {NT_invtype
, -1};
15129 unsigned key_allowed
= 0;
15131 /* Optional registers in Neon instructions are always (not) in operand 1.
15132 Fill in the missing operand here, if it was omitted. */
15133 if (els
> 1 && !inst
.operands
[1].present
)
15134 inst
.operands
[1] = inst
.operands
[0];
15136 /* Suck up all the varargs. */
15138 for (i
= 0; i
< els
; i
++)
15140 unsigned thisarg
= va_arg (ap
, unsigned);
15141 if (thisarg
== N_IGNORE_TYPE
)
15146 types
[i
] = thisarg
;
15147 if ((thisarg
& N_KEY
) != 0)
15152 if (inst
.vectype
.elems
> 0)
15153 for (i
= 0; i
< els
; i
++)
15154 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15156 first_error (_("types specified in both the mnemonic and operands"));
15160 /* Duplicate inst.vectype elements here as necessary.
15161 FIXME: No idea if this is exactly the same as the ARM assembler,
15162 particularly when an insn takes one register and one non-register
15164 if (inst
.vectype
.elems
== 1 && els
> 1)
15167 inst
.vectype
.elems
= els
;
15168 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15169 for (j
= 0; j
< els
; j
++)
15171 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15174 else if (inst
.vectype
.elems
== 0 && els
> 0)
15177 /* No types were given after the mnemonic, so look for types specified
15178 after each operand. We allow some flexibility here; as long as the
15179 "key" operand has a type, we can infer the others. */
15180 for (j
= 0; j
< els
; j
++)
15181 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15182 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15184 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15186 for (j
= 0; j
< els
; j
++)
15187 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15188 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15193 first_error (_("operand types can't be inferred"));
15197 else if (inst
.vectype
.elems
!= els
)
15199 first_error (_("type specifier has the wrong number of parts"));
15203 for (pass
= 0; pass
< 2; pass
++)
15205 for (i
= 0; i
< els
; i
++)
15207 unsigned thisarg
= types
[i
];
15208 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15209 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15210 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15211 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15213 /* Decay more-specific signed & unsigned types to sign-insensitive
15214 integer types if sign-specific variants are unavailable. */
15215 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15216 && (types_allowed
& N_SU_ALL
) == 0)
15217 g_type
= NT_integer
;
15219 /* If only untyped args are allowed, decay any more specific types to
15220 them. Some instructions only care about signs for some element
15221 sizes, so handle that properly. */
15222 if (((types_allowed
& N_UNT
) == 0)
15223 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15224 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15225 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15226 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15227 g_type
= NT_untyped
;
15231 if ((thisarg
& N_KEY
) != 0)
15235 key_allowed
= thisarg
& ~N_KEY
;
15237 /* Check architecture constraint on FP16 extension. */
15239 && k_type
== NT_float
15240 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15242 inst
.error
= _(BAD_FP16
);
15249 if ((thisarg
& N_VFP
) != 0)
15251 enum neon_shape_el regshape
;
15252 unsigned regwidth
, match
;
15254 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15257 first_error (_("invalid instruction shape"));
15260 regshape
= neon_shape_tab
[ns
].el
[i
];
15261 regwidth
= neon_shape_el_size
[regshape
];
15263 /* In VFP mode, operands must match register widths. If we
15264 have a key operand, use its width, else use the width of
15265 the current operand. */
15271 /* FP16 will use a single precision register. */
15272 if (regwidth
== 32 && match
== 16)
15274 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15278 inst
.error
= _(BAD_FP16
);
15283 if (regwidth
!= match
)
15285 first_error (_("operand size must match register width"));
15290 if ((thisarg
& N_EQK
) == 0)
15292 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15294 if ((given_type
& types_allowed
) == 0)
15296 first_error (BAD_SIMD_TYPE
);
15302 enum neon_el_type mod_k_type
= k_type
;
15303 unsigned mod_k_size
= k_size
;
15304 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15305 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15307 first_error (_("inconsistent types in Neon instruction"));
15315 return inst
.vectype
.el
[key_el
];
15318 /* Neon-style VFP instruction forwarding. */
15320 /* Thumb VFP instructions have 0xE in the condition field. */
15323 do_vfp_cond_or_thumb (void)
15328 inst
.instruction
|= 0xe0000000;
15330 inst
.instruction
|= inst
.cond
<< 28;
15333 /* Look up and encode a simple mnemonic, for use as a helper function for the
15334 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15335 etc. It is assumed that operand parsing has already been done, and that the
15336 operands are in the form expected by the given opcode (this isn't necessarily
15337 the same as the form in which they were parsed, hence some massaging must
15338 take place before this function is called).
15339 Checks current arch version against that in the looked-up opcode. */
15342 do_vfp_nsyn_opcode (const char *opname
)
15344 const struct asm_opcode
*opcode
;
15346 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15351 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15352 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15359 inst
.instruction
= opcode
->tvalue
;
15360 opcode
->tencode ();
15364 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15365 opcode
->aencode ();
15370 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15372 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15374 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15377 do_vfp_nsyn_opcode ("fadds");
15379 do_vfp_nsyn_opcode ("fsubs");
15381 /* ARMv8.2 fp16 instruction. */
15383 do_scalar_fp16_v82_encode ();
15388 do_vfp_nsyn_opcode ("faddd");
15390 do_vfp_nsyn_opcode ("fsubd");
15394 /* Check operand types to see if this is a VFP instruction, and if so call
15398 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15400 enum neon_shape rs
;
15401 struct neon_type_el et
;
15406 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15407 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15411 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15412 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15413 N_F_ALL
| N_KEY
| N_VFP
);
15420 if (et
.type
!= NT_invtype
)
15431 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15433 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15435 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15438 do_vfp_nsyn_opcode ("fmacs");
15440 do_vfp_nsyn_opcode ("fnmacs");
15442 /* ARMv8.2 fp16 instruction. */
15444 do_scalar_fp16_v82_encode ();
15449 do_vfp_nsyn_opcode ("fmacd");
15451 do_vfp_nsyn_opcode ("fnmacd");
15456 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15458 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15460 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15463 do_vfp_nsyn_opcode ("ffmas");
15465 do_vfp_nsyn_opcode ("ffnmas");
15467 /* ARMv8.2 fp16 instruction. */
15469 do_scalar_fp16_v82_encode ();
15474 do_vfp_nsyn_opcode ("ffmad");
15476 do_vfp_nsyn_opcode ("ffnmad");
15481 do_vfp_nsyn_mul (enum neon_shape rs
)
15483 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15485 do_vfp_nsyn_opcode ("fmuls");
15487 /* ARMv8.2 fp16 instruction. */
15489 do_scalar_fp16_v82_encode ();
15492 do_vfp_nsyn_opcode ("fmuld");
15496 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15498 int is_neg
= (inst
.instruction
& 0x80) != 0;
15499 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15501 if (rs
== NS_FF
|| rs
== NS_HH
)
15504 do_vfp_nsyn_opcode ("fnegs");
15506 do_vfp_nsyn_opcode ("fabss");
15508 /* ARMv8.2 fp16 instruction. */
15510 do_scalar_fp16_v82_encode ();
15515 do_vfp_nsyn_opcode ("fnegd");
15517 do_vfp_nsyn_opcode ("fabsd");
15521 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15522 insns belong to Neon, and are handled elsewhere. */
15525 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15527 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15531 do_vfp_nsyn_opcode ("fldmdbs");
15533 do_vfp_nsyn_opcode ("fldmias");
15538 do_vfp_nsyn_opcode ("fstmdbs");
15540 do_vfp_nsyn_opcode ("fstmias");
15545 do_vfp_nsyn_sqrt (void)
15547 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15548 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15550 if (rs
== NS_FF
|| rs
== NS_HH
)
15552 do_vfp_nsyn_opcode ("fsqrts");
15554 /* ARMv8.2 fp16 instruction. */
15556 do_scalar_fp16_v82_encode ();
15559 do_vfp_nsyn_opcode ("fsqrtd");
15563 do_vfp_nsyn_div (void)
15565 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15566 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15567 N_F_ALL
| N_KEY
| N_VFP
);
15569 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15571 do_vfp_nsyn_opcode ("fdivs");
15573 /* ARMv8.2 fp16 instruction. */
15575 do_scalar_fp16_v82_encode ();
15578 do_vfp_nsyn_opcode ("fdivd");
15582 do_vfp_nsyn_nmul (void)
15584 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15585 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15586 N_F_ALL
| N_KEY
| N_VFP
);
15588 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15590 NEON_ENCODE (SINGLE
, inst
);
15591 do_vfp_sp_dyadic ();
15593 /* ARMv8.2 fp16 instruction. */
15595 do_scalar_fp16_v82_encode ();
15599 NEON_ENCODE (DOUBLE
, inst
);
15600 do_vfp_dp_rd_rn_rm ();
15602 do_vfp_cond_or_thumb ();
15606 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15610 neon_logbits (unsigned x
)
15612 return ffs (x
) - 4;
15615 #define LOW4(R) ((R) & 0xf)
15616 #define HI1(R) (((R) >> 4) & 1)
15619 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15624 first_error (BAD_EL_TYPE
);
15627 switch (inst
.operands
[0].imm
)
15630 first_error (_("invalid condition"));
15652 /* only accept eq and ne. */
15653 if (inst
.operands
[0].imm
> 1)
15655 first_error (_("invalid condition"));
15658 return inst
.operands
[0].imm
;
15660 if (inst
.operands
[0].imm
== 0x2)
15662 else if (inst
.operands
[0].imm
== 0x8)
15666 first_error (_("invalid condition"));
15670 switch (inst
.operands
[0].imm
)
15673 first_error (_("invalid condition"));
15689 /* Should be unreachable. */
15696 /* We are dealing with a vector predicated block. */
15697 if (inst
.operands
[0].present
)
15699 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15700 struct neon_type_el et
15701 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15704 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15706 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15708 if (et
.type
== NT_invtype
)
15711 if (et
.type
== NT_float
)
15713 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15715 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15716 inst
.instruction
|= (et
.size
== 16) << 28;
15717 inst
.instruction
|= 0x3 << 20;
15721 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15723 inst
.instruction
|= 1 << 28;
15724 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15727 if (inst
.operands
[2].isquad
)
15729 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15730 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15731 inst
.instruction
|= (fcond
& 0x2) >> 1;
15735 if (inst
.operands
[2].reg
== REG_SP
)
15736 as_tsktsk (MVE_BAD_SP
);
15737 inst
.instruction
|= 1 << 6;
15738 inst
.instruction
|= (fcond
& 0x2) << 4;
15739 inst
.instruction
|= inst
.operands
[2].reg
;
15741 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15742 inst
.instruction
|= (fcond
& 0x4) << 10;
15743 inst
.instruction
|= (fcond
& 0x1) << 7;
15746 set_pred_insn_type (VPT_INSN
);
15748 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15749 | ((inst
.instruction
& 0xe000) >> 13);
15750 now_pred
.warn_deprecated
= FALSE
;
15751 now_pred
.type
= VECTOR_PRED
;
15758 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15759 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15760 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15761 if (!inst
.operands
[2].present
)
15762 first_error (_("MVE vector or ARM register expected"));
15763 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15765 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15766 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15767 && inst
.operands
[1].isquad
)
15769 inst
.instruction
= N_MNEM_vcmp
;
15773 if (inst
.cond
> COND_ALWAYS
)
15774 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15776 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15778 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15779 struct neon_type_el et
15780 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15783 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15784 && !inst
.operands
[2].iszr
, BAD_PC
);
15786 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15788 inst
.instruction
= 0xee010f00;
15789 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15790 inst
.instruction
|= (fcond
& 0x4) << 10;
15791 inst
.instruction
|= (fcond
& 0x1) << 7;
15792 if (et
.type
== NT_float
)
15794 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15796 inst
.instruction
|= (et
.size
== 16) << 28;
15797 inst
.instruction
|= 0x3 << 20;
15801 inst
.instruction
|= 1 << 28;
15802 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15804 if (inst
.operands
[2].isquad
)
15806 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15807 inst
.instruction
|= (fcond
& 0x2) >> 1;
15808 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15812 if (inst
.operands
[2].reg
== REG_SP
)
15813 as_tsktsk (MVE_BAD_SP
);
15814 inst
.instruction
|= 1 << 6;
15815 inst
.instruction
|= (fcond
& 0x2) << 4;
15816 inst
.instruction
|= inst
.operands
[2].reg
;
15824 do_mve_vmaxa_vmina (void)
15826 if (inst
.cond
> COND_ALWAYS
)
15827 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15829 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15831 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15832 struct neon_type_el et
15833 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15835 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15836 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15837 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15838 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15839 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15844 do_mve_vfmas (void)
15846 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15847 struct neon_type_el et
15848 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
15850 if (inst
.cond
> COND_ALWAYS
)
15851 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15853 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15855 if (inst
.operands
[2].reg
== REG_SP
)
15856 as_tsktsk (MVE_BAD_SP
);
15857 else if (inst
.operands
[2].reg
== REG_PC
)
15858 as_tsktsk (MVE_BAD_PC
);
15860 inst
.instruction
|= (et
.size
== 16) << 28;
15861 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15862 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15863 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15864 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15865 inst
.instruction
|= inst
.operands
[2].reg
;
15870 do_mve_viddup (void)
15872 if (inst
.cond
> COND_ALWAYS
)
15873 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15875 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15877 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
15878 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
15879 _("immediate must be either 1, 2, 4 or 8"));
15881 enum neon_shape rs
;
15882 struct neon_type_el et
;
15884 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
15886 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
15887 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
15892 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
15893 if (inst
.operands
[2].reg
== REG_SP
)
15894 as_tsktsk (MVE_BAD_SP
);
15895 else if (inst
.operands
[2].reg
== REG_PC
)
15896 first_error (BAD_PC
);
15898 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
15899 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
15900 Rm
= inst
.operands
[2].reg
>> 1;
15902 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15903 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15904 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15905 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15906 inst
.instruction
|= (imm
> 2) << 7;
15907 inst
.instruction
|= Rm
<< 1;
15908 inst
.instruction
|= (imm
== 2 || imm
== 8);
15913 do_mve_vmlas (void)
15915 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15916 struct neon_type_el et
15917 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
15919 if (inst
.operands
[2].reg
== REG_PC
)
15920 as_tsktsk (MVE_BAD_PC
);
15921 else if (inst
.operands
[2].reg
== REG_SP
)
15922 as_tsktsk (MVE_BAD_SP
);
15924 if (inst
.cond
> COND_ALWAYS
)
15925 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15927 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15929 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15930 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15931 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15932 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15933 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15934 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15935 inst
.instruction
|= inst
.operands
[2].reg
;
15940 do_mve_vshll (void)
15942 struct neon_type_el et
15943 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
15945 if (inst
.cond
> COND_ALWAYS
)
15946 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15948 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15950 int imm
= inst
.operands
[2].imm
;
15951 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15952 _("immediate value out of range"));
15954 if ((unsigned)imm
== et
.size
)
15956 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15957 inst
.instruction
|= 0x110001;
15961 inst
.instruction
|= (et
.size
+ imm
) << 16;
15962 inst
.instruction
|= 0x800140;
15965 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15966 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15967 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15968 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15969 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15974 do_mve_vshlc (void)
15976 if (inst
.cond
> COND_ALWAYS
)
15977 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15979 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15981 if (inst
.operands
[1].reg
== REG_PC
)
15982 as_tsktsk (MVE_BAD_PC
);
15983 else if (inst
.operands
[1].reg
== REG_SP
)
15984 as_tsktsk (MVE_BAD_SP
);
15986 int imm
= inst
.operands
[2].imm
;
15987 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
15989 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15990 inst
.instruction
|= (imm
& 0x1f) << 16;
15991 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15992 inst
.instruction
|= inst
.operands
[1].reg
;
15997 do_mve_vshrn (void)
16000 switch (inst
.instruction
)
16002 case M_MNEM_vshrnt
:
16003 case M_MNEM_vshrnb
:
16004 case M_MNEM_vrshrnt
:
16005 case M_MNEM_vrshrnb
:
16006 types
= N_I16
| N_I32
;
16008 case M_MNEM_vqshrnt
:
16009 case M_MNEM_vqshrnb
:
16010 case M_MNEM_vqrshrnt
:
16011 case M_MNEM_vqrshrnb
:
16012 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16014 case M_MNEM_vqshrunt
:
16015 case M_MNEM_vqshrunb
:
16016 case M_MNEM_vqrshrunt
:
16017 case M_MNEM_vqrshrunb
:
16018 types
= N_S16
| N_S32
;
16024 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16026 if (inst
.cond
> COND_ALWAYS
)
16027 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16029 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16031 unsigned Qd
= inst
.operands
[0].reg
;
16032 unsigned Qm
= inst
.operands
[1].reg
;
16033 unsigned imm
= inst
.operands
[2].imm
;
16034 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16036 ? _("immediate operand expected in the range [1,8]")
16037 : _("immediate operand expected in the range [1,16]"));
16039 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16040 inst
.instruction
|= HI1 (Qd
) << 22;
16041 inst
.instruction
|= (et
.size
- imm
) << 16;
16042 inst
.instruction
|= LOW4 (Qd
) << 12;
16043 inst
.instruction
|= HI1 (Qm
) << 5;
16044 inst
.instruction
|= LOW4 (Qm
);
16049 do_mve_vqmovn (void)
16051 struct neon_type_el et
;
16052 if (inst
.instruction
== M_MNEM_vqmovnt
16053 || inst
.instruction
== M_MNEM_vqmovnb
)
16054 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16055 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16057 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16059 if (inst
.cond
> COND_ALWAYS
)
16060 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16062 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16064 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16065 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16066 inst
.instruction
|= (et
.size
== 32) << 18;
16067 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16068 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16069 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16074 do_mve_vpsel (void)
16076 neon_select_shape (NS_QQQ
, NS_NULL
);
16078 if (inst
.cond
> COND_ALWAYS
)
16079 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16081 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16083 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16084 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16085 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16086 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16087 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16088 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16093 do_mve_vpnot (void)
16095 if (inst
.cond
> COND_ALWAYS
)
16096 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16098 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16102 do_mve_vmaxnma_vminnma (void)
16104 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16105 struct neon_type_el et
16106 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16108 if (inst
.cond
> COND_ALWAYS
)
16109 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16111 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16113 inst
.instruction
|= (et
.size
== 16) << 28;
16114 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16115 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16116 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16117 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16122 do_mve_vcmul (void)
16124 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16125 struct neon_type_el et
16126 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16128 if (inst
.cond
> COND_ALWAYS
)
16129 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16131 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16133 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16134 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16135 _("immediate out of range"));
16137 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16138 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16139 as_tsktsk (BAD_MVE_SRCDEST
);
16141 inst
.instruction
|= (et
.size
== 32) << 28;
16142 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16143 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16144 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16145 inst
.instruction
|= (rot
> 90) << 12;
16146 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16147 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16148 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16149 inst
.instruction
|= (rot
== 90 || rot
== 270);
16153 /* To handle the Low Overhead Loop instructions
16154 in Armv8.1-M Mainline and MVE. */
16158 unsigned long insn
= inst
.instruction
;
16160 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16162 if (insn
== T_MNEM_lctp
)
16165 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16167 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16169 struct neon_type_el et
16170 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16171 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16178 constraint (!inst
.operands
[0].present
,
16180 /* fall through. */
16183 if (!inst
.operands
[0].present
)
16184 inst
.instruction
|= 1 << 21;
16186 v8_1_loop_reloc (TRUE
);
16191 v8_1_loop_reloc (FALSE
);
16192 /* fall through. */
16195 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16197 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16198 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16199 else if (inst
.operands
[1].reg
== REG_PC
)
16200 as_tsktsk (MVE_BAD_PC
);
16201 if (inst
.operands
[1].reg
== REG_SP
)
16202 as_tsktsk (MVE_BAD_SP
);
16204 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16214 do_vfp_nsyn_cmp (void)
16216 enum neon_shape rs
;
16217 if (!inst
.operands
[0].isreg
)
16224 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16225 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16229 if (inst
.operands
[1].isreg
)
16231 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16232 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16234 if (rs
== NS_FF
|| rs
== NS_HH
)
16236 NEON_ENCODE (SINGLE
, inst
);
16237 do_vfp_sp_monadic ();
16241 NEON_ENCODE (DOUBLE
, inst
);
16242 do_vfp_dp_rd_rm ();
16247 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16248 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16250 switch (inst
.instruction
& 0x0fffffff)
16253 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16256 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16262 if (rs
== NS_FI
|| rs
== NS_HI
)
16264 NEON_ENCODE (SINGLE
, inst
);
16265 do_vfp_sp_compare_z ();
16269 NEON_ENCODE (DOUBLE
, inst
);
16273 do_vfp_cond_or_thumb ();
16275 /* ARMv8.2 fp16 instruction. */
16276 if (rs
== NS_HI
|| rs
== NS_HH
)
16277 do_scalar_fp16_v82_encode ();
16281 nsyn_insert_sp (void)
16283 inst
.operands
[1] = inst
.operands
[0];
16284 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16285 inst
.operands
[0].reg
= REG_SP
;
16286 inst
.operands
[0].isreg
= 1;
16287 inst
.operands
[0].writeback
= 1;
16288 inst
.operands
[0].present
= 1;
16292 do_vfp_nsyn_push (void)
16296 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16297 _("register list must contain at least 1 and at most 16 "
16300 if (inst
.operands
[1].issingle
)
16301 do_vfp_nsyn_opcode ("fstmdbs");
16303 do_vfp_nsyn_opcode ("fstmdbd");
16307 do_vfp_nsyn_pop (void)
16311 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16312 _("register list must contain at least 1 and at most 16 "
16315 if (inst
.operands
[1].issingle
)
16316 do_vfp_nsyn_opcode ("fldmias");
16318 do_vfp_nsyn_opcode ("fldmiad");
16321 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16322 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16325 neon_dp_fixup (struct arm_it
* insn
)
16327 unsigned int i
= insn
->instruction
;
16332 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16343 insn
->instruction
= i
;
16347 mve_encode_qqr (int size
, int U
, int fp
)
16349 if (inst
.operands
[2].reg
== REG_SP
)
16350 as_tsktsk (MVE_BAD_SP
);
16351 else if (inst
.operands
[2].reg
== REG_PC
)
16352 as_tsktsk (MVE_BAD_PC
);
16357 if (((unsigned)inst
.instruction
) == 0xd00)
16358 inst
.instruction
= 0xee300f40;
16360 else if (((unsigned)inst
.instruction
) == 0x200d00)
16361 inst
.instruction
= 0xee301f40;
16363 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16364 inst
.instruction
= 0xee310e60;
16366 /* Setting size which is 1 for F16 and 0 for F32. */
16367 inst
.instruction
|= (size
== 16) << 28;
16372 if (((unsigned)inst
.instruction
) == 0x800)
16373 inst
.instruction
= 0xee010f40;
16375 else if (((unsigned)inst
.instruction
) == 0x1000800)
16376 inst
.instruction
= 0xee011f40;
16378 else if (((unsigned)inst
.instruction
) == 0)
16379 inst
.instruction
= 0xee000f40;
16381 else if (((unsigned)inst
.instruction
) == 0x200)
16382 inst
.instruction
= 0xee001f40;
16384 else if (((unsigned)inst
.instruction
) == 0x900)
16385 inst
.instruction
= 0xee010e40;
16387 else if (((unsigned)inst
.instruction
) == 0x910)
16388 inst
.instruction
= 0xee011e60;
16390 else if (((unsigned)inst
.instruction
) == 0x10)
16391 inst
.instruction
= 0xee000f60;
16393 else if (((unsigned)inst
.instruction
) == 0x210)
16394 inst
.instruction
= 0xee001f60;
16396 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16397 inst
.instruction
= 0xee000e40;
16399 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16400 inst
.instruction
= 0xee010e60;
16402 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16403 inst
.instruction
= 0xfe010e60;
16406 inst
.instruction
|= U
<< 28;
16408 /* Setting bits for size. */
16409 inst
.instruction
|= neon_logbits (size
) << 20;
16411 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16412 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16413 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16414 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16415 inst
.instruction
|= inst
.operands
[2].reg
;
16420 mve_encode_rqq (unsigned bit28
, unsigned size
)
16422 inst
.instruction
|= bit28
<< 28;
16423 inst
.instruction
|= neon_logbits (size
) << 20;
16424 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16425 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16426 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16427 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16428 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16433 mve_encode_qqq (int ubit
, int size
)
16436 inst
.instruction
|= (ubit
!= 0) << 28;
16437 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16438 inst
.instruction
|= neon_logbits (size
) << 20;
16439 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16440 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16441 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16442 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16443 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16449 mve_encode_rq (unsigned bit28
, unsigned size
)
16451 inst
.instruction
|= bit28
<< 28;
16452 inst
.instruction
|= neon_logbits (size
) << 18;
16453 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16454 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16459 mve_encode_rrqq (unsigned U
, unsigned size
)
16461 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16463 inst
.instruction
|= U
<< 28;
16464 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16465 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16466 inst
.instruction
|= (size
== 32) << 16;
16467 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16468 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16469 inst
.instruction
|= inst
.operands
[3].reg
;
16473 /* Encode insns with bit pattern:
16475 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16476 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16478 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16479 different meaning for some instruction. */
16482 neon_three_same (int isquad
, int ubit
, int size
)
16484 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16485 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16486 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16487 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16488 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16489 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16490 inst
.instruction
|= (isquad
!= 0) << 6;
16491 inst
.instruction
|= (ubit
!= 0) << 24;
16493 inst
.instruction
|= neon_logbits (size
) << 20;
16495 neon_dp_fixup (&inst
);
16498 /* Encode instructions of the form:
16500 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16501 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16503 Don't write size if SIZE == -1. */
16506 neon_two_same (int qbit
, int ubit
, int size
)
16508 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16509 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16510 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16511 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16512 inst
.instruction
|= (qbit
!= 0) << 6;
16513 inst
.instruction
|= (ubit
!= 0) << 24;
16516 inst
.instruction
|= neon_logbits (size
) << 18;
16518 neon_dp_fixup (&inst
);
16521 enum vfp_or_neon_is_neon_bits
16524 NEON_CHECK_ARCH
= 2,
16525 NEON_CHECK_ARCH8
= 4
16528 /* Call this function if an instruction which may have belonged to the VFP or
16529 Neon instruction sets, but turned out to be a Neon instruction (due to the
16530 operand types involved, etc.). We have to check and/or fix-up a couple of
16533 - Make sure the user hasn't attempted to make a Neon instruction
16535 - Alter the value in the condition code field if necessary.
16536 - Make sure that the arch supports Neon instructions.
16538 Which of these operations take place depends on bits from enum
16539 vfp_or_neon_is_neon_bits.
16541 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16542 current instruction's condition is COND_ALWAYS, the condition field is
16543 changed to inst.uncond_value. This is necessary because instructions shared
16544 between VFP and Neon may be conditional for the VFP variants only, and the
16545 unconditional Neon version must have, e.g., 0xF in the condition field. */
16548 vfp_or_neon_is_neon (unsigned check
)
16550 /* Conditions are always legal in Thumb mode (IT blocks). */
16551 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16553 if (inst
.cond
!= COND_ALWAYS
)
16555 first_error (_(BAD_COND
));
16558 if (inst
.uncond_value
!= -1)
16559 inst
.instruction
|= inst
.uncond_value
<< 28;
16563 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16564 || ((check
& NEON_CHECK_ARCH8
)
16565 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16567 first_error (_(BAD_FPU
));
16575 /* Return TRUE if the SIMD instruction is available for the current
16576 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16577 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16578 vfp_or_neon_is_neon for the NEON specific checks. */
16581 check_simd_pred_availability (int fp
, unsigned check
)
16583 if (inst
.cond
> COND_ALWAYS
)
16585 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16587 inst
.error
= BAD_FPU
;
16590 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16592 else if (inst
.cond
< COND_ALWAYS
)
16594 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16595 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16596 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16601 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16602 && vfp_or_neon_is_neon (check
) == FAIL
)
16605 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16606 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16611 /* Neon instruction encoders, in approximate order of appearance. */
16614 do_neon_dyadic_i_su (void)
16616 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16619 enum neon_shape rs
;
16620 struct neon_type_el et
;
16621 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16622 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16624 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16626 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16630 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16632 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16636 do_neon_dyadic_i64_su (void)
16638 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16640 enum neon_shape rs
;
16641 struct neon_type_el et
;
16642 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16644 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16645 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16649 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16650 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16653 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16655 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16659 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16662 unsigned size
= et
.size
>> 3;
16663 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16664 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16665 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16666 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16667 inst
.instruction
|= (isquad
!= 0) << 6;
16668 inst
.instruction
|= immbits
<< 16;
16669 inst
.instruction
|= (size
>> 3) << 7;
16670 inst
.instruction
|= (size
& 0x7) << 19;
16672 inst
.instruction
|= (uval
!= 0) << 24;
16674 neon_dp_fixup (&inst
);
16680 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16683 if (!inst
.operands
[2].isreg
)
16685 enum neon_shape rs
;
16686 struct neon_type_el et
;
16687 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16689 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16690 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16694 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16695 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16697 int imm
= inst
.operands
[2].imm
;
16699 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16700 _("immediate out of range for shift"));
16701 NEON_ENCODE (IMMED
, inst
);
16702 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16706 enum neon_shape rs
;
16707 struct neon_type_el et
;
16708 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16710 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16711 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16715 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16716 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16722 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16723 _("invalid instruction shape"));
16724 if (inst
.operands
[2].reg
== REG_SP
)
16725 as_tsktsk (MVE_BAD_SP
);
16726 else if (inst
.operands
[2].reg
== REG_PC
)
16727 as_tsktsk (MVE_BAD_PC
);
16729 inst
.instruction
= 0xee311e60;
16730 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16731 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16732 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16733 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16734 inst
.instruction
|= inst
.operands
[2].reg
;
16741 /* VSHL/VQSHL 3-register variants have syntax such as:
16743 whereas other 3-register operations encoded by neon_three_same have
16746 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16747 operands[2].reg here. */
16748 tmp
= inst
.operands
[2].reg
;
16749 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16750 inst
.operands
[1].reg
= tmp
;
16751 NEON_ENCODE (INTEGER
, inst
);
16752 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16758 do_neon_qshl (void)
16760 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16763 if (!inst
.operands
[2].isreg
)
16765 enum neon_shape rs
;
16766 struct neon_type_el et
;
16767 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16769 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16770 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
16774 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16775 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16777 int imm
= inst
.operands
[2].imm
;
16779 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16780 _("immediate out of range for shift"));
16781 NEON_ENCODE (IMMED
, inst
);
16782 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16786 enum neon_shape rs
;
16787 struct neon_type_el et
;
16789 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16791 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16792 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16796 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16797 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16802 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16803 _("invalid instruction shape"));
16804 if (inst
.operands
[2].reg
== REG_SP
)
16805 as_tsktsk (MVE_BAD_SP
);
16806 else if (inst
.operands
[2].reg
== REG_PC
)
16807 as_tsktsk (MVE_BAD_PC
);
16809 inst
.instruction
= 0xee311ee0;
16810 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16811 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16812 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16813 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16814 inst
.instruction
|= inst
.operands
[2].reg
;
16821 /* See note in do_neon_shl. */
16822 tmp
= inst
.operands
[2].reg
;
16823 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16824 inst
.operands
[1].reg
= tmp
;
16825 NEON_ENCODE (INTEGER
, inst
);
16826 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16832 do_neon_rshl (void)
16834 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16837 enum neon_shape rs
;
16838 struct neon_type_el et
;
16839 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16841 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16842 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16846 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16847 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16854 if (inst
.operands
[2].reg
== REG_PC
)
16855 as_tsktsk (MVE_BAD_PC
);
16856 else if (inst
.operands
[2].reg
== REG_SP
)
16857 as_tsktsk (MVE_BAD_SP
);
16859 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16860 _("invalid instruction shape"));
16862 if (inst
.instruction
== 0x0000510)
16863 /* We are dealing with vqrshl. */
16864 inst
.instruction
= 0xee331ee0;
16866 /* We are dealing with vrshl. */
16867 inst
.instruction
= 0xee331e60;
16869 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16870 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16871 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16872 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16873 inst
.instruction
|= inst
.operands
[2].reg
;
16878 tmp
= inst
.operands
[2].reg
;
16879 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16880 inst
.operands
[1].reg
= tmp
;
16881 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16886 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
16888 /* Handle .I8 pseudo-instructions. */
16891 /* Unfortunately, this will make everything apart from zero out-of-range.
16892 FIXME is this the intended semantics? There doesn't seem much point in
16893 accepting .I8 if so. */
16894 immediate
|= immediate
<< 8;
16900 if (immediate
== (immediate
& 0x000000ff))
16902 *immbits
= immediate
;
16905 else if (immediate
== (immediate
& 0x0000ff00))
16907 *immbits
= immediate
>> 8;
16910 else if (immediate
== (immediate
& 0x00ff0000))
16912 *immbits
= immediate
>> 16;
16915 else if (immediate
== (immediate
& 0xff000000))
16917 *immbits
= immediate
>> 24;
16920 if ((immediate
& 0xffff) != (immediate
>> 16))
16921 goto bad_immediate
;
16922 immediate
&= 0xffff;
16925 if (immediate
== (immediate
& 0x000000ff))
16927 *immbits
= immediate
;
16930 else if (immediate
== (immediate
& 0x0000ff00))
16932 *immbits
= immediate
>> 8;
16937 first_error (_("immediate value out of range"));
16942 do_neon_logic (void)
16944 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
16946 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16948 && !check_simd_pred_availability (FALSE
,
16949 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16951 else if (rs
!= NS_QQQ
16952 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16953 first_error (BAD_FPU
);
16955 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16956 /* U bit and size field were set as part of the bitmask. */
16957 NEON_ENCODE (INTEGER
, inst
);
16958 neon_three_same (neon_quad (rs
), 0, -1);
16962 const int three_ops_form
= (inst
.operands
[2].present
16963 && !inst
.operands
[2].isreg
);
16964 const int immoperand
= (three_ops_form
? 2 : 1);
16965 enum neon_shape rs
= (three_ops_form
16966 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
16967 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
16968 /* Because neon_select_shape makes the second operand a copy of the first
16969 if the second operand is not present. */
16971 && !check_simd_pred_availability (FALSE
,
16972 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16974 else if (rs
!= NS_QQI
16975 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16976 first_error (BAD_FPU
);
16978 struct neon_type_el et
;
16979 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16980 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
16982 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
16985 if (et
.type
== NT_invtype
)
16987 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
16992 if (three_ops_form
)
16993 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16994 _("first and second operands shall be the same register"));
16996 NEON_ENCODE (IMMED
, inst
);
16998 immbits
= inst
.operands
[immoperand
].imm
;
17001 /* .i64 is a pseudo-op, so the immediate must be a repeating
17003 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17004 inst
.operands
[immoperand
].reg
: 0))
17006 /* Set immbits to an invalid constant. */
17007 immbits
= 0xdeadbeef;
17014 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17018 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17022 /* Pseudo-instruction for VBIC. */
17023 neon_invert_size (&immbits
, 0, et
.size
);
17024 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17028 /* Pseudo-instruction for VORR. */
17029 neon_invert_size (&immbits
, 0, et
.size
);
17030 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17040 inst
.instruction
|= neon_quad (rs
) << 6;
17041 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17042 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17043 inst
.instruction
|= cmode
<< 8;
17044 neon_write_immbits (immbits
);
17046 neon_dp_fixup (&inst
);
17051 do_neon_bitfield (void)
17053 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17054 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17055 neon_three_same (neon_quad (rs
), 0, -1);
17059 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17062 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17063 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17065 if (et
.type
== NT_float
)
17067 NEON_ENCODE (FLOAT
, inst
);
17069 mve_encode_qqr (et
.size
, 0, 1);
17071 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17075 NEON_ENCODE (INTEGER
, inst
);
17077 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17079 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17085 do_neon_dyadic_if_su_d (void)
17087 /* This version only allow D registers, but that constraint is enforced during
17088 operand parsing so we don't need to do anything extra here. */
17089 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17093 do_neon_dyadic_if_i_d (void)
17095 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17096 affected if we specify unsigned args. */
17097 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17101 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17103 constraint (size
< 32, BAD_ADDR_MODE
);
17104 constraint (size
!= elsize
, BAD_EL_TYPE
);
17105 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17106 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17107 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17108 _("destination register and offset register may not be the"
17111 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17118 constraint ((imm
% (size
/ 8) != 0)
17119 || imm
> (0x7f << neon_logbits (size
)),
17120 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17121 " range of +/-[0,508]")
17122 : _("immediate must be a multiple of 8 in the"
17123 " range of +/-[0,1016]"));
17124 inst
.instruction
|= 0x11 << 24;
17125 inst
.instruction
|= add
<< 23;
17126 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17127 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17128 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17129 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17130 inst
.instruction
|= 1 << 12;
17131 inst
.instruction
|= (size
== 64) << 8;
17132 inst
.instruction
&= 0xffffff00;
17133 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17134 inst
.instruction
|= imm
>> neon_logbits (size
);
17138 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17140 unsigned os
= inst
.operands
[1].imm
>> 5;
17141 constraint (os
!= 0 && size
== 8,
17142 _("can not shift offsets when accessing less than half-word"));
17143 constraint (os
&& os
!= neon_logbits (size
),
17144 _("shift immediate must be 1, 2 or 3 for half-word, word"
17145 " or double-word accesses respectively"));
17146 if (inst
.operands
[1].reg
== REG_PC
)
17147 as_tsktsk (MVE_BAD_PC
);
17152 constraint (elsize
>= 64, BAD_EL_TYPE
);
17155 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17159 constraint (elsize
!= size
, BAD_EL_TYPE
);
17164 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17168 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17169 _("destination register and offset register may not be"
17171 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
17173 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
17174 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
17175 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
17179 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
17182 inst
.instruction
|= 1 << 23;
17183 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17184 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17185 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17186 inst
.instruction
|= neon_logbits (elsize
) << 7;
17187 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17188 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17189 inst
.instruction
|= !!os
;
17193 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17195 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17197 constraint (size
>= 64, BAD_ADDR_MODE
);
17201 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17204 constraint (elsize
!= size
, BAD_EL_TYPE
);
17211 constraint (elsize
!= size
&& type
!= NT_unsigned
17212 && type
!= NT_signed
, BAD_EL_TYPE
);
17216 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17219 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17227 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17232 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17235 constraint (1, _("immediate must be a multiple of 2 in the"
17236 " range of +/-[0,254]"));
17239 constraint (1, _("immediate must be a multiple of 4 in the"
17240 " range of +/-[0,508]"));
17245 if (size
!= elsize
)
17247 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17248 constraint (inst
.operands
[0].reg
> 14,
17249 _("MVE vector register in the range [Q0..Q7] expected"));
17250 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17251 inst
.instruction
|= (size
== 16) << 19;
17252 inst
.instruction
|= neon_logbits (elsize
) << 7;
17256 if (inst
.operands
[1].reg
== REG_PC
)
17257 as_tsktsk (MVE_BAD_PC
);
17258 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17259 as_tsktsk (MVE_BAD_SP
);
17260 inst
.instruction
|= 1 << 12;
17261 inst
.instruction
|= neon_logbits (size
) << 7;
17263 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17264 inst
.instruction
|= add
<< 23;
17265 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17266 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17267 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17268 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17269 inst
.instruction
&= 0xffffff80;
17270 inst
.instruction
|= imm
>> neon_logbits (size
);
17275 do_mve_vstr_vldr (void)
17280 if (inst
.cond
> COND_ALWAYS
)
17281 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17283 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17285 switch (inst
.instruction
)
17292 /* fall through. */
17298 /* fall through. */
17304 /* fall through. */
17310 /* fall through. */
17315 unsigned elsize
= inst
.vectype
.el
[0].size
;
17317 if (inst
.operands
[1].isquad
)
17319 /* We are dealing with [Q, imm]{!} cases. */
17320 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17324 if (inst
.operands
[1].immisreg
== 2)
17326 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17327 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17329 else if (!inst
.operands
[1].immisreg
)
17331 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17332 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17335 constraint (1, BAD_ADDR_MODE
);
17342 do_mve_vst_vld (void)
17344 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17347 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17348 || inst
.relocs
[0].exp
.X_add_number
!= 0
17349 || inst
.operands
[1].immisreg
!= 0,
17351 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17352 if (inst
.operands
[1].reg
== REG_PC
)
17353 as_tsktsk (MVE_BAD_PC
);
17354 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17355 as_tsktsk (MVE_BAD_SP
);
17358 /* These instructions are one of the "exceptions" mentioned in
17359 handle_pred_state. They are MVE instructions that are not VPT compatible
17360 and do not accept a VPT code, thus appending such a code is a syntax
17362 if (inst
.cond
> COND_ALWAYS
)
17363 first_error (BAD_SYNTAX
);
17364 /* If we append a scalar condition code we can set this to
17365 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17366 else if (inst
.cond
< COND_ALWAYS
)
17367 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17369 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17371 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17372 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17373 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17374 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17375 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17380 do_mve_vaddlv (void)
17382 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17383 struct neon_type_el et
17384 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17386 if (et
.type
== NT_invtype
)
17387 first_error (BAD_EL_TYPE
);
17389 if (inst
.cond
> COND_ALWAYS
)
17390 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17392 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17394 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17396 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17397 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17398 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17399 inst
.instruction
|= inst
.operands
[2].reg
;
17404 do_neon_dyadic_if_su (void)
17406 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17407 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17410 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17411 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17412 && et
.type
== NT_float
17413 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17415 if (!check_simd_pred_availability (et
.type
== NT_float
,
17416 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17419 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17423 do_neon_addsub_if_i (void)
17425 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17426 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17429 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17430 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17431 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17433 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17434 /* If we are parsing Q registers and the element types match MVE, which NEON
17435 also supports, then we must check whether this is an instruction that can
17436 be used by both MVE/NEON. This distinction can be made based on whether
17437 they are predicated or not. */
17438 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17440 if (!check_simd_pred_availability (et
.type
== NT_float
,
17441 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17446 /* If they are either in a D register or are using an unsupported. */
17448 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17452 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17453 affected if we specify unsigned args. */
17454 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17457 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17459 V<op> A,B (A is operand 0, B is operand 2)
17464 so handle that case specially. */
17467 neon_exchange_operands (void)
17469 if (inst
.operands
[1].present
)
17471 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17473 /* Swap operands[1] and operands[2]. */
17474 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17475 inst
.operands
[1] = inst
.operands
[2];
17476 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17481 inst
.operands
[1] = inst
.operands
[2];
17482 inst
.operands
[2] = inst
.operands
[0];
17487 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17489 if (inst
.operands
[2].isreg
)
17492 neon_exchange_operands ();
17493 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17497 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17498 struct neon_type_el et
= neon_check_type (2, rs
,
17499 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17501 NEON_ENCODE (IMMED
, inst
);
17502 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17503 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17504 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17505 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17506 inst
.instruction
|= neon_quad (rs
) << 6;
17507 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17508 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17510 neon_dp_fixup (&inst
);
17517 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17521 do_neon_cmp_inv (void)
17523 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17529 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17532 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17533 scalars, which are encoded in 5 bits, M : Rm.
17534 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17535 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17538 Dot Product instructions are similar to multiply instructions except elsize
17539 should always be 32.
17541 This function translates SCALAR, which is GAS's internal encoding of indexed
17542 scalar register, to raw encoding. There is also register and index range
17543 check based on ELSIZE. */
17546 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17548 unsigned regno
= NEON_SCALAR_REG (scalar
);
17549 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17554 if (regno
> 7 || elno
> 3)
17556 return regno
| (elno
<< 3);
17559 if (regno
> 15 || elno
> 1)
17561 return regno
| (elno
<< 4);
17565 first_error (_("scalar out of range for multiply instruction"));
17571 /* Encode multiply / multiply-accumulate scalar instructions. */
17574 neon_mul_mac (struct neon_type_el et
, int ubit
)
17578 /* Give a more helpful error message if we have an invalid type. */
17579 if (et
.type
== NT_invtype
)
17582 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17583 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17584 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17585 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17586 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17587 inst
.instruction
|= LOW4 (scalar
);
17588 inst
.instruction
|= HI1 (scalar
) << 5;
17589 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17590 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17591 inst
.instruction
|= (ubit
!= 0) << 24;
17593 neon_dp_fixup (&inst
);
17597 do_neon_mac_maybe_scalar (void)
17599 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17602 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17605 if (inst
.operands
[2].isscalar
)
17607 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17608 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17609 struct neon_type_el et
= neon_check_type (3, rs
,
17610 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17611 NEON_ENCODE (SCALAR
, inst
);
17612 neon_mul_mac (et
, neon_quad (rs
));
17614 else if (!inst
.operands
[2].isvec
)
17616 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17618 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17619 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17621 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17625 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17626 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17627 affected if we specify unsigned args. */
17628 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17633 do_neon_fmac (void)
17635 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17636 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17639 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17642 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17644 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17645 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17650 if (inst
.operands
[2].reg
== REG_SP
)
17651 as_tsktsk (MVE_BAD_SP
);
17652 else if (inst
.operands
[2].reg
== REG_PC
)
17653 as_tsktsk (MVE_BAD_PC
);
17655 inst
.instruction
= 0xee310e40;
17656 inst
.instruction
|= (et
.size
== 16) << 28;
17657 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17658 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17659 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17660 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17661 inst
.instruction
|= inst
.operands
[2].reg
;
17668 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17671 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17677 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17678 struct neon_type_el et
= neon_check_type (3, rs
,
17679 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17680 neon_three_same (neon_quad (rs
), 0, et
.size
);
17683 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17684 same types as the MAC equivalents. The polynomial type for this instruction
17685 is encoded the same as the integer type. */
17690 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17693 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17696 if (inst
.operands
[2].isscalar
)
17698 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17699 do_neon_mac_maybe_scalar ();
17703 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17705 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17706 struct neon_type_el et
17707 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17708 if (et
.type
== NT_float
)
17709 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17712 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17716 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17717 neon_dyadic_misc (NT_poly
,
17718 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17724 do_neon_qdmulh (void)
17726 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17729 if (inst
.operands
[2].isscalar
)
17731 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17732 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17733 struct neon_type_el et
= neon_check_type (3, rs
,
17734 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17735 NEON_ENCODE (SCALAR
, inst
);
17736 neon_mul_mac (et
, neon_quad (rs
));
17740 enum neon_shape rs
;
17741 struct neon_type_el et
;
17742 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17744 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17745 et
= neon_check_type (3, rs
,
17746 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17750 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17751 et
= neon_check_type (3, rs
,
17752 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17755 NEON_ENCODE (INTEGER
, inst
);
17757 mve_encode_qqr (et
.size
, 0, 0);
17759 /* The U bit (rounding) comes from bit mask. */
17760 neon_three_same (neon_quad (rs
), 0, et
.size
);
17765 do_mve_vaddv (void)
17767 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17768 struct neon_type_el et
17769 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17771 if (et
.type
== NT_invtype
)
17772 first_error (BAD_EL_TYPE
);
17774 if (inst
.cond
> COND_ALWAYS
)
17775 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17777 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17779 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17781 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17785 do_mve_vhcadd (void)
17787 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17788 struct neon_type_el et
17789 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17791 if (inst
.cond
> COND_ALWAYS
)
17792 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17794 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17796 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17797 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17799 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17800 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17801 "operand makes instruction UNPREDICTABLE"));
17803 mve_encode_qqq (0, et
.size
);
17804 inst
.instruction
|= (rot
== 270) << 12;
17809 do_mve_vqdmull (void)
17811 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17812 struct neon_type_el et
17813 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17816 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17817 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
17818 as_tsktsk (BAD_MVE_SRCDEST
);
17820 if (inst
.cond
> COND_ALWAYS
)
17821 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17823 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17827 mve_encode_qqq (et
.size
== 32, 64);
17828 inst
.instruction
|= 1;
17832 mve_encode_qqr (64, et
.size
== 32, 0);
17833 inst
.instruction
|= 0x3 << 5;
17840 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17841 struct neon_type_el et
17842 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17844 if (et
.type
== NT_invtype
)
17845 first_error (BAD_EL_TYPE
);
17847 if (inst
.cond
> COND_ALWAYS
)
17848 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17850 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17852 mve_encode_qqq (0, 64);
17856 do_mve_vbrsr (void)
17858 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17859 struct neon_type_el et
17860 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17862 if (inst
.cond
> COND_ALWAYS
)
17863 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17865 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17867 mve_encode_qqr (et
.size
, 0, 0);
17873 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
17875 if (inst
.cond
> COND_ALWAYS
)
17876 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17878 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17880 mve_encode_qqq (1, 64);
17884 do_mve_vmulh (void)
17886 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17887 struct neon_type_el et
17888 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17890 if (inst
.cond
> COND_ALWAYS
)
17891 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17893 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17895 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17899 do_mve_vqdmlah (void)
17901 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17902 struct neon_type_el et
17903 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17905 if (inst
.cond
> COND_ALWAYS
)
17906 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17908 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17910 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
17914 do_mve_vqdmladh (void)
17916 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17917 struct neon_type_el et
17918 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17920 if (inst
.cond
> COND_ALWAYS
)
17921 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17923 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17926 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17927 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17928 as_tsktsk (BAD_MVE_SRCDEST
);
17930 mve_encode_qqq (0, et
.size
);
17935 do_mve_vmull (void)
17938 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
17939 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
17940 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17941 && inst
.cond
== COND_ALWAYS
17942 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
17947 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17948 N_SUF_32
| N_F64
| N_P8
17949 | N_P16
| N_I_MVE
| N_KEY
);
17950 if (((et
.type
== NT_poly
) && et
.size
== 8
17951 && ARM_CPU_IS_ANY (cpu_variant
))
17952 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
17959 constraint (rs
!= NS_QQQ
, BAD_FPU
);
17960 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17961 N_SU_32
| N_P8
| N_P16
| N_KEY
);
17963 /* We are dealing with MVE's vmullt. */
17965 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17966 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17967 as_tsktsk (BAD_MVE_SRCDEST
);
17969 if (inst
.cond
> COND_ALWAYS
)
17970 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17972 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17974 if (et
.type
== NT_poly
)
17975 mve_encode_qqq (neon_logbits (et
.size
), 64);
17977 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17982 inst
.instruction
= N_MNEM_vmul
;
17985 inst
.pred_insn_type
= INSIDE_IT_INSN
;
17990 do_mve_vabav (void)
17992 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17997 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18000 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18001 | N_S16
| N_S32
| N_U8
| N_U16
18004 if (inst
.cond
> COND_ALWAYS
)
18005 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18007 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18009 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18013 do_mve_vmladav (void)
18015 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18016 struct neon_type_el et
= neon_check_type (3, rs
,
18017 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18019 if (et
.type
== NT_unsigned
18020 && (inst
.instruction
== M_MNEM_vmladavx
18021 || inst
.instruction
== M_MNEM_vmladavax
18022 || inst
.instruction
== M_MNEM_vmlsdav
18023 || inst
.instruction
== M_MNEM_vmlsdava
18024 || inst
.instruction
== M_MNEM_vmlsdavx
18025 || inst
.instruction
== M_MNEM_vmlsdavax
))
18026 first_error (BAD_SIMD_TYPE
);
18028 constraint (inst
.operands
[2].reg
> 14,
18029 _("MVE vector register in the range [Q0..Q7] expected"));
18031 if (inst
.cond
> COND_ALWAYS
)
18032 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18034 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18036 if (inst
.instruction
== M_MNEM_vmlsdav
18037 || inst
.instruction
== M_MNEM_vmlsdava
18038 || inst
.instruction
== M_MNEM_vmlsdavx
18039 || inst
.instruction
== M_MNEM_vmlsdavax
)
18040 inst
.instruction
|= (et
.size
== 8) << 28;
18042 inst
.instruction
|= (et
.size
== 8) << 8;
18044 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18045 inst
.instruction
|= (et
.size
== 32) << 16;
18049 do_mve_vmlaldav (void)
18051 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18052 struct neon_type_el et
18053 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18054 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18056 if (et
.type
== NT_unsigned
18057 && (inst
.instruction
== M_MNEM_vmlsldav
18058 || inst
.instruction
== M_MNEM_vmlsldava
18059 || inst
.instruction
== M_MNEM_vmlsldavx
18060 || inst
.instruction
== M_MNEM_vmlsldavax
))
18061 first_error (BAD_SIMD_TYPE
);
18063 if (inst
.cond
> COND_ALWAYS
)
18064 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18066 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18068 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18072 do_mve_vrmlaldavh (void)
18074 struct neon_type_el et
;
18075 if (inst
.instruction
== M_MNEM_vrmlsldavh
18076 || inst
.instruction
== M_MNEM_vrmlsldavha
18077 || inst
.instruction
== M_MNEM_vrmlsldavhx
18078 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18080 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18081 if (inst
.operands
[1].reg
== REG_SP
)
18082 as_tsktsk (MVE_BAD_SP
);
18086 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18087 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18088 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18090 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18091 N_U32
| N_S32
| N_KEY
);
18092 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18093 with vmax/min instructions, making the use of SP in assembly really
18094 nonsensical, so instead of issuing a warning like we do for other uses
18095 of SP for the odd register operand we error out. */
18096 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18099 /* Make sure we still check the second operand is an odd one and that PC is
18100 disallowed. This because we are parsing for any GPR operand, to be able
18101 to distinguish between giving a warning or an error for SP as described
18103 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18104 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18106 if (inst
.cond
> COND_ALWAYS
)
18107 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18109 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18111 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18116 do_mve_vmaxnmv (void)
18118 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18119 struct neon_type_el et
18120 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18122 if (inst
.cond
> COND_ALWAYS
)
18123 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18125 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18127 if (inst
.operands
[0].reg
== REG_SP
)
18128 as_tsktsk (MVE_BAD_SP
);
18129 else if (inst
.operands
[0].reg
== REG_PC
)
18130 as_tsktsk (MVE_BAD_PC
);
18132 mve_encode_rq (et
.size
== 16, 64);
18136 do_mve_vmaxv (void)
18138 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18139 struct neon_type_el et
;
18141 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18142 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18144 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18146 if (inst
.cond
> COND_ALWAYS
)
18147 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18149 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18151 if (inst
.operands
[0].reg
== REG_SP
)
18152 as_tsktsk (MVE_BAD_SP
);
18153 else if (inst
.operands
[0].reg
== REG_PC
)
18154 as_tsktsk (MVE_BAD_PC
);
18156 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18161 do_neon_qrdmlah (void)
18163 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18165 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18167 /* Check we're on the correct architecture. */
18168 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18170 = _("instruction form not available on this architecture.");
18171 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18173 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18174 record_feature_use (&fpu_neon_ext_v8_1
);
18176 if (inst
.operands
[2].isscalar
)
18178 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18179 struct neon_type_el et
= neon_check_type (3, rs
,
18180 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18181 NEON_ENCODE (SCALAR
, inst
);
18182 neon_mul_mac (et
, neon_quad (rs
));
18186 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18187 struct neon_type_el et
= neon_check_type (3, rs
,
18188 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18189 NEON_ENCODE (INTEGER
, inst
);
18190 /* The U bit (rounding) comes from bit mask. */
18191 neon_three_same (neon_quad (rs
), 0, et
.size
);
18196 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18197 struct neon_type_el et
18198 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18200 NEON_ENCODE (INTEGER
, inst
);
18201 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18206 do_neon_fcmp_absolute (void)
18208 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18209 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18210 N_F_16_32
| N_KEY
);
18211 /* Size field comes from bit mask. */
18212 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18216 do_neon_fcmp_absolute_inv (void)
18218 neon_exchange_operands ();
18219 do_neon_fcmp_absolute ();
18223 do_neon_step (void)
18225 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18226 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18227 N_F_16_32
| N_KEY
);
18228 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18232 do_neon_abs_neg (void)
18234 enum neon_shape rs
;
18235 struct neon_type_el et
;
18237 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18240 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18241 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18243 if (!check_simd_pred_availability (et
.type
== NT_float
,
18244 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18247 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18248 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18249 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18250 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18251 inst
.instruction
|= neon_quad (rs
) << 6;
18252 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18253 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18255 neon_dp_fixup (&inst
);
18261 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18264 enum neon_shape rs
;
18265 struct neon_type_el et
;
18266 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18268 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18269 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18273 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18274 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18278 int imm
= inst
.operands
[2].imm
;
18279 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18280 _("immediate out of range for insert"));
18281 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18287 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18290 enum neon_shape rs
;
18291 struct neon_type_el et
;
18292 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18294 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18295 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18299 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18300 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18303 int imm
= inst
.operands
[2].imm
;
18304 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18305 _("immediate out of range for insert"));
18306 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18310 do_neon_qshlu_imm (void)
18312 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18315 enum neon_shape rs
;
18316 struct neon_type_el et
;
18317 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18319 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18320 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18324 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18325 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18326 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18329 int imm
= inst
.operands
[2].imm
;
18330 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18331 _("immediate out of range for shift"));
18332 /* Only encodes the 'U present' variant of the instruction.
18333 In this case, signed types have OP (bit 8) set to 0.
18334 Unsigned types have OP set to 1. */
18335 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18336 /* The rest of the bits are the same as other immediate shifts. */
18337 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18341 do_neon_qmovn (void)
18343 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18344 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18345 /* Saturating move where operands can be signed or unsigned, and the
18346 destination has the same signedness. */
18347 NEON_ENCODE (INTEGER
, inst
);
18348 if (et
.type
== NT_unsigned
)
18349 inst
.instruction
|= 0xc0;
18351 inst
.instruction
|= 0x80;
18352 neon_two_same (0, 1, et
.size
/ 2);
18356 do_neon_qmovun (void)
18358 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18359 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18360 /* Saturating move with unsigned results. Operands must be signed. */
18361 NEON_ENCODE (INTEGER
, inst
);
18362 neon_two_same (0, 1, et
.size
/ 2);
18366 do_neon_rshift_sat_narrow (void)
18368 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18369 or unsigned. If operands are unsigned, results must also be unsigned. */
18370 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18371 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18372 int imm
= inst
.operands
[2].imm
;
18373 /* This gets the bounds check, size encoding and immediate bits calculation
18377 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18378 VQMOVN.I<size> <Dd>, <Qm>. */
18381 inst
.operands
[2].present
= 0;
18382 inst
.instruction
= N_MNEM_vqmovn
;
18387 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18388 _("immediate out of range"));
18389 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18393 do_neon_rshift_sat_narrow_u (void)
18395 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18396 or unsigned. If operands are unsigned, results must also be unsigned. */
18397 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18398 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18399 int imm
= inst
.operands
[2].imm
;
18400 /* This gets the bounds check, size encoding and immediate bits calculation
18404 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18405 VQMOVUN.I<size> <Dd>, <Qm>. */
18408 inst
.operands
[2].present
= 0;
18409 inst
.instruction
= N_MNEM_vqmovun
;
18414 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18415 _("immediate out of range"));
18416 /* FIXME: The manual is kind of unclear about what value U should have in
18417 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18419 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18423 do_neon_movn (void)
18425 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18426 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18427 NEON_ENCODE (INTEGER
, inst
);
18428 neon_two_same (0, 1, et
.size
/ 2);
18432 do_neon_rshift_narrow (void)
18434 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18435 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18436 int imm
= inst
.operands
[2].imm
;
18437 /* This gets the bounds check, size encoding and immediate bits calculation
18441 /* If immediate is zero then we are a pseudo-instruction for
18442 VMOVN.I<size> <Dd>, <Qm> */
18445 inst
.operands
[2].present
= 0;
18446 inst
.instruction
= N_MNEM_vmovn
;
18451 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18452 _("immediate out of range for narrowing operation"));
18453 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18457 do_neon_shll (void)
18459 /* FIXME: Type checking when lengthening. */
18460 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18461 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18462 unsigned imm
= inst
.operands
[2].imm
;
18464 if (imm
== et
.size
)
18466 /* Maximum shift variant. */
18467 NEON_ENCODE (INTEGER
, inst
);
18468 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18469 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18470 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18471 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18472 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18474 neon_dp_fixup (&inst
);
18478 /* A more-specific type check for non-max versions. */
18479 et
= neon_check_type (2, NS_QDI
,
18480 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18481 NEON_ENCODE (IMMED
, inst
);
18482 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18486 /* Check the various types for the VCVT instruction, and return which version
18487 the current instruction is. */
18489 #define CVT_FLAVOUR_VAR \
18490 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18491 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18492 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18493 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18494 /* Half-precision conversions. */ \
18495 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18496 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18497 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18498 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18499 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18500 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18501 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18502 Compared with single/double precision variants, only the co-processor \
18503 field is different, so the encoding flow is reused here. */ \
18504 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18505 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18506 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18507 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18508 /* VFP instructions. */ \
18509 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18510 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18511 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18512 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18513 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18514 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18515 /* VFP instructions with bitshift. */ \
18516 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18517 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18518 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18519 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18520 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18521 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18522 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18523 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18525 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18526 neon_cvt_flavour_##C,
18528 /* The different types of conversions we can do. */
18529 enum neon_cvt_flavour
18532 neon_cvt_flavour_invalid
,
18533 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18538 static enum neon_cvt_flavour
18539 get_neon_cvt_flavour (enum neon_shape rs
)
18541 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18542 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18543 if (et.type != NT_invtype) \
18545 inst.error = NULL; \
18546 return (neon_cvt_flavour_##C); \
18549 struct neon_type_el et
;
18550 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18551 || rs
== NS_FF
) ? N_VFP
: 0;
18552 /* The instruction versions which take an immediate take one register
18553 argument, which is extended to the width of the full register. Thus the
18554 "source" and "destination" registers must have the same width. Hack that
18555 here by making the size equal to the key (wider, in this case) operand. */
18556 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18560 return neon_cvt_flavour_invalid
;
18575 /* Neon-syntax VFP conversions. */
18578 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18580 const char *opname
= 0;
18582 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18583 || rs
== NS_FHI
|| rs
== NS_HFI
)
18585 /* Conversions with immediate bitshift. */
18586 const char *enc
[] =
18588 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18594 if (flavour
< (int) ARRAY_SIZE (enc
))
18596 opname
= enc
[flavour
];
18597 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18598 _("operands 0 and 1 must be the same register"));
18599 inst
.operands
[1] = inst
.operands
[2];
18600 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18605 /* Conversions without bitshift. */
18606 const char *enc
[] =
18608 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18614 if (flavour
< (int) ARRAY_SIZE (enc
))
18615 opname
= enc
[flavour
];
18619 do_vfp_nsyn_opcode (opname
);
18621 /* ARMv8.2 fp16 VCVT instruction. */
18622 if (flavour
== neon_cvt_flavour_s32_f16
18623 || flavour
== neon_cvt_flavour_u32_f16
18624 || flavour
== neon_cvt_flavour_f16_u32
18625 || flavour
== neon_cvt_flavour_f16_s32
)
18626 do_scalar_fp16_v82_encode ();
18630 do_vfp_nsyn_cvtz (void)
18632 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18633 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18634 const char *enc
[] =
18636 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18642 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18643 do_vfp_nsyn_opcode (enc
[flavour
]);
18647 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18648 enum neon_cvt_mode mode
)
18653 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18654 D register operands. */
18655 if (flavour
== neon_cvt_flavour_s32_f64
18656 || flavour
== neon_cvt_flavour_u32_f64
)
18657 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18660 if (flavour
== neon_cvt_flavour_s32_f16
18661 || flavour
== neon_cvt_flavour_u32_f16
)
18662 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18665 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18669 case neon_cvt_flavour_s32_f64
:
18673 case neon_cvt_flavour_s32_f32
:
18677 case neon_cvt_flavour_s32_f16
:
18681 case neon_cvt_flavour_u32_f64
:
18685 case neon_cvt_flavour_u32_f32
:
18689 case neon_cvt_flavour_u32_f16
:
18694 first_error (_("invalid instruction shape"));
18700 case neon_cvt_mode_a
: rm
= 0; break;
18701 case neon_cvt_mode_n
: rm
= 1; break;
18702 case neon_cvt_mode_p
: rm
= 2; break;
18703 case neon_cvt_mode_m
: rm
= 3; break;
18704 default: first_error (_("invalid rounding mode")); return;
18707 NEON_ENCODE (FPV8
, inst
);
18708 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18709 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18710 inst
.instruction
|= sz
<< 8;
18712 /* ARMv8.2 fp16 VCVT instruction. */
18713 if (flavour
== neon_cvt_flavour_s32_f16
18714 ||flavour
== neon_cvt_flavour_u32_f16
)
18715 do_scalar_fp16_v82_encode ();
18716 inst
.instruction
|= op
<< 7;
18717 inst
.instruction
|= rm
<< 16;
18718 inst
.instruction
|= 0xf0000000;
18719 inst
.is_neon
= TRUE
;
18723 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18725 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18726 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18727 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18729 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18731 if (flavour
== neon_cvt_flavour_invalid
)
18734 /* PR11109: Handle round-to-zero for VCVT conversions. */
18735 if (mode
== neon_cvt_mode_z
18736 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18737 && (flavour
== neon_cvt_flavour_s16_f16
18738 || flavour
== neon_cvt_flavour_u16_f16
18739 || flavour
== neon_cvt_flavour_s32_f32
18740 || flavour
== neon_cvt_flavour_u32_f32
18741 || flavour
== neon_cvt_flavour_s32_f64
18742 || flavour
== neon_cvt_flavour_u32_f64
)
18743 && (rs
== NS_FD
|| rs
== NS_FF
))
18745 do_vfp_nsyn_cvtz ();
18749 /* ARMv8.2 fp16 VCVT conversions. */
18750 if (mode
== neon_cvt_mode_z
18751 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
18752 && (flavour
== neon_cvt_flavour_s32_f16
18753 || flavour
== neon_cvt_flavour_u32_f16
)
18756 do_vfp_nsyn_cvtz ();
18757 do_scalar_fp16_v82_encode ();
18761 /* VFP rather than Neon conversions. */
18762 if (flavour
>= neon_cvt_flavour_first_fp
)
18764 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18765 do_vfp_nsyn_cvt (rs
, flavour
);
18767 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18775 if (mode
== neon_cvt_mode_z
18776 && (flavour
== neon_cvt_flavour_f16_s16
18777 || flavour
== neon_cvt_flavour_f16_u16
18778 || flavour
== neon_cvt_flavour_s16_f16
18779 || flavour
== neon_cvt_flavour_u16_f16
18780 || flavour
== neon_cvt_flavour_f32_u32
18781 || flavour
== neon_cvt_flavour_f32_s32
18782 || flavour
== neon_cvt_flavour_s32_f32
18783 || flavour
== neon_cvt_flavour_u32_f32
))
18785 if (!check_simd_pred_availability (TRUE
,
18786 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18789 else if (mode
== neon_cvt_mode_n
)
18791 /* We are dealing with vcvt with the 'ne' condition. */
18793 inst
.instruction
= N_MNEM_vcvt
;
18794 do_neon_cvt_1 (neon_cvt_mode_z
);
18797 /* fall through. */
18801 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18802 0x0000100, 0x1000100, 0x0, 0x1000000};
18804 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18805 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18808 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18810 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
18811 _("immediate value out of range"));
18814 case neon_cvt_flavour_f16_s16
:
18815 case neon_cvt_flavour_f16_u16
:
18816 case neon_cvt_flavour_s16_f16
:
18817 case neon_cvt_flavour_u16_f16
:
18818 constraint (inst
.operands
[2].imm
> 16,
18819 _("immediate value out of range"));
18821 case neon_cvt_flavour_f32_u32
:
18822 case neon_cvt_flavour_f32_s32
:
18823 case neon_cvt_flavour_s32_f32
:
18824 case neon_cvt_flavour_u32_f32
:
18825 constraint (inst
.operands
[2].imm
> 32,
18826 _("immediate value out of range"));
18829 inst
.error
= BAD_FPU
;
18834 /* Fixed-point conversion with #0 immediate is encoded as an
18835 integer conversion. */
18836 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
18838 NEON_ENCODE (IMMED
, inst
);
18839 if (flavour
!= neon_cvt_flavour_invalid
)
18840 inst
.instruction
|= enctab
[flavour
];
18841 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18842 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18843 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18844 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18845 inst
.instruction
|= neon_quad (rs
) << 6;
18846 inst
.instruction
|= 1 << 21;
18847 if (flavour
< neon_cvt_flavour_s16_f16
)
18849 inst
.instruction
|= 1 << 21;
18850 immbits
= 32 - inst
.operands
[2].imm
;
18851 inst
.instruction
|= immbits
<< 16;
18855 inst
.instruction
|= 3 << 20;
18856 immbits
= 16 - inst
.operands
[2].imm
;
18857 inst
.instruction
|= immbits
<< 16;
18858 inst
.instruction
&= ~(1 << 9);
18861 neon_dp_fixup (&inst
);
18866 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
18867 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
18868 && (flavour
== neon_cvt_flavour_s16_f16
18869 || flavour
== neon_cvt_flavour_u16_f16
18870 || flavour
== neon_cvt_flavour_s32_f32
18871 || flavour
== neon_cvt_flavour_u32_f32
))
18873 if (!check_simd_pred_availability (TRUE
,
18874 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18877 else if (mode
== neon_cvt_mode_z
18878 && (flavour
== neon_cvt_flavour_f16_s16
18879 || flavour
== neon_cvt_flavour_f16_u16
18880 || flavour
== neon_cvt_flavour_s16_f16
18881 || flavour
== neon_cvt_flavour_u16_f16
18882 || flavour
== neon_cvt_flavour_f32_u32
18883 || flavour
== neon_cvt_flavour_f32_s32
18884 || flavour
== neon_cvt_flavour_s32_f32
18885 || flavour
== neon_cvt_flavour_u32_f32
))
18887 if (!check_simd_pred_availability (TRUE
,
18888 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18891 /* fall through. */
18893 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
18896 NEON_ENCODE (FLOAT
, inst
);
18897 if (!check_simd_pred_availability (TRUE
,
18898 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18901 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18902 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18903 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18904 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18905 inst
.instruction
|= neon_quad (rs
) << 6;
18906 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
18907 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
18908 inst
.instruction
|= mode
<< 8;
18909 if (flavour
== neon_cvt_flavour_u16_f16
18910 || flavour
== neon_cvt_flavour_s16_f16
)
18911 /* Mask off the original size bits and reencode them. */
18912 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
18915 inst
.instruction
|= 0xfc000000;
18917 inst
.instruction
|= 0xf0000000;
18923 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
18924 0x100, 0x180, 0x0, 0x080};
18926 NEON_ENCODE (INTEGER
, inst
);
18928 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18930 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18934 if (flavour
!= neon_cvt_flavour_invalid
)
18935 inst
.instruction
|= enctab
[flavour
];
18937 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18938 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18939 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18940 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18941 inst
.instruction
|= neon_quad (rs
) << 6;
18942 if (flavour
>= neon_cvt_flavour_s16_f16
18943 && flavour
<= neon_cvt_flavour_f16_u16
)
18944 /* Half precision. */
18945 inst
.instruction
|= 1 << 18;
18947 inst
.instruction
|= 2 << 18;
18949 neon_dp_fixup (&inst
);
18954 /* Half-precision conversions for Advanced SIMD -- neon. */
18957 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18961 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
18963 as_bad (_("operand size must match register width"));
18968 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
18970 as_bad (_("operand size must match register width"));
18975 inst
.instruction
= 0x3b60600;
18977 inst
.instruction
= 0x3b60700;
18979 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18980 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18981 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18982 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18983 neon_dp_fixup (&inst
);
18987 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
18988 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18989 do_vfp_nsyn_cvt (rs
, flavour
);
18991 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18996 do_neon_cvtr (void)
18998 do_neon_cvt_1 (neon_cvt_mode_x
);
19004 do_neon_cvt_1 (neon_cvt_mode_z
);
19008 do_neon_cvta (void)
19010 do_neon_cvt_1 (neon_cvt_mode_a
);
19014 do_neon_cvtn (void)
19016 do_neon_cvt_1 (neon_cvt_mode_n
);
19020 do_neon_cvtp (void)
19022 do_neon_cvt_1 (neon_cvt_mode_p
);
19026 do_neon_cvtm (void)
19028 do_neon_cvt_1 (neon_cvt_mode_m
);
19032 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19035 mark_feature_used (&fpu_vfp_ext_armv8
);
19037 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19038 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19039 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19040 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19041 inst
.instruction
|= to
? 0x10000 : 0;
19042 inst
.instruction
|= t
? 0x80 : 0;
19043 inst
.instruction
|= is_double
? 0x100 : 0;
19044 do_vfp_cond_or_thumb ();
19048 do_neon_cvttb_1 (bfd_boolean t
)
19050 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19051 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19055 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19057 int single_to_half
= 0;
19058 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19061 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19063 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19064 && (flavour
== neon_cvt_flavour_u16_f16
19065 || flavour
== neon_cvt_flavour_s16_f16
19066 || flavour
== neon_cvt_flavour_f16_s16
19067 || flavour
== neon_cvt_flavour_f16_u16
19068 || flavour
== neon_cvt_flavour_u32_f32
19069 || flavour
== neon_cvt_flavour_s32_f32
19070 || flavour
== neon_cvt_flavour_f32_s32
19071 || flavour
== neon_cvt_flavour_f32_u32
))
19074 inst
.instruction
= N_MNEM_vcvt
;
19075 set_pred_insn_type (INSIDE_VPT_INSN
);
19076 do_neon_cvt_1 (neon_cvt_mode_z
);
19079 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19080 single_to_half
= 1;
19081 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19083 first_error (BAD_FPU
);
19087 inst
.instruction
= 0xee3f0e01;
19088 inst
.instruction
|= single_to_half
<< 28;
19089 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19090 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19091 inst
.instruction
|= t
<< 12;
19092 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19093 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19096 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19099 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19101 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19104 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19106 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19108 /* The VCVTB and VCVTT instructions with D-register operands
19109 don't work for SP only targets. */
19110 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19114 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19116 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19118 /* The VCVTB and VCVTT instructions with D-register operands
19119 don't work for SP only targets. */
19120 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19124 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19131 do_neon_cvtb (void)
19133 do_neon_cvttb_1 (FALSE
);
19138 do_neon_cvtt (void)
19140 do_neon_cvttb_1 (TRUE
);
19144 neon_move_immediate (void)
19146 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19147 struct neon_type_el et
= neon_check_type (2, rs
,
19148 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19149 unsigned immlo
, immhi
= 0, immbits
;
19150 int op
, cmode
, float_p
;
19152 constraint (et
.type
== NT_invtype
,
19153 _("operand size must be specified for immediate VMOV"));
19155 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19156 op
= (inst
.instruction
& (1 << 5)) != 0;
19158 immlo
= inst
.operands
[1].imm
;
19159 if (inst
.operands
[1].regisimm
)
19160 immhi
= inst
.operands
[1].reg
;
19162 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19163 _("immediate has bits set outside the operand size"));
19165 float_p
= inst
.operands
[1].immisfloat
;
19167 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19168 et
.size
, et
.type
)) == FAIL
)
19170 /* Invert relevant bits only. */
19171 neon_invert_size (&immlo
, &immhi
, et
.size
);
19172 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19173 with one or the other; those cases are caught by
19174 neon_cmode_for_move_imm. */
19176 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19177 &op
, et
.size
, et
.type
)) == FAIL
)
19179 first_error (_("immediate out of range"));
19184 inst
.instruction
&= ~(1 << 5);
19185 inst
.instruction
|= op
<< 5;
19187 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19188 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19189 inst
.instruction
|= neon_quad (rs
) << 6;
19190 inst
.instruction
|= cmode
<< 8;
19192 neon_write_immbits (immbits
);
19198 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19201 if (inst
.operands
[1].isreg
)
19203 enum neon_shape rs
;
19204 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19205 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19207 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19209 NEON_ENCODE (INTEGER
, inst
);
19210 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19211 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19212 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19213 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19214 inst
.instruction
|= neon_quad (rs
) << 6;
19218 NEON_ENCODE (IMMED
, inst
);
19219 neon_move_immediate ();
19222 neon_dp_fixup (&inst
);
19224 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19226 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19227 constraint ((inst
.instruction
& 0xd00) == 0xd00,
19228 _("immediate value out of range"));
19232 /* Encode instructions of form:
19234 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19235 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19238 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19240 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19241 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19242 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19243 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19244 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19245 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19246 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19247 inst
.instruction
|= neon_logbits (size
) << 20;
19249 neon_dp_fixup (&inst
);
19253 do_neon_dyadic_long (void)
19255 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19258 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19261 NEON_ENCODE (INTEGER
, inst
);
19262 /* FIXME: Type checking for lengthening op. */
19263 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19264 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19265 neon_mixed_length (et
, et
.size
);
19267 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19268 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19270 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19271 in an IT block with le/lt conditions. */
19273 if (inst
.cond
== 0xf)
19275 else if (inst
.cond
== 0x10)
19278 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19280 if (inst
.instruction
== N_MNEM_vaddl
)
19282 inst
.instruction
= N_MNEM_vadd
;
19283 do_neon_addsub_if_i ();
19285 else if (inst
.instruction
== N_MNEM_vsubl
)
19287 inst
.instruction
= N_MNEM_vsub
;
19288 do_neon_addsub_if_i ();
19290 else if (inst
.instruction
== N_MNEM_vabdl
)
19292 inst
.instruction
= N_MNEM_vabd
;
19293 do_neon_dyadic_if_su ();
19297 first_error (BAD_FPU
);
19301 do_neon_abal (void)
19303 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19304 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19305 neon_mixed_length (et
, et
.size
);
19309 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19311 if (inst
.operands
[2].isscalar
)
19313 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19314 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19315 NEON_ENCODE (SCALAR
, inst
);
19316 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19320 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19321 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19322 NEON_ENCODE (INTEGER
, inst
);
19323 neon_mixed_length (et
, et
.size
);
19328 do_neon_mac_maybe_scalar_long (void)
19330 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19333 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19334 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19337 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19339 unsigned regno
= NEON_SCALAR_REG (scalar
);
19340 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19344 if (regno
> 7 || elno
> 3)
19347 return ((regno
& 0x7)
19348 | ((elno
& 0x1) << 3)
19349 | (((elno
>> 1) & 0x1) << 5));
19353 if (regno
> 15 || elno
> 1)
19356 return (((regno
& 0x1) << 5)
19357 | ((regno
>> 1) & 0x7)
19358 | ((elno
& 0x1) << 3));
19362 first_error (_("scalar out of range for multiply instruction"));
19367 do_neon_fmac_maybe_scalar_long (int subtype
)
19369 enum neon_shape rs
;
19371 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19372 field (bits[21:20]) has different meaning. For scalar index variant, it's
19373 used to differentiate add and subtract, otherwise it's with fixed value
19377 if (inst
.cond
!= COND_ALWAYS
)
19378 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19379 "behaviour is UNPREDICTABLE"));
19381 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19384 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19387 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19388 be a scalar index register. */
19389 if (inst
.operands
[2].isscalar
)
19391 high8
= 0xfe000000;
19394 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19398 high8
= 0xfc000000;
19401 inst
.instruction
|= (0x1 << 23);
19402 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19405 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
19407 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19408 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19409 so we simply pass -1 as size. */
19410 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19411 neon_three_same (quad_p
, 0, size
);
19413 /* Undo neon_dp_fixup. Redo the high eight bits. */
19414 inst
.instruction
&= 0x00ffffff;
19415 inst
.instruction
|= high8
;
19417 #define LOW1(R) ((R) & 0x1)
19418 #define HI4(R) (((R) >> 1) & 0xf)
19419 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19420 whether the instruction is in Q form and whether Vm is a scalar indexed
19422 if (inst
.operands
[2].isscalar
)
19425 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19426 inst
.instruction
&= 0xffffffd0;
19427 inst
.instruction
|= rm
;
19431 /* Redo Rn as well. */
19432 inst
.instruction
&= 0xfff0ff7f;
19433 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19434 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19439 /* Redo Rn and Rm. */
19440 inst
.instruction
&= 0xfff0ff50;
19441 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19442 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19443 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19444 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19449 do_neon_vfmal (void)
19451 return do_neon_fmac_maybe_scalar_long (0);
19455 do_neon_vfmsl (void)
19457 return do_neon_fmac_maybe_scalar_long (1);
19461 do_neon_dyadic_wide (void)
19463 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19464 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19465 neon_mixed_length (et
, et
.size
);
19469 do_neon_dyadic_narrow (void)
19471 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19472 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19473 /* Operand sign is unimportant, and the U bit is part of the opcode,
19474 so force the operand type to integer. */
19475 et
.type
= NT_integer
;
19476 neon_mixed_length (et
, et
.size
/ 2);
19480 do_neon_mul_sat_scalar_long (void)
19482 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19486 do_neon_vmull (void)
19488 if (inst
.operands
[2].isscalar
)
19489 do_neon_mac_maybe_scalar_long ();
19492 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19493 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19495 if (et
.type
== NT_poly
)
19496 NEON_ENCODE (POLY
, inst
);
19498 NEON_ENCODE (INTEGER
, inst
);
19500 /* For polynomial encoding the U bit must be zero, and the size must
19501 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19502 obviously, as 0b10). */
19505 /* Check we're on the correct architecture. */
19506 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19508 _("Instruction form not available on this architecture.");
19513 neon_mixed_length (et
, et
.size
);
19520 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19521 struct neon_type_el et
= neon_check_type (3, rs
,
19522 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19523 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19525 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19526 _("shift out of range"));
19527 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19528 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19529 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19530 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19531 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19532 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19533 inst
.instruction
|= neon_quad (rs
) << 6;
19534 inst
.instruction
|= imm
<< 8;
19536 neon_dp_fixup (&inst
);
19542 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19545 enum neon_shape rs
;
19546 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19547 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19549 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19551 struct neon_type_el et
= neon_check_type (2, rs
,
19552 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19554 unsigned op
= (inst
.instruction
>> 7) & 3;
19555 /* N (width of reversed regions) is encoded as part of the bitmask. We
19556 extract it here to check the elements to be reversed are smaller.
19557 Otherwise we'd get a reserved instruction. */
19558 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19560 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19561 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19562 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19563 " operands makes instruction UNPREDICTABLE"));
19565 gas_assert (elsize
!= 0);
19566 constraint (et
.size
>= elsize
,
19567 _("elements must be smaller than reversal region"));
19568 neon_two_same (neon_quad (rs
), 1, et
.size
);
19574 if (inst
.operands
[1].isscalar
)
19576 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19578 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19579 struct neon_type_el et
= neon_check_type (2, rs
,
19580 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19581 unsigned sizebits
= et
.size
>> 3;
19582 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19583 int logsize
= neon_logbits (et
.size
);
19584 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19586 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19589 NEON_ENCODE (SCALAR
, inst
);
19590 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19591 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19592 inst
.instruction
|= LOW4 (dm
);
19593 inst
.instruction
|= HI1 (dm
) << 5;
19594 inst
.instruction
|= neon_quad (rs
) << 6;
19595 inst
.instruction
|= x
<< 17;
19596 inst
.instruction
|= sizebits
<< 16;
19598 neon_dp_fixup (&inst
);
19602 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19603 struct neon_type_el et
= neon_check_type (2, rs
,
19604 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19607 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19611 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19614 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19616 if (inst
.operands
[1].reg
== REG_SP
)
19617 as_tsktsk (MVE_BAD_SP
);
19618 else if (inst
.operands
[1].reg
== REG_PC
)
19619 as_tsktsk (MVE_BAD_PC
);
19622 /* Duplicate ARM register to lanes of vector. */
19623 NEON_ENCODE (ARMREG
, inst
);
19626 case 8: inst
.instruction
|= 0x400000; break;
19627 case 16: inst
.instruction
|= 0x000020; break;
19628 case 32: inst
.instruction
|= 0x000000; break;
19631 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19632 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19633 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19634 inst
.instruction
|= neon_quad (rs
) << 21;
19635 /* The encoding for this instruction is identical for the ARM and Thumb
19636 variants, except for the condition field. */
19637 do_vfp_cond_or_thumb ();
19642 do_mve_mov (int toQ
)
19644 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19646 if (inst
.cond
> COND_ALWAYS
)
19647 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19649 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19658 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19659 _("Index one must be [2,3] and index two must be two less than"
19661 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19662 _("General purpose registers may not be the same"));
19663 constraint (inst
.operands
[Rt
].reg
== REG_SP
19664 || inst
.operands
[Rt2
].reg
== REG_SP
,
19666 constraint (inst
.operands
[Rt
].reg
== REG_PC
19667 || inst
.operands
[Rt2
].reg
== REG_PC
,
19670 inst
.instruction
= 0xec000f00;
19671 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19672 inst
.instruction
|= !!toQ
<< 20;
19673 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19674 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19675 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19676 inst
.instruction
|= inst
.operands
[Rt
].reg
;
19682 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19685 if (inst
.cond
> COND_ALWAYS
)
19686 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19688 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
19690 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
19693 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19694 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
19695 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19696 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19697 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19702 /* VMOV has particularly many variations. It can be one of:
19703 0. VMOV<c><q> <Qd>, <Qm>
19704 1. VMOV<c><q> <Dd>, <Dm>
19705 (Register operations, which are VORR with Rm = Rn.)
19706 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19707 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19709 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19710 (ARM register to scalar.)
19711 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19712 (Two ARM registers to vector.)
19713 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19714 (Scalar to ARM register.)
19715 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19716 (Vector to two ARM registers.)
19717 8. VMOV.F32 <Sd>, <Sm>
19718 9. VMOV.F64 <Dd>, <Dm>
19719 (VFP register moves.)
19720 10. VMOV.F32 <Sd>, #imm
19721 11. VMOV.F64 <Dd>, #imm
19722 (VFP float immediate load.)
19723 12. VMOV <Rd>, <Sm>
19724 (VFP single to ARM reg.)
19725 13. VMOV <Sd>, <Rm>
19726 (ARM reg to VFP single.)
19727 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19728 (Two ARM regs to two VFP singles.)
19729 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19730 (Two VFP singles to two ARM regs.)
19731 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19732 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19733 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19734 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19736 These cases can be disambiguated using neon_select_shape, except cases 1/9
19737 and 3/11 which depend on the operand type too.
19739 All the encoded bits are hardcoded by this function.
19741 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19742 Cases 5, 7 may be used with VFPv2 and above.
19744 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19745 can specify a type where it doesn't make sense to, and is ignored). */
19750 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
19751 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
19752 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
19753 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
19755 struct neon_type_el et
;
19756 const char *ldconst
= 0;
19760 case NS_DD
: /* case 1/9. */
19761 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19762 /* It is not an error here if no type is given. */
19764 if (et
.type
== NT_float
&& et
.size
== 64)
19766 do_vfp_nsyn_opcode ("fcpyd");
19769 /* fall through. */
19771 case NS_QQ
: /* case 0/1. */
19773 if (!check_simd_pred_availability (FALSE
,
19774 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19776 /* The architecture manual I have doesn't explicitly state which
19777 value the U bit should have for register->register moves, but
19778 the equivalent VORR instruction has U = 0, so do that. */
19779 inst
.instruction
= 0x0200110;
19780 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19781 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19782 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19783 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19784 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19785 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19786 inst
.instruction
|= neon_quad (rs
) << 6;
19788 neon_dp_fixup (&inst
);
19792 case NS_DI
: /* case 3/11. */
19793 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19795 if (et
.type
== NT_float
&& et
.size
== 64)
19797 /* case 11 (fconstd). */
19798 ldconst
= "fconstd";
19799 goto encode_fconstd
;
19801 /* fall through. */
19803 case NS_QI
: /* case 2/3. */
19804 if (!check_simd_pred_availability (FALSE
,
19805 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19807 inst
.instruction
= 0x0800010;
19808 neon_move_immediate ();
19809 neon_dp_fixup (&inst
);
19812 case NS_SR
: /* case 4. */
19814 unsigned bcdebits
= 0;
19816 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
19817 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
19819 /* .<size> is optional here, defaulting to .32. */
19820 if (inst
.vectype
.elems
== 0
19821 && inst
.operands
[0].vectype
.type
== NT_invtype
19822 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19824 inst
.vectype
.el
[0].type
= NT_untyped
;
19825 inst
.vectype
.el
[0].size
= 32;
19826 inst
.vectype
.elems
= 1;
19829 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19830 logsize
= neon_logbits (et
.size
);
19834 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19835 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
19840 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19841 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19845 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19847 if (inst
.operands
[1].reg
== REG_SP
)
19848 as_tsktsk (MVE_BAD_SP
);
19849 else if (inst
.operands
[1].reg
== REG_PC
)
19850 as_tsktsk (MVE_BAD_PC
);
19852 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
19854 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19855 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19860 case 8: bcdebits
= 0x8; break;
19861 case 16: bcdebits
= 0x1; break;
19862 case 32: bcdebits
= 0x0; break;
19866 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19868 inst
.instruction
= 0xe000b10;
19869 do_vfp_cond_or_thumb ();
19870 inst
.instruction
|= LOW4 (dn
) << 16;
19871 inst
.instruction
|= HI1 (dn
) << 7;
19872 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19873 inst
.instruction
|= (bcdebits
& 3) << 5;
19874 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
19875 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19879 case NS_DRR
: /* case 5 (fmdrr). */
19880 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19881 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19884 inst
.instruction
= 0xc400b10;
19885 do_vfp_cond_or_thumb ();
19886 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
19887 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
19888 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19889 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
19892 case NS_RS
: /* case 6. */
19895 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19896 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
19897 unsigned abcdebits
= 0;
19899 /* .<dt> is optional here, defaulting to .32. */
19900 if (inst
.vectype
.elems
== 0
19901 && inst
.operands
[0].vectype
.type
== NT_invtype
19902 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19904 inst
.vectype
.el
[0].type
= NT_untyped
;
19905 inst
.vectype
.el
[0].size
= 32;
19906 inst
.vectype
.elems
= 1;
19909 et
= neon_check_type (2, NS_NULL
,
19910 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
19911 logsize
= neon_logbits (et
.size
);
19915 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19916 && vfp_or_neon_is_neon (NEON_CHECK_CC
19917 | NEON_CHECK_ARCH
) == FAIL
)
19922 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19923 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19927 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19929 if (inst
.operands
[0].reg
== REG_SP
)
19930 as_tsktsk (MVE_BAD_SP
);
19931 else if (inst
.operands
[0].reg
== REG_PC
)
19932 as_tsktsk (MVE_BAD_PC
);
19935 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
19937 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19938 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19942 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
19943 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
19944 case 32: abcdebits
= 0x00; break;
19948 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19949 inst
.instruction
= 0xe100b10;
19950 do_vfp_cond_or_thumb ();
19951 inst
.instruction
|= LOW4 (dn
) << 16;
19952 inst
.instruction
|= HI1 (dn
) << 7;
19953 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19954 inst
.instruction
|= (abcdebits
& 3) << 5;
19955 inst
.instruction
|= (abcdebits
>> 2) << 21;
19956 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19960 case NS_RRD
: /* case 7 (fmrrd). */
19961 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19962 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19965 inst
.instruction
= 0xc500b10;
19966 do_vfp_cond_or_thumb ();
19967 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19968 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19969 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19970 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19973 case NS_FF
: /* case 8 (fcpys). */
19974 do_vfp_nsyn_opcode ("fcpys");
19978 case NS_FI
: /* case 10 (fconsts). */
19979 ldconst
= "fconsts";
19981 if (!inst
.operands
[1].immisfloat
)
19984 /* Immediate has to fit in 8 bits so float is enough. */
19985 float imm
= (float) inst
.operands
[1].imm
;
19986 memcpy (&new_imm
, &imm
, sizeof (float));
19987 /* But the assembly may have been written to provide an integer
19988 bit pattern that equates to a float, so check that the
19989 conversion has worked. */
19990 if (is_quarter_float (new_imm
))
19992 if (is_quarter_float (inst
.operands
[1].imm
))
19993 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
19995 inst
.operands
[1].imm
= new_imm
;
19996 inst
.operands
[1].immisfloat
= 1;
20000 if (is_quarter_float (inst
.operands
[1].imm
))
20002 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20003 do_vfp_nsyn_opcode (ldconst
);
20005 /* ARMv8.2 fp16 vmov.f16 instruction. */
20007 do_scalar_fp16_v82_encode ();
20010 first_error (_("immediate out of range"));
20014 case NS_RF
: /* case 12 (fmrs). */
20015 do_vfp_nsyn_opcode ("fmrs");
20016 /* ARMv8.2 fp16 vmov.f16 instruction. */
20018 do_scalar_fp16_v82_encode ();
20022 case NS_FR
: /* case 13 (fmsr). */
20023 do_vfp_nsyn_opcode ("fmsr");
20024 /* ARMv8.2 fp16 vmov.f16 instruction. */
20026 do_scalar_fp16_v82_encode ();
20036 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20037 (one of which is a list), but we have parsed four. Do some fiddling to
20038 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20040 case NS_RRFF
: /* case 14 (fmrrs). */
20041 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20042 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20044 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20045 _("VFP registers must be adjacent"));
20046 inst
.operands
[2].imm
= 2;
20047 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20048 do_vfp_nsyn_opcode ("fmrrs");
20051 case NS_FFRR
: /* case 15 (fmsrr). */
20052 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20053 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20055 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20056 _("VFP registers must be adjacent"));
20057 inst
.operands
[1] = inst
.operands
[2];
20058 inst
.operands
[2] = inst
.operands
[3];
20059 inst
.operands
[0].imm
= 2;
20060 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20061 do_vfp_nsyn_opcode ("fmsrr");
20065 /* neon_select_shape has determined that the instruction
20066 shape is wrong and has already set the error message. */
20077 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20078 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20079 && !inst
.operands
[2].present
))
20081 inst
.instruction
= 0;
20084 set_pred_insn_type (INSIDE_IT_INSN
);
20089 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20092 if (inst
.cond
!= COND_ALWAYS
)
20093 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20095 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20096 | N_S16
| N_U16
| N_KEY
);
20098 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20099 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20100 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20101 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20102 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20103 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20108 do_neon_rshift_round_imm (void)
20110 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20113 enum neon_shape rs
;
20114 struct neon_type_el et
;
20116 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20118 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20119 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20123 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20124 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20126 int imm
= inst
.operands
[2].imm
;
20128 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20131 inst
.operands
[2].present
= 0;
20136 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20137 _("immediate out of range for shift"));
20138 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20143 do_neon_movhf (void)
20145 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20146 constraint (rs
!= NS_HH
, _("invalid suffix"));
20148 if (inst
.cond
!= COND_ALWAYS
)
20152 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20153 " the behaviour is UNPREDICTABLE"));
20157 inst
.error
= BAD_COND
;
20162 do_vfp_sp_monadic ();
20165 inst
.instruction
|= 0xf0000000;
20169 do_neon_movl (void)
20171 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20172 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20173 unsigned sizebits
= et
.size
>> 3;
20174 inst
.instruction
|= sizebits
<< 19;
20175 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20181 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20182 struct neon_type_el et
= neon_check_type (2, rs
,
20183 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20184 NEON_ENCODE (INTEGER
, inst
);
20185 neon_two_same (neon_quad (rs
), 1, et
.size
);
20189 do_neon_zip_uzp (void)
20191 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20192 struct neon_type_el et
= neon_check_type (2, rs
,
20193 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20194 if (rs
== NS_DD
&& et
.size
== 32)
20196 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20197 inst
.instruction
= N_MNEM_vtrn
;
20201 neon_two_same (neon_quad (rs
), 1, et
.size
);
20205 do_neon_sat_abs_neg (void)
20207 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20210 enum neon_shape rs
;
20211 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20212 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20214 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20215 struct neon_type_el et
= neon_check_type (2, rs
,
20216 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20217 neon_two_same (neon_quad (rs
), 1, et
.size
);
20221 do_neon_pair_long (void)
20223 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20224 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20225 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20226 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20227 neon_two_same (neon_quad (rs
), 1, et
.size
);
20231 do_neon_recip_est (void)
20233 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20234 struct neon_type_el et
= neon_check_type (2, rs
,
20235 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20236 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20237 neon_two_same (neon_quad (rs
), 1, et
.size
);
20243 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20246 enum neon_shape rs
;
20247 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20248 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20250 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20252 struct neon_type_el et
= neon_check_type (2, rs
,
20253 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20254 neon_two_same (neon_quad (rs
), 1, et
.size
);
20260 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20263 enum neon_shape rs
;
20264 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20265 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20267 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20269 struct neon_type_el et
= neon_check_type (2, rs
,
20270 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20271 neon_two_same (neon_quad (rs
), 1, et
.size
);
20277 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20278 struct neon_type_el et
= neon_check_type (2, rs
,
20279 N_EQK
| N_INT
, N_8
| N_KEY
);
20280 neon_two_same (neon_quad (rs
), 1, et
.size
);
20286 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20287 neon_two_same (neon_quad (rs
), 1, -1);
20291 do_neon_tbl_tbx (void)
20293 unsigned listlenbits
;
20294 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20296 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20298 first_error (_("bad list length for table lookup"));
20302 listlenbits
= inst
.operands
[1].imm
- 1;
20303 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20304 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20305 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20306 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20307 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20308 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20309 inst
.instruction
|= listlenbits
<< 8;
20311 neon_dp_fixup (&inst
);
20315 do_neon_ldm_stm (void)
20317 /* P, U and L bits are part of bitmask. */
20318 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20319 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20321 if (inst
.operands
[1].issingle
)
20323 do_vfp_nsyn_ldm_stm (is_dbmode
);
20327 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20328 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20330 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20331 _("register list must contain at least 1 and at most 16 "
20334 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20335 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20336 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20337 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20339 inst
.instruction
|= offsetbits
;
20341 do_vfp_cond_or_thumb ();
20345 do_neon_ldr_str (void)
20347 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20349 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20350 And is UNPREDICTABLE in thumb mode. */
20352 && inst
.operands
[1].reg
== REG_PC
20353 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20356 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20357 else if (warn_on_deprecated
)
20358 as_tsktsk (_("Use of PC here is deprecated"));
20361 if (inst
.operands
[0].issingle
)
20364 do_vfp_nsyn_opcode ("flds");
20366 do_vfp_nsyn_opcode ("fsts");
20368 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20369 if (inst
.vectype
.el
[0].size
== 16)
20370 do_scalar_fp16_v82_encode ();
20375 do_vfp_nsyn_opcode ("fldd");
20377 do_vfp_nsyn_opcode ("fstd");
20382 do_t_vldr_vstr_sysreg (void)
20384 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20385 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20387 /* Use of PC is UNPREDICTABLE. */
20388 if (inst
.operands
[1].reg
== REG_PC
)
20389 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20391 if (inst
.operands
[1].immisreg
)
20392 inst
.error
= _("instruction does not accept register index");
20394 if (!inst
.operands
[1].isreg
)
20395 inst
.error
= _("instruction does not accept PC-relative addressing");
20397 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20398 inst
.error
= _("immediate value out of range");
20400 inst
.instruction
= 0xec000f80;
20402 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20403 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20404 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20405 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20409 do_vldr_vstr (void)
20411 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20413 /* VLDR/VSTR (System Register). */
20416 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20417 as_bad (_("Instruction not permitted on this architecture"));
20419 do_t_vldr_vstr_sysreg ();
20424 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20425 as_bad (_("Instruction not permitted on this architecture"));
20426 do_neon_ldr_str ();
20430 /* "interleave" version also handles non-interleaving register VLD1/VST1
20434 do_neon_ld_st_interleave (void)
20436 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20437 N_8
| N_16
| N_32
| N_64
);
20438 unsigned alignbits
= 0;
20440 /* The bits in this table go:
20441 0: register stride of one (0) or two (1)
20442 1,2: register list length, minus one (1, 2, 3, 4).
20443 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20444 We use -1 for invalid entries. */
20445 const int typetable
[] =
20447 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20448 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20449 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20450 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20454 if (et
.type
== NT_invtype
)
20457 if (inst
.operands
[1].immisalign
)
20458 switch (inst
.operands
[1].imm
>> 8)
20460 case 64: alignbits
= 1; break;
20462 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20463 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20464 goto bad_alignment
;
20468 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20469 goto bad_alignment
;
20474 first_error (_("bad alignment"));
20478 inst
.instruction
|= alignbits
<< 4;
20479 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20481 /* Bits [4:6] of the immediate in a list specifier encode register stride
20482 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20483 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20484 up the right value for "type" in a table based on this value and the given
20485 list style, then stick it back. */
20486 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20487 | (((inst
.instruction
>> 8) & 3) << 3);
20489 typebits
= typetable
[idx
];
20491 constraint (typebits
== -1, _("bad list type for instruction"));
20492 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20495 inst
.instruction
&= ~0xf00;
20496 inst
.instruction
|= typebits
<< 8;
20499 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20500 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20501 otherwise. The variable arguments are a list of pairs of legal (size, align)
20502 values, terminated with -1. */
20505 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20508 int result
= FAIL
, thissize
, thisalign
;
20510 if (!inst
.operands
[1].immisalign
)
20516 va_start (ap
, do_alignment
);
20520 thissize
= va_arg (ap
, int);
20521 if (thissize
== -1)
20523 thisalign
= va_arg (ap
, int);
20525 if (size
== thissize
&& align
== thisalign
)
20528 while (result
!= SUCCESS
);
20532 if (result
== SUCCESS
)
20535 first_error (_("unsupported alignment for instruction"));
20541 do_neon_ld_st_lane (void)
20543 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20544 int align_good
, do_alignment
= 0;
20545 int logsize
= neon_logbits (et
.size
);
20546 int align
= inst
.operands
[1].imm
>> 8;
20547 int n
= (inst
.instruction
>> 8) & 3;
20548 int max_el
= 64 / et
.size
;
20550 if (et
.type
== NT_invtype
)
20553 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20554 _("bad list length"));
20555 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20556 _("scalar index out of range"));
20557 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20559 _("stride of 2 unavailable when element size is 8"));
20563 case 0: /* VLD1 / VST1. */
20564 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20566 if (align_good
== FAIL
)
20570 unsigned alignbits
= 0;
20573 case 16: alignbits
= 0x1; break;
20574 case 32: alignbits
= 0x3; break;
20577 inst
.instruction
|= alignbits
<< 4;
20581 case 1: /* VLD2 / VST2. */
20582 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20583 16, 32, 32, 64, -1);
20584 if (align_good
== FAIL
)
20587 inst
.instruction
|= 1 << 4;
20590 case 2: /* VLD3 / VST3. */
20591 constraint (inst
.operands
[1].immisalign
,
20592 _("can't use alignment with this instruction"));
20595 case 3: /* VLD4 / VST4. */
20596 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20597 16, 64, 32, 64, 32, 128, -1);
20598 if (align_good
== FAIL
)
20602 unsigned alignbits
= 0;
20605 case 8: alignbits
= 0x1; break;
20606 case 16: alignbits
= 0x1; break;
20607 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20610 inst
.instruction
|= alignbits
<< 4;
20617 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20618 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20619 inst
.instruction
|= 1 << (4 + logsize
);
20621 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20622 inst
.instruction
|= logsize
<< 10;
20625 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20628 do_neon_ld_dup (void)
20630 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20631 int align_good
, do_alignment
= 0;
20633 if (et
.type
== NT_invtype
)
20636 switch ((inst
.instruction
>> 8) & 3)
20638 case 0: /* VLD1. */
20639 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20640 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20641 &do_alignment
, 16, 16, 32, 32, -1);
20642 if (align_good
== FAIL
)
20644 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20647 case 2: inst
.instruction
|= 1 << 5; break;
20648 default: first_error (_("bad list length")); return;
20650 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20653 case 1: /* VLD2. */
20654 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20655 &do_alignment
, 8, 16, 16, 32, 32, 64,
20657 if (align_good
== FAIL
)
20659 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20660 _("bad list length"));
20661 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20662 inst
.instruction
|= 1 << 5;
20663 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20666 case 2: /* VLD3. */
20667 constraint (inst
.operands
[1].immisalign
,
20668 _("can't use alignment with this instruction"));
20669 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20670 _("bad list length"));
20671 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20672 inst
.instruction
|= 1 << 5;
20673 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20676 case 3: /* VLD4. */
20678 int align
= inst
.operands
[1].imm
>> 8;
20679 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20680 16, 64, 32, 64, 32, 128, -1);
20681 if (align_good
== FAIL
)
20683 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
20684 _("bad list length"));
20685 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20686 inst
.instruction
|= 1 << 5;
20687 if (et
.size
== 32 && align
== 128)
20688 inst
.instruction
|= 0x3 << 6;
20690 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20697 inst
.instruction
|= do_alignment
<< 4;
20700 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20701 apart from bits [11:4]. */
20704 do_neon_ldx_stx (void)
20706 if (inst
.operands
[1].isreg
)
20707 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
20709 switch (NEON_LANE (inst
.operands
[0].imm
))
20711 case NEON_INTERLEAVE_LANES
:
20712 NEON_ENCODE (INTERLV
, inst
);
20713 do_neon_ld_st_interleave ();
20716 case NEON_ALL_LANES
:
20717 NEON_ENCODE (DUP
, inst
);
20718 if (inst
.instruction
== N_INV
)
20720 first_error ("only loads support such operands");
20727 NEON_ENCODE (LANE
, inst
);
20728 do_neon_ld_st_lane ();
20731 /* L bit comes from bit mask. */
20732 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20733 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20734 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20736 if (inst
.operands
[1].postind
)
20738 int postreg
= inst
.operands
[1].imm
& 0xf;
20739 constraint (!inst
.operands
[1].immisreg
,
20740 _("post-index must be a register"));
20741 constraint (postreg
== 0xd || postreg
== 0xf,
20742 _("bad register for post-index"));
20743 inst
.instruction
|= postreg
;
20747 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
20748 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
20749 || inst
.relocs
[0].exp
.X_add_number
!= 0,
20752 if (inst
.operands
[1].writeback
)
20754 inst
.instruction
|= 0xd;
20757 inst
.instruction
|= 0xf;
20761 inst
.instruction
|= 0xf9000000;
20763 inst
.instruction
|= 0xf4000000;
20768 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
20770 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20771 D register operands. */
20772 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20773 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20776 NEON_ENCODE (FPV8
, inst
);
20778 if (rs
== NS_FFF
|| rs
== NS_HHH
)
20780 do_vfp_sp_dyadic ();
20782 /* ARMv8.2 fp16 instruction. */
20784 do_scalar_fp16_v82_encode ();
20787 do_vfp_dp_rd_rn_rm ();
20790 inst
.instruction
|= 0x100;
20792 inst
.instruction
|= 0xf0000000;
20798 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20800 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
20801 first_error (_("invalid instruction shape"));
20807 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20808 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20810 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
20813 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20816 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
20820 do_vrint_1 (enum neon_cvt_mode mode
)
20822 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
20823 struct neon_type_el et
;
20828 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20829 D register operands. */
20830 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20831 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20834 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
20836 if (et
.type
!= NT_invtype
)
20838 /* VFP encodings. */
20839 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
20840 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
20841 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20843 NEON_ENCODE (FPV8
, inst
);
20844 if (rs
== NS_FF
|| rs
== NS_HH
)
20845 do_vfp_sp_monadic ();
20847 do_vfp_dp_rd_rm ();
20851 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
20852 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
20853 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
20854 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
20855 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
20856 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
20857 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
20861 inst
.instruction
|= (rs
== NS_DD
) << 8;
20862 do_vfp_cond_or_thumb ();
20864 /* ARMv8.2 fp16 vrint instruction. */
20866 do_scalar_fp16_v82_encode ();
20870 /* Neon encodings (or something broken...). */
20872 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
20874 if (et
.type
== NT_invtype
)
20877 if (!check_simd_pred_availability (TRUE
,
20878 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20881 NEON_ENCODE (FLOAT
, inst
);
20883 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20884 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20885 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20886 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20887 inst
.instruction
|= neon_quad (rs
) << 6;
20888 /* Mask off the original size bits and reencode them. */
20889 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
20890 | neon_logbits (et
.size
) << 18);
20894 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
20895 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
20896 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
20897 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
20898 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
20899 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
20900 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
20905 inst
.instruction
|= 0xfc000000;
20907 inst
.instruction
|= 0xf0000000;
20914 do_vrint_1 (neon_cvt_mode_x
);
20920 do_vrint_1 (neon_cvt_mode_z
);
20926 do_vrint_1 (neon_cvt_mode_r
);
20932 do_vrint_1 (neon_cvt_mode_a
);
20938 do_vrint_1 (neon_cvt_mode_n
);
20944 do_vrint_1 (neon_cvt_mode_p
);
20950 do_vrint_1 (neon_cvt_mode_m
);
20954 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
20956 unsigned regno
= NEON_SCALAR_REG (opnd
);
20957 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
20959 if (elsize
== 16 && elno
< 2 && regno
< 16)
20960 return regno
| (elno
<< 4);
20961 else if (elsize
== 32 && elno
== 0)
20964 first_error (_("scalar out of range"));
20971 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
20972 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20973 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20974 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20975 _("expression too complex"));
20976 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20977 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
20978 _("immediate out of range"));
20981 if (!check_simd_pred_availability (TRUE
,
20982 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
20985 if (inst
.operands
[2].isscalar
)
20987 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20988 first_error (_("invalid instruction shape"));
20989 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
20990 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20991 N_KEY
| N_F16
| N_F32
).size
;
20992 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
20994 inst
.instruction
= 0xfe000800;
20995 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20996 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20997 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20998 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20999 inst
.instruction
|= LOW4 (m
);
21000 inst
.instruction
|= HI1 (m
) << 5;
21001 inst
.instruction
|= neon_quad (rs
) << 6;
21002 inst
.instruction
|= rot
<< 20;
21003 inst
.instruction
|= (size
== 32) << 23;
21007 enum neon_shape rs
;
21008 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21009 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21011 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21013 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21014 N_KEY
| N_F16
| N_F32
).size
;
21015 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21016 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21017 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21018 as_tsktsk (BAD_MVE_SRCDEST
);
21020 neon_three_same (neon_quad (rs
), 0, -1);
21021 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21022 inst
.instruction
|= 0xfc200800;
21023 inst
.instruction
|= rot
<< 23;
21024 inst
.instruction
|= (size
== 32) << 20;
21031 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21032 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21033 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21034 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21035 _("expression too complex"));
21037 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21038 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21039 enum neon_shape rs
;
21040 struct neon_type_el et
;
21041 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21043 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21044 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21048 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21049 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21051 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21052 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21053 "operand makes instruction UNPREDICTABLE"));
21056 if (et
.type
== NT_invtype
)
21059 if (!check_simd_pred_availability (et
.type
== NT_float
,
21060 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21063 if (et
.type
== NT_float
)
21065 neon_three_same (neon_quad (rs
), 0, -1);
21066 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21067 inst
.instruction
|= 0xfc800800;
21068 inst
.instruction
|= (rot
== 270) << 24;
21069 inst
.instruction
|= (et
.size
== 32) << 20;
21073 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21074 inst
.instruction
= 0xfe000f00;
21075 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21076 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21077 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21078 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21079 inst
.instruction
|= (rot
== 270) << 12;
21080 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21081 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21082 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21087 /* Dot Product instructions encoding support. */
21090 do_neon_dotproduct (int unsigned_p
)
21092 enum neon_shape rs
;
21093 unsigned scalar_oprd2
= 0;
21096 if (inst
.cond
!= COND_ALWAYS
)
21097 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21098 "is UNPREDICTABLE"));
21100 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21103 /* Dot Product instructions are in three-same D/Q register format or the third
21104 operand can be a scalar index register. */
21105 if (inst
.operands
[2].isscalar
)
21107 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21108 high8
= 0xfe000000;
21109 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21113 high8
= 0xfc000000;
21114 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21118 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21120 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21122 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21123 Product instruction, so we pass 0 as the "ubit" parameter. And the
21124 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21125 neon_three_same (neon_quad (rs
), 0, 32);
21127 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21128 different NEON three-same encoding. */
21129 inst
.instruction
&= 0x00ffffff;
21130 inst
.instruction
|= high8
;
21131 /* Encode 'U' bit which indicates signedness. */
21132 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21133 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21134 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21135 the instruction encoding. */
21136 if (inst
.operands
[2].isscalar
)
21138 inst
.instruction
&= 0xffffffd0;
21139 inst
.instruction
|= LOW4 (scalar_oprd2
);
21140 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21144 /* Dot Product instructions for signed integer. */
21147 do_neon_dotproduct_s (void)
21149 return do_neon_dotproduct (0);
21152 /* Dot Product instructions for unsigned integer. */
21155 do_neon_dotproduct_u (void)
21157 return do_neon_dotproduct (1);
21160 /* Crypto v1 instructions. */
21162 do_crypto_2op_1 (unsigned elttype
, int op
)
21164 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21166 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
21172 NEON_ENCODE (INTEGER
, inst
);
21173 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21174 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21175 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21176 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21178 inst
.instruction
|= op
<< 6;
21181 inst
.instruction
|= 0xfc000000;
21183 inst
.instruction
|= 0xf0000000;
21187 do_crypto_3op_1 (int u
, int op
)
21189 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21191 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
21192 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
21197 NEON_ENCODE (INTEGER
, inst
);
21198 neon_three_same (1, u
, 8 << op
);
21204 do_crypto_2op_1 (N_8
, 0);
21210 do_crypto_2op_1 (N_8
, 1);
21216 do_crypto_2op_1 (N_8
, 2);
21222 do_crypto_2op_1 (N_8
, 3);
21228 do_crypto_3op_1 (0, 0);
21234 do_crypto_3op_1 (0, 1);
21240 do_crypto_3op_1 (0, 2);
21246 do_crypto_3op_1 (0, 3);
21252 do_crypto_3op_1 (1, 0);
21258 do_crypto_3op_1 (1, 1);
21262 do_sha256su1 (void)
21264 do_crypto_3op_1 (1, 2);
21270 do_crypto_2op_1 (N_32
, -1);
21276 do_crypto_2op_1 (N_32
, 0);
21280 do_sha256su0 (void)
21282 do_crypto_2op_1 (N_32
, 1);
21286 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21288 unsigned int Rd
= inst
.operands
[0].reg
;
21289 unsigned int Rn
= inst
.operands
[1].reg
;
21290 unsigned int Rm
= inst
.operands
[2].reg
;
21292 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21293 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21294 inst
.instruction
|= LOW4 (Rn
) << 16;
21295 inst
.instruction
|= LOW4 (Rm
);
21296 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21297 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21299 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21300 as_warn (UNPRED_REG ("r15"));
21342 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21344 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21345 do_vfp_sp_dp_cvt ();
21346 do_vfp_cond_or_thumb ();
21350 /* Overall per-instruction processing. */
21352 /* We need to be able to fix up arbitrary expressions in some statements.
21353 This is so that we can handle symbols that are an arbitrary distance from
21354 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21355 which returns part of an address in a form which will be valid for
21356 a data instruction. We do this by pushing the expression into a symbol
21357 in the expr_section, and creating a fix for that. */
21360 fix_new_arm (fragS
* frag
,
21374 /* Create an absolute valued symbol, so we have something to
21375 refer to in the object file. Unfortunately for us, gas's
21376 generic expression parsing will already have folded out
21377 any use of .set foo/.type foo %function that may have
21378 been used to set type information of the target location,
21379 that's being specified symbolically. We have to presume
21380 the user knows what they are doing. */
21384 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21386 symbol
= symbol_find_or_make (name
);
21387 S_SET_SEGMENT (symbol
, absolute_section
);
21388 symbol_set_frag (symbol
, &zero_address_frag
);
21389 S_SET_VALUE (symbol
, exp
->X_add_number
);
21390 exp
->X_op
= O_symbol
;
21391 exp
->X_add_symbol
= symbol
;
21392 exp
->X_add_number
= 0;
21398 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21399 (enum bfd_reloc_code_real
) reloc
);
21403 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21404 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21408 /* Mark whether the fix is to a THUMB instruction, or an ARM
21410 new_fix
->tc_fix_data
= thumb_mode
;
21413 /* Create a frg for an instruction requiring relaxation. */
21415 output_relax_insn (void)
21421 /* The size of the instruction is unknown, so tie the debug info to the
21422 start of the instruction. */
21423 dwarf2_emit_insn (0);
21425 switch (inst
.relocs
[0].exp
.X_op
)
21428 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21429 offset
= inst
.relocs
[0].exp
.X_add_number
;
21433 offset
= inst
.relocs
[0].exp
.X_add_number
;
21436 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21440 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21441 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21442 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21445 /* Write a 32-bit thumb instruction to buf. */
21447 put_thumb32_insn (char * buf
, unsigned long insn
)
21449 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21450 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21454 output_inst (const char * str
)
21460 as_bad ("%s -- `%s'", inst
.error
, str
);
21465 output_relax_insn ();
21468 if (inst
.size
== 0)
21471 to
= frag_more (inst
.size
);
21472 /* PR 9814: Record the thumb mode into the current frag so that we know
21473 what type of NOP padding to use, if necessary. We override any previous
21474 setting so that if the mode has changed then the NOPS that we use will
21475 match the encoding of the last instruction in the frag. */
21476 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21478 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21480 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21481 put_thumb32_insn (to
, inst
.instruction
);
21483 else if (inst
.size
> INSN_SIZE
)
21485 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21486 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21487 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21490 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21493 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21495 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21496 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21497 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21498 inst
.relocs
[r
].type
);
21501 dwarf2_emit_insn (inst
.size
);
21505 output_it_inst (int cond
, int mask
, char * to
)
21507 unsigned long instruction
= 0xbf00;
21510 instruction
|= mask
;
21511 instruction
|= cond
<< 4;
21515 to
= frag_more (2);
21517 dwarf2_emit_insn (2);
21521 md_number_to_chars (to
, instruction
, 2);
21526 /* Tag values used in struct asm_opcode's tag field. */
21529 OT_unconditional
, /* Instruction cannot be conditionalized.
21530 The ARM condition field is still 0xE. */
21531 OT_unconditionalF
, /* Instruction cannot be conditionalized
21532 and carries 0xF in its ARM condition field. */
21533 OT_csuffix
, /* Instruction takes a conditional suffix. */
21534 OT_csuffixF
, /* Some forms of the instruction take a scalar
21535 conditional suffix, others place 0xF where the
21536 condition field would be, others take a vector
21537 conditional suffix. */
21538 OT_cinfix3
, /* Instruction takes a conditional infix,
21539 beginning at character index 3. (In
21540 unified mode, it becomes a suffix.) */
21541 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21542 tsts, cmps, cmns, and teqs. */
21543 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21544 character index 3, even in unified mode. Used for
21545 legacy instructions where suffix and infix forms
21546 may be ambiguous. */
21547 OT_csuf_or_in3
, /* Instruction takes either a conditional
21548 suffix or an infix at character index 3. */
21549 OT_odd_infix_unc
, /* This is the unconditional variant of an
21550 instruction that takes a conditional infix
21551 at an unusual position. In unified mode,
21552 this variant will accept a suffix. */
21553 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21554 are the conditional variants of instructions that
21555 take conditional infixes in unusual positions.
21556 The infix appears at character index
21557 (tag - OT_odd_infix_0). These are not accepted
21558 in unified mode. */
21561 /* Subroutine of md_assemble, responsible for looking up the primary
21562 opcode from the mnemonic the user wrote. STR points to the
21563 beginning of the mnemonic.
21565 This is not simply a hash table lookup, because of conditional
21566 variants. Most instructions have conditional variants, which are
21567 expressed with a _conditional affix_ to the mnemonic. If we were
21568 to encode each conditional variant as a literal string in the opcode
21569 table, it would have approximately 20,000 entries.
21571 Most mnemonics take this affix as a suffix, and in unified syntax,
21572 'most' is upgraded to 'all'. However, in the divided syntax, some
21573 instructions take the affix as an infix, notably the s-variants of
21574 the arithmetic instructions. Of those instructions, all but six
21575 have the infix appear after the third character of the mnemonic.
21577 Accordingly, the algorithm for looking up primary opcodes given
21580 1. Look up the identifier in the opcode table.
21581 If we find a match, go to step U.
21583 2. Look up the last two characters of the identifier in the
21584 conditions table. If we find a match, look up the first N-2
21585 characters of the identifier in the opcode table. If we
21586 find a match, go to step CE.
21588 3. Look up the fourth and fifth characters of the identifier in
21589 the conditions table. If we find a match, extract those
21590 characters from the identifier, and look up the remaining
21591 characters in the opcode table. If we find a match, go
21596 U. Examine the tag field of the opcode structure, in case this is
21597 one of the six instructions with its conditional infix in an
21598 unusual place. If it is, the tag tells us where to find the
21599 infix; look it up in the conditions table and set inst.cond
21600 accordingly. Otherwise, this is an unconditional instruction.
21601 Again set inst.cond accordingly. Return the opcode structure.
21603 CE. Examine the tag field to make sure this is an instruction that
21604 should receive a conditional suffix. If it is not, fail.
21605 Otherwise, set inst.cond from the suffix we already looked up,
21606 and return the opcode structure.
21608 CM. Examine the tag field to make sure this is an instruction that
21609 should receive a conditional infix after the third character.
21610 If it is not, fail. Otherwise, undo the edits to the current
21611 line of input and proceed as for case CE. */
21613 static const struct asm_opcode
*
21614 opcode_lookup (char **str
)
21618 const struct asm_opcode
*opcode
;
21619 const struct asm_cond
*cond
;
21622 /* Scan up to the end of the mnemonic, which must end in white space,
21623 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21624 for (base
= end
= *str
; *end
!= '\0'; end
++)
21625 if (*end
== ' ' || *end
== '.')
21631 /* Handle a possible width suffix and/or Neon type suffix. */
21636 /* The .w and .n suffixes are only valid if the unified syntax is in
21638 if (unified_syntax
&& end
[1] == 'w')
21640 else if (unified_syntax
&& end
[1] == 'n')
21645 inst
.vectype
.elems
= 0;
21647 *str
= end
+ offset
;
21649 if (end
[offset
] == '.')
21651 /* See if we have a Neon type suffix (possible in either unified or
21652 non-unified ARM syntax mode). */
21653 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
21656 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
21662 /* Look for unaffixed or special-case affixed mnemonic. */
21663 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21668 if (opcode
->tag
< OT_odd_infix_0
)
21670 inst
.cond
= COND_ALWAYS
;
21674 if (warn_on_deprecated
&& unified_syntax
)
21675 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21676 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
21677 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21680 inst
.cond
= cond
->value
;
21683 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21685 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21687 if (end
- base
< 2)
21690 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
21691 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21693 /* If this opcode can not be vector predicated then don't accept it with a
21694 vector predication code. */
21695 if (opcode
&& !opcode
->mayBeVecPred
)
21698 if (!opcode
|| !cond
)
21700 /* Cannot have a conditional suffix on a mnemonic of less than two
21702 if (end
- base
< 3)
21705 /* Look for suffixed mnemonic. */
21707 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21708 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21712 if (opcode
&& cond
)
21715 switch (opcode
->tag
)
21717 case OT_cinfix3_legacy
:
21718 /* Ignore conditional suffixes matched on infix only mnemonics. */
21722 case OT_cinfix3_deprecated
:
21723 case OT_odd_infix_unc
:
21724 if (!unified_syntax
)
21726 /* Fall through. */
21730 case OT_csuf_or_in3
:
21731 inst
.cond
= cond
->value
;
21734 case OT_unconditional
:
21735 case OT_unconditionalF
:
21737 inst
.cond
= cond
->value
;
21740 /* Delayed diagnostic. */
21741 inst
.error
= BAD_COND
;
21742 inst
.cond
= COND_ALWAYS
;
21751 /* Cannot have a usual-position infix on a mnemonic of less than
21752 six characters (five would be a suffix). */
21753 if (end
- base
< 6)
21756 /* Look for infixed mnemonic in the usual position. */
21758 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21762 memcpy (save
, affix
, 2);
21763 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
21764 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21766 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
21767 memcpy (affix
, save
, 2);
21770 && (opcode
->tag
== OT_cinfix3
21771 || opcode
->tag
== OT_cinfix3_deprecated
21772 || opcode
->tag
== OT_csuf_or_in3
21773 || opcode
->tag
== OT_cinfix3_legacy
))
21776 if (warn_on_deprecated
&& unified_syntax
21777 && (opcode
->tag
== OT_cinfix3
21778 || opcode
->tag
== OT_cinfix3_deprecated
))
21779 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21781 inst
.cond
= cond
->value
;
21788 /* This function generates an initial IT instruction, leaving its block
21789 virtually open for the new instructions. Eventually,
21790 the mask will be updated by now_pred_add_mask () each time
21791 a new instruction needs to be included in the IT block.
21792 Finally, the block is closed with close_automatic_it_block ().
21793 The block closure can be requested either from md_assemble (),
21794 a tencode (), or due to a label hook. */
21797 new_automatic_it_block (int cond
)
21799 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
21800 now_pred
.mask
= 0x18;
21801 now_pred
.cc
= cond
;
21802 now_pred
.block_length
= 1;
21803 mapping_state (MAP_THUMB
);
21804 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
21805 now_pred
.warn_deprecated
= FALSE
;
21806 now_pred
.insn_cond
= TRUE
;
21809 /* Close an automatic IT block.
21810 See comments in new_automatic_it_block (). */
21813 close_automatic_it_block (void)
21815 now_pred
.mask
= 0x10;
21816 now_pred
.block_length
= 0;
21819 /* Update the mask of the current automatically-generated IT
21820 instruction. See comments in new_automatic_it_block (). */
21823 now_pred_add_mask (int cond
)
21825 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21826 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21827 | ((bitvalue) << (nbit)))
21828 const int resulting_bit
= (cond
& 1);
21830 now_pred
.mask
&= 0xf;
21831 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21833 (5 - now_pred
.block_length
));
21834 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21836 ((5 - now_pred
.block_length
) - 1));
21837 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
21840 #undef SET_BIT_VALUE
21843 /* The IT blocks handling machinery is accessed through the these functions:
21844 it_fsm_pre_encode () from md_assemble ()
21845 set_pred_insn_type () optional, from the tencode functions
21846 set_pred_insn_type_last () ditto
21847 in_pred_block () ditto
21848 it_fsm_post_encode () from md_assemble ()
21849 force_automatic_it_block_close () from label handling functions
21852 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21853 initializing the IT insn type with a generic initial value depending
21854 on the inst.condition.
21855 2) During the tencode function, two things may happen:
21856 a) The tencode function overrides the IT insn type by
21857 calling either set_pred_insn_type (type) or
21858 set_pred_insn_type_last ().
21859 b) The tencode function queries the IT block state by
21860 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
21862 Both set_pred_insn_type and in_pred_block run the internal FSM state
21863 handling function (handle_pred_state), because: a) setting the IT insn
21864 type may incur in an invalid state (exiting the function),
21865 and b) querying the state requires the FSM to be updated.
21866 Specifically we want to avoid creating an IT block for conditional
21867 branches, so it_fsm_pre_encode is actually a guess and we can't
21868 determine whether an IT block is required until the tencode () routine
21869 has decided what type of instruction this actually it.
21870 Because of this, if set_pred_insn_type and in_pred_block have to be
21871 used, set_pred_insn_type has to be called first.
21873 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21874 that determines the insn IT type depending on the inst.cond code.
21875 When a tencode () routine encodes an instruction that can be
21876 either outside an IT block, or, in the case of being inside, has to be
21877 the last one, set_pred_insn_type_last () will determine the proper
21878 IT instruction type based on the inst.cond code. Otherwise,
21879 set_pred_insn_type can be called for overriding that logic or
21880 for covering other cases.
21882 Calling handle_pred_state () may not transition the IT block state to
21883 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21884 still queried. Instead, if the FSM determines that the state should
21885 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21886 after the tencode () function: that's what it_fsm_post_encode () does.
21888 Since in_pred_block () calls the state handling function to get an
21889 updated state, an error may occur (due to invalid insns combination).
21890 In that case, inst.error is set.
21891 Therefore, inst.error has to be checked after the execution of
21892 the tencode () routine.
21894 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21895 any pending state change (if any) that didn't take place in
21896 handle_pred_state () as explained above. */
21899 it_fsm_pre_encode (void)
21901 if (inst
.cond
!= COND_ALWAYS
)
21902 inst
.pred_insn_type
= INSIDE_IT_INSN
;
21904 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
21906 now_pred
.state_handled
= 0;
21909 /* IT state FSM handling function. */
21910 /* MVE instructions and non-MVE instructions are handled differently because of
21911 the introduction of VPT blocks.
21912 Specifications say that any non-MVE instruction inside a VPT block is
21913 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
21914 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
21915 few exceptions we have MVE_UNPREDICABLE_INSN.
21916 The error messages provided depending on the different combinations possible
21917 are described in the cases below:
21918 For 'most' MVE instructions:
21919 1) In an IT block, with an IT code: syntax error
21920 2) In an IT block, with a VPT code: error: must be in a VPT block
21921 3) In an IT block, with no code: warning: UNPREDICTABLE
21922 4) In a VPT block, with an IT code: syntax error
21923 5) In a VPT block, with a VPT code: OK!
21924 6) In a VPT block, with no code: error: missing code
21925 7) Outside a pred block, with an IT code: error: syntax error
21926 8) Outside a pred block, with a VPT code: error: should be in a VPT block
21927 9) Outside a pred block, with no code: OK!
21928 For non-MVE instructions:
21929 10) In an IT block, with an IT code: OK!
21930 11) In an IT block, with a VPT code: syntax error
21931 12) In an IT block, with no code: error: missing code
21932 13) In a VPT block, with an IT code: error: should be in an IT block
21933 14) In a VPT block, with a VPT code: syntax error
21934 15) In a VPT block, with no code: UNPREDICTABLE
21935 16) Outside a pred block, with an IT code: error: should be in an IT block
21936 17) Outside a pred block, with a VPT code: syntax error
21937 18) Outside a pred block, with no code: OK!
21942 handle_pred_state (void)
21944 now_pred
.state_handled
= 1;
21945 now_pred
.insn_cond
= FALSE
;
21947 switch (now_pred
.state
)
21949 case OUTSIDE_PRED_BLOCK
:
21950 switch (inst
.pred_insn_type
)
21952 case MVE_UNPREDICABLE_INSN
:
21953 case MVE_OUTSIDE_PRED_INSN
:
21954 if (inst
.cond
< COND_ALWAYS
)
21956 /* Case 7: Outside a pred block, with an IT code: error: syntax
21958 inst
.error
= BAD_SYNTAX
;
21961 /* Case 9: Outside a pred block, with no code: OK! */
21963 case OUTSIDE_PRED_INSN
:
21964 if (inst
.cond
> COND_ALWAYS
)
21966 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21968 inst
.error
= BAD_SYNTAX
;
21971 /* Case 18: Outside a pred block, with no code: OK! */
21974 case INSIDE_VPT_INSN
:
21975 /* Case 8: Outside a pred block, with a VPT code: error: should be in
21977 inst
.error
= BAD_OUT_VPT
;
21980 case INSIDE_IT_INSN
:
21981 case INSIDE_IT_LAST_INSN
:
21982 if (inst
.cond
< COND_ALWAYS
)
21984 /* Case 16: Outside a pred block, with an IT code: error: should
21985 be in an IT block. */
21986 if (thumb_mode
== 0)
21989 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
21990 as_tsktsk (_("Warning: conditional outside an IT block"\
21995 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
21996 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
21998 /* Automatically generate the IT instruction. */
21999 new_automatic_it_block (inst
.cond
);
22000 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22001 close_automatic_it_block ();
22005 inst
.error
= BAD_OUT_IT
;
22011 else if (inst
.cond
> COND_ALWAYS
)
22013 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22015 inst
.error
= BAD_SYNTAX
;
22020 case IF_INSIDE_IT_LAST_INSN
:
22021 case NEUTRAL_IT_INSN
:
22025 if (inst
.cond
!= COND_ALWAYS
)
22026 first_error (BAD_SYNTAX
);
22027 now_pred
.state
= MANUAL_PRED_BLOCK
;
22028 now_pred
.block_length
= 0;
22029 now_pred
.type
= VECTOR_PRED
;
22033 now_pred
.state
= MANUAL_PRED_BLOCK
;
22034 now_pred
.block_length
= 0;
22035 now_pred
.type
= SCALAR_PRED
;
22040 case AUTOMATIC_PRED_BLOCK
:
22041 /* Three things may happen now:
22042 a) We should increment current it block size;
22043 b) We should close current it block (closing insn or 4 insns);
22044 c) We should close current it block and start a new one (due
22045 to incompatible conditions or
22046 4 insns-length block reached). */
22048 switch (inst
.pred_insn_type
)
22050 case INSIDE_VPT_INSN
:
22052 case MVE_UNPREDICABLE_INSN
:
22053 case MVE_OUTSIDE_PRED_INSN
:
22055 case OUTSIDE_PRED_INSN
:
22056 /* The closure of the block shall happen immediately,
22057 so any in_pred_block () call reports the block as closed. */
22058 force_automatic_it_block_close ();
22061 case INSIDE_IT_INSN
:
22062 case INSIDE_IT_LAST_INSN
:
22063 case IF_INSIDE_IT_LAST_INSN
:
22064 now_pred
.block_length
++;
22066 if (now_pred
.block_length
> 4
22067 || !now_pred_compatible (inst
.cond
))
22069 force_automatic_it_block_close ();
22070 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
22071 new_automatic_it_block (inst
.cond
);
22075 now_pred
.insn_cond
= TRUE
;
22076 now_pred_add_mask (inst
.cond
);
22079 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
22080 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
22081 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
22082 close_automatic_it_block ();
22085 case NEUTRAL_IT_INSN
:
22086 now_pred
.block_length
++;
22087 now_pred
.insn_cond
= TRUE
;
22089 if (now_pred
.block_length
> 4)
22090 force_automatic_it_block_close ();
22092 now_pred_add_mask (now_pred
.cc
& 1);
22096 close_automatic_it_block ();
22097 now_pred
.state
= MANUAL_PRED_BLOCK
;
22102 case MANUAL_PRED_BLOCK
:
22105 if (now_pred
.type
== SCALAR_PRED
)
22107 /* Check conditional suffixes. */
22108 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
22109 now_pred
.mask
<<= 1;
22110 now_pred
.mask
&= 0x1f;
22111 is_last
= (now_pred
.mask
== 0x10);
22115 now_pred
.cc
^= (now_pred
.mask
>> 4);
22116 cond
= now_pred
.cc
+ 0xf;
22117 now_pred
.mask
<<= 1;
22118 now_pred
.mask
&= 0x1f;
22119 is_last
= now_pred
.mask
== 0x10;
22121 now_pred
.insn_cond
= TRUE
;
22123 switch (inst
.pred_insn_type
)
22125 case OUTSIDE_PRED_INSN
:
22126 if (now_pred
.type
== SCALAR_PRED
)
22128 if (inst
.cond
== COND_ALWAYS
)
22130 /* Case 12: In an IT block, with no code: error: missing
22132 inst
.error
= BAD_NOT_IT
;
22135 else if (inst
.cond
> COND_ALWAYS
)
22137 /* Case 11: In an IT block, with a VPT code: syntax error.
22139 inst
.error
= BAD_SYNTAX
;
22142 else if (thumb_mode
)
22144 /* This is for some special cases where a non-MVE
22145 instruction is not allowed in an IT block, such as cbz,
22146 but are put into one with a condition code.
22147 You could argue this should be a syntax error, but we
22148 gave the 'not allowed in IT block' diagnostic in the
22149 past so we will keep doing so. */
22150 inst
.error
= BAD_NOT_IT
;
22157 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22158 as_tsktsk (MVE_NOT_VPT
);
22161 case MVE_OUTSIDE_PRED_INSN
:
22162 if (now_pred
.type
== SCALAR_PRED
)
22164 if (inst
.cond
== COND_ALWAYS
)
22166 /* Case 3: In an IT block, with no code: warning:
22168 as_tsktsk (MVE_NOT_IT
);
22171 else if (inst
.cond
< COND_ALWAYS
)
22173 /* Case 1: In an IT block, with an IT code: syntax error.
22175 inst
.error
= BAD_SYNTAX
;
22183 if (inst
.cond
< COND_ALWAYS
)
22185 /* Case 4: In a VPT block, with an IT code: syntax error.
22187 inst
.error
= BAD_SYNTAX
;
22190 else if (inst
.cond
== COND_ALWAYS
)
22192 /* Case 6: In a VPT block, with no code: error: missing
22194 inst
.error
= BAD_NOT_VPT
;
22202 case MVE_UNPREDICABLE_INSN
:
22203 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
22205 case INSIDE_IT_INSN
:
22206 if (inst
.cond
> COND_ALWAYS
)
22208 /* Case 11: In an IT block, with a VPT code: syntax error. */
22209 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22210 inst
.error
= BAD_SYNTAX
;
22213 else if (now_pred
.type
== SCALAR_PRED
)
22215 /* Case 10: In an IT block, with an IT code: OK! */
22216 if (cond
!= inst
.cond
)
22218 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
22225 /* Case 13: In a VPT block, with an IT code: error: should be
22227 inst
.error
= BAD_OUT_IT
;
22232 case INSIDE_VPT_INSN
:
22233 if (now_pred
.type
== SCALAR_PRED
)
22235 /* Case 2: In an IT block, with a VPT code: error: must be in a
22237 inst
.error
= BAD_OUT_VPT
;
22240 /* Case 5: In a VPT block, with a VPT code: OK! */
22241 else if (cond
!= inst
.cond
)
22243 inst
.error
= BAD_VPT_COND
;
22247 case INSIDE_IT_LAST_INSN
:
22248 case IF_INSIDE_IT_LAST_INSN
:
22249 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22251 /* Case 4: In a VPT block, with an IT code: syntax error. */
22252 /* Case 11: In an IT block, with a VPT code: syntax error. */
22253 inst
.error
= BAD_SYNTAX
;
22256 else if (cond
!= inst
.cond
)
22258 inst
.error
= BAD_IT_COND
;
22263 inst
.error
= BAD_BRANCH
;
22268 case NEUTRAL_IT_INSN
:
22269 /* The BKPT instruction is unconditional even in a IT or VPT
22274 if (now_pred
.type
== SCALAR_PRED
)
22276 inst
.error
= BAD_IT_IT
;
22279 /* fall through. */
22281 if (inst
.cond
== COND_ALWAYS
)
22283 /* Executing a VPT/VPST instruction inside an IT block or a
22284 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22286 if (now_pred
.type
== SCALAR_PRED
)
22287 as_tsktsk (MVE_NOT_IT
);
22289 as_tsktsk (MVE_NOT_VPT
);
22294 /* VPT/VPST do not accept condition codes. */
22295 inst
.error
= BAD_SYNTAX
;
22306 struct depr_insn_mask
22308 unsigned long pattern
;
22309 unsigned long mask
;
22310 const char* description
;
22313 /* List of 16-bit instruction patterns deprecated in an IT block in
22315 static const struct depr_insn_mask depr_it_insns
[] = {
22316 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22317 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22318 { 0xa000, 0xb800, N_("ADR") },
22319 { 0x4800, 0xf800, N_("Literal loads") },
22320 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22321 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22322 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22323 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22324 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22329 it_fsm_post_encode (void)
22333 if (!now_pred
.state_handled
)
22334 handle_pred_state ();
22336 if (now_pred
.insn_cond
22337 && !now_pred
.warn_deprecated
22338 && warn_on_deprecated
22339 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22340 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22342 if (inst
.instruction
>= 0x10000)
22344 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22345 "performance deprecated in ARMv8-A and ARMv8-R"));
22346 now_pred
.warn_deprecated
= TRUE
;
22350 const struct depr_insn_mask
*p
= depr_it_insns
;
22352 while (p
->mask
!= 0)
22354 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22356 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22357 "instructions of the following class are "
22358 "performance deprecated in ARMv8-A and "
22359 "ARMv8-R: %s"), p
->description
);
22360 now_pred
.warn_deprecated
= TRUE
;
22368 if (now_pred
.block_length
> 1)
22370 as_tsktsk (_("IT blocks containing more than one conditional "
22371 "instruction are performance deprecated in ARMv8-A and "
22373 now_pred
.warn_deprecated
= TRUE
;
22377 is_last
= (now_pred
.mask
== 0x10);
22380 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22386 force_automatic_it_block_close (void)
22388 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22390 close_automatic_it_block ();
22391 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22397 in_pred_block (void)
22399 if (!now_pred
.state_handled
)
22400 handle_pred_state ();
22402 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22405 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22406 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22407 here, hence the "known" in the function name. */
22410 known_t32_only_insn (const struct asm_opcode
*opcode
)
22412 /* Original Thumb-1 wide instruction. */
22413 if (opcode
->tencode
== do_t_blx
22414 || opcode
->tencode
== do_t_branch23
22415 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22416 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22419 /* Wide-only instruction added to ARMv8-M Baseline. */
22420 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22421 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22422 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22423 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22429 /* Whether wide instruction variant can be used if available for a valid OPCODE
22433 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22435 if (known_t32_only_insn (opcode
))
22438 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22439 of variant T3 of B.W is checked in do_t_branch. */
22440 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22441 && opcode
->tencode
== do_t_branch
)
22444 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22445 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22446 && opcode
->tencode
== do_t_mov_cmp
22447 /* Make sure CMP instruction is not affected. */
22448 && opcode
->aencode
== do_mov
)
22451 /* Wide instruction variants of all instructions with narrow *and* wide
22452 variants become available with ARMv6t2. Other opcodes are either
22453 narrow-only or wide-only and are thus available if OPCODE is valid. */
22454 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22457 /* OPCODE with narrow only instruction variant or wide variant not
22463 md_assemble (char *str
)
22466 const struct asm_opcode
* opcode
;
22468 /* Align the previous label if needed. */
22469 if (last_label_seen
!= NULL
)
22471 symbol_set_frag (last_label_seen
, frag_now
);
22472 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22473 S_SET_SEGMENT (last_label_seen
, now_seg
);
22476 memset (&inst
, '\0', sizeof (inst
));
22478 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22479 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22481 opcode
= opcode_lookup (&p
);
22484 /* It wasn't an instruction, but it might be a register alias of
22485 the form alias .req reg, or a Neon .dn/.qn directive. */
22486 if (! create_register_alias (str
, p
)
22487 && ! create_neon_reg_alias (str
, p
))
22488 as_bad (_("bad instruction `%s'"), str
);
22493 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22494 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22496 /* The value which unconditional instructions should have in place of the
22497 condition field. */
22498 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22502 arm_feature_set variant
;
22504 variant
= cpu_variant
;
22505 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22506 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22507 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22508 /* Check that this instruction is supported for this CPU. */
22509 if (!opcode
->tvariant
22510 || (thumb_mode
== 1
22511 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22513 if (opcode
->tencode
== do_t_swi
)
22514 as_bad (_("SVC is not permitted on this architecture"));
22516 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22519 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22520 && opcode
->tencode
!= do_t_branch
)
22522 as_bad (_("Thumb does not support conditional execution"));
22526 /* Two things are addressed here:
22527 1) Implicit require narrow instructions on Thumb-1.
22528 This avoids relaxation accidentally introducing Thumb-2
22530 2) Reject wide instructions in non Thumb-2 cores.
22532 Only instructions with narrow and wide variants need to be handled
22533 but selecting all non wide-only instructions is easier. */
22534 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22535 && !t32_insn_ok (variant
, opcode
))
22537 if (inst
.size_req
== 0)
22539 else if (inst
.size_req
== 4)
22541 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22542 as_bad (_("selected processor does not support 32bit wide "
22543 "variant of instruction `%s'"), str
);
22545 as_bad (_("selected processor does not support `%s' in "
22546 "Thumb-2 mode"), str
);
22551 inst
.instruction
= opcode
->tvalue
;
22553 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22555 /* Prepare the pred_insn_type for those encodings that don't set
22557 it_fsm_pre_encode ();
22559 opcode
->tencode ();
22561 it_fsm_post_encode ();
22564 if (!(inst
.error
|| inst
.relax
))
22566 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
22567 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
22568 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
22570 as_bad (_("cannot honor width suffix -- `%s'"), str
);
22575 /* Something has gone badly wrong if we try to relax a fixed size
22577 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
22579 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22580 *opcode
->tvariant
);
22581 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22582 set those bits when Thumb-2 32-bit instructions are seen. The impact
22583 of relaxable instructions will be considered later after we finish all
22585 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
22586 variant
= arm_arch_none
;
22588 variant
= cpu_variant
;
22589 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
22590 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22593 check_neon_suffixes
;
22597 mapping_state (MAP_THUMB
);
22600 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22604 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22605 is_bx
= (opcode
->aencode
== do_bx
);
22607 /* Check that this instruction is supported for this CPU. */
22608 if (!(is_bx
&& fix_v4bx
)
22609 && !(opcode
->avariant
&&
22610 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
22612 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
22617 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
22621 inst
.instruction
= opcode
->avalue
;
22622 if (opcode
->tag
== OT_unconditionalF
)
22623 inst
.instruction
|= 0xFU
<< 28;
22625 inst
.instruction
|= inst
.cond
<< 28;
22626 inst
.size
= INSN_SIZE
;
22627 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
22629 it_fsm_pre_encode ();
22630 opcode
->aencode ();
22631 it_fsm_post_encode ();
22633 /* Arm mode bx is marked as both v4T and v5 because it's still required
22634 on a hypothetical non-thumb v5 core. */
22636 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
22638 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
22639 *opcode
->avariant
);
22641 check_neon_suffixes
;
22645 mapping_state (MAP_ARM
);
22650 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22658 check_pred_blocks_finished (void)
22663 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
22664 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
22665 == MANUAL_PRED_BLOCK
)
22667 if (now_pred
.type
== SCALAR_PRED
)
22668 as_warn (_("section '%s' finished with an open IT block."),
22671 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22675 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
22677 if (now_pred
.type
== SCALAR_PRED
)
22678 as_warn (_("file finished with an open IT block."));
22680 as_warn (_("file finished with an open VPT/VPST block."));
22685 /* Various frobbings of labels and their addresses. */
22688 arm_start_line_hook (void)
22690 last_label_seen
= NULL
;
22694 arm_frob_label (symbolS
* sym
)
22696 last_label_seen
= sym
;
22698 ARM_SET_THUMB (sym
, thumb_mode
);
22700 #if defined OBJ_COFF || defined OBJ_ELF
22701 ARM_SET_INTERWORK (sym
, support_interwork
);
22704 force_automatic_it_block_close ();
22706 /* Note - do not allow local symbols (.Lxxx) to be labelled
22707 as Thumb functions. This is because these labels, whilst
22708 they exist inside Thumb code, are not the entry points for
22709 possible ARM->Thumb calls. Also, these labels can be used
22710 as part of a computed goto or switch statement. eg gcc
22711 can generate code that looks like this:
22713 ldr r2, [pc, .Laaa]
22723 The first instruction loads the address of the jump table.
22724 The second instruction converts a table index into a byte offset.
22725 The third instruction gets the jump address out of the table.
22726 The fourth instruction performs the jump.
22728 If the address stored at .Laaa is that of a symbol which has the
22729 Thumb_Func bit set, then the linker will arrange for this address
22730 to have the bottom bit set, which in turn would mean that the
22731 address computation performed by the third instruction would end
22732 up with the bottom bit set. Since the ARM is capable of unaligned
22733 word loads, the instruction would then load the incorrect address
22734 out of the jump table, and chaos would ensue. */
22735 if (label_is_thumb_function_name
22736 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
22737 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
22739 /* When the address of a Thumb function is taken the bottom
22740 bit of that address should be set. This will allow
22741 interworking between Arm and Thumb functions to work
22744 THUMB_SET_FUNC (sym
, 1);
22746 label_is_thumb_function_name
= FALSE
;
22749 dwarf2_emit_label (sym
);
22753 arm_data_in_code (void)
22755 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
22757 *input_line_pointer
= '/';
22758 input_line_pointer
+= 5;
22759 *input_line_pointer
= 0;
22767 arm_canonicalize_symbol_name (char * name
)
22771 if (thumb_mode
&& (len
= strlen (name
)) > 5
22772 && streq (name
+ len
- 5, "/data"))
22773 *(name
+ len
- 5) = 0;
22778 /* Table of all register names defined by default. The user can
22779 define additional names with .req. Note that all register names
22780 should appear in both upper and lowercase variants. Some registers
22781 also have mixed-case names. */
22783 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22784 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22785 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22786 #define REGSET(p,t) \
22787 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22788 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22789 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22790 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22791 #define REGSETH(p,t) \
22792 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22793 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22794 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22795 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22796 #define REGSET2(p,t) \
22797 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22798 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22799 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22800 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22801 #define SPLRBANK(base,bank,t) \
22802 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22803 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22804 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22805 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22806 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22807 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22809 static const struct reg_entry reg_names
[] =
22811 /* ARM integer registers. */
22812 REGSET(r
, RN
), REGSET(R
, RN
),
22814 /* ATPCS synonyms. */
22815 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
22816 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
22817 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
22819 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
22820 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
22821 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
22823 /* Well-known aliases. */
22824 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
22825 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
22827 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
22828 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
22830 /* Defining the new Zero register from ARMv8.1-M. */
22834 /* Coprocessor numbers. */
22835 REGSET(p
, CP
), REGSET(P
, CP
),
22837 /* Coprocessor register numbers. The "cr" variants are for backward
22839 REGSET(c
, CN
), REGSET(C
, CN
),
22840 REGSET(cr
, CN
), REGSET(CR
, CN
),
22842 /* ARM banked registers. */
22843 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
22844 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
22845 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
22846 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
22847 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
22848 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
22849 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
22851 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
22852 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
22853 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
22854 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
22855 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
22856 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
22857 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
22858 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
22860 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
22861 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
22862 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
22863 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
22864 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
22865 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
22866 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
22867 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22868 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22870 /* FPA registers. */
22871 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
22872 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
22874 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
22875 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
22877 /* VFP SP registers. */
22878 REGSET(s
,VFS
), REGSET(S
,VFS
),
22879 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
22881 /* VFP DP Registers. */
22882 REGSET(d
,VFD
), REGSET(D
,VFD
),
22883 /* Extra Neon DP registers. */
22884 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
22886 /* Neon QP registers. */
22887 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
22889 /* VFP control registers. */
22890 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
22891 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
22892 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
22893 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
22894 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
22895 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
22896 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
22897 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
22898 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
22899 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
22900 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
22902 /* Maverick DSP coprocessor registers. */
22903 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
22904 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
22906 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
22907 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
22908 REGDEF(dspsc
,0,DSPSC
),
22910 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
22911 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
22912 REGDEF(DSPSC
,0,DSPSC
),
22914 /* iWMMXt data registers - p0, c0-15. */
22915 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
22917 /* iWMMXt control registers - p1, c0-3. */
22918 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
22919 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
22920 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
22921 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
22923 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
22924 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
22925 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
22926 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
22927 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
22929 /* XScale accumulator registers. */
22930 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
22936 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
22937 within psr_required_here. */
22938 static const struct asm_psr psrs
[] =
22940 /* Backward compatibility notation. Note that "all" is no longer
22941 truly all possible PSR bits. */
22942 {"all", PSR_c
| PSR_f
},
22946 /* Individual flags. */
22952 /* Combinations of flags. */
22953 {"fs", PSR_f
| PSR_s
},
22954 {"fx", PSR_f
| PSR_x
},
22955 {"fc", PSR_f
| PSR_c
},
22956 {"sf", PSR_s
| PSR_f
},
22957 {"sx", PSR_s
| PSR_x
},
22958 {"sc", PSR_s
| PSR_c
},
22959 {"xf", PSR_x
| PSR_f
},
22960 {"xs", PSR_x
| PSR_s
},
22961 {"xc", PSR_x
| PSR_c
},
22962 {"cf", PSR_c
| PSR_f
},
22963 {"cs", PSR_c
| PSR_s
},
22964 {"cx", PSR_c
| PSR_x
},
22965 {"fsx", PSR_f
| PSR_s
| PSR_x
},
22966 {"fsc", PSR_f
| PSR_s
| PSR_c
},
22967 {"fxs", PSR_f
| PSR_x
| PSR_s
},
22968 {"fxc", PSR_f
| PSR_x
| PSR_c
},
22969 {"fcs", PSR_f
| PSR_c
| PSR_s
},
22970 {"fcx", PSR_f
| PSR_c
| PSR_x
},
22971 {"sfx", PSR_s
| PSR_f
| PSR_x
},
22972 {"sfc", PSR_s
| PSR_f
| PSR_c
},
22973 {"sxf", PSR_s
| PSR_x
| PSR_f
},
22974 {"sxc", PSR_s
| PSR_x
| PSR_c
},
22975 {"scf", PSR_s
| PSR_c
| PSR_f
},
22976 {"scx", PSR_s
| PSR_c
| PSR_x
},
22977 {"xfs", PSR_x
| PSR_f
| PSR_s
},
22978 {"xfc", PSR_x
| PSR_f
| PSR_c
},
22979 {"xsf", PSR_x
| PSR_s
| PSR_f
},
22980 {"xsc", PSR_x
| PSR_s
| PSR_c
},
22981 {"xcf", PSR_x
| PSR_c
| PSR_f
},
22982 {"xcs", PSR_x
| PSR_c
| PSR_s
},
22983 {"cfs", PSR_c
| PSR_f
| PSR_s
},
22984 {"cfx", PSR_c
| PSR_f
| PSR_x
},
22985 {"csf", PSR_c
| PSR_s
| PSR_f
},
22986 {"csx", PSR_c
| PSR_s
| PSR_x
},
22987 {"cxf", PSR_c
| PSR_x
| PSR_f
},
22988 {"cxs", PSR_c
| PSR_x
| PSR_s
},
22989 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
22990 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
22991 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
22992 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
22993 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
22994 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
22995 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
22996 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
22997 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
22998 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
22999 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23000 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23001 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23002 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23003 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23004 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23005 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23006 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23007 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23008 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23009 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23010 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23011 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23012 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23015 /* Table of V7M psr names. */
23016 static const struct asm_psr v7m_psrs
[] =
23018 {"apsr", 0x0 }, {"APSR", 0x0 },
23019 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23020 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23021 {"psr", 0x3 }, {"PSR", 0x3 },
23022 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23023 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23024 {"epsr", 0x6 }, {"EPSR", 0x6 },
23025 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23026 {"msp", 0x8 }, {"MSP", 0x8 },
23027 {"psp", 0x9 }, {"PSP", 0x9 },
23028 {"msplim", 0xa }, {"MSPLIM", 0xa },
23029 {"psplim", 0xb }, {"PSPLIM", 0xb },
23030 {"primask", 0x10}, {"PRIMASK", 0x10},
23031 {"basepri", 0x11}, {"BASEPRI", 0x11},
23032 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23033 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23034 {"control", 0x14}, {"CONTROL", 0x14},
23035 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23036 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23037 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
23038 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
23039 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
23040 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
23041 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
23042 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
23043 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
23046 /* Table of all shift-in-operand names. */
23047 static const struct asm_shift_name shift_names
[] =
23049 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
23050 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
23051 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
23052 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
23053 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
23054 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
23055 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
23058 /* Table of all explicit relocation names. */
23060 static struct reloc_entry reloc_names
[] =
23062 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
23063 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
23064 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
23065 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
23066 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
23067 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
23068 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
23069 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
23070 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
23071 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
23072 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
23073 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
23074 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
23075 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
23076 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
23077 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
23078 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
23079 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
23080 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
23081 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
23082 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23083 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23084 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
23085 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
23086 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
23087 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
23088 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
23092 /* Table of all conditional affixes. */
23093 static const struct asm_cond conds
[] =
23097 {"cs", 0x2}, {"hs", 0x2},
23098 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
23111 static const struct asm_cond vconds
[] =
23117 #define UL_BARRIER(L,U,CODE,FEAT) \
23118 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
23119 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
23121 static struct asm_barrier_opt barrier_opt_names
[] =
23123 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
23124 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
23125 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
23126 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
23127 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
23128 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
23129 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
23130 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
23131 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
23132 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
23133 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
23134 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
23135 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
23136 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
23137 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
23138 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
23143 /* Table of ARM-format instructions. */
23145 /* Macros for gluing together operand strings. N.B. In all cases
23146 other than OPS0, the trailing OP_stop comes from default
23147 zero-initialization of the unspecified elements of the array. */
23148 #define OPS0() { OP_stop, }
23149 #define OPS1(a) { OP_##a, }
23150 #define OPS2(a,b) { OP_##a,OP_##b, }
23151 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
23152 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
23153 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
23154 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23156 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23157 This is useful when mixing operands for ARM and THUMB, i.e. using the
23158 MIX_ARM_THUMB_OPERANDS macro.
23159 In order to use these macros, prefix the number of operands with _
23161 #define OPS_1(a) { a, }
23162 #define OPS_2(a,b) { a,b, }
23163 #define OPS_3(a,b,c) { a,b,c, }
23164 #define OPS_4(a,b,c,d) { a,b,c,d, }
23165 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23166 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23168 /* These macros abstract out the exact format of the mnemonic table and
23169 save some repeated characters. */
23171 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23172 #define TxCE(mnem, op, top, nops, ops, ae, te) \
23173 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
23174 THUMB_VARIANT, do_##ae, do_##te, 0 }
23176 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23177 a T_MNEM_xyz enumerator. */
23178 #define TCE(mnem, aop, top, nops, ops, ae, te) \
23179 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
23180 #define tCE(mnem, aop, top, nops, ops, ae, te) \
23181 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23183 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23184 infix after the third character. */
23185 #define TxC3(mnem, op, top, nops, ops, ae, te) \
23186 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
23187 THUMB_VARIANT, do_##ae, do_##te, 0 }
23188 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
23189 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
23190 THUMB_VARIANT, do_##ae, do_##te, 0 }
23191 #define TC3(mnem, aop, top, nops, ops, ae, te) \
23192 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
23193 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
23194 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
23195 #define tC3(mnem, aop, top, nops, ops, ae, te) \
23196 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23197 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
23198 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23200 /* Mnemonic that cannot be conditionalized. The ARM condition-code
23201 field is still 0xE. Many of the Thumb variants can be executed
23202 conditionally, so this is checked separately. */
23203 #define TUE(mnem, op, top, nops, ops, ae, te) \
23204 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23205 THUMB_VARIANT, do_##ae, do_##te, 0 }
23207 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23208 Used by mnemonics that have very minimal differences in the encoding for
23209 ARM and Thumb variants and can be handled in a common function. */
23210 #define TUEc(mnem, op, top, nops, ops, en) \
23211 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23212 THUMB_VARIANT, do_##en, do_##en, 0 }
23214 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23215 condition code field. */
23216 #define TUF(mnem, op, top, nops, ops, ae, te) \
23217 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
23218 THUMB_VARIANT, do_##ae, do_##te, 0 }
23220 /* ARM-only variants of all the above. */
23221 #define CE(mnem, op, nops, ops, ae) \
23222 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23224 #define C3(mnem, op, nops, ops, ae) \
23225 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23227 /* Thumb-only variants of TCE and TUE. */
23228 #define ToC(mnem, top, nops, ops, te) \
23229 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23232 #define ToU(mnem, top, nops, ops, te) \
23233 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
23236 /* T_MNEM_xyz enumerator variants of ToC. */
23237 #define toC(mnem, top, nops, ops, te) \
23238 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23241 /* T_MNEM_xyz enumerator variants of ToU. */
23242 #define toU(mnem, top, nops, ops, te) \
23243 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23246 /* Legacy mnemonics that always have conditional infix after the third
23248 #define CL(mnem, op, nops, ops, ae) \
23249 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23250 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23252 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23253 #define cCE(mnem, op, nops, ops, ae) \
23254 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23256 /* mov instructions that are shared between coprocessor and MVE. */
23257 #define mcCE(mnem, op, nops, ops, ae) \
23258 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23260 /* Legacy coprocessor instructions where conditional infix and conditional
23261 suffix are ambiguous. For consistency this includes all FPA instructions,
23262 not just the potentially ambiguous ones. */
23263 #define cCL(mnem, op, nops, ops, ae) \
23264 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23265 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23267 /* Coprocessor, takes either a suffix or a position-3 infix
23268 (for an FPA corner case). */
23269 #define C3E(mnem, op, nops, ops, ae) \
23270 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23271 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23273 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23274 { m1 #m2 m3, OPS##nops ops, \
23275 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23276 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23278 #define CM(m1, m2, op, nops, ops, ae) \
23279 xCM_ (m1, , m2, op, nops, ops, ae), \
23280 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23281 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23282 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23283 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23284 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23285 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23286 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23287 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23288 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23289 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23290 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23291 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23292 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23293 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23294 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23295 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23296 xCM_ (m1, le, m2, op, nops, ops, ae), \
23297 xCM_ (m1, al, m2, op, nops, ops, ae)
23299 #define UE(mnem, op, nops, ops, ae) \
23300 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23302 #define UF(mnem, op, nops, ops, ae) \
23303 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23305 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23306 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23307 use the same encoding function for each. */
23308 #define NUF(mnem, op, nops, ops, enc) \
23309 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23310 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23312 /* Neon data processing, version which indirects through neon_enc_tab for
23313 the various overloaded versions of opcodes. */
23314 #define nUF(mnem, op, nops, ops, enc) \
23315 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23316 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23318 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23320 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23321 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23322 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23324 #define NCE(mnem, op, nops, ops, enc) \
23325 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23327 #define NCEF(mnem, op, nops, ops, enc) \
23328 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23330 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23331 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23332 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23333 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23335 #define nCE(mnem, op, nops, ops, enc) \
23336 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23338 #define nCEF(mnem, op, nops, ops, enc) \
23339 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23342 #define mCEF(mnem, op, nops, ops, enc) \
23343 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23344 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23347 /* nCEF but for MVE predicated instructions. */
23348 #define mnCEF(mnem, op, nops, ops, enc) \
23349 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23351 /* nCE but for MVE predicated instructions. */
23352 #define mnCE(mnem, op, nops, ops, enc) \
23353 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23355 /* NUF but for potentially MVE predicated instructions. */
23356 #define MNUF(mnem, op, nops, ops, enc) \
23357 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23358 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23360 /* nUF but for potentially MVE predicated instructions. */
23361 #define mnUF(mnem, op, nops, ops, enc) \
23362 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23363 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23365 /* ToC but for potentially MVE predicated instructions. */
23366 #define mToC(mnem, top, nops, ops, te) \
23367 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23370 /* NCE but for MVE predicated instructions. */
23371 #define MNCE(mnem, op, nops, ops, enc) \
23372 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23374 /* NCEF but for MVE predicated instructions. */
23375 #define MNCEF(mnem, op, nops, ops, enc) \
23376 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23379 static const struct asm_opcode insns
[] =
23381 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23382 #define THUMB_VARIANT & arm_ext_v4t
23383 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23384 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23385 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23386 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23387 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23388 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23389 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23390 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23391 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23392 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23393 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23394 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23395 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23396 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23397 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23398 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23400 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23401 for setting PSR flag bits. They are obsolete in V6 and do not
23402 have Thumb equivalents. */
23403 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23404 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23405 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23406 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23407 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23408 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23409 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23410 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23411 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23413 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23414 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23415 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23416 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23418 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23419 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23420 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23422 OP_ADDRGLDR
),ldst
, t_ldst
),
23423 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23425 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23426 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23427 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23428 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23429 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23430 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23432 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23433 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23436 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23437 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23438 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23439 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23441 /* Thumb-compatibility pseudo ops. */
23442 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23443 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23444 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23445 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23446 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23447 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23448 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23449 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23450 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23451 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23452 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23453 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23455 /* These may simplify to neg. */
23456 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23457 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23459 #undef THUMB_VARIANT
23460 #define THUMB_VARIANT & arm_ext_os
23462 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23463 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23465 #undef THUMB_VARIANT
23466 #define THUMB_VARIANT & arm_ext_v6
23468 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23470 /* V1 instructions with no Thumb analogue prior to V6T2. */
23471 #undef THUMB_VARIANT
23472 #define THUMB_VARIANT & arm_ext_v6t2
23474 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23475 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23476 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23478 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23479 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23480 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23481 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23483 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23484 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23486 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23487 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23489 /* V1 instructions with no Thumb analogue at all. */
23490 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23491 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23493 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23494 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23495 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23496 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23497 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23498 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23499 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23500 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23503 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23504 #undef THUMB_VARIANT
23505 #define THUMB_VARIANT & arm_ext_v4t
23507 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23508 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23510 #undef THUMB_VARIANT
23511 #define THUMB_VARIANT & arm_ext_v6t2
23513 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23514 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23516 /* Generic coprocessor instructions. */
23517 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23518 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23519 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23520 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23521 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23522 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23523 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23526 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23528 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23529 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23532 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23533 #undef THUMB_VARIANT
23534 #define THUMB_VARIANT & arm_ext_msr
23536 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23537 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23540 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23541 #undef THUMB_VARIANT
23542 #define THUMB_VARIANT & arm_ext_v6t2
23544 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23545 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23546 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23547 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23548 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23549 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23550 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23551 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23554 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23555 #undef THUMB_VARIANT
23556 #define THUMB_VARIANT & arm_ext_v4t
23558 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23559 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23560 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23561 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23562 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23563 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23566 #define ARM_VARIANT & arm_ext_v4t_5
23568 /* ARM Architecture 4T. */
23569 /* Note: bx (and blx) are required on V5, even if the processor does
23570 not support Thumb. */
23571 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
23574 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23575 #undef THUMB_VARIANT
23576 #define THUMB_VARIANT & arm_ext_v5t
23578 /* Note: blx has 2 variants; the .value coded here is for
23579 BLX(2). Only this variant has conditional execution. */
23580 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
23581 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
23583 #undef THUMB_VARIANT
23584 #define THUMB_VARIANT & arm_ext_v6t2
23586 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
23587 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23588 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23589 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23590 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23591 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23592 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23593 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23596 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23597 #undef THUMB_VARIANT
23598 #define THUMB_VARIANT & arm_ext_v5exp
23600 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23601 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23602 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23603 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23605 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23606 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23608 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23609 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23610 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23611 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23613 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23614 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23615 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23616 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23618 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23619 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23621 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23622 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23623 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23624 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23627 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23628 #undef THUMB_VARIANT
23629 #define THUMB_VARIANT & arm_ext_v6t2
23631 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
23632 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
23634 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
23635 ADDRGLDRS
), ldrd
, t_ldstd
),
23637 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23638 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23641 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23643 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
23646 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23647 #undef THUMB_VARIANT
23648 #define THUMB_VARIANT & arm_ext_v6
23650 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23651 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23652 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23653 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23654 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23655 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23656 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23657 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23658 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23659 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
23661 #undef THUMB_VARIANT
23662 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23664 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
23665 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23667 #undef THUMB_VARIANT
23668 #define THUMB_VARIANT & arm_ext_v6t2
23670 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23671 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23673 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
23674 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
23676 /* ARM V6 not included in V7M. */
23677 #undef THUMB_VARIANT
23678 #define THUMB_VARIANT & arm_ext_v6_notm
23679 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23680 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23681 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
23682 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
23683 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23684 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23685 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
23686 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23687 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
23688 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23689 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23690 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23691 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23692 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23693 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
23694 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
23695 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23696 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23697 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
23699 /* ARM V6 not included in V7M (eg. integer SIMD). */
23700 #undef THUMB_VARIANT
23701 #define THUMB_VARIANT & arm_ext_v6_dsp
23702 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
23703 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
23704 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23705 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23706 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23707 /* Old name for QASX. */
23708 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23709 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23710 /* Old name for QSAX. */
23711 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23712 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23713 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23714 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23715 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23716 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23717 /* Old name for SASX. */
23718 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23719 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23720 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23721 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23722 /* Old name for SHASX. */
23723 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23724 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23725 /* Old name for SHSAX. */
23726 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23727 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23728 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23729 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23730 /* Old name for SSAX. */
23731 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23732 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23733 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23734 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23735 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23736 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23737 /* Old name for UASX. */
23738 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23739 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23740 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23741 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23742 /* Old name for UHASX. */
23743 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23744 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23745 /* Old name for UHSAX. */
23746 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23747 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23748 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23749 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23750 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23751 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23752 /* Old name for UQASX. */
23753 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23754 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23755 /* Old name for UQSAX. */
23756 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23757 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23758 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23759 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23760 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23761 /* Old name for USAX. */
23762 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23763 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23764 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23765 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23766 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23767 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23768 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23769 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23770 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23771 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23772 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23773 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23774 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23775 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23776 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23777 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23778 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23779 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23780 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23781 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23782 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23783 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23784 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23785 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23786 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23787 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23788 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23789 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23790 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23791 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
23792 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
23793 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23794 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23795 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
23798 #define ARM_VARIANT & arm_ext_v6k_v6t2
23799 #undef THUMB_VARIANT
23800 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23802 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
23803 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
23804 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
23805 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
23807 #undef THUMB_VARIANT
23808 #define THUMB_VARIANT & arm_ext_v6_notm
23809 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
23811 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
23812 RRnpcb
), strexd
, t_strexd
),
23814 #undef THUMB_VARIANT
23815 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23816 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
23818 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
23820 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23822 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23824 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
23827 #define ARM_VARIANT & arm_ext_sec
23828 #undef THUMB_VARIANT
23829 #define THUMB_VARIANT & arm_ext_sec
23831 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
23834 #define ARM_VARIANT & arm_ext_virt
23835 #undef THUMB_VARIANT
23836 #define THUMB_VARIANT & arm_ext_virt
23838 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
23839 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
23842 #define ARM_VARIANT & arm_ext_pan
23843 #undef THUMB_VARIANT
23844 #define THUMB_VARIANT & arm_ext_pan
23846 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
23849 #define ARM_VARIANT & arm_ext_v6t2
23850 #undef THUMB_VARIANT
23851 #define THUMB_VARIANT & arm_ext_v6t2
23853 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
23854 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
23855 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23856 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23858 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23859 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
23861 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23862 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23863 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23864 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23867 #define ARM_VARIANT & arm_ext_v3
23868 #undef THUMB_VARIANT
23869 #define THUMB_VARIANT & arm_ext_v6t2
23871 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
23872 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
23873 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
23876 #define ARM_VARIANT & arm_ext_v6t2
23877 #undef THUMB_VARIANT
23878 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23879 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23880 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23882 /* Thumb-only instructions. */
23884 #define ARM_VARIANT NULL
23885 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
23886 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
23888 /* ARM does not really have an IT instruction, so always allow it.
23889 The opcode is copied from Thumb in order to allow warnings in
23890 -mimplicit-it=[never | arm] modes. */
23892 #define ARM_VARIANT & arm_ext_v1
23893 #undef THUMB_VARIANT
23894 #define THUMB_VARIANT & arm_ext_v6t2
23896 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
23897 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
23898 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
23899 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
23900 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
23901 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
23902 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
23903 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
23904 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
23905 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
23906 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
23907 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
23908 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
23909 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
23910 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
23911 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
23912 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23913 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23915 /* Thumb2 only instructions. */
23917 #define ARM_VARIANT NULL
23919 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23920 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23921 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23922 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23923 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
23924 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
23926 /* Hardware division instructions. */
23928 #define ARM_VARIANT & arm_ext_adiv
23929 #undef THUMB_VARIANT
23930 #define THUMB_VARIANT & arm_ext_div
23932 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23933 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23935 /* ARM V6M/V7 instructions. */
23937 #define ARM_VARIANT & arm_ext_barrier
23938 #undef THUMB_VARIANT
23939 #define THUMB_VARIANT & arm_ext_barrier
23941 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
23942 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
23943 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
23945 /* ARM V7 instructions. */
23947 #define ARM_VARIANT & arm_ext_v7
23948 #undef THUMB_VARIANT
23949 #define THUMB_VARIANT & arm_ext_v7
23951 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
23952 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
23955 #define ARM_VARIANT & arm_ext_mp
23956 #undef THUMB_VARIANT
23957 #define THUMB_VARIANT & arm_ext_mp
23959 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
23961 /* AArchv8 instructions. */
23963 #define ARM_VARIANT & arm_ext_v8
23965 /* Instructions shared between armv8-a and armv8-m. */
23966 #undef THUMB_VARIANT
23967 #define THUMB_VARIANT & arm_ext_atomics
23969 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23970 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23971 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23972 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23973 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23974 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23975 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23976 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
23977 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23978 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23980 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23982 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23984 #undef THUMB_VARIANT
23985 #define THUMB_VARIANT & arm_ext_v8
23987 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
23988 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
23990 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
23993 /* Defined in V8 but is in undefined encoding space for earlier
23994 architectures. However earlier architectures are required to treat
23995 this instuction as a semihosting trap as well. Hence while not explicitly
23996 defined as such, it is in fact correct to define the instruction for all
23998 #undef THUMB_VARIANT
23999 #define THUMB_VARIANT & arm_ext_v1
24001 #define ARM_VARIANT & arm_ext_v1
24002 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24004 /* ARMv8 T32 only. */
24006 #define ARM_VARIANT NULL
24007 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24008 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24009 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24011 /* FP for ARMv8. */
24013 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24014 #undef THUMB_VARIANT
24015 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24017 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24018 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24019 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24020 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24021 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24022 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24023 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24024 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24025 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
24026 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
24027 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
24029 /* Crypto v1 extensions. */
24031 #define ARM_VARIANT & fpu_crypto_ext_armv8
24032 #undef THUMB_VARIANT
24033 #define THUMB_VARIANT & fpu_crypto_ext_armv8
24035 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
24036 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
24037 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
24038 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
24039 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
24040 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
24041 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
24042 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
24043 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
24044 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
24045 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
24046 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
24047 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
24048 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
24051 #define ARM_VARIANT & crc_ext_armv8
24052 #undef THUMB_VARIANT
24053 #define THUMB_VARIANT & crc_ext_armv8
24054 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
24055 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
24056 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
24057 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
24058 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
24059 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
24061 /* ARMv8.2 RAS extension. */
24063 #define ARM_VARIANT & arm_ext_ras
24064 #undef THUMB_VARIANT
24065 #define THUMB_VARIANT & arm_ext_ras
24066 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
24069 #define ARM_VARIANT & arm_ext_v8_3
24070 #undef THUMB_VARIANT
24071 #define THUMB_VARIANT & arm_ext_v8_3
24072 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
24075 #define ARM_VARIANT & fpu_neon_ext_dotprod
24076 #undef THUMB_VARIANT
24077 #define THUMB_VARIANT & fpu_neon_ext_dotprod
24078 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
24079 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
24082 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
24083 #undef THUMB_VARIANT
24084 #define THUMB_VARIANT NULL
24086 cCE("wfs", e200110
, 1, (RR
), rd
),
24087 cCE("rfs", e300110
, 1, (RR
), rd
),
24088 cCE("wfc", e400110
, 1, (RR
), rd
),
24089 cCE("rfc", e500110
, 1, (RR
), rd
),
24091 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24092 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24093 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24094 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24096 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24097 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24098 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24099 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24101 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
24102 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
24103 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
24104 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
24105 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
24106 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
24107 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
24108 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
24109 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
24110 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
24111 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
24112 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
24114 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
24115 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
24116 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
24117 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
24118 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
24119 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
24120 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
24121 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
24122 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
24123 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
24124 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
24125 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
24127 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
24128 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
24129 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
24130 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
24131 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
24132 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
24133 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
24134 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
24135 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
24136 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
24137 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
24138 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
24140 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
24141 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
24142 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
24143 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
24144 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
24145 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
24146 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
24147 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
24148 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
24149 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
24150 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
24151 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
24153 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
24154 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
24155 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
24156 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
24157 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
24158 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
24159 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
24160 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
24161 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
24162 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
24163 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
24164 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
24166 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
24167 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
24168 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
24169 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
24170 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
24171 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
24172 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
24173 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
24174 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
24175 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
24176 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
24177 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
24179 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
24180 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
24181 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
24182 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
24183 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
24184 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
24185 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
24186 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
24187 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
24188 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
24189 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
24190 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
24192 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
24193 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
24194 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
24195 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
24196 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
24197 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
24198 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
24199 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
24200 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
24201 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
24202 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
24203 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
24205 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
24206 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
24207 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
24208 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
24209 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
24210 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
24211 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
24212 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
24213 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
24214 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
24215 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
24216 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
24218 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
24219 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
24220 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
24221 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
24222 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
24223 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
24224 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
24225 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
24226 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
24227 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
24228 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
24229 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
24231 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
24232 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
24233 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
24234 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
24235 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
24236 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
24237 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
24238 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
24239 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24240 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24241 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24242 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24244 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24245 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24246 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24247 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24248 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24249 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24250 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24251 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24252 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24253 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24254 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24255 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24257 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24258 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24259 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24260 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24261 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24262 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24263 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24264 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24265 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24266 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24267 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24268 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24270 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24271 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24272 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24273 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24274 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24275 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24276 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24277 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24278 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24279 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24280 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24281 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24283 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24284 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24285 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24286 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24287 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24288 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24289 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24290 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24291 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24292 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24293 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24294 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24296 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24297 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24298 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24299 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24300 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24301 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24302 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24303 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24304 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24305 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24306 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24307 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24309 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24310 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24311 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24312 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24313 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24314 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24315 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24316 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24317 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24318 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24319 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24320 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24322 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24323 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24324 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24325 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24326 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24327 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24328 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24329 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24330 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24331 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24332 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24333 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24335 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24336 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24337 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24338 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24339 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24340 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24341 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24342 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24343 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24344 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24345 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24346 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24348 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24349 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24350 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24351 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24352 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24353 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24354 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24355 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24356 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24357 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24358 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24359 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24361 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24362 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24363 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24364 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24365 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24366 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24367 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24368 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24369 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24370 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24371 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24372 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24374 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24375 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24376 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24377 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24378 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24379 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24380 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24381 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24382 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24383 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24384 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24385 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24387 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24388 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24389 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24390 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24391 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24392 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24393 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24394 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24395 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24396 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24397 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24398 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24400 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24401 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24402 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24403 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24404 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24405 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24406 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24407 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24408 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24409 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24410 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24411 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24413 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24414 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24415 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24416 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24417 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24418 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24419 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24420 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24421 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24422 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24423 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24424 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24426 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24427 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24428 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24429 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24430 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24431 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24432 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24433 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24434 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24435 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24436 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24437 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24439 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24440 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24441 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24442 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24443 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24444 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24445 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24446 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24447 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24448 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24449 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24450 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24452 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24453 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24454 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24455 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24456 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24457 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24458 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24459 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24460 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24461 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24462 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24463 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24465 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24466 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24467 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24468 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24469 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24470 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24471 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24472 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24473 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24474 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24475 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24476 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24478 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24479 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24480 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24481 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24483 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24484 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24485 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24486 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24487 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24488 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24489 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24490 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24491 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24492 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24493 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24494 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24496 /* The implementation of the FIX instruction is broken on some
24497 assemblers, in that it accepts a precision specifier as well as a
24498 rounding specifier, despite the fact that this is meaningless.
24499 To be more compatible, we accept it as well, though of course it
24500 does not set any bits. */
24501 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24502 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24503 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24504 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24505 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24506 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24507 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24508 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24509 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24510 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24511 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24512 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24513 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24515 /* Instructions that were new with the real FPA, call them V2. */
24517 #define ARM_VARIANT & fpu_fpa_ext_v2
24519 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24520 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24521 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24522 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24523 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24524 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24527 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24528 #undef THUMB_VARIANT
24529 #define THUMB_VARIANT & arm_ext_v6t2
24530 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24531 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
24532 #undef THUMB_VARIANT
24534 /* Moves and type conversions. */
24535 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24536 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24537 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24538 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24539 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24540 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24541 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24542 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24543 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24545 /* Memory operations. */
24546 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24547 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24548 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24549 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24550 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24551 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24552 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24553 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24554 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24555 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24556 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24557 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24558 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24559 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24560 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24561 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24562 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24563 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24565 /* Monadic operations. */
24566 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24567 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24568 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24570 /* Dyadic operations. */
24571 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24572 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24573 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24574 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24575 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24576 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24577 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24578 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24579 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24582 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24583 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
24584 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24585 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
24587 /* Double precision load/store are still present on single precision
24588 implementations. */
24589 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24590 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24591 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24592 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24593 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24594 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24595 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24596 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24597 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24598 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24601 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24603 /* Moves and type conversions. */
24604 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24605 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24606 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24607 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24608 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24609 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24610 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24611 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24612 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24613 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24614 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24615 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24617 /* Monadic operations. */
24618 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24619 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24620 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24622 /* Dyadic operations. */
24623 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24624 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24625 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24626 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24627 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24628 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24629 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24630 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24631 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24634 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24635 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
24636 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24637 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
24639 /* Instructions which may belong to either the Neon or VFP instruction sets.
24640 Individual encoder functions perform additional architecture checks. */
24642 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24643 #undef THUMB_VARIANT
24644 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24646 /* These mnemonics are unique to VFP. */
24647 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
24648 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
24649 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24650 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24651 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24652 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
24653 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
24654 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
24656 /* Mnemonics shared by Neon and VFP. */
24657 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
24659 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24660 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24661 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24662 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24663 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24664 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24666 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
24667 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
24668 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
24669 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
24672 /* NOTE: All VMOV encoding is special-cased! */
24673 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
24675 #undef THUMB_VARIANT
24676 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24677 by different feature bits. Since we are setting the Thumb guard, we can
24678 require Thumb-1 which makes it a nop guard and set the right feature bit in
24679 do_vldr_vstr (). */
24680 #define THUMB_VARIANT & arm_ext_v4t
24681 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24682 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24685 #define ARM_VARIANT & arm_ext_fp16
24686 #undef THUMB_VARIANT
24687 #define THUMB_VARIANT & arm_ext_fp16
24688 /* New instructions added from v8.2, allowing the extraction and insertion of
24689 the upper 16 bits of a 32-bit vector register. */
24690 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
24691 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
24693 /* New backported fma/fms instructions optional in v8.2. */
24694 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
24695 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
24697 #undef THUMB_VARIANT
24698 #define THUMB_VARIANT & fpu_neon_ext_v1
24700 #define ARM_VARIANT & fpu_neon_ext_v1
24702 /* Data processing with three registers of the same length. */
24703 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24704 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
24705 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
24706 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24707 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24708 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24709 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
24710 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24711 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24712 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24713 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24714 /* If not immediate, fall back to neon_dyadic_i64_su.
24715 shl should accept I8 I16 I32 I64,
24716 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24717 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
24718 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
24719 /* Logic ops, types optional & ignored. */
24720 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24721 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24722 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24723 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24724 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
24725 /* Bitfield ops, untyped. */
24726 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24727 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24728 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24729 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24730 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24731 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24732 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
24733 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24734 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24735 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24736 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24737 back to neon_dyadic_if_su. */
24738 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24739 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24740 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24741 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24742 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24743 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24744 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24745 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24746 /* Comparison. Type I8 I16 I32 F32. */
24747 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
24748 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
24749 /* As above, D registers only. */
24750 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24751 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24752 /* Int and float variants, signedness unimportant. */
24753 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24754 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24755 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
24756 /* Add/sub take types I8 I16 I32 I64 F32. */
24757 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24758 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24759 /* vtst takes sizes 8, 16, 32. */
24760 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
24761 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
24762 /* VMUL takes I8 I16 I32 F32 P8. */
24763 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
24764 /* VQD{R}MULH takes S16 S32. */
24765 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24766 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24767 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24768 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24769 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24770 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24771 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24772 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24773 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24774 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24775 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24776 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24777 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24778 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24779 /* ARM v8.1 extension. */
24780 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24781 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24782 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24784 /* Two address, int/float. Types S8 S16 S32 F32. */
24785 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24786 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24788 /* Data processing with two registers and a shift amount. */
24789 /* Right shifts, and variants with rounding.
24790 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24791 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24792 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24793 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24794 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24795 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24796 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24797 /* Shift and insert. Sizes accepted 8 16 32 64. */
24798 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
24799 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
24800 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24801 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
24802 /* Right shift immediate, saturating & narrowing, with rounding variants.
24803 Types accepted S16 S32 S64 U16 U32 U64. */
24804 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24805 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24806 /* As above, unsigned. Types accepted S16 S32 S64. */
24807 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24808 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24809 /* Right shift narrowing. Types accepted I16 I32 I64. */
24810 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24811 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24812 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24813 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
24814 /* CVT with optional immediate for fixed-point variant. */
24815 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
24817 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
24819 /* Data processing, three registers of different lengths. */
24820 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24821 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
24822 /* If not scalar, fall back to neon_dyadic_long.
24823 Vector types as above, scalar types S16 S32 U16 U32. */
24824 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24825 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24826 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24827 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24828 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24829 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24830 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24831 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24832 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24833 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24834 /* Saturating doubling multiplies. Types S16 S32. */
24835 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24836 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24837 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24838 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24839 S16 S32 U16 U32. */
24840 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
24842 /* Extract. Size 8. */
24843 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
24844 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
24846 /* Two registers, miscellaneous. */
24847 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24848 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
24849 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
24850 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
24851 /* Vector replicate. Sizes 8 16 32. */
24852 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
24853 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24854 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
24855 /* VMOVN. Types I16 I32 I64. */
24856 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
24857 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24858 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
24859 /* VQMOVUN. Types S16 S32 S64. */
24860 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
24861 /* VZIP / VUZP. Sizes 8 16 32. */
24862 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24863 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24864 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24865 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24866 /* VQABS / VQNEG. Types S8 S16 S32. */
24867 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24868 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24869 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24870 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24871 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
24872 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24873 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
24874 /* Reciprocal estimates. Types U32 F16 F32. */
24875 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24876 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
24877 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24878 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
24879 /* VCLS. Types S8 S16 S32. */
24880 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
24881 /* VCLZ. Types I8 I16 I32. */
24882 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
24883 /* VCNT. Size 8. */
24884 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
24885 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
24886 /* Two address, untyped. */
24887 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
24888 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
24889 /* VTRN. Sizes 8 16 32. */
24890 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
24891 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
24893 /* Table lookup. Size 8. */
24894 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24895 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24897 #undef THUMB_VARIANT
24898 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24900 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24902 /* Neon element/structure load/store. */
24903 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24904 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24905 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24906 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24907 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24908 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24909 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24910 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24912 #undef THUMB_VARIANT
24913 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
24915 #define ARM_VARIANT & fpu_vfp_ext_v3xd
24916 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
24917 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24918 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24919 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24920 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24921 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24922 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24923 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24924 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24926 #undef THUMB_VARIANT
24927 #define THUMB_VARIANT & fpu_vfp_ext_v3
24929 #define ARM_VARIANT & fpu_vfp_ext_v3
24931 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
24932 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24933 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24934 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24935 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24936 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24937 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24938 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24939 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24942 #define ARM_VARIANT & fpu_vfp_ext_fma
24943 #undef THUMB_VARIANT
24944 #define THUMB_VARIANT & fpu_vfp_ext_fma
24945 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
24946 VFP FMA variant; NEON and VFP FMA always includes the NEON
24947 FMA instructions. */
24948 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
24949 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
24951 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
24952 the v form should always be used. */
24953 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24954 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24955 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24956 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24957 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24958 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24960 #undef THUMB_VARIANT
24962 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
24964 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24965 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24966 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24967 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24968 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24969 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24970 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
24971 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
24974 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
24976 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
24977 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
24978 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
24979 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
24980 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
24981 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
24982 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
24983 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
24984 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
24985 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24986 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24987 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24988 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24989 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24990 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24991 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24992 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24993 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24994 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
24995 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
24996 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24997 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24998 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24999 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25000 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25001 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25002 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25003 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25004 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25005 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25006 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25007 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25008 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25009 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25010 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25011 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25012 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25013 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25014 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25015 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25016 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25017 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25018 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25019 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25020 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25021 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25022 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
25023 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25024 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25025 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25026 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25027 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25028 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25029 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25030 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25031 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25032 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25033 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25034 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25035 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25036 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25037 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25038 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25039 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25040 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25041 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25042 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25043 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25044 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25045 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25046 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25047 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25048 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25049 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25050 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25051 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25052 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25053 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25054 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25055 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25056 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25057 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25058 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25059 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25060 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25061 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25062 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25063 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25064 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
25065 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25066 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25067 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25068 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25069 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25070 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25071 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25072 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25073 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25074 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25075 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25076 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25077 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25078 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25079 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25080 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25081 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25082 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25083 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25084 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25085 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25086 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
25087 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25088 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25089 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25090 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25091 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25092 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25093 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25094 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25095 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25096 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25097 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25098 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25099 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25100 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25101 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25102 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25103 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25104 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25105 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25106 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25107 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25108 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25109 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25110 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25111 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25112 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25113 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25114 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25115 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25116 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25117 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25118 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25119 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25120 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25121 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25122 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25123 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25124 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25125 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25126 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25127 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25128 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25129 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25130 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25131 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25132 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25133 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25134 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25135 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25136 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25137 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
25140 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
25142 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
25143 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
25144 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
25145 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25146 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25147 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25148 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25149 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25150 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25151 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25152 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25153 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25154 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25155 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25156 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25157 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25158 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25159 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25160 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25161 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25162 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
25163 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25164 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25165 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25166 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25167 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25168 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25169 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25170 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25171 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25172 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25173 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25174 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25175 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25176 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25177 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25178 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25179 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25180 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25181 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25182 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25183 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25184 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25185 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25186 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25187 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25188 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25189 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25190 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25191 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25192 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25193 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25194 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25195 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25196 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25197 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25198 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25201 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25203 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25204 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25205 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25206 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25207 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25208 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25209 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25210 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25211 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
25212 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
25213 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
25214 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
25215 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
25216 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
25217 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
25218 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
25219 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
25220 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
25221 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
25222 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
25223 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
25224 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
25225 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
25226 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
25227 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
25228 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
25229 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
25230 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
25231 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
25232 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
25233 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
25234 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
25235 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
25236 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
25237 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
25238 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
25239 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
25240 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
25241 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
25242 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25243 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25244 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25245 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25246 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25247 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25248 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25249 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25250 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25251 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25252 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25253 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25254 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25255 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25256 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25257 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25258 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25259 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25260 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25261 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25262 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25263 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25264 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25265 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25266 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25267 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25268 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25269 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25270 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25271 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25272 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25273 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25274 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25275 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25276 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25277 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25278 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25280 /* ARMv8.5-A instructions. */
25282 #define ARM_VARIANT & arm_ext_sb
25283 #undef THUMB_VARIANT
25284 #define THUMB_VARIANT & arm_ext_sb
25285 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25288 #define ARM_VARIANT & arm_ext_predres
25289 #undef THUMB_VARIANT
25290 #define THUMB_VARIANT & arm_ext_predres
25291 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25292 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25293 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25295 /* ARMv8-M instructions. */
25297 #define ARM_VARIANT NULL
25298 #undef THUMB_VARIANT
25299 #define THUMB_VARIANT & arm_ext_v8m
25300 ToU("sg", e97fe97f
, 0, (), noargs
),
25301 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25302 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25303 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25304 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25305 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25306 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25308 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25309 instructions behave as nop if no VFP is present. */
25310 #undef THUMB_VARIANT
25311 #define THUMB_VARIANT & arm_ext_v8m_main
25312 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25313 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25315 /* Armv8.1-M Mainline instructions. */
25316 #undef THUMB_VARIANT
25317 #define THUMB_VARIANT & arm_ext_v8_1m_main
25318 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25319 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25320 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25321 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25322 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
25323 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
25324 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25325 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25326 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25328 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25329 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25330 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25331 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25332 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25334 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25335 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25336 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25338 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25339 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25341 #undef THUMB_VARIANT
25342 #define THUMB_VARIANT & mve_ext
25343 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25344 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25345 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25346 ToC("uqrshll", ea51010d
, 3, (RRe
, RRo
, RRnpcsp
), mve_scalar_shift
),
25347 ToC("sqrshrl", ea51012d
, 3, (RRe
, RRo
, RRnpcsp
), mve_scalar_shift
),
25348 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25349 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25350 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25351 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25352 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25353 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25354 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25355 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25356 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25357 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25359 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25360 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25361 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25362 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25363 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25364 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25365 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25366 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25367 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25368 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25369 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25370 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25371 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25372 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25373 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25375 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25376 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25377 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25378 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25379 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25380 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25381 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25382 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25383 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25384 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25385 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25386 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25387 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25388 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25389 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25391 /* MVE and MVE FP only. */
25392 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25393 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25394 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25395 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25396 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25397 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25398 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25399 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25400 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25401 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25402 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25403 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25404 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25405 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25406 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25407 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25408 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25410 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25411 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25412 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25413 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25414 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25415 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25416 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25417 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25418 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25419 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25420 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25421 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25422 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25423 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25424 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25425 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25426 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25427 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25428 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25429 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25431 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25432 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25433 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25434 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25435 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25436 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25437 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25438 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25439 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25440 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25441 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25442 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25443 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25444 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25445 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25446 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25447 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25449 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25450 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25451 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25452 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25453 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25454 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25455 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25456 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25457 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25458 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25459 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25460 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25461 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25462 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25463 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25464 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25465 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25466 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25467 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25468 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25470 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25471 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25472 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25473 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25474 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25476 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25477 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25478 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25479 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25480 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25481 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25482 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25483 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25484 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25485 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25486 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25487 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25488 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25489 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25490 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25491 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25492 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25494 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25495 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25496 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25497 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25498 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25499 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25500 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25501 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25502 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25503 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25504 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25505 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25507 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25508 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25509 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25511 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
25512 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
25513 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
25514 toU("lctp", _lctp
, 0, (), t_loloop
),
25516 #undef THUMB_VARIANT
25517 #define THUMB_VARIANT & mve_fp_ext
25518 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25519 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25520 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25521 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25522 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25523 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25524 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25525 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25528 #define ARM_VARIANT & fpu_vfp_ext_v1
25529 #undef THUMB_VARIANT
25530 #define THUMB_VARIANT & arm_ext_v6t2
25531 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25532 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25534 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25537 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25539 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25540 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25541 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25542 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25544 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25545 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25546 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25548 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25549 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25551 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25552 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25554 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25555 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25558 #define ARM_VARIANT & fpu_vfp_ext_v2
25560 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
25561 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
25562 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
25563 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
25566 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25567 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
25568 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
25569 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
25570 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
25571 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25572 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25575 #define ARM_VARIANT & fpu_neon_ext_v1
25576 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25577 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
25578 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25579 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25580 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25581 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25582 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25583 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25584 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
25585 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
25586 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
25587 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
25588 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25589 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
25590 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25591 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25592 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25593 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25594 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25595 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
25596 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25597 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25598 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
25599 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25600 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25601 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25602 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25603 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25604 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25605 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
25606 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
25607 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25608 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25609 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25610 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
25611 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
25612 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
25615 #define ARM_VARIANT & arm_ext_v8_3
25616 #undef THUMB_VARIANT
25617 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25618 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
25619 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
25622 #undef THUMB_VARIANT
25654 /* MD interface: bits in the object file. */
25656 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25657 for use in the a.out file, and stores them in the array pointed to by buf.
25658 This knows about the endian-ness of the target machine and does
25659 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25660 2 (short) and 4 (long) Floating numbers are put out as a series of
25661 LITTLENUMS (shorts, here at least). */
25664 md_number_to_chars (char * buf
, valueT val
, int n
)
25666 if (target_big_endian
)
25667 number_to_chars_bigendian (buf
, val
, n
);
25669 number_to_chars_littleendian (buf
, val
, n
);
25673 md_chars_to_number (char * buf
, int n
)
25676 unsigned char * where
= (unsigned char *) buf
;
25678 if (target_big_endian
)
25683 result
|= (*where
++ & 255);
25691 result
|= (where
[n
] & 255);
25698 /* MD interface: Sections. */
25700 /* Calculate the maximum variable size (i.e., excluding fr_fix)
25701 that an rs_machine_dependent frag may reach. */
25704 arm_frag_max_var (fragS
*fragp
)
25706 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25707 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25709 Note that we generate relaxable instructions even for cases that don't
25710 really need it, like an immediate that's a trivial constant. So we're
25711 overestimating the instruction size for some of those cases. Rather
25712 than putting more intelligence here, it would probably be better to
25713 avoid generating a relaxation frag in the first place when it can be
25714 determined up front that a short instruction will suffice. */
25716 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
25720 /* Estimate the size of a frag before relaxing. Assume everything fits in
25724 md_estimate_size_before_relax (fragS
* fragp
,
25725 segT segtype ATTRIBUTE_UNUSED
)
25731 /* Convert a machine dependent frag. */
25734 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
25736 unsigned long insn
;
25737 unsigned long old_op
;
25745 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25747 old_op
= bfd_get_16(abfd
, buf
);
25748 if (fragp
->fr_symbol
)
25750 exp
.X_op
= O_symbol
;
25751 exp
.X_add_symbol
= fragp
->fr_symbol
;
25755 exp
.X_op
= O_constant
;
25757 exp
.X_add_number
= fragp
->fr_offset
;
25758 opcode
= fragp
->fr_subtype
;
25761 case T_MNEM_ldr_pc
:
25762 case T_MNEM_ldr_pc2
:
25763 case T_MNEM_ldr_sp
:
25764 case T_MNEM_str_sp
:
25771 if (fragp
->fr_var
== 4)
25773 insn
= THUMB_OP32 (opcode
);
25774 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
25776 insn
|= (old_op
& 0x700) << 4;
25780 insn
|= (old_op
& 7) << 12;
25781 insn
|= (old_op
& 0x38) << 13;
25783 insn
|= 0x00000c00;
25784 put_thumb32_insn (buf
, insn
);
25785 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
25789 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
25791 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
25794 if (fragp
->fr_var
== 4)
25796 insn
= THUMB_OP32 (opcode
);
25797 insn
|= (old_op
& 0xf0) << 4;
25798 put_thumb32_insn (buf
, insn
);
25799 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
25803 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25804 exp
.X_add_number
-= 4;
25812 if (fragp
->fr_var
== 4)
25814 int r0off
= (opcode
== T_MNEM_mov
25815 || opcode
== T_MNEM_movs
) ? 0 : 8;
25816 insn
= THUMB_OP32 (opcode
);
25817 insn
= (insn
& 0xe1ffffff) | 0x10000000;
25818 insn
|= (old_op
& 0x700) << r0off
;
25819 put_thumb32_insn (buf
, insn
);
25820 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25824 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
25829 if (fragp
->fr_var
== 4)
25831 insn
= THUMB_OP32(opcode
);
25832 put_thumb32_insn (buf
, insn
);
25833 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
25836 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
25840 if (fragp
->fr_var
== 4)
25842 insn
= THUMB_OP32(opcode
);
25843 insn
|= (old_op
& 0xf00) << 14;
25844 put_thumb32_insn (buf
, insn
);
25845 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
25848 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
25851 case T_MNEM_add_sp
:
25852 case T_MNEM_add_pc
:
25853 case T_MNEM_inc_sp
:
25854 case T_MNEM_dec_sp
:
25855 if (fragp
->fr_var
== 4)
25857 /* ??? Choose between add and addw. */
25858 insn
= THUMB_OP32 (opcode
);
25859 insn
|= (old_op
& 0xf0) << 4;
25860 put_thumb32_insn (buf
, insn
);
25861 if (opcode
== T_MNEM_add_pc
)
25862 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
25864 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25867 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25875 if (fragp
->fr_var
== 4)
25877 insn
= THUMB_OP32 (opcode
);
25878 insn
|= (old_op
& 0xf0) << 4;
25879 insn
|= (old_op
& 0xf) << 16;
25880 put_thumb32_insn (buf
, insn
);
25881 if (insn
& (1 << 20))
25882 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25884 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25887 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25893 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
25894 (enum bfd_reloc_code_real
) reloc_type
);
25895 fixp
->fx_file
= fragp
->fr_file
;
25896 fixp
->fx_line
= fragp
->fr_line
;
25897 fragp
->fr_fix
+= fragp
->fr_var
;
25899 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25900 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
25901 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
25902 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
25905 /* Return the size of a relaxable immediate operand instruction.
25906 SHIFT and SIZE specify the form of the allowable immediate. */
25908 relax_immediate (fragS
*fragp
, int size
, int shift
)
25914 /* ??? Should be able to do better than this. */
25915 if (fragp
->fr_symbol
)
25918 low
= (1 << shift
) - 1;
25919 mask
= (1 << (shift
+ size
)) - (1 << shift
);
25920 offset
= fragp
->fr_offset
;
25921 /* Force misaligned offsets to 32-bit variant. */
25924 if (offset
& ~mask
)
25929 /* Get the address of a symbol during relaxation. */
25931 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
25937 sym
= fragp
->fr_symbol
;
25938 sym_frag
= symbol_get_frag (sym
);
25939 know (S_GET_SEGMENT (sym
) != absolute_section
25940 || sym_frag
== &zero_address_frag
);
25941 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
25943 /* If frag has yet to be reached on this pass, assume it will
25944 move by STRETCH just as we did. If this is not so, it will
25945 be because some frag between grows, and that will force
25949 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
25953 /* Adjust stretch for any alignment frag. Note that if have
25954 been expanding the earlier code, the symbol may be
25955 defined in what appears to be an earlier frag. FIXME:
25956 This doesn't handle the fr_subtype field, which specifies
25957 a maximum number of bytes to skip when doing an
25959 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
25961 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
25964 stretch
= - ((- stretch
)
25965 & ~ ((1 << (int) f
->fr_offset
) - 1));
25967 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
25979 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
25982 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
25987 /* Assume worst case for symbols not known to be in the same section. */
25988 if (fragp
->fr_symbol
== NULL
25989 || !S_IS_DEFINED (fragp
->fr_symbol
)
25990 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25991 || S_IS_WEAK (fragp
->fr_symbol
))
25994 val
= relaxed_symbol_addr (fragp
, stretch
);
25995 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
25996 addr
= (addr
+ 4) & ~3;
25997 /* Force misaligned targets to 32-bit variant. */
26001 if (val
< 0 || val
> 1020)
26006 /* Return the size of a relaxable add/sub immediate instruction. */
26008 relax_addsub (fragS
*fragp
, asection
*sec
)
26013 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26014 op
= bfd_get_16(sec
->owner
, buf
);
26015 if ((op
& 0xf) == ((op
>> 4) & 0xf))
26016 return relax_immediate (fragp
, 8, 0);
26018 return relax_immediate (fragp
, 3, 0);
26021 /* Return TRUE iff the definition of symbol S could be pre-empted
26022 (overridden) at link or load time. */
26024 symbol_preemptible (symbolS
*s
)
26026 /* Weak symbols can always be pre-empted. */
26030 /* Non-global symbols cannot be pre-empted. */
26031 if (! S_IS_EXTERNAL (s
))
26035 /* In ELF, a global symbol can be marked protected, or private. In that
26036 case it can't be pre-empted (other definitions in the same link unit
26037 would violate the ODR). */
26038 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
26042 /* Other global symbols might be pre-empted. */
26046 /* Return the size of a relaxable branch instruction. BITS is the
26047 size of the offset field in the narrow instruction. */
26050 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
26056 /* Assume worst case for symbols not known to be in the same section. */
26057 if (!S_IS_DEFINED (fragp
->fr_symbol
)
26058 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26059 || S_IS_WEAK (fragp
->fr_symbol
))
26063 /* A branch to a function in ARM state will require interworking. */
26064 if (S_IS_DEFINED (fragp
->fr_symbol
)
26065 && ARM_IS_FUNC (fragp
->fr_symbol
))
26069 if (symbol_preemptible (fragp
->fr_symbol
))
26072 val
= relaxed_symbol_addr (fragp
, stretch
);
26073 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
26076 /* Offset is a signed value *2 */
26078 if (val
>= limit
|| val
< -limit
)
26084 /* Relax a machine dependent frag. This returns the amount by which
26085 the current size of the frag should change. */
26088 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
26093 oldsize
= fragp
->fr_var
;
26094 switch (fragp
->fr_subtype
)
26096 case T_MNEM_ldr_pc2
:
26097 newsize
= relax_adr (fragp
, sec
, stretch
);
26099 case T_MNEM_ldr_pc
:
26100 case T_MNEM_ldr_sp
:
26101 case T_MNEM_str_sp
:
26102 newsize
= relax_immediate (fragp
, 8, 2);
26106 newsize
= relax_immediate (fragp
, 5, 2);
26110 newsize
= relax_immediate (fragp
, 5, 1);
26114 newsize
= relax_immediate (fragp
, 5, 0);
26117 newsize
= relax_adr (fragp
, sec
, stretch
);
26123 newsize
= relax_immediate (fragp
, 8, 0);
26126 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
26129 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
26131 case T_MNEM_add_sp
:
26132 case T_MNEM_add_pc
:
26133 newsize
= relax_immediate (fragp
, 8, 2);
26135 case T_MNEM_inc_sp
:
26136 case T_MNEM_dec_sp
:
26137 newsize
= relax_immediate (fragp
, 7, 2);
26143 newsize
= relax_addsub (fragp
, sec
);
26149 fragp
->fr_var
= newsize
;
26150 /* Freeze wide instructions that are at or before the same location as
26151 in the previous pass. This avoids infinite loops.
26152 Don't freeze them unconditionally because targets may be artificially
26153 misaligned by the expansion of preceding frags. */
26154 if (stretch
<= 0 && newsize
> 2)
26156 md_convert_frag (sec
->owner
, sec
, fragp
);
26160 return newsize
- oldsize
;
26163 /* Round up a section size to the appropriate boundary. */
26166 md_section_align (segT segment ATTRIBUTE_UNUSED
,
26172 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26173 of an rs_align_code fragment. */
26176 arm_handle_align (fragS
* fragP
)
26178 static unsigned char const arm_noop
[2][2][4] =
26181 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26182 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26185 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26186 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26189 static unsigned char const thumb_noop
[2][2][2] =
26192 {0xc0, 0x46}, /* LE */
26193 {0x46, 0xc0}, /* BE */
26196 {0x00, 0xbf}, /* LE */
26197 {0xbf, 0x00} /* BE */
26200 static unsigned char const wide_thumb_noop
[2][4] =
26201 { /* Wide Thumb-2 */
26202 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26203 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26206 unsigned bytes
, fix
, noop_size
;
26208 const unsigned char * noop
;
26209 const unsigned char *narrow_noop
= NULL
;
26214 if (fragP
->fr_type
!= rs_align_code
)
26217 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
26218 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
26221 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26222 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
26224 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
26226 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
26228 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26229 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
26231 narrow_noop
= thumb_noop
[1][target_big_endian
];
26232 noop
= wide_thumb_noop
[target_big_endian
];
26235 noop
= thumb_noop
[0][target_big_endian
];
26243 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26244 ? selected_cpu
: arm_arch_none
,
26246 [target_big_endian
];
26253 fragP
->fr_var
= noop_size
;
26255 if (bytes
& (noop_size
- 1))
26257 fix
= bytes
& (noop_size
- 1);
26259 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
26261 memset (p
, 0, fix
);
26268 if (bytes
& noop_size
)
26270 /* Insert a narrow noop. */
26271 memcpy (p
, narrow_noop
, noop_size
);
26273 bytes
-= noop_size
;
26277 /* Use wide noops for the remainder */
26281 while (bytes
>= noop_size
)
26283 memcpy (p
, noop
, noop_size
);
26285 bytes
-= noop_size
;
26289 fragP
->fr_fix
+= fix
;
26292 /* Called from md_do_align. Used to create an alignment
26293 frag in a code section. */
26296 arm_frag_align_code (int n
, int max
)
26300 /* We assume that there will never be a requirement
26301 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26302 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26307 _("alignments greater than %d bytes not supported in .text sections."),
26308 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26309 as_fatal ("%s", err_msg
);
26312 p
= frag_var (rs_align_code
,
26313 MAX_MEM_FOR_RS_ALIGN_CODE
,
26315 (relax_substateT
) max
,
26322 /* Perform target specific initialisation of a frag.
26323 Note - despite the name this initialisation is not done when the frag
26324 is created, but only when its type is assigned. A frag can be created
26325 and used a long time before its type is set, so beware of assuming that
26326 this initialisation is performed first. */
26330 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26332 /* Record whether this frag is in an ARM or a THUMB area. */
26333 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26336 #else /* OBJ_ELF is defined. */
26338 arm_init_frag (fragS
* fragP
, int max_chars
)
26340 bfd_boolean frag_thumb_mode
;
26342 /* If the current ARM vs THUMB mode has not already
26343 been recorded into this frag then do so now. */
26344 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26345 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26347 /* PR 21809: Do not set a mapping state for debug sections
26348 - it just confuses other tools. */
26349 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
26352 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26354 /* Record a mapping symbol for alignment frags. We will delete this
26355 later if the alignment ends up empty. */
26356 switch (fragP
->fr_type
)
26359 case rs_align_test
:
26361 mapping_state_2 (MAP_DATA
, max_chars
);
26363 case rs_align_code
:
26364 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26371 /* When we change sections we need to issue a new mapping symbol. */
26374 arm_elf_change_section (void)
26376 /* Link an unlinked unwind index table section to the .text section. */
26377 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26378 && elf_linked_to_section (now_seg
) == NULL
)
26379 elf_linked_to_section (now_seg
) = text_section
;
26383 arm_elf_section_type (const char * str
, size_t len
)
26385 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26386 return SHT_ARM_EXIDX
;
26391 /* Code to deal with unwinding tables. */
26393 static void add_unwind_adjustsp (offsetT
);
26395 /* Generate any deferred unwind frame offset. */
26398 flush_pending_unwind (void)
26402 offset
= unwind
.pending_offset
;
26403 unwind
.pending_offset
= 0;
26405 add_unwind_adjustsp (offset
);
26408 /* Add an opcode to this list for this function. Two-byte opcodes should
26409 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26413 add_unwind_opcode (valueT op
, int length
)
26415 /* Add any deferred stack adjustment. */
26416 if (unwind
.pending_offset
)
26417 flush_pending_unwind ();
26419 unwind
.sp_restored
= 0;
26421 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26423 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26424 if (unwind
.opcodes
)
26425 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26426 unwind
.opcode_alloc
);
26428 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26433 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26435 unwind
.opcode_count
++;
26439 /* Add unwind opcodes to adjust the stack pointer. */
26442 add_unwind_adjustsp (offsetT offset
)
26446 if (offset
> 0x200)
26448 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26453 /* Long form: 0xb2, uleb128. */
26454 /* This might not fit in a word so add the individual bytes,
26455 remembering the list is built in reverse order. */
26456 o
= (valueT
) ((offset
- 0x204) >> 2);
26458 add_unwind_opcode (0, 1);
26460 /* Calculate the uleb128 encoding of the offset. */
26464 bytes
[n
] = o
& 0x7f;
26470 /* Add the insn. */
26472 add_unwind_opcode (bytes
[n
- 1], 1);
26473 add_unwind_opcode (0xb2, 1);
26475 else if (offset
> 0x100)
26477 /* Two short opcodes. */
26478 add_unwind_opcode (0x3f, 1);
26479 op
= (offset
- 0x104) >> 2;
26480 add_unwind_opcode (op
, 1);
26482 else if (offset
> 0)
26484 /* Short opcode. */
26485 op
= (offset
- 4) >> 2;
26486 add_unwind_opcode (op
, 1);
26488 else if (offset
< 0)
26491 while (offset
> 0x100)
26493 add_unwind_opcode (0x7f, 1);
26496 op
= ((offset
- 4) >> 2) | 0x40;
26497 add_unwind_opcode (op
, 1);
26501 /* Finish the list of unwind opcodes for this function. */
26504 finish_unwind_opcodes (void)
26508 if (unwind
.fp_used
)
26510 /* Adjust sp as necessary. */
26511 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26512 flush_pending_unwind ();
26514 /* After restoring sp from the frame pointer. */
26515 op
= 0x90 | unwind
.fp_reg
;
26516 add_unwind_opcode (op
, 1);
26519 flush_pending_unwind ();
26523 /* Start an exception table entry. If idx is nonzero this is an index table
26527 start_unwind_section (const segT text_seg
, int idx
)
26529 const char * text_name
;
26530 const char * prefix
;
26531 const char * prefix_once
;
26532 const char * group_name
;
26540 prefix
= ELF_STRING_ARM_unwind
;
26541 prefix_once
= ELF_STRING_ARM_unwind_once
;
26542 type
= SHT_ARM_EXIDX
;
26546 prefix
= ELF_STRING_ARM_unwind_info
;
26547 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
26548 type
= SHT_PROGBITS
;
26551 text_name
= segment_name (text_seg
);
26552 if (streq (text_name
, ".text"))
26555 if (strncmp (text_name
, ".gnu.linkonce.t.",
26556 strlen (".gnu.linkonce.t.")) == 0)
26558 prefix
= prefix_once
;
26559 text_name
+= strlen (".gnu.linkonce.t.");
26562 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
26568 /* Handle COMDAT group. */
26569 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
26571 group_name
= elf_group_name (text_seg
);
26572 if (group_name
== NULL
)
26574 as_bad (_("Group section `%s' has no group signature"),
26575 segment_name (text_seg
));
26576 ignore_rest_of_line ();
26579 flags
|= SHF_GROUP
;
26583 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
26586 /* Set the section link for index tables. */
26588 elf_linked_to_section (now_seg
) = text_seg
;
26592 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26593 personality routine data. Returns zero, or the index table value for
26594 an inline entry. */
26597 create_unwind_entry (int have_data
)
26602 /* The current word of data. */
26604 /* The number of bytes left in this word. */
26607 finish_unwind_opcodes ();
26609 /* Remember the current text section. */
26610 unwind
.saved_seg
= now_seg
;
26611 unwind
.saved_subseg
= now_subseg
;
26613 start_unwind_section (now_seg
, 0);
26615 if (unwind
.personality_routine
== NULL
)
26617 if (unwind
.personality_index
== -2)
26620 as_bad (_("handlerdata in cantunwind frame"));
26621 return 1; /* EXIDX_CANTUNWIND. */
26624 /* Use a default personality routine if none is specified. */
26625 if (unwind
.personality_index
== -1)
26627 if (unwind
.opcode_count
> 3)
26628 unwind
.personality_index
= 1;
26630 unwind
.personality_index
= 0;
26633 /* Space for the personality routine entry. */
26634 if (unwind
.personality_index
== 0)
26636 if (unwind
.opcode_count
> 3)
26637 as_bad (_("too many unwind opcodes for personality routine 0"));
26641 /* All the data is inline in the index table. */
26644 while (unwind
.opcode_count
> 0)
26646 unwind
.opcode_count
--;
26647 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26651 /* Pad with "finish" opcodes. */
26653 data
= (data
<< 8) | 0xb0;
26660 /* We get two opcodes "free" in the first word. */
26661 size
= unwind
.opcode_count
- 2;
26665 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26666 if (unwind
.personality_index
!= -1)
26668 as_bad (_("attempt to recreate an unwind entry"));
26672 /* An extra byte is required for the opcode count. */
26673 size
= unwind
.opcode_count
+ 1;
26676 size
= (size
+ 3) >> 2;
26678 as_bad (_("too many unwind opcodes"));
26680 frag_align (2, 0, 0);
26681 record_alignment (now_seg
, 2);
26682 unwind
.table_entry
= expr_build_dot ();
26684 /* Allocate the table entry. */
26685 ptr
= frag_more ((size
<< 2) + 4);
26686 /* PR 13449: Zero the table entries in case some of them are not used. */
26687 memset (ptr
, 0, (size
<< 2) + 4);
26688 where
= frag_now_fix () - ((size
<< 2) + 4);
26690 switch (unwind
.personality_index
)
26693 /* ??? Should this be a PLT generating relocation? */
26694 /* Custom personality routine. */
26695 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
26696 BFD_RELOC_ARM_PREL31
);
26701 /* Set the first byte to the number of additional words. */
26702 data
= size
> 0 ? size
- 1 : 0;
26706 /* ABI defined personality routines. */
26708 /* Three opcodes bytes are packed into the first word. */
26715 /* The size and first two opcode bytes go in the first word. */
26716 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
26721 /* Should never happen. */
26725 /* Pack the opcodes into words (MSB first), reversing the list at the same
26727 while (unwind
.opcode_count
> 0)
26731 md_number_to_chars (ptr
, data
, 4);
26736 unwind
.opcode_count
--;
26738 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26741 /* Finish off the last word. */
26744 /* Pad with "finish" opcodes. */
26746 data
= (data
<< 8) | 0xb0;
26748 md_number_to_chars (ptr
, data
, 4);
26753 /* Add an empty descriptor if there is no user-specified data. */
26754 ptr
= frag_more (4);
26755 md_number_to_chars (ptr
, 0, 4);
26762 /* Initialize the DWARF-2 unwind information for this procedure. */
26765 tc_arm_frame_initial_instructions (void)
26767 cfi_add_CFA_def_cfa (REG_SP
, 0);
26769 #endif /* OBJ_ELF */
26771 /* Convert REGNAME to a DWARF-2 register number. */
26774 tc_arm_regname_to_dw2regnum (char *regname
)
26776 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
26780 /* PR 16694: Allow VFP registers as well. */
26781 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
26785 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
26794 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
26798 exp
.X_op
= O_secrel
;
26799 exp
.X_add_symbol
= symbol
;
26800 exp
.X_add_number
= 0;
26801 emit_expr (&exp
, size
);
26805 /* MD interface: Symbol and relocation handling. */
26807 /* Return the address within the segment that a PC-relative fixup is
26808 relative to. For ARM, PC-relative fixups applied to instructions
26809 are generally relative to the location of the fixup plus 8 bytes.
26810 Thumb branches are offset by 4, and Thumb loads relative to PC
26811 require special handling. */
26814 md_pcrel_from_section (fixS
* fixP
, segT seg
)
26816 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26818 /* If this is pc-relative and we are going to emit a relocation
26819 then we just want to put out any pipeline compensation that the linker
26820 will need. Otherwise we want to use the calculated base.
26821 For WinCE we skip the bias for externals as well, since this
26822 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26824 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26825 || (arm_force_relocation (fixP
)
26827 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
26833 switch (fixP
->fx_r_type
)
26835 /* PC relative addressing on the Thumb is slightly odd as the
26836 bottom two bits of the PC are forced to zero for the
26837 calculation. This happens *after* application of the
26838 pipeline offset. However, Thumb adrl already adjusts for
26839 this, so we need not do it again. */
26840 case BFD_RELOC_ARM_THUMB_ADD
:
26843 case BFD_RELOC_ARM_THUMB_OFFSET
:
26844 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26845 case BFD_RELOC_ARM_T32_ADD_PC12
:
26846 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26847 return (base
+ 4) & ~3;
26849 /* Thumb branches are simply offset by +4. */
26850 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26851 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
26852 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
26853 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
26854 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26855 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26856 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
26857 case BFD_RELOC_ARM_THUMB_BF17
:
26858 case BFD_RELOC_ARM_THUMB_BF19
:
26859 case BFD_RELOC_ARM_THUMB_BF13
:
26860 case BFD_RELOC_ARM_THUMB_LOOP12
:
26863 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26865 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26866 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26867 && ARM_IS_FUNC (fixP
->fx_addsy
)
26868 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26869 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26872 /* BLX is like branches above, but forces the low two bits of PC to
26874 case BFD_RELOC_THUMB_PCREL_BLX
:
26876 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26877 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26878 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26879 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26880 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26881 return (base
+ 4) & ~3;
26883 /* ARM mode branches are offset by +8. However, the Windows CE
26884 loader expects the relocation not to take this into account. */
26885 case BFD_RELOC_ARM_PCREL_BLX
:
26887 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26888 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26889 && ARM_IS_FUNC (fixP
->fx_addsy
)
26890 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26891 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26894 case BFD_RELOC_ARM_PCREL_CALL
:
26896 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26897 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26898 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26899 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26900 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26903 case BFD_RELOC_ARM_PCREL_BRANCH
:
26904 case BFD_RELOC_ARM_PCREL_JUMP
:
26905 case BFD_RELOC_ARM_PLT32
:
26907 /* When handling fixups immediately, because we have already
26908 discovered the value of a symbol, or the address of the frag involved
26909 we must account for the offset by +8, as the OS loader will never see the reloc.
26910 see fixup_segment() in write.c
26911 The S_IS_EXTERNAL test handles the case of global symbols.
26912 Those need the calculated base, not just the pipe compensation the linker will need. */
26914 && fixP
->fx_addsy
!= NULL
26915 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26916 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
26924 /* ARM mode loads relative to PC are also offset by +8. Unlike
26925 branches, the Windows CE loader *does* expect the relocation
26926 to take this into account. */
26927 case BFD_RELOC_ARM_OFFSET_IMM
:
26928 case BFD_RELOC_ARM_OFFSET_IMM8
:
26929 case BFD_RELOC_ARM_HWLITERAL
:
26930 case BFD_RELOC_ARM_LITERAL
:
26931 case BFD_RELOC_ARM_CP_OFF_IMM
:
26935 /* Other PC-relative relocations are un-offset. */
26941 static bfd_boolean flag_warn_syms
= TRUE
;
26944 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
26946 /* PR 18347 - Warn if the user attempts to create a symbol with the same
26947 name as an ARM instruction. Whilst strictly speaking it is allowed, it
26948 does mean that the resulting code might be very confusing to the reader.
26949 Also this warning can be triggered if the user omits an operand before
26950 an immediate address, eg:
26954 GAS treats this as an assignment of the value of the symbol foo to a
26955 symbol LDR, and so (without this code) it will not issue any kind of
26956 warning or error message.
26958 Note - ARM instructions are case-insensitive but the strings in the hash
26959 table are all stored in lower case, so we must first ensure that name is
26961 if (flag_warn_syms
&& arm_ops_hsh
)
26963 char * nbuf
= strdup (name
);
26966 for (p
= nbuf
; *p
; p
++)
26968 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
26970 static struct hash_control
* already_warned
= NULL
;
26972 if (already_warned
== NULL
)
26973 already_warned
= hash_new ();
26974 /* Only warn about the symbol once. To keep the code
26975 simple we let hash_insert do the lookup for us. */
26976 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
26977 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
26986 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
26987 Otherwise we have no need to default values of symbols. */
26990 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
26993 if (name
[0] == '_' && name
[1] == 'G'
26994 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
26998 if (symbol_find (name
))
26999 as_bad (_("GOT already in the symbol table"));
27001 GOT_symbol
= symbol_new (name
, undefined_section
,
27002 (valueT
) 0, & zero_address_frag
);
27012 /* Subroutine of md_apply_fix. Check to see if an immediate can be
27013 computed as two separate immediate values, added together. We
27014 already know that this value cannot be computed by just one ARM
27017 static unsigned int
27018 validate_immediate_twopart (unsigned int val
,
27019 unsigned int * highpart
)
27024 for (i
= 0; i
< 32; i
+= 2)
27025 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
27031 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
27033 else if (a
& 0xff0000)
27035 if (a
& 0xff000000)
27037 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
27041 gas_assert (a
& 0xff000000);
27042 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
27045 return (a
& 0xff) | (i
<< 7);
27052 validate_offset_imm (unsigned int val
, int hwse
)
27054 if ((hwse
&& val
> 255) || val
> 4095)
27059 /* Subroutine of md_apply_fix. Do those data_ops which can take a
27060 negative immediate constant by altering the instruction. A bit of
27065 by inverting the second operand, and
27068 by negating the second operand. */
27071 negate_data_op (unsigned long * instruction
,
27072 unsigned long value
)
27075 unsigned long negated
, inverted
;
27077 negated
= encode_arm_immediate (-value
);
27078 inverted
= encode_arm_immediate (~value
);
27080 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
27083 /* First negates. */
27084 case OPCODE_SUB
: /* ADD <-> SUB */
27085 new_inst
= OPCODE_ADD
;
27090 new_inst
= OPCODE_SUB
;
27094 case OPCODE_CMP
: /* CMP <-> CMN */
27095 new_inst
= OPCODE_CMN
;
27100 new_inst
= OPCODE_CMP
;
27104 /* Now Inverted ops. */
27105 case OPCODE_MOV
: /* MOV <-> MVN */
27106 new_inst
= OPCODE_MVN
;
27111 new_inst
= OPCODE_MOV
;
27115 case OPCODE_AND
: /* AND <-> BIC */
27116 new_inst
= OPCODE_BIC
;
27121 new_inst
= OPCODE_AND
;
27125 case OPCODE_ADC
: /* ADC <-> SBC */
27126 new_inst
= OPCODE_SBC
;
27131 new_inst
= OPCODE_ADC
;
27135 /* We cannot do anything. */
27140 if (value
== (unsigned) FAIL
)
27143 *instruction
&= OPCODE_MASK
;
27144 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
27148 /* Like negate_data_op, but for Thumb-2. */
27150 static unsigned int
27151 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
27155 unsigned int negated
, inverted
;
27157 negated
= encode_thumb32_immediate (-value
);
27158 inverted
= encode_thumb32_immediate (~value
);
27160 rd
= (*instruction
>> 8) & 0xf;
27161 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
27164 /* ADD <-> SUB. Includes CMP <-> CMN. */
27165 case T2_OPCODE_SUB
:
27166 new_inst
= T2_OPCODE_ADD
;
27170 case T2_OPCODE_ADD
:
27171 new_inst
= T2_OPCODE_SUB
;
27175 /* ORR <-> ORN. Includes MOV <-> MVN. */
27176 case T2_OPCODE_ORR
:
27177 new_inst
= T2_OPCODE_ORN
;
27181 case T2_OPCODE_ORN
:
27182 new_inst
= T2_OPCODE_ORR
;
27186 /* AND <-> BIC. TST has no inverted equivalent. */
27187 case T2_OPCODE_AND
:
27188 new_inst
= T2_OPCODE_BIC
;
27195 case T2_OPCODE_BIC
:
27196 new_inst
= T2_OPCODE_AND
;
27201 case T2_OPCODE_ADC
:
27202 new_inst
= T2_OPCODE_SBC
;
27206 case T2_OPCODE_SBC
:
27207 new_inst
= T2_OPCODE_ADC
;
27211 /* We cannot do anything. */
27216 if (value
== (unsigned int)FAIL
)
27219 *instruction
&= T2_OPCODE_MASK
;
27220 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
27224 /* Read a 32-bit thumb instruction from buf. */
27226 static unsigned long
27227 get_thumb32_insn (char * buf
)
27229 unsigned long insn
;
27230 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
27231 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27236 /* We usually want to set the low bit on the address of thumb function
27237 symbols. In particular .word foo - . should have the low bit set.
27238 Generic code tries to fold the difference of two symbols to
27239 a constant. Prevent this and force a relocation when the first symbols
27240 is a thumb function. */
27243 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
27245 if (op
== O_subtract
27246 && l
->X_op
== O_symbol
27247 && r
->X_op
== O_symbol
27248 && THUMB_IS_FUNC (l
->X_add_symbol
))
27250 l
->X_op
= O_subtract
;
27251 l
->X_op_symbol
= r
->X_add_symbol
;
27252 l
->X_add_number
-= r
->X_add_number
;
27256 /* Process as normal. */
27260 /* Encode Thumb2 unconditional branches and calls. The encoding
27261 for the 2 are identical for the immediate values. */
27264 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
27266 #define T2I1I2MASK ((1 << 13) | (1 << 11))
27269 addressT S
, I1
, I2
, lo
, hi
;
27271 S
= (value
>> 24) & 0x01;
27272 I1
= (value
>> 23) & 0x01;
27273 I2
= (value
>> 22) & 0x01;
27274 hi
= (value
>> 12) & 0x3ff;
27275 lo
= (value
>> 1) & 0x7ff;
27276 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27277 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27278 newval
|= (S
<< 10) | hi
;
27279 newval2
&= ~T2I1I2MASK
;
27280 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27281 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27282 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27286 md_apply_fix (fixS
* fixP
,
27290 offsetT value
= * valP
;
27292 unsigned int newimm
;
27293 unsigned long temp
;
27295 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27297 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27299 /* Note whether this will delete the relocation. */
27301 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27304 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27305 consistency with the behaviour on 32-bit hosts. Remember value
27307 value
&= 0xffffffff;
27308 value
^= 0x80000000;
27309 value
-= 0x80000000;
27312 fixP
->fx_addnumber
= value
;
27314 /* Same treatment for fixP->fx_offset. */
27315 fixP
->fx_offset
&= 0xffffffff;
27316 fixP
->fx_offset
^= 0x80000000;
27317 fixP
->fx_offset
-= 0x80000000;
27319 switch (fixP
->fx_r_type
)
27321 case BFD_RELOC_NONE
:
27322 /* This will need to go in the object file. */
27326 case BFD_RELOC_ARM_IMMEDIATE
:
27327 /* We claim that this fixup has been processed here,
27328 even if in fact we generate an error because we do
27329 not have a reloc for it, so tc_gen_reloc will reject it. */
27332 if (fixP
->fx_addsy
)
27334 const char *msg
= 0;
27336 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27337 msg
= _("undefined symbol %s used as an immediate value");
27338 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27339 msg
= _("symbol %s is in a different section");
27340 else if (S_IS_WEAK (fixP
->fx_addsy
))
27341 msg
= _("symbol %s is weak and may be overridden later");
27345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27346 msg
, S_GET_NAME (fixP
->fx_addsy
));
27351 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27353 /* If the offset is negative, we should use encoding A2 for ADR. */
27354 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27355 newimm
= negate_data_op (&temp
, value
);
27358 newimm
= encode_arm_immediate (value
);
27360 /* If the instruction will fail, see if we can fix things up by
27361 changing the opcode. */
27362 if (newimm
== (unsigned int) FAIL
)
27363 newimm
= negate_data_op (&temp
, value
);
27364 /* MOV accepts both ARM modified immediate (A1 encoding) and
27365 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27366 When disassembling, MOV is preferred when there is no encoding
27368 if (newimm
== (unsigned int) FAIL
27369 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27370 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27371 && !((temp
>> SBIT_SHIFT
) & 0x1)
27372 && value
>= 0 && value
<= 0xffff)
27374 /* Clear bits[23:20] to change encoding from A1 to A2. */
27375 temp
&= 0xff0fffff;
27376 /* Encoding high 4bits imm. Code below will encode the remaining
27378 temp
|= (value
& 0x0000f000) << 4;
27379 newimm
= value
& 0x00000fff;
27383 if (newimm
== (unsigned int) FAIL
)
27385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27386 _("invalid constant (%lx) after fixup"),
27387 (unsigned long) value
);
27391 newimm
|= (temp
& 0xfffff000);
27392 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27395 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27397 unsigned int highpart
= 0;
27398 unsigned int newinsn
= 0xe1a00000; /* nop. */
27400 if (fixP
->fx_addsy
)
27402 const char *msg
= 0;
27404 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27405 msg
= _("undefined symbol %s used as an immediate value");
27406 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27407 msg
= _("symbol %s is in a different section");
27408 else if (S_IS_WEAK (fixP
->fx_addsy
))
27409 msg
= _("symbol %s is weak and may be overridden later");
27413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27414 msg
, S_GET_NAME (fixP
->fx_addsy
));
27419 newimm
= encode_arm_immediate (value
);
27420 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27422 /* If the instruction will fail, see if we can fix things up by
27423 changing the opcode. */
27424 if (newimm
== (unsigned int) FAIL
27425 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27427 /* No ? OK - try using two ADD instructions to generate
27429 newimm
= validate_immediate_twopart (value
, & highpart
);
27431 /* Yes - then make sure that the second instruction is
27433 if (newimm
!= (unsigned int) FAIL
)
27435 /* Still No ? Try using a negated value. */
27436 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27437 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27438 /* Otherwise - give up. */
27441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27442 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27447 /* Replace the first operand in the 2nd instruction (which
27448 is the PC) with the destination register. We have
27449 already added in the PC in the first instruction and we
27450 do not want to do it again. */
27451 newinsn
&= ~ 0xf0000;
27452 newinsn
|= ((newinsn
& 0x0f000) << 4);
27455 newimm
|= (temp
& 0xfffff000);
27456 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27458 highpart
|= (newinsn
& 0xfffff000);
27459 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27463 case BFD_RELOC_ARM_OFFSET_IMM
:
27464 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27466 /* Fall through. */
27468 case BFD_RELOC_ARM_LITERAL
:
27474 if (validate_offset_imm (value
, 0) == FAIL
)
27476 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27477 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27478 _("invalid literal constant: pool needs to be closer"));
27480 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27481 _("bad immediate value for offset (%ld)"),
27486 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27488 newval
&= 0xfffff000;
27491 newval
&= 0xff7ff000;
27492 newval
|= value
| (sign
? INDEX_UP
: 0);
27494 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27497 case BFD_RELOC_ARM_OFFSET_IMM8
:
27498 case BFD_RELOC_ARM_HWLITERAL
:
27504 if (validate_offset_imm (value
, 1) == FAIL
)
27506 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27507 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27508 _("invalid literal constant: pool needs to be closer"));
27510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27511 _("bad immediate value for 8-bit offset (%ld)"),
27516 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27518 newval
&= 0xfffff0f0;
27521 newval
&= 0xff7ff0f0;
27522 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27524 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27527 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27528 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27529 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27530 _("bad immediate value for offset (%ld)"), (long) value
);
27533 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27535 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27538 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27539 /* This is a complicated relocation used for all varieties of Thumb32
27540 load/store instruction with immediate offset:
27542 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27543 *4, optional writeback(W)
27544 (doubleword load/store)
27546 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27547 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27548 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27549 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27550 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27552 Uppercase letters indicate bits that are already encoded at
27553 this point. Lowercase letters are our problem. For the
27554 second block of instructions, the secondary opcode nybble
27555 (bits 8..11) is present, and bit 23 is zero, even if this is
27556 a PC-relative operation. */
27557 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27559 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
27561 if ((newval
& 0xf0000000) == 0xe0000000)
27563 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27565 newval
|= (1 << 23);
27568 if (value
% 4 != 0)
27570 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27571 _("offset not a multiple of 4"));
27577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27578 _("offset out of range"));
27583 else if ((newval
& 0x000f0000) == 0x000f0000)
27585 /* PC-relative, 12-bit offset. */
27587 newval
|= (1 << 23);
27592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27593 _("offset out of range"));
27598 else if ((newval
& 0x00000100) == 0x00000100)
27600 /* Writeback: 8-bit, +/- offset. */
27602 newval
|= (1 << 9);
27607 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27608 _("offset out of range"));
27613 else if ((newval
& 0x00000f00) == 0x00000e00)
27615 /* T-instruction: positive 8-bit offset. */
27616 if (value
< 0 || value
> 0xff)
27618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27619 _("offset out of range"));
27627 /* Positive 12-bit or negative 8-bit offset. */
27631 newval
|= (1 << 23);
27641 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27642 _("offset out of range"));
27649 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
27650 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
27653 case BFD_RELOC_ARM_SHIFT_IMM
:
27654 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27655 if (((unsigned long) value
) > 32
27657 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
27659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27660 _("shift expression is too large"));
27665 /* Shifts of zero must be done as lsl. */
27667 else if (value
== 32)
27669 newval
&= 0xfffff07f;
27670 newval
|= (value
& 0x1f) << 7;
27671 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27674 case BFD_RELOC_ARM_T32_IMMEDIATE
:
27675 case BFD_RELOC_ARM_T32_ADD_IMM
:
27676 case BFD_RELOC_ARM_T32_IMM12
:
27677 case BFD_RELOC_ARM_T32_ADD_PC12
:
27678 /* We claim that this fixup has been processed here,
27679 even if in fact we generate an error because we do
27680 not have a reloc for it, so tc_gen_reloc will reject it. */
27684 && ! S_IS_DEFINED (fixP
->fx_addsy
))
27686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27687 _("undefined symbol %s used as an immediate value"),
27688 S_GET_NAME (fixP
->fx_addsy
));
27692 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27694 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
27697 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27698 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27699 Thumb2 modified immediate encoding (T2). */
27700 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
27701 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27703 newimm
= encode_thumb32_immediate (value
);
27704 if (newimm
== (unsigned int) FAIL
)
27705 newimm
= thumb32_negate_data_op (&newval
, value
);
27707 if (newimm
== (unsigned int) FAIL
)
27709 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
27711 /* Turn add/sum into addw/subw. */
27712 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27713 newval
= (newval
& 0xfeffffff) | 0x02000000;
27714 /* No flat 12-bit imm encoding for addsw/subsw. */
27715 if ((newval
& 0x00100000) == 0)
27717 /* 12 bit immediate for addw/subw. */
27721 newval
^= 0x00a00000;
27724 newimm
= (unsigned int) FAIL
;
27731 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27732 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27733 disassembling, MOV is preferred when there is no encoding
27735 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
27736 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27737 but with the Rn field [19:16] set to 1111. */
27738 && (((newval
>> 16) & 0xf) == 0xf)
27739 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
27740 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
27741 && value
>= 0 && value
<= 0xffff)
27743 /* Toggle bit[25] to change encoding from T2 to T3. */
27745 /* Clear bits[19:16]. */
27746 newval
&= 0xfff0ffff;
27747 /* Encoding high 4bits imm. Code below will encode the
27748 remaining low 12bits. */
27749 newval
|= (value
& 0x0000f000) << 4;
27750 newimm
= value
& 0x00000fff;
27755 if (newimm
== (unsigned int)FAIL
)
27757 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27758 _("invalid constant (%lx) after fixup"),
27759 (unsigned long) value
);
27763 newval
|= (newimm
& 0x800) << 15;
27764 newval
|= (newimm
& 0x700) << 4;
27765 newval
|= (newimm
& 0x0ff);
27767 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
27768 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
27771 case BFD_RELOC_ARM_SMC
:
27772 if (((unsigned long) value
) > 0xf)
27773 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27774 _("invalid smc expression"));
27776 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27777 newval
|= (value
& 0xf);
27778 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27781 case BFD_RELOC_ARM_HVC
:
27782 if (((unsigned long) value
) > 0xffff)
27783 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27784 _("invalid hvc expression"));
27785 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27786 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27787 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27790 case BFD_RELOC_ARM_SWI
:
27791 if (fixP
->tc_fix_data
!= 0)
27793 if (((unsigned long) value
) > 0xff)
27794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27795 _("invalid swi expression"));
27796 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27798 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27802 if (((unsigned long) value
) > 0x00ffffff)
27803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27804 _("invalid swi expression"));
27805 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27807 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27811 case BFD_RELOC_ARM_MULTI
:
27812 if (((unsigned long) value
) > 0xffff)
27813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27814 _("invalid expression in load/store multiple"));
27815 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
27816 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27820 case BFD_RELOC_ARM_PCREL_CALL
:
27822 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27824 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27825 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27826 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27827 /* Flip the bl to blx. This is a simple flip
27828 bit here because we generate PCREL_CALL for
27829 unconditional bls. */
27831 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27832 newval
= newval
| 0x10000000;
27833 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27839 goto arm_branch_common
;
27841 case BFD_RELOC_ARM_PCREL_JUMP
:
27842 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27844 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27845 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27846 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27848 /* This would map to a bl<cond>, b<cond>,
27849 b<always> to a Thumb function. We
27850 need to force a relocation for this particular
27852 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27855 /* Fall through. */
27857 case BFD_RELOC_ARM_PLT32
:
27859 case BFD_RELOC_ARM_PCREL_BRANCH
:
27861 goto arm_branch_common
;
27863 case BFD_RELOC_ARM_PCREL_BLX
:
27866 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27868 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27869 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27870 && ARM_IS_FUNC (fixP
->fx_addsy
))
27872 /* Flip the blx to a bl and warn. */
27873 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27874 newval
= 0xeb000000;
27875 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27876 _("blx to '%s' an ARM ISA state function changed to bl"),
27878 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27884 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27885 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
27889 /* We are going to store value (shifted right by two) in the
27890 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27891 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
27894 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27895 _("misaligned branch destination"));
27896 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
27897 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
27898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27900 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27902 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27903 newval
|= (value
>> 2) & 0x00ffffff;
27904 /* Set the H bit on BLX instructions. */
27908 newval
|= 0x01000000;
27910 newval
&= ~0x01000000;
27912 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27916 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
27917 /* CBZ can only branch forward. */
27919 /* Attempts to use CBZ to branch to the next instruction
27920 (which, strictly speaking, are prohibited) will be turned into
27923 FIXME: It may be better to remove the instruction completely and
27924 perform relaxation. */
27927 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27928 newval
= 0xbf00; /* NOP encoding T1 */
27929 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27936 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27938 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27939 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
27940 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27945 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
27946 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
27947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27949 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27951 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27952 newval
|= (value
& 0x1ff) >> 1;
27953 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27957 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
27958 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
27959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27961 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27963 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27964 newval
|= (value
& 0xfff) >> 1;
27965 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27969 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27971 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27972 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27973 && ARM_IS_FUNC (fixP
->fx_addsy
)
27974 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27976 /* Force a relocation for a branch 20 bits wide. */
27979 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
27980 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27981 _("conditional branch out of range"));
27983 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27986 addressT S
, J1
, J2
, lo
, hi
;
27988 S
= (value
& 0x00100000) >> 20;
27989 J2
= (value
& 0x00080000) >> 19;
27990 J1
= (value
& 0x00040000) >> 18;
27991 hi
= (value
& 0x0003f000) >> 12;
27992 lo
= (value
& 0x00000ffe) >> 1;
27994 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27995 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27996 newval
|= (S
<< 10) | hi
;
27997 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
27998 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27999 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28003 case BFD_RELOC_THUMB_PCREL_BLX
:
28004 /* If there is a blx from a thumb state function to
28005 another thumb function flip this to a bl and warn
28009 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28010 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28011 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28013 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28014 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28015 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
28017 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28018 newval
= newval
| 0x1000;
28019 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28020 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28025 goto thumb_bl_common
;
28027 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28028 /* A bl from Thumb state ISA to an internal ARM state function
28029 is converted to a blx. */
28031 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28032 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28033 && ARM_IS_FUNC (fixP
->fx_addsy
)
28034 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28036 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28037 newval
= newval
& ~0x1000;
28038 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28039 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
28045 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28046 /* For a BLX instruction, make sure that the relocation is rounded up
28047 to a word boundary. This follows the semantics of the instruction
28048 which specifies that bit 1 of the target address will come from bit
28049 1 of the base address. */
28050 value
= (value
+ 3) & ~ 3;
28053 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
28054 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28055 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28058 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
28060 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
28061 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28062 else if ((value
& ~0x1ffffff)
28063 && ((value
& ~0x1ffffff) != ~0x1ffffff))
28064 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28065 _("Thumb2 branch out of range"));
28068 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28069 encode_thumb2_b_bl_offset (buf
, value
);
28073 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28074 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
28075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28077 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28078 encode_thumb2_b_bl_offset (buf
, value
);
28083 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28088 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28089 md_number_to_chars (buf
, value
, 2);
28093 case BFD_RELOC_ARM_TLS_CALL
:
28094 case BFD_RELOC_ARM_THM_TLS_CALL
:
28095 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28096 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28097 case BFD_RELOC_ARM_TLS_GOTDESC
:
28098 case BFD_RELOC_ARM_TLS_GD32
:
28099 case BFD_RELOC_ARM_TLS_LE32
:
28100 case BFD_RELOC_ARM_TLS_IE32
:
28101 case BFD_RELOC_ARM_TLS_LDM32
:
28102 case BFD_RELOC_ARM_TLS_LDO32
:
28103 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28106 /* Same handling as above, but with the arm_fdpic guard. */
28107 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28108 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28109 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28112 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28116 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28117 _("Relocation supported only in FDPIC mode"));
28121 case BFD_RELOC_ARM_GOT32
:
28122 case BFD_RELOC_ARM_GOTOFF
:
28125 case BFD_RELOC_ARM_GOT_PREL
:
28126 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28127 md_number_to_chars (buf
, value
, 4);
28130 case BFD_RELOC_ARM_TARGET2
:
28131 /* TARGET2 is not partial-inplace, so we need to write the
28132 addend here for REL targets, because it won't be written out
28133 during reloc processing later. */
28134 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28135 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
28138 /* Relocations for FDPIC. */
28139 case BFD_RELOC_ARM_GOTFUNCDESC
:
28140 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28141 case BFD_RELOC_ARM_FUNCDESC
:
28144 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28145 md_number_to_chars (buf
, 0, 4);
28149 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28150 _("Relocation supported only in FDPIC mode"));
28155 case BFD_RELOC_RVA
:
28157 case BFD_RELOC_ARM_TARGET1
:
28158 case BFD_RELOC_ARM_ROSEGREL32
:
28159 case BFD_RELOC_ARM_SBREL32
:
28160 case BFD_RELOC_32_PCREL
:
28162 case BFD_RELOC_32_SECREL
:
28164 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28166 /* For WinCE we only do this for pcrel fixups. */
28167 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
28169 md_number_to_chars (buf
, value
, 4);
28173 case BFD_RELOC_ARM_PREL31
:
28174 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28176 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
28177 if ((value
^ (value
>> 1)) & 0x40000000)
28179 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28180 _("rel31 relocation overflow"));
28182 newval
|= value
& 0x7fffffff;
28183 md_number_to_chars (buf
, newval
, 4);
28188 case BFD_RELOC_ARM_CP_OFF_IMM
:
28189 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
28190 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
28191 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
28192 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28194 newval
= get_thumb32_insn (buf
);
28195 if ((newval
& 0x0f200f00) == 0x0d000900)
28197 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28198 has permitted values that are multiples of 2, in the range 0
28200 if (value
< -510 || value
> 510 || (value
& 1))
28201 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28202 _("co-processor offset out of range"));
28204 else if ((newval
& 0xfe001f80) == 0xec000f80)
28206 if (value
< -511 || value
> 512 || (value
& 3))
28207 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28208 _("co-processor offset out of range"));
28210 else if (value
< -1023 || value
> 1023 || (value
& 3))
28211 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28212 _("co-processor offset out of range"));
28217 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28218 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28219 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28221 newval
= get_thumb32_insn (buf
);
28224 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28225 newval
&= 0xffffff80;
28227 newval
&= 0xffffff00;
28231 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28232 newval
&= 0xff7fff80;
28234 newval
&= 0xff7fff00;
28235 if ((newval
& 0x0f200f00) == 0x0d000900)
28237 /* This is a fp16 vstr/vldr.
28239 It requires the immediate offset in the instruction is shifted
28240 left by 1 to be a half-word offset.
28242 Here, left shift by 1 first, and later right shift by 2
28243 should get the right offset. */
28246 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
28248 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28249 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28250 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28252 put_thumb32_insn (buf
, newval
);
28255 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
28256 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
28257 if (value
< -255 || value
> 255)
28258 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28259 _("co-processor offset out of range"));
28261 goto cp_off_common
;
28263 case BFD_RELOC_ARM_THUMB_OFFSET
:
28264 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28265 /* Exactly what ranges, and where the offset is inserted depends
28266 on the type of instruction, we can establish this from the
28268 switch (newval
>> 12)
28270 case 4: /* PC load. */
28271 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28272 forced to zero for these loads; md_pcrel_from has already
28273 compensated for this. */
28275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28276 _("invalid offset, target not word aligned (0x%08lX)"),
28277 (((unsigned long) fixP
->fx_frag
->fr_address
28278 + (unsigned long) fixP
->fx_where
) & ~3)
28279 + (unsigned long) value
);
28281 if (value
& ~0x3fc)
28282 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28283 _("invalid offset, value too big (0x%08lX)"),
28286 newval
|= value
>> 2;
28289 case 9: /* SP load/store. */
28290 if (value
& ~0x3fc)
28291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28292 _("invalid offset, value too big (0x%08lX)"),
28294 newval
|= value
>> 2;
28297 case 6: /* Word load/store. */
28299 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28300 _("invalid offset, value too big (0x%08lX)"),
28302 newval
|= value
<< 4; /* 6 - 2. */
28305 case 7: /* Byte load/store. */
28307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28308 _("invalid offset, value too big (0x%08lX)"),
28310 newval
|= value
<< 6;
28313 case 8: /* Halfword load/store. */
28315 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28316 _("invalid offset, value too big (0x%08lX)"),
28318 newval
|= value
<< 5; /* 6 - 1. */
28322 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28323 "Unable to process relocation for thumb opcode: %lx",
28324 (unsigned long) newval
);
28327 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28330 case BFD_RELOC_ARM_THUMB_ADD
:
28331 /* This is a complicated relocation, since we use it for all of
28332 the following immediate relocations:
28336 9bit ADD/SUB SP word-aligned
28337 10bit ADD PC/SP word-aligned
28339 The type of instruction being processed is encoded in the
28346 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28348 int rd
= (newval
>> 4) & 0xf;
28349 int rs
= newval
& 0xf;
28350 int subtract
= !!(newval
& 0x8000);
28352 /* Check for HI regs, only very restricted cases allowed:
28353 Adjusting SP, and using PC or SP to get an address. */
28354 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28355 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28356 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28357 _("invalid Hi register with immediate"));
28359 /* If value is negative, choose the opposite instruction. */
28363 subtract
= !subtract
;
28365 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28366 _("immediate value out of range"));
28371 if (value
& ~0x1fc)
28372 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28373 _("invalid immediate for stack address calculation"));
28374 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28375 newval
|= value
>> 2;
28377 else if (rs
== REG_PC
|| rs
== REG_SP
)
28379 /* PR gas/18541. If the addition is for a defined symbol
28380 within range of an ADR instruction then accept it. */
28383 && fixP
->fx_addsy
!= NULL
)
28387 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28388 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28389 || S_IS_WEAK (fixP
->fx_addsy
))
28391 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28392 _("address calculation needs a strongly defined nearby symbol"));
28396 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28398 /* Round up to the next 4-byte boundary. */
28403 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28407 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28408 _("symbol too far away"));
28418 if (subtract
|| value
& ~0x3fc)
28419 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28420 _("invalid immediate for address calculation (value = 0x%08lX)"),
28421 (unsigned long) (subtract
? - value
: value
));
28422 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28424 newval
|= value
>> 2;
28429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28430 _("immediate value out of range"));
28431 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28432 newval
|= (rd
<< 8) | value
;
28437 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28438 _("immediate value out of range"));
28439 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28440 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28443 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28446 case BFD_RELOC_ARM_THUMB_IMM
:
28447 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28448 if (value
< 0 || value
> 255)
28449 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28450 _("invalid immediate: %ld is out of range"),
28453 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28456 case BFD_RELOC_ARM_THUMB_SHIFT
:
28457 /* 5bit shift value (0..32). LSL cannot take 32. */
28458 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28459 temp
= newval
& 0xf800;
28460 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28461 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28462 _("invalid shift value: %ld"), (long) value
);
28463 /* Shifts of zero must be encoded as LSL. */
28465 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28466 /* Shifts of 32 are encoded as zero. */
28467 else if (value
== 32)
28469 newval
|= value
<< 6;
28470 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28473 case BFD_RELOC_VTABLE_INHERIT
:
28474 case BFD_RELOC_VTABLE_ENTRY
:
28478 case BFD_RELOC_ARM_MOVW
:
28479 case BFD_RELOC_ARM_MOVT
:
28480 case BFD_RELOC_ARM_THUMB_MOVW
:
28481 case BFD_RELOC_ARM_THUMB_MOVT
:
28482 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28484 /* REL format relocations are limited to a 16-bit addend. */
28485 if (!fixP
->fx_done
)
28487 if (value
< -0x8000 || value
> 0x7fff)
28488 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28489 _("offset out of range"));
28491 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28492 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28497 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28498 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28500 newval
= get_thumb32_insn (buf
);
28501 newval
&= 0xfbf08f00;
28502 newval
|= (value
& 0xf000) << 4;
28503 newval
|= (value
& 0x0800) << 15;
28504 newval
|= (value
& 0x0700) << 4;
28505 newval
|= (value
& 0x00ff);
28506 put_thumb32_insn (buf
, newval
);
28510 newval
= md_chars_to_number (buf
, 4);
28511 newval
&= 0xfff0f000;
28512 newval
|= value
& 0x0fff;
28513 newval
|= (value
& 0xf000) << 4;
28514 md_number_to_chars (buf
, newval
, 4);
28519 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28520 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28521 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28522 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28523 gas_assert (!fixP
->fx_done
);
28526 bfd_boolean is_mov
;
28527 bfd_vma encoded_addend
= value
;
28529 /* Check that addend can be encoded in instruction. */
28530 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28531 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28532 _("the offset 0x%08lX is not representable"),
28533 (unsigned long) encoded_addend
);
28535 /* Extract the instruction. */
28536 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28537 is_mov
= (insn
& 0xf800) == 0x2000;
28542 if (!seg
->use_rela_p
)
28543 insn
|= encoded_addend
;
28549 /* Extract the instruction. */
28550 /* Encoding is the following
28555 /* The following conditions must be true :
28560 rd
= (insn
>> 4) & 0xf;
28562 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
28563 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28564 _("Unable to process relocation for thumb opcode: %lx"),
28565 (unsigned long) insn
);
28567 /* Encode as ADD immediate8 thumb 1 code. */
28568 insn
= 0x3000 | (rd
<< 8);
28570 /* Place the encoded addend into the first 8 bits of the
28572 if (!seg
->use_rela_p
)
28573 insn
|= encoded_addend
;
28576 /* Update the instruction. */
28577 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
28581 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28582 case BFD_RELOC_ARM_ALU_PC_G0
:
28583 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28584 case BFD_RELOC_ARM_ALU_PC_G1
:
28585 case BFD_RELOC_ARM_ALU_PC_G2
:
28586 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28587 case BFD_RELOC_ARM_ALU_SB_G0
:
28588 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28589 case BFD_RELOC_ARM_ALU_SB_G1
:
28590 case BFD_RELOC_ARM_ALU_SB_G2
:
28591 gas_assert (!fixP
->fx_done
);
28592 if (!seg
->use_rela_p
)
28595 bfd_vma encoded_addend
;
28596 bfd_vma addend_abs
= llabs (value
);
28598 /* Check that the absolute value of the addend can be
28599 expressed as an 8-bit constant plus a rotation. */
28600 encoded_addend
= encode_arm_immediate (addend_abs
);
28601 if (encoded_addend
== (unsigned int) FAIL
)
28602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28603 _("the offset 0x%08lX is not representable"),
28604 (unsigned long) addend_abs
);
28606 /* Extract the instruction. */
28607 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28609 /* If the addend is positive, use an ADD instruction.
28610 Otherwise use a SUB. Take care not to destroy the S bit. */
28611 insn
&= 0xff1fffff;
28617 /* Place the encoded addend into the first 12 bits of the
28619 insn
&= 0xfffff000;
28620 insn
|= encoded_addend
;
28622 /* Update the instruction. */
28623 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28627 case BFD_RELOC_ARM_LDR_PC_G0
:
28628 case BFD_RELOC_ARM_LDR_PC_G1
:
28629 case BFD_RELOC_ARM_LDR_PC_G2
:
28630 case BFD_RELOC_ARM_LDR_SB_G0
:
28631 case BFD_RELOC_ARM_LDR_SB_G1
:
28632 case BFD_RELOC_ARM_LDR_SB_G2
:
28633 gas_assert (!fixP
->fx_done
);
28634 if (!seg
->use_rela_p
)
28637 bfd_vma addend_abs
= llabs (value
);
28639 /* Check that the absolute value of the addend can be
28640 encoded in 12 bits. */
28641 if (addend_abs
>= 0x1000)
28642 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28643 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28644 (unsigned long) addend_abs
);
28646 /* Extract the instruction. */
28647 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28649 /* If the addend is negative, clear bit 23 of the instruction.
28650 Otherwise set it. */
28652 insn
&= ~(1 << 23);
28656 /* Place the absolute value of the addend into the first 12 bits
28657 of the instruction. */
28658 insn
&= 0xfffff000;
28659 insn
|= addend_abs
;
28661 /* Update the instruction. */
28662 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28666 case BFD_RELOC_ARM_LDRS_PC_G0
:
28667 case BFD_RELOC_ARM_LDRS_PC_G1
:
28668 case BFD_RELOC_ARM_LDRS_PC_G2
:
28669 case BFD_RELOC_ARM_LDRS_SB_G0
:
28670 case BFD_RELOC_ARM_LDRS_SB_G1
:
28671 case BFD_RELOC_ARM_LDRS_SB_G2
:
28672 gas_assert (!fixP
->fx_done
);
28673 if (!seg
->use_rela_p
)
28676 bfd_vma addend_abs
= llabs (value
);
28678 /* Check that the absolute value of the addend can be
28679 encoded in 8 bits. */
28680 if (addend_abs
>= 0x100)
28681 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28682 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28683 (unsigned long) addend_abs
);
28685 /* Extract the instruction. */
28686 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28688 /* If the addend is negative, clear bit 23 of the instruction.
28689 Otherwise set it. */
28691 insn
&= ~(1 << 23);
28695 /* Place the first four bits of the absolute value of the addend
28696 into the first 4 bits of the instruction, and the remaining
28697 four into bits 8 .. 11. */
28698 insn
&= 0xfffff0f0;
28699 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
28701 /* Update the instruction. */
28702 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28706 case BFD_RELOC_ARM_LDC_PC_G0
:
28707 case BFD_RELOC_ARM_LDC_PC_G1
:
28708 case BFD_RELOC_ARM_LDC_PC_G2
:
28709 case BFD_RELOC_ARM_LDC_SB_G0
:
28710 case BFD_RELOC_ARM_LDC_SB_G1
:
28711 case BFD_RELOC_ARM_LDC_SB_G2
:
28712 gas_assert (!fixP
->fx_done
);
28713 if (!seg
->use_rela_p
)
28716 bfd_vma addend_abs
= llabs (value
);
28718 /* Check that the absolute value of the addend is a multiple of
28719 four and, when divided by four, fits in 8 bits. */
28720 if (addend_abs
& 0x3)
28721 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28722 _("bad offset 0x%08lX (must be word-aligned)"),
28723 (unsigned long) addend_abs
);
28725 if ((addend_abs
>> 2) > 0xff)
28726 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28727 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28728 (unsigned long) addend_abs
);
28730 /* Extract the instruction. */
28731 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28733 /* If the addend is negative, clear bit 23 of the instruction.
28734 Otherwise set it. */
28736 insn
&= ~(1 << 23);
28740 /* Place the addend (divided by four) into the first eight
28741 bits of the instruction. */
28742 insn
&= 0xfffffff0;
28743 insn
|= addend_abs
>> 2;
28745 /* Update the instruction. */
28746 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28750 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28752 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28753 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28754 && ARM_IS_FUNC (fixP
->fx_addsy
)
28755 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28757 /* Force a relocation for a branch 5 bits wide. */
28760 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
28761 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28764 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28766 addressT boff
= value
>> 1;
28768 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28769 newval
|= (boff
<< 7);
28770 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28774 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28776 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28777 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28778 && ARM_IS_FUNC (fixP
->fx_addsy
)
28779 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28783 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
28784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28785 _("branch out of range"));
28787 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28789 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28791 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
28792 addressT diff
= value
- boff
;
28796 newval
|= 1 << 1; /* T bit. */
28798 else if (diff
!= 2)
28800 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28801 _("out of range label-relative fixup value"));
28803 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28807 case BFD_RELOC_ARM_THUMB_BF17
:
28809 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28810 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28811 && ARM_IS_FUNC (fixP
->fx_addsy
)
28812 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28814 /* Force a relocation for a branch 17 bits wide. */
28818 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
28819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28822 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28825 addressT immA
, immB
, immC
;
28827 immA
= (value
& 0x0001f000) >> 12;
28828 immB
= (value
& 0x00000ffc) >> 2;
28829 immC
= (value
& 0x00000002) >> 1;
28831 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28832 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28834 newval2
|= (immC
<< 11) | (immB
<< 1);
28835 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28836 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28840 case BFD_RELOC_ARM_THUMB_BF19
:
28842 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28843 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28844 && ARM_IS_FUNC (fixP
->fx_addsy
)
28845 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28847 /* Force a relocation for a branch 19 bits wide. */
28851 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
28852 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28855 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28858 addressT immA
, immB
, immC
;
28860 immA
= (value
& 0x0007f000) >> 12;
28861 immB
= (value
& 0x00000ffc) >> 2;
28862 immC
= (value
& 0x00000002) >> 1;
28864 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28865 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28867 newval2
|= (immC
<< 11) | (immB
<< 1);
28868 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28869 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28873 case BFD_RELOC_ARM_THUMB_BF13
:
28875 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28876 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28877 && ARM_IS_FUNC (fixP
->fx_addsy
)
28878 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28880 /* Force a relocation for a branch 13 bits wide. */
28884 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
28885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28888 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28891 addressT immA
, immB
, immC
;
28893 immA
= (value
& 0x00001000) >> 12;
28894 immB
= (value
& 0x00000ffc) >> 2;
28895 immC
= (value
& 0x00000002) >> 1;
28897 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28898 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28900 newval2
|= (immC
<< 11) | (immB
<< 1);
28901 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28902 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28906 case BFD_RELOC_ARM_THUMB_LOOP12
:
28908 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28909 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28910 && ARM_IS_FUNC (fixP
->fx_addsy
)
28911 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28913 /* Force a relocation for a branch 12 bits wide. */
28917 bfd_vma insn
= get_thumb32_insn (buf
);
28918 /* le lr, <label>, le <label> or letp lr, <label> */
28919 if (((insn
& 0xffffffff) == 0xf00fc001)
28920 || ((insn
& 0xffffffff) == 0xf02fc001)
28921 || ((insn
& 0xffffffff) == 0xf01fc001))
28924 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
28925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28927 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28929 addressT imml
, immh
;
28931 immh
= (value
& 0x00000ffc) >> 2;
28932 imml
= (value
& 0x00000002) >> 1;
28934 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28935 newval
|= (imml
<< 11) | (immh
<< 1);
28936 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
28940 case BFD_RELOC_ARM_V4BX
:
28941 /* This will need to go in the object file. */
28945 case BFD_RELOC_UNUSED
:
28947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28948 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
28952 /* Translate internal representation of relocation info to BFD target
28956 tc_gen_reloc (asection
*section
, fixS
*fixp
)
28959 bfd_reloc_code_real_type code
;
28961 reloc
= XNEW (arelent
);
28963 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
28964 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
28965 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
28967 if (fixp
->fx_pcrel
)
28969 if (section
->use_rela_p
)
28970 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
28972 fixp
->fx_offset
= reloc
->address
;
28974 reloc
->addend
= fixp
->fx_offset
;
28976 switch (fixp
->fx_r_type
)
28979 if (fixp
->fx_pcrel
)
28981 code
= BFD_RELOC_8_PCREL
;
28984 /* Fall through. */
28987 if (fixp
->fx_pcrel
)
28989 code
= BFD_RELOC_16_PCREL
;
28992 /* Fall through. */
28995 if (fixp
->fx_pcrel
)
28997 code
= BFD_RELOC_32_PCREL
;
29000 /* Fall through. */
29002 case BFD_RELOC_ARM_MOVW
:
29003 if (fixp
->fx_pcrel
)
29005 code
= BFD_RELOC_ARM_MOVW_PCREL
;
29008 /* Fall through. */
29010 case BFD_RELOC_ARM_MOVT
:
29011 if (fixp
->fx_pcrel
)
29013 code
= BFD_RELOC_ARM_MOVT_PCREL
;
29016 /* Fall through. */
29018 case BFD_RELOC_ARM_THUMB_MOVW
:
29019 if (fixp
->fx_pcrel
)
29021 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
29024 /* Fall through. */
29026 case BFD_RELOC_ARM_THUMB_MOVT
:
29027 if (fixp
->fx_pcrel
)
29029 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
29032 /* Fall through. */
29034 case BFD_RELOC_NONE
:
29035 case BFD_RELOC_ARM_PCREL_BRANCH
:
29036 case BFD_RELOC_ARM_PCREL_BLX
:
29037 case BFD_RELOC_RVA
:
29038 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
29039 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
29040 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
29041 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29042 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29043 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29044 case BFD_RELOC_VTABLE_ENTRY
:
29045 case BFD_RELOC_VTABLE_INHERIT
:
29047 case BFD_RELOC_32_SECREL
:
29049 code
= fixp
->fx_r_type
;
29052 case BFD_RELOC_THUMB_PCREL_BLX
:
29054 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
29055 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29058 code
= BFD_RELOC_THUMB_PCREL_BLX
;
29061 case BFD_RELOC_ARM_LITERAL
:
29062 case BFD_RELOC_ARM_HWLITERAL
:
29063 /* If this is called then the a literal has
29064 been referenced across a section boundary. */
29065 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29066 _("literal referenced across section boundary"));
29070 case BFD_RELOC_ARM_TLS_CALL
:
29071 case BFD_RELOC_ARM_THM_TLS_CALL
:
29072 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29073 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29074 case BFD_RELOC_ARM_GOT32
:
29075 case BFD_RELOC_ARM_GOTOFF
:
29076 case BFD_RELOC_ARM_GOT_PREL
:
29077 case BFD_RELOC_ARM_PLT32
:
29078 case BFD_RELOC_ARM_TARGET1
:
29079 case BFD_RELOC_ARM_ROSEGREL32
:
29080 case BFD_RELOC_ARM_SBREL32
:
29081 case BFD_RELOC_ARM_PREL31
:
29082 case BFD_RELOC_ARM_TARGET2
:
29083 case BFD_RELOC_ARM_TLS_LDO32
:
29084 case BFD_RELOC_ARM_PCREL_CALL
:
29085 case BFD_RELOC_ARM_PCREL_JUMP
:
29086 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29087 case BFD_RELOC_ARM_ALU_PC_G0
:
29088 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29089 case BFD_RELOC_ARM_ALU_PC_G1
:
29090 case BFD_RELOC_ARM_ALU_PC_G2
:
29091 case BFD_RELOC_ARM_LDR_PC_G0
:
29092 case BFD_RELOC_ARM_LDR_PC_G1
:
29093 case BFD_RELOC_ARM_LDR_PC_G2
:
29094 case BFD_RELOC_ARM_LDRS_PC_G0
:
29095 case BFD_RELOC_ARM_LDRS_PC_G1
:
29096 case BFD_RELOC_ARM_LDRS_PC_G2
:
29097 case BFD_RELOC_ARM_LDC_PC_G0
:
29098 case BFD_RELOC_ARM_LDC_PC_G1
:
29099 case BFD_RELOC_ARM_LDC_PC_G2
:
29100 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29101 case BFD_RELOC_ARM_ALU_SB_G0
:
29102 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29103 case BFD_RELOC_ARM_ALU_SB_G1
:
29104 case BFD_RELOC_ARM_ALU_SB_G2
:
29105 case BFD_RELOC_ARM_LDR_SB_G0
:
29106 case BFD_RELOC_ARM_LDR_SB_G1
:
29107 case BFD_RELOC_ARM_LDR_SB_G2
:
29108 case BFD_RELOC_ARM_LDRS_SB_G0
:
29109 case BFD_RELOC_ARM_LDRS_SB_G1
:
29110 case BFD_RELOC_ARM_LDRS_SB_G2
:
29111 case BFD_RELOC_ARM_LDC_SB_G0
:
29112 case BFD_RELOC_ARM_LDC_SB_G1
:
29113 case BFD_RELOC_ARM_LDC_SB_G2
:
29114 case BFD_RELOC_ARM_V4BX
:
29115 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29116 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29117 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29118 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29119 case BFD_RELOC_ARM_GOTFUNCDESC
:
29120 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29121 case BFD_RELOC_ARM_FUNCDESC
:
29122 case BFD_RELOC_ARM_THUMB_BF17
:
29123 case BFD_RELOC_ARM_THUMB_BF19
:
29124 case BFD_RELOC_ARM_THUMB_BF13
:
29125 code
= fixp
->fx_r_type
;
29128 case BFD_RELOC_ARM_TLS_GOTDESC
:
29129 case BFD_RELOC_ARM_TLS_GD32
:
29130 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29131 case BFD_RELOC_ARM_TLS_LE32
:
29132 case BFD_RELOC_ARM_TLS_IE32
:
29133 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29134 case BFD_RELOC_ARM_TLS_LDM32
:
29135 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29136 /* BFD will include the symbol's address in the addend.
29137 But we don't want that, so subtract it out again here. */
29138 if (!S_IS_COMMON (fixp
->fx_addsy
))
29139 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
29140 code
= fixp
->fx_r_type
;
29144 case BFD_RELOC_ARM_IMMEDIATE
:
29145 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29146 _("internal relocation (type: IMMEDIATE) not fixed up"));
29149 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
29150 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29151 _("ADRL used for a symbol not defined in the same file"));
29154 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29155 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29156 case BFD_RELOC_ARM_THUMB_LOOP12
:
29157 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29158 _("%s used for a symbol not defined in the same file"),
29159 bfd_get_reloc_code_name (fixp
->fx_r_type
));
29162 case BFD_RELOC_ARM_OFFSET_IMM
:
29163 if (section
->use_rela_p
)
29165 code
= fixp
->fx_r_type
;
29169 if (fixp
->fx_addsy
!= NULL
29170 && !S_IS_DEFINED (fixp
->fx_addsy
)
29171 && S_IS_LOCAL (fixp
->fx_addsy
))
29173 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29174 _("undefined local label `%s'"),
29175 S_GET_NAME (fixp
->fx_addsy
));
29179 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29180 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29187 switch (fixp
->fx_r_type
)
29189 case BFD_RELOC_NONE
: type
= "NONE"; break;
29190 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
29191 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
29192 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
29193 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
29194 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
29195 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
29196 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
29197 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
29198 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
29199 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
29200 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
29201 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
29202 default: type
= _("<unknown>"); break;
29204 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29205 _("cannot represent %s relocation in this object file format"),
29212 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
29214 && fixp
->fx_addsy
== GOT_symbol
)
29216 code
= BFD_RELOC_ARM_GOTPC
;
29217 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
29221 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
29223 if (reloc
->howto
== NULL
)
29225 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29226 _("cannot represent %s relocation in this object file format"),
29227 bfd_get_reloc_code_name (code
));
29231 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29232 vtable entry to be used in the relocation's section offset. */
29233 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29234 reloc
->address
= fixp
->fx_offset
;
29239 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
29242 cons_fix_new_arm (fragS
* frag
,
29246 bfd_reloc_code_real_type reloc
)
29251 FIXME: @@ Should look at CPU word size. */
29255 reloc
= BFD_RELOC_8
;
29258 reloc
= BFD_RELOC_16
;
29262 reloc
= BFD_RELOC_32
;
29265 reloc
= BFD_RELOC_64
;
29270 if (exp
->X_op
== O_secrel
)
29272 exp
->X_op
= O_symbol
;
29273 reloc
= BFD_RELOC_32_SECREL
;
29277 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29280 #if defined (OBJ_COFF)
29282 arm_validate_fix (fixS
* fixP
)
29284 /* If the destination of the branch is a defined symbol which does not have
29285 the THUMB_FUNC attribute, then we must be calling a function which has
29286 the (interfacearm) attribute. We look for the Thumb entry point to that
29287 function and change the branch to refer to that function instead. */
29288 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29289 && fixP
->fx_addsy
!= NULL
29290 && S_IS_DEFINED (fixP
->fx_addsy
)
29291 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29293 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29300 arm_force_relocation (struct fix
* fixp
)
29302 #if defined (OBJ_COFF) && defined (TE_PE)
29303 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29307 /* In case we have a call or a branch to a function in ARM ISA mode from
29308 a thumb function or vice-versa force the relocation. These relocations
29309 are cleared off for some cores that might have blx and simple transformations
29313 switch (fixp
->fx_r_type
)
29315 case BFD_RELOC_ARM_PCREL_JUMP
:
29316 case BFD_RELOC_ARM_PCREL_CALL
:
29317 case BFD_RELOC_THUMB_PCREL_BLX
:
29318 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29322 case BFD_RELOC_ARM_PCREL_BLX
:
29323 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29324 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29325 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29326 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29335 /* Resolve these relocations even if the symbol is extern or weak.
29336 Technically this is probably wrong due to symbol preemption.
29337 In practice these relocations do not have enough range to be useful
29338 at dynamic link time, and some code (e.g. in the Linux kernel)
29339 expects these references to be resolved. */
29340 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29341 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29342 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29343 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29344 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29345 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29346 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29347 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29348 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29349 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29350 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29351 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29352 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29353 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29356 /* Always leave these relocations for the linker. */
29357 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29358 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29359 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29362 /* Always generate relocations against function symbols. */
29363 if (fixp
->fx_r_type
== BFD_RELOC_32
29365 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29368 return generic_force_reloc (fixp
);
29371 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29372 /* Relocations against function names must be left unadjusted,
29373 so that the linker can use this information to generate interworking
29374 stubs. The MIPS version of this function
29375 also prevents relocations that are mips-16 specific, but I do not
29376 know why it does this.
29379 There is one other problem that ought to be addressed here, but
29380 which currently is not: Taking the address of a label (rather
29381 than a function) and then later jumping to that address. Such
29382 addresses also ought to have their bottom bit set (assuming that
29383 they reside in Thumb code), but at the moment they will not. */
29386 arm_fix_adjustable (fixS
* fixP
)
29388 if (fixP
->fx_addsy
== NULL
)
29391 /* Preserve relocations against symbols with function type. */
29392 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29395 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29396 && fixP
->fx_subsy
== NULL
)
29399 /* We need the symbol name for the VTABLE entries. */
29400 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29401 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29404 /* Don't allow symbols to be discarded on GOT related relocs. */
29405 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29406 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29407 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29408 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29409 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29410 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29411 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29412 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29413 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29414 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29415 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29416 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29417 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29418 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29419 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29420 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29421 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29424 /* Similarly for group relocations. */
29425 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29426 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29427 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29430 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29431 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29432 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29433 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29434 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29435 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29436 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29437 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29438 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29441 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29442 offsets, so keep these symbols. */
29443 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29444 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29449 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29453 elf32_arm_target_format (void)
29456 return (target_big_endian
29457 ? "elf32-bigarm-symbian"
29458 : "elf32-littlearm-symbian");
29459 #elif defined (TE_VXWORKS)
29460 return (target_big_endian
29461 ? "elf32-bigarm-vxworks"
29462 : "elf32-littlearm-vxworks");
29463 #elif defined (TE_NACL)
29464 return (target_big_endian
29465 ? "elf32-bigarm-nacl"
29466 : "elf32-littlearm-nacl");
29470 if (target_big_endian
)
29471 return "elf32-bigarm-fdpic";
29473 return "elf32-littlearm-fdpic";
29477 if (target_big_endian
)
29478 return "elf32-bigarm";
29480 return "elf32-littlearm";
29486 armelf_frob_symbol (symbolS
* symp
,
29489 elf_frob_symbol (symp
, puntp
);
29493 /* MD interface: Finalization. */
29498 literal_pool
* pool
;
29500 /* Ensure that all the predication blocks are properly closed. */
29501 check_pred_blocks_finished ();
29503 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29505 /* Put it at the end of the relevant section. */
29506 subseg_set (pool
->section
, pool
->sub_section
);
29508 arm_elf_change_section ();
29515 /* Remove any excess mapping symbols generated for alignment frags in
29516 SEC. We may have created a mapping symbol before a zero byte
29517 alignment; remove it if there's a mapping symbol after the
29520 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29521 void *dummy ATTRIBUTE_UNUSED
)
29523 segment_info_type
*seginfo
= seg_info (sec
);
29526 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29529 for (fragp
= seginfo
->frchainP
->frch_root
;
29531 fragp
= fragp
->fr_next
)
29533 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29534 fragS
*next
= fragp
->fr_next
;
29536 /* Variable-sized frags have been converted to fixed size by
29537 this point. But if this was variable-sized to start with,
29538 there will be a fixed-size frag after it. So don't handle
29540 if (sym
== NULL
|| next
== NULL
)
29543 if (S_GET_VALUE (sym
) < next
->fr_address
)
29544 /* Not at the end of this frag. */
29546 know (S_GET_VALUE (sym
) == next
->fr_address
);
29550 if (next
->tc_frag_data
.first_map
!= NULL
)
29552 /* Next frag starts with a mapping symbol. Discard this
29554 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29558 if (next
->fr_next
== NULL
)
29560 /* This mapping symbol is at the end of the section. Discard
29562 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
29563 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29567 /* As long as we have empty frags without any mapping symbols,
29569 /* If the next frag is non-empty and does not start with a
29570 mapping symbol, then this mapping symbol is required. */
29571 if (next
->fr_address
!= next
->fr_next
->fr_address
)
29574 next
= next
->fr_next
;
29576 while (next
!= NULL
);
29581 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29585 arm_adjust_symtab (void)
29590 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29592 if (ARM_IS_THUMB (sym
))
29594 if (THUMB_IS_FUNC (sym
))
29596 /* Mark the symbol as a Thumb function. */
29597 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
29598 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
29599 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
29601 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
29602 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
29604 as_bad (_("%s: unexpected function type: %d"),
29605 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
29607 else switch (S_GET_STORAGE_CLASS (sym
))
29610 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
29613 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
29616 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
29624 if (ARM_IS_INTERWORK (sym
))
29625 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
29632 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29634 if (ARM_IS_THUMB (sym
))
29636 elf_symbol_type
* elf_sym
;
29638 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
29639 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
29641 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
29642 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
29644 /* If it's a .thumb_func, declare it as so,
29645 otherwise tag label as .code 16. */
29646 if (THUMB_IS_FUNC (sym
))
29647 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
29648 ST_BRANCH_TO_THUMB
);
29649 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29650 elf_sym
->internal_elf_sym
.st_info
=
29651 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
29656 /* Remove any overlapping mapping symbols generated by alignment frags. */
29657 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
29658 /* Now do generic ELF adjustments. */
29659 elf_adjust_symtab ();
29663 /* MD interface: Initialization. */
29666 set_constant_flonums (void)
29670 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
29671 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
29675 /* Auto-select Thumb mode if it's the only available instruction set for the
29676 given architecture. */
29679 autoselect_thumb_from_cpu_variant (void)
29681 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
29682 opcode_select (16);
29691 if ( (arm_ops_hsh
= hash_new ()) == NULL
29692 || (arm_cond_hsh
= hash_new ()) == NULL
29693 || (arm_vcond_hsh
= hash_new ()) == NULL
29694 || (arm_shift_hsh
= hash_new ()) == NULL
29695 || (arm_psr_hsh
= hash_new ()) == NULL
29696 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
29697 || (arm_reg_hsh
= hash_new ()) == NULL
29698 || (arm_reloc_hsh
= hash_new ()) == NULL
29699 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
29700 as_fatal (_("virtual memory exhausted"));
29702 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
29703 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
29704 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
29705 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
29706 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
29707 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
29708 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
29709 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
29710 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
29711 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
29712 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
29713 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
29714 (void *) (v7m_psrs
+ i
));
29715 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
29716 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
29718 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
29720 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
29721 (void *) (barrier_opt_names
+ i
));
29723 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
29725 struct reloc_entry
* entry
= reloc_names
+ i
;
29727 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
29728 /* This makes encode_branch() use the EABI versions of this relocation. */
29729 entry
->reloc
= BFD_RELOC_UNUSED
;
29731 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
29735 set_constant_flonums ();
29737 /* Set the cpu variant based on the command-line options. We prefer
29738 -mcpu= over -march= if both are set (as for GCC); and we prefer
29739 -mfpu= over any other way of setting the floating point unit.
29740 Use of legacy options with new options are faulted. */
29743 if (mcpu_cpu_opt
|| march_cpu_opt
)
29744 as_bad (_("use of old and new-style options to set CPU type"));
29746 selected_arch
= *legacy_cpu
;
29748 else if (mcpu_cpu_opt
)
29750 selected_arch
= *mcpu_cpu_opt
;
29751 selected_ext
= *mcpu_ext_opt
;
29753 else if (march_cpu_opt
)
29755 selected_arch
= *march_cpu_opt
;
29756 selected_ext
= *march_ext_opt
;
29758 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29763 as_bad (_("use of old and new-style options to set FPU type"));
29765 selected_fpu
= *legacy_fpu
;
29768 selected_fpu
= *mfpu_opt
;
29771 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29772 || defined (TE_NetBSD) || defined (TE_VXWORKS))
29773 /* Some environments specify a default FPU. If they don't, infer it
29774 from the processor. */
29776 selected_fpu
= *mcpu_fpu_opt
;
29777 else if (march_fpu_opt
)
29778 selected_fpu
= *march_fpu_opt
;
29780 selected_fpu
= fpu_default
;
29784 if (ARM_FEATURE_ZERO (selected_fpu
))
29786 if (!no_cpu_selected ())
29787 selected_fpu
= fpu_default
;
29789 selected_fpu
= fpu_arch_fpa
;
29793 if (ARM_FEATURE_ZERO (selected_arch
))
29795 selected_arch
= cpu_default
;
29796 selected_cpu
= selected_arch
;
29798 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29800 /* Autodection of feature mode: allow all features in cpu_variant but leave
29801 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29802 after all instruction have been processed and we can decide what CPU
29803 should be selected. */
29804 if (ARM_FEATURE_ZERO (selected_arch
))
29805 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
29807 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29810 autoselect_thumb_from_cpu_variant ();
29812 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
29814 #if defined OBJ_COFF || defined OBJ_ELF
29816 unsigned int flags
= 0;
29818 #if defined OBJ_ELF
29819 flags
= meabi_flags
;
29821 switch (meabi_flags
)
29823 case EF_ARM_EABI_UNKNOWN
:
29825 /* Set the flags in the private structure. */
29826 if (uses_apcs_26
) flags
|= F_APCS26
;
29827 if (support_interwork
) flags
|= F_INTERWORK
;
29828 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
29829 if (pic_code
) flags
|= F_PIC
;
29830 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
29831 flags
|= F_SOFT_FLOAT
;
29833 switch (mfloat_abi_opt
)
29835 case ARM_FLOAT_ABI_SOFT
:
29836 case ARM_FLOAT_ABI_SOFTFP
:
29837 flags
|= F_SOFT_FLOAT
;
29840 case ARM_FLOAT_ABI_HARD
:
29841 if (flags
& F_SOFT_FLOAT
)
29842 as_bad (_("hard-float conflicts with specified fpu"));
29846 /* Using pure-endian doubles (even if soft-float). */
29847 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
29848 flags
|= F_VFP_FLOAT
;
29850 #if defined OBJ_ELF
29851 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
29852 flags
|= EF_ARM_MAVERICK_FLOAT
;
29855 case EF_ARM_EABI_VER4
:
29856 case EF_ARM_EABI_VER5
:
29857 /* No additional flags to set. */
29864 bfd_set_private_flags (stdoutput
, flags
);
29866 /* We have run out flags in the COFF header to encode the
29867 status of ATPCS support, so instead we create a dummy,
29868 empty, debug section called .arm.atpcs. */
29873 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
29877 bfd_set_section_flags
29878 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
29879 bfd_set_section_size (stdoutput
, sec
, 0);
29880 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
29886 /* Record the CPU type as well. */
29887 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
29888 mach
= bfd_mach_arm_iWMMXt2
;
29889 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
29890 mach
= bfd_mach_arm_iWMMXt
;
29891 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
29892 mach
= bfd_mach_arm_XScale
;
29893 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
29894 mach
= bfd_mach_arm_ep9312
;
29895 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
29896 mach
= bfd_mach_arm_5TE
;
29897 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
29899 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29900 mach
= bfd_mach_arm_5T
;
29902 mach
= bfd_mach_arm_5
;
29904 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
29906 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29907 mach
= bfd_mach_arm_4T
;
29909 mach
= bfd_mach_arm_4
;
29911 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
29912 mach
= bfd_mach_arm_3M
;
29913 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
29914 mach
= bfd_mach_arm_3
;
29915 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
29916 mach
= bfd_mach_arm_2a
;
29917 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
29918 mach
= bfd_mach_arm_2
;
29920 mach
= bfd_mach_arm_unknown
;
29922 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
29925 /* Command line processing. */
29928 Invocation line includes a switch not recognized by the base assembler.
29929 See if it's a processor-specific option.
29931 This routine is somewhat complicated by the need for backwards
29932 compatibility (since older releases of gcc can't be changed).
29933 The new options try to make the interface as compatible as
29936 New options (supported) are:
29938 -mcpu=<cpu name> Assemble for selected processor
29939 -march=<architecture name> Assemble for selected architecture
29940 -mfpu=<fpu architecture> Assemble for selected FPU.
29941 -EB/-mbig-endian Big-endian
29942 -EL/-mlittle-endian Little-endian
29943 -k Generate PIC code
29944 -mthumb Start in Thumb mode
29945 -mthumb-interwork Code supports ARM/Thumb interworking
29947 -m[no-]warn-deprecated Warn about deprecated features
29948 -m[no-]warn-syms Warn when symbols match instructions
29950 For now we will also provide support for:
29952 -mapcs-32 32-bit Program counter
29953 -mapcs-26 26-bit Program counter
29954 -macps-float Floats passed in FP registers
29955 -mapcs-reentrant Reentrant code
29957 (sometime these will probably be replaced with -mapcs=<list of options>
29958 and -matpcs=<list of options>)
29960 The remaining options are only supported for back-wards compatibility.
29961 Cpu variants, the arm part is optional:
29962 -m[arm]1 Currently not supported.
29963 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
29964 -m[arm]3 Arm 3 processor
29965 -m[arm]6[xx], Arm 6 processors
29966 -m[arm]7[xx][t][[d]m] Arm 7 processors
29967 -m[arm]8[10] Arm 8 processors
29968 -m[arm]9[20][tdmi] Arm 9 processors
29969 -mstrongarm[110[0]] StrongARM processors
29970 -mxscale XScale processors
29971 -m[arm]v[2345[t[e]]] Arm architectures
29972 -mall All (except the ARM1)
29974 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
29975 -mfpe-old (No float load/store multiples)
29976 -mvfpxd VFP Single precision
29978 -mno-fpu Disable all floating point instructions
29980 The following CPU names are recognized:
29981 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
29982 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
29983 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
29984 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
29985 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
29986 arm10t arm10e, arm1020t, arm1020e, arm10200e,
29987 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
29991 const char * md_shortopts
= "m:k";
29993 #ifdef ARM_BI_ENDIAN
29994 #define OPTION_EB (OPTION_MD_BASE + 0)
29995 #define OPTION_EL (OPTION_MD_BASE + 1)
29997 #if TARGET_BYTES_BIG_ENDIAN
29998 #define OPTION_EB (OPTION_MD_BASE + 0)
30000 #define OPTION_EL (OPTION_MD_BASE + 1)
30003 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
30004 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
30006 struct option md_longopts
[] =
30009 {"EB", no_argument
, NULL
, OPTION_EB
},
30012 {"EL", no_argument
, NULL
, OPTION_EL
},
30014 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
30016 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
30018 {NULL
, no_argument
, NULL
, 0}
30021 size_t md_longopts_size
= sizeof (md_longopts
);
30023 struct arm_option_table
30025 const char * option
; /* Option name to match. */
30026 const char * help
; /* Help information. */
30027 int * var
; /* Variable to change. */
30028 int value
; /* What to change it to. */
30029 const char * deprecated
; /* If non-null, print this message. */
30032 struct arm_option_table arm_opts
[] =
30034 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
30035 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
30036 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
30037 &support_interwork
, 1, NULL
},
30038 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
30039 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
30040 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
30042 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
30043 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
30044 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
30045 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
30048 /* These are recognized by the assembler, but have no affect on code. */
30049 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
30050 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
30052 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
30053 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
30054 &warn_on_deprecated
, 0, NULL
},
30055 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
30056 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
30057 {NULL
, NULL
, NULL
, 0, NULL
}
30060 struct arm_legacy_option_table
30062 const char * option
; /* Option name to match. */
30063 const arm_feature_set
** var
; /* Variable to change. */
30064 const arm_feature_set value
; /* What to change it to. */
30065 const char * deprecated
; /* If non-null, print this message. */
30068 const struct arm_legacy_option_table arm_legacy_opts
[] =
30070 /* DON'T add any new processors to this list -- we want the whole list
30071 to go away... Add them to the processors table instead. */
30072 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30073 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30074 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30075 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30076 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30077 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30078 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30079 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30080 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30081 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30082 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30083 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30084 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30085 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30086 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30087 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30088 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30089 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30090 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30091 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30092 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30093 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30094 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30095 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30096 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30097 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30098 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30099 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30100 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30101 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30102 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30103 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30104 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30105 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30106 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30107 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30108 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30109 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30110 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30111 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30112 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30113 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30114 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30115 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30116 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30117 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30118 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30119 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30120 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30121 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30122 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30123 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30124 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30125 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30126 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30127 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30128 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30129 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30130 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30131 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30132 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30133 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30134 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30135 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30136 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30137 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30138 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30139 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30140 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
30141 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
30142 N_("use -mcpu=strongarm110")},
30143 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
30144 N_("use -mcpu=strongarm1100")},
30145 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
30146 N_("use -mcpu=strongarm1110")},
30147 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
30148 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
30149 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
30151 /* Architecture variants -- don't add any more to this list either. */
30152 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30153 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30154 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30155 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30156 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30157 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30158 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30159 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30160 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30161 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30162 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30163 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30164 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30165 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30166 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30167 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30168 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30169 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30171 /* Floating point variants -- don't add any more to this list either. */
30172 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
30173 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
30174 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
30175 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
30176 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
30178 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
30181 struct arm_cpu_option_table
30185 const arm_feature_set value
;
30186 const arm_feature_set ext
;
30187 /* For some CPUs we assume an FPU unless the user explicitly sets
30189 const arm_feature_set default_fpu
;
30190 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30192 const char * canonical_name
;
30195 /* This list should, at a minimum, contain all the cpu names
30196 recognized by GCC. */
30197 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
30199 static const struct arm_cpu_option_table arm_cpus
[] =
30201 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
30204 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
30207 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
30210 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
30213 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
30216 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
30219 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
30222 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
30225 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
30228 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
30231 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
30234 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
30237 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
30240 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
30243 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
30246 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
30249 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
30252 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
30255 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
30258 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
30261 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
30264 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
30267 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
30270 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
30273 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30276 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30279 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30282 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30285 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30288 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30291 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30294 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30297 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30300 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30303 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30306 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30309 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30312 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30315 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30318 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30321 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30324 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30327 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30330 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30333 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30336 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30340 /* For V5 or later processors we default to using VFP; but the user
30341 should really set the FPU type explicitly. */
30342 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30345 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30348 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30351 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30354 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30357 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30360 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30363 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30366 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30369 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30372 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30375 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30378 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30381 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30384 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30387 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30390 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30393 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30396 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30399 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30402 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30405 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30408 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30411 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30414 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30417 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30420 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30423 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30426 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30429 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30432 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30435 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30438 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30441 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30444 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30447 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30450 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30451 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30453 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30455 FPU_ARCH_NEON_VFP_V4
),
30456 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30457 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30458 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30459 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30460 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30461 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30462 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30464 FPU_ARCH_NEON_VFP_V4
),
30465 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30467 FPU_ARCH_NEON_VFP_V4
),
30468 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30470 FPU_ARCH_NEON_VFP_V4
),
30471 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30472 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30473 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30474 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30475 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30476 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30477 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30478 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30479 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30480 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30481 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30482 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30483 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30484 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30485 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30486 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30487 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30488 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30489 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30490 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30491 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30492 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30493 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30494 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30495 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30496 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30497 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30498 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30499 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30500 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30501 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30504 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30506 FPU_ARCH_VFP_V3D16
),
30507 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30508 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30510 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30511 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30512 FPU_ARCH_VFP_V3D16
),
30513 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30514 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30515 FPU_ARCH_VFP_V3D16
),
30516 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30517 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30518 FPU_ARCH_NEON_VFP_ARMV8
),
30519 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30520 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30522 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30525 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30528 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30531 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30534 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
30537 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
30540 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
30543 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
30544 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30545 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30546 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
30547 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30548 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30549 /* ??? XSCALE is really an architecture. */
30550 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
30554 /* ??? iwmmxt is not a processor. */
30555 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
30558 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
30561 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
30566 ARM_CPU_OPT ("ep9312", "ARM920T",
30567 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
30568 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
30570 /* Marvell processors. */
30571 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
30572 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30573 FPU_ARCH_VFP_V3D16
),
30574 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
30575 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30576 FPU_ARCH_NEON_VFP_V4
),
30578 /* APM X-Gene family. */
30579 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
30581 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30582 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
30583 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30584 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30586 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30590 struct arm_ext_table
30594 const arm_feature_set merge
;
30595 const arm_feature_set clear
;
30598 struct arm_arch_option_table
30602 const arm_feature_set value
;
30603 const arm_feature_set default_fpu
;
30604 const struct arm_ext_table
* ext_table
;
30607 /* Used to add support for +E and +noE extension. */
30608 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30609 /* Used to add support for a +E extension. */
30610 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30611 /* Used to add support for a +noE extension. */
30612 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30614 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30615 ~0 & ~FPU_ENDIAN_PURE)
30617 static const struct arm_ext_table armv5te_ext_table
[] =
30619 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
30620 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30623 static const struct arm_ext_table armv7_ext_table
[] =
30625 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30626 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30629 static const struct arm_ext_table armv7ve_ext_table
[] =
30631 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
30632 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
30633 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30634 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30635 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30636 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
30637 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30639 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
30640 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30642 /* Aliases for +simd. */
30643 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30645 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30646 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30647 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30649 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30652 static const struct arm_ext_table armv7a_ext_table
[] =
30654 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30655 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30656 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30657 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30658 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30659 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
30660 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30662 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
30663 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30665 /* Aliases for +simd. */
30666 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30667 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30669 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30670 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30672 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
30673 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
30674 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30677 static const struct arm_ext_table armv7r_ext_table
[] =
30679 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
30680 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
30681 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30682 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30683 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
30684 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30685 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30686 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
30687 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30690 static const struct arm_ext_table armv7em_ext_table
[] =
30692 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
30693 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30694 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
30695 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
30696 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30697 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
30698 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30701 static const struct arm_ext_table armv8a_ext_table
[] =
30703 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30704 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30705 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30706 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30708 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30709 should use the +simd option to turn on FP. */
30710 ARM_REMOVE ("fp", ALL_FP
),
30711 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30712 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30713 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30717 static const struct arm_ext_table armv81a_ext_table
[] =
30719 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30720 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30721 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30723 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30724 should use the +simd option to turn on FP. */
30725 ARM_REMOVE ("fp", ALL_FP
),
30726 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30727 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30728 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30731 static const struct arm_ext_table armv82a_ext_table
[] =
30733 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30734 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
30735 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
30736 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30737 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30738 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30740 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30741 should use the +simd option to turn on FP. */
30742 ARM_REMOVE ("fp", ALL_FP
),
30743 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30744 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30745 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30748 static const struct arm_ext_table armv84a_ext_table
[] =
30750 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30751 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30752 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30753 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30755 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30756 should use the +simd option to turn on FP. */
30757 ARM_REMOVE ("fp", ALL_FP
),
30758 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30759 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30760 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30763 static const struct arm_ext_table armv85a_ext_table
[] =
30765 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30766 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30767 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30768 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30770 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30771 should use the +simd option to turn on FP. */
30772 ARM_REMOVE ("fp", ALL_FP
),
30773 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30776 static const struct arm_ext_table armv8m_main_ext_table
[] =
30778 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30779 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30780 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
30781 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30782 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30785 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
30787 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30788 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30790 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30791 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
30794 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30795 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30796 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
30797 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
30799 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30800 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
30801 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30802 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30805 static const struct arm_ext_table armv8r_ext_table
[] =
30807 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30808 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30809 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30810 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30811 ARM_REMOVE ("fp", ALL_FP
),
30812 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
30813 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30816 /* This list should, at a minimum, contain all the architecture names
30817 recognized by GCC. */
30818 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30819 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30820 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30822 static const struct arm_arch_option_table arm_archs
[] =
30824 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
30825 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
30826 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
30827 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30828 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30829 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
30830 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
30831 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
30832 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
30833 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
30834 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
30835 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
30836 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
30837 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
30838 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
30839 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
30840 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
30841 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30842 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30843 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
30844 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
30845 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30846 kept to preserve existing behaviour. */
30847 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30848 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30849 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
30850 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
30851 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
30852 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30853 kept to preserve existing behaviour. */
30854 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30855 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30856 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
30857 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
30858 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
30859 /* The official spelling of the ARMv7 profile variants is the dashed form.
30860 Accept the non-dashed form for compatibility with old toolchains. */
30861 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30862 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
30863 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30864 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30865 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30866 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30867 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30868 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
30869 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
30870 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
30872 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
30874 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
30875 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
30876 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
30877 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
30878 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
30879 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
30880 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
30881 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
30882 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
30883 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
30884 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30886 #undef ARM_ARCH_OPT
30888 /* ISA extensions in the co-processor and main instruction set space. */
30890 struct arm_option_extension_value_table
30894 const arm_feature_set merge_value
;
30895 const arm_feature_set clear_value
;
30896 /* List of architectures for which an extension is available. ARM_ARCH_NONE
30897 indicates that an extension is available for all architectures while
30898 ARM_ANY marks an empty entry. */
30899 const arm_feature_set allowed_archs
[2];
30902 /* The following table must be in alphabetical order with a NULL last entry. */
30904 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
30905 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
30907 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
30908 use the context sensitive approach using arm_ext_table's. */
30909 static const struct arm_option_extension_value_table arm_extensions
[] =
30911 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30912 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30913 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30914 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
30915 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30916 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
30917 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
30919 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30920 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30921 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
30922 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
30923 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30924 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30925 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30927 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30928 | ARM_EXT2_FP16_FML
),
30929 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30930 | ARM_EXT2_FP16_FML
),
30932 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30933 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30934 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30935 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30936 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
30937 Thumb divide instruction. Due to this having the same name as the
30938 previous entry, this will be ignored when doing command-line parsing and
30939 only considered by build attribute selection code. */
30940 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30941 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30942 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
30943 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
30944 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
30945 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
30946 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
30947 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
30948 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
30949 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30950 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30951 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30952 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30953 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30954 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30955 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
30956 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
30957 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
30958 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30959 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30960 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30962 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
30963 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
30964 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30965 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
30966 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
30967 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30968 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30969 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30971 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30972 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30973 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
30974 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30975 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
30976 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
30977 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30978 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
30980 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
30981 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30982 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
30983 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
30984 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
30988 /* ISA floating-point and Advanced SIMD extensions. */
30989 struct arm_option_fpu_value_table
30992 const arm_feature_set value
;
30995 /* This list should, at a minimum, contain all the fpu names
30996 recognized by GCC. */
30997 static const struct arm_option_fpu_value_table arm_fpus
[] =
30999 {"softfpa", FPU_NONE
},
31000 {"fpe", FPU_ARCH_FPE
},
31001 {"fpe2", FPU_ARCH_FPE
},
31002 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
31003 {"fpa", FPU_ARCH_FPA
},
31004 {"fpa10", FPU_ARCH_FPA
},
31005 {"fpa11", FPU_ARCH_FPA
},
31006 {"arm7500fe", FPU_ARCH_FPA
},
31007 {"softvfp", FPU_ARCH_VFP
},
31008 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
31009 {"vfp", FPU_ARCH_VFP_V2
},
31010 {"vfp9", FPU_ARCH_VFP_V2
},
31011 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
31012 {"vfp10", FPU_ARCH_VFP_V2
},
31013 {"vfp10-r0", FPU_ARCH_VFP_V1
},
31014 {"vfpxd", FPU_ARCH_VFP_V1xD
},
31015 {"vfpv2", FPU_ARCH_VFP_V2
},
31016 {"vfpv3", FPU_ARCH_VFP_V3
},
31017 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
31018 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
31019 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
31020 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
31021 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
31022 {"arm1020t", FPU_ARCH_VFP_V1
},
31023 {"arm1020e", FPU_ARCH_VFP_V2
},
31024 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
31025 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
31026 {"maverick", FPU_ARCH_MAVERICK
},
31027 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31028 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31029 {"neon-fp16", FPU_ARCH_NEON_FP16
},
31030 {"vfpv4", FPU_ARCH_VFP_V4
},
31031 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
31032 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
31033 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
31034 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
31035 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
31036 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
31037 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
31038 {"crypto-neon-fp-armv8",
31039 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
31040 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
31041 {"crypto-neon-fp-armv8.1",
31042 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
31043 {NULL
, ARM_ARCH_NONE
}
31046 struct arm_option_value_table
31052 static const struct arm_option_value_table arm_float_abis
[] =
31054 {"hard", ARM_FLOAT_ABI_HARD
},
31055 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
31056 {"soft", ARM_FLOAT_ABI_SOFT
},
31061 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
31062 static const struct arm_option_value_table arm_eabis
[] =
31064 {"gnu", EF_ARM_EABI_UNKNOWN
},
31065 {"4", EF_ARM_EABI_VER4
},
31066 {"5", EF_ARM_EABI_VER5
},
31071 struct arm_long_option_table
31073 const char * option
; /* Substring to match. */
31074 const char * help
; /* Help information. */
31075 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
31076 const char * deprecated
; /* If non-null, print this message. */
31080 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
31081 arm_feature_set
*ext_set
,
31082 const struct arm_ext_table
*ext_table
)
31084 /* We insist on extensions being specified in alphabetical order, and with
31085 extensions being added before being removed. We achieve this by having
31086 the global ARM_EXTENSIONS table in alphabetical order, and using the
31087 ADDING_VALUE variable to indicate whether we are adding an extension (1)
31088 or removing it (0) and only allowing it to change in the order
31090 const struct arm_option_extension_value_table
* opt
= NULL
;
31091 const arm_feature_set arm_any
= ARM_ANY
;
31092 int adding_value
= -1;
31094 while (str
!= NULL
&& *str
!= 0)
31101 as_bad (_("invalid architectural extension"));
31106 ext
= strchr (str
, '+');
31111 len
= strlen (str
);
31113 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
31115 if (adding_value
!= 0)
31118 opt
= arm_extensions
;
31126 if (adding_value
== -1)
31129 opt
= arm_extensions
;
31131 else if (adding_value
!= 1)
31133 as_bad (_("must specify extensions to add before specifying "
31134 "those to remove"));
31141 as_bad (_("missing architectural extension"));
31145 gas_assert (adding_value
!= -1);
31146 gas_assert (opt
!= NULL
);
31148 if (ext_table
!= NULL
)
31150 const struct arm_ext_table
* ext_opt
= ext_table
;
31151 bfd_boolean found
= FALSE
;
31152 for (; ext_opt
->name
!= NULL
; ext_opt
++)
31153 if (ext_opt
->name_len
== len
31154 && strncmp (ext_opt
->name
, str
, len
) == 0)
31158 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
31159 /* TODO: Option not supported. When we remove the
31160 legacy table this case should error out. */
31163 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
31167 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
31168 /* TODO: Option not supported. When we remove the
31169 legacy table this case should error out. */
31171 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
31183 /* Scan over the options table trying to find an exact match. */
31184 for (; opt
->name
!= NULL
; opt
++)
31185 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31187 int i
, nb_allowed_archs
=
31188 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31189 /* Check we can apply the extension to this architecture. */
31190 for (i
= 0; i
< nb_allowed_archs
; i
++)
31193 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
31195 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
31198 if (i
== nb_allowed_archs
)
31200 as_bad (_("extension does not apply to the base architecture"));
31204 /* Add or remove the extension. */
31206 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
31208 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
31210 /* Allowing Thumb division instructions for ARMv7 in autodetection
31211 rely on this break so that duplicate extensions (extensions
31212 with the same name as a previous extension in the list) are not
31213 considered for command-line parsing. */
31217 if (opt
->name
== NULL
)
31219 /* Did we fail to find an extension because it wasn't specified in
31220 alphabetical order, or because it does not exist? */
31222 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31223 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31226 if (opt
->name
== NULL
)
31227 as_bad (_("unknown architectural extension `%s'"), str
);
31229 as_bad (_("architectural extensions must be specified in "
31230 "alphabetical order"));
31236 /* We should skip the extension we've just matched the next time
31248 arm_parse_cpu (const char *str
)
31250 const struct arm_cpu_option_table
*opt
;
31251 const char *ext
= strchr (str
, '+');
31257 len
= strlen (str
);
31261 as_bad (_("missing cpu name `%s'"), str
);
31265 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
31266 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31268 mcpu_cpu_opt
= &opt
->value
;
31269 if (mcpu_ext_opt
== NULL
)
31270 mcpu_ext_opt
= XNEW (arm_feature_set
);
31271 *mcpu_ext_opt
= opt
->ext
;
31272 mcpu_fpu_opt
= &opt
->default_fpu
;
31273 if (opt
->canonical_name
)
31275 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31276 strcpy (selected_cpu_name
, opt
->canonical_name
);
31282 if (len
>= sizeof selected_cpu_name
)
31283 len
= (sizeof selected_cpu_name
) - 1;
31285 for (i
= 0; i
< len
; i
++)
31286 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31287 selected_cpu_name
[i
] = 0;
31291 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31296 as_bad (_("unknown cpu `%s'"), str
);
31301 arm_parse_arch (const char *str
)
31303 const struct arm_arch_option_table
*opt
;
31304 const char *ext
= strchr (str
, '+');
31310 len
= strlen (str
);
31314 as_bad (_("missing architecture name `%s'"), str
);
31318 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31319 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31321 march_cpu_opt
= &opt
->value
;
31322 if (march_ext_opt
== NULL
)
31323 march_ext_opt
= XNEW (arm_feature_set
);
31324 *march_ext_opt
= arm_arch_none
;
31325 march_fpu_opt
= &opt
->default_fpu
;
31326 strcpy (selected_cpu_name
, opt
->name
);
31329 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31335 as_bad (_("unknown architecture `%s'\n"), str
);
31340 arm_parse_fpu (const char * str
)
31342 const struct arm_option_fpu_value_table
* opt
;
31344 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31345 if (streq (opt
->name
, str
))
31347 mfpu_opt
= &opt
->value
;
31351 as_bad (_("unknown floating point format `%s'\n"), str
);
31356 arm_parse_float_abi (const char * str
)
31358 const struct arm_option_value_table
* opt
;
31360 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31361 if (streq (opt
->name
, str
))
31363 mfloat_abi_opt
= opt
->value
;
31367 as_bad (_("unknown floating point abi `%s'\n"), str
);
31373 arm_parse_eabi (const char * str
)
31375 const struct arm_option_value_table
*opt
;
31377 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31378 if (streq (opt
->name
, str
))
31380 meabi_flags
= opt
->value
;
31383 as_bad (_("unknown EABI `%s'\n"), str
);
31389 arm_parse_it_mode (const char * str
)
31391 bfd_boolean ret
= TRUE
;
31393 if (streq ("arm", str
))
31394 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31395 else if (streq ("thumb", str
))
31396 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31397 else if (streq ("always", str
))
31398 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31399 else if (streq ("never", str
))
31400 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31403 as_bad (_("unknown implicit IT mode `%s', should be "\
31404 "arm, thumb, always, or never."), str
);
31412 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31414 codecomposer_syntax
= TRUE
;
31415 arm_comment_chars
[0] = ';';
31416 arm_line_separator_chars
[0] = 0;
31420 struct arm_long_option_table arm_long_opts
[] =
31422 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31423 arm_parse_cpu
, NULL
},
31424 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31425 arm_parse_arch
, NULL
},
31426 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31427 arm_parse_fpu
, NULL
},
31428 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31429 arm_parse_float_abi
, NULL
},
31431 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31432 arm_parse_eabi
, NULL
},
31434 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31435 arm_parse_it_mode
, NULL
},
31436 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31437 arm_ccs_mode
, NULL
},
31438 {NULL
, NULL
, 0, NULL
}
31442 md_parse_option (int c
, const char * arg
)
31444 struct arm_option_table
*opt
;
31445 const struct arm_legacy_option_table
*fopt
;
31446 struct arm_long_option_table
*lopt
;
31452 target_big_endian
= 1;
31458 target_big_endian
= 0;
31462 case OPTION_FIX_V4BX
:
31470 #endif /* OBJ_ELF */
31473 /* Listing option. Just ignore these, we don't support additional
31478 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31480 if (c
== opt
->option
[0]
31481 && ((arg
== NULL
&& opt
->option
[1] == 0)
31482 || streq (arg
, opt
->option
+ 1)))
31484 /* If the option is deprecated, tell the user. */
31485 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31486 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31487 arg
? arg
: "", _(opt
->deprecated
));
31489 if (opt
->var
!= NULL
)
31490 *opt
->var
= opt
->value
;
31496 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31498 if (c
== fopt
->option
[0]
31499 && ((arg
== NULL
&& fopt
->option
[1] == 0)
31500 || streq (arg
, fopt
->option
+ 1)))
31502 /* If the option is deprecated, tell the user. */
31503 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
31504 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31505 arg
? arg
: "", _(fopt
->deprecated
));
31507 if (fopt
->var
!= NULL
)
31508 *fopt
->var
= &fopt
->value
;
31514 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31516 /* These options are expected to have an argument. */
31517 if (c
== lopt
->option
[0]
31519 && strncmp (arg
, lopt
->option
+ 1,
31520 strlen (lopt
->option
+ 1)) == 0)
31522 /* If the option is deprecated, tell the user. */
31523 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
31524 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
31525 _(lopt
->deprecated
));
31527 /* Call the sup-option parser. */
31528 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
31539 md_show_usage (FILE * fp
)
31541 struct arm_option_table
*opt
;
31542 struct arm_long_option_table
*lopt
;
31544 fprintf (fp
, _(" ARM-specific assembler options:\n"));
31546 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31547 if (opt
->help
!= NULL
)
31548 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
31550 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31551 if (lopt
->help
!= NULL
)
31552 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
31556 -EB assemble code for a big-endian cpu\n"));
31561 -EL assemble code for a little-endian cpu\n"));
31565 --fix-v4bx Allow BX in ARMv4 code\n"));
31569 --fdpic generate an FDPIC object file\n"));
31570 #endif /* OBJ_ELF */
31578 arm_feature_set flags
;
31579 } cpu_arch_ver_table
;
31581 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31582 chronologically for architectures, with an exception for ARMv6-M and
31583 ARMv6S-M due to legacy reasons. No new architecture should have a
31584 special case. This allows for build attribute selection results to be
31585 stable when new architectures are added. */
31586 static const cpu_arch_ver_table cpu_arch_ver
[] =
31588 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
31589 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
31590 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
31591 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
31592 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
31593 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
31594 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
31595 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
31596 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
31597 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
31598 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
31599 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
31600 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
31601 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
31602 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
31603 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
31604 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
31605 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
31606 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
31607 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
31608 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
31609 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
31610 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
31611 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
31613 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31614 always selected build attributes to match those of ARMv6-M
31615 (resp. ARMv6S-M). However, due to these architectures being a strict
31616 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31617 would be selected when fully respecting chronology of architectures.
31618 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31619 move them before ARMv7 architectures. */
31620 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
31621 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
31623 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
31624 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
31625 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
31626 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
31627 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
31628 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
31629 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
31630 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
31631 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
31632 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
31633 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
31634 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
31635 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
31636 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
31637 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
31638 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
31639 {-1, ARM_ARCH_NONE
}
31642 /* Set an attribute if it has not already been set by the user. */
31645 aeabi_set_attribute_int (int tag
, int value
)
31648 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31649 || !attributes_set_explicitly
[tag
])
31650 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
31654 aeabi_set_attribute_string (int tag
, const char *value
)
31657 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31658 || !attributes_set_explicitly
[tag
])
31659 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
31662 /* Return whether features in the *NEEDED feature set are available via
31663 extensions for the architecture whose feature set is *ARCH_FSET. */
31666 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
31667 const arm_feature_set
*needed
)
31669 int i
, nb_allowed_archs
;
31670 arm_feature_set ext_fset
;
31671 const struct arm_option_extension_value_table
*opt
;
31673 ext_fset
= arm_arch_none
;
31674 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31676 /* Extension does not provide any feature we need. */
31677 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
31681 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31682 for (i
= 0; i
< nb_allowed_archs
; i
++)
31685 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
31688 /* Extension is available, add it. */
31689 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
31690 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
31694 /* Can we enable all features in *needed? */
31695 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
31698 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31699 a given architecture feature set *ARCH_EXT_FSET including extension feature
31700 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31701 - if true, check for an exact match of the architecture modulo extensions;
31702 - otherwise, select build attribute value of the first superset
31703 architecture released so that results remains stable when new architectures
31705 For -march/-mcpu=all the build attribute value of the most featureful
31706 architecture is returned. Tag_CPU_arch_profile result is returned in
31710 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
31711 const arm_feature_set
*ext_fset
,
31712 char *profile
, int exact_match
)
31714 arm_feature_set arch_fset
;
31715 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
31717 /* Select most featureful architecture with all its extensions if building
31718 for -march=all as the feature sets used to set build attributes. */
31719 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
31721 /* Force revisiting of decision for each new architecture. */
31722 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31724 return TAG_CPU_ARCH_V8
;
31727 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
31729 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
31731 arm_feature_set known_arch_fset
;
31733 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
31736 /* Base architecture match user-specified architecture and
31737 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31738 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
31743 /* Base architecture match user-specified architecture only
31744 (eg. ARMv6-M in the same case as above). Record it in case we
31745 find a match with above condition. */
31746 else if (p_ver_ret
== NULL
31747 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
31753 /* Architecture has all features wanted. */
31754 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
31756 arm_feature_set added_fset
;
31758 /* Compute features added by this architecture over the one
31759 recorded in p_ver_ret. */
31760 if (p_ver_ret
!= NULL
)
31761 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
31763 /* First architecture that match incl. with extensions, or the
31764 only difference in features over the recorded match is
31765 features that were optional and are now mandatory. */
31766 if (p_ver_ret
== NULL
31767 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
31773 else if (p_ver_ret
== NULL
)
31775 arm_feature_set needed_ext_fset
;
31777 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
31779 /* Architecture has all features needed when using some
31780 extensions. Record it and continue searching in case there
31781 exist an architecture providing all needed features without
31782 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31784 if (have_ext_for_needed_feat_p (&known_arch_fset
,
31791 if (p_ver_ret
== NULL
)
31795 /* Tag_CPU_arch_profile. */
31796 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
31797 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
31798 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
31799 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
31801 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
31803 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
31807 return p_ver_ret
->val
;
31810 /* Set the public EABI object attributes. */
31813 aeabi_set_public_attributes (void)
31815 char profile
= '\0';
31818 int fp16_optional
= 0;
31819 int skip_exact_match
= 0;
31820 arm_feature_set flags
, flags_arch
, flags_ext
;
31822 /* Autodetection mode, choose the architecture based the instructions
31824 if (no_cpu_selected ())
31826 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
31828 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
31829 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
31831 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
31832 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
31834 /* Code run during relaxation relies on selected_cpu being set. */
31835 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31836 flags_ext
= arm_arch_none
;
31837 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
31838 selected_ext
= flags_ext
;
31839 selected_cpu
= flags
;
31841 /* Otherwise, choose the architecture based on the capabilities of the
31845 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
31846 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
31847 flags_ext
= selected_ext
;
31848 flags
= selected_cpu
;
31850 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
31852 /* Allow the user to override the reported architecture. */
31853 if (!ARM_FEATURE_ZERO (selected_object_arch
))
31855 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
31856 flags_ext
= arm_arch_none
;
31859 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
31861 /* When this function is run again after relaxation has happened there is no
31862 way to determine whether an architecture or CPU was specified by the user:
31863 - selected_cpu is set above for relaxation to work;
31864 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31865 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31866 Therefore, if not in -march=all case we first try an exact match and fall
31867 back to autodetection. */
31868 if (!skip_exact_match
)
31869 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
31871 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
31873 as_bad (_("no architecture contains all the instructions used\n"));
31875 /* Tag_CPU_name. */
31876 if (selected_cpu_name
[0])
31880 q
= selected_cpu_name
;
31881 if (strncmp (q
, "armv", 4) == 0)
31886 for (i
= 0; q
[i
]; i
++)
31887 q
[i
] = TOUPPER (q
[i
]);
31889 aeabi_set_attribute_string (Tag_CPU_name
, q
);
31892 /* Tag_CPU_arch. */
31893 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
31895 /* Tag_CPU_arch_profile. */
31896 if (profile
!= '\0')
31897 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
31899 /* Tag_DSP_extension. */
31900 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
31901 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
31903 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31904 /* Tag_ARM_ISA_use. */
31905 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
31906 || ARM_FEATURE_ZERO (flags_arch
))
31907 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
31909 /* Tag_THUMB_ISA_use. */
31910 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
31911 || ARM_FEATURE_ZERO (flags_arch
))
31915 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31916 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
31918 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
31922 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
31925 /* Tag_VFP_arch. */
31926 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
31927 aeabi_set_attribute_int (Tag_VFP_arch
,
31928 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31930 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
31931 aeabi_set_attribute_int (Tag_VFP_arch
,
31932 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31934 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
31937 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
31939 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
31941 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
31944 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
31945 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
31946 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
31947 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
31948 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
31950 /* Tag_ABI_HardFP_use. */
31951 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
31952 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
31953 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
31955 /* Tag_WMMX_arch. */
31956 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
31957 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
31958 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
31959 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
31961 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
31962 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
31963 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
31964 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
31965 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
31966 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
31968 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
31970 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
31974 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
31979 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
31980 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
31981 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
31982 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
31984 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
31985 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
31986 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
31990 We set Tag_DIV_use to two when integer divide instructions have been used
31991 in ARM state, or when Thumb integer divide instructions have been used,
31992 but we have no architecture profile set, nor have we any ARM instructions.
31994 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
31995 by the base architecture.
31997 For new architectures we will have to check these tests. */
31998 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31999 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32000 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
32001 aeabi_set_attribute_int (Tag_DIV_use
, 0);
32002 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
32003 || (profile
== '\0'
32004 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
32005 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
32006 aeabi_set_attribute_int (Tag_DIV_use
, 2);
32008 /* Tag_MP_extension_use. */
32009 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
32010 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
32012 /* Tag Virtualization_use. */
32013 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
32015 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
32018 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
32021 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
32022 finished and free extension feature bits which will not be used anymore. */
32025 arm_md_post_relax (void)
32027 aeabi_set_public_attributes ();
32028 XDELETE (mcpu_ext_opt
);
32029 mcpu_ext_opt
= NULL
;
32030 XDELETE (march_ext_opt
);
32031 march_ext_opt
= NULL
;
32034 /* Add the default contents for the .ARM.attributes section. */
32039 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
32042 aeabi_set_public_attributes ();
32044 #endif /* OBJ_ELF */
32046 /* Parse a .cpu directive. */
32049 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
32051 const struct arm_cpu_option_table
*opt
;
32055 name
= input_line_pointer
;
32056 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32057 input_line_pointer
++;
32058 saved_char
= *input_line_pointer
;
32059 *input_line_pointer
= 0;
32061 /* Skip the first "all" entry. */
32062 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
32063 if (streq (opt
->name
, name
))
32065 selected_arch
= opt
->value
;
32066 selected_ext
= opt
->ext
;
32067 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32068 if (opt
->canonical_name
)
32069 strcpy (selected_cpu_name
, opt
->canonical_name
);
32073 for (i
= 0; opt
->name
[i
]; i
++)
32074 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32076 selected_cpu_name
[i
] = 0;
32078 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32080 *input_line_pointer
= saved_char
;
32081 demand_empty_rest_of_line ();
32084 as_bad (_("unknown cpu `%s'"), name
);
32085 *input_line_pointer
= saved_char
;
32086 ignore_rest_of_line ();
32089 /* Parse a .arch directive. */
32092 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
32094 const struct arm_arch_option_table
*opt
;
32098 name
= input_line_pointer
;
32099 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32100 input_line_pointer
++;
32101 saved_char
= *input_line_pointer
;
32102 *input_line_pointer
= 0;
32104 /* Skip the first "all" entry. */
32105 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32106 if (streq (opt
->name
, name
))
32108 selected_arch
= opt
->value
;
32109 selected_ext
= arm_arch_none
;
32110 selected_cpu
= selected_arch
;
32111 strcpy (selected_cpu_name
, opt
->name
);
32112 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32113 *input_line_pointer
= saved_char
;
32114 demand_empty_rest_of_line ();
32118 as_bad (_("unknown architecture `%s'\n"), name
);
32119 *input_line_pointer
= saved_char
;
32120 ignore_rest_of_line ();
32123 /* Parse a .object_arch directive. */
32126 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
32128 const struct arm_arch_option_table
*opt
;
32132 name
= input_line_pointer
;
32133 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32134 input_line_pointer
++;
32135 saved_char
= *input_line_pointer
;
32136 *input_line_pointer
= 0;
32138 /* Skip the first "all" entry. */
32139 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32140 if (streq (opt
->name
, name
))
32142 selected_object_arch
= opt
->value
;
32143 *input_line_pointer
= saved_char
;
32144 demand_empty_rest_of_line ();
32148 as_bad (_("unknown architecture `%s'\n"), name
);
32149 *input_line_pointer
= saved_char
;
32150 ignore_rest_of_line ();
32153 /* Parse a .arch_extension directive. */
32156 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
32158 const struct arm_option_extension_value_table
*opt
;
32161 int adding_value
= 1;
32163 name
= input_line_pointer
;
32164 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32165 input_line_pointer
++;
32166 saved_char
= *input_line_pointer
;
32167 *input_line_pointer
= 0;
32169 if (strlen (name
) >= 2
32170 && strncmp (name
, "no", 2) == 0)
32176 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32177 if (streq (opt
->name
, name
))
32179 int i
, nb_allowed_archs
=
32180 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
32181 for (i
= 0; i
< nb_allowed_archs
; i
++)
32184 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
32186 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
32190 if (i
== nb_allowed_archs
)
32192 as_bad (_("architectural extension `%s' is not allowed for the "
32193 "current base architecture"), name
);
32198 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32201 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
32203 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32204 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32205 *input_line_pointer
= saved_char
;
32206 demand_empty_rest_of_line ();
32207 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32208 on this return so that duplicate extensions (extensions with the
32209 same name as a previous extension in the list) are not considered
32210 for command-line parsing. */
32214 if (opt
->name
== NULL
)
32215 as_bad (_("unknown architecture extension `%s'\n"), name
);
32217 *input_line_pointer
= saved_char
;
32218 ignore_rest_of_line ();
32221 /* Parse a .fpu directive. */
32224 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
32226 const struct arm_option_fpu_value_table
*opt
;
32230 name
= input_line_pointer
;
32231 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32232 input_line_pointer
++;
32233 saved_char
= *input_line_pointer
;
32234 *input_line_pointer
= 0;
32236 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32237 if (streq (opt
->name
, name
))
32239 selected_fpu
= opt
->value
;
32240 #ifndef CPU_DEFAULT
32241 if (no_cpu_selected ())
32242 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
32245 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32246 *input_line_pointer
= saved_char
;
32247 demand_empty_rest_of_line ();
32251 as_bad (_("unknown floating point format `%s'\n"), name
);
32252 *input_line_pointer
= saved_char
;
32253 ignore_rest_of_line ();
32256 /* Copy symbol information. */
32259 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
32261 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
32265 /* Given a symbolic attribute NAME, return the proper integer value.
32266 Returns -1 if the attribute is not known. */
32269 arm_convert_symbolic_attribute (const char *name
)
32271 static const struct
32276 attribute_table
[] =
32278 /* When you modify this table you should
32279 also modify the list in doc/c-arm.texi. */
32280 #define T(tag) {#tag, tag}
32281 T (Tag_CPU_raw_name
),
32284 T (Tag_CPU_arch_profile
),
32285 T (Tag_ARM_ISA_use
),
32286 T (Tag_THUMB_ISA_use
),
32290 T (Tag_Advanced_SIMD_arch
),
32291 T (Tag_PCS_config
),
32292 T (Tag_ABI_PCS_R9_use
),
32293 T (Tag_ABI_PCS_RW_data
),
32294 T (Tag_ABI_PCS_RO_data
),
32295 T (Tag_ABI_PCS_GOT_use
),
32296 T (Tag_ABI_PCS_wchar_t
),
32297 T (Tag_ABI_FP_rounding
),
32298 T (Tag_ABI_FP_denormal
),
32299 T (Tag_ABI_FP_exceptions
),
32300 T (Tag_ABI_FP_user_exceptions
),
32301 T (Tag_ABI_FP_number_model
),
32302 T (Tag_ABI_align_needed
),
32303 T (Tag_ABI_align8_needed
),
32304 T (Tag_ABI_align_preserved
),
32305 T (Tag_ABI_align8_preserved
),
32306 T (Tag_ABI_enum_size
),
32307 T (Tag_ABI_HardFP_use
),
32308 T (Tag_ABI_VFP_args
),
32309 T (Tag_ABI_WMMX_args
),
32310 T (Tag_ABI_optimization_goals
),
32311 T (Tag_ABI_FP_optimization_goals
),
32312 T (Tag_compatibility
),
32313 T (Tag_CPU_unaligned_access
),
32314 T (Tag_FP_HP_extension
),
32315 T (Tag_VFP_HP_extension
),
32316 T (Tag_ABI_FP_16bit_format
),
32317 T (Tag_MPextension_use
),
32319 T (Tag_nodefaults
),
32320 T (Tag_also_compatible_with
),
32321 T (Tag_conformance
),
32323 T (Tag_Virtualization_use
),
32324 T (Tag_DSP_extension
),
32326 /* We deliberately do not include Tag_MPextension_use_legacy. */
32334 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32335 if (streq (name
, attribute_table
[i
].name
))
32336 return attribute_table
[i
].tag
;
32341 /* Apply sym value for relocations only in the case that they are for
32342 local symbols in the same segment as the fixup and you have the
32343 respective architectural feature for blx and simple switches. */
32346 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32349 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32350 /* PR 17444: If the local symbol is in a different section then a reloc
32351 will always be generated for it, so applying the symbol value now
32352 will result in a double offset being stored in the relocation. */
32353 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32354 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32356 switch (fixP
->fx_r_type
)
32358 case BFD_RELOC_ARM_PCREL_BLX
:
32359 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32360 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32364 case BFD_RELOC_ARM_PCREL_CALL
:
32365 case BFD_RELOC_THUMB_PCREL_BLX
:
32366 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32377 #endif /* OBJ_ELF */