1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_v8
= ARM_FEATURE (ARM_EXT_V8
, 0);
199 static const arm_feature_set arm_ext_m
=
200 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
202 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
203 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
204 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
205 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
207 static const arm_feature_set arm_arch_any
= ARM_ANY
;
208 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
209 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
210 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
211 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
213 static const arm_feature_set arm_cext_iwmmxt2
=
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
215 static const arm_feature_set arm_cext_iwmmxt
=
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
217 static const arm_feature_set arm_cext_xscale
=
218 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
219 static const arm_feature_set arm_cext_maverick
=
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
221 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
222 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
223 static const arm_feature_set fpu_vfp_ext_v1xd
=
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
225 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
226 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
227 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
228 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
229 static const arm_feature_set fpu_vfp_ext_d32
=
230 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
231 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
232 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
233 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
234 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
235 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
236 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static const arm_feature_set fpu_vfp_ext_armv8
=
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8
);
239 static const arm_feature_set fpu_vfp_ext_armv8xd
=
240 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8xD
);
241 static const arm_feature_set fpu_neon_ext_armv8
=
242 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8
);
243 static const arm_feature_set fpu_crypto_ext_armv8
=
244 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8
);
245 static const arm_feature_set crc_ext_armv8
=
246 ARM_FEATURE (0, CRC_EXT_ARMV8
);
248 static int mfloat_abi_opt
= -1;
249 /* Record user cpu selection for object attributes. */
250 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
251 /* Must be long enough to hold any of the names in arm_cpus. */
252 static char selected_cpu_name
[16];
254 extern FLONUM_TYPE generic_floating_point_number
;
256 /* Return if no cpu was selected on command-line. */
258 no_cpu_selected (void)
260 return selected_cpu
.core
== arm_arch_none
.core
261 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
266 static int meabi_flags
= EABI_DEFAULT
;
268 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
271 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
276 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
281 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
282 symbolS
* GOT_symbol
;
285 /* 0: assemble for ARM,
286 1: assemble for Thumb,
287 2: assemble for Thumb even though target CPU does not support thumb
289 static int thumb_mode
= 0;
290 /* A value distinct from the possible values for thumb_mode that we
291 can use to record whether thumb_mode has been copied into the
292 tc_frag_data field of a frag. */
293 #define MODE_RECORDED (1 << 4)
295 /* Specifies the intrinsic IT insn behavior mode. */
296 enum implicit_it_mode
298 IMPLICIT_IT_MODE_NEVER
= 0x00,
299 IMPLICIT_IT_MODE_ARM
= 0x01,
300 IMPLICIT_IT_MODE_THUMB
= 0x02,
301 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
303 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
305 /* If unified_syntax is true, we are processing the new unified
306 ARM/Thumb syntax. Important differences from the old ARM mode:
308 - Immediate operands do not require a # prefix.
309 - Conditional affixes always appear at the end of the
310 instruction. (For backward compatibility, those instructions
311 that formerly had them in the middle, continue to accept them
313 - The IT instruction may appear, and if it does is validated
314 against subsequent conditional affixes. It does not generate
317 Important differences from the old Thumb mode:
319 - Immediate operands do not require a # prefix.
320 - Most of the V6T2 instructions are only available in unified mode.
321 - The .N and .W suffixes are recognized and honored (it is an error
322 if they cannot be honored).
323 - All instructions set the flags if and only if they have an 's' affix.
324 - Conditional affixes may be used. They are validated against
325 preceding IT instructions. Unlike ARM mode, you cannot use a
326 conditional affix except in the scope of an IT instruction. */
328 static bfd_boolean unified_syntax
= FALSE
;
330 /* An immediate operand can start with #, and ld*, st*, pld operands
331 can contain [ and ]. We need to tell APP not to elide whitespace
332 before a [, which can appear as the first operand for pld.
333 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
334 const char arm_symbol_chars
[] = "#[]{}";
349 enum neon_el_type type
;
353 #define NEON_MAX_TYPE_ELS 4
357 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
361 enum it_instruction_type
366 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
367 if inside, should be the last one. */
368 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
369 i.e. BKPT and NOP. */
370 IT_INSN
/* The IT insn has been parsed. */
373 /* The maximum number of operands we need. */
374 #define ARM_IT_MAX_OPERANDS 6
379 unsigned long instruction
;
383 /* "uncond_value" is set to the value in place of the conditional field in
384 unconditional versions of the instruction, or -1 if nothing is
387 struct neon_type vectype
;
388 /* This does not indicate an actual NEON instruction, only that
389 the mnemonic accepts neon-style type suffixes. */
391 /* Set to the opcode if the instruction needs relaxation.
392 Zero if the instruction is not relaxed. */
396 bfd_reloc_code_real_type type
;
401 enum it_instruction_type it_insn_type
;
407 struct neon_type_el vectype
;
408 unsigned present
: 1; /* Operand present. */
409 unsigned isreg
: 1; /* Operand was a register. */
410 unsigned immisreg
: 1; /* .imm field is a second register. */
411 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
412 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
413 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
414 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
415 instructions. This allows us to disambiguate ARM <-> vector insns. */
416 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
417 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
418 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
419 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
420 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
421 unsigned writeback
: 1; /* Operand has trailing ! */
422 unsigned preind
: 1; /* Preindexed address. */
423 unsigned postind
: 1; /* Postindexed address. */
424 unsigned negative
: 1; /* Index register was negated. */
425 unsigned shifted
: 1; /* Shift applied to operation. */
426 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
427 } operands
[ARM_IT_MAX_OPERANDS
];
430 static struct arm_it inst
;
432 #define NUM_FLOAT_VALS 8
434 const char * fp_const
[] =
436 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
439 /* Number of littlenums required to hold an extended precision number. */
440 #define MAX_LITTLENUMS 6
442 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
452 #define CP_T_X 0x00008000
453 #define CP_T_Y 0x00400000
455 #define CONDS_BIT 0x00100000
456 #define LOAD_BIT 0x00100000
458 #define DOUBLE_LOAD_FLAG 0x00000001
462 const char * template_name
;
466 #define COND_ALWAYS 0xE
470 const char * template_name
;
474 struct asm_barrier_opt
476 const char * template_name
;
478 const arm_feature_set arch
;
481 /* The bit that distinguishes CPSR and SPSR. */
482 #define SPSR_BIT (1 << 22)
484 /* The individual PSR flag bits. */
485 #define PSR_c (1 << 16)
486 #define PSR_x (1 << 17)
487 #define PSR_s (1 << 18)
488 #define PSR_f (1 << 19)
493 bfd_reloc_code_real_type reloc
;
498 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
499 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
504 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
507 /* Bits for DEFINED field in neon_typed_alias. */
508 #define NTA_HASTYPE 1
509 #define NTA_HASINDEX 2
511 struct neon_typed_alias
513 unsigned char defined
;
515 struct neon_type_el eltype
;
518 /* ARM register categories. This includes coprocessor numbers and various
519 architecture extensions' registers. */
546 /* Structure for a hash table entry for a register.
547 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
548 information which states whether a vector type or index is specified (for a
549 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
555 unsigned char builtin
;
556 struct neon_typed_alias
* neon
;
559 /* Diagnostics used when we don't get a register of the expected type. */
560 const char * const reg_expected_msgs
[] =
562 N_("ARM register expected"),
563 N_("bad or missing co-processor number"),
564 N_("co-processor register expected"),
565 N_("FPA register expected"),
566 N_("VFP single precision register expected"),
567 N_("VFP/Neon double precision register expected"),
568 N_("Neon quad precision register expected"),
569 N_("VFP single or double precision register expected"),
570 N_("Neon double or quad precision register expected"),
571 N_("VFP single, double or Neon quad precision register expected"),
572 N_("VFP system register expected"),
573 N_("Maverick MVF register expected"),
574 N_("Maverick MVD register expected"),
575 N_("Maverick MVFX register expected"),
576 N_("Maverick MVDX register expected"),
577 N_("Maverick MVAX register expected"),
578 N_("Maverick DSPSC register expected"),
579 N_("iWMMXt data register expected"),
580 N_("iWMMXt control register expected"),
581 N_("iWMMXt scalar register expected"),
582 N_("XScale accumulator register expected"),
585 /* Some well known registers that we refer to directly elsewhere. */
591 /* ARM instructions take 4bytes in the object file, Thumb instructions
597 /* Basic string to match. */
598 const char * template_name
;
600 /* Parameters to instruction. */
601 unsigned int operands
[8];
603 /* Conditional tag - see opcode_lookup. */
604 unsigned int tag
: 4;
606 /* Basic instruction code. */
607 unsigned int avalue
: 28;
609 /* Thumb-format instruction code. */
612 /* Which architecture variant provides this instruction. */
613 const arm_feature_set
* avariant
;
614 const arm_feature_set
* tvariant
;
616 /* Function to call to encode instruction in ARM format. */
617 void (* aencode
) (void);
619 /* Function to call to encode instruction in Thumb format. */
620 void (* tencode
) (void);
623 /* Defines for various bits that we will want to toggle. */
624 #define INST_IMMEDIATE 0x02000000
625 #define OFFSET_REG 0x02000000
626 #define HWOFFSET_IMM 0x00400000
627 #define SHIFT_BY_REG 0x00000010
628 #define PRE_INDEX 0x01000000
629 #define INDEX_UP 0x00800000
630 #define WRITE_BACK 0x00200000
631 #define LDM_TYPE_2_OR_3 0x00400000
632 #define CPSI_MMOD 0x00020000
634 #define LITERAL_MASK 0xf000f000
635 #define OPCODE_MASK 0xfe1fffff
636 #define V4_STR_BIT 0x00000020
637 #define VLDR_VMOV_SAME 0x0040f000
639 #define T2_SUBS_PC_LR 0xf3de8f00
641 #define DATA_OP_SHIFT 21
643 #define T2_OPCODE_MASK 0xfe1fffff
644 #define T2_DATA_OP_SHIFT 21
646 #define A_COND_MASK 0xf0000000
647 #define A_PUSH_POP_OP_MASK 0x0fff0000
649 /* Opcodes for pushing/poping registers to/from the stack. */
650 #define A1_OPCODE_PUSH 0x092d0000
651 #define A2_OPCODE_PUSH 0x052d0004
652 #define A2_OPCODE_POP 0x049d0004
654 /* Codes to distinguish the arithmetic instructions. */
665 #define OPCODE_CMP 10
666 #define OPCODE_CMN 11
667 #define OPCODE_ORR 12
668 #define OPCODE_MOV 13
669 #define OPCODE_BIC 14
670 #define OPCODE_MVN 15
672 #define T2_OPCODE_AND 0
673 #define T2_OPCODE_BIC 1
674 #define T2_OPCODE_ORR 2
675 #define T2_OPCODE_ORN 3
676 #define T2_OPCODE_EOR 4
677 #define T2_OPCODE_ADD 8
678 #define T2_OPCODE_ADC 10
679 #define T2_OPCODE_SBC 11
680 #define T2_OPCODE_SUB 13
681 #define T2_OPCODE_RSB 14
683 #define T_OPCODE_MUL 0x4340
684 #define T_OPCODE_TST 0x4200
685 #define T_OPCODE_CMN 0x42c0
686 #define T_OPCODE_NEG 0x4240
687 #define T_OPCODE_MVN 0x43c0
689 #define T_OPCODE_ADD_R3 0x1800
690 #define T_OPCODE_SUB_R3 0x1a00
691 #define T_OPCODE_ADD_HI 0x4400
692 #define T_OPCODE_ADD_ST 0xb000
693 #define T_OPCODE_SUB_ST 0xb080
694 #define T_OPCODE_ADD_SP 0xa800
695 #define T_OPCODE_ADD_PC 0xa000
696 #define T_OPCODE_ADD_I8 0x3000
697 #define T_OPCODE_SUB_I8 0x3800
698 #define T_OPCODE_ADD_I3 0x1c00
699 #define T_OPCODE_SUB_I3 0x1e00
701 #define T_OPCODE_ASR_R 0x4100
702 #define T_OPCODE_LSL_R 0x4080
703 #define T_OPCODE_LSR_R 0x40c0
704 #define T_OPCODE_ROR_R 0x41c0
705 #define T_OPCODE_ASR_I 0x1000
706 #define T_OPCODE_LSL_I 0x0000
707 #define T_OPCODE_LSR_I 0x0800
709 #define T_OPCODE_MOV_I8 0x2000
710 #define T_OPCODE_CMP_I8 0x2800
711 #define T_OPCODE_CMP_LR 0x4280
712 #define T_OPCODE_MOV_HR 0x4600
713 #define T_OPCODE_CMP_HR 0x4500
715 #define T_OPCODE_LDR_PC 0x4800
716 #define T_OPCODE_LDR_SP 0x9800
717 #define T_OPCODE_STR_SP 0x9000
718 #define T_OPCODE_LDR_IW 0x6800
719 #define T_OPCODE_STR_IW 0x6000
720 #define T_OPCODE_LDR_IH 0x8800
721 #define T_OPCODE_STR_IH 0x8000
722 #define T_OPCODE_LDR_IB 0x7800
723 #define T_OPCODE_STR_IB 0x7000
724 #define T_OPCODE_LDR_RW 0x5800
725 #define T_OPCODE_STR_RW 0x5000
726 #define T_OPCODE_LDR_RH 0x5a00
727 #define T_OPCODE_STR_RH 0x5200
728 #define T_OPCODE_LDR_RB 0x5c00
729 #define T_OPCODE_STR_RB 0x5400
731 #define T_OPCODE_PUSH 0xb400
732 #define T_OPCODE_POP 0xbc00
734 #define T_OPCODE_BRANCH 0xe000
736 #define THUMB_SIZE 2 /* Size of thumb instruction. */
737 #define THUMB_PP_PC_LR 0x0100
738 #define THUMB_LOAD_BIT 0x0800
739 #define THUMB2_LOAD_BIT 0x00100000
741 #define BAD_ARGS _("bad arguments to instruction")
742 #define BAD_SP _("r13 not allowed here")
743 #define BAD_PC _("r15 not allowed here")
744 #define BAD_COND _("instruction cannot be conditional")
745 #define BAD_OVERLAP _("registers may not be the same")
746 #define BAD_HIREG _("lo register required")
747 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
748 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
749 #define BAD_BRANCH _("branch must be last instruction in IT block")
750 #define BAD_NOT_IT _("instruction not allowed in IT block")
751 #define BAD_FPU _("selected FPU does not support instruction")
752 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
753 #define BAD_IT_COND _("incorrect condition in IT block")
754 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
755 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
756 #define BAD_PC_ADDRESSING \
757 _("cannot use register index with PC-relative addressing")
758 #define BAD_PC_WRITEBACK \
759 _("cannot use writeback with PC-relative addressing")
760 #define BAD_RANGE _("branch out of range")
761 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
763 static struct hash_control
* arm_ops_hsh
;
764 static struct hash_control
* arm_cond_hsh
;
765 static struct hash_control
* arm_shift_hsh
;
766 static struct hash_control
* arm_psr_hsh
;
767 static struct hash_control
* arm_v7m_psr_hsh
;
768 static struct hash_control
* arm_reg_hsh
;
769 static struct hash_control
* arm_reloc_hsh
;
770 static struct hash_control
* arm_barrier_opt_hsh
;
772 /* Stuff needed to resolve the label ambiguity
781 symbolS
* last_label_seen
;
782 static int label_is_thumb_function_name
= FALSE
;
784 /* Literal pool structure. Held on a per-section
785 and per-sub-section basis. */
787 #define MAX_LITERAL_POOL_SIZE 1024
788 typedef struct literal_pool
790 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
791 unsigned int next_free_entry
;
797 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
799 struct literal_pool
* next
;
800 unsigned int alignment
;
803 /* Pointer to a linked list of literal pools. */
804 literal_pool
* list_of_pools
= NULL
;
806 typedef enum asmfunc_states
809 WAITING_ASMFUNC_NAME
,
813 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
816 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
818 static struct current_it now_it
;
822 now_it_compatible (int cond
)
824 return (cond
& ~1) == (now_it
.cc
& ~1);
828 conditional_insn (void)
830 return inst
.cond
!= COND_ALWAYS
;
833 static int in_it_block (void);
835 static int handle_it_state (void);
837 static void force_automatic_it_block_close (void);
839 static void it_fsm_post_encode (void);
841 #define set_it_insn_type(type) \
844 inst.it_insn_type = type; \
845 if (handle_it_state () == FAIL) \
850 #define set_it_insn_type_nonvoid(type, failret) \
853 inst.it_insn_type = type; \
854 if (handle_it_state () == FAIL) \
859 #define set_it_insn_type_last() \
862 if (inst.cond == COND_ALWAYS) \
863 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
865 set_it_insn_type (INSIDE_IT_LAST_INSN); \
871 /* This array holds the chars that always start a comment. If the
872 pre-processor is disabled, these aren't very useful. */
873 char arm_comment_chars
[] = "@";
875 /* This array holds the chars that only start a comment at the beginning of
876 a line. If the line seems to have the form '# 123 filename'
877 .line and .file directives will appear in the pre-processed output. */
878 /* Note that input_file.c hand checks for '#' at the beginning of the
879 first line of the input file. This is because the compiler outputs
880 #NO_APP at the beginning of its output. */
881 /* Also note that comments like this one will always work. */
882 const char line_comment_chars
[] = "#";
884 char arm_line_separator_chars
[] = ";";
886 /* Chars that can be used to separate mant
887 from exp in floating point numbers. */
888 const char EXP_CHARS
[] = "eE";
890 /* Chars that mean this number is a floating point constant. */
894 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
896 /* Prefix characters that indicate the start of an immediate
898 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
900 /* Separator character handling. */
902 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
905 skip_past_char (char ** str
, char c
)
907 /* PR gas/14987: Allow for whitespace before the expected character. */
908 skip_whitespace (*str
);
919 #define skip_past_comma(str) skip_past_char (str, ',')
921 /* Arithmetic expressions (possibly involving symbols). */
923 /* Return TRUE if anything in the expression is a bignum. */
926 walk_no_bignums (symbolS
* sp
)
928 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
931 if (symbol_get_value_expression (sp
)->X_add_symbol
)
933 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
934 || (symbol_get_value_expression (sp
)->X_op_symbol
935 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
941 static int in_my_get_expression
= 0;
943 /* Third argument to my_get_expression. */
944 #define GE_NO_PREFIX 0
945 #define GE_IMM_PREFIX 1
946 #define GE_OPT_PREFIX 2
947 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
948 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
949 #define GE_OPT_PREFIX_BIG 3
952 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
957 /* In unified syntax, all prefixes are optional. */
959 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
964 case GE_NO_PREFIX
: break;
966 if (!is_immediate_prefix (**str
))
968 inst
.error
= _("immediate expression requires a # prefix");
974 case GE_OPT_PREFIX_BIG
:
975 if (is_immediate_prefix (**str
))
981 memset (ep
, 0, sizeof (expressionS
));
983 save_in
= input_line_pointer
;
984 input_line_pointer
= *str
;
985 in_my_get_expression
= 1;
986 seg
= expression (ep
);
987 in_my_get_expression
= 0;
989 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
991 /* We found a bad or missing expression in md_operand(). */
992 *str
= input_line_pointer
;
993 input_line_pointer
= save_in
;
994 if (inst
.error
== NULL
)
995 inst
.error
= (ep
->X_op
== O_absent
996 ? _("missing expression") :_("bad expression"));
1001 if (seg
!= absolute_section
1002 && seg
!= text_section
1003 && seg
!= data_section
1004 && seg
!= bss_section
1005 && seg
!= undefined_section
)
1007 inst
.error
= _("bad segment");
1008 *str
= input_line_pointer
;
1009 input_line_pointer
= save_in
;
1016 /* Get rid of any bignums now, so that we don't generate an error for which
1017 we can't establish a line number later on. Big numbers are never valid
1018 in instructions, which is where this routine is always called. */
1019 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1020 && (ep
->X_op
== O_big
1021 || (ep
->X_add_symbol
1022 && (walk_no_bignums (ep
->X_add_symbol
)
1024 && walk_no_bignums (ep
->X_op_symbol
))))))
1026 inst
.error
= _("invalid constant");
1027 *str
= input_line_pointer
;
1028 input_line_pointer
= save_in
;
1032 *str
= input_line_pointer
;
1033 input_line_pointer
= save_in
;
1037 /* Turn a string in input_line_pointer into a floating point constant
1038 of type TYPE, and store the appropriate bytes in *LITP. The number
1039 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1040 returned, or NULL on OK.
1042 Note that fp constants aren't represent in the normal way on the ARM.
1043 In big endian mode, things are as expected. However, in little endian
1044 mode fp constants are big-endian word-wise, and little-endian byte-wise
1045 within the words. For example, (double) 1.1 in big endian mode is
1046 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1047 the byte sequence 99 99 f1 3f 9a 99 99 99.
1049 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1052 md_atof (int type
, char * litP
, int * sizeP
)
1055 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1087 return _("Unrecognized or unsupported floating point constant");
1090 t
= atof_ieee (input_line_pointer
, type
, words
);
1092 input_line_pointer
= t
;
1093 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1095 if (target_big_endian
)
1097 for (i
= 0; i
< prec
; i
++)
1099 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1100 litP
+= sizeof (LITTLENUM_TYPE
);
1105 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1106 for (i
= prec
- 1; i
>= 0; i
--)
1108 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1109 litP
+= sizeof (LITTLENUM_TYPE
);
1112 /* For a 4 byte float the order of elements in `words' is 1 0.
1113 For an 8 byte float the order is 1 0 3 2. */
1114 for (i
= 0; i
< prec
; i
+= 2)
1116 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1117 sizeof (LITTLENUM_TYPE
));
1118 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1119 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1120 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1127 /* We handle all bad expressions here, so that we can report the faulty
1128 instruction in the error message. */
1130 md_operand (expressionS
* exp
)
1132 if (in_my_get_expression
)
1133 exp
->X_op
= O_illegal
;
1136 /* Immediate values. */
1138 /* Generic immediate-value read function for use in directives.
1139 Accepts anything that 'expression' can fold to a constant.
1140 *val receives the number. */
1143 immediate_for_directive (int *val
)
1146 exp
.X_op
= O_illegal
;
1148 if (is_immediate_prefix (*input_line_pointer
))
1150 input_line_pointer
++;
1154 if (exp
.X_op
!= O_constant
)
1156 as_bad (_("expected #constant"));
1157 ignore_rest_of_line ();
1160 *val
= exp
.X_add_number
;
1165 /* Register parsing. */
1167 /* Generic register parser. CCP points to what should be the
1168 beginning of a register name. If it is indeed a valid register
1169 name, advance CCP over it and return the reg_entry structure;
1170 otherwise return NULL. Does not issue diagnostics. */
1172 static struct reg_entry
*
1173 arm_reg_parse_multi (char **ccp
)
1177 struct reg_entry
*reg
;
1179 skip_whitespace (start
);
1181 #ifdef REGISTER_PREFIX
1182 if (*start
!= REGISTER_PREFIX
)
1186 #ifdef OPTIONAL_REGISTER_PREFIX
1187 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1192 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1197 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1199 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1209 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1210 enum arm_reg_type type
)
1212 /* Alternative syntaxes are accepted for a few register classes. */
1219 /* Generic coprocessor register names are allowed for these. */
1220 if (reg
&& reg
->type
== REG_TYPE_CN
)
1225 /* For backward compatibility, a bare number is valid here. */
1227 unsigned long processor
= strtoul (start
, ccp
, 10);
1228 if (*ccp
!= start
&& processor
<= 15)
1232 case REG_TYPE_MMXWC
:
1233 /* WC includes WCG. ??? I'm not sure this is true for all
1234 instructions that take WC registers. */
1235 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1246 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1247 return value is the register number or FAIL. */
1250 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1253 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1256 /* Do not allow a scalar (reg+index) to parse as a register. */
1257 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1260 if (reg
&& reg
->type
== type
)
1263 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1270 /* Parse a Neon type specifier. *STR should point at the leading '.'
1271 character. Does no verification at this stage that the type fits the opcode
1278 Can all be legally parsed by this function.
1280 Fills in neon_type struct pointer with parsed information, and updates STR
1281 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1282 type, FAIL if not. */
1285 parse_neon_type (struct neon_type
*type
, char **str
)
1292 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1294 enum neon_el_type thistype
= NT_untyped
;
1295 unsigned thissize
= -1u;
1302 /* Just a size without an explicit type. */
1306 switch (TOLOWER (*ptr
))
1308 case 'i': thistype
= NT_integer
; break;
1309 case 'f': thistype
= NT_float
; break;
1310 case 'p': thistype
= NT_poly
; break;
1311 case 's': thistype
= NT_signed
; break;
1312 case 'u': thistype
= NT_unsigned
; break;
1314 thistype
= NT_float
;
1319 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1325 /* .f is an abbreviation for .f32. */
1326 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1331 thissize
= strtoul (ptr
, &ptr
, 10);
1333 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1336 as_bad (_("bad size %d in type specifier"), thissize
);
1344 type
->el
[type
->elems
].type
= thistype
;
1345 type
->el
[type
->elems
].size
= thissize
;
1350 /* Empty/missing type is not a successful parse. */
1351 if (type
->elems
== 0)
1359 /* Errors may be set multiple times during parsing or bit encoding
1360 (particularly in the Neon bits), but usually the earliest error which is set
1361 will be the most meaningful. Avoid overwriting it with later (cascading)
1362 errors by calling this function. */
1365 first_error (const char *err
)
1371 /* Parse a single type, e.g. ".s32", leading period included. */
1373 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1376 struct neon_type optype
;
1380 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1382 if (optype
.elems
== 1)
1383 *vectype
= optype
.el
[0];
1386 first_error (_("only one type should be specified for operand"));
1392 first_error (_("vector type expected"));
1404 /* Special meanings for indices (which have a range of 0-7), which will fit into
1407 #define NEON_ALL_LANES 15
1408 #define NEON_INTERLEAVE_LANES 14
1410 /* Parse either a register or a scalar, with an optional type. Return the
1411 register number, and optionally fill in the actual type of the register
1412 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1413 type/index information in *TYPEINFO. */
1416 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1417 enum arm_reg_type
*rtype
,
1418 struct neon_typed_alias
*typeinfo
)
1421 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1422 struct neon_typed_alias atype
;
1423 struct neon_type_el parsetype
;
1427 atype
.eltype
.type
= NT_invtype
;
1428 atype
.eltype
.size
= -1;
1430 /* Try alternate syntax for some types of register. Note these are mutually
1431 exclusive with the Neon syntax extensions. */
1434 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1442 /* Undo polymorphism when a set of register types may be accepted. */
1443 if ((type
== REG_TYPE_NDQ
1444 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1445 || (type
== REG_TYPE_VFSD
1446 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1447 || (type
== REG_TYPE_NSDQ
1448 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1449 || reg
->type
== REG_TYPE_NQ
))
1450 || (type
== REG_TYPE_MMXWC
1451 && (reg
->type
== REG_TYPE_MMXWCG
)))
1452 type
= (enum arm_reg_type
) reg
->type
;
1454 if (type
!= reg
->type
)
1460 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1462 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1464 first_error (_("can't redefine type for operand"));
1467 atype
.defined
|= NTA_HASTYPE
;
1468 atype
.eltype
= parsetype
;
1471 if (skip_past_char (&str
, '[') == SUCCESS
)
1473 if (type
!= REG_TYPE_VFD
)
1475 first_error (_("only D registers may be indexed"));
1479 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1481 first_error (_("can't change index for operand"));
1485 atype
.defined
|= NTA_HASINDEX
;
1487 if (skip_past_char (&str
, ']') == SUCCESS
)
1488 atype
.index
= NEON_ALL_LANES
;
1493 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1495 if (exp
.X_op
!= O_constant
)
1497 first_error (_("constant expression required"));
1501 if (skip_past_char (&str
, ']') == FAIL
)
1504 atype
.index
= exp
.X_add_number
;
1519 /* Like arm_reg_parse, but allow allow the following extra features:
1520 - If RTYPE is non-zero, return the (possibly restricted) type of the
1521 register (e.g. Neon double or quad reg when either has been requested).
1522 - If this is a Neon vector type with additional type information, fill
1523 in the struct pointed to by VECTYPE (if non-NULL).
1524 This function will fault on encountering a scalar. */
1527 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1528 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1530 struct neon_typed_alias atype
;
1532 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1537 /* Do not allow regname(... to parse as a register. */
1541 /* Do not allow a scalar (reg+index) to parse as a register. */
1542 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1544 first_error (_("register operand expected, but got scalar"));
1549 *vectype
= atype
.eltype
;
1556 #define NEON_SCALAR_REG(X) ((X) >> 4)
1557 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1559 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1560 have enough information to be able to do a good job bounds-checking. So, we
1561 just do easy checks here, and do further checks later. */
1564 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1568 struct neon_typed_alias atype
;
1570 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1572 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1575 if (atype
.index
== NEON_ALL_LANES
)
1577 first_error (_("scalar must have an index"));
1580 else if (atype
.index
>= 64 / elsize
)
1582 first_error (_("scalar index out of range"));
1587 *type
= atype
.eltype
;
1591 return reg
* 16 + atype
.index
;
1594 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1597 parse_reg_list (char ** strp
)
1599 char * str
= * strp
;
1603 /* We come back here if we get ranges concatenated by '+' or '|'. */
1606 skip_whitespace (str
);
1620 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1622 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1632 first_error (_("bad range in register list"));
1636 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1638 if (range
& (1 << i
))
1640 (_("Warning: duplicated register (r%d) in register list"),
1648 if (range
& (1 << reg
))
1649 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1651 else if (reg
<= cur_reg
)
1652 as_tsktsk (_("Warning: register range not in ascending order"));
1657 while (skip_past_comma (&str
) != FAIL
1658 || (in_range
= 1, *str
++ == '-'));
1661 if (skip_past_char (&str
, '}') == FAIL
)
1663 first_error (_("missing `}'"));
1671 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1674 if (exp
.X_op
== O_constant
)
1676 if (exp
.X_add_number
1677 != (exp
.X_add_number
& 0x0000ffff))
1679 inst
.error
= _("invalid register mask");
1683 if ((range
& exp
.X_add_number
) != 0)
1685 int regno
= range
& exp
.X_add_number
;
1688 regno
= (1 << regno
) - 1;
1690 (_("Warning: duplicated register (r%d) in register list"),
1694 range
|= exp
.X_add_number
;
1698 if (inst
.reloc
.type
!= 0)
1700 inst
.error
= _("expression too complex");
1704 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1705 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1706 inst
.reloc
.pc_rel
= 0;
1710 if (*str
== '|' || *str
== '+')
1716 while (another_range
);
1722 /* Types of registers in a list. */
1731 /* Parse a VFP register list. If the string is invalid return FAIL.
1732 Otherwise return the number of registers, and set PBASE to the first
1733 register. Parses registers of type ETYPE.
1734 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1735 - Q registers can be used to specify pairs of D registers
1736 - { } can be omitted from around a singleton register list
1737 FIXME: This is not implemented, as it would require backtracking in
1740 This could be done (the meaning isn't really ambiguous), but doesn't
1741 fit in well with the current parsing framework.
1742 - 32 D registers may be used (also true for VFPv3).
1743 FIXME: Types are ignored in these register lists, which is probably a
1747 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1752 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1756 unsigned long mask
= 0;
1759 if (skip_past_char (&str
, '{') == FAIL
)
1761 inst
.error
= _("expecting {");
1768 regtype
= REG_TYPE_VFS
;
1773 regtype
= REG_TYPE_VFD
;
1776 case REGLIST_NEON_D
:
1777 regtype
= REG_TYPE_NDQ
;
1781 if (etype
!= REGLIST_VFP_S
)
1783 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1784 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1788 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1791 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1798 base_reg
= max_regs
;
1802 int setmask
= 1, addregs
= 1;
1804 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1806 if (new_base
== FAIL
)
1808 first_error (_(reg_expected_msgs
[regtype
]));
1812 if (new_base
>= max_regs
)
1814 first_error (_("register out of range in list"));
1818 /* Note: a value of 2 * n is returned for the register Q<n>. */
1819 if (regtype
== REG_TYPE_NQ
)
1825 if (new_base
< base_reg
)
1826 base_reg
= new_base
;
1828 if (mask
& (setmask
<< new_base
))
1830 first_error (_("invalid register list"));
1834 if ((mask
>> new_base
) != 0 && ! warned
)
1836 as_tsktsk (_("register list not in ascending order"));
1840 mask
|= setmask
<< new_base
;
1843 if (*str
== '-') /* We have the start of a range expression */
1849 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1852 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1856 if (high_range
>= max_regs
)
1858 first_error (_("register out of range in list"));
1862 if (regtype
== REG_TYPE_NQ
)
1863 high_range
= high_range
+ 1;
1865 if (high_range
<= new_base
)
1867 inst
.error
= _("register range not in ascending order");
1871 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1873 if (mask
& (setmask
<< new_base
))
1875 inst
.error
= _("invalid register list");
1879 mask
|= setmask
<< new_base
;
1884 while (skip_past_comma (&str
) != FAIL
);
1888 /* Sanity check -- should have raised a parse error above. */
1889 if (count
== 0 || count
> max_regs
)
1894 /* Final test -- the registers must be consecutive. */
1896 for (i
= 0; i
< count
; i
++)
1898 if ((mask
& (1u << i
)) == 0)
1900 inst
.error
= _("non-contiguous register range");
1910 /* True if two alias types are the same. */
1913 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1921 if (a
->defined
!= b
->defined
)
1924 if ((a
->defined
& NTA_HASTYPE
) != 0
1925 && (a
->eltype
.type
!= b
->eltype
.type
1926 || a
->eltype
.size
!= b
->eltype
.size
))
1929 if ((a
->defined
& NTA_HASINDEX
) != 0
1930 && (a
->index
!= b
->index
))
1936 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1937 The base register is put in *PBASE.
1938 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1940 The register stride (minus one) is put in bit 4 of the return value.
1941 Bits [6:5] encode the list length (minus one).
1942 The type of the list elements is put in *ELTYPE, if non-NULL. */
1944 #define NEON_LANE(X) ((X) & 0xf)
1945 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1946 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1949 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1950 struct neon_type_el
*eltype
)
1957 int leading_brace
= 0;
1958 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1959 const char *const incr_error
= _("register stride must be 1 or 2");
1960 const char *const type_error
= _("mismatched element/structure types in list");
1961 struct neon_typed_alias firsttype
;
1963 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1968 struct neon_typed_alias atype
;
1969 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1973 first_error (_(reg_expected_msgs
[rtype
]));
1980 if (rtype
== REG_TYPE_NQ
)
1986 else if (reg_incr
== -1)
1988 reg_incr
= getreg
- base_reg
;
1989 if (reg_incr
< 1 || reg_incr
> 2)
1991 first_error (_(incr_error
));
1995 else if (getreg
!= base_reg
+ reg_incr
* count
)
1997 first_error (_(incr_error
));
2001 if (! neon_alias_types_same (&atype
, &firsttype
))
2003 first_error (_(type_error
));
2007 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2011 struct neon_typed_alias htype
;
2012 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2014 lane
= NEON_INTERLEAVE_LANES
;
2015 else if (lane
!= NEON_INTERLEAVE_LANES
)
2017 first_error (_(type_error
));
2022 else if (reg_incr
!= 1)
2024 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2028 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2031 first_error (_(reg_expected_msgs
[rtype
]));
2034 if (! neon_alias_types_same (&htype
, &firsttype
))
2036 first_error (_(type_error
));
2039 count
+= hireg
+ dregs
- getreg
;
2043 /* If we're using Q registers, we can't use [] or [n] syntax. */
2044 if (rtype
== REG_TYPE_NQ
)
2050 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2054 else if (lane
!= atype
.index
)
2056 first_error (_(type_error
));
2060 else if (lane
== -1)
2061 lane
= NEON_INTERLEAVE_LANES
;
2062 else if (lane
!= NEON_INTERLEAVE_LANES
)
2064 first_error (_(type_error
));
2069 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2071 /* No lane set by [x]. We must be interleaving structures. */
2073 lane
= NEON_INTERLEAVE_LANES
;
2076 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2077 || (count
> 1 && reg_incr
== -1))
2079 first_error (_("error parsing element/structure list"));
2083 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2085 first_error (_("expected }"));
2093 *eltype
= firsttype
.eltype
;
2098 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2101 /* Parse an explicit relocation suffix on an expression. This is
2102 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2103 arm_reloc_hsh contains no entries, so this function can only
2104 succeed if there is no () after the word. Returns -1 on error,
2105 BFD_RELOC_UNUSED if there wasn't any suffix. */
2108 parse_reloc (char **str
)
2110 struct reloc_entry
*r
;
2114 return BFD_RELOC_UNUSED
;
2119 while (*q
&& *q
!= ')' && *q
!= ',')
2124 if ((r
= (struct reloc_entry
*)
2125 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2132 /* Directives: register aliases. */
2134 static struct reg_entry
*
2135 insert_reg_alias (char *str
, unsigned number
, int type
)
2137 struct reg_entry
*new_reg
;
2140 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2142 if (new_reg
->builtin
)
2143 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2145 /* Only warn about a redefinition if it's not defined as the
2147 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2148 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2153 name
= xstrdup (str
);
2154 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2156 new_reg
->name
= name
;
2157 new_reg
->number
= number
;
2158 new_reg
->type
= type
;
2159 new_reg
->builtin
= FALSE
;
2160 new_reg
->neon
= NULL
;
2162 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2169 insert_neon_reg_alias (char *str
, int number
, int type
,
2170 struct neon_typed_alias
*atype
)
2172 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2176 first_error (_("attempt to redefine typed alias"));
2182 reg
->neon
= (struct neon_typed_alias
*)
2183 xmalloc (sizeof (struct neon_typed_alias
));
2184 *reg
->neon
= *atype
;
2188 /* Look for the .req directive. This is of the form:
2190 new_register_name .req existing_register_name
2192 If we find one, or if it looks sufficiently like one that we want to
2193 handle any error here, return TRUE. Otherwise return FALSE. */
2196 create_register_alias (char * newname
, char *p
)
2198 struct reg_entry
*old
;
2199 char *oldname
, *nbuf
;
2202 /* The input scrubber ensures that whitespace after the mnemonic is
2203 collapsed to single spaces. */
2205 if (strncmp (oldname
, " .req ", 6) != 0)
2209 if (*oldname
== '\0')
2212 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2215 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2219 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2220 the desired alias name, and p points to its end. If not, then
2221 the desired alias name is in the global original_case_string. */
2222 #ifdef TC_CASE_SENSITIVE
2225 newname
= original_case_string
;
2226 nlen
= strlen (newname
);
2229 nbuf
= (char *) alloca (nlen
+ 1);
2230 memcpy (nbuf
, newname
, nlen
);
2233 /* Create aliases under the new name as stated; an all-lowercase
2234 version of the new name; and an all-uppercase version of the new
2236 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2238 for (p
= nbuf
; *p
; p
++)
2241 if (strncmp (nbuf
, newname
, nlen
))
2243 /* If this attempt to create an additional alias fails, do not bother
2244 trying to create the all-lower case alias. We will fail and issue
2245 a second, duplicate error message. This situation arises when the
2246 programmer does something like:
2249 The second .req creates the "Foo" alias but then fails to create
2250 the artificial FOO alias because it has already been created by the
2252 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2256 for (p
= nbuf
; *p
; p
++)
2259 if (strncmp (nbuf
, newname
, nlen
))
2260 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2266 /* Create a Neon typed/indexed register alias using directives, e.g.:
2271 These typed registers can be used instead of the types specified after the
2272 Neon mnemonic, so long as all operands given have types. Types can also be
2273 specified directly, e.g.:
2274 vadd d0.s32, d1.s32, d2.s32 */
2277 create_neon_reg_alias (char *newname
, char *p
)
2279 enum arm_reg_type basetype
;
2280 struct reg_entry
*basereg
;
2281 struct reg_entry mybasereg
;
2282 struct neon_type ntype
;
2283 struct neon_typed_alias typeinfo
;
2284 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2287 typeinfo
.defined
= 0;
2288 typeinfo
.eltype
.type
= NT_invtype
;
2289 typeinfo
.eltype
.size
= -1;
2290 typeinfo
.index
= -1;
2294 if (strncmp (p
, " .dn ", 5) == 0)
2295 basetype
= REG_TYPE_VFD
;
2296 else if (strncmp (p
, " .qn ", 5) == 0)
2297 basetype
= REG_TYPE_NQ
;
2306 basereg
= arm_reg_parse_multi (&p
);
2308 if (basereg
&& basereg
->type
!= basetype
)
2310 as_bad (_("bad type for register"));
2314 if (basereg
== NULL
)
2317 /* Try parsing as an integer. */
2318 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2319 if (exp
.X_op
!= O_constant
)
2321 as_bad (_("expression must be constant"));
2324 basereg
= &mybasereg
;
2325 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2331 typeinfo
= *basereg
->neon
;
2333 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2335 /* We got a type. */
2336 if (typeinfo
.defined
& NTA_HASTYPE
)
2338 as_bad (_("can't redefine the type of a register alias"));
2342 typeinfo
.defined
|= NTA_HASTYPE
;
2343 if (ntype
.elems
!= 1)
2345 as_bad (_("you must specify a single type only"));
2348 typeinfo
.eltype
= ntype
.el
[0];
2351 if (skip_past_char (&p
, '[') == SUCCESS
)
2354 /* We got a scalar index. */
2356 if (typeinfo
.defined
& NTA_HASINDEX
)
2358 as_bad (_("can't redefine the index of a scalar alias"));
2362 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2364 if (exp
.X_op
!= O_constant
)
2366 as_bad (_("scalar index must be constant"));
2370 typeinfo
.defined
|= NTA_HASINDEX
;
2371 typeinfo
.index
= exp
.X_add_number
;
2373 if (skip_past_char (&p
, ']') == FAIL
)
2375 as_bad (_("expecting ]"));
2380 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2381 the desired alias name, and p points to its end. If not, then
2382 the desired alias name is in the global original_case_string. */
2383 #ifdef TC_CASE_SENSITIVE
2384 namelen
= nameend
- newname
;
2386 newname
= original_case_string
;
2387 namelen
= strlen (newname
);
2390 namebuf
= (char *) alloca (namelen
+ 1);
2391 strncpy (namebuf
, newname
, namelen
);
2392 namebuf
[namelen
] = '\0';
2394 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2395 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2397 /* Insert name in all uppercase. */
2398 for (p
= namebuf
; *p
; p
++)
2401 if (strncmp (namebuf
, newname
, namelen
))
2402 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2403 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2405 /* Insert name in all lowercase. */
2406 for (p
= namebuf
; *p
; p
++)
2409 if (strncmp (namebuf
, newname
, namelen
))
2410 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2411 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2416 /* Should never be called, as .req goes between the alias and the
2417 register name, not at the beginning of the line. */
2420 s_req (int a ATTRIBUTE_UNUSED
)
2422 as_bad (_("invalid syntax for .req directive"));
2426 s_dn (int a ATTRIBUTE_UNUSED
)
2428 as_bad (_("invalid syntax for .dn directive"));
2432 s_qn (int a ATTRIBUTE_UNUSED
)
2434 as_bad (_("invalid syntax for .qn directive"));
2437 /* The .unreq directive deletes an alias which was previously defined
2438 by .req. For example:
2444 s_unreq (int a ATTRIBUTE_UNUSED
)
2449 name
= input_line_pointer
;
2451 while (*input_line_pointer
!= 0
2452 && *input_line_pointer
!= ' '
2453 && *input_line_pointer
!= '\n')
2454 ++input_line_pointer
;
2456 saved_char
= *input_line_pointer
;
2457 *input_line_pointer
= 0;
2460 as_bad (_("invalid syntax for .unreq directive"));
2463 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2467 as_bad (_("unknown register alias '%s'"), name
);
2468 else if (reg
->builtin
)
2469 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2476 hash_delete (arm_reg_hsh
, name
, FALSE
);
2477 free ((char *) reg
->name
);
2482 /* Also locate the all upper case and all lower case versions.
2483 Do not complain if we cannot find one or the other as it
2484 was probably deleted above. */
2486 nbuf
= strdup (name
);
2487 for (p
= nbuf
; *p
; p
++)
2489 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2492 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2493 free ((char *) reg
->name
);
2499 for (p
= nbuf
; *p
; p
++)
2501 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2504 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2505 free ((char *) reg
->name
);
2515 *input_line_pointer
= saved_char
;
2516 demand_empty_rest_of_line ();
2519 /* Directives: Instruction set selection. */
2522 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2523 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2524 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2525 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2527 /* Create a new mapping symbol for the transition to STATE. */
2530 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2533 const char * symname
;
2540 type
= BSF_NO_FLAGS
;
2544 type
= BSF_NO_FLAGS
;
2548 type
= BSF_NO_FLAGS
;
2554 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2555 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2560 THUMB_SET_FUNC (symbolP
, 0);
2561 ARM_SET_THUMB (symbolP
, 0);
2562 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2566 THUMB_SET_FUNC (symbolP
, 1);
2567 ARM_SET_THUMB (symbolP
, 1);
2568 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2576 /* Save the mapping symbols for future reference. Also check that
2577 we do not place two mapping symbols at the same offset within a
2578 frag. We'll handle overlap between frags in
2579 check_mapping_symbols.
2581 If .fill or other data filling directive generates zero sized data,
2582 the mapping symbol for the following code will have the same value
2583 as the one generated for the data filling directive. In this case,
2584 we replace the old symbol with the new one at the same address. */
2587 if (frag
->tc_frag_data
.first_map
!= NULL
)
2589 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2590 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2592 frag
->tc_frag_data
.first_map
= symbolP
;
2594 if (frag
->tc_frag_data
.last_map
!= NULL
)
2596 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2597 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2598 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2600 frag
->tc_frag_data
.last_map
= symbolP
;
2603 /* We must sometimes convert a region marked as code to data during
2604 code alignment, if an odd number of bytes have to be padded. The
2605 code mapping symbol is pushed to an aligned address. */
2608 insert_data_mapping_symbol (enum mstate state
,
2609 valueT value
, fragS
*frag
, offsetT bytes
)
2611 /* If there was already a mapping symbol, remove it. */
2612 if (frag
->tc_frag_data
.last_map
!= NULL
2613 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2615 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2619 know (frag
->tc_frag_data
.first_map
== symp
);
2620 frag
->tc_frag_data
.first_map
= NULL
;
2622 frag
->tc_frag_data
.last_map
= NULL
;
2623 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2626 make_mapping_symbol (MAP_DATA
, value
, frag
);
2627 make_mapping_symbol (state
, value
+ bytes
, frag
);
2630 static void mapping_state_2 (enum mstate state
, int max_chars
);
2632 /* Set the mapping state to STATE. Only call this when about to
2633 emit some STATE bytes to the file. */
2636 mapping_state (enum mstate state
)
2638 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2640 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2642 if (mapstate
== state
)
2643 /* The mapping symbol has already been emitted.
2644 There is nothing else to do. */
2647 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2649 All ARM instructions require 4-byte alignment.
2650 (Almost) all Thumb instructions require 2-byte alignment.
2652 When emitting instructions into any section, mark the section
2655 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2656 but themselves require 2-byte alignment; this applies to some
2657 PC- relative forms. However, these cases will invovle implicit
2658 literal pool generation or an explicit .align >=2, both of
2659 which will cause the section to me marked with sufficient
2660 alignment. Thus, we don't handle those cases here. */
2661 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2663 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2664 /* This case will be evaluated later in the next else. */
2666 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2667 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2669 /* Only add the symbol if the offset is > 0:
2670 if we're at the first frag, check it's size > 0;
2671 if we're not at the first frag, then for sure
2672 the offset is > 0. */
2673 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2674 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2677 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2680 mapping_state_2 (state
, 0);
2684 /* Same as mapping_state, but MAX_CHARS bytes have already been
2685 allocated. Put the mapping symbol that far back. */
2688 mapping_state_2 (enum mstate state
, int max_chars
)
2690 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2692 if (!SEG_NORMAL (now_seg
))
2695 if (mapstate
== state
)
2696 /* The mapping symbol has already been emitted.
2697 There is nothing else to do. */
2700 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2701 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2704 #define mapping_state(x) ((void)0)
2705 #define mapping_state_2(x, y) ((void)0)
2708 /* Find the real, Thumb encoded start of a Thumb function. */
2712 find_real_start (symbolS
* symbolP
)
2715 const char * name
= S_GET_NAME (symbolP
);
2716 symbolS
* new_target
;
2718 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2719 #define STUB_NAME ".real_start_of"
2724 /* The compiler may generate BL instructions to local labels because
2725 it needs to perform a branch to a far away location. These labels
2726 do not have a corresponding ".real_start_of" label. We check
2727 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2728 the ".real_start_of" convention for nonlocal branches. */
2729 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2732 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2733 new_target
= symbol_find (real_start
);
2735 if (new_target
== NULL
)
2737 as_warn (_("Failed to find real start of function: %s\n"), name
);
2738 new_target
= symbolP
;
2746 opcode_select (int width
)
2753 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2754 as_bad (_("selected processor does not support THUMB opcodes"));
2757 /* No need to force the alignment, since we will have been
2758 coming from ARM mode, which is word-aligned. */
2759 record_alignment (now_seg
, 1);
2766 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2767 as_bad (_("selected processor does not support ARM opcodes"));
2772 frag_align (2, 0, 0);
2774 record_alignment (now_seg
, 1);
2779 as_bad (_("invalid instruction size selected (%d)"), width
);
2784 s_arm (int ignore ATTRIBUTE_UNUSED
)
2787 demand_empty_rest_of_line ();
2791 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2794 demand_empty_rest_of_line ();
2798 s_code (int unused ATTRIBUTE_UNUSED
)
2802 temp
= get_absolute_expression ();
2807 opcode_select (temp
);
2811 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2816 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2818 /* If we are not already in thumb mode go into it, EVEN if
2819 the target processor does not support thumb instructions.
2820 This is used by gcc/config/arm/lib1funcs.asm for example
2821 to compile interworking support functions even if the
2822 target processor should not support interworking. */
2826 record_alignment (now_seg
, 1);
2829 demand_empty_rest_of_line ();
2833 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2837 /* The following label is the name/address of the start of a Thumb function.
2838 We need to know this for the interworking support. */
2839 label_is_thumb_function_name
= TRUE
;
2842 /* Perform a .set directive, but also mark the alias as
2843 being a thumb function. */
2846 s_thumb_set (int equiv
)
2848 /* XXX the following is a duplicate of the code for s_set() in read.c
2849 We cannot just call that code as we need to get at the symbol that
2856 /* Especial apologies for the random logic:
2857 This just grew, and could be parsed much more simply!
2859 name
= input_line_pointer
;
2860 delim
= get_symbol_end ();
2861 end_name
= input_line_pointer
;
2864 if (*input_line_pointer
!= ',')
2867 as_bad (_("expected comma after name \"%s\""), name
);
2869 ignore_rest_of_line ();
2873 input_line_pointer
++;
2876 if (name
[0] == '.' && name
[1] == '\0')
2878 /* XXX - this should not happen to .thumb_set. */
2882 if ((symbolP
= symbol_find (name
)) == NULL
2883 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2886 /* When doing symbol listings, play games with dummy fragments living
2887 outside the normal fragment chain to record the file and line info
2889 if (listing
& LISTING_SYMBOLS
)
2891 extern struct list_info_struct
* listing_tail
;
2892 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2894 memset (dummy_frag
, 0, sizeof (fragS
));
2895 dummy_frag
->fr_type
= rs_fill
;
2896 dummy_frag
->line
= listing_tail
;
2897 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2898 dummy_frag
->fr_symbol
= symbolP
;
2902 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2905 /* "set" symbols are local unless otherwise specified. */
2906 SF_SET_LOCAL (symbolP
);
2907 #endif /* OBJ_COFF */
2908 } /* Make a new symbol. */
2910 symbol_table_insert (symbolP
);
2915 && S_IS_DEFINED (symbolP
)
2916 && S_GET_SEGMENT (symbolP
) != reg_section
)
2917 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2919 pseudo_set (symbolP
);
2921 demand_empty_rest_of_line ();
2923 /* XXX Now we come to the Thumb specific bit of code. */
2925 THUMB_SET_FUNC (symbolP
, 1);
2926 ARM_SET_THUMB (symbolP
, 1);
2927 #if defined OBJ_ELF || defined OBJ_COFF
2928 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2932 /* Directives: Mode selection. */
2934 /* .syntax [unified|divided] - choose the new unified syntax
2935 (same for Arm and Thumb encoding, modulo slight differences in what
2936 can be represented) or the old divergent syntax for each mode. */
2938 s_syntax (int unused ATTRIBUTE_UNUSED
)
2942 name
= input_line_pointer
;
2943 delim
= get_symbol_end ();
2945 if (!strcasecmp (name
, "unified"))
2946 unified_syntax
= TRUE
;
2947 else if (!strcasecmp (name
, "divided"))
2948 unified_syntax
= FALSE
;
2951 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2954 *input_line_pointer
= delim
;
2955 demand_empty_rest_of_line ();
2958 /* Directives: sectioning and alignment. */
2960 /* Same as s_align_ptwo but align 0 => align 2. */
2963 s_align (int unused ATTRIBUTE_UNUSED
)
2968 long max_alignment
= 15;
2970 temp
= get_absolute_expression ();
2971 if (temp
> max_alignment
)
2972 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2975 as_bad (_("alignment negative. 0 assumed."));
2979 if (*input_line_pointer
== ',')
2981 input_line_pointer
++;
2982 temp_fill
= get_absolute_expression ();
2994 /* Only make a frag if we HAVE to. */
2995 if (temp
&& !need_pass_2
)
2997 if (!fill_p
&& subseg_text_p (now_seg
))
2998 frag_align_code (temp
, 0);
3000 frag_align (temp
, (int) temp_fill
, 0);
3002 demand_empty_rest_of_line ();
3004 record_alignment (now_seg
, temp
);
3008 s_bss (int ignore ATTRIBUTE_UNUSED
)
3010 /* We don't support putting frags in the BSS segment, we fake it by
3011 marking in_bss, then looking at s_skip for clues. */
3012 subseg_set (bss_section
, 0);
3013 demand_empty_rest_of_line ();
3015 #ifdef md_elf_section_change_hook
3016 md_elf_section_change_hook ();
3021 s_even (int ignore ATTRIBUTE_UNUSED
)
3023 /* Never make frag if expect extra pass. */
3025 frag_align (1, 0, 0);
3027 record_alignment (now_seg
, 1);
3029 demand_empty_rest_of_line ();
3032 /* Directives: CodeComposer Studio. */
3034 /* .ref (for CodeComposer Studio syntax only). */
3036 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3038 if (codecomposer_syntax
)
3039 ignore_rest_of_line ();
3041 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3044 /* If name is not NULL, then it is used for marking the beginning of a
3045 function, wherease if it is NULL then it means the function end. */
3047 asmfunc_debug (const char * name
)
3049 static const char * last_name
= NULL
;
3053 gas_assert (last_name
== NULL
);
3056 if (debug_type
== DEBUG_STABS
)
3057 stabs_generate_asm_func (name
, name
);
3061 gas_assert (last_name
!= NULL
);
3063 if (debug_type
== DEBUG_STABS
)
3064 stabs_generate_asm_endfunc (last_name
, last_name
);
3071 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3073 if (codecomposer_syntax
)
3075 switch (asmfunc_state
)
3077 case OUTSIDE_ASMFUNC
:
3078 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3081 case WAITING_ASMFUNC_NAME
:
3082 as_bad (_(".asmfunc repeated."));
3085 case WAITING_ENDASMFUNC
:
3086 as_bad (_(".asmfunc without function."));
3089 demand_empty_rest_of_line ();
3092 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3096 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3098 if (codecomposer_syntax
)
3100 switch (asmfunc_state
)
3102 case OUTSIDE_ASMFUNC
:
3103 as_bad (_(".endasmfunc without a .asmfunc."));
3106 case WAITING_ASMFUNC_NAME
:
3107 as_bad (_(".endasmfunc without function."));
3110 case WAITING_ENDASMFUNC
:
3111 asmfunc_state
= OUTSIDE_ASMFUNC
;
3112 asmfunc_debug (NULL
);
3115 demand_empty_rest_of_line ();
3118 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3122 s_ccs_def (int name
)
3124 if (codecomposer_syntax
)
3127 as_bad (_(".def pseudo-op only available with -mccs flag."));
3130 /* Directives: Literal pools. */
3132 static literal_pool
*
3133 find_literal_pool (void)
3135 literal_pool
* pool
;
3137 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3139 if (pool
->section
== now_seg
3140 && pool
->sub_section
== now_subseg
)
3147 static literal_pool
*
3148 find_or_make_literal_pool (void)
3150 /* Next literal pool ID number. */
3151 static unsigned int latest_pool_num
= 1;
3152 literal_pool
* pool
;
3154 pool
= find_literal_pool ();
3158 /* Create a new pool. */
3159 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3163 pool
->next_free_entry
= 0;
3164 pool
->section
= now_seg
;
3165 pool
->sub_section
= now_subseg
;
3166 pool
->next
= list_of_pools
;
3167 pool
->symbol
= NULL
;
3168 pool
->alignment
= 2;
3170 /* Add it to the list. */
3171 list_of_pools
= pool
;
3174 /* New pools, and emptied pools, will have a NULL symbol. */
3175 if (pool
->symbol
== NULL
)
3177 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3178 (valueT
) 0, &zero_address_frag
);
3179 pool
->id
= latest_pool_num
++;
3186 /* Add the literal in the global 'inst'
3187 structure to the relevant literal pool. */
3190 add_to_lit_pool (unsigned int nbytes
)
3192 #define PADDING_SLOT 0x1
3193 #define LIT_ENTRY_SIZE_MASK 0xFF
3194 literal_pool
* pool
;
3195 unsigned int entry
, pool_size
= 0;
3196 bfd_boolean padding_slot_p
= FALSE
;
3202 imm1
= inst
.operands
[1].imm
;
3203 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3204 : inst
.reloc
.exp
.X_unsigned
? 0
3205 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3206 if (target_big_endian
)
3209 imm2
= inst
.operands
[1].imm
;
3213 pool
= find_or_make_literal_pool ();
3215 /* Check if this literal value is already in the pool. */
3216 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3220 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3221 && (inst
.reloc
.exp
.X_op
== O_constant
)
3222 && (pool
->literals
[entry
].X_add_number
3223 == inst
.reloc
.exp
.X_add_number
)
3224 && (pool
->literals
[entry
].X_md
== nbytes
)
3225 && (pool
->literals
[entry
].X_unsigned
3226 == inst
.reloc
.exp
.X_unsigned
))
3229 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3230 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3231 && (pool
->literals
[entry
].X_add_number
3232 == inst
.reloc
.exp
.X_add_number
)
3233 && (pool
->literals
[entry
].X_add_symbol
3234 == inst
.reloc
.exp
.X_add_symbol
)
3235 && (pool
->literals
[entry
].X_op_symbol
3236 == inst
.reloc
.exp
.X_op_symbol
)
3237 && (pool
->literals
[entry
].X_md
== nbytes
))
3240 else if ((nbytes
== 8)
3241 && !(pool_size
& 0x7)
3242 && ((entry
+ 1) != pool
->next_free_entry
)
3243 && (pool
->literals
[entry
].X_op
== O_constant
)
3244 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3245 && (pool
->literals
[entry
].X_unsigned
3246 == inst
.reloc
.exp
.X_unsigned
)
3247 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3248 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3249 && (pool
->literals
[entry
+ 1].X_unsigned
3250 == inst
.reloc
.exp
.X_unsigned
))
3253 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3254 if (padding_slot_p
&& (nbytes
== 4))
3260 /* Do we need to create a new entry? */
3261 if (entry
== pool
->next_free_entry
)
3263 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3265 inst
.error
= _("literal pool overflow");
3271 /* For 8-byte entries, we align to an 8-byte boundary,
3272 and split it into two 4-byte entries, because on 32-bit
3273 host, 8-byte constants are treated as big num, thus
3274 saved in "generic_bignum" which will be overwritten
3275 by later assignments.
3277 We also need to make sure there is enough space for
3280 We also check to make sure the literal operand is a
3282 if (!(inst
.reloc
.exp
.X_op
== O_constant
3283 || inst
.reloc
.exp
.X_op
== O_big
))
3285 inst
.error
= _("invalid type for literal pool");
3288 else if (pool_size
& 0x7)
3290 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3292 inst
.error
= _("literal pool overflow");
3296 pool
->literals
[entry
] = inst
.reloc
.exp
;
3297 pool
->literals
[entry
].X_add_number
= 0;
3298 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3299 pool
->next_free_entry
+= 1;
3302 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3304 inst
.error
= _("literal pool overflow");
3308 pool
->literals
[entry
] = inst
.reloc
.exp
;
3309 pool
->literals
[entry
].X_op
= O_constant
;
3310 pool
->literals
[entry
].X_add_number
= imm1
;
3311 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3312 pool
->literals
[entry
++].X_md
= 4;
3313 pool
->literals
[entry
] = inst
.reloc
.exp
;
3314 pool
->literals
[entry
].X_op
= O_constant
;
3315 pool
->literals
[entry
].X_add_number
= imm2
;
3316 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3317 pool
->literals
[entry
].X_md
= 4;
3318 pool
->alignment
= 3;
3319 pool
->next_free_entry
+= 1;
3323 pool
->literals
[entry
] = inst
.reloc
.exp
;
3324 pool
->literals
[entry
].X_md
= 4;
3328 /* PR ld/12974: Record the location of the first source line to reference
3329 this entry in the literal pool. If it turns out during linking that the
3330 symbol does not exist we will be able to give an accurate line number for
3331 the (first use of the) missing reference. */
3332 if (debug_type
== DEBUG_DWARF2
)
3333 dwarf2_where (pool
->locs
+ entry
);
3335 pool
->next_free_entry
+= 1;
3337 else if (padding_slot_p
)
3339 pool
->literals
[entry
] = inst
.reloc
.exp
;
3340 pool
->literals
[entry
].X_md
= nbytes
;
3343 inst
.reloc
.exp
.X_op
= O_symbol
;
3344 inst
.reloc
.exp
.X_add_number
= pool_size
;
3345 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3351 tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED
, const char * rest
)
3353 bfd_boolean ret
= TRUE
;
3355 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3357 const char *label
= rest
;
3359 while (!is_end_of_line
[(int) label
[-1]])
3364 as_bad (_("Invalid label '%s'"), label
);
3368 asmfunc_debug (label
);
3370 asmfunc_state
= WAITING_ENDASMFUNC
;
3376 /* Can't use symbol_new here, so have to create a symbol and then at
3377 a later date assign it a value. Thats what these functions do. */
3380 symbol_locate (symbolS
* symbolP
,
3381 const char * name
, /* It is copied, the caller can modify. */
3382 segT segment
, /* Segment identifier (SEG_<something>). */
3383 valueT valu
, /* Symbol value. */
3384 fragS
* frag
) /* Associated fragment. */
3387 char * preserved_copy_of_name
;
3389 name_length
= strlen (name
) + 1; /* +1 for \0. */
3390 obstack_grow (¬es
, name
, name_length
);
3391 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3393 #ifdef tc_canonicalize_symbol_name
3394 preserved_copy_of_name
=
3395 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3398 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3400 S_SET_SEGMENT (symbolP
, segment
);
3401 S_SET_VALUE (symbolP
, valu
);
3402 symbol_clear_list_pointers (symbolP
);
3404 symbol_set_frag (symbolP
, frag
);
3406 /* Link to end of symbol chain. */
3408 extern int symbol_table_frozen
;
3410 if (symbol_table_frozen
)
3414 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3416 obj_symbol_new_hook (symbolP
);
3418 #ifdef tc_symbol_new_hook
3419 tc_symbol_new_hook (symbolP
);
3423 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3424 #endif /* DEBUG_SYMS */
3428 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3431 literal_pool
* pool
;
3434 pool
= find_literal_pool ();
3436 || pool
->symbol
== NULL
3437 || pool
->next_free_entry
== 0)
3440 /* Align pool as you have word accesses.
3441 Only make a frag if we have to. */
3443 frag_align (pool
->alignment
, 0, 0);
3445 record_alignment (now_seg
, 2);
3448 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3449 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3451 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3453 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3454 (valueT
) frag_now_fix (), frag_now
);
3455 symbol_table_insert (pool
->symbol
);
3457 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3459 #if defined OBJ_COFF || defined OBJ_ELF
3460 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3463 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3466 if (debug_type
== DEBUG_DWARF2
)
3467 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3469 /* First output the expression in the instruction to the pool. */
3470 emit_expr (&(pool
->literals
[entry
]),
3471 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3474 /* Mark the pool as empty. */
3475 pool
->next_free_entry
= 0;
3476 pool
->symbol
= NULL
;
3480 /* Forward declarations for functions below, in the MD interface
3482 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3483 static valueT
create_unwind_entry (int);
3484 static void start_unwind_section (const segT
, int);
3485 static void add_unwind_opcode (valueT
, int);
3486 static void flush_pending_unwind (void);
3488 /* Directives: Data. */
3491 s_arm_elf_cons (int nbytes
)
3495 #ifdef md_flush_pending_output
3496 md_flush_pending_output ();
3499 if (is_it_end_of_statement ())
3501 demand_empty_rest_of_line ();
3505 #ifdef md_cons_align
3506 md_cons_align (nbytes
);
3509 mapping_state (MAP_DATA
);
3513 char *base
= input_line_pointer
;
3517 if (exp
.X_op
!= O_symbol
)
3518 emit_expr (&exp
, (unsigned int) nbytes
);
3521 char *before_reloc
= input_line_pointer
;
3522 reloc
= parse_reloc (&input_line_pointer
);
3525 as_bad (_("unrecognized relocation suffix"));
3526 ignore_rest_of_line ();
3529 else if (reloc
== BFD_RELOC_UNUSED
)
3530 emit_expr (&exp
, (unsigned int) nbytes
);
3533 reloc_howto_type
*howto
= (reloc_howto_type
*)
3534 bfd_reloc_type_lookup (stdoutput
,
3535 (bfd_reloc_code_real_type
) reloc
);
3536 int size
= bfd_get_reloc_size (howto
);
3538 if (reloc
== BFD_RELOC_ARM_PLT32
)
3540 as_bad (_("(plt) is only valid on branch targets"));
3541 reloc
= BFD_RELOC_UNUSED
;
3546 as_bad (_("%s relocations do not fit in %d bytes"),
3547 howto
->name
, nbytes
);
3550 /* We've parsed an expression stopping at O_symbol.
3551 But there may be more expression left now that we
3552 have parsed the relocation marker. Parse it again.
3553 XXX Surely there is a cleaner way to do this. */
3554 char *p
= input_line_pointer
;
3556 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3557 memcpy (save_buf
, base
, input_line_pointer
- base
);
3558 memmove (base
+ (input_line_pointer
- before_reloc
),
3559 base
, before_reloc
- base
);
3561 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3563 memcpy (base
, save_buf
, p
- base
);
3565 offset
= nbytes
- size
;
3566 p
= frag_more (nbytes
);
3567 memset (p
, 0, nbytes
);
3568 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3569 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3574 while (*input_line_pointer
++ == ',');
3576 /* Put terminator back into stream. */
3577 input_line_pointer
--;
3578 demand_empty_rest_of_line ();
3581 /* Emit an expression containing a 32-bit thumb instruction.
3582 Implementation based on put_thumb32_insn. */
3585 emit_thumb32_expr (expressionS
* exp
)
3587 expressionS exp_high
= *exp
;
3589 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3590 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3591 exp
->X_add_number
&= 0xffff;
3592 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3595 /* Guess the instruction size based on the opcode. */
3598 thumb_insn_size (int opcode
)
3600 if ((unsigned int) opcode
< 0xe800u
)
3602 else if ((unsigned int) opcode
>= 0xe8000000u
)
3609 emit_insn (expressionS
*exp
, int nbytes
)
3613 if (exp
->X_op
== O_constant
)
3618 size
= thumb_insn_size (exp
->X_add_number
);
3622 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3624 as_bad (_(".inst.n operand too big. "\
3625 "Use .inst.w instead"));
3630 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3631 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3633 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3635 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3636 emit_thumb32_expr (exp
);
3638 emit_expr (exp
, (unsigned int) size
);
3640 it_fsm_post_encode ();
3644 as_bad (_("cannot determine Thumb instruction size. " \
3645 "Use .inst.n/.inst.w instead"));
3648 as_bad (_("constant expression required"));
3653 /* Like s_arm_elf_cons but do not use md_cons_align and
3654 set the mapping state to MAP_ARM/MAP_THUMB. */
3657 s_arm_elf_inst (int nbytes
)
3659 if (is_it_end_of_statement ())
3661 demand_empty_rest_of_line ();
3665 /* Calling mapping_state () here will not change ARM/THUMB,
3666 but will ensure not to be in DATA state. */
3669 mapping_state (MAP_THUMB
);
3674 as_bad (_("width suffixes are invalid in ARM mode"));
3675 ignore_rest_of_line ();
3681 mapping_state (MAP_ARM
);
3690 if (! emit_insn (& exp
, nbytes
))
3692 ignore_rest_of_line ();
3696 while (*input_line_pointer
++ == ',');
3698 /* Put terminator back into stream. */
3699 input_line_pointer
--;
3700 demand_empty_rest_of_line ();
3703 /* Parse a .rel31 directive. */
3706 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3713 if (*input_line_pointer
== '1')
3714 highbit
= 0x80000000;
3715 else if (*input_line_pointer
!= '0')
3716 as_bad (_("expected 0 or 1"));
3718 input_line_pointer
++;
3719 if (*input_line_pointer
!= ',')
3720 as_bad (_("missing comma"));
3721 input_line_pointer
++;
3723 #ifdef md_flush_pending_output
3724 md_flush_pending_output ();
3727 #ifdef md_cons_align
3731 mapping_state (MAP_DATA
);
3736 md_number_to_chars (p
, highbit
, 4);
3737 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3738 BFD_RELOC_ARM_PREL31
);
3740 demand_empty_rest_of_line ();
3743 /* Directives: AEABI stack-unwind tables. */
3745 /* Parse an unwind_fnstart directive. Simply records the current location. */
3748 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3750 demand_empty_rest_of_line ();
3751 if (unwind
.proc_start
)
3753 as_bad (_("duplicate .fnstart directive"));
3757 /* Mark the start of the function. */
3758 unwind
.proc_start
= expr_build_dot ();
3760 /* Reset the rest of the unwind info. */
3761 unwind
.opcode_count
= 0;
3762 unwind
.table_entry
= NULL
;
3763 unwind
.personality_routine
= NULL
;
3764 unwind
.personality_index
= -1;
3765 unwind
.frame_size
= 0;
3766 unwind
.fp_offset
= 0;
3767 unwind
.fp_reg
= REG_SP
;
3769 unwind
.sp_restored
= 0;
3773 /* Parse a handlerdata directive. Creates the exception handling table entry
3774 for the function. */
3777 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3779 demand_empty_rest_of_line ();
3780 if (!unwind
.proc_start
)
3781 as_bad (MISSING_FNSTART
);
3783 if (unwind
.table_entry
)
3784 as_bad (_("duplicate .handlerdata directive"));
3786 create_unwind_entry (1);
3789 /* Parse an unwind_fnend directive. Generates the index table entry. */
3792 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3797 unsigned int marked_pr_dependency
;
3799 demand_empty_rest_of_line ();
3801 if (!unwind
.proc_start
)
3803 as_bad (_(".fnend directive without .fnstart"));
3807 /* Add eh table entry. */
3808 if (unwind
.table_entry
== NULL
)
3809 val
= create_unwind_entry (0);
3813 /* Add index table entry. This is two words. */
3814 start_unwind_section (unwind
.saved_seg
, 1);
3815 frag_align (2, 0, 0);
3816 record_alignment (now_seg
, 2);
3818 ptr
= frag_more (8);
3820 where
= frag_now_fix () - 8;
3822 /* Self relative offset of the function start. */
3823 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3824 BFD_RELOC_ARM_PREL31
);
3826 /* Indicate dependency on EHABI-defined personality routines to the
3827 linker, if it hasn't been done already. */
3828 marked_pr_dependency
3829 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3830 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3831 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3833 static const char *const name
[] =
3835 "__aeabi_unwind_cpp_pr0",
3836 "__aeabi_unwind_cpp_pr1",
3837 "__aeabi_unwind_cpp_pr2"
3839 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3840 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3841 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3842 |= 1 << unwind
.personality_index
;
3846 /* Inline exception table entry. */
3847 md_number_to_chars (ptr
+ 4, val
, 4);
3849 /* Self relative offset of the table entry. */
3850 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3851 BFD_RELOC_ARM_PREL31
);
3853 /* Restore the original section. */
3854 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3856 unwind
.proc_start
= NULL
;
3860 /* Parse an unwind_cantunwind directive. */
3863 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3865 demand_empty_rest_of_line ();
3866 if (!unwind
.proc_start
)
3867 as_bad (MISSING_FNSTART
);
3869 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3870 as_bad (_("personality routine specified for cantunwind frame"));
3872 unwind
.personality_index
= -2;
3876 /* Parse a personalityindex directive. */
3879 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3883 if (!unwind
.proc_start
)
3884 as_bad (MISSING_FNSTART
);
3886 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3887 as_bad (_("duplicate .personalityindex directive"));
3891 if (exp
.X_op
!= O_constant
3892 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3894 as_bad (_("bad personality routine number"));
3895 ignore_rest_of_line ();
3899 unwind
.personality_index
= exp
.X_add_number
;
3901 demand_empty_rest_of_line ();
3905 /* Parse a personality directive. */
3908 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3912 if (!unwind
.proc_start
)
3913 as_bad (MISSING_FNSTART
);
3915 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3916 as_bad (_("duplicate .personality directive"));
3918 name
= input_line_pointer
;
3919 c
= get_symbol_end ();
3920 p
= input_line_pointer
;
3921 unwind
.personality_routine
= symbol_find_or_make (name
);
3923 demand_empty_rest_of_line ();
3927 /* Parse a directive saving core registers. */
3930 s_arm_unwind_save_core (void)
3936 range
= parse_reg_list (&input_line_pointer
);
3939 as_bad (_("expected register list"));
3940 ignore_rest_of_line ();
3944 demand_empty_rest_of_line ();
3946 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3947 into .unwind_save {..., sp...}. We aren't bothered about the value of
3948 ip because it is clobbered by calls. */
3949 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3950 && (range
& 0x3000) == 0x1000)
3952 unwind
.opcode_count
--;
3953 unwind
.sp_restored
= 0;
3954 range
= (range
| 0x2000) & ~0x1000;
3955 unwind
.pending_offset
= 0;
3961 /* See if we can use the short opcodes. These pop a block of up to 8
3962 registers starting with r4, plus maybe r14. */
3963 for (n
= 0; n
< 8; n
++)
3965 /* Break at the first non-saved register. */
3966 if ((range
& (1 << (n
+ 4))) == 0)
3969 /* See if there are any other bits set. */
3970 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3972 /* Use the long form. */
3973 op
= 0x8000 | ((range
>> 4) & 0xfff);
3974 add_unwind_opcode (op
, 2);
3978 /* Use the short form. */
3980 op
= 0xa8; /* Pop r14. */
3982 op
= 0xa0; /* Do not pop r14. */
3984 add_unwind_opcode (op
, 1);
3991 op
= 0xb100 | (range
& 0xf);
3992 add_unwind_opcode (op
, 2);
3995 /* Record the number of bytes pushed. */
3996 for (n
= 0; n
< 16; n
++)
3998 if (range
& (1 << n
))
3999 unwind
.frame_size
+= 4;
4004 /* Parse a directive saving FPA registers. */
4007 s_arm_unwind_save_fpa (int reg
)
4013 /* Get Number of registers to transfer. */
4014 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4017 exp
.X_op
= O_illegal
;
4019 if (exp
.X_op
!= O_constant
)
4021 as_bad (_("expected , <constant>"));
4022 ignore_rest_of_line ();
4026 num_regs
= exp
.X_add_number
;
4028 if (num_regs
< 1 || num_regs
> 4)
4030 as_bad (_("number of registers must be in the range [1:4]"));
4031 ignore_rest_of_line ();
4035 demand_empty_rest_of_line ();
4040 op
= 0xb4 | (num_regs
- 1);
4041 add_unwind_opcode (op
, 1);
4046 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4047 add_unwind_opcode (op
, 2);
4049 unwind
.frame_size
+= num_regs
* 12;
4053 /* Parse a directive saving VFP registers for ARMv6 and above. */
4056 s_arm_unwind_save_vfp_armv6 (void)
4061 int num_vfpv3_regs
= 0;
4062 int num_regs_below_16
;
4064 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4067 as_bad (_("expected register list"));
4068 ignore_rest_of_line ();
4072 demand_empty_rest_of_line ();
4074 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4075 than FSTMX/FLDMX-style ones). */
4077 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4079 num_vfpv3_regs
= count
;
4080 else if (start
+ count
> 16)
4081 num_vfpv3_regs
= start
+ count
- 16;
4083 if (num_vfpv3_regs
> 0)
4085 int start_offset
= start
> 16 ? start
- 16 : 0;
4086 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4087 add_unwind_opcode (op
, 2);
4090 /* Generate opcode for registers numbered in the range 0 .. 15. */
4091 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4092 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4093 if (num_regs_below_16
> 0)
4095 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4096 add_unwind_opcode (op
, 2);
4099 unwind
.frame_size
+= count
* 8;
4103 /* Parse a directive saving VFP registers for pre-ARMv6. */
4106 s_arm_unwind_save_vfp (void)
4112 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4115 as_bad (_("expected register list"));
4116 ignore_rest_of_line ();
4120 demand_empty_rest_of_line ();
4125 op
= 0xb8 | (count
- 1);
4126 add_unwind_opcode (op
, 1);
4131 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4132 add_unwind_opcode (op
, 2);
4134 unwind
.frame_size
+= count
* 8 + 4;
4138 /* Parse a directive saving iWMMXt data registers. */
4141 s_arm_unwind_save_mmxwr (void)
4149 if (*input_line_pointer
== '{')
4150 input_line_pointer
++;
4154 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4158 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4163 as_tsktsk (_("register list not in ascending order"));
4166 if (*input_line_pointer
== '-')
4168 input_line_pointer
++;
4169 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4172 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4175 else if (reg
>= hi_reg
)
4177 as_bad (_("bad register range"));
4180 for (; reg
< hi_reg
; reg
++)
4184 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4186 skip_past_char (&input_line_pointer
, '}');
4188 demand_empty_rest_of_line ();
4190 /* Generate any deferred opcodes because we're going to be looking at
4192 flush_pending_unwind ();
4194 for (i
= 0; i
< 16; i
++)
4196 if (mask
& (1 << i
))
4197 unwind
.frame_size
+= 8;
4200 /* Attempt to combine with a previous opcode. We do this because gcc
4201 likes to output separate unwind directives for a single block of
4203 if (unwind
.opcode_count
> 0)
4205 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4206 if ((i
& 0xf8) == 0xc0)
4209 /* Only merge if the blocks are contiguous. */
4212 if ((mask
& 0xfe00) == (1 << 9))
4214 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4215 unwind
.opcode_count
--;
4218 else if (i
== 6 && unwind
.opcode_count
>= 2)
4220 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4224 op
= 0xffff << (reg
- 1);
4226 && ((mask
& op
) == (1u << (reg
- 1))))
4228 op
= (1 << (reg
+ i
+ 1)) - 1;
4229 op
&= ~((1 << reg
) - 1);
4231 unwind
.opcode_count
-= 2;
4238 /* We want to generate opcodes in the order the registers have been
4239 saved, ie. descending order. */
4240 for (reg
= 15; reg
>= -1; reg
--)
4242 /* Save registers in blocks. */
4244 || !(mask
& (1 << reg
)))
4246 /* We found an unsaved reg. Generate opcodes to save the
4253 op
= 0xc0 | (hi_reg
- 10);
4254 add_unwind_opcode (op
, 1);
4259 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4260 add_unwind_opcode (op
, 2);
4269 ignore_rest_of_line ();
4273 s_arm_unwind_save_mmxwcg (void)
4280 if (*input_line_pointer
== '{')
4281 input_line_pointer
++;
4283 skip_whitespace (input_line_pointer
);
4287 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4291 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4297 as_tsktsk (_("register list not in ascending order"));
4300 if (*input_line_pointer
== '-')
4302 input_line_pointer
++;
4303 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4306 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4309 else if (reg
>= hi_reg
)
4311 as_bad (_("bad register range"));
4314 for (; reg
< hi_reg
; reg
++)
4318 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4320 skip_past_char (&input_line_pointer
, '}');
4322 demand_empty_rest_of_line ();
4324 /* Generate any deferred opcodes because we're going to be looking at
4326 flush_pending_unwind ();
4328 for (reg
= 0; reg
< 16; reg
++)
4330 if (mask
& (1 << reg
))
4331 unwind
.frame_size
+= 4;
4334 add_unwind_opcode (op
, 2);
4337 ignore_rest_of_line ();
4341 /* Parse an unwind_save directive.
4342 If the argument is non-zero, this is a .vsave directive. */
4345 s_arm_unwind_save (int arch_v6
)
4348 struct reg_entry
*reg
;
4349 bfd_boolean had_brace
= FALSE
;
4351 if (!unwind
.proc_start
)
4352 as_bad (MISSING_FNSTART
);
4354 /* Figure out what sort of save we have. */
4355 peek
= input_line_pointer
;
4363 reg
= arm_reg_parse_multi (&peek
);
4367 as_bad (_("register expected"));
4368 ignore_rest_of_line ();
4377 as_bad (_("FPA .unwind_save does not take a register list"));
4378 ignore_rest_of_line ();
4381 input_line_pointer
= peek
;
4382 s_arm_unwind_save_fpa (reg
->number
);
4386 s_arm_unwind_save_core ();
4391 s_arm_unwind_save_vfp_armv6 ();
4393 s_arm_unwind_save_vfp ();
4396 case REG_TYPE_MMXWR
:
4397 s_arm_unwind_save_mmxwr ();
4400 case REG_TYPE_MMXWCG
:
4401 s_arm_unwind_save_mmxwcg ();
4405 as_bad (_(".unwind_save does not support this kind of register"));
4406 ignore_rest_of_line ();
4411 /* Parse an unwind_movsp directive. */
4414 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4420 if (!unwind
.proc_start
)
4421 as_bad (MISSING_FNSTART
);
4423 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4426 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4427 ignore_rest_of_line ();
4431 /* Optional constant. */
4432 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4434 if (immediate_for_directive (&offset
) == FAIL
)
4440 demand_empty_rest_of_line ();
4442 if (reg
== REG_SP
|| reg
== REG_PC
)
4444 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4448 if (unwind
.fp_reg
!= REG_SP
)
4449 as_bad (_("unexpected .unwind_movsp directive"));
4451 /* Generate opcode to restore the value. */
4453 add_unwind_opcode (op
, 1);
4455 /* Record the information for later. */
4456 unwind
.fp_reg
= reg
;
4457 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4458 unwind
.sp_restored
= 1;
4461 /* Parse an unwind_pad directive. */
4464 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4468 if (!unwind
.proc_start
)
4469 as_bad (MISSING_FNSTART
);
4471 if (immediate_for_directive (&offset
) == FAIL
)
4476 as_bad (_("stack increment must be multiple of 4"));
4477 ignore_rest_of_line ();
4481 /* Don't generate any opcodes, just record the details for later. */
4482 unwind
.frame_size
+= offset
;
4483 unwind
.pending_offset
+= offset
;
4485 demand_empty_rest_of_line ();
4488 /* Parse an unwind_setfp directive. */
4491 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4497 if (!unwind
.proc_start
)
4498 as_bad (MISSING_FNSTART
);
4500 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4501 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4504 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4506 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4508 as_bad (_("expected <reg>, <reg>"));
4509 ignore_rest_of_line ();
4513 /* Optional constant. */
4514 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4516 if (immediate_for_directive (&offset
) == FAIL
)
4522 demand_empty_rest_of_line ();
4524 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4526 as_bad (_("register must be either sp or set by a previous"
4527 "unwind_movsp directive"));
4531 /* Don't generate any opcodes, just record the information for later. */
4532 unwind
.fp_reg
= fp_reg
;
4534 if (sp_reg
== REG_SP
)
4535 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4537 unwind
.fp_offset
-= offset
;
4540 /* Parse an unwind_raw directive. */
4543 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4546 /* This is an arbitrary limit. */
4547 unsigned char op
[16];
4550 if (!unwind
.proc_start
)
4551 as_bad (MISSING_FNSTART
);
4554 if (exp
.X_op
== O_constant
4555 && skip_past_comma (&input_line_pointer
) != FAIL
)
4557 unwind
.frame_size
+= exp
.X_add_number
;
4561 exp
.X_op
= O_illegal
;
4563 if (exp
.X_op
!= O_constant
)
4565 as_bad (_("expected <offset>, <opcode>"));
4566 ignore_rest_of_line ();
4572 /* Parse the opcode. */
4577 as_bad (_("unwind opcode too long"));
4578 ignore_rest_of_line ();
4580 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4582 as_bad (_("invalid unwind opcode"));
4583 ignore_rest_of_line ();
4586 op
[count
++] = exp
.X_add_number
;
4588 /* Parse the next byte. */
4589 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4595 /* Add the opcode bytes in reverse order. */
4597 add_unwind_opcode (op
[count
], 1);
4599 demand_empty_rest_of_line ();
4603 /* Parse a .eabi_attribute directive. */
4606 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4608 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4610 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4611 attributes_set_explicitly
[tag
] = 1;
4614 /* Emit a tls fix for the symbol. */
4617 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4621 #ifdef md_flush_pending_output
4622 md_flush_pending_output ();
4625 #ifdef md_cons_align
4629 /* Since we're just labelling the code, there's no need to define a
4632 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4633 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4634 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4635 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4637 #endif /* OBJ_ELF */
4639 static void s_arm_arch (int);
4640 static void s_arm_object_arch (int);
4641 static void s_arm_cpu (int);
4642 static void s_arm_fpu (int);
4643 static void s_arm_arch_extension (int);
4648 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4655 if (exp
.X_op
== O_symbol
)
4656 exp
.X_op
= O_secrel
;
4658 emit_expr (&exp
, 4);
4660 while (*input_line_pointer
++ == ',');
4662 input_line_pointer
--;
4663 demand_empty_rest_of_line ();
4667 /* This table describes all the machine specific pseudo-ops the assembler
4668 has to support. The fields are:
4669 pseudo-op name without dot
4670 function to call to execute this pseudo-op
4671 Integer arg to pass to the function. */
4673 const pseudo_typeS md_pseudo_table
[] =
4675 /* Never called because '.req' does not start a line. */
4676 { "req", s_req
, 0 },
4677 /* Following two are likewise never called. */
4680 { "unreq", s_unreq
, 0 },
4681 { "bss", s_bss
, 0 },
4682 { "align", s_align
, 0 },
4683 { "arm", s_arm
, 0 },
4684 { "thumb", s_thumb
, 0 },
4685 { "code", s_code
, 0 },
4686 { "force_thumb", s_force_thumb
, 0 },
4687 { "thumb_func", s_thumb_func
, 0 },
4688 { "thumb_set", s_thumb_set
, 0 },
4689 { "even", s_even
, 0 },
4690 { "ltorg", s_ltorg
, 0 },
4691 { "pool", s_ltorg
, 0 },
4692 { "syntax", s_syntax
, 0 },
4693 { "cpu", s_arm_cpu
, 0 },
4694 { "arch", s_arm_arch
, 0 },
4695 { "object_arch", s_arm_object_arch
, 0 },
4696 { "fpu", s_arm_fpu
, 0 },
4697 { "arch_extension", s_arm_arch_extension
, 0 },
4699 { "word", s_arm_elf_cons
, 4 },
4700 { "long", s_arm_elf_cons
, 4 },
4701 { "inst.n", s_arm_elf_inst
, 2 },
4702 { "inst.w", s_arm_elf_inst
, 4 },
4703 { "inst", s_arm_elf_inst
, 0 },
4704 { "rel31", s_arm_rel31
, 0 },
4705 { "fnstart", s_arm_unwind_fnstart
, 0 },
4706 { "fnend", s_arm_unwind_fnend
, 0 },
4707 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4708 { "personality", s_arm_unwind_personality
, 0 },
4709 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4710 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4711 { "save", s_arm_unwind_save
, 0 },
4712 { "vsave", s_arm_unwind_save
, 1 },
4713 { "movsp", s_arm_unwind_movsp
, 0 },
4714 { "pad", s_arm_unwind_pad
, 0 },
4715 { "setfp", s_arm_unwind_setfp
, 0 },
4716 { "unwind_raw", s_arm_unwind_raw
, 0 },
4717 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4718 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4722 /* These are used for dwarf. */
4726 /* These are used for dwarf2. */
4727 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4728 { "loc", dwarf2_directive_loc
, 0 },
4729 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4731 { "extend", float_cons
, 'x' },
4732 { "ldouble", float_cons
, 'x' },
4733 { "packed", float_cons
, 'p' },
4735 {"secrel32", pe_directive_secrel
, 0},
4738 /* These are for compatibility with CodeComposer Studio. */
4739 {"ref", s_ccs_ref
, 0},
4740 {"def", s_ccs_def
, 0},
4741 {"asmfunc", s_ccs_asmfunc
, 0},
4742 {"endasmfunc", s_ccs_endasmfunc
, 0},
4747 /* Parser functions used exclusively in instruction operands. */
4749 /* Generic immediate-value read function for use in insn parsing.
4750 STR points to the beginning of the immediate (the leading #);
4751 VAL receives the value; if the value is outside [MIN, MAX]
4752 issue an error. PREFIX_OPT is true if the immediate prefix is
4756 parse_immediate (char **str
, int *val
, int min
, int max
,
4757 bfd_boolean prefix_opt
)
4760 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4761 if (exp
.X_op
!= O_constant
)
4763 inst
.error
= _("constant expression required");
4767 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4769 inst
.error
= _("immediate value out of range");
4773 *val
= exp
.X_add_number
;
4777 /* Less-generic immediate-value read function with the possibility of loading a
4778 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4779 instructions. Puts the result directly in inst.operands[i]. */
4782 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4783 bfd_boolean allow_symbol_p
)
4786 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4789 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4791 if (exp_p
->X_op
== O_constant
)
4793 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4794 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4795 O_constant. We have to be careful not to break compilation for
4796 32-bit X_add_number, though. */
4797 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4799 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4800 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4802 inst
.operands
[i
].regisimm
= 1;
4805 else if (exp_p
->X_op
== O_big
4806 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4808 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4810 /* Bignums have their least significant bits in
4811 generic_bignum[0]. Make sure we put 32 bits in imm and
4812 32 bits in reg, in a (hopefully) portable way. */
4813 gas_assert (parts
!= 0);
4815 /* Make sure that the number is not too big.
4816 PR 11972: Bignums can now be sign-extended to the
4817 size of a .octa so check that the out of range bits
4818 are all zero or all one. */
4819 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4821 LITTLENUM_TYPE m
= -1;
4823 if (generic_bignum
[parts
* 2] != 0
4824 && generic_bignum
[parts
* 2] != m
)
4827 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4828 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4832 inst
.operands
[i
].imm
= 0;
4833 for (j
= 0; j
< parts
; j
++, idx
++)
4834 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4835 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4836 inst
.operands
[i
].reg
= 0;
4837 for (j
= 0; j
< parts
; j
++, idx
++)
4838 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4839 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4840 inst
.operands
[i
].regisimm
= 1;
4842 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4850 /* Returns the pseudo-register number of an FPA immediate constant,
4851 or FAIL if there isn't a valid constant here. */
4854 parse_fpa_immediate (char ** str
)
4856 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4862 /* First try and match exact strings, this is to guarantee
4863 that some formats will work even for cross assembly. */
4865 for (i
= 0; fp_const
[i
]; i
++)
4867 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4871 *str
+= strlen (fp_const
[i
]);
4872 if (is_end_of_line
[(unsigned char) **str
])
4878 /* Just because we didn't get a match doesn't mean that the constant
4879 isn't valid, just that it is in a format that we don't
4880 automatically recognize. Try parsing it with the standard
4881 expression routines. */
4883 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4885 /* Look for a raw floating point number. */
4886 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4887 && is_end_of_line
[(unsigned char) *save_in
])
4889 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4891 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4893 if (words
[j
] != fp_values
[i
][j
])
4897 if (j
== MAX_LITTLENUMS
)
4905 /* Try and parse a more complex expression, this will probably fail
4906 unless the code uses a floating point prefix (eg "0f"). */
4907 save_in
= input_line_pointer
;
4908 input_line_pointer
= *str
;
4909 if (expression (&exp
) == absolute_section
4910 && exp
.X_op
== O_big
4911 && exp
.X_add_number
< 0)
4913 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4915 if (gen_to_words (words
, 5, (long) 15) == 0)
4917 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4919 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4921 if (words
[j
] != fp_values
[i
][j
])
4925 if (j
== MAX_LITTLENUMS
)
4927 *str
= input_line_pointer
;
4928 input_line_pointer
= save_in
;
4935 *str
= input_line_pointer
;
4936 input_line_pointer
= save_in
;
4937 inst
.error
= _("invalid FPA immediate expression");
4941 /* Returns 1 if a number has "quarter-precision" float format
4942 0baBbbbbbc defgh000 00000000 00000000. */
4945 is_quarter_float (unsigned imm
)
4947 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4948 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4952 /* Detect the presence of a floating point or integer zero constant,
4956 parse_ifimm_zero (char **in
)
4960 if (!is_immediate_prefix (**in
))
4964 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4965 &generic_floating_point_number
);
4968 && generic_floating_point_number
.sign
== '+'
4969 && (generic_floating_point_number
.low
4970 > generic_floating_point_number
.leader
))
4976 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4977 0baBbbbbbc defgh000 00000000 00000000.
4978 The zero and minus-zero cases need special handling, since they can't be
4979 encoded in the "quarter-precision" float format, but can nonetheless be
4980 loaded as integer constants. */
4983 parse_qfloat_immediate (char **ccp
, int *immed
)
4987 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4988 int found_fpchar
= 0;
4990 skip_past_char (&str
, '#');
4992 /* We must not accidentally parse an integer as a floating-point number. Make
4993 sure that the value we parse is not an integer by checking for special
4994 characters '.' or 'e'.
4995 FIXME: This is a horrible hack, but doing better is tricky because type
4996 information isn't in a very usable state at parse time. */
4998 skip_whitespace (fpnum
);
5000 if (strncmp (fpnum
, "0x", 2) == 0)
5004 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5005 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5015 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5017 unsigned fpword
= 0;
5020 /* Our FP word must be 32 bits (single-precision FP). */
5021 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5023 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5027 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5040 /* Shift operands. */
5043 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5046 struct asm_shift_name
5049 enum shift_kind kind
;
5052 /* Third argument to parse_shift. */
5053 enum parse_shift_mode
5055 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5056 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5057 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5058 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5059 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5062 /* Parse a <shift> specifier on an ARM data processing instruction.
5063 This has three forms:
5065 (LSL|LSR|ASL|ASR|ROR) Rs
5066 (LSL|LSR|ASL|ASR|ROR) #imm
5069 Note that ASL is assimilated to LSL in the instruction encoding, and
5070 RRX to ROR #0 (which cannot be written as such). */
5073 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5075 const struct asm_shift_name
*shift_name
;
5076 enum shift_kind shift
;
5081 for (p
= *str
; ISALPHA (*p
); p
++)
5086 inst
.error
= _("shift expression expected");
5090 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5093 if (shift_name
== NULL
)
5095 inst
.error
= _("shift expression expected");
5099 shift
= shift_name
->kind
;
5103 case NO_SHIFT_RESTRICT
:
5104 case SHIFT_IMMEDIATE
: break;
5106 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5107 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5109 inst
.error
= _("'LSL' or 'ASR' required");
5114 case SHIFT_LSL_IMMEDIATE
:
5115 if (shift
!= SHIFT_LSL
)
5117 inst
.error
= _("'LSL' required");
5122 case SHIFT_ASR_IMMEDIATE
:
5123 if (shift
!= SHIFT_ASR
)
5125 inst
.error
= _("'ASR' required");
5133 if (shift
!= SHIFT_RRX
)
5135 /* Whitespace can appear here if the next thing is a bare digit. */
5136 skip_whitespace (p
);
5138 if (mode
== NO_SHIFT_RESTRICT
5139 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5141 inst
.operands
[i
].imm
= reg
;
5142 inst
.operands
[i
].immisreg
= 1;
5144 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5147 inst
.operands
[i
].shift_kind
= shift
;
5148 inst
.operands
[i
].shifted
= 1;
5153 /* Parse a <shifter_operand> for an ARM data processing instruction:
5156 #<immediate>, <rotate>
5160 where <shift> is defined by parse_shift above, and <rotate> is a
5161 multiple of 2 between 0 and 30. Validation of immediate operands
5162 is deferred to md_apply_fix. */
5165 parse_shifter_operand (char **str
, int i
)
5170 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5172 inst
.operands
[i
].reg
= value
;
5173 inst
.operands
[i
].isreg
= 1;
5175 /* parse_shift will override this if appropriate */
5176 inst
.reloc
.exp
.X_op
= O_constant
;
5177 inst
.reloc
.exp
.X_add_number
= 0;
5179 if (skip_past_comma (str
) == FAIL
)
5182 /* Shift operation on register. */
5183 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5186 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5189 if (skip_past_comma (str
) == SUCCESS
)
5191 /* #x, y -- ie explicit rotation by Y. */
5192 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5195 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5197 inst
.error
= _("constant expression expected");
5201 value
= exp
.X_add_number
;
5202 if (value
< 0 || value
> 30 || value
% 2 != 0)
5204 inst
.error
= _("invalid rotation");
5207 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5209 inst
.error
= _("invalid constant");
5213 /* Encode as specified. */
5214 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5218 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5219 inst
.reloc
.pc_rel
= 0;
5223 /* Group relocation information. Each entry in the table contains the
5224 textual name of the relocation as may appear in assembler source
5225 and must end with a colon.
5226 Along with this textual name are the relocation codes to be used if
5227 the corresponding instruction is an ALU instruction (ADD or SUB only),
5228 an LDR, an LDRS, or an LDC. */
5230 struct group_reloc_table_entry
5241 /* Varieties of non-ALU group relocation. */
5248 static struct group_reloc_table_entry group_reloc_table
[] =
5249 { /* Program counter relative: */
5251 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5256 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5257 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5258 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5259 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5261 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5266 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5267 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5268 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5269 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5271 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5272 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5273 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5274 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5275 /* Section base relative */
5277 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5282 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5283 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5284 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5285 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5287 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5292 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5293 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5294 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5295 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5297 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5298 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5299 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5300 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
5302 /* Given the address of a pointer pointing to the textual name of a group
5303 relocation as may appear in assembler source, attempt to find its details
5304 in group_reloc_table. The pointer will be updated to the character after
5305 the trailing colon. On failure, FAIL will be returned; SUCCESS
5306 otherwise. On success, *entry will be updated to point at the relevant
5307 group_reloc_table entry. */
5310 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5313 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5315 int length
= strlen (group_reloc_table
[i
].name
);
5317 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5318 && (*str
)[length
] == ':')
5320 *out
= &group_reloc_table
[i
];
5321 *str
+= (length
+ 1);
5329 /* Parse a <shifter_operand> for an ARM data processing instruction
5330 (as for parse_shifter_operand) where group relocations are allowed:
5333 #<immediate>, <rotate>
5334 #:<group_reloc>:<expression>
5338 where <group_reloc> is one of the strings defined in group_reloc_table.
5339 The hashes are optional.
5341 Everything else is as for parse_shifter_operand. */
5343 static parse_operand_result
5344 parse_shifter_operand_group_reloc (char **str
, int i
)
5346 /* Determine if we have the sequence of characters #: or just :
5347 coming next. If we do, then we check for a group relocation.
5348 If we don't, punt the whole lot to parse_shifter_operand. */
5350 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5351 || (*str
)[0] == ':')
5353 struct group_reloc_table_entry
*entry
;
5355 if ((*str
)[0] == '#')
5360 /* Try to parse a group relocation. Anything else is an error. */
5361 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5363 inst
.error
= _("unknown group relocation");
5364 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5367 /* We now have the group relocation table entry corresponding to
5368 the name in the assembler source. Next, we parse the expression. */
5369 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5370 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5372 /* Record the relocation type (always the ALU variant here). */
5373 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5374 gas_assert (inst
.reloc
.type
!= 0);
5376 return PARSE_OPERAND_SUCCESS
;
5379 return parse_shifter_operand (str
, i
) == SUCCESS
5380 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5382 /* Never reached. */
5385 /* Parse a Neon alignment expression. Information is written to
5386 inst.operands[i]. We assume the initial ':' has been skipped.
5388 align .imm = align << 8, .immisalign=1, .preind=0 */
5389 static parse_operand_result
5390 parse_neon_alignment (char **str
, int i
)
5395 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5397 if (exp
.X_op
!= O_constant
)
5399 inst
.error
= _("alignment must be constant");
5400 return PARSE_OPERAND_FAIL
;
5403 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5404 inst
.operands
[i
].immisalign
= 1;
5405 /* Alignments are not pre-indexes. */
5406 inst
.operands
[i
].preind
= 0;
5409 return PARSE_OPERAND_SUCCESS
;
5412 /* Parse all forms of an ARM address expression. Information is written
5413 to inst.operands[i] and/or inst.reloc.
5415 Preindexed addressing (.preind=1):
5417 [Rn, #offset] .reg=Rn .reloc.exp=offset
5418 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5419 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5420 .shift_kind=shift .reloc.exp=shift_imm
5422 These three may have a trailing ! which causes .writeback to be set also.
5424 Postindexed addressing (.postind=1, .writeback=1):
5426 [Rn], #offset .reg=Rn .reloc.exp=offset
5427 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5428 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5429 .shift_kind=shift .reloc.exp=shift_imm
5431 Unindexed addressing (.preind=0, .postind=0):
5433 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5437 [Rn]{!} shorthand for [Rn,#0]{!}
5438 =immediate .isreg=0 .reloc.exp=immediate
5439 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5441 It is the caller's responsibility to check for addressing modes not
5442 supported by the instruction, and to set inst.reloc.type. */
5444 static parse_operand_result
5445 parse_address_main (char **str
, int i
, int group_relocations
,
5446 group_reloc_type group_type
)
5451 if (skip_past_char (&p
, '[') == FAIL
)
5453 if (skip_past_char (&p
, '=') == FAIL
)
5455 /* Bare address - translate to PC-relative offset. */
5456 inst
.reloc
.pc_rel
= 1;
5457 inst
.operands
[i
].reg
= REG_PC
;
5458 inst
.operands
[i
].isreg
= 1;
5459 inst
.operands
[i
].preind
= 1;
5461 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5462 return PARSE_OPERAND_FAIL
;
5464 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5465 /*allow_symbol_p=*/TRUE
))
5466 return PARSE_OPERAND_FAIL
;
5469 return PARSE_OPERAND_SUCCESS
;
5472 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5473 skip_whitespace (p
);
5475 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5477 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5478 return PARSE_OPERAND_FAIL
;
5480 inst
.operands
[i
].reg
= reg
;
5481 inst
.operands
[i
].isreg
= 1;
5483 if (skip_past_comma (&p
) == SUCCESS
)
5485 inst
.operands
[i
].preind
= 1;
5488 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5490 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5492 inst
.operands
[i
].imm
= reg
;
5493 inst
.operands
[i
].immisreg
= 1;
5495 if (skip_past_comma (&p
) == SUCCESS
)
5496 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5497 return PARSE_OPERAND_FAIL
;
5499 else if (skip_past_char (&p
, ':') == SUCCESS
)
5501 /* FIXME: '@' should be used here, but it's filtered out by generic
5502 code before we get to see it here. This may be subject to
5504 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5506 if (result
!= PARSE_OPERAND_SUCCESS
)
5511 if (inst
.operands
[i
].negative
)
5513 inst
.operands
[i
].negative
= 0;
5517 if (group_relocations
5518 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5520 struct group_reloc_table_entry
*entry
;
5522 /* Skip over the #: or : sequence. */
5528 /* Try to parse a group relocation. Anything else is an
5530 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5532 inst
.error
= _("unknown group relocation");
5533 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5536 /* We now have the group relocation table entry corresponding to
5537 the name in the assembler source. Next, we parse the
5539 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5540 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5542 /* Record the relocation type. */
5546 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5550 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5554 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5561 if (inst
.reloc
.type
== 0)
5563 inst
.error
= _("this group relocation is not allowed on this instruction");
5564 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5570 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5571 return PARSE_OPERAND_FAIL
;
5572 /* If the offset is 0, find out if it's a +0 or -0. */
5573 if (inst
.reloc
.exp
.X_op
== O_constant
5574 && inst
.reloc
.exp
.X_add_number
== 0)
5576 skip_whitespace (q
);
5580 skip_whitespace (q
);
5583 inst
.operands
[i
].negative
= 1;
5588 else if (skip_past_char (&p
, ':') == SUCCESS
)
5590 /* FIXME: '@' should be used here, but it's filtered out by generic code
5591 before we get to see it here. This may be subject to change. */
5592 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5594 if (result
!= PARSE_OPERAND_SUCCESS
)
5598 if (skip_past_char (&p
, ']') == FAIL
)
5600 inst
.error
= _("']' expected");
5601 return PARSE_OPERAND_FAIL
;
5604 if (skip_past_char (&p
, '!') == SUCCESS
)
5605 inst
.operands
[i
].writeback
= 1;
5607 else if (skip_past_comma (&p
) == SUCCESS
)
5609 if (skip_past_char (&p
, '{') == SUCCESS
)
5611 /* [Rn], {expr} - unindexed, with option */
5612 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5613 0, 255, TRUE
) == FAIL
)
5614 return PARSE_OPERAND_FAIL
;
5616 if (skip_past_char (&p
, '}') == FAIL
)
5618 inst
.error
= _("'}' expected at end of 'option' field");
5619 return PARSE_OPERAND_FAIL
;
5621 if (inst
.operands
[i
].preind
)
5623 inst
.error
= _("cannot combine index with option");
5624 return PARSE_OPERAND_FAIL
;
5627 return PARSE_OPERAND_SUCCESS
;
5631 inst
.operands
[i
].postind
= 1;
5632 inst
.operands
[i
].writeback
= 1;
5634 if (inst
.operands
[i
].preind
)
5636 inst
.error
= _("cannot combine pre- and post-indexing");
5637 return PARSE_OPERAND_FAIL
;
5641 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5643 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5645 /* We might be using the immediate for alignment already. If we
5646 are, OR the register number into the low-order bits. */
5647 if (inst
.operands
[i
].immisalign
)
5648 inst
.operands
[i
].imm
|= reg
;
5650 inst
.operands
[i
].imm
= reg
;
5651 inst
.operands
[i
].immisreg
= 1;
5653 if (skip_past_comma (&p
) == SUCCESS
)
5654 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5655 return PARSE_OPERAND_FAIL
;
5660 if (inst
.operands
[i
].negative
)
5662 inst
.operands
[i
].negative
= 0;
5665 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5666 return PARSE_OPERAND_FAIL
;
5667 /* If the offset is 0, find out if it's a +0 or -0. */
5668 if (inst
.reloc
.exp
.X_op
== O_constant
5669 && inst
.reloc
.exp
.X_add_number
== 0)
5671 skip_whitespace (q
);
5675 skip_whitespace (q
);
5678 inst
.operands
[i
].negative
= 1;
5684 /* If at this point neither .preind nor .postind is set, we have a
5685 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5686 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5688 inst
.operands
[i
].preind
= 1;
5689 inst
.reloc
.exp
.X_op
= O_constant
;
5690 inst
.reloc
.exp
.X_add_number
= 0;
5693 return PARSE_OPERAND_SUCCESS
;
5697 parse_address (char **str
, int i
)
5699 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5703 static parse_operand_result
5704 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5706 return parse_address_main (str
, i
, 1, type
);
5709 /* Parse an operand for a MOVW or MOVT instruction. */
5711 parse_half (char **str
)
5716 skip_past_char (&p
, '#');
5717 if (strncasecmp (p
, ":lower16:", 9) == 0)
5718 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5719 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5720 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5722 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5725 skip_whitespace (p
);
5728 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5731 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5733 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5735 inst
.error
= _("constant expression expected");
5738 if (inst
.reloc
.exp
.X_add_number
< 0
5739 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5741 inst
.error
= _("immediate value out of range");
5749 /* Miscellaneous. */
5751 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5752 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5754 parse_psr (char **str
, bfd_boolean lhs
)
5757 unsigned long psr_field
;
5758 const struct asm_psr
*psr
;
5760 bfd_boolean is_apsr
= FALSE
;
5761 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5763 /* PR gas/12698: If the user has specified -march=all then m_profile will
5764 be TRUE, but we want to ignore it in this case as we are building for any
5765 CPU type, including non-m variants. */
5766 if (selected_cpu
.core
== arm_arch_any
.core
)
5769 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5770 feature for ease of use and backwards compatibility. */
5772 if (strncasecmp (p
, "SPSR", 4) == 0)
5775 goto unsupported_psr
;
5777 psr_field
= SPSR_BIT
;
5779 else if (strncasecmp (p
, "CPSR", 4) == 0)
5782 goto unsupported_psr
;
5786 else if (strncasecmp (p
, "APSR", 4) == 0)
5788 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5789 and ARMv7-R architecture CPUs. */
5798 while (ISALNUM (*p
) || *p
== '_');
5800 if (strncasecmp (start
, "iapsr", 5) == 0
5801 || strncasecmp (start
, "eapsr", 5) == 0
5802 || strncasecmp (start
, "xpsr", 4) == 0
5803 || strncasecmp (start
, "psr", 3) == 0)
5804 p
= start
+ strcspn (start
, "rR") + 1;
5806 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5812 /* If APSR is being written, a bitfield may be specified. Note that
5813 APSR itself is handled above. */
5814 if (psr
->field
<= 3)
5816 psr_field
= psr
->field
;
5822 /* M-profile MSR instructions have the mask field set to "10", except
5823 *PSR variants which modify APSR, which may use a different mask (and
5824 have been handled already). Do that by setting the PSR_f field
5826 return psr
->field
| (lhs
? PSR_f
: 0);
5829 goto unsupported_psr
;
5835 /* A suffix follows. */
5841 while (ISALNUM (*p
) || *p
== '_');
5845 /* APSR uses a notation for bits, rather than fields. */
5846 unsigned int nzcvq_bits
= 0;
5847 unsigned int g_bit
= 0;
5850 for (bit
= start
; bit
!= p
; bit
++)
5852 switch (TOLOWER (*bit
))
5855 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5859 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5863 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5867 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5871 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5875 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5879 inst
.error
= _("unexpected bit specified after APSR");
5884 if (nzcvq_bits
== 0x1f)
5889 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5891 inst
.error
= _("selected processor does not "
5892 "support DSP extension");
5899 if ((nzcvq_bits
& 0x20) != 0
5900 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5901 || (g_bit
& 0x2) != 0)
5903 inst
.error
= _("bad bitmask specified after APSR");
5909 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5914 psr_field
|= psr
->field
;
5920 goto error
; /* Garbage after "[CS]PSR". */
5922 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5923 is deprecated, but allow it anyway. */
5927 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5930 else if (!m_profile
)
5931 /* These bits are never right for M-profile devices: don't set them
5932 (only code paths which read/write APSR reach here). */
5933 psr_field
|= (PSR_c
| PSR_f
);
5939 inst
.error
= _("selected processor does not support requested special "
5940 "purpose register");
5944 inst
.error
= _("flag for {c}psr instruction expected");
5948 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5949 value suitable for splatting into the AIF field of the instruction. */
5952 parse_cps_flags (char **str
)
5961 case '\0': case ',':
5964 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5965 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5966 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5969 inst
.error
= _("unrecognized CPS flag");
5974 if (saw_a_flag
== 0)
5976 inst
.error
= _("missing CPS flags");
5984 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5985 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5988 parse_endian_specifier (char **str
)
5993 if (strncasecmp (s
, "BE", 2))
5995 else if (strncasecmp (s
, "LE", 2))
5999 inst
.error
= _("valid endian specifiers are be or le");
6003 if (ISALNUM (s
[2]) || s
[2] == '_')
6005 inst
.error
= _("valid endian specifiers are be or le");
6010 return little_endian
;
6013 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6014 value suitable for poking into the rotate field of an sxt or sxta
6015 instruction, or FAIL on error. */
6018 parse_ror (char **str
)
6023 if (strncasecmp (s
, "ROR", 3) == 0)
6027 inst
.error
= _("missing rotation field after comma");
6031 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6036 case 0: *str
= s
; return 0x0;
6037 case 8: *str
= s
; return 0x1;
6038 case 16: *str
= s
; return 0x2;
6039 case 24: *str
= s
; return 0x3;
6042 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6047 /* Parse a conditional code (from conds[] below). The value returned is in the
6048 range 0 .. 14, or FAIL. */
6050 parse_cond (char **str
)
6053 const struct asm_cond
*c
;
6055 /* Condition codes are always 2 characters, so matching up to
6056 3 characters is sufficient. */
6061 while (ISALPHA (*q
) && n
< 3)
6063 cond
[n
] = TOLOWER (*q
);
6068 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6071 inst
.error
= _("condition required");
6079 /* If the given feature available in the selected CPU, mark it as used.
6080 Returns TRUE iff feature is available. */
6082 mark_feature_used (const arm_feature_set
*feature
)
6084 /* Ensure the option is valid on the current architecture. */
6085 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6088 /* Add the appropriate architecture feature for the barrier option used.
6091 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6093 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6098 /* Parse an option for a barrier instruction. Returns the encoding for the
6101 parse_barrier (char **str
)
6104 const struct asm_barrier_opt
*o
;
6107 while (ISALPHA (*q
))
6110 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6115 if (!mark_feature_used (&o
->arch
))
6122 /* Parse the operands of a table branch instruction. Similar to a memory
6125 parse_tb (char **str
)
6130 if (skip_past_char (&p
, '[') == FAIL
)
6132 inst
.error
= _("'[' expected");
6136 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6138 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6141 inst
.operands
[0].reg
= reg
;
6143 if (skip_past_comma (&p
) == FAIL
)
6145 inst
.error
= _("',' expected");
6149 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6151 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6154 inst
.operands
[0].imm
= reg
;
6156 if (skip_past_comma (&p
) == SUCCESS
)
6158 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6160 if (inst
.reloc
.exp
.X_add_number
!= 1)
6162 inst
.error
= _("invalid shift");
6165 inst
.operands
[0].shifted
= 1;
6168 if (skip_past_char (&p
, ']') == FAIL
)
6170 inst
.error
= _("']' expected");
6177 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6178 information on the types the operands can take and how they are encoded.
6179 Up to four operands may be read; this function handles setting the
6180 ".present" field for each read operand itself.
6181 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6182 else returns FAIL. */
6185 parse_neon_mov (char **str
, int *which_operand
)
6187 int i
= *which_operand
, val
;
6188 enum arm_reg_type rtype
;
6190 struct neon_type_el optype
;
6192 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6194 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6195 inst
.operands
[i
].reg
= val
;
6196 inst
.operands
[i
].isscalar
= 1;
6197 inst
.operands
[i
].vectype
= optype
;
6198 inst
.operands
[i
++].present
= 1;
6200 if (skip_past_comma (&ptr
) == FAIL
)
6203 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6206 inst
.operands
[i
].reg
= val
;
6207 inst
.operands
[i
].isreg
= 1;
6208 inst
.operands
[i
].present
= 1;
6210 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6213 /* Cases 0, 1, 2, 3, 5 (D only). */
6214 if (skip_past_comma (&ptr
) == FAIL
)
6217 inst
.operands
[i
].reg
= val
;
6218 inst
.operands
[i
].isreg
= 1;
6219 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6220 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6221 inst
.operands
[i
].isvec
= 1;
6222 inst
.operands
[i
].vectype
= optype
;
6223 inst
.operands
[i
++].present
= 1;
6225 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6227 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6228 Case 13: VMOV <Sd>, <Rm> */
6229 inst
.operands
[i
].reg
= val
;
6230 inst
.operands
[i
].isreg
= 1;
6231 inst
.operands
[i
].present
= 1;
6233 if (rtype
== REG_TYPE_NQ
)
6235 first_error (_("can't use Neon quad register here"));
6238 else if (rtype
!= REG_TYPE_VFS
)
6241 if (skip_past_comma (&ptr
) == FAIL
)
6243 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6245 inst
.operands
[i
].reg
= val
;
6246 inst
.operands
[i
].isreg
= 1;
6247 inst
.operands
[i
].present
= 1;
6250 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6253 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6254 Case 1: VMOV<c><q> <Dd>, <Dm>
6255 Case 8: VMOV.F32 <Sd>, <Sm>
6256 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6258 inst
.operands
[i
].reg
= val
;
6259 inst
.operands
[i
].isreg
= 1;
6260 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6261 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6262 inst
.operands
[i
].isvec
= 1;
6263 inst
.operands
[i
].vectype
= optype
;
6264 inst
.operands
[i
].present
= 1;
6266 if (skip_past_comma (&ptr
) == SUCCESS
)
6271 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6274 inst
.operands
[i
].reg
= val
;
6275 inst
.operands
[i
].isreg
= 1;
6276 inst
.operands
[i
++].present
= 1;
6278 if (skip_past_comma (&ptr
) == FAIL
)
6281 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6284 inst
.operands
[i
].reg
= val
;
6285 inst
.operands
[i
].isreg
= 1;
6286 inst
.operands
[i
].present
= 1;
6289 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6290 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6291 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6292 Case 10: VMOV.F32 <Sd>, #<imm>
6293 Case 11: VMOV.F64 <Dd>, #<imm> */
6294 inst
.operands
[i
].immisfloat
= 1;
6295 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6297 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6298 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6302 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6306 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6309 inst
.operands
[i
].reg
= val
;
6310 inst
.operands
[i
].isreg
= 1;
6311 inst
.operands
[i
++].present
= 1;
6313 if (skip_past_comma (&ptr
) == FAIL
)
6316 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6318 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6319 inst
.operands
[i
].reg
= val
;
6320 inst
.operands
[i
].isscalar
= 1;
6321 inst
.operands
[i
].present
= 1;
6322 inst
.operands
[i
].vectype
= optype
;
6324 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6326 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6327 inst
.operands
[i
].reg
= val
;
6328 inst
.operands
[i
].isreg
= 1;
6329 inst
.operands
[i
++].present
= 1;
6331 if (skip_past_comma (&ptr
) == FAIL
)
6334 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6337 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6341 inst
.operands
[i
].reg
= val
;
6342 inst
.operands
[i
].isreg
= 1;
6343 inst
.operands
[i
].isvec
= 1;
6344 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6345 inst
.operands
[i
].vectype
= optype
;
6346 inst
.operands
[i
].present
= 1;
6348 if (rtype
== REG_TYPE_VFS
)
6352 if (skip_past_comma (&ptr
) == FAIL
)
6354 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6357 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6360 inst
.operands
[i
].reg
= val
;
6361 inst
.operands
[i
].isreg
= 1;
6362 inst
.operands
[i
].isvec
= 1;
6363 inst
.operands
[i
].issingle
= 1;
6364 inst
.operands
[i
].vectype
= optype
;
6365 inst
.operands
[i
].present
= 1;
6368 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6372 inst
.operands
[i
].reg
= val
;
6373 inst
.operands
[i
].isreg
= 1;
6374 inst
.operands
[i
].isvec
= 1;
6375 inst
.operands
[i
].issingle
= 1;
6376 inst
.operands
[i
].vectype
= optype
;
6377 inst
.operands
[i
].present
= 1;
6382 first_error (_("parse error"));
6386 /* Successfully parsed the operands. Update args. */
6392 first_error (_("expected comma"));
6396 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6400 /* Use this macro when the operand constraints are different
6401 for ARM and THUMB (e.g. ldrd). */
6402 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6403 ((arm_operand) | ((thumb_operand) << 16))
6405 /* Matcher codes for parse_operands. */
6406 enum operand_parse_code
6408 OP_stop
, /* end of line */
6410 OP_RR
, /* ARM register */
6411 OP_RRnpc
, /* ARM register, not r15 */
6412 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6413 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6414 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6415 optional trailing ! */
6416 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6417 OP_RCP
, /* Coprocessor number */
6418 OP_RCN
, /* Coprocessor register */
6419 OP_RF
, /* FPA register */
6420 OP_RVS
, /* VFP single precision register */
6421 OP_RVD
, /* VFP double precision register (0..15) */
6422 OP_RND
, /* Neon double precision register (0..31) */
6423 OP_RNQ
, /* Neon quad precision register */
6424 OP_RVSD
, /* VFP single or double precision register */
6425 OP_RNDQ
, /* Neon double or quad precision register */
6426 OP_RNSDQ
, /* Neon single, double or quad precision register */
6427 OP_RNSC
, /* Neon scalar D[X] */
6428 OP_RVC
, /* VFP control register */
6429 OP_RMF
, /* Maverick F register */
6430 OP_RMD
, /* Maverick D register */
6431 OP_RMFX
, /* Maverick FX register */
6432 OP_RMDX
, /* Maverick DX register */
6433 OP_RMAX
, /* Maverick AX register */
6434 OP_RMDS
, /* Maverick DSPSC register */
6435 OP_RIWR
, /* iWMMXt wR register */
6436 OP_RIWC
, /* iWMMXt wC register */
6437 OP_RIWG
, /* iWMMXt wCG register */
6438 OP_RXA
, /* XScale accumulator register */
6440 OP_REGLST
, /* ARM register list */
6441 OP_VRSLST
, /* VFP single-precision register list */
6442 OP_VRDLST
, /* VFP double-precision register list */
6443 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6444 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6445 OP_NSTRLST
, /* Neon element/structure list */
6447 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6448 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6449 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6450 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6451 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6452 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6453 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6454 OP_VMOV
, /* Neon VMOV operands. */
6455 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6456 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6457 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6459 OP_I0
, /* immediate zero */
6460 OP_I7
, /* immediate value 0 .. 7 */
6461 OP_I15
, /* 0 .. 15 */
6462 OP_I16
, /* 1 .. 16 */
6463 OP_I16z
, /* 0 .. 16 */
6464 OP_I31
, /* 0 .. 31 */
6465 OP_I31w
, /* 0 .. 31, optional trailing ! */
6466 OP_I32
, /* 1 .. 32 */
6467 OP_I32z
, /* 0 .. 32 */
6468 OP_I63
, /* 0 .. 63 */
6469 OP_I63s
, /* -64 .. 63 */
6470 OP_I64
, /* 1 .. 64 */
6471 OP_I64z
, /* 0 .. 64 */
6472 OP_I255
, /* 0 .. 255 */
6474 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6475 OP_I7b
, /* 0 .. 7 */
6476 OP_I15b
, /* 0 .. 15 */
6477 OP_I31b
, /* 0 .. 31 */
6479 OP_SH
, /* shifter operand */
6480 OP_SHG
, /* shifter operand with possible group relocation */
6481 OP_ADDR
, /* Memory address expression (any mode) */
6482 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6483 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6484 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6485 OP_EXP
, /* arbitrary expression */
6486 OP_EXPi
, /* same, with optional immediate prefix */
6487 OP_EXPr
, /* same, with optional relocation suffix */
6488 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6490 OP_CPSF
, /* CPS flags */
6491 OP_ENDI
, /* Endianness specifier */
6492 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6493 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6494 OP_COND
, /* conditional code */
6495 OP_TB
, /* Table branch. */
6497 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6499 OP_RRnpc_I0
, /* ARM register or literal 0 */
6500 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6501 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6502 OP_RF_IF
, /* FPA register or immediate */
6503 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6504 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6506 /* Optional operands. */
6507 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6508 OP_oI31b
, /* 0 .. 31 */
6509 OP_oI32b
, /* 1 .. 32 */
6510 OP_oI32z
, /* 0 .. 32 */
6511 OP_oIffffb
, /* 0 .. 65535 */
6512 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6514 OP_oRR
, /* ARM register */
6515 OP_oRRnpc
, /* ARM register, not the PC */
6516 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6517 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6518 OP_oRND
, /* Optional Neon double precision register */
6519 OP_oRNQ
, /* Optional Neon quad precision register */
6520 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6521 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6522 OP_oSHll
, /* LSL immediate */
6523 OP_oSHar
, /* ASR immediate */
6524 OP_oSHllar
, /* LSL or ASR immediate */
6525 OP_oROR
, /* ROR 0/8/16/24 */
6526 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6528 /* Some pre-defined mixed (ARM/THUMB) operands. */
6529 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6530 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6531 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6533 OP_FIRST_OPTIONAL
= OP_oI7b
6536 /* Generic instruction operand parser. This does no encoding and no
6537 semantic validation; it merely squirrels values away in the inst
6538 structure. Returns SUCCESS or FAIL depending on whether the
6539 specified grammar matched. */
6541 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6543 unsigned const int *upat
= pattern
;
6544 char *backtrack_pos
= 0;
6545 const char *backtrack_error
= 0;
6546 int i
, val
= 0, backtrack_index
= 0;
6547 enum arm_reg_type rtype
;
6548 parse_operand_result result
;
6549 unsigned int op_parse_code
;
6551 #define po_char_or_fail(chr) \
6554 if (skip_past_char (&str, chr) == FAIL) \
6559 #define po_reg_or_fail(regtype) \
6562 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6563 & inst.operands[i].vectype); \
6566 first_error (_(reg_expected_msgs[regtype])); \
6569 inst.operands[i].reg = val; \
6570 inst.operands[i].isreg = 1; \
6571 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6572 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6573 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6574 || rtype == REG_TYPE_VFD \
6575 || rtype == REG_TYPE_NQ); \
6579 #define po_reg_or_goto(regtype, label) \
6582 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6583 & inst.operands[i].vectype); \
6587 inst.operands[i].reg = val; \
6588 inst.operands[i].isreg = 1; \
6589 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6590 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6591 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6592 || rtype == REG_TYPE_VFD \
6593 || rtype == REG_TYPE_NQ); \
6597 #define po_imm_or_fail(min, max, popt) \
6600 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6602 inst.operands[i].imm = val; \
6606 #define po_scalar_or_goto(elsz, label) \
6609 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6612 inst.operands[i].reg = val; \
6613 inst.operands[i].isscalar = 1; \
6617 #define po_misc_or_fail(expr) \
6625 #define po_misc_or_fail_no_backtrack(expr) \
6629 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6630 backtrack_pos = 0; \
6631 if (result != PARSE_OPERAND_SUCCESS) \
6636 #define po_barrier_or_imm(str) \
6639 val = parse_barrier (&str); \
6640 if (val == FAIL && ! ISALPHA (*str)) \
6643 /* ISB can only take SY as an option. */ \
6644 || ((inst.instruction & 0xf0) == 0x60 \
6647 inst.error = _("invalid barrier type"); \
6648 backtrack_pos = 0; \
6654 skip_whitespace (str
);
6656 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6658 op_parse_code
= upat
[i
];
6659 if (op_parse_code
>= 1<<16)
6660 op_parse_code
= thumb
? (op_parse_code
>> 16)
6661 : (op_parse_code
& ((1<<16)-1));
6663 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6665 /* Remember where we are in case we need to backtrack. */
6666 gas_assert (!backtrack_pos
);
6667 backtrack_pos
= str
;
6668 backtrack_error
= inst
.error
;
6669 backtrack_index
= i
;
6672 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6673 po_char_or_fail (',');
6675 switch (op_parse_code
)
6683 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6684 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6685 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6686 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6687 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6688 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6690 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6692 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6694 /* Also accept generic coprocessor regs for unknown registers. */
6696 po_reg_or_fail (REG_TYPE_CN
);
6698 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6699 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6700 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6701 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6702 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6703 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6704 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6705 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6706 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6707 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6709 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6711 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6712 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6714 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6716 /* Neon scalar. Using an element size of 8 means that some invalid
6717 scalars are accepted here, so deal with those in later code. */
6718 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6722 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6725 po_imm_or_fail (0, 0, TRUE
);
6730 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6735 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6738 if (parse_ifimm_zero (&str
))
6739 inst
.operands
[i
].imm
= 0;
6743 = _("only floating point zero is allowed as immediate value");
6751 po_scalar_or_goto (8, try_rr
);
6754 po_reg_or_fail (REG_TYPE_RN
);
6760 po_scalar_or_goto (8, try_nsdq
);
6763 po_reg_or_fail (REG_TYPE_NSDQ
);
6769 po_scalar_or_goto (8, try_ndq
);
6772 po_reg_or_fail (REG_TYPE_NDQ
);
6778 po_scalar_or_goto (8, try_vfd
);
6781 po_reg_or_fail (REG_TYPE_VFD
);
6786 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6787 not careful then bad things might happen. */
6788 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6793 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6796 /* There's a possibility of getting a 64-bit immediate here, so
6797 we need special handling. */
6798 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6801 inst
.error
= _("immediate value is out of range");
6809 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6812 po_imm_or_fail (0, 63, TRUE
);
6817 po_char_or_fail ('[');
6818 po_reg_or_fail (REG_TYPE_RN
);
6819 po_char_or_fail (']');
6825 po_reg_or_fail (REG_TYPE_RN
);
6826 if (skip_past_char (&str
, '!') == SUCCESS
)
6827 inst
.operands
[i
].writeback
= 1;
6831 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6832 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6833 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6834 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6835 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6836 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6837 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6838 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6839 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6840 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6841 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6842 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6844 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6846 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6847 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6849 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6850 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6851 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6852 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6854 /* Immediate variants */
6856 po_char_or_fail ('{');
6857 po_imm_or_fail (0, 255, TRUE
);
6858 po_char_or_fail ('}');
6862 /* The expression parser chokes on a trailing !, so we have
6863 to find it first and zap it. */
6866 while (*s
&& *s
!= ',')
6871 inst
.operands
[i
].writeback
= 1;
6873 po_imm_or_fail (0, 31, TRUE
);
6881 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6886 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6891 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6893 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6895 val
= parse_reloc (&str
);
6898 inst
.error
= _("unrecognized relocation suffix");
6901 else if (val
!= BFD_RELOC_UNUSED
)
6903 inst
.operands
[i
].imm
= val
;
6904 inst
.operands
[i
].hasreloc
= 1;
6909 /* Operand for MOVW or MOVT. */
6911 po_misc_or_fail (parse_half (&str
));
6914 /* Register or expression. */
6915 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6916 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6918 /* Register or immediate. */
6919 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6920 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6922 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6924 if (!is_immediate_prefix (*str
))
6927 val
= parse_fpa_immediate (&str
);
6930 /* FPA immediates are encoded as registers 8-15.
6931 parse_fpa_immediate has already applied the offset. */
6932 inst
.operands
[i
].reg
= val
;
6933 inst
.operands
[i
].isreg
= 1;
6936 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6937 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6939 /* Two kinds of register. */
6942 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6944 || (rege
->type
!= REG_TYPE_MMXWR
6945 && rege
->type
!= REG_TYPE_MMXWC
6946 && rege
->type
!= REG_TYPE_MMXWCG
))
6948 inst
.error
= _("iWMMXt data or control register expected");
6951 inst
.operands
[i
].reg
= rege
->number
;
6952 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6958 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6960 || (rege
->type
!= REG_TYPE_MMXWC
6961 && rege
->type
!= REG_TYPE_MMXWCG
))
6963 inst
.error
= _("iWMMXt control register expected");
6966 inst
.operands
[i
].reg
= rege
->number
;
6967 inst
.operands
[i
].isreg
= 1;
6972 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6973 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6974 case OP_oROR
: val
= parse_ror (&str
); break;
6975 case OP_COND
: val
= parse_cond (&str
); break;
6976 case OP_oBARRIER_I15
:
6977 po_barrier_or_imm (str
); break;
6979 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6985 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6986 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6988 inst
.error
= _("Banked registers are not available with this "
6994 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6998 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7001 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7003 if (strncasecmp (str
, "APSR_", 5) == 0)
7010 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7011 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7012 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7013 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7014 default: found
= 16;
7018 inst
.operands
[i
].isvec
= 1;
7019 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7020 inst
.operands
[i
].reg
= REG_PC
;
7027 po_misc_or_fail (parse_tb (&str
));
7030 /* Register lists. */
7032 val
= parse_reg_list (&str
);
7035 inst
.operands
[1].writeback
= 1;
7041 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7045 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7049 /* Allow Q registers too. */
7050 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7055 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7057 inst
.operands
[i
].issingle
= 1;
7062 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7067 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7068 &inst
.operands
[i
].vectype
);
7071 /* Addressing modes */
7073 po_misc_or_fail (parse_address (&str
, i
));
7077 po_misc_or_fail_no_backtrack (
7078 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7082 po_misc_or_fail_no_backtrack (
7083 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7087 po_misc_or_fail_no_backtrack (
7088 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7092 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7096 po_misc_or_fail_no_backtrack (
7097 parse_shifter_operand_group_reloc (&str
, i
));
7101 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7105 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7109 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7113 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7116 /* Various value-based sanity checks and shared operations. We
7117 do not signal immediate failures for the register constraints;
7118 this allows a syntax error to take precedence. */
7119 switch (op_parse_code
)
7127 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7128 inst
.error
= BAD_PC
;
7133 if (inst
.operands
[i
].isreg
)
7135 if (inst
.operands
[i
].reg
== REG_PC
)
7136 inst
.error
= BAD_PC
;
7137 else if (inst
.operands
[i
].reg
== REG_SP
)
7138 inst
.error
= BAD_SP
;
7143 if (inst
.operands
[i
].isreg
7144 && inst
.operands
[i
].reg
== REG_PC
7145 && (inst
.operands
[i
].writeback
|| thumb
))
7146 inst
.error
= BAD_PC
;
7155 case OP_oBARRIER_I15
:
7164 inst
.operands
[i
].imm
= val
;
7171 /* If we get here, this operand was successfully parsed. */
7172 inst
.operands
[i
].present
= 1;
7176 inst
.error
= BAD_ARGS
;
7181 /* The parse routine should already have set inst.error, but set a
7182 default here just in case. */
7184 inst
.error
= _("syntax error");
7188 /* Do not backtrack over a trailing optional argument that
7189 absorbed some text. We will only fail again, with the
7190 'garbage following instruction' error message, which is
7191 probably less helpful than the current one. */
7192 if (backtrack_index
== i
&& backtrack_pos
!= str
7193 && upat
[i
+1] == OP_stop
)
7196 inst
.error
= _("syntax error");
7200 /* Try again, skipping the optional argument at backtrack_pos. */
7201 str
= backtrack_pos
;
7202 inst
.error
= backtrack_error
;
7203 inst
.operands
[backtrack_index
].present
= 0;
7204 i
= backtrack_index
;
7208 /* Check that we have parsed all the arguments. */
7209 if (*str
!= '\0' && !inst
.error
)
7210 inst
.error
= _("garbage following instruction");
7212 return inst
.error
? FAIL
: SUCCESS
;
7215 #undef po_char_or_fail
7216 #undef po_reg_or_fail
7217 #undef po_reg_or_goto
7218 #undef po_imm_or_fail
7219 #undef po_scalar_or_fail
7220 #undef po_barrier_or_imm
7222 /* Shorthand macro for instruction encoding functions issuing errors. */
7223 #define constraint(expr, err) \
7234 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7235 instructions are unpredictable if these registers are used. This
7236 is the BadReg predicate in ARM's Thumb-2 documentation. */
7237 #define reject_bad_reg(reg) \
7239 if (reg == REG_SP || reg == REG_PC) \
7241 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7246 /* If REG is R13 (the stack pointer), warn that its use is
7248 #define warn_deprecated_sp(reg) \
7250 if (warn_on_deprecated && reg == REG_SP) \
7251 as_warn (_("use of r13 is deprecated")); \
7254 /* Functions for operand encoding. ARM, then Thumb. */
7256 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7258 /* If VAL can be encoded in the immediate field of an ARM instruction,
7259 return the encoded form. Otherwise, return FAIL. */
7262 encode_arm_immediate (unsigned int val
)
7266 for (i
= 0; i
< 32; i
+= 2)
7267 if ((a
= rotate_left (val
, i
)) <= 0xff)
7268 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7273 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7274 return the encoded form. Otherwise, return FAIL. */
7276 encode_thumb32_immediate (unsigned int val
)
7283 for (i
= 1; i
<= 24; i
++)
7286 if ((val
& ~(0xff << i
)) == 0)
7287 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7291 if (val
== ((a
<< 16) | a
))
7293 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7297 if (val
== ((a
<< 16) | a
))
7298 return 0x200 | (a
>> 8);
7302 /* Encode a VFP SP or DP register number into inst.instruction. */
7305 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7307 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7310 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7313 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7316 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7321 first_error (_("D register out of range for selected VFP version"));
7329 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7333 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7337 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7341 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7345 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7349 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7357 /* Encode a <shift> in an ARM-format instruction. The immediate,
7358 if any, is handled by md_apply_fix. */
7360 encode_arm_shift (int i
)
7362 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7363 inst
.instruction
|= SHIFT_ROR
<< 5;
7366 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7367 if (inst
.operands
[i
].immisreg
)
7369 inst
.instruction
|= SHIFT_BY_REG
;
7370 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7373 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7378 encode_arm_shifter_operand (int i
)
7380 if (inst
.operands
[i
].isreg
)
7382 inst
.instruction
|= inst
.operands
[i
].reg
;
7383 encode_arm_shift (i
);
7387 inst
.instruction
|= INST_IMMEDIATE
;
7388 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7389 inst
.instruction
|= inst
.operands
[i
].imm
;
7393 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7395 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7398 Generate an error if the operand is not a register. */
7399 constraint (!inst
.operands
[i
].isreg
,
7400 _("Instruction does not support =N addresses"));
7402 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7404 if (inst
.operands
[i
].preind
)
7408 inst
.error
= _("instruction does not accept preindexed addressing");
7411 inst
.instruction
|= PRE_INDEX
;
7412 if (inst
.operands
[i
].writeback
)
7413 inst
.instruction
|= WRITE_BACK
;
7416 else if (inst
.operands
[i
].postind
)
7418 gas_assert (inst
.operands
[i
].writeback
);
7420 inst
.instruction
|= WRITE_BACK
;
7422 else /* unindexed - only for coprocessor */
7424 inst
.error
= _("instruction does not accept unindexed addressing");
7428 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7429 && (((inst
.instruction
& 0x000f0000) >> 16)
7430 == ((inst
.instruction
& 0x0000f000) >> 12)))
7431 as_warn ((inst
.instruction
& LOAD_BIT
)
7432 ? _("destination register same as write-back base")
7433 : _("source register same as write-back base"));
7436 /* inst.operands[i] was set up by parse_address. Encode it into an
7437 ARM-format mode 2 load or store instruction. If is_t is true,
7438 reject forms that cannot be used with a T instruction (i.e. not
7441 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7443 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7445 encode_arm_addr_mode_common (i
, is_t
);
7447 if (inst
.operands
[i
].immisreg
)
7449 constraint ((inst
.operands
[i
].imm
== REG_PC
7450 || (is_pc
&& inst
.operands
[i
].writeback
)),
7452 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7453 inst
.instruction
|= inst
.operands
[i
].imm
;
7454 if (!inst
.operands
[i
].negative
)
7455 inst
.instruction
|= INDEX_UP
;
7456 if (inst
.operands
[i
].shifted
)
7458 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7459 inst
.instruction
|= SHIFT_ROR
<< 5;
7462 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7463 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7467 else /* immediate offset in inst.reloc */
7469 if (is_pc
&& !inst
.reloc
.pc_rel
)
7471 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7473 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7474 cannot use PC in addressing.
7475 PC cannot be used in writeback addressing, either. */
7476 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7479 /* Use of PC in str is deprecated for ARMv7. */
7480 if (warn_on_deprecated
7482 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7483 as_warn (_("use of PC in this instruction is deprecated"));
7486 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7488 /* Prefer + for zero encoded value. */
7489 if (!inst
.operands
[i
].negative
)
7490 inst
.instruction
|= INDEX_UP
;
7491 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7496 /* inst.operands[i] was set up by parse_address. Encode it into an
7497 ARM-format mode 3 load or store instruction. Reject forms that
7498 cannot be used with such instructions. If is_t is true, reject
7499 forms that cannot be used with a T instruction (i.e. not
7502 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7504 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7506 inst
.error
= _("instruction does not accept scaled register index");
7510 encode_arm_addr_mode_common (i
, is_t
);
7512 if (inst
.operands
[i
].immisreg
)
7514 constraint ((inst
.operands
[i
].imm
== REG_PC
7515 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7517 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7519 inst
.instruction
|= inst
.operands
[i
].imm
;
7520 if (!inst
.operands
[i
].negative
)
7521 inst
.instruction
|= INDEX_UP
;
7523 else /* immediate offset in inst.reloc */
7525 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7526 && inst
.operands
[i
].writeback
),
7528 inst
.instruction
|= HWOFFSET_IMM
;
7529 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7531 /* Prefer + for zero encoded value. */
7532 if (!inst
.operands
[i
].negative
)
7533 inst
.instruction
|= INDEX_UP
;
7535 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7540 /* Write immediate bits [7:0] to the following locations:
7542 |28/24|23 19|18 16|15 4|3 0|
7543 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7545 This function is used by VMOV/VMVN/VORR/VBIC. */
7548 neon_write_immbits (unsigned immbits
)
7550 inst
.instruction
|= immbits
& 0xf;
7551 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7552 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7555 /* Invert low-order SIZE bits of XHI:XLO. */
7558 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7560 unsigned immlo
= xlo
? *xlo
: 0;
7561 unsigned immhi
= xhi
? *xhi
: 0;
7566 immlo
= (~immlo
) & 0xff;
7570 immlo
= (~immlo
) & 0xffff;
7574 immhi
= (~immhi
) & 0xffffffff;
7578 immlo
= (~immlo
) & 0xffffffff;
7592 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7596 neon_bits_same_in_bytes (unsigned imm
)
7598 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7599 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7600 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7601 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7604 /* For immediate of above form, return 0bABCD. */
7607 neon_squash_bits (unsigned imm
)
7609 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7610 | ((imm
& 0x01000000) >> 21);
7613 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7616 neon_qfloat_bits (unsigned imm
)
7618 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7621 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7622 the instruction. *OP is passed as the initial value of the op field, and
7623 may be set to a different value depending on the constant (i.e.
7624 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7625 MVN). If the immediate looks like a repeated pattern then also
7626 try smaller element sizes. */
7629 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7630 unsigned *immbits
, int *op
, int size
,
7631 enum neon_el_type type
)
7633 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7635 if (type
== NT_float
&& !float_p
)
7638 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7640 if (size
!= 32 || *op
== 1)
7642 *immbits
= neon_qfloat_bits (immlo
);
7648 if (neon_bits_same_in_bytes (immhi
)
7649 && neon_bits_same_in_bytes (immlo
))
7653 *immbits
= (neon_squash_bits (immhi
) << 4)
7654 | neon_squash_bits (immlo
);
7665 if (immlo
== (immlo
& 0x000000ff))
7670 else if (immlo
== (immlo
& 0x0000ff00))
7672 *immbits
= immlo
>> 8;
7675 else if (immlo
== (immlo
& 0x00ff0000))
7677 *immbits
= immlo
>> 16;
7680 else if (immlo
== (immlo
& 0xff000000))
7682 *immbits
= immlo
>> 24;
7685 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7687 *immbits
= (immlo
>> 8) & 0xff;
7690 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7692 *immbits
= (immlo
>> 16) & 0xff;
7696 if ((immlo
& 0xffff) != (immlo
>> 16))
7703 if (immlo
== (immlo
& 0x000000ff))
7708 else if (immlo
== (immlo
& 0x0000ff00))
7710 *immbits
= immlo
>> 8;
7714 if ((immlo
& 0xff) != (immlo
>> 8))
7719 if (immlo
== (immlo
& 0x000000ff))
7721 /* Don't allow MVN with 8-bit immediate. */
7738 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7739 Determine whether it can be performed with a move instruction; if
7740 it can, convert inst.instruction to that move instruction and
7741 return TRUE; if it can't, convert inst.instruction to a literal-pool
7742 load and return FALSE. If this is not a valid thing to do in the
7743 current context, set inst.error and return TRUE.
7745 inst.operands[i] describes the destination register. */
7748 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7751 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7752 bfd_boolean arm_p
= (t
== CONST_ARM
);
7753 bfd_boolean vec64_p
= (t
== CONST_VEC
) && !inst
.operands
[i
].issingle
;
7756 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7760 if ((inst
.instruction
& tbit
) == 0)
7762 inst
.error
= _("invalid pseudo operation");
7765 if (inst
.reloc
.exp
.X_op
!= O_constant
7766 && inst
.reloc
.exp
.X_op
!= O_symbol
7767 && inst
.reloc
.exp
.X_op
!= O_big
)
7769 inst
.error
= _("constant expression expected");
7772 if ((inst
.reloc
.exp
.X_op
== O_constant
7773 || inst
.reloc
.exp
.X_op
== O_big
)
7774 && !inst
.operands
[i
].issingle
)
7776 if (thumb_p
&& inst
.reloc
.exp
.X_op
== O_constant
)
7778 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7780 /* This can be done with a mov(1) instruction. */
7781 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7782 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7786 else if (arm_p
&& inst
.reloc
.exp
.X_op
== O_constant
)
7788 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7791 /* This can be done with a mov instruction. */
7792 inst
.instruction
&= LITERAL_MASK
;
7793 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7794 inst
.instruction
|= value
& 0xfff;
7798 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7801 /* This can be done with a mvn instruction. */
7802 inst
.instruction
&= LITERAL_MASK
;
7803 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7804 inst
.instruction
|= value
& 0xfff;
7811 unsigned immbits
= 0;
7812 unsigned immlo
= inst
.operands
[1].imm
;
7813 unsigned immhi
= inst
.operands
[1].regisimm
7814 ? inst
.operands
[1].reg
7815 : inst
.reloc
.exp
.X_unsigned
7817 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7818 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7819 &op
, 64, NT_invtype
);
7823 neon_invert_size (&immlo
, &immhi
, 64);
7825 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7826 &op
, 64, NT_invtype
);
7830 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
7835 /* Fill other bits in vmov encoding for both thumb and arm. */
7837 inst
.instruction
|= (0x7 << 29) | (0xF << 24);
7839 inst
.instruction
|= (0xF << 28) | (0x1 << 25);
7840 neon_write_immbits (immbits
);
7846 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
7847 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
7850 inst
.operands
[1].reg
= REG_PC
;
7851 inst
.operands
[1].isreg
= 1;
7852 inst
.operands
[1].preind
= 1;
7853 inst
.reloc
.pc_rel
= 1;
7854 inst
.reloc
.type
= (thumb_p
7855 ? BFD_RELOC_ARM_THUMB_OFFSET
7857 ? BFD_RELOC_ARM_HWLITERAL
7858 : BFD_RELOC_ARM_LITERAL
));
7862 /* inst.operands[i] was set up by parse_address. Encode it into an
7863 ARM-format instruction. Reject all forms which cannot be encoded
7864 into a coprocessor load/store instruction. If wb_ok is false,
7865 reject use of writeback; if unind_ok is false, reject use of
7866 unindexed addressing. If reloc_override is not 0, use it instead
7867 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7868 (in which case it is preserved). */
7871 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7873 if (!inst
.operands
[i
].isreg
)
7875 gas_assert (inst
.operands
[0].isvec
);
7876 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
7880 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7882 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7884 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7886 gas_assert (!inst
.operands
[i
].writeback
);
7889 inst
.error
= _("instruction does not support unindexed addressing");
7892 inst
.instruction
|= inst
.operands
[i
].imm
;
7893 inst
.instruction
|= INDEX_UP
;
7897 if (inst
.operands
[i
].preind
)
7898 inst
.instruction
|= PRE_INDEX
;
7900 if (inst
.operands
[i
].writeback
)
7902 if (inst
.operands
[i
].reg
== REG_PC
)
7904 inst
.error
= _("pc may not be used with write-back");
7909 inst
.error
= _("instruction does not support writeback");
7912 inst
.instruction
|= WRITE_BACK
;
7916 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7917 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7918 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7919 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7922 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7924 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7927 /* Prefer + for zero encoded value. */
7928 if (!inst
.operands
[i
].negative
)
7929 inst
.instruction
|= INDEX_UP
;
7934 /* Functions for instruction encoding, sorted by sub-architecture.
7935 First some generics; their names are taken from the conventional
7936 bit positions for register arguments in ARM format instructions. */
7946 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7952 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7953 inst
.instruction
|= inst
.operands
[1].reg
;
7959 inst
.instruction
|= inst
.operands
[0].reg
;
7960 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7966 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7967 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7973 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7974 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7978 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
7980 if (ARM_CPU_IS_ANY (cpu_variant
))
7982 as_warn ("%s", msg
);
7985 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
7997 unsigned Rn
= inst
.operands
[2].reg
;
7998 /* Enforce restrictions on SWP instruction. */
7999 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8001 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8002 _("Rn must not overlap other operands"));
8004 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8006 if (!check_obsolete (&arm_ext_v8
,
8007 _("swp{b} use is obsoleted for ARMv8 and later"))
8008 && warn_on_deprecated
8009 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8010 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8013 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8014 inst
.instruction
|= inst
.operands
[1].reg
;
8015 inst
.instruction
|= Rn
<< 16;
8021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8022 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8023 inst
.instruction
|= inst
.operands
[2].reg
;
8029 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8030 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8031 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8032 || inst
.reloc
.exp
.X_add_number
!= 0),
8034 inst
.instruction
|= inst
.operands
[0].reg
;
8035 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8036 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8042 inst
.instruction
|= inst
.operands
[0].imm
;
8048 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8049 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8052 /* ARM instructions, in alphabetical order by function name (except
8053 that wrapper functions appear immediately after the function they
8056 /* This is a pseudo-op of the form "adr rd, label" to be converted
8057 into a relative address of the form "add rd, pc, #label-.-8". */
8062 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8064 /* Frag hacking will turn this into a sub instruction if the offset turns
8065 out to be negative. */
8066 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8067 inst
.reloc
.pc_rel
= 1;
8068 inst
.reloc
.exp
.X_add_number
-= 8;
8071 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8072 into a relative address of the form:
8073 add rd, pc, #low(label-.-8)"
8074 add rd, rd, #high(label-.-8)" */
8079 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8081 /* Frag hacking will turn this into a sub instruction if the offset turns
8082 out to be negative. */
8083 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8084 inst
.reloc
.pc_rel
= 1;
8085 inst
.size
= INSN_SIZE
* 2;
8086 inst
.reloc
.exp
.X_add_number
-= 8;
8092 if (!inst
.operands
[1].present
)
8093 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8094 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8095 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8096 encode_arm_shifter_operand (2);
8102 if (inst
.operands
[0].present
)
8103 inst
.instruction
|= inst
.operands
[0].imm
;
8105 inst
.instruction
|= 0xf;
8111 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8112 constraint (msb
> 32, _("bit-field extends past end of register"));
8113 /* The instruction encoding stores the LSB and MSB,
8114 not the LSB and width. */
8115 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8116 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8117 inst
.instruction
|= (msb
- 1) << 16;
8125 /* #0 in second position is alternative syntax for bfc, which is
8126 the same instruction but with REG_PC in the Rm field. */
8127 if (!inst
.operands
[1].isreg
)
8128 inst
.operands
[1].reg
= REG_PC
;
8130 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8131 constraint (msb
> 32, _("bit-field extends past end of register"));
8132 /* The instruction encoding stores the LSB and MSB,
8133 not the LSB and width. */
8134 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8135 inst
.instruction
|= inst
.operands
[1].reg
;
8136 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8137 inst
.instruction
|= (msb
- 1) << 16;
8143 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8144 _("bit-field extends past end of register"));
8145 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8146 inst
.instruction
|= inst
.operands
[1].reg
;
8147 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8148 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8151 /* ARM V5 breakpoint instruction (argument parse)
8152 BKPT <16 bit unsigned immediate>
8153 Instruction is not conditional.
8154 The bit pattern given in insns[] has the COND_ALWAYS condition,
8155 and it is an error if the caller tried to override that. */
8160 /* Top 12 of 16 bits to bits 19:8. */
8161 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8163 /* Bottom 4 of 16 bits to bits 3:0. */
8164 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8168 encode_branch (int default_reloc
)
8170 if (inst
.operands
[0].hasreloc
)
8172 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8173 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8174 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8175 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8176 ? BFD_RELOC_ARM_PLT32
8177 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8180 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8181 inst
.reloc
.pc_rel
= 1;
8188 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8189 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8192 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8199 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8201 if (inst
.cond
== COND_ALWAYS
)
8202 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8204 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8208 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8211 /* ARM V5 branch-link-exchange instruction (argument parse)
8212 BLX <target_addr> ie BLX(1)
8213 BLX{<condition>} <Rm> ie BLX(2)
8214 Unfortunately, there are two different opcodes for this mnemonic.
8215 So, the insns[].value is not used, and the code here zaps values
8216 into inst.instruction.
8217 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8222 if (inst
.operands
[0].isreg
)
8224 /* Arg is a register; the opcode provided by insns[] is correct.
8225 It is not illegal to do "blx pc", just useless. */
8226 if (inst
.operands
[0].reg
== REG_PC
)
8227 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8229 inst
.instruction
|= inst
.operands
[0].reg
;
8233 /* Arg is an address; this instruction cannot be executed
8234 conditionally, and the opcode must be adjusted.
8235 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8236 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8237 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8238 inst
.instruction
= 0xfa000000;
8239 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8246 bfd_boolean want_reloc
;
8248 if (inst
.operands
[0].reg
== REG_PC
)
8249 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8251 inst
.instruction
|= inst
.operands
[0].reg
;
8252 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8253 it is for ARMv4t or earlier. */
8254 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8255 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8259 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8264 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8268 /* ARM v5TEJ. Jump to Jazelle code. */
8273 if (inst
.operands
[0].reg
== REG_PC
)
8274 as_tsktsk (_("use of r15 in bxj is not really useful"));
8276 inst
.instruction
|= inst
.operands
[0].reg
;
8279 /* Co-processor data operation:
8280 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8281 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8285 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8286 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8287 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8288 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8289 inst
.instruction
|= inst
.operands
[4].reg
;
8290 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8296 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8297 encode_arm_shifter_operand (1);
8300 /* Transfer between coprocessor and ARM registers.
8301 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8306 No special properties. */
8308 struct deprecated_coproc_regs_s
8315 arm_feature_set deprecated
;
8316 arm_feature_set obsoleted
;
8317 const char *dep_msg
;
8318 const char *obs_msg
;
8321 #define DEPR_ACCESS_V8 \
8322 N_("This coprocessor register access is deprecated in ARMv8")
8324 /* Table of all deprecated coprocessor registers. */
8325 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8327 {15, 0, 7, 10, 5, /* CP15DMB. */
8328 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
8329 DEPR_ACCESS_V8
, NULL
},
8330 {15, 0, 7, 10, 4, /* CP15DSB. */
8331 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
8332 DEPR_ACCESS_V8
, NULL
},
8333 {15, 0, 7, 5, 4, /* CP15ISB. */
8334 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
8335 DEPR_ACCESS_V8
, NULL
},
8336 {14, 6, 1, 0, 0, /* TEEHBR. */
8337 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
8338 DEPR_ACCESS_V8
, NULL
},
8339 {14, 6, 0, 0, 0, /* TEECR. */
8340 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
8341 DEPR_ACCESS_V8
, NULL
},
8344 #undef DEPR_ACCESS_V8
8346 static const size_t deprecated_coproc_reg_count
=
8347 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8355 Rd
= inst
.operands
[2].reg
;
8358 if (inst
.instruction
== 0xee000010
8359 || inst
.instruction
== 0xfe000010)
8361 reject_bad_reg (Rd
);
8364 constraint (Rd
== REG_SP
, BAD_SP
);
8369 if (inst
.instruction
== 0xe000010)
8370 constraint (Rd
== REG_PC
, BAD_PC
);
8373 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8375 const struct deprecated_coproc_regs_s
*r
=
8376 deprecated_coproc_regs
+ i
;
8378 if (inst
.operands
[0].reg
== r
->cp
8379 && inst
.operands
[1].imm
== r
->opc1
8380 && inst
.operands
[3].reg
== r
->crn
8381 && inst
.operands
[4].reg
== r
->crm
8382 && inst
.operands
[5].imm
== r
->opc2
)
8384 if (! ARM_CPU_IS_ANY (cpu_variant
)
8385 && warn_on_deprecated
8386 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8387 as_warn ("%s", r
->dep_msg
);
8391 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8392 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8393 inst
.instruction
|= Rd
<< 12;
8394 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8395 inst
.instruction
|= inst
.operands
[4].reg
;
8396 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8399 /* Transfer between coprocessor register and pair of ARM registers.
8400 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8405 Two XScale instructions are special cases of these:
8407 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8408 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8410 Result unpredictable if Rd or Rn is R15. */
8417 Rd
= inst
.operands
[2].reg
;
8418 Rn
= inst
.operands
[3].reg
;
8422 reject_bad_reg (Rd
);
8423 reject_bad_reg (Rn
);
8427 constraint (Rd
== REG_PC
, BAD_PC
);
8428 constraint (Rn
== REG_PC
, BAD_PC
);
8431 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8432 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8433 inst
.instruction
|= Rd
<< 12;
8434 inst
.instruction
|= Rn
<< 16;
8435 inst
.instruction
|= inst
.operands
[4].reg
;
8441 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8442 if (inst
.operands
[1].present
)
8444 inst
.instruction
|= CPSI_MMOD
;
8445 inst
.instruction
|= inst
.operands
[1].imm
;
8452 inst
.instruction
|= inst
.operands
[0].imm
;
8458 unsigned Rd
, Rn
, Rm
;
8460 Rd
= inst
.operands
[0].reg
;
8461 Rn
= (inst
.operands
[1].present
8462 ? inst
.operands
[1].reg
: Rd
);
8463 Rm
= inst
.operands
[2].reg
;
8465 constraint ((Rd
== REG_PC
), BAD_PC
);
8466 constraint ((Rn
== REG_PC
), BAD_PC
);
8467 constraint ((Rm
== REG_PC
), BAD_PC
);
8469 inst
.instruction
|= Rd
<< 16;
8470 inst
.instruction
|= Rn
<< 0;
8471 inst
.instruction
|= Rm
<< 8;
8477 /* There is no IT instruction in ARM mode. We
8478 process it to do the validation as if in
8479 thumb mode, just in case the code gets
8480 assembled for thumb using the unified syntax. */
8485 set_it_insn_type (IT_INSN
);
8486 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8487 now_it
.cc
= inst
.operands
[0].imm
;
8491 /* If there is only one register in the register list,
8492 then return its register number. Otherwise return -1. */
8494 only_one_reg_in_list (int range
)
8496 int i
= ffs (range
) - 1;
8497 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8501 encode_ldmstm(int from_push_pop_mnem
)
8503 int base_reg
= inst
.operands
[0].reg
;
8504 int range
= inst
.operands
[1].imm
;
8507 inst
.instruction
|= base_reg
<< 16;
8508 inst
.instruction
|= range
;
8510 if (inst
.operands
[1].writeback
)
8511 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8513 if (inst
.operands
[0].writeback
)
8515 inst
.instruction
|= WRITE_BACK
;
8516 /* Check for unpredictable uses of writeback. */
8517 if (inst
.instruction
& LOAD_BIT
)
8519 /* Not allowed in LDM type 2. */
8520 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8521 && ((range
& (1 << REG_PC
)) == 0))
8522 as_warn (_("writeback of base register is UNPREDICTABLE"));
8523 /* Only allowed if base reg not in list for other types. */
8524 else if (range
& (1 << base_reg
))
8525 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8529 /* Not allowed for type 2. */
8530 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8531 as_warn (_("writeback of base register is UNPREDICTABLE"));
8532 /* Only allowed if base reg not in list, or first in list. */
8533 else if ((range
& (1 << base_reg
))
8534 && (range
& ((1 << base_reg
) - 1)))
8535 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8539 /* If PUSH/POP has only one register, then use the A2 encoding. */
8540 one_reg
= only_one_reg_in_list (range
);
8541 if (from_push_pop_mnem
&& one_reg
>= 0)
8543 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8545 inst
.instruction
&= A_COND_MASK
;
8546 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8547 inst
.instruction
|= one_reg
<< 12;
8554 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8557 /* ARMv5TE load-consecutive (argument parse)
8566 constraint (inst
.operands
[0].reg
% 2 != 0,
8567 _("first transfer register must be even"));
8568 constraint (inst
.operands
[1].present
8569 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8570 _("can only transfer two consecutive registers"));
8571 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8572 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8574 if (!inst
.operands
[1].present
)
8575 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8577 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8578 register and the first register written; we have to diagnose
8579 overlap between the base and the second register written here. */
8581 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8582 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8583 as_warn (_("base register written back, and overlaps "
8584 "second transfer register"));
8586 if (!(inst
.instruction
& V4_STR_BIT
))
8588 /* For an index-register load, the index register must not overlap the
8589 destination (even if not write-back). */
8590 if (inst
.operands
[2].immisreg
8591 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8592 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8593 as_warn (_("index register overlaps transfer register"));
8595 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8596 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8602 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8603 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8604 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8605 || inst
.operands
[1].negative
8606 /* This can arise if the programmer has written
8608 or if they have mistakenly used a register name as the last
8611 It is very difficult to distinguish between these two cases
8612 because "rX" might actually be a label. ie the register
8613 name has been occluded by a symbol of the same name. So we
8614 just generate a general 'bad addressing mode' type error
8615 message and leave it up to the programmer to discover the
8616 true cause and fix their mistake. */
8617 || (inst
.operands
[1].reg
== REG_PC
),
8620 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8621 || inst
.reloc
.exp
.X_add_number
!= 0,
8622 _("offset must be zero in ARM encoding"));
8624 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8626 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8627 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8628 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8634 constraint (inst
.operands
[0].reg
% 2 != 0,
8635 _("even register required"));
8636 constraint (inst
.operands
[1].present
8637 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8638 _("can only load two consecutive registers"));
8639 /* If op 1 were present and equal to PC, this function wouldn't
8640 have been called in the first place. */
8641 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8643 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8644 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8647 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8648 which is not a multiple of four is UNPREDICTABLE. */
8650 check_ldr_r15_aligned (void)
8652 constraint (!(inst
.operands
[1].immisreg
)
8653 && (inst
.operands
[0].reg
== REG_PC
8654 && inst
.operands
[1].reg
== REG_PC
8655 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8656 _("ldr to register 15 must be 4-byte alligned"));
8662 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8663 if (!inst
.operands
[1].isreg
)
8664 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8666 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8667 check_ldr_r15_aligned ();
8673 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8675 if (inst
.operands
[1].preind
)
8677 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8678 || inst
.reloc
.exp
.X_add_number
!= 0,
8679 _("this instruction requires a post-indexed address"));
8681 inst
.operands
[1].preind
= 0;
8682 inst
.operands
[1].postind
= 1;
8683 inst
.operands
[1].writeback
= 1;
8685 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8686 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8689 /* Halfword and signed-byte load/store operations. */
8694 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8695 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8696 if (!inst
.operands
[1].isreg
)
8697 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8699 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8705 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8707 if (inst
.operands
[1].preind
)
8709 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8710 || inst
.reloc
.exp
.X_add_number
!= 0,
8711 _("this instruction requires a post-indexed address"));
8713 inst
.operands
[1].preind
= 0;
8714 inst
.operands
[1].postind
= 1;
8715 inst
.operands
[1].writeback
= 1;
8717 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8718 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8721 /* Co-processor register load/store.
8722 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8726 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8727 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8728 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8734 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8735 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8736 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8737 && !(inst
.instruction
& 0x00400000))
8738 as_tsktsk (_("Rd and Rm should be different in mla"));
8740 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8741 inst
.instruction
|= inst
.operands
[1].reg
;
8742 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8743 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8749 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8750 encode_arm_shifter_operand (1);
8753 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8760 top
= (inst
.instruction
& 0x00400000) != 0;
8761 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8762 _(":lower16: not allowed this instruction"));
8763 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8764 _(":upper16: not allowed instruction"));
8765 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8766 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8768 imm
= inst
.reloc
.exp
.X_add_number
;
8769 /* The value is in two pieces: 0:11, 16:19. */
8770 inst
.instruction
|= (imm
& 0x00000fff);
8771 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8775 static void do_vfp_nsyn_opcode (const char *);
8778 do_vfp_nsyn_mrs (void)
8780 if (inst
.operands
[0].isvec
)
8782 if (inst
.operands
[1].reg
!= 1)
8783 first_error (_("operand 1 must be FPSCR"));
8784 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8785 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8786 do_vfp_nsyn_opcode ("fmstat");
8788 else if (inst
.operands
[1].isvec
)
8789 do_vfp_nsyn_opcode ("fmrx");
8797 do_vfp_nsyn_msr (void)
8799 if (inst
.operands
[0].isvec
)
8800 do_vfp_nsyn_opcode ("fmxr");
8810 unsigned Rt
= inst
.operands
[0].reg
;
8812 if (thumb_mode
&& Rt
== REG_SP
)
8814 inst
.error
= BAD_SP
;
8818 /* APSR_ sets isvec. All other refs to PC are illegal. */
8819 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
8821 inst
.error
= BAD_PC
;
8825 /* If we get through parsing the register name, we just insert the number
8826 generated into the instruction without further validation. */
8827 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
8828 inst
.instruction
|= (Rt
<< 12);
8834 unsigned Rt
= inst
.operands
[1].reg
;
8837 reject_bad_reg (Rt
);
8838 else if (Rt
== REG_PC
)
8840 inst
.error
= BAD_PC
;
8844 /* If we get through parsing the register name, we just insert the number
8845 generated into the instruction without further validation. */
8846 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
8847 inst
.instruction
|= (Rt
<< 12);
8855 if (do_vfp_nsyn_mrs () == SUCCESS
)
8858 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8859 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8861 if (inst
.operands
[1].isreg
)
8863 br
= inst
.operands
[1].reg
;
8864 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8865 as_bad (_("bad register for mrs"));
8869 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8870 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8872 _("'APSR', 'CPSR' or 'SPSR' expected"));
8873 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8876 inst
.instruction
|= br
;
8879 /* Two possible forms:
8880 "{C|S}PSR_<field>, Rm",
8881 "{C|S}PSR_f, #expression". */
8886 if (do_vfp_nsyn_msr () == SUCCESS
)
8889 inst
.instruction
|= inst
.operands
[0].imm
;
8890 if (inst
.operands
[1].isreg
)
8891 inst
.instruction
|= inst
.operands
[1].reg
;
8894 inst
.instruction
|= INST_IMMEDIATE
;
8895 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8896 inst
.reloc
.pc_rel
= 0;
8903 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8905 if (!inst
.operands
[2].present
)
8906 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8907 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8908 inst
.instruction
|= inst
.operands
[1].reg
;
8909 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8911 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8912 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8913 as_tsktsk (_("Rd and Rm should be different in mul"));
8916 /* Long Multiply Parser
8917 UMULL RdLo, RdHi, Rm, Rs
8918 SMULL RdLo, RdHi, Rm, Rs
8919 UMLAL RdLo, RdHi, Rm, Rs
8920 SMLAL RdLo, RdHi, Rm, Rs. */
8925 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8926 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8927 inst
.instruction
|= inst
.operands
[2].reg
;
8928 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8930 /* rdhi and rdlo must be different. */
8931 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8932 as_tsktsk (_("rdhi and rdlo must be different"));
8934 /* rdhi, rdlo and rm must all be different before armv6. */
8935 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8936 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8937 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8938 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8944 if (inst
.operands
[0].present
8945 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8947 /* Architectural NOP hints are CPSR sets with no bits selected. */
8948 inst
.instruction
&= 0xf0000000;
8949 inst
.instruction
|= 0x0320f000;
8950 if (inst
.operands
[0].present
)
8951 inst
.instruction
|= inst
.operands
[0].imm
;
8955 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8956 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8957 Condition defaults to COND_ALWAYS.
8958 Error if Rd, Rn or Rm are R15. */
8963 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8964 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8965 inst
.instruction
|= inst
.operands
[2].reg
;
8966 if (inst
.operands
[3].present
)
8967 encode_arm_shift (3);
8970 /* ARM V6 PKHTB (Argument Parse). */
8975 if (!inst
.operands
[3].present
)
8977 /* If the shift specifier is omitted, turn the instruction
8978 into pkhbt rd, rm, rn. */
8979 inst
.instruction
&= 0xfff00010;
8980 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8981 inst
.instruction
|= inst
.operands
[1].reg
;
8982 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8986 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8987 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8988 inst
.instruction
|= inst
.operands
[2].reg
;
8989 encode_arm_shift (3);
8993 /* ARMv5TE: Preload-Cache
8994 MP Extensions: Preload for write
8998 Syntactically, like LDR with B=1, W=0, L=1. */
9003 constraint (!inst
.operands
[0].isreg
,
9004 _("'[' expected after PLD mnemonic"));
9005 constraint (inst
.operands
[0].postind
,
9006 _("post-indexed expression used in preload instruction"));
9007 constraint (inst
.operands
[0].writeback
,
9008 _("writeback used in preload instruction"));
9009 constraint (!inst
.operands
[0].preind
,
9010 _("unindexed addressing used in preload instruction"));
9011 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9014 /* ARMv7: PLI <addr_mode> */
9018 constraint (!inst
.operands
[0].isreg
,
9019 _("'[' expected after PLI mnemonic"));
9020 constraint (inst
.operands
[0].postind
,
9021 _("post-indexed expression used in preload instruction"));
9022 constraint (inst
.operands
[0].writeback
,
9023 _("writeback used in preload instruction"));
9024 constraint (!inst
.operands
[0].preind
,
9025 _("unindexed addressing used in preload instruction"));
9026 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9027 inst
.instruction
&= ~PRE_INDEX
;
9033 inst
.operands
[1] = inst
.operands
[0];
9034 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9035 inst
.operands
[0].isreg
= 1;
9036 inst
.operands
[0].writeback
= 1;
9037 inst
.operands
[0].reg
= REG_SP
;
9038 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9041 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9042 word at the specified address and the following word
9044 Unconditionally executed.
9045 Error if Rn is R15. */
9050 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9051 if (inst
.operands
[0].writeback
)
9052 inst
.instruction
|= WRITE_BACK
;
9055 /* ARM V6 ssat (argument parse). */
9060 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9061 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9062 inst
.instruction
|= inst
.operands
[2].reg
;
9064 if (inst
.operands
[3].present
)
9065 encode_arm_shift (3);
9068 /* ARM V6 usat (argument parse). */
9073 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9074 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9075 inst
.instruction
|= inst
.operands
[2].reg
;
9077 if (inst
.operands
[3].present
)
9078 encode_arm_shift (3);
9081 /* ARM V6 ssat16 (argument parse). */
9086 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9087 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9088 inst
.instruction
|= inst
.operands
[2].reg
;
9094 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9095 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9096 inst
.instruction
|= inst
.operands
[2].reg
;
9099 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9100 preserving the other bits.
9102 setend <endian_specifier>, where <endian_specifier> is either
9108 if (warn_on_deprecated
9109 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9110 as_warn (_("setend use is deprecated for ARMv8"));
9112 if (inst
.operands
[0].imm
)
9113 inst
.instruction
|= 0x200;
9119 unsigned int Rm
= (inst
.operands
[1].present
9120 ? inst
.operands
[1].reg
9121 : inst
.operands
[0].reg
);
9123 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9124 inst
.instruction
|= Rm
;
9125 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9127 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9128 inst
.instruction
|= SHIFT_BY_REG
;
9129 /* PR 12854: Error on extraneous shifts. */
9130 constraint (inst
.operands
[2].shifted
,
9131 _("extraneous shift as part of operand to shift insn"));
9134 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9140 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9141 inst
.reloc
.pc_rel
= 0;
9147 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9148 inst
.reloc
.pc_rel
= 0;
9154 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9155 inst
.reloc
.pc_rel
= 0;
9158 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9159 SMLAxy{cond} Rd,Rm,Rs,Rn
9160 SMLAWy{cond} Rd,Rm,Rs,Rn
9161 Error if any register is R15. */
9166 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9167 inst
.instruction
|= inst
.operands
[1].reg
;
9168 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9169 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9172 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9173 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9174 Error if any register is R15.
9175 Warning if Rdlo == Rdhi. */
9180 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9181 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9182 inst
.instruction
|= inst
.operands
[2].reg
;
9183 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9185 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9186 as_tsktsk (_("rdhi and rdlo must be different"));
9189 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9190 SMULxy{cond} Rd,Rm,Rs
9191 Error if any register is R15. */
9196 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9197 inst
.instruction
|= inst
.operands
[1].reg
;
9198 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9201 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9202 the same for both ARM and Thumb-2. */
9209 if (inst
.operands
[0].present
)
9211 reg
= inst
.operands
[0].reg
;
9212 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9217 inst
.instruction
|= reg
<< 16;
9218 inst
.instruction
|= inst
.operands
[1].imm
;
9219 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9220 inst
.instruction
|= WRITE_BACK
;
9223 /* ARM V6 strex (argument parse). */
9228 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9229 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9230 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9231 || inst
.operands
[2].negative
9232 /* See comment in do_ldrex(). */
9233 || (inst
.operands
[2].reg
== REG_PC
),
9236 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9237 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9239 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9240 || inst
.reloc
.exp
.X_add_number
!= 0,
9241 _("offset must be zero in ARM encoding"));
9243 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9244 inst
.instruction
|= inst
.operands
[1].reg
;
9245 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9246 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9252 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9253 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9254 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9255 || inst
.operands
[2].negative
,
9258 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9259 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9267 constraint (inst
.operands
[1].reg
% 2 != 0,
9268 _("even register required"));
9269 constraint (inst
.operands
[2].present
9270 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9271 _("can only store two consecutive registers"));
9272 /* If op 2 were present and equal to PC, this function wouldn't
9273 have been called in the first place. */
9274 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9276 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9277 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9278 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9281 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9282 inst
.instruction
|= inst
.operands
[1].reg
;
9283 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9290 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9291 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9299 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9300 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9305 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9306 extends it to 32-bits, and adds the result to a value in another
9307 register. You can specify a rotation by 0, 8, 16, or 24 bits
9308 before extracting the 16-bit value.
9309 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9310 Condition defaults to COND_ALWAYS.
9311 Error if any register uses R15. */
9316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9317 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9318 inst
.instruction
|= inst
.operands
[2].reg
;
9319 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9324 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9325 Condition defaults to COND_ALWAYS.
9326 Error if any register uses R15. */
9331 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9332 inst
.instruction
|= inst
.operands
[1].reg
;
9333 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9336 /* VFP instructions. In a logical order: SP variant first, monad
9337 before dyad, arithmetic then move then load/store. */
9340 do_vfp_sp_monadic (void)
9342 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9343 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9347 do_vfp_sp_dyadic (void)
9349 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9350 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9351 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9355 do_vfp_sp_compare_z (void)
9357 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9361 do_vfp_dp_sp_cvt (void)
9363 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9364 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9368 do_vfp_sp_dp_cvt (void)
9370 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9371 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9375 do_vfp_reg_from_sp (void)
9377 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9378 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9382 do_vfp_reg2_from_sp2 (void)
9384 constraint (inst
.operands
[2].imm
!= 2,
9385 _("only two consecutive VFP SP registers allowed here"));
9386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9387 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9388 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9392 do_vfp_sp_from_reg (void)
9394 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9395 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9399 do_vfp_sp2_from_reg2 (void)
9401 constraint (inst
.operands
[0].imm
!= 2,
9402 _("only two consecutive VFP SP registers allowed here"));
9403 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9404 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9405 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9409 do_vfp_sp_ldst (void)
9411 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9412 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9416 do_vfp_dp_ldst (void)
9418 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9419 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9424 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9426 if (inst
.operands
[0].writeback
)
9427 inst
.instruction
|= WRITE_BACK
;
9429 constraint (ldstm_type
!= VFP_LDSTMIA
,
9430 _("this addressing mode requires base-register writeback"));
9431 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9432 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9433 inst
.instruction
|= inst
.operands
[1].imm
;
9437 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9441 if (inst
.operands
[0].writeback
)
9442 inst
.instruction
|= WRITE_BACK
;
9444 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9445 _("this addressing mode requires base-register writeback"));
9447 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9448 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9450 count
= inst
.operands
[1].imm
<< 1;
9451 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9454 inst
.instruction
|= count
;
9458 do_vfp_sp_ldstmia (void)
9460 vfp_sp_ldstm (VFP_LDSTMIA
);
9464 do_vfp_sp_ldstmdb (void)
9466 vfp_sp_ldstm (VFP_LDSTMDB
);
9470 do_vfp_dp_ldstmia (void)
9472 vfp_dp_ldstm (VFP_LDSTMIA
);
9476 do_vfp_dp_ldstmdb (void)
9478 vfp_dp_ldstm (VFP_LDSTMDB
);
9482 do_vfp_xp_ldstmia (void)
9484 vfp_dp_ldstm (VFP_LDSTMIAX
);
9488 do_vfp_xp_ldstmdb (void)
9490 vfp_dp_ldstm (VFP_LDSTMDBX
);
9494 do_vfp_dp_rd_rm (void)
9496 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9497 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9501 do_vfp_dp_rn_rd (void)
9503 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9504 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9508 do_vfp_dp_rd_rn (void)
9510 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9511 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9515 do_vfp_dp_rd_rn_rm (void)
9517 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9518 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9519 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9525 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9529 do_vfp_dp_rm_rd_rn (void)
9531 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9532 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9533 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9536 /* VFPv3 instructions. */
9538 do_vfp_sp_const (void)
9540 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9541 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9542 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9546 do_vfp_dp_const (void)
9548 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9549 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9550 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9554 vfp_conv (int srcsize
)
9556 int immbits
= srcsize
- inst
.operands
[1].imm
;
9558 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9560 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9561 i.e. immbits must be in range 0 - 16. */
9562 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9565 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9567 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9568 i.e. immbits must be in range 0 - 31. */
9569 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9573 inst
.instruction
|= (immbits
& 1) << 5;
9574 inst
.instruction
|= (immbits
>> 1);
9578 do_vfp_sp_conv_16 (void)
9580 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9585 do_vfp_dp_conv_16 (void)
9587 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9592 do_vfp_sp_conv_32 (void)
9594 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9599 do_vfp_dp_conv_32 (void)
9601 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9605 /* FPA instructions. Also in a logical order. */
9610 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9611 inst
.instruction
|= inst
.operands
[1].reg
;
9615 do_fpa_ldmstm (void)
9617 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9618 switch (inst
.operands
[1].imm
)
9620 case 1: inst
.instruction
|= CP_T_X
; break;
9621 case 2: inst
.instruction
|= CP_T_Y
; break;
9622 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9627 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9629 /* The instruction specified "ea" or "fd", so we can only accept
9630 [Rn]{!}. The instruction does not really support stacking or
9631 unstacking, so we have to emulate these by setting appropriate
9632 bits and offsets. */
9633 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9634 || inst
.reloc
.exp
.X_add_number
!= 0,
9635 _("this instruction does not support indexing"));
9637 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9638 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9640 if (!(inst
.instruction
& INDEX_UP
))
9641 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9643 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9645 inst
.operands
[2].preind
= 0;
9646 inst
.operands
[2].postind
= 1;
9650 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9653 /* iWMMXt instructions: strictly in alphabetical order. */
9656 do_iwmmxt_tandorc (void)
9658 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9662 do_iwmmxt_textrc (void)
9664 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9665 inst
.instruction
|= inst
.operands
[1].imm
;
9669 do_iwmmxt_textrm (void)
9671 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9672 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9673 inst
.instruction
|= inst
.operands
[2].imm
;
9677 do_iwmmxt_tinsr (void)
9679 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9680 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9681 inst
.instruction
|= inst
.operands
[2].imm
;
9685 do_iwmmxt_tmia (void)
9687 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9688 inst
.instruction
|= inst
.operands
[1].reg
;
9689 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9693 do_iwmmxt_waligni (void)
9695 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9696 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9697 inst
.instruction
|= inst
.operands
[2].reg
;
9698 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9702 do_iwmmxt_wmerge (void)
9704 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9705 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9706 inst
.instruction
|= inst
.operands
[2].reg
;
9707 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9711 do_iwmmxt_wmov (void)
9713 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9714 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9715 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9716 inst
.instruction
|= inst
.operands
[1].reg
;
9720 do_iwmmxt_wldstbh (void)
9723 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9725 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9727 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9728 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9732 do_iwmmxt_wldstw (void)
9734 /* RIWR_RIWC clears .isreg for a control register. */
9735 if (!inst
.operands
[0].isreg
)
9737 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9738 inst
.instruction
|= 0xf0000000;
9741 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9742 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9746 do_iwmmxt_wldstd (void)
9748 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9749 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9750 && inst
.operands
[1].immisreg
)
9752 inst
.instruction
&= ~0x1a000ff;
9753 inst
.instruction
|= (0xf << 28);
9754 if (inst
.operands
[1].preind
)
9755 inst
.instruction
|= PRE_INDEX
;
9756 if (!inst
.operands
[1].negative
)
9757 inst
.instruction
|= INDEX_UP
;
9758 if (inst
.operands
[1].writeback
)
9759 inst
.instruction
|= WRITE_BACK
;
9760 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9761 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9762 inst
.instruction
|= inst
.operands
[1].imm
;
9765 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9769 do_iwmmxt_wshufh (void)
9771 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9772 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9773 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9774 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9778 do_iwmmxt_wzero (void)
9780 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9781 inst
.instruction
|= inst
.operands
[0].reg
;
9782 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9783 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9787 do_iwmmxt_wrwrwr_or_imm5 (void)
9789 if (inst
.operands
[2].isreg
)
9792 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9793 _("immediate operand requires iWMMXt2"));
9795 if (inst
.operands
[2].imm
== 0)
9797 switch ((inst
.instruction
>> 20) & 0xf)
9803 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9804 inst
.operands
[2].imm
= 16;
9805 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9811 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9812 inst
.operands
[2].imm
= 32;
9813 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9820 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9822 wrn
= (inst
.instruction
>> 16) & 0xf;
9823 inst
.instruction
&= 0xff0fff0f;
9824 inst
.instruction
|= wrn
;
9825 /* Bail out here; the instruction is now assembled. */
9830 /* Map 32 -> 0, etc. */
9831 inst
.operands
[2].imm
&= 0x1f;
9832 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
9836 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9837 operations first, then control, shift, and load/store. */
9839 /* Insns like "foo X,Y,Z". */
9842 do_mav_triple (void)
9844 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9845 inst
.instruction
|= inst
.operands
[1].reg
;
9846 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9849 /* Insns like "foo W,X,Y,Z".
9850 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9855 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9856 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9857 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9858 inst
.instruction
|= inst
.operands
[3].reg
;
9861 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9865 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9868 /* Maverick shift immediate instructions.
9869 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9870 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9875 int imm
= inst
.operands
[2].imm
;
9877 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9878 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9880 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9881 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9882 Bit 4 should be 0. */
9883 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
9885 inst
.instruction
|= imm
;
9888 /* XScale instructions. Also sorted arithmetic before move. */
9890 /* Xscale multiply-accumulate (argument parse)
9893 MIAxycc acc0,Rm,Rs. */
9898 inst
.instruction
|= inst
.operands
[1].reg
;
9899 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9902 /* Xscale move-accumulator-register (argument parse)
9904 MARcc acc0,RdLo,RdHi. */
9909 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9910 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9913 /* Xscale move-register-accumulator (argument parse)
9915 MRAcc RdLo,RdHi,acc0. */
9920 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9921 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9922 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9925 /* Encoding functions relevant only to Thumb. */
9927 /* inst.operands[i] is a shifted-register operand; encode
9928 it into inst.instruction in the format used by Thumb32. */
9931 encode_thumb32_shifted_operand (int i
)
9933 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9934 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9936 constraint (inst
.operands
[i
].immisreg
,
9937 _("shift by register not allowed in thumb mode"));
9938 inst
.instruction
|= inst
.operands
[i
].reg
;
9939 if (shift
== SHIFT_RRX
)
9940 inst
.instruction
|= SHIFT_ROR
<< 4;
9943 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9944 _("expression too complex"));
9946 constraint (value
> 32
9947 || (value
== 32 && (shift
== SHIFT_LSL
9948 || shift
== SHIFT_ROR
)),
9949 _("shift expression is too large"));
9953 else if (value
== 32)
9956 inst
.instruction
|= shift
<< 4;
9957 inst
.instruction
|= (value
& 0x1c) << 10;
9958 inst
.instruction
|= (value
& 0x03) << 6;
9963 /* inst.operands[i] was set up by parse_address. Encode it into a
9964 Thumb32 format load or store instruction. Reject forms that cannot
9965 be used with such instructions. If is_t is true, reject forms that
9966 cannot be used with a T instruction; if is_d is true, reject forms
9967 that cannot be used with a D instruction. If it is a store insn,
9971 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9973 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9975 constraint (!inst
.operands
[i
].isreg
,
9976 _("Instruction does not support =N addresses"));
9978 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9979 if (inst
.operands
[i
].immisreg
)
9981 constraint (is_pc
, BAD_PC_ADDRESSING
);
9982 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9983 constraint (inst
.operands
[i
].negative
,
9984 _("Thumb does not support negative register indexing"));
9985 constraint (inst
.operands
[i
].postind
,
9986 _("Thumb does not support register post-indexing"));
9987 constraint (inst
.operands
[i
].writeback
,
9988 _("Thumb does not support register indexing with writeback"));
9989 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9990 _("Thumb supports only LSL in shifted register indexing"));
9992 inst
.instruction
|= inst
.operands
[i
].imm
;
9993 if (inst
.operands
[i
].shifted
)
9995 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9996 _("expression too complex"));
9997 constraint (inst
.reloc
.exp
.X_add_number
< 0
9998 || inst
.reloc
.exp
.X_add_number
> 3,
9999 _("shift out of range"));
10000 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10002 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10004 else if (inst
.operands
[i
].preind
)
10006 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10007 constraint (is_t
&& inst
.operands
[i
].writeback
,
10008 _("cannot use writeback with this instruction"));
10009 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10010 BAD_PC_ADDRESSING
);
10014 inst
.instruction
|= 0x01000000;
10015 if (inst
.operands
[i
].writeback
)
10016 inst
.instruction
|= 0x00200000;
10020 inst
.instruction
|= 0x00000c00;
10021 if (inst
.operands
[i
].writeback
)
10022 inst
.instruction
|= 0x00000100;
10024 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10026 else if (inst
.operands
[i
].postind
)
10028 gas_assert (inst
.operands
[i
].writeback
);
10029 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10030 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10033 inst
.instruction
|= 0x00200000;
10035 inst
.instruction
|= 0x00000900;
10036 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10038 else /* unindexed - only for coprocessor */
10039 inst
.error
= _("instruction does not accept unindexed addressing");
10042 /* Table of Thumb instructions which exist in both 16- and 32-bit
10043 encodings (the latter only in post-V6T2 cores). The index is the
10044 value used in the insns table below. When there is more than one
10045 possible 16-bit encoding for the instruction, this table always
10047 Also contains several pseudo-instructions used during relaxation. */
10048 #define T16_32_TAB \
10049 X(_adc, 4140, eb400000), \
10050 X(_adcs, 4140, eb500000), \
10051 X(_add, 1c00, eb000000), \
10052 X(_adds, 1c00, eb100000), \
10053 X(_addi, 0000, f1000000), \
10054 X(_addis, 0000, f1100000), \
10055 X(_add_pc,000f, f20f0000), \
10056 X(_add_sp,000d, f10d0000), \
10057 X(_adr, 000f, f20f0000), \
10058 X(_and, 4000, ea000000), \
10059 X(_ands, 4000, ea100000), \
10060 X(_asr, 1000, fa40f000), \
10061 X(_asrs, 1000, fa50f000), \
10062 X(_b, e000, f000b000), \
10063 X(_bcond, d000, f0008000), \
10064 X(_bic, 4380, ea200000), \
10065 X(_bics, 4380, ea300000), \
10066 X(_cmn, 42c0, eb100f00), \
10067 X(_cmp, 2800, ebb00f00), \
10068 X(_cpsie, b660, f3af8400), \
10069 X(_cpsid, b670, f3af8600), \
10070 X(_cpy, 4600, ea4f0000), \
10071 X(_dec_sp,80dd, f1ad0d00), \
10072 X(_eor, 4040, ea800000), \
10073 X(_eors, 4040, ea900000), \
10074 X(_inc_sp,00dd, f10d0d00), \
10075 X(_ldmia, c800, e8900000), \
10076 X(_ldr, 6800, f8500000), \
10077 X(_ldrb, 7800, f8100000), \
10078 X(_ldrh, 8800, f8300000), \
10079 X(_ldrsb, 5600, f9100000), \
10080 X(_ldrsh, 5e00, f9300000), \
10081 X(_ldr_pc,4800, f85f0000), \
10082 X(_ldr_pc2,4800, f85f0000), \
10083 X(_ldr_sp,9800, f85d0000), \
10084 X(_lsl, 0000, fa00f000), \
10085 X(_lsls, 0000, fa10f000), \
10086 X(_lsr, 0800, fa20f000), \
10087 X(_lsrs, 0800, fa30f000), \
10088 X(_mov, 2000, ea4f0000), \
10089 X(_movs, 2000, ea5f0000), \
10090 X(_mul, 4340, fb00f000), \
10091 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10092 X(_mvn, 43c0, ea6f0000), \
10093 X(_mvns, 43c0, ea7f0000), \
10094 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10095 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10096 X(_orr, 4300, ea400000), \
10097 X(_orrs, 4300, ea500000), \
10098 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10099 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10100 X(_rev, ba00, fa90f080), \
10101 X(_rev16, ba40, fa90f090), \
10102 X(_revsh, bac0, fa90f0b0), \
10103 X(_ror, 41c0, fa60f000), \
10104 X(_rors, 41c0, fa70f000), \
10105 X(_sbc, 4180, eb600000), \
10106 X(_sbcs, 4180, eb700000), \
10107 X(_stmia, c000, e8800000), \
10108 X(_str, 6000, f8400000), \
10109 X(_strb, 7000, f8000000), \
10110 X(_strh, 8000, f8200000), \
10111 X(_str_sp,9000, f84d0000), \
10112 X(_sub, 1e00, eba00000), \
10113 X(_subs, 1e00, ebb00000), \
10114 X(_subi, 8000, f1a00000), \
10115 X(_subis, 8000, f1b00000), \
10116 X(_sxtb, b240, fa4ff080), \
10117 X(_sxth, b200, fa0ff080), \
10118 X(_tst, 4200, ea100f00), \
10119 X(_uxtb, b2c0, fa5ff080), \
10120 X(_uxth, b280, fa1ff080), \
10121 X(_nop, bf00, f3af8000), \
10122 X(_yield, bf10, f3af8001), \
10123 X(_wfe, bf20, f3af8002), \
10124 X(_wfi, bf30, f3af8003), \
10125 X(_sev, bf40, f3af8004), \
10126 X(_sevl, bf50, f3af8005), \
10127 X(_udf, de00, f7f0a000)
10129 /* To catch errors in encoding functions, the codes are all offset by
10130 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10131 as 16-bit instructions. */
10132 #define X(a,b,c) T_MNEM##a
10133 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10136 #define X(a,b,c) 0x##b
10137 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10138 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10141 #define X(a,b,c) 0x##c
10142 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10143 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10144 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10148 /* Thumb instruction encoders, in alphabetical order. */
10150 /* ADDW or SUBW. */
10153 do_t_add_sub_w (void)
10157 Rd
= inst
.operands
[0].reg
;
10158 Rn
= inst
.operands
[1].reg
;
10160 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10161 is the SP-{plus,minus}-immediate form of the instruction. */
10163 constraint (Rd
== REG_PC
, BAD_PC
);
10165 reject_bad_reg (Rd
);
10167 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10168 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10171 /* Parse an add or subtract instruction. We get here with inst.instruction
10172 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10175 do_t_add_sub (void)
10179 Rd
= inst
.operands
[0].reg
;
10180 Rs
= (inst
.operands
[1].present
10181 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10182 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10185 set_it_insn_type_last ();
10187 if (unified_syntax
)
10190 bfd_boolean narrow
;
10193 flags
= (inst
.instruction
== T_MNEM_adds
10194 || inst
.instruction
== T_MNEM_subs
);
10196 narrow
= !in_it_block ();
10198 narrow
= in_it_block ();
10199 if (!inst
.operands
[2].isreg
)
10203 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10205 add
= (inst
.instruction
== T_MNEM_add
10206 || inst
.instruction
== T_MNEM_adds
);
10208 if (inst
.size_req
!= 4)
10210 /* Attempt to use a narrow opcode, with relaxation if
10212 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10213 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10214 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10215 opcode
= T_MNEM_add_sp
;
10216 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10217 opcode
= T_MNEM_add_pc
;
10218 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10221 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10223 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10227 inst
.instruction
= THUMB_OP16(opcode
);
10228 inst
.instruction
|= (Rd
<< 4) | Rs
;
10229 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10230 if (inst
.size_req
!= 2)
10231 inst
.relax
= opcode
;
10234 constraint (inst
.size_req
== 2, BAD_HIREG
);
10236 if (inst
.size_req
== 4
10237 || (inst
.size_req
!= 2 && !opcode
))
10241 constraint (add
, BAD_PC
);
10242 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10243 _("only SUBS PC, LR, #const allowed"));
10244 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10245 _("expression too complex"));
10246 constraint (inst
.reloc
.exp
.X_add_number
< 0
10247 || inst
.reloc
.exp
.X_add_number
> 0xff,
10248 _("immediate value out of range"));
10249 inst
.instruction
= T2_SUBS_PC_LR
10250 | inst
.reloc
.exp
.X_add_number
;
10251 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10254 else if (Rs
== REG_PC
)
10256 /* Always use addw/subw. */
10257 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10258 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10262 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10263 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10266 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10268 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10270 inst
.instruction
|= Rd
<< 8;
10271 inst
.instruction
|= Rs
<< 16;
10276 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10277 unsigned int shift
= inst
.operands
[2].shift_kind
;
10279 Rn
= inst
.operands
[2].reg
;
10280 /* See if we can do this with a 16-bit instruction. */
10281 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10283 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10288 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10289 || inst
.instruction
== T_MNEM_add
)
10291 : T_OPCODE_SUB_R3
);
10292 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10296 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10298 /* Thumb-1 cores (except v6-M) require at least one high
10299 register in a narrow non flag setting add. */
10300 if (Rd
> 7 || Rn
> 7
10301 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10302 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10309 inst
.instruction
= T_OPCODE_ADD_HI
;
10310 inst
.instruction
|= (Rd
& 8) << 4;
10311 inst
.instruction
|= (Rd
& 7);
10312 inst
.instruction
|= Rn
<< 3;
10318 constraint (Rd
== REG_PC
, BAD_PC
);
10319 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10320 constraint (Rs
== REG_PC
, BAD_PC
);
10321 reject_bad_reg (Rn
);
10323 /* If we get here, it can't be done in 16 bits. */
10324 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10325 _("shift must be constant"));
10326 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10327 inst
.instruction
|= Rd
<< 8;
10328 inst
.instruction
|= Rs
<< 16;
10329 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10330 _("shift value over 3 not allowed in thumb mode"));
10331 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10332 _("only LSL shift allowed in thumb mode"));
10333 encode_thumb32_shifted_operand (2);
10338 constraint (inst
.instruction
== T_MNEM_adds
10339 || inst
.instruction
== T_MNEM_subs
,
10342 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10344 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10345 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10348 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10349 ? 0x0000 : 0x8000);
10350 inst
.instruction
|= (Rd
<< 4) | Rs
;
10351 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10355 Rn
= inst
.operands
[2].reg
;
10356 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10358 /* We now have Rd, Rs, and Rn set to registers. */
10359 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10361 /* Can't do this for SUB. */
10362 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10363 inst
.instruction
= T_OPCODE_ADD_HI
;
10364 inst
.instruction
|= (Rd
& 8) << 4;
10365 inst
.instruction
|= (Rd
& 7);
10367 inst
.instruction
|= Rn
<< 3;
10369 inst
.instruction
|= Rs
<< 3;
10371 constraint (1, _("dest must overlap one source register"));
10375 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10376 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10377 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10387 Rd
= inst
.operands
[0].reg
;
10388 reject_bad_reg (Rd
);
10390 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10392 /* Defer to section relaxation. */
10393 inst
.relax
= inst
.instruction
;
10394 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10395 inst
.instruction
|= Rd
<< 4;
10397 else if (unified_syntax
&& inst
.size_req
!= 2)
10399 /* Generate a 32-bit opcode. */
10400 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10401 inst
.instruction
|= Rd
<< 8;
10402 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10403 inst
.reloc
.pc_rel
= 1;
10407 /* Generate a 16-bit opcode. */
10408 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10409 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10410 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10411 inst
.reloc
.pc_rel
= 1;
10413 inst
.instruction
|= Rd
<< 4;
10417 /* Arithmetic instructions for which there is just one 16-bit
10418 instruction encoding, and it allows only two low registers.
10419 For maximal compatibility with ARM syntax, we allow three register
10420 operands even when Thumb-32 instructions are not available, as long
10421 as the first two are identical. For instance, both "sbc r0,r1" and
10422 "sbc r0,r0,r1" are allowed. */
10428 Rd
= inst
.operands
[0].reg
;
10429 Rs
= (inst
.operands
[1].present
10430 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10431 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10432 Rn
= inst
.operands
[2].reg
;
10434 reject_bad_reg (Rd
);
10435 reject_bad_reg (Rs
);
10436 if (inst
.operands
[2].isreg
)
10437 reject_bad_reg (Rn
);
10439 if (unified_syntax
)
10441 if (!inst
.operands
[2].isreg
)
10443 /* For an immediate, we always generate a 32-bit opcode;
10444 section relaxation will shrink it later if possible. */
10445 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10446 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10447 inst
.instruction
|= Rd
<< 8;
10448 inst
.instruction
|= Rs
<< 16;
10449 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10453 bfd_boolean narrow
;
10455 /* See if we can do this with a 16-bit instruction. */
10456 if (THUMB_SETS_FLAGS (inst
.instruction
))
10457 narrow
= !in_it_block ();
10459 narrow
= in_it_block ();
10461 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10463 if (inst
.operands
[2].shifted
)
10465 if (inst
.size_req
== 4)
10471 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10472 inst
.instruction
|= Rd
;
10473 inst
.instruction
|= Rn
<< 3;
10477 /* If we get here, it can't be done in 16 bits. */
10478 constraint (inst
.operands
[2].shifted
10479 && inst
.operands
[2].immisreg
,
10480 _("shift must be constant"));
10481 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10482 inst
.instruction
|= Rd
<< 8;
10483 inst
.instruction
|= Rs
<< 16;
10484 encode_thumb32_shifted_operand (2);
10489 /* On its face this is a lie - the instruction does set the
10490 flags. However, the only supported mnemonic in this mode
10491 says it doesn't. */
10492 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10494 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10495 _("unshifted register required"));
10496 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10497 constraint (Rd
!= Rs
,
10498 _("dest and source1 must be the same register"));
10500 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10501 inst
.instruction
|= Rd
;
10502 inst
.instruction
|= Rn
<< 3;
10506 /* Similarly, but for instructions where the arithmetic operation is
10507 commutative, so we can allow either of them to be different from
10508 the destination operand in a 16-bit instruction. For instance, all
10509 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10516 Rd
= inst
.operands
[0].reg
;
10517 Rs
= (inst
.operands
[1].present
10518 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10519 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10520 Rn
= inst
.operands
[2].reg
;
10522 reject_bad_reg (Rd
);
10523 reject_bad_reg (Rs
);
10524 if (inst
.operands
[2].isreg
)
10525 reject_bad_reg (Rn
);
10527 if (unified_syntax
)
10529 if (!inst
.operands
[2].isreg
)
10531 /* For an immediate, we always generate a 32-bit opcode;
10532 section relaxation will shrink it later if possible. */
10533 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10534 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10535 inst
.instruction
|= Rd
<< 8;
10536 inst
.instruction
|= Rs
<< 16;
10537 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10541 bfd_boolean narrow
;
10543 /* See if we can do this with a 16-bit instruction. */
10544 if (THUMB_SETS_FLAGS (inst
.instruction
))
10545 narrow
= !in_it_block ();
10547 narrow
= in_it_block ();
10549 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10551 if (inst
.operands
[2].shifted
)
10553 if (inst
.size_req
== 4)
10560 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10561 inst
.instruction
|= Rd
;
10562 inst
.instruction
|= Rn
<< 3;
10567 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10568 inst
.instruction
|= Rd
;
10569 inst
.instruction
|= Rs
<< 3;
10574 /* If we get here, it can't be done in 16 bits. */
10575 constraint (inst
.operands
[2].shifted
10576 && inst
.operands
[2].immisreg
,
10577 _("shift must be constant"));
10578 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10579 inst
.instruction
|= Rd
<< 8;
10580 inst
.instruction
|= Rs
<< 16;
10581 encode_thumb32_shifted_operand (2);
10586 /* On its face this is a lie - the instruction does set the
10587 flags. However, the only supported mnemonic in this mode
10588 says it doesn't. */
10589 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10591 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10592 _("unshifted register required"));
10593 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10595 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10596 inst
.instruction
|= Rd
;
10599 inst
.instruction
|= Rn
<< 3;
10601 inst
.instruction
|= Rs
<< 3;
10603 constraint (1, _("dest must overlap one source register"));
10611 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10612 constraint (msb
> 32, _("bit-field extends past end of register"));
10613 /* The instruction encoding stores the LSB and MSB,
10614 not the LSB and width. */
10615 Rd
= inst
.operands
[0].reg
;
10616 reject_bad_reg (Rd
);
10617 inst
.instruction
|= Rd
<< 8;
10618 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10619 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10620 inst
.instruction
|= msb
- 1;
10629 Rd
= inst
.operands
[0].reg
;
10630 reject_bad_reg (Rd
);
10632 /* #0 in second position is alternative syntax for bfc, which is
10633 the same instruction but with REG_PC in the Rm field. */
10634 if (!inst
.operands
[1].isreg
)
10638 Rn
= inst
.operands
[1].reg
;
10639 reject_bad_reg (Rn
);
10642 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10643 constraint (msb
> 32, _("bit-field extends past end of register"));
10644 /* The instruction encoding stores the LSB and MSB,
10645 not the LSB and width. */
10646 inst
.instruction
|= Rd
<< 8;
10647 inst
.instruction
|= Rn
<< 16;
10648 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10649 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10650 inst
.instruction
|= msb
- 1;
10658 Rd
= inst
.operands
[0].reg
;
10659 Rn
= inst
.operands
[1].reg
;
10661 reject_bad_reg (Rd
);
10662 reject_bad_reg (Rn
);
10664 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10665 _("bit-field extends past end of register"));
10666 inst
.instruction
|= Rd
<< 8;
10667 inst
.instruction
|= Rn
<< 16;
10668 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10669 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10670 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10673 /* ARM V5 Thumb BLX (argument parse)
10674 BLX <target_addr> which is BLX(1)
10675 BLX <Rm> which is BLX(2)
10676 Unfortunately, there are two different opcodes for this mnemonic.
10677 So, the insns[].value is not used, and the code here zaps values
10678 into inst.instruction.
10680 ??? How to take advantage of the additional two bits of displacement
10681 available in Thumb32 mode? Need new relocation? */
10686 set_it_insn_type_last ();
10688 if (inst
.operands
[0].isreg
)
10690 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10691 /* We have a register, so this is BLX(2). */
10692 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10696 /* No register. This must be BLX(1). */
10697 inst
.instruction
= 0xf000e800;
10698 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10710 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10712 if (in_it_block ())
10714 /* Conditional branches inside IT blocks are encoded as unconditional
10716 cond
= COND_ALWAYS
;
10721 if (cond
!= COND_ALWAYS
)
10722 opcode
= T_MNEM_bcond
;
10724 opcode
= inst
.instruction
;
10727 && (inst
.size_req
== 4
10728 || (inst
.size_req
!= 2
10729 && (inst
.operands
[0].hasreloc
10730 || inst
.reloc
.exp
.X_op
== O_constant
))))
10732 inst
.instruction
= THUMB_OP32(opcode
);
10733 if (cond
== COND_ALWAYS
)
10734 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10737 gas_assert (cond
!= 0xF);
10738 inst
.instruction
|= cond
<< 22;
10739 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10744 inst
.instruction
= THUMB_OP16(opcode
);
10745 if (cond
== COND_ALWAYS
)
10746 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10749 inst
.instruction
|= cond
<< 8;
10750 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10752 /* Allow section relaxation. */
10753 if (unified_syntax
&& inst
.size_req
!= 2)
10754 inst
.relax
= opcode
;
10756 inst
.reloc
.type
= reloc
;
10757 inst
.reloc
.pc_rel
= 1;
10760 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10761 between the two is the maximum immediate allowed - which is passed in
10764 do_t_bkpt_hlt1 (int range
)
10766 constraint (inst
.cond
!= COND_ALWAYS
,
10767 _("instruction is always unconditional"));
10768 if (inst
.operands
[0].present
)
10770 constraint (inst
.operands
[0].imm
> range
,
10771 _("immediate value out of range"));
10772 inst
.instruction
|= inst
.operands
[0].imm
;
10775 set_it_insn_type (NEUTRAL_IT_INSN
);
10781 do_t_bkpt_hlt1 (63);
10787 do_t_bkpt_hlt1 (255);
10791 do_t_branch23 (void)
10793 set_it_insn_type_last ();
10794 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10796 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10797 this file. We used to simply ignore the PLT reloc type here --
10798 the branch encoding is now needed to deal with TLSCALL relocs.
10799 So if we see a PLT reloc now, put it back to how it used to be to
10800 keep the preexisting behaviour. */
10801 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10802 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10804 #if defined(OBJ_COFF)
10805 /* If the destination of the branch is a defined symbol which does not have
10806 the THUMB_FUNC attribute, then we must be calling a function which has
10807 the (interfacearm) attribute. We look for the Thumb entry point to that
10808 function and change the branch to refer to that function instead. */
10809 if ( inst
.reloc
.exp
.X_op
== O_symbol
10810 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10811 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10812 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10813 inst
.reloc
.exp
.X_add_symbol
=
10814 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10821 set_it_insn_type_last ();
10822 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10823 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10824 should cause the alignment to be checked once it is known. This is
10825 because BX PC only works if the instruction is word aligned. */
10833 set_it_insn_type_last ();
10834 Rm
= inst
.operands
[0].reg
;
10835 reject_bad_reg (Rm
);
10836 inst
.instruction
|= Rm
<< 16;
10845 Rd
= inst
.operands
[0].reg
;
10846 Rm
= inst
.operands
[1].reg
;
10848 reject_bad_reg (Rd
);
10849 reject_bad_reg (Rm
);
10851 inst
.instruction
|= Rd
<< 8;
10852 inst
.instruction
|= Rm
<< 16;
10853 inst
.instruction
|= Rm
;
10859 set_it_insn_type (OUTSIDE_IT_INSN
);
10860 inst
.instruction
|= inst
.operands
[0].imm
;
10866 set_it_insn_type (OUTSIDE_IT_INSN
);
10868 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
10869 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
10871 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
10872 inst
.instruction
= 0xf3af8000;
10873 inst
.instruction
|= imod
<< 9;
10874 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
10875 if (inst
.operands
[1].present
)
10876 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
10880 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
10881 && (inst
.operands
[0].imm
& 4),
10882 _("selected processor does not support 'A' form "
10883 "of this instruction"));
10884 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
10885 _("Thumb does not support the 2-argument "
10886 "form of this instruction"));
10887 inst
.instruction
|= inst
.operands
[0].imm
;
10891 /* THUMB CPY instruction (argument parse). */
10896 if (inst
.size_req
== 4)
10898 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10899 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10900 inst
.instruction
|= inst
.operands
[1].reg
;
10904 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10905 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10906 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10913 set_it_insn_type (OUTSIDE_IT_INSN
);
10914 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10915 inst
.instruction
|= inst
.operands
[0].reg
;
10916 inst
.reloc
.pc_rel
= 1;
10917 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10923 inst
.instruction
|= inst
.operands
[0].imm
;
10929 unsigned Rd
, Rn
, Rm
;
10931 Rd
= inst
.operands
[0].reg
;
10932 Rn
= (inst
.operands
[1].present
10933 ? inst
.operands
[1].reg
: Rd
);
10934 Rm
= inst
.operands
[2].reg
;
10936 reject_bad_reg (Rd
);
10937 reject_bad_reg (Rn
);
10938 reject_bad_reg (Rm
);
10940 inst
.instruction
|= Rd
<< 8;
10941 inst
.instruction
|= Rn
<< 16;
10942 inst
.instruction
|= Rm
;
10948 if (unified_syntax
&& inst
.size_req
== 4)
10949 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10951 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10957 unsigned int cond
= inst
.operands
[0].imm
;
10959 set_it_insn_type (IT_INSN
);
10960 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10962 now_it
.warn_deprecated
= FALSE
;
10964 /* If the condition is a negative condition, invert the mask. */
10965 if ((cond
& 0x1) == 0x0)
10967 unsigned int mask
= inst
.instruction
& 0x000f;
10969 if ((mask
& 0x7) == 0)
10971 /* No conversion needed. */
10972 now_it
.block_length
= 1;
10974 else if ((mask
& 0x3) == 0)
10977 now_it
.block_length
= 2;
10979 else if ((mask
& 0x1) == 0)
10982 now_it
.block_length
= 3;
10987 now_it
.block_length
= 4;
10990 inst
.instruction
&= 0xfff0;
10991 inst
.instruction
|= mask
;
10994 inst
.instruction
|= cond
<< 4;
10997 /* Helper function used for both push/pop and ldm/stm. */
10999 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11003 load
= (inst
.instruction
& (1 << 20)) != 0;
11005 if (mask
& (1 << 13))
11006 inst
.error
= _("SP not allowed in register list");
11008 if ((mask
& (1 << base
)) != 0
11010 inst
.error
= _("having the base register in the register list when "
11011 "using write back is UNPREDICTABLE");
11015 if (mask
& (1 << 15))
11017 if (mask
& (1 << 14))
11018 inst
.error
= _("LR and PC should not both be in register list");
11020 set_it_insn_type_last ();
11025 if (mask
& (1 << 15))
11026 inst
.error
= _("PC not allowed in register list");
11029 if ((mask
& (mask
- 1)) == 0)
11031 /* Single register transfers implemented as str/ldr. */
11034 if (inst
.instruction
& (1 << 23))
11035 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11037 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11041 if (inst
.instruction
& (1 << 23))
11042 inst
.instruction
= 0x00800000; /* ia -> [base] */
11044 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11047 inst
.instruction
|= 0xf8400000;
11049 inst
.instruction
|= 0x00100000;
11051 mask
= ffs (mask
) - 1;
11054 else if (writeback
)
11055 inst
.instruction
|= WRITE_BACK
;
11057 inst
.instruction
|= mask
;
11058 inst
.instruction
|= base
<< 16;
11064 /* This really doesn't seem worth it. */
11065 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11066 _("expression too complex"));
11067 constraint (inst
.operands
[1].writeback
,
11068 _("Thumb load/store multiple does not support {reglist}^"));
11070 if (unified_syntax
)
11072 bfd_boolean narrow
;
11076 /* See if we can use a 16-bit instruction. */
11077 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11078 && inst
.size_req
!= 4
11079 && !(inst
.operands
[1].imm
& ~0xff))
11081 mask
= 1 << inst
.operands
[0].reg
;
11083 if (inst
.operands
[0].reg
<= 7)
11085 if (inst
.instruction
== T_MNEM_stmia
11086 ? inst
.operands
[0].writeback
11087 : (inst
.operands
[0].writeback
11088 == !(inst
.operands
[1].imm
& mask
)))
11090 if (inst
.instruction
== T_MNEM_stmia
11091 && (inst
.operands
[1].imm
& mask
)
11092 && (inst
.operands
[1].imm
& (mask
- 1)))
11093 as_warn (_("value stored for r%d is UNKNOWN"),
11094 inst
.operands
[0].reg
);
11096 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11097 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11098 inst
.instruction
|= inst
.operands
[1].imm
;
11101 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11103 /* This means 1 register in reg list one of 3 situations:
11104 1. Instruction is stmia, but without writeback.
11105 2. lmdia without writeback, but with Rn not in
11107 3. ldmia with writeback, but with Rn in reglist.
11108 Case 3 is UNPREDICTABLE behaviour, so we handle
11109 case 1 and 2 which can be converted into a 16-bit
11110 str or ldr. The SP cases are handled below. */
11111 unsigned long opcode
;
11112 /* First, record an error for Case 3. */
11113 if (inst
.operands
[1].imm
& mask
11114 && inst
.operands
[0].writeback
)
11116 _("having the base register in the register list when "
11117 "using write back is UNPREDICTABLE");
11119 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11121 inst
.instruction
= THUMB_OP16 (opcode
);
11122 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11123 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11127 else if (inst
.operands
[0] .reg
== REG_SP
)
11129 if (inst
.operands
[0].writeback
)
11132 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11133 ? T_MNEM_push
: T_MNEM_pop
);
11134 inst
.instruction
|= inst
.operands
[1].imm
;
11137 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11140 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11141 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11142 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11150 if (inst
.instruction
< 0xffff)
11151 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11153 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11154 inst
.operands
[0].writeback
);
11159 constraint (inst
.operands
[0].reg
> 7
11160 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11161 constraint (inst
.instruction
!= T_MNEM_ldmia
11162 && inst
.instruction
!= T_MNEM_stmia
,
11163 _("Thumb-2 instruction only valid in unified syntax"));
11164 if (inst
.instruction
== T_MNEM_stmia
)
11166 if (!inst
.operands
[0].writeback
)
11167 as_warn (_("this instruction will write back the base register"));
11168 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11169 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11170 as_warn (_("value stored for r%d is UNKNOWN"),
11171 inst
.operands
[0].reg
);
11175 if (!inst
.operands
[0].writeback
11176 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11177 as_warn (_("this instruction will write back the base register"));
11178 else if (inst
.operands
[0].writeback
11179 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11180 as_warn (_("this instruction will not write back the base register"));
11183 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11184 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11185 inst
.instruction
|= inst
.operands
[1].imm
;
11192 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11193 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11194 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11195 || inst
.operands
[1].negative
,
11198 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11200 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11201 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11202 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11208 if (!inst
.operands
[1].present
)
11210 constraint (inst
.operands
[0].reg
== REG_LR
,
11211 _("r14 not allowed as first register "
11212 "when second register is omitted"));
11213 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11215 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11218 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11219 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11220 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11226 unsigned long opcode
;
11229 if (inst
.operands
[0].isreg
11230 && !inst
.operands
[0].preind
11231 && inst
.operands
[0].reg
== REG_PC
)
11232 set_it_insn_type_last ();
11234 opcode
= inst
.instruction
;
11235 if (unified_syntax
)
11237 if (!inst
.operands
[1].isreg
)
11239 if (opcode
<= 0xffff)
11240 inst
.instruction
= THUMB_OP32 (opcode
);
11241 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11244 if (inst
.operands
[1].isreg
11245 && !inst
.operands
[1].writeback
11246 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11247 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11248 && opcode
<= 0xffff
11249 && inst
.size_req
!= 4)
11251 /* Insn may have a 16-bit form. */
11252 Rn
= inst
.operands
[1].reg
;
11253 if (inst
.operands
[1].immisreg
)
11255 inst
.instruction
= THUMB_OP16 (opcode
);
11257 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11259 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11260 reject_bad_reg (inst
.operands
[1].imm
);
11262 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11263 && opcode
!= T_MNEM_ldrsb
)
11264 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11265 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11272 if (inst
.reloc
.pc_rel
)
11273 opcode
= T_MNEM_ldr_pc2
;
11275 opcode
= T_MNEM_ldr_pc
;
11279 if (opcode
== T_MNEM_ldr
)
11280 opcode
= T_MNEM_ldr_sp
;
11282 opcode
= T_MNEM_str_sp
;
11284 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11288 inst
.instruction
= inst
.operands
[0].reg
;
11289 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11291 inst
.instruction
|= THUMB_OP16 (opcode
);
11292 if (inst
.size_req
== 2)
11293 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11295 inst
.relax
= opcode
;
11299 /* Definitely a 32-bit variant. */
11301 /* Warning for Erratum 752419. */
11302 if (opcode
== T_MNEM_ldr
11303 && inst
.operands
[0].reg
== REG_SP
11304 && inst
.operands
[1].writeback
== 1
11305 && !inst
.operands
[1].immisreg
)
11307 if (no_cpu_selected ()
11308 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11309 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11310 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11311 as_warn (_("This instruction may be unpredictable "
11312 "if executed on M-profile cores "
11313 "with interrupts enabled."));
11316 /* Do some validations regarding addressing modes. */
11317 if (inst
.operands
[1].immisreg
)
11318 reject_bad_reg (inst
.operands
[1].imm
);
11320 constraint (inst
.operands
[1].writeback
== 1
11321 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11324 inst
.instruction
= THUMB_OP32 (opcode
);
11325 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11326 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11327 check_ldr_r15_aligned ();
11331 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11333 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11335 /* Only [Rn,Rm] is acceptable. */
11336 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11337 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11338 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11339 || inst
.operands
[1].negative
,
11340 _("Thumb does not support this addressing mode"));
11341 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11345 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11346 if (!inst
.operands
[1].isreg
)
11347 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11350 constraint (!inst
.operands
[1].preind
11351 || inst
.operands
[1].shifted
11352 || inst
.operands
[1].writeback
,
11353 _("Thumb does not support this addressing mode"));
11354 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11356 constraint (inst
.instruction
& 0x0600,
11357 _("byte or halfword not valid for base register"));
11358 constraint (inst
.operands
[1].reg
== REG_PC
11359 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11360 _("r15 based store not allowed"));
11361 constraint (inst
.operands
[1].immisreg
,
11362 _("invalid base register for register offset"));
11364 if (inst
.operands
[1].reg
== REG_PC
)
11365 inst
.instruction
= T_OPCODE_LDR_PC
;
11366 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11367 inst
.instruction
= T_OPCODE_LDR_SP
;
11369 inst
.instruction
= T_OPCODE_STR_SP
;
11371 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11372 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11376 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11377 if (!inst
.operands
[1].immisreg
)
11379 /* Immediate offset. */
11380 inst
.instruction
|= inst
.operands
[0].reg
;
11381 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11382 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11386 /* Register offset. */
11387 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11388 constraint (inst
.operands
[1].negative
,
11389 _("Thumb does not support this addressing mode"));
11392 switch (inst
.instruction
)
11394 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11395 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11396 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11397 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11398 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11399 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11400 case 0x5600 /* ldrsb */:
11401 case 0x5e00 /* ldrsh */: break;
11405 inst
.instruction
|= inst
.operands
[0].reg
;
11406 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11407 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11413 if (!inst
.operands
[1].present
)
11415 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11416 constraint (inst
.operands
[0].reg
== REG_LR
,
11417 _("r14 not allowed here"));
11418 constraint (inst
.operands
[0].reg
== REG_R12
,
11419 _("r12 not allowed here"));
11422 if (inst
.operands
[2].writeback
11423 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11424 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11425 as_warn (_("base register written back, and overlaps "
11426 "one of transfer registers"));
11428 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11429 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11430 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11436 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11437 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11443 unsigned Rd
, Rn
, Rm
, Ra
;
11445 Rd
= inst
.operands
[0].reg
;
11446 Rn
= inst
.operands
[1].reg
;
11447 Rm
= inst
.operands
[2].reg
;
11448 Ra
= inst
.operands
[3].reg
;
11450 reject_bad_reg (Rd
);
11451 reject_bad_reg (Rn
);
11452 reject_bad_reg (Rm
);
11453 reject_bad_reg (Ra
);
11455 inst
.instruction
|= Rd
<< 8;
11456 inst
.instruction
|= Rn
<< 16;
11457 inst
.instruction
|= Rm
;
11458 inst
.instruction
|= Ra
<< 12;
11464 unsigned RdLo
, RdHi
, Rn
, Rm
;
11466 RdLo
= inst
.operands
[0].reg
;
11467 RdHi
= inst
.operands
[1].reg
;
11468 Rn
= inst
.operands
[2].reg
;
11469 Rm
= inst
.operands
[3].reg
;
11471 reject_bad_reg (RdLo
);
11472 reject_bad_reg (RdHi
);
11473 reject_bad_reg (Rn
);
11474 reject_bad_reg (Rm
);
11476 inst
.instruction
|= RdLo
<< 12;
11477 inst
.instruction
|= RdHi
<< 8;
11478 inst
.instruction
|= Rn
<< 16;
11479 inst
.instruction
|= Rm
;
11483 do_t_mov_cmp (void)
11487 Rn
= inst
.operands
[0].reg
;
11488 Rm
= inst
.operands
[1].reg
;
11491 set_it_insn_type_last ();
11493 if (unified_syntax
)
11495 int r0off
= (inst
.instruction
== T_MNEM_mov
11496 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11497 unsigned long opcode
;
11498 bfd_boolean narrow
;
11499 bfd_boolean low_regs
;
11501 low_regs
= (Rn
<= 7 && Rm
<= 7);
11502 opcode
= inst
.instruction
;
11503 if (in_it_block ())
11504 narrow
= opcode
!= T_MNEM_movs
;
11506 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11507 if (inst
.size_req
== 4
11508 || inst
.operands
[1].shifted
)
11511 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11512 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11513 && !inst
.operands
[1].shifted
11517 inst
.instruction
= T2_SUBS_PC_LR
;
11521 if (opcode
== T_MNEM_cmp
)
11523 constraint (Rn
== REG_PC
, BAD_PC
);
11526 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11528 warn_deprecated_sp (Rm
);
11529 /* R15 was documented as a valid choice for Rm in ARMv6,
11530 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11531 tools reject R15, so we do too. */
11532 constraint (Rm
== REG_PC
, BAD_PC
);
11535 reject_bad_reg (Rm
);
11537 else if (opcode
== T_MNEM_mov
11538 || opcode
== T_MNEM_movs
)
11540 if (inst
.operands
[1].isreg
)
11542 if (opcode
== T_MNEM_movs
)
11544 reject_bad_reg (Rn
);
11545 reject_bad_reg (Rm
);
11549 /* This is mov.n. */
11550 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11551 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11553 as_warn (_("Use of r%u as a source register is "
11554 "deprecated when r%u is the destination "
11555 "register."), Rm
, Rn
);
11560 /* This is mov.w. */
11561 constraint (Rn
== REG_PC
, BAD_PC
);
11562 constraint (Rm
== REG_PC
, BAD_PC
);
11563 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11567 reject_bad_reg (Rn
);
11570 if (!inst
.operands
[1].isreg
)
11572 /* Immediate operand. */
11573 if (!in_it_block () && opcode
== T_MNEM_mov
)
11575 if (low_regs
&& narrow
)
11577 inst
.instruction
= THUMB_OP16 (opcode
);
11578 inst
.instruction
|= Rn
<< 8;
11579 if (inst
.size_req
== 2)
11580 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11582 inst
.relax
= opcode
;
11586 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11587 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11588 inst
.instruction
|= Rn
<< r0off
;
11589 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11592 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11593 && (inst
.instruction
== T_MNEM_mov
11594 || inst
.instruction
== T_MNEM_movs
))
11596 /* Register shifts are encoded as separate shift instructions. */
11597 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11599 if (in_it_block ())
11604 if (inst
.size_req
== 4)
11607 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11613 switch (inst
.operands
[1].shift_kind
)
11616 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11619 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11622 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11625 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11631 inst
.instruction
= opcode
;
11634 inst
.instruction
|= Rn
;
11635 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11640 inst
.instruction
|= CONDS_BIT
;
11642 inst
.instruction
|= Rn
<< 8;
11643 inst
.instruction
|= Rm
<< 16;
11644 inst
.instruction
|= inst
.operands
[1].imm
;
11649 /* Some mov with immediate shift have narrow variants.
11650 Register shifts are handled above. */
11651 if (low_regs
&& inst
.operands
[1].shifted
11652 && (inst
.instruction
== T_MNEM_mov
11653 || inst
.instruction
== T_MNEM_movs
))
11655 if (in_it_block ())
11656 narrow
= (inst
.instruction
== T_MNEM_mov
);
11658 narrow
= (inst
.instruction
== T_MNEM_movs
);
11663 switch (inst
.operands
[1].shift_kind
)
11665 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11666 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11667 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11668 default: narrow
= FALSE
; break;
11674 inst
.instruction
|= Rn
;
11675 inst
.instruction
|= Rm
<< 3;
11676 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11680 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11681 inst
.instruction
|= Rn
<< r0off
;
11682 encode_thumb32_shifted_operand (1);
11686 switch (inst
.instruction
)
11689 /* In v4t or v5t a move of two lowregs produces unpredictable
11690 results. Don't allow this. */
11693 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11694 "MOV Rd, Rs with two low registers is not "
11695 "permitted on this architecture");
11696 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11700 inst
.instruction
= T_OPCODE_MOV_HR
;
11701 inst
.instruction
|= (Rn
& 0x8) << 4;
11702 inst
.instruction
|= (Rn
& 0x7);
11703 inst
.instruction
|= Rm
<< 3;
11707 /* We know we have low registers at this point.
11708 Generate LSLS Rd, Rs, #0. */
11709 inst
.instruction
= T_OPCODE_LSL_I
;
11710 inst
.instruction
|= Rn
;
11711 inst
.instruction
|= Rm
<< 3;
11717 inst
.instruction
= T_OPCODE_CMP_LR
;
11718 inst
.instruction
|= Rn
;
11719 inst
.instruction
|= Rm
<< 3;
11723 inst
.instruction
= T_OPCODE_CMP_HR
;
11724 inst
.instruction
|= (Rn
& 0x8) << 4;
11725 inst
.instruction
|= (Rn
& 0x7);
11726 inst
.instruction
|= Rm
<< 3;
11733 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11735 /* PR 10443: Do not silently ignore shifted operands. */
11736 constraint (inst
.operands
[1].shifted
,
11737 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11739 if (inst
.operands
[1].isreg
)
11741 if (Rn
< 8 && Rm
< 8)
11743 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11744 since a MOV instruction produces unpredictable results. */
11745 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11746 inst
.instruction
= T_OPCODE_ADD_I3
;
11748 inst
.instruction
= T_OPCODE_CMP_LR
;
11750 inst
.instruction
|= Rn
;
11751 inst
.instruction
|= Rm
<< 3;
11755 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11756 inst
.instruction
= T_OPCODE_MOV_HR
;
11758 inst
.instruction
= T_OPCODE_CMP_HR
;
11764 constraint (Rn
> 7,
11765 _("only lo regs allowed with immediate"));
11766 inst
.instruction
|= Rn
<< 8;
11767 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11778 top
= (inst
.instruction
& 0x00800000) != 0;
11779 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11781 constraint (top
, _(":lower16: not allowed this instruction"));
11782 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11784 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11786 constraint (!top
, _(":upper16: not allowed this instruction"));
11787 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11790 Rd
= inst
.operands
[0].reg
;
11791 reject_bad_reg (Rd
);
11793 inst
.instruction
|= Rd
<< 8;
11794 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11796 imm
= inst
.reloc
.exp
.X_add_number
;
11797 inst
.instruction
|= (imm
& 0xf000) << 4;
11798 inst
.instruction
|= (imm
& 0x0800) << 15;
11799 inst
.instruction
|= (imm
& 0x0700) << 4;
11800 inst
.instruction
|= (imm
& 0x00ff);
11805 do_t_mvn_tst (void)
11809 Rn
= inst
.operands
[0].reg
;
11810 Rm
= inst
.operands
[1].reg
;
11812 if (inst
.instruction
== T_MNEM_cmp
11813 || inst
.instruction
== T_MNEM_cmn
)
11814 constraint (Rn
== REG_PC
, BAD_PC
);
11816 reject_bad_reg (Rn
);
11817 reject_bad_reg (Rm
);
11819 if (unified_syntax
)
11821 int r0off
= (inst
.instruction
== T_MNEM_mvn
11822 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
11823 bfd_boolean narrow
;
11825 if (inst
.size_req
== 4
11826 || inst
.instruction
> 0xffff
11827 || inst
.operands
[1].shifted
11828 || Rn
> 7 || Rm
> 7)
11830 else if (inst
.instruction
== T_MNEM_cmn
11831 || inst
.instruction
== T_MNEM_tst
)
11833 else if (THUMB_SETS_FLAGS (inst
.instruction
))
11834 narrow
= !in_it_block ();
11836 narrow
= in_it_block ();
11838 if (!inst
.operands
[1].isreg
)
11840 /* For an immediate, we always generate a 32-bit opcode;
11841 section relaxation will shrink it later if possible. */
11842 if (inst
.instruction
< 0xffff)
11843 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11844 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11845 inst
.instruction
|= Rn
<< r0off
;
11846 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11850 /* See if we can do this with a 16-bit instruction. */
11853 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11854 inst
.instruction
|= Rn
;
11855 inst
.instruction
|= Rm
<< 3;
11859 constraint (inst
.operands
[1].shifted
11860 && inst
.operands
[1].immisreg
,
11861 _("shift must be constant"));
11862 if (inst
.instruction
< 0xffff)
11863 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11864 inst
.instruction
|= Rn
<< r0off
;
11865 encode_thumb32_shifted_operand (1);
11871 constraint (inst
.instruction
> 0xffff
11872 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
11873 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
11874 _("unshifted register required"));
11875 constraint (Rn
> 7 || Rm
> 7,
11878 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11879 inst
.instruction
|= Rn
;
11880 inst
.instruction
|= Rm
<< 3;
11889 if (do_vfp_nsyn_mrs () == SUCCESS
)
11892 Rd
= inst
.operands
[0].reg
;
11893 reject_bad_reg (Rd
);
11894 inst
.instruction
|= Rd
<< 8;
11896 if (inst
.operands
[1].isreg
)
11898 unsigned br
= inst
.operands
[1].reg
;
11899 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
11900 as_bad (_("bad register for mrs"));
11902 inst
.instruction
|= br
& (0xf << 16);
11903 inst
.instruction
|= (br
& 0x300) >> 4;
11904 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
11908 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11910 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11912 /* PR gas/12698: The constraint is only applied for m_profile.
11913 If the user has specified -march=all, we want to ignore it as
11914 we are building for any CPU type, including non-m variants. */
11915 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11916 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
11917 "not support requested special purpose register"));
11920 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11922 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
11923 _("'APSR', 'CPSR' or 'SPSR' expected"));
11925 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11926 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
11927 inst
.instruction
|= 0xf0000;
11937 if (do_vfp_nsyn_msr () == SUCCESS
)
11940 constraint (!inst
.operands
[1].isreg
,
11941 _("Thumb encoding does not support an immediate here"));
11943 if (inst
.operands
[0].isreg
)
11944 flags
= (int)(inst
.operands
[0].reg
);
11946 flags
= inst
.operands
[0].imm
;
11948 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11950 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11952 /* PR gas/12698: The constraint is only applied for m_profile.
11953 If the user has specified -march=all, we want to ignore it as
11954 we are building for any CPU type, including non-m variants. */
11955 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11956 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11957 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11958 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11959 && bits
!= PSR_f
)) && m_profile
,
11960 _("selected processor does not support requested special "
11961 "purpose register"));
11964 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11965 "requested special purpose register"));
11967 Rn
= inst
.operands
[1].reg
;
11968 reject_bad_reg (Rn
);
11970 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11971 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11972 inst
.instruction
|= (flags
& 0x300) >> 4;
11973 inst
.instruction
|= (flags
& 0xff);
11974 inst
.instruction
|= Rn
<< 16;
11980 bfd_boolean narrow
;
11981 unsigned Rd
, Rn
, Rm
;
11983 if (!inst
.operands
[2].present
)
11984 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11986 Rd
= inst
.operands
[0].reg
;
11987 Rn
= inst
.operands
[1].reg
;
11988 Rm
= inst
.operands
[2].reg
;
11990 if (unified_syntax
)
11992 if (inst
.size_req
== 4
11998 else if (inst
.instruction
== T_MNEM_muls
)
11999 narrow
= !in_it_block ();
12001 narrow
= in_it_block ();
12005 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12006 constraint (Rn
> 7 || Rm
> 7,
12013 /* 16-bit MULS/Conditional MUL. */
12014 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12015 inst
.instruction
|= Rd
;
12018 inst
.instruction
|= Rm
<< 3;
12020 inst
.instruction
|= Rn
<< 3;
12022 constraint (1, _("dest must overlap one source register"));
12026 constraint (inst
.instruction
!= T_MNEM_mul
,
12027 _("Thumb-2 MUL must not set flags"));
12029 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12030 inst
.instruction
|= Rd
<< 8;
12031 inst
.instruction
|= Rn
<< 16;
12032 inst
.instruction
|= Rm
<< 0;
12034 reject_bad_reg (Rd
);
12035 reject_bad_reg (Rn
);
12036 reject_bad_reg (Rm
);
12043 unsigned RdLo
, RdHi
, Rn
, Rm
;
12045 RdLo
= inst
.operands
[0].reg
;
12046 RdHi
= inst
.operands
[1].reg
;
12047 Rn
= inst
.operands
[2].reg
;
12048 Rm
= inst
.operands
[3].reg
;
12050 reject_bad_reg (RdLo
);
12051 reject_bad_reg (RdHi
);
12052 reject_bad_reg (Rn
);
12053 reject_bad_reg (Rm
);
12055 inst
.instruction
|= RdLo
<< 12;
12056 inst
.instruction
|= RdHi
<< 8;
12057 inst
.instruction
|= Rn
<< 16;
12058 inst
.instruction
|= Rm
;
12061 as_tsktsk (_("rdhi and rdlo must be different"));
12067 set_it_insn_type (NEUTRAL_IT_INSN
);
12069 if (unified_syntax
)
12071 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12073 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12074 inst
.instruction
|= inst
.operands
[0].imm
;
12078 /* PR9722: Check for Thumb2 availability before
12079 generating a thumb2 nop instruction. */
12080 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12082 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12083 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12086 inst
.instruction
= 0x46c0;
12091 constraint (inst
.operands
[0].present
,
12092 _("Thumb does not support NOP with hints"));
12093 inst
.instruction
= 0x46c0;
12100 if (unified_syntax
)
12102 bfd_boolean narrow
;
12104 if (THUMB_SETS_FLAGS (inst
.instruction
))
12105 narrow
= !in_it_block ();
12107 narrow
= in_it_block ();
12108 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12110 if (inst
.size_req
== 4)
12115 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12116 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12117 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12121 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12122 inst
.instruction
|= inst
.operands
[0].reg
;
12123 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12128 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12130 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12132 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12133 inst
.instruction
|= inst
.operands
[0].reg
;
12134 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12143 Rd
= inst
.operands
[0].reg
;
12144 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12146 reject_bad_reg (Rd
);
12147 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12148 reject_bad_reg (Rn
);
12150 inst
.instruction
|= Rd
<< 8;
12151 inst
.instruction
|= Rn
<< 16;
12153 if (!inst
.operands
[2].isreg
)
12155 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12156 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12162 Rm
= inst
.operands
[2].reg
;
12163 reject_bad_reg (Rm
);
12165 constraint (inst
.operands
[2].shifted
12166 && inst
.operands
[2].immisreg
,
12167 _("shift must be constant"));
12168 encode_thumb32_shifted_operand (2);
12175 unsigned Rd
, Rn
, Rm
;
12177 Rd
= inst
.operands
[0].reg
;
12178 Rn
= inst
.operands
[1].reg
;
12179 Rm
= inst
.operands
[2].reg
;
12181 reject_bad_reg (Rd
);
12182 reject_bad_reg (Rn
);
12183 reject_bad_reg (Rm
);
12185 inst
.instruction
|= Rd
<< 8;
12186 inst
.instruction
|= Rn
<< 16;
12187 inst
.instruction
|= Rm
;
12188 if (inst
.operands
[3].present
)
12190 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12191 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12192 _("expression too complex"));
12193 inst
.instruction
|= (val
& 0x1c) << 10;
12194 inst
.instruction
|= (val
& 0x03) << 6;
12201 if (!inst
.operands
[3].present
)
12205 inst
.instruction
&= ~0x00000020;
12207 /* PR 10168. Swap the Rm and Rn registers. */
12208 Rtmp
= inst
.operands
[1].reg
;
12209 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12210 inst
.operands
[2].reg
= Rtmp
;
12218 if (inst
.operands
[0].immisreg
)
12219 reject_bad_reg (inst
.operands
[0].imm
);
12221 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12225 do_t_push_pop (void)
12229 constraint (inst
.operands
[0].writeback
,
12230 _("push/pop do not support {reglist}^"));
12231 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12232 _("expression too complex"));
12234 mask
= inst
.operands
[0].imm
;
12235 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12236 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12237 else if (inst
.size_req
!= 4
12238 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12239 ? REG_LR
: REG_PC
)))
12241 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12242 inst
.instruction
|= THUMB_PP_PC_LR
;
12243 inst
.instruction
|= mask
& 0xff;
12245 else if (unified_syntax
)
12247 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12248 encode_thumb2_ldmstm (13, mask
, TRUE
);
12252 inst
.error
= _("invalid register list to push/pop instruction");
12262 Rd
= inst
.operands
[0].reg
;
12263 Rm
= inst
.operands
[1].reg
;
12265 reject_bad_reg (Rd
);
12266 reject_bad_reg (Rm
);
12268 inst
.instruction
|= Rd
<< 8;
12269 inst
.instruction
|= Rm
<< 16;
12270 inst
.instruction
|= Rm
;
12278 Rd
= inst
.operands
[0].reg
;
12279 Rm
= inst
.operands
[1].reg
;
12281 reject_bad_reg (Rd
);
12282 reject_bad_reg (Rm
);
12284 if (Rd
<= 7 && Rm
<= 7
12285 && inst
.size_req
!= 4)
12287 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12288 inst
.instruction
|= Rd
;
12289 inst
.instruction
|= Rm
<< 3;
12291 else if (unified_syntax
)
12293 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12294 inst
.instruction
|= Rd
<< 8;
12295 inst
.instruction
|= Rm
<< 16;
12296 inst
.instruction
|= Rm
;
12299 inst
.error
= BAD_HIREG
;
12307 Rd
= inst
.operands
[0].reg
;
12308 Rm
= inst
.operands
[1].reg
;
12310 reject_bad_reg (Rd
);
12311 reject_bad_reg (Rm
);
12313 inst
.instruction
|= Rd
<< 8;
12314 inst
.instruction
|= Rm
;
12322 Rd
= inst
.operands
[0].reg
;
12323 Rs
= (inst
.operands
[1].present
12324 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12325 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12327 reject_bad_reg (Rd
);
12328 reject_bad_reg (Rs
);
12329 if (inst
.operands
[2].isreg
)
12330 reject_bad_reg (inst
.operands
[2].reg
);
12332 inst
.instruction
|= Rd
<< 8;
12333 inst
.instruction
|= Rs
<< 16;
12334 if (!inst
.operands
[2].isreg
)
12336 bfd_boolean narrow
;
12338 if ((inst
.instruction
& 0x00100000) != 0)
12339 narrow
= !in_it_block ();
12341 narrow
= in_it_block ();
12343 if (Rd
> 7 || Rs
> 7)
12346 if (inst
.size_req
== 4 || !unified_syntax
)
12349 if (inst
.reloc
.exp
.X_op
!= O_constant
12350 || inst
.reloc
.exp
.X_add_number
!= 0)
12353 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12354 relaxation, but it doesn't seem worth the hassle. */
12357 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12358 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12359 inst
.instruction
|= Rs
<< 3;
12360 inst
.instruction
|= Rd
;
12364 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12365 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12369 encode_thumb32_shifted_operand (2);
12375 if (warn_on_deprecated
12376 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12377 as_warn (_("setend use is deprecated for ARMv8"));
12379 set_it_insn_type (OUTSIDE_IT_INSN
);
12380 if (inst
.operands
[0].imm
)
12381 inst
.instruction
|= 0x8;
12387 if (!inst
.operands
[1].present
)
12388 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12390 if (unified_syntax
)
12392 bfd_boolean narrow
;
12395 switch (inst
.instruction
)
12398 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12400 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12402 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12404 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12408 if (THUMB_SETS_FLAGS (inst
.instruction
))
12409 narrow
= !in_it_block ();
12411 narrow
= in_it_block ();
12412 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12414 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12416 if (inst
.operands
[2].isreg
12417 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12418 || inst
.operands
[2].reg
> 7))
12420 if (inst
.size_req
== 4)
12423 reject_bad_reg (inst
.operands
[0].reg
);
12424 reject_bad_reg (inst
.operands
[1].reg
);
12428 if (inst
.operands
[2].isreg
)
12430 reject_bad_reg (inst
.operands
[2].reg
);
12431 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12432 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12433 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12434 inst
.instruction
|= inst
.operands
[2].reg
;
12436 /* PR 12854: Error on extraneous shifts. */
12437 constraint (inst
.operands
[2].shifted
,
12438 _("extraneous shift as part of operand to shift insn"));
12442 inst
.operands
[1].shifted
= 1;
12443 inst
.operands
[1].shift_kind
= shift_kind
;
12444 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12445 ? T_MNEM_movs
: T_MNEM_mov
);
12446 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12447 encode_thumb32_shifted_operand (1);
12448 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12449 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12454 if (inst
.operands
[2].isreg
)
12456 switch (shift_kind
)
12458 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12459 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12460 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12461 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12465 inst
.instruction
|= inst
.operands
[0].reg
;
12466 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12468 /* PR 12854: Error on extraneous shifts. */
12469 constraint (inst
.operands
[2].shifted
,
12470 _("extraneous shift as part of operand to shift insn"));
12474 switch (shift_kind
)
12476 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12477 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12478 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12481 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12482 inst
.instruction
|= inst
.operands
[0].reg
;
12483 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12489 constraint (inst
.operands
[0].reg
> 7
12490 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12491 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12493 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12495 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12496 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12497 _("source1 and dest must be same register"));
12499 switch (inst
.instruction
)
12501 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12502 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12503 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12504 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12508 inst
.instruction
|= inst
.operands
[0].reg
;
12509 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12511 /* PR 12854: Error on extraneous shifts. */
12512 constraint (inst
.operands
[2].shifted
,
12513 _("extraneous shift as part of operand to shift insn"));
12517 switch (inst
.instruction
)
12519 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12520 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12521 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12522 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12525 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12526 inst
.instruction
|= inst
.operands
[0].reg
;
12527 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12535 unsigned Rd
, Rn
, Rm
;
12537 Rd
= inst
.operands
[0].reg
;
12538 Rn
= inst
.operands
[1].reg
;
12539 Rm
= inst
.operands
[2].reg
;
12541 reject_bad_reg (Rd
);
12542 reject_bad_reg (Rn
);
12543 reject_bad_reg (Rm
);
12545 inst
.instruction
|= Rd
<< 8;
12546 inst
.instruction
|= Rn
<< 16;
12547 inst
.instruction
|= Rm
;
12553 unsigned Rd
, Rn
, Rm
;
12555 Rd
= inst
.operands
[0].reg
;
12556 Rm
= inst
.operands
[1].reg
;
12557 Rn
= inst
.operands
[2].reg
;
12559 reject_bad_reg (Rd
);
12560 reject_bad_reg (Rn
);
12561 reject_bad_reg (Rm
);
12563 inst
.instruction
|= Rd
<< 8;
12564 inst
.instruction
|= Rn
<< 16;
12565 inst
.instruction
|= Rm
;
12571 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12572 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12573 _("SMC is not permitted on this architecture"));
12574 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12575 _("expression too complex"));
12576 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12577 inst
.instruction
|= (value
& 0xf000) >> 12;
12578 inst
.instruction
|= (value
& 0x0ff0);
12579 inst
.instruction
|= (value
& 0x000f) << 16;
12580 /* PR gas/15623: SMC instructions must be last in an IT block. */
12581 set_it_insn_type_last ();
12587 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12589 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12590 inst
.instruction
|= (value
& 0x0fff);
12591 inst
.instruction
|= (value
& 0xf000) << 4;
12595 do_t_ssat_usat (int bias
)
12599 Rd
= inst
.operands
[0].reg
;
12600 Rn
= inst
.operands
[2].reg
;
12602 reject_bad_reg (Rd
);
12603 reject_bad_reg (Rn
);
12605 inst
.instruction
|= Rd
<< 8;
12606 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12607 inst
.instruction
|= Rn
<< 16;
12609 if (inst
.operands
[3].present
)
12611 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12613 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12615 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12616 _("expression too complex"));
12618 if (shift_amount
!= 0)
12620 constraint (shift_amount
> 31,
12621 _("shift expression is too large"));
12623 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12624 inst
.instruction
|= 0x00200000; /* sh bit. */
12626 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12627 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12635 do_t_ssat_usat (1);
12643 Rd
= inst
.operands
[0].reg
;
12644 Rn
= inst
.operands
[2].reg
;
12646 reject_bad_reg (Rd
);
12647 reject_bad_reg (Rn
);
12649 inst
.instruction
|= Rd
<< 8;
12650 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12651 inst
.instruction
|= Rn
<< 16;
12657 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12658 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12659 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12660 || inst
.operands
[2].negative
,
12663 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12665 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12666 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12667 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12668 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12674 if (!inst
.operands
[2].present
)
12675 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12677 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12678 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12679 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12682 inst
.instruction
|= inst
.operands
[0].reg
;
12683 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12684 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12685 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12691 unsigned Rd
, Rn
, Rm
;
12693 Rd
= inst
.operands
[0].reg
;
12694 Rn
= inst
.operands
[1].reg
;
12695 Rm
= inst
.operands
[2].reg
;
12697 reject_bad_reg (Rd
);
12698 reject_bad_reg (Rn
);
12699 reject_bad_reg (Rm
);
12701 inst
.instruction
|= Rd
<< 8;
12702 inst
.instruction
|= Rn
<< 16;
12703 inst
.instruction
|= Rm
;
12704 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12712 Rd
= inst
.operands
[0].reg
;
12713 Rm
= inst
.operands
[1].reg
;
12715 reject_bad_reg (Rd
);
12716 reject_bad_reg (Rm
);
12718 if (inst
.instruction
<= 0xffff
12719 && inst
.size_req
!= 4
12720 && Rd
<= 7 && Rm
<= 7
12721 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12723 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12724 inst
.instruction
|= Rd
;
12725 inst
.instruction
|= Rm
<< 3;
12727 else if (unified_syntax
)
12729 if (inst
.instruction
<= 0xffff)
12730 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12731 inst
.instruction
|= Rd
<< 8;
12732 inst
.instruction
|= Rm
;
12733 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12737 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12738 _("Thumb encoding does not support rotation"));
12739 constraint (1, BAD_HIREG
);
12746 /* We have to do the following check manually as ARM_EXT_OS only applies
12748 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12750 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12751 /* This only applies to the v6m howver, not later architectures. */
12752 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12753 as_bad (_("SVC is not permitted on this architecture"));
12754 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12757 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12766 half
= (inst
.instruction
& 0x10) != 0;
12767 set_it_insn_type_last ();
12768 constraint (inst
.operands
[0].immisreg
,
12769 _("instruction requires register index"));
12771 Rn
= inst
.operands
[0].reg
;
12772 Rm
= inst
.operands
[0].imm
;
12774 constraint (Rn
== REG_SP
, BAD_SP
);
12775 reject_bad_reg (Rm
);
12777 constraint (!half
&& inst
.operands
[0].shifted
,
12778 _("instruction does not allow shifted index"));
12779 inst
.instruction
|= (Rn
<< 16) | Rm
;
12785 if (!inst
.operands
[0].present
)
12786 inst
.operands
[0].imm
= 0;
12788 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
12790 constraint (inst
.size_req
== 2,
12791 _("immediate value out of range"));
12792 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12793 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
12794 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
12798 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12799 inst
.instruction
|= inst
.operands
[0].imm
;
12802 set_it_insn_type (NEUTRAL_IT_INSN
);
12809 do_t_ssat_usat (0);
12817 Rd
= inst
.operands
[0].reg
;
12818 Rn
= inst
.operands
[2].reg
;
12820 reject_bad_reg (Rd
);
12821 reject_bad_reg (Rn
);
12823 inst
.instruction
|= Rd
<< 8;
12824 inst
.instruction
|= inst
.operands
[1].imm
;
12825 inst
.instruction
|= Rn
<< 16;
12828 /* Neon instruction encoder helpers. */
12830 /* Encodings for the different types for various Neon opcodes. */
12832 /* An "invalid" code for the following tables. */
12835 struct neon_tab_entry
12838 unsigned float_or_poly
;
12839 unsigned scalar_or_imm
;
12842 /* Map overloaded Neon opcodes to their respective encodings. */
12843 #define NEON_ENC_TAB \
12844 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12845 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12846 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12847 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12848 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12849 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12850 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12851 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12852 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12853 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12854 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12855 /* Register variants of the following two instructions are encoded as
12856 vcge / vcgt with the operands reversed. */ \
12857 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12858 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12859 X(vfma, N_INV, 0x0000c10, N_INV), \
12860 X(vfms, N_INV, 0x0200c10, N_INV), \
12861 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12862 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12863 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12864 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12865 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12866 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12867 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12868 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12869 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12870 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12871 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12872 X(vshl, 0x0000400, N_INV, 0x0800510), \
12873 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12874 X(vand, 0x0000110, N_INV, 0x0800030), \
12875 X(vbic, 0x0100110, N_INV, 0x0800030), \
12876 X(veor, 0x1000110, N_INV, N_INV), \
12877 X(vorn, 0x0300110, N_INV, 0x0800010), \
12878 X(vorr, 0x0200110, N_INV, 0x0800010), \
12879 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12880 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12881 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12882 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12883 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12884 X(vst1, 0x0000000, 0x0800000, N_INV), \
12885 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12886 X(vst2, 0x0000100, 0x0800100, N_INV), \
12887 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12888 X(vst3, 0x0000200, 0x0800200, N_INV), \
12889 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12890 X(vst4, 0x0000300, 0x0800300, N_INV), \
12891 X(vmovn, 0x1b20200, N_INV, N_INV), \
12892 X(vtrn, 0x1b20080, N_INV, N_INV), \
12893 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12894 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12895 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12896 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12897 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12898 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12899 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12900 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12901 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12902 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12903 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12904 X(vseleq, 0xe000a00, N_INV, N_INV), \
12905 X(vselvs, 0xe100a00, N_INV, N_INV), \
12906 X(vselge, 0xe200a00, N_INV, N_INV), \
12907 X(vselgt, 0xe300a00, N_INV, N_INV), \
12908 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12909 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12910 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12911 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12912 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12913 X(aes, 0x3b00300, N_INV, N_INV), \
12914 X(sha3op, 0x2000c00, N_INV, N_INV), \
12915 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12916 X(sha2op, 0x3ba0380, N_INV, N_INV)
12920 #define X(OPC,I,F,S) N_MNEM_##OPC
12925 static const struct neon_tab_entry neon_enc_tab
[] =
12927 #define X(OPC,I,F,S) { (I), (F), (S) }
12932 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12933 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12934 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12935 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12936 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12937 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12938 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12939 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12940 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12941 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12942 #define NEON_ENC_SINGLE_(X) \
12943 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12944 #define NEON_ENC_DOUBLE_(X) \
12945 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12946 #define NEON_ENC_FPV8_(X) \
12947 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12949 #define NEON_ENCODE(type, inst) \
12952 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12953 inst.is_neon = 1; \
12957 #define check_neon_suffixes \
12960 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12962 as_bad (_("invalid neon suffix for non neon instruction")); \
12968 /* Define shapes for instruction operands. The following mnemonic characters
12969 are used in this table:
12971 F - VFP S<n> register
12972 D - Neon D<n> register
12973 Q - Neon Q<n> register
12977 L - D<n> register list
12979 This table is used to generate various data:
12980 - enumerations of the form NS_DDR to be used as arguments to
12982 - a table classifying shapes into single, double, quad, mixed.
12983 - a table used to drive neon_select_shape. */
12985 #define NEON_SHAPE_DEF \
12986 X(3, (D, D, D), DOUBLE), \
12987 X(3, (Q, Q, Q), QUAD), \
12988 X(3, (D, D, I), DOUBLE), \
12989 X(3, (Q, Q, I), QUAD), \
12990 X(3, (D, D, S), DOUBLE), \
12991 X(3, (Q, Q, S), QUAD), \
12992 X(2, (D, D), DOUBLE), \
12993 X(2, (Q, Q), QUAD), \
12994 X(2, (D, S), DOUBLE), \
12995 X(2, (Q, S), QUAD), \
12996 X(2, (D, R), DOUBLE), \
12997 X(2, (Q, R), QUAD), \
12998 X(2, (D, I), DOUBLE), \
12999 X(2, (Q, I), QUAD), \
13000 X(3, (D, L, D), DOUBLE), \
13001 X(2, (D, Q), MIXED), \
13002 X(2, (Q, D), MIXED), \
13003 X(3, (D, Q, I), MIXED), \
13004 X(3, (Q, D, I), MIXED), \
13005 X(3, (Q, D, D), MIXED), \
13006 X(3, (D, Q, Q), MIXED), \
13007 X(3, (Q, Q, D), MIXED), \
13008 X(3, (Q, D, S), MIXED), \
13009 X(3, (D, Q, S), MIXED), \
13010 X(4, (D, D, D, I), DOUBLE), \
13011 X(4, (Q, Q, Q, I), QUAD), \
13012 X(2, (F, F), SINGLE), \
13013 X(3, (F, F, F), SINGLE), \
13014 X(2, (F, I), SINGLE), \
13015 X(2, (F, D), MIXED), \
13016 X(2, (D, F), MIXED), \
13017 X(3, (F, F, I), MIXED), \
13018 X(4, (R, R, F, F), SINGLE), \
13019 X(4, (F, F, R, R), SINGLE), \
13020 X(3, (D, R, R), DOUBLE), \
13021 X(3, (R, R, D), DOUBLE), \
13022 X(2, (S, R), SINGLE), \
13023 X(2, (R, S), SINGLE), \
13024 X(2, (F, R), SINGLE), \
13025 X(2, (R, F), SINGLE)
13027 #define S2(A,B) NS_##A##B
13028 #define S3(A,B,C) NS_##A##B##C
13029 #define S4(A,B,C,D) NS_##A##B##C##D
13031 #define X(N, L, C) S##N L
13044 enum neon_shape_class
13052 #define X(N, L, C) SC_##C
13054 static enum neon_shape_class neon_shape_class
[] =
13072 /* Register widths of above. */
13073 static unsigned neon_shape_el_size
[] =
13084 struct neon_shape_info
13087 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13090 #define S2(A,B) { SE_##A, SE_##B }
13091 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13092 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13094 #define X(N, L, C) { N, S##N L }
13096 static struct neon_shape_info neon_shape_tab
[] =
13106 /* Bit masks used in type checking given instructions.
13107 'N_EQK' means the type must be the same as (or based on in some way) the key
13108 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13109 set, various other bits can be set as well in order to modify the meaning of
13110 the type constraint. */
13112 enum neon_type_mask
13136 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13137 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13138 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13139 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13140 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13141 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13142 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13143 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13144 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13145 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13146 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13148 N_MAX_NONSPECIAL
= N_P64
13151 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13153 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13154 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13155 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13156 #define N_SUF_32 (N_SU_32 | N_F32)
13157 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13158 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13160 /* Pass this as the first type argument to neon_check_type to ignore types
13162 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13164 /* Select a "shape" for the current instruction (describing register types or
13165 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13166 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13167 function of operand parsing, so this function doesn't need to be called.
13168 Shapes should be listed in order of decreasing length. */
13170 static enum neon_shape
13171 neon_select_shape (enum neon_shape shape
, ...)
13174 enum neon_shape first_shape
= shape
;
13176 /* Fix missing optional operands. FIXME: we don't know at this point how
13177 many arguments we should have, so this makes the assumption that we have
13178 > 1. This is true of all current Neon opcodes, I think, but may not be
13179 true in the future. */
13180 if (!inst
.operands
[1].present
)
13181 inst
.operands
[1] = inst
.operands
[0];
13183 va_start (ap
, shape
);
13185 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13190 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13192 if (!inst
.operands
[j
].present
)
13198 switch (neon_shape_tab
[shape
].el
[j
])
13201 if (!(inst
.operands
[j
].isreg
13202 && inst
.operands
[j
].isvec
13203 && inst
.operands
[j
].issingle
13204 && !inst
.operands
[j
].isquad
))
13209 if (!(inst
.operands
[j
].isreg
13210 && inst
.operands
[j
].isvec
13211 && !inst
.operands
[j
].isquad
13212 && !inst
.operands
[j
].issingle
))
13217 if (!(inst
.operands
[j
].isreg
13218 && !inst
.operands
[j
].isvec
))
13223 if (!(inst
.operands
[j
].isreg
13224 && inst
.operands
[j
].isvec
13225 && inst
.operands
[j
].isquad
13226 && !inst
.operands
[j
].issingle
))
13231 if (!(!inst
.operands
[j
].isreg
13232 && !inst
.operands
[j
].isscalar
))
13237 if (!(!inst
.operands
[j
].isreg
13238 && inst
.operands
[j
].isscalar
))
13248 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13249 /* We've matched all the entries in the shape table, and we don't
13250 have any left over operands which have not been matched. */
13256 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13257 first_error (_("invalid instruction shape"));
13262 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13263 means the Q bit should be set). */
13266 neon_quad (enum neon_shape shape
)
13268 return neon_shape_class
[shape
] == SC_QUAD
;
13272 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13275 /* Allow modification to be made to types which are constrained to be
13276 based on the key element, based on bits set alongside N_EQK. */
13277 if ((typebits
& N_EQK
) != 0)
13279 if ((typebits
& N_HLF
) != 0)
13281 else if ((typebits
& N_DBL
) != 0)
13283 if ((typebits
& N_SGN
) != 0)
13284 *g_type
= NT_signed
;
13285 else if ((typebits
& N_UNS
) != 0)
13286 *g_type
= NT_unsigned
;
13287 else if ((typebits
& N_INT
) != 0)
13288 *g_type
= NT_integer
;
13289 else if ((typebits
& N_FLT
) != 0)
13290 *g_type
= NT_float
;
13291 else if ((typebits
& N_SIZ
) != 0)
13292 *g_type
= NT_untyped
;
13296 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13297 operand type, i.e. the single type specified in a Neon instruction when it
13298 is the only one given. */
13300 static struct neon_type_el
13301 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13303 struct neon_type_el dest
= *key
;
13305 gas_assert ((thisarg
& N_EQK
) != 0);
13307 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13312 /* Convert Neon type and size into compact bitmask representation. */
13314 static enum neon_type_mask
13315 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13322 case 8: return N_8
;
13323 case 16: return N_16
;
13324 case 32: return N_32
;
13325 case 64: return N_64
;
13333 case 8: return N_I8
;
13334 case 16: return N_I16
;
13335 case 32: return N_I32
;
13336 case 64: return N_I64
;
13344 case 16: return N_F16
;
13345 case 32: return N_F32
;
13346 case 64: return N_F64
;
13354 case 8: return N_P8
;
13355 case 16: return N_P16
;
13356 case 64: return N_P64
;
13364 case 8: return N_S8
;
13365 case 16: return N_S16
;
13366 case 32: return N_S32
;
13367 case 64: return N_S64
;
13375 case 8: return N_U8
;
13376 case 16: return N_U16
;
13377 case 32: return N_U32
;
13378 case 64: return N_U64
;
13389 /* Convert compact Neon bitmask type representation to a type and size. Only
13390 handles the case where a single bit is set in the mask. */
13393 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13394 enum neon_type_mask mask
)
13396 if ((mask
& N_EQK
) != 0)
13399 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13401 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13403 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13405 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13410 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13412 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13413 *type
= NT_unsigned
;
13414 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13415 *type
= NT_integer
;
13416 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13417 *type
= NT_untyped
;
13418 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13420 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13428 /* Modify a bitmask of allowed types. This is only needed for type
13432 modify_types_allowed (unsigned allowed
, unsigned mods
)
13435 enum neon_el_type type
;
13441 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13443 if (el_type_of_type_chk (&type
, &size
,
13444 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13446 neon_modify_type_size (mods
, &type
, &size
);
13447 destmask
|= type_chk_of_el_type (type
, size
);
13454 /* Check type and return type classification.
13455 The manual states (paraphrase): If one datatype is given, it indicates the
13457 - the second operand, if there is one
13458 - the operand, if there is no second operand
13459 - the result, if there are no operands.
13460 This isn't quite good enough though, so we use a concept of a "key" datatype
13461 which is set on a per-instruction basis, which is the one which matters when
13462 only one data type is written.
13463 Note: this function has side-effects (e.g. filling in missing operands). All
13464 Neon instructions should call it before performing bit encoding. */
13466 static struct neon_type_el
13467 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13470 unsigned i
, pass
, key_el
= 0;
13471 unsigned types
[NEON_MAX_TYPE_ELS
];
13472 enum neon_el_type k_type
= NT_invtype
;
13473 unsigned k_size
= -1u;
13474 struct neon_type_el badtype
= {NT_invtype
, -1};
13475 unsigned key_allowed
= 0;
13477 /* Optional registers in Neon instructions are always (not) in operand 1.
13478 Fill in the missing operand here, if it was omitted. */
13479 if (els
> 1 && !inst
.operands
[1].present
)
13480 inst
.operands
[1] = inst
.operands
[0];
13482 /* Suck up all the varargs. */
13484 for (i
= 0; i
< els
; i
++)
13486 unsigned thisarg
= va_arg (ap
, unsigned);
13487 if (thisarg
== N_IGNORE_TYPE
)
13492 types
[i
] = thisarg
;
13493 if ((thisarg
& N_KEY
) != 0)
13498 if (inst
.vectype
.elems
> 0)
13499 for (i
= 0; i
< els
; i
++)
13500 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13502 first_error (_("types specified in both the mnemonic and operands"));
13506 /* Duplicate inst.vectype elements here as necessary.
13507 FIXME: No idea if this is exactly the same as the ARM assembler,
13508 particularly when an insn takes one register and one non-register
13510 if (inst
.vectype
.elems
== 1 && els
> 1)
13513 inst
.vectype
.elems
= els
;
13514 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13515 for (j
= 0; j
< els
; j
++)
13517 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13520 else if (inst
.vectype
.elems
== 0 && els
> 0)
13523 /* No types were given after the mnemonic, so look for types specified
13524 after each operand. We allow some flexibility here; as long as the
13525 "key" operand has a type, we can infer the others. */
13526 for (j
= 0; j
< els
; j
++)
13527 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13528 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13530 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13532 for (j
= 0; j
< els
; j
++)
13533 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13534 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13539 first_error (_("operand types can't be inferred"));
13543 else if (inst
.vectype
.elems
!= els
)
13545 first_error (_("type specifier has the wrong number of parts"));
13549 for (pass
= 0; pass
< 2; pass
++)
13551 for (i
= 0; i
< els
; i
++)
13553 unsigned thisarg
= types
[i
];
13554 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13555 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13556 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13557 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13559 /* Decay more-specific signed & unsigned types to sign-insensitive
13560 integer types if sign-specific variants are unavailable. */
13561 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13562 && (types_allowed
& N_SU_ALL
) == 0)
13563 g_type
= NT_integer
;
13565 /* If only untyped args are allowed, decay any more specific types to
13566 them. Some instructions only care about signs for some element
13567 sizes, so handle that properly. */
13568 if (((types_allowed
& N_UNT
) == 0)
13569 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13570 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13571 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13572 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13573 g_type
= NT_untyped
;
13577 if ((thisarg
& N_KEY
) != 0)
13581 key_allowed
= thisarg
& ~N_KEY
;
13586 if ((thisarg
& N_VFP
) != 0)
13588 enum neon_shape_el regshape
;
13589 unsigned regwidth
, match
;
13591 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13594 first_error (_("invalid instruction shape"));
13597 regshape
= neon_shape_tab
[ns
].el
[i
];
13598 regwidth
= neon_shape_el_size
[regshape
];
13600 /* In VFP mode, operands must match register widths. If we
13601 have a key operand, use its width, else use the width of
13602 the current operand. */
13608 if (regwidth
!= match
)
13610 first_error (_("operand size must match register width"));
13615 if ((thisarg
& N_EQK
) == 0)
13617 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13619 if ((given_type
& types_allowed
) == 0)
13621 first_error (_("bad type in Neon instruction"));
13627 enum neon_el_type mod_k_type
= k_type
;
13628 unsigned mod_k_size
= k_size
;
13629 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13630 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13632 first_error (_("inconsistent types in Neon instruction"));
13640 return inst
.vectype
.el
[key_el
];
13643 /* Neon-style VFP instruction forwarding. */
13645 /* Thumb VFP instructions have 0xE in the condition field. */
13648 do_vfp_cond_or_thumb (void)
13653 inst
.instruction
|= 0xe0000000;
13655 inst
.instruction
|= inst
.cond
<< 28;
13658 /* Look up and encode a simple mnemonic, for use as a helper function for the
13659 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13660 etc. It is assumed that operand parsing has already been done, and that the
13661 operands are in the form expected by the given opcode (this isn't necessarily
13662 the same as the form in which they were parsed, hence some massaging must
13663 take place before this function is called).
13664 Checks current arch version against that in the looked-up opcode. */
13667 do_vfp_nsyn_opcode (const char *opname
)
13669 const struct asm_opcode
*opcode
;
13671 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13676 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13677 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13684 inst
.instruction
= opcode
->tvalue
;
13685 opcode
->tencode ();
13689 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13690 opcode
->aencode ();
13695 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13697 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13702 do_vfp_nsyn_opcode ("fadds");
13704 do_vfp_nsyn_opcode ("fsubs");
13709 do_vfp_nsyn_opcode ("faddd");
13711 do_vfp_nsyn_opcode ("fsubd");
13715 /* Check operand types to see if this is a VFP instruction, and if so call
13719 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13721 enum neon_shape rs
;
13722 struct neon_type_el et
;
13727 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13728 et
= neon_check_type (2, rs
,
13729 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13733 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13734 et
= neon_check_type (3, rs
,
13735 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13742 if (et
.type
!= NT_invtype
)
13753 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13755 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13760 do_vfp_nsyn_opcode ("fmacs");
13762 do_vfp_nsyn_opcode ("fnmacs");
13767 do_vfp_nsyn_opcode ("fmacd");
13769 do_vfp_nsyn_opcode ("fnmacd");
13774 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13776 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13781 do_vfp_nsyn_opcode ("ffmas");
13783 do_vfp_nsyn_opcode ("ffnmas");
13788 do_vfp_nsyn_opcode ("ffmad");
13790 do_vfp_nsyn_opcode ("ffnmad");
13795 do_vfp_nsyn_mul (enum neon_shape rs
)
13798 do_vfp_nsyn_opcode ("fmuls");
13800 do_vfp_nsyn_opcode ("fmuld");
13804 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
13806 int is_neg
= (inst
.instruction
& 0x80) != 0;
13807 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
13812 do_vfp_nsyn_opcode ("fnegs");
13814 do_vfp_nsyn_opcode ("fabss");
13819 do_vfp_nsyn_opcode ("fnegd");
13821 do_vfp_nsyn_opcode ("fabsd");
13825 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13826 insns belong to Neon, and are handled elsewhere. */
13829 do_vfp_nsyn_ldm_stm (int is_dbmode
)
13831 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
13835 do_vfp_nsyn_opcode ("fldmdbs");
13837 do_vfp_nsyn_opcode ("fldmias");
13842 do_vfp_nsyn_opcode ("fstmdbs");
13844 do_vfp_nsyn_opcode ("fstmias");
13849 do_vfp_nsyn_sqrt (void)
13851 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13852 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13855 do_vfp_nsyn_opcode ("fsqrts");
13857 do_vfp_nsyn_opcode ("fsqrtd");
13861 do_vfp_nsyn_div (void)
13863 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13864 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13865 N_F32
| N_F64
| N_KEY
| N_VFP
);
13868 do_vfp_nsyn_opcode ("fdivs");
13870 do_vfp_nsyn_opcode ("fdivd");
13874 do_vfp_nsyn_nmul (void)
13876 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13877 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13878 N_F32
| N_F64
| N_KEY
| N_VFP
);
13882 NEON_ENCODE (SINGLE
, inst
);
13883 do_vfp_sp_dyadic ();
13887 NEON_ENCODE (DOUBLE
, inst
);
13888 do_vfp_dp_rd_rn_rm ();
13890 do_vfp_cond_or_thumb ();
13894 do_vfp_nsyn_cmp (void)
13896 if (inst
.operands
[1].isreg
)
13898 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13899 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13903 NEON_ENCODE (SINGLE
, inst
);
13904 do_vfp_sp_monadic ();
13908 NEON_ENCODE (DOUBLE
, inst
);
13909 do_vfp_dp_rd_rm ();
13914 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
13915 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
13917 switch (inst
.instruction
& 0x0fffffff)
13920 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
13923 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
13931 NEON_ENCODE (SINGLE
, inst
);
13932 do_vfp_sp_compare_z ();
13936 NEON_ENCODE (DOUBLE
, inst
);
13940 do_vfp_cond_or_thumb ();
13944 nsyn_insert_sp (void)
13946 inst
.operands
[1] = inst
.operands
[0];
13947 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
13948 inst
.operands
[0].reg
= REG_SP
;
13949 inst
.operands
[0].isreg
= 1;
13950 inst
.operands
[0].writeback
= 1;
13951 inst
.operands
[0].present
= 1;
13955 do_vfp_nsyn_push (void)
13958 if (inst
.operands
[1].issingle
)
13959 do_vfp_nsyn_opcode ("fstmdbs");
13961 do_vfp_nsyn_opcode ("fstmdbd");
13965 do_vfp_nsyn_pop (void)
13968 if (inst
.operands
[1].issingle
)
13969 do_vfp_nsyn_opcode ("fldmias");
13971 do_vfp_nsyn_opcode ("fldmiad");
13974 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13975 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13978 neon_dp_fixup (struct arm_it
* insn
)
13980 unsigned int i
= insn
->instruction
;
13985 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13996 insn
->instruction
= i
;
13999 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14003 neon_logbits (unsigned x
)
14005 return ffs (x
) - 4;
14008 #define LOW4(R) ((R) & 0xf)
14009 #define HI1(R) (((R) >> 4) & 1)
14011 /* Encode insns with bit pattern:
14013 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14014 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14016 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14017 different meaning for some instruction. */
14020 neon_three_same (int isquad
, int ubit
, int size
)
14022 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14023 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14024 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14025 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14026 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14027 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14028 inst
.instruction
|= (isquad
!= 0) << 6;
14029 inst
.instruction
|= (ubit
!= 0) << 24;
14031 inst
.instruction
|= neon_logbits (size
) << 20;
14033 neon_dp_fixup (&inst
);
14036 /* Encode instructions of the form:
14038 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14039 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14041 Don't write size if SIZE == -1. */
14044 neon_two_same (int qbit
, int ubit
, int size
)
14046 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14047 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14048 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14049 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14050 inst
.instruction
|= (qbit
!= 0) << 6;
14051 inst
.instruction
|= (ubit
!= 0) << 24;
14054 inst
.instruction
|= neon_logbits (size
) << 18;
14056 neon_dp_fixup (&inst
);
14059 /* Neon instruction encoders, in approximate order of appearance. */
14062 do_neon_dyadic_i_su (void)
14064 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14065 struct neon_type_el et
= neon_check_type (3, rs
,
14066 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14067 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14071 do_neon_dyadic_i64_su (void)
14073 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14074 struct neon_type_el et
= neon_check_type (3, rs
,
14075 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14076 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14080 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14083 unsigned size
= et
.size
>> 3;
14084 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14085 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14086 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14087 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14088 inst
.instruction
|= (isquad
!= 0) << 6;
14089 inst
.instruction
|= immbits
<< 16;
14090 inst
.instruction
|= (size
>> 3) << 7;
14091 inst
.instruction
|= (size
& 0x7) << 19;
14093 inst
.instruction
|= (uval
!= 0) << 24;
14095 neon_dp_fixup (&inst
);
14099 do_neon_shl_imm (void)
14101 if (!inst
.operands
[2].isreg
)
14103 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14104 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14105 int imm
= inst
.operands
[2].imm
;
14107 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14108 _("immediate out of range for shift"));
14109 NEON_ENCODE (IMMED
, inst
);
14110 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14114 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14115 struct neon_type_el et
= neon_check_type (3, rs
,
14116 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14119 /* VSHL/VQSHL 3-register variants have syntax such as:
14121 whereas other 3-register operations encoded by neon_three_same have
14124 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14126 tmp
= inst
.operands
[2].reg
;
14127 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14128 inst
.operands
[1].reg
= tmp
;
14129 NEON_ENCODE (INTEGER
, inst
);
14130 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14135 do_neon_qshl_imm (void)
14137 if (!inst
.operands
[2].isreg
)
14139 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14140 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14141 int imm
= inst
.operands
[2].imm
;
14143 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14144 _("immediate out of range for shift"));
14145 NEON_ENCODE (IMMED
, inst
);
14146 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14150 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14151 struct neon_type_el et
= neon_check_type (3, rs
,
14152 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14155 /* See note in do_neon_shl_imm. */
14156 tmp
= inst
.operands
[2].reg
;
14157 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14158 inst
.operands
[1].reg
= tmp
;
14159 NEON_ENCODE (INTEGER
, inst
);
14160 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14165 do_neon_rshl (void)
14167 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14168 struct neon_type_el et
= neon_check_type (3, rs
,
14169 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14172 tmp
= inst
.operands
[2].reg
;
14173 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14174 inst
.operands
[1].reg
= tmp
;
14175 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14179 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14181 /* Handle .I8 pseudo-instructions. */
14184 /* Unfortunately, this will make everything apart from zero out-of-range.
14185 FIXME is this the intended semantics? There doesn't seem much point in
14186 accepting .I8 if so. */
14187 immediate
|= immediate
<< 8;
14193 if (immediate
== (immediate
& 0x000000ff))
14195 *immbits
= immediate
;
14198 else if (immediate
== (immediate
& 0x0000ff00))
14200 *immbits
= immediate
>> 8;
14203 else if (immediate
== (immediate
& 0x00ff0000))
14205 *immbits
= immediate
>> 16;
14208 else if (immediate
== (immediate
& 0xff000000))
14210 *immbits
= immediate
>> 24;
14213 if ((immediate
& 0xffff) != (immediate
>> 16))
14214 goto bad_immediate
;
14215 immediate
&= 0xffff;
14218 if (immediate
== (immediate
& 0x000000ff))
14220 *immbits
= immediate
;
14223 else if (immediate
== (immediate
& 0x0000ff00))
14225 *immbits
= immediate
>> 8;
14230 first_error (_("immediate value out of range"));
14235 do_neon_logic (void)
14237 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14239 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14240 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14241 /* U bit and size field were set as part of the bitmask. */
14242 NEON_ENCODE (INTEGER
, inst
);
14243 neon_three_same (neon_quad (rs
), 0, -1);
14247 const int three_ops_form
= (inst
.operands
[2].present
14248 && !inst
.operands
[2].isreg
);
14249 const int immoperand
= (three_ops_form
? 2 : 1);
14250 enum neon_shape rs
= (three_ops_form
14251 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14252 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14253 struct neon_type_el et
= neon_check_type (2, rs
,
14254 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14255 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14259 if (et
.type
== NT_invtype
)
14262 if (three_ops_form
)
14263 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14264 _("first and second operands shall be the same register"));
14266 NEON_ENCODE (IMMED
, inst
);
14268 immbits
= inst
.operands
[immoperand
].imm
;
14271 /* .i64 is a pseudo-op, so the immediate must be a repeating
14273 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14274 inst
.operands
[immoperand
].reg
: 0))
14276 /* Set immbits to an invalid constant. */
14277 immbits
= 0xdeadbeef;
14284 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14288 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14292 /* Pseudo-instruction for VBIC. */
14293 neon_invert_size (&immbits
, 0, et
.size
);
14294 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14298 /* Pseudo-instruction for VORR. */
14299 neon_invert_size (&immbits
, 0, et
.size
);
14300 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14310 inst
.instruction
|= neon_quad (rs
) << 6;
14311 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14312 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14313 inst
.instruction
|= cmode
<< 8;
14314 neon_write_immbits (immbits
);
14316 neon_dp_fixup (&inst
);
14321 do_neon_bitfield (void)
14323 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14324 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14325 neon_three_same (neon_quad (rs
), 0, -1);
14329 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14332 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14333 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14335 if (et
.type
== NT_float
)
14337 NEON_ENCODE (FLOAT
, inst
);
14338 neon_three_same (neon_quad (rs
), 0, -1);
14342 NEON_ENCODE (INTEGER
, inst
);
14343 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14348 do_neon_dyadic_if_su (void)
14350 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14354 do_neon_dyadic_if_su_d (void)
14356 /* This version only allow D registers, but that constraint is enforced during
14357 operand parsing so we don't need to do anything extra here. */
14358 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14362 do_neon_dyadic_if_i_d (void)
14364 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14365 affected if we specify unsigned args. */
14366 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14369 enum vfp_or_neon_is_neon_bits
14372 NEON_CHECK_ARCH
= 2,
14373 NEON_CHECK_ARCH8
= 4
14376 /* Call this function if an instruction which may have belonged to the VFP or
14377 Neon instruction sets, but turned out to be a Neon instruction (due to the
14378 operand types involved, etc.). We have to check and/or fix-up a couple of
14381 - Make sure the user hasn't attempted to make a Neon instruction
14383 - Alter the value in the condition code field if necessary.
14384 - Make sure that the arch supports Neon instructions.
14386 Which of these operations take place depends on bits from enum
14387 vfp_or_neon_is_neon_bits.
14389 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14390 current instruction's condition is COND_ALWAYS, the condition field is
14391 changed to inst.uncond_value. This is necessary because instructions shared
14392 between VFP and Neon may be conditional for the VFP variants only, and the
14393 unconditional Neon version must have, e.g., 0xF in the condition field. */
14396 vfp_or_neon_is_neon (unsigned check
)
14398 /* Conditions are always legal in Thumb mode (IT blocks). */
14399 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14401 if (inst
.cond
!= COND_ALWAYS
)
14403 first_error (_(BAD_COND
));
14406 if (inst
.uncond_value
!= -1)
14407 inst
.instruction
|= inst
.uncond_value
<< 28;
14410 if ((check
& NEON_CHECK_ARCH
)
14411 && !mark_feature_used (&fpu_neon_ext_v1
))
14413 first_error (_(BAD_FPU
));
14417 if ((check
& NEON_CHECK_ARCH8
)
14418 && !mark_feature_used (&fpu_neon_ext_armv8
))
14420 first_error (_(BAD_FPU
));
14428 do_neon_addsub_if_i (void)
14430 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14433 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14436 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14437 affected if we specify unsigned args. */
14438 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14441 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14443 V<op> A,B (A is operand 0, B is operand 2)
14448 so handle that case specially. */
14451 neon_exchange_operands (void)
14453 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14454 if (inst
.operands
[1].present
)
14456 /* Swap operands[1] and operands[2]. */
14457 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14458 inst
.operands
[1] = inst
.operands
[2];
14459 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14463 inst
.operands
[1] = inst
.operands
[2];
14464 inst
.operands
[2] = inst
.operands
[0];
14469 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14471 if (inst
.operands
[2].isreg
)
14474 neon_exchange_operands ();
14475 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14479 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14480 struct neon_type_el et
= neon_check_type (2, rs
,
14481 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14483 NEON_ENCODE (IMMED
, inst
);
14484 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14485 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14486 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14487 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14488 inst
.instruction
|= neon_quad (rs
) << 6;
14489 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14490 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14492 neon_dp_fixup (&inst
);
14499 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14503 do_neon_cmp_inv (void)
14505 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14511 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14514 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14515 scalars, which are encoded in 5 bits, M : Rm.
14516 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14517 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14521 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14523 unsigned regno
= NEON_SCALAR_REG (scalar
);
14524 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14529 if (regno
> 7 || elno
> 3)
14531 return regno
| (elno
<< 3);
14534 if (regno
> 15 || elno
> 1)
14536 return regno
| (elno
<< 4);
14540 first_error (_("scalar out of range for multiply instruction"));
14546 /* Encode multiply / multiply-accumulate scalar instructions. */
14549 neon_mul_mac (struct neon_type_el et
, int ubit
)
14553 /* Give a more helpful error message if we have an invalid type. */
14554 if (et
.type
== NT_invtype
)
14557 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14558 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14559 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14560 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14561 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14562 inst
.instruction
|= LOW4 (scalar
);
14563 inst
.instruction
|= HI1 (scalar
) << 5;
14564 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14565 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14566 inst
.instruction
|= (ubit
!= 0) << 24;
14568 neon_dp_fixup (&inst
);
14572 do_neon_mac_maybe_scalar (void)
14574 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14577 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14580 if (inst
.operands
[2].isscalar
)
14582 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14583 struct neon_type_el et
= neon_check_type (3, rs
,
14584 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14585 NEON_ENCODE (SCALAR
, inst
);
14586 neon_mul_mac (et
, neon_quad (rs
));
14590 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14591 affected if we specify unsigned args. */
14592 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14597 do_neon_fmac (void)
14599 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14602 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14605 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14611 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14612 struct neon_type_el et
= neon_check_type (3, rs
,
14613 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14614 neon_three_same (neon_quad (rs
), 0, et
.size
);
14617 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14618 same types as the MAC equivalents. The polynomial type for this instruction
14619 is encoded the same as the integer type. */
14624 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14627 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14630 if (inst
.operands
[2].isscalar
)
14631 do_neon_mac_maybe_scalar ();
14633 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14637 do_neon_qdmulh (void)
14639 if (inst
.operands
[2].isscalar
)
14641 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14642 struct neon_type_el et
= neon_check_type (3, rs
,
14643 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14644 NEON_ENCODE (SCALAR
, inst
);
14645 neon_mul_mac (et
, neon_quad (rs
));
14649 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14650 struct neon_type_el et
= neon_check_type (3, rs
,
14651 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14652 NEON_ENCODE (INTEGER
, inst
);
14653 /* The U bit (rounding) comes from bit mask. */
14654 neon_three_same (neon_quad (rs
), 0, et
.size
);
14659 do_neon_fcmp_absolute (void)
14661 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14662 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14663 /* Size field comes from bit mask. */
14664 neon_three_same (neon_quad (rs
), 1, -1);
14668 do_neon_fcmp_absolute_inv (void)
14670 neon_exchange_operands ();
14671 do_neon_fcmp_absolute ();
14675 do_neon_step (void)
14677 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14678 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14679 neon_three_same (neon_quad (rs
), 0, -1);
14683 do_neon_abs_neg (void)
14685 enum neon_shape rs
;
14686 struct neon_type_el et
;
14688 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14691 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14694 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14695 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14697 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14698 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14699 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14700 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14701 inst
.instruction
|= neon_quad (rs
) << 6;
14702 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14703 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14705 neon_dp_fixup (&inst
);
14711 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14712 struct neon_type_el et
= neon_check_type (2, rs
,
14713 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14714 int imm
= inst
.operands
[2].imm
;
14715 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14716 _("immediate out of range for insert"));
14717 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14723 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14724 struct neon_type_el et
= neon_check_type (2, rs
,
14725 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14726 int imm
= inst
.operands
[2].imm
;
14727 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14728 _("immediate out of range for insert"));
14729 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14733 do_neon_qshlu_imm (void)
14735 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14736 struct neon_type_el et
= neon_check_type (2, rs
,
14737 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14738 int imm
= inst
.operands
[2].imm
;
14739 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14740 _("immediate out of range for shift"));
14741 /* Only encodes the 'U present' variant of the instruction.
14742 In this case, signed types have OP (bit 8) set to 0.
14743 Unsigned types have OP set to 1. */
14744 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14745 /* The rest of the bits are the same as other immediate shifts. */
14746 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14750 do_neon_qmovn (void)
14752 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14753 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14754 /* Saturating move where operands can be signed or unsigned, and the
14755 destination has the same signedness. */
14756 NEON_ENCODE (INTEGER
, inst
);
14757 if (et
.type
== NT_unsigned
)
14758 inst
.instruction
|= 0xc0;
14760 inst
.instruction
|= 0x80;
14761 neon_two_same (0, 1, et
.size
/ 2);
14765 do_neon_qmovun (void)
14767 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14768 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14769 /* Saturating move with unsigned results. Operands must be signed. */
14770 NEON_ENCODE (INTEGER
, inst
);
14771 neon_two_same (0, 1, et
.size
/ 2);
14775 do_neon_rshift_sat_narrow (void)
14777 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14778 or unsigned. If operands are unsigned, results must also be unsigned. */
14779 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14780 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14781 int imm
= inst
.operands
[2].imm
;
14782 /* This gets the bounds check, size encoding and immediate bits calculation
14786 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14787 VQMOVN.I<size> <Dd>, <Qm>. */
14790 inst
.operands
[2].present
= 0;
14791 inst
.instruction
= N_MNEM_vqmovn
;
14796 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14797 _("immediate out of range"));
14798 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14802 do_neon_rshift_sat_narrow_u (void)
14804 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14805 or unsigned. If operands are unsigned, results must also be unsigned. */
14806 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14807 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14808 int imm
= inst
.operands
[2].imm
;
14809 /* This gets the bounds check, size encoding and immediate bits calculation
14813 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14814 VQMOVUN.I<size> <Dd>, <Qm>. */
14817 inst
.operands
[2].present
= 0;
14818 inst
.instruction
= N_MNEM_vqmovun
;
14823 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14824 _("immediate out of range"));
14825 /* FIXME: The manual is kind of unclear about what value U should have in
14826 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14828 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14832 do_neon_movn (void)
14834 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14835 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14836 NEON_ENCODE (INTEGER
, inst
);
14837 neon_two_same (0, 1, et
.size
/ 2);
14841 do_neon_rshift_narrow (void)
14843 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14844 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14845 int imm
= inst
.operands
[2].imm
;
14846 /* This gets the bounds check, size encoding and immediate bits calculation
14850 /* If immediate is zero then we are a pseudo-instruction for
14851 VMOVN.I<size> <Dd>, <Qm> */
14854 inst
.operands
[2].present
= 0;
14855 inst
.instruction
= N_MNEM_vmovn
;
14860 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14861 _("immediate out of range for narrowing operation"));
14862 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14866 do_neon_shll (void)
14868 /* FIXME: Type checking when lengthening. */
14869 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14870 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14871 unsigned imm
= inst
.operands
[2].imm
;
14873 if (imm
== et
.size
)
14875 /* Maximum shift variant. */
14876 NEON_ENCODE (INTEGER
, inst
);
14877 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14878 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14879 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14880 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14881 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14883 neon_dp_fixup (&inst
);
14887 /* A more-specific type check for non-max versions. */
14888 et
= neon_check_type (2, NS_QDI
,
14889 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14890 NEON_ENCODE (IMMED
, inst
);
14891 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14895 /* Check the various types for the VCVT instruction, and return which version
14896 the current instruction is. */
14898 #define CVT_FLAVOUR_VAR \
14899 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14900 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14901 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14902 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14903 /* Half-precision conversions. */ \
14904 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14905 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14906 /* VFP instructions. */ \
14907 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14908 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14909 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14910 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14911 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14912 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14913 /* VFP instructions with bitshift. */ \
14914 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14915 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14916 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14917 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14918 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14919 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14920 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14921 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14923 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14924 neon_cvt_flavour_##C,
14926 /* The different types of conversions we can do. */
14927 enum neon_cvt_flavour
14930 neon_cvt_flavour_invalid
,
14931 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
14936 static enum neon_cvt_flavour
14937 get_neon_cvt_flavour (enum neon_shape rs
)
14939 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14940 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14941 if (et.type != NT_invtype) \
14943 inst.error = NULL; \
14944 return (neon_cvt_flavour_##C); \
14947 struct neon_type_el et
;
14948 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14949 || rs
== NS_FF
) ? N_VFP
: 0;
14950 /* The instruction versions which take an immediate take one register
14951 argument, which is extended to the width of the full register. Thus the
14952 "source" and "destination" registers must have the same width. Hack that
14953 here by making the size equal to the key (wider, in this case) operand. */
14954 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14958 return neon_cvt_flavour_invalid
;
14973 /* Neon-syntax VFP conversions. */
14976 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
14978 const char *opname
= 0;
14980 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14982 /* Conversions with immediate bitshift. */
14983 const char *enc
[] =
14985 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14991 if (flavour
< (int) ARRAY_SIZE (enc
))
14993 opname
= enc
[flavour
];
14994 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14995 _("operands 0 and 1 must be the same register"));
14996 inst
.operands
[1] = inst
.operands
[2];
14997 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15002 /* Conversions without bitshift. */
15003 const char *enc
[] =
15005 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15011 if (flavour
< (int) ARRAY_SIZE (enc
))
15012 opname
= enc
[flavour
];
15016 do_vfp_nsyn_opcode (opname
);
15020 do_vfp_nsyn_cvtz (void)
15022 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
15023 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15024 const char *enc
[] =
15026 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15032 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15033 do_vfp_nsyn_opcode (enc
[flavour
]);
15037 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15038 enum neon_cvt_mode mode
)
15043 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15044 D register operands. */
15045 if (flavour
== neon_cvt_flavour_s32_f64
15046 || flavour
== neon_cvt_flavour_u32_f64
)
15047 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15050 set_it_insn_type (OUTSIDE_IT_INSN
);
15054 case neon_cvt_flavour_s32_f64
:
15058 case neon_cvt_flavour_s32_f32
:
15062 case neon_cvt_flavour_u32_f64
:
15066 case neon_cvt_flavour_u32_f32
:
15071 first_error (_("invalid instruction shape"));
15077 case neon_cvt_mode_a
: rm
= 0; break;
15078 case neon_cvt_mode_n
: rm
= 1; break;
15079 case neon_cvt_mode_p
: rm
= 2; break;
15080 case neon_cvt_mode_m
: rm
= 3; break;
15081 default: first_error (_("invalid rounding mode")); return;
15084 NEON_ENCODE (FPV8
, inst
);
15085 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15086 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15087 inst
.instruction
|= sz
<< 8;
15088 inst
.instruction
|= op
<< 7;
15089 inst
.instruction
|= rm
<< 16;
15090 inst
.instruction
|= 0xf0000000;
15091 inst
.is_neon
= TRUE
;
15095 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15097 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15098 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
15099 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15101 /* PR11109: Handle round-to-zero for VCVT conversions. */
15102 if (mode
== neon_cvt_mode_z
15103 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15104 && (flavour
== neon_cvt_flavour_s32_f32
15105 || flavour
== neon_cvt_flavour_u32_f32
15106 || flavour
== neon_cvt_flavour_s32_f64
15107 || flavour
== neon_cvt_flavour_u32_f64
)
15108 && (rs
== NS_FD
|| rs
== NS_FF
))
15110 do_vfp_nsyn_cvtz ();
15114 /* VFP rather than Neon conversions. */
15115 if (flavour
>= neon_cvt_flavour_first_fp
)
15117 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15118 do_vfp_nsyn_cvt (rs
, flavour
);
15120 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15131 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15133 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15136 /* Fixed-point conversion with #0 immediate is encoded as an
15137 integer conversion. */
15138 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15140 immbits
= 32 - inst
.operands
[2].imm
;
15141 NEON_ENCODE (IMMED
, inst
);
15142 if (flavour
!= neon_cvt_flavour_invalid
)
15143 inst
.instruction
|= enctab
[flavour
];
15144 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15145 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15146 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15147 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15148 inst
.instruction
|= neon_quad (rs
) << 6;
15149 inst
.instruction
|= 1 << 21;
15150 inst
.instruction
|= immbits
<< 16;
15152 neon_dp_fixup (&inst
);
15158 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15160 NEON_ENCODE (FLOAT
, inst
);
15161 set_it_insn_type (OUTSIDE_IT_INSN
);
15163 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15166 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15167 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15168 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15169 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15170 inst
.instruction
|= neon_quad (rs
) << 6;
15171 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
15172 inst
.instruction
|= mode
<< 8;
15174 inst
.instruction
|= 0xfc000000;
15176 inst
.instruction
|= 0xf0000000;
15182 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
15184 NEON_ENCODE (INTEGER
, inst
);
15186 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15189 if (flavour
!= neon_cvt_flavour_invalid
)
15190 inst
.instruction
|= enctab
[flavour
];
15192 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15193 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15194 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15195 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15196 inst
.instruction
|= neon_quad (rs
) << 6;
15197 inst
.instruction
|= 2 << 18;
15199 neon_dp_fixup (&inst
);
15204 /* Half-precision conversions for Advanced SIMD -- neon. */
15209 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15211 as_bad (_("operand size must match register width"));
15216 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15218 as_bad (_("operand size must match register width"));
15223 inst
.instruction
= 0x3b60600;
15225 inst
.instruction
= 0x3b60700;
15227 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15228 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15229 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15230 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15231 neon_dp_fixup (&inst
);
15235 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15236 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15237 do_vfp_nsyn_cvt (rs
, flavour
);
15239 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15244 do_neon_cvtr (void)
15246 do_neon_cvt_1 (neon_cvt_mode_x
);
15252 do_neon_cvt_1 (neon_cvt_mode_z
);
15256 do_neon_cvta (void)
15258 do_neon_cvt_1 (neon_cvt_mode_a
);
15262 do_neon_cvtn (void)
15264 do_neon_cvt_1 (neon_cvt_mode_n
);
15268 do_neon_cvtp (void)
15270 do_neon_cvt_1 (neon_cvt_mode_p
);
15274 do_neon_cvtm (void)
15276 do_neon_cvt_1 (neon_cvt_mode_m
);
15280 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15283 mark_feature_used (&fpu_vfp_ext_armv8
);
15285 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15286 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15287 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15288 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15289 inst
.instruction
|= to
? 0x10000 : 0;
15290 inst
.instruction
|= t
? 0x80 : 0;
15291 inst
.instruction
|= is_double
? 0x100 : 0;
15292 do_vfp_cond_or_thumb ();
15296 do_neon_cvttb_1 (bfd_boolean t
)
15298 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15302 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15305 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15307 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15310 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15312 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15314 /* The VCVTB and VCVTT instructions with D-register operands
15315 don't work for SP only targets. */
15316 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15320 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15322 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15324 /* The VCVTB and VCVTT instructions with D-register operands
15325 don't work for SP only targets. */
15326 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15330 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15337 do_neon_cvtb (void)
15339 do_neon_cvttb_1 (FALSE
);
15344 do_neon_cvtt (void)
15346 do_neon_cvttb_1 (TRUE
);
15350 neon_move_immediate (void)
15352 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15353 struct neon_type_el et
= neon_check_type (2, rs
,
15354 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15355 unsigned immlo
, immhi
= 0, immbits
;
15356 int op
, cmode
, float_p
;
15358 constraint (et
.type
== NT_invtype
,
15359 _("operand size must be specified for immediate VMOV"));
15361 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15362 op
= (inst
.instruction
& (1 << 5)) != 0;
15364 immlo
= inst
.operands
[1].imm
;
15365 if (inst
.operands
[1].regisimm
)
15366 immhi
= inst
.operands
[1].reg
;
15368 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15369 _("immediate has bits set outside the operand size"));
15371 float_p
= inst
.operands
[1].immisfloat
;
15373 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15374 et
.size
, et
.type
)) == FAIL
)
15376 /* Invert relevant bits only. */
15377 neon_invert_size (&immlo
, &immhi
, et
.size
);
15378 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15379 with one or the other; those cases are caught by
15380 neon_cmode_for_move_imm. */
15382 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15383 &op
, et
.size
, et
.type
)) == FAIL
)
15385 first_error (_("immediate out of range"));
15390 inst
.instruction
&= ~(1 << 5);
15391 inst
.instruction
|= op
<< 5;
15393 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15394 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15395 inst
.instruction
|= neon_quad (rs
) << 6;
15396 inst
.instruction
|= cmode
<< 8;
15398 neon_write_immbits (immbits
);
15404 if (inst
.operands
[1].isreg
)
15406 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15408 NEON_ENCODE (INTEGER
, inst
);
15409 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15410 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15411 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15412 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15413 inst
.instruction
|= neon_quad (rs
) << 6;
15417 NEON_ENCODE (IMMED
, inst
);
15418 neon_move_immediate ();
15421 neon_dp_fixup (&inst
);
15424 /* Encode instructions of form:
15426 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15427 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15430 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15432 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15433 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15434 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15435 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15436 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15437 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15438 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15439 inst
.instruction
|= neon_logbits (size
) << 20;
15441 neon_dp_fixup (&inst
);
15445 do_neon_dyadic_long (void)
15447 /* FIXME: Type checking for lengthening op. */
15448 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15449 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15450 neon_mixed_length (et
, et
.size
);
15454 do_neon_abal (void)
15456 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15457 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15458 neon_mixed_length (et
, et
.size
);
15462 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15464 if (inst
.operands
[2].isscalar
)
15466 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15467 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15468 NEON_ENCODE (SCALAR
, inst
);
15469 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15473 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15474 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15475 NEON_ENCODE (INTEGER
, inst
);
15476 neon_mixed_length (et
, et
.size
);
15481 do_neon_mac_maybe_scalar_long (void)
15483 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15487 do_neon_dyadic_wide (void)
15489 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15490 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15491 neon_mixed_length (et
, et
.size
);
15495 do_neon_dyadic_narrow (void)
15497 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15498 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15499 /* Operand sign is unimportant, and the U bit is part of the opcode,
15500 so force the operand type to integer. */
15501 et
.type
= NT_integer
;
15502 neon_mixed_length (et
, et
.size
/ 2);
15506 do_neon_mul_sat_scalar_long (void)
15508 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15512 do_neon_vmull (void)
15514 if (inst
.operands
[2].isscalar
)
15515 do_neon_mac_maybe_scalar_long ();
15518 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15519 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15521 if (et
.type
== NT_poly
)
15522 NEON_ENCODE (POLY
, inst
);
15524 NEON_ENCODE (INTEGER
, inst
);
15526 /* For polynomial encoding the U bit must be zero, and the size must
15527 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15528 obviously, as 0b10). */
15531 /* Check we're on the correct architecture. */
15532 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15534 _("Instruction form not available on this architecture.");
15539 neon_mixed_length (et
, et
.size
);
15546 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15547 struct neon_type_el et
= neon_check_type (3, rs
,
15548 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15549 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15551 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15552 _("shift out of range"));
15553 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15554 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15555 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15556 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15557 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15558 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15559 inst
.instruction
|= neon_quad (rs
) << 6;
15560 inst
.instruction
|= imm
<< 8;
15562 neon_dp_fixup (&inst
);
15568 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15569 struct neon_type_el et
= neon_check_type (2, rs
,
15570 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15571 unsigned op
= (inst
.instruction
>> 7) & 3;
15572 /* N (width of reversed regions) is encoded as part of the bitmask. We
15573 extract it here to check the elements to be reversed are smaller.
15574 Otherwise we'd get a reserved instruction. */
15575 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15576 gas_assert (elsize
!= 0);
15577 constraint (et
.size
>= elsize
,
15578 _("elements must be smaller than reversal region"));
15579 neon_two_same (neon_quad (rs
), 1, et
.size
);
15585 if (inst
.operands
[1].isscalar
)
15587 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15588 struct neon_type_el et
= neon_check_type (2, rs
,
15589 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15590 unsigned sizebits
= et
.size
>> 3;
15591 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15592 int logsize
= neon_logbits (et
.size
);
15593 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15595 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15598 NEON_ENCODE (SCALAR
, inst
);
15599 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15600 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15601 inst
.instruction
|= LOW4 (dm
);
15602 inst
.instruction
|= HI1 (dm
) << 5;
15603 inst
.instruction
|= neon_quad (rs
) << 6;
15604 inst
.instruction
|= x
<< 17;
15605 inst
.instruction
|= sizebits
<< 16;
15607 neon_dp_fixup (&inst
);
15611 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15612 struct neon_type_el et
= neon_check_type (2, rs
,
15613 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15614 /* Duplicate ARM register to lanes of vector. */
15615 NEON_ENCODE (ARMREG
, inst
);
15618 case 8: inst
.instruction
|= 0x400000; break;
15619 case 16: inst
.instruction
|= 0x000020; break;
15620 case 32: inst
.instruction
|= 0x000000; break;
15623 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15624 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15625 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15626 inst
.instruction
|= neon_quad (rs
) << 21;
15627 /* The encoding for this instruction is identical for the ARM and Thumb
15628 variants, except for the condition field. */
15629 do_vfp_cond_or_thumb ();
15633 /* VMOV has particularly many variations. It can be one of:
15634 0. VMOV<c><q> <Qd>, <Qm>
15635 1. VMOV<c><q> <Dd>, <Dm>
15636 (Register operations, which are VORR with Rm = Rn.)
15637 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15638 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15640 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15641 (ARM register to scalar.)
15642 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15643 (Two ARM registers to vector.)
15644 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15645 (Scalar to ARM register.)
15646 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15647 (Vector to two ARM registers.)
15648 8. VMOV.F32 <Sd>, <Sm>
15649 9. VMOV.F64 <Dd>, <Dm>
15650 (VFP register moves.)
15651 10. VMOV.F32 <Sd>, #imm
15652 11. VMOV.F64 <Dd>, #imm
15653 (VFP float immediate load.)
15654 12. VMOV <Rd>, <Sm>
15655 (VFP single to ARM reg.)
15656 13. VMOV <Sd>, <Rm>
15657 (ARM reg to VFP single.)
15658 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15659 (Two ARM regs to two VFP singles.)
15660 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15661 (Two VFP singles to two ARM regs.)
15663 These cases can be disambiguated using neon_select_shape, except cases 1/9
15664 and 3/11 which depend on the operand type too.
15666 All the encoded bits are hardcoded by this function.
15668 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15669 Cases 5, 7 may be used with VFPv2 and above.
15671 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15672 can specify a type where it doesn't make sense to, and is ignored). */
15677 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15678 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15680 struct neon_type_el et
;
15681 const char *ldconst
= 0;
15685 case NS_DD
: /* case 1/9. */
15686 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15687 /* It is not an error here if no type is given. */
15689 if (et
.type
== NT_float
&& et
.size
== 64)
15691 do_vfp_nsyn_opcode ("fcpyd");
15694 /* fall through. */
15696 case NS_QQ
: /* case 0/1. */
15698 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15700 /* The architecture manual I have doesn't explicitly state which
15701 value the U bit should have for register->register moves, but
15702 the equivalent VORR instruction has U = 0, so do that. */
15703 inst
.instruction
= 0x0200110;
15704 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15705 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15706 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15707 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15708 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15709 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15710 inst
.instruction
|= neon_quad (rs
) << 6;
15712 neon_dp_fixup (&inst
);
15716 case NS_DI
: /* case 3/11. */
15717 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15719 if (et
.type
== NT_float
&& et
.size
== 64)
15721 /* case 11 (fconstd). */
15722 ldconst
= "fconstd";
15723 goto encode_fconstd
;
15725 /* fall through. */
15727 case NS_QI
: /* case 2/3. */
15728 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15730 inst
.instruction
= 0x0800010;
15731 neon_move_immediate ();
15732 neon_dp_fixup (&inst
);
15735 case NS_SR
: /* case 4. */
15737 unsigned bcdebits
= 0;
15739 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15740 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15742 /* .<size> is optional here, defaulting to .32. */
15743 if (inst
.vectype
.elems
== 0
15744 && inst
.operands
[0].vectype
.type
== NT_invtype
15745 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15747 inst
.vectype
.el
[0].type
= NT_untyped
;
15748 inst
.vectype
.el
[0].size
= 32;
15749 inst
.vectype
.elems
= 1;
15752 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15753 logsize
= neon_logbits (et
.size
);
15755 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15757 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15758 && et
.size
!= 32, _(BAD_FPU
));
15759 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15760 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15764 case 8: bcdebits
= 0x8; break;
15765 case 16: bcdebits
= 0x1; break;
15766 case 32: bcdebits
= 0x0; break;
15770 bcdebits
|= x
<< logsize
;
15772 inst
.instruction
= 0xe000b10;
15773 do_vfp_cond_or_thumb ();
15774 inst
.instruction
|= LOW4 (dn
) << 16;
15775 inst
.instruction
|= HI1 (dn
) << 7;
15776 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15777 inst
.instruction
|= (bcdebits
& 3) << 5;
15778 inst
.instruction
|= (bcdebits
>> 2) << 21;
15782 case NS_DRR
: /* case 5 (fmdrr). */
15783 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15786 inst
.instruction
= 0xc400b10;
15787 do_vfp_cond_or_thumb ();
15788 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15789 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15790 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15791 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15794 case NS_RS
: /* case 6. */
15797 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15798 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
15799 unsigned abcdebits
= 0;
15801 /* .<dt> is optional here, defaulting to .32. */
15802 if (inst
.vectype
.elems
== 0
15803 && inst
.operands
[0].vectype
.type
== NT_invtype
15804 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15806 inst
.vectype
.el
[0].type
= NT_untyped
;
15807 inst
.vectype
.el
[0].size
= 32;
15808 inst
.vectype
.elems
= 1;
15811 et
= neon_check_type (2, NS_NULL
,
15812 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
15813 logsize
= neon_logbits (et
.size
);
15815 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15817 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15818 && et
.size
!= 32, _(BAD_FPU
));
15819 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15820 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15824 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
15825 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
15826 case 32: abcdebits
= 0x00; break;
15830 abcdebits
|= x
<< logsize
;
15831 inst
.instruction
= 0xe100b10;
15832 do_vfp_cond_or_thumb ();
15833 inst
.instruction
|= LOW4 (dn
) << 16;
15834 inst
.instruction
|= HI1 (dn
) << 7;
15835 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15836 inst
.instruction
|= (abcdebits
& 3) << 5;
15837 inst
.instruction
|= (abcdebits
>> 2) << 21;
15841 case NS_RRD
: /* case 7 (fmrrd). */
15842 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15845 inst
.instruction
= 0xc500b10;
15846 do_vfp_cond_or_thumb ();
15847 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15848 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15849 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15850 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15853 case NS_FF
: /* case 8 (fcpys). */
15854 do_vfp_nsyn_opcode ("fcpys");
15857 case NS_FI
: /* case 10 (fconsts). */
15858 ldconst
= "fconsts";
15860 if (is_quarter_float (inst
.operands
[1].imm
))
15862 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
15863 do_vfp_nsyn_opcode (ldconst
);
15866 first_error (_("immediate out of range"));
15869 case NS_RF
: /* case 12 (fmrs). */
15870 do_vfp_nsyn_opcode ("fmrs");
15873 case NS_FR
: /* case 13 (fmsr). */
15874 do_vfp_nsyn_opcode ("fmsr");
15877 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15878 (one of which is a list), but we have parsed four. Do some fiddling to
15879 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15881 case NS_RRFF
: /* case 14 (fmrrs). */
15882 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
15883 _("VFP registers must be adjacent"));
15884 inst
.operands
[2].imm
= 2;
15885 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15886 do_vfp_nsyn_opcode ("fmrrs");
15889 case NS_FFRR
: /* case 15 (fmsrr). */
15890 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
15891 _("VFP registers must be adjacent"));
15892 inst
.operands
[1] = inst
.operands
[2];
15893 inst
.operands
[2] = inst
.operands
[3];
15894 inst
.operands
[0].imm
= 2;
15895 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15896 do_vfp_nsyn_opcode ("fmsrr");
15900 /* neon_select_shape has determined that the instruction
15901 shape is wrong and has already set the error message. */
15910 do_neon_rshift_round_imm (void)
15912 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15913 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15914 int imm
= inst
.operands
[2].imm
;
15916 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15919 inst
.operands
[2].present
= 0;
15924 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15925 _("immediate out of range for shift"));
15926 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
15931 do_neon_movl (void)
15933 struct neon_type_el et
= neon_check_type (2, NS_QD
,
15934 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15935 unsigned sizebits
= et
.size
>> 3;
15936 inst
.instruction
|= sizebits
<< 19;
15937 neon_two_same (0, et
.type
== NT_unsigned
, -1);
15943 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15944 struct neon_type_el et
= neon_check_type (2, rs
,
15945 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15946 NEON_ENCODE (INTEGER
, inst
);
15947 neon_two_same (neon_quad (rs
), 1, et
.size
);
15951 do_neon_zip_uzp (void)
15953 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15954 struct neon_type_el et
= neon_check_type (2, rs
,
15955 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15956 if (rs
== NS_DD
&& et
.size
== 32)
15958 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15959 inst
.instruction
= N_MNEM_vtrn
;
15963 neon_two_same (neon_quad (rs
), 1, et
.size
);
15967 do_neon_sat_abs_neg (void)
15969 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15970 struct neon_type_el et
= neon_check_type (2, rs
,
15971 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15972 neon_two_same (neon_quad (rs
), 1, et
.size
);
15976 do_neon_pair_long (void)
15978 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15979 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
15980 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15981 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
15982 neon_two_same (neon_quad (rs
), 1, et
.size
);
15986 do_neon_recip_est (void)
15988 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15989 struct neon_type_el et
= neon_check_type (2, rs
,
15990 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
15991 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15992 neon_two_same (neon_quad (rs
), 1, et
.size
);
15998 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15999 struct neon_type_el et
= neon_check_type (2, rs
,
16000 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16001 neon_two_same (neon_quad (rs
), 1, et
.size
);
16007 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16008 struct neon_type_el et
= neon_check_type (2, rs
,
16009 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16010 neon_two_same (neon_quad (rs
), 1, et
.size
);
16016 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16017 struct neon_type_el et
= neon_check_type (2, rs
,
16018 N_EQK
| N_INT
, N_8
| N_KEY
);
16019 neon_two_same (neon_quad (rs
), 1, et
.size
);
16025 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16026 neon_two_same (neon_quad (rs
), 1, -1);
16030 do_neon_tbl_tbx (void)
16032 unsigned listlenbits
;
16033 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16035 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16037 first_error (_("bad list length for table lookup"));
16041 listlenbits
= inst
.operands
[1].imm
- 1;
16042 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16043 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16044 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16045 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16046 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16047 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16048 inst
.instruction
|= listlenbits
<< 8;
16050 neon_dp_fixup (&inst
);
16054 do_neon_ldm_stm (void)
16056 /* P, U and L bits are part of bitmask. */
16057 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16058 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16060 if (inst
.operands
[1].issingle
)
16062 do_vfp_nsyn_ldm_stm (is_dbmode
);
16066 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16067 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16069 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16070 _("register list must contain at least 1 and at most 16 "
16073 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16074 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16075 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16076 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16078 inst
.instruction
|= offsetbits
;
16080 do_vfp_cond_or_thumb ();
16084 do_neon_ldr_str (void)
16086 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16088 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16089 And is UNPREDICTABLE in thumb mode. */
16091 && inst
.operands
[1].reg
== REG_PC
16092 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16095 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16096 else if (warn_on_deprecated
)
16097 as_warn (_("Use of PC here is deprecated"));
16100 if (inst
.operands
[0].issingle
)
16103 do_vfp_nsyn_opcode ("flds");
16105 do_vfp_nsyn_opcode ("fsts");
16110 do_vfp_nsyn_opcode ("fldd");
16112 do_vfp_nsyn_opcode ("fstd");
16116 /* "interleave" version also handles non-interleaving register VLD1/VST1
16120 do_neon_ld_st_interleave (void)
16122 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16123 N_8
| N_16
| N_32
| N_64
);
16124 unsigned alignbits
= 0;
16126 /* The bits in this table go:
16127 0: register stride of one (0) or two (1)
16128 1,2: register list length, minus one (1, 2, 3, 4).
16129 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16130 We use -1 for invalid entries. */
16131 const int typetable
[] =
16133 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16134 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16135 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16136 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16140 if (et
.type
== NT_invtype
)
16143 if (inst
.operands
[1].immisalign
)
16144 switch (inst
.operands
[1].imm
>> 8)
16146 case 64: alignbits
= 1; break;
16148 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16149 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16150 goto bad_alignment
;
16154 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16155 goto bad_alignment
;
16160 first_error (_("bad alignment"));
16164 inst
.instruction
|= alignbits
<< 4;
16165 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16167 /* Bits [4:6] of the immediate in a list specifier encode register stride
16168 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16169 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16170 up the right value for "type" in a table based on this value and the given
16171 list style, then stick it back. */
16172 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16173 | (((inst
.instruction
>> 8) & 3) << 3);
16175 typebits
= typetable
[idx
];
16177 constraint (typebits
== -1, _("bad list type for instruction"));
16178 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16179 _("bad element type for instruction"));
16181 inst
.instruction
&= ~0xf00;
16182 inst
.instruction
|= typebits
<< 8;
16185 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16186 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16187 otherwise. The variable arguments are a list of pairs of legal (size, align)
16188 values, terminated with -1. */
16191 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
16194 int result
= FAIL
, thissize
, thisalign
;
16196 if (!inst
.operands
[1].immisalign
)
16202 va_start (ap
, do_align
);
16206 thissize
= va_arg (ap
, int);
16207 if (thissize
== -1)
16209 thisalign
= va_arg (ap
, int);
16211 if (size
== thissize
&& align
== thisalign
)
16214 while (result
!= SUCCESS
);
16218 if (result
== SUCCESS
)
16221 first_error (_("unsupported alignment for instruction"));
16227 do_neon_ld_st_lane (void)
16229 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16230 int align_good
, do_align
= 0;
16231 int logsize
= neon_logbits (et
.size
);
16232 int align
= inst
.operands
[1].imm
>> 8;
16233 int n
= (inst
.instruction
>> 8) & 3;
16234 int max_el
= 64 / et
.size
;
16236 if (et
.type
== NT_invtype
)
16239 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16240 _("bad list length"));
16241 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16242 _("scalar index out of range"));
16243 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16245 _("stride of 2 unavailable when element size is 8"));
16249 case 0: /* VLD1 / VST1. */
16250 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16252 if (align_good
== FAIL
)
16256 unsigned alignbits
= 0;
16259 case 16: alignbits
= 0x1; break;
16260 case 32: alignbits
= 0x3; break;
16263 inst
.instruction
|= alignbits
<< 4;
16267 case 1: /* VLD2 / VST2. */
16268 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16270 if (align_good
== FAIL
)
16273 inst
.instruction
|= 1 << 4;
16276 case 2: /* VLD3 / VST3. */
16277 constraint (inst
.operands
[1].immisalign
,
16278 _("can't use alignment with this instruction"));
16281 case 3: /* VLD4 / VST4. */
16282 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16283 16, 64, 32, 64, 32, 128, -1);
16284 if (align_good
== FAIL
)
16288 unsigned alignbits
= 0;
16291 case 8: alignbits
= 0x1; break;
16292 case 16: alignbits
= 0x1; break;
16293 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16296 inst
.instruction
|= alignbits
<< 4;
16303 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16304 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16305 inst
.instruction
|= 1 << (4 + logsize
);
16307 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16308 inst
.instruction
|= logsize
<< 10;
16311 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16314 do_neon_ld_dup (void)
16316 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16317 int align_good
, do_align
= 0;
16319 if (et
.type
== NT_invtype
)
16322 switch ((inst
.instruction
>> 8) & 3)
16324 case 0: /* VLD1. */
16325 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16326 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16327 &do_align
, 16, 16, 32, 32, -1);
16328 if (align_good
== FAIL
)
16330 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16333 case 2: inst
.instruction
|= 1 << 5; break;
16334 default: first_error (_("bad list length")); return;
16336 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16339 case 1: /* VLD2. */
16340 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16341 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16342 if (align_good
== FAIL
)
16344 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16345 _("bad list length"));
16346 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16347 inst
.instruction
|= 1 << 5;
16348 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16351 case 2: /* VLD3. */
16352 constraint (inst
.operands
[1].immisalign
,
16353 _("can't use alignment with this instruction"));
16354 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16355 _("bad list length"));
16356 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16357 inst
.instruction
|= 1 << 5;
16358 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16361 case 3: /* VLD4. */
16363 int align
= inst
.operands
[1].imm
>> 8;
16364 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16365 16, 64, 32, 64, 32, 128, -1);
16366 if (align_good
== FAIL
)
16368 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16369 _("bad list length"));
16370 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16371 inst
.instruction
|= 1 << 5;
16372 if (et
.size
== 32 && align
== 128)
16373 inst
.instruction
|= 0x3 << 6;
16375 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16382 inst
.instruction
|= do_align
<< 4;
16385 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16386 apart from bits [11:4]. */
16389 do_neon_ldx_stx (void)
16391 if (inst
.operands
[1].isreg
)
16392 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16394 switch (NEON_LANE (inst
.operands
[0].imm
))
16396 case NEON_INTERLEAVE_LANES
:
16397 NEON_ENCODE (INTERLV
, inst
);
16398 do_neon_ld_st_interleave ();
16401 case NEON_ALL_LANES
:
16402 NEON_ENCODE (DUP
, inst
);
16403 if (inst
.instruction
== N_INV
)
16405 first_error ("only loads support such operands");
16412 NEON_ENCODE (LANE
, inst
);
16413 do_neon_ld_st_lane ();
16416 /* L bit comes from bit mask. */
16417 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16418 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16419 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16421 if (inst
.operands
[1].postind
)
16423 int postreg
= inst
.operands
[1].imm
& 0xf;
16424 constraint (!inst
.operands
[1].immisreg
,
16425 _("post-index must be a register"));
16426 constraint (postreg
== 0xd || postreg
== 0xf,
16427 _("bad register for post-index"));
16428 inst
.instruction
|= postreg
;
16432 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16433 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16434 || inst
.reloc
.exp
.X_add_number
!= 0,
16437 if (inst
.operands
[1].writeback
)
16439 inst
.instruction
|= 0xd;
16442 inst
.instruction
|= 0xf;
16446 inst
.instruction
|= 0xf9000000;
16448 inst
.instruction
|= 0xf4000000;
16453 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16455 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16456 D register operands. */
16457 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16458 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16461 NEON_ENCODE (FPV8
, inst
);
16464 do_vfp_sp_dyadic ();
16466 do_vfp_dp_rd_rn_rm ();
16469 inst
.instruction
|= 0x100;
16471 inst
.instruction
|= 0xf0000000;
16477 set_it_insn_type (OUTSIDE_IT_INSN
);
16479 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16480 first_error (_("invalid instruction shape"));
16486 set_it_insn_type (OUTSIDE_IT_INSN
);
16488 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16491 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16494 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16498 do_vrint_1 (enum neon_cvt_mode mode
)
16500 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16501 struct neon_type_el et
;
16506 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16507 D register operands. */
16508 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16509 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16512 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16513 if (et
.type
!= NT_invtype
)
16515 /* VFP encodings. */
16516 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16517 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16518 set_it_insn_type (OUTSIDE_IT_INSN
);
16520 NEON_ENCODE (FPV8
, inst
);
16522 do_vfp_sp_monadic ();
16524 do_vfp_dp_rd_rm ();
16528 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16529 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16530 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16531 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16532 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16533 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16534 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16538 inst
.instruction
|= (rs
== NS_DD
) << 8;
16539 do_vfp_cond_or_thumb ();
16543 /* Neon encodings (or something broken...). */
16545 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16547 if (et
.type
== NT_invtype
)
16550 set_it_insn_type (OUTSIDE_IT_INSN
);
16551 NEON_ENCODE (FLOAT
, inst
);
16553 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16556 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16557 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16558 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16559 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16560 inst
.instruction
|= neon_quad (rs
) << 6;
16563 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16564 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16565 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16566 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16567 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16568 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16569 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16574 inst
.instruction
|= 0xfc000000;
16576 inst
.instruction
|= 0xf0000000;
16583 do_vrint_1 (neon_cvt_mode_x
);
16589 do_vrint_1 (neon_cvt_mode_z
);
16595 do_vrint_1 (neon_cvt_mode_r
);
16601 do_vrint_1 (neon_cvt_mode_a
);
16607 do_vrint_1 (neon_cvt_mode_n
);
16613 do_vrint_1 (neon_cvt_mode_p
);
16619 do_vrint_1 (neon_cvt_mode_m
);
16622 /* Crypto v1 instructions. */
16624 do_crypto_2op_1 (unsigned elttype
, int op
)
16626 set_it_insn_type (OUTSIDE_IT_INSN
);
16628 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16634 NEON_ENCODE (INTEGER
, inst
);
16635 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16636 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16637 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16638 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16640 inst
.instruction
|= op
<< 6;
16643 inst
.instruction
|= 0xfc000000;
16645 inst
.instruction
|= 0xf0000000;
16649 do_crypto_3op_1 (int u
, int op
)
16651 set_it_insn_type (OUTSIDE_IT_INSN
);
16653 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16654 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16659 NEON_ENCODE (INTEGER
, inst
);
16660 neon_three_same (1, u
, 8 << op
);
16666 do_crypto_2op_1 (N_8
, 0);
16672 do_crypto_2op_1 (N_8
, 1);
16678 do_crypto_2op_1 (N_8
, 2);
16684 do_crypto_2op_1 (N_8
, 3);
16690 do_crypto_3op_1 (0, 0);
16696 do_crypto_3op_1 (0, 1);
16702 do_crypto_3op_1 (0, 2);
16708 do_crypto_3op_1 (0, 3);
16714 do_crypto_3op_1 (1, 0);
16720 do_crypto_3op_1 (1, 1);
16724 do_sha256su1 (void)
16726 do_crypto_3op_1 (1, 2);
16732 do_crypto_2op_1 (N_32
, -1);
16738 do_crypto_2op_1 (N_32
, 0);
16742 do_sha256su0 (void)
16744 do_crypto_2op_1 (N_32
, 1);
16748 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16750 unsigned int Rd
= inst
.operands
[0].reg
;
16751 unsigned int Rn
= inst
.operands
[1].reg
;
16752 unsigned int Rm
= inst
.operands
[2].reg
;
16754 set_it_insn_type (OUTSIDE_IT_INSN
);
16755 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16756 inst
.instruction
|= LOW4 (Rn
) << 16;
16757 inst
.instruction
|= LOW4 (Rm
);
16758 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16759 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16761 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16762 as_warn (UNPRED_REG ("r15"));
16763 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16764 as_warn (UNPRED_REG ("r13"));
16804 /* Overall per-instruction processing. */
16806 /* We need to be able to fix up arbitrary expressions in some statements.
16807 This is so that we can handle symbols that are an arbitrary distance from
16808 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16809 which returns part of an address in a form which will be valid for
16810 a data instruction. We do this by pushing the expression into a symbol
16811 in the expr_section, and creating a fix for that. */
16814 fix_new_arm (fragS
* frag
,
16828 /* Create an absolute valued symbol, so we have something to
16829 refer to in the object file. Unfortunately for us, gas's
16830 generic expression parsing will already have folded out
16831 any use of .set foo/.type foo %function that may have
16832 been used to set type information of the target location,
16833 that's being specified symbolically. We have to presume
16834 the user knows what they are doing. */
16838 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
16840 symbol
= symbol_find_or_make (name
);
16841 S_SET_SEGMENT (symbol
, absolute_section
);
16842 symbol_set_frag (symbol
, &zero_address_frag
);
16843 S_SET_VALUE (symbol
, exp
->X_add_number
);
16844 exp
->X_op
= O_symbol
;
16845 exp
->X_add_symbol
= symbol
;
16846 exp
->X_add_number
= 0;
16852 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
16853 (enum bfd_reloc_code_real
) reloc
);
16857 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
16858 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
16862 /* Mark whether the fix is to a THUMB instruction, or an ARM
16864 new_fix
->tc_fix_data
= thumb_mode
;
16867 /* Create a frg for an instruction requiring relaxation. */
16869 output_relax_insn (void)
16875 /* The size of the instruction is unknown, so tie the debug info to the
16876 start of the instruction. */
16877 dwarf2_emit_insn (0);
16879 switch (inst
.reloc
.exp
.X_op
)
16882 sym
= inst
.reloc
.exp
.X_add_symbol
;
16883 offset
= inst
.reloc
.exp
.X_add_number
;
16887 offset
= inst
.reloc
.exp
.X_add_number
;
16890 sym
= make_expr_symbol (&inst
.reloc
.exp
);
16894 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
16895 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
16896 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
16899 /* Write a 32-bit thumb instruction to buf. */
16901 put_thumb32_insn (char * buf
, unsigned long insn
)
16903 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
16904 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
16908 output_inst (const char * str
)
16914 as_bad ("%s -- `%s'", inst
.error
, str
);
16919 output_relax_insn ();
16922 if (inst
.size
== 0)
16925 to
= frag_more (inst
.size
);
16926 /* PR 9814: Record the thumb mode into the current frag so that we know
16927 what type of NOP padding to use, if necessary. We override any previous
16928 setting so that if the mode has changed then the NOPS that we use will
16929 match the encoding of the last instruction in the frag. */
16930 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
16932 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
16934 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
16935 put_thumb32_insn (to
, inst
.instruction
);
16937 else if (inst
.size
> INSN_SIZE
)
16939 gas_assert (inst
.size
== (2 * INSN_SIZE
));
16940 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
16941 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
16944 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
16946 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
16947 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
16948 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
16951 dwarf2_emit_insn (inst
.size
);
16955 output_it_inst (int cond
, int mask
, char * to
)
16957 unsigned long instruction
= 0xbf00;
16960 instruction
|= mask
;
16961 instruction
|= cond
<< 4;
16965 to
= frag_more (2);
16967 dwarf2_emit_insn (2);
16971 md_number_to_chars (to
, instruction
, 2);
16976 /* Tag values used in struct asm_opcode's tag field. */
16979 OT_unconditional
, /* Instruction cannot be conditionalized.
16980 The ARM condition field is still 0xE. */
16981 OT_unconditionalF
, /* Instruction cannot be conditionalized
16982 and carries 0xF in its ARM condition field. */
16983 OT_csuffix
, /* Instruction takes a conditional suffix. */
16984 OT_csuffixF
, /* Some forms of the instruction take a conditional
16985 suffix, others place 0xF where the condition field
16987 OT_cinfix3
, /* Instruction takes a conditional infix,
16988 beginning at character index 3. (In
16989 unified mode, it becomes a suffix.) */
16990 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
16991 tsts, cmps, cmns, and teqs. */
16992 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
16993 character index 3, even in unified mode. Used for
16994 legacy instructions where suffix and infix forms
16995 may be ambiguous. */
16996 OT_csuf_or_in3
, /* Instruction takes either a conditional
16997 suffix or an infix at character index 3. */
16998 OT_odd_infix_unc
, /* This is the unconditional variant of an
16999 instruction that takes a conditional infix
17000 at an unusual position. In unified mode,
17001 this variant will accept a suffix. */
17002 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17003 are the conditional variants of instructions that
17004 take conditional infixes in unusual positions.
17005 The infix appears at character index
17006 (tag - OT_odd_infix_0). These are not accepted
17007 in unified mode. */
17010 /* Subroutine of md_assemble, responsible for looking up the primary
17011 opcode from the mnemonic the user wrote. STR points to the
17012 beginning of the mnemonic.
17014 This is not simply a hash table lookup, because of conditional
17015 variants. Most instructions have conditional variants, which are
17016 expressed with a _conditional affix_ to the mnemonic. If we were
17017 to encode each conditional variant as a literal string in the opcode
17018 table, it would have approximately 20,000 entries.
17020 Most mnemonics take this affix as a suffix, and in unified syntax,
17021 'most' is upgraded to 'all'. However, in the divided syntax, some
17022 instructions take the affix as an infix, notably the s-variants of
17023 the arithmetic instructions. Of those instructions, all but six
17024 have the infix appear after the third character of the mnemonic.
17026 Accordingly, the algorithm for looking up primary opcodes given
17029 1. Look up the identifier in the opcode table.
17030 If we find a match, go to step U.
17032 2. Look up the last two characters of the identifier in the
17033 conditions table. If we find a match, look up the first N-2
17034 characters of the identifier in the opcode table. If we
17035 find a match, go to step CE.
17037 3. Look up the fourth and fifth characters of the identifier in
17038 the conditions table. If we find a match, extract those
17039 characters from the identifier, and look up the remaining
17040 characters in the opcode table. If we find a match, go
17045 U. Examine the tag field of the opcode structure, in case this is
17046 one of the six instructions with its conditional infix in an
17047 unusual place. If it is, the tag tells us where to find the
17048 infix; look it up in the conditions table and set inst.cond
17049 accordingly. Otherwise, this is an unconditional instruction.
17050 Again set inst.cond accordingly. Return the opcode structure.
17052 CE. Examine the tag field to make sure this is an instruction that
17053 should receive a conditional suffix. If it is not, fail.
17054 Otherwise, set inst.cond from the suffix we already looked up,
17055 and return the opcode structure.
17057 CM. Examine the tag field to make sure this is an instruction that
17058 should receive a conditional infix after the third character.
17059 If it is not, fail. Otherwise, undo the edits to the current
17060 line of input and proceed as for case CE. */
17062 static const struct asm_opcode
*
17063 opcode_lookup (char **str
)
17067 const struct asm_opcode
*opcode
;
17068 const struct asm_cond
*cond
;
17071 /* Scan up to the end of the mnemonic, which must end in white space,
17072 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17073 for (base
= end
= *str
; *end
!= '\0'; end
++)
17074 if (*end
== ' ' || *end
== '.')
17080 /* Handle a possible width suffix and/or Neon type suffix. */
17085 /* The .w and .n suffixes are only valid if the unified syntax is in
17087 if (unified_syntax
&& end
[1] == 'w')
17089 else if (unified_syntax
&& end
[1] == 'n')
17094 inst
.vectype
.elems
= 0;
17096 *str
= end
+ offset
;
17098 if (end
[offset
] == '.')
17100 /* See if we have a Neon type suffix (possible in either unified or
17101 non-unified ARM syntax mode). */
17102 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17105 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17111 /* Look for unaffixed or special-case affixed mnemonic. */
17112 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17117 if (opcode
->tag
< OT_odd_infix_0
)
17119 inst
.cond
= COND_ALWAYS
;
17123 if (warn_on_deprecated
&& unified_syntax
)
17124 as_warn (_("conditional infixes are deprecated in unified syntax"));
17125 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17126 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17129 inst
.cond
= cond
->value
;
17133 /* Cannot have a conditional suffix on a mnemonic of less than two
17135 if (end
- base
< 3)
17138 /* Look for suffixed mnemonic. */
17140 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17141 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17143 if (opcode
&& cond
)
17146 switch (opcode
->tag
)
17148 case OT_cinfix3_legacy
:
17149 /* Ignore conditional suffixes matched on infix only mnemonics. */
17153 case OT_cinfix3_deprecated
:
17154 case OT_odd_infix_unc
:
17155 if (!unified_syntax
)
17157 /* else fall through */
17161 case OT_csuf_or_in3
:
17162 inst
.cond
= cond
->value
;
17165 case OT_unconditional
:
17166 case OT_unconditionalF
:
17168 inst
.cond
= cond
->value
;
17171 /* Delayed diagnostic. */
17172 inst
.error
= BAD_COND
;
17173 inst
.cond
= COND_ALWAYS
;
17182 /* Cannot have a usual-position infix on a mnemonic of less than
17183 six characters (five would be a suffix). */
17184 if (end
- base
< 6)
17187 /* Look for infixed mnemonic in the usual position. */
17189 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17193 memcpy (save
, affix
, 2);
17194 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17195 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17197 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17198 memcpy (affix
, save
, 2);
17201 && (opcode
->tag
== OT_cinfix3
17202 || opcode
->tag
== OT_cinfix3_deprecated
17203 || opcode
->tag
== OT_csuf_or_in3
17204 || opcode
->tag
== OT_cinfix3_legacy
))
17207 if (warn_on_deprecated
&& unified_syntax
17208 && (opcode
->tag
== OT_cinfix3
17209 || opcode
->tag
== OT_cinfix3_deprecated
))
17210 as_warn (_("conditional infixes are deprecated in unified syntax"));
17212 inst
.cond
= cond
->value
;
17219 /* This function generates an initial IT instruction, leaving its block
17220 virtually open for the new instructions. Eventually,
17221 the mask will be updated by now_it_add_mask () each time
17222 a new instruction needs to be included in the IT block.
17223 Finally, the block is closed with close_automatic_it_block ().
17224 The block closure can be requested either from md_assemble (),
17225 a tencode (), or due to a label hook. */
17228 new_automatic_it_block (int cond
)
17230 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17231 now_it
.mask
= 0x18;
17233 now_it
.block_length
= 1;
17234 mapping_state (MAP_THUMB
);
17235 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17236 now_it
.warn_deprecated
= FALSE
;
17237 now_it
.insn_cond
= TRUE
;
17240 /* Close an automatic IT block.
17241 See comments in new_automatic_it_block (). */
17244 close_automatic_it_block (void)
17246 now_it
.mask
= 0x10;
17247 now_it
.block_length
= 0;
17250 /* Update the mask of the current automatically-generated IT
17251 instruction. See comments in new_automatic_it_block (). */
17254 now_it_add_mask (int cond
)
17256 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17257 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17258 | ((bitvalue) << (nbit)))
17259 const int resulting_bit
= (cond
& 1);
17261 now_it
.mask
&= 0xf;
17262 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17264 (5 - now_it
.block_length
));
17265 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17267 ((5 - now_it
.block_length
) - 1) );
17268 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17271 #undef SET_BIT_VALUE
17274 /* The IT blocks handling machinery is accessed through the these functions:
17275 it_fsm_pre_encode () from md_assemble ()
17276 set_it_insn_type () optional, from the tencode functions
17277 set_it_insn_type_last () ditto
17278 in_it_block () ditto
17279 it_fsm_post_encode () from md_assemble ()
17280 force_automatic_it_block_close () from label habdling functions
17283 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17284 initializing the IT insn type with a generic initial value depending
17285 on the inst.condition.
17286 2) During the tencode function, two things may happen:
17287 a) The tencode function overrides the IT insn type by
17288 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17289 b) The tencode function queries the IT block state by
17290 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17292 Both set_it_insn_type and in_it_block run the internal FSM state
17293 handling function (handle_it_state), because: a) setting the IT insn
17294 type may incur in an invalid state (exiting the function),
17295 and b) querying the state requires the FSM to be updated.
17296 Specifically we want to avoid creating an IT block for conditional
17297 branches, so it_fsm_pre_encode is actually a guess and we can't
17298 determine whether an IT block is required until the tencode () routine
17299 has decided what type of instruction this actually it.
17300 Because of this, if set_it_insn_type and in_it_block have to be used,
17301 set_it_insn_type has to be called first.
17303 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17304 determines the insn IT type depending on the inst.cond code.
17305 When a tencode () routine encodes an instruction that can be
17306 either outside an IT block, or, in the case of being inside, has to be
17307 the last one, set_it_insn_type_last () will determine the proper
17308 IT instruction type based on the inst.cond code. Otherwise,
17309 set_it_insn_type can be called for overriding that logic or
17310 for covering other cases.
17312 Calling handle_it_state () may not transition the IT block state to
17313 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17314 still queried. Instead, if the FSM determines that the state should
17315 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17316 after the tencode () function: that's what it_fsm_post_encode () does.
17318 Since in_it_block () calls the state handling function to get an
17319 updated state, an error may occur (due to invalid insns combination).
17320 In that case, inst.error is set.
17321 Therefore, inst.error has to be checked after the execution of
17322 the tencode () routine.
17324 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17325 any pending state change (if any) that didn't take place in
17326 handle_it_state () as explained above. */
17329 it_fsm_pre_encode (void)
17331 if (inst
.cond
!= COND_ALWAYS
)
17332 inst
.it_insn_type
= INSIDE_IT_INSN
;
17334 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17336 now_it
.state_handled
= 0;
17339 /* IT state FSM handling function. */
17342 handle_it_state (void)
17344 now_it
.state_handled
= 1;
17345 now_it
.insn_cond
= FALSE
;
17347 switch (now_it
.state
)
17349 case OUTSIDE_IT_BLOCK
:
17350 switch (inst
.it_insn_type
)
17352 case OUTSIDE_IT_INSN
:
17355 case INSIDE_IT_INSN
:
17356 case INSIDE_IT_LAST_INSN
:
17357 if (thumb_mode
== 0)
17360 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17361 as_tsktsk (_("Warning: conditional outside an IT block"\
17366 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17367 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
17369 /* Automatically generate the IT instruction. */
17370 new_automatic_it_block (inst
.cond
);
17371 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17372 close_automatic_it_block ();
17376 inst
.error
= BAD_OUT_IT
;
17382 case IF_INSIDE_IT_LAST_INSN
:
17383 case NEUTRAL_IT_INSN
:
17387 now_it
.state
= MANUAL_IT_BLOCK
;
17388 now_it
.block_length
= 0;
17393 case AUTOMATIC_IT_BLOCK
:
17394 /* Three things may happen now:
17395 a) We should increment current it block size;
17396 b) We should close current it block (closing insn or 4 insns);
17397 c) We should close current it block and start a new one (due
17398 to incompatible conditions or
17399 4 insns-length block reached). */
17401 switch (inst
.it_insn_type
)
17403 case OUTSIDE_IT_INSN
:
17404 /* The closure of the block shall happen immediatelly,
17405 so any in_it_block () call reports the block as closed. */
17406 force_automatic_it_block_close ();
17409 case INSIDE_IT_INSN
:
17410 case INSIDE_IT_LAST_INSN
:
17411 case IF_INSIDE_IT_LAST_INSN
:
17412 now_it
.block_length
++;
17414 if (now_it
.block_length
> 4
17415 || !now_it_compatible (inst
.cond
))
17417 force_automatic_it_block_close ();
17418 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17419 new_automatic_it_block (inst
.cond
);
17423 now_it
.insn_cond
= TRUE
;
17424 now_it_add_mask (inst
.cond
);
17427 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17428 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17429 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17430 close_automatic_it_block ();
17433 case NEUTRAL_IT_INSN
:
17434 now_it
.block_length
++;
17435 now_it
.insn_cond
= TRUE
;
17437 if (now_it
.block_length
> 4)
17438 force_automatic_it_block_close ();
17440 now_it_add_mask (now_it
.cc
& 1);
17444 close_automatic_it_block ();
17445 now_it
.state
= MANUAL_IT_BLOCK
;
17450 case MANUAL_IT_BLOCK
:
17452 /* Check conditional suffixes. */
17453 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17456 now_it
.mask
&= 0x1f;
17457 is_last
= (now_it
.mask
== 0x10);
17458 now_it
.insn_cond
= TRUE
;
17460 switch (inst
.it_insn_type
)
17462 case OUTSIDE_IT_INSN
:
17463 inst
.error
= BAD_NOT_IT
;
17466 case INSIDE_IT_INSN
:
17467 if (cond
!= inst
.cond
)
17469 inst
.error
= BAD_IT_COND
;
17474 case INSIDE_IT_LAST_INSN
:
17475 case IF_INSIDE_IT_LAST_INSN
:
17476 if (cond
!= inst
.cond
)
17478 inst
.error
= BAD_IT_COND
;
17483 inst
.error
= BAD_BRANCH
;
17488 case NEUTRAL_IT_INSN
:
17489 /* The BKPT instruction is unconditional even in an IT block. */
17493 inst
.error
= BAD_IT_IT
;
17503 struct depr_insn_mask
17505 unsigned long pattern
;
17506 unsigned long mask
;
17507 const char* description
;
17510 /* List of 16-bit instruction patterns deprecated in an IT block in
17512 static const struct depr_insn_mask depr_it_insns
[] = {
17513 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17514 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17515 { 0xa000, 0xb800, N_("ADR") },
17516 { 0x4800, 0xf800, N_("Literal loads") },
17517 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17518 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17519 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17520 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17521 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
17526 it_fsm_post_encode (void)
17530 if (!now_it
.state_handled
)
17531 handle_it_state ();
17533 if (now_it
.insn_cond
17534 && !now_it
.warn_deprecated
17535 && warn_on_deprecated
17536 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17538 if (inst
.instruction
>= 0x10000)
17540 as_warn (_("IT blocks containing 32-bit Thumb instructions are "
17541 "deprecated in ARMv8"));
17542 now_it
.warn_deprecated
= TRUE
;
17546 const struct depr_insn_mask
*p
= depr_it_insns
;
17548 while (p
->mask
!= 0)
17550 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17552 as_warn (_("IT blocks containing 16-bit Thumb instructions "
17553 "of the following class are deprecated in ARMv8: "
17554 "%s"), p
->description
);
17555 now_it
.warn_deprecated
= TRUE
;
17563 if (now_it
.block_length
> 1)
17565 as_warn (_("IT blocks containing more than one conditional "
17566 "instruction are deprecated in ARMv8"));
17567 now_it
.warn_deprecated
= TRUE
;
17571 is_last
= (now_it
.mask
== 0x10);
17574 now_it
.state
= OUTSIDE_IT_BLOCK
;
17580 force_automatic_it_block_close (void)
17582 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17584 close_automatic_it_block ();
17585 now_it
.state
= OUTSIDE_IT_BLOCK
;
17593 if (!now_it
.state_handled
)
17594 handle_it_state ();
17596 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17600 md_assemble (char *str
)
17603 const struct asm_opcode
* opcode
;
17605 /* Align the previous label if needed. */
17606 if (last_label_seen
!= NULL
)
17608 symbol_set_frag (last_label_seen
, frag_now
);
17609 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17610 S_SET_SEGMENT (last_label_seen
, now_seg
);
17613 memset (&inst
, '\0', sizeof (inst
));
17614 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17616 opcode
= opcode_lookup (&p
);
17619 /* It wasn't an instruction, but it might be a register alias of
17620 the form alias .req reg, or a Neon .dn/.qn directive. */
17621 if (! create_register_alias (str
, p
)
17622 && ! create_neon_reg_alias (str
, p
))
17623 as_bad (_("bad instruction `%s'"), str
);
17628 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17629 as_warn (_("s suffix on comparison instruction is deprecated"));
17631 /* The value which unconditional instructions should have in place of the
17632 condition field. */
17633 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17637 arm_feature_set variant
;
17639 variant
= cpu_variant
;
17640 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17641 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17642 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17643 /* Check that this instruction is supported for this CPU. */
17644 if (!opcode
->tvariant
17645 || (thumb_mode
== 1
17646 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17648 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
17651 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17652 && opcode
->tencode
!= do_t_branch
)
17654 as_bad (_("Thumb does not support conditional execution"));
17658 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17660 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17661 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17662 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17664 /* Two things are addressed here.
17665 1) Implicit require narrow instructions on Thumb-1.
17666 This avoids relaxation accidentally introducing Thumb-2
17668 2) Reject wide instructions in non Thumb-2 cores. */
17669 if (inst
.size_req
== 0)
17671 else if (inst
.size_req
== 4)
17673 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
17679 inst
.instruction
= opcode
->tvalue
;
17681 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17683 /* Prepare the it_insn_type for those encodings that don't set
17685 it_fsm_pre_encode ();
17687 opcode
->tencode ();
17689 it_fsm_post_encode ();
17692 if (!(inst
.error
|| inst
.relax
))
17694 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17695 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17696 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17698 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17703 /* Something has gone badly wrong if we try to relax a fixed size
17705 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17707 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17708 *opcode
->tvariant
);
17709 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17710 set those bits when Thumb-2 32-bit instructions are seen. ie.
17711 anything other than bl/blx and v6-M instructions.
17712 The impact of relaxable instructions will be considered later after we
17713 finish all relaxation. */
17714 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17715 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17716 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17717 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17720 check_neon_suffixes
;
17724 mapping_state (MAP_THUMB
);
17727 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17731 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17732 is_bx
= (opcode
->aencode
== do_bx
);
17734 /* Check that this instruction is supported for this CPU. */
17735 if (!(is_bx
&& fix_v4bx
)
17736 && !(opcode
->avariant
&&
17737 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17739 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
17744 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17748 inst
.instruction
= opcode
->avalue
;
17749 if (opcode
->tag
== OT_unconditionalF
)
17750 inst
.instruction
|= 0xF << 28;
17752 inst
.instruction
|= inst
.cond
<< 28;
17753 inst
.size
= INSN_SIZE
;
17754 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17756 it_fsm_pre_encode ();
17757 opcode
->aencode ();
17758 it_fsm_post_encode ();
17760 /* Arm mode bx is marked as both v4T and v5 because it's still required
17761 on a hypothetical non-thumb v5 core. */
17763 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17765 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17766 *opcode
->avariant
);
17768 check_neon_suffixes
;
17772 mapping_state (MAP_ARM
);
17777 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17785 check_it_blocks_finished (void)
17790 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
17791 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
17792 == MANUAL_IT_BLOCK
)
17794 as_warn (_("section '%s' finished with an open IT block."),
17798 if (now_it
.state
== MANUAL_IT_BLOCK
)
17799 as_warn (_("file finished with an open IT block."));
17803 /* Various frobbings of labels and their addresses. */
17806 arm_start_line_hook (void)
17808 last_label_seen
= NULL
;
17812 arm_frob_label (symbolS
* sym
)
17814 last_label_seen
= sym
;
17816 ARM_SET_THUMB (sym
, thumb_mode
);
17818 #if defined OBJ_COFF || defined OBJ_ELF
17819 ARM_SET_INTERWORK (sym
, support_interwork
);
17822 force_automatic_it_block_close ();
17824 /* Note - do not allow local symbols (.Lxxx) to be labelled
17825 as Thumb functions. This is because these labels, whilst
17826 they exist inside Thumb code, are not the entry points for
17827 possible ARM->Thumb calls. Also, these labels can be used
17828 as part of a computed goto or switch statement. eg gcc
17829 can generate code that looks like this:
17831 ldr r2, [pc, .Laaa]
17841 The first instruction loads the address of the jump table.
17842 The second instruction converts a table index into a byte offset.
17843 The third instruction gets the jump address out of the table.
17844 The fourth instruction performs the jump.
17846 If the address stored at .Laaa is that of a symbol which has the
17847 Thumb_Func bit set, then the linker will arrange for this address
17848 to have the bottom bit set, which in turn would mean that the
17849 address computation performed by the third instruction would end
17850 up with the bottom bit set. Since the ARM is capable of unaligned
17851 word loads, the instruction would then load the incorrect address
17852 out of the jump table, and chaos would ensue. */
17853 if (label_is_thumb_function_name
17854 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
17855 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
17857 /* When the address of a Thumb function is taken the bottom
17858 bit of that address should be set. This will allow
17859 interworking between Arm and Thumb functions to work
17862 THUMB_SET_FUNC (sym
, 1);
17864 label_is_thumb_function_name
= FALSE
;
17867 dwarf2_emit_label (sym
);
17871 arm_data_in_code (void)
17873 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
17875 *input_line_pointer
= '/';
17876 input_line_pointer
+= 5;
17877 *input_line_pointer
= 0;
17885 arm_canonicalize_symbol_name (char * name
)
17889 if (thumb_mode
&& (len
= strlen (name
)) > 5
17890 && streq (name
+ len
- 5, "/data"))
17891 *(name
+ len
- 5) = 0;
17896 /* Table of all register names defined by default. The user can
17897 define additional names with .req. Note that all register names
17898 should appear in both upper and lowercase variants. Some registers
17899 also have mixed-case names. */
17901 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17902 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17903 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17904 #define REGSET(p,t) \
17905 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17906 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17907 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17908 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17909 #define REGSETH(p,t) \
17910 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17911 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17912 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17913 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17914 #define REGSET2(p,t) \
17915 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17916 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17917 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17918 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17919 #define SPLRBANK(base,bank,t) \
17920 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17921 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17922 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17923 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17924 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17925 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17927 static const struct reg_entry reg_names
[] =
17929 /* ARM integer registers. */
17930 REGSET(r
, RN
), REGSET(R
, RN
),
17932 /* ATPCS synonyms. */
17933 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
17934 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
17935 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
17937 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
17938 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
17939 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
17941 /* Well-known aliases. */
17942 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
17943 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
17945 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
17946 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
17948 /* Coprocessor numbers. */
17949 REGSET(p
, CP
), REGSET(P
, CP
),
17951 /* Coprocessor register numbers. The "cr" variants are for backward
17953 REGSET(c
, CN
), REGSET(C
, CN
),
17954 REGSET(cr
, CN
), REGSET(CR
, CN
),
17956 /* ARM banked registers. */
17957 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
17958 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
17959 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
17960 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
17961 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
17962 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
17963 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
17965 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
17966 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
17967 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
17968 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
17969 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
17970 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
17971 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
17972 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
17974 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
17975 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
17976 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
17977 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
17978 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
17979 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
17980 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
17981 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
17982 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
17984 /* FPA registers. */
17985 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
17986 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
17988 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
17989 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
17991 /* VFP SP registers. */
17992 REGSET(s
,VFS
), REGSET(S
,VFS
),
17993 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
17995 /* VFP DP Registers. */
17996 REGSET(d
,VFD
), REGSET(D
,VFD
),
17997 /* Extra Neon DP registers. */
17998 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18000 /* Neon QP registers. */
18001 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18003 /* VFP control registers. */
18004 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18005 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18006 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18007 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18008 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18009 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18011 /* Maverick DSP coprocessor registers. */
18012 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18013 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18015 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18016 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18017 REGDEF(dspsc
,0,DSPSC
),
18019 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18020 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18021 REGDEF(DSPSC
,0,DSPSC
),
18023 /* iWMMXt data registers - p0, c0-15. */
18024 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18026 /* iWMMXt control registers - p1, c0-3. */
18027 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18028 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18029 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18030 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18032 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18033 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18034 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18035 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18036 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18038 /* XScale accumulator registers. */
18039 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18045 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18046 within psr_required_here. */
18047 static const struct asm_psr psrs
[] =
18049 /* Backward compatibility notation. Note that "all" is no longer
18050 truly all possible PSR bits. */
18051 {"all", PSR_c
| PSR_f
},
18055 /* Individual flags. */
18061 /* Combinations of flags. */
18062 {"fs", PSR_f
| PSR_s
},
18063 {"fx", PSR_f
| PSR_x
},
18064 {"fc", PSR_f
| PSR_c
},
18065 {"sf", PSR_s
| PSR_f
},
18066 {"sx", PSR_s
| PSR_x
},
18067 {"sc", PSR_s
| PSR_c
},
18068 {"xf", PSR_x
| PSR_f
},
18069 {"xs", PSR_x
| PSR_s
},
18070 {"xc", PSR_x
| PSR_c
},
18071 {"cf", PSR_c
| PSR_f
},
18072 {"cs", PSR_c
| PSR_s
},
18073 {"cx", PSR_c
| PSR_x
},
18074 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18075 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18076 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18077 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18078 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18079 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18080 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18081 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18082 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18083 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18084 {"scf", PSR_s
| PSR_c
| PSR_f
},
18085 {"scx", PSR_s
| PSR_c
| PSR_x
},
18086 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18087 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18088 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18089 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18090 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18091 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18092 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18093 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18094 {"csf", PSR_c
| PSR_s
| PSR_f
},
18095 {"csx", PSR_c
| PSR_s
| PSR_x
},
18096 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18097 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18098 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18099 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18100 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18101 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18102 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18103 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18104 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18105 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18106 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18107 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18108 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18109 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18110 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18111 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18112 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18113 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18114 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18115 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18116 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18117 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18118 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18119 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18120 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18121 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18124 /* Table of V7M psr names. */
18125 static const struct asm_psr v7m_psrs
[] =
18127 {"apsr", 0 }, {"APSR", 0 },
18128 {"iapsr", 1 }, {"IAPSR", 1 },
18129 {"eapsr", 2 }, {"EAPSR", 2 },
18130 {"psr", 3 }, {"PSR", 3 },
18131 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18132 {"ipsr", 5 }, {"IPSR", 5 },
18133 {"epsr", 6 }, {"EPSR", 6 },
18134 {"iepsr", 7 }, {"IEPSR", 7 },
18135 {"msp", 8 }, {"MSP", 8 },
18136 {"psp", 9 }, {"PSP", 9 },
18137 {"primask", 16}, {"PRIMASK", 16},
18138 {"basepri", 17}, {"BASEPRI", 17},
18139 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18140 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18141 {"faultmask", 19}, {"FAULTMASK", 19},
18142 {"control", 20}, {"CONTROL", 20}
18145 /* Table of all shift-in-operand names. */
18146 static const struct asm_shift_name shift_names
[] =
18148 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18149 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18150 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18151 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18152 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18153 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18156 /* Table of all explicit relocation names. */
18158 static struct reloc_entry reloc_names
[] =
18160 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18161 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18162 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18163 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18164 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18165 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18166 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18167 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18168 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18169 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18170 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18171 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18172 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18173 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18174 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18175 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18176 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18177 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18181 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18182 static const struct asm_cond conds
[] =
18186 {"cs", 0x2}, {"hs", 0x2},
18187 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18201 #define UL_BARRIER(L,U,CODE,FEAT) \
18202 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
18203 { U, CODE, ARM_FEATURE (FEAT, 0) }
18205 static struct asm_barrier_opt barrier_opt_names
[] =
18207 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18208 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18209 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18210 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18211 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18212 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18213 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18214 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18215 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18216 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18217 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18218 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18219 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18220 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18221 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18222 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18227 /* Table of ARM-format instructions. */
18229 /* Macros for gluing together operand strings. N.B. In all cases
18230 other than OPS0, the trailing OP_stop comes from default
18231 zero-initialization of the unspecified elements of the array. */
18232 #define OPS0() { OP_stop, }
18233 #define OPS1(a) { OP_##a, }
18234 #define OPS2(a,b) { OP_##a,OP_##b, }
18235 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18236 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18237 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18238 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18240 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18241 This is useful when mixing operands for ARM and THUMB, i.e. using the
18242 MIX_ARM_THUMB_OPERANDS macro.
18243 In order to use these macros, prefix the number of operands with _
18245 #define OPS_1(a) { a, }
18246 #define OPS_2(a,b) { a,b, }
18247 #define OPS_3(a,b,c) { a,b,c, }
18248 #define OPS_4(a,b,c,d) { a,b,c,d, }
18249 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18250 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18252 /* These macros abstract out the exact format of the mnemonic table and
18253 save some repeated characters. */
18255 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18256 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18257 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18258 THUMB_VARIANT, do_##ae, do_##te }
18260 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18261 a T_MNEM_xyz enumerator. */
18262 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18263 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18264 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18265 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18267 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18268 infix after the third character. */
18269 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18270 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18271 THUMB_VARIANT, do_##ae, do_##te }
18272 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18273 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18274 THUMB_VARIANT, do_##ae, do_##te }
18275 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18276 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18277 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18278 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18279 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18280 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18281 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18282 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18284 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18285 field is still 0xE. Many of the Thumb variants can be executed
18286 conditionally, so this is checked separately. */
18287 #define TUE(mnem, op, top, nops, ops, ae, te) \
18288 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18289 THUMB_VARIANT, do_##ae, do_##te }
18291 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18292 Used by mnemonics that have very minimal differences in the encoding for
18293 ARM and Thumb variants and can be handled in a common function. */
18294 #define TUEc(mnem, op, top, nops, ops, en) \
18295 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18296 THUMB_VARIANT, do_##en, do_##en }
18298 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18299 condition code field. */
18300 #define TUF(mnem, op, top, nops, ops, ae, te) \
18301 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18302 THUMB_VARIANT, do_##ae, do_##te }
18304 /* ARM-only variants of all the above. */
18305 #define CE(mnem, op, nops, ops, ae) \
18306 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18308 #define C3(mnem, op, nops, ops, ae) \
18309 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18311 /* Legacy mnemonics that always have conditional infix after the third
18313 #define CL(mnem, op, nops, ops, ae) \
18314 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18315 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18317 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18318 #define cCE(mnem, op, nops, ops, ae) \
18319 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18321 /* Legacy coprocessor instructions where conditional infix and conditional
18322 suffix are ambiguous. For consistency this includes all FPA instructions,
18323 not just the potentially ambiguous ones. */
18324 #define cCL(mnem, op, nops, ops, ae) \
18325 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18326 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18328 /* Coprocessor, takes either a suffix or a position-3 infix
18329 (for an FPA corner case). */
18330 #define C3E(mnem, op, nops, ops, ae) \
18331 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18332 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18334 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18335 { m1 #m2 m3, OPS##nops ops, \
18336 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18337 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18339 #define CM(m1, m2, op, nops, ops, ae) \
18340 xCM_ (m1, , m2, op, nops, ops, ae), \
18341 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18342 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18343 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18344 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18345 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18346 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18347 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18348 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18349 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18350 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18351 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18352 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18353 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18354 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18355 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18356 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18357 xCM_ (m1, le, m2, op, nops, ops, ae), \
18358 xCM_ (m1, al, m2, op, nops, ops, ae)
18360 #define UE(mnem, op, nops, ops, ae) \
18361 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18363 #define UF(mnem, op, nops, ops, ae) \
18364 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18366 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18367 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18368 use the same encoding function for each. */
18369 #define NUF(mnem, op, nops, ops, enc) \
18370 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18371 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18373 /* Neon data processing, version which indirects through neon_enc_tab for
18374 the various overloaded versions of opcodes. */
18375 #define nUF(mnem, op, nops, ops, enc) \
18376 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18377 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18379 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18381 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18382 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18383 THUMB_VARIANT, do_##enc, do_##enc }
18385 #define NCE(mnem, op, nops, ops, enc) \
18386 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18388 #define NCEF(mnem, op, nops, ops, enc) \
18389 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18391 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18392 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18393 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18394 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18396 #define nCE(mnem, op, nops, ops, enc) \
18397 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18399 #define nCEF(mnem, op, nops, ops, enc) \
18400 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18404 static const struct asm_opcode insns
[] =
18406 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18407 #define THUMB_VARIANT & arm_ext_v4t
18408 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18409 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18410 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18411 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18412 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18413 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18414 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18415 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18416 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18417 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18418 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18419 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18420 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18421 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18422 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18423 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18425 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18426 for setting PSR flag bits. They are obsolete in V6 and do not
18427 have Thumb equivalents. */
18428 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18429 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18430 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18431 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18432 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18433 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18434 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18435 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18436 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18438 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18439 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18440 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18441 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18443 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18444 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18445 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18447 OP_ADDRGLDR
),ldst
, t_ldst
),
18448 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18450 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18451 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18452 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18453 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18454 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18455 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18457 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18458 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18459 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18460 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18463 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18464 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18465 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18466 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18468 /* Thumb-compatibility pseudo ops. */
18469 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18470 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18471 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18472 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18473 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18474 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18475 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18476 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18477 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18478 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18479 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18480 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18482 /* These may simplify to neg. */
18483 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18484 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18486 #undef THUMB_VARIANT
18487 #define THUMB_VARIANT & arm_ext_v6
18489 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18491 /* V1 instructions with no Thumb analogue prior to V6T2. */
18492 #undef THUMB_VARIANT
18493 #define THUMB_VARIANT & arm_ext_v6t2
18495 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18496 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18497 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18499 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18500 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18501 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18502 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18504 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18505 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18507 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18508 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18510 /* V1 instructions with no Thumb analogue at all. */
18511 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18512 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18514 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18515 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18516 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18517 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18518 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18519 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18520 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18521 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18524 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18525 #undef THUMB_VARIANT
18526 #define THUMB_VARIANT & arm_ext_v4t
18528 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18529 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18531 #undef THUMB_VARIANT
18532 #define THUMB_VARIANT & arm_ext_v6t2
18534 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18535 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18537 /* Generic coprocessor instructions. */
18538 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18539 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18540 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18541 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18542 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18543 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18544 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18547 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18549 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18550 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18553 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18554 #undef THUMB_VARIANT
18555 #define THUMB_VARIANT & arm_ext_msr
18557 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18558 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18561 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18562 #undef THUMB_VARIANT
18563 #define THUMB_VARIANT & arm_ext_v6t2
18565 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18566 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18567 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18568 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18569 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18570 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18571 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18572 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18575 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18576 #undef THUMB_VARIANT
18577 #define THUMB_VARIANT & arm_ext_v4t
18579 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18580 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18581 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18582 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18583 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18584 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18587 #define ARM_VARIANT & arm_ext_v4t_5
18589 /* ARM Architecture 4T. */
18590 /* Note: bx (and blx) are required on V5, even if the processor does
18591 not support Thumb. */
18592 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18595 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18596 #undef THUMB_VARIANT
18597 #define THUMB_VARIANT & arm_ext_v5t
18599 /* Note: blx has 2 variants; the .value coded here is for
18600 BLX(2). Only this variant has conditional execution. */
18601 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18602 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18604 #undef THUMB_VARIANT
18605 #define THUMB_VARIANT & arm_ext_v6t2
18607 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18608 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18609 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18610 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18611 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18612 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18613 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18614 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18617 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18618 #undef THUMB_VARIANT
18619 #define THUMB_VARIANT & arm_ext_v5exp
18621 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18622 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18623 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18624 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18626 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18627 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18629 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18630 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18631 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18632 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18634 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18635 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18636 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18637 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18639 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18640 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18642 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18643 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18644 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18645 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18648 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18649 #undef THUMB_VARIANT
18650 #define THUMB_VARIANT & arm_ext_v6t2
18652 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18653 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18655 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18656 ADDRGLDRS
), ldrd
, t_ldstd
),
18658 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18659 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18662 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18664 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18667 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18668 #undef THUMB_VARIANT
18669 #define THUMB_VARIANT & arm_ext_v6
18671 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18672 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18673 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18674 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18675 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18676 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18677 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18678 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18679 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18680 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18682 #undef THUMB_VARIANT
18683 #define THUMB_VARIANT & arm_ext_v6t2
18685 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18686 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18688 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18689 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18691 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18692 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18694 /* ARM V6 not included in V7M. */
18695 #undef THUMB_VARIANT
18696 #define THUMB_VARIANT & arm_ext_v6_notm
18697 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18698 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18699 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18700 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18701 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18702 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18703 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18704 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18705 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18706 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18707 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18708 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18709 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18710 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18711 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18712 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18713 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18714 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18716 /* ARM V6 not included in V7M (eg. integer SIMD). */
18717 #undef THUMB_VARIANT
18718 #define THUMB_VARIANT & arm_ext_v6_dsp
18719 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18720 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18721 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18722 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18723 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18724 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18725 /* Old name for QASX. */
18726 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18727 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18728 /* Old name for QSAX. */
18729 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18730 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18731 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18732 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18733 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18734 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18735 /* Old name for SASX. */
18736 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18737 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18738 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18739 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18740 /* Old name for SHASX. */
18741 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18742 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18743 /* Old name for SHSAX. */
18744 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18745 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18746 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18747 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18748 /* Old name for SSAX. */
18749 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18750 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18751 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18752 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18753 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18754 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18755 /* Old name for UASX. */
18756 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18757 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18758 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18759 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18760 /* Old name for UHASX. */
18761 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18762 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18763 /* Old name for UHSAX. */
18764 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18765 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18766 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18767 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18768 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18769 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18770 /* Old name for UQASX. */
18771 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18772 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18773 /* Old name for UQSAX. */
18774 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18775 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18776 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18777 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18778 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18779 /* Old name for USAX. */
18780 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18781 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18782 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18783 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18784 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18785 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18786 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18787 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18788 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18789 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18790 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18791 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18792 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18793 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18794 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18795 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18796 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18797 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18798 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18799 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18800 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18801 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18802 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18803 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18804 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18805 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18806 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18807 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18808 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18809 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
18810 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
18811 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18812 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18813 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
18816 #define ARM_VARIANT & arm_ext_v6k
18817 #undef THUMB_VARIANT
18818 #define THUMB_VARIANT & arm_ext_v6k
18820 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
18821 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
18822 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
18823 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
18825 #undef THUMB_VARIANT
18826 #define THUMB_VARIANT & arm_ext_v6_notm
18827 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
18829 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
18830 RRnpcb
), strexd
, t_strexd
),
18832 #undef THUMB_VARIANT
18833 #define THUMB_VARIANT & arm_ext_v6t2
18834 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
18836 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
18838 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18840 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18842 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
18845 #define ARM_VARIANT & arm_ext_sec
18846 #undef THUMB_VARIANT
18847 #define THUMB_VARIANT & arm_ext_sec
18849 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
18852 #define ARM_VARIANT & arm_ext_virt
18853 #undef THUMB_VARIANT
18854 #define THUMB_VARIANT & arm_ext_virt
18856 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
18857 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
18860 #define ARM_VARIANT & arm_ext_v6t2
18861 #undef THUMB_VARIANT
18862 #define THUMB_VARIANT & arm_ext_v6t2
18864 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
18865 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
18866 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18867 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18869 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18870 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18871 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18872 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
18874 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18875 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18876 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18877 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18879 /* Thumb-only instructions. */
18881 #define ARM_VARIANT NULL
18882 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
18883 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
18885 /* ARM does not really have an IT instruction, so always allow it.
18886 The opcode is copied from Thumb in order to allow warnings in
18887 -mimplicit-it=[never | arm] modes. */
18889 #define ARM_VARIANT & arm_ext_v1
18891 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
18892 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
18893 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
18894 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
18895 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
18896 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
18897 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
18898 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
18899 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
18900 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
18901 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
18902 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
18903 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
18904 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
18905 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
18906 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18907 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18908 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18910 /* Thumb2 only instructions. */
18912 #define ARM_VARIANT NULL
18914 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18915 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18916 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18917 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18918 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
18919 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
18921 /* Hardware division instructions. */
18923 #define ARM_VARIANT & arm_ext_adiv
18924 #undef THUMB_VARIANT
18925 #define THUMB_VARIANT & arm_ext_div
18927 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18928 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18930 /* ARM V6M/V7 instructions. */
18932 #define ARM_VARIANT & arm_ext_barrier
18933 #undef THUMB_VARIANT
18934 #define THUMB_VARIANT & arm_ext_barrier
18936 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
18937 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
18938 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
18940 /* ARM V7 instructions. */
18942 #define ARM_VARIANT & arm_ext_v7
18943 #undef THUMB_VARIANT
18944 #define THUMB_VARIANT & arm_ext_v7
18946 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
18947 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
18950 #define ARM_VARIANT & arm_ext_mp
18951 #undef THUMB_VARIANT
18952 #define THUMB_VARIANT & arm_ext_mp
18954 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
18956 /* AArchv8 instructions. */
18958 #define ARM_VARIANT & arm_ext_v8
18959 #undef THUMB_VARIANT
18960 #define THUMB_VARIANT & arm_ext_v8
18962 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
18963 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
18964 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18965 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
18967 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
18968 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18969 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18971 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
18973 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18975 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18977 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18978 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18979 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18980 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18981 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18982 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18984 /* ARMv8 T32 only. */
18986 #define ARM_VARIANT NULL
18987 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
18988 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
18989 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
18991 /* FP for ARMv8. */
18993 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
18994 #undef THUMB_VARIANT
18995 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
18997 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18998 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18999 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19000 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19001 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19002 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19003 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19004 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19005 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19006 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19007 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19008 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19009 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19010 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19011 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19012 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19013 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19015 /* Crypto v1 extensions. */
19017 #define ARM_VARIANT & fpu_crypto_ext_armv8
19018 #undef THUMB_VARIANT
19019 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19021 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19022 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19023 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19024 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19025 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19026 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19027 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19028 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19029 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19030 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19031 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19032 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19033 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19034 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19037 #define ARM_VARIANT & crc_ext_armv8
19038 #undef THUMB_VARIANT
19039 #define THUMB_VARIANT & crc_ext_armv8
19040 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19041 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19042 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19043 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19044 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19045 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19048 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19049 #undef THUMB_VARIANT
19050 #define THUMB_VARIANT NULL
19052 cCE("wfs", e200110
, 1, (RR
), rd
),
19053 cCE("rfs", e300110
, 1, (RR
), rd
),
19054 cCE("wfc", e400110
, 1, (RR
), rd
),
19055 cCE("rfc", e500110
, 1, (RR
), rd
),
19057 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19058 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19059 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19060 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19062 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19063 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19064 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19065 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19067 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19068 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19069 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19070 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19071 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19072 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19073 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19074 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19075 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19076 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19077 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19078 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19080 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19081 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19082 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19083 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19084 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19085 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19086 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19087 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19088 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19089 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19090 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19091 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19093 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19094 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19095 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19096 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19097 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19098 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19099 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19100 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19101 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19102 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19103 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19104 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19106 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19107 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19108 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19109 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19110 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19111 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19112 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19113 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19114 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19115 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19116 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19117 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19119 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19120 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19121 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19122 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19123 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19124 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19125 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19126 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19127 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19128 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19129 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19130 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19132 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19133 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19134 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19135 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19136 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19137 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19138 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19139 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19140 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19141 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19142 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19143 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19145 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19146 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19147 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19148 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19149 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19150 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19151 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19152 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19153 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19154 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19155 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19156 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19158 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19159 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19160 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19161 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19162 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19163 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19164 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19165 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19166 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19167 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19168 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19169 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19171 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19172 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19173 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19174 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19175 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19176 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19177 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19178 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19179 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19180 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19181 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19182 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19184 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19185 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19186 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19187 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19188 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19189 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19190 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19191 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19192 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19193 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19194 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19195 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19197 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19198 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19199 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19200 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19201 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19202 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19203 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19204 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19205 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19206 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19207 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19208 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19210 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19211 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19212 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19213 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19214 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19215 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19216 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19217 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19218 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19219 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19220 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19221 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19223 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19224 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19225 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19226 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19227 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19228 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19229 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19230 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19231 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19232 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19233 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19234 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19236 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19237 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19238 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19239 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19240 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19241 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19242 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19243 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19244 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19245 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19246 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19247 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19249 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19250 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19251 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19252 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19253 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19254 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19255 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19256 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19257 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19258 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19259 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19260 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19262 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19263 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19264 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19265 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19266 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19267 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19268 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19269 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19270 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19271 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19272 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19273 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19275 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19276 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19277 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19278 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19279 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19280 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19281 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19282 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19283 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19284 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19285 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19286 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19288 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19289 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19290 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19291 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19292 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19293 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19294 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19295 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19296 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19297 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19298 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19299 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19301 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19302 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19303 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19304 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19305 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19306 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19307 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19308 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19309 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19310 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19311 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19312 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19314 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19315 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19316 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19317 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19318 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19319 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19320 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19321 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19322 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19323 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19324 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19325 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19327 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19328 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19329 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19330 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19331 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19332 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19333 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19334 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19335 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19336 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19337 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19338 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19340 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19341 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19342 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19343 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19344 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19345 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19346 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19347 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19348 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19349 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19350 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19351 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19353 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19354 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19355 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19356 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19357 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19358 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19359 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19360 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19361 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19362 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19363 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19364 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19366 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19367 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19368 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19369 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19370 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19371 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19372 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19373 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19374 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19375 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19376 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19377 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19379 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19380 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19381 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19382 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19383 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19384 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19385 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19386 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19387 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19388 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19389 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19390 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19392 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19393 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19394 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19395 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19396 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19397 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19398 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19399 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19400 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19401 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19402 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19403 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19405 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19406 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19407 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19408 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19409 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19410 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19411 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19412 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19413 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19414 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19415 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19416 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19418 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19419 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19420 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19421 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19422 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19423 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19424 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19425 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19426 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19427 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19428 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19429 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19431 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19432 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19433 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19434 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19435 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19436 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19437 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19438 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19439 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19440 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19441 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19442 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19444 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19445 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19446 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19447 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19449 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19450 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19451 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19452 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19453 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19454 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19455 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19456 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19457 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19458 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19459 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19460 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19462 /* The implementation of the FIX instruction is broken on some
19463 assemblers, in that it accepts a precision specifier as well as a
19464 rounding specifier, despite the fact that this is meaningless.
19465 To be more compatible, we accept it as well, though of course it
19466 does not set any bits. */
19467 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19468 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19469 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19470 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19471 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19472 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19473 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19474 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19475 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19476 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19477 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19478 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19479 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19481 /* Instructions that were new with the real FPA, call them V2. */
19483 #define ARM_VARIANT & fpu_fpa_ext_v2
19485 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19486 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19487 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19488 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19489 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19490 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19493 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19495 /* Moves and type conversions. */
19496 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19497 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19498 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19499 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19500 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19501 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19502 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19503 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19504 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19505 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19506 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19507 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19508 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19509 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19511 /* Memory operations. */
19512 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19513 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19514 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19515 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19516 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19517 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19518 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19519 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19520 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19521 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19522 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19523 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19524 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19525 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19526 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19527 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19528 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19529 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19531 /* Monadic operations. */
19532 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19533 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19534 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19536 /* Dyadic operations. */
19537 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19538 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19539 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19540 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19541 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19542 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19543 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19544 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19545 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19548 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19549 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19550 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19551 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19553 /* Double precision load/store are still present on single precision
19554 implementations. */
19555 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19556 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19557 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19558 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19559 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19560 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19561 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19562 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19563 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19564 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19567 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19569 /* Moves and type conversions. */
19570 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19571 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19572 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19573 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19574 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19575 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19576 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19577 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19578 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19579 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19580 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19581 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19582 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19584 /* Monadic operations. */
19585 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19586 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19587 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19589 /* Dyadic operations. */
19590 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19591 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19592 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19593 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19594 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19595 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19596 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19597 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19598 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19601 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19602 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19603 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19604 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19607 #define ARM_VARIANT & fpu_vfp_ext_v2
19609 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19610 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19611 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19612 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19614 /* Instructions which may belong to either the Neon or VFP instruction sets.
19615 Individual encoder functions perform additional architecture checks. */
19617 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19618 #undef THUMB_VARIANT
19619 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19621 /* These mnemonics are unique to VFP. */
19622 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19623 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19624 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19625 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19626 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19627 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19628 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19629 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19630 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19631 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19633 /* Mnemonics shared by Neon and VFP. */
19634 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19635 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19636 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19638 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19639 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19641 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19642 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19644 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19645 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19646 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19647 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19648 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19649 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19650 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19651 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19653 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19654 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19655 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19656 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19659 /* NOTE: All VMOV encoding is special-cased! */
19660 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19661 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19663 #undef THUMB_VARIANT
19664 #define THUMB_VARIANT & fpu_neon_ext_v1
19666 #define ARM_VARIANT & fpu_neon_ext_v1
19668 /* Data processing with three registers of the same length. */
19669 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19670 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19671 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19672 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19673 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19674 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19675 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19676 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19677 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19678 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19679 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19680 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19681 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19682 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19683 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19684 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19685 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19686 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19687 /* If not immediate, fall back to neon_dyadic_i64_su.
19688 shl_imm should accept I8 I16 I32 I64,
19689 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19690 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19691 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19692 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19693 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19694 /* Logic ops, types optional & ignored. */
19695 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19696 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19697 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19698 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19699 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19700 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19701 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19702 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19703 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19704 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19705 /* Bitfield ops, untyped. */
19706 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19707 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19708 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19709 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19710 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19711 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19712 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19713 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19714 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19715 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19716 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19717 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19718 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19719 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19720 back to neon_dyadic_if_su. */
19721 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19722 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19723 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19724 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19725 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19726 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19727 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19728 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19729 /* Comparison. Type I8 I16 I32 F32. */
19730 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19731 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19732 /* As above, D registers only. */
19733 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19734 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19735 /* Int and float variants, signedness unimportant. */
19736 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19737 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19738 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19739 /* Add/sub take types I8 I16 I32 I64 F32. */
19740 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19741 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19742 /* vtst takes sizes 8, 16, 32. */
19743 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19744 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19745 /* VMUL takes I8 I16 I32 F32 P8. */
19746 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19747 /* VQD{R}MULH takes S16 S32. */
19748 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19749 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19750 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19751 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19752 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19753 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19754 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19755 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19756 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19757 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19758 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19759 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19760 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19761 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19762 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19763 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19765 /* Two address, int/float. Types S8 S16 S32 F32. */
19766 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19767 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19769 /* Data processing with two registers and a shift amount. */
19770 /* Right shifts, and variants with rounding.
19771 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19772 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19773 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19774 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19775 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19776 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19777 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19778 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19779 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19780 /* Shift and insert. Sizes accepted 8 16 32 64. */
19781 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
19782 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
19783 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
19784 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
19785 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19786 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
19787 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
19788 /* Right shift immediate, saturating & narrowing, with rounding variants.
19789 Types accepted S16 S32 S64 U16 U32 U64. */
19790 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19791 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19792 /* As above, unsigned. Types accepted S16 S32 S64. */
19793 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19794 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19795 /* Right shift narrowing. Types accepted I16 I32 I64. */
19796 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19797 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19798 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19799 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
19800 /* CVT with optional immediate for fixed-point variant. */
19801 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
19803 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
19804 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
19806 /* Data processing, three registers of different lengths. */
19807 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19808 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
19809 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19810 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19811 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19812 /* If not scalar, fall back to neon_dyadic_long.
19813 Vector types as above, scalar types S16 S32 U16 U32. */
19814 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19815 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19816 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19817 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19818 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19819 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19820 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19821 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19822 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19823 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19824 /* Saturating doubling multiplies. Types S16 S32. */
19825 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19826 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19827 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19828 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19829 S16 S32 U16 U32. */
19830 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
19832 /* Extract. Size 8. */
19833 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
19834 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
19836 /* Two registers, miscellaneous. */
19837 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19838 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
19839 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
19840 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
19841 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
19842 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
19843 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
19844 /* Vector replicate. Sizes 8 16 32. */
19845 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
19846 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
19847 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19848 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
19849 /* VMOVN. Types I16 I32 I64. */
19850 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
19851 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19852 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
19853 /* VQMOVUN. Types S16 S32 S64. */
19854 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
19855 /* VZIP / VUZP. Sizes 8 16 32. */
19856 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19857 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19858 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19859 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19860 /* VQABS / VQNEG. Types S8 S16 S32. */
19861 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19862 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19863 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19864 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19865 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19866 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19867 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
19868 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19869 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
19870 /* Reciprocal estimates. Types U32 F32. */
19871 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19872 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
19873 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19874 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
19875 /* VCLS. Types S8 S16 S32. */
19876 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
19877 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
19878 /* VCLZ. Types I8 I16 I32. */
19879 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
19880 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
19881 /* VCNT. Size 8. */
19882 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
19883 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
19884 /* Two address, untyped. */
19885 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
19886 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
19887 /* VTRN. Sizes 8 16 32. */
19888 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
19889 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
19891 /* Table lookup. Size 8. */
19892 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19893 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19895 #undef THUMB_VARIANT
19896 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19898 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19900 /* Neon element/structure load/store. */
19901 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19902 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19903 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19904 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19905 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19906 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19907 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19908 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19910 #undef THUMB_VARIANT
19911 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
19913 #define ARM_VARIANT & fpu_vfp_ext_v3xd
19914 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
19915 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19916 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19917 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19918 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19919 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19920 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19921 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19922 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19924 #undef THUMB_VARIANT
19925 #define THUMB_VARIANT & fpu_vfp_ext_v3
19927 #define ARM_VARIANT & fpu_vfp_ext_v3
19929 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
19930 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19931 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19932 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19933 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19934 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19935 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19936 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19937 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19940 #define ARM_VARIANT & fpu_vfp_ext_fma
19941 #undef THUMB_VARIANT
19942 #define THUMB_VARIANT & fpu_vfp_ext_fma
19943 /* Mnemonics shared by Neon and VFP. These are included in the
19944 VFP FMA variant; NEON and VFP FMA always includes the NEON
19945 FMA instructions. */
19946 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
19947 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
19948 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19949 the v form should always be used. */
19950 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19951 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19952 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19953 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19954 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19955 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19957 #undef THUMB_VARIANT
19959 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19961 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19962 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19963 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19964 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19965 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19966 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19967 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
19968 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
19971 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19973 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
19974 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
19975 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
19976 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
19977 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
19978 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
19979 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
19980 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
19981 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
19982 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19983 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19984 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19985 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19986 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19987 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19988 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19989 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19990 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19991 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
19992 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
19993 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19994 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19995 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19996 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19997 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19998 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19999 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20000 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20001 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20002 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20003 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20004 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20005 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20006 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20007 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20008 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20009 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20010 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20011 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20012 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20013 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20014 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20015 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20016 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20017 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20018 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20019 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20020 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20021 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20022 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20023 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20024 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20025 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20026 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20027 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20028 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20029 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20030 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20031 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20032 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20033 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20034 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20035 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20036 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20037 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20038 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20039 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20040 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20041 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20042 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20043 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20044 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20045 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20046 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20047 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20048 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20049 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20050 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20051 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20052 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20053 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20054 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20055 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20056 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20057 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20058 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20059 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20060 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20061 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20062 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20063 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20064 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20065 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20066 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20067 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20068 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20069 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20070 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20071 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20072 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20073 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20074 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20075 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20076 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20077 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20078 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20079 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20080 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20081 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20082 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20083 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20084 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20085 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20086 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20087 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20088 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20089 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20090 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20091 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20092 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20093 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20094 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20095 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20096 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20097 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20098 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20099 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20100 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20101 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20102 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20103 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20104 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20105 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20106 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20107 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20108 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20109 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20110 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20111 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20112 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20113 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20114 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20115 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20116 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20117 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20118 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20119 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20120 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20121 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20122 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20123 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20124 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20125 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20126 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20127 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20128 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20129 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20130 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20131 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20132 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20133 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20134 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20137 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20139 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20140 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20141 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20142 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20143 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20144 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20145 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20146 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20147 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20148 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20149 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20150 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20151 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20152 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20153 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20154 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20155 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20156 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20157 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20158 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20159 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20160 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20161 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20162 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20163 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20164 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20165 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20166 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20167 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20168 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20169 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20170 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20171 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20172 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20173 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20174 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20175 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20176 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20177 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20178 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20179 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20180 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20181 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20182 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20183 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20184 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20185 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20186 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20187 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20188 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20189 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20190 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20191 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20192 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20193 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20194 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20195 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20198 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20200 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20201 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20202 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20203 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20204 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20205 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20206 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20207 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20208 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20209 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20210 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20211 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20212 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20213 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20214 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20215 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20216 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20217 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20218 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20219 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20220 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20221 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20222 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20223 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20224 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20225 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20226 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20227 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20228 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20229 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20230 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20231 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20232 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20233 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20234 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20235 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20236 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20237 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20238 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20239 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20240 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20241 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20242 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20243 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20244 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20245 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20246 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20247 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20248 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20249 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20250 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20251 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20252 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20253 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20254 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20255 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20256 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20257 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20258 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20259 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20260 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20261 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20262 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20263 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20264 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20265 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20266 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20267 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20268 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20269 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20270 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20271 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20272 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20273 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20274 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20275 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20278 #undef THUMB_VARIANT
20304 /* MD interface: bits in the object file. */
20306 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20307 for use in the a.out file, and stores them in the array pointed to by buf.
20308 This knows about the endian-ness of the target machine and does
20309 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20310 2 (short) and 4 (long) Floating numbers are put out as a series of
20311 LITTLENUMS (shorts, here at least). */
20314 md_number_to_chars (char * buf
, valueT val
, int n
)
20316 if (target_big_endian
)
20317 number_to_chars_bigendian (buf
, val
, n
);
20319 number_to_chars_littleendian (buf
, val
, n
);
20323 md_chars_to_number (char * buf
, int n
)
20326 unsigned char * where
= (unsigned char *) buf
;
20328 if (target_big_endian
)
20333 result
|= (*where
++ & 255);
20341 result
|= (where
[n
] & 255);
20348 /* MD interface: Sections. */
20350 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20351 that an rs_machine_dependent frag may reach. */
20354 arm_frag_max_var (fragS
*fragp
)
20356 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20357 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20359 Note that we generate relaxable instructions even for cases that don't
20360 really need it, like an immediate that's a trivial constant. So we're
20361 overestimating the instruction size for some of those cases. Rather
20362 than putting more intelligence here, it would probably be better to
20363 avoid generating a relaxation frag in the first place when it can be
20364 determined up front that a short instruction will suffice. */
20366 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20370 /* Estimate the size of a frag before relaxing. Assume everything fits in
20374 md_estimate_size_before_relax (fragS
* fragp
,
20375 segT segtype ATTRIBUTE_UNUSED
)
20381 /* Convert a machine dependent frag. */
20384 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20386 unsigned long insn
;
20387 unsigned long old_op
;
20395 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20397 old_op
= bfd_get_16(abfd
, buf
);
20398 if (fragp
->fr_symbol
)
20400 exp
.X_op
= O_symbol
;
20401 exp
.X_add_symbol
= fragp
->fr_symbol
;
20405 exp
.X_op
= O_constant
;
20407 exp
.X_add_number
= fragp
->fr_offset
;
20408 opcode
= fragp
->fr_subtype
;
20411 case T_MNEM_ldr_pc
:
20412 case T_MNEM_ldr_pc2
:
20413 case T_MNEM_ldr_sp
:
20414 case T_MNEM_str_sp
:
20421 if (fragp
->fr_var
== 4)
20423 insn
= THUMB_OP32 (opcode
);
20424 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20426 insn
|= (old_op
& 0x700) << 4;
20430 insn
|= (old_op
& 7) << 12;
20431 insn
|= (old_op
& 0x38) << 13;
20433 insn
|= 0x00000c00;
20434 put_thumb32_insn (buf
, insn
);
20435 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20439 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20441 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20444 if (fragp
->fr_var
== 4)
20446 insn
= THUMB_OP32 (opcode
);
20447 insn
|= (old_op
& 0xf0) << 4;
20448 put_thumb32_insn (buf
, insn
);
20449 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20453 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20454 exp
.X_add_number
-= 4;
20462 if (fragp
->fr_var
== 4)
20464 int r0off
= (opcode
== T_MNEM_mov
20465 || opcode
== T_MNEM_movs
) ? 0 : 8;
20466 insn
= THUMB_OP32 (opcode
);
20467 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20468 insn
|= (old_op
& 0x700) << r0off
;
20469 put_thumb32_insn (buf
, insn
);
20470 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20474 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20479 if (fragp
->fr_var
== 4)
20481 insn
= THUMB_OP32(opcode
);
20482 put_thumb32_insn (buf
, insn
);
20483 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20486 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20490 if (fragp
->fr_var
== 4)
20492 insn
= THUMB_OP32(opcode
);
20493 insn
|= (old_op
& 0xf00) << 14;
20494 put_thumb32_insn (buf
, insn
);
20495 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20498 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20501 case T_MNEM_add_sp
:
20502 case T_MNEM_add_pc
:
20503 case T_MNEM_inc_sp
:
20504 case T_MNEM_dec_sp
:
20505 if (fragp
->fr_var
== 4)
20507 /* ??? Choose between add and addw. */
20508 insn
= THUMB_OP32 (opcode
);
20509 insn
|= (old_op
& 0xf0) << 4;
20510 put_thumb32_insn (buf
, insn
);
20511 if (opcode
== T_MNEM_add_pc
)
20512 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20514 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20517 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20525 if (fragp
->fr_var
== 4)
20527 insn
= THUMB_OP32 (opcode
);
20528 insn
|= (old_op
& 0xf0) << 4;
20529 insn
|= (old_op
& 0xf) << 16;
20530 put_thumb32_insn (buf
, insn
);
20531 if (insn
& (1 << 20))
20532 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20534 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20537 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20543 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20544 (enum bfd_reloc_code_real
) reloc_type
);
20545 fixp
->fx_file
= fragp
->fr_file
;
20546 fixp
->fx_line
= fragp
->fr_line
;
20547 fragp
->fr_fix
+= fragp
->fr_var
;
20549 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20550 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
20551 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
20552 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
20555 /* Return the size of a relaxable immediate operand instruction.
20556 SHIFT and SIZE specify the form of the allowable immediate. */
20558 relax_immediate (fragS
*fragp
, int size
, int shift
)
20564 /* ??? Should be able to do better than this. */
20565 if (fragp
->fr_symbol
)
20568 low
= (1 << shift
) - 1;
20569 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20570 offset
= fragp
->fr_offset
;
20571 /* Force misaligned offsets to 32-bit variant. */
20574 if (offset
& ~mask
)
20579 /* Get the address of a symbol during relaxation. */
20581 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20587 sym
= fragp
->fr_symbol
;
20588 sym_frag
= symbol_get_frag (sym
);
20589 know (S_GET_SEGMENT (sym
) != absolute_section
20590 || sym_frag
== &zero_address_frag
);
20591 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20593 /* If frag has yet to be reached on this pass, assume it will
20594 move by STRETCH just as we did. If this is not so, it will
20595 be because some frag between grows, and that will force
20599 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20603 /* Adjust stretch for any alignment frag. Note that if have
20604 been expanding the earlier code, the symbol may be
20605 defined in what appears to be an earlier frag. FIXME:
20606 This doesn't handle the fr_subtype field, which specifies
20607 a maximum number of bytes to skip when doing an
20609 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20611 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20614 stretch
= - ((- stretch
)
20615 & ~ ((1 << (int) f
->fr_offset
) - 1));
20617 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20629 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20632 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20637 /* Assume worst case for symbols not known to be in the same section. */
20638 if (fragp
->fr_symbol
== NULL
20639 || !S_IS_DEFINED (fragp
->fr_symbol
)
20640 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20641 || S_IS_WEAK (fragp
->fr_symbol
))
20644 val
= relaxed_symbol_addr (fragp
, stretch
);
20645 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20646 addr
= (addr
+ 4) & ~3;
20647 /* Force misaligned targets to 32-bit variant. */
20651 if (val
< 0 || val
> 1020)
20656 /* Return the size of a relaxable add/sub immediate instruction. */
20658 relax_addsub (fragS
*fragp
, asection
*sec
)
20663 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20664 op
= bfd_get_16(sec
->owner
, buf
);
20665 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20666 return relax_immediate (fragp
, 8, 0);
20668 return relax_immediate (fragp
, 3, 0);
20671 /* Return TRUE iff the definition of symbol S could be pre-empted
20672 (overridden) at link or load time. */
20674 symbol_preemptible (symbolS
*s
)
20676 /* Weak symbols can always be pre-empted. */
20680 /* Non-global symbols cannot be pre-empted. */
20681 if (! S_IS_EXTERNAL (s
))
20685 /* In ELF, a global symbol can be marked protected, or private. In that
20686 case it can't be pre-empted (other definitions in the same link unit
20687 would violate the ODR). */
20688 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20692 /* Other global symbols might be pre-empted. */
20696 /* Return the size of a relaxable branch instruction. BITS is the
20697 size of the offset field in the narrow instruction. */
20700 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20706 /* Assume worst case for symbols not known to be in the same section. */
20707 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20708 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20709 || S_IS_WEAK (fragp
->fr_symbol
))
20713 /* A branch to a function in ARM state will require interworking. */
20714 if (S_IS_DEFINED (fragp
->fr_symbol
)
20715 && ARM_IS_FUNC (fragp
->fr_symbol
))
20719 if (symbol_preemptible (fragp
->fr_symbol
))
20722 val
= relaxed_symbol_addr (fragp
, stretch
);
20723 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20726 /* Offset is a signed value *2 */
20728 if (val
>= limit
|| val
< -limit
)
20734 /* Relax a machine dependent frag. This returns the amount by which
20735 the current size of the frag should change. */
20738 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20743 oldsize
= fragp
->fr_var
;
20744 switch (fragp
->fr_subtype
)
20746 case T_MNEM_ldr_pc2
:
20747 newsize
= relax_adr (fragp
, sec
, stretch
);
20749 case T_MNEM_ldr_pc
:
20750 case T_MNEM_ldr_sp
:
20751 case T_MNEM_str_sp
:
20752 newsize
= relax_immediate (fragp
, 8, 2);
20756 newsize
= relax_immediate (fragp
, 5, 2);
20760 newsize
= relax_immediate (fragp
, 5, 1);
20764 newsize
= relax_immediate (fragp
, 5, 0);
20767 newsize
= relax_adr (fragp
, sec
, stretch
);
20773 newsize
= relax_immediate (fragp
, 8, 0);
20776 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
20779 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
20781 case T_MNEM_add_sp
:
20782 case T_MNEM_add_pc
:
20783 newsize
= relax_immediate (fragp
, 8, 2);
20785 case T_MNEM_inc_sp
:
20786 case T_MNEM_dec_sp
:
20787 newsize
= relax_immediate (fragp
, 7, 2);
20793 newsize
= relax_addsub (fragp
, sec
);
20799 fragp
->fr_var
= newsize
;
20800 /* Freeze wide instructions that are at or before the same location as
20801 in the previous pass. This avoids infinite loops.
20802 Don't freeze them unconditionally because targets may be artificially
20803 misaligned by the expansion of preceding frags. */
20804 if (stretch
<= 0 && newsize
> 2)
20806 md_convert_frag (sec
->owner
, sec
, fragp
);
20810 return newsize
- oldsize
;
20813 /* Round up a section size to the appropriate boundary. */
20816 md_section_align (segT segment ATTRIBUTE_UNUSED
,
20819 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20820 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
20822 /* For a.out, force the section size to be aligned. If we don't do
20823 this, BFD will align it for us, but it will not write out the
20824 final bytes of the section. This may be a bug in BFD, but it is
20825 easier to fix it here since that is how the other a.out targets
20829 align
= bfd_get_section_alignment (stdoutput
, segment
);
20830 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
20837 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20838 of an rs_align_code fragment. */
20841 arm_handle_align (fragS
* fragP
)
20843 static char const arm_noop
[2][2][4] =
20846 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20847 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20850 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20851 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20854 static char const thumb_noop
[2][2][2] =
20857 {0xc0, 0x46}, /* LE */
20858 {0x46, 0xc0}, /* BE */
20861 {0x00, 0xbf}, /* LE */
20862 {0xbf, 0x00} /* BE */
20865 static char const wide_thumb_noop
[2][4] =
20866 { /* Wide Thumb-2 */
20867 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20868 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20871 unsigned bytes
, fix
, noop_size
;
20874 const char *narrow_noop
= NULL
;
20879 if (fragP
->fr_type
!= rs_align_code
)
20882 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
20883 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
20886 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
20887 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
20889 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
20891 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
20893 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
20894 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
20896 narrow_noop
= thumb_noop
[1][target_big_endian
];
20897 noop
= wide_thumb_noop
[target_big_endian
];
20900 noop
= thumb_noop
[0][target_big_endian
];
20908 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
20909 ? selected_cpu
: arm_arch_none
,
20911 [target_big_endian
];
20918 fragP
->fr_var
= noop_size
;
20920 if (bytes
& (noop_size
- 1))
20922 fix
= bytes
& (noop_size
- 1);
20924 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
20926 memset (p
, 0, fix
);
20933 if (bytes
& noop_size
)
20935 /* Insert a narrow noop. */
20936 memcpy (p
, narrow_noop
, noop_size
);
20938 bytes
-= noop_size
;
20942 /* Use wide noops for the remainder */
20946 while (bytes
>= noop_size
)
20948 memcpy (p
, noop
, noop_size
);
20950 bytes
-= noop_size
;
20954 fragP
->fr_fix
+= fix
;
20957 /* Called from md_do_align. Used to create an alignment
20958 frag in a code section. */
20961 arm_frag_align_code (int n
, int max
)
20965 /* We assume that there will never be a requirement
20966 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20967 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
20972 _("alignments greater than %d bytes not supported in .text sections."),
20973 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
20974 as_fatal ("%s", err_msg
);
20977 p
= frag_var (rs_align_code
,
20978 MAX_MEM_FOR_RS_ALIGN_CODE
,
20980 (relax_substateT
) max
,
20987 /* Perform target specific initialisation of a frag.
20988 Note - despite the name this initialisation is not done when the frag
20989 is created, but only when its type is assigned. A frag can be created
20990 and used a long time before its type is set, so beware of assuming that
20991 this initialisationis performed first. */
20995 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
20997 /* Record whether this frag is in an ARM or a THUMB area. */
20998 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21001 #else /* OBJ_ELF is defined. */
21003 arm_init_frag (fragS
* fragP
, int max_chars
)
21005 /* If the current ARM vs THUMB mode has not already
21006 been recorded into this frag then do so now. */
21007 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21009 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21011 /* Record a mapping symbol for alignment frags. We will delete this
21012 later if the alignment ends up empty. */
21013 switch (fragP
->fr_type
)
21016 case rs_align_test
:
21018 mapping_state_2 (MAP_DATA
, max_chars
);
21020 case rs_align_code
:
21021 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21029 /* When we change sections we need to issue a new mapping symbol. */
21032 arm_elf_change_section (void)
21034 /* Link an unlinked unwind index table section to the .text section. */
21035 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21036 && elf_linked_to_section (now_seg
) == NULL
)
21037 elf_linked_to_section (now_seg
) = text_section
;
21041 arm_elf_section_type (const char * str
, size_t len
)
21043 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21044 return SHT_ARM_EXIDX
;
21049 /* Code to deal with unwinding tables. */
21051 static void add_unwind_adjustsp (offsetT
);
21053 /* Generate any deferred unwind frame offset. */
21056 flush_pending_unwind (void)
21060 offset
= unwind
.pending_offset
;
21061 unwind
.pending_offset
= 0;
21063 add_unwind_adjustsp (offset
);
21066 /* Add an opcode to this list for this function. Two-byte opcodes should
21067 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21071 add_unwind_opcode (valueT op
, int length
)
21073 /* Add any deferred stack adjustment. */
21074 if (unwind
.pending_offset
)
21075 flush_pending_unwind ();
21077 unwind
.sp_restored
= 0;
21079 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21081 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21082 if (unwind
.opcodes
)
21083 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21084 unwind
.opcode_alloc
);
21086 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21091 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21093 unwind
.opcode_count
++;
21097 /* Add unwind opcodes to adjust the stack pointer. */
21100 add_unwind_adjustsp (offsetT offset
)
21104 if (offset
> 0x200)
21106 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21111 /* Long form: 0xb2, uleb128. */
21112 /* This might not fit in a word so add the individual bytes,
21113 remembering the list is built in reverse order. */
21114 o
= (valueT
) ((offset
- 0x204) >> 2);
21116 add_unwind_opcode (0, 1);
21118 /* Calculate the uleb128 encoding of the offset. */
21122 bytes
[n
] = o
& 0x7f;
21128 /* Add the insn. */
21130 add_unwind_opcode (bytes
[n
- 1], 1);
21131 add_unwind_opcode (0xb2, 1);
21133 else if (offset
> 0x100)
21135 /* Two short opcodes. */
21136 add_unwind_opcode (0x3f, 1);
21137 op
= (offset
- 0x104) >> 2;
21138 add_unwind_opcode (op
, 1);
21140 else if (offset
> 0)
21142 /* Short opcode. */
21143 op
= (offset
- 4) >> 2;
21144 add_unwind_opcode (op
, 1);
21146 else if (offset
< 0)
21149 while (offset
> 0x100)
21151 add_unwind_opcode (0x7f, 1);
21154 op
= ((offset
- 4) >> 2) | 0x40;
21155 add_unwind_opcode (op
, 1);
21159 /* Finish the list of unwind opcodes for this function. */
21161 finish_unwind_opcodes (void)
21165 if (unwind
.fp_used
)
21167 /* Adjust sp as necessary. */
21168 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21169 flush_pending_unwind ();
21171 /* After restoring sp from the frame pointer. */
21172 op
= 0x90 | unwind
.fp_reg
;
21173 add_unwind_opcode (op
, 1);
21176 flush_pending_unwind ();
21180 /* Start an exception table entry. If idx is nonzero this is an index table
21184 start_unwind_section (const segT text_seg
, int idx
)
21186 const char * text_name
;
21187 const char * prefix
;
21188 const char * prefix_once
;
21189 const char * group_name
;
21193 size_t sec_name_len
;
21200 prefix
= ELF_STRING_ARM_unwind
;
21201 prefix_once
= ELF_STRING_ARM_unwind_once
;
21202 type
= SHT_ARM_EXIDX
;
21206 prefix
= ELF_STRING_ARM_unwind_info
;
21207 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21208 type
= SHT_PROGBITS
;
21211 text_name
= segment_name (text_seg
);
21212 if (streq (text_name
, ".text"))
21215 if (strncmp (text_name
, ".gnu.linkonce.t.",
21216 strlen (".gnu.linkonce.t.")) == 0)
21218 prefix
= prefix_once
;
21219 text_name
+= strlen (".gnu.linkonce.t.");
21222 prefix_len
= strlen (prefix
);
21223 text_len
= strlen (text_name
);
21224 sec_name_len
= prefix_len
+ text_len
;
21225 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21226 memcpy (sec_name
, prefix
, prefix_len
);
21227 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21228 sec_name
[prefix_len
+ text_len
] = '\0';
21234 /* Handle COMDAT group. */
21235 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21237 group_name
= elf_group_name (text_seg
);
21238 if (group_name
== NULL
)
21240 as_bad (_("Group section `%s' has no group signature"),
21241 segment_name (text_seg
));
21242 ignore_rest_of_line ();
21245 flags
|= SHF_GROUP
;
21249 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21251 /* Set the section link for index tables. */
21253 elf_linked_to_section (now_seg
) = text_seg
;
21257 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21258 personality routine data. Returns zero, or the index table value for
21259 an inline entry. */
21262 create_unwind_entry (int have_data
)
21267 /* The current word of data. */
21269 /* The number of bytes left in this word. */
21272 finish_unwind_opcodes ();
21274 /* Remember the current text section. */
21275 unwind
.saved_seg
= now_seg
;
21276 unwind
.saved_subseg
= now_subseg
;
21278 start_unwind_section (now_seg
, 0);
21280 if (unwind
.personality_routine
== NULL
)
21282 if (unwind
.personality_index
== -2)
21285 as_bad (_("handlerdata in cantunwind frame"));
21286 return 1; /* EXIDX_CANTUNWIND. */
21289 /* Use a default personality routine if none is specified. */
21290 if (unwind
.personality_index
== -1)
21292 if (unwind
.opcode_count
> 3)
21293 unwind
.personality_index
= 1;
21295 unwind
.personality_index
= 0;
21298 /* Space for the personality routine entry. */
21299 if (unwind
.personality_index
== 0)
21301 if (unwind
.opcode_count
> 3)
21302 as_bad (_("too many unwind opcodes for personality routine 0"));
21306 /* All the data is inline in the index table. */
21309 while (unwind
.opcode_count
> 0)
21311 unwind
.opcode_count
--;
21312 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21316 /* Pad with "finish" opcodes. */
21318 data
= (data
<< 8) | 0xb0;
21325 /* We get two opcodes "free" in the first word. */
21326 size
= unwind
.opcode_count
- 2;
21330 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21331 if (unwind
.personality_index
!= -1)
21333 as_bad (_("attempt to recreate an unwind entry"));
21337 /* An extra byte is required for the opcode count. */
21338 size
= unwind
.opcode_count
+ 1;
21341 size
= (size
+ 3) >> 2;
21343 as_bad (_("too many unwind opcodes"));
21345 frag_align (2, 0, 0);
21346 record_alignment (now_seg
, 2);
21347 unwind
.table_entry
= expr_build_dot ();
21349 /* Allocate the table entry. */
21350 ptr
= frag_more ((size
<< 2) + 4);
21351 /* PR 13449: Zero the table entries in case some of them are not used. */
21352 memset (ptr
, 0, (size
<< 2) + 4);
21353 where
= frag_now_fix () - ((size
<< 2) + 4);
21355 switch (unwind
.personality_index
)
21358 /* ??? Should this be a PLT generating relocation? */
21359 /* Custom personality routine. */
21360 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21361 BFD_RELOC_ARM_PREL31
);
21366 /* Set the first byte to the number of additional words. */
21367 data
= size
> 0 ? size
- 1 : 0;
21371 /* ABI defined personality routines. */
21373 /* Three opcodes bytes are packed into the first word. */
21380 /* The size and first two opcode bytes go in the first word. */
21381 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21386 /* Should never happen. */
21390 /* Pack the opcodes into words (MSB first), reversing the list at the same
21392 while (unwind
.opcode_count
> 0)
21396 md_number_to_chars (ptr
, data
, 4);
21401 unwind
.opcode_count
--;
21403 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21406 /* Finish off the last word. */
21409 /* Pad with "finish" opcodes. */
21411 data
= (data
<< 8) | 0xb0;
21413 md_number_to_chars (ptr
, data
, 4);
21418 /* Add an empty descriptor if there is no user-specified data. */
21419 ptr
= frag_more (4);
21420 md_number_to_chars (ptr
, 0, 4);
21427 /* Initialize the DWARF-2 unwind information for this procedure. */
21430 tc_arm_frame_initial_instructions (void)
21432 cfi_add_CFA_def_cfa (REG_SP
, 0);
21434 #endif /* OBJ_ELF */
21436 /* Convert REGNAME to a DWARF-2 register number. */
21439 tc_arm_regname_to_dw2regnum (char *regname
)
21441 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21445 /* PR 16694: Allow VFP registers as well. */
21446 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21450 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21459 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21463 exp
.X_op
= O_secrel
;
21464 exp
.X_add_symbol
= symbol
;
21465 exp
.X_add_number
= 0;
21466 emit_expr (&exp
, size
);
21470 /* MD interface: Symbol and relocation handling. */
21472 /* Return the address within the segment that a PC-relative fixup is
21473 relative to. For ARM, PC-relative fixups applied to instructions
21474 are generally relative to the location of the fixup plus 8 bytes.
21475 Thumb branches are offset by 4, and Thumb loads relative to PC
21476 require special handling. */
21479 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21481 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21483 /* If this is pc-relative and we are going to emit a relocation
21484 then we just want to put out any pipeline compensation that the linker
21485 will need. Otherwise we want to use the calculated base.
21486 For WinCE we skip the bias for externals as well, since this
21487 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21489 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21490 || (arm_force_relocation (fixP
)
21492 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21498 switch (fixP
->fx_r_type
)
21500 /* PC relative addressing on the Thumb is slightly odd as the
21501 bottom two bits of the PC are forced to zero for the
21502 calculation. This happens *after* application of the
21503 pipeline offset. However, Thumb adrl already adjusts for
21504 this, so we need not do it again. */
21505 case BFD_RELOC_ARM_THUMB_ADD
:
21508 case BFD_RELOC_ARM_THUMB_OFFSET
:
21509 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21510 case BFD_RELOC_ARM_T32_ADD_PC12
:
21511 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21512 return (base
+ 4) & ~3;
21514 /* Thumb branches are simply offset by +4. */
21515 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21516 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21517 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21518 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21519 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21522 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21524 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21525 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21526 && ARM_IS_FUNC (fixP
->fx_addsy
)
21527 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21528 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21531 /* BLX is like branches above, but forces the low two bits of PC to
21533 case BFD_RELOC_THUMB_PCREL_BLX
:
21535 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21536 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21537 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21538 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21539 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21540 return (base
+ 4) & ~3;
21542 /* ARM mode branches are offset by +8. However, the Windows CE
21543 loader expects the relocation not to take this into account. */
21544 case BFD_RELOC_ARM_PCREL_BLX
:
21546 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21547 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21548 && ARM_IS_FUNC (fixP
->fx_addsy
)
21549 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21550 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21553 case BFD_RELOC_ARM_PCREL_CALL
:
21555 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21556 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21557 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21558 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21559 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21562 case BFD_RELOC_ARM_PCREL_BRANCH
:
21563 case BFD_RELOC_ARM_PCREL_JUMP
:
21564 case BFD_RELOC_ARM_PLT32
:
21566 /* When handling fixups immediately, because we have already
21567 discovered the value of a symbol, or the address of the frag involved
21568 we must account for the offset by +8, as the OS loader will never see the reloc.
21569 see fixup_segment() in write.c
21570 The S_IS_EXTERNAL test handles the case of global symbols.
21571 Those need the calculated base, not just the pipe compensation the linker will need. */
21573 && fixP
->fx_addsy
!= NULL
21574 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21575 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21583 /* ARM mode loads relative to PC are also offset by +8. Unlike
21584 branches, the Windows CE loader *does* expect the relocation
21585 to take this into account. */
21586 case BFD_RELOC_ARM_OFFSET_IMM
:
21587 case BFD_RELOC_ARM_OFFSET_IMM8
:
21588 case BFD_RELOC_ARM_HWLITERAL
:
21589 case BFD_RELOC_ARM_LITERAL
:
21590 case BFD_RELOC_ARM_CP_OFF_IMM
:
21594 /* Other PC-relative relocations are un-offset. */
21600 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21601 Otherwise we have no need to default values of symbols. */
21604 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21607 if (name
[0] == '_' && name
[1] == 'G'
21608 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21612 if (symbol_find (name
))
21613 as_bad (_("GOT already in the symbol table"));
21615 GOT_symbol
= symbol_new (name
, undefined_section
,
21616 (valueT
) 0, & zero_address_frag
);
21626 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21627 computed as two separate immediate values, added together. We
21628 already know that this value cannot be computed by just one ARM
21631 static unsigned int
21632 validate_immediate_twopart (unsigned int val
,
21633 unsigned int * highpart
)
21638 for (i
= 0; i
< 32; i
+= 2)
21639 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21645 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21647 else if (a
& 0xff0000)
21649 if (a
& 0xff000000)
21651 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21655 gas_assert (a
& 0xff000000);
21656 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21659 return (a
& 0xff) | (i
<< 7);
21666 validate_offset_imm (unsigned int val
, int hwse
)
21668 if ((hwse
&& val
> 255) || val
> 4095)
21673 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21674 negative immediate constant by altering the instruction. A bit of
21679 by inverting the second operand, and
21682 by negating the second operand. */
21685 negate_data_op (unsigned long * instruction
,
21686 unsigned long value
)
21689 unsigned long negated
, inverted
;
21691 negated
= encode_arm_immediate (-value
);
21692 inverted
= encode_arm_immediate (~value
);
21694 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21697 /* First negates. */
21698 case OPCODE_SUB
: /* ADD <-> SUB */
21699 new_inst
= OPCODE_ADD
;
21704 new_inst
= OPCODE_SUB
;
21708 case OPCODE_CMP
: /* CMP <-> CMN */
21709 new_inst
= OPCODE_CMN
;
21714 new_inst
= OPCODE_CMP
;
21718 /* Now Inverted ops. */
21719 case OPCODE_MOV
: /* MOV <-> MVN */
21720 new_inst
= OPCODE_MVN
;
21725 new_inst
= OPCODE_MOV
;
21729 case OPCODE_AND
: /* AND <-> BIC */
21730 new_inst
= OPCODE_BIC
;
21735 new_inst
= OPCODE_AND
;
21739 case OPCODE_ADC
: /* ADC <-> SBC */
21740 new_inst
= OPCODE_SBC
;
21745 new_inst
= OPCODE_ADC
;
21749 /* We cannot do anything. */
21754 if (value
== (unsigned) FAIL
)
21757 *instruction
&= OPCODE_MASK
;
21758 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
21762 /* Like negate_data_op, but for Thumb-2. */
21764 static unsigned int
21765 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
21769 unsigned int negated
, inverted
;
21771 negated
= encode_thumb32_immediate (-value
);
21772 inverted
= encode_thumb32_immediate (~value
);
21774 rd
= (*instruction
>> 8) & 0xf;
21775 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
21778 /* ADD <-> SUB. Includes CMP <-> CMN. */
21779 case T2_OPCODE_SUB
:
21780 new_inst
= T2_OPCODE_ADD
;
21784 case T2_OPCODE_ADD
:
21785 new_inst
= T2_OPCODE_SUB
;
21789 /* ORR <-> ORN. Includes MOV <-> MVN. */
21790 case T2_OPCODE_ORR
:
21791 new_inst
= T2_OPCODE_ORN
;
21795 case T2_OPCODE_ORN
:
21796 new_inst
= T2_OPCODE_ORR
;
21800 /* AND <-> BIC. TST has no inverted equivalent. */
21801 case T2_OPCODE_AND
:
21802 new_inst
= T2_OPCODE_BIC
;
21809 case T2_OPCODE_BIC
:
21810 new_inst
= T2_OPCODE_AND
;
21815 case T2_OPCODE_ADC
:
21816 new_inst
= T2_OPCODE_SBC
;
21820 case T2_OPCODE_SBC
:
21821 new_inst
= T2_OPCODE_ADC
;
21825 /* We cannot do anything. */
21830 if (value
== (unsigned int)FAIL
)
21833 *instruction
&= T2_OPCODE_MASK
;
21834 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
21838 /* Read a 32-bit thumb instruction from buf. */
21839 static unsigned long
21840 get_thumb32_insn (char * buf
)
21842 unsigned long insn
;
21843 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
21844 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21850 /* We usually want to set the low bit on the address of thumb function
21851 symbols. In particular .word foo - . should have the low bit set.
21852 Generic code tries to fold the difference of two symbols to
21853 a constant. Prevent this and force a relocation when the first symbols
21854 is a thumb function. */
21857 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
21859 if (op
== O_subtract
21860 && l
->X_op
== O_symbol
21861 && r
->X_op
== O_symbol
21862 && THUMB_IS_FUNC (l
->X_add_symbol
))
21864 l
->X_op
= O_subtract
;
21865 l
->X_op_symbol
= r
->X_add_symbol
;
21866 l
->X_add_number
-= r
->X_add_number
;
21870 /* Process as normal. */
21874 /* Encode Thumb2 unconditional branches and calls. The encoding
21875 for the 2 are identical for the immediate values. */
21878 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
21880 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21883 addressT S
, I1
, I2
, lo
, hi
;
21885 S
= (value
>> 24) & 0x01;
21886 I1
= (value
>> 23) & 0x01;
21887 I2
= (value
>> 22) & 0x01;
21888 hi
= (value
>> 12) & 0x3ff;
21889 lo
= (value
>> 1) & 0x7ff;
21890 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21891 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21892 newval
|= (S
<< 10) | hi
;
21893 newval2
&= ~T2I1I2MASK
;
21894 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
21895 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21896 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
21900 md_apply_fix (fixS
* fixP
,
21904 offsetT value
= * valP
;
21906 unsigned int newimm
;
21907 unsigned long temp
;
21909 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
21911 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
21913 /* Note whether this will delete the relocation. */
21915 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
21918 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21919 consistency with the behaviour on 32-bit hosts. Remember value
21921 value
&= 0xffffffff;
21922 value
^= 0x80000000;
21923 value
-= 0x80000000;
21926 fixP
->fx_addnumber
= value
;
21928 /* Same treatment for fixP->fx_offset. */
21929 fixP
->fx_offset
&= 0xffffffff;
21930 fixP
->fx_offset
^= 0x80000000;
21931 fixP
->fx_offset
-= 0x80000000;
21933 switch (fixP
->fx_r_type
)
21935 case BFD_RELOC_NONE
:
21936 /* This will need to go in the object file. */
21940 case BFD_RELOC_ARM_IMMEDIATE
:
21941 /* We claim that this fixup has been processed here,
21942 even if in fact we generate an error because we do
21943 not have a reloc for it, so tc_gen_reloc will reject it. */
21946 if (fixP
->fx_addsy
)
21948 const char *msg
= 0;
21950 if (! S_IS_DEFINED (fixP
->fx_addsy
))
21951 msg
= _("undefined symbol %s used as an immediate value");
21952 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21953 msg
= _("symbol %s is in a different section");
21954 else if (S_IS_WEAK (fixP
->fx_addsy
))
21955 msg
= _("symbol %s is weak and may be overridden later");
21959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21960 msg
, S_GET_NAME (fixP
->fx_addsy
));
21965 temp
= md_chars_to_number (buf
, INSN_SIZE
);
21967 /* If the offset is negative, we should use encoding A2 for ADR. */
21968 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
21969 newimm
= negate_data_op (&temp
, value
);
21972 newimm
= encode_arm_immediate (value
);
21974 /* If the instruction will fail, see if we can fix things up by
21975 changing the opcode. */
21976 if (newimm
== (unsigned int) FAIL
)
21977 newimm
= negate_data_op (&temp
, value
);
21980 if (newimm
== (unsigned int) FAIL
)
21982 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21983 _("invalid constant (%lx) after fixup"),
21984 (unsigned long) value
);
21988 newimm
|= (temp
& 0xfffff000);
21989 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
21992 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21994 unsigned int highpart
= 0;
21995 unsigned int newinsn
= 0xe1a00000; /* nop. */
21997 if (fixP
->fx_addsy
)
21999 const char *msg
= 0;
22001 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22002 msg
= _("undefined symbol %s used as an immediate value");
22003 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22004 msg
= _("symbol %s is in a different section");
22005 else if (S_IS_WEAK (fixP
->fx_addsy
))
22006 msg
= _("symbol %s is weak and may be overridden later");
22010 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22011 msg
, S_GET_NAME (fixP
->fx_addsy
));
22016 newimm
= encode_arm_immediate (value
);
22017 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22019 /* If the instruction will fail, see if we can fix things up by
22020 changing the opcode. */
22021 if (newimm
== (unsigned int) FAIL
22022 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22024 /* No ? OK - try using two ADD instructions to generate
22026 newimm
= validate_immediate_twopart (value
, & highpart
);
22028 /* Yes - then make sure that the second instruction is
22030 if (newimm
!= (unsigned int) FAIL
)
22032 /* Still No ? Try using a negated value. */
22033 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22034 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22035 /* Otherwise - give up. */
22038 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22039 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22044 /* Replace the first operand in the 2nd instruction (which
22045 is the PC) with the destination register. We have
22046 already added in the PC in the first instruction and we
22047 do not want to do it again. */
22048 newinsn
&= ~ 0xf0000;
22049 newinsn
|= ((newinsn
& 0x0f000) << 4);
22052 newimm
|= (temp
& 0xfffff000);
22053 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22055 highpart
|= (newinsn
& 0xfffff000);
22056 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22060 case BFD_RELOC_ARM_OFFSET_IMM
:
22061 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22064 case BFD_RELOC_ARM_LITERAL
:
22070 if (validate_offset_imm (value
, 0) == FAIL
)
22072 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22073 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22074 _("invalid literal constant: pool needs to be closer"));
22076 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22077 _("bad immediate value for offset (%ld)"),
22082 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22084 newval
&= 0xfffff000;
22087 newval
&= 0xff7ff000;
22088 newval
|= value
| (sign
? INDEX_UP
: 0);
22090 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22093 case BFD_RELOC_ARM_OFFSET_IMM8
:
22094 case BFD_RELOC_ARM_HWLITERAL
:
22100 if (validate_offset_imm (value
, 1) == FAIL
)
22102 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22103 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22104 _("invalid literal constant: pool needs to be closer"));
22106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22107 _("bad immediate value for 8-bit offset (%ld)"),
22112 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22114 newval
&= 0xfffff0f0;
22117 newval
&= 0xff7ff0f0;
22118 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22120 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22123 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22124 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22126 _("bad immediate value for offset (%ld)"), (long) value
);
22129 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22131 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22134 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22135 /* This is a complicated relocation used for all varieties of Thumb32
22136 load/store instruction with immediate offset:
22138 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22139 *4, optional writeback(W)
22140 (doubleword load/store)
22142 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22143 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22144 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22145 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22146 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22148 Uppercase letters indicate bits that are already encoded at
22149 this point. Lowercase letters are our problem. For the
22150 second block of instructions, the secondary opcode nybble
22151 (bits 8..11) is present, and bit 23 is zero, even if this is
22152 a PC-relative operation. */
22153 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22155 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22157 if ((newval
& 0xf0000000) == 0xe0000000)
22159 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22161 newval
|= (1 << 23);
22164 if (value
% 4 != 0)
22166 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22167 _("offset not a multiple of 4"));
22173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22174 _("offset out of range"));
22179 else if ((newval
& 0x000f0000) == 0x000f0000)
22181 /* PC-relative, 12-bit offset. */
22183 newval
|= (1 << 23);
22188 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22189 _("offset out of range"));
22194 else if ((newval
& 0x00000100) == 0x00000100)
22196 /* Writeback: 8-bit, +/- offset. */
22198 newval
|= (1 << 9);
22203 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22204 _("offset out of range"));
22209 else if ((newval
& 0x00000f00) == 0x00000e00)
22211 /* T-instruction: positive 8-bit offset. */
22212 if (value
< 0 || value
> 0xff)
22214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22215 _("offset out of range"));
22223 /* Positive 12-bit or negative 8-bit offset. */
22227 newval
|= (1 << 23);
22237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22238 _("offset out of range"));
22245 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22246 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22249 case BFD_RELOC_ARM_SHIFT_IMM
:
22250 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22251 if (((unsigned long) value
) > 32
22253 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22255 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22256 _("shift expression is too large"));
22261 /* Shifts of zero must be done as lsl. */
22263 else if (value
== 32)
22265 newval
&= 0xfffff07f;
22266 newval
|= (value
& 0x1f) << 7;
22267 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22270 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22271 case BFD_RELOC_ARM_T32_ADD_IMM
:
22272 case BFD_RELOC_ARM_T32_IMM12
:
22273 case BFD_RELOC_ARM_T32_ADD_PC12
:
22274 /* We claim that this fixup has been processed here,
22275 even if in fact we generate an error because we do
22276 not have a reloc for it, so tc_gen_reloc will reject it. */
22280 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22282 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22283 _("undefined symbol %s used as an immediate value"),
22284 S_GET_NAME (fixP
->fx_addsy
));
22288 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22290 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22293 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22294 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22296 newimm
= encode_thumb32_immediate (value
);
22297 if (newimm
== (unsigned int) FAIL
)
22298 newimm
= thumb32_negate_data_op (&newval
, value
);
22300 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22301 && newimm
== (unsigned int) FAIL
)
22303 /* Turn add/sum into addw/subw. */
22304 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22305 newval
= (newval
& 0xfeffffff) | 0x02000000;
22306 /* No flat 12-bit imm encoding for addsw/subsw. */
22307 if ((newval
& 0x00100000) == 0)
22309 /* 12 bit immediate for addw/subw. */
22313 newval
^= 0x00a00000;
22316 newimm
= (unsigned int) FAIL
;
22322 if (newimm
== (unsigned int)FAIL
)
22324 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22325 _("invalid constant (%lx) after fixup"),
22326 (unsigned long) value
);
22330 newval
|= (newimm
& 0x800) << 15;
22331 newval
|= (newimm
& 0x700) << 4;
22332 newval
|= (newimm
& 0x0ff);
22334 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22335 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22338 case BFD_RELOC_ARM_SMC
:
22339 if (((unsigned long) value
) > 0xffff)
22340 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22341 _("invalid smc expression"));
22342 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22343 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22344 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22347 case BFD_RELOC_ARM_HVC
:
22348 if (((unsigned long) value
) > 0xffff)
22349 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22350 _("invalid hvc expression"));
22351 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22352 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22353 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22356 case BFD_RELOC_ARM_SWI
:
22357 if (fixP
->tc_fix_data
!= 0)
22359 if (((unsigned long) value
) > 0xff)
22360 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22361 _("invalid swi expression"));
22362 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22364 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22368 if (((unsigned long) value
) > 0x00ffffff)
22369 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22370 _("invalid swi expression"));
22371 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22373 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22377 case BFD_RELOC_ARM_MULTI
:
22378 if (((unsigned long) value
) > 0xffff)
22379 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22380 _("invalid expression in load/store multiple"));
22381 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22382 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22386 case BFD_RELOC_ARM_PCREL_CALL
:
22388 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22390 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22391 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22392 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22393 /* Flip the bl to blx. This is a simple flip
22394 bit here because we generate PCREL_CALL for
22395 unconditional bls. */
22397 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22398 newval
= newval
| 0x10000000;
22399 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22405 goto arm_branch_common
;
22407 case BFD_RELOC_ARM_PCREL_JUMP
:
22408 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22410 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22411 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22412 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22414 /* This would map to a bl<cond>, b<cond>,
22415 b<always> to a Thumb function. We
22416 need to force a relocation for this particular
22418 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22422 case BFD_RELOC_ARM_PLT32
:
22424 case BFD_RELOC_ARM_PCREL_BRANCH
:
22426 goto arm_branch_common
;
22428 case BFD_RELOC_ARM_PCREL_BLX
:
22431 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22433 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22434 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22435 && ARM_IS_FUNC (fixP
->fx_addsy
))
22437 /* Flip the blx to a bl and warn. */
22438 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22439 newval
= 0xeb000000;
22440 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22441 _("blx to '%s' an ARM ISA state function changed to bl"),
22443 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22449 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22450 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22454 /* We are going to store value (shifted right by two) in the
22455 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22456 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22457 also be be clear. */
22459 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22460 _("misaligned branch destination"));
22461 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22462 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22465 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22467 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22468 newval
|= (value
>> 2) & 0x00ffffff;
22469 /* Set the H bit on BLX instructions. */
22473 newval
|= 0x01000000;
22475 newval
&= ~0x01000000;
22477 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22481 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22482 /* CBZ can only branch forward. */
22484 /* Attempts to use CBZ to branch to the next instruction
22485 (which, strictly speaking, are prohibited) will be turned into
22488 FIXME: It may be better to remove the instruction completely and
22489 perform relaxation. */
22492 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22493 newval
= 0xbf00; /* NOP encoding T1 */
22494 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22499 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22501 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22503 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22504 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22505 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22510 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22511 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22512 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22514 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22516 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22517 newval
|= (value
& 0x1ff) >> 1;
22518 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22522 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22523 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22524 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22526 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22528 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22529 newval
|= (value
& 0xfff) >> 1;
22530 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22534 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22536 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22537 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22538 && ARM_IS_FUNC (fixP
->fx_addsy
)
22539 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22541 /* Force a relocation for a branch 20 bits wide. */
22544 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22545 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22546 _("conditional branch out of range"));
22548 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22551 addressT S
, J1
, J2
, lo
, hi
;
22553 S
= (value
& 0x00100000) >> 20;
22554 J2
= (value
& 0x00080000) >> 19;
22555 J1
= (value
& 0x00040000) >> 18;
22556 hi
= (value
& 0x0003f000) >> 12;
22557 lo
= (value
& 0x00000ffe) >> 1;
22559 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22560 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22561 newval
|= (S
<< 10) | hi
;
22562 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22563 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22564 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22568 case BFD_RELOC_THUMB_PCREL_BLX
:
22569 /* If there is a blx from a thumb state function to
22570 another thumb function flip this to a bl and warn
22574 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22575 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22576 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22578 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22579 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22580 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22582 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22583 newval
= newval
| 0x1000;
22584 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22585 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22590 goto thumb_bl_common
;
22592 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22593 /* A bl from Thumb state ISA to an internal ARM state function
22594 is converted to a blx. */
22596 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22597 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22598 && ARM_IS_FUNC (fixP
->fx_addsy
)
22599 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22601 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22602 newval
= newval
& ~0x1000;
22603 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22604 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22610 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22611 /* For a BLX instruction, make sure that the relocation is rounded up
22612 to a word boundary. This follows the semantics of the instruction
22613 which specifies that bit 1 of the target address will come from bit
22614 1 of the base address. */
22615 value
= (value
+ 3) & ~ 3;
22618 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22619 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22620 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22623 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22625 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22626 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22627 else if ((value
& ~0x1ffffff)
22628 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22630 _("Thumb2 branch out of range"));
22633 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22634 encode_thumb2_b_bl_offset (buf
, value
);
22638 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22639 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22640 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22642 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22643 encode_thumb2_b_bl_offset (buf
, value
);
22648 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22653 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22654 md_number_to_chars (buf
, value
, 2);
22658 case BFD_RELOC_ARM_TLS_CALL
:
22659 case BFD_RELOC_ARM_THM_TLS_CALL
:
22660 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22661 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22662 case BFD_RELOC_ARM_TLS_GOTDESC
:
22663 case BFD_RELOC_ARM_TLS_GD32
:
22664 case BFD_RELOC_ARM_TLS_LE32
:
22665 case BFD_RELOC_ARM_TLS_IE32
:
22666 case BFD_RELOC_ARM_TLS_LDM32
:
22667 case BFD_RELOC_ARM_TLS_LDO32
:
22668 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22671 case BFD_RELOC_ARM_GOT32
:
22672 case BFD_RELOC_ARM_GOTOFF
:
22675 case BFD_RELOC_ARM_GOT_PREL
:
22676 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22677 md_number_to_chars (buf
, value
, 4);
22680 case BFD_RELOC_ARM_TARGET2
:
22681 /* TARGET2 is not partial-inplace, so we need to write the
22682 addend here for REL targets, because it won't be written out
22683 during reloc processing later. */
22684 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22685 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22689 case BFD_RELOC_RVA
:
22691 case BFD_RELOC_ARM_TARGET1
:
22692 case BFD_RELOC_ARM_ROSEGREL32
:
22693 case BFD_RELOC_ARM_SBREL32
:
22694 case BFD_RELOC_32_PCREL
:
22696 case BFD_RELOC_32_SECREL
:
22698 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22700 /* For WinCE we only do this for pcrel fixups. */
22701 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22703 md_number_to_chars (buf
, value
, 4);
22707 case BFD_RELOC_ARM_PREL31
:
22708 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22710 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22711 if ((value
^ (value
>> 1)) & 0x40000000)
22713 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22714 _("rel31 relocation overflow"));
22716 newval
|= value
& 0x7fffffff;
22717 md_number_to_chars (buf
, newval
, 4);
22722 case BFD_RELOC_ARM_CP_OFF_IMM
:
22723 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22724 if (value
< -1023 || value
> 1023 || (value
& 3))
22725 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22726 _("co-processor offset out of range"));
22731 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22732 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22733 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22735 newval
= get_thumb32_insn (buf
);
22737 newval
&= 0xffffff00;
22740 newval
&= 0xff7fff00;
22741 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
22743 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22744 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22745 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22747 put_thumb32_insn (buf
, newval
);
22750 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
22751 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
22752 if (value
< -255 || value
> 255)
22753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22754 _("co-processor offset out of range"));
22756 goto cp_off_common
;
22758 case BFD_RELOC_ARM_THUMB_OFFSET
:
22759 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22760 /* Exactly what ranges, and where the offset is inserted depends
22761 on the type of instruction, we can establish this from the
22763 switch (newval
>> 12)
22765 case 4: /* PC load. */
22766 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22767 forced to zero for these loads; md_pcrel_from has already
22768 compensated for this. */
22770 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22771 _("invalid offset, target not word aligned (0x%08lX)"),
22772 (((unsigned long) fixP
->fx_frag
->fr_address
22773 + (unsigned long) fixP
->fx_where
) & ~3)
22774 + (unsigned long) value
);
22776 if (value
& ~0x3fc)
22777 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22778 _("invalid offset, value too big (0x%08lX)"),
22781 newval
|= value
>> 2;
22784 case 9: /* SP load/store. */
22785 if (value
& ~0x3fc)
22786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22787 _("invalid offset, value too big (0x%08lX)"),
22789 newval
|= value
>> 2;
22792 case 6: /* Word load/store. */
22794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22795 _("invalid offset, value too big (0x%08lX)"),
22797 newval
|= value
<< 4; /* 6 - 2. */
22800 case 7: /* Byte load/store. */
22802 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22803 _("invalid offset, value too big (0x%08lX)"),
22805 newval
|= value
<< 6;
22808 case 8: /* Halfword load/store. */
22810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22811 _("invalid offset, value too big (0x%08lX)"),
22813 newval
|= value
<< 5; /* 6 - 1. */
22817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22818 "Unable to process relocation for thumb opcode: %lx",
22819 (unsigned long) newval
);
22822 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22825 case BFD_RELOC_ARM_THUMB_ADD
:
22826 /* This is a complicated relocation, since we use it for all of
22827 the following immediate relocations:
22831 9bit ADD/SUB SP word-aligned
22832 10bit ADD PC/SP word-aligned
22834 The type of instruction being processed is encoded in the
22841 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22843 int rd
= (newval
>> 4) & 0xf;
22844 int rs
= newval
& 0xf;
22845 int subtract
= !!(newval
& 0x8000);
22847 /* Check for HI regs, only very restricted cases allowed:
22848 Adjusting SP, and using PC or SP to get an address. */
22849 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
22850 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
22851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22852 _("invalid Hi register with immediate"));
22854 /* If value is negative, choose the opposite instruction. */
22858 subtract
= !subtract
;
22860 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22861 _("immediate value out of range"));
22866 if (value
& ~0x1fc)
22867 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22868 _("invalid immediate for stack address calculation"));
22869 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
22870 newval
|= value
>> 2;
22872 else if (rs
== REG_PC
|| rs
== REG_SP
)
22874 if (subtract
|| value
& ~0x3fc)
22875 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22876 _("invalid immediate for address calculation (value = 0x%08lX)"),
22877 (unsigned long) value
);
22878 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
22880 newval
|= value
>> 2;
22885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22886 _("immediate value out of range"));
22887 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
22888 newval
|= (rd
<< 8) | value
;
22893 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22894 _("immediate value out of range"));
22895 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
22896 newval
|= rd
| (rs
<< 3) | (value
<< 6);
22899 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22902 case BFD_RELOC_ARM_THUMB_IMM
:
22903 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22904 if (value
< 0 || value
> 255)
22905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22906 _("invalid immediate: %ld is out of range"),
22909 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22912 case BFD_RELOC_ARM_THUMB_SHIFT
:
22913 /* 5bit shift value (0..32). LSL cannot take 32. */
22914 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
22915 temp
= newval
& 0xf800;
22916 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
22917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22918 _("invalid shift value: %ld"), (long) value
);
22919 /* Shifts of zero must be encoded as LSL. */
22921 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
22922 /* Shifts of 32 are encoded as zero. */
22923 else if (value
== 32)
22925 newval
|= value
<< 6;
22926 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22929 case BFD_RELOC_VTABLE_INHERIT
:
22930 case BFD_RELOC_VTABLE_ENTRY
:
22934 case BFD_RELOC_ARM_MOVW
:
22935 case BFD_RELOC_ARM_MOVT
:
22936 case BFD_RELOC_ARM_THUMB_MOVW
:
22937 case BFD_RELOC_ARM_THUMB_MOVT
:
22938 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22940 /* REL format relocations are limited to a 16-bit addend. */
22941 if (!fixP
->fx_done
)
22943 if (value
< -0x8000 || value
> 0x7fff)
22944 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22945 _("offset out of range"));
22947 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
22948 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
22953 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
22954 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
22956 newval
= get_thumb32_insn (buf
);
22957 newval
&= 0xfbf08f00;
22958 newval
|= (value
& 0xf000) << 4;
22959 newval
|= (value
& 0x0800) << 15;
22960 newval
|= (value
& 0x0700) << 4;
22961 newval
|= (value
& 0x00ff);
22962 put_thumb32_insn (buf
, newval
);
22966 newval
= md_chars_to_number (buf
, 4);
22967 newval
&= 0xfff0f000;
22968 newval
|= value
& 0x0fff;
22969 newval
|= (value
& 0xf000) << 4;
22970 md_number_to_chars (buf
, newval
, 4);
22975 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
22976 case BFD_RELOC_ARM_ALU_PC_G0
:
22977 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
22978 case BFD_RELOC_ARM_ALU_PC_G1
:
22979 case BFD_RELOC_ARM_ALU_PC_G2
:
22980 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
22981 case BFD_RELOC_ARM_ALU_SB_G0
:
22982 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
22983 case BFD_RELOC_ARM_ALU_SB_G1
:
22984 case BFD_RELOC_ARM_ALU_SB_G2
:
22985 gas_assert (!fixP
->fx_done
);
22986 if (!seg
->use_rela_p
)
22989 bfd_vma encoded_addend
;
22990 bfd_vma addend_abs
= abs (value
);
22992 /* Check that the absolute value of the addend can be
22993 expressed as an 8-bit constant plus a rotation. */
22994 encoded_addend
= encode_arm_immediate (addend_abs
);
22995 if (encoded_addend
== (unsigned int) FAIL
)
22996 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22997 _("the offset 0x%08lX is not representable"),
22998 (unsigned long) addend_abs
);
23000 /* Extract the instruction. */
23001 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23003 /* If the addend is positive, use an ADD instruction.
23004 Otherwise use a SUB. Take care not to destroy the S bit. */
23005 insn
&= 0xff1fffff;
23011 /* Place the encoded addend into the first 12 bits of the
23013 insn
&= 0xfffff000;
23014 insn
|= encoded_addend
;
23016 /* Update the instruction. */
23017 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23021 case BFD_RELOC_ARM_LDR_PC_G0
:
23022 case BFD_RELOC_ARM_LDR_PC_G1
:
23023 case BFD_RELOC_ARM_LDR_PC_G2
:
23024 case BFD_RELOC_ARM_LDR_SB_G0
:
23025 case BFD_RELOC_ARM_LDR_SB_G1
:
23026 case BFD_RELOC_ARM_LDR_SB_G2
:
23027 gas_assert (!fixP
->fx_done
);
23028 if (!seg
->use_rela_p
)
23031 bfd_vma addend_abs
= abs (value
);
23033 /* Check that the absolute value of the addend can be
23034 encoded in 12 bits. */
23035 if (addend_abs
>= 0x1000)
23036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23037 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23038 (unsigned long) addend_abs
);
23040 /* Extract the instruction. */
23041 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23043 /* If the addend is negative, clear bit 23 of the instruction.
23044 Otherwise set it. */
23046 insn
&= ~(1 << 23);
23050 /* Place the absolute value of the addend into the first 12 bits
23051 of the instruction. */
23052 insn
&= 0xfffff000;
23053 insn
|= addend_abs
;
23055 /* Update the instruction. */
23056 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23060 case BFD_RELOC_ARM_LDRS_PC_G0
:
23061 case BFD_RELOC_ARM_LDRS_PC_G1
:
23062 case BFD_RELOC_ARM_LDRS_PC_G2
:
23063 case BFD_RELOC_ARM_LDRS_SB_G0
:
23064 case BFD_RELOC_ARM_LDRS_SB_G1
:
23065 case BFD_RELOC_ARM_LDRS_SB_G2
:
23066 gas_assert (!fixP
->fx_done
);
23067 if (!seg
->use_rela_p
)
23070 bfd_vma addend_abs
= abs (value
);
23072 /* Check that the absolute value of the addend can be
23073 encoded in 8 bits. */
23074 if (addend_abs
>= 0x100)
23075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23076 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23077 (unsigned long) addend_abs
);
23079 /* Extract the instruction. */
23080 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23082 /* If the addend is negative, clear bit 23 of the instruction.
23083 Otherwise set it. */
23085 insn
&= ~(1 << 23);
23089 /* Place the first four bits of the absolute value of the addend
23090 into the first 4 bits of the instruction, and the remaining
23091 four into bits 8 .. 11. */
23092 insn
&= 0xfffff0f0;
23093 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23095 /* Update the instruction. */
23096 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23100 case BFD_RELOC_ARM_LDC_PC_G0
:
23101 case BFD_RELOC_ARM_LDC_PC_G1
:
23102 case BFD_RELOC_ARM_LDC_PC_G2
:
23103 case BFD_RELOC_ARM_LDC_SB_G0
:
23104 case BFD_RELOC_ARM_LDC_SB_G1
:
23105 case BFD_RELOC_ARM_LDC_SB_G2
:
23106 gas_assert (!fixP
->fx_done
);
23107 if (!seg
->use_rela_p
)
23110 bfd_vma addend_abs
= abs (value
);
23112 /* Check that the absolute value of the addend is a multiple of
23113 four and, when divided by four, fits in 8 bits. */
23114 if (addend_abs
& 0x3)
23115 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23116 _("bad offset 0x%08lX (must be word-aligned)"),
23117 (unsigned long) addend_abs
);
23119 if ((addend_abs
>> 2) > 0xff)
23120 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23121 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23122 (unsigned long) addend_abs
);
23124 /* Extract the instruction. */
23125 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23127 /* If the addend is negative, clear bit 23 of the instruction.
23128 Otherwise set it. */
23130 insn
&= ~(1 << 23);
23134 /* Place the addend (divided by four) into the first eight
23135 bits of the instruction. */
23136 insn
&= 0xfffffff0;
23137 insn
|= addend_abs
>> 2;
23139 /* Update the instruction. */
23140 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23144 case BFD_RELOC_ARM_V4BX
:
23145 /* This will need to go in the object file. */
23149 case BFD_RELOC_UNUSED
:
23151 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23152 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23156 /* Translate internal representation of relocation info to BFD target
23160 tc_gen_reloc (asection
*section
, fixS
*fixp
)
23163 bfd_reloc_code_real_type code
;
23165 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
23167 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
23168 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
23169 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
23171 if (fixp
->fx_pcrel
)
23173 if (section
->use_rela_p
)
23174 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
23176 fixp
->fx_offset
= reloc
->address
;
23178 reloc
->addend
= fixp
->fx_offset
;
23180 switch (fixp
->fx_r_type
)
23183 if (fixp
->fx_pcrel
)
23185 code
= BFD_RELOC_8_PCREL
;
23190 if (fixp
->fx_pcrel
)
23192 code
= BFD_RELOC_16_PCREL
;
23197 if (fixp
->fx_pcrel
)
23199 code
= BFD_RELOC_32_PCREL
;
23203 case BFD_RELOC_ARM_MOVW
:
23204 if (fixp
->fx_pcrel
)
23206 code
= BFD_RELOC_ARM_MOVW_PCREL
;
23210 case BFD_RELOC_ARM_MOVT
:
23211 if (fixp
->fx_pcrel
)
23213 code
= BFD_RELOC_ARM_MOVT_PCREL
;
23217 case BFD_RELOC_ARM_THUMB_MOVW
:
23218 if (fixp
->fx_pcrel
)
23220 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
23224 case BFD_RELOC_ARM_THUMB_MOVT
:
23225 if (fixp
->fx_pcrel
)
23227 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
23231 case BFD_RELOC_NONE
:
23232 case BFD_RELOC_ARM_PCREL_BRANCH
:
23233 case BFD_RELOC_ARM_PCREL_BLX
:
23234 case BFD_RELOC_RVA
:
23235 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23236 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23237 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23238 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23239 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23240 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23241 case BFD_RELOC_VTABLE_ENTRY
:
23242 case BFD_RELOC_VTABLE_INHERIT
:
23244 case BFD_RELOC_32_SECREL
:
23246 code
= fixp
->fx_r_type
;
23249 case BFD_RELOC_THUMB_PCREL_BLX
:
23251 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23252 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23255 code
= BFD_RELOC_THUMB_PCREL_BLX
;
23258 case BFD_RELOC_ARM_LITERAL
:
23259 case BFD_RELOC_ARM_HWLITERAL
:
23260 /* If this is called then the a literal has
23261 been referenced across a section boundary. */
23262 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23263 _("literal referenced across section boundary"));
23267 case BFD_RELOC_ARM_TLS_CALL
:
23268 case BFD_RELOC_ARM_THM_TLS_CALL
:
23269 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23270 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23271 case BFD_RELOC_ARM_GOT32
:
23272 case BFD_RELOC_ARM_GOTOFF
:
23273 case BFD_RELOC_ARM_GOT_PREL
:
23274 case BFD_RELOC_ARM_PLT32
:
23275 case BFD_RELOC_ARM_TARGET1
:
23276 case BFD_RELOC_ARM_ROSEGREL32
:
23277 case BFD_RELOC_ARM_SBREL32
:
23278 case BFD_RELOC_ARM_PREL31
:
23279 case BFD_RELOC_ARM_TARGET2
:
23280 case BFD_RELOC_ARM_TLS_LE32
:
23281 case BFD_RELOC_ARM_TLS_LDO32
:
23282 case BFD_RELOC_ARM_PCREL_CALL
:
23283 case BFD_RELOC_ARM_PCREL_JUMP
:
23284 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23285 case BFD_RELOC_ARM_ALU_PC_G0
:
23286 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23287 case BFD_RELOC_ARM_ALU_PC_G1
:
23288 case BFD_RELOC_ARM_ALU_PC_G2
:
23289 case BFD_RELOC_ARM_LDR_PC_G0
:
23290 case BFD_RELOC_ARM_LDR_PC_G1
:
23291 case BFD_RELOC_ARM_LDR_PC_G2
:
23292 case BFD_RELOC_ARM_LDRS_PC_G0
:
23293 case BFD_RELOC_ARM_LDRS_PC_G1
:
23294 case BFD_RELOC_ARM_LDRS_PC_G2
:
23295 case BFD_RELOC_ARM_LDC_PC_G0
:
23296 case BFD_RELOC_ARM_LDC_PC_G1
:
23297 case BFD_RELOC_ARM_LDC_PC_G2
:
23298 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23299 case BFD_RELOC_ARM_ALU_SB_G0
:
23300 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23301 case BFD_RELOC_ARM_ALU_SB_G1
:
23302 case BFD_RELOC_ARM_ALU_SB_G2
:
23303 case BFD_RELOC_ARM_LDR_SB_G0
:
23304 case BFD_RELOC_ARM_LDR_SB_G1
:
23305 case BFD_RELOC_ARM_LDR_SB_G2
:
23306 case BFD_RELOC_ARM_LDRS_SB_G0
:
23307 case BFD_RELOC_ARM_LDRS_SB_G1
:
23308 case BFD_RELOC_ARM_LDRS_SB_G2
:
23309 case BFD_RELOC_ARM_LDC_SB_G0
:
23310 case BFD_RELOC_ARM_LDC_SB_G1
:
23311 case BFD_RELOC_ARM_LDC_SB_G2
:
23312 case BFD_RELOC_ARM_V4BX
:
23313 code
= fixp
->fx_r_type
;
23316 case BFD_RELOC_ARM_TLS_GOTDESC
:
23317 case BFD_RELOC_ARM_TLS_GD32
:
23318 case BFD_RELOC_ARM_TLS_IE32
:
23319 case BFD_RELOC_ARM_TLS_LDM32
:
23320 /* BFD will include the symbol's address in the addend.
23321 But we don't want that, so subtract it out again here. */
23322 if (!S_IS_COMMON (fixp
->fx_addsy
))
23323 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23324 code
= fixp
->fx_r_type
;
23328 case BFD_RELOC_ARM_IMMEDIATE
:
23329 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23330 _("internal relocation (type: IMMEDIATE) not fixed up"));
23333 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23334 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23335 _("ADRL used for a symbol not defined in the same file"));
23338 case BFD_RELOC_ARM_OFFSET_IMM
:
23339 if (section
->use_rela_p
)
23341 code
= fixp
->fx_r_type
;
23345 if (fixp
->fx_addsy
!= NULL
23346 && !S_IS_DEFINED (fixp
->fx_addsy
)
23347 && S_IS_LOCAL (fixp
->fx_addsy
))
23349 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23350 _("undefined local label `%s'"),
23351 S_GET_NAME (fixp
->fx_addsy
));
23355 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23356 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23363 switch (fixp
->fx_r_type
)
23365 case BFD_RELOC_NONE
: type
= "NONE"; break;
23366 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23367 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23368 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23369 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23370 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23371 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23372 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23373 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23374 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23375 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23376 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23377 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23378 default: type
= _("<unknown>"); break;
23380 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23381 _("cannot represent %s relocation in this object file format"),
23388 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23390 && fixp
->fx_addsy
== GOT_symbol
)
23392 code
= BFD_RELOC_ARM_GOTPC
;
23393 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23397 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23399 if (reloc
->howto
== NULL
)
23401 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23402 _("cannot represent %s relocation in this object file format"),
23403 bfd_get_reloc_code_name (code
));
23407 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23408 vtable entry to be used in the relocation's section offset. */
23409 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23410 reloc
->address
= fixp
->fx_offset
;
23415 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23418 cons_fix_new_arm (fragS
* frag
,
23422 bfd_reloc_code_real_type reloc
)
23427 FIXME: @@ Should look at CPU word size. */
23431 reloc
= BFD_RELOC_8
;
23434 reloc
= BFD_RELOC_16
;
23438 reloc
= BFD_RELOC_32
;
23441 reloc
= BFD_RELOC_64
;
23446 if (exp
->X_op
== O_secrel
)
23448 exp
->X_op
= O_symbol
;
23449 reloc
= BFD_RELOC_32_SECREL
;
23453 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
23456 #if defined (OBJ_COFF)
23458 arm_validate_fix (fixS
* fixP
)
23460 /* If the destination of the branch is a defined symbol which does not have
23461 the THUMB_FUNC attribute, then we must be calling a function which has
23462 the (interfacearm) attribute. We look for the Thumb entry point to that
23463 function and change the branch to refer to that function instead. */
23464 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23465 && fixP
->fx_addsy
!= NULL
23466 && S_IS_DEFINED (fixP
->fx_addsy
)
23467 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23469 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23476 arm_force_relocation (struct fix
* fixp
)
23478 #if defined (OBJ_COFF) && defined (TE_PE)
23479 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23483 /* In case we have a call or a branch to a function in ARM ISA mode from
23484 a thumb function or vice-versa force the relocation. These relocations
23485 are cleared off for some cores that might have blx and simple transformations
23489 switch (fixp
->fx_r_type
)
23491 case BFD_RELOC_ARM_PCREL_JUMP
:
23492 case BFD_RELOC_ARM_PCREL_CALL
:
23493 case BFD_RELOC_THUMB_PCREL_BLX
:
23494 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23498 case BFD_RELOC_ARM_PCREL_BLX
:
23499 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23500 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23501 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23502 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23511 /* Resolve these relocations even if the symbol is extern or weak.
23512 Technically this is probably wrong due to symbol preemption.
23513 In practice these relocations do not have enough range to be useful
23514 at dynamic link time, and some code (e.g. in the Linux kernel)
23515 expects these references to be resolved. */
23516 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23517 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23518 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23519 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23520 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23521 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23522 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23523 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23524 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23525 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23526 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23527 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23528 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23529 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23532 /* Always leave these relocations for the linker. */
23533 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23534 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23535 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23538 /* Always generate relocations against function symbols. */
23539 if (fixp
->fx_r_type
== BFD_RELOC_32
23541 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23544 return generic_force_reloc (fixp
);
23547 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23548 /* Relocations against function names must be left unadjusted,
23549 so that the linker can use this information to generate interworking
23550 stubs. The MIPS version of this function
23551 also prevents relocations that are mips-16 specific, but I do not
23552 know why it does this.
23555 There is one other problem that ought to be addressed here, but
23556 which currently is not: Taking the address of a label (rather
23557 than a function) and then later jumping to that address. Such
23558 addresses also ought to have their bottom bit set (assuming that
23559 they reside in Thumb code), but at the moment they will not. */
23562 arm_fix_adjustable (fixS
* fixP
)
23564 if (fixP
->fx_addsy
== NULL
)
23567 /* Preserve relocations against symbols with function type. */
23568 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23571 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23572 && fixP
->fx_subsy
== NULL
)
23575 /* We need the symbol name for the VTABLE entries. */
23576 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23577 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23580 /* Don't allow symbols to be discarded on GOT related relocs. */
23581 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23582 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23583 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23584 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23585 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23586 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23587 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23588 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23589 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23590 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23591 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23592 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23593 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23594 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23597 /* Similarly for group relocations. */
23598 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23599 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23600 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23603 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23604 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23605 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23606 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23607 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23608 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23609 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23610 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23611 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23616 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23621 elf32_arm_target_format (void)
23624 return (target_big_endian
23625 ? "elf32-bigarm-symbian"
23626 : "elf32-littlearm-symbian");
23627 #elif defined (TE_VXWORKS)
23628 return (target_big_endian
23629 ? "elf32-bigarm-vxworks"
23630 : "elf32-littlearm-vxworks");
23631 #elif defined (TE_NACL)
23632 return (target_big_endian
23633 ? "elf32-bigarm-nacl"
23634 : "elf32-littlearm-nacl");
23636 if (target_big_endian
)
23637 return "elf32-bigarm";
23639 return "elf32-littlearm";
23644 armelf_frob_symbol (symbolS
* symp
,
23647 elf_frob_symbol (symp
, puntp
);
23651 /* MD interface: Finalization. */
23656 literal_pool
* pool
;
23658 /* Ensure that all the IT blocks are properly closed. */
23659 check_it_blocks_finished ();
23661 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
23663 /* Put it at the end of the relevant section. */
23664 subseg_set (pool
->section
, pool
->sub_section
);
23666 arm_elf_change_section ();
23673 /* Remove any excess mapping symbols generated for alignment frags in
23674 SEC. We may have created a mapping symbol before a zero byte
23675 alignment; remove it if there's a mapping symbol after the
23678 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
23679 void *dummy ATTRIBUTE_UNUSED
)
23681 segment_info_type
*seginfo
= seg_info (sec
);
23684 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
23687 for (fragp
= seginfo
->frchainP
->frch_root
;
23689 fragp
= fragp
->fr_next
)
23691 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
23692 fragS
*next
= fragp
->fr_next
;
23694 /* Variable-sized frags have been converted to fixed size by
23695 this point. But if this was variable-sized to start with,
23696 there will be a fixed-size frag after it. So don't handle
23698 if (sym
== NULL
|| next
== NULL
)
23701 if (S_GET_VALUE (sym
) < next
->fr_address
)
23702 /* Not at the end of this frag. */
23704 know (S_GET_VALUE (sym
) == next
->fr_address
);
23708 if (next
->tc_frag_data
.first_map
!= NULL
)
23710 /* Next frag starts with a mapping symbol. Discard this
23712 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23716 if (next
->fr_next
== NULL
)
23718 /* This mapping symbol is at the end of the section. Discard
23720 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
23721 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23725 /* As long as we have empty frags without any mapping symbols,
23727 /* If the next frag is non-empty and does not start with a
23728 mapping symbol, then this mapping symbol is required. */
23729 if (next
->fr_address
!= next
->fr_next
->fr_address
)
23732 next
= next
->fr_next
;
23734 while (next
!= NULL
);
23739 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23743 arm_adjust_symtab (void)
23748 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23750 if (ARM_IS_THUMB (sym
))
23752 if (THUMB_IS_FUNC (sym
))
23754 /* Mark the symbol as a Thumb function. */
23755 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
23756 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
23757 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
23759 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
23760 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
23762 as_bad (_("%s: unexpected function type: %d"),
23763 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
23765 else switch (S_GET_STORAGE_CLASS (sym
))
23768 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
23771 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
23774 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
23782 if (ARM_IS_INTERWORK (sym
))
23783 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
23790 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23792 if (ARM_IS_THUMB (sym
))
23794 elf_symbol_type
* elf_sym
;
23796 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
23797 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
23799 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
23800 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
23802 /* If it's a .thumb_func, declare it as so,
23803 otherwise tag label as .code 16. */
23804 if (THUMB_IS_FUNC (sym
))
23805 elf_sym
->internal_elf_sym
.st_target_internal
23806 = ST_BRANCH_TO_THUMB
;
23807 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23808 elf_sym
->internal_elf_sym
.st_info
=
23809 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
23814 /* Remove any overlapping mapping symbols generated by alignment frags. */
23815 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
23816 /* Now do generic ELF adjustments. */
23817 elf_adjust_symtab ();
23821 /* MD interface: Initialization. */
23824 set_constant_flonums (void)
23828 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
23829 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
23833 /* Auto-select Thumb mode if it's the only available instruction set for the
23834 given architecture. */
23837 autoselect_thumb_from_cpu_variant (void)
23839 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23840 opcode_select (16);
23849 if ( (arm_ops_hsh
= hash_new ()) == NULL
23850 || (arm_cond_hsh
= hash_new ()) == NULL
23851 || (arm_shift_hsh
= hash_new ()) == NULL
23852 || (arm_psr_hsh
= hash_new ()) == NULL
23853 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
23854 || (arm_reg_hsh
= hash_new ()) == NULL
23855 || (arm_reloc_hsh
= hash_new ()) == NULL
23856 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
23857 as_fatal (_("virtual memory exhausted"));
23859 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
23860 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
23861 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
23862 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
23863 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
23864 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
23865 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
23866 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
23867 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
23868 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
23869 (void *) (v7m_psrs
+ i
));
23870 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
23871 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
23873 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
23875 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
23876 (void *) (barrier_opt_names
+ i
));
23878 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
23880 struct reloc_entry
* entry
= reloc_names
+ i
;
23882 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
23883 /* This makes encode_branch() use the EABI versions of this relocation. */
23884 entry
->reloc
= BFD_RELOC_UNUSED
;
23886 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
23890 set_constant_flonums ();
23892 /* Set the cpu variant based on the command-line options. We prefer
23893 -mcpu= over -march= if both are set (as for GCC); and we prefer
23894 -mfpu= over any other way of setting the floating point unit.
23895 Use of legacy options with new options are faulted. */
23898 if (mcpu_cpu_opt
|| march_cpu_opt
)
23899 as_bad (_("use of old and new-style options to set CPU type"));
23901 mcpu_cpu_opt
= legacy_cpu
;
23903 else if (!mcpu_cpu_opt
)
23904 mcpu_cpu_opt
= march_cpu_opt
;
23909 as_bad (_("use of old and new-style options to set FPU type"));
23911 mfpu_opt
= legacy_fpu
;
23913 else if (!mfpu_opt
)
23915 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23916 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23917 /* Some environments specify a default FPU. If they don't, infer it
23918 from the processor. */
23920 mfpu_opt
= mcpu_fpu_opt
;
23922 mfpu_opt
= march_fpu_opt
;
23924 mfpu_opt
= &fpu_default
;
23930 if (mcpu_cpu_opt
!= NULL
)
23931 mfpu_opt
= &fpu_default
;
23932 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
23933 mfpu_opt
= &fpu_arch_vfp_v2
;
23935 mfpu_opt
= &fpu_arch_fpa
;
23941 mcpu_cpu_opt
= &cpu_default
;
23942 selected_cpu
= cpu_default
;
23946 selected_cpu
= *mcpu_cpu_opt
;
23948 mcpu_cpu_opt
= &arm_arch_any
;
23951 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23953 autoselect_thumb_from_cpu_variant ();
23955 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
23957 #if defined OBJ_COFF || defined OBJ_ELF
23959 unsigned int flags
= 0;
23961 #if defined OBJ_ELF
23962 flags
= meabi_flags
;
23964 switch (meabi_flags
)
23966 case EF_ARM_EABI_UNKNOWN
:
23968 /* Set the flags in the private structure. */
23969 if (uses_apcs_26
) flags
|= F_APCS26
;
23970 if (support_interwork
) flags
|= F_INTERWORK
;
23971 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
23972 if (pic_code
) flags
|= F_PIC
;
23973 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
23974 flags
|= F_SOFT_FLOAT
;
23976 switch (mfloat_abi_opt
)
23978 case ARM_FLOAT_ABI_SOFT
:
23979 case ARM_FLOAT_ABI_SOFTFP
:
23980 flags
|= F_SOFT_FLOAT
;
23983 case ARM_FLOAT_ABI_HARD
:
23984 if (flags
& F_SOFT_FLOAT
)
23985 as_bad (_("hard-float conflicts with specified fpu"));
23989 /* Using pure-endian doubles (even if soft-float). */
23990 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
23991 flags
|= F_VFP_FLOAT
;
23993 #if defined OBJ_ELF
23994 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
23995 flags
|= EF_ARM_MAVERICK_FLOAT
;
23998 case EF_ARM_EABI_VER4
:
23999 case EF_ARM_EABI_VER5
:
24000 /* No additional flags to set. */
24007 bfd_set_private_flags (stdoutput
, flags
);
24009 /* We have run out flags in the COFF header to encode the
24010 status of ATPCS support, so instead we create a dummy,
24011 empty, debug section called .arm.atpcs. */
24016 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24020 bfd_set_section_flags
24021 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24022 bfd_set_section_size (stdoutput
, sec
, 0);
24023 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24029 /* Record the CPU type as well. */
24030 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24031 mach
= bfd_mach_arm_iWMMXt2
;
24032 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24033 mach
= bfd_mach_arm_iWMMXt
;
24034 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24035 mach
= bfd_mach_arm_XScale
;
24036 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24037 mach
= bfd_mach_arm_ep9312
;
24038 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24039 mach
= bfd_mach_arm_5TE
;
24040 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24042 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24043 mach
= bfd_mach_arm_5T
;
24045 mach
= bfd_mach_arm_5
;
24047 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24049 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24050 mach
= bfd_mach_arm_4T
;
24052 mach
= bfd_mach_arm_4
;
24054 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24055 mach
= bfd_mach_arm_3M
;
24056 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24057 mach
= bfd_mach_arm_3
;
24058 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24059 mach
= bfd_mach_arm_2a
;
24060 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24061 mach
= bfd_mach_arm_2
;
24063 mach
= bfd_mach_arm_unknown
;
24065 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24068 /* Command line processing. */
24071 Invocation line includes a switch not recognized by the base assembler.
24072 See if it's a processor-specific option.
24074 This routine is somewhat complicated by the need for backwards
24075 compatibility (since older releases of gcc can't be changed).
24076 The new options try to make the interface as compatible as
24079 New options (supported) are:
24081 -mcpu=<cpu name> Assemble for selected processor
24082 -march=<architecture name> Assemble for selected architecture
24083 -mfpu=<fpu architecture> Assemble for selected FPU.
24084 -EB/-mbig-endian Big-endian
24085 -EL/-mlittle-endian Little-endian
24086 -k Generate PIC code
24087 -mthumb Start in Thumb mode
24088 -mthumb-interwork Code supports ARM/Thumb interworking
24090 -m[no-]warn-deprecated Warn about deprecated features
24092 For now we will also provide support for:
24094 -mapcs-32 32-bit Program counter
24095 -mapcs-26 26-bit Program counter
24096 -macps-float Floats passed in FP registers
24097 -mapcs-reentrant Reentrant code
24099 (sometime these will probably be replaced with -mapcs=<list of options>
24100 and -matpcs=<list of options>)
24102 The remaining options are only supported for back-wards compatibility.
24103 Cpu variants, the arm part is optional:
24104 -m[arm]1 Currently not supported.
24105 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24106 -m[arm]3 Arm 3 processor
24107 -m[arm]6[xx], Arm 6 processors
24108 -m[arm]7[xx][t][[d]m] Arm 7 processors
24109 -m[arm]8[10] Arm 8 processors
24110 -m[arm]9[20][tdmi] Arm 9 processors
24111 -mstrongarm[110[0]] StrongARM processors
24112 -mxscale XScale processors
24113 -m[arm]v[2345[t[e]]] Arm architectures
24114 -mall All (except the ARM1)
24116 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24117 -mfpe-old (No float load/store multiples)
24118 -mvfpxd VFP Single precision
24120 -mno-fpu Disable all floating point instructions
24122 The following CPU names are recognized:
24123 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24124 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24125 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24126 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24127 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24128 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24129 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24133 const char * md_shortopts
= "m:k";
24135 #ifdef ARM_BI_ENDIAN
24136 #define OPTION_EB (OPTION_MD_BASE + 0)
24137 #define OPTION_EL (OPTION_MD_BASE + 1)
24139 #if TARGET_BYTES_BIG_ENDIAN
24140 #define OPTION_EB (OPTION_MD_BASE + 0)
24142 #define OPTION_EL (OPTION_MD_BASE + 1)
24145 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24147 struct option md_longopts
[] =
24150 {"EB", no_argument
, NULL
, OPTION_EB
},
24153 {"EL", no_argument
, NULL
, OPTION_EL
},
24155 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
24156 {NULL
, no_argument
, NULL
, 0}
24159 size_t md_longopts_size
= sizeof (md_longopts
);
24161 struct arm_option_table
24163 char *option
; /* Option name to match. */
24164 char *help
; /* Help information. */
24165 int *var
; /* Variable to change. */
24166 int value
; /* What to change it to. */
24167 char *deprecated
; /* If non-null, print this message. */
24170 struct arm_option_table arm_opts
[] =
24172 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
24173 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
24174 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24175 &support_interwork
, 1, NULL
},
24176 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
24177 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
24178 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
24180 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
24181 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
24182 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
24183 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
24186 /* These are recognized by the assembler, but have no affect on code. */
24187 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
24188 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
24190 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
24191 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24192 &warn_on_deprecated
, 0, NULL
},
24193 {NULL
, NULL
, NULL
, 0, NULL
}
24196 struct arm_legacy_option_table
24198 char *option
; /* Option name to match. */
24199 const arm_feature_set
**var
; /* Variable to change. */
24200 const arm_feature_set value
; /* What to change it to. */
24201 char *deprecated
; /* If non-null, print this message. */
24204 const struct arm_legacy_option_table arm_legacy_opts
[] =
24206 /* DON'T add any new processors to this list -- we want the whole list
24207 to go away... Add them to the processors table instead. */
24208 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24209 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24210 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24211 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24212 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24213 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24214 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24215 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24216 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24217 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24218 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24219 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24220 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24221 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24222 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24223 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24224 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24225 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24226 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24227 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24228 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24229 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24230 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24231 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24232 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24233 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24234 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24235 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24236 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24237 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24238 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24239 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24240 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24241 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24242 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24243 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24244 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24245 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24246 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24247 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24248 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24249 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24250 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24251 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24252 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24253 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24254 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24255 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24256 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24257 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24258 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24259 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24260 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24261 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24262 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24263 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24264 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24265 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24266 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24267 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24268 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24269 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24270 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24271 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24272 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24273 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24274 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24275 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24276 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24277 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24278 N_("use -mcpu=strongarm110")},
24279 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24280 N_("use -mcpu=strongarm1100")},
24281 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24282 N_("use -mcpu=strongarm1110")},
24283 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24284 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24285 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24287 /* Architecture variants -- don't add any more to this list either. */
24288 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24289 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24290 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24291 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24292 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24293 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24294 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24295 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24296 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24297 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24298 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24299 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24300 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24301 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24302 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24303 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24304 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24305 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24307 /* Floating point variants -- don't add any more to this list either. */
24308 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24309 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24310 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24311 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24312 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24314 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24317 struct arm_cpu_option_table
24321 const arm_feature_set value
;
24322 /* For some CPUs we assume an FPU unless the user explicitly sets
24324 const arm_feature_set default_fpu
;
24325 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24327 const char *canonical_name
;
24330 /* This list should, at a minimum, contain all the cpu names
24331 recognized by GCC. */
24332 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24333 static const struct arm_cpu_option_table arm_cpus
[] =
24335 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24336 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24337 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24338 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24339 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24340 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24341 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24342 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24343 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24344 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24345 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24346 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24347 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24348 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24349 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24350 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24351 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24352 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24353 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24354 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24355 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24356 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24357 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24358 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24359 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24360 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24361 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24362 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24363 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24364 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24365 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24366 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24367 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24368 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24369 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24370 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24371 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24372 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24373 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24374 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24375 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24376 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24377 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24378 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24379 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24380 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24381 /* For V5 or later processors we default to using VFP; but the user
24382 should really set the FPU type explicitly. */
24383 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24384 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24385 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24386 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24387 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24388 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24389 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24390 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24391 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24392 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24393 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24394 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24395 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24396 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24397 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24398 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24399 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24400 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24401 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24402 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24404 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24405 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24406 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24407 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24408 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24409 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24410 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24411 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24412 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24414 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24415 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24416 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24417 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24418 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24419 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
),
24420 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
),
24421 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24422 FPU_NONE
, "Cortex-A5"),
24423 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24425 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24426 ARM_FEATURE (0, FPU_VFP_V3
24427 | FPU_NEON_EXT_V1
),
24429 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24430 ARM_FEATURE (0, FPU_VFP_V3
24431 | FPU_NEON_EXT_V1
),
24433 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24435 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24437 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24439 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24441 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24443 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24444 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24446 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24447 FPU_NONE
, "Cortex-R5"),
24448 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24449 FPU_ARCH_VFP_V3D16
,
24451 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
24452 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24453 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24454 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24455 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24456 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24457 /* ??? XSCALE is really an architecture. */
24458 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24459 /* ??? iwmmxt is not a processor. */
24460 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24461 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24462 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24464 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24465 FPU_ARCH_MAVERICK
, "ARM920T"),
24466 /* Marvell processors. */
24467 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A
| ARM_EXT_MP
| ARM_EXT_SEC
, 0),
24468 FPU_ARCH_VFP_V3D16
, NULL
),
24469 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE (ARM_AEXT_V7A
| ARM_EXT_MP
24471 FPU_ARCH_NEON_VFP_V4
, NULL
),
24472 /* APM X-Gene family. */
24473 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24475 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24478 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24482 struct arm_arch_option_table
24486 const arm_feature_set value
;
24487 const arm_feature_set default_fpu
;
24490 /* This list should, at a minimum, contain all the architecture names
24491 recognized by GCC. */
24492 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24493 static const struct arm_arch_option_table arm_archs
[] =
24495 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24496 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24497 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24498 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24499 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24500 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24501 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24502 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24503 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24504 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24505 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24506 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24507 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24508 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24509 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24510 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24511 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24512 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24513 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24514 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24515 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24516 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
),
24517 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24518 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24519 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24520 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
),
24521 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24522 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24523 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24524 /* The official spelling of the ARMv7 profile variants is the dashed form.
24525 Accept the non-dashed form for compatibility with old toolchains. */
24526 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24527 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24528 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24529 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24530 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24531 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24532 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24533 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24534 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24535 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24536 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24537 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24538 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24540 #undef ARM_ARCH_OPT
24542 /* ISA extensions in the co-processor and main instruction set space. */
24543 struct arm_option_extension_value_table
24547 const arm_feature_set merge_value
;
24548 const arm_feature_set clear_value
;
24549 const arm_feature_set allowed_archs
;
24552 /* The following table must be in alphabetical order with a NULL last entry.
24554 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
24555 static const struct arm_option_extension_value_table arm_extensions
[] =
24557 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE (0, CRC_EXT_ARMV8
),
24558 ARM_FEATURE (ARM_EXT_V8
, 0)),
24559 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24560 ARM_FEATURE (0, FPU_CRYPTO_ARMV8
),
24561 ARM_FEATURE (ARM_EXT_V8
, 0)),
24562 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE (0, FPU_VFP_ARMV8
),
24563 ARM_FEATURE (ARM_EXT_V8
, 0)),
24564 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
24565 ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
24566 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
24567 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT
),
24568 ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
),
24569 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
),
24570 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
),
24571 ARM_EXT_OPT ("maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
),
24572 ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
),
24573 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP
, 0),
24574 ARM_FEATURE (ARM_EXT_MP
, 0),
24575 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
24576 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24577 ARM_FEATURE(0, FPU_NEON_ARMV8
),
24578 ARM_FEATURE (ARM_EXT_V8
, 0)),
24579 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS
, 0),
24580 ARM_FEATURE (ARM_EXT_OS
, 0),
24581 ARM_FEATURE (ARM_EXT_V6M
, 0)),
24582 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
24583 ARM_FEATURE (ARM_EXT_SEC
, 0),
24584 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)),
24585 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
24587 ARM_FEATURE (ARM_EXT_VIRT
, 0),
24588 ARM_FEATURE (ARM_EXT_V7A
, 0)),
24589 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE
),
24590 ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
),
24591 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24595 /* ISA floating-point and Advanced SIMD extensions. */
24596 struct arm_option_fpu_value_table
24599 const arm_feature_set value
;
24602 /* This list should, at a minimum, contain all the fpu names
24603 recognized by GCC. */
24604 static const struct arm_option_fpu_value_table arm_fpus
[] =
24606 {"softfpa", FPU_NONE
},
24607 {"fpe", FPU_ARCH_FPE
},
24608 {"fpe2", FPU_ARCH_FPE
},
24609 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
24610 {"fpa", FPU_ARCH_FPA
},
24611 {"fpa10", FPU_ARCH_FPA
},
24612 {"fpa11", FPU_ARCH_FPA
},
24613 {"arm7500fe", FPU_ARCH_FPA
},
24614 {"softvfp", FPU_ARCH_VFP
},
24615 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
24616 {"vfp", FPU_ARCH_VFP_V2
},
24617 {"vfp9", FPU_ARCH_VFP_V2
},
24618 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
24619 {"vfp10", FPU_ARCH_VFP_V2
},
24620 {"vfp10-r0", FPU_ARCH_VFP_V1
},
24621 {"vfpxd", FPU_ARCH_VFP_V1xD
},
24622 {"vfpv2", FPU_ARCH_VFP_V2
},
24623 {"vfpv3", FPU_ARCH_VFP_V3
},
24624 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
24625 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
24626 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
24627 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
24628 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
24629 {"arm1020t", FPU_ARCH_VFP_V1
},
24630 {"arm1020e", FPU_ARCH_VFP_V2
},
24631 {"arm1136jfs", FPU_ARCH_VFP_V2
},
24632 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
24633 {"maverick", FPU_ARCH_MAVERICK
},
24634 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
24635 {"neon-fp16", FPU_ARCH_NEON_FP16
},
24636 {"vfpv4", FPU_ARCH_VFP_V4
},
24637 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
24638 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
24639 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
24640 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
24641 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
24642 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
24643 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
24644 {"crypto-neon-fp-armv8",
24645 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
24646 {NULL
, ARM_ARCH_NONE
}
24649 struct arm_option_value_table
24655 static const struct arm_option_value_table arm_float_abis
[] =
24657 {"hard", ARM_FLOAT_ABI_HARD
},
24658 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
24659 {"soft", ARM_FLOAT_ABI_SOFT
},
24664 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24665 static const struct arm_option_value_table arm_eabis
[] =
24667 {"gnu", EF_ARM_EABI_UNKNOWN
},
24668 {"4", EF_ARM_EABI_VER4
},
24669 {"5", EF_ARM_EABI_VER5
},
24674 struct arm_long_option_table
24676 char * option
; /* Substring to match. */
24677 char * help
; /* Help information. */
24678 int (* func
) (char * subopt
); /* Function to decode sub-option. */
24679 char * deprecated
; /* If non-null, print this message. */
24683 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
24685 arm_feature_set
*ext_set
= (arm_feature_set
*)
24686 xmalloc (sizeof (arm_feature_set
));
24688 /* We insist on extensions being specified in alphabetical order, and with
24689 extensions being added before being removed. We achieve this by having
24690 the global ARM_EXTENSIONS table in alphabetical order, and using the
24691 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24692 or removing it (0) and only allowing it to change in the order
24694 const struct arm_option_extension_value_table
* opt
= NULL
;
24695 int adding_value
= -1;
24697 /* Copy the feature set, so that we can modify it. */
24698 *ext_set
= **opt_p
;
24701 while (str
!= NULL
&& *str
!= 0)
24708 as_bad (_("invalid architectural extension"));
24713 ext
= strchr (str
, '+');
24718 len
= strlen (str
);
24720 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
24722 if (adding_value
!= 0)
24725 opt
= arm_extensions
;
24733 if (adding_value
== -1)
24736 opt
= arm_extensions
;
24738 else if (adding_value
!= 1)
24740 as_bad (_("must specify extensions to add before specifying "
24741 "those to remove"));
24748 as_bad (_("missing architectural extension"));
24752 gas_assert (adding_value
!= -1);
24753 gas_assert (opt
!= NULL
);
24755 /* Scan over the options table trying to find an exact match. */
24756 for (; opt
->name
!= NULL
; opt
++)
24757 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24759 /* Check we can apply the extension to this architecture. */
24760 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
24762 as_bad (_("extension does not apply to the base architecture"));
24766 /* Add or remove the extension. */
24768 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
24770 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
24775 if (opt
->name
== NULL
)
24777 /* Did we fail to find an extension because it wasn't specified in
24778 alphabetical order, or because it does not exist? */
24780 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
24781 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24784 if (opt
->name
== NULL
)
24785 as_bad (_("unknown architectural extension `%s'"), str
);
24787 as_bad (_("architectural extensions must be specified in "
24788 "alphabetical order"));
24794 /* We should skip the extension we've just matched the next time
24806 arm_parse_cpu (char *str
)
24808 const struct arm_cpu_option_table
*opt
;
24809 char *ext
= strchr (str
, '+');
24815 len
= strlen (str
);
24819 as_bad (_("missing cpu name `%s'"), str
);
24823 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
24824 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24826 mcpu_cpu_opt
= &opt
->value
;
24827 mcpu_fpu_opt
= &opt
->default_fpu
;
24828 if (opt
->canonical_name
)
24829 strcpy (selected_cpu_name
, opt
->canonical_name
);
24834 for (i
= 0; i
< len
; i
++)
24835 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
24836 selected_cpu_name
[i
] = 0;
24840 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
24845 as_bad (_("unknown cpu `%s'"), str
);
24850 arm_parse_arch (char *str
)
24852 const struct arm_arch_option_table
*opt
;
24853 char *ext
= strchr (str
, '+');
24859 len
= strlen (str
);
24863 as_bad (_("missing architecture name `%s'"), str
);
24867 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
24868 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24870 march_cpu_opt
= &opt
->value
;
24871 march_fpu_opt
= &opt
->default_fpu
;
24872 strcpy (selected_cpu_name
, opt
->name
);
24875 return arm_parse_extension (ext
, &march_cpu_opt
);
24880 as_bad (_("unknown architecture `%s'\n"), str
);
24885 arm_parse_fpu (char * str
)
24887 const struct arm_option_fpu_value_table
* opt
;
24889 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
24890 if (streq (opt
->name
, str
))
24892 mfpu_opt
= &opt
->value
;
24896 as_bad (_("unknown floating point format `%s'\n"), str
);
24901 arm_parse_float_abi (char * str
)
24903 const struct arm_option_value_table
* opt
;
24905 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
24906 if (streq (opt
->name
, str
))
24908 mfloat_abi_opt
= opt
->value
;
24912 as_bad (_("unknown floating point abi `%s'\n"), str
);
24918 arm_parse_eabi (char * str
)
24920 const struct arm_option_value_table
*opt
;
24922 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
24923 if (streq (opt
->name
, str
))
24925 meabi_flags
= opt
->value
;
24928 as_bad (_("unknown EABI `%s'\n"), str
);
24934 arm_parse_it_mode (char * str
)
24936 bfd_boolean ret
= TRUE
;
24938 if (streq ("arm", str
))
24939 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
24940 else if (streq ("thumb", str
))
24941 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
24942 else if (streq ("always", str
))
24943 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
24944 else if (streq ("never", str
))
24945 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
24948 as_bad (_("unknown implicit IT mode `%s', should be "\
24949 "arm, thumb, always, or never."), str
);
24957 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
24959 codecomposer_syntax
= TRUE
;
24960 arm_comment_chars
[0] = ';';
24961 arm_line_separator_chars
[0] = 0;
24965 struct arm_long_option_table arm_long_opts
[] =
24967 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24968 arm_parse_cpu
, NULL
},
24969 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24970 arm_parse_arch
, NULL
},
24971 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24972 arm_parse_fpu
, NULL
},
24973 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24974 arm_parse_float_abi
, NULL
},
24976 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24977 arm_parse_eabi
, NULL
},
24979 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24980 arm_parse_it_mode
, NULL
},
24981 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
24982 arm_ccs_mode
, NULL
},
24983 {NULL
, NULL
, 0, NULL
}
24987 md_parse_option (int c
, char * arg
)
24989 struct arm_option_table
*opt
;
24990 const struct arm_legacy_option_table
*fopt
;
24991 struct arm_long_option_table
*lopt
;
24997 target_big_endian
= 1;
25003 target_big_endian
= 0;
25007 case OPTION_FIX_V4BX
:
25012 /* Listing option. Just ignore these, we don't support additional
25017 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25019 if (c
== opt
->option
[0]
25020 && ((arg
== NULL
&& opt
->option
[1] == 0)
25021 || streq (arg
, opt
->option
+ 1)))
25023 /* If the option is deprecated, tell the user. */
25024 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25025 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25026 arg
? arg
: "", _(opt
->deprecated
));
25028 if (opt
->var
!= NULL
)
25029 *opt
->var
= opt
->value
;
25035 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25037 if (c
== fopt
->option
[0]
25038 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25039 || streq (arg
, fopt
->option
+ 1)))
25041 /* If the option is deprecated, tell the user. */
25042 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25043 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25044 arg
? arg
: "", _(fopt
->deprecated
));
25046 if (fopt
->var
!= NULL
)
25047 *fopt
->var
= &fopt
->value
;
25053 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25055 /* These options are expected to have an argument. */
25056 if (c
== lopt
->option
[0]
25058 && strncmp (arg
, lopt
->option
+ 1,
25059 strlen (lopt
->option
+ 1)) == 0)
25061 /* If the option is deprecated, tell the user. */
25062 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25063 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25064 _(lopt
->deprecated
));
25066 /* Call the sup-option parser. */
25067 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25078 md_show_usage (FILE * fp
)
25080 struct arm_option_table
*opt
;
25081 struct arm_long_option_table
*lopt
;
25083 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25085 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25086 if (opt
->help
!= NULL
)
25087 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25089 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25090 if (lopt
->help
!= NULL
)
25091 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25095 -EB assemble code for a big-endian cpu\n"));
25100 -EL assemble code for a little-endian cpu\n"));
25104 --fix-v4bx Allow BX in ARMv4 code\n"));
25112 arm_feature_set flags
;
25113 } cpu_arch_ver_table
;
25115 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25116 least features first. */
25117 static const cpu_arch_ver_table cpu_arch_ver
[] =
25123 {4, ARM_ARCH_V5TE
},
25124 {5, ARM_ARCH_V5TEJ
},
25128 {11, ARM_ARCH_V6M
},
25129 {12, ARM_ARCH_V6SM
},
25130 {8, ARM_ARCH_V6T2
},
25131 {10, ARM_ARCH_V7VE
},
25132 {10, ARM_ARCH_V7R
},
25133 {10, ARM_ARCH_V7M
},
25134 {14, ARM_ARCH_V8A
},
25138 /* Set an attribute if it has not already been set by the user. */
25140 aeabi_set_attribute_int (int tag
, int value
)
25143 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25144 || !attributes_set_explicitly
[tag
])
25145 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
25149 aeabi_set_attribute_string (int tag
, const char *value
)
25152 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25153 || !attributes_set_explicitly
[tag
])
25154 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
25157 /* Set the public EABI object attributes. */
25159 aeabi_set_public_attributes (void)
25164 int fp16_optional
= 0;
25165 arm_feature_set flags
;
25166 arm_feature_set tmp
;
25167 const cpu_arch_ver_table
*p
;
25169 /* Choose the architecture based on the capabilities of the requested cpu
25170 (if any) and/or the instructions actually used. */
25171 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
25172 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
25173 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
25175 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
25176 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
25178 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
25179 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
25181 selected_cpu
= flags
;
25183 /* Allow the user to override the reported architecture. */
25186 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
25187 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
25190 /* We need to make sure that the attributes do not identify us as v6S-M
25191 when the only v6S-M feature in use is the Operating System Extensions. */
25192 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
25193 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
25194 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
25198 for (p
= cpu_arch_ver
; p
->val
; p
++)
25200 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
25203 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
25207 /* The table lookup above finds the last architecture to contribute
25208 a new feature. Unfortunately, Tag13 is a subset of the union of
25209 v6T2 and v7-M, so it is never seen as contributing a new feature.
25210 We can not search for the last entry which is entirely used,
25211 because if no CPU is specified we build up only those flags
25212 actually used. Perhaps we should separate out the specified
25213 and implicit cases. Avoid taking this path for -march=all by
25214 checking for contradictory v7-A / v7-M features. */
25216 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
25217 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
25218 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
25221 /* Tag_CPU_name. */
25222 if (selected_cpu_name
[0])
25226 q
= selected_cpu_name
;
25227 if (strncmp (q
, "armv", 4) == 0)
25232 for (i
= 0; q
[i
]; i
++)
25233 q
[i
] = TOUPPER (q
[i
]);
25235 aeabi_set_attribute_string (Tag_CPU_name
, q
);
25238 /* Tag_CPU_arch. */
25239 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
25241 /* Tag_CPU_arch_profile. */
25242 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
25244 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
25246 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
25251 if (profile
!= '\0')
25252 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
25254 /* Tag_ARM_ISA_use. */
25255 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
25257 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
25259 /* Tag_THUMB_ISA_use. */
25260 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
25262 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
25263 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
25265 /* Tag_VFP_arch. */
25266 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
25267 aeabi_set_attribute_int (Tag_VFP_arch
,
25268 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25270 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
25271 aeabi_set_attribute_int (Tag_VFP_arch
,
25272 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25274 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
25277 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
25279 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
25281 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
25284 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
25285 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
25286 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
25287 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
25288 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
25290 /* Tag_ABI_HardFP_use. */
25291 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25292 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25293 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25295 /* Tag_WMMX_arch. */
25296 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25297 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25298 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25299 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25301 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25302 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25303 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25304 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25306 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25308 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25312 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25317 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25318 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25319 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25323 We set Tag_DIV_use to two when integer divide instructions have been used
25324 in ARM state, or when Thumb integer divide instructions have been used,
25325 but we have no architecture profile set, nor have we any ARM instructions.
25327 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25330 For new architectures we will have to check these tests. */
25331 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25332 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25333 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25334 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25335 || (profile
== '\0'
25336 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25337 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25338 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25340 /* Tag_MP_extension_use. */
25341 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25342 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25344 /* Tag Virtualization_use. */
25345 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25347 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25350 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25353 /* Add the default contents for the .ARM.attributes section. */
25357 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25360 aeabi_set_public_attributes ();
25362 #endif /* OBJ_ELF */
25365 /* Parse a .cpu directive. */
25368 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25370 const struct arm_cpu_option_table
*opt
;
25374 name
= input_line_pointer
;
25375 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25376 input_line_pointer
++;
25377 saved_char
= *input_line_pointer
;
25378 *input_line_pointer
= 0;
25380 /* Skip the first "all" entry. */
25381 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25382 if (streq (opt
->name
, name
))
25384 mcpu_cpu_opt
= &opt
->value
;
25385 selected_cpu
= opt
->value
;
25386 if (opt
->canonical_name
)
25387 strcpy (selected_cpu_name
, opt
->canonical_name
);
25391 for (i
= 0; opt
->name
[i
]; i
++)
25392 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25394 selected_cpu_name
[i
] = 0;
25396 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25397 *input_line_pointer
= saved_char
;
25398 demand_empty_rest_of_line ();
25401 as_bad (_("unknown cpu `%s'"), name
);
25402 *input_line_pointer
= saved_char
;
25403 ignore_rest_of_line ();
25407 /* Parse a .arch directive. */
25410 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25412 const struct arm_arch_option_table
*opt
;
25416 name
= input_line_pointer
;
25417 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25418 input_line_pointer
++;
25419 saved_char
= *input_line_pointer
;
25420 *input_line_pointer
= 0;
25422 /* Skip the first "all" entry. */
25423 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25424 if (streq (opt
->name
, name
))
25426 mcpu_cpu_opt
= &opt
->value
;
25427 selected_cpu
= opt
->value
;
25428 strcpy (selected_cpu_name
, opt
->name
);
25429 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25430 *input_line_pointer
= saved_char
;
25431 demand_empty_rest_of_line ();
25435 as_bad (_("unknown architecture `%s'\n"), name
);
25436 *input_line_pointer
= saved_char
;
25437 ignore_rest_of_line ();
25441 /* Parse a .object_arch directive. */
25444 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25446 const struct arm_arch_option_table
*opt
;
25450 name
= input_line_pointer
;
25451 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25452 input_line_pointer
++;
25453 saved_char
= *input_line_pointer
;
25454 *input_line_pointer
= 0;
25456 /* Skip the first "all" entry. */
25457 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25458 if (streq (opt
->name
, name
))
25460 object_arch
= &opt
->value
;
25461 *input_line_pointer
= saved_char
;
25462 demand_empty_rest_of_line ();
25466 as_bad (_("unknown architecture `%s'\n"), name
);
25467 *input_line_pointer
= saved_char
;
25468 ignore_rest_of_line ();
25471 /* Parse a .arch_extension directive. */
25474 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25476 const struct arm_option_extension_value_table
*opt
;
25479 int adding_value
= 1;
25481 name
= input_line_pointer
;
25482 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25483 input_line_pointer
++;
25484 saved_char
= *input_line_pointer
;
25485 *input_line_pointer
= 0;
25487 if (strlen (name
) >= 2
25488 && strncmp (name
, "no", 2) == 0)
25494 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25495 if (streq (opt
->name
, name
))
25497 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25499 as_bad (_("architectural extension `%s' is not allowed for the "
25500 "current base architecture"), name
);
25505 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
25508 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
25510 mcpu_cpu_opt
= &selected_cpu
;
25511 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25512 *input_line_pointer
= saved_char
;
25513 demand_empty_rest_of_line ();
25517 if (opt
->name
== NULL
)
25518 as_bad (_("unknown architecture extension `%s'\n"), name
);
25520 *input_line_pointer
= saved_char
;
25521 ignore_rest_of_line ();
25524 /* Parse a .fpu directive. */
25527 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25529 const struct arm_option_fpu_value_table
*opt
;
25533 name
= input_line_pointer
;
25534 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25535 input_line_pointer
++;
25536 saved_char
= *input_line_pointer
;
25537 *input_line_pointer
= 0;
25539 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25540 if (streq (opt
->name
, name
))
25542 mfpu_opt
= &opt
->value
;
25543 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25544 *input_line_pointer
= saved_char
;
25545 demand_empty_rest_of_line ();
25549 as_bad (_("unknown floating point format `%s'\n"), name
);
25550 *input_line_pointer
= saved_char
;
25551 ignore_rest_of_line ();
25554 /* Copy symbol information. */
25557 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25559 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25563 /* Given a symbolic attribute NAME, return the proper integer value.
25564 Returns -1 if the attribute is not known. */
25567 arm_convert_symbolic_attribute (const char *name
)
25569 static const struct
25574 attribute_table
[] =
25576 /* When you modify this table you should
25577 also modify the list in doc/c-arm.texi. */
25578 #define T(tag) {#tag, tag}
25579 T (Tag_CPU_raw_name
),
25582 T (Tag_CPU_arch_profile
),
25583 T (Tag_ARM_ISA_use
),
25584 T (Tag_THUMB_ISA_use
),
25588 T (Tag_Advanced_SIMD_arch
),
25589 T (Tag_PCS_config
),
25590 T (Tag_ABI_PCS_R9_use
),
25591 T (Tag_ABI_PCS_RW_data
),
25592 T (Tag_ABI_PCS_RO_data
),
25593 T (Tag_ABI_PCS_GOT_use
),
25594 T (Tag_ABI_PCS_wchar_t
),
25595 T (Tag_ABI_FP_rounding
),
25596 T (Tag_ABI_FP_denormal
),
25597 T (Tag_ABI_FP_exceptions
),
25598 T (Tag_ABI_FP_user_exceptions
),
25599 T (Tag_ABI_FP_number_model
),
25600 T (Tag_ABI_align_needed
),
25601 T (Tag_ABI_align8_needed
),
25602 T (Tag_ABI_align_preserved
),
25603 T (Tag_ABI_align8_preserved
),
25604 T (Tag_ABI_enum_size
),
25605 T (Tag_ABI_HardFP_use
),
25606 T (Tag_ABI_VFP_args
),
25607 T (Tag_ABI_WMMX_args
),
25608 T (Tag_ABI_optimization_goals
),
25609 T (Tag_ABI_FP_optimization_goals
),
25610 T (Tag_compatibility
),
25611 T (Tag_CPU_unaligned_access
),
25612 T (Tag_FP_HP_extension
),
25613 T (Tag_VFP_HP_extension
),
25614 T (Tag_ABI_FP_16bit_format
),
25615 T (Tag_MPextension_use
),
25617 T (Tag_nodefaults
),
25618 T (Tag_also_compatible_with
),
25619 T (Tag_conformance
),
25621 T (Tag_Virtualization_use
),
25622 /* We deliberately do not include Tag_MPextension_use_legacy. */
25630 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
25631 if (streq (name
, attribute_table
[i
].name
))
25632 return attribute_table
[i
].tag
;
25638 /* Apply sym value for relocations only in the case that
25639 they are for local symbols and you have the respective
25640 architectural feature for blx and simple switches. */
25642 arm_apply_sym_value (struct fix
* fixP
)
25645 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25646 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
25648 switch (fixP
->fx_r_type
)
25650 case BFD_RELOC_ARM_PCREL_BLX
:
25651 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25652 if (ARM_IS_FUNC (fixP
->fx_addsy
))
25656 case BFD_RELOC_ARM_PCREL_CALL
:
25657 case BFD_RELOC_THUMB_PCREL_BLX
:
25658 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
25669 #endif /* OBJ_ELF */