1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
39 #include "dw2gencfi.h"
42 #include "dwarf2dbg.h"
45 /* Must be at least the size of the largest unwind opcode (currently two). */
46 #define ARM_OPCODE_CHUNK_SIZE 8
48 /* This structure holds the unwinding state. */
53 symbolS
* table_entry
;
54 symbolS
* personality_routine
;
55 int personality_index
;
56 /* The segment containing the function. */
59 /* Opcodes generated from this function. */
60 unsigned char * opcodes
;
63 /* The number of bytes pushed to the stack. */
65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
68 offsetT pending_offset
;
69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
70 hold the reg+offset to use when restoring sp from a frame pointer. */
73 /* Nonzero if an unwind_setfp directive has been seen. */
75 /* Nonzero if the last opcode restores sp from fp_reg. */
76 unsigned sp_restored
:1;
79 /* Whether --fdpic was given. */
84 /* Results from operand parsing worker functions. */
88 PARSE_OPERAND_SUCCESS
,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91 } parse_operand_result
;
100 /* Types of processor to assemble for. */
102 /* The code that was here used to select a default CPU depending on compiler
103 pre-defines which were only present when doing native builds, thus
104 changing gas' default behaviour depending upon the build host.
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
110 /* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112 static bfd_boolean
out_of_range_p (offsetT value
, offsetT bits
)
114 gas_assert (bits
< (offsetT
)(sizeof (value
) * 8));
115 return (value
& ~((1 << bits
)-1))
116 && ((value
& ~((1 << bits
)-1)) != ~((1 << bits
)-1));
121 # define FPU_DEFAULT FPU_ARCH_FPA
122 # elif defined (TE_NetBSD)
124 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
126 /* Legacy a.out format. */
127 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
129 # elif defined (TE_VXWORKS)
130 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
132 /* For backwards compatibility, default to FPA. */
133 # define FPU_DEFAULT FPU_ARCH_FPA
135 #endif /* ifndef FPU_DEFAULT */
137 #define streq(a, b) (strcmp (a, b) == 0)
139 /* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
142 static arm_feature_set cpu_variant
;
143 /* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
145 static arm_feature_set arm_arch_used
;
146 static arm_feature_set thumb_arch_used
;
148 /* Flags stored in private area of BFD structure. */
149 static int uses_apcs_26
= FALSE
;
150 static int atpcs
= FALSE
;
151 static int support_interwork
= FALSE
;
152 static int uses_apcs_float
= FALSE
;
153 static int pic_code
= FALSE
;
154 static int fix_v4bx
= FALSE
;
155 /* Warn on using deprecated features. */
156 static int warn_on_deprecated
= TRUE
;
158 /* Understand CodeComposer Studio assembly syntax. */
159 bfd_boolean codecomposer_syntax
= FALSE
;
161 /* Variables that we set while parsing command-line options. Once all
162 options have been read we re-process these values to set the real
165 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
166 instead of -mcpu=arm1). */
167 static const arm_feature_set
*legacy_cpu
= NULL
;
168 static const arm_feature_set
*legacy_fpu
= NULL
;
170 /* CPU, extension and FPU feature bits selected by -mcpu. */
171 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
172 static arm_feature_set
*mcpu_ext_opt
= NULL
;
173 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
175 /* CPU, extension and FPU feature bits selected by -march. */
176 static const arm_feature_set
*march_cpu_opt
= NULL
;
177 static arm_feature_set
*march_ext_opt
= NULL
;
178 static const arm_feature_set
*march_fpu_opt
= NULL
;
180 /* Feature bits selected by -mfpu. */
181 static const arm_feature_set
*mfpu_opt
= NULL
;
183 /* Constants for known architecture features. */
184 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
185 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
186 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
187 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
188 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
189 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
190 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
192 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
194 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
197 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
200 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
201 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
202 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
203 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
204 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
205 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
206 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
207 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
208 static const arm_feature_set arm_ext_v4t_5
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
210 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
211 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
212 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
213 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
214 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
215 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
216 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
217 /* Only for compatability of hint instructions. */
218 static const arm_feature_set arm_ext_v6k_v6t2
=
219 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
220 static const arm_feature_set arm_ext_v6_notm
=
221 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
222 static const arm_feature_set arm_ext_v6_dsp
=
223 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
224 static const arm_feature_set arm_ext_barrier
=
225 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
226 static const arm_feature_set arm_ext_msr
=
227 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
228 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
229 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
230 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
231 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
233 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
235 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
236 static const arm_feature_set arm_ext_m
=
237 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
238 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
239 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
240 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
241 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
242 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
243 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
244 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
245 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
246 static const arm_feature_set arm_ext_v8m_main
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
248 static const arm_feature_set arm_ext_v8_1m_main
=
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
250 /* Instructions in ARMv8-M only found in M profile architectures. */
251 static const arm_feature_set arm_ext_v8m_m_only
=
252 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
253 static const arm_feature_set arm_ext_v6t2_v8m
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
255 /* Instructions shared between ARMv8-A and ARMv8-M. */
256 static const arm_feature_set arm_ext_atomics
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
259 /* DSP instructions Tag_DSP_extension refers to. */
260 static const arm_feature_set arm_ext_dsp
=
261 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
263 static const arm_feature_set arm_ext_ras
=
264 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
265 /* FP16 instructions. */
266 static const arm_feature_set arm_ext_fp16
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
268 static const arm_feature_set arm_ext_fp16_fml
=
269 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
270 static const arm_feature_set arm_ext_v8_2
=
271 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
272 static const arm_feature_set arm_ext_v8_3
=
273 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
274 static const arm_feature_set arm_ext_sb
=
275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
276 static const arm_feature_set arm_ext_predres
=
277 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
278 static const arm_feature_set arm_ext_bf16
=
279 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
);
280 static const arm_feature_set arm_ext_i8mm
=
281 ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
);
283 static const arm_feature_set arm_arch_any
= ARM_ANY
;
284 static const arm_feature_set fpu_any
= FPU_ANY
;
285 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
286 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
287 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
289 static const arm_feature_set arm_cext_iwmmxt2
=
290 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
291 static const arm_feature_set arm_cext_iwmmxt
=
292 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
293 static const arm_feature_set arm_cext_xscale
=
294 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
295 static const arm_feature_set arm_cext_maverick
=
296 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
297 static const arm_feature_set fpu_fpa_ext_v1
=
298 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
299 static const arm_feature_set fpu_fpa_ext_v2
=
300 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
301 static const arm_feature_set fpu_vfp_ext_v1xd
=
302 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
303 static const arm_feature_set fpu_vfp_ext_v1
=
304 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
305 static const arm_feature_set fpu_vfp_ext_v2
=
306 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
307 static const arm_feature_set fpu_vfp_ext_v3xd
=
308 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
309 static const arm_feature_set fpu_vfp_ext_v3
=
310 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
311 static const arm_feature_set fpu_vfp_ext_d32
=
312 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
313 static const arm_feature_set fpu_neon_ext_v1
=
314 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
315 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
316 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
317 static const arm_feature_set mve_ext
=
318 ARM_FEATURE_COPROC (FPU_MVE
);
319 static const arm_feature_set mve_fp_ext
=
320 ARM_FEATURE_COPROC (FPU_MVE_FP
);
322 static const arm_feature_set fpu_vfp_fp16
=
323 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
324 static const arm_feature_set fpu_neon_ext_fma
=
325 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
327 static const arm_feature_set fpu_vfp_ext_fma
=
328 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
329 static const arm_feature_set fpu_vfp_ext_armv8
=
330 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
331 static const arm_feature_set fpu_vfp_ext_armv8xd
=
332 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
333 static const arm_feature_set fpu_neon_ext_armv8
=
334 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
335 static const arm_feature_set fpu_crypto_ext_armv8
=
336 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
337 static const arm_feature_set crc_ext_armv8
=
338 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
339 static const arm_feature_set fpu_neon_ext_v8_1
=
340 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
341 static const arm_feature_set fpu_neon_ext_dotprod
=
342 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
344 static int mfloat_abi_opt
= -1;
345 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
347 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
348 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
350 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
351 /* Feature bits selected by the last -mcpu/-march or by the combination of the
352 last .cpu/.arch directive .arch_extension directives since that
354 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
355 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
356 static arm_feature_set selected_fpu
= FPU_NONE
;
357 /* Feature bits selected by the last .object_arch directive. */
358 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
359 /* Must be long enough to hold any of the names in arm_cpus. */
360 static const struct arm_ext_table
* selected_ctx_ext_table
= NULL
;
361 static char selected_cpu_name
[20];
363 extern FLONUM_TYPE generic_floating_point_number
;
365 /* Return if no cpu was selected on command-line. */
367 no_cpu_selected (void)
369 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
374 static int meabi_flags
= EABI_DEFAULT
;
376 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
379 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
384 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
389 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
390 symbolS
* GOT_symbol
;
393 /* 0: assemble for ARM,
394 1: assemble for Thumb,
395 2: assemble for Thumb even though target CPU does not support thumb
397 static int thumb_mode
= 0;
398 /* A value distinct from the possible values for thumb_mode that we
399 can use to record whether thumb_mode has been copied into the
400 tc_frag_data field of a frag. */
401 #define MODE_RECORDED (1 << 4)
403 /* Specifies the intrinsic IT insn behavior mode. */
404 enum implicit_it_mode
406 IMPLICIT_IT_MODE_NEVER
= 0x00,
407 IMPLICIT_IT_MODE_ARM
= 0x01,
408 IMPLICIT_IT_MODE_THUMB
= 0x02,
409 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
411 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
413 /* If unified_syntax is true, we are processing the new unified
414 ARM/Thumb syntax. Important differences from the old ARM mode:
416 - Immediate operands do not require a # prefix.
417 - Conditional affixes always appear at the end of the
418 instruction. (For backward compatibility, those instructions
419 that formerly had them in the middle, continue to accept them
421 - The IT instruction may appear, and if it does is validated
422 against subsequent conditional affixes. It does not generate
425 Important differences from the old Thumb mode:
427 - Immediate operands do not require a # prefix.
428 - Most of the V6T2 instructions are only available in unified mode.
429 - The .N and .W suffixes are recognized and honored (it is an error
430 if they cannot be honored).
431 - All instructions set the flags if and only if they have an 's' affix.
432 - Conditional affixes may be used. They are validated against
433 preceding IT instructions. Unlike ARM mode, you cannot use a
434 conditional affix except in the scope of an IT instruction. */
436 static bfd_boolean unified_syntax
= FALSE
;
438 /* An immediate operand can start with #, and ld*, st*, pld operands
439 can contain [ and ]. We need to tell APP not to elide whitespace
440 before a [, which can appear as the first operand for pld.
441 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
442 const char arm_symbol_chars
[] = "#[]{}";
458 enum neon_el_type type
;
462 #define NEON_MAX_TYPE_ELS 4
466 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
470 enum pred_instruction_type
476 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
477 if inside, should be the last one. */
478 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
479 i.e. BKPT and NOP. */
480 IT_INSN
, /* The IT insn has been parsed. */
481 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
482 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
483 a predication code. */
484 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
487 /* The maximum number of operands we need. */
488 #define ARM_IT_MAX_OPERANDS 6
489 #define ARM_IT_MAX_RELOCS 3
494 unsigned long instruction
;
498 /* "uncond_value" is set to the value in place of the conditional field in
499 unconditional versions of the instruction, or -1 if nothing is
502 struct neon_type vectype
;
503 /* This does not indicate an actual NEON instruction, only that
504 the mnemonic accepts neon-style type suffixes. */
506 /* Set to the opcode if the instruction needs relaxation.
507 Zero if the instruction is not relaxed. */
511 bfd_reloc_code_real_type type
;
514 } relocs
[ARM_IT_MAX_RELOCS
];
516 enum pred_instruction_type pred_insn_type
;
522 struct neon_type_el vectype
;
523 unsigned present
: 1; /* Operand present. */
524 unsigned isreg
: 1; /* Operand was a register. */
525 unsigned immisreg
: 2; /* .imm field is a second register.
526 0: imm, 1: gpr, 2: MVE Q-register. */
527 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
531 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
532 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
533 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
534 instructions. This allows us to disambiguate ARM <-> vector insns. */
535 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
536 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
537 unsigned isquad
: 1; /* Operand is SIMD quad register. */
538 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
539 unsigned iszr
: 1; /* Operand is ZR register. */
540 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
541 unsigned writeback
: 1; /* Operand has trailing ! */
542 unsigned preind
: 1; /* Preindexed address. */
543 unsigned postind
: 1; /* Postindexed address. */
544 unsigned negative
: 1; /* Index register was negated. */
545 unsigned shifted
: 1; /* Shift applied to operation. */
546 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
547 } operands
[ARM_IT_MAX_OPERANDS
];
550 static struct arm_it inst
;
552 #define NUM_FLOAT_VALS 8
554 const char * fp_const
[] =
556 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
559 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
569 #define CP_T_X 0x00008000
570 #define CP_T_Y 0x00400000
572 #define CONDS_BIT 0x00100000
573 #define LOAD_BIT 0x00100000
575 #define DOUBLE_LOAD_FLAG 0x00000001
579 const char * template_name
;
583 #define COND_ALWAYS 0xE
587 const char * template_name
;
591 struct asm_barrier_opt
593 const char * template_name
;
595 const arm_feature_set arch
;
598 /* The bit that distinguishes CPSR and SPSR. */
599 #define SPSR_BIT (1 << 22)
601 /* The individual PSR flag bits. */
602 #define PSR_c (1 << 16)
603 #define PSR_x (1 << 17)
604 #define PSR_s (1 << 18)
605 #define PSR_f (1 << 19)
610 bfd_reloc_code_real_type reloc
;
615 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
616 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
621 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
624 /* Bits for DEFINED field in neon_typed_alias. */
625 #define NTA_HASTYPE 1
626 #define NTA_HASINDEX 2
628 struct neon_typed_alias
630 unsigned char defined
;
632 struct neon_type_el eltype
;
635 /* ARM register categories. This includes coprocessor numbers and various
636 architecture extensions' registers. Each entry should have an error message
637 in reg_expected_msgs below. */
667 /* Structure for a hash table entry for a register.
668 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
669 information which states whether a vector type or index is specified (for a
670 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
676 unsigned char builtin
;
677 struct neon_typed_alias
* neon
;
680 /* Diagnostics used when we don't get a register of the expected type. */
681 const char * const reg_expected_msgs
[] =
683 [REG_TYPE_RN
] = N_("ARM register expected"),
684 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
685 [REG_TYPE_CN
] = N_("co-processor register expected"),
686 [REG_TYPE_FN
] = N_("FPA register expected"),
687 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
688 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
689 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
690 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
691 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
692 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
693 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
695 [REG_TYPE_VFC
] = N_("VFP system register expected"),
696 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
697 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
698 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
699 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
700 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
701 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
702 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
703 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
704 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
705 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
706 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
707 [REG_TYPE_RNB
] = N_("")
710 /* Some well known registers that we refer to directly elsewhere. */
716 /* ARM instructions take 4bytes in the object file, Thumb instructions
722 /* Basic string to match. */
723 const char * template_name
;
725 /* Parameters to instruction. */
726 unsigned int operands
[8];
728 /* Conditional tag - see opcode_lookup. */
729 unsigned int tag
: 4;
731 /* Basic instruction code. */
734 /* Thumb-format instruction code. */
737 /* Which architecture variant provides this instruction. */
738 const arm_feature_set
* avariant
;
739 const arm_feature_set
* tvariant
;
741 /* Function to call to encode instruction in ARM format. */
742 void (* aencode
) (void);
744 /* Function to call to encode instruction in Thumb format. */
745 void (* tencode
) (void);
747 /* Indicates whether this instruction may be vector predicated. */
748 unsigned int mayBeVecPred
: 1;
751 /* Defines for various bits that we will want to toggle. */
752 #define INST_IMMEDIATE 0x02000000
753 #define OFFSET_REG 0x02000000
754 #define HWOFFSET_IMM 0x00400000
755 #define SHIFT_BY_REG 0x00000010
756 #define PRE_INDEX 0x01000000
757 #define INDEX_UP 0x00800000
758 #define WRITE_BACK 0x00200000
759 #define LDM_TYPE_2_OR_3 0x00400000
760 #define CPSI_MMOD 0x00020000
762 #define LITERAL_MASK 0xf000f000
763 #define OPCODE_MASK 0xfe1fffff
764 #define V4_STR_BIT 0x00000020
765 #define VLDR_VMOV_SAME 0x0040f000
767 #define T2_SUBS_PC_LR 0xf3de8f00
769 #define DATA_OP_SHIFT 21
770 #define SBIT_SHIFT 20
772 #define T2_OPCODE_MASK 0xfe1fffff
773 #define T2_DATA_OP_SHIFT 21
774 #define T2_SBIT_SHIFT 20
776 #define A_COND_MASK 0xf0000000
777 #define A_PUSH_POP_OP_MASK 0x0fff0000
779 /* Opcodes for pushing/poping registers to/from the stack. */
780 #define A1_OPCODE_PUSH 0x092d0000
781 #define A2_OPCODE_PUSH 0x052d0004
782 #define A2_OPCODE_POP 0x049d0004
784 /* Codes to distinguish the arithmetic instructions. */
795 #define OPCODE_CMP 10
796 #define OPCODE_CMN 11
797 #define OPCODE_ORR 12
798 #define OPCODE_MOV 13
799 #define OPCODE_BIC 14
800 #define OPCODE_MVN 15
802 #define T2_OPCODE_AND 0
803 #define T2_OPCODE_BIC 1
804 #define T2_OPCODE_ORR 2
805 #define T2_OPCODE_ORN 3
806 #define T2_OPCODE_EOR 4
807 #define T2_OPCODE_ADD 8
808 #define T2_OPCODE_ADC 10
809 #define T2_OPCODE_SBC 11
810 #define T2_OPCODE_SUB 13
811 #define T2_OPCODE_RSB 14
813 #define T_OPCODE_MUL 0x4340
814 #define T_OPCODE_TST 0x4200
815 #define T_OPCODE_CMN 0x42c0
816 #define T_OPCODE_NEG 0x4240
817 #define T_OPCODE_MVN 0x43c0
819 #define T_OPCODE_ADD_R3 0x1800
820 #define T_OPCODE_SUB_R3 0x1a00
821 #define T_OPCODE_ADD_HI 0x4400
822 #define T_OPCODE_ADD_ST 0xb000
823 #define T_OPCODE_SUB_ST 0xb080
824 #define T_OPCODE_ADD_SP 0xa800
825 #define T_OPCODE_ADD_PC 0xa000
826 #define T_OPCODE_ADD_I8 0x3000
827 #define T_OPCODE_SUB_I8 0x3800
828 #define T_OPCODE_ADD_I3 0x1c00
829 #define T_OPCODE_SUB_I3 0x1e00
831 #define T_OPCODE_ASR_R 0x4100
832 #define T_OPCODE_LSL_R 0x4080
833 #define T_OPCODE_LSR_R 0x40c0
834 #define T_OPCODE_ROR_R 0x41c0
835 #define T_OPCODE_ASR_I 0x1000
836 #define T_OPCODE_LSL_I 0x0000
837 #define T_OPCODE_LSR_I 0x0800
839 #define T_OPCODE_MOV_I8 0x2000
840 #define T_OPCODE_CMP_I8 0x2800
841 #define T_OPCODE_CMP_LR 0x4280
842 #define T_OPCODE_MOV_HR 0x4600
843 #define T_OPCODE_CMP_HR 0x4500
845 #define T_OPCODE_LDR_PC 0x4800
846 #define T_OPCODE_LDR_SP 0x9800
847 #define T_OPCODE_STR_SP 0x9000
848 #define T_OPCODE_LDR_IW 0x6800
849 #define T_OPCODE_STR_IW 0x6000
850 #define T_OPCODE_LDR_IH 0x8800
851 #define T_OPCODE_STR_IH 0x8000
852 #define T_OPCODE_LDR_IB 0x7800
853 #define T_OPCODE_STR_IB 0x7000
854 #define T_OPCODE_LDR_RW 0x5800
855 #define T_OPCODE_STR_RW 0x5000
856 #define T_OPCODE_LDR_RH 0x5a00
857 #define T_OPCODE_STR_RH 0x5200
858 #define T_OPCODE_LDR_RB 0x5c00
859 #define T_OPCODE_STR_RB 0x5400
861 #define T_OPCODE_PUSH 0xb400
862 #define T_OPCODE_POP 0xbc00
864 #define T_OPCODE_BRANCH 0xe000
866 #define THUMB_SIZE 2 /* Size of thumb instruction. */
867 #define THUMB_PP_PC_LR 0x0100
868 #define THUMB_LOAD_BIT 0x0800
869 #define THUMB2_LOAD_BIT 0x00100000
871 #define BAD_SYNTAX _("syntax error")
872 #define BAD_ARGS _("bad arguments to instruction")
873 #define BAD_SP _("r13 not allowed here")
874 #define BAD_PC _("r15 not allowed here")
875 #define BAD_ODD _("Odd register not allowed here")
876 #define BAD_EVEN _("Even register not allowed here")
877 #define BAD_COND _("instruction cannot be conditional")
878 #define BAD_OVERLAP _("registers may not be the same")
879 #define BAD_HIREG _("lo register required")
880 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
881 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
882 #define BAD_BRANCH _("branch must be last instruction in IT block")
883 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
884 #define BAD_NOT_IT _("instruction not allowed in IT block")
885 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
886 #define BAD_FPU _("selected FPU does not support instruction")
887 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
888 #define BAD_OUT_VPT \
889 _("vector predicated instruction should be in VPT/VPST block")
890 #define BAD_IT_COND _("incorrect condition in IT block")
891 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
892 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
893 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
894 #define BAD_PC_ADDRESSING \
895 _("cannot use register index with PC-relative addressing")
896 #define BAD_PC_WRITEBACK \
897 _("cannot use writeback with PC-relative addressing")
898 #define BAD_RANGE _("branch out of range")
899 #define BAD_FP16 _("selected processor does not support fp16 instruction")
900 #define BAD_BF16 _("selected processor does not support bf16 instruction")
901 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
902 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
903 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
905 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
907 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
909 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
911 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
912 #define BAD_MVE_AUTO \
913 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
914 " use a valid -march or -mcpu option.")
915 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
916 "and source operands makes instruction UNPREDICTABLE")
917 #define BAD_EL_TYPE _("bad element type for instruction")
918 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
920 static struct hash_control
* arm_ops_hsh
;
921 static struct hash_control
* arm_cond_hsh
;
922 static struct hash_control
* arm_vcond_hsh
;
923 static struct hash_control
* arm_shift_hsh
;
924 static struct hash_control
* arm_psr_hsh
;
925 static struct hash_control
* arm_v7m_psr_hsh
;
926 static struct hash_control
* arm_reg_hsh
;
927 static struct hash_control
* arm_reloc_hsh
;
928 static struct hash_control
* arm_barrier_opt_hsh
;
930 /* Stuff needed to resolve the label ambiguity
939 symbolS
* last_label_seen
;
940 static int label_is_thumb_function_name
= FALSE
;
942 /* Literal pool structure. Held on a per-section
943 and per-sub-section basis. */
945 #define MAX_LITERAL_POOL_SIZE 1024
946 typedef struct literal_pool
948 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
949 unsigned int next_free_entry
;
955 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
957 struct literal_pool
* next
;
958 unsigned int alignment
;
961 /* Pointer to a linked list of literal pools. */
962 literal_pool
* list_of_pools
= NULL
;
964 typedef enum asmfunc_states
967 WAITING_ASMFUNC_NAME
,
971 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
974 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
976 static struct current_pred now_pred
;
980 now_pred_compatible (int cond
)
982 return (cond
& ~1) == (now_pred
.cc
& ~1);
986 conditional_insn (void)
988 return inst
.cond
!= COND_ALWAYS
;
991 static int in_pred_block (void);
993 static int handle_pred_state (void);
995 static void force_automatic_it_block_close (void);
997 static void it_fsm_post_encode (void);
999 #define set_pred_insn_type(type) \
1002 inst.pred_insn_type = type; \
1003 if (handle_pred_state () == FAIL) \
1008 #define set_pred_insn_type_nonvoid(type, failret) \
1011 inst.pred_insn_type = type; \
1012 if (handle_pred_state () == FAIL) \
1017 #define set_pred_insn_type_last() \
1020 if (inst.cond == COND_ALWAYS) \
1021 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1023 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1027 /* Toggle value[pos]. */
1028 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1032 /* This array holds the chars that always start a comment. If the
1033 pre-processor is disabled, these aren't very useful. */
1034 char arm_comment_chars
[] = "@";
1036 /* This array holds the chars that only start a comment at the beginning of
1037 a line. If the line seems to have the form '# 123 filename'
1038 .line and .file directives will appear in the pre-processed output. */
1039 /* Note that input_file.c hand checks for '#' at the beginning of the
1040 first line of the input file. This is because the compiler outputs
1041 #NO_APP at the beginning of its output. */
1042 /* Also note that comments like this one will always work. */
1043 const char line_comment_chars
[] = "#";
1045 char arm_line_separator_chars
[] = ";";
1047 /* Chars that can be used to separate mant
1048 from exp in floating point numbers. */
1049 const char EXP_CHARS
[] = "eE";
1051 /* Chars that mean this number is a floating point constant. */
1052 /* As in 0f12.456 */
1053 /* or 0d1.2345e12 */
1055 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1057 /* Prefix characters that indicate the start of an immediate
1059 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1061 /* Separator character handling. */
1063 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1065 enum fp_16bit_format
1067 ARM_FP16_FORMAT_IEEE
= 0x1,
1068 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1069 ARM_FP16_FORMAT_DEFAULT
= 0x3
1072 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1076 skip_past_char (char ** str
, char c
)
1078 /* PR gas/14987: Allow for whitespace before the expected character. */
1079 skip_whitespace (*str
);
1090 #define skip_past_comma(str) skip_past_char (str, ',')
1092 /* Arithmetic expressions (possibly involving symbols). */
1094 /* Return TRUE if anything in the expression is a bignum. */
1097 walk_no_bignums (symbolS
* sp
)
1099 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1102 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1104 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1105 || (symbol_get_value_expression (sp
)->X_op_symbol
1106 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1112 static bfd_boolean in_my_get_expression
= FALSE
;
1114 /* Third argument to my_get_expression. */
1115 #define GE_NO_PREFIX 0
1116 #define GE_IMM_PREFIX 1
1117 #define GE_OPT_PREFIX 2
1118 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1119 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1120 #define GE_OPT_PREFIX_BIG 3
1123 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1127 /* In unified syntax, all prefixes are optional. */
1129 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1132 switch (prefix_mode
)
1134 case GE_NO_PREFIX
: break;
1136 if (!is_immediate_prefix (**str
))
1138 inst
.error
= _("immediate expression requires a # prefix");
1144 case GE_OPT_PREFIX_BIG
:
1145 if (is_immediate_prefix (**str
))
1152 memset (ep
, 0, sizeof (expressionS
));
1154 save_in
= input_line_pointer
;
1155 input_line_pointer
= *str
;
1156 in_my_get_expression
= TRUE
;
1158 in_my_get_expression
= FALSE
;
1160 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1162 /* We found a bad or missing expression in md_operand(). */
1163 *str
= input_line_pointer
;
1164 input_line_pointer
= save_in
;
1165 if (inst
.error
== NULL
)
1166 inst
.error
= (ep
->X_op
== O_absent
1167 ? _("missing expression") :_("bad expression"));
1171 /* Get rid of any bignums now, so that we don't generate an error for which
1172 we can't establish a line number later on. Big numbers are never valid
1173 in instructions, which is where this routine is always called. */
1174 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1175 && (ep
->X_op
== O_big
1176 || (ep
->X_add_symbol
1177 && (walk_no_bignums (ep
->X_add_symbol
)
1179 && walk_no_bignums (ep
->X_op_symbol
))))))
1181 inst
.error
= _("invalid constant");
1182 *str
= input_line_pointer
;
1183 input_line_pointer
= save_in
;
1187 *str
= input_line_pointer
;
1188 input_line_pointer
= save_in
;
1192 /* Turn a string in input_line_pointer into a floating point constant
1193 of type TYPE, and store the appropriate bytes in *LITP. The number
1194 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1195 returned, or NULL on OK.
1197 Note that fp constants aren't represent in the normal way on the ARM.
1198 In big endian mode, things are as expected. However, in little endian
1199 mode fp constants are big-endian word-wise, and little-endian byte-wise
1200 within the words. For example, (double) 1.1 in big endian mode is
1201 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1202 the byte sequence 99 99 f1 3f 9a 99 99 99.
1204 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1207 md_atof (int type
, char * litP
, int * sizeP
)
1210 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1221 /* If this is a bfloat16, then parse it slightly differently, as it
1222 does not follow the IEEE specification for floating point numbers
1226 FLONUM_TYPE generic_float
;
1228 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
1231 input_line_pointer
= t
;
1233 return _("invalid floating point number");
1235 switch (generic_float
.sign
)
1248 /* bfloat16 has two types of NaN - quiet and signalling.
1249 Quiet NaN has bit[6] == 1 && faction != 0, whereas
1250 signalling NaN's have bit[0] == 0 && fraction != 0.
1251 Chosen this specific encoding as it is the same form
1252 as used by other IEEE 754 encodings in GAS. */
1263 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
1293 return _("Unrecognized or unsupported floating point constant");
1296 t
= atof_ieee (input_line_pointer
, type
, words
);
1298 input_line_pointer
= t
;
1299 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1301 if (target_big_endian
|| prec
== 1)
1302 for (i
= 0; i
< prec
; i
++)
1304 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1305 litP
+= sizeof (LITTLENUM_TYPE
);
1307 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1308 for (i
= prec
- 1; i
>= 0; i
--)
1310 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1311 litP
+= sizeof (LITTLENUM_TYPE
);
1314 /* For a 4 byte float the order of elements in `words' is 1 0.
1315 For an 8 byte float the order is 1 0 3 2. */
1316 for (i
= 0; i
< prec
; i
+= 2)
1318 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1319 sizeof (LITTLENUM_TYPE
));
1320 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1321 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1322 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1328 /* We handle all bad expressions here, so that we can report the faulty
1329 instruction in the error message. */
1332 md_operand (expressionS
* exp
)
1334 if (in_my_get_expression
)
1335 exp
->X_op
= O_illegal
;
1338 /* Immediate values. */
1341 /* Generic immediate-value read function for use in directives.
1342 Accepts anything that 'expression' can fold to a constant.
1343 *val receives the number. */
1346 immediate_for_directive (int *val
)
1349 exp
.X_op
= O_illegal
;
1351 if (is_immediate_prefix (*input_line_pointer
))
1353 input_line_pointer
++;
1357 if (exp
.X_op
!= O_constant
)
1359 as_bad (_("expected #constant"));
1360 ignore_rest_of_line ();
1363 *val
= exp
.X_add_number
;
1368 /* Register parsing. */
1370 /* Generic register parser. CCP points to what should be the
1371 beginning of a register name. If it is indeed a valid register
1372 name, advance CCP over it and return the reg_entry structure;
1373 otherwise return NULL. Does not issue diagnostics. */
1375 static struct reg_entry
*
1376 arm_reg_parse_multi (char **ccp
)
1380 struct reg_entry
*reg
;
1382 skip_whitespace (start
);
1384 #ifdef REGISTER_PREFIX
1385 if (*start
!= REGISTER_PREFIX
)
1389 #ifdef OPTIONAL_REGISTER_PREFIX
1390 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1395 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1400 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1402 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1412 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1413 enum arm_reg_type type
)
1415 /* Alternative syntaxes are accepted for a few register classes. */
1422 /* Generic coprocessor register names are allowed for these. */
1423 if (reg
&& reg
->type
== REG_TYPE_CN
)
1428 /* For backward compatibility, a bare number is valid here. */
1430 unsigned long processor
= strtoul (start
, ccp
, 10);
1431 if (*ccp
!= start
&& processor
<= 15)
1436 case REG_TYPE_MMXWC
:
1437 /* WC includes WCG. ??? I'm not sure this is true for all
1438 instructions that take WC registers. */
1439 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1450 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1451 return value is the register number or FAIL. */
1454 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1457 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1460 /* Do not allow a scalar (reg+index) to parse as a register. */
1461 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1464 if (reg
&& reg
->type
== type
)
1467 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1474 /* Parse a Neon type specifier. *STR should point at the leading '.'
1475 character. Does no verification at this stage that the type fits the opcode
1482 Can all be legally parsed by this function.
1484 Fills in neon_type struct pointer with parsed information, and updates STR
1485 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1486 type, FAIL if not. */
1489 parse_neon_type (struct neon_type
*type
, char **str
)
1496 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1498 enum neon_el_type thistype
= NT_untyped
;
1499 unsigned thissize
= -1u;
1506 /* Just a size without an explicit type. */
1510 switch (TOLOWER (*ptr
))
1512 case 'i': thistype
= NT_integer
; break;
1513 case 'f': thistype
= NT_float
; break;
1514 case 'p': thistype
= NT_poly
; break;
1515 case 's': thistype
= NT_signed
; break;
1516 case 'u': thistype
= NT_unsigned
; break;
1518 thistype
= NT_float
;
1523 thistype
= NT_bfloat
;
1524 switch (TOLOWER (*(++ptr
)))
1528 thissize
= strtoul (ptr
, &ptr
, 10);
1531 as_bad (_("bad size %d in type specifier"), thissize
);
1535 case '0': case '1': case '2': case '3': case '4':
1536 case '5': case '6': case '7': case '8': case '9':
1538 as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1545 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1551 /* .f is an abbreviation for .f32. */
1552 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1557 thissize
= strtoul (ptr
, &ptr
, 10);
1559 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1562 as_bad (_("bad size %d in type specifier"), thissize
);
1570 type
->el
[type
->elems
].type
= thistype
;
1571 type
->el
[type
->elems
].size
= thissize
;
1576 /* Empty/missing type is not a successful parse. */
1577 if (type
->elems
== 0)
1585 /* Errors may be set multiple times during parsing or bit encoding
1586 (particularly in the Neon bits), but usually the earliest error which is set
1587 will be the most meaningful. Avoid overwriting it with later (cascading)
1588 errors by calling this function. */
1591 first_error (const char *err
)
1597 /* Parse a single type, e.g. ".s32", leading period included. */
1599 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1602 struct neon_type optype
;
1606 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1608 if (optype
.elems
== 1)
1609 *vectype
= optype
.el
[0];
1612 first_error (_("only one type should be specified for operand"));
1618 first_error (_("vector type expected"));
1630 /* Special meanings for indices (which have a range of 0-7), which will fit into
1633 #define NEON_ALL_LANES 15
1634 #define NEON_INTERLEAVE_LANES 14
1636 /* Record a use of the given feature. */
1638 record_feature_use (const arm_feature_set
*feature
)
1641 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1643 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1646 /* If the given feature available in the selected CPU, mark it as used.
1647 Returns TRUE iff feature is available. */
1649 mark_feature_used (const arm_feature_set
*feature
)
1652 /* Do not support the use of MVE only instructions when in auto-detection or
1654 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1655 && ARM_CPU_IS_ANY (cpu_variant
))
1657 first_error (BAD_MVE_AUTO
);
1660 /* Ensure the option is valid on the current architecture. */
1661 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1664 /* Add the appropriate architecture feature for the barrier option used.
1666 record_feature_use (feature
);
1671 /* Parse either a register or a scalar, with an optional type. Return the
1672 register number, and optionally fill in the actual type of the register
1673 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1674 type/index information in *TYPEINFO. */
1677 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1678 enum arm_reg_type
*rtype
,
1679 struct neon_typed_alias
*typeinfo
)
1682 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1683 struct neon_typed_alias atype
;
1684 struct neon_type_el parsetype
;
1688 atype
.eltype
.type
= NT_invtype
;
1689 atype
.eltype
.size
= -1;
1691 /* Try alternate syntax for some types of register. Note these are mutually
1692 exclusive with the Neon syntax extensions. */
1695 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1703 /* Undo polymorphism when a set of register types may be accepted. */
1704 if ((type
== REG_TYPE_NDQ
1705 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1706 || (type
== REG_TYPE_VFSD
1707 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1708 || (type
== REG_TYPE_NSDQ
1709 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1710 || reg
->type
== REG_TYPE_NQ
))
1711 || (type
== REG_TYPE_NSD
1712 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1713 || (type
== REG_TYPE_MMXWC
1714 && (reg
->type
== REG_TYPE_MMXWCG
)))
1715 type
= (enum arm_reg_type
) reg
->type
;
1717 if (type
== REG_TYPE_MQ
)
1719 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1722 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1725 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1727 first_error (_("expected MVE register [q0..q7]"));
1732 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1733 && (type
== REG_TYPE_NQ
))
1737 if (type
!= reg
->type
)
1743 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1745 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1747 first_error (_("can't redefine type for operand"));
1750 atype
.defined
|= NTA_HASTYPE
;
1751 atype
.eltype
= parsetype
;
1754 if (skip_past_char (&str
, '[') == SUCCESS
)
1756 if (type
!= REG_TYPE_VFD
1757 && !(type
== REG_TYPE_VFS
1758 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1759 && !(type
== REG_TYPE_NQ
1760 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1762 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1763 first_error (_("only D and Q registers may be indexed"));
1765 first_error (_("only D registers may be indexed"));
1769 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1771 first_error (_("can't change index for operand"));
1775 atype
.defined
|= NTA_HASINDEX
;
1777 if (skip_past_char (&str
, ']') == SUCCESS
)
1778 atype
.index
= NEON_ALL_LANES
;
1783 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1785 if (exp
.X_op
!= O_constant
)
1787 first_error (_("constant expression required"));
1791 if (skip_past_char (&str
, ']') == FAIL
)
1794 atype
.index
= exp
.X_add_number
;
1809 /* Like arm_reg_parse, but also allow the following extra features:
1810 - If RTYPE is non-zero, return the (possibly restricted) type of the
1811 register (e.g. Neon double or quad reg when either has been requested).
1812 - If this is a Neon vector type with additional type information, fill
1813 in the struct pointed to by VECTYPE (if non-NULL).
1814 This function will fault on encountering a scalar. */
1817 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1818 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1820 struct neon_typed_alias atype
;
1822 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1827 /* Do not allow regname(... to parse as a register. */
1831 /* Do not allow a scalar (reg+index) to parse as a register. */
1832 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1834 first_error (_("register operand expected, but got scalar"));
1839 *vectype
= atype
.eltype
;
1846 #define NEON_SCALAR_REG(X) ((X) >> 4)
1847 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1849 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1850 have enough information to be able to do a good job bounds-checking. So, we
1851 just do easy checks here, and do further checks later. */
1854 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1855 arm_reg_type reg_type
)
1859 struct neon_typed_alias atype
;
1862 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1880 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1883 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1885 first_error (_("scalar must have an index"));
1888 else if (atype
.index
>= reg_size
/ elsize
)
1890 first_error (_("scalar index out of range"));
1895 *type
= atype
.eltype
;
1899 return reg
* 16 + atype
.index
;
1902 /* Types of registers in a list. */
1915 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1918 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1924 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1926 /* We come back here if we get ranges concatenated by '+' or '|'. */
1929 skip_whitespace (str
);
1942 const char apsr_str
[] = "apsr";
1943 int apsr_str_len
= strlen (apsr_str
);
1945 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1946 if (etype
== REGLIST_CLRM
)
1948 if (reg
== REG_SP
|| reg
== REG_PC
)
1950 else if (reg
== FAIL
1951 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1952 && !ISALPHA (*(str
+ apsr_str_len
)))
1955 str
+= apsr_str_len
;
1960 first_error (_("r0-r12, lr or APSR expected"));
1964 else /* etype == REGLIST_RN. */
1968 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1979 first_error (_("bad range in register list"));
1983 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1985 if (range
& (1 << i
))
1987 (_("Warning: duplicated register (r%d) in register list"),
1995 if (range
& (1 << reg
))
1996 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1998 else if (reg
<= cur_reg
)
1999 as_tsktsk (_("Warning: register range not in ascending order"));
2004 while (skip_past_comma (&str
) != FAIL
2005 || (in_range
= 1, *str
++ == '-'));
2008 if (skip_past_char (&str
, '}') == FAIL
)
2010 first_error (_("missing `}'"));
2014 else if (etype
== REGLIST_RN
)
2018 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
2021 if (exp
.X_op
== O_constant
)
2023 if (exp
.X_add_number
2024 != (exp
.X_add_number
& 0x0000ffff))
2026 inst
.error
= _("invalid register mask");
2030 if ((range
& exp
.X_add_number
) != 0)
2032 int regno
= range
& exp
.X_add_number
;
2035 regno
= (1 << regno
) - 1;
2037 (_("Warning: duplicated register (r%d) in register list"),
2041 range
|= exp
.X_add_number
;
2045 if (inst
.relocs
[0].type
!= 0)
2047 inst
.error
= _("expression too complex");
2051 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
2052 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
2053 inst
.relocs
[0].pc_rel
= 0;
2057 if (*str
== '|' || *str
== '+')
2063 while (another_range
);
2069 /* Parse a VFP register list. If the string is invalid return FAIL.
2070 Otherwise return the number of registers, and set PBASE to the first
2071 register. Parses registers of type ETYPE.
2072 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2073 - Q registers can be used to specify pairs of D registers
2074 - { } can be omitted from around a singleton register list
2075 FIXME: This is not implemented, as it would require backtracking in
2078 This could be done (the meaning isn't really ambiguous), but doesn't
2079 fit in well with the current parsing framework.
2080 - 32 D registers may be used (also true for VFPv3).
2081 FIXME: Types are ignored in these register lists, which is probably a
2085 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2086 bfd_boolean
*partial_match
)
2091 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2095 unsigned long mask
= 0;
2097 bfd_boolean vpr_seen
= FALSE
;
2098 bfd_boolean expect_vpr
=
2099 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2101 if (skip_past_char (&str
, '{') == FAIL
)
2103 inst
.error
= _("expecting {");
2110 case REGLIST_VFP_S_VPR
:
2111 regtype
= REG_TYPE_VFS
;
2116 case REGLIST_VFP_D_VPR
:
2117 regtype
= REG_TYPE_VFD
;
2120 case REGLIST_NEON_D
:
2121 regtype
= REG_TYPE_NDQ
;
2128 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2130 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2131 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2135 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2138 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2145 base_reg
= max_regs
;
2146 *partial_match
= FALSE
;
2150 int setmask
= 1, addregs
= 1;
2151 const char vpr_str
[] = "vpr";
2152 int vpr_str_len
= strlen (vpr_str
);
2154 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2158 if (new_base
== FAIL
2159 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2160 && !ISALPHA (*(str
+ vpr_str_len
))
2166 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2170 first_error (_("VPR expected last"));
2173 else if (new_base
== FAIL
)
2175 if (regtype
== REG_TYPE_VFS
)
2176 first_error (_("VFP single precision register or VPR "
2178 else /* regtype == REG_TYPE_VFD. */
2179 first_error (_("VFP/Neon double precision register or VPR "
2184 else if (new_base
== FAIL
)
2186 first_error (_(reg_expected_msgs
[regtype
]));
2190 *partial_match
= TRUE
;
2194 if (new_base
>= max_regs
)
2196 first_error (_("register out of range in list"));
2200 /* Note: a value of 2 * n is returned for the register Q<n>. */
2201 if (regtype
== REG_TYPE_NQ
)
2207 if (new_base
< base_reg
)
2208 base_reg
= new_base
;
2210 if (mask
& (setmask
<< new_base
))
2212 first_error (_("invalid register list"));
2216 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2218 as_tsktsk (_("register list not in ascending order"));
2222 mask
|= setmask
<< new_base
;
2225 if (*str
== '-') /* We have the start of a range expression */
2231 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2234 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2238 if (high_range
>= max_regs
)
2240 first_error (_("register out of range in list"));
2244 if (regtype
== REG_TYPE_NQ
)
2245 high_range
= high_range
+ 1;
2247 if (high_range
<= new_base
)
2249 inst
.error
= _("register range not in ascending order");
2253 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2255 if (mask
& (setmask
<< new_base
))
2257 inst
.error
= _("invalid register list");
2261 mask
|= setmask
<< new_base
;
2266 while (skip_past_comma (&str
) != FAIL
);
2270 /* Sanity check -- should have raised a parse error above. */
2271 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2276 if (expect_vpr
&& !vpr_seen
)
2278 first_error (_("VPR expected last"));
2282 /* Final test -- the registers must be consecutive. */
2284 for (i
= 0; i
< count
; i
++)
2286 if ((mask
& (1u << i
)) == 0)
2288 inst
.error
= _("non-contiguous register range");
2298 /* True if two alias types are the same. */
2301 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2309 if (a
->defined
!= b
->defined
)
2312 if ((a
->defined
& NTA_HASTYPE
) != 0
2313 && (a
->eltype
.type
!= b
->eltype
.type
2314 || a
->eltype
.size
!= b
->eltype
.size
))
2317 if ((a
->defined
& NTA_HASINDEX
) != 0
2318 && (a
->index
!= b
->index
))
2324 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2325 The base register is put in *PBASE.
2326 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2328 The register stride (minus one) is put in bit 4 of the return value.
2329 Bits [6:5] encode the list length (minus one).
2330 The type of the list elements is put in *ELTYPE, if non-NULL. */
2332 #define NEON_LANE(X) ((X) & 0xf)
2333 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2334 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2337 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2339 struct neon_type_el
*eltype
)
2346 int leading_brace
= 0;
2347 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2348 const char *const incr_error
= mve
? _("register stride must be 1") :
2349 _("register stride must be 1 or 2");
2350 const char *const type_error
= _("mismatched element/structure types in list");
2351 struct neon_typed_alias firsttype
;
2352 firsttype
.defined
= 0;
2353 firsttype
.eltype
.type
= NT_invtype
;
2354 firsttype
.eltype
.size
= -1;
2355 firsttype
.index
= -1;
2357 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2362 struct neon_typed_alias atype
;
2364 rtype
= REG_TYPE_MQ
;
2365 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2369 first_error (_(reg_expected_msgs
[rtype
]));
2376 if (rtype
== REG_TYPE_NQ
)
2382 else if (reg_incr
== -1)
2384 reg_incr
= getreg
- base_reg
;
2385 if (reg_incr
< 1 || reg_incr
> 2)
2387 first_error (_(incr_error
));
2391 else if (getreg
!= base_reg
+ reg_incr
* count
)
2393 first_error (_(incr_error
));
2397 if (! neon_alias_types_same (&atype
, &firsttype
))
2399 first_error (_(type_error
));
2403 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2407 struct neon_typed_alias htype
;
2408 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2410 lane
= NEON_INTERLEAVE_LANES
;
2411 else if (lane
!= NEON_INTERLEAVE_LANES
)
2413 first_error (_(type_error
));
2418 else if (reg_incr
!= 1)
2420 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2424 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2427 first_error (_(reg_expected_msgs
[rtype
]));
2430 if (! neon_alias_types_same (&htype
, &firsttype
))
2432 first_error (_(type_error
));
2435 count
+= hireg
+ dregs
- getreg
;
2439 /* If we're using Q registers, we can't use [] or [n] syntax. */
2440 if (rtype
== REG_TYPE_NQ
)
2446 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2450 else if (lane
!= atype
.index
)
2452 first_error (_(type_error
));
2456 else if (lane
== -1)
2457 lane
= NEON_INTERLEAVE_LANES
;
2458 else if (lane
!= NEON_INTERLEAVE_LANES
)
2460 first_error (_(type_error
));
2465 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2467 /* No lane set by [x]. We must be interleaving structures. */
2469 lane
= NEON_INTERLEAVE_LANES
;
2472 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2473 || (count
> 1 && reg_incr
== -1))
2475 first_error (_("error parsing element/structure list"));
2479 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2481 first_error (_("expected }"));
2489 *eltype
= firsttype
.eltype
;
2494 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2497 /* Parse an explicit relocation suffix on an expression. This is
2498 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2499 arm_reloc_hsh contains no entries, so this function can only
2500 succeed if there is no () after the word. Returns -1 on error,
2501 BFD_RELOC_UNUSED if there wasn't any suffix. */
2504 parse_reloc (char **str
)
2506 struct reloc_entry
*r
;
2510 return BFD_RELOC_UNUSED
;
2515 while (*q
&& *q
!= ')' && *q
!= ',')
2520 if ((r
= (struct reloc_entry
*)
2521 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2528 /* Directives: register aliases. */
2530 static struct reg_entry
*
2531 insert_reg_alias (char *str
, unsigned number
, int type
)
2533 struct reg_entry
*new_reg
;
2536 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2538 if (new_reg
->builtin
)
2539 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2541 /* Only warn about a redefinition if it's not defined as the
2543 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2544 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2549 name
= xstrdup (str
);
2550 new_reg
= XNEW (struct reg_entry
);
2552 new_reg
->name
= name
;
2553 new_reg
->number
= number
;
2554 new_reg
->type
= type
;
2555 new_reg
->builtin
= FALSE
;
2556 new_reg
->neon
= NULL
;
2558 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2565 insert_neon_reg_alias (char *str
, int number
, int type
,
2566 struct neon_typed_alias
*atype
)
2568 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2572 first_error (_("attempt to redefine typed alias"));
2578 reg
->neon
= XNEW (struct neon_typed_alias
);
2579 *reg
->neon
= *atype
;
2583 /* Look for the .req directive. This is of the form:
2585 new_register_name .req existing_register_name
2587 If we find one, or if it looks sufficiently like one that we want to
2588 handle any error here, return TRUE. Otherwise return FALSE. */
2591 create_register_alias (char * newname
, char *p
)
2593 struct reg_entry
*old
;
2594 char *oldname
, *nbuf
;
2597 /* The input scrubber ensures that whitespace after the mnemonic is
2598 collapsed to single spaces. */
2600 if (strncmp (oldname
, " .req ", 6) != 0)
2604 if (*oldname
== '\0')
2607 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2610 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2614 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2615 the desired alias name, and p points to its end. If not, then
2616 the desired alias name is in the global original_case_string. */
2617 #ifdef TC_CASE_SENSITIVE
2620 newname
= original_case_string
;
2621 nlen
= strlen (newname
);
2624 nbuf
= xmemdup0 (newname
, nlen
);
2626 /* Create aliases under the new name as stated; an all-lowercase
2627 version of the new name; and an all-uppercase version of the new
2629 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2631 for (p
= nbuf
; *p
; p
++)
2634 if (strncmp (nbuf
, newname
, nlen
))
2636 /* If this attempt to create an additional alias fails, do not bother
2637 trying to create the all-lower case alias. We will fail and issue
2638 a second, duplicate error message. This situation arises when the
2639 programmer does something like:
2642 The second .req creates the "Foo" alias but then fails to create
2643 the artificial FOO alias because it has already been created by the
2645 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2652 for (p
= nbuf
; *p
; p
++)
2655 if (strncmp (nbuf
, newname
, nlen
))
2656 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2663 /* Create a Neon typed/indexed register alias using directives, e.g.:
2668 These typed registers can be used instead of the types specified after the
2669 Neon mnemonic, so long as all operands given have types. Types can also be
2670 specified directly, e.g.:
2671 vadd d0.s32, d1.s32, d2.s32 */
2674 create_neon_reg_alias (char *newname
, char *p
)
2676 enum arm_reg_type basetype
;
2677 struct reg_entry
*basereg
;
2678 struct reg_entry mybasereg
;
2679 struct neon_type ntype
;
2680 struct neon_typed_alias typeinfo
;
2681 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2684 typeinfo
.defined
= 0;
2685 typeinfo
.eltype
.type
= NT_invtype
;
2686 typeinfo
.eltype
.size
= -1;
2687 typeinfo
.index
= -1;
2691 if (strncmp (p
, " .dn ", 5) == 0)
2692 basetype
= REG_TYPE_VFD
;
2693 else if (strncmp (p
, " .qn ", 5) == 0)
2694 basetype
= REG_TYPE_NQ
;
2703 basereg
= arm_reg_parse_multi (&p
);
2705 if (basereg
&& basereg
->type
!= basetype
)
2707 as_bad (_("bad type for register"));
2711 if (basereg
== NULL
)
2714 /* Try parsing as an integer. */
2715 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2716 if (exp
.X_op
!= O_constant
)
2718 as_bad (_("expression must be constant"));
2721 basereg
= &mybasereg
;
2722 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2728 typeinfo
= *basereg
->neon
;
2730 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2732 /* We got a type. */
2733 if (typeinfo
.defined
& NTA_HASTYPE
)
2735 as_bad (_("can't redefine the type of a register alias"));
2739 typeinfo
.defined
|= NTA_HASTYPE
;
2740 if (ntype
.elems
!= 1)
2742 as_bad (_("you must specify a single type only"));
2745 typeinfo
.eltype
= ntype
.el
[0];
2748 if (skip_past_char (&p
, '[') == SUCCESS
)
2751 /* We got a scalar index. */
2753 if (typeinfo
.defined
& NTA_HASINDEX
)
2755 as_bad (_("can't redefine the index of a scalar alias"));
2759 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2761 if (exp
.X_op
!= O_constant
)
2763 as_bad (_("scalar index must be constant"));
2767 typeinfo
.defined
|= NTA_HASINDEX
;
2768 typeinfo
.index
= exp
.X_add_number
;
2770 if (skip_past_char (&p
, ']') == FAIL
)
2772 as_bad (_("expecting ]"));
2777 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2778 the desired alias name, and p points to its end. If not, then
2779 the desired alias name is in the global original_case_string. */
2780 #ifdef TC_CASE_SENSITIVE
2781 namelen
= nameend
- newname
;
2783 newname
= original_case_string
;
2784 namelen
= strlen (newname
);
2787 namebuf
= xmemdup0 (newname
, namelen
);
2789 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2790 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2792 /* Insert name in all uppercase. */
2793 for (p
= namebuf
; *p
; p
++)
2796 if (strncmp (namebuf
, newname
, namelen
))
2797 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2798 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2800 /* Insert name in all lowercase. */
2801 for (p
= namebuf
; *p
; p
++)
2804 if (strncmp (namebuf
, newname
, namelen
))
2805 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2806 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2812 /* Should never be called, as .req goes between the alias and the
2813 register name, not at the beginning of the line. */
2816 s_req (int a ATTRIBUTE_UNUSED
)
2818 as_bad (_("invalid syntax for .req directive"));
2822 s_dn (int a ATTRIBUTE_UNUSED
)
2824 as_bad (_("invalid syntax for .dn directive"));
2828 s_qn (int a ATTRIBUTE_UNUSED
)
2830 as_bad (_("invalid syntax for .qn directive"));
2833 /* The .unreq directive deletes an alias which was previously defined
2834 by .req. For example:
2840 s_unreq (int a ATTRIBUTE_UNUSED
)
2845 name
= input_line_pointer
;
2847 while (*input_line_pointer
!= 0
2848 && *input_line_pointer
!= ' '
2849 && *input_line_pointer
!= '\n')
2850 ++input_line_pointer
;
2852 saved_char
= *input_line_pointer
;
2853 *input_line_pointer
= 0;
2856 as_bad (_("invalid syntax for .unreq directive"));
2859 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2863 as_bad (_("unknown register alias '%s'"), name
);
2864 else if (reg
->builtin
)
2865 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2872 hash_delete (arm_reg_hsh
, name
, FALSE
);
2873 free ((char *) reg
->name
);
2878 /* Also locate the all upper case and all lower case versions.
2879 Do not complain if we cannot find one or the other as it
2880 was probably deleted above. */
2882 nbuf
= strdup (name
);
2883 for (p
= nbuf
; *p
; p
++)
2885 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2888 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2889 free ((char *) reg
->name
);
2895 for (p
= nbuf
; *p
; p
++)
2897 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2900 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2901 free ((char *) reg
->name
);
2911 *input_line_pointer
= saved_char
;
2912 demand_empty_rest_of_line ();
2915 /* Directives: Instruction set selection. */
2918 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2919 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2920 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2921 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2923 /* Create a new mapping symbol for the transition to STATE. */
2926 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2929 const char * symname
;
2936 type
= BSF_NO_FLAGS
;
2940 type
= BSF_NO_FLAGS
;
2944 type
= BSF_NO_FLAGS
;
2950 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2951 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2956 THUMB_SET_FUNC (symbolP
, 0);
2957 ARM_SET_THUMB (symbolP
, 0);
2958 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2962 THUMB_SET_FUNC (symbolP
, 1);
2963 ARM_SET_THUMB (symbolP
, 1);
2964 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2972 /* Save the mapping symbols for future reference. Also check that
2973 we do not place two mapping symbols at the same offset within a
2974 frag. We'll handle overlap between frags in
2975 check_mapping_symbols.
2977 If .fill or other data filling directive generates zero sized data,
2978 the mapping symbol for the following code will have the same value
2979 as the one generated for the data filling directive. In this case,
2980 we replace the old symbol with the new one at the same address. */
2983 if (frag
->tc_frag_data
.first_map
!= NULL
)
2985 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2986 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2988 frag
->tc_frag_data
.first_map
= symbolP
;
2990 if (frag
->tc_frag_data
.last_map
!= NULL
)
2992 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2993 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2994 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2996 frag
->tc_frag_data
.last_map
= symbolP
;
2999 /* We must sometimes convert a region marked as code to data during
3000 code alignment, if an odd number of bytes have to be padded. The
3001 code mapping symbol is pushed to an aligned address. */
3004 insert_data_mapping_symbol (enum mstate state
,
3005 valueT value
, fragS
*frag
, offsetT bytes
)
3007 /* If there was already a mapping symbol, remove it. */
3008 if (frag
->tc_frag_data
.last_map
!= NULL
3009 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
3011 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
3015 know (frag
->tc_frag_data
.first_map
== symp
);
3016 frag
->tc_frag_data
.first_map
= NULL
;
3018 frag
->tc_frag_data
.last_map
= NULL
;
3019 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
3022 make_mapping_symbol (MAP_DATA
, value
, frag
);
3023 make_mapping_symbol (state
, value
+ bytes
, frag
);
3026 static void mapping_state_2 (enum mstate state
, int max_chars
);
3028 /* Set the mapping state to STATE. Only call this when about to
3029 emit some STATE bytes to the file. */
3031 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
3033 mapping_state (enum mstate state
)
3035 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3037 if (mapstate
== state
)
3038 /* The mapping symbol has already been emitted.
3039 There is nothing else to do. */
3042 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
3044 All ARM instructions require 4-byte alignment.
3045 (Almost) all Thumb instructions require 2-byte alignment.
3047 When emitting instructions into any section, mark the section
3050 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3051 but themselves require 2-byte alignment; this applies to some
3052 PC- relative forms. However, these cases will involve implicit
3053 literal pool generation or an explicit .align >=2, both of
3054 which will cause the section to me marked with sufficient
3055 alignment. Thus, we don't handle those cases here. */
3056 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
3058 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
3059 /* This case will be evaluated later. */
3062 mapping_state_2 (state
, 0);
3065 /* Same as mapping_state, but MAX_CHARS bytes have already been
3066 allocated. Put the mapping symbol that far back. */
3069 mapping_state_2 (enum mstate state
, int max_chars
)
3071 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3073 if (!SEG_NORMAL (now_seg
))
3076 if (mapstate
== state
)
3077 /* The mapping symbol has already been emitted.
3078 There is nothing else to do. */
3081 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
3082 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3084 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3085 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3088 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3091 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3092 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3096 #define mapping_state(x) ((void)0)
3097 #define mapping_state_2(x, y) ((void)0)
3100 /* Find the real, Thumb encoded start of a Thumb function. */
3104 find_real_start (symbolS
* symbolP
)
3107 const char * name
= S_GET_NAME (symbolP
);
3108 symbolS
* new_target
;
3110 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3111 #define STUB_NAME ".real_start_of"
3116 /* The compiler may generate BL instructions to local labels because
3117 it needs to perform a branch to a far away location. These labels
3118 do not have a corresponding ".real_start_of" label. We check
3119 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3120 the ".real_start_of" convention for nonlocal branches. */
3121 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3124 real_start
= concat (STUB_NAME
, name
, NULL
);
3125 new_target
= symbol_find (real_start
);
3128 if (new_target
== NULL
)
3130 as_warn (_("Failed to find real start of function: %s\n"), name
);
3131 new_target
= symbolP
;
3139 opcode_select (int width
)
3146 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3147 as_bad (_("selected processor does not support THUMB opcodes"));
3150 /* No need to force the alignment, since we will have been
3151 coming from ARM mode, which is word-aligned. */
3152 record_alignment (now_seg
, 1);
3159 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3160 as_bad (_("selected processor does not support ARM opcodes"));
3165 frag_align (2, 0, 0);
3167 record_alignment (now_seg
, 1);
3172 as_bad (_("invalid instruction size selected (%d)"), width
);
3177 s_arm (int ignore ATTRIBUTE_UNUSED
)
3180 demand_empty_rest_of_line ();
3184 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3187 demand_empty_rest_of_line ();
3191 s_code (int unused ATTRIBUTE_UNUSED
)
3195 temp
= get_absolute_expression ();
3200 opcode_select (temp
);
3204 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3209 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3211 /* If we are not already in thumb mode go into it, EVEN if
3212 the target processor does not support thumb instructions.
3213 This is used by gcc/config/arm/lib1funcs.asm for example
3214 to compile interworking support functions even if the
3215 target processor should not support interworking. */
3219 record_alignment (now_seg
, 1);
3222 demand_empty_rest_of_line ();
3226 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3230 /* The following label is the name/address of the start of a Thumb function.
3231 We need to know this for the interworking support. */
3232 label_is_thumb_function_name
= TRUE
;
3235 /* Perform a .set directive, but also mark the alias as
3236 being a thumb function. */
3239 s_thumb_set (int equiv
)
3241 /* XXX the following is a duplicate of the code for s_set() in read.c
3242 We cannot just call that code as we need to get at the symbol that
3249 /* Especial apologies for the random logic:
3250 This just grew, and could be parsed much more simply!
3252 delim
= get_symbol_name (& name
);
3253 end_name
= input_line_pointer
;
3254 (void) restore_line_pointer (delim
);
3256 if (*input_line_pointer
!= ',')
3259 as_bad (_("expected comma after name \"%s\""), name
);
3261 ignore_rest_of_line ();
3265 input_line_pointer
++;
3268 if (name
[0] == '.' && name
[1] == '\0')
3270 /* XXX - this should not happen to .thumb_set. */
3274 if ((symbolP
= symbol_find (name
)) == NULL
3275 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3278 /* When doing symbol listings, play games with dummy fragments living
3279 outside the normal fragment chain to record the file and line info
3281 if (listing
& LISTING_SYMBOLS
)
3283 extern struct list_info_struct
* listing_tail
;
3284 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3286 memset (dummy_frag
, 0, sizeof (fragS
));
3287 dummy_frag
->fr_type
= rs_fill
;
3288 dummy_frag
->line
= listing_tail
;
3289 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3290 dummy_frag
->fr_symbol
= symbolP
;
3294 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3297 /* "set" symbols are local unless otherwise specified. */
3298 SF_SET_LOCAL (symbolP
);
3299 #endif /* OBJ_COFF */
3300 } /* Make a new symbol. */
3302 symbol_table_insert (symbolP
);
3307 && S_IS_DEFINED (symbolP
)
3308 && S_GET_SEGMENT (symbolP
) != reg_section
)
3309 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3311 pseudo_set (symbolP
);
3313 demand_empty_rest_of_line ();
3315 /* XXX Now we come to the Thumb specific bit of code. */
3317 THUMB_SET_FUNC (symbolP
, 1);
3318 ARM_SET_THUMB (symbolP
, 1);
3319 #if defined OBJ_ELF || defined OBJ_COFF
3320 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3324 /* Directives: Mode selection. */
3326 /* .syntax [unified|divided] - choose the new unified syntax
3327 (same for Arm and Thumb encoding, modulo slight differences in what
3328 can be represented) or the old divergent syntax for each mode. */
3330 s_syntax (int unused ATTRIBUTE_UNUSED
)
3334 delim
= get_symbol_name (& name
);
3336 if (!strcasecmp (name
, "unified"))
3337 unified_syntax
= TRUE
;
3338 else if (!strcasecmp (name
, "divided"))
3339 unified_syntax
= FALSE
;
3342 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3345 (void) restore_line_pointer (delim
);
3346 demand_empty_rest_of_line ();
3349 /* Directives: sectioning and alignment. */
3352 s_bss (int ignore ATTRIBUTE_UNUSED
)
3354 /* We don't support putting frags in the BSS segment, we fake it by
3355 marking in_bss, then looking at s_skip for clues. */
3356 subseg_set (bss_section
, 0);
3357 demand_empty_rest_of_line ();
3359 #ifdef md_elf_section_change_hook
3360 md_elf_section_change_hook ();
3365 s_even (int ignore ATTRIBUTE_UNUSED
)
3367 /* Never make frag if expect extra pass. */
3369 frag_align (1, 0, 0);
3371 record_alignment (now_seg
, 1);
3373 demand_empty_rest_of_line ();
3376 /* Directives: CodeComposer Studio. */
3378 /* .ref (for CodeComposer Studio syntax only). */
3380 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3382 if (codecomposer_syntax
)
3383 ignore_rest_of_line ();
3385 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3388 /* If name is not NULL, then it is used for marking the beginning of a
3389 function, whereas if it is NULL then it means the function end. */
3391 asmfunc_debug (const char * name
)
3393 static const char * last_name
= NULL
;
3397 gas_assert (last_name
== NULL
);
3400 if (debug_type
== DEBUG_STABS
)
3401 stabs_generate_asm_func (name
, name
);
3405 gas_assert (last_name
!= NULL
);
3407 if (debug_type
== DEBUG_STABS
)
3408 stabs_generate_asm_endfunc (last_name
, last_name
);
3415 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3417 if (codecomposer_syntax
)
3419 switch (asmfunc_state
)
3421 case OUTSIDE_ASMFUNC
:
3422 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3425 case WAITING_ASMFUNC_NAME
:
3426 as_bad (_(".asmfunc repeated."));
3429 case WAITING_ENDASMFUNC
:
3430 as_bad (_(".asmfunc without function."));
3433 demand_empty_rest_of_line ();
3436 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3440 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3442 if (codecomposer_syntax
)
3444 switch (asmfunc_state
)
3446 case OUTSIDE_ASMFUNC
:
3447 as_bad (_(".endasmfunc without a .asmfunc."));
3450 case WAITING_ASMFUNC_NAME
:
3451 as_bad (_(".endasmfunc without function."));
3454 case WAITING_ENDASMFUNC
:
3455 asmfunc_state
= OUTSIDE_ASMFUNC
;
3456 asmfunc_debug (NULL
);
3459 demand_empty_rest_of_line ();
3462 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3466 s_ccs_def (int name
)
3468 if (codecomposer_syntax
)
3471 as_bad (_(".def pseudo-op only available with -mccs flag."));
3474 /* Directives: Literal pools. */
3476 static literal_pool
*
3477 find_literal_pool (void)
3479 literal_pool
* pool
;
3481 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3483 if (pool
->section
== now_seg
3484 && pool
->sub_section
== now_subseg
)
3491 static literal_pool
*
3492 find_or_make_literal_pool (void)
3494 /* Next literal pool ID number. */
3495 static unsigned int latest_pool_num
= 1;
3496 literal_pool
* pool
;
3498 pool
= find_literal_pool ();
3502 /* Create a new pool. */
3503 pool
= XNEW (literal_pool
);
3507 pool
->next_free_entry
= 0;
3508 pool
->section
= now_seg
;
3509 pool
->sub_section
= now_subseg
;
3510 pool
->next
= list_of_pools
;
3511 pool
->symbol
= NULL
;
3512 pool
->alignment
= 2;
3514 /* Add it to the list. */
3515 list_of_pools
= pool
;
3518 /* New pools, and emptied pools, will have a NULL symbol. */
3519 if (pool
->symbol
== NULL
)
3521 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3522 (valueT
) 0, &zero_address_frag
);
3523 pool
->id
= latest_pool_num
++;
3530 /* Add the literal in the global 'inst'
3531 structure to the relevant literal pool. */
3534 add_to_lit_pool (unsigned int nbytes
)
3536 #define PADDING_SLOT 0x1
3537 #define LIT_ENTRY_SIZE_MASK 0xFF
3538 literal_pool
* pool
;
3539 unsigned int entry
, pool_size
= 0;
3540 bfd_boolean padding_slot_p
= FALSE
;
3546 imm1
= inst
.operands
[1].imm
;
3547 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3548 : inst
.relocs
[0].exp
.X_unsigned
? 0
3549 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3550 if (target_big_endian
)
3553 imm2
= inst
.operands
[1].imm
;
3557 pool
= find_or_make_literal_pool ();
3559 /* Check if this literal value is already in the pool. */
3560 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3564 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3565 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3566 && (pool
->literals
[entry
].X_add_number
3567 == inst
.relocs
[0].exp
.X_add_number
)
3568 && (pool
->literals
[entry
].X_md
== nbytes
)
3569 && (pool
->literals
[entry
].X_unsigned
3570 == inst
.relocs
[0].exp
.X_unsigned
))
3573 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3574 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3575 && (pool
->literals
[entry
].X_add_number
3576 == inst
.relocs
[0].exp
.X_add_number
)
3577 && (pool
->literals
[entry
].X_add_symbol
3578 == inst
.relocs
[0].exp
.X_add_symbol
)
3579 && (pool
->literals
[entry
].X_op_symbol
3580 == inst
.relocs
[0].exp
.X_op_symbol
)
3581 && (pool
->literals
[entry
].X_md
== nbytes
))
3584 else if ((nbytes
== 8)
3585 && !(pool_size
& 0x7)
3586 && ((entry
+ 1) != pool
->next_free_entry
)
3587 && (pool
->literals
[entry
].X_op
== O_constant
)
3588 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3589 && (pool
->literals
[entry
].X_unsigned
3590 == inst
.relocs
[0].exp
.X_unsigned
)
3591 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3592 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3593 && (pool
->literals
[entry
+ 1].X_unsigned
3594 == inst
.relocs
[0].exp
.X_unsigned
))
3597 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3598 if (padding_slot_p
&& (nbytes
== 4))
3604 /* Do we need to create a new entry? */
3605 if (entry
== pool
->next_free_entry
)
3607 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3609 inst
.error
= _("literal pool overflow");
3615 /* For 8-byte entries, we align to an 8-byte boundary,
3616 and split it into two 4-byte entries, because on 32-bit
3617 host, 8-byte constants are treated as big num, thus
3618 saved in "generic_bignum" which will be overwritten
3619 by later assignments.
3621 We also need to make sure there is enough space for
3624 We also check to make sure the literal operand is a
3626 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3627 || inst
.relocs
[0].exp
.X_op
== O_big
))
3629 inst
.error
= _("invalid type for literal pool");
3632 else if (pool_size
& 0x7)
3634 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3636 inst
.error
= _("literal pool overflow");
3640 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3641 pool
->literals
[entry
].X_op
= O_constant
;
3642 pool
->literals
[entry
].X_add_number
= 0;
3643 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3644 pool
->next_free_entry
+= 1;
3647 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3649 inst
.error
= _("literal pool overflow");
3653 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3654 pool
->literals
[entry
].X_op
= O_constant
;
3655 pool
->literals
[entry
].X_add_number
= imm1
;
3656 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3657 pool
->literals
[entry
++].X_md
= 4;
3658 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3659 pool
->literals
[entry
].X_op
= O_constant
;
3660 pool
->literals
[entry
].X_add_number
= imm2
;
3661 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3662 pool
->literals
[entry
].X_md
= 4;
3663 pool
->alignment
= 3;
3664 pool
->next_free_entry
+= 1;
3668 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3669 pool
->literals
[entry
].X_md
= 4;
3673 /* PR ld/12974: Record the location of the first source line to reference
3674 this entry in the literal pool. If it turns out during linking that the
3675 symbol does not exist we will be able to give an accurate line number for
3676 the (first use of the) missing reference. */
3677 if (debug_type
== DEBUG_DWARF2
)
3678 dwarf2_where (pool
->locs
+ entry
);
3680 pool
->next_free_entry
+= 1;
3682 else if (padding_slot_p
)
3684 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3685 pool
->literals
[entry
].X_md
= nbytes
;
3688 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3689 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3690 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3696 tc_start_label_without_colon (void)
3698 bfd_boolean ret
= TRUE
;
3700 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3702 const char *label
= input_line_pointer
;
3704 while (!is_end_of_line
[(int) label
[-1]])
3709 as_bad (_("Invalid label '%s'"), label
);
3713 asmfunc_debug (label
);
3715 asmfunc_state
= WAITING_ENDASMFUNC
;
3721 /* Can't use symbol_new here, so have to create a symbol and then at
3722 a later date assign it a value. That's what these functions do. */
3725 symbol_locate (symbolS
* symbolP
,
3726 const char * name
, /* It is copied, the caller can modify. */
3727 segT segment
, /* Segment identifier (SEG_<something>). */
3728 valueT valu
, /* Symbol value. */
3729 fragS
* frag
) /* Associated fragment. */
3732 char * preserved_copy_of_name
;
3734 name_length
= strlen (name
) + 1; /* +1 for \0. */
3735 obstack_grow (¬es
, name
, name_length
);
3736 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3738 #ifdef tc_canonicalize_symbol_name
3739 preserved_copy_of_name
=
3740 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3743 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3745 S_SET_SEGMENT (symbolP
, segment
);
3746 S_SET_VALUE (symbolP
, valu
);
3747 symbol_clear_list_pointers (symbolP
);
3749 symbol_set_frag (symbolP
, frag
);
3751 /* Link to end of symbol chain. */
3753 extern int symbol_table_frozen
;
3755 if (symbol_table_frozen
)
3759 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3761 obj_symbol_new_hook (symbolP
);
3763 #ifdef tc_symbol_new_hook
3764 tc_symbol_new_hook (symbolP
);
3768 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3769 #endif /* DEBUG_SYMS */
3773 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3776 literal_pool
* pool
;
3779 pool
= find_literal_pool ();
3781 || pool
->symbol
== NULL
3782 || pool
->next_free_entry
== 0)
3785 /* Align pool as you have word accesses.
3786 Only make a frag if we have to. */
3788 frag_align (pool
->alignment
, 0, 0);
3790 record_alignment (now_seg
, 2);
3793 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3794 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3796 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3798 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3799 (valueT
) frag_now_fix (), frag_now
);
3800 symbol_table_insert (pool
->symbol
);
3802 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3804 #if defined OBJ_COFF || defined OBJ_ELF
3805 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3808 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3811 if (debug_type
== DEBUG_DWARF2
)
3812 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3814 /* First output the expression in the instruction to the pool. */
3815 emit_expr (&(pool
->literals
[entry
]),
3816 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3819 /* Mark the pool as empty. */
3820 pool
->next_free_entry
= 0;
3821 pool
->symbol
= NULL
;
3825 /* Forward declarations for functions below, in the MD interface
3827 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3828 static valueT
create_unwind_entry (int);
3829 static void start_unwind_section (const segT
, int);
3830 static void add_unwind_opcode (valueT
, int);
3831 static void flush_pending_unwind (void);
3833 /* Directives: Data. */
3836 s_arm_elf_cons (int nbytes
)
3840 #ifdef md_flush_pending_output
3841 md_flush_pending_output ();
3844 if (is_it_end_of_statement ())
3846 demand_empty_rest_of_line ();
3850 #ifdef md_cons_align
3851 md_cons_align (nbytes
);
3854 mapping_state (MAP_DATA
);
3858 char *base
= input_line_pointer
;
3862 if (exp
.X_op
!= O_symbol
)
3863 emit_expr (&exp
, (unsigned int) nbytes
);
3866 char *before_reloc
= input_line_pointer
;
3867 reloc
= parse_reloc (&input_line_pointer
);
3870 as_bad (_("unrecognized relocation suffix"));
3871 ignore_rest_of_line ();
3874 else if (reloc
== BFD_RELOC_UNUSED
)
3875 emit_expr (&exp
, (unsigned int) nbytes
);
3878 reloc_howto_type
*howto
= (reloc_howto_type
*)
3879 bfd_reloc_type_lookup (stdoutput
,
3880 (bfd_reloc_code_real_type
) reloc
);
3881 int size
= bfd_get_reloc_size (howto
);
3883 if (reloc
== BFD_RELOC_ARM_PLT32
)
3885 as_bad (_("(plt) is only valid on branch targets"));
3886 reloc
= BFD_RELOC_UNUSED
;
3891 as_bad (ngettext ("%s relocations do not fit in %d byte",
3892 "%s relocations do not fit in %d bytes",
3894 howto
->name
, nbytes
);
3897 /* We've parsed an expression stopping at O_symbol.
3898 But there may be more expression left now that we
3899 have parsed the relocation marker. Parse it again.
3900 XXX Surely there is a cleaner way to do this. */
3901 char *p
= input_line_pointer
;
3903 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3905 memcpy (save_buf
, base
, input_line_pointer
- base
);
3906 memmove (base
+ (input_line_pointer
- before_reloc
),
3907 base
, before_reloc
- base
);
3909 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3911 memcpy (base
, save_buf
, p
- base
);
3913 offset
= nbytes
- size
;
3914 p
= frag_more (nbytes
);
3915 memset (p
, 0, nbytes
);
3916 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3917 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3923 while (*input_line_pointer
++ == ',');
3925 /* Put terminator back into stream. */
3926 input_line_pointer
--;
3927 demand_empty_rest_of_line ();
3930 /* Emit an expression containing a 32-bit thumb instruction.
3931 Implementation based on put_thumb32_insn. */
3934 emit_thumb32_expr (expressionS
* exp
)
3936 expressionS exp_high
= *exp
;
3938 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3939 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3940 exp
->X_add_number
&= 0xffff;
3941 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3944 /* Guess the instruction size based on the opcode. */
3947 thumb_insn_size (int opcode
)
3949 if ((unsigned int) opcode
< 0xe800u
)
3951 else if ((unsigned int) opcode
>= 0xe8000000u
)
3958 emit_insn (expressionS
*exp
, int nbytes
)
3962 if (exp
->X_op
== O_constant
)
3967 size
= thumb_insn_size (exp
->X_add_number
);
3971 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3973 as_bad (_(".inst.n operand too big. "\
3974 "Use .inst.w instead"));
3979 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3980 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3982 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3984 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3985 emit_thumb32_expr (exp
);
3987 emit_expr (exp
, (unsigned int) size
);
3989 it_fsm_post_encode ();
3993 as_bad (_("cannot determine Thumb instruction size. " \
3994 "Use .inst.n/.inst.w instead"));
3997 as_bad (_("constant expression required"));
4002 /* Like s_arm_elf_cons but do not use md_cons_align and
4003 set the mapping state to MAP_ARM/MAP_THUMB. */
4006 s_arm_elf_inst (int nbytes
)
4008 if (is_it_end_of_statement ())
4010 demand_empty_rest_of_line ();
4014 /* Calling mapping_state () here will not change ARM/THUMB,
4015 but will ensure not to be in DATA state. */
4018 mapping_state (MAP_THUMB
);
4023 as_bad (_("width suffixes are invalid in ARM mode"));
4024 ignore_rest_of_line ();
4030 mapping_state (MAP_ARM
);
4039 if (! emit_insn (& exp
, nbytes
))
4041 ignore_rest_of_line ();
4045 while (*input_line_pointer
++ == ',');
4047 /* Put terminator back into stream. */
4048 input_line_pointer
--;
4049 demand_empty_rest_of_line ();
4052 /* Parse a .rel31 directive. */
4055 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
4062 if (*input_line_pointer
== '1')
4063 highbit
= 0x80000000;
4064 else if (*input_line_pointer
!= '0')
4065 as_bad (_("expected 0 or 1"));
4067 input_line_pointer
++;
4068 if (*input_line_pointer
!= ',')
4069 as_bad (_("missing comma"));
4070 input_line_pointer
++;
4072 #ifdef md_flush_pending_output
4073 md_flush_pending_output ();
4076 #ifdef md_cons_align
4080 mapping_state (MAP_DATA
);
4085 md_number_to_chars (p
, highbit
, 4);
4086 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4087 BFD_RELOC_ARM_PREL31
);
4089 demand_empty_rest_of_line ();
4092 /* Directives: AEABI stack-unwind tables. */
4094 /* Parse an unwind_fnstart directive. Simply records the current location. */
4097 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4099 demand_empty_rest_of_line ();
4100 if (unwind
.proc_start
)
4102 as_bad (_("duplicate .fnstart directive"));
4106 /* Mark the start of the function. */
4107 unwind
.proc_start
= expr_build_dot ();
4109 /* Reset the rest of the unwind info. */
4110 unwind
.opcode_count
= 0;
4111 unwind
.table_entry
= NULL
;
4112 unwind
.personality_routine
= NULL
;
4113 unwind
.personality_index
= -1;
4114 unwind
.frame_size
= 0;
4115 unwind
.fp_offset
= 0;
4116 unwind
.fp_reg
= REG_SP
;
4118 unwind
.sp_restored
= 0;
4122 /* Parse a handlerdata directive. Creates the exception handling table entry
4123 for the function. */
4126 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4128 demand_empty_rest_of_line ();
4129 if (!unwind
.proc_start
)
4130 as_bad (MISSING_FNSTART
);
4132 if (unwind
.table_entry
)
4133 as_bad (_("duplicate .handlerdata directive"));
4135 create_unwind_entry (1);
4138 /* Parse an unwind_fnend directive. Generates the index table entry. */
4141 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4146 unsigned int marked_pr_dependency
;
4148 demand_empty_rest_of_line ();
4150 if (!unwind
.proc_start
)
4152 as_bad (_(".fnend directive without .fnstart"));
4156 /* Add eh table entry. */
4157 if (unwind
.table_entry
== NULL
)
4158 val
= create_unwind_entry (0);
4162 /* Add index table entry. This is two words. */
4163 start_unwind_section (unwind
.saved_seg
, 1);
4164 frag_align (2, 0, 0);
4165 record_alignment (now_seg
, 2);
4167 ptr
= frag_more (8);
4169 where
= frag_now_fix () - 8;
4171 /* Self relative offset of the function start. */
4172 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4173 BFD_RELOC_ARM_PREL31
);
4175 /* Indicate dependency on EHABI-defined personality routines to the
4176 linker, if it hasn't been done already. */
4177 marked_pr_dependency
4178 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4179 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4180 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4182 static const char *const name
[] =
4184 "__aeabi_unwind_cpp_pr0",
4185 "__aeabi_unwind_cpp_pr1",
4186 "__aeabi_unwind_cpp_pr2"
4188 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4189 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4190 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4191 |= 1 << unwind
.personality_index
;
4195 /* Inline exception table entry. */
4196 md_number_to_chars (ptr
+ 4, val
, 4);
4198 /* Self relative offset of the table entry. */
4199 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4200 BFD_RELOC_ARM_PREL31
);
4202 /* Restore the original section. */
4203 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4205 unwind
.proc_start
= NULL
;
4209 /* Parse an unwind_cantunwind directive. */
4212 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4214 demand_empty_rest_of_line ();
4215 if (!unwind
.proc_start
)
4216 as_bad (MISSING_FNSTART
);
4218 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4219 as_bad (_("personality routine specified for cantunwind frame"));
4221 unwind
.personality_index
= -2;
4225 /* Parse a personalityindex directive. */
4228 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4232 if (!unwind
.proc_start
)
4233 as_bad (MISSING_FNSTART
);
4235 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4236 as_bad (_("duplicate .personalityindex directive"));
4240 if (exp
.X_op
!= O_constant
4241 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4243 as_bad (_("bad personality routine number"));
4244 ignore_rest_of_line ();
4248 unwind
.personality_index
= exp
.X_add_number
;
4250 demand_empty_rest_of_line ();
4254 /* Parse a personality directive. */
4257 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4261 if (!unwind
.proc_start
)
4262 as_bad (MISSING_FNSTART
);
4264 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4265 as_bad (_("duplicate .personality directive"));
4267 c
= get_symbol_name (& name
);
4268 p
= input_line_pointer
;
4270 ++ input_line_pointer
;
4271 unwind
.personality_routine
= symbol_find_or_make (name
);
4273 demand_empty_rest_of_line ();
4277 /* Parse a directive saving core registers. */
4280 s_arm_unwind_save_core (void)
4286 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4289 as_bad (_("expected register list"));
4290 ignore_rest_of_line ();
4294 demand_empty_rest_of_line ();
4296 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4297 into .unwind_save {..., sp...}. We aren't bothered about the value of
4298 ip because it is clobbered by calls. */
4299 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4300 && (range
& 0x3000) == 0x1000)
4302 unwind
.opcode_count
--;
4303 unwind
.sp_restored
= 0;
4304 range
= (range
| 0x2000) & ~0x1000;
4305 unwind
.pending_offset
= 0;
4311 /* See if we can use the short opcodes. These pop a block of up to 8
4312 registers starting with r4, plus maybe r14. */
4313 for (n
= 0; n
< 8; n
++)
4315 /* Break at the first non-saved register. */
4316 if ((range
& (1 << (n
+ 4))) == 0)
4319 /* See if there are any other bits set. */
4320 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4322 /* Use the long form. */
4323 op
= 0x8000 | ((range
>> 4) & 0xfff);
4324 add_unwind_opcode (op
, 2);
4328 /* Use the short form. */
4330 op
= 0xa8; /* Pop r14. */
4332 op
= 0xa0; /* Do not pop r14. */
4334 add_unwind_opcode (op
, 1);
4341 op
= 0xb100 | (range
& 0xf);
4342 add_unwind_opcode (op
, 2);
4345 /* Record the number of bytes pushed. */
4346 for (n
= 0; n
< 16; n
++)
4348 if (range
& (1 << n
))
4349 unwind
.frame_size
+= 4;
4354 /* Parse a directive saving FPA registers. */
4357 s_arm_unwind_save_fpa (int reg
)
4363 /* Get Number of registers to transfer. */
4364 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4367 exp
.X_op
= O_illegal
;
4369 if (exp
.X_op
!= O_constant
)
4371 as_bad (_("expected , <constant>"));
4372 ignore_rest_of_line ();
4376 num_regs
= exp
.X_add_number
;
4378 if (num_regs
< 1 || num_regs
> 4)
4380 as_bad (_("number of registers must be in the range [1:4]"));
4381 ignore_rest_of_line ();
4385 demand_empty_rest_of_line ();
4390 op
= 0xb4 | (num_regs
- 1);
4391 add_unwind_opcode (op
, 1);
4396 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4397 add_unwind_opcode (op
, 2);
4399 unwind
.frame_size
+= num_regs
* 12;
4403 /* Parse a directive saving VFP registers for ARMv6 and above. */
4406 s_arm_unwind_save_vfp_armv6 (void)
4411 int num_vfpv3_regs
= 0;
4412 int num_regs_below_16
;
4413 bfd_boolean partial_match
;
4415 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4419 as_bad (_("expected register list"));
4420 ignore_rest_of_line ();
4424 demand_empty_rest_of_line ();
4426 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4427 than FSTMX/FLDMX-style ones). */
4429 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4431 num_vfpv3_regs
= count
;
4432 else if (start
+ count
> 16)
4433 num_vfpv3_regs
= start
+ count
- 16;
4435 if (num_vfpv3_regs
> 0)
4437 int start_offset
= start
> 16 ? start
- 16 : 0;
4438 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4439 add_unwind_opcode (op
, 2);
4442 /* Generate opcode for registers numbered in the range 0 .. 15. */
4443 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4444 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4445 if (num_regs_below_16
> 0)
4447 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4448 add_unwind_opcode (op
, 2);
4451 unwind
.frame_size
+= count
* 8;
4455 /* Parse a directive saving VFP registers for pre-ARMv6. */
4458 s_arm_unwind_save_vfp (void)
4463 bfd_boolean partial_match
;
4465 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4469 as_bad (_("expected register list"));
4470 ignore_rest_of_line ();
4474 demand_empty_rest_of_line ();
4479 op
= 0xb8 | (count
- 1);
4480 add_unwind_opcode (op
, 1);
4485 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4486 add_unwind_opcode (op
, 2);
4488 unwind
.frame_size
+= count
* 8 + 4;
4492 /* Parse a directive saving iWMMXt data registers. */
4495 s_arm_unwind_save_mmxwr (void)
4503 if (*input_line_pointer
== '{')
4504 input_line_pointer
++;
4508 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4512 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4517 as_tsktsk (_("register list not in ascending order"));
4520 if (*input_line_pointer
== '-')
4522 input_line_pointer
++;
4523 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4526 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4529 else if (reg
>= hi_reg
)
4531 as_bad (_("bad register range"));
4534 for (; reg
< hi_reg
; reg
++)
4538 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4540 skip_past_char (&input_line_pointer
, '}');
4542 demand_empty_rest_of_line ();
4544 /* Generate any deferred opcodes because we're going to be looking at
4546 flush_pending_unwind ();
4548 for (i
= 0; i
< 16; i
++)
4550 if (mask
& (1 << i
))
4551 unwind
.frame_size
+= 8;
4554 /* Attempt to combine with a previous opcode. We do this because gcc
4555 likes to output separate unwind directives for a single block of
4557 if (unwind
.opcode_count
> 0)
4559 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4560 if ((i
& 0xf8) == 0xc0)
4563 /* Only merge if the blocks are contiguous. */
4566 if ((mask
& 0xfe00) == (1 << 9))
4568 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4569 unwind
.opcode_count
--;
4572 else if (i
== 6 && unwind
.opcode_count
>= 2)
4574 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4578 op
= 0xffff << (reg
- 1);
4580 && ((mask
& op
) == (1u << (reg
- 1))))
4582 op
= (1 << (reg
+ i
+ 1)) - 1;
4583 op
&= ~((1 << reg
) - 1);
4585 unwind
.opcode_count
-= 2;
4592 /* We want to generate opcodes in the order the registers have been
4593 saved, ie. descending order. */
4594 for (reg
= 15; reg
>= -1; reg
--)
4596 /* Save registers in blocks. */
4598 || !(mask
& (1 << reg
)))
4600 /* We found an unsaved reg. Generate opcodes to save the
4607 op
= 0xc0 | (hi_reg
- 10);
4608 add_unwind_opcode (op
, 1);
4613 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4614 add_unwind_opcode (op
, 2);
4623 ignore_rest_of_line ();
4627 s_arm_unwind_save_mmxwcg (void)
4634 if (*input_line_pointer
== '{')
4635 input_line_pointer
++;
4637 skip_whitespace (input_line_pointer
);
4641 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4645 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4651 as_tsktsk (_("register list not in ascending order"));
4654 if (*input_line_pointer
== '-')
4656 input_line_pointer
++;
4657 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4660 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4663 else if (reg
>= hi_reg
)
4665 as_bad (_("bad register range"));
4668 for (; reg
< hi_reg
; reg
++)
4672 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4674 skip_past_char (&input_line_pointer
, '}');
4676 demand_empty_rest_of_line ();
4678 /* Generate any deferred opcodes because we're going to be looking at
4680 flush_pending_unwind ();
4682 for (reg
= 0; reg
< 16; reg
++)
4684 if (mask
& (1 << reg
))
4685 unwind
.frame_size
+= 4;
4688 add_unwind_opcode (op
, 2);
4691 ignore_rest_of_line ();
4695 /* Parse an unwind_save directive.
4696 If the argument is non-zero, this is a .vsave directive. */
4699 s_arm_unwind_save (int arch_v6
)
4702 struct reg_entry
*reg
;
4703 bfd_boolean had_brace
= FALSE
;
4705 if (!unwind
.proc_start
)
4706 as_bad (MISSING_FNSTART
);
4708 /* Figure out what sort of save we have. */
4709 peek
= input_line_pointer
;
4717 reg
= arm_reg_parse_multi (&peek
);
4721 as_bad (_("register expected"));
4722 ignore_rest_of_line ();
4731 as_bad (_("FPA .unwind_save does not take a register list"));
4732 ignore_rest_of_line ();
4735 input_line_pointer
= peek
;
4736 s_arm_unwind_save_fpa (reg
->number
);
4740 s_arm_unwind_save_core ();
4745 s_arm_unwind_save_vfp_armv6 ();
4747 s_arm_unwind_save_vfp ();
4750 case REG_TYPE_MMXWR
:
4751 s_arm_unwind_save_mmxwr ();
4754 case REG_TYPE_MMXWCG
:
4755 s_arm_unwind_save_mmxwcg ();
4759 as_bad (_(".unwind_save does not support this kind of register"));
4760 ignore_rest_of_line ();
4765 /* Parse an unwind_movsp directive. */
4768 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4774 if (!unwind
.proc_start
)
4775 as_bad (MISSING_FNSTART
);
4777 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4780 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4781 ignore_rest_of_line ();
4785 /* Optional constant. */
4786 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4788 if (immediate_for_directive (&offset
) == FAIL
)
4794 demand_empty_rest_of_line ();
4796 if (reg
== REG_SP
|| reg
== REG_PC
)
4798 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4802 if (unwind
.fp_reg
!= REG_SP
)
4803 as_bad (_("unexpected .unwind_movsp directive"));
4805 /* Generate opcode to restore the value. */
4807 add_unwind_opcode (op
, 1);
4809 /* Record the information for later. */
4810 unwind
.fp_reg
= reg
;
4811 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4812 unwind
.sp_restored
= 1;
4815 /* Parse an unwind_pad directive. */
4818 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4822 if (!unwind
.proc_start
)
4823 as_bad (MISSING_FNSTART
);
4825 if (immediate_for_directive (&offset
) == FAIL
)
4830 as_bad (_("stack increment must be multiple of 4"));
4831 ignore_rest_of_line ();
4835 /* Don't generate any opcodes, just record the details for later. */
4836 unwind
.frame_size
+= offset
;
4837 unwind
.pending_offset
+= offset
;
4839 demand_empty_rest_of_line ();
4842 /* Parse an unwind_setfp directive. */
4845 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4851 if (!unwind
.proc_start
)
4852 as_bad (MISSING_FNSTART
);
4854 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4855 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4858 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4860 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4862 as_bad (_("expected <reg>, <reg>"));
4863 ignore_rest_of_line ();
4867 /* Optional constant. */
4868 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4870 if (immediate_for_directive (&offset
) == FAIL
)
4876 demand_empty_rest_of_line ();
4878 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4880 as_bad (_("register must be either sp or set by a previous"
4881 "unwind_movsp directive"));
4885 /* Don't generate any opcodes, just record the information for later. */
4886 unwind
.fp_reg
= fp_reg
;
4888 if (sp_reg
== REG_SP
)
4889 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4891 unwind
.fp_offset
-= offset
;
4894 /* Parse an unwind_raw directive. */
4897 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4900 /* This is an arbitrary limit. */
4901 unsigned char op
[16];
4904 if (!unwind
.proc_start
)
4905 as_bad (MISSING_FNSTART
);
4908 if (exp
.X_op
== O_constant
4909 && skip_past_comma (&input_line_pointer
) != FAIL
)
4911 unwind
.frame_size
+= exp
.X_add_number
;
4915 exp
.X_op
= O_illegal
;
4917 if (exp
.X_op
!= O_constant
)
4919 as_bad (_("expected <offset>, <opcode>"));
4920 ignore_rest_of_line ();
4926 /* Parse the opcode. */
4931 as_bad (_("unwind opcode too long"));
4932 ignore_rest_of_line ();
4934 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4936 as_bad (_("invalid unwind opcode"));
4937 ignore_rest_of_line ();
4940 op
[count
++] = exp
.X_add_number
;
4942 /* Parse the next byte. */
4943 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4949 /* Add the opcode bytes in reverse order. */
4951 add_unwind_opcode (op
[count
], 1);
4953 demand_empty_rest_of_line ();
4957 /* Parse a .eabi_attribute directive. */
4960 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4962 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4964 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4965 attributes_set_explicitly
[tag
] = 1;
4968 /* Emit a tls fix for the symbol. */
4971 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4975 #ifdef md_flush_pending_output
4976 md_flush_pending_output ();
4979 #ifdef md_cons_align
4983 /* Since we're just labelling the code, there's no need to define a
4986 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4987 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4988 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4989 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4991 #endif /* OBJ_ELF */
4993 static void s_arm_arch (int);
4994 static void s_arm_object_arch (int);
4995 static void s_arm_cpu (int);
4996 static void s_arm_fpu (int);
4997 static void s_arm_arch_extension (int);
5002 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
5009 if (exp
.X_op
== O_symbol
)
5010 exp
.X_op
= O_secrel
;
5012 emit_expr (&exp
, 4);
5014 while (*input_line_pointer
++ == ',');
5016 input_line_pointer
--;
5017 demand_empty_rest_of_line ();
5022 arm_is_largest_exponent_ok (int precision
)
5024 /* precision == 1 ensures that this will only return
5025 true for 16 bit floats. */
5026 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
5030 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
5034 enum fp_16bit_format new_format
;
5036 new_format
= ARM_FP16_FORMAT_DEFAULT
;
5038 name
= input_line_pointer
;
5039 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
5040 input_line_pointer
++;
5042 saved_char
= *input_line_pointer
;
5043 *input_line_pointer
= 0;
5045 if (strcasecmp (name
, "ieee") == 0)
5046 new_format
= ARM_FP16_FORMAT_IEEE
;
5047 else if (strcasecmp (name
, "alternative") == 0)
5048 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
5051 as_bad (_("unrecognised float16 format \"%s\""), name
);
5055 /* Only set fp16_format if it is still the default (aka not already
5057 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
5058 fp16_format
= new_format
;
5061 if (new_format
!= fp16_format
)
5062 as_warn (_("float16 format cannot be set more than once, ignoring."));
5066 *input_line_pointer
= saved_char
;
5067 ignore_rest_of_line ();
5070 /* This table describes all the machine specific pseudo-ops the assembler
5071 has to support. The fields are:
5072 pseudo-op name without dot
5073 function to call to execute this pseudo-op
5074 Integer arg to pass to the function. */
5076 const pseudo_typeS md_pseudo_table
[] =
5078 /* Never called because '.req' does not start a line. */
5079 { "req", s_req
, 0 },
5080 /* Following two are likewise never called. */
5083 { "unreq", s_unreq
, 0 },
5084 { "bss", s_bss
, 0 },
5085 { "align", s_align_ptwo
, 2 },
5086 { "arm", s_arm
, 0 },
5087 { "thumb", s_thumb
, 0 },
5088 { "code", s_code
, 0 },
5089 { "force_thumb", s_force_thumb
, 0 },
5090 { "thumb_func", s_thumb_func
, 0 },
5091 { "thumb_set", s_thumb_set
, 0 },
5092 { "even", s_even
, 0 },
5093 { "ltorg", s_ltorg
, 0 },
5094 { "pool", s_ltorg
, 0 },
5095 { "syntax", s_syntax
, 0 },
5096 { "cpu", s_arm_cpu
, 0 },
5097 { "arch", s_arm_arch
, 0 },
5098 { "object_arch", s_arm_object_arch
, 0 },
5099 { "fpu", s_arm_fpu
, 0 },
5100 { "arch_extension", s_arm_arch_extension
, 0 },
5102 { "word", s_arm_elf_cons
, 4 },
5103 { "long", s_arm_elf_cons
, 4 },
5104 { "inst.n", s_arm_elf_inst
, 2 },
5105 { "inst.w", s_arm_elf_inst
, 4 },
5106 { "inst", s_arm_elf_inst
, 0 },
5107 { "rel31", s_arm_rel31
, 0 },
5108 { "fnstart", s_arm_unwind_fnstart
, 0 },
5109 { "fnend", s_arm_unwind_fnend
, 0 },
5110 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5111 { "personality", s_arm_unwind_personality
, 0 },
5112 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5113 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5114 { "save", s_arm_unwind_save
, 0 },
5115 { "vsave", s_arm_unwind_save
, 1 },
5116 { "movsp", s_arm_unwind_movsp
, 0 },
5117 { "pad", s_arm_unwind_pad
, 0 },
5118 { "setfp", s_arm_unwind_setfp
, 0 },
5119 { "unwind_raw", s_arm_unwind_raw
, 0 },
5120 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5121 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5125 /* These are used for dwarf. */
5129 /* These are used for dwarf2. */
5130 { "file", dwarf2_directive_file
, 0 },
5131 { "loc", dwarf2_directive_loc
, 0 },
5132 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5134 { "extend", float_cons
, 'x' },
5135 { "ldouble", float_cons
, 'x' },
5136 { "packed", float_cons
, 'p' },
5137 { "bfloat16", float_cons
, 'b' },
5139 {"secrel32", pe_directive_secrel
, 0},
5142 /* These are for compatibility with CodeComposer Studio. */
5143 {"ref", s_ccs_ref
, 0},
5144 {"def", s_ccs_def
, 0},
5145 {"asmfunc", s_ccs_asmfunc
, 0},
5146 {"endasmfunc", s_ccs_endasmfunc
, 0},
5148 {"float16", float_cons
, 'h' },
5149 {"float16_format", set_fp16_format
, 0 },
5154 /* Parser functions used exclusively in instruction operands. */
5156 /* Generic immediate-value read function for use in insn parsing.
5157 STR points to the beginning of the immediate (the leading #);
5158 VAL receives the value; if the value is outside [MIN, MAX]
5159 issue an error. PREFIX_OPT is true if the immediate prefix is
5163 parse_immediate (char **str
, int *val
, int min
, int max
,
5164 bfd_boolean prefix_opt
)
5168 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5169 if (exp
.X_op
!= O_constant
)
5171 inst
.error
= _("constant expression required");
5175 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5177 inst
.error
= _("immediate value out of range");
5181 *val
= exp
.X_add_number
;
5185 /* Less-generic immediate-value read function with the possibility of loading a
5186 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5187 instructions. Puts the result directly in inst.operands[i]. */
5190 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5191 bfd_boolean allow_symbol_p
)
5194 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5197 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5199 if (exp_p
->X_op
== O_constant
)
5201 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5202 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5203 O_constant. We have to be careful not to break compilation for
5204 32-bit X_add_number, though. */
5205 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5207 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5208 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5210 inst
.operands
[i
].regisimm
= 1;
5213 else if (exp_p
->X_op
== O_big
5214 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5216 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5218 /* Bignums have their least significant bits in
5219 generic_bignum[0]. Make sure we put 32 bits in imm and
5220 32 bits in reg, in a (hopefully) portable way. */
5221 gas_assert (parts
!= 0);
5223 /* Make sure that the number is not too big.
5224 PR 11972: Bignums can now be sign-extended to the
5225 size of a .octa so check that the out of range bits
5226 are all zero or all one. */
5227 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5229 LITTLENUM_TYPE m
= -1;
5231 if (generic_bignum
[parts
* 2] != 0
5232 && generic_bignum
[parts
* 2] != m
)
5235 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5236 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5240 inst
.operands
[i
].imm
= 0;
5241 for (j
= 0; j
< parts
; j
++, idx
++)
5242 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5243 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5244 inst
.operands
[i
].reg
= 0;
5245 for (j
= 0; j
< parts
; j
++, idx
++)
5246 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5247 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5248 inst
.operands
[i
].regisimm
= 1;
5250 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5258 /* Returns the pseudo-register number of an FPA immediate constant,
5259 or FAIL if there isn't a valid constant here. */
5262 parse_fpa_immediate (char ** str
)
5264 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5270 /* First try and match exact strings, this is to guarantee
5271 that some formats will work even for cross assembly. */
5273 for (i
= 0; fp_const
[i
]; i
++)
5275 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5279 *str
+= strlen (fp_const
[i
]);
5280 if (is_end_of_line
[(unsigned char) **str
])
5286 /* Just because we didn't get a match doesn't mean that the constant
5287 isn't valid, just that it is in a format that we don't
5288 automatically recognize. Try parsing it with the standard
5289 expression routines. */
5291 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5293 /* Look for a raw floating point number. */
5294 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5295 && is_end_of_line
[(unsigned char) *save_in
])
5297 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5299 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5301 if (words
[j
] != fp_values
[i
][j
])
5305 if (j
== MAX_LITTLENUMS
)
5313 /* Try and parse a more complex expression, this will probably fail
5314 unless the code uses a floating point prefix (eg "0f"). */
5315 save_in
= input_line_pointer
;
5316 input_line_pointer
= *str
;
5317 if (expression (&exp
) == absolute_section
5318 && exp
.X_op
== O_big
5319 && exp
.X_add_number
< 0)
5321 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5323 #define X_PRECISION 5
5324 #define E_PRECISION 15L
5325 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5327 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5329 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5331 if (words
[j
] != fp_values
[i
][j
])
5335 if (j
== MAX_LITTLENUMS
)
5337 *str
= input_line_pointer
;
5338 input_line_pointer
= save_in
;
5345 *str
= input_line_pointer
;
5346 input_line_pointer
= save_in
;
5347 inst
.error
= _("invalid FPA immediate expression");
5351 /* Returns 1 if a number has "quarter-precision" float format
5352 0baBbbbbbc defgh000 00000000 00000000. */
5355 is_quarter_float (unsigned imm
)
5357 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5358 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5362 /* Detect the presence of a floating point or integer zero constant,
5366 parse_ifimm_zero (char **in
)
5370 if (!is_immediate_prefix (**in
))
5372 /* In unified syntax, all prefixes are optional. */
5373 if (!unified_syntax
)
5379 /* Accept #0x0 as a synonym for #0. */
5380 if (strncmp (*in
, "0x", 2) == 0)
5383 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5388 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5389 &generic_floating_point_number
);
5392 && generic_floating_point_number
.sign
== '+'
5393 && (generic_floating_point_number
.low
5394 > generic_floating_point_number
.leader
))
5400 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5401 0baBbbbbbc defgh000 00000000 00000000.
5402 The zero and minus-zero cases need special handling, since they can't be
5403 encoded in the "quarter-precision" float format, but can nonetheless be
5404 loaded as integer constants. */
5407 parse_qfloat_immediate (char **ccp
, int *immed
)
5411 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5412 int found_fpchar
= 0;
5414 skip_past_char (&str
, '#');
5416 /* We must not accidentally parse an integer as a floating-point number. Make
5417 sure that the value we parse is not an integer by checking for special
5418 characters '.' or 'e'.
5419 FIXME: This is a horrible hack, but doing better is tricky because type
5420 information isn't in a very usable state at parse time. */
5422 skip_whitespace (fpnum
);
5424 if (strncmp (fpnum
, "0x", 2) == 0)
5428 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5429 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5439 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5441 unsigned fpword
= 0;
5444 /* Our FP word must be 32 bits (single-precision FP). */
5445 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5447 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5451 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5464 /* Shift operands. */
5467 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5470 struct asm_shift_name
5473 enum shift_kind kind
;
5476 /* Third argument to parse_shift. */
5477 enum parse_shift_mode
5479 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5480 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5481 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5482 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5483 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5484 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5487 /* Parse a <shift> specifier on an ARM data processing instruction.
5488 This has three forms:
5490 (LSL|LSR|ASL|ASR|ROR) Rs
5491 (LSL|LSR|ASL|ASR|ROR) #imm
5494 Note that ASL is assimilated to LSL in the instruction encoding, and
5495 RRX to ROR #0 (which cannot be written as such). */
5498 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5500 const struct asm_shift_name
*shift_name
;
5501 enum shift_kind shift
;
5506 for (p
= *str
; ISALPHA (*p
); p
++)
5511 inst
.error
= _("shift expression expected");
5515 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5518 if (shift_name
== NULL
)
5520 inst
.error
= _("shift expression expected");
5524 shift
= shift_name
->kind
;
5528 case NO_SHIFT_RESTRICT
:
5529 case SHIFT_IMMEDIATE
:
5530 if (shift
== SHIFT_UXTW
)
5532 inst
.error
= _("'UXTW' not allowed here");
5537 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5538 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5540 inst
.error
= _("'LSL' or 'ASR' required");
5545 case SHIFT_LSL_IMMEDIATE
:
5546 if (shift
!= SHIFT_LSL
)
5548 inst
.error
= _("'LSL' required");
5553 case SHIFT_ASR_IMMEDIATE
:
5554 if (shift
!= SHIFT_ASR
)
5556 inst
.error
= _("'ASR' required");
5560 case SHIFT_UXTW_IMMEDIATE
:
5561 if (shift
!= SHIFT_UXTW
)
5563 inst
.error
= _("'UXTW' required");
5571 if (shift
!= SHIFT_RRX
)
5573 /* Whitespace can appear here if the next thing is a bare digit. */
5574 skip_whitespace (p
);
5576 if (mode
== NO_SHIFT_RESTRICT
5577 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5579 inst
.operands
[i
].imm
= reg
;
5580 inst
.operands
[i
].immisreg
= 1;
5582 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5585 inst
.operands
[i
].shift_kind
= shift
;
5586 inst
.operands
[i
].shifted
= 1;
5591 /* Parse a <shifter_operand> for an ARM data processing instruction:
5594 #<immediate>, <rotate>
5598 where <shift> is defined by parse_shift above, and <rotate> is a
5599 multiple of 2 between 0 and 30. Validation of immediate operands
5600 is deferred to md_apply_fix. */
5603 parse_shifter_operand (char **str
, int i
)
5608 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5610 inst
.operands
[i
].reg
= value
;
5611 inst
.operands
[i
].isreg
= 1;
5613 /* parse_shift will override this if appropriate */
5614 inst
.relocs
[0].exp
.X_op
= O_constant
;
5615 inst
.relocs
[0].exp
.X_add_number
= 0;
5617 if (skip_past_comma (str
) == FAIL
)
5620 /* Shift operation on register. */
5621 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5624 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5627 if (skip_past_comma (str
) == SUCCESS
)
5629 /* #x, y -- ie explicit rotation by Y. */
5630 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5633 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5635 inst
.error
= _("constant expression expected");
5639 value
= exp
.X_add_number
;
5640 if (value
< 0 || value
> 30 || value
% 2 != 0)
5642 inst
.error
= _("invalid rotation");
5645 if (inst
.relocs
[0].exp
.X_add_number
< 0
5646 || inst
.relocs
[0].exp
.X_add_number
> 255)
5648 inst
.error
= _("invalid constant");
5652 /* Encode as specified. */
5653 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5657 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5658 inst
.relocs
[0].pc_rel
= 0;
5662 /* Group relocation information. Each entry in the table contains the
5663 textual name of the relocation as may appear in assembler source
5664 and must end with a colon.
5665 Along with this textual name are the relocation codes to be used if
5666 the corresponding instruction is an ALU instruction (ADD or SUB only),
5667 an LDR, an LDRS, or an LDC. */
5669 struct group_reloc_table_entry
5680 /* Varieties of non-ALU group relocation. */
5688 static struct group_reloc_table_entry group_reloc_table
[] =
5689 { /* Program counter relative: */
5691 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5696 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5697 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5698 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5699 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5701 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5706 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5707 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5708 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5709 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5711 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5712 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5713 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5714 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5715 /* Section base relative */
5717 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5722 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5723 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5724 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5725 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5727 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5732 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5733 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5734 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5735 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5737 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5738 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5739 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5740 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5741 /* Absolute thumb alu relocations. */
5743 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5748 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5753 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5758 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5763 /* Given the address of a pointer pointing to the textual name of a group
5764 relocation as may appear in assembler source, attempt to find its details
5765 in group_reloc_table. The pointer will be updated to the character after
5766 the trailing colon. On failure, FAIL will be returned; SUCCESS
5767 otherwise. On success, *entry will be updated to point at the relevant
5768 group_reloc_table entry. */
5771 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5774 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5776 int length
= strlen (group_reloc_table
[i
].name
);
5778 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5779 && (*str
)[length
] == ':')
5781 *out
= &group_reloc_table
[i
];
5782 *str
+= (length
+ 1);
5790 /* Parse a <shifter_operand> for an ARM data processing instruction
5791 (as for parse_shifter_operand) where group relocations are allowed:
5794 #<immediate>, <rotate>
5795 #:<group_reloc>:<expression>
5799 where <group_reloc> is one of the strings defined in group_reloc_table.
5800 The hashes are optional.
5802 Everything else is as for parse_shifter_operand. */
5804 static parse_operand_result
5805 parse_shifter_operand_group_reloc (char **str
, int i
)
5807 /* Determine if we have the sequence of characters #: or just :
5808 coming next. If we do, then we check for a group relocation.
5809 If we don't, punt the whole lot to parse_shifter_operand. */
5811 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5812 || (*str
)[0] == ':')
5814 struct group_reloc_table_entry
*entry
;
5816 if ((*str
)[0] == '#')
5821 /* Try to parse a group relocation. Anything else is an error. */
5822 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5824 inst
.error
= _("unknown group relocation");
5825 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5828 /* We now have the group relocation table entry corresponding to
5829 the name in the assembler source. Next, we parse the expression. */
5830 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5831 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5833 /* Record the relocation type (always the ALU variant here). */
5834 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5835 gas_assert (inst
.relocs
[0].type
!= 0);
5837 return PARSE_OPERAND_SUCCESS
;
5840 return parse_shifter_operand (str
, i
) == SUCCESS
5841 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5843 /* Never reached. */
5846 /* Parse a Neon alignment expression. Information is written to
5847 inst.operands[i]. We assume the initial ':' has been skipped.
5849 align .imm = align << 8, .immisalign=1, .preind=0 */
5850 static parse_operand_result
5851 parse_neon_alignment (char **str
, int i
)
5856 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5858 if (exp
.X_op
!= O_constant
)
5860 inst
.error
= _("alignment must be constant");
5861 return PARSE_OPERAND_FAIL
;
5864 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5865 inst
.operands
[i
].immisalign
= 1;
5866 /* Alignments are not pre-indexes. */
5867 inst
.operands
[i
].preind
= 0;
5870 return PARSE_OPERAND_SUCCESS
;
5873 /* Parse all forms of an ARM address expression. Information is written
5874 to inst.operands[i] and/or inst.relocs[0].
5876 Preindexed addressing (.preind=1):
5878 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5879 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5880 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5881 .shift_kind=shift .relocs[0].exp=shift_imm
5883 These three may have a trailing ! which causes .writeback to be set also.
5885 Postindexed addressing (.postind=1, .writeback=1):
5887 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5888 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5889 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5890 .shift_kind=shift .relocs[0].exp=shift_imm
5892 Unindexed addressing (.preind=0, .postind=0):
5894 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5898 [Rn]{!} shorthand for [Rn,#0]{!}
5899 =immediate .isreg=0 .relocs[0].exp=immediate
5900 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5902 It is the caller's responsibility to check for addressing modes not
5903 supported by the instruction, and to set inst.relocs[0].type. */
5905 static parse_operand_result
5906 parse_address_main (char **str
, int i
, int group_relocations
,
5907 group_reloc_type group_type
)
5912 if (skip_past_char (&p
, '[') == FAIL
)
5914 if (skip_past_char (&p
, '=') == FAIL
)
5916 /* Bare address - translate to PC-relative offset. */
5917 inst
.relocs
[0].pc_rel
= 1;
5918 inst
.operands
[i
].reg
= REG_PC
;
5919 inst
.operands
[i
].isreg
= 1;
5920 inst
.operands
[i
].preind
= 1;
5922 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5923 return PARSE_OPERAND_FAIL
;
5925 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5926 /*allow_symbol_p=*/TRUE
))
5927 return PARSE_OPERAND_FAIL
;
5930 return PARSE_OPERAND_SUCCESS
;
5933 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5934 skip_whitespace (p
);
5936 if (group_type
== GROUP_MVE
)
5938 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5939 struct neon_type_el et
;
5940 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5942 inst
.operands
[i
].isquad
= 1;
5944 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5946 inst
.error
= BAD_ADDR_MODE
;
5947 return PARSE_OPERAND_FAIL
;
5950 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5952 if (group_type
== GROUP_MVE
)
5953 inst
.error
= BAD_ADDR_MODE
;
5955 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5956 return PARSE_OPERAND_FAIL
;
5958 inst
.operands
[i
].reg
= reg
;
5959 inst
.operands
[i
].isreg
= 1;
5961 if (skip_past_comma (&p
) == SUCCESS
)
5963 inst
.operands
[i
].preind
= 1;
5966 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5968 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5969 struct neon_type_el et
;
5970 if (group_type
== GROUP_MVE
5971 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5973 inst
.operands
[i
].immisreg
= 2;
5974 inst
.operands
[i
].imm
= reg
;
5976 if (skip_past_comma (&p
) == SUCCESS
)
5978 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5980 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5981 inst
.relocs
[0].exp
.X_add_number
= 0;
5984 return PARSE_OPERAND_FAIL
;
5987 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5989 inst
.operands
[i
].imm
= reg
;
5990 inst
.operands
[i
].immisreg
= 1;
5992 if (skip_past_comma (&p
) == SUCCESS
)
5993 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5994 return PARSE_OPERAND_FAIL
;
5996 else if (skip_past_char (&p
, ':') == SUCCESS
)
5998 /* FIXME: '@' should be used here, but it's filtered out by generic
5999 code before we get to see it here. This may be subject to
6001 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6003 if (result
!= PARSE_OPERAND_SUCCESS
)
6008 if (inst
.operands
[i
].negative
)
6010 inst
.operands
[i
].negative
= 0;
6014 if (group_relocations
6015 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
6017 struct group_reloc_table_entry
*entry
;
6019 /* Skip over the #: or : sequence. */
6025 /* Try to parse a group relocation. Anything else is an
6027 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
6029 inst
.error
= _("unknown group relocation");
6030 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6033 /* We now have the group relocation table entry corresponding to
6034 the name in the assembler source. Next, we parse the
6036 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6037 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6039 /* Record the relocation type. */
6044 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
6049 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
6054 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
6061 if (inst
.relocs
[0].type
== 0)
6063 inst
.error
= _("this group relocation is not allowed on this instruction");
6064 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6071 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6072 return PARSE_OPERAND_FAIL
;
6073 /* If the offset is 0, find out if it's a +0 or -0. */
6074 if (inst
.relocs
[0].exp
.X_op
== O_constant
6075 && inst
.relocs
[0].exp
.X_add_number
== 0)
6077 skip_whitespace (q
);
6081 skip_whitespace (q
);
6084 inst
.operands
[i
].negative
= 1;
6089 else if (skip_past_char (&p
, ':') == SUCCESS
)
6091 /* FIXME: '@' should be used here, but it's filtered out by generic code
6092 before we get to see it here. This may be subject to change. */
6093 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6095 if (result
!= PARSE_OPERAND_SUCCESS
)
6099 if (skip_past_char (&p
, ']') == FAIL
)
6101 inst
.error
= _("']' expected");
6102 return PARSE_OPERAND_FAIL
;
6105 if (skip_past_char (&p
, '!') == SUCCESS
)
6106 inst
.operands
[i
].writeback
= 1;
6108 else if (skip_past_comma (&p
) == SUCCESS
)
6110 if (skip_past_char (&p
, '{') == SUCCESS
)
6112 /* [Rn], {expr} - unindexed, with option */
6113 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6114 0, 255, TRUE
) == FAIL
)
6115 return PARSE_OPERAND_FAIL
;
6117 if (skip_past_char (&p
, '}') == FAIL
)
6119 inst
.error
= _("'}' expected at end of 'option' field");
6120 return PARSE_OPERAND_FAIL
;
6122 if (inst
.operands
[i
].preind
)
6124 inst
.error
= _("cannot combine index with option");
6125 return PARSE_OPERAND_FAIL
;
6128 return PARSE_OPERAND_SUCCESS
;
6132 inst
.operands
[i
].postind
= 1;
6133 inst
.operands
[i
].writeback
= 1;
6135 if (inst
.operands
[i
].preind
)
6137 inst
.error
= _("cannot combine pre- and post-indexing");
6138 return PARSE_OPERAND_FAIL
;
6142 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6144 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6145 struct neon_type_el et
;
6146 if (group_type
== GROUP_MVE
6147 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6149 inst
.operands
[i
].immisreg
= 2;
6150 inst
.operands
[i
].imm
= reg
;
6152 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6154 /* We might be using the immediate for alignment already. If we
6155 are, OR the register number into the low-order bits. */
6156 if (inst
.operands
[i
].immisalign
)
6157 inst
.operands
[i
].imm
|= reg
;
6159 inst
.operands
[i
].imm
= reg
;
6160 inst
.operands
[i
].immisreg
= 1;
6162 if (skip_past_comma (&p
) == SUCCESS
)
6163 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6164 return PARSE_OPERAND_FAIL
;
6170 if (inst
.operands
[i
].negative
)
6172 inst
.operands
[i
].negative
= 0;
6175 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6176 return PARSE_OPERAND_FAIL
;
6177 /* If the offset is 0, find out if it's a +0 or -0. */
6178 if (inst
.relocs
[0].exp
.X_op
== O_constant
6179 && inst
.relocs
[0].exp
.X_add_number
== 0)
6181 skip_whitespace (q
);
6185 skip_whitespace (q
);
6188 inst
.operands
[i
].negative
= 1;
6194 /* If at this point neither .preind nor .postind is set, we have a
6195 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6196 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6198 inst
.operands
[i
].preind
= 1;
6199 inst
.relocs
[0].exp
.X_op
= O_constant
;
6200 inst
.relocs
[0].exp
.X_add_number
= 0;
6203 return PARSE_OPERAND_SUCCESS
;
6207 parse_address (char **str
, int i
)
6209 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6213 static parse_operand_result
6214 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6216 return parse_address_main (str
, i
, 1, type
);
6219 /* Parse an operand for a MOVW or MOVT instruction. */
6221 parse_half (char **str
)
6226 skip_past_char (&p
, '#');
6227 if (strncasecmp (p
, ":lower16:", 9) == 0)
6228 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6229 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6230 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6232 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6235 skip_whitespace (p
);
6238 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6241 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6243 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6245 inst
.error
= _("constant expression expected");
6248 if (inst
.relocs
[0].exp
.X_add_number
< 0
6249 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6251 inst
.error
= _("immediate value out of range");
6259 /* Miscellaneous. */
6261 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6262 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6264 parse_psr (char **str
, bfd_boolean lhs
)
6267 unsigned long psr_field
;
6268 const struct asm_psr
*psr
;
6270 bfd_boolean is_apsr
= FALSE
;
6271 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6273 /* PR gas/12698: If the user has specified -march=all then m_profile will
6274 be TRUE, but we want to ignore it in this case as we are building for any
6275 CPU type, including non-m variants. */
6276 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6279 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6280 feature for ease of use and backwards compatibility. */
6282 if (strncasecmp (p
, "SPSR", 4) == 0)
6285 goto unsupported_psr
;
6287 psr_field
= SPSR_BIT
;
6289 else if (strncasecmp (p
, "CPSR", 4) == 0)
6292 goto unsupported_psr
;
6296 else if (strncasecmp (p
, "APSR", 4) == 0)
6298 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6299 and ARMv7-R architecture CPUs. */
6308 while (ISALNUM (*p
) || *p
== '_');
6310 if (strncasecmp (start
, "iapsr", 5) == 0
6311 || strncasecmp (start
, "eapsr", 5) == 0
6312 || strncasecmp (start
, "xpsr", 4) == 0
6313 || strncasecmp (start
, "psr", 3) == 0)
6314 p
= start
+ strcspn (start
, "rR") + 1;
6316 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6322 /* If APSR is being written, a bitfield may be specified. Note that
6323 APSR itself is handled above. */
6324 if (psr
->field
<= 3)
6326 psr_field
= psr
->field
;
6332 /* M-profile MSR instructions have the mask field set to "10", except
6333 *PSR variants which modify APSR, which may use a different mask (and
6334 have been handled already). Do that by setting the PSR_f field
6336 return psr
->field
| (lhs
? PSR_f
: 0);
6339 goto unsupported_psr
;
6345 /* A suffix follows. */
6351 while (ISALNUM (*p
) || *p
== '_');
6355 /* APSR uses a notation for bits, rather than fields. */
6356 unsigned int nzcvq_bits
= 0;
6357 unsigned int g_bit
= 0;
6360 for (bit
= start
; bit
!= p
; bit
++)
6362 switch (TOLOWER (*bit
))
6365 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6369 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6373 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6377 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6381 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6385 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6389 inst
.error
= _("unexpected bit specified after APSR");
6394 if (nzcvq_bits
== 0x1f)
6399 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6401 inst
.error
= _("selected processor does not "
6402 "support DSP extension");
6409 if ((nzcvq_bits
& 0x20) != 0
6410 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6411 || (g_bit
& 0x2) != 0)
6413 inst
.error
= _("bad bitmask specified after APSR");
6419 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6424 psr_field
|= psr
->field
;
6430 goto error
; /* Garbage after "[CS]PSR". */
6432 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6433 is deprecated, but allow it anyway. */
6437 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6440 else if (!m_profile
)
6441 /* These bits are never right for M-profile devices: don't set them
6442 (only code paths which read/write APSR reach here). */
6443 psr_field
|= (PSR_c
| PSR_f
);
6449 inst
.error
= _("selected processor does not support requested special "
6450 "purpose register");
6454 inst
.error
= _("flag for {c}psr instruction expected");
6459 parse_sys_vldr_vstr (char **str
)
6468 {"FPSCR", 0x1, 0x0},
6469 {"FPSCR_nzcvqc", 0x2, 0x0},
6472 {"FPCXTNS", 0x6, 0x1},
6473 {"FPCXTS", 0x7, 0x1}
6475 char *op_end
= strchr (*str
, ',');
6476 size_t op_strlen
= op_end
- *str
;
6478 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6480 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6482 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6491 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6492 value suitable for splatting into the AIF field of the instruction. */
6495 parse_cps_flags (char **str
)
6504 case '\0': case ',':
6507 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6508 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6509 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6512 inst
.error
= _("unrecognized CPS flag");
6517 if (saw_a_flag
== 0)
6519 inst
.error
= _("missing CPS flags");
6527 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6528 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6531 parse_endian_specifier (char **str
)
6536 if (strncasecmp (s
, "BE", 2))
6538 else if (strncasecmp (s
, "LE", 2))
6542 inst
.error
= _("valid endian specifiers are be or le");
6546 if (ISALNUM (s
[2]) || s
[2] == '_')
6548 inst
.error
= _("valid endian specifiers are be or le");
6553 return little_endian
;
6556 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6557 value suitable for poking into the rotate field of an sxt or sxta
6558 instruction, or FAIL on error. */
6561 parse_ror (char **str
)
6566 if (strncasecmp (s
, "ROR", 3) == 0)
6570 inst
.error
= _("missing rotation field after comma");
6574 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6579 case 0: *str
= s
; return 0x0;
6580 case 8: *str
= s
; return 0x1;
6581 case 16: *str
= s
; return 0x2;
6582 case 24: *str
= s
; return 0x3;
6585 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6590 /* Parse a conditional code (from conds[] below). The value returned is in the
6591 range 0 .. 14, or FAIL. */
6593 parse_cond (char **str
)
6596 const struct asm_cond
*c
;
6598 /* Condition codes are always 2 characters, so matching up to
6599 3 characters is sufficient. */
6604 while (ISALPHA (*q
) && n
< 3)
6606 cond
[n
] = TOLOWER (*q
);
6611 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6614 inst
.error
= _("condition required");
6622 /* Parse an option for a barrier instruction. Returns the encoding for the
6625 parse_barrier (char **str
)
6628 const struct asm_barrier_opt
*o
;
6631 while (ISALPHA (*q
))
6634 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6639 if (!mark_feature_used (&o
->arch
))
6646 /* Parse the operands of a table branch instruction. Similar to a memory
6649 parse_tb (char **str
)
6654 if (skip_past_char (&p
, '[') == FAIL
)
6656 inst
.error
= _("'[' expected");
6660 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6662 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6665 inst
.operands
[0].reg
= reg
;
6667 if (skip_past_comma (&p
) == FAIL
)
6669 inst
.error
= _("',' expected");
6673 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6675 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6678 inst
.operands
[0].imm
= reg
;
6680 if (skip_past_comma (&p
) == SUCCESS
)
6682 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6684 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6686 inst
.error
= _("invalid shift");
6689 inst
.operands
[0].shifted
= 1;
6692 if (skip_past_char (&p
, ']') == FAIL
)
6694 inst
.error
= _("']' expected");
6701 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6702 information on the types the operands can take and how they are encoded.
6703 Up to four operands may be read; this function handles setting the
6704 ".present" field for each read operand itself.
6705 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6706 else returns FAIL. */
6709 parse_neon_mov (char **str
, int *which_operand
)
6711 int i
= *which_operand
, val
;
6712 enum arm_reg_type rtype
;
6714 struct neon_type_el optype
;
6716 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6718 /* Cases 17 or 19. */
6719 inst
.operands
[i
].reg
= val
;
6720 inst
.operands
[i
].isvec
= 1;
6721 inst
.operands
[i
].isscalar
= 2;
6722 inst
.operands
[i
].vectype
= optype
;
6723 inst
.operands
[i
++].present
= 1;
6725 if (skip_past_comma (&ptr
) == FAIL
)
6728 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6730 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6731 inst
.operands
[i
].reg
= val
;
6732 inst
.operands
[i
].isreg
= 1;
6733 inst
.operands
[i
].present
= 1;
6735 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6737 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6738 inst
.operands
[i
].reg
= val
;
6739 inst
.operands
[i
].isvec
= 1;
6740 inst
.operands
[i
].isscalar
= 2;
6741 inst
.operands
[i
].vectype
= optype
;
6742 inst
.operands
[i
++].present
= 1;
6744 if (skip_past_comma (&ptr
) == FAIL
)
6747 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6750 inst
.operands
[i
].reg
= val
;
6751 inst
.operands
[i
].isreg
= 1;
6752 inst
.operands
[i
++].present
= 1;
6754 if (skip_past_comma (&ptr
) == FAIL
)
6757 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6760 inst
.operands
[i
].reg
= val
;
6761 inst
.operands
[i
].isreg
= 1;
6762 inst
.operands
[i
].present
= 1;
6766 first_error (_("expected ARM or MVE vector register"));
6770 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6772 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6773 inst
.operands
[i
].reg
= val
;
6774 inst
.operands
[i
].isscalar
= 1;
6775 inst
.operands
[i
].vectype
= optype
;
6776 inst
.operands
[i
++].present
= 1;
6778 if (skip_past_comma (&ptr
) == FAIL
)
6781 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6784 inst
.operands
[i
].reg
= val
;
6785 inst
.operands
[i
].isreg
= 1;
6786 inst
.operands
[i
].present
= 1;
6788 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6790 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6793 /* Cases 0, 1, 2, 3, 5 (D only). */
6794 if (skip_past_comma (&ptr
) == FAIL
)
6797 inst
.operands
[i
].reg
= val
;
6798 inst
.operands
[i
].isreg
= 1;
6799 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6800 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6801 inst
.operands
[i
].isvec
= 1;
6802 inst
.operands
[i
].vectype
= optype
;
6803 inst
.operands
[i
++].present
= 1;
6805 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6807 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6808 Case 13: VMOV <Sd>, <Rm> */
6809 inst
.operands
[i
].reg
= val
;
6810 inst
.operands
[i
].isreg
= 1;
6811 inst
.operands
[i
].present
= 1;
6813 if (rtype
== REG_TYPE_NQ
)
6815 first_error (_("can't use Neon quad register here"));
6818 else if (rtype
!= REG_TYPE_VFS
)
6821 if (skip_past_comma (&ptr
) == FAIL
)
6823 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6825 inst
.operands
[i
].reg
= val
;
6826 inst
.operands
[i
].isreg
= 1;
6827 inst
.operands
[i
].present
= 1;
6830 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6832 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6835 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6836 Case 1: VMOV<c><q> <Dd>, <Dm>
6837 Case 8: VMOV.F32 <Sd>, <Sm>
6838 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6840 inst
.operands
[i
].reg
= val
;
6841 inst
.operands
[i
].isreg
= 1;
6842 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6843 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6844 inst
.operands
[i
].isvec
= 1;
6845 inst
.operands
[i
].vectype
= optype
;
6846 inst
.operands
[i
].present
= 1;
6848 if (skip_past_comma (&ptr
) == SUCCESS
)
6853 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6856 inst
.operands
[i
].reg
= val
;
6857 inst
.operands
[i
].isreg
= 1;
6858 inst
.operands
[i
++].present
= 1;
6860 if (skip_past_comma (&ptr
) == FAIL
)
6863 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6866 inst
.operands
[i
].reg
= val
;
6867 inst
.operands
[i
].isreg
= 1;
6868 inst
.operands
[i
].present
= 1;
6871 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6872 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6873 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6874 Case 10: VMOV.F32 <Sd>, #<imm>
6875 Case 11: VMOV.F64 <Dd>, #<imm> */
6876 inst
.operands
[i
].immisfloat
= 1;
6877 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6879 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6880 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6884 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6888 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6890 /* Cases 6, 7, 16, 18. */
6891 inst
.operands
[i
].reg
= val
;
6892 inst
.operands
[i
].isreg
= 1;
6893 inst
.operands
[i
++].present
= 1;
6895 if (skip_past_comma (&ptr
) == FAIL
)
6898 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6900 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6901 inst
.operands
[i
].reg
= val
;
6902 inst
.operands
[i
].isscalar
= 2;
6903 inst
.operands
[i
].present
= 1;
6904 inst
.operands
[i
].vectype
= optype
;
6906 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6908 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6909 inst
.operands
[i
].reg
= val
;
6910 inst
.operands
[i
].isscalar
= 1;
6911 inst
.operands
[i
].present
= 1;
6912 inst
.operands
[i
].vectype
= optype
;
6914 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6916 inst
.operands
[i
].reg
= val
;
6917 inst
.operands
[i
].isreg
= 1;
6918 inst
.operands
[i
++].present
= 1;
6920 if (skip_past_comma (&ptr
) == FAIL
)
6923 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6926 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6928 inst
.operands
[i
].reg
= val
;
6929 inst
.operands
[i
].isreg
= 1;
6930 inst
.operands
[i
].isvec
= 1;
6931 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6932 inst
.operands
[i
].vectype
= optype
;
6933 inst
.operands
[i
].present
= 1;
6935 if (rtype
== REG_TYPE_VFS
)
6939 if (skip_past_comma (&ptr
) == FAIL
)
6941 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6944 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6947 inst
.operands
[i
].reg
= val
;
6948 inst
.operands
[i
].isreg
= 1;
6949 inst
.operands
[i
].isvec
= 1;
6950 inst
.operands
[i
].issingle
= 1;
6951 inst
.operands
[i
].vectype
= optype
;
6952 inst
.operands
[i
].present
= 1;
6957 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6960 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6961 inst
.operands
[i
].reg
= val
;
6962 inst
.operands
[i
].isvec
= 1;
6963 inst
.operands
[i
].isscalar
= 2;
6964 inst
.operands
[i
].vectype
= optype
;
6965 inst
.operands
[i
++].present
= 1;
6967 if (skip_past_comma (&ptr
) == FAIL
)
6970 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6973 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6976 inst
.operands
[i
].reg
= val
;
6977 inst
.operands
[i
].isvec
= 1;
6978 inst
.operands
[i
].isscalar
= 2;
6979 inst
.operands
[i
].vectype
= optype
;
6980 inst
.operands
[i
].present
= 1;
6984 first_error (_("VFP single, double or MVE vector register"
6990 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6994 inst
.operands
[i
].reg
= val
;
6995 inst
.operands
[i
].isreg
= 1;
6996 inst
.operands
[i
].isvec
= 1;
6997 inst
.operands
[i
].issingle
= 1;
6998 inst
.operands
[i
].vectype
= optype
;
6999 inst
.operands
[i
].present
= 1;
7004 first_error (_("parse error"));
7008 /* Successfully parsed the operands. Update args. */
7014 first_error (_("expected comma"));
7018 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
7022 /* Use this macro when the operand constraints are different
7023 for ARM and THUMB (e.g. ldrd). */
7024 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
7025 ((arm_operand) | ((thumb_operand) << 16))
7027 /* Matcher codes for parse_operands. */
7028 enum operand_parse_code
7030 OP_stop
, /* end of line */
7032 OP_RR
, /* ARM register */
7033 OP_RRnpc
, /* ARM register, not r15 */
7034 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
7035 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
7036 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
7037 optional trailing ! */
7038 OP_RRw
, /* ARM register, not r15, optional trailing ! */
7039 OP_RCP
, /* Coprocessor number */
7040 OP_RCN
, /* Coprocessor register */
7041 OP_RF
, /* FPA register */
7042 OP_RVS
, /* VFP single precision register */
7043 OP_RVD
, /* VFP double precision register (0..15) */
7044 OP_RND
, /* Neon double precision register (0..31) */
7045 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
7046 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
7048 OP_RNQ
, /* Neon quad precision register */
7049 OP_RNQMQ
, /* Neon quad or MVE vector register. */
7050 OP_RVSD
, /* VFP single or double precision register */
7051 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
7052 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
7053 OP_RNSD
, /* Neon single or double precision register */
7054 OP_RNDQ
, /* Neon double or quad precision register */
7055 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
7056 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
7057 OP_RNSDQ
, /* Neon single, double or quad precision register */
7058 OP_RNSC
, /* Neon scalar D[X] */
7059 OP_RVC
, /* VFP control register */
7060 OP_RMF
, /* Maverick F register */
7061 OP_RMD
, /* Maverick D register */
7062 OP_RMFX
, /* Maverick FX register */
7063 OP_RMDX
, /* Maverick DX register */
7064 OP_RMAX
, /* Maverick AX register */
7065 OP_RMDS
, /* Maverick DSPSC register */
7066 OP_RIWR
, /* iWMMXt wR register */
7067 OP_RIWC
, /* iWMMXt wC register */
7068 OP_RIWG
, /* iWMMXt wCG register */
7069 OP_RXA
, /* XScale accumulator register */
7071 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
7073 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
7075 OP_RMQ
, /* MVE vector register. */
7076 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
7077 OP_RMQRR
, /* MVE vector or ARM register. */
7079 /* New operands for Armv8.1-M Mainline. */
7080 OP_LR
, /* ARM LR register */
7081 OP_RRe
, /* ARM register, only even numbered. */
7082 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
7083 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7084 OP_RR_ZR
, /* ARM register or ZR but no PC */
7086 OP_REGLST
, /* ARM register list */
7087 OP_CLRMLST
, /* CLRM register list */
7088 OP_VRSLST
, /* VFP single-precision register list */
7089 OP_VRDLST
, /* VFP double-precision register list */
7090 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7091 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7092 OP_NSTRLST
, /* Neon element/structure list */
7093 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7094 OP_MSTRLST2
, /* MVE vector list with two elements. */
7095 OP_MSTRLST4
, /* MVE vector list with four elements. */
7097 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7098 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7099 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7100 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7102 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7103 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7104 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7105 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7107 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7108 scalar, or ARM register. */
7109 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7110 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7111 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7113 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7114 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7115 OP_VMOV
, /* Neon VMOV operands. */
7116 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7117 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7119 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7120 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7122 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7123 OP_VLDR
, /* VLDR operand. */
7125 OP_I0
, /* immediate zero */
7126 OP_I7
, /* immediate value 0 .. 7 */
7127 OP_I15
, /* 0 .. 15 */
7128 OP_I16
, /* 1 .. 16 */
7129 OP_I16z
, /* 0 .. 16 */
7130 OP_I31
, /* 0 .. 31 */
7131 OP_I31w
, /* 0 .. 31, optional trailing ! */
7132 OP_I32
, /* 1 .. 32 */
7133 OP_I32z
, /* 0 .. 32 */
7134 OP_I48_I64
, /* 48 or 64 */
7135 OP_I63
, /* 0 .. 63 */
7136 OP_I63s
, /* -64 .. 63 */
7137 OP_I64
, /* 1 .. 64 */
7138 OP_I64z
, /* 0 .. 64 */
7139 OP_I255
, /* 0 .. 255 */
7141 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7142 OP_I7b
, /* 0 .. 7 */
7143 OP_I15b
, /* 0 .. 15 */
7144 OP_I31b
, /* 0 .. 31 */
7146 OP_SH
, /* shifter operand */
7147 OP_SHG
, /* shifter operand with possible group relocation */
7148 OP_ADDR
, /* Memory address expression (any mode) */
7149 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7150 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7151 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7152 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7153 OP_EXP
, /* arbitrary expression */
7154 OP_EXPi
, /* same, with optional immediate prefix */
7155 OP_EXPr
, /* same, with optional relocation suffix */
7156 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7157 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7158 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7159 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7161 OP_CPSF
, /* CPS flags */
7162 OP_ENDI
, /* Endianness specifier */
7163 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7164 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7165 OP_COND
, /* conditional code */
7166 OP_TB
, /* Table branch. */
7168 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7170 OP_RRnpc_I0
, /* ARM register or literal 0 */
7171 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7172 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7173 OP_RF_IF
, /* FPA register or immediate */
7174 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7175 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7177 /* Optional operands. */
7178 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7179 OP_oI31b
, /* 0 .. 31 */
7180 OP_oI32b
, /* 1 .. 32 */
7181 OP_oI32z
, /* 0 .. 32 */
7182 OP_oIffffb
, /* 0 .. 65535 */
7183 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7185 OP_oRR
, /* ARM register */
7186 OP_oLR
, /* ARM LR register */
7187 OP_oRRnpc
, /* ARM register, not the PC */
7188 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7189 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7190 OP_oRND
, /* Optional Neon double precision register */
7191 OP_oRNQ
, /* Optional Neon quad precision register */
7192 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7193 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7194 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7195 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7197 OP_oSHll
, /* LSL immediate */
7198 OP_oSHar
, /* ASR immediate */
7199 OP_oSHllar
, /* LSL or ASR immediate */
7200 OP_oROR
, /* ROR 0/8/16/24 */
7201 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7203 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7205 /* Some pre-defined mixed (ARM/THUMB) operands. */
7206 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7207 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7208 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7210 OP_FIRST_OPTIONAL
= OP_oI7b
7213 /* Generic instruction operand parser. This does no encoding and no
7214 semantic validation; it merely squirrels values away in the inst
7215 structure. Returns SUCCESS or FAIL depending on whether the
7216 specified grammar matched. */
7218 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7220 unsigned const int *upat
= pattern
;
7221 char *backtrack_pos
= 0;
7222 const char *backtrack_error
= 0;
7223 int i
, val
= 0, backtrack_index
= 0;
7224 enum arm_reg_type rtype
;
7225 parse_operand_result result
;
7226 unsigned int op_parse_code
;
7227 bfd_boolean partial_match
;
7229 #define po_char_or_fail(chr) \
7232 if (skip_past_char (&str, chr) == FAIL) \
7237 #define po_reg_or_fail(regtype) \
7240 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7241 & inst.operands[i].vectype); \
7244 first_error (_(reg_expected_msgs[regtype])); \
7247 inst.operands[i].reg = val; \
7248 inst.operands[i].isreg = 1; \
7249 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7250 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7251 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7252 || rtype == REG_TYPE_VFD \
7253 || rtype == REG_TYPE_NQ); \
7254 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7258 #define po_reg_or_goto(regtype, label) \
7261 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7262 & inst.operands[i].vectype); \
7266 inst.operands[i].reg = val; \
7267 inst.operands[i].isreg = 1; \
7268 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7269 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7270 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7271 || rtype == REG_TYPE_VFD \
7272 || rtype == REG_TYPE_NQ); \
7273 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7277 #define po_imm_or_fail(min, max, popt) \
7280 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7282 inst.operands[i].imm = val; \
7286 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7290 my_get_expression (&exp, &str, popt); \
7291 if (exp.X_op != O_constant) \
7293 inst.error = _("constant expression required"); \
7296 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7298 inst.error = _("immediate value 48 or 64 expected"); \
7301 inst.operands[i].imm = exp.X_add_number; \
7305 #define po_scalar_or_goto(elsz, label, reg_type) \
7308 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7312 inst.operands[i].reg = val; \
7313 inst.operands[i].isscalar = 1; \
7317 #define po_misc_or_fail(expr) \
7325 #define po_misc_or_fail_no_backtrack(expr) \
7329 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7330 backtrack_pos = 0; \
7331 if (result != PARSE_OPERAND_SUCCESS) \
7336 #define po_barrier_or_imm(str) \
7339 val = parse_barrier (&str); \
7340 if (val == FAIL && ! ISALPHA (*str)) \
7343 /* ISB can only take SY as an option. */ \
7344 || ((inst.instruction & 0xf0) == 0x60 \
7347 inst.error = _("invalid barrier type"); \
7348 backtrack_pos = 0; \
7354 skip_whitespace (str
);
7356 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7358 op_parse_code
= upat
[i
];
7359 if (op_parse_code
>= 1<<16)
7360 op_parse_code
= thumb
? (op_parse_code
>> 16)
7361 : (op_parse_code
& ((1<<16)-1));
7363 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7365 /* Remember where we are in case we need to backtrack. */
7366 backtrack_pos
= str
;
7367 backtrack_error
= inst
.error
;
7368 backtrack_index
= i
;
7371 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7372 po_char_or_fail (',');
7374 switch (op_parse_code
)
7386 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7387 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7388 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7389 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7390 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7391 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7394 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7398 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7401 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7403 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7405 /* Also accept generic coprocessor regs for unknown registers. */
7407 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7409 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7410 existing register with a value of 0, this seems like the
7411 best way to parse P0. */
7413 if (strncasecmp (str
, "P0", 2) == 0)
7416 inst
.operands
[i
].isreg
= 1;
7417 inst
.operands
[i
].reg
= 13;
7422 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7423 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7424 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7425 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7426 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7427 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7428 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7429 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7430 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7431 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7434 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7437 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7438 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7440 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7445 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7449 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7451 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7454 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7456 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7459 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7461 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7466 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7469 po_reg_or_fail (REG_TYPE_NSDQ
);
7473 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7477 po_reg_or_fail (REG_TYPE_MQ
);
7479 /* Neon scalar. Using an element size of 8 means that some invalid
7480 scalars are accepted here, so deal with those in later code. */
7481 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7485 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7488 po_imm_or_fail (0, 0, TRUE
);
7493 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7497 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7502 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7505 if (parse_ifimm_zero (&str
))
7506 inst
.operands
[i
].imm
= 0;
7510 = _("only floating point zero is allowed as immediate value");
7518 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7521 po_reg_or_fail (REG_TYPE_RN
);
7525 case OP_RNSDQ_RNSC_MQ_RR
:
7526 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7529 case OP_RNSDQ_RNSC_MQ
:
7530 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7535 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7539 po_reg_or_fail (REG_TYPE_NSDQ
);
7546 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7549 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7552 po_reg_or_fail (REG_TYPE_NSD
);
7556 case OP_RNDQMQ_RNSC_RR
:
7557 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7560 case OP_RNDQ_RNSC_RR
:
7561 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7563 case OP_RNDQMQ_RNSC
:
7564 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7569 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7572 po_reg_or_fail (REG_TYPE_NDQ
);
7578 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7581 po_reg_or_fail (REG_TYPE_VFD
);
7586 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7587 not careful then bad things might happen. */
7588 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7591 case OP_RNDQMQ_Ibig
:
7592 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7597 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7600 /* There's a possibility of getting a 64-bit immediate here, so
7601 we need special handling. */
7602 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7605 inst
.error
= _("immediate value is out of range");
7611 case OP_RNDQMQ_I63b_RR
:
7612 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7615 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7620 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7623 po_imm_or_fail (0, 63, TRUE
);
7628 po_char_or_fail ('[');
7629 po_reg_or_fail (REG_TYPE_RN
);
7630 po_char_or_fail (']');
7636 po_reg_or_fail (REG_TYPE_RN
);
7637 if (skip_past_char (&str
, '!') == SUCCESS
)
7638 inst
.operands
[i
].writeback
= 1;
7642 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7643 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7644 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7645 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7646 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7647 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7648 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7649 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7650 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7651 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7652 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7653 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7654 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7656 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7658 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7659 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7661 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7662 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7663 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7664 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7666 /* Immediate variants */
7668 po_char_or_fail ('{');
7669 po_imm_or_fail (0, 255, TRUE
);
7670 po_char_or_fail ('}');
7674 /* The expression parser chokes on a trailing !, so we have
7675 to find it first and zap it. */
7678 while (*s
&& *s
!= ',')
7683 inst
.operands
[i
].writeback
= 1;
7685 po_imm_or_fail (0, 31, TRUE
);
7693 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7698 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7703 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7705 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7707 val
= parse_reloc (&str
);
7710 inst
.error
= _("unrecognized relocation suffix");
7713 else if (val
!= BFD_RELOC_UNUSED
)
7715 inst
.operands
[i
].imm
= val
;
7716 inst
.operands
[i
].hasreloc
= 1;
7722 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7724 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7726 inst
.operands
[i
].hasreloc
= 1;
7728 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7730 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7731 inst
.operands
[i
].hasreloc
= 0;
7735 /* Operand for MOVW or MOVT. */
7737 po_misc_or_fail (parse_half (&str
));
7740 /* Register or expression. */
7741 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7742 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7744 /* Register or immediate. */
7745 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7746 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7748 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7749 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7751 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7753 if (!is_immediate_prefix (*str
))
7756 val
= parse_fpa_immediate (&str
);
7759 /* FPA immediates are encoded as registers 8-15.
7760 parse_fpa_immediate has already applied the offset. */
7761 inst
.operands
[i
].reg
= val
;
7762 inst
.operands
[i
].isreg
= 1;
7765 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7766 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7768 /* Two kinds of register. */
7771 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7773 || (rege
->type
!= REG_TYPE_MMXWR
7774 && rege
->type
!= REG_TYPE_MMXWC
7775 && rege
->type
!= REG_TYPE_MMXWCG
))
7777 inst
.error
= _("iWMMXt data or control register expected");
7780 inst
.operands
[i
].reg
= rege
->number
;
7781 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7787 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7789 || (rege
->type
!= REG_TYPE_MMXWC
7790 && rege
->type
!= REG_TYPE_MMXWCG
))
7792 inst
.error
= _("iWMMXt control register expected");
7795 inst
.operands
[i
].reg
= rege
->number
;
7796 inst
.operands
[i
].isreg
= 1;
7801 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7802 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7803 case OP_oROR
: val
= parse_ror (&str
); break;
7805 case OP_COND
: val
= parse_cond (&str
); break;
7806 case OP_oBARRIER_I15
:
7807 po_barrier_or_imm (str
); break;
7809 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7815 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7816 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7818 inst
.error
= _("Banked registers are not available with this "
7824 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7828 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7831 val
= parse_sys_vldr_vstr (&str
);
7835 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7838 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7840 if (strncasecmp (str
, "APSR_", 5) == 0)
7847 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7848 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7849 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7850 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7851 default: found
= 16;
7855 inst
.operands
[i
].isvec
= 1;
7856 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7857 inst
.operands
[i
].reg
= REG_PC
;
7864 po_misc_or_fail (parse_tb (&str
));
7867 /* Register lists. */
7869 val
= parse_reg_list (&str
, REGLIST_RN
);
7872 inst
.operands
[i
].writeback
= 1;
7878 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7882 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7887 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7892 /* Allow Q registers too. */
7893 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7894 REGLIST_NEON_D
, &partial_match
);
7898 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7899 REGLIST_VFP_S
, &partial_match
);
7900 inst
.operands
[i
].issingle
= 1;
7905 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7906 REGLIST_VFP_D_VPR
, &partial_match
);
7907 if (val
== FAIL
&& !partial_match
)
7910 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7911 REGLIST_VFP_S_VPR
, &partial_match
);
7912 inst
.operands
[i
].issingle
= 1;
7917 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7918 REGLIST_NEON_D
, &partial_match
);
7923 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7924 1, &inst
.operands
[i
].vectype
);
7925 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7929 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7930 0, &inst
.operands
[i
].vectype
);
7933 /* Addressing modes */
7935 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7939 po_misc_or_fail (parse_address (&str
, i
));
7943 po_misc_or_fail_no_backtrack (
7944 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7948 po_misc_or_fail_no_backtrack (
7949 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7953 po_misc_or_fail_no_backtrack (
7954 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7958 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7962 po_misc_or_fail_no_backtrack (
7963 parse_shifter_operand_group_reloc (&str
, i
));
7967 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7971 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7975 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7980 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7985 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7988 po_reg_or_fail (REG_TYPE_ZR
);
7992 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7995 /* Various value-based sanity checks and shared operations. We
7996 do not signal immediate failures for the register constraints;
7997 this allows a syntax error to take precedence. */
7998 switch (op_parse_code
)
8006 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
8007 inst
.error
= BAD_PC
;
8012 case OP_RRnpcsp_I32
:
8013 if (inst
.operands
[i
].isreg
)
8015 if (inst
.operands
[i
].reg
== REG_PC
)
8016 inst
.error
= BAD_PC
;
8017 else if (inst
.operands
[i
].reg
== REG_SP
8018 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
8019 relaxed since ARMv8-A. */
8020 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8023 inst
.error
= BAD_SP
;
8029 if (inst
.operands
[i
].isreg
8030 && inst
.operands
[i
].reg
== REG_PC
8031 && (inst
.operands
[i
].writeback
|| thumb
))
8032 inst
.error
= BAD_PC
;
8037 if (inst
.operands
[i
].isreg
)
8047 case OP_oBARRIER_I15
:
8060 inst
.operands
[i
].imm
= val
;
8065 if (inst
.operands
[i
].reg
!= REG_LR
)
8066 inst
.error
= _("operand must be LR register");
8072 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
8073 inst
.error
= BAD_PC
;
8077 if (inst
.operands
[i
].isreg
8078 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
8079 inst
.error
= BAD_ODD
;
8083 if (inst
.operands
[i
].isreg
)
8085 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8086 inst
.error
= BAD_EVEN
;
8087 else if (inst
.operands
[i
].reg
== REG_SP
)
8088 as_tsktsk (MVE_BAD_SP
);
8089 else if (inst
.operands
[i
].reg
== REG_PC
)
8090 inst
.error
= BAD_PC
;
8098 /* If we get here, this operand was successfully parsed. */
8099 inst
.operands
[i
].present
= 1;
8103 inst
.error
= BAD_ARGS
;
8108 /* The parse routine should already have set inst.error, but set a
8109 default here just in case. */
8111 inst
.error
= BAD_SYNTAX
;
8115 /* Do not backtrack over a trailing optional argument that
8116 absorbed some text. We will only fail again, with the
8117 'garbage following instruction' error message, which is
8118 probably less helpful than the current one. */
8119 if (backtrack_index
== i
&& backtrack_pos
!= str
8120 && upat
[i
+1] == OP_stop
)
8123 inst
.error
= BAD_SYNTAX
;
8127 /* Try again, skipping the optional argument at backtrack_pos. */
8128 str
= backtrack_pos
;
8129 inst
.error
= backtrack_error
;
8130 inst
.operands
[backtrack_index
].present
= 0;
8131 i
= backtrack_index
;
8135 /* Check that we have parsed all the arguments. */
8136 if (*str
!= '\0' && !inst
.error
)
8137 inst
.error
= _("garbage following instruction");
8139 return inst
.error
? FAIL
: SUCCESS
;
8142 #undef po_char_or_fail
8143 #undef po_reg_or_fail
8144 #undef po_reg_or_goto
8145 #undef po_imm_or_fail
8146 #undef po_scalar_or_fail
8147 #undef po_barrier_or_imm
8149 /* Shorthand macro for instruction encoding functions issuing errors. */
8150 #define constraint(expr, err) \
8161 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8162 instructions are unpredictable if these registers are used. This
8163 is the BadReg predicate in ARM's Thumb-2 documentation.
8165 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8166 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8167 #define reject_bad_reg(reg) \
8169 if (reg == REG_PC) \
8171 inst.error = BAD_PC; \
8174 else if (reg == REG_SP \
8175 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8177 inst.error = BAD_SP; \
8182 /* If REG is R13 (the stack pointer), warn that its use is
8184 #define warn_deprecated_sp(reg) \
8186 if (warn_on_deprecated && reg == REG_SP) \
8187 as_tsktsk (_("use of r13 is deprecated")); \
8190 /* Functions for operand encoding. ARM, then Thumb. */
8192 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8194 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8196 The only binary encoding difference is the Coprocessor number. Coprocessor
8197 9 is used for half-precision calculations or conversions. The format of the
8198 instruction is the same as the equivalent Coprocessor 10 instruction that
8199 exists for Single-Precision operation. */
8202 do_scalar_fp16_v82_encode (void)
8204 if (inst
.cond
< COND_ALWAYS
)
8205 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8206 " the behaviour is UNPREDICTABLE"));
8207 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8210 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8211 mark_feature_used (&arm_ext_fp16
);
8214 /* If VAL can be encoded in the immediate field of an ARM instruction,
8215 return the encoded form. Otherwise, return FAIL. */
8218 encode_arm_immediate (unsigned int val
)
8225 for (i
= 2; i
< 32; i
+= 2)
8226 if ((a
= rotate_left (val
, i
)) <= 0xff)
8227 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8232 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8233 return the encoded form. Otherwise, return FAIL. */
8235 encode_thumb32_immediate (unsigned int val
)
8242 for (i
= 1; i
<= 24; i
++)
8245 if ((val
& ~(0xff << i
)) == 0)
8246 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8250 if (val
== ((a
<< 16) | a
))
8252 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8256 if (val
== ((a
<< 16) | a
))
8257 return 0x200 | (a
>> 8);
8261 /* Encode a VFP SP or DP register number into inst.instruction. */
8264 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8266 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8269 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8272 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8275 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8280 first_error (_("D register out of range for selected VFP version"));
8288 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8292 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8296 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8300 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8304 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8308 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8316 /* Encode a <shift> in an ARM-format instruction. The immediate,
8317 if any, is handled by md_apply_fix. */
8319 encode_arm_shift (int i
)
8321 /* register-shifted register. */
8322 if (inst
.operands
[i
].immisreg
)
8325 for (op_index
= 0; op_index
<= i
; ++op_index
)
8327 /* Check the operand only when it's presented. In pre-UAL syntax,
8328 if the destination register is the same as the first operand, two
8329 register form of the instruction can be used. */
8330 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8331 && inst
.operands
[op_index
].reg
== REG_PC
)
8332 as_warn (UNPRED_REG ("r15"));
8335 if (inst
.operands
[i
].imm
== REG_PC
)
8336 as_warn (UNPRED_REG ("r15"));
8339 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8340 inst
.instruction
|= SHIFT_ROR
<< 5;
8343 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8344 if (inst
.operands
[i
].immisreg
)
8346 inst
.instruction
|= SHIFT_BY_REG
;
8347 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8350 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8355 encode_arm_shifter_operand (int i
)
8357 if (inst
.operands
[i
].isreg
)
8359 inst
.instruction
|= inst
.operands
[i
].reg
;
8360 encode_arm_shift (i
);
8364 inst
.instruction
|= INST_IMMEDIATE
;
8365 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8366 inst
.instruction
|= inst
.operands
[i
].imm
;
8370 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8372 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8375 Generate an error if the operand is not a register. */
8376 constraint (!inst
.operands
[i
].isreg
,
8377 _("Instruction does not support =N addresses"));
8379 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8381 if (inst
.operands
[i
].preind
)
8385 inst
.error
= _("instruction does not accept preindexed addressing");
8388 inst
.instruction
|= PRE_INDEX
;
8389 if (inst
.operands
[i
].writeback
)
8390 inst
.instruction
|= WRITE_BACK
;
8393 else if (inst
.operands
[i
].postind
)
8395 gas_assert (inst
.operands
[i
].writeback
);
8397 inst
.instruction
|= WRITE_BACK
;
8399 else /* unindexed - only for coprocessor */
8401 inst
.error
= _("instruction does not accept unindexed addressing");
8405 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8406 && (((inst
.instruction
& 0x000f0000) >> 16)
8407 == ((inst
.instruction
& 0x0000f000) >> 12)))
8408 as_warn ((inst
.instruction
& LOAD_BIT
)
8409 ? _("destination register same as write-back base")
8410 : _("source register same as write-back base"));
8413 /* inst.operands[i] was set up by parse_address. Encode it into an
8414 ARM-format mode 2 load or store instruction. If is_t is true,
8415 reject forms that cannot be used with a T instruction (i.e. not
8418 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8420 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8422 encode_arm_addr_mode_common (i
, is_t
);
8424 if (inst
.operands
[i
].immisreg
)
8426 constraint ((inst
.operands
[i
].imm
== REG_PC
8427 || (is_pc
&& inst
.operands
[i
].writeback
)),
8429 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8430 inst
.instruction
|= inst
.operands
[i
].imm
;
8431 if (!inst
.operands
[i
].negative
)
8432 inst
.instruction
|= INDEX_UP
;
8433 if (inst
.operands
[i
].shifted
)
8435 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8436 inst
.instruction
|= SHIFT_ROR
<< 5;
8439 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8440 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8444 else /* immediate offset in inst.relocs[0] */
8446 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8448 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8450 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8451 cannot use PC in addressing.
8452 PC cannot be used in writeback addressing, either. */
8453 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8456 /* Use of PC in str is deprecated for ARMv7. */
8457 if (warn_on_deprecated
8459 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8460 as_tsktsk (_("use of PC in this instruction is deprecated"));
8463 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8465 /* Prefer + for zero encoded value. */
8466 if (!inst
.operands
[i
].negative
)
8467 inst
.instruction
|= INDEX_UP
;
8468 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8473 /* inst.operands[i] was set up by parse_address. Encode it into an
8474 ARM-format mode 3 load or store instruction. Reject forms that
8475 cannot be used with such instructions. If is_t is true, reject
8476 forms that cannot be used with a T instruction (i.e. not
8479 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8481 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8483 inst
.error
= _("instruction does not accept scaled register index");
8487 encode_arm_addr_mode_common (i
, is_t
);
8489 if (inst
.operands
[i
].immisreg
)
8491 constraint ((inst
.operands
[i
].imm
== REG_PC
8492 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8494 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8496 inst
.instruction
|= inst
.operands
[i
].imm
;
8497 if (!inst
.operands
[i
].negative
)
8498 inst
.instruction
|= INDEX_UP
;
8500 else /* immediate offset in inst.relocs[0] */
8502 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8503 && inst
.operands
[i
].writeback
),
8505 inst
.instruction
|= HWOFFSET_IMM
;
8506 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8508 /* Prefer + for zero encoded value. */
8509 if (!inst
.operands
[i
].negative
)
8510 inst
.instruction
|= INDEX_UP
;
8512 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8517 /* Write immediate bits [7:0] to the following locations:
8519 |28/24|23 19|18 16|15 4|3 0|
8520 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8522 This function is used by VMOV/VMVN/VORR/VBIC. */
8525 neon_write_immbits (unsigned immbits
)
8527 inst
.instruction
|= immbits
& 0xf;
8528 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8529 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8532 /* Invert low-order SIZE bits of XHI:XLO. */
8535 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8537 unsigned immlo
= xlo
? *xlo
: 0;
8538 unsigned immhi
= xhi
? *xhi
: 0;
8543 immlo
= (~immlo
) & 0xff;
8547 immlo
= (~immlo
) & 0xffff;
8551 immhi
= (~immhi
) & 0xffffffff;
8555 immlo
= (~immlo
) & 0xffffffff;
8569 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8573 neon_bits_same_in_bytes (unsigned imm
)
8575 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8576 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8577 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8578 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8581 /* For immediate of above form, return 0bABCD. */
8584 neon_squash_bits (unsigned imm
)
8586 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8587 | ((imm
& 0x01000000) >> 21);
8590 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8593 neon_qfloat_bits (unsigned imm
)
8595 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8598 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8599 the instruction. *OP is passed as the initial value of the op field, and
8600 may be set to a different value depending on the constant (i.e.
8601 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8602 MVN). If the immediate looks like a repeated pattern then also
8603 try smaller element sizes. */
8606 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8607 unsigned *immbits
, int *op
, int size
,
8608 enum neon_el_type type
)
8610 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8612 if (type
== NT_float
&& !float_p
)
8615 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8617 if (size
!= 32 || *op
== 1)
8619 *immbits
= neon_qfloat_bits (immlo
);
8625 if (neon_bits_same_in_bytes (immhi
)
8626 && neon_bits_same_in_bytes (immlo
))
8630 *immbits
= (neon_squash_bits (immhi
) << 4)
8631 | neon_squash_bits (immlo
);
8642 if (immlo
== (immlo
& 0x000000ff))
8647 else if (immlo
== (immlo
& 0x0000ff00))
8649 *immbits
= immlo
>> 8;
8652 else if (immlo
== (immlo
& 0x00ff0000))
8654 *immbits
= immlo
>> 16;
8657 else if (immlo
== (immlo
& 0xff000000))
8659 *immbits
= immlo
>> 24;
8662 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8664 *immbits
= (immlo
>> 8) & 0xff;
8667 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8669 *immbits
= (immlo
>> 16) & 0xff;
8673 if ((immlo
& 0xffff) != (immlo
>> 16))
8680 if (immlo
== (immlo
& 0x000000ff))
8685 else if (immlo
== (immlo
& 0x0000ff00))
8687 *immbits
= immlo
>> 8;
8691 if ((immlo
& 0xff) != (immlo
>> 8))
8696 if (immlo
== (immlo
& 0x000000ff))
8698 /* Don't allow MVN with 8-bit immediate. */
8708 #if defined BFD_HOST_64_BIT
8709 /* Returns TRUE if double precision value V may be cast
8710 to single precision without loss of accuracy. */
8713 is_double_a_single (bfd_int64_t v
)
8715 int exp
= (int)((v
>> 52) & 0x7FF);
8716 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8718 return (exp
== 0 || exp
== 0x7FF
8719 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8720 && (mantissa
& 0x1FFFFFFFl
) == 0;
8723 /* Returns a double precision value casted to single precision
8724 (ignoring the least significant bits in exponent and mantissa). */
8727 double_to_single (bfd_int64_t v
)
8729 int sign
= (int) ((v
>> 63) & 1l);
8730 int exp
= (int) ((v
>> 52) & 0x7FF);
8731 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8737 exp
= exp
- 1023 + 127;
8746 /* No denormalized numbers. */
8752 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8754 #endif /* BFD_HOST_64_BIT */
8763 static void do_vfp_nsyn_opcode (const char *);
8765 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8766 Determine whether it can be performed with a move instruction; if
8767 it can, convert inst.instruction to that move instruction and
8768 return TRUE; if it can't, convert inst.instruction to a literal-pool
8769 load and return FALSE. If this is not a valid thing to do in the
8770 current context, set inst.error and return TRUE.
8772 inst.operands[i] describes the destination register. */
8775 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8778 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8779 bfd_boolean arm_p
= (t
== CONST_ARM
);
8782 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8786 if ((inst
.instruction
& tbit
) == 0)
8788 inst
.error
= _("invalid pseudo operation");
8792 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8793 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8794 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8796 inst
.error
= _("constant expression expected");
8800 if (inst
.relocs
[0].exp
.X_op
== O_constant
8801 || inst
.relocs
[0].exp
.X_op
== O_big
)
8803 #if defined BFD_HOST_64_BIT
8808 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8810 LITTLENUM_TYPE w
[X_PRECISION
];
8813 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8815 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8817 /* FIXME: Should we check words w[2..5] ? */
8822 #if defined BFD_HOST_64_BIT
8824 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8825 << LITTLENUM_NUMBER_OF_BITS
)
8826 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8827 << LITTLENUM_NUMBER_OF_BITS
)
8828 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8829 << LITTLENUM_NUMBER_OF_BITS
)
8830 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8832 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8833 | (l
[0] & LITTLENUM_MASK
);
8837 v
= inst
.relocs
[0].exp
.X_add_number
;
8839 if (!inst
.operands
[i
].issingle
)
8843 /* LDR should not use lead in a flag-setting instruction being
8844 chosen so we do not check whether movs can be used. */
8846 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8847 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8848 && inst
.operands
[i
].reg
!= 13
8849 && inst
.operands
[i
].reg
!= 15)
8851 /* Check if on thumb2 it can be done with a mov.w, mvn or
8852 movw instruction. */
8853 unsigned int newimm
;
8854 bfd_boolean isNegated
;
8856 newimm
= encode_thumb32_immediate (v
);
8857 if (newimm
!= (unsigned int) FAIL
)
8861 newimm
= encode_thumb32_immediate (~v
);
8862 if (newimm
!= (unsigned int) FAIL
)
8866 /* The number can be loaded with a mov.w or mvn
8868 if (newimm
!= (unsigned int) FAIL
8869 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8871 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8872 | (inst
.operands
[i
].reg
<< 8));
8873 /* Change to MOVN. */
8874 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8875 inst
.instruction
|= (newimm
& 0x800) << 15;
8876 inst
.instruction
|= (newimm
& 0x700) << 4;
8877 inst
.instruction
|= (newimm
& 0x0ff);
8880 /* The number can be loaded with a movw instruction. */
8881 else if ((v
& ~0xFFFF) == 0
8882 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8884 int imm
= v
& 0xFFFF;
8886 inst
.instruction
= 0xf2400000; /* MOVW. */
8887 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8888 inst
.instruction
|= (imm
& 0xf000) << 4;
8889 inst
.instruction
|= (imm
& 0x0800) << 15;
8890 inst
.instruction
|= (imm
& 0x0700) << 4;
8891 inst
.instruction
|= (imm
& 0x00ff);
8892 /* In case this replacement is being done on Armv8-M
8893 Baseline we need to make sure to disable the
8894 instruction size check, as otherwise GAS will reject
8895 the use of this T32 instruction. */
8903 int value
= encode_arm_immediate (v
);
8907 /* This can be done with a mov instruction. */
8908 inst
.instruction
&= LITERAL_MASK
;
8909 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8910 inst
.instruction
|= value
& 0xfff;
8914 value
= encode_arm_immediate (~ v
);
8917 /* This can be done with a mvn instruction. */
8918 inst
.instruction
&= LITERAL_MASK
;
8919 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8920 inst
.instruction
|= value
& 0xfff;
8924 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8927 unsigned immbits
= 0;
8928 unsigned immlo
= inst
.operands
[1].imm
;
8929 unsigned immhi
= inst
.operands
[1].regisimm
8930 ? inst
.operands
[1].reg
8931 : inst
.relocs
[0].exp
.X_unsigned
8933 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8934 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8935 &op
, 64, NT_invtype
);
8939 neon_invert_size (&immlo
, &immhi
, 64);
8941 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8942 &op
, 64, NT_invtype
);
8947 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8953 /* Fill other bits in vmov encoding for both thumb and arm. */
8955 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8957 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8958 neon_write_immbits (immbits
);
8966 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8967 if (inst
.operands
[i
].issingle
8968 && is_quarter_float (inst
.operands
[1].imm
)
8969 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8971 inst
.operands
[1].imm
=
8972 neon_qfloat_bits (v
);
8973 do_vfp_nsyn_opcode ("fconsts");
8977 /* If our host does not support a 64-bit type then we cannot perform
8978 the following optimization. This mean that there will be a
8979 discrepancy between the output produced by an assembler built for
8980 a 32-bit-only host and the output produced from a 64-bit host, but
8981 this cannot be helped. */
8982 #if defined BFD_HOST_64_BIT
8983 else if (!inst
.operands
[1].issingle
8984 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8986 if (is_double_a_single (v
)
8987 && is_quarter_float (double_to_single (v
)))
8989 inst
.operands
[1].imm
=
8990 neon_qfloat_bits (double_to_single (v
));
8991 do_vfp_nsyn_opcode ("fconstd");
8999 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
9000 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
9003 inst
.operands
[1].reg
= REG_PC
;
9004 inst
.operands
[1].isreg
= 1;
9005 inst
.operands
[1].preind
= 1;
9006 inst
.relocs
[0].pc_rel
= 1;
9007 inst
.relocs
[0].type
= (thumb_p
9008 ? BFD_RELOC_ARM_THUMB_OFFSET
9010 ? BFD_RELOC_ARM_HWLITERAL
9011 : BFD_RELOC_ARM_LITERAL
));
9015 /* inst.operands[i] was set up by parse_address. Encode it into an
9016 ARM-format instruction. Reject all forms which cannot be encoded
9017 into a coprocessor load/store instruction. If wb_ok is false,
9018 reject use of writeback; if unind_ok is false, reject use of
9019 unindexed addressing. If reloc_override is not 0, use it instead
9020 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
9021 (in which case it is preserved). */
9024 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
9026 if (!inst
.operands
[i
].isreg
)
9029 if (! inst
.operands
[0].isvec
)
9031 inst
.error
= _("invalid co-processor operand");
9034 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
9038 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9040 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
9042 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
9044 gas_assert (!inst
.operands
[i
].writeback
);
9047 inst
.error
= _("instruction does not support unindexed addressing");
9050 inst
.instruction
|= inst
.operands
[i
].imm
;
9051 inst
.instruction
|= INDEX_UP
;
9055 if (inst
.operands
[i
].preind
)
9056 inst
.instruction
|= PRE_INDEX
;
9058 if (inst
.operands
[i
].writeback
)
9060 if (inst
.operands
[i
].reg
== REG_PC
)
9062 inst
.error
= _("pc may not be used with write-back");
9067 inst
.error
= _("instruction does not support writeback");
9070 inst
.instruction
|= WRITE_BACK
;
9074 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
9075 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
9076 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
9077 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
9080 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
9082 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9085 /* Prefer + for zero encoded value. */
9086 if (!inst
.operands
[i
].negative
)
9087 inst
.instruction
|= INDEX_UP
;
9092 /* Functions for instruction encoding, sorted by sub-architecture.
9093 First some generics; their names are taken from the conventional
9094 bit positions for register arguments in ARM format instructions. */
9104 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9110 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9117 inst
.instruction
|= inst
.operands
[1].reg
;
9123 inst
.instruction
|= inst
.operands
[0].reg
;
9124 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9130 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9131 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9137 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9138 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9144 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9145 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9149 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9151 if (ARM_CPU_IS_ANY (cpu_variant
))
9153 as_tsktsk ("%s", msg
);
9156 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9168 unsigned Rn
= inst
.operands
[2].reg
;
9169 /* Enforce restrictions on SWP instruction. */
9170 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9172 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9173 _("Rn must not overlap other operands"));
9175 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9177 if (!check_obsolete (&arm_ext_v8
,
9178 _("swp{b} use is obsoleted for ARMv8 and later"))
9179 && warn_on_deprecated
9180 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9181 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9185 inst
.instruction
|= inst
.operands
[1].reg
;
9186 inst
.instruction
|= Rn
<< 16;
9192 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9193 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9194 inst
.instruction
|= inst
.operands
[2].reg
;
9200 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9201 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9202 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9203 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9205 inst
.instruction
|= inst
.operands
[0].reg
;
9206 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9207 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9213 inst
.instruction
|= inst
.operands
[0].imm
;
9219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9220 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9223 /* ARM instructions, in alphabetical order by function name (except
9224 that wrapper functions appear immediately after the function they
9227 /* This is a pseudo-op of the form "adr rd, label" to be converted
9228 into a relative address of the form "add rd, pc, #label-.-8". */
9233 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9235 /* Frag hacking will turn this into a sub instruction if the offset turns
9236 out to be negative. */
9237 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9238 inst
.relocs
[0].pc_rel
= 1;
9239 inst
.relocs
[0].exp
.X_add_number
-= 8;
9241 if (support_interwork
9242 && inst
.relocs
[0].exp
.X_op
== O_symbol
9243 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9244 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9245 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9246 inst
.relocs
[0].exp
.X_add_number
|= 1;
9249 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9250 into a relative address of the form:
9251 add rd, pc, #low(label-.-8)"
9252 add rd, rd, #high(label-.-8)" */
9257 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9259 /* Frag hacking will turn this into a sub instruction if the offset turns
9260 out to be negative. */
9261 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9262 inst
.relocs
[0].pc_rel
= 1;
9263 inst
.size
= INSN_SIZE
* 2;
9264 inst
.relocs
[0].exp
.X_add_number
-= 8;
9266 if (support_interwork
9267 && inst
.relocs
[0].exp
.X_op
== O_symbol
9268 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9269 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9270 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9271 inst
.relocs
[0].exp
.X_add_number
|= 1;
9277 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9278 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9280 if (!inst
.operands
[1].present
)
9281 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9282 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9283 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9284 encode_arm_shifter_operand (2);
9290 if (inst
.operands
[0].present
)
9291 inst
.instruction
|= inst
.operands
[0].imm
;
9293 inst
.instruction
|= 0xf;
9299 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9300 constraint (msb
> 32, _("bit-field extends past end of register"));
9301 /* The instruction encoding stores the LSB and MSB,
9302 not the LSB and width. */
9303 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9304 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9305 inst
.instruction
|= (msb
- 1) << 16;
9313 /* #0 in second position is alternative syntax for bfc, which is
9314 the same instruction but with REG_PC in the Rm field. */
9315 if (!inst
.operands
[1].isreg
)
9316 inst
.operands
[1].reg
= REG_PC
;
9318 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9319 constraint (msb
> 32, _("bit-field extends past end of register"));
9320 /* The instruction encoding stores the LSB and MSB,
9321 not the LSB and width. */
9322 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9323 inst
.instruction
|= inst
.operands
[1].reg
;
9324 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9325 inst
.instruction
|= (msb
- 1) << 16;
9331 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9332 _("bit-field extends past end of register"));
9333 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9334 inst
.instruction
|= inst
.operands
[1].reg
;
9335 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9336 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9339 /* ARM V5 breakpoint instruction (argument parse)
9340 BKPT <16 bit unsigned immediate>
9341 Instruction is not conditional.
9342 The bit pattern given in insns[] has the COND_ALWAYS condition,
9343 and it is an error if the caller tried to override that. */
9348 /* Top 12 of 16 bits to bits 19:8. */
9349 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9351 /* Bottom 4 of 16 bits to bits 3:0. */
9352 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9356 encode_branch (int default_reloc
)
9358 if (inst
.operands
[0].hasreloc
)
9360 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9361 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9362 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9363 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9364 ? BFD_RELOC_ARM_PLT32
9365 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9368 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9369 inst
.relocs
[0].pc_rel
= 1;
9376 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9377 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9380 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9387 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9389 if (inst
.cond
== COND_ALWAYS
)
9390 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9392 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9396 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9399 /* ARM V5 branch-link-exchange instruction (argument parse)
9400 BLX <target_addr> ie BLX(1)
9401 BLX{<condition>} <Rm> ie BLX(2)
9402 Unfortunately, there are two different opcodes for this mnemonic.
9403 So, the insns[].value is not used, and the code here zaps values
9404 into inst.instruction.
9405 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9410 if (inst
.operands
[0].isreg
)
9412 /* Arg is a register; the opcode provided by insns[] is correct.
9413 It is not illegal to do "blx pc", just useless. */
9414 if (inst
.operands
[0].reg
== REG_PC
)
9415 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9417 inst
.instruction
|= inst
.operands
[0].reg
;
9421 /* Arg is an address; this instruction cannot be executed
9422 conditionally, and the opcode must be adjusted.
9423 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9424 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9425 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9426 inst
.instruction
= 0xfa000000;
9427 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9434 bfd_boolean want_reloc
;
9436 if (inst
.operands
[0].reg
== REG_PC
)
9437 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9439 inst
.instruction
|= inst
.operands
[0].reg
;
9440 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9441 it is for ARMv4t or earlier. */
9442 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9443 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9444 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9448 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9453 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9457 /* ARM v5TEJ. Jump to Jazelle code. */
9462 if (inst
.operands
[0].reg
== REG_PC
)
9463 as_tsktsk (_("use of r15 in bxj is not really useful"));
9465 inst
.instruction
|= inst
.operands
[0].reg
;
9468 /* Co-processor data operation:
9469 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9470 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9474 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9475 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9476 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9477 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9478 inst
.instruction
|= inst
.operands
[4].reg
;
9479 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9485 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9486 encode_arm_shifter_operand (1);
9489 /* Transfer between coprocessor and ARM registers.
9490 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9495 No special properties. */
9497 struct deprecated_coproc_regs_s
9504 arm_feature_set deprecated
;
9505 arm_feature_set obsoleted
;
9506 const char *dep_msg
;
9507 const char *obs_msg
;
9510 #define DEPR_ACCESS_V8 \
9511 N_("This coprocessor register access is deprecated in ARMv8")
9513 /* Table of all deprecated coprocessor registers. */
9514 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9516 {15, 0, 7, 10, 5, /* CP15DMB. */
9517 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9518 DEPR_ACCESS_V8
, NULL
},
9519 {15, 0, 7, 10, 4, /* CP15DSB. */
9520 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9521 DEPR_ACCESS_V8
, NULL
},
9522 {15, 0, 7, 5, 4, /* CP15ISB. */
9523 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9524 DEPR_ACCESS_V8
, NULL
},
9525 {14, 6, 1, 0, 0, /* TEEHBR. */
9526 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9527 DEPR_ACCESS_V8
, NULL
},
9528 {14, 6, 0, 0, 0, /* TEECR. */
9529 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9530 DEPR_ACCESS_V8
, NULL
},
9533 #undef DEPR_ACCESS_V8
9535 static const size_t deprecated_coproc_reg_count
=
9536 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9544 Rd
= inst
.operands
[2].reg
;
9547 if (inst
.instruction
== 0xee000010
9548 || inst
.instruction
== 0xfe000010)
9550 reject_bad_reg (Rd
);
9551 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9553 constraint (Rd
== REG_SP
, BAD_SP
);
9558 if (inst
.instruction
== 0xe000010)
9559 constraint (Rd
== REG_PC
, BAD_PC
);
9562 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9564 const struct deprecated_coproc_regs_s
*r
=
9565 deprecated_coproc_regs
+ i
;
9567 if (inst
.operands
[0].reg
== r
->cp
9568 && inst
.operands
[1].imm
== r
->opc1
9569 && inst
.operands
[3].reg
== r
->crn
9570 && inst
.operands
[4].reg
== r
->crm
9571 && inst
.operands
[5].imm
== r
->opc2
)
9573 if (! ARM_CPU_IS_ANY (cpu_variant
)
9574 && warn_on_deprecated
9575 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9576 as_tsktsk ("%s", r
->dep_msg
);
9580 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9581 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9582 inst
.instruction
|= Rd
<< 12;
9583 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9584 inst
.instruction
|= inst
.operands
[4].reg
;
9585 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9588 /* Transfer between coprocessor register and pair of ARM registers.
9589 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9594 Two XScale instructions are special cases of these:
9596 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9597 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9599 Result unpredictable if Rd or Rn is R15. */
9606 Rd
= inst
.operands
[2].reg
;
9607 Rn
= inst
.operands
[3].reg
;
9611 reject_bad_reg (Rd
);
9612 reject_bad_reg (Rn
);
9616 constraint (Rd
== REG_PC
, BAD_PC
);
9617 constraint (Rn
== REG_PC
, BAD_PC
);
9620 /* Only check the MRRC{2} variants. */
9621 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9623 /* If Rd == Rn, error that the operation is
9624 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9625 constraint (Rd
== Rn
, BAD_OVERLAP
);
9628 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9629 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9630 inst
.instruction
|= Rd
<< 12;
9631 inst
.instruction
|= Rn
<< 16;
9632 inst
.instruction
|= inst
.operands
[4].reg
;
9638 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9639 if (inst
.operands
[1].present
)
9641 inst
.instruction
|= CPSI_MMOD
;
9642 inst
.instruction
|= inst
.operands
[1].imm
;
9649 inst
.instruction
|= inst
.operands
[0].imm
;
9655 unsigned Rd
, Rn
, Rm
;
9657 Rd
= inst
.operands
[0].reg
;
9658 Rn
= (inst
.operands
[1].present
9659 ? inst
.operands
[1].reg
: Rd
);
9660 Rm
= inst
.operands
[2].reg
;
9662 constraint ((Rd
== REG_PC
), BAD_PC
);
9663 constraint ((Rn
== REG_PC
), BAD_PC
);
9664 constraint ((Rm
== REG_PC
), BAD_PC
);
9666 inst
.instruction
|= Rd
<< 16;
9667 inst
.instruction
|= Rn
<< 0;
9668 inst
.instruction
|= Rm
<< 8;
9674 /* There is no IT instruction in ARM mode. We
9675 process it to do the validation as if in
9676 thumb mode, just in case the code gets
9677 assembled for thumb using the unified syntax. */
9682 set_pred_insn_type (IT_INSN
);
9683 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9684 now_pred
.cc
= inst
.operands
[0].imm
;
9688 /* If there is only one register in the register list,
9689 then return its register number. Otherwise return -1. */
9691 only_one_reg_in_list (int range
)
9693 int i
= ffs (range
) - 1;
9694 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9698 encode_ldmstm(int from_push_pop_mnem
)
9700 int base_reg
= inst
.operands
[0].reg
;
9701 int range
= inst
.operands
[1].imm
;
9704 inst
.instruction
|= base_reg
<< 16;
9705 inst
.instruction
|= range
;
9707 if (inst
.operands
[1].writeback
)
9708 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9710 if (inst
.operands
[0].writeback
)
9712 inst
.instruction
|= WRITE_BACK
;
9713 /* Check for unpredictable uses of writeback. */
9714 if (inst
.instruction
& LOAD_BIT
)
9716 /* Not allowed in LDM type 2. */
9717 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9718 && ((range
& (1 << REG_PC
)) == 0))
9719 as_warn (_("writeback of base register is UNPREDICTABLE"));
9720 /* Only allowed if base reg not in list for other types. */
9721 else if (range
& (1 << base_reg
))
9722 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9726 /* Not allowed for type 2. */
9727 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9728 as_warn (_("writeback of base register is UNPREDICTABLE"));
9729 /* Only allowed if base reg not in list, or first in list. */
9730 else if ((range
& (1 << base_reg
))
9731 && (range
& ((1 << base_reg
) - 1)))
9732 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9736 /* If PUSH/POP has only one register, then use the A2 encoding. */
9737 one_reg
= only_one_reg_in_list (range
);
9738 if (from_push_pop_mnem
&& one_reg
>= 0)
9740 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9742 if (is_push
&& one_reg
== 13 /* SP */)
9743 /* PR 22483: The A2 encoding cannot be used when
9744 pushing the stack pointer as this is UNPREDICTABLE. */
9747 inst
.instruction
&= A_COND_MASK
;
9748 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9749 inst
.instruction
|= one_reg
<< 12;
9756 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9759 /* ARMv5TE load-consecutive (argument parse)
9768 constraint (inst
.operands
[0].reg
% 2 != 0,
9769 _("first transfer register must be even"));
9770 constraint (inst
.operands
[1].present
9771 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9772 _("can only transfer two consecutive registers"));
9773 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9774 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9776 if (!inst
.operands
[1].present
)
9777 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9779 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9780 register and the first register written; we have to diagnose
9781 overlap between the base and the second register written here. */
9783 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9784 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9785 as_warn (_("base register written back, and overlaps "
9786 "second transfer register"));
9788 if (!(inst
.instruction
& V4_STR_BIT
))
9790 /* For an index-register load, the index register must not overlap the
9791 destination (even if not write-back). */
9792 if (inst
.operands
[2].immisreg
9793 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9794 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9795 as_warn (_("index register overlaps transfer register"));
9797 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9798 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9804 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9805 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9806 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9807 || inst
.operands
[1].negative
9808 /* This can arise if the programmer has written
9810 or if they have mistakenly used a register name as the last
9813 It is very difficult to distinguish between these two cases
9814 because "rX" might actually be a label. ie the register
9815 name has been occluded by a symbol of the same name. So we
9816 just generate a general 'bad addressing mode' type error
9817 message and leave it up to the programmer to discover the
9818 true cause and fix their mistake. */
9819 || (inst
.operands
[1].reg
== REG_PC
),
9822 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9823 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9824 _("offset must be zero in ARM encoding"));
9826 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9828 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9829 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9830 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9836 constraint (inst
.operands
[0].reg
% 2 != 0,
9837 _("even register required"));
9838 constraint (inst
.operands
[1].present
9839 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9840 _("can only load two consecutive registers"));
9841 /* If op 1 were present and equal to PC, this function wouldn't
9842 have been called in the first place. */
9843 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9845 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9846 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9849 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9850 which is not a multiple of four is UNPREDICTABLE. */
9852 check_ldr_r15_aligned (void)
9854 constraint (!(inst
.operands
[1].immisreg
)
9855 && (inst
.operands
[0].reg
== REG_PC
9856 && inst
.operands
[1].reg
== REG_PC
9857 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9858 _("ldr to register 15 must be 4-byte aligned"));
9864 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9865 if (!inst
.operands
[1].isreg
)
9866 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9868 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9869 check_ldr_r15_aligned ();
9875 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9877 if (inst
.operands
[1].preind
)
9879 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9880 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9881 _("this instruction requires a post-indexed address"));
9883 inst
.operands
[1].preind
= 0;
9884 inst
.operands
[1].postind
= 1;
9885 inst
.operands
[1].writeback
= 1;
9887 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9888 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9891 /* Halfword and signed-byte load/store operations. */
9896 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9897 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9898 if (!inst
.operands
[1].isreg
)
9899 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9901 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9907 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9909 if (inst
.operands
[1].preind
)
9911 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9912 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9913 _("this instruction requires a post-indexed address"));
9915 inst
.operands
[1].preind
= 0;
9916 inst
.operands
[1].postind
= 1;
9917 inst
.operands
[1].writeback
= 1;
9919 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9920 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9923 /* Co-processor register load/store.
9924 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9928 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9929 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9930 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9936 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9937 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9938 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9939 && !(inst
.instruction
& 0x00400000))
9940 as_tsktsk (_("Rd and Rm should be different in mla"));
9942 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9943 inst
.instruction
|= inst
.operands
[1].reg
;
9944 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9945 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9951 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9952 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9955 encode_arm_shifter_operand (1);
9958 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9965 top
= (inst
.instruction
& 0x00400000) != 0;
9966 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9967 _(":lower16: not allowed in this instruction"));
9968 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9969 _(":upper16: not allowed in this instruction"));
9970 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9971 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9973 imm
= inst
.relocs
[0].exp
.X_add_number
;
9974 /* The value is in two pieces: 0:11, 16:19. */
9975 inst
.instruction
|= (imm
& 0x00000fff);
9976 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9981 do_vfp_nsyn_mrs (void)
9983 if (inst
.operands
[0].isvec
)
9985 if (inst
.operands
[1].reg
!= 1)
9986 first_error (_("operand 1 must be FPSCR"));
9987 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9988 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9989 do_vfp_nsyn_opcode ("fmstat");
9991 else if (inst
.operands
[1].isvec
)
9992 do_vfp_nsyn_opcode ("fmrx");
10000 do_vfp_nsyn_msr (void)
10002 if (inst
.operands
[0].isvec
)
10003 do_vfp_nsyn_opcode ("fmxr");
10013 unsigned Rt
= inst
.operands
[0].reg
;
10015 if (thumb_mode
&& Rt
== REG_SP
)
10017 inst
.error
= BAD_SP
;
10021 switch (inst
.operands
[1].reg
)
10023 /* MVFR2 is only valid for Armv8-A. */
10025 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10029 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10030 case 1: /* fpscr. */
10031 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10032 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10036 case 14: /* fpcxt_ns. */
10037 case 15: /* fpcxt_s. */
10038 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10039 _("selected processor does not support instruction"));
10042 case 2: /* fpscr_nzcvqc. */
10043 case 12: /* vpr. */
10045 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10046 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10047 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10048 _("selected processor does not support instruction"));
10049 if (inst
.operands
[0].reg
!= 2
10050 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10051 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10058 /* APSR_ sets isvec. All other refs to PC are illegal. */
10059 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
10061 inst
.error
= BAD_PC
;
10065 /* If we get through parsing the register name, we just insert the number
10066 generated into the instruction without further validation. */
10067 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
10068 inst
.instruction
|= (Rt
<< 12);
10074 unsigned Rt
= inst
.operands
[1].reg
;
10077 reject_bad_reg (Rt
);
10078 else if (Rt
== REG_PC
)
10080 inst
.error
= BAD_PC
;
10084 switch (inst
.operands
[0].reg
)
10086 /* MVFR2 is only valid for Armv8-A. */
10088 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10092 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10093 case 1: /* fpcr. */
10094 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10095 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10099 case 14: /* fpcxt_ns. */
10100 case 15: /* fpcxt_s. */
10101 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10102 _("selected processor does not support instruction"));
10105 case 2: /* fpscr_nzcvqc. */
10106 case 12: /* vpr. */
10108 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10109 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10110 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10111 _("selected processor does not support instruction"));
10112 if (inst
.operands
[0].reg
!= 2
10113 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10114 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10121 /* If we get through parsing the register name, we just insert the number
10122 generated into the instruction without further validation. */
10123 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10124 inst
.instruction
|= (Rt
<< 12);
10132 if (do_vfp_nsyn_mrs () == SUCCESS
)
10135 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10136 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10138 if (inst
.operands
[1].isreg
)
10140 br
= inst
.operands
[1].reg
;
10141 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10142 as_bad (_("bad register for mrs"));
10146 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10147 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10149 _("'APSR', 'CPSR' or 'SPSR' expected"));
10150 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10153 inst
.instruction
|= br
;
10156 /* Two possible forms:
10157 "{C|S}PSR_<field>, Rm",
10158 "{C|S}PSR_f, #expression". */
10163 if (do_vfp_nsyn_msr () == SUCCESS
)
10166 inst
.instruction
|= inst
.operands
[0].imm
;
10167 if (inst
.operands
[1].isreg
)
10168 inst
.instruction
|= inst
.operands
[1].reg
;
10171 inst
.instruction
|= INST_IMMEDIATE
;
10172 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10173 inst
.relocs
[0].pc_rel
= 0;
10180 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10182 if (!inst
.operands
[2].present
)
10183 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10184 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10185 inst
.instruction
|= inst
.operands
[1].reg
;
10186 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10188 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10189 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10190 as_tsktsk (_("Rd and Rm should be different in mul"));
10193 /* Long Multiply Parser
10194 UMULL RdLo, RdHi, Rm, Rs
10195 SMULL RdLo, RdHi, Rm, Rs
10196 UMLAL RdLo, RdHi, Rm, Rs
10197 SMLAL RdLo, RdHi, Rm, Rs. */
10202 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10203 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10204 inst
.instruction
|= inst
.operands
[2].reg
;
10205 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10207 /* rdhi and rdlo must be different. */
10208 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10209 as_tsktsk (_("rdhi and rdlo must be different"));
10211 /* rdhi, rdlo and rm must all be different before armv6. */
10212 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10213 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10214 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10215 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10221 if (inst
.operands
[0].present
10222 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10224 /* Architectural NOP hints are CPSR sets with no bits selected. */
10225 inst
.instruction
&= 0xf0000000;
10226 inst
.instruction
|= 0x0320f000;
10227 if (inst
.operands
[0].present
)
10228 inst
.instruction
|= inst
.operands
[0].imm
;
10232 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10233 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10234 Condition defaults to COND_ALWAYS.
10235 Error if Rd, Rn or Rm are R15. */
10240 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10241 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10242 inst
.instruction
|= inst
.operands
[2].reg
;
10243 if (inst
.operands
[3].present
)
10244 encode_arm_shift (3);
10247 /* ARM V6 PKHTB (Argument Parse). */
10252 if (!inst
.operands
[3].present
)
10254 /* If the shift specifier is omitted, turn the instruction
10255 into pkhbt rd, rm, rn. */
10256 inst
.instruction
&= 0xfff00010;
10257 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10258 inst
.instruction
|= inst
.operands
[1].reg
;
10259 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10263 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10264 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10265 inst
.instruction
|= inst
.operands
[2].reg
;
10266 encode_arm_shift (3);
10270 /* ARMv5TE: Preload-Cache
10271 MP Extensions: Preload for write
10275 Syntactically, like LDR with B=1, W=0, L=1. */
10280 constraint (!inst
.operands
[0].isreg
,
10281 _("'[' expected after PLD mnemonic"));
10282 constraint (inst
.operands
[0].postind
,
10283 _("post-indexed expression used in preload instruction"));
10284 constraint (inst
.operands
[0].writeback
,
10285 _("writeback used in preload instruction"));
10286 constraint (!inst
.operands
[0].preind
,
10287 _("unindexed addressing used in preload instruction"));
10288 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10291 /* ARMv7: PLI <addr_mode> */
10295 constraint (!inst
.operands
[0].isreg
,
10296 _("'[' expected after PLI mnemonic"));
10297 constraint (inst
.operands
[0].postind
,
10298 _("post-indexed expression used in preload instruction"));
10299 constraint (inst
.operands
[0].writeback
,
10300 _("writeback used in preload instruction"));
10301 constraint (!inst
.operands
[0].preind
,
10302 _("unindexed addressing used in preload instruction"));
10303 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10304 inst
.instruction
&= ~PRE_INDEX
;
10310 constraint (inst
.operands
[0].writeback
,
10311 _("push/pop do not support {reglist}^"));
10312 inst
.operands
[1] = inst
.operands
[0];
10313 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10314 inst
.operands
[0].isreg
= 1;
10315 inst
.operands
[0].writeback
= 1;
10316 inst
.operands
[0].reg
= REG_SP
;
10317 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10320 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10321 word at the specified address and the following word
10323 Unconditionally executed.
10324 Error if Rn is R15. */
10329 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10330 if (inst
.operands
[0].writeback
)
10331 inst
.instruction
|= WRITE_BACK
;
10334 /* ARM V6 ssat (argument parse). */
10339 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10340 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10341 inst
.instruction
|= inst
.operands
[2].reg
;
10343 if (inst
.operands
[3].present
)
10344 encode_arm_shift (3);
10347 /* ARM V6 usat (argument parse). */
10352 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10353 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10354 inst
.instruction
|= inst
.operands
[2].reg
;
10356 if (inst
.operands
[3].present
)
10357 encode_arm_shift (3);
10360 /* ARM V6 ssat16 (argument parse). */
10365 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10366 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10367 inst
.instruction
|= inst
.operands
[2].reg
;
10373 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10374 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10375 inst
.instruction
|= inst
.operands
[2].reg
;
10378 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10379 preserving the other bits.
10381 setend <endian_specifier>, where <endian_specifier> is either
10387 if (warn_on_deprecated
10388 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10389 as_tsktsk (_("setend use is deprecated for ARMv8"));
10391 if (inst
.operands
[0].imm
)
10392 inst
.instruction
|= 0x200;
10398 unsigned int Rm
= (inst
.operands
[1].present
10399 ? inst
.operands
[1].reg
10400 : inst
.operands
[0].reg
);
10402 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10403 inst
.instruction
|= Rm
;
10404 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10406 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10407 inst
.instruction
|= SHIFT_BY_REG
;
10408 /* PR 12854: Error on extraneous shifts. */
10409 constraint (inst
.operands
[2].shifted
,
10410 _("extraneous shift as part of operand to shift insn"));
10413 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10419 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10420 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10422 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10423 inst
.relocs
[0].pc_rel
= 0;
10429 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10430 inst
.relocs
[0].pc_rel
= 0;
10436 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10437 inst
.relocs
[0].pc_rel
= 0;
10443 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10444 _("selected processor does not support SETPAN instruction"));
10446 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10452 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10453 _("selected processor does not support SETPAN instruction"));
10455 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10458 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10459 SMLAxy{cond} Rd,Rm,Rs,Rn
10460 SMLAWy{cond} Rd,Rm,Rs,Rn
10461 Error if any register is R15. */
10466 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10467 inst
.instruction
|= inst
.operands
[1].reg
;
10468 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10469 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10472 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10473 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10474 Error if any register is R15.
10475 Warning if Rdlo == Rdhi. */
10480 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10481 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10482 inst
.instruction
|= inst
.operands
[2].reg
;
10483 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10485 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10486 as_tsktsk (_("rdhi and rdlo must be different"));
10489 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10490 SMULxy{cond} Rd,Rm,Rs
10491 Error if any register is R15. */
10496 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10497 inst
.instruction
|= inst
.operands
[1].reg
;
10498 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10501 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10502 the same for both ARM and Thumb-2. */
10509 if (inst
.operands
[0].present
)
10511 reg
= inst
.operands
[0].reg
;
10512 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10517 inst
.instruction
|= reg
<< 16;
10518 inst
.instruction
|= inst
.operands
[1].imm
;
10519 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10520 inst
.instruction
|= WRITE_BACK
;
10523 /* ARM V6 strex (argument parse). */
10528 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10529 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10530 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10531 || inst
.operands
[2].negative
10532 /* See comment in do_ldrex(). */
10533 || (inst
.operands
[2].reg
== REG_PC
),
10536 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10537 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10539 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10540 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10541 _("offset must be zero in ARM encoding"));
10543 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10544 inst
.instruction
|= inst
.operands
[1].reg
;
10545 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10546 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10550 do_t_strexbh (void)
10552 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10553 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10554 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10555 || inst
.operands
[2].negative
,
10558 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10559 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10567 constraint (inst
.operands
[1].reg
% 2 != 0,
10568 _("even register required"));
10569 constraint (inst
.operands
[2].present
10570 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10571 _("can only store two consecutive registers"));
10572 /* If op 2 were present and equal to PC, this function wouldn't
10573 have been called in the first place. */
10574 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10576 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10577 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10578 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10581 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10582 inst
.instruction
|= inst
.operands
[1].reg
;
10583 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10590 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10591 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10599 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10600 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10605 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10606 extends it to 32-bits, and adds the result to a value in another
10607 register. You can specify a rotation by 0, 8, 16, or 24 bits
10608 before extracting the 16-bit value.
10609 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10610 Condition defaults to COND_ALWAYS.
10611 Error if any register uses R15. */
10616 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10617 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10618 inst
.instruction
|= inst
.operands
[2].reg
;
10619 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10624 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10625 Condition defaults to COND_ALWAYS.
10626 Error if any register uses R15. */
10631 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10632 inst
.instruction
|= inst
.operands
[1].reg
;
10633 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10636 /* VFP instructions. In a logical order: SP variant first, monad
10637 before dyad, arithmetic then move then load/store. */
10640 do_vfp_sp_monadic (void)
10642 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10643 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10646 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10647 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10651 do_vfp_sp_dyadic (void)
10653 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10654 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10655 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10659 do_vfp_sp_compare_z (void)
10661 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10665 do_vfp_dp_sp_cvt (void)
10667 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10668 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10672 do_vfp_sp_dp_cvt (void)
10674 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10675 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10679 do_vfp_reg_from_sp (void)
10681 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10682 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10685 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10686 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10690 do_vfp_reg2_from_sp2 (void)
10692 constraint (inst
.operands
[2].imm
!= 2,
10693 _("only two consecutive VFP SP registers allowed here"));
10694 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10695 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10696 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10700 do_vfp_sp_from_reg (void)
10702 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10703 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10706 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10707 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10711 do_vfp_sp2_from_reg2 (void)
10713 constraint (inst
.operands
[0].imm
!= 2,
10714 _("only two consecutive VFP SP registers allowed here"));
10715 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10716 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10717 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10721 do_vfp_sp_ldst (void)
10723 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10724 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10728 do_vfp_dp_ldst (void)
10730 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10731 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10736 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10738 if (inst
.operands
[0].writeback
)
10739 inst
.instruction
|= WRITE_BACK
;
10741 constraint (ldstm_type
!= VFP_LDSTMIA
,
10742 _("this addressing mode requires base-register writeback"));
10743 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10744 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10745 inst
.instruction
|= inst
.operands
[1].imm
;
10749 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10753 if (inst
.operands
[0].writeback
)
10754 inst
.instruction
|= WRITE_BACK
;
10756 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10757 _("this addressing mode requires base-register writeback"));
10759 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10760 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10762 count
= inst
.operands
[1].imm
<< 1;
10763 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10766 inst
.instruction
|= count
;
10770 do_vfp_sp_ldstmia (void)
10772 vfp_sp_ldstm (VFP_LDSTMIA
);
10776 do_vfp_sp_ldstmdb (void)
10778 vfp_sp_ldstm (VFP_LDSTMDB
);
10782 do_vfp_dp_ldstmia (void)
10784 vfp_dp_ldstm (VFP_LDSTMIA
);
10788 do_vfp_dp_ldstmdb (void)
10790 vfp_dp_ldstm (VFP_LDSTMDB
);
10794 do_vfp_xp_ldstmia (void)
10796 vfp_dp_ldstm (VFP_LDSTMIAX
);
10800 do_vfp_xp_ldstmdb (void)
10802 vfp_dp_ldstm (VFP_LDSTMDBX
);
10806 do_vfp_dp_rd_rm (void)
10808 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10809 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10812 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10813 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10817 do_vfp_dp_rn_rd (void)
10819 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10820 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10824 do_vfp_dp_rd_rn (void)
10826 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10827 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10831 do_vfp_dp_rd_rn_rm (void)
10833 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10834 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10837 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10838 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10839 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10843 do_vfp_dp_rd (void)
10845 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10849 do_vfp_dp_rm_rd_rn (void)
10851 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10852 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10855 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10856 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10857 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10860 /* VFPv3 instructions. */
10862 do_vfp_sp_const (void)
10864 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10865 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10866 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10870 do_vfp_dp_const (void)
10872 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10873 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10874 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10878 vfp_conv (int srcsize
)
10880 int immbits
= srcsize
- inst
.operands
[1].imm
;
10882 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10884 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10885 i.e. immbits must be in range 0 - 16. */
10886 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10889 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10891 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10892 i.e. immbits must be in range 0 - 31. */
10893 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10897 inst
.instruction
|= (immbits
& 1) << 5;
10898 inst
.instruction
|= (immbits
>> 1);
10902 do_vfp_sp_conv_16 (void)
10904 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10909 do_vfp_dp_conv_16 (void)
10911 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10916 do_vfp_sp_conv_32 (void)
10918 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10923 do_vfp_dp_conv_32 (void)
10925 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10929 /* FPA instructions. Also in a logical order. */
10934 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10935 inst
.instruction
|= inst
.operands
[1].reg
;
10939 do_fpa_ldmstm (void)
10941 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10942 switch (inst
.operands
[1].imm
)
10944 case 1: inst
.instruction
|= CP_T_X
; break;
10945 case 2: inst
.instruction
|= CP_T_Y
; break;
10946 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10951 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10953 /* The instruction specified "ea" or "fd", so we can only accept
10954 [Rn]{!}. The instruction does not really support stacking or
10955 unstacking, so we have to emulate these by setting appropriate
10956 bits and offsets. */
10957 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10958 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10959 _("this instruction does not support indexing"));
10961 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10962 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10964 if (!(inst
.instruction
& INDEX_UP
))
10965 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10967 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10969 inst
.operands
[2].preind
= 0;
10970 inst
.operands
[2].postind
= 1;
10974 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10977 /* iWMMXt instructions: strictly in alphabetical order. */
10980 do_iwmmxt_tandorc (void)
10982 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10986 do_iwmmxt_textrc (void)
10988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10989 inst
.instruction
|= inst
.operands
[1].imm
;
10993 do_iwmmxt_textrm (void)
10995 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10996 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10997 inst
.instruction
|= inst
.operands
[2].imm
;
11001 do_iwmmxt_tinsr (void)
11003 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11004 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11005 inst
.instruction
|= inst
.operands
[2].imm
;
11009 do_iwmmxt_tmia (void)
11011 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11012 inst
.instruction
|= inst
.operands
[1].reg
;
11013 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11017 do_iwmmxt_waligni (void)
11019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11020 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11021 inst
.instruction
|= inst
.operands
[2].reg
;
11022 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
11026 do_iwmmxt_wmerge (void)
11028 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11029 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11030 inst
.instruction
|= inst
.operands
[2].reg
;
11031 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
11035 do_iwmmxt_wmov (void)
11037 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
11038 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11039 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11040 inst
.instruction
|= inst
.operands
[1].reg
;
11044 do_iwmmxt_wldstbh (void)
11047 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11049 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
11051 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
11052 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
11056 do_iwmmxt_wldstw (void)
11058 /* RIWR_RIWC clears .isreg for a control register. */
11059 if (!inst
.operands
[0].isreg
)
11061 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
11062 inst
.instruction
|= 0xf0000000;
11065 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11066 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
11070 do_iwmmxt_wldstd (void)
11072 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11073 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
11074 && inst
.operands
[1].immisreg
)
11076 inst
.instruction
&= ~0x1a000ff;
11077 inst
.instruction
|= (0xfU
<< 28);
11078 if (inst
.operands
[1].preind
)
11079 inst
.instruction
|= PRE_INDEX
;
11080 if (!inst
.operands
[1].negative
)
11081 inst
.instruction
|= INDEX_UP
;
11082 if (inst
.operands
[1].writeback
)
11083 inst
.instruction
|= WRITE_BACK
;
11084 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11085 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11086 inst
.instruction
|= inst
.operands
[1].imm
;
11089 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11093 do_iwmmxt_wshufh (void)
11095 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11096 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11097 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11098 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11102 do_iwmmxt_wzero (void)
11104 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11105 inst
.instruction
|= inst
.operands
[0].reg
;
11106 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11107 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11111 do_iwmmxt_wrwrwr_or_imm5 (void)
11113 if (inst
.operands
[2].isreg
)
11116 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11117 _("immediate operand requires iWMMXt2"));
11119 if (inst
.operands
[2].imm
== 0)
11121 switch ((inst
.instruction
>> 20) & 0xf)
11127 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11128 inst
.operands
[2].imm
= 16;
11129 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11135 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11136 inst
.operands
[2].imm
= 32;
11137 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11144 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11146 wrn
= (inst
.instruction
>> 16) & 0xf;
11147 inst
.instruction
&= 0xff0fff0f;
11148 inst
.instruction
|= wrn
;
11149 /* Bail out here; the instruction is now assembled. */
11154 /* Map 32 -> 0, etc. */
11155 inst
.operands
[2].imm
&= 0x1f;
11156 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11160 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11161 operations first, then control, shift, and load/store. */
11163 /* Insns like "foo X,Y,Z". */
11166 do_mav_triple (void)
11168 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11169 inst
.instruction
|= inst
.operands
[1].reg
;
11170 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11173 /* Insns like "foo W,X,Y,Z".
11174 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11179 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11180 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11181 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11182 inst
.instruction
|= inst
.operands
[3].reg
;
11185 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11187 do_mav_dspsc (void)
11189 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11192 /* Maverick shift immediate instructions.
11193 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11194 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11197 do_mav_shift (void)
11199 int imm
= inst
.operands
[2].imm
;
11201 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11202 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11204 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11205 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11206 Bit 4 should be 0. */
11207 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11209 inst
.instruction
|= imm
;
11212 /* XScale instructions. Also sorted arithmetic before move. */
11214 /* Xscale multiply-accumulate (argument parse)
11217 MIAxycc acc0,Rm,Rs. */
11222 inst
.instruction
|= inst
.operands
[1].reg
;
11223 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11226 /* Xscale move-accumulator-register (argument parse)
11228 MARcc acc0,RdLo,RdHi. */
11233 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11234 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11237 /* Xscale move-register-accumulator (argument parse)
11239 MRAcc RdLo,RdHi,acc0. */
11244 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11245 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11246 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11249 /* Encoding functions relevant only to Thumb. */
11251 /* inst.operands[i] is a shifted-register operand; encode
11252 it into inst.instruction in the format used by Thumb32. */
11255 encode_thumb32_shifted_operand (int i
)
11257 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11258 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11260 constraint (inst
.operands
[i
].immisreg
,
11261 _("shift by register not allowed in thumb mode"));
11262 inst
.instruction
|= inst
.operands
[i
].reg
;
11263 if (shift
== SHIFT_RRX
)
11264 inst
.instruction
|= SHIFT_ROR
<< 4;
11267 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11268 _("expression too complex"));
11270 constraint (value
> 32
11271 || (value
== 32 && (shift
== SHIFT_LSL
11272 || shift
== SHIFT_ROR
)),
11273 _("shift expression is too large"));
11277 else if (value
== 32)
11280 inst
.instruction
|= shift
<< 4;
11281 inst
.instruction
|= (value
& 0x1c) << 10;
11282 inst
.instruction
|= (value
& 0x03) << 6;
11287 /* inst.operands[i] was set up by parse_address. Encode it into a
11288 Thumb32 format load or store instruction. Reject forms that cannot
11289 be used with such instructions. If is_t is true, reject forms that
11290 cannot be used with a T instruction; if is_d is true, reject forms
11291 that cannot be used with a D instruction. If it is a store insn,
11292 reject PC in Rn. */
11295 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11297 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11299 constraint (!inst
.operands
[i
].isreg
,
11300 _("Instruction does not support =N addresses"));
11302 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11303 if (inst
.operands
[i
].immisreg
)
11305 constraint (is_pc
, BAD_PC_ADDRESSING
);
11306 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11307 constraint (inst
.operands
[i
].negative
,
11308 _("Thumb does not support negative register indexing"));
11309 constraint (inst
.operands
[i
].postind
,
11310 _("Thumb does not support register post-indexing"));
11311 constraint (inst
.operands
[i
].writeback
,
11312 _("Thumb does not support register indexing with writeback"));
11313 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11314 _("Thumb supports only LSL in shifted register indexing"));
11316 inst
.instruction
|= inst
.operands
[i
].imm
;
11317 if (inst
.operands
[i
].shifted
)
11319 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11320 _("expression too complex"));
11321 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11322 || inst
.relocs
[0].exp
.X_add_number
> 3,
11323 _("shift out of range"));
11324 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11326 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11328 else if (inst
.operands
[i
].preind
)
11330 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11331 constraint (is_t
&& inst
.operands
[i
].writeback
,
11332 _("cannot use writeback with this instruction"));
11333 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11334 BAD_PC_ADDRESSING
);
11338 inst
.instruction
|= 0x01000000;
11339 if (inst
.operands
[i
].writeback
)
11340 inst
.instruction
|= 0x00200000;
11344 inst
.instruction
|= 0x00000c00;
11345 if (inst
.operands
[i
].writeback
)
11346 inst
.instruction
|= 0x00000100;
11348 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11350 else if (inst
.operands
[i
].postind
)
11352 gas_assert (inst
.operands
[i
].writeback
);
11353 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11354 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11357 inst
.instruction
|= 0x00200000;
11359 inst
.instruction
|= 0x00000900;
11360 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11362 else /* unindexed - only for coprocessor */
11363 inst
.error
= _("instruction does not accept unindexed addressing");
11366 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11367 encodings (the latter only in post-V6T2 cores). The index is the
11368 value used in the insns table below. When there is more than one
11369 possible 16-bit encoding for the instruction, this table always
11371 Also contains several pseudo-instructions used during relaxation. */
11372 #define T16_32_TAB \
11373 X(_adc, 4140, eb400000), \
11374 X(_adcs, 4140, eb500000), \
11375 X(_add, 1c00, eb000000), \
11376 X(_adds, 1c00, eb100000), \
11377 X(_addi, 0000, f1000000), \
11378 X(_addis, 0000, f1100000), \
11379 X(_add_pc,000f, f20f0000), \
11380 X(_add_sp,000d, f10d0000), \
11381 X(_adr, 000f, f20f0000), \
11382 X(_and, 4000, ea000000), \
11383 X(_ands, 4000, ea100000), \
11384 X(_asr, 1000, fa40f000), \
11385 X(_asrs, 1000, fa50f000), \
11386 X(_b, e000, f000b000), \
11387 X(_bcond, d000, f0008000), \
11388 X(_bf, 0000, f040e001), \
11389 X(_bfcsel,0000, f000e001), \
11390 X(_bfx, 0000, f060e001), \
11391 X(_bfl, 0000, f000c001), \
11392 X(_bflx, 0000, f070e001), \
11393 X(_bic, 4380, ea200000), \
11394 X(_bics, 4380, ea300000), \
11395 X(_cinc, 0000, ea509000), \
11396 X(_cinv, 0000, ea50a000), \
11397 X(_cmn, 42c0, eb100f00), \
11398 X(_cmp, 2800, ebb00f00), \
11399 X(_cneg, 0000, ea50b000), \
11400 X(_cpsie, b660, f3af8400), \
11401 X(_cpsid, b670, f3af8600), \
11402 X(_cpy, 4600, ea4f0000), \
11403 X(_csel, 0000, ea508000), \
11404 X(_cset, 0000, ea5f900f), \
11405 X(_csetm, 0000, ea5fa00f), \
11406 X(_csinc, 0000, ea509000), \
11407 X(_csinv, 0000, ea50a000), \
11408 X(_csneg, 0000, ea50b000), \
11409 X(_dec_sp,80dd, f1ad0d00), \
11410 X(_dls, 0000, f040e001), \
11411 X(_dlstp, 0000, f000e001), \
11412 X(_eor, 4040, ea800000), \
11413 X(_eors, 4040, ea900000), \
11414 X(_inc_sp,00dd, f10d0d00), \
11415 X(_lctp, 0000, f00fe001), \
11416 X(_ldmia, c800, e8900000), \
11417 X(_ldr, 6800, f8500000), \
11418 X(_ldrb, 7800, f8100000), \
11419 X(_ldrh, 8800, f8300000), \
11420 X(_ldrsb, 5600, f9100000), \
11421 X(_ldrsh, 5e00, f9300000), \
11422 X(_ldr_pc,4800, f85f0000), \
11423 X(_ldr_pc2,4800, f85f0000), \
11424 X(_ldr_sp,9800, f85d0000), \
11425 X(_le, 0000, f00fc001), \
11426 X(_letp, 0000, f01fc001), \
11427 X(_lsl, 0000, fa00f000), \
11428 X(_lsls, 0000, fa10f000), \
11429 X(_lsr, 0800, fa20f000), \
11430 X(_lsrs, 0800, fa30f000), \
11431 X(_mov, 2000, ea4f0000), \
11432 X(_movs, 2000, ea5f0000), \
11433 X(_mul, 4340, fb00f000), \
11434 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11435 X(_mvn, 43c0, ea6f0000), \
11436 X(_mvns, 43c0, ea7f0000), \
11437 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11438 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11439 X(_orr, 4300, ea400000), \
11440 X(_orrs, 4300, ea500000), \
11441 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11442 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11443 X(_rev, ba00, fa90f080), \
11444 X(_rev16, ba40, fa90f090), \
11445 X(_revsh, bac0, fa90f0b0), \
11446 X(_ror, 41c0, fa60f000), \
11447 X(_rors, 41c0, fa70f000), \
11448 X(_sbc, 4180, eb600000), \
11449 X(_sbcs, 4180, eb700000), \
11450 X(_stmia, c000, e8800000), \
11451 X(_str, 6000, f8400000), \
11452 X(_strb, 7000, f8000000), \
11453 X(_strh, 8000, f8200000), \
11454 X(_str_sp,9000, f84d0000), \
11455 X(_sub, 1e00, eba00000), \
11456 X(_subs, 1e00, ebb00000), \
11457 X(_subi, 8000, f1a00000), \
11458 X(_subis, 8000, f1b00000), \
11459 X(_sxtb, b240, fa4ff080), \
11460 X(_sxth, b200, fa0ff080), \
11461 X(_tst, 4200, ea100f00), \
11462 X(_uxtb, b2c0, fa5ff080), \
11463 X(_uxth, b280, fa1ff080), \
11464 X(_nop, bf00, f3af8000), \
11465 X(_yield, bf10, f3af8001), \
11466 X(_wfe, bf20, f3af8002), \
11467 X(_wfi, bf30, f3af8003), \
11468 X(_wls, 0000, f040c001), \
11469 X(_wlstp, 0000, f000c001), \
11470 X(_sev, bf40, f3af8004), \
11471 X(_sevl, bf50, f3af8005), \
11472 X(_udf, de00, f7f0a000)
11474 /* To catch errors in encoding functions, the codes are all offset by
11475 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11476 as 16-bit instructions. */
11477 #define X(a,b,c) T_MNEM##a
11478 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11481 #define X(a,b,c) 0x##b
11482 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11483 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11486 #define X(a,b,c) 0x##c
11487 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11488 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11489 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11493 /* Thumb instruction encoders, in alphabetical order. */
11495 /* ADDW or SUBW. */
11498 do_t_add_sub_w (void)
11502 Rd
= inst
.operands
[0].reg
;
11503 Rn
= inst
.operands
[1].reg
;
11505 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11506 is the SP-{plus,minus}-immediate form of the instruction. */
11508 constraint (Rd
== REG_PC
, BAD_PC
);
11510 reject_bad_reg (Rd
);
11512 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11513 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11516 /* Parse an add or subtract instruction. We get here with inst.instruction
11517 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11520 do_t_add_sub (void)
11524 Rd
= inst
.operands
[0].reg
;
11525 Rs
= (inst
.operands
[1].present
11526 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11527 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11530 set_pred_insn_type_last ();
11532 if (unified_syntax
)
11535 bfd_boolean narrow
;
11538 flags
= (inst
.instruction
== T_MNEM_adds
11539 || inst
.instruction
== T_MNEM_subs
);
11541 narrow
= !in_pred_block ();
11543 narrow
= in_pred_block ();
11544 if (!inst
.operands
[2].isreg
)
11548 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11549 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11551 add
= (inst
.instruction
== T_MNEM_add
11552 || inst
.instruction
== T_MNEM_adds
);
11554 if (inst
.size_req
!= 4)
11556 /* Attempt to use a narrow opcode, with relaxation if
11558 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11559 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11560 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11561 opcode
= T_MNEM_add_sp
;
11562 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11563 opcode
= T_MNEM_add_pc
;
11564 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11567 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11569 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11573 inst
.instruction
= THUMB_OP16(opcode
);
11574 inst
.instruction
|= (Rd
<< 4) | Rs
;
11575 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11576 || (inst
.relocs
[0].type
11577 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11579 if (inst
.size_req
== 2)
11580 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11582 inst
.relax
= opcode
;
11586 constraint (inst
.size_req
== 2, BAD_HIREG
);
11588 if (inst
.size_req
== 4
11589 || (inst
.size_req
!= 2 && !opcode
))
11591 constraint ((inst
.relocs
[0].type
11592 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11593 && (inst
.relocs
[0].type
11594 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11595 THUMB1_RELOC_ONLY
);
11598 constraint (add
, BAD_PC
);
11599 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11600 _("only SUBS PC, LR, #const allowed"));
11601 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11602 _("expression too complex"));
11603 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11604 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11605 _("immediate value out of range"));
11606 inst
.instruction
= T2_SUBS_PC_LR
11607 | inst
.relocs
[0].exp
.X_add_number
;
11608 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11611 else if (Rs
== REG_PC
)
11613 /* Always use addw/subw. */
11614 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11615 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11619 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11620 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11623 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11625 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11627 inst
.instruction
|= Rd
<< 8;
11628 inst
.instruction
|= Rs
<< 16;
11633 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11634 unsigned int shift
= inst
.operands
[2].shift_kind
;
11636 Rn
= inst
.operands
[2].reg
;
11637 /* See if we can do this with a 16-bit instruction. */
11638 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11640 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11645 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11646 || inst
.instruction
== T_MNEM_add
)
11648 : T_OPCODE_SUB_R3
);
11649 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11653 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11655 /* Thumb-1 cores (except v6-M) require at least one high
11656 register in a narrow non flag setting add. */
11657 if (Rd
> 7 || Rn
> 7
11658 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11659 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11666 inst
.instruction
= T_OPCODE_ADD_HI
;
11667 inst
.instruction
|= (Rd
& 8) << 4;
11668 inst
.instruction
|= (Rd
& 7);
11669 inst
.instruction
|= Rn
<< 3;
11675 constraint (Rd
== REG_PC
, BAD_PC
);
11676 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11677 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11678 constraint (Rs
== REG_PC
, BAD_PC
);
11679 reject_bad_reg (Rn
);
11681 /* If we get here, it can't be done in 16 bits. */
11682 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11683 _("shift must be constant"));
11684 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11685 inst
.instruction
|= Rd
<< 8;
11686 inst
.instruction
|= Rs
<< 16;
11687 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11688 _("shift value over 3 not allowed in thumb mode"));
11689 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11690 _("only LSL shift allowed in thumb mode"));
11691 encode_thumb32_shifted_operand (2);
11696 constraint (inst
.instruction
== T_MNEM_adds
11697 || inst
.instruction
== T_MNEM_subs
,
11700 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11702 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11703 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11706 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11707 ? 0x0000 : 0x8000);
11708 inst
.instruction
|= (Rd
<< 4) | Rs
;
11709 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11713 Rn
= inst
.operands
[2].reg
;
11714 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11716 /* We now have Rd, Rs, and Rn set to registers. */
11717 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11719 /* Can't do this for SUB. */
11720 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11721 inst
.instruction
= T_OPCODE_ADD_HI
;
11722 inst
.instruction
|= (Rd
& 8) << 4;
11723 inst
.instruction
|= (Rd
& 7);
11725 inst
.instruction
|= Rn
<< 3;
11727 inst
.instruction
|= Rs
<< 3;
11729 constraint (1, _("dest must overlap one source register"));
11733 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11734 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11735 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11745 Rd
= inst
.operands
[0].reg
;
11746 reject_bad_reg (Rd
);
11748 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11750 /* Defer to section relaxation. */
11751 inst
.relax
= inst
.instruction
;
11752 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11753 inst
.instruction
|= Rd
<< 4;
11755 else if (unified_syntax
&& inst
.size_req
!= 2)
11757 /* Generate a 32-bit opcode. */
11758 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11759 inst
.instruction
|= Rd
<< 8;
11760 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11761 inst
.relocs
[0].pc_rel
= 1;
11765 /* Generate a 16-bit opcode. */
11766 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11767 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11768 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11769 inst
.relocs
[0].pc_rel
= 1;
11770 inst
.instruction
|= Rd
<< 4;
11773 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11774 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11775 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11776 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11777 inst
.relocs
[0].exp
.X_add_number
+= 1;
11780 /* Arithmetic instructions for which there is just one 16-bit
11781 instruction encoding, and it allows only two low registers.
11782 For maximal compatibility with ARM syntax, we allow three register
11783 operands even when Thumb-32 instructions are not available, as long
11784 as the first two are identical. For instance, both "sbc r0,r1" and
11785 "sbc r0,r0,r1" are allowed. */
11791 Rd
= inst
.operands
[0].reg
;
11792 Rs
= (inst
.operands
[1].present
11793 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11794 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11795 Rn
= inst
.operands
[2].reg
;
11797 reject_bad_reg (Rd
);
11798 reject_bad_reg (Rs
);
11799 if (inst
.operands
[2].isreg
)
11800 reject_bad_reg (Rn
);
11802 if (unified_syntax
)
11804 if (!inst
.operands
[2].isreg
)
11806 /* For an immediate, we always generate a 32-bit opcode;
11807 section relaxation will shrink it later if possible. */
11808 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11809 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11810 inst
.instruction
|= Rd
<< 8;
11811 inst
.instruction
|= Rs
<< 16;
11812 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11816 bfd_boolean narrow
;
11818 /* See if we can do this with a 16-bit instruction. */
11819 if (THUMB_SETS_FLAGS (inst
.instruction
))
11820 narrow
= !in_pred_block ();
11822 narrow
= in_pred_block ();
11824 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11826 if (inst
.operands
[2].shifted
)
11828 if (inst
.size_req
== 4)
11834 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11835 inst
.instruction
|= Rd
;
11836 inst
.instruction
|= Rn
<< 3;
11840 /* If we get here, it can't be done in 16 bits. */
11841 constraint (inst
.operands
[2].shifted
11842 && inst
.operands
[2].immisreg
,
11843 _("shift must be constant"));
11844 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11845 inst
.instruction
|= Rd
<< 8;
11846 inst
.instruction
|= Rs
<< 16;
11847 encode_thumb32_shifted_operand (2);
11852 /* On its face this is a lie - the instruction does set the
11853 flags. However, the only supported mnemonic in this mode
11854 says it doesn't. */
11855 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11857 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11858 _("unshifted register required"));
11859 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11860 constraint (Rd
!= Rs
,
11861 _("dest and source1 must be the same register"));
11863 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11864 inst
.instruction
|= Rd
;
11865 inst
.instruction
|= Rn
<< 3;
11869 /* Similarly, but for instructions where the arithmetic operation is
11870 commutative, so we can allow either of them to be different from
11871 the destination operand in a 16-bit instruction. For instance, all
11872 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11879 Rd
= inst
.operands
[0].reg
;
11880 Rs
= (inst
.operands
[1].present
11881 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11882 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11883 Rn
= inst
.operands
[2].reg
;
11885 reject_bad_reg (Rd
);
11886 reject_bad_reg (Rs
);
11887 if (inst
.operands
[2].isreg
)
11888 reject_bad_reg (Rn
);
11890 if (unified_syntax
)
11892 if (!inst
.operands
[2].isreg
)
11894 /* For an immediate, we always generate a 32-bit opcode;
11895 section relaxation will shrink it later if possible. */
11896 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11897 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11898 inst
.instruction
|= Rd
<< 8;
11899 inst
.instruction
|= Rs
<< 16;
11900 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11904 bfd_boolean narrow
;
11906 /* See if we can do this with a 16-bit instruction. */
11907 if (THUMB_SETS_FLAGS (inst
.instruction
))
11908 narrow
= !in_pred_block ();
11910 narrow
= in_pred_block ();
11912 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11914 if (inst
.operands
[2].shifted
)
11916 if (inst
.size_req
== 4)
11923 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11924 inst
.instruction
|= Rd
;
11925 inst
.instruction
|= Rn
<< 3;
11930 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11931 inst
.instruction
|= Rd
;
11932 inst
.instruction
|= Rs
<< 3;
11937 /* If we get here, it can't be done in 16 bits. */
11938 constraint (inst
.operands
[2].shifted
11939 && inst
.operands
[2].immisreg
,
11940 _("shift must be constant"));
11941 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11942 inst
.instruction
|= Rd
<< 8;
11943 inst
.instruction
|= Rs
<< 16;
11944 encode_thumb32_shifted_operand (2);
11949 /* On its face this is a lie - the instruction does set the
11950 flags. However, the only supported mnemonic in this mode
11951 says it doesn't. */
11952 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11954 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11955 _("unshifted register required"));
11956 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11958 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11959 inst
.instruction
|= Rd
;
11962 inst
.instruction
|= Rn
<< 3;
11964 inst
.instruction
|= Rs
<< 3;
11966 constraint (1, _("dest must overlap one source register"));
11974 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11975 constraint (msb
> 32, _("bit-field extends past end of register"));
11976 /* The instruction encoding stores the LSB and MSB,
11977 not the LSB and width. */
11978 Rd
= inst
.operands
[0].reg
;
11979 reject_bad_reg (Rd
);
11980 inst
.instruction
|= Rd
<< 8;
11981 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11982 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11983 inst
.instruction
|= msb
- 1;
11992 Rd
= inst
.operands
[0].reg
;
11993 reject_bad_reg (Rd
);
11995 /* #0 in second position is alternative syntax for bfc, which is
11996 the same instruction but with REG_PC in the Rm field. */
11997 if (!inst
.operands
[1].isreg
)
12001 Rn
= inst
.operands
[1].reg
;
12002 reject_bad_reg (Rn
);
12005 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
12006 constraint (msb
> 32, _("bit-field extends past end of register"));
12007 /* The instruction encoding stores the LSB and MSB,
12008 not the LSB and width. */
12009 inst
.instruction
|= Rd
<< 8;
12010 inst
.instruction
|= Rn
<< 16;
12011 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12012 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12013 inst
.instruction
|= msb
- 1;
12021 Rd
= inst
.operands
[0].reg
;
12022 Rn
= inst
.operands
[1].reg
;
12024 reject_bad_reg (Rd
);
12025 reject_bad_reg (Rn
);
12027 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
12028 _("bit-field extends past end of register"));
12029 inst
.instruction
|= Rd
<< 8;
12030 inst
.instruction
|= Rn
<< 16;
12031 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12032 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12033 inst
.instruction
|= inst
.operands
[3].imm
- 1;
12036 /* ARM V5 Thumb BLX (argument parse)
12037 BLX <target_addr> which is BLX(1)
12038 BLX <Rm> which is BLX(2)
12039 Unfortunately, there are two different opcodes for this mnemonic.
12040 So, the insns[].value is not used, and the code here zaps values
12041 into inst.instruction.
12043 ??? How to take advantage of the additional two bits of displacement
12044 available in Thumb32 mode? Need new relocation? */
12049 set_pred_insn_type_last ();
12051 if (inst
.operands
[0].isreg
)
12053 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
12054 /* We have a register, so this is BLX(2). */
12055 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12059 /* No register. This must be BLX(1). */
12060 inst
.instruction
= 0xf000e800;
12061 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
12070 bfd_reloc_code_real_type reloc
;
12073 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
12075 if (in_pred_block ())
12077 /* Conditional branches inside IT blocks are encoded as unconditional
12079 cond
= COND_ALWAYS
;
12084 if (cond
!= COND_ALWAYS
)
12085 opcode
= T_MNEM_bcond
;
12087 opcode
= inst
.instruction
;
12090 && (inst
.size_req
== 4
12091 || (inst
.size_req
!= 2
12092 && (inst
.operands
[0].hasreloc
12093 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12095 inst
.instruction
= THUMB_OP32(opcode
);
12096 if (cond
== COND_ALWAYS
)
12097 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12100 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12101 _("selected architecture does not support "
12102 "wide conditional branch instruction"));
12104 gas_assert (cond
!= 0xF);
12105 inst
.instruction
|= cond
<< 22;
12106 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12111 inst
.instruction
= THUMB_OP16(opcode
);
12112 if (cond
== COND_ALWAYS
)
12113 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12116 inst
.instruction
|= cond
<< 8;
12117 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12119 /* Allow section relaxation. */
12120 if (unified_syntax
&& inst
.size_req
!= 2)
12121 inst
.relax
= opcode
;
12123 inst
.relocs
[0].type
= reloc
;
12124 inst
.relocs
[0].pc_rel
= 1;
12127 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12128 between the two is the maximum immediate allowed - which is passed in
12131 do_t_bkpt_hlt1 (int range
)
12133 constraint (inst
.cond
!= COND_ALWAYS
,
12134 _("instruction is always unconditional"));
12135 if (inst
.operands
[0].present
)
12137 constraint (inst
.operands
[0].imm
> range
,
12138 _("immediate value out of range"));
12139 inst
.instruction
|= inst
.operands
[0].imm
;
12142 set_pred_insn_type (NEUTRAL_IT_INSN
);
12148 do_t_bkpt_hlt1 (63);
12154 do_t_bkpt_hlt1 (255);
12158 do_t_branch23 (void)
12160 set_pred_insn_type_last ();
12161 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12163 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12164 this file. We used to simply ignore the PLT reloc type here --
12165 the branch encoding is now needed to deal with TLSCALL relocs.
12166 So if we see a PLT reloc now, put it back to how it used to be to
12167 keep the preexisting behaviour. */
12168 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12169 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12171 #if defined(OBJ_COFF)
12172 /* If the destination of the branch is a defined symbol which does not have
12173 the THUMB_FUNC attribute, then we must be calling a function which has
12174 the (interfacearm) attribute. We look for the Thumb entry point to that
12175 function and change the branch to refer to that function instead. */
12176 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12177 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12178 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12179 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12180 inst
.relocs
[0].exp
.X_add_symbol
12181 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12188 set_pred_insn_type_last ();
12189 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12190 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12191 should cause the alignment to be checked once it is known. This is
12192 because BX PC only works if the instruction is word aligned. */
12200 set_pred_insn_type_last ();
12201 Rm
= inst
.operands
[0].reg
;
12202 reject_bad_reg (Rm
);
12203 inst
.instruction
|= Rm
<< 16;
12212 Rd
= inst
.operands
[0].reg
;
12213 Rm
= inst
.operands
[1].reg
;
12215 reject_bad_reg (Rd
);
12216 reject_bad_reg (Rm
);
12218 inst
.instruction
|= Rd
<< 8;
12219 inst
.instruction
|= Rm
<< 16;
12220 inst
.instruction
|= Rm
;
12223 /* For the Armv8.1-M conditional instructions. */
12227 unsigned Rd
, Rn
, Rm
;
12230 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12232 Rd
= inst
.operands
[0].reg
;
12233 switch (inst
.instruction
)
12239 Rn
= inst
.operands
[1].reg
;
12240 Rm
= inst
.operands
[2].reg
;
12241 cond
= inst
.operands
[3].imm
;
12242 constraint (Rn
== REG_SP
, BAD_SP
);
12243 constraint (Rm
== REG_SP
, BAD_SP
);
12249 Rn
= inst
.operands
[1].reg
;
12250 cond
= inst
.operands
[2].imm
;
12251 /* Invert the last bit to invert the cond. */
12252 cond
= TOGGLE_BIT (cond
, 0);
12253 constraint (Rn
== REG_SP
, BAD_SP
);
12259 cond
= inst
.operands
[1].imm
;
12260 /* Invert the last bit to invert the cond. */
12261 cond
= TOGGLE_BIT (cond
, 0);
12269 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12270 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12271 inst
.instruction
|= Rd
<< 8;
12272 inst
.instruction
|= Rn
<< 16;
12273 inst
.instruction
|= Rm
;
12274 inst
.instruction
|= cond
<< 4;
12280 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12286 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12287 inst
.instruction
|= inst
.operands
[0].imm
;
12293 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12295 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12296 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12298 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12299 inst
.instruction
= 0xf3af8000;
12300 inst
.instruction
|= imod
<< 9;
12301 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12302 if (inst
.operands
[1].present
)
12303 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12307 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12308 && (inst
.operands
[0].imm
& 4),
12309 _("selected processor does not support 'A' form "
12310 "of this instruction"));
12311 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12312 _("Thumb does not support the 2-argument "
12313 "form of this instruction"));
12314 inst
.instruction
|= inst
.operands
[0].imm
;
12318 /* THUMB CPY instruction (argument parse). */
12323 if (inst
.size_req
== 4)
12325 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12326 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12327 inst
.instruction
|= inst
.operands
[1].reg
;
12331 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12332 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12333 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12340 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12341 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12342 inst
.instruction
|= inst
.operands
[0].reg
;
12343 inst
.relocs
[0].pc_rel
= 1;
12344 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12350 inst
.instruction
|= inst
.operands
[0].imm
;
12356 unsigned Rd
, Rn
, Rm
;
12358 Rd
= inst
.operands
[0].reg
;
12359 Rn
= (inst
.operands
[1].present
12360 ? inst
.operands
[1].reg
: Rd
);
12361 Rm
= inst
.operands
[2].reg
;
12363 reject_bad_reg (Rd
);
12364 reject_bad_reg (Rn
);
12365 reject_bad_reg (Rm
);
12367 inst
.instruction
|= Rd
<< 8;
12368 inst
.instruction
|= Rn
<< 16;
12369 inst
.instruction
|= Rm
;
12375 if (unified_syntax
&& inst
.size_req
== 4)
12376 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12378 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12384 unsigned int cond
= inst
.operands
[0].imm
;
12386 set_pred_insn_type (IT_INSN
);
12387 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12388 now_pred
.cc
= cond
;
12389 now_pred
.warn_deprecated
= FALSE
;
12390 now_pred
.type
= SCALAR_PRED
;
12392 /* If the condition is a negative condition, invert the mask. */
12393 if ((cond
& 0x1) == 0x0)
12395 unsigned int mask
= inst
.instruction
& 0x000f;
12397 if ((mask
& 0x7) == 0)
12399 /* No conversion needed. */
12400 now_pred
.block_length
= 1;
12402 else if ((mask
& 0x3) == 0)
12405 now_pred
.block_length
= 2;
12407 else if ((mask
& 0x1) == 0)
12410 now_pred
.block_length
= 3;
12415 now_pred
.block_length
= 4;
12418 inst
.instruction
&= 0xfff0;
12419 inst
.instruction
|= mask
;
12422 inst
.instruction
|= cond
<< 4;
12425 /* Helper function used for both push/pop and ldm/stm. */
12427 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12428 bfd_boolean writeback
)
12430 bfd_boolean load
, store
;
12432 gas_assert (base
!= -1 || !do_io
);
12433 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12434 store
= do_io
&& !load
;
12436 if (mask
& (1 << 13))
12437 inst
.error
= _("SP not allowed in register list");
12439 if (do_io
&& (mask
& (1 << base
)) != 0
12441 inst
.error
= _("having the base register in the register list when "
12442 "using write back is UNPREDICTABLE");
12446 if (mask
& (1 << 15))
12448 if (mask
& (1 << 14))
12449 inst
.error
= _("LR and PC should not both be in register list");
12451 set_pred_insn_type_last ();
12456 if (mask
& (1 << 15))
12457 inst
.error
= _("PC not allowed in register list");
12460 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12462 /* Single register transfers implemented as str/ldr. */
12465 if (inst
.instruction
& (1 << 23))
12466 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12468 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12472 if (inst
.instruction
& (1 << 23))
12473 inst
.instruction
= 0x00800000; /* ia -> [base] */
12475 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12478 inst
.instruction
|= 0xf8400000;
12480 inst
.instruction
|= 0x00100000;
12482 mask
= ffs (mask
) - 1;
12485 else if (writeback
)
12486 inst
.instruction
|= WRITE_BACK
;
12488 inst
.instruction
|= mask
;
12490 inst
.instruction
|= base
<< 16;
12496 /* This really doesn't seem worth it. */
12497 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12498 _("expression too complex"));
12499 constraint (inst
.operands
[1].writeback
,
12500 _("Thumb load/store multiple does not support {reglist}^"));
12502 if (unified_syntax
)
12504 bfd_boolean narrow
;
12508 /* See if we can use a 16-bit instruction. */
12509 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12510 && inst
.size_req
!= 4
12511 && !(inst
.operands
[1].imm
& ~0xff))
12513 mask
= 1 << inst
.operands
[0].reg
;
12515 if (inst
.operands
[0].reg
<= 7)
12517 if (inst
.instruction
== T_MNEM_stmia
12518 ? inst
.operands
[0].writeback
12519 : (inst
.operands
[0].writeback
12520 == !(inst
.operands
[1].imm
& mask
)))
12522 if (inst
.instruction
== T_MNEM_stmia
12523 && (inst
.operands
[1].imm
& mask
)
12524 && (inst
.operands
[1].imm
& (mask
- 1)))
12525 as_warn (_("value stored for r%d is UNKNOWN"),
12526 inst
.operands
[0].reg
);
12528 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12529 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12530 inst
.instruction
|= inst
.operands
[1].imm
;
12533 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12535 /* This means 1 register in reg list one of 3 situations:
12536 1. Instruction is stmia, but without writeback.
12537 2. lmdia without writeback, but with Rn not in
12539 3. ldmia with writeback, but with Rn in reglist.
12540 Case 3 is UNPREDICTABLE behaviour, so we handle
12541 case 1 and 2 which can be converted into a 16-bit
12542 str or ldr. The SP cases are handled below. */
12543 unsigned long opcode
;
12544 /* First, record an error for Case 3. */
12545 if (inst
.operands
[1].imm
& mask
12546 && inst
.operands
[0].writeback
)
12548 _("having the base register in the register list when "
12549 "using write back is UNPREDICTABLE");
12551 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12553 inst
.instruction
= THUMB_OP16 (opcode
);
12554 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12555 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12559 else if (inst
.operands
[0] .reg
== REG_SP
)
12561 if (inst
.operands
[0].writeback
)
12564 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12565 ? T_MNEM_push
: T_MNEM_pop
);
12566 inst
.instruction
|= inst
.operands
[1].imm
;
12569 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12572 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12573 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12574 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12582 if (inst
.instruction
< 0xffff)
12583 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12585 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12586 inst
.operands
[1].imm
,
12587 inst
.operands
[0].writeback
);
12592 constraint (inst
.operands
[0].reg
> 7
12593 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12594 constraint (inst
.instruction
!= T_MNEM_ldmia
12595 && inst
.instruction
!= T_MNEM_stmia
,
12596 _("Thumb-2 instruction only valid in unified syntax"));
12597 if (inst
.instruction
== T_MNEM_stmia
)
12599 if (!inst
.operands
[0].writeback
)
12600 as_warn (_("this instruction will write back the base register"));
12601 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12602 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12603 as_warn (_("value stored for r%d is UNKNOWN"),
12604 inst
.operands
[0].reg
);
12608 if (!inst
.operands
[0].writeback
12609 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12610 as_warn (_("this instruction will write back the base register"));
12611 else if (inst
.operands
[0].writeback
12612 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12613 as_warn (_("this instruction will not write back the base register"));
12616 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12617 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12618 inst
.instruction
|= inst
.operands
[1].imm
;
12625 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12626 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12627 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12628 || inst
.operands
[1].negative
,
12631 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12633 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12634 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12635 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12641 if (!inst
.operands
[1].present
)
12643 constraint (inst
.operands
[0].reg
== REG_LR
,
12644 _("r14 not allowed as first register "
12645 "when second register is omitted"));
12646 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12648 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12651 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12652 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12653 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12659 unsigned long opcode
;
12662 if (inst
.operands
[0].isreg
12663 && !inst
.operands
[0].preind
12664 && inst
.operands
[0].reg
== REG_PC
)
12665 set_pred_insn_type_last ();
12667 opcode
= inst
.instruction
;
12668 if (unified_syntax
)
12670 if (!inst
.operands
[1].isreg
)
12672 if (opcode
<= 0xffff)
12673 inst
.instruction
= THUMB_OP32 (opcode
);
12674 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12677 if (inst
.operands
[1].isreg
12678 && !inst
.operands
[1].writeback
12679 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12680 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12681 && opcode
<= 0xffff
12682 && inst
.size_req
!= 4)
12684 /* Insn may have a 16-bit form. */
12685 Rn
= inst
.operands
[1].reg
;
12686 if (inst
.operands
[1].immisreg
)
12688 inst
.instruction
= THUMB_OP16 (opcode
);
12690 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12692 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12693 reject_bad_reg (inst
.operands
[1].imm
);
12695 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12696 && opcode
!= T_MNEM_ldrsb
)
12697 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12698 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12705 if (inst
.relocs
[0].pc_rel
)
12706 opcode
= T_MNEM_ldr_pc2
;
12708 opcode
= T_MNEM_ldr_pc
;
12712 if (opcode
== T_MNEM_ldr
)
12713 opcode
= T_MNEM_ldr_sp
;
12715 opcode
= T_MNEM_str_sp
;
12717 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12721 inst
.instruction
= inst
.operands
[0].reg
;
12722 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12724 inst
.instruction
|= THUMB_OP16 (opcode
);
12725 if (inst
.size_req
== 2)
12726 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12728 inst
.relax
= opcode
;
12732 /* Definitely a 32-bit variant. */
12734 /* Warning for Erratum 752419. */
12735 if (opcode
== T_MNEM_ldr
12736 && inst
.operands
[0].reg
== REG_SP
12737 && inst
.operands
[1].writeback
== 1
12738 && !inst
.operands
[1].immisreg
)
12740 if (no_cpu_selected ()
12741 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12742 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12743 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12744 as_warn (_("This instruction may be unpredictable "
12745 "if executed on M-profile cores "
12746 "with interrupts enabled."));
12749 /* Do some validations regarding addressing modes. */
12750 if (inst
.operands
[1].immisreg
)
12751 reject_bad_reg (inst
.operands
[1].imm
);
12753 constraint (inst
.operands
[1].writeback
== 1
12754 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12757 inst
.instruction
= THUMB_OP32 (opcode
);
12758 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12759 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12760 check_ldr_r15_aligned ();
12764 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12766 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12768 /* Only [Rn,Rm] is acceptable. */
12769 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12770 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12771 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12772 || inst
.operands
[1].negative
,
12773 _("Thumb does not support this addressing mode"));
12774 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12778 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12779 if (!inst
.operands
[1].isreg
)
12780 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12783 constraint (!inst
.operands
[1].preind
12784 || inst
.operands
[1].shifted
12785 || inst
.operands
[1].writeback
,
12786 _("Thumb does not support this addressing mode"));
12787 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12789 constraint (inst
.instruction
& 0x0600,
12790 _("byte or halfword not valid for base register"));
12791 constraint (inst
.operands
[1].reg
== REG_PC
12792 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12793 _("r15 based store not allowed"));
12794 constraint (inst
.operands
[1].immisreg
,
12795 _("invalid base register for register offset"));
12797 if (inst
.operands
[1].reg
== REG_PC
)
12798 inst
.instruction
= T_OPCODE_LDR_PC
;
12799 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12800 inst
.instruction
= T_OPCODE_LDR_SP
;
12802 inst
.instruction
= T_OPCODE_STR_SP
;
12804 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12805 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12809 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12810 if (!inst
.operands
[1].immisreg
)
12812 /* Immediate offset. */
12813 inst
.instruction
|= inst
.operands
[0].reg
;
12814 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12815 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12819 /* Register offset. */
12820 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12821 constraint (inst
.operands
[1].negative
,
12822 _("Thumb does not support this addressing mode"));
12825 switch (inst
.instruction
)
12827 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12828 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12829 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12830 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12831 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12832 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12833 case 0x5600 /* ldrsb */:
12834 case 0x5e00 /* ldrsh */: break;
12838 inst
.instruction
|= inst
.operands
[0].reg
;
12839 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12840 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12846 if (!inst
.operands
[1].present
)
12848 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12849 constraint (inst
.operands
[0].reg
== REG_LR
,
12850 _("r14 not allowed here"));
12851 constraint (inst
.operands
[0].reg
== REG_R12
,
12852 _("r12 not allowed here"));
12855 if (inst
.operands
[2].writeback
12856 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12857 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12858 as_warn (_("base register written back, and overlaps "
12859 "one of transfer registers"));
12861 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12862 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12863 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12869 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12870 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12876 unsigned Rd
, Rn
, Rm
, Ra
;
12878 Rd
= inst
.operands
[0].reg
;
12879 Rn
= inst
.operands
[1].reg
;
12880 Rm
= inst
.operands
[2].reg
;
12881 Ra
= inst
.operands
[3].reg
;
12883 reject_bad_reg (Rd
);
12884 reject_bad_reg (Rn
);
12885 reject_bad_reg (Rm
);
12886 reject_bad_reg (Ra
);
12888 inst
.instruction
|= Rd
<< 8;
12889 inst
.instruction
|= Rn
<< 16;
12890 inst
.instruction
|= Rm
;
12891 inst
.instruction
|= Ra
<< 12;
12897 unsigned RdLo
, RdHi
, Rn
, Rm
;
12899 RdLo
= inst
.operands
[0].reg
;
12900 RdHi
= inst
.operands
[1].reg
;
12901 Rn
= inst
.operands
[2].reg
;
12902 Rm
= inst
.operands
[3].reg
;
12904 reject_bad_reg (RdLo
);
12905 reject_bad_reg (RdHi
);
12906 reject_bad_reg (Rn
);
12907 reject_bad_reg (Rm
);
12909 inst
.instruction
|= RdLo
<< 12;
12910 inst
.instruction
|= RdHi
<< 8;
12911 inst
.instruction
|= Rn
<< 16;
12912 inst
.instruction
|= Rm
;
12916 do_t_mov_cmp (void)
12920 Rn
= inst
.operands
[0].reg
;
12921 Rm
= inst
.operands
[1].reg
;
12924 set_pred_insn_type_last ();
12926 if (unified_syntax
)
12928 int r0off
= (inst
.instruction
== T_MNEM_mov
12929 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12930 unsigned long opcode
;
12931 bfd_boolean narrow
;
12932 bfd_boolean low_regs
;
12934 low_regs
= (Rn
<= 7 && Rm
<= 7);
12935 opcode
= inst
.instruction
;
12936 if (in_pred_block ())
12937 narrow
= opcode
!= T_MNEM_movs
;
12939 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12940 if (inst
.size_req
== 4
12941 || inst
.operands
[1].shifted
)
12944 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12945 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12946 && !inst
.operands
[1].shifted
12950 inst
.instruction
= T2_SUBS_PC_LR
;
12954 if (opcode
== T_MNEM_cmp
)
12956 constraint (Rn
== REG_PC
, BAD_PC
);
12959 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12961 warn_deprecated_sp (Rm
);
12962 /* R15 was documented as a valid choice for Rm in ARMv6,
12963 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12964 tools reject R15, so we do too. */
12965 constraint (Rm
== REG_PC
, BAD_PC
);
12968 reject_bad_reg (Rm
);
12970 else if (opcode
== T_MNEM_mov
12971 || opcode
== T_MNEM_movs
)
12973 if (inst
.operands
[1].isreg
)
12975 if (opcode
== T_MNEM_movs
)
12977 reject_bad_reg (Rn
);
12978 reject_bad_reg (Rm
);
12982 /* This is mov.n. */
12983 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12984 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12986 as_tsktsk (_("Use of r%u as a source register is "
12987 "deprecated when r%u is the destination "
12988 "register."), Rm
, Rn
);
12993 /* This is mov.w. */
12994 constraint (Rn
== REG_PC
, BAD_PC
);
12995 constraint (Rm
== REG_PC
, BAD_PC
);
12996 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12997 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
13001 reject_bad_reg (Rn
);
13004 if (!inst
.operands
[1].isreg
)
13006 /* Immediate operand. */
13007 if (!in_pred_block () && opcode
== T_MNEM_mov
)
13009 if (low_regs
&& narrow
)
13011 inst
.instruction
= THUMB_OP16 (opcode
);
13012 inst
.instruction
|= Rn
<< 8;
13013 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
13014 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
13016 if (inst
.size_req
== 2)
13017 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13019 inst
.relax
= opcode
;
13024 constraint ((inst
.relocs
[0].type
13025 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
13026 && (inst
.relocs
[0].type
13027 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
13028 THUMB1_RELOC_ONLY
);
13030 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13031 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13032 inst
.instruction
|= Rn
<< r0off
;
13033 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13036 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
13037 && (inst
.instruction
== T_MNEM_mov
13038 || inst
.instruction
== T_MNEM_movs
))
13040 /* Register shifts are encoded as separate shift instructions. */
13041 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
13043 if (in_pred_block ())
13048 if (inst
.size_req
== 4)
13051 if (!low_regs
|| inst
.operands
[1].imm
> 7)
13057 switch (inst
.operands
[1].shift_kind
)
13060 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
13063 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
13066 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
13069 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
13075 inst
.instruction
= opcode
;
13078 inst
.instruction
|= Rn
;
13079 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13084 inst
.instruction
|= CONDS_BIT
;
13086 inst
.instruction
|= Rn
<< 8;
13087 inst
.instruction
|= Rm
<< 16;
13088 inst
.instruction
|= inst
.operands
[1].imm
;
13093 /* Some mov with immediate shift have narrow variants.
13094 Register shifts are handled above. */
13095 if (low_regs
&& inst
.operands
[1].shifted
13096 && (inst
.instruction
== T_MNEM_mov
13097 || inst
.instruction
== T_MNEM_movs
))
13099 if (in_pred_block ())
13100 narrow
= (inst
.instruction
== T_MNEM_mov
);
13102 narrow
= (inst
.instruction
== T_MNEM_movs
);
13107 switch (inst
.operands
[1].shift_kind
)
13109 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13110 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13111 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13112 default: narrow
= FALSE
; break;
13118 inst
.instruction
|= Rn
;
13119 inst
.instruction
|= Rm
<< 3;
13120 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13124 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13125 inst
.instruction
|= Rn
<< r0off
;
13126 encode_thumb32_shifted_operand (1);
13130 switch (inst
.instruction
)
13133 /* In v4t or v5t a move of two lowregs produces unpredictable
13134 results. Don't allow this. */
13137 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13138 "MOV Rd, Rs with two low registers is not "
13139 "permitted on this architecture");
13140 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13144 inst
.instruction
= T_OPCODE_MOV_HR
;
13145 inst
.instruction
|= (Rn
& 0x8) << 4;
13146 inst
.instruction
|= (Rn
& 0x7);
13147 inst
.instruction
|= Rm
<< 3;
13151 /* We know we have low registers at this point.
13152 Generate LSLS Rd, Rs, #0. */
13153 inst
.instruction
= T_OPCODE_LSL_I
;
13154 inst
.instruction
|= Rn
;
13155 inst
.instruction
|= Rm
<< 3;
13161 inst
.instruction
= T_OPCODE_CMP_LR
;
13162 inst
.instruction
|= Rn
;
13163 inst
.instruction
|= Rm
<< 3;
13167 inst
.instruction
= T_OPCODE_CMP_HR
;
13168 inst
.instruction
|= (Rn
& 0x8) << 4;
13169 inst
.instruction
|= (Rn
& 0x7);
13170 inst
.instruction
|= Rm
<< 3;
13177 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13179 /* PR 10443: Do not silently ignore shifted operands. */
13180 constraint (inst
.operands
[1].shifted
,
13181 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13183 if (inst
.operands
[1].isreg
)
13185 if (Rn
< 8 && Rm
< 8)
13187 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13188 since a MOV instruction produces unpredictable results. */
13189 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13190 inst
.instruction
= T_OPCODE_ADD_I3
;
13192 inst
.instruction
= T_OPCODE_CMP_LR
;
13194 inst
.instruction
|= Rn
;
13195 inst
.instruction
|= Rm
<< 3;
13199 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13200 inst
.instruction
= T_OPCODE_MOV_HR
;
13202 inst
.instruction
= T_OPCODE_CMP_HR
;
13208 constraint (Rn
> 7,
13209 _("only lo regs allowed with immediate"));
13210 inst
.instruction
|= Rn
<< 8;
13211 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13222 top
= (inst
.instruction
& 0x00800000) != 0;
13223 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13225 constraint (top
, _(":lower16: not allowed in this instruction"));
13226 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13228 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13230 constraint (!top
, _(":upper16: not allowed in this instruction"));
13231 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13234 Rd
= inst
.operands
[0].reg
;
13235 reject_bad_reg (Rd
);
13237 inst
.instruction
|= Rd
<< 8;
13238 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13240 imm
= inst
.relocs
[0].exp
.X_add_number
;
13241 inst
.instruction
|= (imm
& 0xf000) << 4;
13242 inst
.instruction
|= (imm
& 0x0800) << 15;
13243 inst
.instruction
|= (imm
& 0x0700) << 4;
13244 inst
.instruction
|= (imm
& 0x00ff);
13249 do_t_mvn_tst (void)
13253 Rn
= inst
.operands
[0].reg
;
13254 Rm
= inst
.operands
[1].reg
;
13256 if (inst
.instruction
== T_MNEM_cmp
13257 || inst
.instruction
== T_MNEM_cmn
)
13258 constraint (Rn
== REG_PC
, BAD_PC
);
13260 reject_bad_reg (Rn
);
13261 reject_bad_reg (Rm
);
13263 if (unified_syntax
)
13265 int r0off
= (inst
.instruction
== T_MNEM_mvn
13266 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13267 bfd_boolean narrow
;
13269 if (inst
.size_req
== 4
13270 || inst
.instruction
> 0xffff
13271 || inst
.operands
[1].shifted
13272 || Rn
> 7 || Rm
> 7)
13274 else if (inst
.instruction
== T_MNEM_cmn
13275 || inst
.instruction
== T_MNEM_tst
)
13277 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13278 narrow
= !in_pred_block ();
13280 narrow
= in_pred_block ();
13282 if (!inst
.operands
[1].isreg
)
13284 /* For an immediate, we always generate a 32-bit opcode;
13285 section relaxation will shrink it later if possible. */
13286 if (inst
.instruction
< 0xffff)
13287 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13288 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13289 inst
.instruction
|= Rn
<< r0off
;
13290 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13294 /* See if we can do this with a 16-bit instruction. */
13297 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13298 inst
.instruction
|= Rn
;
13299 inst
.instruction
|= Rm
<< 3;
13303 constraint (inst
.operands
[1].shifted
13304 && inst
.operands
[1].immisreg
,
13305 _("shift must be constant"));
13306 if (inst
.instruction
< 0xffff)
13307 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13308 inst
.instruction
|= Rn
<< r0off
;
13309 encode_thumb32_shifted_operand (1);
13315 constraint (inst
.instruction
> 0xffff
13316 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13317 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13318 _("unshifted register required"));
13319 constraint (Rn
> 7 || Rm
> 7,
13322 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13323 inst
.instruction
|= Rn
;
13324 inst
.instruction
|= Rm
<< 3;
13333 if (do_vfp_nsyn_mrs () == SUCCESS
)
13336 Rd
= inst
.operands
[0].reg
;
13337 reject_bad_reg (Rd
);
13338 inst
.instruction
|= Rd
<< 8;
13340 if (inst
.operands
[1].isreg
)
13342 unsigned br
= inst
.operands
[1].reg
;
13343 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13344 as_bad (_("bad register for mrs"));
13346 inst
.instruction
|= br
& (0xf << 16);
13347 inst
.instruction
|= (br
& 0x300) >> 4;
13348 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13352 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13354 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13356 /* PR gas/12698: The constraint is only applied for m_profile.
13357 If the user has specified -march=all, we want to ignore it as
13358 we are building for any CPU type, including non-m variants. */
13359 bfd_boolean m_profile
=
13360 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13361 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13362 "not support requested special purpose register"));
13365 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13367 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13368 _("'APSR', 'CPSR' or 'SPSR' expected"));
13370 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13371 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13372 inst
.instruction
|= 0xf0000;
13382 if (do_vfp_nsyn_msr () == SUCCESS
)
13385 constraint (!inst
.operands
[1].isreg
,
13386 _("Thumb encoding does not support an immediate here"));
13388 if (inst
.operands
[0].isreg
)
13389 flags
= (int)(inst
.operands
[0].reg
);
13391 flags
= inst
.operands
[0].imm
;
13393 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13395 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13397 /* PR gas/12698: The constraint is only applied for m_profile.
13398 If the user has specified -march=all, we want to ignore it as
13399 we are building for any CPU type, including non-m variants. */
13400 bfd_boolean m_profile
=
13401 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13402 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13403 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13404 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13405 && bits
!= PSR_f
)) && m_profile
,
13406 _("selected processor does not support requested special "
13407 "purpose register"));
13410 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13411 "requested special purpose register"));
13413 Rn
= inst
.operands
[1].reg
;
13414 reject_bad_reg (Rn
);
13416 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13417 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13418 inst
.instruction
|= (flags
& 0x300) >> 4;
13419 inst
.instruction
|= (flags
& 0xff);
13420 inst
.instruction
|= Rn
<< 16;
13426 bfd_boolean narrow
;
13427 unsigned Rd
, Rn
, Rm
;
13429 if (!inst
.operands
[2].present
)
13430 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13432 Rd
= inst
.operands
[0].reg
;
13433 Rn
= inst
.operands
[1].reg
;
13434 Rm
= inst
.operands
[2].reg
;
13436 if (unified_syntax
)
13438 if (inst
.size_req
== 4
13444 else if (inst
.instruction
== T_MNEM_muls
)
13445 narrow
= !in_pred_block ();
13447 narrow
= in_pred_block ();
13451 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13452 constraint (Rn
> 7 || Rm
> 7,
13459 /* 16-bit MULS/Conditional MUL. */
13460 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13461 inst
.instruction
|= Rd
;
13464 inst
.instruction
|= Rm
<< 3;
13466 inst
.instruction
|= Rn
<< 3;
13468 constraint (1, _("dest must overlap one source register"));
13472 constraint (inst
.instruction
!= T_MNEM_mul
,
13473 _("Thumb-2 MUL must not set flags"));
13475 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13476 inst
.instruction
|= Rd
<< 8;
13477 inst
.instruction
|= Rn
<< 16;
13478 inst
.instruction
|= Rm
<< 0;
13480 reject_bad_reg (Rd
);
13481 reject_bad_reg (Rn
);
13482 reject_bad_reg (Rm
);
13489 unsigned RdLo
, RdHi
, Rn
, Rm
;
13491 RdLo
= inst
.operands
[0].reg
;
13492 RdHi
= inst
.operands
[1].reg
;
13493 Rn
= inst
.operands
[2].reg
;
13494 Rm
= inst
.operands
[3].reg
;
13496 reject_bad_reg (RdLo
);
13497 reject_bad_reg (RdHi
);
13498 reject_bad_reg (Rn
);
13499 reject_bad_reg (Rm
);
13501 inst
.instruction
|= RdLo
<< 12;
13502 inst
.instruction
|= RdHi
<< 8;
13503 inst
.instruction
|= Rn
<< 16;
13504 inst
.instruction
|= Rm
;
13507 as_tsktsk (_("rdhi and rdlo must be different"));
13513 set_pred_insn_type (NEUTRAL_IT_INSN
);
13515 if (unified_syntax
)
13517 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13519 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13520 inst
.instruction
|= inst
.operands
[0].imm
;
13524 /* PR9722: Check for Thumb2 availability before
13525 generating a thumb2 nop instruction. */
13526 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13528 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13529 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13532 inst
.instruction
= 0x46c0;
13537 constraint (inst
.operands
[0].present
,
13538 _("Thumb does not support NOP with hints"));
13539 inst
.instruction
= 0x46c0;
13546 if (unified_syntax
)
13548 bfd_boolean narrow
;
13550 if (THUMB_SETS_FLAGS (inst
.instruction
))
13551 narrow
= !in_pred_block ();
13553 narrow
= in_pred_block ();
13554 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13556 if (inst
.size_req
== 4)
13561 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13562 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13563 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13567 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13568 inst
.instruction
|= inst
.operands
[0].reg
;
13569 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13574 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13576 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13578 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13579 inst
.instruction
|= inst
.operands
[0].reg
;
13580 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13589 Rd
= inst
.operands
[0].reg
;
13590 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13592 reject_bad_reg (Rd
);
13593 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13594 reject_bad_reg (Rn
);
13596 inst
.instruction
|= Rd
<< 8;
13597 inst
.instruction
|= Rn
<< 16;
13599 if (!inst
.operands
[2].isreg
)
13601 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13602 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13608 Rm
= inst
.operands
[2].reg
;
13609 reject_bad_reg (Rm
);
13611 constraint (inst
.operands
[2].shifted
13612 && inst
.operands
[2].immisreg
,
13613 _("shift must be constant"));
13614 encode_thumb32_shifted_operand (2);
13621 unsigned Rd
, Rn
, Rm
;
13623 Rd
= inst
.operands
[0].reg
;
13624 Rn
= inst
.operands
[1].reg
;
13625 Rm
= inst
.operands
[2].reg
;
13627 reject_bad_reg (Rd
);
13628 reject_bad_reg (Rn
);
13629 reject_bad_reg (Rm
);
13631 inst
.instruction
|= Rd
<< 8;
13632 inst
.instruction
|= Rn
<< 16;
13633 inst
.instruction
|= Rm
;
13634 if (inst
.operands
[3].present
)
13636 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13637 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13638 _("expression too complex"));
13639 inst
.instruction
|= (val
& 0x1c) << 10;
13640 inst
.instruction
|= (val
& 0x03) << 6;
13647 if (!inst
.operands
[3].present
)
13651 inst
.instruction
&= ~0x00000020;
13653 /* PR 10168. Swap the Rm and Rn registers. */
13654 Rtmp
= inst
.operands
[1].reg
;
13655 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13656 inst
.operands
[2].reg
= Rtmp
;
13664 if (inst
.operands
[0].immisreg
)
13665 reject_bad_reg (inst
.operands
[0].imm
);
13667 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13671 do_t_push_pop (void)
13675 constraint (inst
.operands
[0].writeback
,
13676 _("push/pop do not support {reglist}^"));
13677 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13678 _("expression too complex"));
13680 mask
= inst
.operands
[0].imm
;
13681 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13682 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13683 else if (inst
.size_req
!= 4
13684 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13685 ? REG_LR
: REG_PC
)))
13687 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13688 inst
.instruction
|= THUMB_PP_PC_LR
;
13689 inst
.instruction
|= mask
& 0xff;
13691 else if (unified_syntax
)
13693 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13694 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13698 inst
.error
= _("invalid register list to push/pop instruction");
13706 if (unified_syntax
)
13707 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13710 inst
.error
= _("invalid register list to push/pop instruction");
13716 do_t_vscclrm (void)
13718 if (inst
.operands
[0].issingle
)
13720 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13721 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13722 inst
.instruction
|= inst
.operands
[0].imm
;
13726 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13727 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13728 inst
.instruction
|= 1 << 8;
13729 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13738 Rd
= inst
.operands
[0].reg
;
13739 Rm
= inst
.operands
[1].reg
;
13741 reject_bad_reg (Rd
);
13742 reject_bad_reg (Rm
);
13744 inst
.instruction
|= Rd
<< 8;
13745 inst
.instruction
|= Rm
<< 16;
13746 inst
.instruction
|= Rm
;
13754 Rd
= inst
.operands
[0].reg
;
13755 Rm
= inst
.operands
[1].reg
;
13757 reject_bad_reg (Rd
);
13758 reject_bad_reg (Rm
);
13760 if (Rd
<= 7 && Rm
<= 7
13761 && inst
.size_req
!= 4)
13763 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13764 inst
.instruction
|= Rd
;
13765 inst
.instruction
|= Rm
<< 3;
13767 else if (unified_syntax
)
13769 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13770 inst
.instruction
|= Rd
<< 8;
13771 inst
.instruction
|= Rm
<< 16;
13772 inst
.instruction
|= Rm
;
13775 inst
.error
= BAD_HIREG
;
13783 Rd
= inst
.operands
[0].reg
;
13784 Rm
= inst
.operands
[1].reg
;
13786 reject_bad_reg (Rd
);
13787 reject_bad_reg (Rm
);
13789 inst
.instruction
|= Rd
<< 8;
13790 inst
.instruction
|= Rm
;
13798 Rd
= inst
.operands
[0].reg
;
13799 Rs
= (inst
.operands
[1].present
13800 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13801 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13803 reject_bad_reg (Rd
);
13804 reject_bad_reg (Rs
);
13805 if (inst
.operands
[2].isreg
)
13806 reject_bad_reg (inst
.operands
[2].reg
);
13808 inst
.instruction
|= Rd
<< 8;
13809 inst
.instruction
|= Rs
<< 16;
13810 if (!inst
.operands
[2].isreg
)
13812 bfd_boolean narrow
;
13814 if ((inst
.instruction
& 0x00100000) != 0)
13815 narrow
= !in_pred_block ();
13817 narrow
= in_pred_block ();
13819 if (Rd
> 7 || Rs
> 7)
13822 if (inst
.size_req
== 4 || !unified_syntax
)
13825 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13826 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13829 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13830 relaxation, but it doesn't seem worth the hassle. */
13833 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13834 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13835 inst
.instruction
|= Rs
<< 3;
13836 inst
.instruction
|= Rd
;
13840 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13841 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13845 encode_thumb32_shifted_operand (2);
13851 if (warn_on_deprecated
13852 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13853 as_tsktsk (_("setend use is deprecated for ARMv8"));
13855 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13856 if (inst
.operands
[0].imm
)
13857 inst
.instruction
|= 0x8;
13863 if (!inst
.operands
[1].present
)
13864 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13866 if (unified_syntax
)
13868 bfd_boolean narrow
;
13871 switch (inst
.instruction
)
13874 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13876 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13878 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13880 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13884 if (THUMB_SETS_FLAGS (inst
.instruction
))
13885 narrow
= !in_pred_block ();
13887 narrow
= in_pred_block ();
13888 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13890 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13892 if (inst
.operands
[2].isreg
13893 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13894 || inst
.operands
[2].reg
> 7))
13896 if (inst
.size_req
== 4)
13899 reject_bad_reg (inst
.operands
[0].reg
);
13900 reject_bad_reg (inst
.operands
[1].reg
);
13904 if (inst
.operands
[2].isreg
)
13906 reject_bad_reg (inst
.operands
[2].reg
);
13907 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13908 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13909 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13910 inst
.instruction
|= inst
.operands
[2].reg
;
13912 /* PR 12854: Error on extraneous shifts. */
13913 constraint (inst
.operands
[2].shifted
,
13914 _("extraneous shift as part of operand to shift insn"));
13918 inst
.operands
[1].shifted
= 1;
13919 inst
.operands
[1].shift_kind
= shift_kind
;
13920 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13921 ? T_MNEM_movs
: T_MNEM_mov
);
13922 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13923 encode_thumb32_shifted_operand (1);
13924 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13925 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13930 if (inst
.operands
[2].isreg
)
13932 switch (shift_kind
)
13934 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13935 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13936 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13937 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13941 inst
.instruction
|= inst
.operands
[0].reg
;
13942 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13944 /* PR 12854: Error on extraneous shifts. */
13945 constraint (inst
.operands
[2].shifted
,
13946 _("extraneous shift as part of operand to shift insn"));
13950 switch (shift_kind
)
13952 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13953 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13954 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13957 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13958 inst
.instruction
|= inst
.operands
[0].reg
;
13959 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13965 constraint (inst
.operands
[0].reg
> 7
13966 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13967 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13969 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13971 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13972 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13973 _("source1 and dest must be same register"));
13975 switch (inst
.instruction
)
13977 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13978 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13979 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13980 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13984 inst
.instruction
|= inst
.operands
[0].reg
;
13985 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13987 /* PR 12854: Error on extraneous shifts. */
13988 constraint (inst
.operands
[2].shifted
,
13989 _("extraneous shift as part of operand to shift insn"));
13993 switch (inst
.instruction
)
13995 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13996 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13997 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13998 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
14001 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14002 inst
.instruction
|= inst
.operands
[0].reg
;
14003 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14011 unsigned Rd
, Rn
, Rm
;
14013 Rd
= inst
.operands
[0].reg
;
14014 Rn
= inst
.operands
[1].reg
;
14015 Rm
= inst
.operands
[2].reg
;
14017 reject_bad_reg (Rd
);
14018 reject_bad_reg (Rn
);
14019 reject_bad_reg (Rm
);
14021 inst
.instruction
|= Rd
<< 8;
14022 inst
.instruction
|= Rn
<< 16;
14023 inst
.instruction
|= Rm
;
14029 unsigned Rd
, Rn
, Rm
;
14031 Rd
= inst
.operands
[0].reg
;
14032 Rm
= inst
.operands
[1].reg
;
14033 Rn
= inst
.operands
[2].reg
;
14035 reject_bad_reg (Rd
);
14036 reject_bad_reg (Rn
);
14037 reject_bad_reg (Rm
);
14039 inst
.instruction
|= Rd
<< 8;
14040 inst
.instruction
|= Rn
<< 16;
14041 inst
.instruction
|= Rm
;
14047 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14048 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
14049 _("SMC is not permitted on this architecture"));
14050 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14051 _("expression too complex"));
14052 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
14054 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14055 inst
.instruction
|= (value
& 0x000f) << 16;
14057 /* PR gas/15623: SMC instructions must be last in an IT block. */
14058 set_pred_insn_type_last ();
14064 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14066 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14067 inst
.instruction
|= (value
& 0x0fff);
14068 inst
.instruction
|= (value
& 0xf000) << 4;
14072 do_t_ssat_usat (int bias
)
14076 Rd
= inst
.operands
[0].reg
;
14077 Rn
= inst
.operands
[2].reg
;
14079 reject_bad_reg (Rd
);
14080 reject_bad_reg (Rn
);
14082 inst
.instruction
|= Rd
<< 8;
14083 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14084 inst
.instruction
|= Rn
<< 16;
14086 if (inst
.operands
[3].present
)
14088 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14090 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14092 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14093 _("expression too complex"));
14095 if (shift_amount
!= 0)
14097 constraint (shift_amount
> 31,
14098 _("shift expression is too large"));
14100 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14101 inst
.instruction
|= 0x00200000; /* sh bit. */
14103 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14104 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14112 do_t_ssat_usat (1);
14120 Rd
= inst
.operands
[0].reg
;
14121 Rn
= inst
.operands
[2].reg
;
14123 reject_bad_reg (Rd
);
14124 reject_bad_reg (Rn
);
14126 inst
.instruction
|= Rd
<< 8;
14127 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14128 inst
.instruction
|= Rn
<< 16;
14134 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14135 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14136 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14137 || inst
.operands
[2].negative
,
14140 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14142 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14143 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14144 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14145 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14151 if (!inst
.operands
[2].present
)
14152 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14154 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14155 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14156 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14159 inst
.instruction
|= inst
.operands
[0].reg
;
14160 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14161 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14162 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14168 unsigned Rd
, Rn
, Rm
;
14170 Rd
= inst
.operands
[0].reg
;
14171 Rn
= inst
.operands
[1].reg
;
14172 Rm
= inst
.operands
[2].reg
;
14174 reject_bad_reg (Rd
);
14175 reject_bad_reg (Rn
);
14176 reject_bad_reg (Rm
);
14178 inst
.instruction
|= Rd
<< 8;
14179 inst
.instruction
|= Rn
<< 16;
14180 inst
.instruction
|= Rm
;
14181 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14189 Rd
= inst
.operands
[0].reg
;
14190 Rm
= inst
.operands
[1].reg
;
14192 reject_bad_reg (Rd
);
14193 reject_bad_reg (Rm
);
14195 if (inst
.instruction
<= 0xffff
14196 && inst
.size_req
!= 4
14197 && Rd
<= 7 && Rm
<= 7
14198 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14200 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14201 inst
.instruction
|= Rd
;
14202 inst
.instruction
|= Rm
<< 3;
14204 else if (unified_syntax
)
14206 if (inst
.instruction
<= 0xffff)
14207 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14208 inst
.instruction
|= Rd
<< 8;
14209 inst
.instruction
|= Rm
;
14210 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14214 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14215 _("Thumb encoding does not support rotation"));
14216 constraint (1, BAD_HIREG
);
14223 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14232 half
= (inst
.instruction
& 0x10) != 0;
14233 set_pred_insn_type_last ();
14234 constraint (inst
.operands
[0].immisreg
,
14235 _("instruction requires register index"));
14237 Rn
= inst
.operands
[0].reg
;
14238 Rm
= inst
.operands
[0].imm
;
14240 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14241 constraint (Rn
== REG_SP
, BAD_SP
);
14242 reject_bad_reg (Rm
);
14244 constraint (!half
&& inst
.operands
[0].shifted
,
14245 _("instruction does not allow shifted index"));
14246 inst
.instruction
|= (Rn
<< 16) | Rm
;
14252 if (!inst
.operands
[0].present
)
14253 inst
.operands
[0].imm
= 0;
14255 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14257 constraint (inst
.size_req
== 2,
14258 _("immediate value out of range"));
14259 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14260 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14261 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14265 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14266 inst
.instruction
|= inst
.operands
[0].imm
;
14269 set_pred_insn_type (NEUTRAL_IT_INSN
);
14276 do_t_ssat_usat (0);
14284 Rd
= inst
.operands
[0].reg
;
14285 Rn
= inst
.operands
[2].reg
;
14287 reject_bad_reg (Rd
);
14288 reject_bad_reg (Rn
);
14290 inst
.instruction
|= Rd
<< 8;
14291 inst
.instruction
|= inst
.operands
[1].imm
;
14292 inst
.instruction
|= Rn
<< 16;
14295 /* Checking the range of the branch offset (VAL) with NBITS bits
14296 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14298 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14300 gas_assert (nbits
> 0 && nbits
<= 32);
14303 int cmp
= (1 << (nbits
- 1));
14304 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14309 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14315 /* For branches in Armv8.1-M Mainline. */
14317 do_t_branch_future (void)
14319 unsigned long insn
= inst
.instruction
;
14321 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14322 if (inst
.operands
[0].hasreloc
== 0)
14324 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14325 as_bad (BAD_BRANCH_OFF
);
14327 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14331 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14332 inst
.relocs
[0].pc_rel
= 1;
14338 if (inst
.operands
[1].hasreloc
== 0)
14340 int val
= inst
.operands
[1].imm
;
14341 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14342 as_bad (BAD_BRANCH_OFF
);
14344 int immA
= (val
& 0x0001f000) >> 12;
14345 int immB
= (val
& 0x00000ffc) >> 2;
14346 int immC
= (val
& 0x00000002) >> 1;
14347 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14351 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14352 inst
.relocs
[1].pc_rel
= 1;
14357 if (inst
.operands
[1].hasreloc
== 0)
14359 int val
= inst
.operands
[1].imm
;
14360 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14361 as_bad (BAD_BRANCH_OFF
);
14363 int immA
= (val
& 0x0007f000) >> 12;
14364 int immB
= (val
& 0x00000ffc) >> 2;
14365 int immC
= (val
& 0x00000002) >> 1;
14366 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14370 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14371 inst
.relocs
[1].pc_rel
= 1;
14375 case T_MNEM_bfcsel
:
14377 if (inst
.operands
[1].hasreloc
== 0)
14379 int val
= inst
.operands
[1].imm
;
14380 int immA
= (val
& 0x00001000) >> 12;
14381 int immB
= (val
& 0x00000ffc) >> 2;
14382 int immC
= (val
& 0x00000002) >> 1;
14383 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14387 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14388 inst
.relocs
[1].pc_rel
= 1;
14392 if (inst
.operands
[2].hasreloc
== 0)
14394 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14395 int val2
= inst
.operands
[2].imm
;
14396 int val0
= inst
.operands
[0].imm
& 0x1f;
14397 int diff
= val2
- val0
;
14399 inst
.instruction
|= 1 << 17; /* T bit. */
14400 else if (diff
!= 2)
14401 as_bad (_("out of range label-relative fixup value"));
14405 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14406 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14407 inst
.relocs
[2].pc_rel
= 1;
14411 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14412 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14417 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14424 /* Helper function for do_t_loloop to handle relocations. */
14426 v8_1_loop_reloc (int is_le
)
14428 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14430 int value
= inst
.relocs
[0].exp
.X_add_number
;
14431 value
= (is_le
) ? -value
: value
;
14433 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14434 as_bad (BAD_BRANCH_OFF
);
14438 immh
= (value
& 0x00000ffc) >> 2;
14439 imml
= (value
& 0x00000002) >> 1;
14441 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14445 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14446 inst
.relocs
[0].pc_rel
= 1;
14450 /* For shifts with four operands in MVE. */
14452 do_mve_scalar_shift1 (void)
14454 unsigned int value
= inst
.operands
[2].imm
;
14456 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14457 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14459 /* Setting the bit for saturation. */
14460 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14462 /* Assuming Rm is already checked not to be 11x1. */
14463 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14464 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14465 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14468 /* For shifts in MVE. */
14470 do_mve_scalar_shift (void)
14472 if (!inst
.operands
[2].present
)
14474 inst
.operands
[2] = inst
.operands
[1];
14475 inst
.operands
[1].reg
= 0xf;
14478 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14479 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14481 if (inst
.operands
[2].isreg
)
14483 /* Assuming Rm is already checked not to be 11x1. */
14484 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14485 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14486 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14490 /* Assuming imm is already checked as [1,32]. */
14491 unsigned int value
= inst
.operands
[2].imm
;
14492 inst
.instruction
|= (value
& 0x1c) << 10;
14493 inst
.instruction
|= (value
& 0x03) << 6;
14494 /* Change last 4 bits from 0xd to 0xf. */
14495 inst
.instruction
|= 0x2;
14499 /* MVE instruction encoder helpers. */
14500 #define M_MNEM_vabav 0xee800f01
14501 #define M_MNEM_vmladav 0xeef00e00
14502 #define M_MNEM_vmladava 0xeef00e20
14503 #define M_MNEM_vmladavx 0xeef01e00
14504 #define M_MNEM_vmladavax 0xeef01e20
14505 #define M_MNEM_vmlsdav 0xeef00e01
14506 #define M_MNEM_vmlsdava 0xeef00e21
14507 #define M_MNEM_vmlsdavx 0xeef01e01
14508 #define M_MNEM_vmlsdavax 0xeef01e21
14509 #define M_MNEM_vmullt 0xee011e00
14510 #define M_MNEM_vmullb 0xee010e00
14511 #define M_MNEM_vctp 0xf000e801
14512 #define M_MNEM_vst20 0xfc801e00
14513 #define M_MNEM_vst21 0xfc801e20
14514 #define M_MNEM_vst40 0xfc801e01
14515 #define M_MNEM_vst41 0xfc801e21
14516 #define M_MNEM_vst42 0xfc801e41
14517 #define M_MNEM_vst43 0xfc801e61
14518 #define M_MNEM_vld20 0xfc901e00
14519 #define M_MNEM_vld21 0xfc901e20
14520 #define M_MNEM_vld40 0xfc901e01
14521 #define M_MNEM_vld41 0xfc901e21
14522 #define M_MNEM_vld42 0xfc901e41
14523 #define M_MNEM_vld43 0xfc901e61
14524 #define M_MNEM_vstrb 0xec000e00
14525 #define M_MNEM_vstrh 0xec000e10
14526 #define M_MNEM_vstrw 0xec000e40
14527 #define M_MNEM_vstrd 0xec000e50
14528 #define M_MNEM_vldrb 0xec100e00
14529 #define M_MNEM_vldrh 0xec100e10
14530 #define M_MNEM_vldrw 0xec100e40
14531 #define M_MNEM_vldrd 0xec100e50
14532 #define M_MNEM_vmovlt 0xeea01f40
14533 #define M_MNEM_vmovlb 0xeea00f40
14534 #define M_MNEM_vmovnt 0xfe311e81
14535 #define M_MNEM_vmovnb 0xfe310e81
14536 #define M_MNEM_vadc 0xee300f00
14537 #define M_MNEM_vadci 0xee301f00
14538 #define M_MNEM_vbrsr 0xfe011e60
14539 #define M_MNEM_vaddlv 0xee890f00
14540 #define M_MNEM_vaddlva 0xee890f20
14541 #define M_MNEM_vaddv 0xeef10f00
14542 #define M_MNEM_vaddva 0xeef10f20
14543 #define M_MNEM_vddup 0xee011f6e
14544 #define M_MNEM_vdwdup 0xee011f60
14545 #define M_MNEM_vidup 0xee010f6e
14546 #define M_MNEM_viwdup 0xee010f60
14547 #define M_MNEM_vmaxv 0xeee20f00
14548 #define M_MNEM_vmaxav 0xeee00f00
14549 #define M_MNEM_vminv 0xeee20f80
14550 #define M_MNEM_vminav 0xeee00f80
14551 #define M_MNEM_vmlaldav 0xee800e00
14552 #define M_MNEM_vmlaldava 0xee800e20
14553 #define M_MNEM_vmlaldavx 0xee801e00
14554 #define M_MNEM_vmlaldavax 0xee801e20
14555 #define M_MNEM_vmlsldav 0xee800e01
14556 #define M_MNEM_vmlsldava 0xee800e21
14557 #define M_MNEM_vmlsldavx 0xee801e01
14558 #define M_MNEM_vmlsldavax 0xee801e21
14559 #define M_MNEM_vrmlaldavhx 0xee801f00
14560 #define M_MNEM_vrmlaldavhax 0xee801f20
14561 #define M_MNEM_vrmlsldavh 0xfe800e01
14562 #define M_MNEM_vrmlsldavha 0xfe800e21
14563 #define M_MNEM_vrmlsldavhx 0xfe801e01
14564 #define M_MNEM_vrmlsldavhax 0xfe801e21
14565 #define M_MNEM_vqmovnt 0xee331e01
14566 #define M_MNEM_vqmovnb 0xee330e01
14567 #define M_MNEM_vqmovunt 0xee311e81
14568 #define M_MNEM_vqmovunb 0xee310e81
14569 #define M_MNEM_vshrnt 0xee801fc1
14570 #define M_MNEM_vshrnb 0xee800fc1
14571 #define M_MNEM_vrshrnt 0xfe801fc1
14572 #define M_MNEM_vqshrnt 0xee801f40
14573 #define M_MNEM_vqshrnb 0xee800f40
14574 #define M_MNEM_vqshrunt 0xee801fc0
14575 #define M_MNEM_vqshrunb 0xee800fc0
14576 #define M_MNEM_vrshrnb 0xfe800fc1
14577 #define M_MNEM_vqrshrnt 0xee801f41
14578 #define M_MNEM_vqrshrnb 0xee800f41
14579 #define M_MNEM_vqrshrunt 0xfe801fc0
14580 #define M_MNEM_vqrshrunb 0xfe800fc0
14582 /* Bfloat16 instruction encoder helpers. */
14583 #define B_MNEM_vfmat 0xfc300850
14584 #define B_MNEM_vfmab 0xfc300810
14586 /* Neon instruction encoder helpers. */
14588 /* Encodings for the different types for various Neon opcodes. */
14590 /* An "invalid" code for the following tables. */
14593 struct neon_tab_entry
14596 unsigned float_or_poly
;
14597 unsigned scalar_or_imm
;
14600 /* Map overloaded Neon opcodes to their respective encodings. */
14601 #define NEON_ENC_TAB \
14602 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14603 X(vabdl, 0x0800700, N_INV, N_INV), \
14604 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14605 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14606 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14607 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14608 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14609 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14610 X(vaddl, 0x0800000, N_INV, N_INV), \
14611 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14612 X(vsubl, 0x0800200, N_INV, N_INV), \
14613 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14614 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14615 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14616 /* Register variants of the following two instructions are encoded as
14617 vcge / vcgt with the operands reversed. */ \
14618 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14619 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14620 X(vfma, N_INV, 0x0000c10, N_INV), \
14621 X(vfms, N_INV, 0x0200c10, N_INV), \
14622 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14623 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14624 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14625 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14626 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14627 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14628 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14629 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14630 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14631 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14632 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14633 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14634 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14635 X(vshl, 0x0000400, N_INV, 0x0800510), \
14636 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14637 X(vand, 0x0000110, N_INV, 0x0800030), \
14638 X(vbic, 0x0100110, N_INV, 0x0800030), \
14639 X(veor, 0x1000110, N_INV, N_INV), \
14640 X(vorn, 0x0300110, N_INV, 0x0800010), \
14641 X(vorr, 0x0200110, N_INV, 0x0800010), \
14642 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14643 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14644 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14645 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14646 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14647 X(vst1, 0x0000000, 0x0800000, N_INV), \
14648 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14649 X(vst2, 0x0000100, 0x0800100, N_INV), \
14650 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14651 X(vst3, 0x0000200, 0x0800200, N_INV), \
14652 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14653 X(vst4, 0x0000300, 0x0800300, N_INV), \
14654 X(vmovn, 0x1b20200, N_INV, N_INV), \
14655 X(vtrn, 0x1b20080, N_INV, N_INV), \
14656 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14657 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14658 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14659 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14660 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14661 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14662 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14663 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14664 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14665 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14666 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14667 X(vseleq, 0xe000a00, N_INV, N_INV), \
14668 X(vselvs, 0xe100a00, N_INV, N_INV), \
14669 X(vselge, 0xe200a00, N_INV, N_INV), \
14670 X(vselgt, 0xe300a00, N_INV, N_INV), \
14671 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14672 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14673 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14674 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14675 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14676 X(aes, 0x3b00300, N_INV, N_INV), \
14677 X(sha3op, 0x2000c00, N_INV, N_INV), \
14678 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14679 X(sha2op, 0x3ba0380, N_INV, N_INV)
14683 #define X(OPC,I,F,S) N_MNEM_##OPC
14688 static const struct neon_tab_entry neon_enc_tab
[] =
14690 #define X(OPC,I,F,S) { (I), (F), (S) }
14695 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14696 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14697 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14698 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14699 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14700 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14701 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14702 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14703 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14704 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14705 #define NEON_ENC_SINGLE_(X) \
14706 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14707 #define NEON_ENC_DOUBLE_(X) \
14708 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14709 #define NEON_ENC_FPV8_(X) \
14710 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14712 #define NEON_ENCODE(type, inst) \
14715 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14716 inst.is_neon = 1; \
14720 #define check_neon_suffixes \
14723 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14725 as_bad (_("invalid neon suffix for non neon instruction")); \
14731 /* Define shapes for instruction operands. The following mnemonic characters
14732 are used in this table:
14734 F - VFP S<n> register
14735 D - Neon D<n> register
14736 Q - Neon Q<n> register
14740 L - D<n> register list
14742 This table is used to generate various data:
14743 - enumerations of the form NS_DDR to be used as arguments to
14745 - a table classifying shapes into single, double, quad, mixed.
14746 - a table used to drive neon_select_shape. */
14748 #define NEON_SHAPE_DEF \
14749 X(4, (R, R, Q, Q), QUAD), \
14750 X(4, (Q, R, R, I), QUAD), \
14751 X(4, (R, R, S, S), QUAD), \
14752 X(4, (S, S, R, R), QUAD), \
14753 X(3, (Q, R, I), QUAD), \
14754 X(3, (I, Q, Q), QUAD), \
14755 X(3, (I, Q, R), QUAD), \
14756 X(3, (R, Q, Q), QUAD), \
14757 X(3, (D, D, D), DOUBLE), \
14758 X(3, (Q, Q, Q), QUAD), \
14759 X(3, (D, D, I), DOUBLE), \
14760 X(3, (Q, Q, I), QUAD), \
14761 X(3, (D, D, S), DOUBLE), \
14762 X(3, (Q, Q, S), QUAD), \
14763 X(3, (Q, Q, R), QUAD), \
14764 X(3, (R, R, Q), QUAD), \
14765 X(2, (R, Q), QUAD), \
14766 X(2, (D, D), DOUBLE), \
14767 X(2, (Q, Q), QUAD), \
14768 X(2, (D, S), DOUBLE), \
14769 X(2, (Q, S), QUAD), \
14770 X(2, (D, R), DOUBLE), \
14771 X(2, (Q, R), QUAD), \
14772 X(2, (D, I), DOUBLE), \
14773 X(2, (Q, I), QUAD), \
14774 X(3, (D, L, D), DOUBLE), \
14775 X(2, (D, Q), MIXED), \
14776 X(2, (Q, D), MIXED), \
14777 X(3, (D, Q, I), MIXED), \
14778 X(3, (Q, D, I), MIXED), \
14779 X(3, (Q, D, D), MIXED), \
14780 X(3, (D, Q, Q), MIXED), \
14781 X(3, (Q, Q, D), MIXED), \
14782 X(3, (Q, D, S), MIXED), \
14783 X(3, (D, Q, S), MIXED), \
14784 X(4, (D, D, D, I), DOUBLE), \
14785 X(4, (Q, Q, Q, I), QUAD), \
14786 X(4, (D, D, S, I), DOUBLE), \
14787 X(4, (Q, Q, S, I), QUAD), \
14788 X(2, (F, F), SINGLE), \
14789 X(3, (F, F, F), SINGLE), \
14790 X(2, (F, I), SINGLE), \
14791 X(2, (F, D), MIXED), \
14792 X(2, (D, F), MIXED), \
14793 X(3, (F, F, I), MIXED), \
14794 X(4, (R, R, F, F), SINGLE), \
14795 X(4, (F, F, R, R), SINGLE), \
14796 X(3, (D, R, R), DOUBLE), \
14797 X(3, (R, R, D), DOUBLE), \
14798 X(2, (S, R), SINGLE), \
14799 X(2, (R, S), SINGLE), \
14800 X(2, (F, R), SINGLE), \
14801 X(2, (R, F), SINGLE), \
14802 /* Used for MVE tail predicated loop instructions. */\
14803 X(2, (R, R), QUAD), \
14804 /* Half float shape supported so far. */\
14805 X (2, (H, D), MIXED), \
14806 X (2, (D, H), MIXED), \
14807 X (2, (H, F), MIXED), \
14808 X (2, (F, H), MIXED), \
14809 X (2, (H, H), HALF), \
14810 X (2, (H, R), HALF), \
14811 X (2, (R, H), HALF), \
14812 X (2, (H, I), HALF), \
14813 X (3, (H, H, H), HALF), \
14814 X (3, (H, F, I), MIXED), \
14815 X (3, (F, H, I), MIXED), \
14816 X (3, (D, H, H), MIXED), \
14817 X (3, (D, H, S), MIXED)
14819 #define S2(A,B) NS_##A##B
14820 #define S3(A,B,C) NS_##A##B##C
14821 #define S4(A,B,C,D) NS_##A##B##C##D
14823 #define X(N, L, C) S##N L
14836 enum neon_shape_class
14845 #define X(N, L, C) SC_##C
14847 static enum neon_shape_class neon_shape_class
[] =
14866 /* Register widths of above. */
14867 static unsigned neon_shape_el_size
[] =
14879 struct neon_shape_info
14882 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14885 #define S2(A,B) { SE_##A, SE_##B }
14886 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14887 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14889 #define X(N, L, C) { N, S##N L }
14891 static struct neon_shape_info neon_shape_tab
[] =
14901 /* Bit masks used in type checking given instructions.
14902 'N_EQK' means the type must be the same as (or based on in some way) the key
14903 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14904 set, various other bits can be set as well in order to modify the meaning of
14905 the type constraint. */
14907 enum neon_type_mask
14931 N_BF16
= 0x0400000,
14932 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14933 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14934 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14935 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14936 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14937 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14938 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14939 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14940 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14941 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14942 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14944 N_MAX_NONSPECIAL
= N_P64
14947 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14949 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14950 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14951 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14952 #define N_S_32 (N_S8 | N_S16 | N_S32)
14953 #define N_F_16_32 (N_F16 | N_F32)
14954 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14955 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14956 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14957 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14958 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14959 #define N_F_MVE (N_F16 | N_F32)
14960 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14962 /* Pass this as the first type argument to neon_check_type to ignore types
14964 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14966 /* Select a "shape" for the current instruction (describing register types or
14967 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14968 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14969 function of operand parsing, so this function doesn't need to be called.
14970 Shapes should be listed in order of decreasing length. */
14972 static enum neon_shape
14973 neon_select_shape (enum neon_shape shape
, ...)
14976 enum neon_shape first_shape
= shape
;
14978 /* Fix missing optional operands. FIXME: we don't know at this point how
14979 many arguments we should have, so this makes the assumption that we have
14980 > 1. This is true of all current Neon opcodes, I think, but may not be
14981 true in the future. */
14982 if (!inst
.operands
[1].present
)
14983 inst
.operands
[1] = inst
.operands
[0];
14985 va_start (ap
, shape
);
14987 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14992 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14994 if (!inst
.operands
[j
].present
)
15000 switch (neon_shape_tab
[shape
].el
[j
])
15002 /* If a .f16, .16, .u16, .s16 type specifier is given over
15003 a VFP single precision register operand, it's essentially
15004 means only half of the register is used.
15006 If the type specifier is given after the mnemonics, the
15007 information is stored in inst.vectype. If the type specifier
15008 is given after register operand, the information is stored
15009 in inst.operands[].vectype.
15011 When there is only one type specifier, and all the register
15012 operands are the same type of hardware register, the type
15013 specifier applies to all register operands.
15015 If no type specifier is given, the shape is inferred from
15016 operand information.
15019 vadd.f16 s0, s1, s2: NS_HHH
15020 vabs.f16 s0, s1: NS_HH
15021 vmov.f16 s0, r1: NS_HR
15022 vmov.f16 r0, s1: NS_RH
15023 vcvt.f16 r0, s1: NS_RH
15024 vcvt.f16.s32 s2, s2, #29: NS_HFI
15025 vcvt.f16.s32 s2, s2: NS_HF
15028 if (!(inst
.operands
[j
].isreg
15029 && inst
.operands
[j
].isvec
15030 && inst
.operands
[j
].issingle
15031 && !inst
.operands
[j
].isquad
15032 && ((inst
.vectype
.elems
== 1
15033 && inst
.vectype
.el
[0].size
== 16)
15034 || (inst
.vectype
.elems
> 1
15035 && inst
.vectype
.el
[j
].size
== 16)
15036 || (inst
.vectype
.elems
== 0
15037 && inst
.operands
[j
].vectype
.type
!= NT_invtype
15038 && inst
.operands
[j
].vectype
.size
== 16))))
15043 if (!(inst
.operands
[j
].isreg
15044 && inst
.operands
[j
].isvec
15045 && inst
.operands
[j
].issingle
15046 && !inst
.operands
[j
].isquad
15047 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
15048 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
15049 || (inst
.vectype
.elems
== 0
15050 && (inst
.operands
[j
].vectype
.size
== 32
15051 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
15056 if (!(inst
.operands
[j
].isreg
15057 && inst
.operands
[j
].isvec
15058 && !inst
.operands
[j
].isquad
15059 && !inst
.operands
[j
].issingle
))
15064 if (!(inst
.operands
[j
].isreg
15065 && !inst
.operands
[j
].isvec
))
15070 if (!(inst
.operands
[j
].isreg
15071 && inst
.operands
[j
].isvec
15072 && inst
.operands
[j
].isquad
15073 && !inst
.operands
[j
].issingle
))
15078 if (!(!inst
.operands
[j
].isreg
15079 && !inst
.operands
[j
].isscalar
))
15084 if (!(!inst
.operands
[j
].isreg
15085 && inst
.operands
[j
].isscalar
))
15095 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15096 /* We've matched all the entries in the shape table, and we don't
15097 have any left over operands which have not been matched. */
15103 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15104 first_error (_("invalid instruction shape"));
15109 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15110 means the Q bit should be set). */
15113 neon_quad (enum neon_shape shape
)
15115 return neon_shape_class
[shape
] == SC_QUAD
;
15119 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15122 /* Allow modification to be made to types which are constrained to be
15123 based on the key element, based on bits set alongside N_EQK. */
15124 if ((typebits
& N_EQK
) != 0)
15126 if ((typebits
& N_HLF
) != 0)
15128 else if ((typebits
& N_DBL
) != 0)
15130 if ((typebits
& N_SGN
) != 0)
15131 *g_type
= NT_signed
;
15132 else if ((typebits
& N_UNS
) != 0)
15133 *g_type
= NT_unsigned
;
15134 else if ((typebits
& N_INT
) != 0)
15135 *g_type
= NT_integer
;
15136 else if ((typebits
& N_FLT
) != 0)
15137 *g_type
= NT_float
;
15138 else if ((typebits
& N_SIZ
) != 0)
15139 *g_type
= NT_untyped
;
15143 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15144 operand type, i.e. the single type specified in a Neon instruction when it
15145 is the only one given. */
15147 static struct neon_type_el
15148 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15150 struct neon_type_el dest
= *key
;
15152 gas_assert ((thisarg
& N_EQK
) != 0);
15154 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15159 /* Convert Neon type and size into compact bitmask representation. */
15161 static enum neon_type_mask
15162 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15169 case 8: return N_8
;
15170 case 16: return N_16
;
15171 case 32: return N_32
;
15172 case 64: return N_64
;
15180 case 8: return N_I8
;
15181 case 16: return N_I16
;
15182 case 32: return N_I32
;
15183 case 64: return N_I64
;
15191 case 16: return N_F16
;
15192 case 32: return N_F32
;
15193 case 64: return N_F64
;
15201 case 8: return N_P8
;
15202 case 16: return N_P16
;
15203 case 64: return N_P64
;
15211 case 8: return N_S8
;
15212 case 16: return N_S16
;
15213 case 32: return N_S32
;
15214 case 64: return N_S64
;
15222 case 8: return N_U8
;
15223 case 16: return N_U16
;
15224 case 32: return N_U32
;
15225 case 64: return N_U64
;
15231 if (size
== 16) return N_BF16
;
15240 /* Convert compact Neon bitmask type representation to a type and size. Only
15241 handles the case where a single bit is set in the mask. */
15244 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15245 enum neon_type_mask mask
)
15247 if ((mask
& N_EQK
) != 0)
15250 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15252 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
| N_BF16
))
15255 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15257 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15262 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15264 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15265 *type
= NT_unsigned
;
15266 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15267 *type
= NT_integer
;
15268 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15269 *type
= NT_untyped
;
15270 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15272 else if ((mask
& (N_F_ALL
)) != 0)
15274 else if ((mask
& (N_BF16
)) != 0)
15282 /* Modify a bitmask of allowed types. This is only needed for type
15286 modify_types_allowed (unsigned allowed
, unsigned mods
)
15289 enum neon_el_type type
;
15295 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15297 if (el_type_of_type_chk (&type
, &size
,
15298 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15300 neon_modify_type_size (mods
, &type
, &size
);
15301 destmask
|= type_chk_of_el_type (type
, size
);
15308 /* Check type and return type classification.
15309 The manual states (paraphrase): If one datatype is given, it indicates the
15311 - the second operand, if there is one
15312 - the operand, if there is no second operand
15313 - the result, if there are no operands.
15314 This isn't quite good enough though, so we use a concept of a "key" datatype
15315 which is set on a per-instruction basis, which is the one which matters when
15316 only one data type is written.
15317 Note: this function has side-effects (e.g. filling in missing operands). All
15318 Neon instructions should call it before performing bit encoding. */
15320 static struct neon_type_el
15321 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15324 unsigned i
, pass
, key_el
= 0;
15325 unsigned types
[NEON_MAX_TYPE_ELS
];
15326 enum neon_el_type k_type
= NT_invtype
;
15327 unsigned k_size
= -1u;
15328 struct neon_type_el badtype
= {NT_invtype
, -1};
15329 unsigned key_allowed
= 0;
15331 /* Optional registers in Neon instructions are always (not) in operand 1.
15332 Fill in the missing operand here, if it was omitted. */
15333 if (els
> 1 && !inst
.operands
[1].present
)
15334 inst
.operands
[1] = inst
.operands
[0];
15336 /* Suck up all the varargs. */
15338 for (i
= 0; i
< els
; i
++)
15340 unsigned thisarg
= va_arg (ap
, unsigned);
15341 if (thisarg
== N_IGNORE_TYPE
)
15346 types
[i
] = thisarg
;
15347 if ((thisarg
& N_KEY
) != 0)
15352 if (inst
.vectype
.elems
> 0)
15353 for (i
= 0; i
< els
; i
++)
15354 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15356 first_error (_("types specified in both the mnemonic and operands"));
15360 /* Duplicate inst.vectype elements here as necessary.
15361 FIXME: No idea if this is exactly the same as the ARM assembler,
15362 particularly when an insn takes one register and one non-register
15364 if (inst
.vectype
.elems
== 1 && els
> 1)
15367 inst
.vectype
.elems
= els
;
15368 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15369 for (j
= 0; j
< els
; j
++)
15371 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15374 else if (inst
.vectype
.elems
== 0 && els
> 0)
15377 /* No types were given after the mnemonic, so look for types specified
15378 after each operand. We allow some flexibility here; as long as the
15379 "key" operand has a type, we can infer the others. */
15380 for (j
= 0; j
< els
; j
++)
15381 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15382 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15384 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15386 for (j
= 0; j
< els
; j
++)
15387 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15388 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15393 first_error (_("operand types can't be inferred"));
15397 else if (inst
.vectype
.elems
!= els
)
15399 first_error (_("type specifier has the wrong number of parts"));
15403 for (pass
= 0; pass
< 2; pass
++)
15405 for (i
= 0; i
< els
; i
++)
15407 unsigned thisarg
= types
[i
];
15408 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15409 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15410 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15411 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15413 /* Decay more-specific signed & unsigned types to sign-insensitive
15414 integer types if sign-specific variants are unavailable. */
15415 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15416 && (types_allowed
& N_SU_ALL
) == 0)
15417 g_type
= NT_integer
;
15419 /* If only untyped args are allowed, decay any more specific types to
15420 them. Some instructions only care about signs for some element
15421 sizes, so handle that properly. */
15422 if (((types_allowed
& N_UNT
) == 0)
15423 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15424 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15425 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15426 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15427 g_type
= NT_untyped
;
15431 if ((thisarg
& N_KEY
) != 0)
15435 key_allowed
= thisarg
& ~N_KEY
;
15437 /* Check architecture constraint on FP16 extension. */
15439 && k_type
== NT_float
15440 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15442 inst
.error
= _(BAD_FP16
);
15449 if ((thisarg
& N_VFP
) != 0)
15451 enum neon_shape_el regshape
;
15452 unsigned regwidth
, match
;
15454 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15457 first_error (_("invalid instruction shape"));
15460 regshape
= neon_shape_tab
[ns
].el
[i
];
15461 regwidth
= neon_shape_el_size
[regshape
];
15463 /* In VFP mode, operands must match register widths. If we
15464 have a key operand, use its width, else use the width of
15465 the current operand. */
15471 /* FP16 will use a single precision register. */
15472 if (regwidth
== 32 && match
== 16)
15474 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15478 inst
.error
= _(BAD_FP16
);
15483 if (regwidth
!= match
)
15485 first_error (_("operand size must match register width"));
15490 if ((thisarg
& N_EQK
) == 0)
15492 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15494 if ((given_type
& types_allowed
) == 0)
15496 first_error (BAD_SIMD_TYPE
);
15502 enum neon_el_type mod_k_type
= k_type
;
15503 unsigned mod_k_size
= k_size
;
15504 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15505 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15507 first_error (_("inconsistent types in Neon instruction"));
15515 return inst
.vectype
.el
[key_el
];
15518 /* Neon-style VFP instruction forwarding. */
15520 /* Thumb VFP instructions have 0xE in the condition field. */
15523 do_vfp_cond_or_thumb (void)
15528 inst
.instruction
|= 0xe0000000;
15530 inst
.instruction
|= inst
.cond
<< 28;
15533 /* Look up and encode a simple mnemonic, for use as a helper function for the
15534 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15535 etc. It is assumed that operand parsing has already been done, and that the
15536 operands are in the form expected by the given opcode (this isn't necessarily
15537 the same as the form in which they were parsed, hence some massaging must
15538 take place before this function is called).
15539 Checks current arch version against that in the looked-up opcode. */
15542 do_vfp_nsyn_opcode (const char *opname
)
15544 const struct asm_opcode
*opcode
;
15546 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15551 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15552 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15559 inst
.instruction
= opcode
->tvalue
;
15560 opcode
->tencode ();
15564 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15565 opcode
->aencode ();
15570 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15572 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15574 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15577 do_vfp_nsyn_opcode ("fadds");
15579 do_vfp_nsyn_opcode ("fsubs");
15581 /* ARMv8.2 fp16 instruction. */
15583 do_scalar_fp16_v82_encode ();
15588 do_vfp_nsyn_opcode ("faddd");
15590 do_vfp_nsyn_opcode ("fsubd");
15594 /* Check operand types to see if this is a VFP instruction, and if so call
15598 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15600 enum neon_shape rs
;
15601 struct neon_type_el et
;
15606 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15607 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15611 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15612 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15613 N_F_ALL
| N_KEY
| N_VFP
);
15620 if (et
.type
!= NT_invtype
)
15631 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15633 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15635 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15638 do_vfp_nsyn_opcode ("fmacs");
15640 do_vfp_nsyn_opcode ("fnmacs");
15642 /* ARMv8.2 fp16 instruction. */
15644 do_scalar_fp16_v82_encode ();
15649 do_vfp_nsyn_opcode ("fmacd");
15651 do_vfp_nsyn_opcode ("fnmacd");
15656 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15658 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15660 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15663 do_vfp_nsyn_opcode ("ffmas");
15665 do_vfp_nsyn_opcode ("ffnmas");
15667 /* ARMv8.2 fp16 instruction. */
15669 do_scalar_fp16_v82_encode ();
15674 do_vfp_nsyn_opcode ("ffmad");
15676 do_vfp_nsyn_opcode ("ffnmad");
15681 do_vfp_nsyn_mul (enum neon_shape rs
)
15683 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15685 do_vfp_nsyn_opcode ("fmuls");
15687 /* ARMv8.2 fp16 instruction. */
15689 do_scalar_fp16_v82_encode ();
15692 do_vfp_nsyn_opcode ("fmuld");
15696 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15698 int is_neg
= (inst
.instruction
& 0x80) != 0;
15699 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15701 if (rs
== NS_FF
|| rs
== NS_HH
)
15704 do_vfp_nsyn_opcode ("fnegs");
15706 do_vfp_nsyn_opcode ("fabss");
15708 /* ARMv8.2 fp16 instruction. */
15710 do_scalar_fp16_v82_encode ();
15715 do_vfp_nsyn_opcode ("fnegd");
15717 do_vfp_nsyn_opcode ("fabsd");
15721 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15722 insns belong to Neon, and are handled elsewhere. */
15725 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15727 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15731 do_vfp_nsyn_opcode ("fldmdbs");
15733 do_vfp_nsyn_opcode ("fldmias");
15738 do_vfp_nsyn_opcode ("fstmdbs");
15740 do_vfp_nsyn_opcode ("fstmias");
15745 do_vfp_nsyn_sqrt (void)
15747 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15748 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15750 if (rs
== NS_FF
|| rs
== NS_HH
)
15752 do_vfp_nsyn_opcode ("fsqrts");
15754 /* ARMv8.2 fp16 instruction. */
15756 do_scalar_fp16_v82_encode ();
15759 do_vfp_nsyn_opcode ("fsqrtd");
15763 do_vfp_nsyn_div (void)
15765 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15766 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15767 N_F_ALL
| N_KEY
| N_VFP
);
15769 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15771 do_vfp_nsyn_opcode ("fdivs");
15773 /* ARMv8.2 fp16 instruction. */
15775 do_scalar_fp16_v82_encode ();
15778 do_vfp_nsyn_opcode ("fdivd");
15782 do_vfp_nsyn_nmul (void)
15784 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15785 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15786 N_F_ALL
| N_KEY
| N_VFP
);
15788 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15790 NEON_ENCODE (SINGLE
, inst
);
15791 do_vfp_sp_dyadic ();
15793 /* ARMv8.2 fp16 instruction. */
15795 do_scalar_fp16_v82_encode ();
15799 NEON_ENCODE (DOUBLE
, inst
);
15800 do_vfp_dp_rd_rn_rm ();
15802 do_vfp_cond_or_thumb ();
15806 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15810 neon_logbits (unsigned x
)
15812 return ffs (x
) - 4;
15815 #define LOW4(R) ((R) & 0xf)
15816 #define HI1(R) (((R) >> 4) & 1)
15819 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15824 first_error (BAD_EL_TYPE
);
15827 switch (inst
.operands
[0].imm
)
15830 first_error (_("invalid condition"));
15852 /* only accept eq and ne. */
15853 if (inst
.operands
[0].imm
> 1)
15855 first_error (_("invalid condition"));
15858 return inst
.operands
[0].imm
;
15860 if (inst
.operands
[0].imm
== 0x2)
15862 else if (inst
.operands
[0].imm
== 0x8)
15866 first_error (_("invalid condition"));
15870 switch (inst
.operands
[0].imm
)
15873 first_error (_("invalid condition"));
15889 /* Should be unreachable. */
15893 /* For VCTP (create vector tail predicate) in MVE. */
15898 unsigned size
= 0x0;
15900 if (inst
.cond
> COND_ALWAYS
)
15901 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15903 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15905 /* This is a typical MVE instruction which has no type but have size 8, 16,
15906 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15907 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15908 if ((inst
.operands
[0].present
) && (inst
.vectype
.el
[0].type
== NT_untyped
))
15909 dt
= inst
.vectype
.el
[0].size
;
15911 /* Setting this does not indicate an actual NEON instruction, but only
15912 indicates that the mnemonic accepts neon-style type suffixes. */
15926 first_error (_("Type is not allowed for this instruction"));
15928 inst
.instruction
|= size
<< 20;
15929 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15935 /* We are dealing with a vector predicated block. */
15936 if (inst
.operands
[0].present
)
15938 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15939 struct neon_type_el et
15940 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15943 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15945 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15947 if (et
.type
== NT_invtype
)
15950 if (et
.type
== NT_float
)
15952 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15954 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15955 inst
.instruction
|= (et
.size
== 16) << 28;
15956 inst
.instruction
|= 0x3 << 20;
15960 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15962 inst
.instruction
|= 1 << 28;
15963 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15966 if (inst
.operands
[2].isquad
)
15968 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15969 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15970 inst
.instruction
|= (fcond
& 0x2) >> 1;
15974 if (inst
.operands
[2].reg
== REG_SP
)
15975 as_tsktsk (MVE_BAD_SP
);
15976 inst
.instruction
|= 1 << 6;
15977 inst
.instruction
|= (fcond
& 0x2) << 4;
15978 inst
.instruction
|= inst
.operands
[2].reg
;
15980 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15981 inst
.instruction
|= (fcond
& 0x4) << 10;
15982 inst
.instruction
|= (fcond
& 0x1) << 7;
15985 set_pred_insn_type (VPT_INSN
);
15987 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15988 | ((inst
.instruction
& 0xe000) >> 13);
15989 now_pred
.warn_deprecated
= FALSE
;
15990 now_pred
.type
= VECTOR_PRED
;
15997 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15998 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15999 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
16000 if (!inst
.operands
[2].present
)
16001 first_error (_("MVE vector or ARM register expected"));
16002 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16004 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
16005 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
16006 && inst
.operands
[1].isquad
)
16008 inst
.instruction
= N_MNEM_vcmp
;
16012 if (inst
.cond
> COND_ALWAYS
)
16013 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16015 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16017 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16018 struct neon_type_el et
16019 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16022 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
16023 && !inst
.operands
[2].iszr
, BAD_PC
);
16025 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16027 inst
.instruction
= 0xee010f00;
16028 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16029 inst
.instruction
|= (fcond
& 0x4) << 10;
16030 inst
.instruction
|= (fcond
& 0x1) << 7;
16031 if (et
.type
== NT_float
)
16033 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16035 inst
.instruction
|= (et
.size
== 16) << 28;
16036 inst
.instruction
|= 0x3 << 20;
16040 inst
.instruction
|= 1 << 28;
16041 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16043 if (inst
.operands
[2].isquad
)
16045 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16046 inst
.instruction
|= (fcond
& 0x2) >> 1;
16047 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16051 if (inst
.operands
[2].reg
== REG_SP
)
16052 as_tsktsk (MVE_BAD_SP
);
16053 inst
.instruction
|= 1 << 6;
16054 inst
.instruction
|= (fcond
& 0x2) << 4;
16055 inst
.instruction
|= inst
.operands
[2].reg
;
16063 do_mve_vmaxa_vmina (void)
16065 if (inst
.cond
> COND_ALWAYS
)
16066 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16068 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16070 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16071 struct neon_type_el et
16072 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
16074 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16075 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16076 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16077 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16078 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16083 do_mve_vfmas (void)
16085 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16086 struct neon_type_el et
16087 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
16089 if (inst
.cond
> COND_ALWAYS
)
16090 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16092 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16094 if (inst
.operands
[2].reg
== REG_SP
)
16095 as_tsktsk (MVE_BAD_SP
);
16096 else if (inst
.operands
[2].reg
== REG_PC
)
16097 as_tsktsk (MVE_BAD_PC
);
16099 inst
.instruction
|= (et
.size
== 16) << 28;
16100 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16101 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16102 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16103 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16104 inst
.instruction
|= inst
.operands
[2].reg
;
16109 do_mve_viddup (void)
16111 if (inst
.cond
> COND_ALWAYS
)
16112 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16114 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16116 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
16117 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
16118 _("immediate must be either 1, 2, 4 or 8"));
16120 enum neon_shape rs
;
16121 struct neon_type_el et
;
16123 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
16125 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
16126 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
16131 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
16132 if (inst
.operands
[2].reg
== REG_SP
)
16133 as_tsktsk (MVE_BAD_SP
);
16134 else if (inst
.operands
[2].reg
== REG_PC
)
16135 first_error (BAD_PC
);
16137 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16138 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16139 Rm
= inst
.operands
[2].reg
>> 1;
16141 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16142 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16143 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16144 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16145 inst
.instruction
|= (imm
> 2) << 7;
16146 inst
.instruction
|= Rm
<< 1;
16147 inst
.instruction
|= (imm
== 2 || imm
== 8);
16152 do_mve_vmlas (void)
16154 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16155 struct neon_type_el et
16156 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16158 if (inst
.operands
[2].reg
== REG_PC
)
16159 as_tsktsk (MVE_BAD_PC
);
16160 else if (inst
.operands
[2].reg
== REG_SP
)
16161 as_tsktsk (MVE_BAD_SP
);
16163 if (inst
.cond
> COND_ALWAYS
)
16164 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16166 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16168 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16169 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16170 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16171 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16172 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16173 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16174 inst
.instruction
|= inst
.operands
[2].reg
;
16179 do_mve_vshll (void)
16181 struct neon_type_el et
16182 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16184 if (inst
.cond
> COND_ALWAYS
)
16185 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16187 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16189 int imm
= inst
.operands
[2].imm
;
16190 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16191 _("immediate value out of range"));
16193 if ((unsigned)imm
== et
.size
)
16195 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16196 inst
.instruction
|= 0x110001;
16200 inst
.instruction
|= (et
.size
+ imm
) << 16;
16201 inst
.instruction
|= 0x800140;
16204 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16205 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16206 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16207 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16208 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16213 do_mve_vshlc (void)
16215 if (inst
.cond
> COND_ALWAYS
)
16216 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16218 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16220 if (inst
.operands
[1].reg
== REG_PC
)
16221 as_tsktsk (MVE_BAD_PC
);
16222 else if (inst
.operands
[1].reg
== REG_SP
)
16223 as_tsktsk (MVE_BAD_SP
);
16225 int imm
= inst
.operands
[2].imm
;
16226 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16228 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16229 inst
.instruction
|= (imm
& 0x1f) << 16;
16230 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16231 inst
.instruction
|= inst
.operands
[1].reg
;
16236 do_mve_vshrn (void)
16239 switch (inst
.instruction
)
16241 case M_MNEM_vshrnt
:
16242 case M_MNEM_vshrnb
:
16243 case M_MNEM_vrshrnt
:
16244 case M_MNEM_vrshrnb
:
16245 types
= N_I16
| N_I32
;
16247 case M_MNEM_vqshrnt
:
16248 case M_MNEM_vqshrnb
:
16249 case M_MNEM_vqrshrnt
:
16250 case M_MNEM_vqrshrnb
:
16251 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16253 case M_MNEM_vqshrunt
:
16254 case M_MNEM_vqshrunb
:
16255 case M_MNEM_vqrshrunt
:
16256 case M_MNEM_vqrshrunb
:
16257 types
= N_S16
| N_S32
;
16263 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16265 if (inst
.cond
> COND_ALWAYS
)
16266 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16268 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16270 unsigned Qd
= inst
.operands
[0].reg
;
16271 unsigned Qm
= inst
.operands
[1].reg
;
16272 unsigned imm
= inst
.operands
[2].imm
;
16273 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16275 ? _("immediate operand expected in the range [1,8]")
16276 : _("immediate operand expected in the range [1,16]"));
16278 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16279 inst
.instruction
|= HI1 (Qd
) << 22;
16280 inst
.instruction
|= (et
.size
- imm
) << 16;
16281 inst
.instruction
|= LOW4 (Qd
) << 12;
16282 inst
.instruction
|= HI1 (Qm
) << 5;
16283 inst
.instruction
|= LOW4 (Qm
);
16288 do_mve_vqmovn (void)
16290 struct neon_type_el et
;
16291 if (inst
.instruction
== M_MNEM_vqmovnt
16292 || inst
.instruction
== M_MNEM_vqmovnb
)
16293 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16294 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16296 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16298 if (inst
.cond
> COND_ALWAYS
)
16299 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16301 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16303 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16304 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16305 inst
.instruction
|= (et
.size
== 32) << 18;
16306 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16307 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16308 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16313 do_mve_vpsel (void)
16315 neon_select_shape (NS_QQQ
, NS_NULL
);
16317 if (inst
.cond
> COND_ALWAYS
)
16318 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16320 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16322 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16323 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16324 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16325 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16326 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16327 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16332 do_mve_vpnot (void)
16334 if (inst
.cond
> COND_ALWAYS
)
16335 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16337 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16341 do_mve_vmaxnma_vminnma (void)
16343 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16344 struct neon_type_el et
16345 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16347 if (inst
.cond
> COND_ALWAYS
)
16348 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16350 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16352 inst
.instruction
|= (et
.size
== 16) << 28;
16353 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16354 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16355 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16356 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16361 do_mve_vcmul (void)
16363 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16364 struct neon_type_el et
16365 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16367 if (inst
.cond
> COND_ALWAYS
)
16368 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16370 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16372 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16373 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16374 _("immediate out of range"));
16376 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16377 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16378 as_tsktsk (BAD_MVE_SRCDEST
);
16380 inst
.instruction
|= (et
.size
== 32) << 28;
16381 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16382 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16383 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16384 inst
.instruction
|= (rot
> 90) << 12;
16385 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16386 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16387 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16388 inst
.instruction
|= (rot
== 90 || rot
== 270);
16392 /* To handle the Low Overhead Loop instructions
16393 in Armv8.1-M Mainline and MVE. */
16397 unsigned long insn
= inst
.instruction
;
16399 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16401 if (insn
== T_MNEM_lctp
)
16404 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16406 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16408 struct neon_type_el et
16409 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16410 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16417 constraint (!inst
.operands
[0].present
,
16419 /* fall through. */
16422 if (!inst
.operands
[0].present
)
16423 inst
.instruction
|= 1 << 21;
16425 v8_1_loop_reloc (TRUE
);
16430 v8_1_loop_reloc (FALSE
);
16431 /* fall through. */
16434 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16436 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16437 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16438 else if (inst
.operands
[1].reg
== REG_PC
)
16439 as_tsktsk (MVE_BAD_PC
);
16440 if (inst
.operands
[1].reg
== REG_SP
)
16441 as_tsktsk (MVE_BAD_SP
);
16443 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16453 do_vfp_nsyn_cmp (void)
16455 enum neon_shape rs
;
16456 if (!inst
.operands
[0].isreg
)
16463 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16464 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16468 if (inst
.operands
[1].isreg
)
16470 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16471 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16473 if (rs
== NS_FF
|| rs
== NS_HH
)
16475 NEON_ENCODE (SINGLE
, inst
);
16476 do_vfp_sp_monadic ();
16480 NEON_ENCODE (DOUBLE
, inst
);
16481 do_vfp_dp_rd_rm ();
16486 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16487 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16489 switch (inst
.instruction
& 0x0fffffff)
16492 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16495 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16501 if (rs
== NS_FI
|| rs
== NS_HI
)
16503 NEON_ENCODE (SINGLE
, inst
);
16504 do_vfp_sp_compare_z ();
16508 NEON_ENCODE (DOUBLE
, inst
);
16512 do_vfp_cond_or_thumb ();
16514 /* ARMv8.2 fp16 instruction. */
16515 if (rs
== NS_HI
|| rs
== NS_HH
)
16516 do_scalar_fp16_v82_encode ();
16520 nsyn_insert_sp (void)
16522 inst
.operands
[1] = inst
.operands
[0];
16523 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16524 inst
.operands
[0].reg
= REG_SP
;
16525 inst
.operands
[0].isreg
= 1;
16526 inst
.operands
[0].writeback
= 1;
16527 inst
.operands
[0].present
= 1;
16531 do_vfp_nsyn_push (void)
16535 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16536 _("register list must contain at least 1 and at most 16 "
16539 if (inst
.operands
[1].issingle
)
16540 do_vfp_nsyn_opcode ("fstmdbs");
16542 do_vfp_nsyn_opcode ("fstmdbd");
16546 do_vfp_nsyn_pop (void)
16550 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16551 _("register list must contain at least 1 and at most 16 "
16554 if (inst
.operands
[1].issingle
)
16555 do_vfp_nsyn_opcode ("fldmias");
16557 do_vfp_nsyn_opcode ("fldmiad");
16560 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16561 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16564 neon_dp_fixup (struct arm_it
* insn
)
16566 unsigned int i
= insn
->instruction
;
16571 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16582 insn
->instruction
= i
;
16586 mve_encode_qqr (int size
, int U
, int fp
)
16588 if (inst
.operands
[2].reg
== REG_SP
)
16589 as_tsktsk (MVE_BAD_SP
);
16590 else if (inst
.operands
[2].reg
== REG_PC
)
16591 as_tsktsk (MVE_BAD_PC
);
16596 if (((unsigned)inst
.instruction
) == 0xd00)
16597 inst
.instruction
= 0xee300f40;
16599 else if (((unsigned)inst
.instruction
) == 0x200d00)
16600 inst
.instruction
= 0xee301f40;
16602 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16603 inst
.instruction
= 0xee310e60;
16605 /* Setting size which is 1 for F16 and 0 for F32. */
16606 inst
.instruction
|= (size
== 16) << 28;
16611 if (((unsigned)inst
.instruction
) == 0x800)
16612 inst
.instruction
= 0xee010f40;
16614 else if (((unsigned)inst
.instruction
) == 0x1000800)
16615 inst
.instruction
= 0xee011f40;
16617 else if (((unsigned)inst
.instruction
) == 0)
16618 inst
.instruction
= 0xee000f40;
16620 else if (((unsigned)inst
.instruction
) == 0x200)
16621 inst
.instruction
= 0xee001f40;
16623 else if (((unsigned)inst
.instruction
) == 0x900)
16624 inst
.instruction
= 0xee010e40;
16626 else if (((unsigned)inst
.instruction
) == 0x910)
16627 inst
.instruction
= 0xee011e60;
16629 else if (((unsigned)inst
.instruction
) == 0x10)
16630 inst
.instruction
= 0xee000f60;
16632 else if (((unsigned)inst
.instruction
) == 0x210)
16633 inst
.instruction
= 0xee001f60;
16635 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16636 inst
.instruction
= 0xee000e40;
16638 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16639 inst
.instruction
= 0xee010e60;
16641 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16642 inst
.instruction
= 0xfe010e60;
16645 inst
.instruction
|= U
<< 28;
16647 /* Setting bits for size. */
16648 inst
.instruction
|= neon_logbits (size
) << 20;
16650 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16651 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16652 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16653 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16654 inst
.instruction
|= inst
.operands
[2].reg
;
16659 mve_encode_rqq (unsigned bit28
, unsigned size
)
16661 inst
.instruction
|= bit28
<< 28;
16662 inst
.instruction
|= neon_logbits (size
) << 20;
16663 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16664 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16665 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16666 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16667 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16672 mve_encode_qqq (int ubit
, int size
)
16675 inst
.instruction
|= (ubit
!= 0) << 28;
16676 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16677 inst
.instruction
|= neon_logbits (size
) << 20;
16678 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16679 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16680 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16681 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16682 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16688 mve_encode_rq (unsigned bit28
, unsigned size
)
16690 inst
.instruction
|= bit28
<< 28;
16691 inst
.instruction
|= neon_logbits (size
) << 18;
16692 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16693 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16698 mve_encode_rrqq (unsigned U
, unsigned size
)
16700 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16702 inst
.instruction
|= U
<< 28;
16703 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16704 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16705 inst
.instruction
|= (size
== 32) << 16;
16706 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16707 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16708 inst
.instruction
|= inst
.operands
[3].reg
;
16712 /* Helper function for neon_three_same handling the operands. */
16714 neon_three_args (int isquad
)
16716 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16717 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16718 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16719 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16720 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16721 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16722 inst
.instruction
|= (isquad
!= 0) << 6;
16726 /* Encode insns with bit pattern:
16728 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16729 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16731 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16732 different meaning for some instruction. */
16735 neon_three_same (int isquad
, int ubit
, int size
)
16737 neon_three_args (isquad
);
16738 inst
.instruction
|= (ubit
!= 0) << 24;
16740 inst
.instruction
|= neon_logbits (size
) << 20;
16742 neon_dp_fixup (&inst
);
16745 /* Encode instructions of the form:
16747 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16748 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16750 Don't write size if SIZE == -1. */
16753 neon_two_same (int qbit
, int ubit
, int size
)
16755 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16756 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16757 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16758 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16759 inst
.instruction
|= (qbit
!= 0) << 6;
16760 inst
.instruction
|= (ubit
!= 0) << 24;
16763 inst
.instruction
|= neon_logbits (size
) << 18;
16765 neon_dp_fixup (&inst
);
16768 enum vfp_or_neon_is_neon_bits
16771 NEON_CHECK_ARCH
= 2,
16772 NEON_CHECK_ARCH8
= 4
16775 /* Call this function if an instruction which may have belonged to the VFP or
16776 Neon instruction sets, but turned out to be a Neon instruction (due to the
16777 operand types involved, etc.). We have to check and/or fix-up a couple of
16780 - Make sure the user hasn't attempted to make a Neon instruction
16782 - Alter the value in the condition code field if necessary.
16783 - Make sure that the arch supports Neon instructions.
16785 Which of these operations take place depends on bits from enum
16786 vfp_or_neon_is_neon_bits.
16788 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16789 current instruction's condition is COND_ALWAYS, the condition field is
16790 changed to inst.uncond_value. This is necessary because instructions shared
16791 between VFP and Neon may be conditional for the VFP variants only, and the
16792 unconditional Neon version must have, e.g., 0xF in the condition field. */
16795 vfp_or_neon_is_neon (unsigned check
)
16797 /* Conditions are always legal in Thumb mode (IT blocks). */
16798 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16800 if (inst
.cond
!= COND_ALWAYS
)
16802 first_error (_(BAD_COND
));
16805 if (inst
.uncond_value
!= -1)
16806 inst
.instruction
|= inst
.uncond_value
<< 28;
16810 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16811 || ((check
& NEON_CHECK_ARCH8
)
16812 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16814 first_error (_(BAD_FPU
));
16822 /* Return TRUE if the SIMD instruction is available for the current
16823 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16824 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16825 vfp_or_neon_is_neon for the NEON specific checks. */
16828 check_simd_pred_availability (int fp
, unsigned check
)
16830 if (inst
.cond
> COND_ALWAYS
)
16832 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16834 inst
.error
= BAD_FPU
;
16837 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16839 else if (inst
.cond
< COND_ALWAYS
)
16841 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16842 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16843 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16848 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16849 && vfp_or_neon_is_neon (check
) == FAIL
)
16852 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16853 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16858 /* Neon instruction encoders, in approximate order of appearance. */
16861 do_neon_dyadic_i_su (void)
16863 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16866 enum neon_shape rs
;
16867 struct neon_type_el et
;
16868 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16869 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16871 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16873 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16877 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16879 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16883 do_neon_dyadic_i64_su (void)
16885 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16887 enum neon_shape rs
;
16888 struct neon_type_el et
;
16889 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16891 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16892 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16896 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16897 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16900 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16902 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16906 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16909 unsigned size
= et
.size
>> 3;
16910 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16911 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16912 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16913 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16914 inst
.instruction
|= (isquad
!= 0) << 6;
16915 inst
.instruction
|= immbits
<< 16;
16916 inst
.instruction
|= (size
>> 3) << 7;
16917 inst
.instruction
|= (size
& 0x7) << 19;
16919 inst
.instruction
|= (uval
!= 0) << 24;
16921 neon_dp_fixup (&inst
);
16927 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16930 if (!inst
.operands
[2].isreg
)
16932 enum neon_shape rs
;
16933 struct neon_type_el et
;
16934 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16936 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16937 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16941 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16942 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16944 int imm
= inst
.operands
[2].imm
;
16946 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16947 _("immediate out of range for shift"));
16948 NEON_ENCODE (IMMED
, inst
);
16949 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16953 enum neon_shape rs
;
16954 struct neon_type_el et
;
16955 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16957 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16958 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16962 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16963 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16969 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16970 _("invalid instruction shape"));
16971 if (inst
.operands
[2].reg
== REG_SP
)
16972 as_tsktsk (MVE_BAD_SP
);
16973 else if (inst
.operands
[2].reg
== REG_PC
)
16974 as_tsktsk (MVE_BAD_PC
);
16976 inst
.instruction
= 0xee311e60;
16977 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16978 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16979 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16980 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16981 inst
.instruction
|= inst
.operands
[2].reg
;
16988 /* VSHL/VQSHL 3-register variants have syntax such as:
16990 whereas other 3-register operations encoded by neon_three_same have
16993 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16994 operands[2].reg here. */
16995 tmp
= inst
.operands
[2].reg
;
16996 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16997 inst
.operands
[1].reg
= tmp
;
16998 NEON_ENCODE (INTEGER
, inst
);
16999 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17005 do_neon_qshl (void)
17007 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17010 if (!inst
.operands
[2].isreg
)
17012 enum neon_shape rs
;
17013 struct neon_type_el et
;
17014 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17016 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
17017 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
17021 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17022 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
17024 int imm
= inst
.operands
[2].imm
;
17026 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17027 _("immediate out of range for shift"));
17028 NEON_ENCODE (IMMED
, inst
);
17029 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
17033 enum neon_shape rs
;
17034 struct neon_type_el et
;
17036 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17038 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17039 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
17043 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17044 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17049 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17050 _("invalid instruction shape"));
17051 if (inst
.operands
[2].reg
== REG_SP
)
17052 as_tsktsk (MVE_BAD_SP
);
17053 else if (inst
.operands
[2].reg
== REG_PC
)
17054 as_tsktsk (MVE_BAD_PC
);
17056 inst
.instruction
= 0xee311ee0;
17057 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17058 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17059 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17060 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17061 inst
.instruction
|= inst
.operands
[2].reg
;
17068 /* See note in do_neon_shl. */
17069 tmp
= inst
.operands
[2].reg
;
17070 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17071 inst
.operands
[1].reg
= tmp
;
17072 NEON_ENCODE (INTEGER
, inst
);
17073 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17079 do_neon_rshl (void)
17081 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17084 enum neon_shape rs
;
17085 struct neon_type_el et
;
17086 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17088 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17089 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17093 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17094 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
17101 if (inst
.operands
[2].reg
== REG_PC
)
17102 as_tsktsk (MVE_BAD_PC
);
17103 else if (inst
.operands
[2].reg
== REG_SP
)
17104 as_tsktsk (MVE_BAD_SP
);
17106 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17107 _("invalid instruction shape"));
17109 if (inst
.instruction
== 0x0000510)
17110 /* We are dealing with vqrshl. */
17111 inst
.instruction
= 0xee331ee0;
17113 /* We are dealing with vrshl. */
17114 inst
.instruction
= 0xee331e60;
17116 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17117 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17118 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17119 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17120 inst
.instruction
|= inst
.operands
[2].reg
;
17125 tmp
= inst
.operands
[2].reg
;
17126 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17127 inst
.operands
[1].reg
= tmp
;
17128 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17133 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
17135 /* Handle .I8 pseudo-instructions. */
17138 /* Unfortunately, this will make everything apart from zero out-of-range.
17139 FIXME is this the intended semantics? There doesn't seem much point in
17140 accepting .I8 if so. */
17141 immediate
|= immediate
<< 8;
17147 if (immediate
== (immediate
& 0x000000ff))
17149 *immbits
= immediate
;
17152 else if (immediate
== (immediate
& 0x0000ff00))
17154 *immbits
= immediate
>> 8;
17157 else if (immediate
== (immediate
& 0x00ff0000))
17159 *immbits
= immediate
>> 16;
17162 else if (immediate
== (immediate
& 0xff000000))
17164 *immbits
= immediate
>> 24;
17167 if ((immediate
& 0xffff) != (immediate
>> 16))
17168 goto bad_immediate
;
17169 immediate
&= 0xffff;
17172 if (immediate
== (immediate
& 0x000000ff))
17174 *immbits
= immediate
;
17177 else if (immediate
== (immediate
& 0x0000ff00))
17179 *immbits
= immediate
>> 8;
17184 first_error (_("immediate value out of range"));
17189 do_neon_logic (void)
17191 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17193 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17195 && !check_simd_pred_availability (FALSE
,
17196 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17198 else if (rs
!= NS_QQQ
17199 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17200 first_error (BAD_FPU
);
17202 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17203 /* U bit and size field were set as part of the bitmask. */
17204 NEON_ENCODE (INTEGER
, inst
);
17205 neon_three_same (neon_quad (rs
), 0, -1);
17209 const int three_ops_form
= (inst
.operands
[2].present
17210 && !inst
.operands
[2].isreg
);
17211 const int immoperand
= (three_ops_form
? 2 : 1);
17212 enum neon_shape rs
= (three_ops_form
17213 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17214 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17215 /* Because neon_select_shape makes the second operand a copy of the first
17216 if the second operand is not present. */
17218 && !check_simd_pred_availability (FALSE
,
17219 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17221 else if (rs
!= NS_QQI
17222 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17223 first_error (BAD_FPU
);
17225 struct neon_type_el et
;
17226 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17227 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17229 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17232 if (et
.type
== NT_invtype
)
17234 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17239 if (three_ops_form
)
17240 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17241 _("first and second operands shall be the same register"));
17243 NEON_ENCODE (IMMED
, inst
);
17245 immbits
= inst
.operands
[immoperand
].imm
;
17248 /* .i64 is a pseudo-op, so the immediate must be a repeating
17250 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17251 inst
.operands
[immoperand
].reg
: 0))
17253 /* Set immbits to an invalid constant. */
17254 immbits
= 0xdeadbeef;
17261 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17265 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17269 /* Pseudo-instruction for VBIC. */
17270 neon_invert_size (&immbits
, 0, et
.size
);
17271 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17275 /* Pseudo-instruction for VORR. */
17276 neon_invert_size (&immbits
, 0, et
.size
);
17277 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17287 inst
.instruction
|= neon_quad (rs
) << 6;
17288 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17289 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17290 inst
.instruction
|= cmode
<< 8;
17291 neon_write_immbits (immbits
);
17293 neon_dp_fixup (&inst
);
17298 do_neon_bitfield (void)
17300 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17301 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17302 neon_three_same (neon_quad (rs
), 0, -1);
17306 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17309 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17310 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17312 if (et
.type
== NT_float
)
17314 NEON_ENCODE (FLOAT
, inst
);
17316 mve_encode_qqr (et
.size
, 0, 1);
17318 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17322 NEON_ENCODE (INTEGER
, inst
);
17324 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17326 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17332 do_neon_dyadic_if_su_d (void)
17334 /* This version only allow D registers, but that constraint is enforced during
17335 operand parsing so we don't need to do anything extra here. */
17336 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17340 do_neon_dyadic_if_i_d (void)
17342 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17343 affected if we specify unsigned args. */
17344 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17348 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17350 constraint (size
< 32, BAD_ADDR_MODE
);
17351 constraint (size
!= elsize
, BAD_EL_TYPE
);
17352 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17353 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17354 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17355 _("destination register and offset register may not be the"
17358 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17365 constraint ((imm
% (size
/ 8) != 0)
17366 || imm
> (0x7f << neon_logbits (size
)),
17367 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17368 " range of +/-[0,508]")
17369 : _("immediate must be a multiple of 8 in the"
17370 " range of +/-[0,1016]"));
17371 inst
.instruction
|= 0x11 << 24;
17372 inst
.instruction
|= add
<< 23;
17373 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17374 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17375 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17376 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17377 inst
.instruction
|= 1 << 12;
17378 inst
.instruction
|= (size
== 64) << 8;
17379 inst
.instruction
&= 0xffffff00;
17380 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17381 inst
.instruction
|= imm
>> neon_logbits (size
);
17385 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17387 unsigned os
= inst
.operands
[1].imm
>> 5;
17388 unsigned type
= inst
.vectype
.el
[0].type
;
17389 constraint (os
!= 0 && size
== 8,
17390 _("can not shift offsets when accessing less than half-word"));
17391 constraint (os
&& os
!= neon_logbits (size
),
17392 _("shift immediate must be 1, 2 or 3 for half-word, word"
17393 " or double-word accesses respectively"));
17394 if (inst
.operands
[1].reg
== REG_PC
)
17395 as_tsktsk (MVE_BAD_PC
);
17400 constraint (elsize
>= 64, BAD_EL_TYPE
);
17403 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17407 constraint (elsize
!= size
, BAD_EL_TYPE
);
17412 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17416 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17417 _("destination register and offset register may not be"
17419 constraint (size
== elsize
&& type
== NT_signed
, BAD_EL_TYPE
);
17420 constraint (size
!= elsize
&& type
!= NT_unsigned
&& type
!= NT_signed
,
17422 inst
.instruction
|= ((size
== elsize
) || (type
== NT_unsigned
)) << 28;
17426 constraint (type
!= NT_untyped
, BAD_EL_TYPE
);
17429 inst
.instruction
|= 1 << 23;
17430 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17431 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17432 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17433 inst
.instruction
|= neon_logbits (elsize
) << 7;
17434 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17435 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17436 inst
.instruction
|= !!os
;
17440 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17442 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17444 constraint (size
>= 64, BAD_ADDR_MODE
);
17448 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17451 constraint (elsize
!= size
, BAD_EL_TYPE
);
17458 constraint (elsize
!= size
&& type
!= NT_unsigned
17459 && type
!= NT_signed
, BAD_EL_TYPE
);
17463 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17466 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17474 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17479 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17482 constraint (1, _("immediate must be a multiple of 2 in the"
17483 " range of +/-[0,254]"));
17486 constraint (1, _("immediate must be a multiple of 4 in the"
17487 " range of +/-[0,508]"));
17492 if (size
!= elsize
)
17494 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17495 constraint (inst
.operands
[0].reg
> 14,
17496 _("MVE vector register in the range [Q0..Q7] expected"));
17497 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17498 inst
.instruction
|= (size
== 16) << 19;
17499 inst
.instruction
|= neon_logbits (elsize
) << 7;
17503 if (inst
.operands
[1].reg
== REG_PC
)
17504 as_tsktsk (MVE_BAD_PC
);
17505 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17506 as_tsktsk (MVE_BAD_SP
);
17507 inst
.instruction
|= 1 << 12;
17508 inst
.instruction
|= neon_logbits (size
) << 7;
17510 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17511 inst
.instruction
|= add
<< 23;
17512 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17513 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17514 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17515 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17516 inst
.instruction
&= 0xffffff80;
17517 inst
.instruction
|= imm
>> neon_logbits (size
);
17522 do_mve_vstr_vldr (void)
17527 if (inst
.cond
> COND_ALWAYS
)
17528 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17530 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17532 switch (inst
.instruction
)
17539 /* fall through. */
17545 /* fall through. */
17551 /* fall through. */
17557 /* fall through. */
17562 unsigned elsize
= inst
.vectype
.el
[0].size
;
17564 if (inst
.operands
[1].isquad
)
17566 /* We are dealing with [Q, imm]{!} cases. */
17567 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17571 if (inst
.operands
[1].immisreg
== 2)
17573 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17574 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17576 else if (!inst
.operands
[1].immisreg
)
17578 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17579 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17582 constraint (1, BAD_ADDR_MODE
);
17589 do_mve_vst_vld (void)
17591 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17594 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17595 || inst
.relocs
[0].exp
.X_add_number
!= 0
17596 || inst
.operands
[1].immisreg
!= 0,
17598 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17599 if (inst
.operands
[1].reg
== REG_PC
)
17600 as_tsktsk (MVE_BAD_PC
);
17601 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17602 as_tsktsk (MVE_BAD_SP
);
17605 /* These instructions are one of the "exceptions" mentioned in
17606 handle_pred_state. They are MVE instructions that are not VPT compatible
17607 and do not accept a VPT code, thus appending such a code is a syntax
17609 if (inst
.cond
> COND_ALWAYS
)
17610 first_error (BAD_SYNTAX
);
17611 /* If we append a scalar condition code we can set this to
17612 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17613 else if (inst
.cond
< COND_ALWAYS
)
17614 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17616 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17618 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17619 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17620 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17621 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17622 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17627 do_mve_vaddlv (void)
17629 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17630 struct neon_type_el et
17631 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17633 if (et
.type
== NT_invtype
)
17634 first_error (BAD_EL_TYPE
);
17636 if (inst
.cond
> COND_ALWAYS
)
17637 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17639 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17641 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17643 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17644 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17645 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17646 inst
.instruction
|= inst
.operands
[2].reg
;
17651 do_neon_dyadic_if_su (void)
17653 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17654 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17657 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17658 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17659 && et
.type
== NT_float
17660 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17662 if (!check_simd_pred_availability (et
.type
== NT_float
,
17663 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17666 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17670 do_neon_addsub_if_i (void)
17672 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17673 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17676 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17677 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17678 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17680 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17681 /* If we are parsing Q registers and the element types match MVE, which NEON
17682 also supports, then we must check whether this is an instruction that can
17683 be used by both MVE/NEON. This distinction can be made based on whether
17684 they are predicated or not. */
17685 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17687 if (!check_simd_pred_availability (et
.type
== NT_float
,
17688 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17693 /* If they are either in a D register or are using an unsupported. */
17695 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17699 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17700 affected if we specify unsigned args. */
17701 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17704 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17706 V<op> A,B (A is operand 0, B is operand 2)
17711 so handle that case specially. */
17714 neon_exchange_operands (void)
17716 if (inst
.operands
[1].present
)
17718 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17720 /* Swap operands[1] and operands[2]. */
17721 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17722 inst
.operands
[1] = inst
.operands
[2];
17723 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17728 inst
.operands
[1] = inst
.operands
[2];
17729 inst
.operands
[2] = inst
.operands
[0];
17734 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17736 if (inst
.operands
[2].isreg
)
17739 neon_exchange_operands ();
17740 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17744 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17745 struct neon_type_el et
= neon_check_type (2, rs
,
17746 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17748 NEON_ENCODE (IMMED
, inst
);
17749 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17750 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17751 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17752 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17753 inst
.instruction
|= neon_quad (rs
) << 6;
17754 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17755 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17757 neon_dp_fixup (&inst
);
17764 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17768 do_neon_cmp_inv (void)
17770 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17776 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17779 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17780 scalars, which are encoded in 5 bits, M : Rm.
17781 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17782 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17785 Dot Product instructions are similar to multiply instructions except elsize
17786 should always be 32.
17788 This function translates SCALAR, which is GAS's internal encoding of indexed
17789 scalar register, to raw encoding. There is also register and index range
17790 check based on ELSIZE. */
17793 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17795 unsigned regno
= NEON_SCALAR_REG (scalar
);
17796 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17801 if (regno
> 7 || elno
> 3)
17803 return regno
| (elno
<< 3);
17806 if (regno
> 15 || elno
> 1)
17808 return regno
| (elno
<< 4);
17812 first_error (_("scalar out of range for multiply instruction"));
17818 /* Encode multiply / multiply-accumulate scalar instructions. */
17821 neon_mul_mac (struct neon_type_el et
, int ubit
)
17825 /* Give a more helpful error message if we have an invalid type. */
17826 if (et
.type
== NT_invtype
)
17829 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17830 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17831 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17832 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17833 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17834 inst
.instruction
|= LOW4 (scalar
);
17835 inst
.instruction
|= HI1 (scalar
) << 5;
17836 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17837 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17838 inst
.instruction
|= (ubit
!= 0) << 24;
17840 neon_dp_fixup (&inst
);
17844 do_neon_mac_maybe_scalar (void)
17846 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17849 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17852 if (inst
.operands
[2].isscalar
)
17854 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17855 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17856 struct neon_type_el et
= neon_check_type (3, rs
,
17857 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17858 NEON_ENCODE (SCALAR
, inst
);
17859 neon_mul_mac (et
, neon_quad (rs
));
17861 else if (!inst
.operands
[2].isvec
)
17863 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17865 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17866 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17868 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17872 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17873 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17874 affected if we specify unsigned args. */
17875 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17880 do_bfloat_vfma (void)
17882 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
17883 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
17884 enum neon_shape rs
;
17887 if (inst
.instruction
!= B_MNEM_vfmab
)
17890 inst
.instruction
= B_MNEM_vfmat
;
17893 if (inst
.operands
[2].isscalar
)
17895 rs
= neon_select_shape (NS_QQS
, NS_NULL
);
17896 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17898 inst
.instruction
|= (1 << 25);
17899 int index
= inst
.operands
[2].reg
& 0xf;
17900 constraint (!(index
< 4), _("index must be in the range 0 to 3"));
17901 inst
.operands
[2].reg
>>= 4;
17902 constraint (!(inst
.operands
[2].reg
< 8),
17903 _("indexed register must be less than 8"));
17904 neon_three_args (t_bit
);
17905 inst
.instruction
|= ((index
& 1) << 3);
17906 inst
.instruction
|= ((index
& 2) << 4);
17910 rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17911 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17912 neon_three_args (t_bit
);
17918 do_neon_fmac (void)
17920 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17921 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17924 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17927 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17929 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17930 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17936 if (inst
.operands
[2].reg
== REG_SP
)
17937 as_tsktsk (MVE_BAD_SP
);
17938 else if (inst
.operands
[2].reg
== REG_PC
)
17939 as_tsktsk (MVE_BAD_PC
);
17941 inst
.instruction
= 0xee310e40;
17942 inst
.instruction
|= (et
.size
== 16) << 28;
17943 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17944 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17945 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17946 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17947 inst
.instruction
|= inst
.operands
[2].reg
;
17954 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17957 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17963 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_bf16
) &&
17964 inst
.cond
== COND_ALWAYS
)
17966 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17967 inst
.instruction
= N_MNEM_vfma
;
17968 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17970 return do_neon_fmac();
17981 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17982 struct neon_type_el et
= neon_check_type (3, rs
,
17983 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17984 neon_three_same (neon_quad (rs
), 0, et
.size
);
17987 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17988 same types as the MAC equivalents. The polynomial type for this instruction
17989 is encoded the same as the integer type. */
17994 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17997 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18000 if (inst
.operands
[2].isscalar
)
18002 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18003 do_neon_mac_maybe_scalar ();
18007 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18009 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18010 struct neon_type_el et
18011 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
18012 if (et
.type
== NT_float
)
18013 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
18016 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
18020 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
18021 neon_dyadic_misc (NT_poly
,
18022 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
18028 do_neon_qdmulh (void)
18030 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18033 if (inst
.operands
[2].isscalar
)
18035 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18036 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18037 struct neon_type_el et
= neon_check_type (3, rs
,
18038 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18039 NEON_ENCODE (SCALAR
, inst
);
18040 neon_mul_mac (et
, neon_quad (rs
));
18044 enum neon_shape rs
;
18045 struct neon_type_el et
;
18046 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18048 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18049 et
= neon_check_type (3, rs
,
18050 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18054 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18055 et
= neon_check_type (3, rs
,
18056 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18059 NEON_ENCODE (INTEGER
, inst
);
18061 mve_encode_qqr (et
.size
, 0, 0);
18063 /* The U bit (rounding) comes from bit mask. */
18064 neon_three_same (neon_quad (rs
), 0, et
.size
);
18069 do_mve_vaddv (void)
18071 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18072 struct neon_type_el et
18073 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18075 if (et
.type
== NT_invtype
)
18076 first_error (BAD_EL_TYPE
);
18078 if (inst
.cond
> COND_ALWAYS
)
18079 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18081 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18083 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
18085 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18089 do_mve_vhcadd (void)
18091 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
18092 struct neon_type_el et
18093 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18095 if (inst
.cond
> COND_ALWAYS
)
18096 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18098 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18100 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
18101 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
18103 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
18104 as_tsktsk (_("Warning: 32-bit element size and same first and third "
18105 "operand makes instruction UNPREDICTABLE"));
18107 mve_encode_qqq (0, et
.size
);
18108 inst
.instruction
|= (rot
== 270) << 12;
18113 do_mve_vqdmull (void)
18115 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
18116 struct neon_type_el et
18117 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18120 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18121 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
18122 as_tsktsk (BAD_MVE_SRCDEST
);
18124 if (inst
.cond
> COND_ALWAYS
)
18125 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18127 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18131 mve_encode_qqq (et
.size
== 32, 64);
18132 inst
.instruction
|= 1;
18136 mve_encode_qqr (64, et
.size
== 32, 0);
18137 inst
.instruction
|= 0x3 << 5;
18144 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18145 struct neon_type_el et
18146 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
18148 if (et
.type
== NT_invtype
)
18149 first_error (BAD_EL_TYPE
);
18151 if (inst
.cond
> COND_ALWAYS
)
18152 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18154 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18156 mve_encode_qqq (0, 64);
18160 do_mve_vbrsr (void)
18162 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18163 struct neon_type_el et
18164 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18166 if (inst
.cond
> COND_ALWAYS
)
18167 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18169 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18171 mve_encode_qqr (et
.size
, 0, 0);
18177 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
18179 if (inst
.cond
> COND_ALWAYS
)
18180 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18182 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18184 mve_encode_qqq (1, 64);
18188 do_mve_vmulh (void)
18190 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18191 struct neon_type_el et
18192 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18194 if (inst
.cond
> COND_ALWAYS
)
18195 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18197 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18199 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18203 do_mve_vqdmlah (void)
18205 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18206 struct neon_type_el et
18207 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18209 if (inst
.cond
> COND_ALWAYS
)
18210 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18212 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18214 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18218 do_mve_vqdmladh (void)
18220 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18221 struct neon_type_el et
18222 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18224 if (inst
.cond
> COND_ALWAYS
)
18225 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18227 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18229 mve_encode_qqq (0, et
.size
);
18234 do_mve_vmull (void)
18237 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18238 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18239 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18240 && inst
.cond
== COND_ALWAYS
18241 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18246 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18247 N_SUF_32
| N_F64
| N_P8
18248 | N_P16
| N_I_MVE
| N_KEY
);
18249 if (((et
.type
== NT_poly
) && et
.size
== 8
18250 && ARM_CPU_IS_ANY (cpu_variant
))
18251 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
18258 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18259 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18260 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18262 /* We are dealing with MVE's vmullt. */
18264 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18265 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18266 as_tsktsk (BAD_MVE_SRCDEST
);
18268 if (inst
.cond
> COND_ALWAYS
)
18269 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18271 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18273 if (et
.type
== NT_poly
)
18274 mve_encode_qqq (neon_logbits (et
.size
), 64);
18276 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18281 inst
.instruction
= N_MNEM_vmul
;
18284 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18289 do_mve_vabav (void)
18291 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18296 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18299 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18300 | N_S16
| N_S32
| N_U8
| N_U16
18303 if (inst
.cond
> COND_ALWAYS
)
18304 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18306 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18308 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18312 do_mve_vmladav (void)
18314 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18315 struct neon_type_el et
= neon_check_type (3, rs
,
18316 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18318 if (et
.type
== NT_unsigned
18319 && (inst
.instruction
== M_MNEM_vmladavx
18320 || inst
.instruction
== M_MNEM_vmladavax
18321 || inst
.instruction
== M_MNEM_vmlsdav
18322 || inst
.instruction
== M_MNEM_vmlsdava
18323 || inst
.instruction
== M_MNEM_vmlsdavx
18324 || inst
.instruction
== M_MNEM_vmlsdavax
))
18325 first_error (BAD_SIMD_TYPE
);
18327 constraint (inst
.operands
[2].reg
> 14,
18328 _("MVE vector register in the range [Q0..Q7] expected"));
18330 if (inst
.cond
> COND_ALWAYS
)
18331 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18333 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18335 if (inst
.instruction
== M_MNEM_vmlsdav
18336 || inst
.instruction
== M_MNEM_vmlsdava
18337 || inst
.instruction
== M_MNEM_vmlsdavx
18338 || inst
.instruction
== M_MNEM_vmlsdavax
)
18339 inst
.instruction
|= (et
.size
== 8) << 28;
18341 inst
.instruction
|= (et
.size
== 8) << 8;
18343 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18344 inst
.instruction
|= (et
.size
== 32) << 16;
18348 do_mve_vmlaldav (void)
18350 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18351 struct neon_type_el et
18352 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18353 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18355 if (et
.type
== NT_unsigned
18356 && (inst
.instruction
== M_MNEM_vmlsldav
18357 || inst
.instruction
== M_MNEM_vmlsldava
18358 || inst
.instruction
== M_MNEM_vmlsldavx
18359 || inst
.instruction
== M_MNEM_vmlsldavax
))
18360 first_error (BAD_SIMD_TYPE
);
18362 if (inst
.cond
> COND_ALWAYS
)
18363 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18365 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18367 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18371 do_mve_vrmlaldavh (void)
18373 struct neon_type_el et
;
18374 if (inst
.instruction
== M_MNEM_vrmlsldavh
18375 || inst
.instruction
== M_MNEM_vrmlsldavha
18376 || inst
.instruction
== M_MNEM_vrmlsldavhx
18377 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18379 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18380 if (inst
.operands
[1].reg
== REG_SP
)
18381 as_tsktsk (MVE_BAD_SP
);
18385 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18386 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18387 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18389 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18390 N_U32
| N_S32
| N_KEY
);
18391 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18392 with vmax/min instructions, making the use of SP in assembly really
18393 nonsensical, so instead of issuing a warning like we do for other uses
18394 of SP for the odd register operand we error out. */
18395 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18398 /* Make sure we still check the second operand is an odd one and that PC is
18399 disallowed. This because we are parsing for any GPR operand, to be able
18400 to distinguish between giving a warning or an error for SP as described
18402 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18403 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18405 if (inst
.cond
> COND_ALWAYS
)
18406 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18408 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18410 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18415 do_mve_vmaxnmv (void)
18417 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18418 struct neon_type_el et
18419 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18421 if (inst
.cond
> COND_ALWAYS
)
18422 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18424 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18426 if (inst
.operands
[0].reg
== REG_SP
)
18427 as_tsktsk (MVE_BAD_SP
);
18428 else if (inst
.operands
[0].reg
== REG_PC
)
18429 as_tsktsk (MVE_BAD_PC
);
18431 mve_encode_rq (et
.size
== 16, 64);
18435 do_mve_vmaxv (void)
18437 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18438 struct neon_type_el et
;
18440 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18441 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18443 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18445 if (inst
.cond
> COND_ALWAYS
)
18446 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18448 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18450 if (inst
.operands
[0].reg
== REG_SP
)
18451 as_tsktsk (MVE_BAD_SP
);
18452 else if (inst
.operands
[0].reg
== REG_PC
)
18453 as_tsktsk (MVE_BAD_PC
);
18455 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18460 do_neon_qrdmlah (void)
18462 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18464 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18466 /* Check we're on the correct architecture. */
18467 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18469 = _("instruction form not available on this architecture.");
18470 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18472 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18473 record_feature_use (&fpu_neon_ext_v8_1
);
18475 if (inst
.operands
[2].isscalar
)
18477 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18478 struct neon_type_el et
= neon_check_type (3, rs
,
18479 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18480 NEON_ENCODE (SCALAR
, inst
);
18481 neon_mul_mac (et
, neon_quad (rs
));
18485 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18486 struct neon_type_el et
= neon_check_type (3, rs
,
18487 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18488 NEON_ENCODE (INTEGER
, inst
);
18489 /* The U bit (rounding) comes from bit mask. */
18490 neon_three_same (neon_quad (rs
), 0, et
.size
);
18495 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18496 struct neon_type_el et
18497 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18499 NEON_ENCODE (INTEGER
, inst
);
18500 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18505 do_neon_fcmp_absolute (void)
18507 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18508 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18509 N_F_16_32
| N_KEY
);
18510 /* Size field comes from bit mask. */
18511 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18515 do_neon_fcmp_absolute_inv (void)
18517 neon_exchange_operands ();
18518 do_neon_fcmp_absolute ();
18522 do_neon_step (void)
18524 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18525 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18526 N_F_16_32
| N_KEY
);
18527 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18531 do_neon_abs_neg (void)
18533 enum neon_shape rs
;
18534 struct neon_type_el et
;
18536 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18539 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18540 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18542 if (!check_simd_pred_availability (et
.type
== NT_float
,
18543 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18546 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18547 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18548 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18549 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18550 inst
.instruction
|= neon_quad (rs
) << 6;
18551 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18552 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18554 neon_dp_fixup (&inst
);
18560 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18563 enum neon_shape rs
;
18564 struct neon_type_el et
;
18565 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18567 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18568 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18572 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18573 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18577 int imm
= inst
.operands
[2].imm
;
18578 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18579 _("immediate out of range for insert"));
18580 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18586 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18589 enum neon_shape rs
;
18590 struct neon_type_el et
;
18591 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18593 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18594 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18598 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18599 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18602 int imm
= inst
.operands
[2].imm
;
18603 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18604 _("immediate out of range for insert"));
18605 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18609 do_neon_qshlu_imm (void)
18611 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18614 enum neon_shape rs
;
18615 struct neon_type_el et
;
18616 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18618 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18619 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18623 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18624 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18625 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18628 int imm
= inst
.operands
[2].imm
;
18629 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18630 _("immediate out of range for shift"));
18631 /* Only encodes the 'U present' variant of the instruction.
18632 In this case, signed types have OP (bit 8) set to 0.
18633 Unsigned types have OP set to 1. */
18634 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18635 /* The rest of the bits are the same as other immediate shifts. */
18636 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18640 do_neon_qmovn (void)
18642 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18643 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18644 /* Saturating move where operands can be signed or unsigned, and the
18645 destination has the same signedness. */
18646 NEON_ENCODE (INTEGER
, inst
);
18647 if (et
.type
== NT_unsigned
)
18648 inst
.instruction
|= 0xc0;
18650 inst
.instruction
|= 0x80;
18651 neon_two_same (0, 1, et
.size
/ 2);
18655 do_neon_qmovun (void)
18657 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18658 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18659 /* Saturating move with unsigned results. Operands must be signed. */
18660 NEON_ENCODE (INTEGER
, inst
);
18661 neon_two_same (0, 1, et
.size
/ 2);
18665 do_neon_rshift_sat_narrow (void)
18667 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18668 or unsigned. If operands are unsigned, results must also be unsigned. */
18669 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18670 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18671 int imm
= inst
.operands
[2].imm
;
18672 /* This gets the bounds check, size encoding and immediate bits calculation
18676 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18677 VQMOVN.I<size> <Dd>, <Qm>. */
18680 inst
.operands
[2].present
= 0;
18681 inst
.instruction
= N_MNEM_vqmovn
;
18686 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18687 _("immediate out of range"));
18688 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18692 do_neon_rshift_sat_narrow_u (void)
18694 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18695 or unsigned. If operands are unsigned, results must also be unsigned. */
18696 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18697 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18698 int imm
= inst
.operands
[2].imm
;
18699 /* This gets the bounds check, size encoding and immediate bits calculation
18703 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18704 VQMOVUN.I<size> <Dd>, <Qm>. */
18707 inst
.operands
[2].present
= 0;
18708 inst
.instruction
= N_MNEM_vqmovun
;
18713 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18714 _("immediate out of range"));
18715 /* FIXME: The manual is kind of unclear about what value U should have in
18716 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18718 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18722 do_neon_movn (void)
18724 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18725 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18726 NEON_ENCODE (INTEGER
, inst
);
18727 neon_two_same (0, 1, et
.size
/ 2);
18731 do_neon_rshift_narrow (void)
18733 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18734 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18735 int imm
= inst
.operands
[2].imm
;
18736 /* This gets the bounds check, size encoding and immediate bits calculation
18740 /* If immediate is zero then we are a pseudo-instruction for
18741 VMOVN.I<size> <Dd>, <Qm> */
18744 inst
.operands
[2].present
= 0;
18745 inst
.instruction
= N_MNEM_vmovn
;
18750 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18751 _("immediate out of range for narrowing operation"));
18752 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18756 do_neon_shll (void)
18758 /* FIXME: Type checking when lengthening. */
18759 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18760 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18761 unsigned imm
= inst
.operands
[2].imm
;
18763 if (imm
== et
.size
)
18765 /* Maximum shift variant. */
18766 NEON_ENCODE (INTEGER
, inst
);
18767 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18768 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18769 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18770 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18771 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18773 neon_dp_fixup (&inst
);
18777 /* A more-specific type check for non-max versions. */
18778 et
= neon_check_type (2, NS_QDI
,
18779 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18780 NEON_ENCODE (IMMED
, inst
);
18781 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18785 /* Check the various types for the VCVT instruction, and return which version
18786 the current instruction is. */
18788 #define CVT_FLAVOUR_VAR \
18789 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18790 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18791 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18792 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18793 /* Half-precision conversions. */ \
18794 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18795 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18796 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18797 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18798 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18799 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18800 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18801 Compared with single/double precision variants, only the co-processor \
18802 field is different, so the encoding flow is reused here. */ \
18803 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18804 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18805 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18806 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18807 CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg, NULL, NULL, NULL) \
18808 /* VFP instructions. */ \
18809 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18810 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18811 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18812 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18813 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18814 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18815 /* VFP instructions with bitshift. */ \
18816 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18817 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18818 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18819 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18820 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18821 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18822 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18823 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18825 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18826 neon_cvt_flavour_##C,
18828 /* The different types of conversions we can do. */
18829 enum neon_cvt_flavour
18832 neon_cvt_flavour_invalid
,
18833 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18838 static enum neon_cvt_flavour
18839 get_neon_cvt_flavour (enum neon_shape rs
)
18841 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18842 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18843 if (et.type != NT_invtype) \
18845 inst.error = NULL; \
18846 return (neon_cvt_flavour_##C); \
18849 struct neon_type_el et
;
18850 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18851 || rs
== NS_FF
) ? N_VFP
: 0;
18852 /* The instruction versions which take an immediate take one register
18853 argument, which is extended to the width of the full register. Thus the
18854 "source" and "destination" registers must have the same width. Hack that
18855 here by making the size equal to the key (wider, in this case) operand. */
18856 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18860 return neon_cvt_flavour_invalid
;
18875 /* Neon-syntax VFP conversions. */
18878 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18880 const char *opname
= 0;
18882 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18883 || rs
== NS_FHI
|| rs
== NS_HFI
)
18885 /* Conversions with immediate bitshift. */
18886 const char *enc
[] =
18888 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18894 if (flavour
< (int) ARRAY_SIZE (enc
))
18896 opname
= enc
[flavour
];
18897 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18898 _("operands 0 and 1 must be the same register"));
18899 inst
.operands
[1] = inst
.operands
[2];
18900 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18905 /* Conversions without bitshift. */
18906 const char *enc
[] =
18908 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18914 if (flavour
< (int) ARRAY_SIZE (enc
))
18915 opname
= enc
[flavour
];
18919 do_vfp_nsyn_opcode (opname
);
18921 /* ARMv8.2 fp16 VCVT instruction. */
18922 if (flavour
== neon_cvt_flavour_s32_f16
18923 || flavour
== neon_cvt_flavour_u32_f16
18924 || flavour
== neon_cvt_flavour_f16_u32
18925 || flavour
== neon_cvt_flavour_f16_s32
)
18926 do_scalar_fp16_v82_encode ();
18930 do_vfp_nsyn_cvtz (void)
18932 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18933 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18934 const char *enc
[] =
18936 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18942 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18943 do_vfp_nsyn_opcode (enc
[flavour
]);
18947 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18948 enum neon_cvt_mode mode
)
18953 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18954 D register operands. */
18955 if (flavour
== neon_cvt_flavour_s32_f64
18956 || flavour
== neon_cvt_flavour_u32_f64
)
18957 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18960 if (flavour
== neon_cvt_flavour_s32_f16
18961 || flavour
== neon_cvt_flavour_u32_f16
)
18962 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18965 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18969 case neon_cvt_flavour_s32_f64
:
18973 case neon_cvt_flavour_s32_f32
:
18977 case neon_cvt_flavour_s32_f16
:
18981 case neon_cvt_flavour_u32_f64
:
18985 case neon_cvt_flavour_u32_f32
:
18989 case neon_cvt_flavour_u32_f16
:
18994 first_error (_("invalid instruction shape"));
19000 case neon_cvt_mode_a
: rm
= 0; break;
19001 case neon_cvt_mode_n
: rm
= 1; break;
19002 case neon_cvt_mode_p
: rm
= 2; break;
19003 case neon_cvt_mode_m
: rm
= 3; break;
19004 default: first_error (_("invalid rounding mode")); return;
19007 NEON_ENCODE (FPV8
, inst
);
19008 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
19009 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
19010 inst
.instruction
|= sz
<< 8;
19012 /* ARMv8.2 fp16 VCVT instruction. */
19013 if (flavour
== neon_cvt_flavour_s32_f16
19014 ||flavour
== neon_cvt_flavour_u32_f16
)
19015 do_scalar_fp16_v82_encode ();
19016 inst
.instruction
|= op
<< 7;
19017 inst
.instruction
|= rm
<< 16;
19018 inst
.instruction
|= 0xf0000000;
19019 inst
.is_neon
= TRUE
;
19023 do_neon_cvt_1 (enum neon_cvt_mode mode
)
19025 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
19026 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
19027 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
19029 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19031 if (flavour
== neon_cvt_flavour_invalid
)
19034 /* PR11109: Handle round-to-zero for VCVT conversions. */
19035 if (mode
== neon_cvt_mode_z
19036 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
19037 && (flavour
== neon_cvt_flavour_s16_f16
19038 || flavour
== neon_cvt_flavour_u16_f16
19039 || flavour
== neon_cvt_flavour_s32_f32
19040 || flavour
== neon_cvt_flavour_u32_f32
19041 || flavour
== neon_cvt_flavour_s32_f64
19042 || flavour
== neon_cvt_flavour_u32_f64
)
19043 && (rs
== NS_FD
|| rs
== NS_FF
))
19045 do_vfp_nsyn_cvtz ();
19049 /* ARMv8.2 fp16 VCVT conversions. */
19050 if (mode
== neon_cvt_mode_z
19051 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
19052 && (flavour
== neon_cvt_flavour_s32_f16
19053 || flavour
== neon_cvt_flavour_u32_f16
)
19056 do_vfp_nsyn_cvtz ();
19057 do_scalar_fp16_v82_encode ();
19061 /* VFP rather than Neon conversions. */
19062 if (flavour
>= neon_cvt_flavour_first_fp
)
19064 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19065 do_vfp_nsyn_cvt (rs
, flavour
);
19067 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19075 if (mode
== neon_cvt_mode_z
19076 && (flavour
== neon_cvt_flavour_f16_s16
19077 || flavour
== neon_cvt_flavour_f16_u16
19078 || flavour
== neon_cvt_flavour_s16_f16
19079 || flavour
== neon_cvt_flavour_u16_f16
19080 || flavour
== neon_cvt_flavour_f32_u32
19081 || flavour
== neon_cvt_flavour_f32_s32
19082 || flavour
== neon_cvt_flavour_s32_f32
19083 || flavour
== neon_cvt_flavour_u32_f32
))
19085 if (!check_simd_pred_availability (TRUE
,
19086 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19089 else if (mode
== neon_cvt_mode_n
)
19091 /* We are dealing with vcvt with the 'ne' condition. */
19093 inst
.instruction
= N_MNEM_vcvt
;
19094 do_neon_cvt_1 (neon_cvt_mode_z
);
19097 /* fall through. */
19101 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19102 0x0000100, 0x1000100, 0x0, 0x1000000};
19104 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19105 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19108 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19110 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
19111 _("immediate value out of range"));
19114 case neon_cvt_flavour_f16_s16
:
19115 case neon_cvt_flavour_f16_u16
:
19116 case neon_cvt_flavour_s16_f16
:
19117 case neon_cvt_flavour_u16_f16
:
19118 constraint (inst
.operands
[2].imm
> 16,
19119 _("immediate value out of range"));
19121 case neon_cvt_flavour_f32_u32
:
19122 case neon_cvt_flavour_f32_s32
:
19123 case neon_cvt_flavour_s32_f32
:
19124 case neon_cvt_flavour_u32_f32
:
19125 constraint (inst
.operands
[2].imm
> 32,
19126 _("immediate value out of range"));
19129 inst
.error
= BAD_FPU
;
19134 /* Fixed-point conversion with #0 immediate is encoded as an
19135 integer conversion. */
19136 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
19138 NEON_ENCODE (IMMED
, inst
);
19139 if (flavour
!= neon_cvt_flavour_invalid
)
19140 inst
.instruction
|= enctab
[flavour
];
19141 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19142 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19143 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19144 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19145 inst
.instruction
|= neon_quad (rs
) << 6;
19146 inst
.instruction
|= 1 << 21;
19147 if (flavour
< neon_cvt_flavour_s16_f16
)
19149 inst
.instruction
|= 1 << 21;
19150 immbits
= 32 - inst
.operands
[2].imm
;
19151 inst
.instruction
|= immbits
<< 16;
19155 inst
.instruction
|= 3 << 20;
19156 immbits
= 16 - inst
.operands
[2].imm
;
19157 inst
.instruction
|= immbits
<< 16;
19158 inst
.instruction
&= ~(1 << 9);
19161 neon_dp_fixup (&inst
);
19166 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19167 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
19168 && (flavour
== neon_cvt_flavour_s16_f16
19169 || flavour
== neon_cvt_flavour_u16_f16
19170 || flavour
== neon_cvt_flavour_s32_f32
19171 || flavour
== neon_cvt_flavour_u32_f32
))
19173 if (!check_simd_pred_availability (TRUE
,
19174 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19177 else if (mode
== neon_cvt_mode_z
19178 && (flavour
== neon_cvt_flavour_f16_s16
19179 || flavour
== neon_cvt_flavour_f16_u16
19180 || flavour
== neon_cvt_flavour_s16_f16
19181 || flavour
== neon_cvt_flavour_u16_f16
19182 || flavour
== neon_cvt_flavour_f32_u32
19183 || flavour
== neon_cvt_flavour_f32_s32
19184 || flavour
== neon_cvt_flavour_s32_f32
19185 || flavour
== neon_cvt_flavour_u32_f32
))
19187 if (!check_simd_pred_availability (TRUE
,
19188 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19191 /* fall through. */
19193 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
19196 NEON_ENCODE (FLOAT
, inst
);
19197 if (!check_simd_pred_availability (TRUE
,
19198 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19201 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19202 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19203 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19204 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19205 inst
.instruction
|= neon_quad (rs
) << 6;
19206 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19207 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19208 inst
.instruction
|= mode
<< 8;
19209 if (flavour
== neon_cvt_flavour_u16_f16
19210 || flavour
== neon_cvt_flavour_s16_f16
)
19211 /* Mask off the original size bits and reencode them. */
19212 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19215 inst
.instruction
|= 0xfc000000;
19217 inst
.instruction
|= 0xf0000000;
19223 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19224 0x100, 0x180, 0x0, 0x080};
19226 NEON_ENCODE (INTEGER
, inst
);
19228 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19230 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19234 if (flavour
!= neon_cvt_flavour_invalid
)
19235 inst
.instruction
|= enctab
[flavour
];
19237 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19238 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19239 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19240 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19241 inst
.instruction
|= neon_quad (rs
) << 6;
19242 if (flavour
>= neon_cvt_flavour_s16_f16
19243 && flavour
<= neon_cvt_flavour_f16_u16
)
19244 /* Half precision. */
19245 inst
.instruction
|= 1 << 18;
19247 inst
.instruction
|= 2 << 18;
19249 neon_dp_fixup (&inst
);
19254 /* Half-precision conversions for Advanced SIMD -- neon. */
19257 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19261 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19263 as_bad (_("operand size must match register width"));
19268 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19270 as_bad (_("operand size must match register width"));
19276 if (flavour
== neon_cvt_flavour_bf16_f32
)
19278 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8
) == FAIL
)
19280 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19281 /* VCVT.bf16.f32. */
19282 inst
.instruction
= 0x11b60640;
19285 /* VCVT.f16.f32. */
19286 inst
.instruction
= 0x3b60600;
19289 /* VCVT.f32.f16. */
19290 inst
.instruction
= 0x3b60700;
19292 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19293 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19294 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19295 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19296 neon_dp_fixup (&inst
);
19300 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19301 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19302 do_vfp_nsyn_cvt (rs
, flavour
);
19304 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19309 do_neon_cvtr (void)
19311 do_neon_cvt_1 (neon_cvt_mode_x
);
19317 do_neon_cvt_1 (neon_cvt_mode_z
);
19321 do_neon_cvta (void)
19323 do_neon_cvt_1 (neon_cvt_mode_a
);
19327 do_neon_cvtn (void)
19329 do_neon_cvt_1 (neon_cvt_mode_n
);
19333 do_neon_cvtp (void)
19335 do_neon_cvt_1 (neon_cvt_mode_p
);
19339 do_neon_cvtm (void)
19341 do_neon_cvt_1 (neon_cvt_mode_m
);
19345 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19348 mark_feature_used (&fpu_vfp_ext_armv8
);
19350 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19351 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19352 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19353 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19354 inst
.instruction
|= to
? 0x10000 : 0;
19355 inst
.instruction
|= t
? 0x80 : 0;
19356 inst
.instruction
|= is_double
? 0x100 : 0;
19357 do_vfp_cond_or_thumb ();
19361 do_neon_cvttb_1 (bfd_boolean t
)
19363 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19364 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19368 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19370 int single_to_half
= 0;
19371 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19374 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19376 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19377 && (flavour
== neon_cvt_flavour_u16_f16
19378 || flavour
== neon_cvt_flavour_s16_f16
19379 || flavour
== neon_cvt_flavour_f16_s16
19380 || flavour
== neon_cvt_flavour_f16_u16
19381 || flavour
== neon_cvt_flavour_u32_f32
19382 || flavour
== neon_cvt_flavour_s32_f32
19383 || flavour
== neon_cvt_flavour_f32_s32
19384 || flavour
== neon_cvt_flavour_f32_u32
))
19387 inst
.instruction
= N_MNEM_vcvt
;
19388 set_pred_insn_type (INSIDE_VPT_INSN
);
19389 do_neon_cvt_1 (neon_cvt_mode_z
);
19392 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19393 single_to_half
= 1;
19394 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19396 first_error (BAD_FPU
);
19400 inst
.instruction
= 0xee3f0e01;
19401 inst
.instruction
|= single_to_half
<< 28;
19402 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19403 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19404 inst
.instruction
|= t
<< 12;
19405 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19406 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19409 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19412 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19414 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19417 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19419 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19421 /* The VCVTB and VCVTT instructions with D-register operands
19422 don't work for SP only targets. */
19423 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19427 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19429 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19431 /* The VCVTB and VCVTT instructions with D-register operands
19432 don't work for SP only targets. */
19433 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19437 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19439 else if (neon_check_type (2, rs
, N_BF16
| N_VFP
, N_F32
).type
!= NT_invtype
)
19441 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19443 inst
.instruction
|= (1 << 8);
19444 inst
.instruction
&= ~(1 << 9);
19445 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19452 do_neon_cvtb (void)
19454 do_neon_cvttb_1 (FALSE
);
19459 do_neon_cvtt (void)
19461 do_neon_cvttb_1 (TRUE
);
19465 neon_move_immediate (void)
19467 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19468 struct neon_type_el et
= neon_check_type (2, rs
,
19469 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19470 unsigned immlo
, immhi
= 0, immbits
;
19471 int op
, cmode
, float_p
;
19473 constraint (et
.type
== NT_invtype
,
19474 _("operand size must be specified for immediate VMOV"));
19476 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19477 op
= (inst
.instruction
& (1 << 5)) != 0;
19479 immlo
= inst
.operands
[1].imm
;
19480 if (inst
.operands
[1].regisimm
)
19481 immhi
= inst
.operands
[1].reg
;
19483 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19484 _("immediate has bits set outside the operand size"));
19486 float_p
= inst
.operands
[1].immisfloat
;
19488 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19489 et
.size
, et
.type
)) == FAIL
)
19491 /* Invert relevant bits only. */
19492 neon_invert_size (&immlo
, &immhi
, et
.size
);
19493 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19494 with one or the other; those cases are caught by
19495 neon_cmode_for_move_imm. */
19497 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19498 &op
, et
.size
, et
.type
)) == FAIL
)
19500 first_error (_("immediate out of range"));
19505 inst
.instruction
&= ~(1 << 5);
19506 inst
.instruction
|= op
<< 5;
19508 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19509 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19510 inst
.instruction
|= neon_quad (rs
) << 6;
19511 inst
.instruction
|= cmode
<< 8;
19513 neon_write_immbits (immbits
);
19519 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19522 if (inst
.operands
[1].isreg
)
19524 enum neon_shape rs
;
19525 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19526 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19528 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19530 NEON_ENCODE (INTEGER
, inst
);
19531 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19532 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19533 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19534 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19535 inst
.instruction
|= neon_quad (rs
) << 6;
19539 NEON_ENCODE (IMMED
, inst
);
19540 neon_move_immediate ();
19543 neon_dp_fixup (&inst
);
19545 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19547 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19551 /* Encode instructions of form:
19553 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19554 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19557 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19559 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19560 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19561 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19562 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19563 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19564 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19565 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19566 inst
.instruction
|= neon_logbits (size
) << 20;
19568 neon_dp_fixup (&inst
);
19572 do_neon_dyadic_long (void)
19574 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19577 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19580 NEON_ENCODE (INTEGER
, inst
);
19581 /* FIXME: Type checking for lengthening op. */
19582 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19583 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19584 neon_mixed_length (et
, et
.size
);
19586 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19587 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19589 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19590 in an IT block with le/lt conditions. */
19592 if (inst
.cond
== 0xf)
19594 else if (inst
.cond
== 0x10)
19597 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19599 if (inst
.instruction
== N_MNEM_vaddl
)
19601 inst
.instruction
= N_MNEM_vadd
;
19602 do_neon_addsub_if_i ();
19604 else if (inst
.instruction
== N_MNEM_vsubl
)
19606 inst
.instruction
= N_MNEM_vsub
;
19607 do_neon_addsub_if_i ();
19609 else if (inst
.instruction
== N_MNEM_vabdl
)
19611 inst
.instruction
= N_MNEM_vabd
;
19612 do_neon_dyadic_if_su ();
19616 first_error (BAD_FPU
);
19620 do_neon_abal (void)
19622 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19623 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19624 neon_mixed_length (et
, et
.size
);
19628 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19630 if (inst
.operands
[2].isscalar
)
19632 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19633 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19634 NEON_ENCODE (SCALAR
, inst
);
19635 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19639 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19640 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19641 NEON_ENCODE (INTEGER
, inst
);
19642 neon_mixed_length (et
, et
.size
);
19647 do_neon_mac_maybe_scalar_long (void)
19649 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19652 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19653 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19656 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19658 unsigned regno
= NEON_SCALAR_REG (scalar
);
19659 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19663 if (regno
> 7 || elno
> 3)
19666 return ((regno
& 0x7)
19667 | ((elno
& 0x1) << 3)
19668 | (((elno
>> 1) & 0x1) << 5));
19672 if (regno
> 15 || elno
> 1)
19675 return (((regno
& 0x1) << 5)
19676 | ((regno
>> 1) & 0x7)
19677 | ((elno
& 0x1) << 3));
19681 first_error (_("scalar out of range for multiply instruction"));
19686 do_neon_fmac_maybe_scalar_long (int subtype
)
19688 enum neon_shape rs
;
19690 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19691 field (bits[21:20]) has different meaning. For scalar index variant, it's
19692 used to differentiate add and subtract, otherwise it's with fixed value
19696 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19697 be a scalar index register. */
19698 if (inst
.operands
[2].isscalar
)
19700 high8
= 0xfe000000;
19703 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19707 high8
= 0xfc000000;
19710 inst
.instruction
|= (0x1 << 23);
19711 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19715 if (inst
.cond
!= COND_ALWAYS
)
19716 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19717 "behaviour is UNPREDICTABLE"));
19719 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19722 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19725 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19726 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19727 so we simply pass -1 as size. */
19728 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19729 neon_three_same (quad_p
, 0, size
);
19731 /* Undo neon_dp_fixup. Redo the high eight bits. */
19732 inst
.instruction
&= 0x00ffffff;
19733 inst
.instruction
|= high8
;
19735 #define LOW1(R) ((R) & 0x1)
19736 #define HI4(R) (((R) >> 1) & 0xf)
19737 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19738 whether the instruction is in Q form and whether Vm is a scalar indexed
19740 if (inst
.operands
[2].isscalar
)
19743 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19744 inst
.instruction
&= 0xffffffd0;
19745 inst
.instruction
|= rm
;
19749 /* Redo Rn as well. */
19750 inst
.instruction
&= 0xfff0ff7f;
19751 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19752 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19757 /* Redo Rn and Rm. */
19758 inst
.instruction
&= 0xfff0ff50;
19759 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19760 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19761 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19762 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19767 do_neon_vfmal (void)
19769 return do_neon_fmac_maybe_scalar_long (0);
19773 do_neon_vfmsl (void)
19775 return do_neon_fmac_maybe_scalar_long (1);
19779 do_neon_dyadic_wide (void)
19781 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19782 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19783 neon_mixed_length (et
, et
.size
);
19787 do_neon_dyadic_narrow (void)
19789 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19790 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19791 /* Operand sign is unimportant, and the U bit is part of the opcode,
19792 so force the operand type to integer. */
19793 et
.type
= NT_integer
;
19794 neon_mixed_length (et
, et
.size
/ 2);
19798 do_neon_mul_sat_scalar_long (void)
19800 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19804 do_neon_vmull (void)
19806 if (inst
.operands
[2].isscalar
)
19807 do_neon_mac_maybe_scalar_long ();
19810 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19811 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19813 if (et
.type
== NT_poly
)
19814 NEON_ENCODE (POLY
, inst
);
19816 NEON_ENCODE (INTEGER
, inst
);
19818 /* For polynomial encoding the U bit must be zero, and the size must
19819 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19820 obviously, as 0b10). */
19823 /* Check we're on the correct architecture. */
19824 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19826 _("Instruction form not available on this architecture.");
19831 neon_mixed_length (et
, et
.size
);
19838 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19839 struct neon_type_el et
= neon_check_type (3, rs
,
19840 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19841 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19843 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19844 _("shift out of range"));
19845 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19846 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19847 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19848 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19849 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19850 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19851 inst
.instruction
|= neon_quad (rs
) << 6;
19852 inst
.instruction
|= imm
<< 8;
19854 neon_dp_fixup (&inst
);
19860 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19863 enum neon_shape rs
;
19864 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19865 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19867 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19869 struct neon_type_el et
= neon_check_type (2, rs
,
19870 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19872 unsigned op
= (inst
.instruction
>> 7) & 3;
19873 /* N (width of reversed regions) is encoded as part of the bitmask. We
19874 extract it here to check the elements to be reversed are smaller.
19875 Otherwise we'd get a reserved instruction. */
19876 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19878 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19879 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19880 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19881 " operands makes instruction UNPREDICTABLE"));
19883 gas_assert (elsize
!= 0);
19884 constraint (et
.size
>= elsize
,
19885 _("elements must be smaller than reversal region"));
19886 neon_two_same (neon_quad (rs
), 1, et
.size
);
19892 if (inst
.operands
[1].isscalar
)
19894 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19896 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19897 struct neon_type_el et
= neon_check_type (2, rs
,
19898 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19899 unsigned sizebits
= et
.size
>> 3;
19900 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19901 int logsize
= neon_logbits (et
.size
);
19902 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19904 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19907 NEON_ENCODE (SCALAR
, inst
);
19908 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19909 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19910 inst
.instruction
|= LOW4 (dm
);
19911 inst
.instruction
|= HI1 (dm
) << 5;
19912 inst
.instruction
|= neon_quad (rs
) << 6;
19913 inst
.instruction
|= x
<< 17;
19914 inst
.instruction
|= sizebits
<< 16;
19916 neon_dp_fixup (&inst
);
19920 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19921 struct neon_type_el et
= neon_check_type (2, rs
,
19922 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19925 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19929 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19932 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19934 if (inst
.operands
[1].reg
== REG_SP
)
19935 as_tsktsk (MVE_BAD_SP
);
19936 else if (inst
.operands
[1].reg
== REG_PC
)
19937 as_tsktsk (MVE_BAD_PC
);
19940 /* Duplicate ARM register to lanes of vector. */
19941 NEON_ENCODE (ARMREG
, inst
);
19944 case 8: inst
.instruction
|= 0x400000; break;
19945 case 16: inst
.instruction
|= 0x000020; break;
19946 case 32: inst
.instruction
|= 0x000000; break;
19949 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19950 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19951 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19952 inst
.instruction
|= neon_quad (rs
) << 21;
19953 /* The encoding for this instruction is identical for the ARM and Thumb
19954 variants, except for the condition field. */
19955 do_vfp_cond_or_thumb ();
19960 do_mve_mov (int toQ
)
19962 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19964 if (inst
.cond
> COND_ALWAYS
)
19965 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19967 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19976 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19977 _("Index one must be [2,3] and index two must be two less than"
19979 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19980 _("General purpose registers may not be the same"));
19981 constraint (inst
.operands
[Rt
].reg
== REG_SP
19982 || inst
.operands
[Rt2
].reg
== REG_SP
,
19984 constraint (inst
.operands
[Rt
].reg
== REG_PC
19985 || inst
.operands
[Rt2
].reg
== REG_PC
,
19988 inst
.instruction
= 0xec000f00;
19989 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19990 inst
.instruction
|= !!toQ
<< 20;
19991 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19992 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19993 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19994 inst
.instruction
|= inst
.operands
[Rt
].reg
;
20000 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20003 if (inst
.cond
> COND_ALWAYS
)
20004 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20006 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
20008 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
20011 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20012 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
20013 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20014 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20015 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20020 /* VMOV has particularly many variations. It can be one of:
20021 0. VMOV<c><q> <Qd>, <Qm>
20022 1. VMOV<c><q> <Dd>, <Dm>
20023 (Register operations, which are VORR with Rm = Rn.)
20024 2. VMOV<c><q>.<dt> <Qd>, #<imm>
20025 3. VMOV<c><q>.<dt> <Dd>, #<imm>
20027 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
20028 (ARM register to scalar.)
20029 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
20030 (Two ARM registers to vector.)
20031 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
20032 (Scalar to ARM register.)
20033 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
20034 (Vector to two ARM registers.)
20035 8. VMOV.F32 <Sd>, <Sm>
20036 9. VMOV.F64 <Dd>, <Dm>
20037 (VFP register moves.)
20038 10. VMOV.F32 <Sd>, #imm
20039 11. VMOV.F64 <Dd>, #imm
20040 (VFP float immediate load.)
20041 12. VMOV <Rd>, <Sm>
20042 (VFP single to ARM reg.)
20043 13. VMOV <Sd>, <Rm>
20044 (ARM reg to VFP single.)
20045 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20046 (Two ARM regs to two VFP singles.)
20047 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20048 (Two VFP singles to two ARM regs.)
20049 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20050 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20051 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20052 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
20054 These cases can be disambiguated using neon_select_shape, except cases 1/9
20055 and 3/11 which depend on the operand type too.
20057 All the encoded bits are hardcoded by this function.
20059 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20060 Cases 5, 7 may be used with VFPv2 and above.
20062 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
20063 can specify a type where it doesn't make sense to, and is ignored). */
20068 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
20069 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
20070 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
20071 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
20073 struct neon_type_el et
;
20074 const char *ldconst
= 0;
20078 case NS_DD
: /* case 1/9. */
20079 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20080 /* It is not an error here if no type is given. */
20083 /* In MVE we interpret the following instructions as same, so ignoring
20084 the following type (float) and size (64) checks.
20085 a: VMOV<c><q> <Dd>, <Dm>
20086 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
20087 if ((et
.type
== NT_float
&& et
.size
== 64)
20088 || (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
20090 do_vfp_nsyn_opcode ("fcpyd");
20093 /* fall through. */
20095 case NS_QQ
: /* case 0/1. */
20097 if (!check_simd_pred_availability (FALSE
,
20098 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20100 /* The architecture manual I have doesn't explicitly state which
20101 value the U bit should have for register->register moves, but
20102 the equivalent VORR instruction has U = 0, so do that. */
20103 inst
.instruction
= 0x0200110;
20104 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20105 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20106 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20107 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20108 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20109 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20110 inst
.instruction
|= neon_quad (rs
) << 6;
20112 neon_dp_fixup (&inst
);
20116 case NS_DI
: /* case 3/11. */
20117 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20119 if (et
.type
== NT_float
&& et
.size
== 64)
20121 /* case 11 (fconstd). */
20122 ldconst
= "fconstd";
20123 goto encode_fconstd
;
20125 /* fall through. */
20127 case NS_QI
: /* case 2/3. */
20128 if (!check_simd_pred_availability (FALSE
,
20129 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20131 inst
.instruction
= 0x0800010;
20132 neon_move_immediate ();
20133 neon_dp_fixup (&inst
);
20136 case NS_SR
: /* case 4. */
20138 unsigned bcdebits
= 0;
20140 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
20141 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
20143 /* .<size> is optional here, defaulting to .32. */
20144 if (inst
.vectype
.elems
== 0
20145 && inst
.operands
[0].vectype
.type
== NT_invtype
20146 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20148 inst
.vectype
.el
[0].type
= NT_untyped
;
20149 inst
.vectype
.el
[0].size
= 32;
20150 inst
.vectype
.elems
= 1;
20153 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
20154 logsize
= neon_logbits (et
.size
);
20158 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20159 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
20164 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20165 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20169 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20171 if (inst
.operands
[1].reg
== REG_SP
)
20172 as_tsktsk (MVE_BAD_SP
);
20173 else if (inst
.operands
[1].reg
== REG_PC
)
20174 as_tsktsk (MVE_BAD_PC
);
20176 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
20178 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20179 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20184 case 8: bcdebits
= 0x8; break;
20185 case 16: bcdebits
= 0x1; break;
20186 case 32: bcdebits
= 0x0; break;
20190 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20192 inst
.instruction
= 0xe000b10;
20193 do_vfp_cond_or_thumb ();
20194 inst
.instruction
|= LOW4 (dn
) << 16;
20195 inst
.instruction
|= HI1 (dn
) << 7;
20196 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20197 inst
.instruction
|= (bcdebits
& 3) << 5;
20198 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
20199 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20203 case NS_DRR
: /* case 5 (fmdrr). */
20204 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20205 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20208 inst
.instruction
= 0xc400b10;
20209 do_vfp_cond_or_thumb ();
20210 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
20211 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
20212 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20213 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
20216 case NS_RS
: /* case 6. */
20219 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
20220 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
20221 unsigned abcdebits
= 0;
20223 /* .<dt> is optional here, defaulting to .32. */
20224 if (inst
.vectype
.elems
== 0
20225 && inst
.operands
[0].vectype
.type
== NT_invtype
20226 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20228 inst
.vectype
.el
[0].type
= NT_untyped
;
20229 inst
.vectype
.el
[0].size
= 32;
20230 inst
.vectype
.elems
= 1;
20233 et
= neon_check_type (2, NS_NULL
,
20234 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20235 logsize
= neon_logbits (et
.size
);
20239 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20240 && vfp_or_neon_is_neon (NEON_CHECK_CC
20241 | NEON_CHECK_ARCH
) == FAIL
)
20246 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20247 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20251 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20253 if (inst
.operands
[0].reg
== REG_SP
)
20254 as_tsktsk (MVE_BAD_SP
);
20255 else if (inst
.operands
[0].reg
== REG_PC
)
20256 as_tsktsk (MVE_BAD_PC
);
20259 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20261 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20262 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20266 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20267 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20268 case 32: abcdebits
= 0x00; break;
20272 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20273 inst
.instruction
= 0xe100b10;
20274 do_vfp_cond_or_thumb ();
20275 inst
.instruction
|= LOW4 (dn
) << 16;
20276 inst
.instruction
|= HI1 (dn
) << 7;
20277 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20278 inst
.instruction
|= (abcdebits
& 3) << 5;
20279 inst
.instruction
|= (abcdebits
>> 2) << 21;
20280 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20284 case NS_RRD
: /* case 7 (fmrrd). */
20285 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20286 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20289 inst
.instruction
= 0xc500b10;
20290 do_vfp_cond_or_thumb ();
20291 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20292 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20293 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20294 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20297 case NS_FF
: /* case 8 (fcpys). */
20298 do_vfp_nsyn_opcode ("fcpys");
20302 case NS_FI
: /* case 10 (fconsts). */
20303 ldconst
= "fconsts";
20305 if (!inst
.operands
[1].immisfloat
)
20308 /* Immediate has to fit in 8 bits so float is enough. */
20309 float imm
= (float) inst
.operands
[1].imm
;
20310 memcpy (&new_imm
, &imm
, sizeof (float));
20311 /* But the assembly may have been written to provide an integer
20312 bit pattern that equates to a float, so check that the
20313 conversion has worked. */
20314 if (is_quarter_float (new_imm
))
20316 if (is_quarter_float (inst
.operands
[1].imm
))
20317 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20319 inst
.operands
[1].imm
= new_imm
;
20320 inst
.operands
[1].immisfloat
= 1;
20324 if (is_quarter_float (inst
.operands
[1].imm
))
20326 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20327 do_vfp_nsyn_opcode (ldconst
);
20329 /* ARMv8.2 fp16 vmov.f16 instruction. */
20331 do_scalar_fp16_v82_encode ();
20334 first_error (_("immediate out of range"));
20338 case NS_RF
: /* case 12 (fmrs). */
20339 do_vfp_nsyn_opcode ("fmrs");
20340 /* ARMv8.2 fp16 vmov.f16 instruction. */
20342 do_scalar_fp16_v82_encode ();
20346 case NS_FR
: /* case 13 (fmsr). */
20347 do_vfp_nsyn_opcode ("fmsr");
20348 /* ARMv8.2 fp16 vmov.f16 instruction. */
20350 do_scalar_fp16_v82_encode ();
20360 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20361 (one of which is a list), but we have parsed four. Do some fiddling to
20362 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20364 case NS_RRFF
: /* case 14 (fmrrs). */
20365 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20366 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20368 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20369 _("VFP registers must be adjacent"));
20370 inst
.operands
[2].imm
= 2;
20371 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20372 do_vfp_nsyn_opcode ("fmrrs");
20375 case NS_FFRR
: /* case 15 (fmsrr). */
20376 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20377 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20379 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20380 _("VFP registers must be adjacent"));
20381 inst
.operands
[1] = inst
.operands
[2];
20382 inst
.operands
[2] = inst
.operands
[3];
20383 inst
.operands
[0].imm
= 2;
20384 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20385 do_vfp_nsyn_opcode ("fmsrr");
20389 /* neon_select_shape has determined that the instruction
20390 shape is wrong and has already set the error message. */
20401 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20402 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20403 && !inst
.operands
[2].present
))
20405 inst
.instruction
= 0;
20408 set_pred_insn_type (INSIDE_IT_INSN
);
20413 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20416 if (inst
.cond
!= COND_ALWAYS
)
20417 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20419 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20420 | N_S16
| N_U16
| N_KEY
);
20422 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20423 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20424 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20425 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20426 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20427 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20432 do_neon_rshift_round_imm (void)
20434 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20437 enum neon_shape rs
;
20438 struct neon_type_el et
;
20440 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20442 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20443 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20447 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20448 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20450 int imm
= inst
.operands
[2].imm
;
20452 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20455 inst
.operands
[2].present
= 0;
20460 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20461 _("immediate out of range for shift"));
20462 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20467 do_neon_movhf (void)
20469 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20470 constraint (rs
!= NS_HH
, _("invalid suffix"));
20472 if (inst
.cond
!= COND_ALWAYS
)
20476 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20477 " the behaviour is UNPREDICTABLE"));
20481 inst
.error
= BAD_COND
;
20486 do_vfp_sp_monadic ();
20489 inst
.instruction
|= 0xf0000000;
20493 do_neon_movl (void)
20495 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20496 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20497 unsigned sizebits
= et
.size
>> 3;
20498 inst
.instruction
|= sizebits
<< 19;
20499 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20505 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20506 struct neon_type_el et
= neon_check_type (2, rs
,
20507 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20508 NEON_ENCODE (INTEGER
, inst
);
20509 neon_two_same (neon_quad (rs
), 1, et
.size
);
20513 do_neon_zip_uzp (void)
20515 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20516 struct neon_type_el et
= neon_check_type (2, rs
,
20517 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20518 if (rs
== NS_DD
&& et
.size
== 32)
20520 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20521 inst
.instruction
= N_MNEM_vtrn
;
20525 neon_two_same (neon_quad (rs
), 1, et
.size
);
20529 do_neon_sat_abs_neg (void)
20531 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20534 enum neon_shape rs
;
20535 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20536 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20538 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20539 struct neon_type_el et
= neon_check_type (2, rs
,
20540 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20541 neon_two_same (neon_quad (rs
), 1, et
.size
);
20545 do_neon_pair_long (void)
20547 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20548 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20549 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20550 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20551 neon_two_same (neon_quad (rs
), 1, et
.size
);
20555 do_neon_recip_est (void)
20557 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20558 struct neon_type_el et
= neon_check_type (2, rs
,
20559 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20560 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20561 neon_two_same (neon_quad (rs
), 1, et
.size
);
20567 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20570 enum neon_shape rs
;
20571 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20572 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20574 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20576 struct neon_type_el et
= neon_check_type (2, rs
,
20577 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20578 neon_two_same (neon_quad (rs
), 1, et
.size
);
20584 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20587 enum neon_shape rs
;
20588 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20589 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20591 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20593 struct neon_type_el et
= neon_check_type (2, rs
,
20594 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20595 neon_two_same (neon_quad (rs
), 1, et
.size
);
20601 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20602 struct neon_type_el et
= neon_check_type (2, rs
,
20603 N_EQK
| N_INT
, N_8
| N_KEY
);
20604 neon_two_same (neon_quad (rs
), 1, et
.size
);
20610 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20611 neon_two_same (neon_quad (rs
), 1, -1);
20615 do_neon_tbl_tbx (void)
20617 unsigned listlenbits
;
20618 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20620 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20622 first_error (_("bad list length for table lookup"));
20626 listlenbits
= inst
.operands
[1].imm
- 1;
20627 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20628 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20629 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20630 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20631 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20632 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20633 inst
.instruction
|= listlenbits
<< 8;
20635 neon_dp_fixup (&inst
);
20639 do_neon_ldm_stm (void)
20641 /* P, U and L bits are part of bitmask. */
20642 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20643 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20645 if (inst
.operands
[1].issingle
)
20647 do_vfp_nsyn_ldm_stm (is_dbmode
);
20651 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20652 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20654 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20655 _("register list must contain at least 1 and at most 16 "
20658 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20659 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20660 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20661 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20663 inst
.instruction
|= offsetbits
;
20665 do_vfp_cond_or_thumb ();
20669 do_neon_ldr_str (void)
20671 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20673 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20674 And is UNPREDICTABLE in thumb mode. */
20676 && inst
.operands
[1].reg
== REG_PC
20677 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20680 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20681 else if (warn_on_deprecated
)
20682 as_tsktsk (_("Use of PC here is deprecated"));
20685 if (inst
.operands
[0].issingle
)
20688 do_vfp_nsyn_opcode ("flds");
20690 do_vfp_nsyn_opcode ("fsts");
20692 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20693 if (inst
.vectype
.el
[0].size
== 16)
20694 do_scalar_fp16_v82_encode ();
20699 do_vfp_nsyn_opcode ("fldd");
20701 do_vfp_nsyn_opcode ("fstd");
20706 do_t_vldr_vstr_sysreg (void)
20708 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20709 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20711 /* Use of PC is UNPREDICTABLE. */
20712 if (inst
.operands
[1].reg
== REG_PC
)
20713 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20715 if (inst
.operands
[1].immisreg
)
20716 inst
.error
= _("instruction does not accept register index");
20718 if (!inst
.operands
[1].isreg
)
20719 inst
.error
= _("instruction does not accept PC-relative addressing");
20721 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20722 inst
.error
= _("immediate value out of range");
20724 inst
.instruction
= 0xec000f80;
20726 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20727 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20728 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20729 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20733 do_vldr_vstr (void)
20735 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20737 /* VLDR/VSTR (System Register). */
20740 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20741 as_bad (_("Instruction not permitted on this architecture"));
20743 do_t_vldr_vstr_sysreg ();
20748 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20749 as_bad (_("Instruction not permitted on this architecture"));
20750 do_neon_ldr_str ();
20754 /* "interleave" version also handles non-interleaving register VLD1/VST1
20758 do_neon_ld_st_interleave (void)
20760 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20761 N_8
| N_16
| N_32
| N_64
);
20762 unsigned alignbits
= 0;
20764 /* The bits in this table go:
20765 0: register stride of one (0) or two (1)
20766 1,2: register list length, minus one (1, 2, 3, 4).
20767 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20768 We use -1 for invalid entries. */
20769 const int typetable
[] =
20771 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20772 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20773 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20774 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20778 if (et
.type
== NT_invtype
)
20781 if (inst
.operands
[1].immisalign
)
20782 switch (inst
.operands
[1].imm
>> 8)
20784 case 64: alignbits
= 1; break;
20786 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20787 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20788 goto bad_alignment
;
20792 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20793 goto bad_alignment
;
20798 first_error (_("bad alignment"));
20802 inst
.instruction
|= alignbits
<< 4;
20803 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20805 /* Bits [4:6] of the immediate in a list specifier encode register stride
20806 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20807 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20808 up the right value for "type" in a table based on this value and the given
20809 list style, then stick it back. */
20810 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20811 | (((inst
.instruction
>> 8) & 3) << 3);
20813 typebits
= typetable
[idx
];
20815 constraint (typebits
== -1, _("bad list type for instruction"));
20816 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20819 inst
.instruction
&= ~0xf00;
20820 inst
.instruction
|= typebits
<< 8;
20823 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20824 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20825 otherwise. The variable arguments are a list of pairs of legal (size, align)
20826 values, terminated with -1. */
20829 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20832 int result
= FAIL
, thissize
, thisalign
;
20834 if (!inst
.operands
[1].immisalign
)
20840 va_start (ap
, do_alignment
);
20844 thissize
= va_arg (ap
, int);
20845 if (thissize
== -1)
20847 thisalign
= va_arg (ap
, int);
20849 if (size
== thissize
&& align
== thisalign
)
20852 while (result
!= SUCCESS
);
20856 if (result
== SUCCESS
)
20859 first_error (_("unsupported alignment for instruction"));
20865 do_neon_ld_st_lane (void)
20867 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20868 int align_good
, do_alignment
= 0;
20869 int logsize
= neon_logbits (et
.size
);
20870 int align
= inst
.operands
[1].imm
>> 8;
20871 int n
= (inst
.instruction
>> 8) & 3;
20872 int max_el
= 64 / et
.size
;
20874 if (et
.type
== NT_invtype
)
20877 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20878 _("bad list length"));
20879 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20880 _("scalar index out of range"));
20881 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20883 _("stride of 2 unavailable when element size is 8"));
20887 case 0: /* VLD1 / VST1. */
20888 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20890 if (align_good
== FAIL
)
20894 unsigned alignbits
= 0;
20897 case 16: alignbits
= 0x1; break;
20898 case 32: alignbits
= 0x3; break;
20901 inst
.instruction
|= alignbits
<< 4;
20905 case 1: /* VLD2 / VST2. */
20906 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20907 16, 32, 32, 64, -1);
20908 if (align_good
== FAIL
)
20911 inst
.instruction
|= 1 << 4;
20914 case 2: /* VLD3 / VST3. */
20915 constraint (inst
.operands
[1].immisalign
,
20916 _("can't use alignment with this instruction"));
20919 case 3: /* VLD4 / VST4. */
20920 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20921 16, 64, 32, 64, 32, 128, -1);
20922 if (align_good
== FAIL
)
20926 unsigned alignbits
= 0;
20929 case 8: alignbits
= 0x1; break;
20930 case 16: alignbits
= 0x1; break;
20931 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20934 inst
.instruction
|= alignbits
<< 4;
20941 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20942 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20943 inst
.instruction
|= 1 << (4 + logsize
);
20945 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20946 inst
.instruction
|= logsize
<< 10;
20949 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20952 do_neon_ld_dup (void)
20954 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20955 int align_good
, do_alignment
= 0;
20957 if (et
.type
== NT_invtype
)
20960 switch ((inst
.instruction
>> 8) & 3)
20962 case 0: /* VLD1. */
20963 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20964 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20965 &do_alignment
, 16, 16, 32, 32, -1);
20966 if (align_good
== FAIL
)
20968 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20971 case 2: inst
.instruction
|= 1 << 5; break;
20972 default: first_error (_("bad list length")); return;
20974 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20977 case 1: /* VLD2. */
20978 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20979 &do_alignment
, 8, 16, 16, 32, 32, 64,
20981 if (align_good
== FAIL
)
20983 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20984 _("bad list length"));
20985 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20986 inst
.instruction
|= 1 << 5;
20987 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20990 case 2: /* VLD3. */
20991 constraint (inst
.operands
[1].immisalign
,
20992 _("can't use alignment with this instruction"));
20993 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20994 _("bad list length"));
20995 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20996 inst
.instruction
|= 1 << 5;
20997 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21000 case 3: /* VLD4. */
21002 int align
= inst
.operands
[1].imm
>> 8;
21003 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
21004 16, 64, 32, 64, 32, 128, -1);
21005 if (align_good
== FAIL
)
21007 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
21008 _("bad list length"));
21009 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21010 inst
.instruction
|= 1 << 5;
21011 if (et
.size
== 32 && align
== 128)
21012 inst
.instruction
|= 0x3 << 6;
21014 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21021 inst
.instruction
|= do_alignment
<< 4;
21024 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
21025 apart from bits [11:4]. */
21028 do_neon_ldx_stx (void)
21030 if (inst
.operands
[1].isreg
)
21031 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
21033 switch (NEON_LANE (inst
.operands
[0].imm
))
21035 case NEON_INTERLEAVE_LANES
:
21036 NEON_ENCODE (INTERLV
, inst
);
21037 do_neon_ld_st_interleave ();
21040 case NEON_ALL_LANES
:
21041 NEON_ENCODE (DUP
, inst
);
21042 if (inst
.instruction
== N_INV
)
21044 first_error ("only loads support such operands");
21051 NEON_ENCODE (LANE
, inst
);
21052 do_neon_ld_st_lane ();
21055 /* L bit comes from bit mask. */
21056 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21057 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21058 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
21060 if (inst
.operands
[1].postind
)
21062 int postreg
= inst
.operands
[1].imm
& 0xf;
21063 constraint (!inst
.operands
[1].immisreg
,
21064 _("post-index must be a register"));
21065 constraint (postreg
== 0xd || postreg
== 0xf,
21066 _("bad register for post-index"));
21067 inst
.instruction
|= postreg
;
21071 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
21072 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
21073 || inst
.relocs
[0].exp
.X_add_number
!= 0,
21076 if (inst
.operands
[1].writeback
)
21078 inst
.instruction
|= 0xd;
21081 inst
.instruction
|= 0xf;
21085 inst
.instruction
|= 0xf9000000;
21087 inst
.instruction
|= 0xf4000000;
21092 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
21094 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21095 D register operands. */
21096 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21097 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21100 NEON_ENCODE (FPV8
, inst
);
21102 if (rs
== NS_FFF
|| rs
== NS_HHH
)
21104 do_vfp_sp_dyadic ();
21106 /* ARMv8.2 fp16 instruction. */
21108 do_scalar_fp16_v82_encode ();
21111 do_vfp_dp_rd_rn_rm ();
21114 inst
.instruction
|= 0x100;
21116 inst
.instruction
|= 0xf0000000;
21122 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21124 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
21125 first_error (_("invalid instruction shape"));
21131 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21132 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21134 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
21137 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21140 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
21144 do_vrint_1 (enum neon_cvt_mode mode
)
21146 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
21147 struct neon_type_el et
;
21152 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21153 D register operands. */
21154 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21155 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21158 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
21160 if (et
.type
!= NT_invtype
)
21162 /* VFP encodings. */
21163 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
21164 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
21165 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21167 NEON_ENCODE (FPV8
, inst
);
21168 if (rs
== NS_FF
|| rs
== NS_HH
)
21169 do_vfp_sp_monadic ();
21171 do_vfp_dp_rd_rm ();
21175 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
21176 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
21177 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
21178 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
21179 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
21180 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
21181 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
21185 inst
.instruction
|= (rs
== NS_DD
) << 8;
21186 do_vfp_cond_or_thumb ();
21188 /* ARMv8.2 fp16 vrint instruction. */
21190 do_scalar_fp16_v82_encode ();
21194 /* Neon encodings (or something broken...). */
21196 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
21198 if (et
.type
== NT_invtype
)
21201 if (!check_simd_pred_availability (TRUE
,
21202 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21205 NEON_ENCODE (FLOAT
, inst
);
21207 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21208 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21209 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21210 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21211 inst
.instruction
|= neon_quad (rs
) << 6;
21212 /* Mask off the original size bits and reencode them. */
21213 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
21214 | neon_logbits (et
.size
) << 18);
21218 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
21219 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
21220 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
21221 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
21222 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
21223 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
21224 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21229 inst
.instruction
|= 0xfc000000;
21231 inst
.instruction
|= 0xf0000000;
21238 do_vrint_1 (neon_cvt_mode_x
);
21244 do_vrint_1 (neon_cvt_mode_z
);
21250 do_vrint_1 (neon_cvt_mode_r
);
21256 do_vrint_1 (neon_cvt_mode_a
);
21262 do_vrint_1 (neon_cvt_mode_n
);
21268 do_vrint_1 (neon_cvt_mode_p
);
21274 do_vrint_1 (neon_cvt_mode_m
);
21278 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21280 unsigned regno
= NEON_SCALAR_REG (opnd
);
21281 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21283 if (elsize
== 16 && elno
< 2 && regno
< 16)
21284 return regno
| (elno
<< 4);
21285 else if (elsize
== 32 && elno
== 0)
21288 first_error (_("scalar out of range"));
21295 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21296 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21297 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21298 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21299 _("expression too complex"));
21300 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21301 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21302 _("immediate out of range"));
21305 if (!check_simd_pred_availability (TRUE
,
21306 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21309 if (inst
.operands
[2].isscalar
)
21311 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21312 first_error (_("invalid instruction shape"));
21313 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21314 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21315 N_KEY
| N_F16
| N_F32
).size
;
21316 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21318 inst
.instruction
= 0xfe000800;
21319 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21320 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21321 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21322 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21323 inst
.instruction
|= LOW4 (m
);
21324 inst
.instruction
|= HI1 (m
) << 5;
21325 inst
.instruction
|= neon_quad (rs
) << 6;
21326 inst
.instruction
|= rot
<< 20;
21327 inst
.instruction
|= (size
== 32) << 23;
21331 enum neon_shape rs
;
21332 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21333 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21335 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21337 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21338 N_KEY
| N_F16
| N_F32
).size
;
21339 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21340 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21341 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21342 as_tsktsk (BAD_MVE_SRCDEST
);
21344 neon_three_same (neon_quad (rs
), 0, -1);
21345 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21346 inst
.instruction
|= 0xfc200800;
21347 inst
.instruction
|= rot
<< 23;
21348 inst
.instruction
|= (size
== 32) << 20;
21355 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21356 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21357 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21358 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21359 _("expression too complex"));
21361 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21362 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21363 enum neon_shape rs
;
21364 struct neon_type_el et
;
21365 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21367 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21368 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21372 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21373 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21375 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21376 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21377 "operand makes instruction UNPREDICTABLE"));
21380 if (et
.type
== NT_invtype
)
21383 if (!check_simd_pred_availability (et
.type
== NT_float
,
21384 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21387 if (et
.type
== NT_float
)
21389 neon_three_same (neon_quad (rs
), 0, -1);
21390 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21391 inst
.instruction
|= 0xfc800800;
21392 inst
.instruction
|= (rot
== 270) << 24;
21393 inst
.instruction
|= (et
.size
== 32) << 20;
21397 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21398 inst
.instruction
= 0xfe000f00;
21399 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21400 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21401 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21402 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21403 inst
.instruction
|= (rot
== 270) << 12;
21404 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21405 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21406 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21411 /* Dot Product instructions encoding support. */
21414 do_neon_dotproduct (int unsigned_p
)
21416 enum neon_shape rs
;
21417 unsigned scalar_oprd2
= 0;
21420 if (inst
.cond
!= COND_ALWAYS
)
21421 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21422 "is UNPREDICTABLE"));
21424 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21427 /* Dot Product instructions are in three-same D/Q register format or the third
21428 operand can be a scalar index register. */
21429 if (inst
.operands
[2].isscalar
)
21431 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21432 high8
= 0xfe000000;
21433 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21437 high8
= 0xfc000000;
21438 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21442 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21444 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21446 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21447 Product instruction, so we pass 0 as the "ubit" parameter. And the
21448 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21449 neon_three_same (neon_quad (rs
), 0, 32);
21451 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21452 different NEON three-same encoding. */
21453 inst
.instruction
&= 0x00ffffff;
21454 inst
.instruction
|= high8
;
21455 /* Encode 'U' bit which indicates signedness. */
21456 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21457 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21458 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21459 the instruction encoding. */
21460 if (inst
.operands
[2].isscalar
)
21462 inst
.instruction
&= 0xffffffd0;
21463 inst
.instruction
|= LOW4 (scalar_oprd2
);
21464 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21468 /* Dot Product instructions for signed integer. */
21471 do_neon_dotproduct_s (void)
21473 return do_neon_dotproduct (0);
21476 /* Dot Product instructions for unsigned integer. */
21479 do_neon_dotproduct_u (void)
21481 return do_neon_dotproduct (1);
21487 enum neon_shape rs
;
21488 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21489 if (inst
.operands
[2].isscalar
)
21491 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21492 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21494 inst
.instruction
|= (1 << 25);
21495 int index
= inst
.operands
[2].reg
& 0xf;
21496 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21497 inst
.operands
[2].reg
>>= 4;
21498 constraint (!(inst
.operands
[2].reg
< 16),
21499 _("indexed register must be less than 16"));
21500 neon_three_args (rs
== NS_QQS
);
21501 inst
.instruction
|= (index
<< 5);
21505 inst
.instruction
|= (1 << 21);
21506 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21507 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21508 neon_three_args (rs
== NS_QQQ
);
21515 enum neon_shape rs
;
21516 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21517 if (inst
.operands
[2].isscalar
)
21519 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21520 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21522 inst
.instruction
|= (1 << 25);
21523 int index
= inst
.operands
[2].reg
& 0xf;
21524 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21525 inst
.operands
[2].reg
>>= 4;
21526 constraint (!(inst
.operands
[2].reg
< 16),
21527 _("indexed register must be less than 16"));
21528 neon_three_args (rs
== NS_QQS
);
21529 inst
.instruction
|= (index
<< 5);
21536 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21537 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21539 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21541 neon_three_args (1);
21548 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21549 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21551 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21553 neon_three_args (1);
21557 /* Crypto v1 instructions. */
21559 do_crypto_2op_1 (unsigned elttype
, int op
)
21561 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21563 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
21569 NEON_ENCODE (INTEGER
, inst
);
21570 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21571 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21572 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21573 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21575 inst
.instruction
|= op
<< 6;
21578 inst
.instruction
|= 0xfc000000;
21580 inst
.instruction
|= 0xf0000000;
21584 do_crypto_3op_1 (int u
, int op
)
21586 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21588 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
21589 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
21594 NEON_ENCODE (INTEGER
, inst
);
21595 neon_three_same (1, u
, 8 << op
);
21601 do_crypto_2op_1 (N_8
, 0);
21607 do_crypto_2op_1 (N_8
, 1);
21613 do_crypto_2op_1 (N_8
, 2);
21619 do_crypto_2op_1 (N_8
, 3);
21625 do_crypto_3op_1 (0, 0);
21631 do_crypto_3op_1 (0, 1);
21637 do_crypto_3op_1 (0, 2);
21643 do_crypto_3op_1 (0, 3);
21649 do_crypto_3op_1 (1, 0);
21655 do_crypto_3op_1 (1, 1);
21659 do_sha256su1 (void)
21661 do_crypto_3op_1 (1, 2);
21667 do_crypto_2op_1 (N_32
, -1);
21673 do_crypto_2op_1 (N_32
, 0);
21677 do_sha256su0 (void)
21679 do_crypto_2op_1 (N_32
, 1);
21683 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21685 unsigned int Rd
= inst
.operands
[0].reg
;
21686 unsigned int Rn
= inst
.operands
[1].reg
;
21687 unsigned int Rm
= inst
.operands
[2].reg
;
21689 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21690 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21691 inst
.instruction
|= LOW4 (Rn
) << 16;
21692 inst
.instruction
|= LOW4 (Rm
);
21693 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21694 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21696 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21697 as_warn (UNPRED_REG ("r15"));
21739 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21741 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21742 do_vfp_sp_dp_cvt ();
21743 do_vfp_cond_or_thumb ();
21749 enum neon_shape rs
;
21750 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
21751 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21752 if (inst
.operands
[2].isscalar
)
21754 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21755 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
21757 inst
.instruction
|= (1 << 25);
21758 int index
= inst
.operands
[2].reg
& 0xf;
21759 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21760 inst
.operands
[2].reg
>>= 4;
21761 constraint (!(inst
.operands
[2].reg
< 16),
21762 _("indexed register must be less than 16"));
21763 neon_three_args (rs
== NS_QQS
);
21764 inst
.instruction
|= (index
<< 5);
21768 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21769 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
21770 neon_three_args (rs
== NS_QQQ
);
21777 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21778 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
21780 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
21781 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21783 neon_three_args (1);
21787 /* Overall per-instruction processing. */
21789 /* We need to be able to fix up arbitrary expressions in some statements.
21790 This is so that we can handle symbols that are an arbitrary distance from
21791 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21792 which returns part of an address in a form which will be valid for
21793 a data instruction. We do this by pushing the expression into a symbol
21794 in the expr_section, and creating a fix for that. */
21797 fix_new_arm (fragS
* frag
,
21811 /* Create an absolute valued symbol, so we have something to
21812 refer to in the object file. Unfortunately for us, gas's
21813 generic expression parsing will already have folded out
21814 any use of .set foo/.type foo %function that may have
21815 been used to set type information of the target location,
21816 that's being specified symbolically. We have to presume
21817 the user knows what they are doing. */
21821 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21823 symbol
= symbol_find_or_make (name
);
21824 S_SET_SEGMENT (symbol
, absolute_section
);
21825 symbol_set_frag (symbol
, &zero_address_frag
);
21826 S_SET_VALUE (symbol
, exp
->X_add_number
);
21827 exp
->X_op
= O_symbol
;
21828 exp
->X_add_symbol
= symbol
;
21829 exp
->X_add_number
= 0;
21835 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21836 (enum bfd_reloc_code_real
) reloc
);
21840 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21841 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21845 /* Mark whether the fix is to a THUMB instruction, or an ARM
21847 new_fix
->tc_fix_data
= thumb_mode
;
21850 /* Create a frg for an instruction requiring relaxation. */
21852 output_relax_insn (void)
21858 /* The size of the instruction is unknown, so tie the debug info to the
21859 start of the instruction. */
21860 dwarf2_emit_insn (0);
21862 switch (inst
.relocs
[0].exp
.X_op
)
21865 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21866 offset
= inst
.relocs
[0].exp
.X_add_number
;
21870 offset
= inst
.relocs
[0].exp
.X_add_number
;
21873 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21877 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21878 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21879 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21882 /* Write a 32-bit thumb instruction to buf. */
21884 put_thumb32_insn (char * buf
, unsigned long insn
)
21886 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21887 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21891 output_inst (const char * str
)
21897 as_bad ("%s -- `%s'", inst
.error
, str
);
21902 output_relax_insn ();
21905 if (inst
.size
== 0)
21908 to
= frag_more (inst
.size
);
21909 /* PR 9814: Record the thumb mode into the current frag so that we know
21910 what type of NOP padding to use, if necessary. We override any previous
21911 setting so that if the mode has changed then the NOPS that we use will
21912 match the encoding of the last instruction in the frag. */
21913 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21915 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21917 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21918 put_thumb32_insn (to
, inst
.instruction
);
21920 else if (inst
.size
> INSN_SIZE
)
21922 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21923 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21924 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21927 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21930 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21932 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21933 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21934 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21935 inst
.relocs
[r
].type
);
21938 dwarf2_emit_insn (inst
.size
);
21942 output_it_inst (int cond
, int mask
, char * to
)
21944 unsigned long instruction
= 0xbf00;
21947 instruction
|= mask
;
21948 instruction
|= cond
<< 4;
21952 to
= frag_more (2);
21954 dwarf2_emit_insn (2);
21958 md_number_to_chars (to
, instruction
, 2);
21963 /* Tag values used in struct asm_opcode's tag field. */
21966 OT_unconditional
, /* Instruction cannot be conditionalized.
21967 The ARM condition field is still 0xE. */
21968 OT_unconditionalF
, /* Instruction cannot be conditionalized
21969 and carries 0xF in its ARM condition field. */
21970 OT_csuffix
, /* Instruction takes a conditional suffix. */
21971 OT_csuffixF
, /* Some forms of the instruction take a scalar
21972 conditional suffix, others place 0xF where the
21973 condition field would be, others take a vector
21974 conditional suffix. */
21975 OT_cinfix3
, /* Instruction takes a conditional infix,
21976 beginning at character index 3. (In
21977 unified mode, it becomes a suffix.) */
21978 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21979 tsts, cmps, cmns, and teqs. */
21980 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21981 character index 3, even in unified mode. Used for
21982 legacy instructions where suffix and infix forms
21983 may be ambiguous. */
21984 OT_csuf_or_in3
, /* Instruction takes either a conditional
21985 suffix or an infix at character index 3. */
21986 OT_odd_infix_unc
, /* This is the unconditional variant of an
21987 instruction that takes a conditional infix
21988 at an unusual position. In unified mode,
21989 this variant will accept a suffix. */
21990 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21991 are the conditional variants of instructions that
21992 take conditional infixes in unusual positions.
21993 The infix appears at character index
21994 (tag - OT_odd_infix_0). These are not accepted
21995 in unified mode. */
21998 /* Subroutine of md_assemble, responsible for looking up the primary
21999 opcode from the mnemonic the user wrote. STR points to the
22000 beginning of the mnemonic.
22002 This is not simply a hash table lookup, because of conditional
22003 variants. Most instructions have conditional variants, which are
22004 expressed with a _conditional affix_ to the mnemonic. If we were
22005 to encode each conditional variant as a literal string in the opcode
22006 table, it would have approximately 20,000 entries.
22008 Most mnemonics take this affix as a suffix, and in unified syntax,
22009 'most' is upgraded to 'all'. However, in the divided syntax, some
22010 instructions take the affix as an infix, notably the s-variants of
22011 the arithmetic instructions. Of those instructions, all but six
22012 have the infix appear after the third character of the mnemonic.
22014 Accordingly, the algorithm for looking up primary opcodes given
22017 1. Look up the identifier in the opcode table.
22018 If we find a match, go to step U.
22020 2. Look up the last two characters of the identifier in the
22021 conditions table. If we find a match, look up the first N-2
22022 characters of the identifier in the opcode table. If we
22023 find a match, go to step CE.
22025 3. Look up the fourth and fifth characters of the identifier in
22026 the conditions table. If we find a match, extract those
22027 characters from the identifier, and look up the remaining
22028 characters in the opcode table. If we find a match, go
22033 U. Examine the tag field of the opcode structure, in case this is
22034 one of the six instructions with its conditional infix in an
22035 unusual place. If it is, the tag tells us where to find the
22036 infix; look it up in the conditions table and set inst.cond
22037 accordingly. Otherwise, this is an unconditional instruction.
22038 Again set inst.cond accordingly. Return the opcode structure.
22040 CE. Examine the tag field to make sure this is an instruction that
22041 should receive a conditional suffix. If it is not, fail.
22042 Otherwise, set inst.cond from the suffix we already looked up,
22043 and return the opcode structure.
22045 CM. Examine the tag field to make sure this is an instruction that
22046 should receive a conditional infix after the third character.
22047 If it is not, fail. Otherwise, undo the edits to the current
22048 line of input and proceed as for case CE. */
22050 static const struct asm_opcode
*
22051 opcode_lookup (char **str
)
22055 const struct asm_opcode
*opcode
;
22056 const struct asm_cond
*cond
;
22059 /* Scan up to the end of the mnemonic, which must end in white space,
22060 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
22061 for (base
= end
= *str
; *end
!= '\0'; end
++)
22062 if (*end
== ' ' || *end
== '.')
22068 /* Handle a possible width suffix and/or Neon type suffix. */
22073 /* The .w and .n suffixes are only valid if the unified syntax is in
22075 if (unified_syntax
&& end
[1] == 'w')
22077 else if (unified_syntax
&& end
[1] == 'n')
22082 inst
.vectype
.elems
= 0;
22084 *str
= end
+ offset
;
22086 if (end
[offset
] == '.')
22088 /* See if we have a Neon type suffix (possible in either unified or
22089 non-unified ARM syntax mode). */
22090 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
22093 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
22099 /* Look for unaffixed or special-case affixed mnemonic. */
22100 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22105 if (opcode
->tag
< OT_odd_infix_0
)
22107 inst
.cond
= COND_ALWAYS
;
22111 if (warn_on_deprecated
&& unified_syntax
)
22112 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22113 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
22114 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22117 inst
.cond
= cond
->value
;
22120 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
22122 /* Cannot have a conditional suffix on a mnemonic of less than a character.
22124 if (end
- base
< 2)
22127 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
22128 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22130 /* If this opcode can not be vector predicated then don't accept it with a
22131 vector predication code. */
22132 if (opcode
&& !opcode
->mayBeVecPred
)
22135 if (!opcode
|| !cond
)
22137 /* Cannot have a conditional suffix on a mnemonic of less than two
22139 if (end
- base
< 3)
22142 /* Look for suffixed mnemonic. */
22144 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22145 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22149 if (opcode
&& cond
)
22152 switch (opcode
->tag
)
22154 case OT_cinfix3_legacy
:
22155 /* Ignore conditional suffixes matched on infix only mnemonics. */
22159 case OT_cinfix3_deprecated
:
22160 case OT_odd_infix_unc
:
22161 if (!unified_syntax
)
22163 /* Fall through. */
22167 case OT_csuf_or_in3
:
22168 inst
.cond
= cond
->value
;
22171 case OT_unconditional
:
22172 case OT_unconditionalF
:
22174 inst
.cond
= cond
->value
;
22177 /* Delayed diagnostic. */
22178 inst
.error
= BAD_COND
;
22179 inst
.cond
= COND_ALWAYS
;
22188 /* Cannot have a usual-position infix on a mnemonic of less than
22189 six characters (five would be a suffix). */
22190 if (end
- base
< 6)
22193 /* Look for infixed mnemonic in the usual position. */
22195 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22199 memcpy (save
, affix
, 2);
22200 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
22201 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22203 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
22204 memcpy (affix
, save
, 2);
22207 && (opcode
->tag
== OT_cinfix3
22208 || opcode
->tag
== OT_cinfix3_deprecated
22209 || opcode
->tag
== OT_csuf_or_in3
22210 || opcode
->tag
== OT_cinfix3_legacy
))
22213 if (warn_on_deprecated
&& unified_syntax
22214 && (opcode
->tag
== OT_cinfix3
22215 || opcode
->tag
== OT_cinfix3_deprecated
))
22216 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22218 inst
.cond
= cond
->value
;
22225 /* This function generates an initial IT instruction, leaving its block
22226 virtually open for the new instructions. Eventually,
22227 the mask will be updated by now_pred_add_mask () each time
22228 a new instruction needs to be included in the IT block.
22229 Finally, the block is closed with close_automatic_it_block ().
22230 The block closure can be requested either from md_assemble (),
22231 a tencode (), or due to a label hook. */
22234 new_automatic_it_block (int cond
)
22236 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
22237 now_pred
.mask
= 0x18;
22238 now_pred
.cc
= cond
;
22239 now_pred
.block_length
= 1;
22240 mapping_state (MAP_THUMB
);
22241 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
22242 now_pred
.warn_deprecated
= FALSE
;
22243 now_pred
.insn_cond
= TRUE
;
22246 /* Close an automatic IT block.
22247 See comments in new_automatic_it_block (). */
22250 close_automatic_it_block (void)
22252 now_pred
.mask
= 0x10;
22253 now_pred
.block_length
= 0;
22256 /* Update the mask of the current automatically-generated IT
22257 instruction. See comments in new_automatic_it_block (). */
22260 now_pred_add_mask (int cond
)
22262 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
22263 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
22264 | ((bitvalue) << (nbit)))
22265 const int resulting_bit
= (cond
& 1);
22267 now_pred
.mask
&= 0xf;
22268 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22270 (5 - now_pred
.block_length
));
22271 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22273 ((5 - now_pred
.block_length
) - 1));
22274 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
22277 #undef SET_BIT_VALUE
22280 /* The IT blocks handling machinery is accessed through the these functions:
22281 it_fsm_pre_encode () from md_assemble ()
22282 set_pred_insn_type () optional, from the tencode functions
22283 set_pred_insn_type_last () ditto
22284 in_pred_block () ditto
22285 it_fsm_post_encode () from md_assemble ()
22286 force_automatic_it_block_close () from label handling functions
22289 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22290 initializing the IT insn type with a generic initial value depending
22291 on the inst.condition.
22292 2) During the tencode function, two things may happen:
22293 a) The tencode function overrides the IT insn type by
22294 calling either set_pred_insn_type (type) or
22295 set_pred_insn_type_last ().
22296 b) The tencode function queries the IT block state by
22297 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22299 Both set_pred_insn_type and in_pred_block run the internal FSM state
22300 handling function (handle_pred_state), because: a) setting the IT insn
22301 type may incur in an invalid state (exiting the function),
22302 and b) querying the state requires the FSM to be updated.
22303 Specifically we want to avoid creating an IT block for conditional
22304 branches, so it_fsm_pre_encode is actually a guess and we can't
22305 determine whether an IT block is required until the tencode () routine
22306 has decided what type of instruction this actually it.
22307 Because of this, if set_pred_insn_type and in_pred_block have to be
22308 used, set_pred_insn_type has to be called first.
22310 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22311 that determines the insn IT type depending on the inst.cond code.
22312 When a tencode () routine encodes an instruction that can be
22313 either outside an IT block, or, in the case of being inside, has to be
22314 the last one, set_pred_insn_type_last () will determine the proper
22315 IT instruction type based on the inst.cond code. Otherwise,
22316 set_pred_insn_type can be called for overriding that logic or
22317 for covering other cases.
22319 Calling handle_pred_state () may not transition the IT block state to
22320 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22321 still queried. Instead, if the FSM determines that the state should
22322 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22323 after the tencode () function: that's what it_fsm_post_encode () does.
22325 Since in_pred_block () calls the state handling function to get an
22326 updated state, an error may occur (due to invalid insns combination).
22327 In that case, inst.error is set.
22328 Therefore, inst.error has to be checked after the execution of
22329 the tencode () routine.
22331 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22332 any pending state change (if any) that didn't take place in
22333 handle_pred_state () as explained above. */
22336 it_fsm_pre_encode (void)
22338 if (inst
.cond
!= COND_ALWAYS
)
22339 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22341 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22343 now_pred
.state_handled
= 0;
22346 /* IT state FSM handling function. */
22347 /* MVE instructions and non-MVE instructions are handled differently because of
22348 the introduction of VPT blocks.
22349 Specifications say that any non-MVE instruction inside a VPT block is
22350 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22351 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22352 few exceptions we have MVE_UNPREDICABLE_INSN.
22353 The error messages provided depending on the different combinations possible
22354 are described in the cases below:
22355 For 'most' MVE instructions:
22356 1) In an IT block, with an IT code: syntax error
22357 2) In an IT block, with a VPT code: error: must be in a VPT block
22358 3) In an IT block, with no code: warning: UNPREDICTABLE
22359 4) In a VPT block, with an IT code: syntax error
22360 5) In a VPT block, with a VPT code: OK!
22361 6) In a VPT block, with no code: error: missing code
22362 7) Outside a pred block, with an IT code: error: syntax error
22363 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22364 9) Outside a pred block, with no code: OK!
22365 For non-MVE instructions:
22366 10) In an IT block, with an IT code: OK!
22367 11) In an IT block, with a VPT code: syntax error
22368 12) In an IT block, with no code: error: missing code
22369 13) In a VPT block, with an IT code: error: should be in an IT block
22370 14) In a VPT block, with a VPT code: syntax error
22371 15) In a VPT block, with no code: UNPREDICTABLE
22372 16) Outside a pred block, with an IT code: error: should be in an IT block
22373 17) Outside a pred block, with a VPT code: syntax error
22374 18) Outside a pred block, with no code: OK!
22379 handle_pred_state (void)
22381 now_pred
.state_handled
= 1;
22382 now_pred
.insn_cond
= FALSE
;
22384 switch (now_pred
.state
)
22386 case OUTSIDE_PRED_BLOCK
:
22387 switch (inst
.pred_insn_type
)
22389 case MVE_UNPREDICABLE_INSN
:
22390 case MVE_OUTSIDE_PRED_INSN
:
22391 if (inst
.cond
< COND_ALWAYS
)
22393 /* Case 7: Outside a pred block, with an IT code: error: syntax
22395 inst
.error
= BAD_SYNTAX
;
22398 /* Case 9: Outside a pred block, with no code: OK! */
22400 case OUTSIDE_PRED_INSN
:
22401 if (inst
.cond
> COND_ALWAYS
)
22403 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22405 inst
.error
= BAD_SYNTAX
;
22408 /* Case 18: Outside a pred block, with no code: OK! */
22411 case INSIDE_VPT_INSN
:
22412 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22414 inst
.error
= BAD_OUT_VPT
;
22417 case INSIDE_IT_INSN
:
22418 case INSIDE_IT_LAST_INSN
:
22419 if (inst
.cond
< COND_ALWAYS
)
22421 /* Case 16: Outside a pred block, with an IT code: error: should
22422 be in an IT block. */
22423 if (thumb_mode
== 0)
22426 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22427 as_tsktsk (_("Warning: conditional outside an IT block"\
22432 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22433 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22435 /* Automatically generate the IT instruction. */
22436 new_automatic_it_block (inst
.cond
);
22437 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22438 close_automatic_it_block ();
22442 inst
.error
= BAD_OUT_IT
;
22448 else if (inst
.cond
> COND_ALWAYS
)
22450 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22452 inst
.error
= BAD_SYNTAX
;
22457 case IF_INSIDE_IT_LAST_INSN
:
22458 case NEUTRAL_IT_INSN
:
22462 if (inst
.cond
!= COND_ALWAYS
)
22463 first_error (BAD_SYNTAX
);
22464 now_pred
.state
= MANUAL_PRED_BLOCK
;
22465 now_pred
.block_length
= 0;
22466 now_pred
.type
= VECTOR_PRED
;
22470 now_pred
.state
= MANUAL_PRED_BLOCK
;
22471 now_pred
.block_length
= 0;
22472 now_pred
.type
= SCALAR_PRED
;
22477 case AUTOMATIC_PRED_BLOCK
:
22478 /* Three things may happen now:
22479 a) We should increment current it block size;
22480 b) We should close current it block (closing insn or 4 insns);
22481 c) We should close current it block and start a new one (due
22482 to incompatible conditions or
22483 4 insns-length block reached). */
22485 switch (inst
.pred_insn_type
)
22487 case INSIDE_VPT_INSN
:
22489 case MVE_UNPREDICABLE_INSN
:
22490 case MVE_OUTSIDE_PRED_INSN
:
22492 case OUTSIDE_PRED_INSN
:
22493 /* The closure of the block shall happen immediately,
22494 so any in_pred_block () call reports the block as closed. */
22495 force_automatic_it_block_close ();
22498 case INSIDE_IT_INSN
:
22499 case INSIDE_IT_LAST_INSN
:
22500 case IF_INSIDE_IT_LAST_INSN
:
22501 now_pred
.block_length
++;
22503 if (now_pred
.block_length
> 4
22504 || !now_pred_compatible (inst
.cond
))
22506 force_automatic_it_block_close ();
22507 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
22508 new_automatic_it_block (inst
.cond
);
22512 now_pred
.insn_cond
= TRUE
;
22513 now_pred_add_mask (inst
.cond
);
22516 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
22517 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
22518 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
22519 close_automatic_it_block ();
22522 case NEUTRAL_IT_INSN
:
22523 now_pred
.block_length
++;
22524 now_pred
.insn_cond
= TRUE
;
22526 if (now_pred
.block_length
> 4)
22527 force_automatic_it_block_close ();
22529 now_pred_add_mask (now_pred
.cc
& 1);
22533 close_automatic_it_block ();
22534 now_pred
.state
= MANUAL_PRED_BLOCK
;
22539 case MANUAL_PRED_BLOCK
:
22542 if (now_pred
.type
== SCALAR_PRED
)
22544 /* Check conditional suffixes. */
22545 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
22546 now_pred
.mask
<<= 1;
22547 now_pred
.mask
&= 0x1f;
22548 is_last
= (now_pred
.mask
== 0x10);
22552 now_pred
.cc
^= (now_pred
.mask
>> 4);
22553 cond
= now_pred
.cc
+ 0xf;
22554 now_pred
.mask
<<= 1;
22555 now_pred
.mask
&= 0x1f;
22556 is_last
= now_pred
.mask
== 0x10;
22558 now_pred
.insn_cond
= TRUE
;
22560 switch (inst
.pred_insn_type
)
22562 case OUTSIDE_PRED_INSN
:
22563 if (now_pred
.type
== SCALAR_PRED
)
22565 if (inst
.cond
== COND_ALWAYS
)
22567 /* Case 12: In an IT block, with no code: error: missing
22569 inst
.error
= BAD_NOT_IT
;
22572 else if (inst
.cond
> COND_ALWAYS
)
22574 /* Case 11: In an IT block, with a VPT code: syntax error.
22576 inst
.error
= BAD_SYNTAX
;
22579 else if (thumb_mode
)
22581 /* This is for some special cases where a non-MVE
22582 instruction is not allowed in an IT block, such as cbz,
22583 but are put into one with a condition code.
22584 You could argue this should be a syntax error, but we
22585 gave the 'not allowed in IT block' diagnostic in the
22586 past so we will keep doing so. */
22587 inst
.error
= BAD_NOT_IT
;
22594 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22595 as_tsktsk (MVE_NOT_VPT
);
22598 case MVE_OUTSIDE_PRED_INSN
:
22599 if (now_pred
.type
== SCALAR_PRED
)
22601 if (inst
.cond
== COND_ALWAYS
)
22603 /* Case 3: In an IT block, with no code: warning:
22605 as_tsktsk (MVE_NOT_IT
);
22608 else if (inst
.cond
< COND_ALWAYS
)
22610 /* Case 1: In an IT block, with an IT code: syntax error.
22612 inst
.error
= BAD_SYNTAX
;
22620 if (inst
.cond
< COND_ALWAYS
)
22622 /* Case 4: In a VPT block, with an IT code: syntax error.
22624 inst
.error
= BAD_SYNTAX
;
22627 else if (inst
.cond
== COND_ALWAYS
)
22629 /* Case 6: In a VPT block, with no code: error: missing
22631 inst
.error
= BAD_NOT_VPT
;
22639 case MVE_UNPREDICABLE_INSN
:
22640 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
22642 case INSIDE_IT_INSN
:
22643 if (inst
.cond
> COND_ALWAYS
)
22645 /* Case 11: In an IT block, with a VPT code: syntax error. */
22646 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22647 inst
.error
= BAD_SYNTAX
;
22650 else if (now_pred
.type
== SCALAR_PRED
)
22652 /* Case 10: In an IT block, with an IT code: OK! */
22653 if (cond
!= inst
.cond
)
22655 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
22662 /* Case 13: In a VPT block, with an IT code: error: should be
22664 inst
.error
= BAD_OUT_IT
;
22669 case INSIDE_VPT_INSN
:
22670 if (now_pred
.type
== SCALAR_PRED
)
22672 /* Case 2: In an IT block, with a VPT code: error: must be in a
22674 inst
.error
= BAD_OUT_VPT
;
22677 /* Case 5: In a VPT block, with a VPT code: OK! */
22678 else if (cond
!= inst
.cond
)
22680 inst
.error
= BAD_VPT_COND
;
22684 case INSIDE_IT_LAST_INSN
:
22685 case IF_INSIDE_IT_LAST_INSN
:
22686 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22688 /* Case 4: In a VPT block, with an IT code: syntax error. */
22689 /* Case 11: In an IT block, with a VPT code: syntax error. */
22690 inst
.error
= BAD_SYNTAX
;
22693 else if (cond
!= inst
.cond
)
22695 inst
.error
= BAD_IT_COND
;
22700 inst
.error
= BAD_BRANCH
;
22705 case NEUTRAL_IT_INSN
:
22706 /* The BKPT instruction is unconditional even in a IT or VPT
22711 if (now_pred
.type
== SCALAR_PRED
)
22713 inst
.error
= BAD_IT_IT
;
22716 /* fall through. */
22718 if (inst
.cond
== COND_ALWAYS
)
22720 /* Executing a VPT/VPST instruction inside an IT block or a
22721 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22723 if (now_pred
.type
== SCALAR_PRED
)
22724 as_tsktsk (MVE_NOT_IT
);
22726 as_tsktsk (MVE_NOT_VPT
);
22731 /* VPT/VPST do not accept condition codes. */
22732 inst
.error
= BAD_SYNTAX
;
22743 struct depr_insn_mask
22745 unsigned long pattern
;
22746 unsigned long mask
;
22747 const char* description
;
22750 /* List of 16-bit instruction patterns deprecated in an IT block in
22752 static const struct depr_insn_mask depr_it_insns
[] = {
22753 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22754 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22755 { 0xa000, 0xb800, N_("ADR") },
22756 { 0x4800, 0xf800, N_("Literal loads") },
22757 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22758 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22759 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22760 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22761 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22766 it_fsm_post_encode (void)
22770 if (!now_pred
.state_handled
)
22771 handle_pred_state ();
22773 if (now_pred
.insn_cond
22774 && !now_pred
.warn_deprecated
22775 && warn_on_deprecated
22776 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22777 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22779 if (inst
.instruction
>= 0x10000)
22781 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22782 "performance deprecated in ARMv8-A and ARMv8-R"));
22783 now_pred
.warn_deprecated
= TRUE
;
22787 const struct depr_insn_mask
*p
= depr_it_insns
;
22789 while (p
->mask
!= 0)
22791 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22793 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22794 "instructions of the following class are "
22795 "performance deprecated in ARMv8-A and "
22796 "ARMv8-R: %s"), p
->description
);
22797 now_pred
.warn_deprecated
= TRUE
;
22805 if (now_pred
.block_length
> 1)
22807 as_tsktsk (_("IT blocks containing more than one conditional "
22808 "instruction are performance deprecated in ARMv8-A and "
22810 now_pred
.warn_deprecated
= TRUE
;
22814 is_last
= (now_pred
.mask
== 0x10);
22817 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22823 force_automatic_it_block_close (void)
22825 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22827 close_automatic_it_block ();
22828 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22834 in_pred_block (void)
22836 if (!now_pred
.state_handled
)
22837 handle_pred_state ();
22839 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22842 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22843 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22844 here, hence the "known" in the function name. */
22847 known_t32_only_insn (const struct asm_opcode
*opcode
)
22849 /* Original Thumb-1 wide instruction. */
22850 if (opcode
->tencode
== do_t_blx
22851 || opcode
->tencode
== do_t_branch23
22852 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22853 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22856 /* Wide-only instruction added to ARMv8-M Baseline. */
22857 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22858 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22859 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22860 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22866 /* Whether wide instruction variant can be used if available for a valid OPCODE
22870 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22872 if (known_t32_only_insn (opcode
))
22875 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22876 of variant T3 of B.W is checked in do_t_branch. */
22877 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22878 && opcode
->tencode
== do_t_branch
)
22881 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22882 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22883 && opcode
->tencode
== do_t_mov_cmp
22884 /* Make sure CMP instruction is not affected. */
22885 && opcode
->aencode
== do_mov
)
22888 /* Wide instruction variants of all instructions with narrow *and* wide
22889 variants become available with ARMv6t2. Other opcodes are either
22890 narrow-only or wide-only and are thus available if OPCODE is valid. */
22891 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22894 /* OPCODE with narrow only instruction variant or wide variant not
22900 md_assemble (char *str
)
22903 const struct asm_opcode
* opcode
;
22905 /* Align the previous label if needed. */
22906 if (last_label_seen
!= NULL
)
22908 symbol_set_frag (last_label_seen
, frag_now
);
22909 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22910 S_SET_SEGMENT (last_label_seen
, now_seg
);
22913 memset (&inst
, '\0', sizeof (inst
));
22915 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22916 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22918 opcode
= opcode_lookup (&p
);
22921 /* It wasn't an instruction, but it might be a register alias of
22922 the form alias .req reg, or a Neon .dn/.qn directive. */
22923 if (! create_register_alias (str
, p
)
22924 && ! create_neon_reg_alias (str
, p
))
22925 as_bad (_("bad instruction `%s'"), str
);
22930 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22931 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22933 /* The value which unconditional instructions should have in place of the
22934 condition field. */
22935 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22939 arm_feature_set variant
;
22941 variant
= cpu_variant
;
22942 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22943 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22944 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22945 /* Check that this instruction is supported for this CPU. */
22946 if (!opcode
->tvariant
22947 || (thumb_mode
== 1
22948 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22950 if (opcode
->tencode
== do_t_swi
)
22951 as_bad (_("SVC is not permitted on this architecture"));
22953 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22956 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22957 && opcode
->tencode
!= do_t_branch
)
22959 as_bad (_("Thumb does not support conditional execution"));
22963 /* Two things are addressed here:
22964 1) Implicit require narrow instructions on Thumb-1.
22965 This avoids relaxation accidentally introducing Thumb-2
22967 2) Reject wide instructions in non Thumb-2 cores.
22969 Only instructions with narrow and wide variants need to be handled
22970 but selecting all non wide-only instructions is easier. */
22971 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22972 && !t32_insn_ok (variant
, opcode
))
22974 if (inst
.size_req
== 0)
22976 else if (inst
.size_req
== 4)
22978 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22979 as_bad (_("selected processor does not support 32bit wide "
22980 "variant of instruction `%s'"), str
);
22982 as_bad (_("selected processor does not support `%s' in "
22983 "Thumb-2 mode"), str
);
22988 inst
.instruction
= opcode
->tvalue
;
22990 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22992 /* Prepare the pred_insn_type for those encodings that don't set
22994 it_fsm_pre_encode ();
22996 opcode
->tencode ();
22998 it_fsm_post_encode ();
23001 if (!(inst
.error
|| inst
.relax
))
23003 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
23004 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
23005 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
23007 as_bad (_("cannot honor width suffix -- `%s'"), str
);
23012 /* Something has gone badly wrong if we try to relax a fixed size
23014 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
23016 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23017 *opcode
->tvariant
);
23018 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
23019 set those bits when Thumb-2 32-bit instructions are seen. The impact
23020 of relaxable instructions will be considered later after we finish all
23022 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
23023 variant
= arm_arch_none
;
23025 variant
= cpu_variant
;
23026 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
23027 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23030 check_neon_suffixes
;
23034 mapping_state (MAP_THUMB
);
23037 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23041 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23042 is_bx
= (opcode
->aencode
== do_bx
);
23044 /* Check that this instruction is supported for this CPU. */
23045 if (!(is_bx
&& fix_v4bx
)
23046 && !(opcode
->avariant
&&
23047 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
23049 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
23054 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
23058 inst
.instruction
= opcode
->avalue
;
23059 if (opcode
->tag
== OT_unconditionalF
)
23060 inst
.instruction
|= 0xFU
<< 28;
23062 inst
.instruction
|= inst
.cond
<< 28;
23063 inst
.size
= INSN_SIZE
;
23064 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
23066 it_fsm_pre_encode ();
23067 opcode
->aencode ();
23068 it_fsm_post_encode ();
23070 /* Arm mode bx is marked as both v4T and v5 because it's still required
23071 on a hypothetical non-thumb v5 core. */
23073 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
23075 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
23076 *opcode
->avariant
);
23078 check_neon_suffixes
;
23082 mapping_state (MAP_ARM
);
23087 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
23095 check_pred_blocks_finished (void)
23100 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
23101 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
23102 == MANUAL_PRED_BLOCK
)
23104 if (now_pred
.type
== SCALAR_PRED
)
23105 as_warn (_("section '%s' finished with an open IT block."),
23108 as_warn (_("section '%s' finished with an open VPT/VPST block."),
23112 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
23114 if (now_pred
.type
== SCALAR_PRED
)
23115 as_warn (_("file finished with an open IT block."));
23117 as_warn (_("file finished with an open VPT/VPST block."));
23122 /* Various frobbings of labels and their addresses. */
23125 arm_start_line_hook (void)
23127 last_label_seen
= NULL
;
23131 arm_frob_label (symbolS
* sym
)
23133 last_label_seen
= sym
;
23135 ARM_SET_THUMB (sym
, thumb_mode
);
23137 #if defined OBJ_COFF || defined OBJ_ELF
23138 ARM_SET_INTERWORK (sym
, support_interwork
);
23141 force_automatic_it_block_close ();
23143 /* Note - do not allow local symbols (.Lxxx) to be labelled
23144 as Thumb functions. This is because these labels, whilst
23145 they exist inside Thumb code, are not the entry points for
23146 possible ARM->Thumb calls. Also, these labels can be used
23147 as part of a computed goto or switch statement. eg gcc
23148 can generate code that looks like this:
23150 ldr r2, [pc, .Laaa]
23160 The first instruction loads the address of the jump table.
23161 The second instruction converts a table index into a byte offset.
23162 The third instruction gets the jump address out of the table.
23163 The fourth instruction performs the jump.
23165 If the address stored at .Laaa is that of a symbol which has the
23166 Thumb_Func bit set, then the linker will arrange for this address
23167 to have the bottom bit set, which in turn would mean that the
23168 address computation performed by the third instruction would end
23169 up with the bottom bit set. Since the ARM is capable of unaligned
23170 word loads, the instruction would then load the incorrect address
23171 out of the jump table, and chaos would ensue. */
23172 if (label_is_thumb_function_name
23173 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
23174 && (bfd_section_flags (now_seg
) & SEC_CODE
) != 0)
23176 /* When the address of a Thumb function is taken the bottom
23177 bit of that address should be set. This will allow
23178 interworking between Arm and Thumb functions to work
23181 THUMB_SET_FUNC (sym
, 1);
23183 label_is_thumb_function_name
= FALSE
;
23186 dwarf2_emit_label (sym
);
23190 arm_data_in_code (void)
23192 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
23194 *input_line_pointer
= '/';
23195 input_line_pointer
+= 5;
23196 *input_line_pointer
= 0;
23204 arm_canonicalize_symbol_name (char * name
)
23208 if (thumb_mode
&& (len
= strlen (name
)) > 5
23209 && streq (name
+ len
- 5, "/data"))
23210 *(name
+ len
- 5) = 0;
23215 /* Table of all register names defined by default. The user can
23216 define additional names with .req. Note that all register names
23217 should appear in both upper and lowercase variants. Some registers
23218 also have mixed-case names. */
23220 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
23221 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
23222 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
23223 #define REGSET(p,t) \
23224 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23225 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23226 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23227 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
23228 #define REGSETH(p,t) \
23229 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23230 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23231 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23232 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23233 #define REGSET2(p,t) \
23234 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23235 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23236 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23237 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
23238 #define SPLRBANK(base,bank,t) \
23239 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23240 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23241 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23242 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23243 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23244 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
23246 static const struct reg_entry reg_names
[] =
23248 /* ARM integer registers. */
23249 REGSET(r
, RN
), REGSET(R
, RN
),
23251 /* ATPCS synonyms. */
23252 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
23253 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
23254 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
23256 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
23257 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
23258 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
23260 /* Well-known aliases. */
23261 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
23262 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
23264 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
23265 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
23267 /* Defining the new Zero register from ARMv8.1-M. */
23271 /* Coprocessor numbers. */
23272 REGSET(p
, CP
), REGSET(P
, CP
),
23274 /* Coprocessor register numbers. The "cr" variants are for backward
23276 REGSET(c
, CN
), REGSET(C
, CN
),
23277 REGSET(cr
, CN
), REGSET(CR
, CN
),
23279 /* ARM banked registers. */
23280 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
23281 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
23282 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
23283 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
23284 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
23285 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
23286 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
23288 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
23289 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
23290 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
23291 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
23292 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
23293 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
23294 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
23295 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
23297 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
23298 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
23299 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
23300 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
23301 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
23302 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
23303 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
23304 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23305 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23307 /* FPA registers. */
23308 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
23309 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
23311 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
23312 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
23314 /* VFP SP registers. */
23315 REGSET(s
,VFS
), REGSET(S
,VFS
),
23316 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
23318 /* VFP DP Registers. */
23319 REGSET(d
,VFD
), REGSET(D
,VFD
),
23320 /* Extra Neon DP registers. */
23321 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
23323 /* Neon QP registers. */
23324 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
23326 /* VFP control registers. */
23327 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
23328 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
23329 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
23330 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
23331 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
23332 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
23333 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
23334 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
23335 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
23336 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
23337 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23339 /* Maverick DSP coprocessor registers. */
23340 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23341 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23343 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23344 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23345 REGDEF(dspsc
,0,DSPSC
),
23347 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23348 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23349 REGDEF(DSPSC
,0,DSPSC
),
23351 /* iWMMXt data registers - p0, c0-15. */
23352 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23354 /* iWMMXt control registers - p1, c0-3. */
23355 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23356 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23357 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23358 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23360 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23361 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23362 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23363 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23364 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23366 /* XScale accumulator registers. */
23367 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23373 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23374 within psr_required_here. */
23375 static const struct asm_psr psrs
[] =
23377 /* Backward compatibility notation. Note that "all" is no longer
23378 truly all possible PSR bits. */
23379 {"all", PSR_c
| PSR_f
},
23383 /* Individual flags. */
23389 /* Combinations of flags. */
23390 {"fs", PSR_f
| PSR_s
},
23391 {"fx", PSR_f
| PSR_x
},
23392 {"fc", PSR_f
| PSR_c
},
23393 {"sf", PSR_s
| PSR_f
},
23394 {"sx", PSR_s
| PSR_x
},
23395 {"sc", PSR_s
| PSR_c
},
23396 {"xf", PSR_x
| PSR_f
},
23397 {"xs", PSR_x
| PSR_s
},
23398 {"xc", PSR_x
| PSR_c
},
23399 {"cf", PSR_c
| PSR_f
},
23400 {"cs", PSR_c
| PSR_s
},
23401 {"cx", PSR_c
| PSR_x
},
23402 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23403 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23404 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23405 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23406 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23407 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23408 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23409 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23410 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23411 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23412 {"scf", PSR_s
| PSR_c
| PSR_f
},
23413 {"scx", PSR_s
| PSR_c
| PSR_x
},
23414 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23415 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23416 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23417 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23418 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23419 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23420 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23421 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23422 {"csf", PSR_c
| PSR_s
| PSR_f
},
23423 {"csx", PSR_c
| PSR_s
| PSR_x
},
23424 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23425 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23426 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23427 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23428 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23429 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23430 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23431 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23432 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23433 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23434 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23435 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23436 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23437 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23438 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23439 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23440 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23441 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23442 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23443 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23444 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23445 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23446 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23447 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23448 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23449 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23452 /* Table of V7M psr names. */
23453 static const struct asm_psr v7m_psrs
[] =
23455 {"apsr", 0x0 }, {"APSR", 0x0 },
23456 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23457 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23458 {"psr", 0x3 }, {"PSR", 0x3 },
23459 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23460 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23461 {"epsr", 0x6 }, {"EPSR", 0x6 },
23462 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23463 {"msp", 0x8 }, {"MSP", 0x8 },
23464 {"psp", 0x9 }, {"PSP", 0x9 },
23465 {"msplim", 0xa }, {"MSPLIM", 0xa },
23466 {"psplim", 0xb }, {"PSPLIM", 0xb },
23467 {"primask", 0x10}, {"PRIMASK", 0x10},
23468 {"basepri", 0x11}, {"BASEPRI", 0x11},
23469 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23470 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23471 {"control", 0x14}, {"CONTROL", 0x14},
23472 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23473 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23474 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
23475 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
23476 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
23477 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
23478 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
23479 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
23480 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
23483 /* Table of all shift-in-operand names. */
23484 static const struct asm_shift_name shift_names
[] =
23486 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
23487 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
23488 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
23489 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
23490 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
23491 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
23492 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
23495 /* Table of all explicit relocation names. */
23497 static struct reloc_entry reloc_names
[] =
23499 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
23500 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
23501 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
23502 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
23503 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
23504 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
23505 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
23506 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
23507 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
23508 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
23509 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
23510 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
23511 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
23512 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
23513 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
23514 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
23515 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
23516 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
23517 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
23518 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
23519 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23520 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23521 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
23522 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
23523 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
23524 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
23525 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
23529 /* Table of all conditional affixes. */
23530 static const struct asm_cond conds
[] =
23534 {"cs", 0x2}, {"hs", 0x2},
23535 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
23548 static const struct asm_cond vconds
[] =
23554 #define UL_BARRIER(L,U,CODE,FEAT) \
23555 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
23556 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
23558 static struct asm_barrier_opt barrier_opt_names
[] =
23560 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
23561 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
23562 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
23563 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
23564 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
23565 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
23566 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
23567 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
23568 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
23569 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
23570 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
23571 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
23572 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
23573 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
23574 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
23575 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
23580 /* Table of ARM-format instructions. */
23582 /* Macros for gluing together operand strings. N.B. In all cases
23583 other than OPS0, the trailing OP_stop comes from default
23584 zero-initialization of the unspecified elements of the array. */
23585 #define OPS0() { OP_stop, }
23586 #define OPS1(a) { OP_##a, }
23587 #define OPS2(a,b) { OP_##a,OP_##b, }
23588 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
23589 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
23590 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
23591 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23593 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23594 This is useful when mixing operands for ARM and THUMB, i.e. using the
23595 MIX_ARM_THUMB_OPERANDS macro.
23596 In order to use these macros, prefix the number of operands with _
23598 #define OPS_1(a) { a, }
23599 #define OPS_2(a,b) { a,b, }
23600 #define OPS_3(a,b,c) { a,b,c, }
23601 #define OPS_4(a,b,c,d) { a,b,c,d, }
23602 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23603 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23605 /* These macros abstract out the exact format of the mnemonic table and
23606 save some repeated characters. */
23608 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23609 #define TxCE(mnem, op, top, nops, ops, ae, te) \
23610 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
23611 THUMB_VARIANT, do_##ae, do_##te, 0 }
23613 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23614 a T_MNEM_xyz enumerator. */
23615 #define TCE(mnem, aop, top, nops, ops, ae, te) \
23616 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
23617 #define tCE(mnem, aop, top, nops, ops, ae, te) \
23618 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23620 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23621 infix after the third character. */
23622 #define TxC3(mnem, op, top, nops, ops, ae, te) \
23623 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
23624 THUMB_VARIANT, do_##ae, do_##te, 0 }
23625 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
23626 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
23627 THUMB_VARIANT, do_##ae, do_##te, 0 }
23628 #define TC3(mnem, aop, top, nops, ops, ae, te) \
23629 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
23630 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
23631 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
23632 #define tC3(mnem, aop, top, nops, ops, ae, te) \
23633 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23634 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
23635 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23637 /* Mnemonic that cannot be conditionalized. The ARM condition-code
23638 field is still 0xE. Many of the Thumb variants can be executed
23639 conditionally, so this is checked separately. */
23640 #define TUE(mnem, op, top, nops, ops, ae, te) \
23641 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23642 THUMB_VARIANT, do_##ae, do_##te, 0 }
23644 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23645 Used by mnemonics that have very minimal differences in the encoding for
23646 ARM and Thumb variants and can be handled in a common function. */
23647 #define TUEc(mnem, op, top, nops, ops, en) \
23648 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23649 THUMB_VARIANT, do_##en, do_##en, 0 }
23651 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23652 condition code field. */
23653 #define TUF(mnem, op, top, nops, ops, ae, te) \
23654 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
23655 THUMB_VARIANT, do_##ae, do_##te, 0 }
23657 /* ARM-only variants of all the above. */
23658 #define CE(mnem, op, nops, ops, ae) \
23659 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23661 #define C3(mnem, op, nops, ops, ae) \
23662 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23664 /* Thumb-only variants of TCE and TUE. */
23665 #define ToC(mnem, top, nops, ops, te) \
23666 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23669 #define ToU(mnem, top, nops, ops, te) \
23670 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
23673 /* T_MNEM_xyz enumerator variants of ToC. */
23674 #define toC(mnem, top, nops, ops, te) \
23675 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23678 /* T_MNEM_xyz enumerator variants of ToU. */
23679 #define toU(mnem, top, nops, ops, te) \
23680 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23683 /* Legacy mnemonics that always have conditional infix after the third
23685 #define CL(mnem, op, nops, ops, ae) \
23686 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23687 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23689 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23690 #define cCE(mnem, op, nops, ops, ae) \
23691 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23693 /* mov instructions that are shared between coprocessor and MVE. */
23694 #define mcCE(mnem, op, nops, ops, ae) \
23695 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23697 /* Legacy coprocessor instructions where conditional infix and conditional
23698 suffix are ambiguous. For consistency this includes all FPA instructions,
23699 not just the potentially ambiguous ones. */
23700 #define cCL(mnem, op, nops, ops, ae) \
23701 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23702 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23704 /* Coprocessor, takes either a suffix or a position-3 infix
23705 (for an FPA corner case). */
23706 #define C3E(mnem, op, nops, ops, ae) \
23707 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23708 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23710 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23711 { m1 #m2 m3, OPS##nops ops, \
23712 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23713 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23715 #define CM(m1, m2, op, nops, ops, ae) \
23716 xCM_ (m1, , m2, op, nops, ops, ae), \
23717 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23718 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23719 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23720 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23721 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23722 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23723 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23724 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23725 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23726 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23727 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23728 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23729 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23730 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23731 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23732 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23733 xCM_ (m1, le, m2, op, nops, ops, ae), \
23734 xCM_ (m1, al, m2, op, nops, ops, ae)
23736 #define UE(mnem, op, nops, ops, ae) \
23737 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23739 #define UF(mnem, op, nops, ops, ae) \
23740 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23742 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23743 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23744 use the same encoding function for each. */
23745 #define NUF(mnem, op, nops, ops, enc) \
23746 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23747 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23749 /* Neon data processing, version which indirects through neon_enc_tab for
23750 the various overloaded versions of opcodes. */
23751 #define nUF(mnem, op, nops, ops, enc) \
23752 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23753 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23755 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23757 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23758 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23759 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23761 #define NCE(mnem, op, nops, ops, enc) \
23762 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23764 #define NCEF(mnem, op, nops, ops, enc) \
23765 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23767 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23768 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23769 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23770 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23772 #define nCE(mnem, op, nops, ops, enc) \
23773 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23775 #define nCEF(mnem, op, nops, ops, enc) \
23776 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23779 #define mCEF(mnem, op, nops, ops, enc) \
23780 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23781 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23784 /* nCEF but for MVE predicated instructions. */
23785 #define mnCEF(mnem, op, nops, ops, enc) \
23786 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23788 /* nCE but for MVE predicated instructions. */
23789 #define mnCE(mnem, op, nops, ops, enc) \
23790 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23792 /* NUF but for potentially MVE predicated instructions. */
23793 #define MNUF(mnem, op, nops, ops, enc) \
23794 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23795 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23797 /* nUF but for potentially MVE predicated instructions. */
23798 #define mnUF(mnem, op, nops, ops, enc) \
23799 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23800 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23802 /* ToC but for potentially MVE predicated instructions. */
23803 #define mToC(mnem, top, nops, ops, te) \
23804 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23807 /* NCE but for MVE predicated instructions. */
23808 #define MNCE(mnem, op, nops, ops, enc) \
23809 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23811 /* NCEF but for MVE predicated instructions. */
23812 #define MNCEF(mnem, op, nops, ops, enc) \
23813 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23816 static const struct asm_opcode insns
[] =
23818 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23819 #define THUMB_VARIANT & arm_ext_v4t
23820 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23821 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23822 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23823 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23824 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23825 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23826 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23827 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23828 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23829 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23830 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23831 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23832 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23833 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23834 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23835 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23837 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23838 for setting PSR flag bits. They are obsolete in V6 and do not
23839 have Thumb equivalents. */
23840 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23841 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23842 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23843 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23844 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23845 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23846 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23847 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23848 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23850 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23851 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23852 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23853 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23855 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23856 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23857 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23859 OP_ADDRGLDR
),ldst
, t_ldst
),
23860 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23862 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23863 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23864 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23865 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23866 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23867 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23869 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23870 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23873 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23874 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23875 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23876 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23878 /* Thumb-compatibility pseudo ops. */
23879 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23880 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23881 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23882 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23883 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23884 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23885 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23886 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23887 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23888 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23889 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23890 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23892 /* These may simplify to neg. */
23893 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23894 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23896 #undef THUMB_VARIANT
23897 #define THUMB_VARIANT & arm_ext_os
23899 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23900 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23902 #undef THUMB_VARIANT
23903 #define THUMB_VARIANT & arm_ext_v6
23905 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23907 /* V1 instructions with no Thumb analogue prior to V6T2. */
23908 #undef THUMB_VARIANT
23909 #define THUMB_VARIANT & arm_ext_v6t2
23911 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23912 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23913 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23915 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23916 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23917 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23918 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23920 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23921 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23923 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23924 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23926 /* V1 instructions with no Thumb analogue at all. */
23927 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23928 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23930 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23931 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23932 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23933 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23934 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23935 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23936 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23937 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23940 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23941 #undef THUMB_VARIANT
23942 #define THUMB_VARIANT & arm_ext_v4t
23944 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23945 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23947 #undef THUMB_VARIANT
23948 #define THUMB_VARIANT & arm_ext_v6t2
23950 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23951 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23953 /* Generic coprocessor instructions. */
23954 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23955 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23956 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23957 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23958 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23959 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23960 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23963 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23965 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23966 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23969 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23970 #undef THUMB_VARIANT
23971 #define THUMB_VARIANT & arm_ext_msr
23973 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23974 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23977 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23978 #undef THUMB_VARIANT
23979 #define THUMB_VARIANT & arm_ext_v6t2
23981 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23982 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23983 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23984 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23985 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23986 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23987 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23988 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23991 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23992 #undef THUMB_VARIANT
23993 #define THUMB_VARIANT & arm_ext_v4t
23995 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23996 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23997 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23998 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23999 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24000 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24003 #define ARM_VARIANT & arm_ext_v4t_5
24005 /* ARM Architecture 4T. */
24006 /* Note: bx (and blx) are required on V5, even if the processor does
24007 not support Thumb. */
24008 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
24011 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
24012 #undef THUMB_VARIANT
24013 #define THUMB_VARIANT & arm_ext_v5t
24015 /* Note: blx has 2 variants; the .value coded here is for
24016 BLX(2). Only this variant has conditional execution. */
24017 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
24018 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
24020 #undef THUMB_VARIANT
24021 #define THUMB_VARIANT & arm_ext_v6t2
24023 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
24024 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24025 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24026 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24027 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24028 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24029 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24030 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24033 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
24034 #undef THUMB_VARIANT
24035 #define THUMB_VARIANT & arm_ext_v5exp
24037 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24038 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24039 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24040 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24042 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24043 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24045 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24046 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24047 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24048 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24050 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24051 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24052 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24053 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24055 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24056 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24058 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24059 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24060 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24061 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24064 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
24065 #undef THUMB_VARIANT
24066 #define THUMB_VARIANT & arm_ext_v6t2
24068 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
24069 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
24071 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
24072 ADDRGLDRS
), ldrd
, t_ldstd
),
24074 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24075 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24078 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
24080 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
24083 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
24084 #undef THUMB_VARIANT
24085 #define THUMB_VARIANT & arm_ext_v6
24087 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24088 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24089 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24090 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24091 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24092 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24093 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24094 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24095 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24096 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
24098 #undef THUMB_VARIANT
24099 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24101 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
24102 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24104 #undef THUMB_VARIANT
24105 #define THUMB_VARIANT & arm_ext_v6t2
24107 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24108 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24110 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
24111 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
24113 /* ARM V6 not included in V7M. */
24114 #undef THUMB_VARIANT
24115 #define THUMB_VARIANT & arm_ext_v6_notm
24116 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24117 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24118 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
24119 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
24120 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24121 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24122 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
24123 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24124 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
24125 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24126 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24127 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24128 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24129 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24130 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
24131 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
24132 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24133 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24134 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
24136 /* ARM V6 not included in V7M (eg. integer SIMD). */
24137 #undef THUMB_VARIANT
24138 #define THUMB_VARIANT & arm_ext_v6_dsp
24139 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
24140 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
24141 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24142 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24143 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24144 /* Old name for QASX. */
24145 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24146 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24147 /* Old name for QSAX. */
24148 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24149 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24150 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24151 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24152 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24153 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24154 /* Old name for SASX. */
24155 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24156 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24157 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24158 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24159 /* Old name for SHASX. */
24160 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24161 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24162 /* Old name for SHSAX. */
24163 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24164 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24165 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24166 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24167 /* Old name for SSAX. */
24168 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24169 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24170 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24171 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24172 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24173 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24174 /* Old name for UASX. */
24175 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24176 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24177 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24178 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24179 /* Old name for UHASX. */
24180 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24181 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24182 /* Old name for UHSAX. */
24183 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24184 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24185 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24186 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24187 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24188 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24189 /* Old name for UQASX. */
24190 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24191 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24192 /* Old name for UQSAX. */
24193 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24194 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24195 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24196 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24197 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24198 /* Old name for USAX. */
24199 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24200 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24201 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24202 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24203 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24204 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24205 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24206 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24207 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24208 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24209 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24210 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24211 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24212 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24213 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24214 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24215 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24216 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24217 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24218 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24219 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24220 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24221 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24222 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24223 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24224 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24225 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24226 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24227 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24228 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
24229 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
24230 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24231 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24232 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
24235 #define ARM_VARIANT & arm_ext_v6k_v6t2
24236 #undef THUMB_VARIANT
24237 #define THUMB_VARIANT & arm_ext_v6k_v6t2
24239 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
24240 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
24241 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
24242 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
24244 #undef THUMB_VARIANT
24245 #define THUMB_VARIANT & arm_ext_v6_notm
24246 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
24248 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
24249 RRnpcb
), strexd
, t_strexd
),
24251 #undef THUMB_VARIANT
24252 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24253 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
24255 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
24257 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24259 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24261 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
24264 #define ARM_VARIANT & arm_ext_sec
24265 #undef THUMB_VARIANT
24266 #define THUMB_VARIANT & arm_ext_sec
24268 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
24271 #define ARM_VARIANT & arm_ext_virt
24272 #undef THUMB_VARIANT
24273 #define THUMB_VARIANT & arm_ext_virt
24275 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
24276 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
24279 #define ARM_VARIANT & arm_ext_pan
24280 #undef THUMB_VARIANT
24281 #define THUMB_VARIANT & arm_ext_pan
24283 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
24286 #define ARM_VARIANT & arm_ext_v6t2
24287 #undef THUMB_VARIANT
24288 #define THUMB_VARIANT & arm_ext_v6t2
24290 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
24291 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
24292 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24293 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24295 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24296 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
24298 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24299 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24300 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24301 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24304 #define ARM_VARIANT & arm_ext_v3
24305 #undef THUMB_VARIANT
24306 #define THUMB_VARIANT & arm_ext_v6t2
24308 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
24309 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
24310 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
24313 #define ARM_VARIANT & arm_ext_v6t2
24314 #undef THUMB_VARIANT
24315 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24316 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24317 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24319 /* Thumb-only instructions. */
24321 #define ARM_VARIANT NULL
24322 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
24323 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
24325 /* ARM does not really have an IT instruction, so always allow it.
24326 The opcode is copied from Thumb in order to allow warnings in
24327 -mimplicit-it=[never | arm] modes. */
24329 #define ARM_VARIANT & arm_ext_v1
24330 #undef THUMB_VARIANT
24331 #define THUMB_VARIANT & arm_ext_v6t2
24333 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
24334 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
24335 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
24336 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
24337 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
24338 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24339 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24340 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24341 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24342 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24343 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24344 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24345 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24346 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24347 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24348 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24349 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24350 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24352 /* Thumb2 only instructions. */
24354 #define ARM_VARIANT NULL
24356 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24357 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24358 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24359 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24360 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24361 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24363 /* Hardware division instructions. */
24365 #define ARM_VARIANT & arm_ext_adiv
24366 #undef THUMB_VARIANT
24367 #define THUMB_VARIANT & arm_ext_div
24369 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24370 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24372 /* ARM V6M/V7 instructions. */
24374 #define ARM_VARIANT & arm_ext_barrier
24375 #undef THUMB_VARIANT
24376 #define THUMB_VARIANT & arm_ext_barrier
24378 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24379 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24380 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24382 /* ARM V7 instructions. */
24384 #define ARM_VARIANT & arm_ext_v7
24385 #undef THUMB_VARIANT
24386 #define THUMB_VARIANT & arm_ext_v7
24388 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24389 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24392 #define ARM_VARIANT & arm_ext_mp
24393 #undef THUMB_VARIANT
24394 #define THUMB_VARIANT & arm_ext_mp
24396 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24398 /* AArchv8 instructions. */
24400 #define ARM_VARIANT & arm_ext_v8
24402 /* Instructions shared between armv8-a and armv8-m. */
24403 #undef THUMB_VARIANT
24404 #define THUMB_VARIANT & arm_ext_atomics
24406 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24407 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24408 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24409 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24410 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24411 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24412 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24413 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24414 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24415 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24417 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24419 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24421 #undef THUMB_VARIANT
24422 #define THUMB_VARIANT & arm_ext_v8
24424 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24425 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24427 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24430 /* Defined in V8 but is in undefined encoding space for earlier
24431 architectures. However earlier architectures are required to treat
24432 this instuction as a semihosting trap as well. Hence while not explicitly
24433 defined as such, it is in fact correct to define the instruction for all
24435 #undef THUMB_VARIANT
24436 #define THUMB_VARIANT & arm_ext_v1
24438 #define ARM_VARIANT & arm_ext_v1
24439 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24441 /* ARMv8 T32 only. */
24443 #define ARM_VARIANT NULL
24444 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24445 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24446 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24448 /* FP for ARMv8. */
24450 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24451 #undef THUMB_VARIANT
24452 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24454 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24455 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24456 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24457 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24458 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24459 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24460 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24461 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24462 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
24463 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
24464 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
24466 /* Crypto v1 extensions. */
24468 #define ARM_VARIANT & fpu_crypto_ext_armv8
24469 #undef THUMB_VARIANT
24470 #define THUMB_VARIANT & fpu_crypto_ext_armv8
24472 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
24473 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
24474 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
24475 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
24476 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
24477 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
24478 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
24479 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
24480 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
24481 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
24482 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
24483 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
24484 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
24485 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
24488 #define ARM_VARIANT & crc_ext_armv8
24489 #undef THUMB_VARIANT
24490 #define THUMB_VARIANT & crc_ext_armv8
24491 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
24492 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
24493 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
24494 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
24495 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
24496 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
24498 /* ARMv8.2 RAS extension. */
24500 #define ARM_VARIANT & arm_ext_ras
24501 #undef THUMB_VARIANT
24502 #define THUMB_VARIANT & arm_ext_ras
24503 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
24506 #define ARM_VARIANT & arm_ext_v8_3
24507 #undef THUMB_VARIANT
24508 #define THUMB_VARIANT & arm_ext_v8_3
24509 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
24512 #define ARM_VARIANT & fpu_neon_ext_dotprod
24513 #undef THUMB_VARIANT
24514 #define THUMB_VARIANT & fpu_neon_ext_dotprod
24515 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
24516 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
24519 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
24520 #undef THUMB_VARIANT
24521 #define THUMB_VARIANT NULL
24523 cCE("wfs", e200110
, 1, (RR
), rd
),
24524 cCE("rfs", e300110
, 1, (RR
), rd
),
24525 cCE("wfc", e400110
, 1, (RR
), rd
),
24526 cCE("rfc", e500110
, 1, (RR
), rd
),
24528 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24529 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24530 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24531 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24533 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24534 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24535 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24536 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24538 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
24539 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
24540 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
24541 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
24542 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
24543 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
24544 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
24545 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
24546 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
24547 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
24548 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
24549 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
24551 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
24552 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
24553 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
24554 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
24555 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
24556 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
24557 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
24558 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
24559 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
24560 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
24561 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
24562 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
24564 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
24565 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
24566 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
24567 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
24568 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
24569 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
24570 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
24571 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
24572 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
24573 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
24574 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
24575 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
24577 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
24578 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
24579 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
24580 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
24581 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
24582 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
24583 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
24584 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
24585 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
24586 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
24587 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
24588 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
24590 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
24591 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
24592 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
24593 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
24594 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
24595 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
24596 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
24597 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
24598 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
24599 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
24600 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
24601 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
24603 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
24604 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
24605 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
24606 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
24607 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
24608 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
24609 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
24610 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
24611 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
24612 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
24613 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
24614 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
24616 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
24617 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
24618 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
24619 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
24620 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
24621 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
24622 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
24623 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
24624 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
24625 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
24626 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
24627 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
24629 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
24630 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
24631 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
24632 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
24633 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
24634 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
24635 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
24636 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
24637 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
24638 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
24639 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
24640 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
24642 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
24643 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
24644 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
24645 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
24646 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
24647 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
24648 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
24649 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
24650 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
24651 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
24652 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
24653 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
24655 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
24656 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
24657 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
24658 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
24659 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
24660 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
24661 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
24662 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
24663 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
24664 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
24665 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
24666 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
24668 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
24669 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
24670 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
24671 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
24672 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
24673 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
24674 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
24675 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
24676 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24677 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24678 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24679 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24681 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24682 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24683 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24684 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24685 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24686 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24687 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24688 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24689 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24690 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24691 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24692 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24694 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24695 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24696 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24697 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24698 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24699 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24700 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24701 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24702 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24703 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24704 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24705 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24707 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24708 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24709 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24710 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24711 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24712 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24713 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24714 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24715 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24716 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24717 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24718 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24720 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24721 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24722 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24723 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24724 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24725 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24726 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24727 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24728 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24729 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24730 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24731 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24733 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24734 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24735 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24736 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24737 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24738 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24739 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24740 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24741 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24742 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24743 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24744 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24746 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24747 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24748 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24749 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24750 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24751 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24752 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24753 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24754 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24755 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24756 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24757 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24759 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24760 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24761 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24762 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24763 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24764 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24765 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24766 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24767 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24768 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24769 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24770 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24772 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24773 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24774 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24775 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24776 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24777 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24778 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24779 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24780 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24781 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24782 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24783 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24785 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24786 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24787 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24788 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24789 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24790 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24791 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24792 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24793 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24794 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24795 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24796 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24798 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24799 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24800 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24801 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24802 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24803 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24804 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24805 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24806 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24807 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24808 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24809 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24811 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24812 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24813 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24814 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24815 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24816 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24817 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24818 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24819 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24820 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24821 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24822 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24824 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24825 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24826 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24827 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24828 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24829 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24830 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24831 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24832 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24833 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24834 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24835 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24837 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24838 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24839 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24840 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24841 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24842 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24843 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24844 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24845 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24846 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24847 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24848 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24850 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24851 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24852 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24853 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24854 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24855 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24856 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24857 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24858 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24859 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24860 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24861 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24863 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24864 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24865 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24866 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24867 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24868 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24869 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24870 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24871 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24872 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24873 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24874 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24876 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24877 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24878 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24879 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24880 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24881 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24882 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24883 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24884 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24885 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24886 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24887 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24889 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24890 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24891 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24892 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24893 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24894 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24895 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24896 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24897 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24898 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24899 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24900 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24902 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24903 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24904 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24905 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24906 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24907 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24908 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24909 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24910 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24911 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24912 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24913 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24915 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24916 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24917 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24918 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24920 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24921 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24922 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24923 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24924 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24925 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24926 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24927 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24928 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24929 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24930 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24931 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24933 /* The implementation of the FIX instruction is broken on some
24934 assemblers, in that it accepts a precision specifier as well as a
24935 rounding specifier, despite the fact that this is meaningless.
24936 To be more compatible, we accept it as well, though of course it
24937 does not set any bits. */
24938 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24939 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24940 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24941 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24942 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24943 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24944 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24945 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24946 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24947 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24948 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24949 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24950 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24952 /* Instructions that were new with the real FPA, call them V2. */
24954 #define ARM_VARIANT & fpu_fpa_ext_v2
24956 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24957 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24958 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24959 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24960 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24961 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24964 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24965 #undef THUMB_VARIANT
24966 #define THUMB_VARIANT & arm_ext_v6t2
24967 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24968 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
24969 #undef THUMB_VARIANT
24971 /* Moves and type conversions. */
24972 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24973 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24974 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24975 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24976 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24977 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24978 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24979 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24980 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24982 /* Memory operations. */
24983 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24984 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24985 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24986 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24987 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24988 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24989 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24990 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24991 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24992 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24993 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24994 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24995 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24996 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24997 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24998 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24999 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25000 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25002 /* Monadic operations. */
25003 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25004 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25005 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25007 /* Dyadic operations. */
25008 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25009 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25010 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25011 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25012 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25013 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25014 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25015 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25016 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25019 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25020 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
25021 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25022 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
25024 /* Double precision load/store are still present on single precision
25025 implementations. */
25026 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25027 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25028 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25029 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25030 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25031 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25032 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25033 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25034 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25035 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25038 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
25040 /* Moves and type conversions. */
25041 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25042 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25043 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25044 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25045 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25046 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25047 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25048 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25049 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25050 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25051 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25052 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25054 /* Monadic operations. */
25055 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25056 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25057 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25059 /* Dyadic operations. */
25060 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25061 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25062 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25063 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25064 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25065 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25066 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25067 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25068 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25071 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25072 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
25073 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25074 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
25076 /* Instructions which may belong to either the Neon or VFP instruction sets.
25077 Individual encoder functions perform additional architecture checks. */
25079 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25080 #undef THUMB_VARIANT
25081 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
25083 /* These mnemonics are unique to VFP. */
25084 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
25085 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
25086 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25087 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25088 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25089 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
25090 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
25091 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
25093 /* Mnemonics shared by Neon and VFP. */
25094 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
25096 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25097 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25098 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25099 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25100 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25101 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25103 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
25104 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
25105 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
25106 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
25109 /* NOTE: All VMOV encoding is special-cased! */
25110 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
25112 #undef THUMB_VARIANT
25113 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
25114 by different feature bits. Since we are setting the Thumb guard, we can
25115 require Thumb-1 which makes it a nop guard and set the right feature bit in
25116 do_vldr_vstr (). */
25117 #define THUMB_VARIANT & arm_ext_v4t
25118 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25119 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25122 #define ARM_VARIANT & arm_ext_fp16
25123 #undef THUMB_VARIANT
25124 #define THUMB_VARIANT & arm_ext_fp16
25125 /* New instructions added from v8.2, allowing the extraction and insertion of
25126 the upper 16 bits of a 32-bit vector register. */
25127 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
25128 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
25130 /* New backported fma/fms instructions optional in v8.2. */
25131 NUF (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
25132 NUF (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
25134 #undef THUMB_VARIANT
25135 #define THUMB_VARIANT & fpu_neon_ext_v1
25137 #define ARM_VARIANT & fpu_neon_ext_v1
25139 /* Data processing with three registers of the same length. */
25140 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
25141 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
25142 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
25143 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25144 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25145 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25146 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
25147 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25148 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25149 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25150 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25151 /* If not immediate, fall back to neon_dyadic_i64_su.
25152 shl should accept I8 I16 I32 I64,
25153 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
25154 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
25155 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
25156 /* Logic ops, types optional & ignored. */
25157 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25158 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25159 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25160 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25161 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
25162 /* Bitfield ops, untyped. */
25163 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25164 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25165 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25166 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25167 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25168 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25169 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
25170 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25171 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25172 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25173 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25174 back to neon_dyadic_if_su. */
25175 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25176 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25177 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25178 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25179 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25180 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25181 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25182 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25183 /* Comparison. Type I8 I16 I32 F32. */
25184 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
25185 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
25186 /* As above, D registers only. */
25187 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25188 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25189 /* Int and float variants, signedness unimportant. */
25190 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25191 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25192 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
25193 /* Add/sub take types I8 I16 I32 I64 F32. */
25194 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25195 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25196 /* vtst takes sizes 8, 16, 32. */
25197 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
25198 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
25199 /* VMUL takes I8 I16 I32 F32 P8. */
25200 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
25201 /* VQD{R}MULH takes S16 S32. */
25202 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25203 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25204 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25205 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25206 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25207 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25208 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25209 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25210 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25211 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25212 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25213 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25214 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25215 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25216 /* ARM v8.1 extension. */
25217 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25218 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
25219 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25221 /* Two address, int/float. Types S8 S16 S32 F32. */
25222 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25223 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25225 /* Data processing with two registers and a shift amount. */
25226 /* Right shifts, and variants with rounding.
25227 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
25228 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25229 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25230 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25231 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25232 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25233 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25234 /* Shift and insert. Sizes accepted 8 16 32 64. */
25235 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
25236 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
25237 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
25238 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
25239 /* Right shift immediate, saturating & narrowing, with rounding variants.
25240 Types accepted S16 S32 S64 U16 U32 U64. */
25241 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25242 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25243 /* As above, unsigned. Types accepted S16 S32 S64. */
25244 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25245 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25246 /* Right shift narrowing. Types accepted I16 I32 I64. */
25247 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25248 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25249 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
25250 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
25251 /* CVT with optional immediate for fixed-point variant. */
25252 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
25254 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
25256 /* Data processing, three registers of different lengths. */
25257 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
25258 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
25259 /* If not scalar, fall back to neon_dyadic_long.
25260 Vector types as above, scalar types S16 S32 U16 U32. */
25261 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25262 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25263 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
25264 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25265 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25266 /* Dyadic, narrowing insns. Types I16 I32 I64. */
25267 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25268 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25269 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25270 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25271 /* Saturating doubling multiplies. Types S16 S32. */
25272 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25273 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25274 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25275 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25276 S16 S32 U16 U32. */
25277 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
25279 /* Extract. Size 8. */
25280 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
25281 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
25283 /* Two registers, miscellaneous. */
25284 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
25285 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
25286 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
25287 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
25288 /* Vector replicate. Sizes 8 16 32. */
25289 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
25290 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25291 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
25292 /* VMOVN. Types I16 I32 I64. */
25293 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
25294 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25295 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
25296 /* VQMOVUN. Types S16 S32 S64. */
25297 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
25298 /* VZIP / VUZP. Sizes 8 16 32. */
25299 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25300 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25301 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25302 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25303 /* VQABS / VQNEG. Types S8 S16 S32. */
25304 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25305 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25306 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25307 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25308 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
25309 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25310 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
25311 /* Reciprocal estimates. Types U32 F16 F32. */
25312 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25313 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
25314 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25315 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
25316 /* VCLS. Types S8 S16 S32. */
25317 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
25318 /* VCLZ. Types I8 I16 I32. */
25319 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
25320 /* VCNT. Size 8. */
25321 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
25322 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
25323 /* Two address, untyped. */
25324 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
25325 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
25326 /* VTRN. Sizes 8 16 32. */
25327 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
25328 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
25330 /* Table lookup. Size 8. */
25331 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25332 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25334 #undef THUMB_VARIANT
25335 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25337 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25339 /* Neon element/structure load/store. */
25340 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25341 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25342 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25343 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25344 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25345 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25346 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25347 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25349 #undef THUMB_VARIANT
25350 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25352 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25353 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25354 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25355 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25356 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25357 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25358 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25359 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25360 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25361 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25363 #undef THUMB_VARIANT
25364 #define THUMB_VARIANT & fpu_vfp_ext_v3
25366 #define ARM_VARIANT & fpu_vfp_ext_v3
25368 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25369 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25370 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25371 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25372 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25373 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25374 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25375 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25376 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25379 #define ARM_VARIANT & fpu_vfp_ext_fma
25380 #undef THUMB_VARIANT
25381 #define THUMB_VARIANT & fpu_vfp_ext_fma
25382 /* Mnemonics shared by Neon, VFP, MVE and BF16. These are included in the
25383 VFP FMA variant; NEON and VFP FMA always includes the NEON
25384 FMA instructions. */
25385 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25386 TUF ("vfmat", c300850
, fc300850
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), mve_vfma
, mve_vfma
),
25387 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25389 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25390 the v form should always be used. */
25391 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25392 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25393 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25394 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25395 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25396 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25398 #undef THUMB_VARIANT
25400 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25402 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25403 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25404 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25405 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25406 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25407 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25408 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25409 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25412 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25414 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25415 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25416 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25417 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25418 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25419 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25420 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25421 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25422 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25423 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25424 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25425 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25426 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25427 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25428 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25429 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25430 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25431 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25432 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25433 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25434 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25435 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25436 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25437 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25438 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25439 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25440 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25441 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25442 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25443 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25444 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25445 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25446 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25447 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25448 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25449 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25450 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25451 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25452 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25453 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25454 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25455 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25456 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25457 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25458 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25459 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25460 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
25461 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25462 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25463 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25464 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25465 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25466 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25467 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25468 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25469 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25470 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25471 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25472 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25473 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25474 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25475 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25476 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25477 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25478 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25479 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25480 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25481 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25482 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25483 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25484 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25485 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25486 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25487 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25488 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25489 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25490 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25491 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25492 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25493 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25494 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25495 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25496 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25497 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25498 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25499 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25500 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25501 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25502 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
25503 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25504 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25505 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25506 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25507 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25508 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25509 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25510 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25511 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25512 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25513 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25514 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25515 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25516 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25517 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25518 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25519 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25520 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25521 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25522 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25523 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25524 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
25525 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25526 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25527 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25528 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25529 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25530 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25531 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25532 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25533 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25534 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25535 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25536 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25537 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25538 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25539 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25540 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25541 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25542 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25543 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25544 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25545 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25546 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25547 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25548 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25549 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25550 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25551 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25552 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25553 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25554 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25555 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25556 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25557 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25558 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25559 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25560 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25561 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25562 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25563 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25564 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25565 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25566 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25567 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25568 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25569 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25570 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25571 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25572 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25573 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25574 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25575 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
25578 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
25580 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
25581 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
25582 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
25583 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25584 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25585 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25586 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25587 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25588 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25589 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25590 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25591 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25592 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25593 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25594 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25595 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25596 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25597 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25598 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25599 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25600 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
25601 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25602 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25603 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25604 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25605 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25606 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25607 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25608 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25609 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25610 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25611 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25612 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25613 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25614 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25615 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25616 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25617 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25618 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25619 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25620 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25621 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25622 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25623 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25624 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25625 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25626 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25627 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25628 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25629 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25630 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25631 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25632 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25633 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25634 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25635 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25636 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25639 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25641 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25642 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25643 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25644 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25645 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25646 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25647 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25648 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25649 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
25650 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
25651 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
25652 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
25653 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
25654 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
25655 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
25656 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
25657 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
25658 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
25659 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
25660 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
25661 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
25662 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
25663 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
25664 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
25665 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
25666 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
25667 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
25668 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
25669 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
25670 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
25671 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
25672 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
25673 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
25674 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
25675 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
25676 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
25677 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
25678 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
25679 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
25680 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25681 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25682 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25683 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25684 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25685 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25686 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25687 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25688 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25689 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25690 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25691 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25692 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25693 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25694 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25695 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25696 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25697 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25698 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25699 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25700 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25701 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25702 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25703 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25704 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25705 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25706 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25707 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25708 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25709 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25710 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25711 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25712 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25713 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25714 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25715 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25716 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25718 /* ARMv8.5-A instructions. */
25720 #define ARM_VARIANT & arm_ext_sb
25721 #undef THUMB_VARIANT
25722 #define THUMB_VARIANT & arm_ext_sb
25723 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25726 #define ARM_VARIANT & arm_ext_predres
25727 #undef THUMB_VARIANT
25728 #define THUMB_VARIANT & arm_ext_predres
25729 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25730 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25731 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25733 /* ARMv8-M instructions. */
25735 #define ARM_VARIANT NULL
25736 #undef THUMB_VARIANT
25737 #define THUMB_VARIANT & arm_ext_v8m
25738 ToU("sg", e97fe97f
, 0, (), noargs
),
25739 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25740 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25741 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25742 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25743 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25744 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25746 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25747 instructions behave as nop if no VFP is present. */
25748 #undef THUMB_VARIANT
25749 #define THUMB_VARIANT & arm_ext_v8m_main
25750 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25751 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25753 /* Armv8.1-M Mainline instructions. */
25754 #undef THUMB_VARIANT
25755 #define THUMB_VARIANT & arm_ext_v8_1m_main
25756 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25757 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25758 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25759 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25760 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
25761 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
25762 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25763 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25764 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25766 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25767 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25768 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25769 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25770 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25772 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25773 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25774 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25776 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25777 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25779 #undef THUMB_VARIANT
25780 #define THUMB_VARIANT & mve_ext
25781 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25782 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25783 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25784 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25785 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25786 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25787 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25788 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25789 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25790 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25791 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25792 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25793 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25794 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25795 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25797 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25798 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25799 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25800 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25801 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25802 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25803 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25804 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25805 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25806 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25807 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25808 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25809 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25810 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25811 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25813 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25814 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25815 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25816 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25817 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25818 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25819 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25820 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25821 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25822 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25823 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25824 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25825 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25826 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25827 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25829 /* MVE and MVE FP only. */
25830 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25831 mCEF(vctp
, _vctp
, 1, (RRnpc
), mve_vctp
),
25832 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25833 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25834 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25835 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25836 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25837 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25838 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25839 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25840 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25841 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25842 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25843 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25844 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25845 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25846 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25847 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25849 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25850 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25851 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25852 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25853 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25854 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25855 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25856 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25857 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25858 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25859 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25860 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25861 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25862 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25863 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25864 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25865 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25866 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25867 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25868 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25870 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25871 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25872 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25873 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25874 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25875 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25876 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25877 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25878 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25879 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25880 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25881 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25882 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25883 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25884 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25885 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25886 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25888 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25889 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25890 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25891 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25892 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25893 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25894 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25895 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25896 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25897 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25898 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25899 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25900 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25901 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25902 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25903 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25904 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25905 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25906 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25907 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25909 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25910 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25911 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25912 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25913 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25915 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25916 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25917 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25918 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25919 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25920 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25921 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25922 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25923 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25924 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25925 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25926 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25927 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25928 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25929 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25930 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25931 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25933 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25934 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25935 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25936 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25937 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25938 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25939 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25940 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25941 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25942 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25943 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25944 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25946 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25947 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25948 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25950 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
25951 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
25952 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
25953 toU("lctp", _lctp
, 0, (), t_loloop
),
25955 #undef THUMB_VARIANT
25956 #define THUMB_VARIANT & mve_fp_ext
25957 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25958 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25959 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25960 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25961 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25962 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25963 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25964 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25967 #define ARM_VARIANT & fpu_vfp_ext_v1
25968 #undef THUMB_VARIANT
25969 #define THUMB_VARIANT & arm_ext_v6t2
25970 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25971 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25973 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25976 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25978 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25979 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25980 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25981 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25983 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25984 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25985 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25987 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25988 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25990 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25991 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25993 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25994 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25997 #define ARM_VARIANT & fpu_vfp_ext_v2
25999 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
26000 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
26001 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
26002 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
26005 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
26006 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
26007 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
26008 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
26009 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
26010 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26011 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26014 #define ARM_VARIANT & fpu_neon_ext_v1
26015 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26016 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
26017 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
26018 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
26019 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26020 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26021 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26022 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26023 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
26024 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
26025 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
26026 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
26027 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26028 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
26029 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26030 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26031 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26032 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26033 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26034 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
26035 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26036 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26037 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
26038 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26039 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26040 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26041 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26042 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26043 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26044 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
26045 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
26046 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26047 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26048 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26049 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
26050 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
26051 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
26054 #define ARM_VARIANT & arm_ext_v8_3
26055 #undef THUMB_VARIANT
26056 #define THUMB_VARIANT & arm_ext_v6t2_v8m
26057 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
26058 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
26061 #define ARM_VARIANT &arm_ext_bf16
26062 #undef THUMB_VARIANT
26063 #define THUMB_VARIANT &arm_ext_bf16
26064 TUF ("vdot", c000d00
, fc000d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vdot
, vdot
),
26065 TUF ("vmmla", c000c40
, fc000c40
, 3, (RNQ
, RNQ
, RNQ
), vmmla
, vmmla
),
26066 TUF ("vfmab", c300810
, fc300810
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), bfloat_vfma
, bfloat_vfma
),
26069 #define ARM_VARIANT &arm_ext_i8mm
26070 #undef THUMB_VARIANT
26071 #define THUMB_VARIANT &arm_ext_i8mm
26072 TUF ("vsmmla", c200c40
, fc200c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26073 TUF ("vummla", c200c50
, fc200c50
, 3, (RNQ
, RNQ
, RNQ
), vummla
, vummla
),
26074 TUF ("vusmmla", ca00c40
, fca00c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26075 TUF ("vusdot", c800d00
, fc800d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vusdot
, vusdot
),
26076 TUF ("vsudot", c800d10
, fc800d10
, 3, (RNDQ
, RNDQ
, RNSC
), vsudot
, vsudot
),
26079 #undef THUMB_VARIANT
26111 /* MD interface: bits in the object file. */
26113 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
26114 for use in the a.out file, and stores them in the array pointed to by buf.
26115 This knows about the endian-ness of the target machine and does
26116 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
26117 2 (short) and 4 (long) Floating numbers are put out as a series of
26118 LITTLENUMS (shorts, here at least). */
26121 md_number_to_chars (char * buf
, valueT val
, int n
)
26123 if (target_big_endian
)
26124 number_to_chars_bigendian (buf
, val
, n
);
26126 number_to_chars_littleendian (buf
, val
, n
);
26130 md_chars_to_number (char * buf
, int n
)
26133 unsigned char * where
= (unsigned char *) buf
;
26135 if (target_big_endian
)
26140 result
|= (*where
++ & 255);
26148 result
|= (where
[n
] & 255);
26155 /* MD interface: Sections. */
26157 /* Calculate the maximum variable size (i.e., excluding fr_fix)
26158 that an rs_machine_dependent frag may reach. */
26161 arm_frag_max_var (fragS
*fragp
)
26163 /* We only use rs_machine_dependent for variable-size Thumb instructions,
26164 which are either THUMB_SIZE (2) or INSN_SIZE (4).
26166 Note that we generate relaxable instructions even for cases that don't
26167 really need it, like an immediate that's a trivial constant. So we're
26168 overestimating the instruction size for some of those cases. Rather
26169 than putting more intelligence here, it would probably be better to
26170 avoid generating a relaxation frag in the first place when it can be
26171 determined up front that a short instruction will suffice. */
26173 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
26177 /* Estimate the size of a frag before relaxing. Assume everything fits in
26181 md_estimate_size_before_relax (fragS
* fragp
,
26182 segT segtype ATTRIBUTE_UNUSED
)
26188 /* Convert a machine dependent frag. */
26191 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
26193 unsigned long insn
;
26194 unsigned long old_op
;
26202 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26204 old_op
= bfd_get_16(abfd
, buf
);
26205 if (fragp
->fr_symbol
)
26207 exp
.X_op
= O_symbol
;
26208 exp
.X_add_symbol
= fragp
->fr_symbol
;
26212 exp
.X_op
= O_constant
;
26214 exp
.X_add_number
= fragp
->fr_offset
;
26215 opcode
= fragp
->fr_subtype
;
26218 case T_MNEM_ldr_pc
:
26219 case T_MNEM_ldr_pc2
:
26220 case T_MNEM_ldr_sp
:
26221 case T_MNEM_str_sp
:
26228 if (fragp
->fr_var
== 4)
26230 insn
= THUMB_OP32 (opcode
);
26231 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
26233 insn
|= (old_op
& 0x700) << 4;
26237 insn
|= (old_op
& 7) << 12;
26238 insn
|= (old_op
& 0x38) << 13;
26240 insn
|= 0x00000c00;
26241 put_thumb32_insn (buf
, insn
);
26242 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
26246 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
26248 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
26251 if (fragp
->fr_var
== 4)
26253 insn
= THUMB_OP32 (opcode
);
26254 insn
|= (old_op
& 0xf0) << 4;
26255 put_thumb32_insn (buf
, insn
);
26256 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
26260 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26261 exp
.X_add_number
-= 4;
26269 if (fragp
->fr_var
== 4)
26271 int r0off
= (opcode
== T_MNEM_mov
26272 || opcode
== T_MNEM_movs
) ? 0 : 8;
26273 insn
= THUMB_OP32 (opcode
);
26274 insn
= (insn
& 0xe1ffffff) | 0x10000000;
26275 insn
|= (old_op
& 0x700) << r0off
;
26276 put_thumb32_insn (buf
, insn
);
26277 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26281 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
26286 if (fragp
->fr_var
== 4)
26288 insn
= THUMB_OP32(opcode
);
26289 put_thumb32_insn (buf
, insn
);
26290 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
26293 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
26297 if (fragp
->fr_var
== 4)
26299 insn
= THUMB_OP32(opcode
);
26300 insn
|= (old_op
& 0xf00) << 14;
26301 put_thumb32_insn (buf
, insn
);
26302 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
26305 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
26308 case T_MNEM_add_sp
:
26309 case T_MNEM_add_pc
:
26310 case T_MNEM_inc_sp
:
26311 case T_MNEM_dec_sp
:
26312 if (fragp
->fr_var
== 4)
26314 /* ??? Choose between add and addw. */
26315 insn
= THUMB_OP32 (opcode
);
26316 insn
|= (old_op
& 0xf0) << 4;
26317 put_thumb32_insn (buf
, insn
);
26318 if (opcode
== T_MNEM_add_pc
)
26319 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
26321 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26324 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26332 if (fragp
->fr_var
== 4)
26334 insn
= THUMB_OP32 (opcode
);
26335 insn
|= (old_op
& 0xf0) << 4;
26336 insn
|= (old_op
& 0xf) << 16;
26337 put_thumb32_insn (buf
, insn
);
26338 if (insn
& (1 << 20))
26339 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26341 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26344 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26350 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
26351 (enum bfd_reloc_code_real
) reloc_type
);
26352 fixp
->fx_file
= fragp
->fr_file
;
26353 fixp
->fx_line
= fragp
->fr_line
;
26354 fragp
->fr_fix
+= fragp
->fr_var
;
26356 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26357 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
26358 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26359 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26362 /* Return the size of a relaxable immediate operand instruction.
26363 SHIFT and SIZE specify the form of the allowable immediate. */
26365 relax_immediate (fragS
*fragp
, int size
, int shift
)
26371 /* ??? Should be able to do better than this. */
26372 if (fragp
->fr_symbol
)
26375 low
= (1 << shift
) - 1;
26376 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26377 offset
= fragp
->fr_offset
;
26378 /* Force misaligned offsets to 32-bit variant. */
26381 if (offset
& ~mask
)
26386 /* Get the address of a symbol during relaxation. */
26388 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26394 sym
= fragp
->fr_symbol
;
26395 sym_frag
= symbol_get_frag (sym
);
26396 know (S_GET_SEGMENT (sym
) != absolute_section
26397 || sym_frag
== &zero_address_frag
);
26398 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26400 /* If frag has yet to be reached on this pass, assume it will
26401 move by STRETCH just as we did. If this is not so, it will
26402 be because some frag between grows, and that will force
26406 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26410 /* Adjust stretch for any alignment frag. Note that if have
26411 been expanding the earlier code, the symbol may be
26412 defined in what appears to be an earlier frag. FIXME:
26413 This doesn't handle the fr_subtype field, which specifies
26414 a maximum number of bytes to skip when doing an
26416 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26418 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26421 stretch
= - ((- stretch
)
26422 & ~ ((1 << (int) f
->fr_offset
) - 1));
26424 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
26436 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
26439 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
26444 /* Assume worst case for symbols not known to be in the same section. */
26445 if (fragp
->fr_symbol
== NULL
26446 || !S_IS_DEFINED (fragp
->fr_symbol
)
26447 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26448 || S_IS_WEAK (fragp
->fr_symbol
))
26451 val
= relaxed_symbol_addr (fragp
, stretch
);
26452 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
26453 addr
= (addr
+ 4) & ~3;
26454 /* Force misaligned targets to 32-bit variant. */
26458 if (val
< 0 || val
> 1020)
26463 /* Return the size of a relaxable add/sub immediate instruction. */
26465 relax_addsub (fragS
*fragp
, asection
*sec
)
26470 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26471 op
= bfd_get_16(sec
->owner
, buf
);
26472 if ((op
& 0xf) == ((op
>> 4) & 0xf))
26473 return relax_immediate (fragp
, 8, 0);
26475 return relax_immediate (fragp
, 3, 0);
26478 /* Return TRUE iff the definition of symbol S could be pre-empted
26479 (overridden) at link or load time. */
26481 symbol_preemptible (symbolS
*s
)
26483 /* Weak symbols can always be pre-empted. */
26487 /* Non-global symbols cannot be pre-empted. */
26488 if (! S_IS_EXTERNAL (s
))
26492 /* In ELF, a global symbol can be marked protected, or private. In that
26493 case it can't be pre-empted (other definitions in the same link unit
26494 would violate the ODR). */
26495 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
26499 /* Other global symbols might be pre-empted. */
26503 /* Return the size of a relaxable branch instruction. BITS is the
26504 size of the offset field in the narrow instruction. */
26507 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
26513 /* Assume worst case for symbols not known to be in the same section. */
26514 if (!S_IS_DEFINED (fragp
->fr_symbol
)
26515 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26516 || S_IS_WEAK (fragp
->fr_symbol
))
26520 /* A branch to a function in ARM state will require interworking. */
26521 if (S_IS_DEFINED (fragp
->fr_symbol
)
26522 && ARM_IS_FUNC (fragp
->fr_symbol
))
26526 if (symbol_preemptible (fragp
->fr_symbol
))
26529 val
= relaxed_symbol_addr (fragp
, stretch
);
26530 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
26533 /* Offset is a signed value *2 */
26535 if (val
>= limit
|| val
< -limit
)
26541 /* Relax a machine dependent frag. This returns the amount by which
26542 the current size of the frag should change. */
26545 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
26550 oldsize
= fragp
->fr_var
;
26551 switch (fragp
->fr_subtype
)
26553 case T_MNEM_ldr_pc2
:
26554 newsize
= relax_adr (fragp
, sec
, stretch
);
26556 case T_MNEM_ldr_pc
:
26557 case T_MNEM_ldr_sp
:
26558 case T_MNEM_str_sp
:
26559 newsize
= relax_immediate (fragp
, 8, 2);
26563 newsize
= relax_immediate (fragp
, 5, 2);
26567 newsize
= relax_immediate (fragp
, 5, 1);
26571 newsize
= relax_immediate (fragp
, 5, 0);
26574 newsize
= relax_adr (fragp
, sec
, stretch
);
26580 newsize
= relax_immediate (fragp
, 8, 0);
26583 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
26586 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
26588 case T_MNEM_add_sp
:
26589 case T_MNEM_add_pc
:
26590 newsize
= relax_immediate (fragp
, 8, 2);
26592 case T_MNEM_inc_sp
:
26593 case T_MNEM_dec_sp
:
26594 newsize
= relax_immediate (fragp
, 7, 2);
26600 newsize
= relax_addsub (fragp
, sec
);
26606 fragp
->fr_var
= newsize
;
26607 /* Freeze wide instructions that are at or before the same location as
26608 in the previous pass. This avoids infinite loops.
26609 Don't freeze them unconditionally because targets may be artificially
26610 misaligned by the expansion of preceding frags. */
26611 if (stretch
<= 0 && newsize
> 2)
26613 md_convert_frag (sec
->owner
, sec
, fragp
);
26617 return newsize
- oldsize
;
26620 /* Round up a section size to the appropriate boundary. */
26623 md_section_align (segT segment ATTRIBUTE_UNUSED
,
26629 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26630 of an rs_align_code fragment. */
26633 arm_handle_align (fragS
* fragP
)
26635 static unsigned char const arm_noop
[2][2][4] =
26638 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26639 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26642 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26643 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26646 static unsigned char const thumb_noop
[2][2][2] =
26649 {0xc0, 0x46}, /* LE */
26650 {0x46, 0xc0}, /* BE */
26653 {0x00, 0xbf}, /* LE */
26654 {0xbf, 0x00} /* BE */
26657 static unsigned char const wide_thumb_noop
[2][4] =
26658 { /* Wide Thumb-2 */
26659 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26660 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26663 unsigned bytes
, fix
, noop_size
;
26665 const unsigned char * noop
;
26666 const unsigned char *narrow_noop
= NULL
;
26671 if (fragP
->fr_type
!= rs_align_code
)
26674 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
26675 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
26678 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26679 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
26681 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
26683 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
26685 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26686 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
26688 narrow_noop
= thumb_noop
[1][target_big_endian
];
26689 noop
= wide_thumb_noop
[target_big_endian
];
26692 noop
= thumb_noop
[0][target_big_endian
];
26700 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26701 ? selected_cpu
: arm_arch_none
,
26703 [target_big_endian
];
26710 fragP
->fr_var
= noop_size
;
26712 if (bytes
& (noop_size
- 1))
26714 fix
= bytes
& (noop_size
- 1);
26716 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
26718 memset (p
, 0, fix
);
26725 if (bytes
& noop_size
)
26727 /* Insert a narrow noop. */
26728 memcpy (p
, narrow_noop
, noop_size
);
26730 bytes
-= noop_size
;
26734 /* Use wide noops for the remainder */
26738 while (bytes
>= noop_size
)
26740 memcpy (p
, noop
, noop_size
);
26742 bytes
-= noop_size
;
26746 fragP
->fr_fix
+= fix
;
26749 /* Called from md_do_align. Used to create an alignment
26750 frag in a code section. */
26753 arm_frag_align_code (int n
, int max
)
26757 /* We assume that there will never be a requirement
26758 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26759 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26764 _("alignments greater than %d bytes not supported in .text sections."),
26765 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26766 as_fatal ("%s", err_msg
);
26769 p
= frag_var (rs_align_code
,
26770 MAX_MEM_FOR_RS_ALIGN_CODE
,
26772 (relax_substateT
) max
,
26779 /* Perform target specific initialisation of a frag.
26780 Note - despite the name this initialisation is not done when the frag
26781 is created, but only when its type is assigned. A frag can be created
26782 and used a long time before its type is set, so beware of assuming that
26783 this initialisation is performed first. */
26787 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26789 /* Record whether this frag is in an ARM or a THUMB area. */
26790 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26793 #else /* OBJ_ELF is defined. */
26795 arm_init_frag (fragS
* fragP
, int max_chars
)
26797 bfd_boolean frag_thumb_mode
;
26799 /* If the current ARM vs THUMB mode has not already
26800 been recorded into this frag then do so now. */
26801 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26802 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26804 /* PR 21809: Do not set a mapping state for debug sections
26805 - it just confuses other tools. */
26806 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
26809 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26811 /* Record a mapping symbol for alignment frags. We will delete this
26812 later if the alignment ends up empty. */
26813 switch (fragP
->fr_type
)
26816 case rs_align_test
:
26818 mapping_state_2 (MAP_DATA
, max_chars
);
26820 case rs_align_code
:
26821 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26828 /* When we change sections we need to issue a new mapping symbol. */
26831 arm_elf_change_section (void)
26833 /* Link an unlinked unwind index table section to the .text section. */
26834 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26835 && elf_linked_to_section (now_seg
) == NULL
)
26836 elf_linked_to_section (now_seg
) = text_section
;
26840 arm_elf_section_type (const char * str
, size_t len
)
26842 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26843 return SHT_ARM_EXIDX
;
26848 /* Code to deal with unwinding tables. */
26850 static void add_unwind_adjustsp (offsetT
);
26852 /* Generate any deferred unwind frame offset. */
26855 flush_pending_unwind (void)
26859 offset
= unwind
.pending_offset
;
26860 unwind
.pending_offset
= 0;
26862 add_unwind_adjustsp (offset
);
26865 /* Add an opcode to this list for this function. Two-byte opcodes should
26866 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26870 add_unwind_opcode (valueT op
, int length
)
26872 /* Add any deferred stack adjustment. */
26873 if (unwind
.pending_offset
)
26874 flush_pending_unwind ();
26876 unwind
.sp_restored
= 0;
26878 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26880 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26881 if (unwind
.opcodes
)
26882 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26883 unwind
.opcode_alloc
);
26885 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26890 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26892 unwind
.opcode_count
++;
26896 /* Add unwind opcodes to adjust the stack pointer. */
26899 add_unwind_adjustsp (offsetT offset
)
26903 if (offset
> 0x200)
26905 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26910 /* Long form: 0xb2, uleb128. */
26911 /* This might not fit in a word so add the individual bytes,
26912 remembering the list is built in reverse order. */
26913 o
= (valueT
) ((offset
- 0x204) >> 2);
26915 add_unwind_opcode (0, 1);
26917 /* Calculate the uleb128 encoding of the offset. */
26921 bytes
[n
] = o
& 0x7f;
26927 /* Add the insn. */
26929 add_unwind_opcode (bytes
[n
- 1], 1);
26930 add_unwind_opcode (0xb2, 1);
26932 else if (offset
> 0x100)
26934 /* Two short opcodes. */
26935 add_unwind_opcode (0x3f, 1);
26936 op
= (offset
- 0x104) >> 2;
26937 add_unwind_opcode (op
, 1);
26939 else if (offset
> 0)
26941 /* Short opcode. */
26942 op
= (offset
- 4) >> 2;
26943 add_unwind_opcode (op
, 1);
26945 else if (offset
< 0)
26948 while (offset
> 0x100)
26950 add_unwind_opcode (0x7f, 1);
26953 op
= ((offset
- 4) >> 2) | 0x40;
26954 add_unwind_opcode (op
, 1);
26958 /* Finish the list of unwind opcodes for this function. */
26961 finish_unwind_opcodes (void)
26965 if (unwind
.fp_used
)
26967 /* Adjust sp as necessary. */
26968 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26969 flush_pending_unwind ();
26971 /* After restoring sp from the frame pointer. */
26972 op
= 0x90 | unwind
.fp_reg
;
26973 add_unwind_opcode (op
, 1);
26976 flush_pending_unwind ();
26980 /* Start an exception table entry. If idx is nonzero this is an index table
26984 start_unwind_section (const segT text_seg
, int idx
)
26986 const char * text_name
;
26987 const char * prefix
;
26988 const char * prefix_once
;
26989 const char * group_name
;
26997 prefix
= ELF_STRING_ARM_unwind
;
26998 prefix_once
= ELF_STRING_ARM_unwind_once
;
26999 type
= SHT_ARM_EXIDX
;
27003 prefix
= ELF_STRING_ARM_unwind_info
;
27004 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
27005 type
= SHT_PROGBITS
;
27008 text_name
= segment_name (text_seg
);
27009 if (streq (text_name
, ".text"))
27012 if (strncmp (text_name
, ".gnu.linkonce.t.",
27013 strlen (".gnu.linkonce.t.")) == 0)
27015 prefix
= prefix_once
;
27016 text_name
+= strlen (".gnu.linkonce.t.");
27019 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
27025 /* Handle COMDAT group. */
27026 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
27028 group_name
= elf_group_name (text_seg
);
27029 if (group_name
== NULL
)
27031 as_bad (_("Group section `%s' has no group signature"),
27032 segment_name (text_seg
));
27033 ignore_rest_of_line ();
27036 flags
|= SHF_GROUP
;
27040 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
27043 /* Set the section link for index tables. */
27045 elf_linked_to_section (now_seg
) = text_seg
;
27049 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
27050 personality routine data. Returns zero, or the index table value for
27051 an inline entry. */
27054 create_unwind_entry (int have_data
)
27059 /* The current word of data. */
27061 /* The number of bytes left in this word. */
27064 finish_unwind_opcodes ();
27066 /* Remember the current text section. */
27067 unwind
.saved_seg
= now_seg
;
27068 unwind
.saved_subseg
= now_subseg
;
27070 start_unwind_section (now_seg
, 0);
27072 if (unwind
.personality_routine
== NULL
)
27074 if (unwind
.personality_index
== -2)
27077 as_bad (_("handlerdata in cantunwind frame"));
27078 return 1; /* EXIDX_CANTUNWIND. */
27081 /* Use a default personality routine if none is specified. */
27082 if (unwind
.personality_index
== -1)
27084 if (unwind
.opcode_count
> 3)
27085 unwind
.personality_index
= 1;
27087 unwind
.personality_index
= 0;
27090 /* Space for the personality routine entry. */
27091 if (unwind
.personality_index
== 0)
27093 if (unwind
.opcode_count
> 3)
27094 as_bad (_("too many unwind opcodes for personality routine 0"));
27098 /* All the data is inline in the index table. */
27101 while (unwind
.opcode_count
> 0)
27103 unwind
.opcode_count
--;
27104 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27108 /* Pad with "finish" opcodes. */
27110 data
= (data
<< 8) | 0xb0;
27117 /* We get two opcodes "free" in the first word. */
27118 size
= unwind
.opcode_count
- 2;
27122 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
27123 if (unwind
.personality_index
!= -1)
27125 as_bad (_("attempt to recreate an unwind entry"));
27129 /* An extra byte is required for the opcode count. */
27130 size
= unwind
.opcode_count
+ 1;
27133 size
= (size
+ 3) >> 2;
27135 as_bad (_("too many unwind opcodes"));
27137 frag_align (2, 0, 0);
27138 record_alignment (now_seg
, 2);
27139 unwind
.table_entry
= expr_build_dot ();
27141 /* Allocate the table entry. */
27142 ptr
= frag_more ((size
<< 2) + 4);
27143 /* PR 13449: Zero the table entries in case some of them are not used. */
27144 memset (ptr
, 0, (size
<< 2) + 4);
27145 where
= frag_now_fix () - ((size
<< 2) + 4);
27147 switch (unwind
.personality_index
)
27150 /* ??? Should this be a PLT generating relocation? */
27151 /* Custom personality routine. */
27152 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
27153 BFD_RELOC_ARM_PREL31
);
27158 /* Set the first byte to the number of additional words. */
27159 data
= size
> 0 ? size
- 1 : 0;
27163 /* ABI defined personality routines. */
27165 /* Three opcodes bytes are packed into the first word. */
27172 /* The size and first two opcode bytes go in the first word. */
27173 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
27178 /* Should never happen. */
27182 /* Pack the opcodes into words (MSB first), reversing the list at the same
27184 while (unwind
.opcode_count
> 0)
27188 md_number_to_chars (ptr
, data
, 4);
27193 unwind
.opcode_count
--;
27195 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27198 /* Finish off the last word. */
27201 /* Pad with "finish" opcodes. */
27203 data
= (data
<< 8) | 0xb0;
27205 md_number_to_chars (ptr
, data
, 4);
27210 /* Add an empty descriptor if there is no user-specified data. */
27211 ptr
= frag_more (4);
27212 md_number_to_chars (ptr
, 0, 4);
27219 /* Initialize the DWARF-2 unwind information for this procedure. */
27222 tc_arm_frame_initial_instructions (void)
27224 cfi_add_CFA_def_cfa (REG_SP
, 0);
27226 #endif /* OBJ_ELF */
27228 /* Convert REGNAME to a DWARF-2 register number. */
27231 tc_arm_regname_to_dw2regnum (char *regname
)
27233 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
27237 /* PR 16694: Allow VFP registers as well. */
27238 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
27242 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
27251 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
27255 exp
.X_op
= O_secrel
;
27256 exp
.X_add_symbol
= symbol
;
27257 exp
.X_add_number
= 0;
27258 emit_expr (&exp
, size
);
27262 /* MD interface: Symbol and relocation handling. */
27264 /* Return the address within the segment that a PC-relative fixup is
27265 relative to. For ARM, PC-relative fixups applied to instructions
27266 are generally relative to the location of the fixup plus 8 bytes.
27267 Thumb branches are offset by 4, and Thumb loads relative to PC
27268 require special handling. */
27271 md_pcrel_from_section (fixS
* fixP
, segT seg
)
27273 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27275 /* If this is pc-relative and we are going to emit a relocation
27276 then we just want to put out any pipeline compensation that the linker
27277 will need. Otherwise we want to use the calculated base.
27278 For WinCE we skip the bias for externals as well, since this
27279 is how the MS ARM-CE assembler behaves and we want to be compatible. */
27281 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27282 || (arm_force_relocation (fixP
)
27284 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
27290 switch (fixP
->fx_r_type
)
27292 /* PC relative addressing on the Thumb is slightly odd as the
27293 bottom two bits of the PC are forced to zero for the
27294 calculation. This happens *after* application of the
27295 pipeline offset. However, Thumb adrl already adjusts for
27296 this, so we need not do it again. */
27297 case BFD_RELOC_ARM_THUMB_ADD
:
27300 case BFD_RELOC_ARM_THUMB_OFFSET
:
27301 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27302 case BFD_RELOC_ARM_T32_ADD_PC12
:
27303 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27304 return (base
+ 4) & ~3;
27306 /* Thumb branches are simply offset by +4. */
27307 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27308 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27309 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27310 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27311 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27312 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27313 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27314 case BFD_RELOC_ARM_THUMB_BF17
:
27315 case BFD_RELOC_ARM_THUMB_BF19
:
27316 case BFD_RELOC_ARM_THUMB_BF13
:
27317 case BFD_RELOC_ARM_THUMB_LOOP12
:
27320 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27322 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27323 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27324 && ARM_IS_FUNC (fixP
->fx_addsy
)
27325 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27326 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27329 /* BLX is like branches above, but forces the low two bits of PC to
27331 case BFD_RELOC_THUMB_PCREL_BLX
:
27333 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27334 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27335 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27336 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27337 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27338 return (base
+ 4) & ~3;
27340 /* ARM mode branches are offset by +8. However, the Windows CE
27341 loader expects the relocation not to take this into account. */
27342 case BFD_RELOC_ARM_PCREL_BLX
:
27344 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27345 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27346 && ARM_IS_FUNC (fixP
->fx_addsy
)
27347 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27348 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27351 case BFD_RELOC_ARM_PCREL_CALL
:
27353 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27354 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27355 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27356 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27357 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27360 case BFD_RELOC_ARM_PCREL_BRANCH
:
27361 case BFD_RELOC_ARM_PCREL_JUMP
:
27362 case BFD_RELOC_ARM_PLT32
:
27364 /* When handling fixups immediately, because we have already
27365 discovered the value of a symbol, or the address of the frag involved
27366 we must account for the offset by +8, as the OS loader will never see the reloc.
27367 see fixup_segment() in write.c
27368 The S_IS_EXTERNAL test handles the case of global symbols.
27369 Those need the calculated base, not just the pipe compensation the linker will need. */
27371 && fixP
->fx_addsy
!= NULL
27372 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27373 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27381 /* ARM mode loads relative to PC are also offset by +8. Unlike
27382 branches, the Windows CE loader *does* expect the relocation
27383 to take this into account. */
27384 case BFD_RELOC_ARM_OFFSET_IMM
:
27385 case BFD_RELOC_ARM_OFFSET_IMM8
:
27386 case BFD_RELOC_ARM_HWLITERAL
:
27387 case BFD_RELOC_ARM_LITERAL
:
27388 case BFD_RELOC_ARM_CP_OFF_IMM
:
27392 /* Other PC-relative relocations are un-offset. */
27398 static bfd_boolean flag_warn_syms
= TRUE
;
27401 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27403 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27404 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27405 does mean that the resulting code might be very confusing to the reader.
27406 Also this warning can be triggered if the user omits an operand before
27407 an immediate address, eg:
27411 GAS treats this as an assignment of the value of the symbol foo to a
27412 symbol LDR, and so (without this code) it will not issue any kind of
27413 warning or error message.
27415 Note - ARM instructions are case-insensitive but the strings in the hash
27416 table are all stored in lower case, so we must first ensure that name is
27418 if (flag_warn_syms
&& arm_ops_hsh
)
27420 char * nbuf
= strdup (name
);
27423 for (p
= nbuf
; *p
; p
++)
27425 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
27427 static struct hash_control
* already_warned
= NULL
;
27429 if (already_warned
== NULL
)
27430 already_warned
= hash_new ();
27431 /* Only warn about the symbol once. To keep the code
27432 simple we let hash_insert do the lookup for us. */
27433 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
27434 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
27443 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
27444 Otherwise we have no need to default values of symbols. */
27447 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
27450 if (name
[0] == '_' && name
[1] == 'G'
27451 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
27455 if (symbol_find (name
))
27456 as_bad (_("GOT already in the symbol table"));
27458 GOT_symbol
= symbol_new (name
, undefined_section
,
27459 (valueT
) 0, & zero_address_frag
);
27469 /* Subroutine of md_apply_fix. Check to see if an immediate can be
27470 computed as two separate immediate values, added together. We
27471 already know that this value cannot be computed by just one ARM
27474 static unsigned int
27475 validate_immediate_twopart (unsigned int val
,
27476 unsigned int * highpart
)
27481 for (i
= 0; i
< 32; i
+= 2)
27482 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
27488 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
27490 else if (a
& 0xff0000)
27492 if (a
& 0xff000000)
27494 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
27498 gas_assert (a
& 0xff000000);
27499 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
27502 return (a
& 0xff) | (i
<< 7);
27509 validate_offset_imm (unsigned int val
, int hwse
)
27511 if ((hwse
&& val
> 255) || val
> 4095)
27516 /* Subroutine of md_apply_fix. Do those data_ops which can take a
27517 negative immediate constant by altering the instruction. A bit of
27522 by inverting the second operand, and
27525 by negating the second operand. */
27528 negate_data_op (unsigned long * instruction
,
27529 unsigned long value
)
27532 unsigned long negated
, inverted
;
27534 negated
= encode_arm_immediate (-value
);
27535 inverted
= encode_arm_immediate (~value
);
27537 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
27540 /* First negates. */
27541 case OPCODE_SUB
: /* ADD <-> SUB */
27542 new_inst
= OPCODE_ADD
;
27547 new_inst
= OPCODE_SUB
;
27551 case OPCODE_CMP
: /* CMP <-> CMN */
27552 new_inst
= OPCODE_CMN
;
27557 new_inst
= OPCODE_CMP
;
27561 /* Now Inverted ops. */
27562 case OPCODE_MOV
: /* MOV <-> MVN */
27563 new_inst
= OPCODE_MVN
;
27568 new_inst
= OPCODE_MOV
;
27572 case OPCODE_AND
: /* AND <-> BIC */
27573 new_inst
= OPCODE_BIC
;
27578 new_inst
= OPCODE_AND
;
27582 case OPCODE_ADC
: /* ADC <-> SBC */
27583 new_inst
= OPCODE_SBC
;
27588 new_inst
= OPCODE_ADC
;
27592 /* We cannot do anything. */
27597 if (value
== (unsigned) FAIL
)
27600 *instruction
&= OPCODE_MASK
;
27601 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
27605 /* Like negate_data_op, but for Thumb-2. */
27607 static unsigned int
27608 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
27612 unsigned int negated
, inverted
;
27614 negated
= encode_thumb32_immediate (-value
);
27615 inverted
= encode_thumb32_immediate (~value
);
27617 rd
= (*instruction
>> 8) & 0xf;
27618 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
27621 /* ADD <-> SUB. Includes CMP <-> CMN. */
27622 case T2_OPCODE_SUB
:
27623 new_inst
= T2_OPCODE_ADD
;
27627 case T2_OPCODE_ADD
:
27628 new_inst
= T2_OPCODE_SUB
;
27632 /* ORR <-> ORN. Includes MOV <-> MVN. */
27633 case T2_OPCODE_ORR
:
27634 new_inst
= T2_OPCODE_ORN
;
27638 case T2_OPCODE_ORN
:
27639 new_inst
= T2_OPCODE_ORR
;
27643 /* AND <-> BIC. TST has no inverted equivalent. */
27644 case T2_OPCODE_AND
:
27645 new_inst
= T2_OPCODE_BIC
;
27652 case T2_OPCODE_BIC
:
27653 new_inst
= T2_OPCODE_AND
;
27658 case T2_OPCODE_ADC
:
27659 new_inst
= T2_OPCODE_SBC
;
27663 case T2_OPCODE_SBC
:
27664 new_inst
= T2_OPCODE_ADC
;
27668 /* We cannot do anything. */
27673 if (value
== (unsigned int)FAIL
)
27676 *instruction
&= T2_OPCODE_MASK
;
27677 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
27681 /* Read a 32-bit thumb instruction from buf. */
27683 static unsigned long
27684 get_thumb32_insn (char * buf
)
27686 unsigned long insn
;
27687 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
27688 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27693 /* We usually want to set the low bit on the address of thumb function
27694 symbols. In particular .word foo - . should have the low bit set.
27695 Generic code tries to fold the difference of two symbols to
27696 a constant. Prevent this and force a relocation when the first symbols
27697 is a thumb function. */
27700 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
27702 if (op
== O_subtract
27703 && l
->X_op
== O_symbol
27704 && r
->X_op
== O_symbol
27705 && THUMB_IS_FUNC (l
->X_add_symbol
))
27707 l
->X_op
= O_subtract
;
27708 l
->X_op_symbol
= r
->X_add_symbol
;
27709 l
->X_add_number
-= r
->X_add_number
;
27713 /* Process as normal. */
27717 /* Encode Thumb2 unconditional branches and calls. The encoding
27718 for the 2 are identical for the immediate values. */
27721 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
27723 #define T2I1I2MASK ((1 << 13) | (1 << 11))
27726 addressT S
, I1
, I2
, lo
, hi
;
27728 S
= (value
>> 24) & 0x01;
27729 I1
= (value
>> 23) & 0x01;
27730 I2
= (value
>> 22) & 0x01;
27731 hi
= (value
>> 12) & 0x3ff;
27732 lo
= (value
>> 1) & 0x7ff;
27733 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27734 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27735 newval
|= (S
<< 10) | hi
;
27736 newval2
&= ~T2I1I2MASK
;
27737 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27738 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27739 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27743 md_apply_fix (fixS
* fixP
,
27747 offsetT value
= * valP
;
27749 unsigned int newimm
;
27750 unsigned long temp
;
27752 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27754 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27756 /* Note whether this will delete the relocation. */
27758 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27761 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27762 consistency with the behaviour on 32-bit hosts. Remember value
27764 value
&= 0xffffffff;
27765 value
^= 0x80000000;
27766 value
-= 0x80000000;
27769 fixP
->fx_addnumber
= value
;
27771 /* Same treatment for fixP->fx_offset. */
27772 fixP
->fx_offset
&= 0xffffffff;
27773 fixP
->fx_offset
^= 0x80000000;
27774 fixP
->fx_offset
-= 0x80000000;
27776 switch (fixP
->fx_r_type
)
27778 case BFD_RELOC_NONE
:
27779 /* This will need to go in the object file. */
27783 case BFD_RELOC_ARM_IMMEDIATE
:
27784 /* We claim that this fixup has been processed here,
27785 even if in fact we generate an error because we do
27786 not have a reloc for it, so tc_gen_reloc will reject it. */
27789 if (fixP
->fx_addsy
)
27791 const char *msg
= 0;
27793 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27794 msg
= _("undefined symbol %s used as an immediate value");
27795 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27796 msg
= _("symbol %s is in a different section");
27797 else if (S_IS_WEAK (fixP
->fx_addsy
))
27798 msg
= _("symbol %s is weak and may be overridden later");
27802 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27803 msg
, S_GET_NAME (fixP
->fx_addsy
));
27808 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27810 /* If the offset is negative, we should use encoding A2 for ADR. */
27811 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27812 newimm
= negate_data_op (&temp
, value
);
27815 newimm
= encode_arm_immediate (value
);
27817 /* If the instruction will fail, see if we can fix things up by
27818 changing the opcode. */
27819 if (newimm
== (unsigned int) FAIL
)
27820 newimm
= negate_data_op (&temp
, value
);
27821 /* MOV accepts both ARM modified immediate (A1 encoding) and
27822 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27823 When disassembling, MOV is preferred when there is no encoding
27825 if (newimm
== (unsigned int) FAIL
27826 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27827 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27828 && !((temp
>> SBIT_SHIFT
) & 0x1)
27829 && value
>= 0 && value
<= 0xffff)
27831 /* Clear bits[23:20] to change encoding from A1 to A2. */
27832 temp
&= 0xff0fffff;
27833 /* Encoding high 4bits imm. Code below will encode the remaining
27835 temp
|= (value
& 0x0000f000) << 4;
27836 newimm
= value
& 0x00000fff;
27840 if (newimm
== (unsigned int) FAIL
)
27842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27843 _("invalid constant (%lx) after fixup"),
27844 (unsigned long) value
);
27848 newimm
|= (temp
& 0xfffff000);
27849 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27852 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27854 unsigned int highpart
= 0;
27855 unsigned int newinsn
= 0xe1a00000; /* nop. */
27857 if (fixP
->fx_addsy
)
27859 const char *msg
= 0;
27861 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27862 msg
= _("undefined symbol %s used as an immediate value");
27863 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27864 msg
= _("symbol %s is in a different section");
27865 else if (S_IS_WEAK (fixP
->fx_addsy
))
27866 msg
= _("symbol %s is weak and may be overridden later");
27870 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27871 msg
, S_GET_NAME (fixP
->fx_addsy
));
27876 newimm
= encode_arm_immediate (value
);
27877 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27879 /* If the instruction will fail, see if we can fix things up by
27880 changing the opcode. */
27881 if (newimm
== (unsigned int) FAIL
27882 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27884 /* No ? OK - try using two ADD instructions to generate
27886 newimm
= validate_immediate_twopart (value
, & highpart
);
27888 /* Yes - then make sure that the second instruction is
27890 if (newimm
!= (unsigned int) FAIL
)
27892 /* Still No ? Try using a negated value. */
27893 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27894 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27895 /* Otherwise - give up. */
27898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27899 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27904 /* Replace the first operand in the 2nd instruction (which
27905 is the PC) with the destination register. We have
27906 already added in the PC in the first instruction and we
27907 do not want to do it again. */
27908 newinsn
&= ~ 0xf0000;
27909 newinsn
|= ((newinsn
& 0x0f000) << 4);
27912 newimm
|= (temp
& 0xfffff000);
27913 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27915 highpart
|= (newinsn
& 0xfffff000);
27916 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27920 case BFD_RELOC_ARM_OFFSET_IMM
:
27921 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27923 /* Fall through. */
27925 case BFD_RELOC_ARM_LITERAL
:
27931 if (validate_offset_imm (value
, 0) == FAIL
)
27933 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27935 _("invalid literal constant: pool needs to be closer"));
27937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27938 _("bad immediate value for offset (%ld)"),
27943 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27945 newval
&= 0xfffff000;
27948 newval
&= 0xff7ff000;
27949 newval
|= value
| (sign
? INDEX_UP
: 0);
27951 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27954 case BFD_RELOC_ARM_OFFSET_IMM8
:
27955 case BFD_RELOC_ARM_HWLITERAL
:
27961 if (validate_offset_imm (value
, 1) == FAIL
)
27963 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27965 _("invalid literal constant: pool needs to be closer"));
27967 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27968 _("bad immediate value for 8-bit offset (%ld)"),
27973 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27975 newval
&= 0xfffff0f0;
27978 newval
&= 0xff7ff0f0;
27979 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27981 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27984 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27985 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27986 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27987 _("bad immediate value for offset (%ld)"), (long) value
);
27990 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27992 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27995 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27996 /* This is a complicated relocation used for all varieties of Thumb32
27997 load/store instruction with immediate offset:
27999 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
28000 *4, optional writeback(W)
28001 (doubleword load/store)
28003 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
28004 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
28005 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
28006 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
28007 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
28009 Uppercase letters indicate bits that are already encoded at
28010 this point. Lowercase letters are our problem. For the
28011 second block of instructions, the secondary opcode nybble
28012 (bits 8..11) is present, and bit 23 is zero, even if this is
28013 a PC-relative operation. */
28014 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28016 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
28018 if ((newval
& 0xf0000000) == 0xe0000000)
28020 /* Doubleword load/store: 8-bit offset, scaled by 4. */
28022 newval
|= (1 << 23);
28025 if (value
% 4 != 0)
28027 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28028 _("offset not a multiple of 4"));
28034 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28035 _("offset out of range"));
28040 else if ((newval
& 0x000f0000) == 0x000f0000)
28042 /* PC-relative, 12-bit offset. */
28044 newval
|= (1 << 23);
28049 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28050 _("offset out of range"));
28055 else if ((newval
& 0x00000100) == 0x00000100)
28057 /* Writeback: 8-bit, +/- offset. */
28059 newval
|= (1 << 9);
28064 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28065 _("offset out of range"));
28070 else if ((newval
& 0x00000f00) == 0x00000e00)
28072 /* T-instruction: positive 8-bit offset. */
28073 if (value
< 0 || value
> 0xff)
28075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28076 _("offset out of range"));
28084 /* Positive 12-bit or negative 8-bit offset. */
28088 newval
|= (1 << 23);
28098 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28099 _("offset out of range"));
28106 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
28107 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
28110 case BFD_RELOC_ARM_SHIFT_IMM
:
28111 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28112 if (((unsigned long) value
) > 32
28114 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
28116 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28117 _("shift expression is too large"));
28122 /* Shifts of zero must be done as lsl. */
28124 else if (value
== 32)
28126 newval
&= 0xfffff07f;
28127 newval
|= (value
& 0x1f) << 7;
28128 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28131 case BFD_RELOC_ARM_T32_IMMEDIATE
:
28132 case BFD_RELOC_ARM_T32_ADD_IMM
:
28133 case BFD_RELOC_ARM_T32_IMM12
:
28134 case BFD_RELOC_ARM_T32_ADD_PC12
:
28135 /* We claim that this fixup has been processed here,
28136 even if in fact we generate an error because we do
28137 not have a reloc for it, so tc_gen_reloc will reject it. */
28141 && ! S_IS_DEFINED (fixP
->fx_addsy
))
28143 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28144 _("undefined symbol %s used as an immediate value"),
28145 S_GET_NAME (fixP
->fx_addsy
));
28149 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28151 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
28154 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28155 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28156 Thumb2 modified immediate encoding (T2). */
28157 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
28158 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28160 newimm
= encode_thumb32_immediate (value
);
28161 if (newimm
== (unsigned int) FAIL
)
28162 newimm
= thumb32_negate_data_op (&newval
, value
);
28164 if (newimm
== (unsigned int) FAIL
)
28166 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
28168 /* Turn add/sum into addw/subw. */
28169 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28170 newval
= (newval
& 0xfeffffff) | 0x02000000;
28171 /* No flat 12-bit imm encoding for addsw/subsw. */
28172 if ((newval
& 0x00100000) == 0)
28174 /* 12 bit immediate for addw/subw. */
28178 newval
^= 0x00a00000;
28181 newimm
= (unsigned int) FAIL
;
28188 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28189 UINT16 (T3 encoding), MOVW only accepts UINT16. When
28190 disassembling, MOV is preferred when there is no encoding
28192 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
28193 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28194 but with the Rn field [19:16] set to 1111. */
28195 && (((newval
>> 16) & 0xf) == 0xf)
28196 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
28197 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
28198 && value
>= 0 && value
<= 0xffff)
28200 /* Toggle bit[25] to change encoding from T2 to T3. */
28202 /* Clear bits[19:16]. */
28203 newval
&= 0xfff0ffff;
28204 /* Encoding high 4bits imm. Code below will encode the
28205 remaining low 12bits. */
28206 newval
|= (value
& 0x0000f000) << 4;
28207 newimm
= value
& 0x00000fff;
28212 if (newimm
== (unsigned int)FAIL
)
28214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28215 _("invalid constant (%lx) after fixup"),
28216 (unsigned long) value
);
28220 newval
|= (newimm
& 0x800) << 15;
28221 newval
|= (newimm
& 0x700) << 4;
28222 newval
|= (newimm
& 0x0ff);
28224 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
28225 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
28228 case BFD_RELOC_ARM_SMC
:
28229 if (((unsigned long) value
) > 0xf)
28230 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28231 _("invalid smc expression"));
28233 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28234 newval
|= (value
& 0xf);
28235 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28238 case BFD_RELOC_ARM_HVC
:
28239 if (((unsigned long) value
) > 0xffff)
28240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28241 _("invalid hvc expression"));
28242 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28243 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
28244 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28247 case BFD_RELOC_ARM_SWI
:
28248 if (fixP
->tc_fix_data
!= 0)
28250 if (((unsigned long) value
) > 0xff)
28251 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28252 _("invalid swi expression"));
28253 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28255 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28259 if (((unsigned long) value
) > 0x00ffffff)
28260 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28261 _("invalid swi expression"));
28262 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28264 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28268 case BFD_RELOC_ARM_MULTI
:
28269 if (((unsigned long) value
) > 0xffff)
28270 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28271 _("invalid expression in load/store multiple"));
28272 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
28273 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28277 case BFD_RELOC_ARM_PCREL_CALL
:
28279 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28281 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28282 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28283 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28284 /* Flip the bl to blx. This is a simple flip
28285 bit here because we generate PCREL_CALL for
28286 unconditional bls. */
28288 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28289 newval
= newval
| 0x10000000;
28290 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28296 goto arm_branch_common
;
28298 case BFD_RELOC_ARM_PCREL_JUMP
:
28299 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28301 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28302 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28303 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28305 /* This would map to a bl<cond>, b<cond>,
28306 b<always> to a Thumb function. We
28307 need to force a relocation for this particular
28309 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28312 /* Fall through. */
28314 case BFD_RELOC_ARM_PLT32
:
28316 case BFD_RELOC_ARM_PCREL_BRANCH
:
28318 goto arm_branch_common
;
28320 case BFD_RELOC_ARM_PCREL_BLX
:
28323 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28325 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28326 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28327 && ARM_IS_FUNC (fixP
->fx_addsy
))
28329 /* Flip the blx to a bl and warn. */
28330 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28331 newval
= 0xeb000000;
28332 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28333 _("blx to '%s' an ARM ISA state function changed to bl"),
28335 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28341 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28342 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
28346 /* We are going to store value (shifted right by two) in the
28347 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28348 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28351 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28352 _("misaligned branch destination"));
28353 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
28354 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
28355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28357 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28359 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28360 newval
|= (value
>> 2) & 0x00ffffff;
28361 /* Set the H bit on BLX instructions. */
28365 newval
|= 0x01000000;
28367 newval
&= ~0x01000000;
28369 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28373 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28374 /* CBZ can only branch forward. */
28376 /* Attempts to use CBZ to branch to the next instruction
28377 (which, strictly speaking, are prohibited) will be turned into
28380 FIXME: It may be better to remove the instruction completely and
28381 perform relaxation. */
28384 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28385 newval
= 0xbf00; /* NOP encoding T1 */
28386 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28391 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28393 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28395 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28396 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28397 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28402 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28403 if (out_of_range_p (value
, 8))
28404 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28406 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28408 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28409 newval
|= (value
& 0x1ff) >> 1;
28410 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28414 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28415 if (out_of_range_p (value
, 11))
28416 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28418 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28420 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28421 newval
|= (value
& 0xfff) >> 1;
28422 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28426 /* This relocation is misnamed, it should be BRANCH21. */
28427 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28429 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28430 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28431 && ARM_IS_FUNC (fixP
->fx_addsy
)
28432 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28434 /* Force a relocation for a branch 20 bits wide. */
28437 if (out_of_range_p (value
, 20))
28438 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28439 _("conditional branch out of range"));
28441 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28444 addressT S
, J1
, J2
, lo
, hi
;
28446 S
= (value
& 0x00100000) >> 20;
28447 J2
= (value
& 0x00080000) >> 19;
28448 J1
= (value
& 0x00040000) >> 18;
28449 hi
= (value
& 0x0003f000) >> 12;
28450 lo
= (value
& 0x00000ffe) >> 1;
28452 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28453 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28454 newval
|= (S
<< 10) | hi
;
28455 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
28456 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28457 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28461 case BFD_RELOC_THUMB_PCREL_BLX
:
28462 /* If there is a blx from a thumb state function to
28463 another thumb function flip this to a bl and warn
28467 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28468 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28469 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28471 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28472 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28473 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
28475 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28476 newval
= newval
| 0x1000;
28477 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28478 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28483 goto thumb_bl_common
;
28485 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28486 /* A bl from Thumb state ISA to an internal ARM state function
28487 is converted to a blx. */
28489 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28490 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28491 && ARM_IS_FUNC (fixP
->fx_addsy
)
28492 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28494 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28495 newval
= newval
& ~0x1000;
28496 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28497 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
28503 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28504 /* For a BLX instruction, make sure that the relocation is rounded up
28505 to a word boundary. This follows the semantics of the instruction
28506 which specifies that bit 1 of the target address will come from bit
28507 1 of the base address. */
28508 value
= (value
+ 3) & ~ 3;
28511 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
28512 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28513 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28516 if (out_of_range_p (value
, 22))
28518 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
28519 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28520 else if (out_of_range_p (value
, 24))
28521 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28522 _("Thumb2 branch out of range"));
28525 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28526 encode_thumb2_b_bl_offset (buf
, value
);
28530 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28531 if (out_of_range_p (value
, 24))
28532 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28534 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28535 encode_thumb2_b_bl_offset (buf
, value
);
28540 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28545 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28546 md_number_to_chars (buf
, value
, 2);
28550 case BFD_RELOC_ARM_TLS_CALL
:
28551 case BFD_RELOC_ARM_THM_TLS_CALL
:
28552 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28553 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28554 case BFD_RELOC_ARM_TLS_GOTDESC
:
28555 case BFD_RELOC_ARM_TLS_GD32
:
28556 case BFD_RELOC_ARM_TLS_LE32
:
28557 case BFD_RELOC_ARM_TLS_IE32
:
28558 case BFD_RELOC_ARM_TLS_LDM32
:
28559 case BFD_RELOC_ARM_TLS_LDO32
:
28560 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28563 /* Same handling as above, but with the arm_fdpic guard. */
28564 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28565 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28566 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28569 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28573 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28574 _("Relocation supported only in FDPIC mode"));
28578 case BFD_RELOC_ARM_GOT32
:
28579 case BFD_RELOC_ARM_GOTOFF
:
28582 case BFD_RELOC_ARM_GOT_PREL
:
28583 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28584 md_number_to_chars (buf
, value
, 4);
28587 case BFD_RELOC_ARM_TARGET2
:
28588 /* TARGET2 is not partial-inplace, so we need to write the
28589 addend here for REL targets, because it won't be written out
28590 during reloc processing later. */
28591 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28592 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
28595 /* Relocations for FDPIC. */
28596 case BFD_RELOC_ARM_GOTFUNCDESC
:
28597 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28598 case BFD_RELOC_ARM_FUNCDESC
:
28601 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28602 md_number_to_chars (buf
, 0, 4);
28606 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28607 _("Relocation supported only in FDPIC mode"));
28612 case BFD_RELOC_RVA
:
28614 case BFD_RELOC_ARM_TARGET1
:
28615 case BFD_RELOC_ARM_ROSEGREL32
:
28616 case BFD_RELOC_ARM_SBREL32
:
28617 case BFD_RELOC_32_PCREL
:
28619 case BFD_RELOC_32_SECREL
:
28621 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28623 /* For WinCE we only do this for pcrel fixups. */
28624 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
28626 md_number_to_chars (buf
, value
, 4);
28630 case BFD_RELOC_ARM_PREL31
:
28631 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28633 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
28634 if ((value
^ (value
>> 1)) & 0x40000000)
28636 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28637 _("rel31 relocation overflow"));
28639 newval
|= value
& 0x7fffffff;
28640 md_number_to_chars (buf
, newval
, 4);
28645 case BFD_RELOC_ARM_CP_OFF_IMM
:
28646 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
28647 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
28648 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
28649 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28651 newval
= get_thumb32_insn (buf
);
28652 if ((newval
& 0x0f200f00) == 0x0d000900)
28654 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28655 has permitted values that are multiples of 2, in the range 0
28657 if (value
< -510 || value
> 510 || (value
& 1))
28658 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28659 _("co-processor offset out of range"));
28661 else if ((newval
& 0xfe001f80) == 0xec000f80)
28663 if (value
< -511 || value
> 512 || (value
& 3))
28664 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28665 _("co-processor offset out of range"));
28667 else if (value
< -1023 || value
> 1023 || (value
& 3))
28668 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28669 _("co-processor offset out of range"));
28674 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28675 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28676 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28678 newval
= get_thumb32_insn (buf
);
28681 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28682 newval
&= 0xffffff80;
28684 newval
&= 0xffffff00;
28688 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28689 newval
&= 0xff7fff80;
28691 newval
&= 0xff7fff00;
28692 if ((newval
& 0x0f200f00) == 0x0d000900)
28694 /* This is a fp16 vstr/vldr.
28696 It requires the immediate offset in the instruction is shifted
28697 left by 1 to be a half-word offset.
28699 Here, left shift by 1 first, and later right shift by 2
28700 should get the right offset. */
28703 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
28705 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28706 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28707 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28709 put_thumb32_insn (buf
, newval
);
28712 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
28713 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
28714 if (value
< -255 || value
> 255)
28715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28716 _("co-processor offset out of range"));
28718 goto cp_off_common
;
28720 case BFD_RELOC_ARM_THUMB_OFFSET
:
28721 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28722 /* Exactly what ranges, and where the offset is inserted depends
28723 on the type of instruction, we can establish this from the
28725 switch (newval
>> 12)
28727 case 4: /* PC load. */
28728 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28729 forced to zero for these loads; md_pcrel_from has already
28730 compensated for this. */
28732 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28733 _("invalid offset, target not word aligned (0x%08lX)"),
28734 (((unsigned long) fixP
->fx_frag
->fr_address
28735 + (unsigned long) fixP
->fx_where
) & ~3)
28736 + (unsigned long) value
);
28738 if (value
& ~0x3fc)
28739 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28740 _("invalid offset, value too big (0x%08lX)"),
28743 newval
|= value
>> 2;
28746 case 9: /* SP load/store. */
28747 if (value
& ~0x3fc)
28748 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28749 _("invalid offset, value too big (0x%08lX)"),
28751 newval
|= value
>> 2;
28754 case 6: /* Word load/store. */
28756 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28757 _("invalid offset, value too big (0x%08lX)"),
28759 newval
|= value
<< 4; /* 6 - 2. */
28762 case 7: /* Byte load/store. */
28764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28765 _("invalid offset, value too big (0x%08lX)"),
28767 newval
|= value
<< 6;
28770 case 8: /* Halfword load/store. */
28772 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28773 _("invalid offset, value too big (0x%08lX)"),
28775 newval
|= value
<< 5; /* 6 - 1. */
28779 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28780 "Unable to process relocation for thumb opcode: %lx",
28781 (unsigned long) newval
);
28784 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28787 case BFD_RELOC_ARM_THUMB_ADD
:
28788 /* This is a complicated relocation, since we use it for all of
28789 the following immediate relocations:
28793 9bit ADD/SUB SP word-aligned
28794 10bit ADD PC/SP word-aligned
28796 The type of instruction being processed is encoded in the
28803 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28805 int rd
= (newval
>> 4) & 0xf;
28806 int rs
= newval
& 0xf;
28807 int subtract
= !!(newval
& 0x8000);
28809 /* Check for HI regs, only very restricted cases allowed:
28810 Adjusting SP, and using PC or SP to get an address. */
28811 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28812 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28814 _("invalid Hi register with immediate"));
28816 /* If value is negative, choose the opposite instruction. */
28820 subtract
= !subtract
;
28822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28823 _("immediate value out of range"));
28828 if (value
& ~0x1fc)
28829 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28830 _("invalid immediate for stack address calculation"));
28831 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28832 newval
|= value
>> 2;
28834 else if (rs
== REG_PC
|| rs
== REG_SP
)
28836 /* PR gas/18541. If the addition is for a defined symbol
28837 within range of an ADR instruction then accept it. */
28840 && fixP
->fx_addsy
!= NULL
)
28844 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28845 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28846 || S_IS_WEAK (fixP
->fx_addsy
))
28848 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28849 _("address calculation needs a strongly defined nearby symbol"));
28853 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28855 /* Round up to the next 4-byte boundary. */
28860 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28864 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28865 _("symbol too far away"));
28875 if (subtract
|| value
& ~0x3fc)
28876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28877 _("invalid immediate for address calculation (value = 0x%08lX)"),
28878 (unsigned long) (subtract
? - value
: value
));
28879 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28881 newval
|= value
>> 2;
28886 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28887 _("immediate value out of range"));
28888 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28889 newval
|= (rd
<< 8) | value
;
28894 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28895 _("immediate value out of range"));
28896 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28897 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28900 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28903 case BFD_RELOC_ARM_THUMB_IMM
:
28904 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28905 if (value
< 0 || value
> 255)
28906 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28907 _("invalid immediate: %ld is out of range"),
28910 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28913 case BFD_RELOC_ARM_THUMB_SHIFT
:
28914 /* 5bit shift value (0..32). LSL cannot take 32. */
28915 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28916 temp
= newval
& 0xf800;
28917 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28918 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28919 _("invalid shift value: %ld"), (long) value
);
28920 /* Shifts of zero must be encoded as LSL. */
28922 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28923 /* Shifts of 32 are encoded as zero. */
28924 else if (value
== 32)
28926 newval
|= value
<< 6;
28927 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28930 case BFD_RELOC_VTABLE_INHERIT
:
28931 case BFD_RELOC_VTABLE_ENTRY
:
28935 case BFD_RELOC_ARM_MOVW
:
28936 case BFD_RELOC_ARM_MOVT
:
28937 case BFD_RELOC_ARM_THUMB_MOVW
:
28938 case BFD_RELOC_ARM_THUMB_MOVT
:
28939 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28941 /* REL format relocations are limited to a 16-bit addend. */
28942 if (!fixP
->fx_done
)
28944 if (value
< -0x8000 || value
> 0x7fff)
28945 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28946 _("offset out of range"));
28948 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28949 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28954 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28955 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28957 newval
= get_thumb32_insn (buf
);
28958 newval
&= 0xfbf08f00;
28959 newval
|= (value
& 0xf000) << 4;
28960 newval
|= (value
& 0x0800) << 15;
28961 newval
|= (value
& 0x0700) << 4;
28962 newval
|= (value
& 0x00ff);
28963 put_thumb32_insn (buf
, newval
);
28967 newval
= md_chars_to_number (buf
, 4);
28968 newval
&= 0xfff0f000;
28969 newval
|= value
& 0x0fff;
28970 newval
|= (value
& 0xf000) << 4;
28971 md_number_to_chars (buf
, newval
, 4);
28976 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28977 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28978 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28979 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28980 gas_assert (!fixP
->fx_done
);
28983 bfd_boolean is_mov
;
28984 bfd_vma encoded_addend
= value
;
28986 /* Check that addend can be encoded in instruction. */
28987 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28988 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28989 _("the offset 0x%08lX is not representable"),
28990 (unsigned long) encoded_addend
);
28992 /* Extract the instruction. */
28993 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28994 is_mov
= (insn
& 0xf800) == 0x2000;
28999 if (!seg
->use_rela_p
)
29000 insn
|= encoded_addend
;
29006 /* Extract the instruction. */
29007 /* Encoding is the following
29012 /* The following conditions must be true :
29017 rd
= (insn
>> 4) & 0xf;
29019 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
29020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29021 _("Unable to process relocation for thumb opcode: %lx"),
29022 (unsigned long) insn
);
29024 /* Encode as ADD immediate8 thumb 1 code. */
29025 insn
= 0x3000 | (rd
<< 8);
29027 /* Place the encoded addend into the first 8 bits of the
29029 if (!seg
->use_rela_p
)
29030 insn
|= encoded_addend
;
29033 /* Update the instruction. */
29034 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
29038 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29039 case BFD_RELOC_ARM_ALU_PC_G0
:
29040 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29041 case BFD_RELOC_ARM_ALU_PC_G1
:
29042 case BFD_RELOC_ARM_ALU_PC_G2
:
29043 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29044 case BFD_RELOC_ARM_ALU_SB_G0
:
29045 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29046 case BFD_RELOC_ARM_ALU_SB_G1
:
29047 case BFD_RELOC_ARM_ALU_SB_G2
:
29048 gas_assert (!fixP
->fx_done
);
29049 if (!seg
->use_rela_p
)
29052 bfd_vma encoded_addend
;
29053 bfd_vma addend_abs
= llabs (value
);
29055 /* Check that the absolute value of the addend can be
29056 expressed as an 8-bit constant plus a rotation. */
29057 encoded_addend
= encode_arm_immediate (addend_abs
);
29058 if (encoded_addend
== (unsigned int) FAIL
)
29059 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29060 _("the offset 0x%08lX is not representable"),
29061 (unsigned long) addend_abs
);
29063 /* Extract the instruction. */
29064 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29066 /* If the addend is positive, use an ADD instruction.
29067 Otherwise use a SUB. Take care not to destroy the S bit. */
29068 insn
&= 0xff1fffff;
29074 /* Place the encoded addend into the first 12 bits of the
29076 insn
&= 0xfffff000;
29077 insn
|= encoded_addend
;
29079 /* Update the instruction. */
29080 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29084 case BFD_RELOC_ARM_LDR_PC_G0
:
29085 case BFD_RELOC_ARM_LDR_PC_G1
:
29086 case BFD_RELOC_ARM_LDR_PC_G2
:
29087 case BFD_RELOC_ARM_LDR_SB_G0
:
29088 case BFD_RELOC_ARM_LDR_SB_G1
:
29089 case BFD_RELOC_ARM_LDR_SB_G2
:
29090 gas_assert (!fixP
->fx_done
);
29091 if (!seg
->use_rela_p
)
29094 bfd_vma addend_abs
= llabs (value
);
29096 /* Check that the absolute value of the addend can be
29097 encoded in 12 bits. */
29098 if (addend_abs
>= 0x1000)
29099 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29100 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
29101 (unsigned long) addend_abs
);
29103 /* Extract the instruction. */
29104 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29106 /* If the addend is negative, clear bit 23 of the instruction.
29107 Otherwise set it. */
29109 insn
&= ~(1 << 23);
29113 /* Place the absolute value of the addend into the first 12 bits
29114 of the instruction. */
29115 insn
&= 0xfffff000;
29116 insn
|= addend_abs
;
29118 /* Update the instruction. */
29119 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29123 case BFD_RELOC_ARM_LDRS_PC_G0
:
29124 case BFD_RELOC_ARM_LDRS_PC_G1
:
29125 case BFD_RELOC_ARM_LDRS_PC_G2
:
29126 case BFD_RELOC_ARM_LDRS_SB_G0
:
29127 case BFD_RELOC_ARM_LDRS_SB_G1
:
29128 case BFD_RELOC_ARM_LDRS_SB_G2
:
29129 gas_assert (!fixP
->fx_done
);
29130 if (!seg
->use_rela_p
)
29133 bfd_vma addend_abs
= llabs (value
);
29135 /* Check that the absolute value of the addend can be
29136 encoded in 8 bits. */
29137 if (addend_abs
>= 0x100)
29138 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29139 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29140 (unsigned long) addend_abs
);
29142 /* Extract the instruction. */
29143 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29145 /* If the addend is negative, clear bit 23 of the instruction.
29146 Otherwise set it. */
29148 insn
&= ~(1 << 23);
29152 /* Place the first four bits of the absolute value of the addend
29153 into the first 4 bits of the instruction, and the remaining
29154 four into bits 8 .. 11. */
29155 insn
&= 0xfffff0f0;
29156 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
29158 /* Update the instruction. */
29159 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29163 case BFD_RELOC_ARM_LDC_PC_G0
:
29164 case BFD_RELOC_ARM_LDC_PC_G1
:
29165 case BFD_RELOC_ARM_LDC_PC_G2
:
29166 case BFD_RELOC_ARM_LDC_SB_G0
:
29167 case BFD_RELOC_ARM_LDC_SB_G1
:
29168 case BFD_RELOC_ARM_LDC_SB_G2
:
29169 gas_assert (!fixP
->fx_done
);
29170 if (!seg
->use_rela_p
)
29173 bfd_vma addend_abs
= llabs (value
);
29175 /* Check that the absolute value of the addend is a multiple of
29176 four and, when divided by four, fits in 8 bits. */
29177 if (addend_abs
& 0x3)
29178 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29179 _("bad offset 0x%08lX (must be word-aligned)"),
29180 (unsigned long) addend_abs
);
29182 if ((addend_abs
>> 2) > 0xff)
29183 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29184 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29185 (unsigned long) addend_abs
);
29187 /* Extract the instruction. */
29188 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29190 /* If the addend is negative, clear bit 23 of the instruction.
29191 Otherwise set it. */
29193 insn
&= ~(1 << 23);
29197 /* Place the addend (divided by four) into the first eight
29198 bits of the instruction. */
29199 insn
&= 0xfffffff0;
29200 insn
|= addend_abs
>> 2;
29202 /* Update the instruction. */
29203 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29207 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29209 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29210 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29211 && ARM_IS_FUNC (fixP
->fx_addsy
)
29212 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29214 /* Force a relocation for a branch 5 bits wide. */
29217 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
29218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29221 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29223 addressT boff
= value
>> 1;
29225 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29226 newval
|= (boff
<< 7);
29227 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29231 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29233 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29234 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29235 && ARM_IS_FUNC (fixP
->fx_addsy
)
29236 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29240 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
29241 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29242 _("branch out of range"));
29244 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29246 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29248 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
29249 addressT diff
= value
- boff
;
29253 newval
|= 1 << 1; /* T bit. */
29255 else if (diff
!= 2)
29257 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29258 _("out of range label-relative fixup value"));
29260 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29264 case BFD_RELOC_ARM_THUMB_BF17
:
29266 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29267 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29268 && ARM_IS_FUNC (fixP
->fx_addsy
)
29269 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29271 /* Force a relocation for a branch 17 bits wide. */
29275 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
29276 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29279 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29282 addressT immA
, immB
, immC
;
29284 immA
= (value
& 0x0001f000) >> 12;
29285 immB
= (value
& 0x00000ffc) >> 2;
29286 immC
= (value
& 0x00000002) >> 1;
29288 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29289 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29291 newval2
|= (immC
<< 11) | (immB
<< 1);
29292 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29293 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29297 case BFD_RELOC_ARM_THUMB_BF19
:
29299 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29300 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29301 && ARM_IS_FUNC (fixP
->fx_addsy
)
29302 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29304 /* Force a relocation for a branch 19 bits wide. */
29308 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
29309 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29312 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29315 addressT immA
, immB
, immC
;
29317 immA
= (value
& 0x0007f000) >> 12;
29318 immB
= (value
& 0x00000ffc) >> 2;
29319 immC
= (value
& 0x00000002) >> 1;
29321 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29322 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29324 newval2
|= (immC
<< 11) | (immB
<< 1);
29325 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29326 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29330 case BFD_RELOC_ARM_THUMB_BF13
:
29332 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29333 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29334 && ARM_IS_FUNC (fixP
->fx_addsy
)
29335 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29337 /* Force a relocation for a branch 13 bits wide. */
29341 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
29342 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29345 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29348 addressT immA
, immB
, immC
;
29350 immA
= (value
& 0x00001000) >> 12;
29351 immB
= (value
& 0x00000ffc) >> 2;
29352 immC
= (value
& 0x00000002) >> 1;
29354 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29355 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29357 newval2
|= (immC
<< 11) | (immB
<< 1);
29358 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29359 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29363 case BFD_RELOC_ARM_THUMB_LOOP12
:
29365 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29366 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29367 && ARM_IS_FUNC (fixP
->fx_addsy
)
29368 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29370 /* Force a relocation for a branch 12 bits wide. */
29374 bfd_vma insn
= get_thumb32_insn (buf
);
29375 /* le lr, <label>, le <label> or letp lr, <label> */
29376 if (((insn
& 0xffffffff) == 0xf00fc001)
29377 || ((insn
& 0xffffffff) == 0xf02fc001)
29378 || ((insn
& 0xffffffff) == 0xf01fc001))
29381 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29382 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29384 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29386 addressT imml
, immh
;
29388 immh
= (value
& 0x00000ffc) >> 2;
29389 imml
= (value
& 0x00000002) >> 1;
29391 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29392 newval
|= (imml
<< 11) | (immh
<< 1);
29393 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29397 case BFD_RELOC_ARM_V4BX
:
29398 /* This will need to go in the object file. */
29402 case BFD_RELOC_UNUSED
:
29404 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29405 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29409 /* Translate internal representation of relocation info to BFD target
29413 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29416 bfd_reloc_code_real_type code
;
29418 reloc
= XNEW (arelent
);
29420 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29421 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29422 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
29424 if (fixp
->fx_pcrel
)
29426 if (section
->use_rela_p
)
29427 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
29429 fixp
->fx_offset
= reloc
->address
;
29431 reloc
->addend
= fixp
->fx_offset
;
29433 switch (fixp
->fx_r_type
)
29436 if (fixp
->fx_pcrel
)
29438 code
= BFD_RELOC_8_PCREL
;
29441 /* Fall through. */
29444 if (fixp
->fx_pcrel
)
29446 code
= BFD_RELOC_16_PCREL
;
29449 /* Fall through. */
29452 if (fixp
->fx_pcrel
)
29454 code
= BFD_RELOC_32_PCREL
;
29457 /* Fall through. */
29459 case BFD_RELOC_ARM_MOVW
:
29460 if (fixp
->fx_pcrel
)
29462 code
= BFD_RELOC_ARM_MOVW_PCREL
;
29465 /* Fall through. */
29467 case BFD_RELOC_ARM_MOVT
:
29468 if (fixp
->fx_pcrel
)
29470 code
= BFD_RELOC_ARM_MOVT_PCREL
;
29473 /* Fall through. */
29475 case BFD_RELOC_ARM_THUMB_MOVW
:
29476 if (fixp
->fx_pcrel
)
29478 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
29481 /* Fall through. */
29483 case BFD_RELOC_ARM_THUMB_MOVT
:
29484 if (fixp
->fx_pcrel
)
29486 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
29489 /* Fall through. */
29491 case BFD_RELOC_NONE
:
29492 case BFD_RELOC_ARM_PCREL_BRANCH
:
29493 case BFD_RELOC_ARM_PCREL_BLX
:
29494 case BFD_RELOC_RVA
:
29495 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
29496 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
29497 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
29498 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29499 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29500 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29501 case BFD_RELOC_VTABLE_ENTRY
:
29502 case BFD_RELOC_VTABLE_INHERIT
:
29504 case BFD_RELOC_32_SECREL
:
29506 code
= fixp
->fx_r_type
;
29509 case BFD_RELOC_THUMB_PCREL_BLX
:
29511 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
29512 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29515 code
= BFD_RELOC_THUMB_PCREL_BLX
;
29518 case BFD_RELOC_ARM_LITERAL
:
29519 case BFD_RELOC_ARM_HWLITERAL
:
29520 /* If this is called then the a literal has
29521 been referenced across a section boundary. */
29522 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29523 _("literal referenced across section boundary"));
29527 case BFD_RELOC_ARM_TLS_CALL
:
29528 case BFD_RELOC_ARM_THM_TLS_CALL
:
29529 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29530 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29531 case BFD_RELOC_ARM_GOT32
:
29532 case BFD_RELOC_ARM_GOTOFF
:
29533 case BFD_RELOC_ARM_GOT_PREL
:
29534 case BFD_RELOC_ARM_PLT32
:
29535 case BFD_RELOC_ARM_TARGET1
:
29536 case BFD_RELOC_ARM_ROSEGREL32
:
29537 case BFD_RELOC_ARM_SBREL32
:
29538 case BFD_RELOC_ARM_PREL31
:
29539 case BFD_RELOC_ARM_TARGET2
:
29540 case BFD_RELOC_ARM_TLS_LDO32
:
29541 case BFD_RELOC_ARM_PCREL_CALL
:
29542 case BFD_RELOC_ARM_PCREL_JUMP
:
29543 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29544 case BFD_RELOC_ARM_ALU_PC_G0
:
29545 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29546 case BFD_RELOC_ARM_ALU_PC_G1
:
29547 case BFD_RELOC_ARM_ALU_PC_G2
:
29548 case BFD_RELOC_ARM_LDR_PC_G0
:
29549 case BFD_RELOC_ARM_LDR_PC_G1
:
29550 case BFD_RELOC_ARM_LDR_PC_G2
:
29551 case BFD_RELOC_ARM_LDRS_PC_G0
:
29552 case BFD_RELOC_ARM_LDRS_PC_G1
:
29553 case BFD_RELOC_ARM_LDRS_PC_G2
:
29554 case BFD_RELOC_ARM_LDC_PC_G0
:
29555 case BFD_RELOC_ARM_LDC_PC_G1
:
29556 case BFD_RELOC_ARM_LDC_PC_G2
:
29557 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29558 case BFD_RELOC_ARM_ALU_SB_G0
:
29559 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29560 case BFD_RELOC_ARM_ALU_SB_G1
:
29561 case BFD_RELOC_ARM_ALU_SB_G2
:
29562 case BFD_RELOC_ARM_LDR_SB_G0
:
29563 case BFD_RELOC_ARM_LDR_SB_G1
:
29564 case BFD_RELOC_ARM_LDR_SB_G2
:
29565 case BFD_RELOC_ARM_LDRS_SB_G0
:
29566 case BFD_RELOC_ARM_LDRS_SB_G1
:
29567 case BFD_RELOC_ARM_LDRS_SB_G2
:
29568 case BFD_RELOC_ARM_LDC_SB_G0
:
29569 case BFD_RELOC_ARM_LDC_SB_G1
:
29570 case BFD_RELOC_ARM_LDC_SB_G2
:
29571 case BFD_RELOC_ARM_V4BX
:
29572 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29573 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29574 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29575 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29576 case BFD_RELOC_ARM_GOTFUNCDESC
:
29577 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29578 case BFD_RELOC_ARM_FUNCDESC
:
29579 case BFD_RELOC_ARM_THUMB_BF17
:
29580 case BFD_RELOC_ARM_THUMB_BF19
:
29581 case BFD_RELOC_ARM_THUMB_BF13
:
29582 code
= fixp
->fx_r_type
;
29585 case BFD_RELOC_ARM_TLS_GOTDESC
:
29586 case BFD_RELOC_ARM_TLS_GD32
:
29587 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29588 case BFD_RELOC_ARM_TLS_LE32
:
29589 case BFD_RELOC_ARM_TLS_IE32
:
29590 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29591 case BFD_RELOC_ARM_TLS_LDM32
:
29592 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29593 /* BFD will include the symbol's address in the addend.
29594 But we don't want that, so subtract it out again here. */
29595 if (!S_IS_COMMON (fixp
->fx_addsy
))
29596 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
29597 code
= fixp
->fx_r_type
;
29601 case BFD_RELOC_ARM_IMMEDIATE
:
29602 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29603 _("internal relocation (type: IMMEDIATE) not fixed up"));
29606 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
29607 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29608 _("ADRL used for a symbol not defined in the same file"));
29611 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29612 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29613 case BFD_RELOC_ARM_THUMB_LOOP12
:
29614 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29615 _("%s used for a symbol not defined in the same file"),
29616 bfd_get_reloc_code_name (fixp
->fx_r_type
));
29619 case BFD_RELOC_ARM_OFFSET_IMM
:
29620 if (section
->use_rela_p
)
29622 code
= fixp
->fx_r_type
;
29626 if (fixp
->fx_addsy
!= NULL
29627 && !S_IS_DEFINED (fixp
->fx_addsy
)
29628 && S_IS_LOCAL (fixp
->fx_addsy
))
29630 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29631 _("undefined local label `%s'"),
29632 S_GET_NAME (fixp
->fx_addsy
));
29636 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29637 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29644 switch (fixp
->fx_r_type
)
29646 case BFD_RELOC_NONE
: type
= "NONE"; break;
29647 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
29648 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
29649 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
29650 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
29651 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
29652 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
29653 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
29654 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
29655 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
29656 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
29657 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
29658 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
29659 default: type
= _("<unknown>"); break;
29661 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29662 _("cannot represent %s relocation in this object file format"),
29669 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
29671 && fixp
->fx_addsy
== GOT_symbol
)
29673 code
= BFD_RELOC_ARM_GOTPC
;
29674 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
29678 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
29680 if (reloc
->howto
== NULL
)
29682 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29683 _("cannot represent %s relocation in this object file format"),
29684 bfd_get_reloc_code_name (code
));
29688 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29689 vtable entry to be used in the relocation's section offset. */
29690 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29691 reloc
->address
= fixp
->fx_offset
;
29696 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
29699 cons_fix_new_arm (fragS
* frag
,
29703 bfd_reloc_code_real_type reloc
)
29708 FIXME: @@ Should look at CPU word size. */
29712 reloc
= BFD_RELOC_8
;
29715 reloc
= BFD_RELOC_16
;
29719 reloc
= BFD_RELOC_32
;
29722 reloc
= BFD_RELOC_64
;
29727 if (exp
->X_op
== O_secrel
)
29729 exp
->X_op
= O_symbol
;
29730 reloc
= BFD_RELOC_32_SECREL
;
29734 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29737 #if defined (OBJ_COFF)
29739 arm_validate_fix (fixS
* fixP
)
29741 /* If the destination of the branch is a defined symbol which does not have
29742 the THUMB_FUNC attribute, then we must be calling a function which has
29743 the (interfacearm) attribute. We look for the Thumb entry point to that
29744 function and change the branch to refer to that function instead. */
29745 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29746 && fixP
->fx_addsy
!= NULL
29747 && S_IS_DEFINED (fixP
->fx_addsy
)
29748 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29750 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29757 arm_force_relocation (struct fix
* fixp
)
29759 #if defined (OBJ_COFF) && defined (TE_PE)
29760 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29764 /* In case we have a call or a branch to a function in ARM ISA mode from
29765 a thumb function or vice-versa force the relocation. These relocations
29766 are cleared off for some cores that might have blx and simple transformations
29770 switch (fixp
->fx_r_type
)
29772 case BFD_RELOC_ARM_PCREL_JUMP
:
29773 case BFD_RELOC_ARM_PCREL_CALL
:
29774 case BFD_RELOC_THUMB_PCREL_BLX
:
29775 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29779 case BFD_RELOC_ARM_PCREL_BLX
:
29780 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29781 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29782 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29783 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29792 /* Resolve these relocations even if the symbol is extern or weak.
29793 Technically this is probably wrong due to symbol preemption.
29794 In practice these relocations do not have enough range to be useful
29795 at dynamic link time, and some code (e.g. in the Linux kernel)
29796 expects these references to be resolved. */
29797 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29798 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29799 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29800 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29801 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29802 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29803 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29804 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29805 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29806 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29807 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29808 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29809 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29810 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29813 /* Always leave these relocations for the linker. */
29814 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29815 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29816 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29819 /* Always generate relocations against function symbols. */
29820 if (fixp
->fx_r_type
== BFD_RELOC_32
29822 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29825 return generic_force_reloc (fixp
);
29828 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29829 /* Relocations against function names must be left unadjusted,
29830 so that the linker can use this information to generate interworking
29831 stubs. The MIPS version of this function
29832 also prevents relocations that are mips-16 specific, but I do not
29833 know why it does this.
29836 There is one other problem that ought to be addressed here, but
29837 which currently is not: Taking the address of a label (rather
29838 than a function) and then later jumping to that address. Such
29839 addresses also ought to have their bottom bit set (assuming that
29840 they reside in Thumb code), but at the moment they will not. */
29843 arm_fix_adjustable (fixS
* fixP
)
29845 if (fixP
->fx_addsy
== NULL
)
29848 /* Preserve relocations against symbols with function type. */
29849 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29852 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29853 && fixP
->fx_subsy
== NULL
)
29856 /* We need the symbol name for the VTABLE entries. */
29857 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29858 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29861 /* Don't allow symbols to be discarded on GOT related relocs. */
29862 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29863 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29864 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29865 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29866 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29867 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29868 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29869 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29870 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29871 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29872 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29873 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29874 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29875 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29876 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29877 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29878 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29881 /* Similarly for group relocations. */
29882 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29883 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29884 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29887 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29888 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29889 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29890 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29891 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29892 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29893 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29894 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29895 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29898 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29899 offsets, so keep these symbols. */
29900 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29901 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29906 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29910 elf32_arm_target_format (void)
29913 return (target_big_endian
29914 ? "elf32-bigarm-symbian"
29915 : "elf32-littlearm-symbian");
29916 #elif defined (TE_VXWORKS)
29917 return (target_big_endian
29918 ? "elf32-bigarm-vxworks"
29919 : "elf32-littlearm-vxworks");
29920 #elif defined (TE_NACL)
29921 return (target_big_endian
29922 ? "elf32-bigarm-nacl"
29923 : "elf32-littlearm-nacl");
29927 if (target_big_endian
)
29928 return "elf32-bigarm-fdpic";
29930 return "elf32-littlearm-fdpic";
29934 if (target_big_endian
)
29935 return "elf32-bigarm";
29937 return "elf32-littlearm";
29943 armelf_frob_symbol (symbolS
* symp
,
29946 elf_frob_symbol (symp
, puntp
);
29950 /* MD interface: Finalization. */
29955 literal_pool
* pool
;
29957 /* Ensure that all the predication blocks are properly closed. */
29958 check_pred_blocks_finished ();
29960 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29962 /* Put it at the end of the relevant section. */
29963 subseg_set (pool
->section
, pool
->sub_section
);
29965 arm_elf_change_section ();
29972 /* Remove any excess mapping symbols generated for alignment frags in
29973 SEC. We may have created a mapping symbol before a zero byte
29974 alignment; remove it if there's a mapping symbol after the
29977 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29978 void *dummy ATTRIBUTE_UNUSED
)
29980 segment_info_type
*seginfo
= seg_info (sec
);
29983 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29986 for (fragp
= seginfo
->frchainP
->frch_root
;
29988 fragp
= fragp
->fr_next
)
29990 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29991 fragS
*next
= fragp
->fr_next
;
29993 /* Variable-sized frags have been converted to fixed size by
29994 this point. But if this was variable-sized to start with,
29995 there will be a fixed-size frag after it. So don't handle
29997 if (sym
== NULL
|| next
== NULL
)
30000 if (S_GET_VALUE (sym
) < next
->fr_address
)
30001 /* Not at the end of this frag. */
30003 know (S_GET_VALUE (sym
) == next
->fr_address
);
30007 if (next
->tc_frag_data
.first_map
!= NULL
)
30009 /* Next frag starts with a mapping symbol. Discard this
30011 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30015 if (next
->fr_next
== NULL
)
30017 /* This mapping symbol is at the end of the section. Discard
30019 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
30020 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30024 /* As long as we have empty frags without any mapping symbols,
30026 /* If the next frag is non-empty and does not start with a
30027 mapping symbol, then this mapping symbol is required. */
30028 if (next
->fr_address
!= next
->fr_next
->fr_address
)
30031 next
= next
->fr_next
;
30033 while (next
!= NULL
);
30038 /* Adjust the symbol table. This marks Thumb symbols as distinct from
30042 arm_adjust_symtab (void)
30047 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30049 if (ARM_IS_THUMB (sym
))
30051 if (THUMB_IS_FUNC (sym
))
30053 /* Mark the symbol as a Thumb function. */
30054 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
30055 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
30056 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
30058 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
30059 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
30061 as_bad (_("%s: unexpected function type: %d"),
30062 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
30064 else switch (S_GET_STORAGE_CLASS (sym
))
30067 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
30070 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
30073 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
30081 if (ARM_IS_INTERWORK (sym
))
30082 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
30089 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30091 if (ARM_IS_THUMB (sym
))
30093 elf_symbol_type
* elf_sym
;
30095 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
30096 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
30098 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
30099 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
30101 /* If it's a .thumb_func, declare it as so,
30102 otherwise tag label as .code 16. */
30103 if (THUMB_IS_FUNC (sym
))
30104 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
30105 ST_BRANCH_TO_THUMB
);
30106 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30107 elf_sym
->internal_elf_sym
.st_info
=
30108 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
30113 /* Remove any overlapping mapping symbols generated by alignment frags. */
30114 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
30115 /* Now do generic ELF adjustments. */
30116 elf_adjust_symtab ();
30120 /* MD interface: Initialization. */
30123 set_constant_flonums (void)
30127 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
30128 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
30132 /* Auto-select Thumb mode if it's the only available instruction set for the
30133 given architecture. */
30136 autoselect_thumb_from_cpu_variant (void)
30138 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
30139 opcode_select (16);
30148 if ( (arm_ops_hsh
= hash_new ()) == NULL
30149 || (arm_cond_hsh
= hash_new ()) == NULL
30150 || (arm_vcond_hsh
= hash_new ()) == NULL
30151 || (arm_shift_hsh
= hash_new ()) == NULL
30152 || (arm_psr_hsh
= hash_new ()) == NULL
30153 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
30154 || (arm_reg_hsh
= hash_new ()) == NULL
30155 || (arm_reloc_hsh
= hash_new ()) == NULL
30156 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
30157 as_fatal (_("virtual memory exhausted"));
30159 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
30160 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
30161 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
30162 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
30163 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
30164 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
30165 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
30166 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
30167 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
30168 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
30169 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
30170 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
30171 (void *) (v7m_psrs
+ i
));
30172 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
30173 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
30175 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
30177 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
30178 (void *) (barrier_opt_names
+ i
));
30180 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
30182 struct reloc_entry
* entry
= reloc_names
+ i
;
30184 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
30185 /* This makes encode_branch() use the EABI versions of this relocation. */
30186 entry
->reloc
= BFD_RELOC_UNUSED
;
30188 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
30192 set_constant_flonums ();
30194 /* Set the cpu variant based on the command-line options. We prefer
30195 -mcpu= over -march= if both are set (as for GCC); and we prefer
30196 -mfpu= over any other way of setting the floating point unit.
30197 Use of legacy options with new options are faulted. */
30200 if (mcpu_cpu_opt
|| march_cpu_opt
)
30201 as_bad (_("use of old and new-style options to set CPU type"));
30203 selected_arch
= *legacy_cpu
;
30205 else if (mcpu_cpu_opt
)
30207 selected_arch
= *mcpu_cpu_opt
;
30208 selected_ext
= *mcpu_ext_opt
;
30210 else if (march_cpu_opt
)
30212 selected_arch
= *march_cpu_opt
;
30213 selected_ext
= *march_ext_opt
;
30215 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30220 as_bad (_("use of old and new-style options to set FPU type"));
30222 selected_fpu
= *legacy_fpu
;
30225 selected_fpu
= *mfpu_opt
;
30228 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30229 || defined (TE_NetBSD) || defined (TE_VXWORKS))
30230 /* Some environments specify a default FPU. If they don't, infer it
30231 from the processor. */
30233 selected_fpu
= *mcpu_fpu_opt
;
30234 else if (march_fpu_opt
)
30235 selected_fpu
= *march_fpu_opt
;
30237 selected_fpu
= fpu_default
;
30241 if (ARM_FEATURE_ZERO (selected_fpu
))
30243 if (!no_cpu_selected ())
30244 selected_fpu
= fpu_default
;
30246 selected_fpu
= fpu_arch_fpa
;
30250 if (ARM_FEATURE_ZERO (selected_arch
))
30252 selected_arch
= cpu_default
;
30253 selected_cpu
= selected_arch
;
30255 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30257 /* Autodection of feature mode: allow all features in cpu_variant but leave
30258 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
30259 after all instruction have been processed and we can decide what CPU
30260 should be selected. */
30261 if (ARM_FEATURE_ZERO (selected_arch
))
30262 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30264 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30267 autoselect_thumb_from_cpu_variant ();
30269 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
30271 #if defined OBJ_COFF || defined OBJ_ELF
30273 unsigned int flags
= 0;
30275 #if defined OBJ_ELF
30276 flags
= meabi_flags
;
30278 switch (meabi_flags
)
30280 case EF_ARM_EABI_UNKNOWN
:
30282 /* Set the flags in the private structure. */
30283 if (uses_apcs_26
) flags
|= F_APCS26
;
30284 if (support_interwork
) flags
|= F_INTERWORK
;
30285 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
30286 if (pic_code
) flags
|= F_PIC
;
30287 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
30288 flags
|= F_SOFT_FLOAT
;
30290 switch (mfloat_abi_opt
)
30292 case ARM_FLOAT_ABI_SOFT
:
30293 case ARM_FLOAT_ABI_SOFTFP
:
30294 flags
|= F_SOFT_FLOAT
;
30297 case ARM_FLOAT_ABI_HARD
:
30298 if (flags
& F_SOFT_FLOAT
)
30299 as_bad (_("hard-float conflicts with specified fpu"));
30303 /* Using pure-endian doubles (even if soft-float). */
30304 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
30305 flags
|= F_VFP_FLOAT
;
30307 #if defined OBJ_ELF
30308 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
30309 flags
|= EF_ARM_MAVERICK_FLOAT
;
30312 case EF_ARM_EABI_VER4
:
30313 case EF_ARM_EABI_VER5
:
30314 /* No additional flags to set. */
30321 bfd_set_private_flags (stdoutput
, flags
);
30323 /* We have run out flags in the COFF header to encode the
30324 status of ATPCS support, so instead we create a dummy,
30325 empty, debug section called .arm.atpcs. */
30330 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
30334 bfd_set_section_flags (sec
, SEC_READONLY
| SEC_DEBUGGING
);
30335 bfd_set_section_size (sec
, 0);
30336 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
30342 /* Record the CPU type as well. */
30343 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
30344 mach
= bfd_mach_arm_iWMMXt2
;
30345 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
30346 mach
= bfd_mach_arm_iWMMXt
;
30347 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
30348 mach
= bfd_mach_arm_XScale
;
30349 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
30350 mach
= bfd_mach_arm_ep9312
;
30351 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
30352 mach
= bfd_mach_arm_5TE
;
30353 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
30355 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30356 mach
= bfd_mach_arm_5T
;
30358 mach
= bfd_mach_arm_5
;
30360 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30362 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30363 mach
= bfd_mach_arm_4T
;
30365 mach
= bfd_mach_arm_4
;
30367 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30368 mach
= bfd_mach_arm_3M
;
30369 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30370 mach
= bfd_mach_arm_3
;
30371 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30372 mach
= bfd_mach_arm_2a
;
30373 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30374 mach
= bfd_mach_arm_2
;
30376 mach
= bfd_mach_arm_unknown
;
30378 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30381 /* Command line processing. */
30384 Invocation line includes a switch not recognized by the base assembler.
30385 See if it's a processor-specific option.
30387 This routine is somewhat complicated by the need for backwards
30388 compatibility (since older releases of gcc can't be changed).
30389 The new options try to make the interface as compatible as
30392 New options (supported) are:
30394 -mcpu=<cpu name> Assemble for selected processor
30395 -march=<architecture name> Assemble for selected architecture
30396 -mfpu=<fpu architecture> Assemble for selected FPU.
30397 -EB/-mbig-endian Big-endian
30398 -EL/-mlittle-endian Little-endian
30399 -k Generate PIC code
30400 -mthumb Start in Thumb mode
30401 -mthumb-interwork Code supports ARM/Thumb interworking
30403 -m[no-]warn-deprecated Warn about deprecated features
30404 -m[no-]warn-syms Warn when symbols match instructions
30406 For now we will also provide support for:
30408 -mapcs-32 32-bit Program counter
30409 -mapcs-26 26-bit Program counter
30410 -macps-float Floats passed in FP registers
30411 -mapcs-reentrant Reentrant code
30413 (sometime these will probably be replaced with -mapcs=<list of options>
30414 and -matpcs=<list of options>)
30416 The remaining options are only supported for back-wards compatibility.
30417 Cpu variants, the arm part is optional:
30418 -m[arm]1 Currently not supported.
30419 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30420 -m[arm]3 Arm 3 processor
30421 -m[arm]6[xx], Arm 6 processors
30422 -m[arm]7[xx][t][[d]m] Arm 7 processors
30423 -m[arm]8[10] Arm 8 processors
30424 -m[arm]9[20][tdmi] Arm 9 processors
30425 -mstrongarm[110[0]] StrongARM processors
30426 -mxscale XScale processors
30427 -m[arm]v[2345[t[e]]] Arm architectures
30428 -mall All (except the ARM1)
30430 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
30431 -mfpe-old (No float load/store multiples)
30432 -mvfpxd VFP Single precision
30434 -mno-fpu Disable all floating point instructions
30436 The following CPU names are recognized:
30437 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
30438 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
30439 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
30440 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
30441 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
30442 arm10t arm10e, arm1020t, arm1020e, arm10200e,
30443 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
30447 const char * md_shortopts
= "m:k";
30449 #ifdef ARM_BI_ENDIAN
30450 #define OPTION_EB (OPTION_MD_BASE + 0)
30451 #define OPTION_EL (OPTION_MD_BASE + 1)
30453 #if TARGET_BYTES_BIG_ENDIAN
30454 #define OPTION_EB (OPTION_MD_BASE + 0)
30456 #define OPTION_EL (OPTION_MD_BASE + 1)
30459 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
30460 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
30462 struct option md_longopts
[] =
30465 {"EB", no_argument
, NULL
, OPTION_EB
},
30468 {"EL", no_argument
, NULL
, OPTION_EL
},
30470 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
30472 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
30474 {NULL
, no_argument
, NULL
, 0}
30477 size_t md_longopts_size
= sizeof (md_longopts
);
30479 struct arm_option_table
30481 const char * option
; /* Option name to match. */
30482 const char * help
; /* Help information. */
30483 int * var
; /* Variable to change. */
30484 int value
; /* What to change it to. */
30485 const char * deprecated
; /* If non-null, print this message. */
30488 struct arm_option_table arm_opts
[] =
30490 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
30491 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
30492 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
30493 &support_interwork
, 1, NULL
},
30494 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
30495 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
30496 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
30498 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
30499 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
30500 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
30501 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
30504 /* These are recognized by the assembler, but have no affect on code. */
30505 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
30506 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
30508 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
30509 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
30510 &warn_on_deprecated
, 0, NULL
},
30511 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
30512 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
30513 {NULL
, NULL
, NULL
, 0, NULL
}
30516 struct arm_legacy_option_table
30518 const char * option
; /* Option name to match. */
30519 const arm_feature_set
** var
; /* Variable to change. */
30520 const arm_feature_set value
; /* What to change it to. */
30521 const char * deprecated
; /* If non-null, print this message. */
30524 const struct arm_legacy_option_table arm_legacy_opts
[] =
30526 /* DON'T add any new processors to this list -- we want the whole list
30527 to go away... Add them to the processors table instead. */
30528 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30529 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30530 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30531 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30532 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30533 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30534 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30535 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30536 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30537 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30538 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30539 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30540 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30541 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30542 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30543 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30544 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30545 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30546 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30547 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30548 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30549 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30550 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30551 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30552 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30553 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30554 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30555 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30556 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30557 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30558 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30559 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30560 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30561 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30562 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30563 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30564 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30565 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30566 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30567 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30568 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30569 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30570 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30571 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30572 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30573 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30574 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30575 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30576 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30577 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30578 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30579 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30580 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30581 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30582 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30583 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30584 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30585 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30586 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30587 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30588 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30589 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30590 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30591 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30592 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30593 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30594 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30595 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30596 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
30597 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
30598 N_("use -mcpu=strongarm110")},
30599 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
30600 N_("use -mcpu=strongarm1100")},
30601 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
30602 N_("use -mcpu=strongarm1110")},
30603 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
30604 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
30605 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
30607 /* Architecture variants -- don't add any more to this list either. */
30608 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30609 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30610 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30611 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30612 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30613 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30614 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30615 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30616 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30617 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30618 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30619 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30620 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30621 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30622 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30623 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30624 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30625 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30627 /* Floating point variants -- don't add any more to this list either. */
30628 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
30629 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
30630 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
30631 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
30632 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
30634 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
30637 struct arm_cpu_option_table
30641 const arm_feature_set value
;
30642 const arm_feature_set ext
;
30643 /* For some CPUs we assume an FPU unless the user explicitly sets
30645 const arm_feature_set default_fpu
;
30646 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30648 const char * canonical_name
;
30651 /* This list should, at a minimum, contain all the cpu names
30652 recognized by GCC. */
30653 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
30655 static const struct arm_cpu_option_table arm_cpus
[] =
30657 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
30660 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
30663 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
30666 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
30669 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
30672 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
30675 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
30678 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
30681 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
30684 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
30687 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
30690 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
30693 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
30696 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
30699 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
30702 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
30705 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
30708 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
30711 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
30714 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
30717 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
30720 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
30723 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
30726 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
30729 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30732 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30735 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30738 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30741 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30744 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30747 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30750 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30753 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30756 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30759 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30762 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30765 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30768 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30771 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30774 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30777 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30780 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30783 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30786 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30789 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30792 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30796 /* For V5 or later processors we default to using VFP; but the user
30797 should really set the FPU type explicitly. */
30798 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30801 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30804 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30807 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30810 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30813 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30816 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30819 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30822 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30825 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30828 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30831 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30834 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30837 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30840 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30843 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30846 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30849 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30852 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30855 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30858 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30861 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30864 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30867 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30870 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30873 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30876 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30879 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30882 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30885 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30888 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30891 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30894 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30897 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30900 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30903 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30906 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30907 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30909 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30911 FPU_ARCH_NEON_VFP_V4
),
30912 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30913 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30914 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30915 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30916 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30917 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30918 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30920 FPU_ARCH_NEON_VFP_V4
),
30921 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30923 FPU_ARCH_NEON_VFP_V4
),
30924 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30926 FPU_ARCH_NEON_VFP_V4
),
30927 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30928 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30929 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30930 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30931 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30932 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30933 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30934 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30935 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30936 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30937 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30938 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30939 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30940 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30941 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30942 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30943 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30944 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30945 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30946 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30947 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30948 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30949 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30950 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30951 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30952 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30953 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30954 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
30955 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30956 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30957 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
30958 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30959 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30960 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30961 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30962 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30963 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30966 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30968 FPU_ARCH_VFP_V3D16
),
30969 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30970 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30972 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30973 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30974 FPU_ARCH_VFP_V3D16
),
30975 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30976 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30977 FPU_ARCH_VFP_V3D16
),
30978 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30979 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30980 FPU_ARCH_NEON_VFP_ARMV8
),
30981 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
30982 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30984 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30985 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30987 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30990 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30993 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30996 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30999 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
31002 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
31005 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
31008 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
31009 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
31010 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31011 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
31012 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31013 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31014 /* ??? XSCALE is really an architecture. */
31015 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
31019 /* ??? iwmmxt is not a processor. */
31020 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
31023 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
31026 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
31031 ARM_CPU_OPT ("ep9312", "ARM920T",
31032 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
31033 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
31035 /* Marvell processors. */
31036 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
31037 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31038 FPU_ARCH_VFP_V3D16
),
31039 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
31040 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31041 FPU_ARCH_NEON_VFP_V4
),
31043 /* APM X-Gene family. */
31044 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
31046 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31047 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
31048 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
31049 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31051 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31055 struct arm_ext_table
31059 const arm_feature_set merge
;
31060 const arm_feature_set clear
;
31063 struct arm_arch_option_table
31067 const arm_feature_set value
;
31068 const arm_feature_set default_fpu
;
31069 const struct arm_ext_table
* ext_table
;
31072 /* Used to add support for +E and +noE extension. */
31073 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
31074 /* Used to add support for a +E extension. */
31075 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
31076 /* Used to add support for a +noE extension. */
31077 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
31079 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
31080 ~0 & ~FPU_ENDIAN_PURE)
31082 static const struct arm_ext_table armv5te_ext_table
[] =
31084 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
31085 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31088 static const struct arm_ext_table armv7_ext_table
[] =
31090 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31091 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31094 static const struct arm_ext_table armv7ve_ext_table
[] =
31096 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
31097 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
31098 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31099 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31100 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31101 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
31102 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31104 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
31105 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31107 /* Aliases for +simd. */
31108 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31110 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31111 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31112 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31114 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31117 static const struct arm_ext_table armv7a_ext_table
[] =
31119 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31120 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31121 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31122 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31123 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31124 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
31125 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31127 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
31128 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31130 /* Aliases for +simd. */
31131 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31132 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31134 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31135 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31137 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
31138 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
31139 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31142 static const struct arm_ext_table armv7r_ext_table
[] =
31144 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
31145 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
31146 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31147 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31148 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
31149 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31150 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31151 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
31152 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31155 static const struct arm_ext_table armv7em_ext_table
[] =
31157 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
31158 /* Alias for +fp, used to be known as fpv4-sp-d16. */
31159 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
31160 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
31161 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31162 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
31163 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31166 static const struct arm_ext_table armv8a_ext_table
[] =
31168 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
31169 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31170 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31171 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31173 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31174 should use the +simd option to turn on FP. */
31175 ARM_REMOVE ("fp", ALL_FP
),
31176 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31177 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31178 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31182 static const struct arm_ext_table armv81a_ext_table
[] =
31184 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31185 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31186 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31188 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31189 should use the +simd option to turn on FP. */
31190 ARM_REMOVE ("fp", ALL_FP
),
31191 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31192 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31193 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31196 static const struct arm_ext_table armv82a_ext_table
[] =
31198 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31199 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
31200 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
31201 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31202 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31203 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31204 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31205 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31207 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31208 should use the +simd option to turn on FP. */
31209 ARM_REMOVE ("fp", ALL_FP
),
31210 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31211 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31212 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31215 static const struct arm_ext_table armv84a_ext_table
[] =
31217 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31218 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31219 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31220 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31221 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31222 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31224 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31225 should use the +simd option to turn on FP. */
31226 ARM_REMOVE ("fp", ALL_FP
),
31227 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31228 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31229 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31232 static const struct arm_ext_table armv85a_ext_table
[] =
31234 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31235 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31236 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31237 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31238 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31239 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31241 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31242 should use the +simd option to turn on FP. */
31243 ARM_REMOVE ("fp", ALL_FP
),
31244 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31247 static const struct arm_ext_table armv86a_ext_table
[] =
31249 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31250 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31253 static const struct arm_ext_table armv8m_main_ext_table
[] =
31255 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31256 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
31257 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
31258 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31259 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31262 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
31264 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31265 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
31267 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31268 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
31271 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31272 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31273 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
31274 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
31276 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31277 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
31278 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31279 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31282 static const struct arm_ext_table armv8r_ext_table
[] =
31284 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
31285 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31286 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31287 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31288 ARM_REMOVE ("fp", ALL_FP
),
31289 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
31290 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31293 /* This list should, at a minimum, contain all the architecture names
31294 recognized by GCC. */
31295 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
31296 #define ARM_ARCH_OPT2(N, V, DF, ext) \
31297 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
31299 static const struct arm_arch_option_table arm_archs
[] =
31301 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
31302 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
31303 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
31304 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31305 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31306 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
31307 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
31308 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
31309 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
31310 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
31311 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
31312 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
31313 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
31314 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
31315 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
31316 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
31317 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
31318 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31319 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31320 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
31321 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
31322 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31323 kept to preserve existing behaviour. */
31324 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31325 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31326 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
31327 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
31328 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
31329 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31330 kept to preserve existing behaviour. */
31331 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31332 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31333 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
31334 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
31335 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
31336 /* The official spelling of the ARMv7 profile variants is the dashed form.
31337 Accept the non-dashed form for compatibility with old toolchains. */
31338 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31339 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
31340 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31341 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31342 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31343 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31344 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31345 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
31346 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
31347 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
31349 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
31351 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
31352 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
31353 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
31354 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
31355 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
31356 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
31357 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
31358 ARM_ARCH_OPT2 ("armv8.6-a", ARM_ARCH_V8_6A
, FPU_ARCH_VFP
, armv86a
),
31359 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
31360 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
31361 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
31362 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31364 #undef ARM_ARCH_OPT
31366 /* ISA extensions in the co-processor and main instruction set space. */
31368 struct arm_option_extension_value_table
31372 const arm_feature_set merge_value
;
31373 const arm_feature_set clear_value
;
31374 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31375 indicates that an extension is available for all architectures while
31376 ARM_ANY marks an empty entry. */
31377 const arm_feature_set allowed_archs
[2];
31380 /* The following table must be in alphabetical order with a NULL last entry. */
31382 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31383 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
31385 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
31386 use the context sensitive approach using arm_ext_table's. */
31387 static const struct arm_option_extension_value_table arm_extensions
[] =
31389 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
31390 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31391 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31392 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
31393 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31394 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
31395 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
31397 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31398 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31399 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
31400 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
31401 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31402 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31403 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31405 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31406 | ARM_EXT2_FP16_FML
),
31407 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31408 | ARM_EXT2_FP16_FML
),
31410 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31411 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31412 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31413 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31414 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
31415 Thumb divide instruction. Due to this having the same name as the
31416 previous entry, this will be ignored when doing command-line parsing and
31417 only considered by build attribute selection code. */
31418 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31419 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31420 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
31421 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
31422 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
31423 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
31424 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
31425 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
31426 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
31427 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31428 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31429 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31430 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31431 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31432 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31433 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
31434 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
31435 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
31436 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31437 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31438 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31440 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
31441 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
31442 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31443 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
31444 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
31445 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31446 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31447 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31449 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31450 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31451 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
31452 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31453 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
31454 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
31455 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31456 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
31458 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
31459 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31460 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
31461 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
31462 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
31466 /* ISA floating-point and Advanced SIMD extensions. */
31467 struct arm_option_fpu_value_table
31470 const arm_feature_set value
;
31473 /* This list should, at a minimum, contain all the fpu names
31474 recognized by GCC. */
31475 static const struct arm_option_fpu_value_table arm_fpus
[] =
31477 {"softfpa", FPU_NONE
},
31478 {"fpe", FPU_ARCH_FPE
},
31479 {"fpe2", FPU_ARCH_FPE
},
31480 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
31481 {"fpa", FPU_ARCH_FPA
},
31482 {"fpa10", FPU_ARCH_FPA
},
31483 {"fpa11", FPU_ARCH_FPA
},
31484 {"arm7500fe", FPU_ARCH_FPA
},
31485 {"softvfp", FPU_ARCH_VFP
},
31486 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
31487 {"vfp", FPU_ARCH_VFP_V2
},
31488 {"vfp9", FPU_ARCH_VFP_V2
},
31489 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
31490 {"vfp10", FPU_ARCH_VFP_V2
},
31491 {"vfp10-r0", FPU_ARCH_VFP_V1
},
31492 {"vfpxd", FPU_ARCH_VFP_V1xD
},
31493 {"vfpv2", FPU_ARCH_VFP_V2
},
31494 {"vfpv3", FPU_ARCH_VFP_V3
},
31495 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
31496 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
31497 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
31498 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
31499 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
31500 {"arm1020t", FPU_ARCH_VFP_V1
},
31501 {"arm1020e", FPU_ARCH_VFP_V2
},
31502 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
31503 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
31504 {"maverick", FPU_ARCH_MAVERICK
},
31505 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31506 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31507 {"neon-fp16", FPU_ARCH_NEON_FP16
},
31508 {"vfpv4", FPU_ARCH_VFP_V4
},
31509 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
31510 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
31511 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
31512 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
31513 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
31514 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
31515 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
31516 {"crypto-neon-fp-armv8",
31517 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
31518 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
31519 {"crypto-neon-fp-armv8.1",
31520 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
31521 {NULL
, ARM_ARCH_NONE
}
31524 struct arm_option_value_table
31530 static const struct arm_option_value_table arm_float_abis
[] =
31532 {"hard", ARM_FLOAT_ABI_HARD
},
31533 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
31534 {"soft", ARM_FLOAT_ABI_SOFT
},
31539 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
31540 static const struct arm_option_value_table arm_eabis
[] =
31542 {"gnu", EF_ARM_EABI_UNKNOWN
},
31543 {"4", EF_ARM_EABI_VER4
},
31544 {"5", EF_ARM_EABI_VER5
},
31549 struct arm_long_option_table
31551 const char * option
; /* Substring to match. */
31552 const char * help
; /* Help information. */
31553 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
31554 const char * deprecated
; /* If non-null, print this message. */
31558 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
31559 arm_feature_set
*ext_set
,
31560 const struct arm_ext_table
*ext_table
)
31562 /* We insist on extensions being specified in alphabetical order, and with
31563 extensions being added before being removed. We achieve this by having
31564 the global ARM_EXTENSIONS table in alphabetical order, and using the
31565 ADDING_VALUE variable to indicate whether we are adding an extension (1)
31566 or removing it (0) and only allowing it to change in the order
31568 const struct arm_option_extension_value_table
* opt
= NULL
;
31569 const arm_feature_set arm_any
= ARM_ANY
;
31570 int adding_value
= -1;
31572 while (str
!= NULL
&& *str
!= 0)
31579 as_bad (_("invalid architectural extension"));
31584 ext
= strchr (str
, '+');
31589 len
= strlen (str
);
31591 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
31593 if (adding_value
!= 0)
31596 opt
= arm_extensions
;
31604 if (adding_value
== -1)
31607 opt
= arm_extensions
;
31609 else if (adding_value
!= 1)
31611 as_bad (_("must specify extensions to add before specifying "
31612 "those to remove"));
31619 as_bad (_("missing architectural extension"));
31623 gas_assert (adding_value
!= -1);
31624 gas_assert (opt
!= NULL
);
31626 if (ext_table
!= NULL
)
31628 const struct arm_ext_table
* ext_opt
= ext_table
;
31629 bfd_boolean found
= FALSE
;
31630 for (; ext_opt
->name
!= NULL
; ext_opt
++)
31631 if (ext_opt
->name_len
== len
31632 && strncmp (ext_opt
->name
, str
, len
) == 0)
31636 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
31637 /* TODO: Option not supported. When we remove the
31638 legacy table this case should error out. */
31641 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
31645 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
31646 /* TODO: Option not supported. When we remove the
31647 legacy table this case should error out. */
31649 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
31661 /* Scan over the options table trying to find an exact match. */
31662 for (; opt
->name
!= NULL
; opt
++)
31663 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31665 int i
, nb_allowed_archs
=
31666 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31667 /* Check we can apply the extension to this architecture. */
31668 for (i
= 0; i
< nb_allowed_archs
; i
++)
31671 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
31673 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
31676 if (i
== nb_allowed_archs
)
31678 as_bad (_("extension does not apply to the base architecture"));
31682 /* Add or remove the extension. */
31684 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
31686 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
31688 /* Allowing Thumb division instructions for ARMv7 in autodetection
31689 rely on this break so that duplicate extensions (extensions
31690 with the same name as a previous extension in the list) are not
31691 considered for command-line parsing. */
31695 if (opt
->name
== NULL
)
31697 /* Did we fail to find an extension because it wasn't specified in
31698 alphabetical order, or because it does not exist? */
31700 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31701 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31704 if (opt
->name
== NULL
)
31705 as_bad (_("unknown architectural extension `%s'"), str
);
31707 as_bad (_("architectural extensions must be specified in "
31708 "alphabetical order"));
31714 /* We should skip the extension we've just matched the next time
31726 arm_parse_fp16_opt (const char *str
)
31728 if (strcasecmp (str
, "ieee") == 0)
31729 fp16_format
= ARM_FP16_FORMAT_IEEE
;
31730 else if (strcasecmp (str
, "alternative") == 0)
31731 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
31734 as_bad (_("unrecognised float16 format \"%s\""), str
);
31742 arm_parse_cpu (const char *str
)
31744 const struct arm_cpu_option_table
*opt
;
31745 const char *ext
= strchr (str
, '+');
31751 len
= strlen (str
);
31755 as_bad (_("missing cpu name `%s'"), str
);
31759 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
31760 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31762 mcpu_cpu_opt
= &opt
->value
;
31763 if (mcpu_ext_opt
== NULL
)
31764 mcpu_ext_opt
= XNEW (arm_feature_set
);
31765 *mcpu_ext_opt
= opt
->ext
;
31766 mcpu_fpu_opt
= &opt
->default_fpu
;
31767 if (opt
->canonical_name
)
31769 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31770 strcpy (selected_cpu_name
, opt
->canonical_name
);
31776 if (len
>= sizeof selected_cpu_name
)
31777 len
= (sizeof selected_cpu_name
) - 1;
31779 for (i
= 0; i
< len
; i
++)
31780 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31781 selected_cpu_name
[i
] = 0;
31785 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31790 as_bad (_("unknown cpu `%s'"), str
);
31795 arm_parse_arch (const char *str
)
31797 const struct arm_arch_option_table
*opt
;
31798 const char *ext
= strchr (str
, '+');
31804 len
= strlen (str
);
31808 as_bad (_("missing architecture name `%s'"), str
);
31812 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31813 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31815 march_cpu_opt
= &opt
->value
;
31816 if (march_ext_opt
== NULL
)
31817 march_ext_opt
= XNEW (arm_feature_set
);
31818 *march_ext_opt
= arm_arch_none
;
31819 march_fpu_opt
= &opt
->default_fpu
;
31820 selected_ctx_ext_table
= opt
->ext_table
;
31821 strcpy (selected_cpu_name
, opt
->name
);
31824 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31830 as_bad (_("unknown architecture `%s'\n"), str
);
31835 arm_parse_fpu (const char * str
)
31837 const struct arm_option_fpu_value_table
* opt
;
31839 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31840 if (streq (opt
->name
, str
))
31842 mfpu_opt
= &opt
->value
;
31846 as_bad (_("unknown floating point format `%s'\n"), str
);
31851 arm_parse_float_abi (const char * str
)
31853 const struct arm_option_value_table
* opt
;
31855 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31856 if (streq (opt
->name
, str
))
31858 mfloat_abi_opt
= opt
->value
;
31862 as_bad (_("unknown floating point abi `%s'\n"), str
);
31868 arm_parse_eabi (const char * str
)
31870 const struct arm_option_value_table
*opt
;
31872 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31873 if (streq (opt
->name
, str
))
31875 meabi_flags
= opt
->value
;
31878 as_bad (_("unknown EABI `%s'\n"), str
);
31884 arm_parse_it_mode (const char * str
)
31886 bfd_boolean ret
= TRUE
;
31888 if (streq ("arm", str
))
31889 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31890 else if (streq ("thumb", str
))
31891 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31892 else if (streq ("always", str
))
31893 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31894 else if (streq ("never", str
))
31895 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31898 as_bad (_("unknown implicit IT mode `%s', should be "\
31899 "arm, thumb, always, or never."), str
);
31907 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31909 codecomposer_syntax
= TRUE
;
31910 arm_comment_chars
[0] = ';';
31911 arm_line_separator_chars
[0] = 0;
31915 struct arm_long_option_table arm_long_opts
[] =
31917 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31918 arm_parse_cpu
, NULL
},
31919 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31920 arm_parse_arch
, NULL
},
31921 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31922 arm_parse_fpu
, NULL
},
31923 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31924 arm_parse_float_abi
, NULL
},
31926 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31927 arm_parse_eabi
, NULL
},
31929 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31930 arm_parse_it_mode
, NULL
},
31931 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31932 arm_ccs_mode
, NULL
},
31934 N_("[ieee|alternative]\n\
31935 set the encoding for half precision floating point "
31936 "numbers to IEEE\n\
31937 or Arm alternative format."),
31938 arm_parse_fp16_opt
, NULL
},
31939 {NULL
, NULL
, 0, NULL
}
31943 md_parse_option (int c
, const char * arg
)
31945 struct arm_option_table
*opt
;
31946 const struct arm_legacy_option_table
*fopt
;
31947 struct arm_long_option_table
*lopt
;
31953 target_big_endian
= 1;
31959 target_big_endian
= 0;
31963 case OPTION_FIX_V4BX
:
31971 #endif /* OBJ_ELF */
31974 /* Listing option. Just ignore these, we don't support additional
31979 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31981 if (c
== opt
->option
[0]
31982 && ((arg
== NULL
&& opt
->option
[1] == 0)
31983 || streq (arg
, opt
->option
+ 1)))
31985 /* If the option is deprecated, tell the user. */
31986 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31987 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31988 arg
? arg
: "", _(opt
->deprecated
));
31990 if (opt
->var
!= NULL
)
31991 *opt
->var
= opt
->value
;
31997 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31999 if (c
== fopt
->option
[0]
32000 && ((arg
== NULL
&& fopt
->option
[1] == 0)
32001 || streq (arg
, fopt
->option
+ 1)))
32003 /* If the option is deprecated, tell the user. */
32004 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
32005 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32006 arg
? arg
: "", _(fopt
->deprecated
));
32008 if (fopt
->var
!= NULL
)
32009 *fopt
->var
= &fopt
->value
;
32015 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32017 /* These options are expected to have an argument. */
32018 if (c
== lopt
->option
[0]
32020 && strncmp (arg
, lopt
->option
+ 1,
32021 strlen (lopt
->option
+ 1)) == 0)
32023 /* If the option is deprecated, tell the user. */
32024 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
32025 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
32026 _(lopt
->deprecated
));
32028 /* Call the sup-option parser. */
32029 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
32040 md_show_usage (FILE * fp
)
32042 struct arm_option_table
*opt
;
32043 struct arm_long_option_table
*lopt
;
32045 fprintf (fp
, _(" ARM-specific assembler options:\n"));
32047 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32048 if (opt
->help
!= NULL
)
32049 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
32051 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32052 if (lopt
->help
!= NULL
)
32053 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
32057 -EB assemble code for a big-endian cpu\n"));
32062 -EL assemble code for a little-endian cpu\n"));
32066 --fix-v4bx Allow BX in ARMv4 code\n"));
32070 --fdpic generate an FDPIC object file\n"));
32071 #endif /* OBJ_ELF */
32079 arm_feature_set flags
;
32080 } cpu_arch_ver_table
;
32082 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
32083 chronologically for architectures, with an exception for ARMv6-M and
32084 ARMv6S-M due to legacy reasons. No new architecture should have a
32085 special case. This allows for build attribute selection results to be
32086 stable when new architectures are added. */
32087 static const cpu_arch_ver_table cpu_arch_ver
[] =
32089 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
32090 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
32091 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
32092 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
32093 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
32094 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
32095 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
32096 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
32097 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
32098 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
32099 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
32100 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
32101 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
32102 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
32103 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
32104 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
32105 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
32106 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
32107 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
32108 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
32109 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
32110 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
32111 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
32112 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
32114 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
32115 always selected build attributes to match those of ARMv6-M
32116 (resp. ARMv6S-M). However, due to these architectures being a strict
32117 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
32118 would be selected when fully respecting chronology of architectures.
32119 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
32120 move them before ARMv7 architectures. */
32121 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
32122 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
32124 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
32125 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
32126 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
32127 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
32128 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
32129 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
32130 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
32131 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
32132 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
32133 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
32134 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
32135 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
32136 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
32137 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
32138 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
32139 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
32140 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_6A
},
32141 {-1, ARM_ARCH_NONE
}
32144 /* Set an attribute if it has not already been set by the user. */
32147 aeabi_set_attribute_int (int tag
, int value
)
32150 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32151 || !attributes_set_explicitly
[tag
])
32152 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
32156 aeabi_set_attribute_string (int tag
, const char *value
)
32159 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32160 || !attributes_set_explicitly
[tag
])
32161 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
32164 /* Return whether features in the *NEEDED feature set are available via
32165 extensions for the architecture whose feature set is *ARCH_FSET. */
32168 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
32169 const arm_feature_set
*needed
)
32171 int i
, nb_allowed_archs
;
32172 arm_feature_set ext_fset
;
32173 const struct arm_option_extension_value_table
*opt
;
32175 ext_fset
= arm_arch_none
;
32176 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32178 /* Extension does not provide any feature we need. */
32179 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
32183 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32184 for (i
= 0; i
< nb_allowed_archs
; i
++)
32187 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
32190 /* Extension is available, add it. */
32191 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
32192 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
32196 /* Can we enable all features in *needed? */
32197 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
32200 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32201 a given architecture feature set *ARCH_EXT_FSET including extension feature
32202 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
32203 - if true, check for an exact match of the architecture modulo extensions;
32204 - otherwise, select build attribute value of the first superset
32205 architecture released so that results remains stable when new architectures
32207 For -march/-mcpu=all the build attribute value of the most featureful
32208 architecture is returned. Tag_CPU_arch_profile result is returned in
32212 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
32213 const arm_feature_set
*ext_fset
,
32214 char *profile
, int exact_match
)
32216 arm_feature_set arch_fset
;
32217 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
32219 /* Select most featureful architecture with all its extensions if building
32220 for -march=all as the feature sets used to set build attributes. */
32221 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
32223 /* Force revisiting of decision for each new architecture. */
32224 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32226 return TAG_CPU_ARCH_V8
;
32229 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
32231 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
32233 arm_feature_set known_arch_fset
;
32235 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
32238 /* Base architecture match user-specified architecture and
32239 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
32240 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
32245 /* Base architecture match user-specified architecture only
32246 (eg. ARMv6-M in the same case as above). Record it in case we
32247 find a match with above condition. */
32248 else if (p_ver_ret
== NULL
32249 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
32255 /* Architecture has all features wanted. */
32256 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
32258 arm_feature_set added_fset
;
32260 /* Compute features added by this architecture over the one
32261 recorded in p_ver_ret. */
32262 if (p_ver_ret
!= NULL
)
32263 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
32265 /* First architecture that match incl. with extensions, or the
32266 only difference in features over the recorded match is
32267 features that were optional and are now mandatory. */
32268 if (p_ver_ret
== NULL
32269 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
32275 else if (p_ver_ret
== NULL
)
32277 arm_feature_set needed_ext_fset
;
32279 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
32281 /* Architecture has all features needed when using some
32282 extensions. Record it and continue searching in case there
32283 exist an architecture providing all needed features without
32284 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
32286 if (have_ext_for_needed_feat_p (&known_arch_fset
,
32293 if (p_ver_ret
== NULL
)
32297 /* Tag_CPU_arch_profile. */
32298 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
32299 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
32300 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
32301 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
32303 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
32305 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
32309 return p_ver_ret
->val
;
32312 /* Set the public EABI object attributes. */
32315 aeabi_set_public_attributes (void)
32317 char profile
= '\0';
32320 int fp16_optional
= 0;
32321 int skip_exact_match
= 0;
32322 arm_feature_set flags
, flags_arch
, flags_ext
;
32324 /* Autodetection mode, choose the architecture based the instructions
32326 if (no_cpu_selected ())
32328 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
32330 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
32331 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
32333 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
32334 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
32336 /* Code run during relaxation relies on selected_cpu being set. */
32337 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32338 flags_ext
= arm_arch_none
;
32339 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
32340 selected_ext
= flags_ext
;
32341 selected_cpu
= flags
;
32343 /* Otherwise, choose the architecture based on the capabilities of the
32347 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
32348 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
32349 flags_ext
= selected_ext
;
32350 flags
= selected_cpu
;
32352 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
32354 /* Allow the user to override the reported architecture. */
32355 if (!ARM_FEATURE_ZERO (selected_object_arch
))
32357 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
32358 flags_ext
= arm_arch_none
;
32361 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
32363 /* When this function is run again after relaxation has happened there is no
32364 way to determine whether an architecture or CPU was specified by the user:
32365 - selected_cpu is set above for relaxation to work;
32366 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32367 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32368 Therefore, if not in -march=all case we first try an exact match and fall
32369 back to autodetection. */
32370 if (!skip_exact_match
)
32371 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
32373 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
32375 as_bad (_("no architecture contains all the instructions used\n"));
32377 /* Tag_CPU_name. */
32378 if (selected_cpu_name
[0])
32382 q
= selected_cpu_name
;
32383 if (strncmp (q
, "armv", 4) == 0)
32388 for (i
= 0; q
[i
]; i
++)
32389 q
[i
] = TOUPPER (q
[i
]);
32391 aeabi_set_attribute_string (Tag_CPU_name
, q
);
32394 /* Tag_CPU_arch. */
32395 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
32397 /* Tag_CPU_arch_profile. */
32398 if (profile
!= '\0')
32399 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
32401 /* Tag_DSP_extension. */
32402 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
32403 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
32405 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32406 /* Tag_ARM_ISA_use. */
32407 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
32408 || ARM_FEATURE_ZERO (flags_arch
))
32409 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
32411 /* Tag_THUMB_ISA_use. */
32412 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
32413 || ARM_FEATURE_ZERO (flags_arch
))
32417 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32418 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
32420 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
32424 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
32427 /* Tag_VFP_arch. */
32428 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
32429 aeabi_set_attribute_int (Tag_VFP_arch
,
32430 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32432 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
32433 aeabi_set_attribute_int (Tag_VFP_arch
,
32434 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32436 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
32439 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
32441 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
32443 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
32446 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
32447 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
32448 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
32449 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
32450 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
32452 /* Tag_ABI_HardFP_use. */
32453 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
32454 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
32455 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
32457 /* Tag_WMMX_arch. */
32458 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
32459 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
32460 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
32461 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
32463 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
32464 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
32465 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
32466 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
32467 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
32468 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
32470 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
32472 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
32476 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
32481 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
32482 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
32483 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
32484 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
32486 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
32487 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
32488 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
32492 We set Tag_DIV_use to two when integer divide instructions have been used
32493 in ARM state, or when Thumb integer divide instructions have been used,
32494 but we have no architecture profile set, nor have we any ARM instructions.
32496 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
32497 by the base architecture.
32499 For new architectures we will have to check these tests. */
32500 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32501 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32502 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
32503 aeabi_set_attribute_int (Tag_DIV_use
, 0);
32504 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
32505 || (profile
== '\0'
32506 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
32507 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
32508 aeabi_set_attribute_int (Tag_DIV_use
, 2);
32510 /* Tag_MP_extension_use. */
32511 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
32512 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
32514 /* Tag Virtualization_use. */
32515 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
32517 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
32520 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
32522 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
32523 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
32526 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
32527 finished and free extension feature bits which will not be used anymore. */
32530 arm_md_post_relax (void)
32532 aeabi_set_public_attributes ();
32533 XDELETE (mcpu_ext_opt
);
32534 mcpu_ext_opt
= NULL
;
32535 XDELETE (march_ext_opt
);
32536 march_ext_opt
= NULL
;
32539 /* Add the default contents for the .ARM.attributes section. */
32544 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
32547 aeabi_set_public_attributes ();
32549 #endif /* OBJ_ELF */
32551 /* Parse a .cpu directive. */
32554 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
32556 const struct arm_cpu_option_table
*opt
;
32560 name
= input_line_pointer
;
32561 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32562 input_line_pointer
++;
32563 saved_char
= *input_line_pointer
;
32564 *input_line_pointer
= 0;
32566 /* Skip the first "all" entry. */
32567 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
32568 if (streq (opt
->name
, name
))
32570 selected_arch
= opt
->value
;
32571 selected_ext
= opt
->ext
;
32572 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32573 if (opt
->canonical_name
)
32574 strcpy (selected_cpu_name
, opt
->canonical_name
);
32578 for (i
= 0; opt
->name
[i
]; i
++)
32579 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32581 selected_cpu_name
[i
] = 0;
32583 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32585 *input_line_pointer
= saved_char
;
32586 demand_empty_rest_of_line ();
32589 as_bad (_("unknown cpu `%s'"), name
);
32590 *input_line_pointer
= saved_char
;
32591 ignore_rest_of_line ();
32594 /* Parse a .arch directive. */
32597 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
32599 const struct arm_arch_option_table
*opt
;
32603 name
= input_line_pointer
;
32604 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32605 input_line_pointer
++;
32606 saved_char
= *input_line_pointer
;
32607 *input_line_pointer
= 0;
32609 /* Skip the first "all" entry. */
32610 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32611 if (streq (opt
->name
, name
))
32613 selected_arch
= opt
->value
;
32614 selected_ext
= arm_arch_none
;
32615 selected_cpu
= selected_arch
;
32616 strcpy (selected_cpu_name
, opt
->name
);
32617 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32618 *input_line_pointer
= saved_char
;
32619 demand_empty_rest_of_line ();
32623 as_bad (_("unknown architecture `%s'\n"), name
);
32624 *input_line_pointer
= saved_char
;
32625 ignore_rest_of_line ();
32628 /* Parse a .object_arch directive. */
32631 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
32633 const struct arm_arch_option_table
*opt
;
32637 name
= input_line_pointer
;
32638 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32639 input_line_pointer
++;
32640 saved_char
= *input_line_pointer
;
32641 *input_line_pointer
= 0;
32643 /* Skip the first "all" entry. */
32644 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32645 if (streq (opt
->name
, name
))
32647 selected_object_arch
= opt
->value
;
32648 *input_line_pointer
= saved_char
;
32649 demand_empty_rest_of_line ();
32653 as_bad (_("unknown architecture `%s'\n"), name
);
32654 *input_line_pointer
= saved_char
;
32655 ignore_rest_of_line ();
32658 /* Parse a .arch_extension directive. */
32661 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
32663 const struct arm_option_extension_value_table
*opt
;
32666 int adding_value
= 1;
32668 name
= input_line_pointer
;
32669 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32670 input_line_pointer
++;
32671 saved_char
= *input_line_pointer
;
32672 *input_line_pointer
= 0;
32674 if (strlen (name
) >= 2
32675 && strncmp (name
, "no", 2) == 0)
32681 /* Check the context specific extension table */
32682 if (selected_ctx_ext_table
)
32684 const struct arm_ext_table
* ext_opt
;
32685 for (ext_opt
= selected_ctx_ext_table
; ext_opt
->name
!= NULL
; ext_opt
++)
32687 if (streq (ext_opt
->name
, name
))
32691 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
32692 /* TODO: Option not supported. When we remove the
32693 legacy table this case should error out. */
32695 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32699 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, ext_opt
->clear
);
32701 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32702 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32703 *input_line_pointer
= saved_char
;
32704 demand_empty_rest_of_line ();
32710 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32711 if (streq (opt
->name
, name
))
32713 int i
, nb_allowed_archs
=
32714 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
32715 for (i
= 0; i
< nb_allowed_archs
; i
++)
32718 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
32720 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
32724 if (i
== nb_allowed_archs
)
32726 as_bad (_("architectural extension `%s' is not allowed for the "
32727 "current base architecture"), name
);
32732 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32735 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
32737 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32738 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32739 *input_line_pointer
= saved_char
;
32740 demand_empty_rest_of_line ();
32741 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32742 on this return so that duplicate extensions (extensions with the
32743 same name as a previous extension in the list) are not considered
32744 for command-line parsing. */
32748 if (opt
->name
== NULL
)
32749 as_bad (_("unknown architecture extension `%s'\n"), name
);
32751 *input_line_pointer
= saved_char
;
32752 ignore_rest_of_line ();
32755 /* Parse a .fpu directive. */
32758 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
32760 const struct arm_option_fpu_value_table
*opt
;
32764 name
= input_line_pointer
;
32765 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32766 input_line_pointer
++;
32767 saved_char
= *input_line_pointer
;
32768 *input_line_pointer
= 0;
32770 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32771 if (streq (opt
->name
, name
))
32773 selected_fpu
= opt
->value
;
32774 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, fpu_any
);
32775 #ifndef CPU_DEFAULT
32776 if (no_cpu_selected ())
32777 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
32780 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32781 *input_line_pointer
= saved_char
;
32782 demand_empty_rest_of_line ();
32786 as_bad (_("unknown floating point format `%s'\n"), name
);
32787 *input_line_pointer
= saved_char
;
32788 ignore_rest_of_line ();
32791 /* Copy symbol information. */
32794 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
32796 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
32800 /* Given a symbolic attribute NAME, return the proper integer value.
32801 Returns -1 if the attribute is not known. */
32804 arm_convert_symbolic_attribute (const char *name
)
32806 static const struct
32811 attribute_table
[] =
32813 /* When you modify this table you should
32814 also modify the list in doc/c-arm.texi. */
32815 #define T(tag) {#tag, tag}
32816 T (Tag_CPU_raw_name
),
32819 T (Tag_CPU_arch_profile
),
32820 T (Tag_ARM_ISA_use
),
32821 T (Tag_THUMB_ISA_use
),
32825 T (Tag_Advanced_SIMD_arch
),
32826 T (Tag_PCS_config
),
32827 T (Tag_ABI_PCS_R9_use
),
32828 T (Tag_ABI_PCS_RW_data
),
32829 T (Tag_ABI_PCS_RO_data
),
32830 T (Tag_ABI_PCS_GOT_use
),
32831 T (Tag_ABI_PCS_wchar_t
),
32832 T (Tag_ABI_FP_rounding
),
32833 T (Tag_ABI_FP_denormal
),
32834 T (Tag_ABI_FP_exceptions
),
32835 T (Tag_ABI_FP_user_exceptions
),
32836 T (Tag_ABI_FP_number_model
),
32837 T (Tag_ABI_align_needed
),
32838 T (Tag_ABI_align8_needed
),
32839 T (Tag_ABI_align_preserved
),
32840 T (Tag_ABI_align8_preserved
),
32841 T (Tag_ABI_enum_size
),
32842 T (Tag_ABI_HardFP_use
),
32843 T (Tag_ABI_VFP_args
),
32844 T (Tag_ABI_WMMX_args
),
32845 T (Tag_ABI_optimization_goals
),
32846 T (Tag_ABI_FP_optimization_goals
),
32847 T (Tag_compatibility
),
32848 T (Tag_CPU_unaligned_access
),
32849 T (Tag_FP_HP_extension
),
32850 T (Tag_VFP_HP_extension
),
32851 T (Tag_ABI_FP_16bit_format
),
32852 T (Tag_MPextension_use
),
32854 T (Tag_nodefaults
),
32855 T (Tag_also_compatible_with
),
32856 T (Tag_conformance
),
32858 T (Tag_Virtualization_use
),
32859 T (Tag_DSP_extension
),
32861 /* We deliberately do not include Tag_MPextension_use_legacy. */
32869 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32870 if (streq (name
, attribute_table
[i
].name
))
32871 return attribute_table
[i
].tag
;
32876 /* Apply sym value for relocations only in the case that they are for
32877 local symbols in the same segment as the fixup and you have the
32878 respective architectural feature for blx and simple switches. */
32881 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32884 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32885 /* PR 17444: If the local symbol is in a different section then a reloc
32886 will always be generated for it, so applying the symbol value now
32887 will result in a double offset being stored in the relocation. */
32888 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32889 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32891 switch (fixP
->fx_r_type
)
32893 case BFD_RELOC_ARM_PCREL_BLX
:
32894 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32895 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32899 case BFD_RELOC_ARM_PCREL_CALL
:
32900 case BFD_RELOC_THUMB_PCREL_BLX
:
32901 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32912 #endif /* OBJ_ELF */