1 /* tc-avr.c -- Assembler code for the ATMEL AVR
3 Copyright (C) 1999-2017 Free Software Foundation, Inc.
4 Contributed by Denis Chertykov <denisc@overta.ru>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
24 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "elf32-avr.h"
31 /* For building a linked list of AVR_PROPERTY_RECORD structures. */
32 struct avr_property_record_link
34 struct avr_property_record record
;
35 struct avr_property_record_link
*next
;
41 const char * constraints
;
43 int insn_size
; /* In words. */
45 unsigned int bin_opcode
;
48 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
49 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
51 struct avr_opcodes_s avr_opcodes
[] =
53 #include "opcode/avr.h"
54 {NULL
, NULL
, NULL
, 0, 0, 0}
57 const char comment_chars
[] = ";";
58 const char line_comment_chars
[] = "#";
59 const char line_separator_chars
[] = "$";
61 const char *md_shortopts
= "m:";
69 /* XXX - devices that don't seem to exist (renamed, replaced with larger
70 ones, or planned but never produced), left here for compatibility. */
72 static struct mcu_type_s mcu_types
[] =
74 {"avr1", AVR_ISA_AVR1
, bfd_mach_avr1
},
75 /* TODO: instruction set for avr2 architecture should be AVR_ISA_AVR2,
76 but set to AVR_ISA_AVR25 for some following version
77 of GCC (from 4.3) for backward compatibility. */
78 {"avr2", AVR_ISA_AVR25
, bfd_mach_avr2
},
79 {"avr25", AVR_ISA_AVR25
, bfd_mach_avr25
},
80 /* TODO: instruction set for avr3 architecture should be AVR_ISA_AVR3,
81 but set to AVR_ISA_AVR3_ALL for some following version
82 of GCC (from 4.3) for backward compatibility. */
83 {"avr3", AVR_ISA_AVR3_ALL
, bfd_mach_avr3
},
84 {"avr31", AVR_ISA_AVR31
, bfd_mach_avr31
},
85 {"avr35", AVR_ISA_AVR35
, bfd_mach_avr35
},
86 {"avr4", AVR_ISA_AVR4
, bfd_mach_avr4
},
87 /* TODO: instruction set for avr5 architecture should be AVR_ISA_AVR5,
88 but set to AVR_ISA_AVR51 for some following version
89 of GCC (from 4.3) for backward compatibility. */
90 {"avr5", AVR_ISA_AVR51
, bfd_mach_avr5
},
91 {"avr51", AVR_ISA_AVR51
, bfd_mach_avr51
},
92 {"avr6", AVR_ISA_AVR6
, bfd_mach_avr6
},
93 {"avrxmega1", AVR_ISA_XMEGA
, bfd_mach_avrxmega1
},
94 {"avrxmega2", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
95 {"avrxmega3", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
96 {"avrxmega4", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
97 {"avrxmega5", AVR_ISA_XMEGA
, bfd_mach_avrxmega5
},
98 {"avrxmega6", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
99 {"avrxmega7", AVR_ISA_XMEGA
, bfd_mach_avrxmega7
},
100 {"avrtiny", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
101 {"at90s1200", AVR_ISA_1200
, bfd_mach_avr1
},
102 {"attiny11", AVR_ISA_AVR1
, bfd_mach_avr1
},
103 {"attiny12", AVR_ISA_AVR1
, bfd_mach_avr1
},
104 {"attiny15", AVR_ISA_AVR1
, bfd_mach_avr1
},
105 {"attiny28", AVR_ISA_AVR1
, bfd_mach_avr1
},
106 {"at90s2313", AVR_ISA_AVR2
, bfd_mach_avr2
},
107 {"at90s2323", AVR_ISA_AVR2
, bfd_mach_avr2
},
108 {"at90s2333", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 4433 */
109 {"at90s2343", AVR_ISA_AVR2
, bfd_mach_avr2
},
110 {"attiny22", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 2343 */
111 {"attiny26", AVR_ISA_2xxe
, bfd_mach_avr2
},
112 {"at90s4414", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 8515 */
113 {"at90s4433", AVR_ISA_AVR2
, bfd_mach_avr2
},
114 {"at90s4434", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 8535 */
115 {"at90s8515", AVR_ISA_AVR2
, bfd_mach_avr2
},
116 {"at90c8534", AVR_ISA_AVR2
, bfd_mach_avr2
},
117 {"at90s8535", AVR_ISA_AVR2
, bfd_mach_avr2
},
118 {"ata5272", AVR_ISA_AVR25
, bfd_mach_avr25
},
119 {"attiny13", AVR_ISA_AVR25
, bfd_mach_avr25
},
120 {"attiny13a", AVR_ISA_AVR25
, bfd_mach_avr25
},
121 {"attiny2313", AVR_ISA_AVR25
, bfd_mach_avr25
},
122 {"attiny2313a",AVR_ISA_AVR25
, bfd_mach_avr25
},
123 {"attiny24", AVR_ISA_AVR25
, bfd_mach_avr25
},
124 {"attiny24a", AVR_ISA_AVR25
, bfd_mach_avr25
},
125 {"attiny4313", AVR_ISA_AVR25
, bfd_mach_avr25
},
126 {"attiny44", AVR_ISA_AVR25
, bfd_mach_avr25
},
127 {"attiny44a", AVR_ISA_AVR25
, bfd_mach_avr25
},
128 {"attiny84", AVR_ISA_AVR25
, bfd_mach_avr25
},
129 {"attiny84a", AVR_ISA_AVR25
, bfd_mach_avr25
},
130 {"attiny25", AVR_ISA_AVR25
, bfd_mach_avr25
},
131 {"attiny45", AVR_ISA_AVR25
, bfd_mach_avr25
},
132 {"attiny85", AVR_ISA_AVR25
, bfd_mach_avr25
},
133 {"attiny261", AVR_ISA_AVR25
, bfd_mach_avr25
},
134 {"attiny261a", AVR_ISA_AVR25
, bfd_mach_avr25
},
135 {"attiny461", AVR_ISA_AVR25
, bfd_mach_avr25
},
136 {"attiny461a", AVR_ISA_AVR25
, bfd_mach_avr25
},
137 {"attiny861", AVR_ISA_AVR25
, bfd_mach_avr25
},
138 {"attiny861a", AVR_ISA_AVR25
, bfd_mach_avr25
},
139 {"attiny87", AVR_ISA_AVR25
, bfd_mach_avr25
},
140 {"attiny43u", AVR_ISA_AVR25
, bfd_mach_avr25
},
141 {"attiny48", AVR_ISA_AVR25
, bfd_mach_avr25
},
142 {"attiny88", AVR_ISA_AVR25
, bfd_mach_avr25
},
143 {"attiny828", AVR_ISA_AVR25
, bfd_mach_avr25
},
144 {"at86rf401", AVR_ISA_RF401
, bfd_mach_avr25
},
145 {"at43usb355", AVR_ISA_AVR3
, bfd_mach_avr3
},
146 {"at76c711", AVR_ISA_AVR3
, bfd_mach_avr3
},
147 {"atmega103", AVR_ISA_AVR31
, bfd_mach_avr31
},
148 {"at43usb320", AVR_ISA_AVR31
, bfd_mach_avr31
},
149 {"attiny167", AVR_ISA_AVR35
, bfd_mach_avr35
},
150 {"at90usb82", AVR_ISA_AVR35
, bfd_mach_avr35
},
151 {"at90usb162", AVR_ISA_AVR35
, bfd_mach_avr35
},
152 {"ata5505", AVR_ISA_AVR35
, bfd_mach_avr35
},
153 {"atmega8u2", AVR_ISA_AVR35
, bfd_mach_avr35
},
154 {"atmega16u2", AVR_ISA_AVR35
, bfd_mach_avr35
},
155 {"atmega32u2", AVR_ISA_AVR35
, bfd_mach_avr35
},
156 {"attiny1634", AVR_ISA_AVR35
, bfd_mach_avr35
},
157 {"atmega8", AVR_ISA_M8
, bfd_mach_avr4
},
158 {"ata6289", AVR_ISA_AVR4
, bfd_mach_avr4
},
159 {"atmega8a", AVR_ISA_M8
, bfd_mach_avr4
},
160 {"ata6285", AVR_ISA_AVR4
, bfd_mach_avr4
},
161 {"ata6286", AVR_ISA_AVR4
, bfd_mach_avr4
},
162 {"atmega48", AVR_ISA_AVR4
, bfd_mach_avr4
},
163 {"atmega48a", AVR_ISA_AVR4
, bfd_mach_avr4
},
164 {"atmega48pa", AVR_ISA_AVR4
, bfd_mach_avr4
},
165 {"atmega48p", AVR_ISA_AVR4
, bfd_mach_avr4
},
166 {"atmega88", AVR_ISA_AVR4
, bfd_mach_avr4
},
167 {"atmega88a", AVR_ISA_AVR4
, bfd_mach_avr4
},
168 {"atmega88p", AVR_ISA_AVR4
, bfd_mach_avr4
},
169 {"atmega88pa", AVR_ISA_AVR4
, bfd_mach_avr4
},
170 {"atmega8515", AVR_ISA_M8
, bfd_mach_avr4
},
171 {"atmega8535", AVR_ISA_M8
, bfd_mach_avr4
},
172 {"atmega8hva", AVR_ISA_AVR4
, bfd_mach_avr4
},
173 {"at90pwm1", AVR_ISA_AVR4
, bfd_mach_avr4
},
174 {"at90pwm2", AVR_ISA_AVR4
, bfd_mach_avr4
},
175 {"at90pwm2b", AVR_ISA_AVR4
, bfd_mach_avr4
},
176 {"at90pwm3", AVR_ISA_AVR4
, bfd_mach_avr4
},
177 {"at90pwm3b", AVR_ISA_AVR4
, bfd_mach_avr4
},
178 {"at90pwm81", AVR_ISA_AVR4
, bfd_mach_avr4
},
179 {"at90pwm161", AVR_ISA_AVR5
, bfd_mach_avr5
},
180 {"ata5790", AVR_ISA_AVR5
, bfd_mach_avr5
},
181 {"ata5795", AVR_ISA_AVR5
, bfd_mach_avr5
},
182 {"atmega16", AVR_ISA_AVR5
, bfd_mach_avr5
},
183 {"atmega16a", AVR_ISA_AVR5
, bfd_mach_avr5
},
184 {"atmega161", AVR_ISA_M161
, bfd_mach_avr5
},
185 {"atmega162", AVR_ISA_AVR5
, bfd_mach_avr5
},
186 {"atmega163", AVR_ISA_M161
, bfd_mach_avr5
},
187 {"atmega164a", AVR_ISA_AVR5
, bfd_mach_avr5
},
188 {"atmega164p", AVR_ISA_AVR5
, bfd_mach_avr5
},
189 {"atmega164pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
190 {"atmega165", AVR_ISA_AVR5
, bfd_mach_avr5
},
191 {"atmega165a", AVR_ISA_AVR5
, bfd_mach_avr5
},
192 {"atmega165p", AVR_ISA_AVR5
, bfd_mach_avr5
},
193 {"atmega165pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
194 {"atmega168", AVR_ISA_AVR5
, bfd_mach_avr5
},
195 {"atmega168a", AVR_ISA_AVR5
, bfd_mach_avr5
},
196 {"atmega168p", AVR_ISA_AVR5
, bfd_mach_avr5
},
197 {"atmega168pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
198 {"atmega169", AVR_ISA_AVR5
, bfd_mach_avr5
},
199 {"atmega169a", AVR_ISA_AVR5
, bfd_mach_avr5
},
200 {"atmega169p", AVR_ISA_AVR5
, bfd_mach_avr5
},
201 {"atmega169pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
202 {"atmega32", AVR_ISA_AVR5
, bfd_mach_avr5
},
203 {"atmega32a", AVR_ISA_AVR5
, bfd_mach_avr5
},
204 {"atmega323", AVR_ISA_AVR5
, bfd_mach_avr5
},
205 {"atmega324a", AVR_ISA_AVR5
, bfd_mach_avr5
},
206 {"atmega324p", AVR_ISA_AVR5
, bfd_mach_avr5
},
207 {"atmega324pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
208 {"atmega325", AVR_ISA_AVR5
, bfd_mach_avr5
},
209 {"atmega325a", AVR_ISA_AVR5
, bfd_mach_avr5
},
210 {"atmega325p", AVR_ISA_AVR5
, bfd_mach_avr5
},
211 {"atmega325pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
212 {"atmega3250", AVR_ISA_AVR5
, bfd_mach_avr5
},
213 {"atmega3250a",AVR_ISA_AVR5
, bfd_mach_avr5
},
214 {"atmega3250p",AVR_ISA_AVR5
, bfd_mach_avr5
},
215 {"atmega3250pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
216 {"atmega328", AVR_ISA_AVR5
, bfd_mach_avr5
},
217 {"atmega328p", AVR_ISA_AVR5
, bfd_mach_avr5
},
218 {"atmega329", AVR_ISA_AVR5
, bfd_mach_avr5
},
219 {"atmega329a", AVR_ISA_AVR5
, bfd_mach_avr5
},
220 {"atmega329p", AVR_ISA_AVR5
, bfd_mach_avr5
},
221 {"atmega329pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
222 {"atmega3290", AVR_ISA_AVR5
, bfd_mach_avr5
},
223 {"atmega3290a",AVR_ISA_AVR5
, bfd_mach_avr5
},
224 {"atmega3290p",AVR_ISA_AVR5
, bfd_mach_avr5
},
225 {"atmega3290pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
226 {"atmega406", AVR_ISA_AVR5
, bfd_mach_avr5
},
227 {"atmega64rfr2", AVR_ISA_AVR5
, bfd_mach_avr5
},
228 {"atmega644rfr2",AVR_ISA_AVR5
, bfd_mach_avr5
},
229 {"atmega64", AVR_ISA_AVR5
, bfd_mach_avr5
},
230 {"atmega64a", AVR_ISA_AVR5
, bfd_mach_avr5
},
231 {"atmega640", AVR_ISA_AVR5
, bfd_mach_avr5
},
232 {"atmega644", AVR_ISA_AVR5
, bfd_mach_avr5
},
233 {"atmega644a", AVR_ISA_AVR5
, bfd_mach_avr5
},
234 {"atmega644p", AVR_ISA_AVR5
, bfd_mach_avr5
},
235 {"atmega644pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
236 {"atmega645", AVR_ISA_AVR5
, bfd_mach_avr5
},
237 {"atmega645a", AVR_ISA_AVR5
, bfd_mach_avr5
},
238 {"atmega645p", AVR_ISA_AVR5
, bfd_mach_avr5
},
239 {"atmega649", AVR_ISA_AVR5
, bfd_mach_avr5
},
240 {"atmega649a", AVR_ISA_AVR5
, bfd_mach_avr5
},
241 {"atmega649p", AVR_ISA_AVR5
, bfd_mach_avr5
},
242 {"atmega6450", AVR_ISA_AVR5
, bfd_mach_avr5
},
243 {"atmega6450a",AVR_ISA_AVR5
, bfd_mach_avr5
},
244 {"atmega6450p",AVR_ISA_AVR5
, bfd_mach_avr5
},
245 {"atmega6490", AVR_ISA_AVR5
, bfd_mach_avr5
},
246 {"atmega6490a",AVR_ISA_AVR5
, bfd_mach_avr5
},
247 {"atmega6490p",AVR_ISA_AVR5
, bfd_mach_avr5
},
248 {"atmega64rfr2",AVR_ISA_AVR5
, bfd_mach_avr5
},
249 {"atmega644rfr2",AVR_ISA_AVR5
, bfd_mach_avr5
},
250 {"atmega16hva",AVR_ISA_AVR5
, bfd_mach_avr5
},
251 {"atmega16hva2",AVR_ISA_AVR5
, bfd_mach_avr5
},
252 {"atmega16hvb",AVR_ISA_AVR5
, bfd_mach_avr5
},
253 {"atmega16hvbrevb",AVR_ISA_AVR5
,bfd_mach_avr5
},
254 {"atmega32hvb",AVR_ISA_AVR5
, bfd_mach_avr5
},
255 {"atmega32hvbrevb",AVR_ISA_AVR5
,bfd_mach_avr5
},
256 {"atmega64hve",AVR_ISA_AVR5
, bfd_mach_avr5
},
257 {"at90can32" , AVR_ISA_AVR5
, bfd_mach_avr5
},
258 {"at90can64" , AVR_ISA_AVR5
, bfd_mach_avr5
},
259 {"at90pwm161", AVR_ISA_AVR5
, bfd_mach_avr5
},
260 {"at90pwm216", AVR_ISA_AVR5
, bfd_mach_avr5
},
261 {"at90pwm316", AVR_ISA_AVR5
, bfd_mach_avr5
},
262 {"atmega32c1", AVR_ISA_AVR5
, bfd_mach_avr5
},
263 {"atmega64c1", AVR_ISA_AVR5
, bfd_mach_avr5
},
264 {"atmega16m1", AVR_ISA_AVR5
, bfd_mach_avr5
},
265 {"atmega32m1", AVR_ISA_AVR5
, bfd_mach_avr5
},
266 {"atmega64m1", AVR_ISA_AVR5
, bfd_mach_avr5
},
267 {"atmega16u4", AVR_ISA_AVR5
, bfd_mach_avr5
},
268 {"atmega32u4", AVR_ISA_AVR5
, bfd_mach_avr5
},
269 {"atmega32u6", AVR_ISA_AVR5
, bfd_mach_avr5
},
270 {"at90usb646", AVR_ISA_AVR5
, bfd_mach_avr5
},
271 {"at90usb647", AVR_ISA_AVR5
, bfd_mach_avr5
},
272 {"at90scr100", AVR_ISA_AVR5
, bfd_mach_avr5
},
273 {"at94k", AVR_ISA_94K
, bfd_mach_avr5
},
274 {"m3000", AVR_ISA_AVR5
, bfd_mach_avr5
},
275 {"atmega128", AVR_ISA_AVR51
, bfd_mach_avr51
},
276 {"atmega128a", AVR_ISA_AVR51
, bfd_mach_avr51
},
277 {"atmega1280", AVR_ISA_AVR51
, bfd_mach_avr51
},
278 {"atmega1281", AVR_ISA_AVR51
, bfd_mach_avr51
},
279 {"atmega1284", AVR_ISA_AVR51
, bfd_mach_avr51
},
280 {"atmega1284p",AVR_ISA_AVR51
, bfd_mach_avr51
},
281 {"atmega128rfa1",AVR_ISA_AVR51
, bfd_mach_avr51
},
282 {"atmega128rfr2",AVR_ISA_AVR51
, bfd_mach_avr51
},
283 {"atmega1284rfr2",AVR_ISA_AVR51
, bfd_mach_avr51
},
284 {"at90can128", AVR_ISA_AVR51
, bfd_mach_avr51
},
285 {"at90usb1286",AVR_ISA_AVR51
, bfd_mach_avr51
},
286 {"at90usb1287",AVR_ISA_AVR51
, bfd_mach_avr51
},
287 {"atmega2560", AVR_ISA_AVR6
, bfd_mach_avr6
},
288 {"atmega2561", AVR_ISA_AVR6
, bfd_mach_avr6
},
289 {"atmega256rfr2", AVR_ISA_AVR6
, bfd_mach_avr6
},
290 {"atmega2564rfr2", AVR_ISA_AVR6
, bfd_mach_avr6
},
291 {"atxmega16a4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
292 {"atxmega16a4u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
293 {"atxmega16c4", AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
294 {"atxmega16d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
295 {"atxmega32a4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
296 {"atxmega32a4u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
297 {"atxmega32c4", AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
298 {"atxmega32d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
299 {"atxmega32e5", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
300 {"atxmega16e5", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
301 {"atxmega8e5", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
302 {"atxmega32x1", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
303 {"attiny416", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
304 {"attiny417", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
305 {"attiny816", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
306 {"attiny817", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
307 {"atxmega64a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
308 {"atxmega64a3u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
309 {"atxmega64a4u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
310 {"atxmega64b1", AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
311 {"atxmega64b3", AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
312 {"atxmega64c3", AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
313 {"atxmega64d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
314 {"atxmega64d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
315 {"atxmega64a1", AVR_ISA_XMEGA
, bfd_mach_avrxmega5
},
316 {"atxmega64a1u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega5
},
317 {"atxmega128a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
318 {"atxmega128a3u",AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
319 {"atxmega128b1", AVR_ISA_XMEGAU
, bfd_mach_avrxmega6
},
320 {"atxmega128b3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
321 {"atxmega128c3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
322 {"atxmega128d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
323 {"atxmega128d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
324 {"atxmega192a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
325 {"atxmega192a3u",AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
326 {"atxmega192c3", AVR_ISA_XMEGAU
, bfd_mach_avrxmega6
},
327 {"atxmega192d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
328 {"atxmega256a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
329 {"atxmega256a3u",AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
330 {"atxmega256a3b",AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
331 {"atxmega256a3bu",AVR_ISA_XMEGAU
, bfd_mach_avrxmega6
},
332 {"atxmega256c3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
333 {"atxmega256d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
334 {"atxmega384c3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
335 {"atxmega384d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
336 {"atxmega128a1", AVR_ISA_XMEGA
, bfd_mach_avrxmega7
},
337 {"atxmega128a1u", AVR_ISA_XMEGAU
, bfd_mach_avrxmega7
},
338 {"atxmega128a4u", AVR_ISA_XMEGAU
, bfd_mach_avrxmega7
},
339 {"attiny4", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
340 {"attiny5", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
341 {"attiny9", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
342 {"attiny10", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
343 {"attiny20", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
344 {"attiny40", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
349 /* Current MCU type. */
350 static struct mcu_type_s default_mcu
= {"avr2", AVR_ISA_AVR2
, bfd_mach_avr2
};
351 static struct mcu_type_s specified_mcu
;
352 static struct mcu_type_s
* avr_mcu
= & default_mcu
;
354 /* AVR target-specific switches. */
357 int all_opcodes
; /* -mall-opcodes: accept all known AVR opcodes. */
358 int no_skip_bug
; /* -mno-skip-bug: no warnings for skipping 2-word insns. */
359 int no_wrap
; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */
360 int no_link_relax
; /* -mno-link-relax / -mlink-relax: generate (or not)
361 relocations for linker relaxation. */
364 static struct avr_opt_s avr_opt
= { 0, 0, 0, 0 };
366 const char EXP_CHARS
[] = "eE";
367 const char FLT_CHARS
[] = "dD";
369 static void avr_set_arch (int);
371 /* The target specific pseudo-ops which we support. */
372 const pseudo_typeS md_pseudo_table
[] =
374 {"arch", avr_set_arch
, 0},
378 #define LDI_IMMEDIATE(x) (((x) & 0xf) | (((x) << 4) & 0xf00))
380 #define EXP_MOD_NAME(i) exp_mod[i].name
381 #define EXP_MOD_RELOC(i) exp_mod[i].reloc
382 #define EXP_MOD_NEG_RELOC(i) exp_mod[i].neg_reloc
383 #define HAVE_PM_P(i) exp_mod[i].have_pm
388 bfd_reloc_code_real_type reloc
;
389 bfd_reloc_code_real_type neg_reloc
;
393 static struct exp_mod_s exp_mod
[] =
395 {"hh8", BFD_RELOC_AVR_HH8_LDI
, BFD_RELOC_AVR_HH8_LDI_NEG
, 1},
396 {"pm_hh8", BFD_RELOC_AVR_HH8_LDI_PM
, BFD_RELOC_AVR_HH8_LDI_PM_NEG
, 0},
397 {"hi8", BFD_RELOC_AVR_HI8_LDI
, BFD_RELOC_AVR_HI8_LDI_NEG
, 1},
398 {"pm_hi8", BFD_RELOC_AVR_HI8_LDI_PM
, BFD_RELOC_AVR_HI8_LDI_PM_NEG
, 0},
399 {"lo8", BFD_RELOC_AVR_LO8_LDI
, BFD_RELOC_AVR_LO8_LDI_NEG
, 1},
400 {"pm_lo8", BFD_RELOC_AVR_LO8_LDI_PM
, BFD_RELOC_AVR_LO8_LDI_PM_NEG
, 0},
401 {"hlo8", BFD_RELOC_AVR_HH8_LDI
, BFD_RELOC_AVR_HH8_LDI_NEG
, 0},
402 {"hhi8", BFD_RELOC_AVR_MS8_LDI
, BFD_RELOC_AVR_MS8_LDI_NEG
, 0},
405 /* A union used to store indices into the exp_mod[] array
406 in a hash table which expects void * data types. */
413 /* Opcode hash table. */
414 static struct hash_control
*avr_hash
;
416 /* Reloc modifiers hash control (hh8,hi8,lo8,pm_xx). */
417 static struct hash_control
*avr_mod_hash
;
419 #define OPTION_MMCU 'm'
422 OPTION_ALL_OPCODES
= OPTION_MD_BASE
+ 1,
430 struct option md_longopts
[] =
432 { "mmcu", required_argument
, NULL
, OPTION_MMCU
},
433 { "mall-opcodes", no_argument
, NULL
, OPTION_ALL_OPCODES
},
434 { "mno-skip-bug", no_argument
, NULL
, OPTION_NO_SKIP_BUG
},
435 { "mno-wrap", no_argument
, NULL
, OPTION_NO_WRAP
},
436 { "mrmw", no_argument
, NULL
, OPTION_ISA_RMW
},
437 { "mlink-relax", no_argument
, NULL
, OPTION_LINK_RELAX
},
438 { "mno-link-relax", no_argument
, NULL
, OPTION_NO_LINK_RELAX
},
439 { NULL
, no_argument
, NULL
, 0 }
442 size_t md_longopts_size
= sizeof (md_longopts
);
444 /* Display nicely formatted list of known MCU names. */
447 show_mcu_list (FILE *stream
)
451 fprintf (stream
, _("Known MCU names:"));
454 for (i
= 0; mcu_types
[i
].name
; i
++)
456 int len
= strlen (mcu_types
[i
].name
);
461 fprintf (stream
, " %s", mcu_types
[i
].name
);
464 fprintf (stream
, "\n %s", mcu_types
[i
].name
);
469 fprintf (stream
, "\n");
475 while (*s
== ' ' || *s
== '\t')
480 /* Extract one word from FROM and copy it to TO. */
483 extract_word (char *from
, char *to
, int limit
)
488 /* Drop leading whitespace. */
489 from
= skip_space (from
);
492 /* Find the op code end. */
493 for (op_end
= from
; *op_end
!= 0 && is_part_of_name (*op_end
);)
495 to
[size
++] = *op_end
++;
496 if (size
+ 1 >= limit
)
505 md_estimate_size_before_relax (fragS
*fragp ATTRIBUTE_UNUSED
,
506 asection
*seg ATTRIBUTE_UNUSED
)
513 md_show_usage (FILE *stream
)
516 _("AVR Assembler options:\n"
517 " -mmcu=[avr-name] select microcontroller variant\n"
518 " [avr-name] can be:\n"
519 " avr1 - classic AVR core without data RAM\n"
520 " avr2 - classic AVR core with up to 8K program memory\n"
521 " avr25 - classic AVR core with up to 8K program memory\n"
522 " plus the MOVW instruction\n"
523 " avr3 - classic AVR core with up to 64K program memory\n"
524 " avr31 - classic AVR core with up to 128K program memory\n"
525 " avr35 - classic AVR core with up to 64K program memory\n"
526 " plus the MOVW instruction\n"
527 " avr4 - enhanced AVR core with up to 8K program memory\n"
528 " avr5 - enhanced AVR core with up to 64K program memory\n"
529 " avr51 - enhanced AVR core with up to 128K program memory\n"
530 " avr6 - enhanced AVR core with up to 256K program memory\n"
531 " avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM\n"
532 " avrxmega3 - XMEGA, > 8K, <= 64K FLASH, > 64K RAM\n"
533 " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n"
534 " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
535 " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
536 " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
537 " avrtiny - AVR Tiny core with 16 gp registers\n"));
539 _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
540 " -mno-skip-bug disable warnings for skipping two-word instructions\n"
541 " (default for avr4, avr5)\n"
542 " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n"
543 " (default for avr3, avr5)\n"
544 " -mrmw accept Read-Modify-Write instructions\n"
545 " -mlink-relax generate relocations for linker relaxation (default)\n"
546 " -mno-link-relax don't generate relocations for linker relaxation.\n"
548 show_mcu_list (stream
);
552 avr_set_arch (int dummy ATTRIBUTE_UNUSED
)
556 input_line_pointer
= extract_word (input_line_pointer
, str
, 20);
557 md_parse_option (OPTION_MMCU
, str
);
558 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, avr_mcu
->mach
);
562 md_parse_option (int c
, const char *arg
)
570 for (i
= 0; mcu_types
[i
].name
; ++i
)
571 if (strcasecmp (mcu_types
[i
].name
, arg
) == 0)
574 if (!mcu_types
[i
].name
)
576 show_mcu_list (stderr
);
577 as_fatal (_("unknown MCU: %s\n"), arg
);
580 /* It is OK to redefine mcu type within the same avr[1-5] bfd machine
581 type - this for allows passing -mmcu=... via gcc ASM_SPEC as well
582 as .arch ... in the asm output at the same time. */
583 if (avr_mcu
== &default_mcu
|| avr_mcu
->mach
== mcu_types
[i
].mach
)
585 specified_mcu
.name
= mcu_types
[i
].name
;
586 specified_mcu
.isa
|= mcu_types
[i
].isa
;
587 specified_mcu
.mach
= mcu_types
[i
].mach
;
588 avr_mcu
= &specified_mcu
;
591 as_fatal (_("redefinition of mcu type `%s' to `%s'"),
592 avr_mcu
->name
, mcu_types
[i
].name
);
595 case OPTION_ALL_OPCODES
:
596 avr_opt
.all_opcodes
= 1;
598 case OPTION_NO_SKIP_BUG
:
599 avr_opt
.no_skip_bug
= 1;
605 specified_mcu
.isa
|= AVR_ISA_RMW
;
607 case OPTION_LINK_RELAX
:
608 avr_opt
.no_link_relax
= 0;
610 case OPTION_NO_LINK_RELAX
:
611 avr_opt
.no_link_relax
= 1;
619 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
625 md_atof (int type
, char *litP
, int *sizeP
)
627 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
631 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
632 asection
*sec ATTRIBUTE_UNUSED
,
633 fragS
*fragP ATTRIBUTE_UNUSED
)
642 struct avr_opcodes_s
*opcode
;
644 avr_hash
= hash_new ();
646 /* Insert unique names into hash table. This hash table then provides a
647 quick index to the first opcode with a particular name in the opcode
649 for (opcode
= avr_opcodes
; opcode
->name
; opcode
++)
650 hash_insert (avr_hash
, opcode
->name
, (char *) opcode
);
652 avr_mod_hash
= hash_new ();
654 for (i
= 0; i
< ARRAY_SIZE (exp_mod
); ++i
)
659 hash_insert (avr_mod_hash
, EXP_MOD_NAME (i
), m
.ptr
);
662 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, avr_mcu
->mach
);
663 linkrelax
= !avr_opt
.no_link_relax
;
666 /* Resolve STR as a constant expression and return the result.
667 If result greater than MAX then error. */
670 avr_get_constant (char *str
, int max
)
674 str
= skip_space (str
);
675 input_line_pointer
= str
;
678 if (ex
.X_op
!= O_constant
)
679 as_bad (_("constant value required"));
681 if (ex
.X_add_number
> max
|| ex
.X_add_number
< 0)
682 as_bad (_("number must be positive and less than %d"), max
+ 1);
684 return ex
.X_add_number
;
687 /* Parse for ldd/std offset. */
690 avr_offset_expression (expressionS
*exp
)
692 char *str
= input_line_pointer
;
697 str
= extract_word (str
, op
, sizeof (op
));
699 input_line_pointer
= tmp
;
702 /* Warn about expressions that fail to use lo8 (). */
703 if (exp
->X_op
== O_constant
)
705 int x
= exp
->X_add_number
;
707 if (x
< -255 || x
> 255)
708 as_warn (_("constant out of 8-bit range: %d"), x
);
712 /* Parse ordinary expression. */
715 parse_exp (char *s
, expressionS
*op
)
717 input_line_pointer
= s
;
719 if (op
->X_op
== O_absent
)
720 as_bad (_("missing operand"));
721 return input_line_pointer
;
724 /* Parse special expressions (needed for LDI command):
729 where xx is: hh, hi, lo. */
731 static bfd_reloc_code_real_type
732 avr_ldi_expression (expressionS
*exp
)
734 char *str
= input_line_pointer
;
738 int linker_stubs_should_be_generated
= 0;
742 str
= extract_word (str
, op
, sizeof (op
));
748 m
.ptr
= hash_find (avr_mod_hash
, op
);
756 str
= skip_space (str
);
760 bfd_reloc_code_real_type reloc_to_return
;
765 if (strncmp ("pm(", str
, 3) == 0
766 || strncmp ("gs(",str
,3) == 0
767 || strncmp ("-(gs(",str
,5) == 0
768 || strncmp ("-(pm(", str
, 5) == 0)
776 as_bad (_("illegal expression"));
778 if (str
[0] == 'g' || str
[2] == 'g')
779 linker_stubs_should_be_generated
= 1;
791 if (*str
== '-' && *(str
+ 1) == '(')
798 input_line_pointer
= str
;
803 if (*input_line_pointer
!= ')')
805 as_bad (_("`)' required"));
808 input_line_pointer
++;
813 neg_p
? EXP_MOD_NEG_RELOC (mod
) : EXP_MOD_RELOC (mod
);
814 if (linker_stubs_should_be_generated
)
816 switch (reloc_to_return
)
818 case BFD_RELOC_AVR_LO8_LDI_PM
:
819 reloc_to_return
= BFD_RELOC_AVR_LO8_LDI_GS
;
821 case BFD_RELOC_AVR_HI8_LDI_PM
:
822 reloc_to_return
= BFD_RELOC_AVR_HI8_LDI_GS
;
826 /* PR 5523: Do not generate a warning here,
827 legitimate code can trigger this case. */
831 return reloc_to_return
;
836 input_line_pointer
= tmp
;
839 /* Warn about expressions that fail to use lo8 (). */
840 if (exp
->X_op
== O_constant
)
842 int x
= exp
->X_add_number
;
844 if (x
< -255 || x
> 255)
845 as_warn (_("constant out of 8-bit range: %d"), x
);
848 return BFD_RELOC_AVR_LDI
;
851 /* Parse one instruction operand.
852 Return operand bitmask. Also fixups can be generated. */
855 avr_operand (struct avr_opcodes_s
*opcode
,
861 unsigned int op_mask
= 0;
862 char *str
= skip_space (*line
);
866 /* Any register operand. */
873 char * old_str
= str
;
877 str
= extract_word (str
, r_name
, sizeof (r_name
));
878 for (lower
= r_name
; *lower
; ++lower
)
880 if (*lower
>= 'A' && *lower
<= 'Z')
884 if (r_name
[0] == 'r' && ISDIGIT (r_name
[1]) && r_name
[2] == 0)
885 /* Single-digit register number, ie r0-r9. */
886 op_mask
= r_name
[1] - '0';
887 else if (r_name
[0] == 'r' && ISDIGIT (r_name
[1])
888 && ISDIGIT (r_name
[2]) && r_name
[3] == 0)
889 /* Double-digit register number, ie r10 - r32. */
890 op_mask
= (r_name
[1] - '0') * 10 + r_name
[2] - '0';
891 else if (r_name
[0] >= 'x' && r_name
[0] <= 'z'
892 && (r_name
[1] == 'l' || r_name
[1] == 'h') && r_name
[2] == 0)
893 /* Registers r26-r31 referred to by name, ie xl, xh, yl, yh, zl, zh. */
894 op_mask
= (r_name
[0] - 'x') * 2 + (r_name
[1] == 'h') + 26;
895 else if ((*op
== 'v' || *op
== 'w')
896 && r_name
[0] >= 'x' && r_name
[0] <= 'z' && r_name
[1] == 0)
897 /* For the movw and addiw instructions, refer to registers x, y and z by name. */
898 op_mask
= (r_name
[0] - 'x') * 2 + 26;
901 /* Numeric or symbolic constant register number. */
902 op_mask
= avr_get_constant (old_str
, 31);
903 str
= input_line_pointer
;
907 if (avr_mcu
->mach
== bfd_mach_avrtiny
)
909 if (op_mask
< 16 || op_mask
> 31)
911 as_bad (_("register name or number from 16 to 31 required"));
915 else if (op_mask
> 31)
917 as_bad (_("register name or number from 0 to 31 required"));
924 if (op_mask
< 16 || op_mask
> 23)
925 as_bad (_("register r16-r23 required"));
931 as_bad (_("register number above 15 required"));
937 as_bad (_("even register number required"));
942 if ((op_mask
& 1) || op_mask
< 24)
943 as_bad (_("register r24, r26, r28 or r30 required"));
944 op_mask
= (op_mask
- 24) >> 1;
955 str
= skip_space (str
+ 1);
964 as_bad (_("pointer register (X, Y or Z) required"));
966 str
= skip_space (str
+ 1);
971 as_bad (_("cannot both predecrement and postincrement"));
975 /* avr1 can do "ld r,Z" and "st Z,r" but no other pointer
976 registers, no predecrement, no postincrement. */
977 if (!avr_opt
.all_opcodes
&& (op_mask
& 0x100F)
978 && !(avr_mcu
->isa
& AVR_ISA_SRAM
))
979 as_bad (_("addressing mode not supported"));
985 as_bad (_("can't predecrement"));
987 if (! (*str
== 'z' || *str
== 'Z'))
988 as_bad (_("pointer register Z required"));
990 str
= skip_space (str
+ 1);
996 for (s
= opcode
->opcode
; *s
; ++s
)
999 op_mask
|= (1 << (15 - (s
- opcode
->opcode
)));
1003 /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */
1004 if (!avr_opt
.all_opcodes
1005 && (op_mask
& 0x0001)
1006 && !(avr_mcu
->isa
& AVR_ISA_MOVW
))
1007 as_bad (_("postincrement not supported"));
1012 char c
= TOLOWER (*str
++);
1017 as_bad (_("pointer register (Y or Z) required"));
1018 str
= skip_space (str
);
1021 input_line_pointer
= str
;
1022 avr_offset_expression (& op_expr
);
1023 str
= input_line_pointer
;
1024 fix_new_exp (frag_now
, where
, 3,
1025 &op_expr
, FALSE
, BFD_RELOC_AVR_6
);
1031 str
= parse_exp (str
, &op_expr
);
1032 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1033 &op_expr
, FALSE
, BFD_RELOC_AVR_CALL
);
1037 str
= parse_exp (str
, &op_expr
);
1038 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1039 &op_expr
, TRUE
, BFD_RELOC_AVR_13_PCREL
);
1043 str
= parse_exp (str
, &op_expr
);
1044 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1045 &op_expr
, TRUE
, BFD_RELOC_AVR_7_PCREL
);
1049 str
= parse_exp (str
, &op_expr
);
1050 fix_new_exp (frag_now
, where
+ 2, opcode
->insn_size
* 2,
1051 &op_expr
, FALSE
, BFD_RELOC_16
);
1055 str
= parse_exp (str
, &op_expr
);
1056 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1057 &op_expr
, FALSE
, BFD_RELOC_AVR_LDS_STS_16
);
1062 bfd_reloc_code_real_type r_type
;
1064 input_line_pointer
= str
;
1065 r_type
= avr_ldi_expression (&op_expr
);
1066 str
= input_line_pointer
;
1067 fix_new_exp (frag_now
, where
, 3,
1068 &op_expr
, FALSE
, r_type
);
1076 x
= ~avr_get_constant (str
, 255);
1077 str
= input_line_pointer
;
1078 op_mask
|= (x
& 0xf) | ((x
<< 4) & 0xf00);
1083 input_line_pointer
= str
;
1084 avr_offset_expression (& op_expr
);
1085 str
= input_line_pointer
;
1086 fix_new_exp (frag_now
, where
, 3,
1087 & op_expr
, FALSE
, BFD_RELOC_AVR_6_ADIW
);
1095 x
= avr_get_constant (str
, 7);
1096 str
= input_line_pointer
;
1104 str
= parse_exp (str
, &op_expr
);
1105 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1106 &op_expr
, FALSE
, BFD_RELOC_AVR_PORT6
);
1110 str
= parse_exp (str
, &op_expr
);
1111 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1112 &op_expr
, FALSE
, BFD_RELOC_AVR_PORT5
);
1119 x
= avr_get_constant (str
, 15);
1120 str
= input_line_pointer
;
1121 op_mask
|= (x
<< 4);
1129 as_bad (_("unknown constraint `%c'"), *op
);
1136 /* Parse instruction operands.
1137 Return binary opcode. */
1140 avr_operands (struct avr_opcodes_s
*opcode
, char **line
)
1142 const char *op
= opcode
->constraints
;
1143 unsigned int bin
= opcode
->bin_opcode
;
1144 char *frag
= frag_more (opcode
->insn_size
* 2);
1146 int where
= frag
- frag_now
->fr_literal
;
1147 static unsigned int prev
= 0; /* Previous opcode. */
1149 /* Opcode have operands. */
1152 unsigned int reg1
= 0;
1153 unsigned int reg2
= 0;
1154 int reg1_present
= 0;
1155 int reg2_present
= 0;
1157 /* Parse first operand. */
1158 if (REGISTER_P (*op
))
1160 reg1
= avr_operand (opcode
, where
, op
, &str
);
1163 /* Parse second operand. */
1176 if (REGISTER_P (*op
))
1179 str
= skip_space (str
);
1181 as_bad (_("`,' required"));
1182 str
= skip_space (str
);
1184 reg2
= avr_operand (opcode
, where
, op
, &str
);
1187 if (reg1_present
&& reg2_present
)
1188 reg2
= (reg2
& 0xf) | ((reg2
<< 5) & 0x200);
1189 else if (reg2_present
)
1197 /* Detect undefined combinations (like ld r31,Z+). */
1198 if (!avr_opt
.all_opcodes
&& AVR_UNDEF_P (bin
))
1199 as_warn (_("undefined combination of operands"));
1201 if (opcode
->insn_size
== 2)
1203 /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs
1204 (AVR core bug, fixed in the newer devices). */
1205 if (!(avr_opt
.no_skip_bug
||
1206 (avr_mcu
->isa
& (AVR_ISA_MUL
| AVR_ISA_MOVW
)))
1207 && AVR_SKIP_P (prev
))
1208 as_warn (_("skipping two-word instruction"));
1210 bfd_putl32 ((bfd_vma
) bin
, frag
);
1213 bfd_putl16 ((bfd_vma
) bin
, frag
);
1220 /* GAS will call this function for each section at the end of the assembly,
1221 to permit the CPU backend to adjust the alignment of a section. */
1224 md_section_align (asection
*seg
, valueT addr
)
1226 int align
= bfd_get_section_alignment (stdoutput
, seg
);
1227 return ((addr
+ (1 << align
) - 1) & (-1UL << align
));
1230 /* If you define this macro, it should return the offset between the
1231 address of a PC relative fixup and the position from which the PC
1232 relative adjustment should be made. On many processors, the base
1233 of a PC relative instruction is the next instruction, so this
1234 macro would return the length of an instruction. */
1237 md_pcrel_from_section (fixS
*fixp
, segT sec
)
1239 if (fixp
->fx_addsy
!= (symbolS
*) NULL
1240 && (!S_IS_DEFINED (fixp
->fx_addsy
)
1241 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1244 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1248 relaxable_section (asection
*sec
)
1250 return ((sec
->flags
& SEC_DEBUGGING
) == 0
1251 && (sec
->flags
& SEC_CODE
) != 0
1252 && (sec
->flags
& SEC_ALLOC
) != 0);
1255 /* Does whatever the xtensa port does. */
1257 avr_validate_fix_sub (fixS
*fix
)
1259 segT add_symbol_segment
, sub_symbol_segment
;
1261 /* The difference of two symbols should be resolved by the assembler when
1262 linkrelax is not set. If the linker may relax the section containing
1263 the symbols, then an Xtensa DIFF relocation must be generated so that
1264 the linker knows to adjust the difference value. */
1265 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
1268 /* Make sure both symbols are in the same segment, and that segment is
1269 "normal" and relaxable. If the segment is not "normal", then the
1270 fix is not valid. If the segment is not "relaxable", then the fix
1271 should have been handled earlier. */
1272 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
1273 if (! SEG_NORMAL (add_symbol_segment
) ||
1274 ! relaxable_section (add_symbol_segment
))
1277 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
1278 return (sub_symbol_segment
== add_symbol_segment
);
1281 /* TC_FORCE_RELOCATION hook */
1283 /* If linkrelax is turned on, and the symbol to relocate
1284 against is in a relaxable segment, don't compute the value -
1285 generate a relocation instead. */
1287 avr_force_relocation (fixS
*fix
)
1289 if (linkrelax
&& fix
->fx_addsy
1290 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
1293 return generic_force_reloc (fix
);
1296 /* GAS will call this for each fixup. It should store the correct
1297 value in the object file. */
1300 md_apply_fix (fixS
*fixP
, valueT
* valP
, segT seg
)
1302 unsigned char *where
;
1306 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
1309 else if (fixP
->fx_pcrel
)
1311 segT s
= S_GET_SEGMENT (fixP
->fx_addsy
);
1313 if (s
== seg
|| s
== absolute_section
)
1315 value
+= S_GET_VALUE (fixP
->fx_addsy
);
1319 else if (linkrelax
&& fixP
->fx_subsy
)
1321 /* For a subtraction relocation expression, generate one
1322 of the DIFF relocs, with the value being the difference.
1323 Note that a sym1 - sym2 expression is adjusted into a
1324 section_start_sym + sym4_offset_from_section_start - sym1
1325 expression. fixP->fx_addsy holds the section start symbol,
1326 fixP->fx_offset holds sym2's offset, and fixP->fx_subsy
1327 holds sym1. Calculate the current difference and write value,
1328 but leave fx_offset as is - during relaxation,
1329 fx_offset - value gives sym1's value. */
1331 switch (fixP
->fx_r_type
)
1334 fixP
->fx_r_type
= BFD_RELOC_AVR_DIFF8
;
1337 fixP
->fx_r_type
= BFD_RELOC_AVR_DIFF16
;
1340 fixP
->fx_r_type
= BFD_RELOC_AVR_DIFF32
;
1343 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
1347 value
= S_GET_VALUE (fixP
->fx_addsy
) +
1348 fixP
->fx_offset
- S_GET_VALUE (fixP
->fx_subsy
);
1351 fixP
->fx_subsy
= NULL
;
1353 /* We don't actually support subtracting a symbol. */
1354 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
1355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
1357 /* For the DIFF relocs, write the value into the object file while still
1358 keeping fx_done FALSE, as both the difference (recorded in the object file)
1359 and the sym offset (part of fixP) are needed at link relax time. */
1360 where
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
1361 switch (fixP
->fx_r_type
)
1364 fixP
->fx_no_overflow
= 1;
1366 case BFD_RELOC_AVR_7_PCREL
:
1367 case BFD_RELOC_AVR_13_PCREL
:
1371 case BFD_RELOC_AVR_DIFF8
:
1374 case BFD_RELOC_AVR_DIFF16
:
1375 bfd_putl16 ((bfd_vma
) value
, where
);
1377 case BFD_RELOC_AVR_DIFF32
:
1378 bfd_putl32 ((bfd_vma
) value
, where
);
1380 case BFD_RELOC_AVR_CALL
:
1386 /* Fetch the instruction, insert the fully resolved operand
1387 value, and stuff the instruction back again. */
1388 where
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
1389 insn
= bfd_getl16 (where
);
1391 switch (fixP
->fx_r_type
)
1393 case BFD_RELOC_AVR_7_PCREL
:
1395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1396 _("odd address operand: %ld"), value
);
1398 /* Instruction addresses are always right-shifted by 1. */
1400 --value
; /* Correct PC. */
1402 if (value
< -64 || value
> 63)
1403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1404 _("operand out of range: %ld"), value
);
1405 value
= (value
<< 3) & 0x3f8;
1406 bfd_putl16 ((bfd_vma
) (value
| insn
), where
);
1409 case BFD_RELOC_AVR_13_PCREL
:
1411 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1412 _("odd address operand: %ld"), value
);
1414 /* Instruction addresses are always right-shifted by 1. */
1416 --value
; /* Correct PC. */
1418 if (value
< -2048 || value
> 2047)
1420 /* No wrap for devices with >8K of program memory. */
1421 if ((avr_mcu
->isa
& AVR_ISA_MEGA
) || avr_opt
.no_wrap
)
1422 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1423 _("operand out of range: %ld"), value
);
1427 bfd_putl16 ((bfd_vma
) (value
| insn
), where
);
1431 bfd_putl32 ((bfd_vma
) value
, where
);
1435 bfd_putl16 ((bfd_vma
) value
, where
);
1439 if (value
> 255 || value
< -128)
1440 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
1441 _("operand out of range: %ld"), value
);
1445 case BFD_RELOC_AVR_16_PM
:
1446 bfd_putl16 ((bfd_vma
) (value
>> 1), where
);
1449 case BFD_RELOC_AVR_LDI
:
1451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1452 _("operand out of range: %ld"), value
);
1453 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
), where
);
1456 case BFD_RELOC_AVR_LDS_STS_16
:
1457 if ((value
< 0x40) || (value
> 0xBF))
1458 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
1459 _("operand out of range: 0x%lx"),
1460 (unsigned long)value
);
1461 insn
|= ((value
& 0xF) | ((value
& 0x30) << 5) | ((value
& 0x40) << 2));
1462 bfd_putl16 ((bfd_vma
) insn
, where
);
1465 case BFD_RELOC_AVR_6
:
1466 if ((value
> 63) || (value
< 0))
1467 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1468 _("operand out of range: %ld"), value
);
1469 bfd_putl16 ((bfd_vma
) insn
| ((value
& 7) | ((value
& (3 << 3)) << 7)
1470 | ((value
& (1 << 5)) << 8)), where
);
1473 case BFD_RELOC_AVR_6_ADIW
:
1474 if ((value
> 63) || (value
< 0))
1475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1476 _("operand out of range: %ld"), value
);
1477 bfd_putl16 ((bfd_vma
) insn
| (value
& 0xf) | ((value
& 0x30) << 2), where
);
1480 case BFD_RELOC_AVR_LO8_LDI
:
1481 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
), where
);
1484 case BFD_RELOC_AVR_HI8_LDI
:
1485 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 8), where
);
1488 case BFD_RELOC_AVR_MS8_LDI
:
1489 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 24), where
);
1492 case BFD_RELOC_AVR_HH8_LDI
:
1493 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 16), where
);
1496 case BFD_RELOC_AVR_LO8_LDI_NEG
:
1497 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
), where
);
1500 case BFD_RELOC_AVR_HI8_LDI_NEG
:
1501 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 8), where
);
1504 case BFD_RELOC_AVR_MS8_LDI_NEG
:
1505 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 24), where
);
1508 case BFD_RELOC_AVR_HH8_LDI_NEG
:
1509 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 16), where
);
1512 case BFD_RELOC_AVR_LO8_LDI_PM
:
1513 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 1), where
);
1516 case BFD_RELOC_AVR_HI8_LDI_PM
:
1517 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 9), where
);
1520 case BFD_RELOC_AVR_HH8_LDI_PM
:
1521 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 17), where
);
1524 case BFD_RELOC_AVR_LO8_LDI_PM_NEG
:
1525 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 1), where
);
1528 case BFD_RELOC_AVR_HI8_LDI_PM_NEG
:
1529 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 9), where
);
1532 case BFD_RELOC_AVR_HH8_LDI_PM_NEG
:
1533 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 17), where
);
1536 case BFD_RELOC_AVR_CALL
:
1540 x
= bfd_getl16 (where
);
1542 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1543 _("odd address operand: %ld"), value
);
1545 x
|= ((value
& 0x10000) | ((value
<< 3) & 0x1f00000)) >> 16;
1546 bfd_putl16 ((bfd_vma
) x
, where
);
1547 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
1551 case BFD_RELOC_AVR_8_LO
:
1552 *where
= 0xff & value
;
1555 case BFD_RELOC_AVR_8_HI
:
1556 *where
= 0xff & (value
>> 8);
1559 case BFD_RELOC_AVR_8_HLO
:
1560 *where
= 0xff & (value
>> 16);
1564 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1565 fixP
->fx_line
, fixP
->fx_r_type
);
1568 case BFD_RELOC_AVR_PORT6
:
1570 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1571 _("operand out of range: %ld"), value
);
1572 bfd_putl16 ((bfd_vma
) insn
| ((value
& 0x30) << 5) | (value
& 0x0f), where
);
1575 case BFD_RELOC_AVR_PORT5
:
1577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1578 _("operand out of range: %ld"), value
);
1579 bfd_putl16 ((bfd_vma
) insn
| ((value
& 0x1f) << 3), where
);
1585 switch ((int) fixP
->fx_r_type
)
1587 case -BFD_RELOC_AVR_HI8_LDI_NEG
:
1588 case -BFD_RELOC_AVR_HI8_LDI
:
1589 case -BFD_RELOC_AVR_LO8_LDI_NEG
:
1590 case -BFD_RELOC_AVR_LO8_LDI
:
1591 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1592 _("only constant expression allowed"));
1601 /* GAS will call this to generate a reloc, passing the resulting reloc
1602 to `bfd_install_relocation'. This currently works poorly, as
1603 `bfd_install_relocation' often does the wrong thing, and instances of
1604 `tc_gen_reloc' have been written to work around the problems, which
1605 in turns makes it difficult to fix `bfd_install_relocation'. */
1607 /* If while processing a fixup, a reloc really needs to be created
1608 then it is done here. */
1611 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
,
1615 bfd_reloc_code_real_type code
= fixp
->fx_r_type
;
1617 if (fixp
->fx_subsy
!= NULL
)
1619 as_bad_where (fixp
->fx_file
, fixp
->fx_line
, _("expression too complex"));
1623 reloc
= XNEW (arelent
);
1625 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
1626 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1628 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1630 if ((fixp
->fx_r_type
== BFD_RELOC_32
) && (fixp
->fx_pcrel
))
1632 if (seg
->use_rela_p
)
1633 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, seg
);
1635 fixp
->fx_offset
= reloc
->address
;
1637 code
= BFD_RELOC_32_PCREL
;
1640 reloc
->addend
= fixp
->fx_offset
;
1642 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1644 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1646 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1647 _("reloc %d not supported by object file format"),
1648 (int) fixp
->fx_r_type
);
1652 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1653 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1654 reloc
->address
= fixp
->fx_offset
;
1661 md_assemble (char *str
)
1663 struct avr_opcodes_s
*opcode
;
1666 str
= skip_space (extract_word (str
, op
, sizeof (op
)));
1669 as_bad (_("can't find opcode "));
1671 opcode
= (struct avr_opcodes_s
*) hash_find (avr_hash
, op
);
1673 if (opcode
&& !avr_opt
.all_opcodes
)
1675 /* Check if the instruction's ISA bit is ON in the ISA bits of the part
1676 specified by the user. If not look for other instructions
1677 specifications with same mnemonic who's ISA bits matches.
1679 This requires include/opcode/avr.h to have the instructions with
1680 same mnemonic to be specified in sequence. */
1682 while ((opcode
->isa
& avr_mcu
->isa
) != opcode
->isa
)
1686 if (opcode
->name
&& strcmp(op
, opcode
->name
))
1688 as_bad (_("illegal opcode %s for mcu %s"),
1689 opcode
->name
, avr_mcu
->name
);
1697 as_bad (_("unknown opcode `%s'"), op
);
1701 /* Special case for opcodes with optional operands (lpm, elpm) -
1702 version with operands exists in avr_opcodes[] in the next entry. */
1704 if (*str
&& *opcode
->constraints
== '?')
1707 dwarf2_emit_insn (0);
1709 /* We used to set input_line_pointer to the result of get_operands,
1710 but that is wrong. Our caller assumes we don't change it. */
1712 char *t
= input_line_pointer
;
1714 avr_operands (opcode
, &str
);
1715 if (*skip_space (str
))
1716 as_bad (_("garbage at end of line"));
1717 input_line_pointer
= t
;
1721 const exp_mod_data_t exp_mod_data
[] =
1723 /* Default, must be first. */
1724 { "", 0, BFD_RELOC_16
, "" },
1725 /* Divides by 2 to get word address. Generate Stub. */
1726 { "gs", 2, BFD_RELOC_AVR_16_PM
, "`gs' " },
1727 { "pm", 2, BFD_RELOC_AVR_16_PM
, "`pm' " },
1728 /* The following are used together with avr-gcc's __memx address space
1729 in order to initialize a 24-bit pointer variable with a 24-bit address.
1730 For address in flash, hlo8 will contain the flash segment if the
1731 symbol is located in flash. If the symbol is located in RAM; hlo8
1732 will contain 0x80 which matches avr-gcc's notion of how 24-bit RAM/flash
1733 addresses linearize address space. */
1734 { "lo8", 1, BFD_RELOC_AVR_8_LO
, "`lo8' " },
1735 { "hi8", 1, BFD_RELOC_AVR_8_HI
, "`hi8' " },
1736 { "hlo8", 1, BFD_RELOC_AVR_8_HLO
, "`hlo8' " },
1737 { "hh8", 1, BFD_RELOC_AVR_8_HLO
, "`hh8' " },
1740 /* Parse special CONS expression: pm (expression) or alternatively
1741 gs (expression). These are used for addressing program memory. Moreover,
1742 define lo8 (expression), hi8 (expression) and hlo8 (expression). */
1744 const exp_mod_data_t
*
1745 avr_parse_cons_expression (expressionS
*exp
, int nbytes
)
1750 tmp
= input_line_pointer
= skip_space (input_line_pointer
);
1752 /* The first entry of exp_mod_data[] contains an entry if no
1753 expression modifier is present. Skip it. */
1755 for (i
= 0; i
< ARRAY_SIZE (exp_mod_data
); i
++)
1757 const exp_mod_data_t
*pexp
= &exp_mod_data
[i
];
1758 int len
= strlen (pexp
->name
);
1760 if (nbytes
== pexp
->nbytes
1761 && strncasecmp (input_line_pointer
, pexp
->name
, len
) == 0)
1763 input_line_pointer
= skip_space (input_line_pointer
+ len
);
1765 if (*input_line_pointer
== '(')
1767 input_line_pointer
= skip_space (input_line_pointer
+ 1);
1770 if (*input_line_pointer
== ')')
1772 ++input_line_pointer
;
1777 as_bad (_("`)' required"));
1778 return &exp_mod_data
[0];
1782 input_line_pointer
= tmp
;
1789 return &exp_mod_data
[0];
1793 avr_cons_fix_new (fragS
*frag
,
1797 const exp_mod_data_t
*pexp_mod_data
)
1801 switch (pexp_mod_data
->reloc
)
1805 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, BFD_RELOC_8
);
1806 else if (nbytes
== 2)
1807 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, BFD_RELOC_16
);
1808 else if (nbytes
== 4)
1809 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, BFD_RELOC_32
);
1814 case BFD_RELOC_AVR_16_PM
:
1815 case BFD_RELOC_AVR_8_LO
:
1816 case BFD_RELOC_AVR_8_HI
:
1817 case BFD_RELOC_AVR_8_HLO
:
1818 if (nbytes
== pexp_mod_data
->nbytes
)
1819 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, pexp_mod_data
->reloc
);
1826 as_bad (_("illegal %s relocation size: %d"), pexp_mod_data
->error
, nbytes
);
1830 mcu_has_3_byte_pc (void)
1832 int mach
= avr_mcu
->mach
;
1834 return mach
== bfd_mach_avr6
1835 || mach
== bfd_mach_avrxmega6
1836 || mach
== bfd_mach_avrxmega7
;
1840 tc_cfi_frame_initial_instructions (void)
1842 /* AVR6 pushes 3 bytes for calls. */
1843 int return_size
= (mcu_has_3_byte_pc () ? 3 : 2);
1845 /* The CFA is the caller's stack location before the call insn. */
1846 /* Note that the stack pointer is dwarf register number 32. */
1847 cfi_add_CFA_def_cfa (32, return_size
);
1849 /* Note that AVR consistently uses post-decrement, which means that things
1850 do not line up the same way as for targets that use pre-decrement. */
1851 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, 1-return_size
);
1855 avr_allow_local_subtract (expressionS
* left
,
1856 expressionS
* right
,
1859 /* If we are not in relaxation mode, subtraction is OK. */
1863 /* If the symbols are not in a code section then they are OK. */
1864 if ((section
->flags
& SEC_CODE
) == 0)
1867 if (left
->X_add_symbol
== right
->X_add_symbol
)
1870 /* We have to assume that there may be instructions between the
1871 two symbols and that relaxation may increase the distance between
1877 avr_elf_final_processing (void)
1880 elf_elfheader (stdoutput
)->e_flags
|= EF_AVR_LINKRELAX_PREPARED
;
1883 /* Write out the header of a .avr.prop section into the area pointed to by
1884 DATA. The RECORD_COUNT will be placed in the header as the number of
1885 records that are to follow.
1886 The area DATA must be big enough the receive the header, which is
1887 AVR_PROPERTY_SECTION_HEADER_SIZE bytes long. */
1890 avr_output_property_section_header (char *data
,
1891 unsigned int record_count
)
1893 char *orig_data
= data
;
1895 md_number_to_chars (data
, AVR_PROPERTY_RECORDS_VERSION
, 1);
1897 /* There's space for a single byte flags field, but right now there's
1898 nothing to go in here, so just set the value to zero. */
1899 md_number_to_chars (data
, 0, 1);
1901 md_number_to_chars (data
, record_count
, 2);
1904 gas_assert (data
- orig_data
== AVR_PROPERTY_SECTION_HEADER_SIZE
);
1909 /* Return the number of bytes required to store RECORD into the .avr.prop
1910 section. The size returned is the compressed size that corresponds to
1911 how the record will be written out in AVR_OUTPUT_PROPERTY_RECORD. */
1914 avr_record_size (const struct avr_property_record
*record
)
1916 /* The first 5 bytes are a 4-byte address, followed by a 1-byte type
1920 switch (record
->type
)
1923 size
+= 0; /* No extra information. */
1926 case RECORD_ORG_AND_FILL
:
1927 size
+= 4; /* A 4-byte fill value. */
1931 size
+= 4; /* A 4-byte alignment value. */
1934 case RECORD_ALIGN_AND_FILL
:
1935 size
+= 8; /* A 4-byte alignment, and 4-byte fill value. */
1939 as_fatal (_("unknown record type %d (in %s)"),
1940 record
->type
, __PRETTY_FUNCTION__
);
1946 /* Write out RECORD. FRAG_BASE points to the start of the data area setup
1947 to hold all of the .avr.prop content, FRAG_PTR points to the next
1948 writable location. The data area must be big enough to hold all of the
1949 records. The size of the data written out for this RECORD must match
1950 the size from AVR_RECORD_SIZE. */
1953 avr_output_property_record (char * const frag_base
, char *frag_ptr
,
1954 const struct avr_property_record
*record
)
1958 char *init_frag_ptr
= frag_ptr
;
1960 where
= frag_ptr
- frag_base
;
1961 fix
= fix_new (frag_now
, where
, 4,
1962 section_symbol (record
->section
),
1963 record
->offset
, FALSE
, BFD_RELOC_32
);
1964 fix
->fx_file
= "<internal>";
1968 md_number_to_chars (frag_ptr
, (bfd_byte
) record
->type
, 1);
1971 /* Write out the rest of the data. */
1972 switch (record
->type
)
1977 case RECORD_ORG_AND_FILL
:
1978 md_number_to_chars (frag_ptr
, record
->data
.org
.fill
, 4);
1983 md_number_to_chars (frag_ptr
, record
->data
.align
.bytes
, 4);
1987 case RECORD_ALIGN_AND_FILL
:
1988 md_number_to_chars (frag_ptr
, record
->data
.align
.bytes
, 4);
1989 md_number_to_chars (frag_ptr
+ 4, record
->data
.align
.fill
, 4);
1994 as_fatal (_("unknown record type %d (in %s)"),
1995 record
->type
, __PRETTY_FUNCTION__
);
1998 gas_assert (frag_ptr
- init_frag_ptr
== avr_record_size (record
));
2003 /* Create the section to hold the AVR property information. Return the
2007 avr_create_property_section (void)
2010 flagword flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
);
2011 const char *section_name
= AVR_PROPERTY_RECORD_SECTION_NAME
;
2013 sec
= bfd_make_section (stdoutput
, section_name
);
2015 as_fatal (_("Failed to create property section `%s'\n"), section_name
);
2016 bfd_set_section_flags (stdoutput
, sec
, flags
);
2017 sec
->output_section
= sec
;
2021 /* This hook is called when alignment is performed, and allows us to
2022 capture the details of both .org and .align directives. */
2025 avr_handle_align (fragS
*fragP
)
2029 /* Ignore alignment requests at FR_ADDRESS 0, these are at the very
2030 start of a section, and will be handled by the standard section
2031 alignment mechanism. */
2032 if ((fragP
->fr_type
== rs_align
2033 || fragP
->fr_type
== rs_align_code
)
2034 && fragP
->fr_offset
> 0)
2036 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2038 fragP
->tc_frag_data
.is_align
= TRUE
;
2039 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
2040 fragP
->tc_frag_data
.fill
= *p
;
2041 fragP
->tc_frag_data
.has_fill
= (fragP
->tc_frag_data
.fill
!= 0);
2044 if (fragP
->fr_type
== rs_org
&& fragP
->fr_offset
> 0)
2046 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2048 fragP
->tc_frag_data
.is_org
= TRUE
;
2049 fragP
->tc_frag_data
.fill
= *p
;
2050 fragP
->tc_frag_data
.has_fill
= (fragP
->tc_frag_data
.fill
!= 0);
2055 /* Return TRUE if this section is not one for which we need to record
2056 information in the avr property section. */
2059 exclude_section_from_property_tables (segT sec
)
2061 /* Only generate property information for sections on which linker
2062 relaxation could be performed. */
2063 return !relaxable_section (sec
);
2066 /* Create a property record for fragment FRAGP from section SEC and place
2067 it into an AVR_PROPERTY_RECORD_LINK structure, which can then formed
2068 into a linked list by the caller. */
2070 static struct avr_property_record_link
*
2071 create_record_for_frag (segT sec
, fragS
*fragP
)
2073 struct avr_property_record_link
*prop_rec_link
;
2075 prop_rec_link
= XCNEW (struct avr_property_record_link
);
2076 gas_assert (fragP
->fr_next
!= NULL
);
2078 if (fragP
->tc_frag_data
.is_org
)
2080 prop_rec_link
->record
.offset
= fragP
->fr_next
->fr_address
;
2081 prop_rec_link
->record
.section
= sec
;
2083 if (fragP
->tc_frag_data
.has_fill
)
2085 prop_rec_link
->record
.data
.org
.fill
= fragP
->tc_frag_data
.fill
;
2086 prop_rec_link
->record
.type
= RECORD_ORG_AND_FILL
;
2089 prop_rec_link
->record
.type
= RECORD_ORG
;
2093 prop_rec_link
->record
.offset
= fragP
->fr_next
->fr_address
;
2094 prop_rec_link
->record
.section
= sec
;
2096 gas_assert (fragP
->tc_frag_data
.is_align
);
2097 if (fragP
->tc_frag_data
.has_fill
)
2099 prop_rec_link
->record
.data
.align
.fill
= fragP
->tc_frag_data
.fill
;
2100 prop_rec_link
->record
.type
= RECORD_ALIGN_AND_FILL
;
2103 prop_rec_link
->record
.type
= RECORD_ALIGN
;
2104 prop_rec_link
->record
.data
.align
.bytes
= fragP
->tc_frag_data
.alignment
;
2107 return prop_rec_link
;
2110 /* Build a list of AVR_PROPERTY_RECORD_LINK structures for section SEC, and
2111 merged them onto the list pointed to by NEXT_PTR. Return a pointer to
2112 the last list item created. */
2114 static struct avr_property_record_link
**
2115 append_records_for_section (segT sec
,
2116 struct avr_property_record_link
**next_ptr
)
2118 segment_info_type
*seginfo
= seg_info (sec
);
2121 if (seginfo
&& seginfo
->frchainP
)
2123 for (fragP
= seginfo
->frchainP
->frch_root
;
2125 fragP
= fragP
->fr_next
)
2127 if (fragP
->tc_frag_data
.is_align
2128 || fragP
->tc_frag_data
.is_org
)
2130 /* Create a single new entry. */
2131 struct avr_property_record_link
*new_link
2132 = create_record_for_frag (sec
, fragP
);
2134 *next_ptr
= new_link
;
2135 next_ptr
= &new_link
->next
;
2143 /* Create the AVR property section and fill it with records of .org and
2144 .align directives that were used. The section is only created if it
2145 will actually have any content. */
2148 avr_create_and_fill_property_section (void)
2152 struct avr_property_record_link
*r_list
, **next_ptr
;
2153 char *frag_ptr
, *frag_base
;
2154 bfd_size_type sec_size
;
2155 struct avr_property_record_link
*rec
;
2156 unsigned int record_count
;
2158 /* First walk over all sections. For sections on which linker
2159 relaxation could be applied, extend the record list. The record list
2160 holds information that the linker will need to know. */
2165 for (seclist
= &stdoutput
->sections
;
2166 seclist
&& *seclist
;
2167 seclist
= &(*seclist
)->next
)
2169 segT sec
= *seclist
;
2171 if (exclude_section_from_property_tables (sec
))
2174 next_ptr
= append_records_for_section (sec
, next_ptr
);
2177 /* Create property section and ensure the size is correct. We've already
2178 passed the point where gas could size this for us. */
2179 sec_size
= AVR_PROPERTY_SECTION_HEADER_SIZE
;
2181 for (rec
= r_list
; rec
!= NULL
; rec
= rec
->next
)
2184 sec_size
+= avr_record_size (&rec
->record
);
2187 if (record_count
== 0)
2190 prop_sec
= avr_create_property_section ();
2191 bfd_set_section_size (stdoutput
, prop_sec
, sec_size
);
2193 subseg_set (prop_sec
, 0);
2194 frag_base
= frag_more (sec_size
);
2197 avr_output_property_section_header (frag_base
, record_count
);
2199 for (rec
= r_list
; rec
!= NULL
; rec
= rec
->next
)
2200 frag_ptr
= avr_output_property_record (frag_base
, frag_ptr
, &rec
->record
);
2202 frag_wane (frag_now
);
2204 frag_wane (frag_now
);
2207 /* We're using this hook to build up the AVR property section. It's called
2208 late in the assembly process which suits our needs. */
2210 avr_post_relax_hook (void)
2212 avr_create_and_fill_property_section ();