1 /* tc-avr.c -- Assembler code for the ATMEL AVR
3 Copyright (C) 1999-2020 Free Software Foundation, Inc.
4 Contributed by Denis Chertykov <denisc@overta.ru>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
24 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "elf32-avr.h"
31 /* For building a linked list of AVR_PROPERTY_RECORD structures. */
32 struct avr_property_record_link
34 struct avr_property_record record
;
35 struct avr_property_record_link
*next
;
41 const char * constraints
;
43 int insn_size
; /* In words. */
45 unsigned int bin_opcode
;
48 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
49 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
51 struct avr_opcodes_s avr_opcodes
[] =
53 #include "opcode/avr.h"
54 {NULL
, NULL
, NULL
, 0, 0, 0}
58 /* Stuff for the `__gcc_isr' pseudo instruction.
60 Purpose of the pseudo instruction is to emit more efficient ISR prologues
61 and epilogues than GCC currently does. GCC has no explicit (on RTL level)
62 modelling of SREG, TMP_REG or ZERO_REG. These regs are used implicitly
63 during instruction printing. That doesn't hurt too much for ordinary
64 functions, however for small ISRs there might be some overhead.
66 As implementing http://gcc.gnu.org/PR20296 would imply an almost complete
67 rewite of GCC's AVR back-end (which might pop up less optimized code in
68 other places), we provide a pseudo-instruction which is resolved by GAS
69 into ISR prologue / epilogue as expected by GCC.
71 Using GAS for this purpose has the additional benefit that it can scan
72 code emit by inline asm which is opaque to GCC.
74 The pseudo-instruction is only supposed to handle the starting of
75 prologue and the ending of epilogues (without RETI) which deal with
76 SREG, TMP_REG and ZERO_REG and one additional, optional general purpose
79 __gcc_isr consists of 3 different "chunks":
82 Chunk 1 (ISR_CHUNK_Prologue)
83 Start the ISR code. Will be replaced by ISR prologue by next Done chunk.
84 Must be the 1st chunk in a file or follow a Done chunk from previous
85 ISR (which has been patched already).
87 It will finish the current frag and emit a new frag of
88 type rs_machine_dependent, subtype ISR_CHUNK_Prologue.
91 Chunk 2 (ISR_CHUNK_Epilogue)
92 Will be replaced by ISR epilogue by next Done chunk. Must follow
93 chunk 1 (Prologue) or chunk 2 (Epilogue). Functions might come
94 without epilogue or with more than one epilogue, and even code
95 located statically after the last epilogue might belong to a function.
97 It will finish the current frag and emit a new frag of
98 type rs_machine_dependent, subtype ISR_CHUNK_Epilogue.
101 Chunk 0 (ISR_CHUNK_Done)
102 Must follow chunk 1 (Prologue) or chunk 2 (Epilogue) and finishes
103 the ISR code. Only GCC can know where a function's code ends.
105 It triggers the patch-up of all rs_machine_dependent frags in the
106 current frag chain and turns them into ordinary rs_fill code frags.
108 If Rx is a register > ZERO_REG then GCC also wants to push / pop Rx.
109 If neither TMP_REG nor ZERO_REG are needed, Rx will be used in
110 the push / pop sequence avoiding the need for TMP_REG / ZERO_REG.
111 If Rx <= ZERO_REG then GCC doesn't assume anything about Rx.
115 o GCC takes care of code that is opaque to GAS like tail calls
118 o Using SEI / CLI does not count as clobbering SREG. This is
119 because a final RETI will restore the I-flag.
121 o Using OUT or ST* is supposed not to clobber SREG. Sequences like
123 IN-SREG + CLI + Atomic-Code + OUT-SREG
125 will still work as expected because the scan will reveal any
126 clobber of SREG other than I-flag and emit PUSH / POP of SREG.
132 ISR_CHUNK_Prologue
= 1,
133 ISR_CHUNK_Epilogue
= 2
138 /* Previous __gcc_isr chunk (one of the enums above)
139 and it's location for diagnostics. */
143 /* Replacer for __gcc_isr.n_pushed once we know how many regs are
144 pushed by the Prologue chunk. */
145 symbolS
*sym_n_pushed
;
147 /* Set and used during parse from chunk 1 (Prologue) up to chunk 0 (Done).
148 Set by `avr_update_gccisr' and used by `avr_patch_gccisr_frag'. */
154 static void avr_gccisr_operands (struct avr_opcodes_s
*, char**);
155 static void avr_update_gccisr (struct avr_opcodes_s
*, int, int);
156 static struct avr_opcodes_s
*avr_gccisr_opcode
;
158 const char comment_chars
[] = ";";
159 const char line_comment_chars
[] = "#";
160 const char line_separator_chars
[] = "$";
162 const char *md_shortopts
= "m:";
170 /* XXX - devices that don't seem to exist (renamed, replaced with larger
171 ones, or planned but never produced), left here for compatibility. */
173 static struct mcu_type_s mcu_types
[] =
175 {"avr1", AVR_ISA_AVR1
, bfd_mach_avr1
},
176 /* TODO: instruction set for avr2 architecture should be AVR_ISA_AVR2,
177 but set to AVR_ISA_AVR25 for some following version
178 of GCC (from 4.3) for backward compatibility. */
179 {"avr2", AVR_ISA_AVR25
, bfd_mach_avr2
},
180 {"avr25", AVR_ISA_AVR25
, bfd_mach_avr25
},
181 /* TODO: instruction set for avr3 architecture should be AVR_ISA_AVR3,
182 but set to AVR_ISA_AVR3_ALL for some following version
183 of GCC (from 4.3) for backward compatibility. */
184 {"avr3", AVR_ISA_AVR3_ALL
, bfd_mach_avr3
},
185 {"avr31", AVR_ISA_AVR31
, bfd_mach_avr31
},
186 {"avr35", AVR_ISA_AVR35
, bfd_mach_avr35
},
187 {"avr4", AVR_ISA_AVR4
, bfd_mach_avr4
},
188 /* TODO: instruction set for avr5 architecture should be AVR_ISA_AVR5,
189 but set to AVR_ISA_AVR51 for some following version
190 of GCC (from 4.3) for backward compatibility. */
191 {"avr5", AVR_ISA_AVR51
, bfd_mach_avr5
},
192 {"avr51", AVR_ISA_AVR51
, bfd_mach_avr51
},
193 {"avr6", AVR_ISA_AVR6
, bfd_mach_avr6
},
194 {"avrxmega1", AVR_ISA_XMEGA
, bfd_mach_avrxmega1
},
195 {"avrxmega2", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
196 {"avrxmega3", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
197 {"avrxmega4", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
198 {"avrxmega5", AVR_ISA_XMEGA
, bfd_mach_avrxmega5
},
199 {"avrxmega6", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
200 {"avrxmega7", AVR_ISA_XMEGA
, bfd_mach_avrxmega7
},
201 {"avrtiny", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
202 {"at90s1200", AVR_ISA_1200
, bfd_mach_avr1
},
203 {"attiny11", AVR_ISA_AVR1
, bfd_mach_avr1
},
204 {"attiny12", AVR_ISA_AVR1
, bfd_mach_avr1
},
205 {"attiny15", AVR_ISA_AVR1
, bfd_mach_avr1
},
206 {"attiny28", AVR_ISA_AVR1
, bfd_mach_avr1
},
207 {"at90s2313", AVR_ISA_AVR2
, bfd_mach_avr2
},
208 {"at90s2323", AVR_ISA_AVR2
, bfd_mach_avr2
},
209 {"at90s2333", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 4433 */
210 {"at90s2343", AVR_ISA_AVR2
, bfd_mach_avr2
},
211 {"attiny22", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 2343 */
212 {"attiny26", AVR_ISA_2xxe
, bfd_mach_avr2
},
213 {"at90s4414", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 8515 */
214 {"at90s4433", AVR_ISA_AVR2
, bfd_mach_avr2
},
215 {"at90s4434", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 8535 */
216 {"at90s8515", AVR_ISA_AVR2
, bfd_mach_avr2
},
217 {"at90c8534", AVR_ISA_AVR2
, bfd_mach_avr2
},
218 {"at90s8535", AVR_ISA_AVR2
, bfd_mach_avr2
},
219 {"ata5272", AVR_ISA_AVR25
, bfd_mach_avr25
},
220 {"attiny13", AVR_ISA_AVR25
, bfd_mach_avr25
},
221 {"attiny13a", AVR_ISA_AVR25
, bfd_mach_avr25
},
222 {"attiny2313", AVR_ISA_AVR25
, bfd_mach_avr25
},
223 {"attiny2313a",AVR_ISA_AVR25
, bfd_mach_avr25
},
224 {"attiny24", AVR_ISA_AVR25
, bfd_mach_avr25
},
225 {"attiny24a", AVR_ISA_AVR25
, bfd_mach_avr25
},
226 {"attiny4313", AVR_ISA_AVR25
, bfd_mach_avr25
},
227 {"attiny44", AVR_ISA_AVR25
, bfd_mach_avr25
},
228 {"attiny44a", AVR_ISA_AVR25
, bfd_mach_avr25
},
229 {"attiny84", AVR_ISA_AVR25
, bfd_mach_avr25
},
230 {"attiny84a", AVR_ISA_AVR25
, bfd_mach_avr25
},
231 {"attiny25", AVR_ISA_AVR25
, bfd_mach_avr25
},
232 {"attiny45", AVR_ISA_AVR25
, bfd_mach_avr25
},
233 {"attiny85", AVR_ISA_AVR25
, bfd_mach_avr25
},
234 {"attiny261", AVR_ISA_AVR25
, bfd_mach_avr25
},
235 {"attiny261a", AVR_ISA_AVR25
, bfd_mach_avr25
},
236 {"attiny461", AVR_ISA_AVR25
, bfd_mach_avr25
},
237 {"attiny461a", AVR_ISA_AVR25
, bfd_mach_avr25
},
238 {"attiny861", AVR_ISA_AVR25
, bfd_mach_avr25
},
239 {"attiny861a", AVR_ISA_AVR25
, bfd_mach_avr25
},
240 {"attiny87", AVR_ISA_AVR25
, bfd_mach_avr25
},
241 {"attiny43u", AVR_ISA_AVR25
, bfd_mach_avr25
},
242 {"attiny48", AVR_ISA_AVR25
, bfd_mach_avr25
},
243 {"attiny88", AVR_ISA_AVR25
, bfd_mach_avr25
},
244 {"attiny828", AVR_ISA_AVR25
, bfd_mach_avr25
},
245 {"at86rf401", AVR_ISA_RF401
, bfd_mach_avr25
},
246 {"at43usb355", AVR_ISA_AVR3
, bfd_mach_avr3
},
247 {"at76c711", AVR_ISA_AVR3
, bfd_mach_avr3
},
248 {"atmega103", AVR_ISA_AVR31
, bfd_mach_avr31
},
249 {"at43usb320", AVR_ISA_AVR31
, bfd_mach_avr31
},
250 {"attiny167", AVR_ISA_AVR35
, bfd_mach_avr35
},
251 {"at90usb82", AVR_ISA_AVR35
, bfd_mach_avr35
},
252 {"at90usb162", AVR_ISA_AVR35
, bfd_mach_avr35
},
253 {"ata5505", AVR_ISA_AVR35
, bfd_mach_avr35
},
254 {"atmega8u2", AVR_ISA_AVR35
, bfd_mach_avr35
},
255 {"atmega16u2", AVR_ISA_AVR35
, bfd_mach_avr35
},
256 {"atmega32u2", AVR_ISA_AVR35
, bfd_mach_avr35
},
257 {"attiny1634", AVR_ISA_AVR35
, bfd_mach_avr35
},
258 {"atmega8", AVR_ISA_M8
, bfd_mach_avr4
},
259 {"ata6289", AVR_ISA_AVR4
, bfd_mach_avr4
},
260 {"atmega8a", AVR_ISA_M8
, bfd_mach_avr4
},
261 {"ata6285", AVR_ISA_AVR4
, bfd_mach_avr4
},
262 {"ata6286", AVR_ISA_AVR4
, bfd_mach_avr4
},
263 {"atmega48", AVR_ISA_AVR4
, bfd_mach_avr4
},
264 {"atmega48a", AVR_ISA_AVR4
, bfd_mach_avr4
},
265 {"atmega48pa", AVR_ISA_AVR4
, bfd_mach_avr4
},
266 {"atmega48p", AVR_ISA_AVR4
, bfd_mach_avr4
},
267 {"atmega88", AVR_ISA_AVR4
, bfd_mach_avr4
},
268 {"atmega88a", AVR_ISA_AVR4
, bfd_mach_avr4
},
269 {"atmega88p", AVR_ISA_AVR4
, bfd_mach_avr4
},
270 {"atmega88pa", AVR_ISA_AVR4
, bfd_mach_avr4
},
271 {"atmega8515", AVR_ISA_M8
, bfd_mach_avr4
},
272 {"atmega8535", AVR_ISA_M8
, bfd_mach_avr4
},
273 {"atmega8hva", AVR_ISA_AVR4
, bfd_mach_avr4
},
274 {"at90pwm1", AVR_ISA_AVR4
, bfd_mach_avr4
},
275 {"at90pwm2", AVR_ISA_AVR4
, bfd_mach_avr4
},
276 {"at90pwm2b", AVR_ISA_AVR4
, bfd_mach_avr4
},
277 {"at90pwm3", AVR_ISA_AVR4
, bfd_mach_avr4
},
278 {"at90pwm3b", AVR_ISA_AVR4
, bfd_mach_avr4
},
279 {"at90pwm81", AVR_ISA_AVR4
, bfd_mach_avr4
},
280 {"at90pwm161", AVR_ISA_AVR5
, bfd_mach_avr5
},
281 {"ata5790", AVR_ISA_AVR5
, bfd_mach_avr5
},
282 {"ata5795", AVR_ISA_AVR5
, bfd_mach_avr5
},
283 {"atmega16", AVR_ISA_AVR5
, bfd_mach_avr5
},
284 {"atmega16a", AVR_ISA_AVR5
, bfd_mach_avr5
},
285 {"atmega161", AVR_ISA_M161
, bfd_mach_avr5
},
286 {"atmega162", AVR_ISA_AVR5
, bfd_mach_avr5
},
287 {"atmega163", AVR_ISA_M161
, bfd_mach_avr5
},
288 {"atmega164a", AVR_ISA_AVR5
, bfd_mach_avr5
},
289 {"atmega164p", AVR_ISA_AVR5
, bfd_mach_avr5
},
290 {"atmega164pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
291 {"atmega165", AVR_ISA_AVR5
, bfd_mach_avr5
},
292 {"atmega165a", AVR_ISA_AVR5
, bfd_mach_avr5
},
293 {"atmega165p", AVR_ISA_AVR5
, bfd_mach_avr5
},
294 {"atmega165pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
295 {"atmega168", AVR_ISA_AVR5
, bfd_mach_avr5
},
296 {"atmega168a", AVR_ISA_AVR5
, bfd_mach_avr5
},
297 {"atmega168p", AVR_ISA_AVR5
, bfd_mach_avr5
},
298 {"atmega168pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
299 {"atmega169", AVR_ISA_AVR5
, bfd_mach_avr5
},
300 {"atmega169a", AVR_ISA_AVR5
, bfd_mach_avr5
},
301 {"atmega169p", AVR_ISA_AVR5
, bfd_mach_avr5
},
302 {"atmega169pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
303 {"atmega32", AVR_ISA_AVR5
, bfd_mach_avr5
},
304 {"atmega32a", AVR_ISA_AVR5
, bfd_mach_avr5
},
305 {"atmega323", AVR_ISA_AVR5
, bfd_mach_avr5
},
306 {"atmega324a", AVR_ISA_AVR5
, bfd_mach_avr5
},
307 {"atmega324p", AVR_ISA_AVR5
, bfd_mach_avr5
},
308 {"atmega324pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
309 {"atmega325", AVR_ISA_AVR5
, bfd_mach_avr5
},
310 {"atmega325a", AVR_ISA_AVR5
, bfd_mach_avr5
},
311 {"atmega325p", AVR_ISA_AVR5
, bfd_mach_avr5
},
312 {"atmega325pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
313 {"atmega3250", AVR_ISA_AVR5
, bfd_mach_avr5
},
314 {"atmega3250a",AVR_ISA_AVR5
, bfd_mach_avr5
},
315 {"atmega3250p",AVR_ISA_AVR5
, bfd_mach_avr5
},
316 {"atmega3250pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
317 {"atmega328", AVR_ISA_AVR5
, bfd_mach_avr5
},
318 {"atmega328p", AVR_ISA_AVR5
, bfd_mach_avr5
},
319 {"atmega329", AVR_ISA_AVR5
, bfd_mach_avr5
},
320 {"atmega329a", AVR_ISA_AVR5
, bfd_mach_avr5
},
321 {"atmega329p", AVR_ISA_AVR5
, bfd_mach_avr5
},
322 {"atmega329pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
323 {"atmega3290", AVR_ISA_AVR5
, bfd_mach_avr5
},
324 {"atmega3290a",AVR_ISA_AVR5
, bfd_mach_avr5
},
325 {"atmega3290p",AVR_ISA_AVR5
, bfd_mach_avr5
},
326 {"atmega3290pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
327 {"atmega406", AVR_ISA_AVR5
, bfd_mach_avr5
},
328 {"atmega64rfr2", AVR_ISA_AVR5
, bfd_mach_avr5
},
329 {"atmega644rfr2",AVR_ISA_AVR5
, bfd_mach_avr5
},
330 {"atmega64", AVR_ISA_AVR5
, bfd_mach_avr5
},
331 {"atmega64a", AVR_ISA_AVR5
, bfd_mach_avr5
},
332 {"atmega640", AVR_ISA_AVR5
, bfd_mach_avr5
},
333 {"atmega644", AVR_ISA_AVR5
, bfd_mach_avr5
},
334 {"atmega644a", AVR_ISA_AVR5
, bfd_mach_avr5
},
335 {"atmega644p", AVR_ISA_AVR5
, bfd_mach_avr5
},
336 {"atmega644pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
337 {"atmega645", AVR_ISA_AVR5
, bfd_mach_avr5
},
338 {"atmega645a", AVR_ISA_AVR5
, bfd_mach_avr5
},
339 {"atmega645p", AVR_ISA_AVR5
, bfd_mach_avr5
},
340 {"atmega649", AVR_ISA_AVR5
, bfd_mach_avr5
},
341 {"atmega649a", AVR_ISA_AVR5
, bfd_mach_avr5
},
342 {"atmega649p", AVR_ISA_AVR5
, bfd_mach_avr5
},
343 {"atmega6450", AVR_ISA_AVR5
, bfd_mach_avr5
},
344 {"atmega6450a",AVR_ISA_AVR5
, bfd_mach_avr5
},
345 {"atmega6450p",AVR_ISA_AVR5
, bfd_mach_avr5
},
346 {"atmega6490", AVR_ISA_AVR5
, bfd_mach_avr5
},
347 {"atmega6490a",AVR_ISA_AVR5
, bfd_mach_avr5
},
348 {"atmega6490p",AVR_ISA_AVR5
, bfd_mach_avr5
},
349 {"atmega64rfr2",AVR_ISA_AVR5
, bfd_mach_avr5
},
350 {"atmega644rfr2",AVR_ISA_AVR5
, bfd_mach_avr5
},
351 {"atmega16hva",AVR_ISA_AVR5
, bfd_mach_avr5
},
352 {"atmega16hva2",AVR_ISA_AVR5
, bfd_mach_avr5
},
353 {"atmega16hvb",AVR_ISA_AVR5
, bfd_mach_avr5
},
354 {"atmega16hvbrevb",AVR_ISA_AVR5
,bfd_mach_avr5
},
355 {"atmega32hvb",AVR_ISA_AVR5
, bfd_mach_avr5
},
356 {"atmega32hvbrevb",AVR_ISA_AVR5
,bfd_mach_avr5
},
357 {"atmega64hve",AVR_ISA_AVR5
, bfd_mach_avr5
},
358 {"at90can32" , AVR_ISA_AVR5
, bfd_mach_avr5
},
359 {"at90can64" , AVR_ISA_AVR5
, bfd_mach_avr5
},
360 {"at90pwm161", AVR_ISA_AVR5
, bfd_mach_avr5
},
361 {"at90pwm216", AVR_ISA_AVR5
, bfd_mach_avr5
},
362 {"at90pwm316", AVR_ISA_AVR5
, bfd_mach_avr5
},
363 {"atmega32c1", AVR_ISA_AVR5
, bfd_mach_avr5
},
364 {"atmega64c1", AVR_ISA_AVR5
, bfd_mach_avr5
},
365 {"atmega16m1", AVR_ISA_AVR5
, bfd_mach_avr5
},
366 {"atmega32m1", AVR_ISA_AVR5
, bfd_mach_avr5
},
367 {"atmega64m1", AVR_ISA_AVR5
, bfd_mach_avr5
},
368 {"atmega16u4", AVR_ISA_AVR5
, bfd_mach_avr5
},
369 {"atmega32u4", AVR_ISA_AVR5
, bfd_mach_avr5
},
370 {"atmega32u6", AVR_ISA_AVR5
, bfd_mach_avr5
},
371 {"at90usb646", AVR_ISA_AVR5
, bfd_mach_avr5
},
372 {"at90usb647", AVR_ISA_AVR5
, bfd_mach_avr5
},
373 {"at90scr100", AVR_ISA_AVR5
, bfd_mach_avr5
},
374 {"at94k", AVR_ISA_94K
, bfd_mach_avr5
},
375 {"m3000", AVR_ISA_AVR5
, bfd_mach_avr5
},
376 {"atmega128", AVR_ISA_AVR51
, bfd_mach_avr51
},
377 {"atmega128a", AVR_ISA_AVR51
, bfd_mach_avr51
},
378 {"atmega1280", AVR_ISA_AVR51
, bfd_mach_avr51
},
379 {"atmega1281", AVR_ISA_AVR51
, bfd_mach_avr51
},
380 {"atmega1284", AVR_ISA_AVR51
, bfd_mach_avr51
},
381 {"atmega1284p",AVR_ISA_AVR51
, bfd_mach_avr51
},
382 {"atmega128rfa1",AVR_ISA_AVR51
, bfd_mach_avr51
},
383 {"atmega128rfr2",AVR_ISA_AVR51
, bfd_mach_avr51
},
384 {"atmega1284rfr2",AVR_ISA_AVR51
, bfd_mach_avr51
},
385 {"at90can128", AVR_ISA_AVR51
, bfd_mach_avr51
},
386 {"at90usb1286",AVR_ISA_AVR51
, bfd_mach_avr51
},
387 {"at90usb1287",AVR_ISA_AVR51
, bfd_mach_avr51
},
388 {"atmega2560", AVR_ISA_AVR6
, bfd_mach_avr6
},
389 {"atmega2561", AVR_ISA_AVR6
, bfd_mach_avr6
},
390 {"atmega256rfr2", AVR_ISA_AVR6
, bfd_mach_avr6
},
391 {"atmega2564rfr2", AVR_ISA_AVR6
, bfd_mach_avr6
},
392 {"atxmega16a4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
393 {"atxmega16a4u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
394 {"atxmega16c4", AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
395 {"atxmega16d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
396 {"atxmega32a4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
397 {"atxmega32a4u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
398 {"atxmega32c4", AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
399 {"atxmega32d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
400 {"atxmega32e5", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
401 {"atxmega16e5", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
402 {"atxmega8e5", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
403 {"atxmega32x1", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
404 {"attiny212", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
405 {"attiny214", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
406 {"attiny412", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
407 {"attiny414", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
408 {"attiny416", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
409 {"attiny417", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
410 {"attiny814", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
411 {"attiny816", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
412 {"attiny817", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
413 {"attiny1614", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
414 {"attiny1616", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
415 {"attiny1617", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
416 {"attiny3214", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
417 {"attiny3216", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
418 {"attiny3217", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
419 {"atxmega64a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
420 {"atxmega64a3u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
421 {"atxmega64a4u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
422 {"atxmega64b1", AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
423 {"atxmega64b3", AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
424 {"atxmega64c3", AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
425 {"atxmega64d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
426 {"atxmega64d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
427 {"atxmega64a1", AVR_ISA_XMEGA
, bfd_mach_avrxmega5
},
428 {"atxmega64a1u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega5
},
429 {"atxmega128a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
430 {"atxmega128a3u",AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
431 {"atxmega128b1", AVR_ISA_XMEGAU
, bfd_mach_avrxmega6
},
432 {"atxmega128b3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
433 {"atxmega128c3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
434 {"atxmega128d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
435 {"atxmega128d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
436 {"atxmega192a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
437 {"atxmega192a3u",AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
438 {"atxmega192c3", AVR_ISA_XMEGAU
, bfd_mach_avrxmega6
},
439 {"atxmega192d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
440 {"atxmega256a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
441 {"atxmega256a3u",AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
442 {"atxmega256a3b",AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
443 {"atxmega256a3bu",AVR_ISA_XMEGAU
, bfd_mach_avrxmega6
},
444 {"atxmega256c3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
445 {"atxmega256d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
446 {"atxmega384c3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
447 {"atxmega384d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
448 {"atxmega128a1", AVR_ISA_XMEGA
, bfd_mach_avrxmega7
},
449 {"atxmega128a1u", AVR_ISA_XMEGAU
, bfd_mach_avrxmega7
},
450 {"atxmega128a4u", AVR_ISA_XMEGAU
, bfd_mach_avrxmega7
},
451 {"attiny4", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
452 {"attiny5", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
453 {"attiny9", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
454 {"attiny10", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
455 {"attiny20", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
456 {"attiny40", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
461 /* Current MCU type. */
462 static struct mcu_type_s default_mcu
= {"avr2", AVR_ISA_AVR2
, bfd_mach_avr2
};
463 static struct mcu_type_s specified_mcu
;
464 static struct mcu_type_s
* avr_mcu
= & default_mcu
;
466 /* AVR target-specific switches. */
469 int all_opcodes
; /* -mall-opcodes: accept all known AVR opcodes. */
470 int no_skip_bug
; /* -mno-skip-bug: no warnings for skipping 2-word insns. */
471 int no_wrap
; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */
472 int no_link_relax
; /* -mno-link-relax / -mlink-relax: generate (or not)
473 relocations for linker relaxation. */
474 int have_gccisr
; /* Whether "__gcc_isr" is a known (pseudo) insn. */
477 static struct avr_opt_s avr_opt
= { 0, 0, 0, 0, 0 };
479 const char EXP_CHARS
[] = "eE";
480 const char FLT_CHARS
[] = "dD";
482 static void avr_set_arch (int);
484 /* The target specific pseudo-ops which we support. */
485 const pseudo_typeS md_pseudo_table
[] =
487 {"arch", avr_set_arch
, 0},
491 #define LDI_IMMEDIATE(x) (((x) & 0xf) | (((x) << 4) & 0xf00))
493 #define EXP_MOD_NAME(i) exp_mod[i].name
494 #define EXP_MOD_RELOC(i) exp_mod[i].reloc
495 #define EXP_MOD_NEG_RELOC(i) exp_mod[i].neg_reloc
496 #define HAVE_PM_P(i) exp_mod[i].have_pm
501 bfd_reloc_code_real_type reloc
;
502 bfd_reloc_code_real_type neg_reloc
;
506 static struct exp_mod_s exp_mod
[] =
508 {"hh8", BFD_RELOC_AVR_HH8_LDI
, BFD_RELOC_AVR_HH8_LDI_NEG
, 1},
509 {"pm_hh8", BFD_RELOC_AVR_HH8_LDI_PM
, BFD_RELOC_AVR_HH8_LDI_PM_NEG
, 0},
510 {"hi8", BFD_RELOC_AVR_HI8_LDI
, BFD_RELOC_AVR_HI8_LDI_NEG
, 1},
511 {"pm_hi8", BFD_RELOC_AVR_HI8_LDI_PM
, BFD_RELOC_AVR_HI8_LDI_PM_NEG
, 0},
512 {"lo8", BFD_RELOC_AVR_LO8_LDI
, BFD_RELOC_AVR_LO8_LDI_NEG
, 1},
513 {"pm_lo8", BFD_RELOC_AVR_LO8_LDI_PM
, BFD_RELOC_AVR_LO8_LDI_PM_NEG
, 0},
514 {"hlo8", BFD_RELOC_AVR_HH8_LDI
, BFD_RELOC_AVR_HH8_LDI_NEG
, 0},
515 {"hhi8", BFD_RELOC_AVR_MS8_LDI
, BFD_RELOC_AVR_MS8_LDI_NEG
, 0},
518 /* A union used to store indices into the exp_mod[] array
519 in a hash table which expects void * data types. */
526 /* Opcode hash table. */
527 static htab_t avr_hash
;
529 /* Reloc modifiers hash control (hh8,hi8,lo8,pm_xx). */
530 static htab_t avr_mod_hash
;
532 /* Whether some opcode does not change SREG. */
533 static htab_t avr_no_sreg_hash
;
535 static const char* const avr_no_sreg
[] =
538 "ldi", "swap", "mov", "movw",
539 /* Special instructions. I-Flag will be restored by RETI, and we don't
540 consider I-Flag as being clobbered when changed. */
541 "sei", "cli", "reti", "brie", "brid",
542 "nop", "wdr", "sleep",
544 "ld", "ldd", "lds", "pop", "in", "lpm", "elpm",
545 "st", "std", "sts", "push", "out",
546 /* Jumps and Calls. Calls might call code that changes SREG.
547 GCC has to filter out ABI calls. The non-ABI transparent calls
548 must use [R]CALL and are filtered out now by not mentioning them. */
549 "rjmp", "jmp", "ijmp", "ret",
550 /* Skipping. Branches need SREG to be set, hence we regard them
551 as if they changed SREG and don't list them here. */
552 "sbrc", "sbrs", "sbic", "sbis", "cpse",
553 /* I/O Manipulation */
555 /* Read-Modify-Write */
556 "lac", "las", "lat", "xch"
559 #define OPTION_MMCU 'm'
562 OPTION_ALL_OPCODES
= OPTION_MD_BASE
+ 1,
567 OPTION_NO_LINK_RELAX
,
571 struct option md_longopts
[] =
573 { "mmcu", required_argument
, NULL
, OPTION_MMCU
},
574 { "mall-opcodes", no_argument
, NULL
, OPTION_ALL_OPCODES
},
575 { "mno-skip-bug", no_argument
, NULL
, OPTION_NO_SKIP_BUG
},
576 { "mno-wrap", no_argument
, NULL
, OPTION_NO_WRAP
},
577 { "mrmw", no_argument
, NULL
, OPTION_ISA_RMW
},
578 { "mlink-relax", no_argument
, NULL
, OPTION_LINK_RELAX
},
579 { "mno-link-relax", no_argument
, NULL
, OPTION_NO_LINK_RELAX
},
580 { "mgcc-isr", no_argument
, NULL
, OPTION_HAVE_GCCISR
},
581 { NULL
, no_argument
, NULL
, 0 }
584 size_t md_longopts_size
= sizeof (md_longopts
);
586 /* Display nicely formatted list of known MCU names. */
589 show_mcu_list (FILE *stream
)
593 fprintf (stream
, _("Known MCU names:"));
596 for (i
= 0; mcu_types
[i
].name
; i
++)
598 int len
= strlen (mcu_types
[i
].name
);
603 fprintf (stream
, " %s", mcu_types
[i
].name
);
606 fprintf (stream
, "\n %s", mcu_types
[i
].name
);
611 fprintf (stream
, "\n");
617 while (*s
== ' ' || *s
== '\t')
622 /* Extract one word from FROM and copy it to TO. */
625 extract_word (char *from
, char *to
, int limit
)
630 /* Drop leading whitespace. */
631 from
= skip_space (from
);
634 /* Find the op code end. */
635 for (op_end
= from
; *op_end
!= 0 && is_part_of_name (*op_end
);)
637 to
[size
++] = *op_end
++;
638 if (size
+ 1 >= limit
)
647 md_estimate_size_before_relax (fragS
*fragp ATTRIBUTE_UNUSED
,
648 asection
*seg ATTRIBUTE_UNUSED
)
655 md_show_usage (FILE *stream
)
658 _("AVR Assembler options:\n"
659 " -mmcu=[avr-name] select microcontroller variant\n"
660 " [avr-name] can be:\n"
661 " avr1 - classic AVR core without data RAM\n"
662 " avr2 - classic AVR core with up to 8K program memory\n"
663 " avr25 - classic AVR core with up to 8K program memory\n"
664 " plus the MOVW instruction\n"
665 " avr3 - classic AVR core with up to 64K program memory\n"
666 " avr31 - classic AVR core with up to 128K program memory\n"
667 " avr35 - classic AVR core with up to 64K program memory\n"
668 " plus the MOVW instruction\n"
669 " avr4 - enhanced AVR core with up to 8K program memory\n"
670 " avr5 - enhanced AVR core with up to 64K program memory\n"
671 " avr51 - enhanced AVR core with up to 128K program memory\n"
672 " avr6 - enhanced AVR core with up to 256K program memory\n"
673 " avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM\n"
674 " avrxmega3 - XMEGA, RAM + FLASH < 64K, Flash visible in RAM\n"
675 " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n"
676 " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
677 " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
678 " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
679 " avrtiny - AVR Tiny core with 16 gp registers\n"));
681 _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
682 " -mno-skip-bug disable warnings for skipping two-word instructions\n"
683 " (default for avr4, avr5)\n"
684 " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n"
685 " (default for avr3, avr5)\n"
686 " -mrmw accept Read-Modify-Write instructions\n"
687 " -mlink-relax generate relocations for linker relaxation (default)\n"
688 " -mno-link-relax don't generate relocations for linker relaxation.\n"
689 " -mgcc-isr accept the __gcc_isr pseudo-instruction.\n"
691 show_mcu_list (stream
);
695 avr_set_arch (int dummy ATTRIBUTE_UNUSED
)
699 input_line_pointer
= extract_word (input_line_pointer
, str
, 20);
700 md_parse_option (OPTION_MMCU
, str
);
701 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, avr_mcu
->mach
);
705 md_parse_option (int c
, const char *arg
)
713 for (i
= 0; mcu_types
[i
].name
; ++i
)
714 if (strcasecmp (mcu_types
[i
].name
, arg
) == 0)
717 if (!mcu_types
[i
].name
)
719 show_mcu_list (stderr
);
720 as_fatal (_("unknown MCU: %s\n"), arg
);
723 /* It is OK to redefine mcu type within the same avr[1-5] bfd machine
724 type - this for allows passing -mmcu=... via gcc ASM_SPEC as well
725 as .arch ... in the asm output at the same time. */
726 if (avr_mcu
== &default_mcu
|| avr_mcu
->mach
== mcu_types
[i
].mach
)
728 specified_mcu
.name
= mcu_types
[i
].name
;
729 specified_mcu
.isa
|= mcu_types
[i
].isa
;
730 specified_mcu
.mach
= mcu_types
[i
].mach
;
731 avr_mcu
= &specified_mcu
;
734 as_fatal (_("redefinition of mcu type `%s' to `%s'"),
735 avr_mcu
->name
, mcu_types
[i
].name
);
738 case OPTION_ALL_OPCODES
:
739 avr_opt
.all_opcodes
= 1;
741 case OPTION_NO_SKIP_BUG
:
742 avr_opt
.no_skip_bug
= 1;
748 specified_mcu
.isa
|= AVR_ISA_RMW
;
750 case OPTION_LINK_RELAX
:
751 avr_opt
.no_link_relax
= 0;
753 case OPTION_NO_LINK_RELAX
:
754 avr_opt
.no_link_relax
= 1;
756 case OPTION_HAVE_GCCISR
:
757 avr_opt
.have_gccisr
= 1;
765 /* Implement `md_undefined_symbol' */
766 /* If we are in `__gcc_isr' chunk, pop up `__gcc_isr.n_pushed.<NUM>'
767 instead of `__gcc_isr.n_pushed'. This will be resolved by the Done
768 chunk in `avr_patch_gccisr_frag' to the number of PUSHes produced by
769 the Prologue chunk. */
772 avr_undefined_symbol (char *name
)
774 if (ISR_CHUNK_Done
!= avr_isr
.prev_chunk
775 && 0 == strcmp (name
, "__gcc_isr.n_pushed"))
777 if (!avr_isr
.sym_n_pushed
)
779 static unsigned suffix
;
781 sprintf (xname
, "%s.%03u", name
, (++suffix
) % 1000);
782 avr_isr
.sym_n_pushed
= symbol_new (xname
, undefined_section
,
783 &zero_address_frag
, (valueT
) 0);
785 return avr_isr
.sym_n_pushed
;
792 md_atof (int type
, char *litP
, int *sizeP
)
794 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
798 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
799 asection
*sec ATTRIBUTE_UNUSED
,
800 fragS
*fragP ATTRIBUTE_UNUSED
)
809 struct avr_opcodes_s
*opcode
;
811 avr_hash
= str_htab_create ();
813 /* Insert unique names into hash table. This hash table then provides a
814 quick index to the first opcode with a particular name in the opcode
816 for (opcode
= avr_opcodes
; opcode
->name
; opcode
++)
817 if (str_hash_find (avr_hash
, opcode
->name
) == NULL
)
818 str_hash_insert (avr_hash
, opcode
->name
, (char *) opcode
);
820 avr_mod_hash
= str_htab_create ();
822 for (i
= 0; i
< ARRAY_SIZE (exp_mod
); ++i
)
827 str_hash_find (avr_mod_hash
, EXP_MOD_NAME (i
));
828 str_hash_insert (avr_mod_hash
, EXP_MOD_NAME (i
), m
.ptr
);
831 avr_no_sreg_hash
= str_htab_create ();
833 for (i
= 0; i
< ARRAY_SIZE (avr_no_sreg
); ++i
)
835 gas_assert (str_hash_find (avr_hash
, avr_no_sreg
[i
]));
836 str_hash_insert (avr_no_sreg_hash
, avr_no_sreg
[i
], (char*) 4 /* dummy */);
839 avr_gccisr_opcode
= (struct avr_opcodes_s
*) str_hash_find (avr_hash
, "__gcc_isr");
840 gas_assert (avr_gccisr_opcode
);
842 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, avr_mcu
->mach
);
843 linkrelax
= !avr_opt
.no_link_relax
;
846 /* Resolve STR as a constant expression and return the result.
847 If result greater than MAX then error. */
850 avr_get_constant (char *str
, int max
)
854 str
= skip_space (str
);
855 input_line_pointer
= str
;
858 if (ex
.X_op
!= O_constant
)
859 as_bad (_("constant value required"));
861 if (ex
.X_add_number
> max
|| ex
.X_add_number
< 0)
862 as_bad (_("number must be positive and less than %d"), max
+ 1);
864 return ex
.X_add_number
;
867 /* Parse for ldd/std offset. */
870 avr_offset_expression (expressionS
*exp
)
872 char *str
= input_line_pointer
;
877 str
= extract_word (str
, op
, sizeof (op
));
879 input_line_pointer
= tmp
;
882 /* Warn about expressions that fail to use lo8 (). */
883 if (exp
->X_op
== O_constant
)
885 int x
= exp
->X_add_number
;
887 if (x
< -255 || x
> 255)
888 as_warn (_("constant out of 8-bit range: %d"), x
);
892 /* Parse ordinary expression. */
895 parse_exp (char *s
, expressionS
*op
)
897 input_line_pointer
= s
;
899 if (op
->X_op
== O_absent
)
900 as_bad (_("missing operand"));
901 return input_line_pointer
;
904 /* Parse special expressions (needed for LDI command):
909 where xx is: hh, hi, lo. */
911 static bfd_reloc_code_real_type
912 avr_ldi_expression (expressionS
*exp
)
914 char *str
= input_line_pointer
;
918 int linker_stubs_should_be_generated
= 0;
922 str
= extract_word (str
, op
, sizeof (op
));
928 m
.ptr
= str_hash_find (avr_mod_hash
, op
);
936 str
= skip_space (str
);
940 bfd_reloc_code_real_type reloc_to_return
;
945 if (strncmp ("pm(", str
, 3) == 0
946 || strncmp ("gs(",str
,3) == 0
947 || strncmp ("-(gs(",str
,5) == 0
948 || strncmp ("-(pm(", str
, 5) == 0)
956 as_bad (_("illegal expression"));
958 if (str
[0] == 'g' || str
[2] == 'g')
959 linker_stubs_should_be_generated
= 1;
971 if (*str
== '-' && *(str
+ 1) == '(')
978 input_line_pointer
= str
;
983 if (*input_line_pointer
!= ')')
985 as_bad (_("`)' required"));
988 input_line_pointer
++;
993 neg_p
? EXP_MOD_NEG_RELOC (mod
) : EXP_MOD_RELOC (mod
);
994 if (linker_stubs_should_be_generated
)
996 switch (reloc_to_return
)
998 case BFD_RELOC_AVR_LO8_LDI_PM
:
999 reloc_to_return
= BFD_RELOC_AVR_LO8_LDI_GS
;
1001 case BFD_RELOC_AVR_HI8_LDI_PM
:
1002 reloc_to_return
= BFD_RELOC_AVR_HI8_LDI_GS
;
1006 /* PR 5523: Do not generate a warning here,
1007 legitimate code can trigger this case. */
1011 return reloc_to_return
;
1016 input_line_pointer
= tmp
;
1019 /* Warn about expressions that fail to use lo8 (). */
1020 if (exp
->X_op
== O_constant
)
1022 int x
= exp
->X_add_number
;
1024 if (x
< -255 || x
> 255)
1025 as_warn (_("constant out of 8-bit range: %d"), x
);
1028 return BFD_RELOC_AVR_LDI
;
1031 /* Parse one instruction operand.
1032 Return operand bitmask. Also fixups can be generated. */
1035 avr_operand (struct avr_opcodes_s
*opcode
,
1041 expressionS op_expr
;
1042 unsigned int op_mask
= 0;
1043 char *str
= skip_space (*line
);
1047 /* Any register operand. */
1054 char * old_str
= str
;
1058 str
= extract_word (str
, r_name
, sizeof (r_name
));
1059 for (lower
= r_name
; *lower
; ++lower
)
1061 if (*lower
>= 'A' && *lower
<= 'Z')
1062 *lower
+= 'a' - 'A';
1065 if (r_name
[0] == 'r' && ISDIGIT (r_name
[1]) && r_name
[2] == 0)
1066 /* Single-digit register number, ie r0-r9. */
1067 op_mask
= r_name
[1] - '0';
1068 else if (r_name
[0] == 'r' && ISDIGIT (r_name
[1])
1069 && ISDIGIT (r_name
[2]) && r_name
[3] == 0)
1070 /* Double-digit register number, ie r10 - r32. */
1071 op_mask
= (r_name
[1] - '0') * 10 + r_name
[2] - '0';
1072 else if (r_name
[0] >= 'x' && r_name
[0] <= 'z'
1073 && (r_name
[1] == 'l' || r_name
[1] == 'h') && r_name
[2] == 0)
1074 /* Registers r26-r31 referred to by name, ie xl, xh, yl, yh, zl, zh. */
1075 op_mask
= (r_name
[0] - 'x') * 2 + (r_name
[1] == 'h') + 26;
1076 else if ((*op
== 'v' || *op
== 'w')
1077 && r_name
[0] >= 'x' && r_name
[0] <= 'z' && r_name
[1] == 0)
1078 /* For the movw and addiw instructions, refer to registers x, y and z by name. */
1079 op_mask
= (r_name
[0] - 'x') * 2 + 26;
1082 /* Numeric or symbolic constant register number. */
1083 op_mask
= avr_get_constant (old_str
, 31);
1084 str
= input_line_pointer
;
1091 if (avr_mcu
->mach
== bfd_mach_avrtiny
)
1093 if (op_mask
< 16 || op_mask
> 31)
1095 as_bad (_("register name or number from 16 to 31 required"));
1099 else if (op_mask
> 31)
1101 as_bad (_("register name or number from 0 to 31 required"));
1108 if (op_mask
< 16 || op_mask
> 23)
1109 as_bad (_("register r16-r23 required"));
1115 as_bad (_("register number above 15 required"));
1121 as_bad (_("even register number required"));
1126 if ((op_mask
& 1) || op_mask
< 24)
1127 as_bad (_("register r24, r26, r28 or r30 required"));
1128 op_mask
= (op_mask
- 24) >> 1;
1139 str
= skip_space (str
+ 1);
1148 as_bad (_("pointer register (X, Y or Z) required"));
1150 str
= skip_space (str
+ 1);
1155 as_bad (_("cannot both predecrement and postincrement"));
1159 /* avr1 can do "ld r,Z" and "st Z,r" but no other pointer
1160 registers, no predecrement, no postincrement. */
1161 if (!avr_opt
.all_opcodes
&& (op_mask
& 0x100F)
1162 && !(avr_mcu
->isa
& AVR_ISA_SRAM
))
1163 as_bad (_("addressing mode not supported"));
1169 as_bad (_("can't predecrement"));
1171 if (! (*str
== 'z' || *str
== 'Z'))
1172 as_bad (_("pointer register Z required"));
1174 str
= skip_space (str
+ 1);
1180 for (s
= opcode
->opcode
; *s
; ++s
)
1183 op_mask
|= (1 << (15 - (s
- opcode
->opcode
)));
1187 /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */
1188 if (!avr_opt
.all_opcodes
1189 && (op_mask
& 0x0001)
1190 && !(avr_mcu
->isa
& AVR_ISA_MOVW
))
1191 as_bad (_("postincrement not supported"));
1196 char c
= TOLOWER (*str
++);
1201 as_bad (_("pointer register (Y or Z) required"));
1202 str
= skip_space (str
);
1205 input_line_pointer
= str
;
1206 avr_offset_expression (& op_expr
);
1207 str
= input_line_pointer
;
1208 fix_new_exp (frag_now
, where
, 3,
1209 &op_expr
, FALSE
, BFD_RELOC_AVR_6
);
1215 str
= parse_exp (str
, &op_expr
);
1216 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1217 &op_expr
, FALSE
, BFD_RELOC_AVR_CALL
);
1221 str
= parse_exp (str
, &op_expr
);
1222 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1223 &op_expr
, TRUE
, BFD_RELOC_AVR_13_PCREL
);
1227 str
= parse_exp (str
, &op_expr
);
1228 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1229 &op_expr
, TRUE
, BFD_RELOC_AVR_7_PCREL
);
1233 str
= parse_exp (str
, &op_expr
);
1234 fix_new_exp (frag_now
, where
+ 2, opcode
->insn_size
* 2,
1235 &op_expr
, FALSE
, BFD_RELOC_16
);
1239 str
= parse_exp (str
, &op_expr
);
1240 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1241 &op_expr
, FALSE
, BFD_RELOC_AVR_LDS_STS_16
);
1246 bfd_reloc_code_real_type r_type
;
1248 input_line_pointer
= str
;
1249 r_type
= avr_ldi_expression (&op_expr
);
1250 str
= input_line_pointer
;
1251 fix_new_exp (frag_now
, where
, 3,
1252 &op_expr
, FALSE
, r_type
);
1260 x
= ~avr_get_constant (str
, 255);
1261 str
= input_line_pointer
;
1262 op_mask
|= (x
& 0xf) | ((x
<< 4) & 0xf00);
1270 x
= avr_get_constant (str
, 255);
1271 str
= input_line_pointer
;
1277 input_line_pointer
= str
;
1278 avr_offset_expression (& op_expr
);
1279 str
= input_line_pointer
;
1280 fix_new_exp (frag_now
, where
, 3,
1281 & op_expr
, FALSE
, BFD_RELOC_AVR_6_ADIW
);
1289 x
= avr_get_constant (str
, 7);
1290 str
= input_line_pointer
;
1298 str
= parse_exp (str
, &op_expr
);
1299 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1300 &op_expr
, FALSE
, BFD_RELOC_AVR_PORT6
);
1304 str
= parse_exp (str
, &op_expr
);
1305 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1306 &op_expr
, FALSE
, BFD_RELOC_AVR_PORT5
);
1313 x
= avr_get_constant (str
, 15);
1314 str
= input_line_pointer
;
1315 op_mask
|= (x
<< 4);
1323 as_bad (_("unknown constraint `%c'"), *op
);
1330 /* TC_FRAG_INIT hook */
1333 avr_frag_init (fragS
*frag
)
1335 memset (& frag
->tc_frag_data
, 0, sizeof frag
->tc_frag_data
);
1339 /* Parse instruction operands.
1340 Return binary opcode. */
1343 avr_operands (struct avr_opcodes_s
*opcode
, char **line
)
1345 const char *op
= opcode
->constraints
;
1346 unsigned int bin
= opcode
->bin_opcode
;
1347 char *frag
= frag_more (opcode
->insn_size
* 2);
1349 int where
= frag
- frag_now
->fr_literal
;
1353 /* Opcode have operands. */
1356 unsigned int reg1
= 0;
1357 unsigned int reg2
= 0;
1358 int reg1_present
= 0;
1359 int reg2_present
= 0;
1361 /* Parse first operand. */
1362 if (REGISTER_P (*op
))
1364 reg1
= avr_operand (opcode
, where
, op
, &str
, ®no1
);
1367 /* Parse second operand. */
1381 if (REGISTER_P (*op
))
1384 str
= skip_space (str
);
1386 as_bad (_("`,' required"));
1387 str
= skip_space (str
);
1389 reg2
= avr_operand (opcode
, where
, op
, &str
, ®no2
);
1392 if (reg1_present
&& reg2_present
)
1393 reg2
= (reg2
& 0xf) | ((reg2
<< 5) & 0x200);
1394 else if (reg2_present
)
1402 if (avr_opt
.have_gccisr
)
1403 avr_update_gccisr (opcode
, regno1
, regno2
);
1405 /* Detect undefined combinations (like ld r31,Z+). */
1406 if (!avr_opt
.all_opcodes
&& AVR_UNDEF_P (bin
))
1407 as_warn (_("undefined combination of operands"));
1409 if (opcode
->insn_size
== 2)
1411 /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs
1412 (AVR core bug, fixed in the newer devices). */
1413 if (!(avr_opt
.no_skip_bug
||
1414 (avr_mcu
->isa
& (AVR_ISA_MUL
| AVR_ISA_MOVW
)))
1415 && AVR_SKIP_P (frag_now
->tc_frag_data
.prev_opcode
))
1416 as_warn (_("skipping two-word instruction"));
1418 bfd_putl32 ((bfd_vma
) bin
, frag
);
1421 bfd_putl16 ((bfd_vma
) bin
, frag
);
1423 frag_now
->tc_frag_data
.prev_opcode
= bin
;
1428 /* GAS will call this function for each section at the end of the assembly,
1429 to permit the CPU backend to adjust the alignment of a section. */
1432 md_section_align (asection
*seg
, valueT addr
)
1434 int align
= bfd_section_alignment (seg
);
1435 return ((addr
+ (1 << align
) - 1) & (-1UL << align
));
1438 /* If you define this macro, it should return the offset between the
1439 address of a PC relative fixup and the position from which the PC
1440 relative adjustment should be made. On many processors, the base
1441 of a PC relative instruction is the next instruction, so this
1442 macro would return the length of an instruction. */
1445 md_pcrel_from_section (fixS
*fixp
, segT sec
)
1447 if (fixp
->fx_addsy
!= (symbolS
*) NULL
1448 && (!S_IS_DEFINED (fixp
->fx_addsy
)
1449 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1452 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1456 relaxable_section (asection
*sec
)
1458 return ((sec
->flags
& SEC_DEBUGGING
) == 0
1459 && (sec
->flags
& SEC_CODE
) != 0
1460 && (sec
->flags
& SEC_ALLOC
) != 0);
1463 /* Does whatever the xtensa port does. */
1465 avr_validate_fix_sub (fixS
*fix
)
1467 segT add_symbol_segment
, sub_symbol_segment
;
1469 /* The difference of two symbols should be resolved by the assembler when
1470 linkrelax is not set. If the linker may relax the section containing
1471 the symbols, then an Xtensa DIFF relocation must be generated so that
1472 the linker knows to adjust the difference value. */
1473 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
1476 /* Make sure both symbols are in the same segment, and that segment is
1477 "normal" and relaxable. If the segment is not "normal", then the
1478 fix is not valid. If the segment is not "relaxable", then the fix
1479 should have been handled earlier. */
1480 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
1481 if (! SEG_NORMAL (add_symbol_segment
) ||
1482 ! relaxable_section (add_symbol_segment
))
1485 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
1486 return (sub_symbol_segment
== add_symbol_segment
);
1489 /* TC_FORCE_RELOCATION hook */
1491 /* If linkrelax is turned on, and the symbol to relocate
1492 against is in a relaxable segment, don't compute the value -
1493 generate a relocation instead. */
1495 avr_force_relocation (fixS
*fix
)
1497 if (linkrelax
&& fix
->fx_addsy
1498 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
1501 return generic_force_reloc (fix
);
1504 /* GAS will call this for each fixup. It should store the correct
1505 value in the object file. */
1508 md_apply_fix (fixS
*fixP
, valueT
* valP
, segT seg
)
1510 unsigned char *where
;
1514 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
1517 else if (fixP
->fx_pcrel
)
1519 segT s
= S_GET_SEGMENT (fixP
->fx_addsy
);
1521 if (s
== seg
|| s
== absolute_section
)
1523 value
+= S_GET_VALUE (fixP
->fx_addsy
);
1527 else if (linkrelax
&& fixP
->fx_subsy
)
1529 /* For a subtraction relocation expression, generate one
1530 of the DIFF relocs, with the value being the difference.
1531 Note that a sym1 - sym2 expression is adjusted into a
1532 section_start_sym + sym4_offset_from_section_start - sym1
1533 expression. fixP->fx_addsy holds the section start symbol,
1534 fixP->fx_offset holds sym2's offset, and fixP->fx_subsy
1535 holds sym1. Calculate the current difference and write value,
1536 but leave fx_offset as is - during relaxation,
1537 fx_offset - value gives sym1's value. */
1539 switch (fixP
->fx_r_type
)
1542 fixP
->fx_r_type
= BFD_RELOC_AVR_DIFF8
;
1545 fixP
->fx_r_type
= BFD_RELOC_AVR_DIFF16
;
1548 fixP
->fx_r_type
= BFD_RELOC_AVR_DIFF32
;
1551 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
1555 value
= S_GET_VALUE (fixP
->fx_addsy
) +
1556 fixP
->fx_offset
- S_GET_VALUE (fixP
->fx_subsy
);
1559 fixP
->fx_subsy
= NULL
;
1561 /* We don't actually support subtracting a symbol. */
1562 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
1563 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
1565 /* For the DIFF relocs, write the value into the object file while still
1566 keeping fx_done FALSE, as both the difference (recorded in the object file)
1567 and the sym offset (part of fixP) are needed at link relax time. */
1568 where
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
1569 switch (fixP
->fx_r_type
)
1572 fixP
->fx_no_overflow
= 1;
1574 case BFD_RELOC_AVR_7_PCREL
:
1575 case BFD_RELOC_AVR_13_PCREL
:
1579 case BFD_RELOC_AVR_DIFF8
:
1582 case BFD_RELOC_AVR_DIFF16
:
1583 bfd_putl16 ((bfd_vma
) value
, where
);
1585 case BFD_RELOC_AVR_DIFF32
:
1586 bfd_putl32 ((bfd_vma
) value
, where
);
1588 case BFD_RELOC_AVR_CALL
:
1594 /* Fetch the instruction, insert the fully resolved operand
1595 value, and stuff the instruction back again. */
1596 where
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
1597 insn
= bfd_getl16 (where
);
1599 switch (fixP
->fx_r_type
)
1601 case BFD_RELOC_AVR_7_PCREL
:
1603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1604 _("odd address operand: %ld"), value
);
1606 /* Instruction addresses are always right-shifted by 1. */
1608 --value
; /* Correct PC. */
1610 if (value
< -64 || value
> 63)
1611 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1612 _("operand out of range: %ld"), value
);
1613 value
= (value
<< 3) & 0x3f8;
1614 bfd_putl16 ((bfd_vma
) (value
| insn
), where
);
1617 case BFD_RELOC_AVR_13_PCREL
:
1619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1620 _("odd address operand: %ld"), value
);
1622 /* Instruction addresses are always right-shifted by 1. */
1624 --value
; /* Correct PC. */
1626 if (value
< -2048 || value
> 2047)
1628 /* No wrap for devices with >8K of program memory. */
1629 if ((avr_mcu
->isa
& AVR_ISA_MEGA
) || avr_opt
.no_wrap
)
1630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1631 _("operand out of range: %ld"), value
);
1635 bfd_putl16 ((bfd_vma
) (value
| insn
), where
);
1639 bfd_putl32 ((bfd_vma
) value
, where
);
1643 bfd_putl16 ((bfd_vma
) value
, where
);
1647 if (value
> 255 || value
< -128)
1648 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
1649 _("operand out of range: %ld"), value
);
1653 case BFD_RELOC_AVR_16_PM
:
1654 bfd_putl16 ((bfd_vma
) (value
>> 1), where
);
1657 case BFD_RELOC_AVR_LDI
:
1659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1660 _("operand out of range: %ld"), value
);
1661 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
), where
);
1664 case BFD_RELOC_AVR_LDS_STS_16
:
1665 if ((value
< 0x40) || (value
> 0xBF))
1666 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
1667 _("operand out of range: 0x%lx"),
1668 (unsigned long)value
);
1669 insn
|= ((value
& 0xF) | ((value
& 0x30) << 5) | ((value
& 0x40) << 2));
1670 bfd_putl16 ((bfd_vma
) insn
, where
);
1673 case BFD_RELOC_AVR_6
:
1674 if ((value
> 63) || (value
< 0))
1675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1676 _("operand out of range: %ld"), value
);
1677 bfd_putl16 ((bfd_vma
) insn
| ((value
& 7) | ((value
& (3 << 3)) << 7)
1678 | ((value
& (1 << 5)) << 8)), where
);
1681 case BFD_RELOC_AVR_6_ADIW
:
1682 if ((value
> 63) || (value
< 0))
1683 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1684 _("operand out of range: %ld"), value
);
1685 bfd_putl16 ((bfd_vma
) insn
| (value
& 0xf) | ((value
& 0x30) << 2), where
);
1688 case BFD_RELOC_AVR_LO8_LDI
:
1689 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
), where
);
1692 case BFD_RELOC_AVR_HI8_LDI
:
1693 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 8), where
);
1696 case BFD_RELOC_AVR_MS8_LDI
:
1697 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 24), where
);
1700 case BFD_RELOC_AVR_HH8_LDI
:
1701 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 16), where
);
1704 case BFD_RELOC_AVR_LO8_LDI_NEG
:
1705 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
), where
);
1708 case BFD_RELOC_AVR_HI8_LDI_NEG
:
1709 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 8), where
);
1712 case BFD_RELOC_AVR_MS8_LDI_NEG
:
1713 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 24), where
);
1716 case BFD_RELOC_AVR_HH8_LDI_NEG
:
1717 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 16), where
);
1720 case BFD_RELOC_AVR_LO8_LDI_PM
:
1721 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 1), where
);
1724 case BFD_RELOC_AVR_HI8_LDI_PM
:
1725 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 9), where
);
1728 case BFD_RELOC_AVR_HH8_LDI_PM
:
1729 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 17), where
);
1732 case BFD_RELOC_AVR_LO8_LDI_PM_NEG
:
1733 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 1), where
);
1736 case BFD_RELOC_AVR_HI8_LDI_PM_NEG
:
1737 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 9), where
);
1740 case BFD_RELOC_AVR_HH8_LDI_PM_NEG
:
1741 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 17), where
);
1744 case BFD_RELOC_AVR_CALL
:
1748 x
= bfd_getl16 (where
);
1750 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1751 _("odd address operand: %ld"), value
);
1753 x
|= ((value
& 0x10000) | ((value
<< 3) & 0x1f00000)) >> 16;
1754 bfd_putl16 ((bfd_vma
) x
, where
);
1755 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
1759 case BFD_RELOC_AVR_8_LO
:
1760 *where
= 0xff & value
;
1763 case BFD_RELOC_AVR_8_HI
:
1764 *where
= 0xff & (value
>> 8);
1767 case BFD_RELOC_AVR_8_HLO
:
1768 *where
= 0xff & (value
>> 16);
1772 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1773 fixP
->fx_line
, fixP
->fx_r_type
);
1776 case BFD_RELOC_AVR_PORT6
:
1778 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1779 _("operand out of range: %ld"), value
);
1780 bfd_putl16 ((bfd_vma
) insn
| ((value
& 0x30) << 5) | (value
& 0x0f), where
);
1783 case BFD_RELOC_AVR_PORT5
:
1785 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1786 _("operand out of range: %ld"), value
);
1787 bfd_putl16 ((bfd_vma
) insn
| ((value
& 0x1f) << 3), where
);
1793 switch ((int) fixP
->fx_r_type
)
1795 case -BFD_RELOC_AVR_HI8_LDI_NEG
:
1796 case -BFD_RELOC_AVR_HI8_LDI
:
1797 case -BFD_RELOC_AVR_LO8_LDI_NEG
:
1798 case -BFD_RELOC_AVR_LO8_LDI
:
1799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1800 _("only constant expression allowed"));
1809 /* GAS will call this to generate a reloc, passing the resulting reloc
1810 to `bfd_install_relocation'. This currently works poorly, as
1811 `bfd_install_relocation' often does the wrong thing, and instances of
1812 `tc_gen_reloc' have been written to work around the problems, which
1813 in turns makes it difficult to fix `bfd_install_relocation'. */
1815 /* If while processing a fixup, a reloc really needs to be created
1816 then it is done here. */
1819 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
,
1823 bfd_reloc_code_real_type code
= fixp
->fx_r_type
;
1825 if (fixp
->fx_subsy
!= NULL
)
1827 as_bad_where (fixp
->fx_file
, fixp
->fx_line
, _("expression too complex"));
1831 reloc
= XNEW (arelent
);
1833 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
1834 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1836 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1838 if ((fixp
->fx_r_type
== BFD_RELOC_32
) && (fixp
->fx_pcrel
))
1840 if (seg
->use_rela_p
)
1841 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, seg
);
1843 fixp
->fx_offset
= reloc
->address
;
1845 code
= BFD_RELOC_32_PCREL
;
1848 reloc
->addend
= fixp
->fx_offset
;
1850 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1852 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1854 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1855 _("reloc %d not supported by object file format"),
1856 (int) fixp
->fx_r_type
);
1860 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1861 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1862 reloc
->address
= fixp
->fx_offset
;
1869 md_assemble (char *str
)
1871 struct avr_opcodes_s
*opcode
;
1874 str
= skip_space (extract_word (str
, op
, sizeof (op
)));
1877 as_bad (_("can't find opcode "));
1879 opcode
= (struct avr_opcodes_s
*) str_hash_find (avr_hash
, op
);
1881 if (opcode
&& !avr_opt
.all_opcodes
)
1883 /* Check if the instruction's ISA bit is ON in the ISA bits of the part
1884 specified by the user. If not look for other instructions
1885 specifications with same mnemonic who's ISA bits matches.
1887 This requires include/opcode/avr.h to have the instructions with
1888 same mnemonic to be specified in sequence. */
1890 while ((opcode
->isa
& avr_mcu
->isa
) != opcode
->isa
)
1894 if (opcode
->name
&& strcmp(op
, opcode
->name
))
1896 as_bad (_("illegal opcode %s for mcu %s"),
1897 opcode
->name
, avr_mcu
->name
);
1905 as_bad (_("unknown opcode `%s'"), op
);
1909 if (opcode
== avr_gccisr_opcode
1910 && !avr_opt
.have_gccisr
)
1912 as_bad (_("pseudo instruction `%s' not supported"), op
);
1916 /* Special case for opcodes with optional operands (lpm, elpm) -
1917 version with operands exists in avr_opcodes[] in the next entry. */
1919 if (*str
&& *opcode
->constraints
== '?')
1922 dwarf2_emit_insn (0);
1924 /* We used to set input_line_pointer to the result of get_operands,
1925 but that is wrong. Our caller assumes we don't change it. */
1927 char *t
= input_line_pointer
;
1929 if (opcode
== avr_gccisr_opcode
)
1930 avr_gccisr_operands (opcode
, &str
);
1932 avr_operands (opcode
, &str
);
1933 if (*skip_space (str
))
1934 as_bad (_("garbage at end of line"));
1935 input_line_pointer
= t
;
1939 const exp_mod_data_t exp_mod_data
[] =
1941 /* Default, must be first. */
1942 { "", 0, BFD_RELOC_16
, "" },
1943 /* Divides by 2 to get word address. Generate Stub. */
1944 { "gs", 2, BFD_RELOC_AVR_16_PM
, "`gs' " },
1945 { "pm", 2, BFD_RELOC_AVR_16_PM
, "`pm' " },
1946 /* The following are used together with avr-gcc's __memx address space
1947 in order to initialize a 24-bit pointer variable with a 24-bit address.
1948 For address in flash, hlo8 will contain the flash segment if the
1949 symbol is located in flash. If the symbol is located in RAM; hlo8
1950 will contain 0x80 which matches avr-gcc's notion of how 24-bit RAM/flash
1951 addresses linearize address space. */
1952 { "lo8", 1, BFD_RELOC_AVR_8_LO
, "`lo8' " },
1953 { "hi8", 1, BFD_RELOC_AVR_8_HI
, "`hi8' " },
1954 { "hlo8", 1, BFD_RELOC_AVR_8_HLO
, "`hlo8' " },
1955 { "hh8", 1, BFD_RELOC_AVR_8_HLO
, "`hh8' " },
1958 /* Parse special CONS expression: pm (expression) or alternatively
1959 gs (expression). These are used for addressing program memory. Moreover,
1960 define lo8 (expression), hi8 (expression) and hlo8 (expression). */
1962 const exp_mod_data_t
*
1963 avr_parse_cons_expression (expressionS
*exp
, int nbytes
)
1968 tmp
= input_line_pointer
= skip_space (input_line_pointer
);
1970 /* The first entry of exp_mod_data[] contains an entry if no
1971 expression modifier is present. Skip it. */
1973 for (i
= 0; i
< ARRAY_SIZE (exp_mod_data
); i
++)
1975 const exp_mod_data_t
*pexp
= &exp_mod_data
[i
];
1976 int len
= strlen (pexp
->name
);
1978 if (nbytes
== pexp
->nbytes
1979 && strncasecmp (input_line_pointer
, pexp
->name
, len
) == 0)
1981 input_line_pointer
= skip_space (input_line_pointer
+ len
);
1983 if (*input_line_pointer
== '(')
1985 input_line_pointer
= skip_space (input_line_pointer
+ 1);
1988 if (*input_line_pointer
== ')')
1990 ++input_line_pointer
;
1995 as_bad (_("`)' required"));
1996 return &exp_mod_data
[0];
2000 input_line_pointer
= tmp
;
2007 return &exp_mod_data
[0];
2011 avr_cons_fix_new (fragS
*frag
,
2015 const exp_mod_data_t
*pexp_mod_data
)
2019 switch (pexp_mod_data
->reloc
)
2023 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, BFD_RELOC_8
);
2024 else if (nbytes
== 2)
2025 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, BFD_RELOC_16
);
2026 else if (nbytes
== 4)
2027 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, BFD_RELOC_32
);
2032 case BFD_RELOC_AVR_16_PM
:
2033 case BFD_RELOC_AVR_8_LO
:
2034 case BFD_RELOC_AVR_8_HI
:
2035 case BFD_RELOC_AVR_8_HLO
:
2036 if (nbytes
== pexp_mod_data
->nbytes
)
2037 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, pexp_mod_data
->reloc
);
2044 as_bad (_("illegal %s relocation size: %d"), pexp_mod_data
->error
, nbytes
);
2048 mcu_has_3_byte_pc (void)
2050 int mach
= avr_mcu
->mach
;
2052 return mach
== bfd_mach_avr6
2053 || mach
== bfd_mach_avrxmega6
2054 || mach
== bfd_mach_avrxmega7
;
2058 tc_cfi_frame_initial_instructions (void)
2060 /* AVR6 pushes 3 bytes for calls. */
2061 int return_size
= (mcu_has_3_byte_pc () ? 3 : 2);
2063 /* The CFA is the caller's stack location before the call insn. */
2064 /* Note that the stack pointer is dwarf register number 32. */
2065 cfi_add_CFA_def_cfa (32, return_size
);
2067 /* Note that AVR consistently uses post-decrement, which means that things
2068 do not line up the same way as for targets that use pre-decrement. */
2069 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, 1-return_size
);
2073 avr_allow_local_subtract (expressionS
* left
,
2074 expressionS
* right
,
2077 /* If we are not in relaxation mode, subtraction is OK. */
2081 /* If the symbols are not in a code section then they are OK. */
2082 if ((section
->flags
& SEC_CODE
) == 0)
2085 if (left
->X_add_symbol
== right
->X_add_symbol
)
2088 /* We have to assume that there may be instructions between the
2089 two symbols and that relaxation may increase the distance between
2095 avr_elf_final_processing (void)
2098 elf_elfheader (stdoutput
)->e_flags
|= EF_AVR_LINKRELAX_PREPARED
;
2101 /* Write out the header of a .avr.prop section into the area pointed to by
2102 DATA. The RECORD_COUNT will be placed in the header as the number of
2103 records that are to follow.
2104 The area DATA must be big enough the receive the header, which is
2105 AVR_PROPERTY_SECTION_HEADER_SIZE bytes long. */
2108 avr_output_property_section_header (char *data
,
2109 unsigned int record_count
)
2111 char *orig_data
= data
;
2113 md_number_to_chars (data
, AVR_PROPERTY_RECORDS_VERSION
, 1);
2115 /* There's space for a single byte flags field, but right now there's
2116 nothing to go in here, so just set the value to zero. */
2117 md_number_to_chars (data
, 0, 1);
2119 md_number_to_chars (data
, record_count
, 2);
2122 gas_assert (data
- orig_data
== AVR_PROPERTY_SECTION_HEADER_SIZE
);
2127 /* Return the number of bytes required to store RECORD into the .avr.prop
2128 section. The size returned is the compressed size that corresponds to
2129 how the record will be written out in AVR_OUTPUT_PROPERTY_RECORD. */
2132 avr_record_size (const struct avr_property_record
*record
)
2134 /* The first 5 bytes are a 4-byte address, followed by a 1-byte type
2138 switch (record
->type
)
2141 size
+= 0; /* No extra information. */
2144 case RECORD_ORG_AND_FILL
:
2145 size
+= 4; /* A 4-byte fill value. */
2149 size
+= 4; /* A 4-byte alignment value. */
2152 case RECORD_ALIGN_AND_FILL
:
2153 size
+= 8; /* A 4-byte alignment, and 4-byte fill value. */
2157 as_fatal (_("unknown record type %d (in %s)"),
2158 record
->type
, __PRETTY_FUNCTION__
);
2164 /* Write out RECORD. FRAG_BASE points to the start of the data area setup
2165 to hold all of the .avr.prop content, FRAG_PTR points to the next
2166 writable location. The data area must be big enough to hold all of the
2167 records. The size of the data written out for this RECORD must match
2168 the size from AVR_RECORD_SIZE. */
2171 avr_output_property_record (char * const frag_base
, char *frag_ptr
,
2172 const struct avr_property_record
*record
)
2176 char *init_frag_ptr
= frag_ptr
;
2178 where
= frag_ptr
- frag_base
;
2179 fix
= fix_new (frag_now
, where
, 4,
2180 section_symbol (record
->section
),
2181 record
->offset
, FALSE
, BFD_RELOC_32
);
2182 fix
->fx_file
= "<internal>";
2186 md_number_to_chars (frag_ptr
, (bfd_byte
) record
->type
, 1);
2189 /* Write out the rest of the data. */
2190 switch (record
->type
)
2195 case RECORD_ORG_AND_FILL
:
2196 md_number_to_chars (frag_ptr
, record
->data
.org
.fill
, 4);
2201 md_number_to_chars (frag_ptr
, record
->data
.align
.bytes
, 4);
2205 case RECORD_ALIGN_AND_FILL
:
2206 md_number_to_chars (frag_ptr
, record
->data
.align
.bytes
, 4);
2207 md_number_to_chars (frag_ptr
+ 4, record
->data
.align
.fill
, 4);
2212 as_fatal (_("unknown record type %d (in %s)"),
2213 record
->type
, __PRETTY_FUNCTION__
);
2216 gas_assert (frag_ptr
- init_frag_ptr
== avr_record_size (record
));
2221 /* Create the section to hold the AVR property information. Return the
2225 avr_create_property_section (void)
2228 flagword flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
);
2229 const char *section_name
= AVR_PROPERTY_RECORD_SECTION_NAME
;
2231 sec
= bfd_make_section (stdoutput
, section_name
);
2233 as_fatal (_("Failed to create property section `%s'\n"), section_name
);
2234 bfd_set_section_flags (sec
, flags
);
2235 sec
->output_section
= sec
;
2239 /* This hook is called when alignment is performed, and allows us to
2240 capture the details of both .org and .align directives. */
2243 avr_handle_align (fragS
*fragP
)
2247 /* Ignore alignment requests at FR_ADDRESS 0, these are at the very
2248 start of a section, and will be handled by the standard section
2249 alignment mechanism. */
2250 if ((fragP
->fr_type
== rs_align
2251 || fragP
->fr_type
== rs_align_code
)
2252 && fragP
->fr_offset
> 0)
2254 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2256 fragP
->tc_frag_data
.is_align
= TRUE
;
2257 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
2258 fragP
->tc_frag_data
.fill
= *p
;
2259 fragP
->tc_frag_data
.has_fill
= (fragP
->tc_frag_data
.fill
!= 0);
2262 if (fragP
->fr_type
== rs_org
&& fragP
->fr_offset
> 0)
2264 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2266 fragP
->tc_frag_data
.is_org
= TRUE
;
2267 fragP
->tc_frag_data
.fill
= *p
;
2268 fragP
->tc_frag_data
.has_fill
= (fragP
->tc_frag_data
.fill
!= 0);
2273 /* Return TRUE if this section is not one for which we need to record
2274 information in the avr property section. */
2277 exclude_section_from_property_tables (segT sec
)
2279 /* Only generate property information for sections on which linker
2280 relaxation could be performed. */
2281 return !relaxable_section (sec
);
2284 /* Create a property record for fragment FRAGP from section SEC and place
2285 it into an AVR_PROPERTY_RECORD_LINK structure, which can then formed
2286 into a linked list by the caller. */
2288 static struct avr_property_record_link
*
2289 create_record_for_frag (segT sec
, fragS
*fragP
)
2291 struct avr_property_record_link
*prop_rec_link
;
2293 prop_rec_link
= XCNEW (struct avr_property_record_link
);
2294 gas_assert (fragP
->fr_next
!= NULL
);
2296 if (fragP
->tc_frag_data
.is_org
)
2298 prop_rec_link
->record
.offset
= fragP
->fr_next
->fr_address
;
2299 prop_rec_link
->record
.section
= sec
;
2301 if (fragP
->tc_frag_data
.has_fill
)
2303 prop_rec_link
->record
.data
.org
.fill
= fragP
->tc_frag_data
.fill
;
2304 prop_rec_link
->record
.type
= RECORD_ORG_AND_FILL
;
2307 prop_rec_link
->record
.type
= RECORD_ORG
;
2311 prop_rec_link
->record
.offset
= fragP
->fr_next
->fr_address
;
2312 prop_rec_link
->record
.section
= sec
;
2314 gas_assert (fragP
->tc_frag_data
.is_align
);
2315 if (fragP
->tc_frag_data
.has_fill
)
2317 prop_rec_link
->record
.data
.align
.fill
= fragP
->tc_frag_data
.fill
;
2318 prop_rec_link
->record
.type
= RECORD_ALIGN_AND_FILL
;
2321 prop_rec_link
->record
.type
= RECORD_ALIGN
;
2322 prop_rec_link
->record
.data
.align
.bytes
= fragP
->tc_frag_data
.alignment
;
2325 return prop_rec_link
;
2328 /* Build a list of AVR_PROPERTY_RECORD_LINK structures for section SEC, and
2329 merged them onto the list pointed to by NEXT_PTR. Return a pointer to
2330 the last list item created. */
2332 static struct avr_property_record_link
**
2333 append_records_for_section (segT sec
,
2334 struct avr_property_record_link
**next_ptr
)
2336 segment_info_type
*seginfo
= seg_info (sec
);
2339 if (seginfo
&& seginfo
->frchainP
)
2341 for (fragP
= seginfo
->frchainP
->frch_root
;
2343 fragP
= fragP
->fr_next
)
2345 if (fragP
->tc_frag_data
.is_align
2346 || fragP
->tc_frag_data
.is_org
)
2348 /* Create a single new entry. */
2349 struct avr_property_record_link
*new_link
2350 = create_record_for_frag (sec
, fragP
);
2352 *next_ptr
= new_link
;
2353 next_ptr
= &new_link
->next
;
2361 /* Create the AVR property section and fill it with records of .org and
2362 .align directives that were used. The section is only created if it
2363 will actually have any content. */
2366 avr_create_and_fill_property_section (void)
2370 struct avr_property_record_link
*r_list
, **next_ptr
;
2371 char *frag_ptr
, *frag_base
;
2372 bfd_size_type sec_size
;
2373 struct avr_property_record_link
*rec
;
2374 unsigned int record_count
;
2376 /* First walk over all sections. For sections on which linker
2377 relaxation could be applied, extend the record list. The record list
2378 holds information that the linker will need to know. */
2383 for (seclist
= &stdoutput
->sections
;
2384 seclist
&& *seclist
;
2385 seclist
= &(*seclist
)->next
)
2387 segT sec
= *seclist
;
2389 if (exclude_section_from_property_tables (sec
))
2392 next_ptr
= append_records_for_section (sec
, next_ptr
);
2395 /* Create property section and ensure the size is correct. We've already
2396 passed the point where gas could size this for us. */
2397 sec_size
= AVR_PROPERTY_SECTION_HEADER_SIZE
;
2399 for (rec
= r_list
; rec
!= NULL
; rec
= rec
->next
)
2402 sec_size
+= avr_record_size (&rec
->record
);
2405 if (record_count
== 0)
2408 prop_sec
= avr_create_property_section ();
2409 bfd_set_section_size (prop_sec
, sec_size
);
2411 subseg_set (prop_sec
, 0);
2412 frag_base
= frag_more (sec_size
);
2415 avr_output_property_section_header (frag_base
, record_count
);
2417 for (rec
= r_list
; rec
!= NULL
; rec
= rec
->next
)
2418 frag_ptr
= avr_output_property_record (frag_base
, frag_ptr
, &rec
->record
);
2420 frag_wane (frag_now
);
2422 frag_wane (frag_now
);
2425 /* We're using this hook to build up the AVR property section. It's called
2426 late in the assembly process which suits our needs. */
2428 avr_post_relax_hook (void)
2430 avr_create_and_fill_property_section ();
2434 /* Accumulate information about instruction sequence to `avr_isr':
2435 wheter TMP_REG, ZERO_REG and SREG might be touched. Used during parse.
2436 REG1 is either -1 or a register number used by the instruction as input
2437 or output operand. Similar for REG2. */
2440 avr_update_gccisr (struct avr_opcodes_s
*opcode
, int reg1
, int reg2
)
2442 const int tiny_p
= avr_mcu
->mach
== bfd_mach_avrtiny
;
2443 const int reg_tmp
= tiny_p
? 16 : 0;
2444 const int reg_zero
= 1 + reg_tmp
;
2446 if (ISR_CHUNK_Done
== avr_isr
.prev_chunk
2447 || (avr_isr
.need_sreg
2448 && avr_isr
.need_reg_tmp
2449 && avr_isr
.need_reg_zero
))
2451 /* Nothing (more) to do */
2455 /* SREG: Look up instructions that don't clobber SREG. */
2457 if (!avr_isr
.need_sreg
2458 && !str_hash_find (avr_no_sreg_hash
, opcode
->name
))
2460 avr_isr
.need_sreg
= 1;
2463 /* Handle explicit register operands. Record *any* use as clobber.
2464 This is because TMP_REG and ZERO_REG are not global and using
2465 them makes no sense without a previous set. */
2467 avr_isr
.need_reg_tmp
|= reg1
== reg_tmp
|| reg2
== reg_tmp
;
2468 avr_isr
.need_reg_zero
|= reg1
== reg_zero
|| reg2
== reg_zero
;
2470 /* Handle implicit register operands and some opaque stuff. */
2472 if (strstr (opcode
->name
, "lpm")
2473 && '?' == *opcode
->constraints
)
2475 avr_isr
.need_reg_tmp
= 1;
2478 if (strstr (opcode
->name
, "call")
2479 || strstr (opcode
->name
, "mul")
2480 || 0 == strcmp (opcode
->name
, "des")
2481 || (0 == strcmp (opcode
->name
, "movw")
2482 && (reg1
== reg_tmp
|| reg2
== reg_tmp
)))
2484 avr_isr
.need_reg_tmp
= 1;
2485 avr_isr
.need_reg_zero
= 1;
2490 /* Emit some 1-word instruction to **PWHERE and advance *PWHERE by the number
2491 of octets written. INSN specifies the desired instruction and REG is the
2492 register used by it. This function is only used with restricted subset of
2493 instructions as might be emit by `__gcc_isr'. IN / OUT will use SREG
2497 avr_emit_insn (const char *insn
, int reg
, char **pwhere
)
2499 const int sreg
= 0x3f;
2501 const struct avr_opcodes_s
*op
2502 = (struct avr_opcodes_s
*) str_hash_find (avr_hash
, insn
);
2504 /* We only have to deal with: IN, OUT, PUSH, POP, CLR, LDI 0. All of
2505 these deal with at least one Reg and are 1-word instructions. */
2507 gas_assert (op
&& 1 == op
->insn_size
);
2508 gas_assert (reg
>= 0 && reg
<= 31);
2510 if (strchr (op
->constraints
, 'r'))
2512 bin
= op
->bin_opcode
| (reg
<< 4);
2514 else if (strchr (op
->constraints
, 'd'))
2516 gas_assert (reg
>= 16);
2517 bin
= op
->bin_opcode
| ((reg
& 0xf) << 4);
2522 if (strchr (op
->constraints
, 'P'))
2524 bin
|= ((sreg
& 0x30) << 5) | (sreg
& 0x0f);
2526 else if (0 == strcmp ("r=r", op
->constraints
))
2528 bin
|= ((reg
& 0x10) << 5) | (reg
& 0x0f);
2531 gas_assert (0 == strcmp ("r", op
->constraints
)
2532 || 0 == strcmp ("ldi", op
->name
));
2534 bfd_putl16 ((bfd_vma
) bin
, *pwhere
);
2535 (*pwhere
) += 2 * op
->insn_size
;
2539 /* Turn rs_machine_dependent frag *FR into an ordinary rs_fill code frag,
2540 using information gathered in `avr_isr'. REG is the register number as
2541 supplied by Done chunk "__gcc_isr 0,REG". */
2544 avr_patch_gccisr_frag (fragS
*fr
, int reg
)
2548 char *where
= fr
->fr_literal
;
2549 const int tiny_p
= avr_mcu
->mach
== bfd_mach_avrtiny
;
2550 const int reg_tmp
= tiny_p
? 16 : 0;
2551 const int reg_zero
= 1 + reg_tmp
;
2553 /* Clearing ZERO_REG on non-Tiny needs CLR which clobbers SREG. */
2555 avr_isr
.need_sreg
|= !tiny_p
&& avr_isr
.need_reg_zero
;
2557 /* A working register to PUSH / POP the SREG. We might use the register
2558 as supplied by ISR_CHUNK_Done for that purpose as GCC wants to push
2559 it anyways. If GCC passes ZERO_REG or TMP_REG, it has no clue (and
2560 no additional regs to safe) and we use that reg. */
2563 = avr_isr
.need_reg_tmp
? reg_tmp
2564 : avr_isr
.need_reg_zero
? reg_zero
2565 : avr_isr
.need_sreg
? reg
2566 : reg
> reg_zero
? reg
2571 /* Non-empty prologue / epilogue */
2573 if (ISR_CHUNK_Prologue
== fr
->fr_subtype
)
2575 avr_emit_insn ("push", treg
, &where
);
2578 if (avr_isr
.need_sreg
)
2580 avr_emit_insn ("in", treg
, &where
);
2581 avr_emit_insn ("push", treg
, &where
);
2585 if (avr_isr
.need_reg_zero
)
2587 if (reg_zero
!= treg
)
2589 avr_emit_insn ("push", reg_zero
, &where
);
2592 avr_emit_insn (tiny_p
? "ldi" : "clr", reg_zero
, &where
);
2595 if (reg
> reg_zero
&& reg
!= treg
)
2597 avr_emit_insn ("push", reg
, &where
);
2601 else if (ISR_CHUNK_Epilogue
== fr
->fr_subtype
)
2603 /* Same logic as in Prologue but in reverse order and with counter
2604 parts of either instruction: POP instead of PUSH and OUT instead
2605 of IN. Clearing ZERO_REG has no couter part. */
2607 if (reg
> reg_zero
&& reg
!= treg
)
2608 avr_emit_insn ("pop", reg
, &where
);
2610 if (avr_isr
.need_reg_zero
2611 && reg_zero
!= treg
)
2612 avr_emit_insn ("pop", reg_zero
, &where
);
2614 if (avr_isr
.need_sreg
)
2616 avr_emit_insn ("pop", treg
, &where
);
2617 avr_emit_insn ("out", treg
, &where
);
2620 avr_emit_insn ("pop", treg
, &where
);
2626 if (ISR_CHUNK_Prologue
== fr
->fr_subtype
2627 && avr_isr
.sym_n_pushed
)
2629 symbolS
*sy
= avr_isr
.sym_n_pushed
;
2630 /* Turn magic `__gcc_isr.n_pushed' into its now known value. */
2632 S_SET_VALUE (sy
, n_pushed
);
2633 S_SET_SEGMENT (sy
, expr_section
);
2634 avr_isr
.sym_n_pushed
= NULL
;
2637 /* Turn frag into ordinary code frag of now known size. */
2640 fr
->fr_fix
= where
- fr
->fr_literal
;
2641 gas_assert (fr
->fr_fix
<= (valueT
) fr
->fr_offset
);
2643 fr
->fr_type
= rs_fill
;
2648 /* Implements `__gcc_isr' pseudo-instruction. For Prologue and Epilogue
2649 chunks, emit a new rs_machine_dependent frag. For Done chunks, traverse
2650 the current segment and patch all rs_machine_dependent frags to become
2651 appropriate rs_fill code frags. If chunks are seen in an odd ordering,
2652 throw an error instead. */
2655 avr_gccisr_operands (struct avr_opcodes_s
*opcode
, char **line
)
2661 gas_assert (avr_opt
.have_gccisr
);
2663 /* We only use operands "N" and "r" which don't pop new fix-ups. */
2665 /* 1st operand: Which chunk of __gcc_isr: 0...2. */
2667 chunk
= avr_operand (opcode
, -1, "N", &str
, NULL
);
2668 if (chunk
< 0 || chunk
> 2)
2669 as_bad (_("%s requires value 0-2 as operand 1"), opcode
->name
);
2671 if (ISR_CHUNK_Done
== chunk
)
2673 /* 2nd operand: A register to push / pop. */
2675 str
= skip_space (str
);
2676 if (*str
== '\0' || *str
++ != ',')
2677 as_bad (_("`,' required"));
2679 avr_operand (opcode
, -1, "r", &str
, ®
);
2684 /* Chunks must follow in a specific order:
2685 - Prologue: Exactly one
2686 - Epilogue: Any number
2687 - Done: Exactly one. */
2688 bad
|= ISR_CHUNK_Prologue
== chunk
&& avr_isr
.prev_chunk
!= ISR_CHUNK_Done
;
2689 bad
|= ISR_CHUNK_Epilogue
== chunk
&& avr_isr
.prev_chunk
== ISR_CHUNK_Done
;
2690 bad
|= ISR_CHUNK_Done
== chunk
&& avr_isr
.prev_chunk
== ISR_CHUNK_Done
;
2694 as_bad (_("`%s %d' after `%s %d' from %s:%u"), opcode
->name
, chunk
,
2695 opcode
->name
, avr_isr
.prev_chunk
, avr_isr
.file
, avr_isr
.line
);
2697 as_bad (_("`%s %d' but no chunk open yet"), opcode
->name
, chunk
);
2702 /* The longest sequence (prologue) might have up to 6 insns (words):
2711 unsigned int size
= 2 * 6;
2716 case ISR_CHUNK_Prologue
:
2717 avr_isr
.need_reg_tmp
= 0;
2718 avr_isr
.need_reg_zero
= 0;
2719 avr_isr
.need_sreg
= 0;
2720 avr_isr
.sym_n_pushed
= NULL
;
2723 case ISR_CHUNK_Epilogue
:
2724 /* Emit a new rs_machine_dependent fragment into the fragment chain.
2725 It will be patched and cleaned up once we see the matching
2727 frag_wane (frag_now
);
2731 frag_now
->fr_var
= 1;
2732 frag_now
->fr_offset
= size
;
2733 frag_now
->fr_fix
= 0;
2734 frag_now
->fr_type
= rs_machine_dependent
;
2735 frag_now
->fr_subtype
= chunk
;
2739 case ISR_CHUNK_Done
:
2740 /* Traverse all frags of the current subseg and turn ones of type
2741 rs_machine_dependent into ordinary code as expected by GCC. */
2743 for (fr
= frchain_now
->frch_root
; fr
; fr
= fr
->fr_next
)
2744 if (fr
->fr_type
== rs_machine_dependent
)
2745 avr_patch_gccisr_frag (fr
, reg
);
2754 avr_isr
.prev_chunk
= chunk
;
2755 avr_isr
.file
= as_where (&avr_isr
.line
);
2759 /* Callback used by the function below. Diagnose any dangling stuff from
2760 `__gcc_isr', i.e. frags of type rs_machine_dependent. Such frags should
2761 have been resolved during parse by ISR_CHUNK_Done. If such a frag is
2762 seen, report an error and turn it into something harmless. */
2765 avr_check_gccisr_done (bfd
*abfd ATTRIBUTE_UNUSED
,
2767 void *xxx ATTRIBUTE_UNUSED
)
2769 segment_info_type
*info
= seg_info (section
);
2771 if (SEG_NORMAL (section
)
2772 /* BFD may have introduced its own sections without using
2773 subseg_new, so it is possible that seg_info is NULL. */
2779 for (frch
= info
->frchainP
; frch
; frch
= frch
->frch_next
)
2780 for (fr
= frch
->frch_root
; fr
; fr
= fr
->fr_next
)
2781 if (fr
->fr_type
== rs_machine_dependent
)
2784 as_bad_where (avr_isr
.file
, avr_isr
.line
,
2785 _("dangling `__gcc_isr %d'"), avr_isr
.prev_chunk
);
2786 else if (!had_errors())
2787 as_bad (_("dangling `__gcc_isr'"));
2789 avr_isr
.file
= NULL
;
2791 /* Avoid Internal errors due to rs_machine_dependent in the
2792 remainder: Turn frag into something harmless. */
2796 fr
->fr_type
= rs_fill
;
2803 /* Implement `md_pre_output_hook' */
2804 /* Run over all relevant sections and diagnose any dangling `__gcc_isr'.
2805 This runs after parsing all inputs but before relaxing and writing. */
2808 avr_pre_output_hook (void)
2810 if (avr_opt
.have_gccisr
)
2811 bfd_map_over_sections (stdoutput
, avr_check_gccisr_done
, NULL
);