1 /* tc-bfin.c -- Assembler for the ADI Blackfin.
2 Copyright (C) 2005-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 #include "struc-symbol.h"
23 #include "bfin-defs.h"
25 #include "safe-ctype.h"
27 #include "dwarf2dbg.h"
30 #include "elf/common.h"
33 extern int yyparse (void);
34 struct yy_buffer_state
;
35 typedef struct yy_buffer_state
*YY_BUFFER_STATE
;
36 extern YY_BUFFER_STATE
yy_scan_string (const char *yy_str
);
37 extern void yy_delete_buffer (YY_BUFFER_STATE b
);
38 static parse_state
parse (char *line
);
40 /* Global variables. */
41 struct bfin_insn
*insn
;
44 extern struct obstack mempool
;
47 /* Flags to set in the elf header */
48 #define DEFAULT_FLAGS 0
51 # define DEFAULT_FDPIC EF_BFIN_FDPIC
53 # define DEFAULT_FDPIC 0
56 static flagword bfin_flags
= DEFAULT_FLAGS
| DEFAULT_FDPIC
;
57 static const char *bfin_pic_flag
= DEFAULT_FDPIC
? "-mfdpic" : (const char *)0;
59 /* Blackfin specific function to handle FD-PIC pointer initializations. */
62 bfin_pic_ptr (int nbytes
)
70 #ifdef md_flush_pending_output
71 md_flush_pending_output ();
74 if (is_it_end_of_statement ())
76 demand_empty_rest_of_line ();
81 md_cons_align (nbytes
);
86 bfd_reloc_code_real_type reloc_type
= BFD_RELOC_BFIN_FUNCDESC
;
88 if (strncasecmp (input_line_pointer
, "funcdesc(", 9) == 0)
90 input_line_pointer
+= 9;
92 if (*input_line_pointer
== ')')
95 as_bad (_("missing ')'"));
98 error ("missing funcdesc in picptr");
102 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
105 while (*input_line_pointer
++ == ',');
107 input_line_pointer
--; /* Put terminator back into stream. */
108 demand_empty_rest_of_line ();
112 bfin_s_bss (int ignore ATTRIBUTE_UNUSED
)
116 temp
= get_absolute_expression ();
117 subseg_set (bss_section
, (subsegT
) temp
);
118 demand_empty_rest_of_line ();
121 const pseudo_typeS md_pseudo_table
[] = {
122 {"align", s_align_bytes
, 0},
125 {"picptr", bfin_pic_ptr
, 4},
126 {"code", obj_elf_section
, 0},
131 {"pdata", s_ignore
, 0},
132 {"var", s_ignore
, 0},
133 {"bss", bfin_s_bss
, 0},
137 /* Characters that are used to denote comments and line separators. */
138 const char comment_chars
[] = "#";
139 const char line_comment_chars
[] = "#";
140 const char line_separator_chars
[] = ";";
142 /* Characters that can be used to separate the mantissa from the
143 exponent in floating point numbers. */
144 const char EXP_CHARS
[] = "eE";
146 /* Characters that mean this number is a floating point constant.
147 As in 0f12.456 or 0d1.2345e12. */
148 const char FLT_CHARS
[] = "fFdDxX";
150 typedef enum bfin_cpu_type
187 bfin_cpu_t bfin_cpu_type
= BFIN_CPU_UNKNOWN
;
188 /* -msi-revision support. There are three special values:
189 -1 -msi-revision=none.
190 0xffff -msi-revision=any. */
191 int bfin_si_revision
;
193 unsigned int bfin_anomaly_checks
= 0;
200 unsigned int anomaly_checks
;
203 struct bfin_cpu bfin_cpus
[] =
205 {"bf504", BFIN_CPU_BF504
, 0x0000, AC_05000074
},
207 {"bf506", BFIN_CPU_BF506
, 0x0000, AC_05000074
},
209 {"bf512", BFIN_CPU_BF512
, 0x0002, AC_05000074
},
210 {"bf512", BFIN_CPU_BF512
, 0x0001, AC_05000074
},
211 {"bf512", BFIN_CPU_BF512
, 0x0000, AC_05000074
},
213 {"bf514", BFIN_CPU_BF514
, 0x0002, AC_05000074
},
214 {"bf514", BFIN_CPU_BF514
, 0x0001, AC_05000074
},
215 {"bf514", BFIN_CPU_BF514
, 0x0000, AC_05000074
},
217 {"bf516", BFIN_CPU_BF516
, 0x0002, AC_05000074
},
218 {"bf516", BFIN_CPU_BF516
, 0x0001, AC_05000074
},
219 {"bf516", BFIN_CPU_BF516
, 0x0000, AC_05000074
},
221 {"bf518", BFIN_CPU_BF518
, 0x0002, AC_05000074
},
222 {"bf518", BFIN_CPU_BF518
, 0x0001, AC_05000074
},
223 {"bf518", BFIN_CPU_BF518
, 0x0000, AC_05000074
},
225 {"bf522", BFIN_CPU_BF522
, 0x0002, AC_05000074
},
226 {"bf522", BFIN_CPU_BF522
, 0x0001, AC_05000074
},
227 {"bf522", BFIN_CPU_BF522
, 0x0000, AC_05000074
},
229 {"bf523", BFIN_CPU_BF523
, 0x0002, AC_05000074
},
230 {"bf523", BFIN_CPU_BF523
, 0x0001, AC_05000074
},
231 {"bf523", BFIN_CPU_BF523
, 0x0000, AC_05000074
},
233 {"bf524", BFIN_CPU_BF524
, 0x0002, AC_05000074
},
234 {"bf524", BFIN_CPU_BF524
, 0x0001, AC_05000074
},
235 {"bf524", BFIN_CPU_BF524
, 0x0000, AC_05000074
},
237 {"bf525", BFIN_CPU_BF525
, 0x0002, AC_05000074
},
238 {"bf525", BFIN_CPU_BF525
, 0x0001, AC_05000074
},
239 {"bf525", BFIN_CPU_BF525
, 0x0000, AC_05000074
},
241 {"bf526", BFIN_CPU_BF526
, 0x0002, AC_05000074
},
242 {"bf526", BFIN_CPU_BF526
, 0x0001, AC_05000074
},
243 {"bf526", BFIN_CPU_BF526
, 0x0000, AC_05000074
},
245 {"bf527", BFIN_CPU_BF527
, 0x0002, AC_05000074
},
246 {"bf527", BFIN_CPU_BF527
, 0x0001, AC_05000074
},
247 {"bf527", BFIN_CPU_BF527
, 0x0000, AC_05000074
},
249 {"bf531", BFIN_CPU_BF531
, 0x0006, AC_05000074
},
250 {"bf531", BFIN_CPU_BF531
, 0x0005, AC_05000074
},
251 {"bf531", BFIN_CPU_BF531
, 0x0004, AC_05000074
},
252 {"bf531", BFIN_CPU_BF531
, 0x0003, AC_05000074
},
254 {"bf532", BFIN_CPU_BF532
, 0x0006, AC_05000074
},
255 {"bf532", BFIN_CPU_BF532
, 0x0005, AC_05000074
},
256 {"bf532", BFIN_CPU_BF532
, 0x0004, AC_05000074
},
257 {"bf532", BFIN_CPU_BF532
, 0x0003, AC_05000074
},
259 {"bf533", BFIN_CPU_BF533
, 0x0006, AC_05000074
},
260 {"bf533", BFIN_CPU_BF533
, 0x0005, AC_05000074
},
261 {"bf533", BFIN_CPU_BF533
, 0x0004, AC_05000074
},
262 {"bf533", BFIN_CPU_BF533
, 0x0003, AC_05000074
},
264 {"bf534", BFIN_CPU_BF534
, 0x0003, AC_05000074
},
265 {"bf534", BFIN_CPU_BF534
, 0x0002, AC_05000074
},
266 {"bf534", BFIN_CPU_BF534
, 0x0001, AC_05000074
},
268 {"bf536", BFIN_CPU_BF536
, 0x0003, AC_05000074
},
269 {"bf536", BFIN_CPU_BF536
, 0x0002, AC_05000074
},
270 {"bf536", BFIN_CPU_BF536
, 0x0001, AC_05000074
},
272 {"bf537", BFIN_CPU_BF537
, 0x0003, AC_05000074
},
273 {"bf537", BFIN_CPU_BF537
, 0x0002, AC_05000074
},
274 {"bf537", BFIN_CPU_BF537
, 0x0001, AC_05000074
},
276 {"bf538", BFIN_CPU_BF538
, 0x0005, AC_05000074
},
277 {"bf538", BFIN_CPU_BF538
, 0x0004, AC_05000074
},
278 {"bf538", BFIN_CPU_BF538
, 0x0003, AC_05000074
},
279 {"bf538", BFIN_CPU_BF538
, 0x0002, AC_05000074
},
281 {"bf539", BFIN_CPU_BF539
, 0x0005, AC_05000074
},
282 {"bf539", BFIN_CPU_BF539
, 0x0004, AC_05000074
},
283 {"bf539", BFIN_CPU_BF539
, 0x0003, AC_05000074
},
284 {"bf539", BFIN_CPU_BF539
, 0x0002, AC_05000074
},
286 {"bf542m", BFIN_CPU_BF542M
, 0x0003, AC_05000074
},
288 {"bf542", BFIN_CPU_BF542
, 0x0004, AC_05000074
},
289 {"bf542", BFIN_CPU_BF542
, 0x0002, AC_05000074
},
290 {"bf542", BFIN_CPU_BF542
, 0x0001, AC_05000074
},
291 {"bf542", BFIN_CPU_BF542
, 0x0000, AC_05000074
},
293 {"bf544m", BFIN_CPU_BF544M
, 0x0003, AC_05000074
},
295 {"bf544", BFIN_CPU_BF544
, 0x0004, AC_05000074
},
296 {"bf544", BFIN_CPU_BF544
, 0x0002, AC_05000074
},
297 {"bf544", BFIN_CPU_BF544
, 0x0001, AC_05000074
},
298 {"bf544", BFIN_CPU_BF544
, 0x0000, AC_05000074
},
300 {"bf547m", BFIN_CPU_BF547M
, 0x0003, AC_05000074
},
302 {"bf547", BFIN_CPU_BF547
, 0x0004, AC_05000074
},
303 {"bf547", BFIN_CPU_BF547
, 0x0002, AC_05000074
},
304 {"bf547", BFIN_CPU_BF547
, 0x0001, AC_05000074
},
305 {"bf547", BFIN_CPU_BF547
, 0x0000, AC_05000074
},
307 {"bf548m", BFIN_CPU_BF548M
, 0x0003, AC_05000074
},
309 {"bf548", BFIN_CPU_BF548
, 0x0004, AC_05000074
},
310 {"bf548", BFIN_CPU_BF548
, 0x0002, AC_05000074
},
311 {"bf548", BFIN_CPU_BF548
, 0x0001, AC_05000074
},
312 {"bf548", BFIN_CPU_BF548
, 0x0000, AC_05000074
},
314 {"bf549m", BFIN_CPU_BF549M
, 0x0003, AC_05000074
},
316 {"bf549", BFIN_CPU_BF549
, 0x0004, AC_05000074
},
317 {"bf549", BFIN_CPU_BF549
, 0x0002, AC_05000074
},
318 {"bf549", BFIN_CPU_BF549
, 0x0001, AC_05000074
},
319 {"bf549", BFIN_CPU_BF549
, 0x0000, AC_05000074
},
321 {"bf561", BFIN_CPU_BF561
, 0x0005, AC_05000074
},
322 {"bf561", BFIN_CPU_BF561
, 0x0003, AC_05000074
},
323 {"bf561", BFIN_CPU_BF561
, 0x0002, AC_05000074
},
325 {"bf592", BFIN_CPU_BF592
, 0x0001, AC_05000074
},
326 {"bf592", BFIN_CPU_BF592
, 0x0000, AC_05000074
},
331 /* Define bfin-specific command-line options (there are none). */
332 const char *md_shortopts
= "";
334 #define OPTION_FDPIC (OPTION_MD_BASE)
335 #define OPTION_NOPIC (OPTION_MD_BASE + 1)
336 #define OPTION_MCPU (OPTION_MD_BASE + 2)
338 struct option md_longopts
[] =
340 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
341 { "mfdpic", no_argument
, NULL
, OPTION_FDPIC
},
342 { "mnopic", no_argument
, NULL
, OPTION_NOPIC
},
343 { "mno-fdpic", no_argument
, NULL
, OPTION_NOPIC
},
344 { NULL
, no_argument
, NULL
, 0 },
347 size_t md_longopts_size
= sizeof (md_longopts
);
351 md_parse_option (int c ATTRIBUTE_UNUSED
, char *arg ATTRIBUTE_UNUSED
)
364 while ((p
= bfin_cpus
[i
].name
) != NULL
)
366 if (strncmp (arg
, p
, strlen (p
)) == 0)
372 as_fatal ("-mcpu=%s is not valid", arg
);
374 bfin_cpu_type
= bfin_cpus
[i
].type
;
376 q
= arg
+ strlen (p
);
380 bfin_si_revision
= bfin_cpus
[i
].si_revision
;
381 bfin_anomaly_checks
|= bfin_cpus
[i
].anomaly_checks
;
383 else if (strcmp (q
, "-none") == 0)
384 bfin_si_revision
= -1;
385 else if (strcmp (q
, "-any") == 0)
387 bfin_si_revision
= 0xffff;
388 while (bfin_cpus
[i
].type
== bfin_cpu_type
)
390 bfin_anomaly_checks
|= bfin_cpus
[i
].anomaly_checks
;
396 unsigned int si_major
, si_minor
;
399 rev_len
= strlen (q
);
401 if (sscanf (q
, "-%u.%u%n", &si_major
, &si_minor
, &n
) != 2
403 || si_major
> 0xff || si_minor
> 0xff)
405 invalid_silicon_revision
:
406 as_fatal ("-mcpu=%s has invalid silicon revision", arg
);
409 bfin_si_revision
= (si_major
<< 8) | si_minor
;
411 while (bfin_cpus
[i
].type
== bfin_cpu_type
412 && bfin_cpus
[i
].si_revision
!= bfin_si_revision
)
415 if (bfin_cpus
[i
].type
!= bfin_cpu_type
)
416 goto invalid_silicon_revision
;
418 bfin_anomaly_checks
|= bfin_cpus
[i
].anomaly_checks
;
425 bfin_flags
|= EF_BFIN_FDPIC
;
426 bfin_pic_flag
= "-mfdpic";
430 bfin_flags
&= ~(EF_BFIN_FDPIC
);
439 md_show_usage (FILE * stream
)
441 fprintf (stream
, _(" Blackfin specific assembler options:\n"));
442 fprintf (stream
, _(" -mcpu=<cpu[-sirevision]> specify the name of the target CPU\n"));
443 fprintf (stream
, _(" -mfdpic assemble for the FDPIC ABI\n"));
444 fprintf (stream
, _(" -mno-fdpic/-mnopic disable -mfdpic\n"));
447 /* Perform machine-specific initializations. */
451 /* Set the ELF flags if desired. */
453 bfd_set_private_flags (stdoutput
, bfin_flags
);
455 /* Set the default machine type. */
456 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_bfin
, 0))
457 as_warn (_("Could not set architecture and machine."));
459 /* Ensure that lines can begin with '(', for multiple
460 register stack pops. */
461 lex_type
['('] = LEX_BEGIN_NAME
;
464 record_alignment (text_section
, 2);
465 record_alignment (data_section
, 2);
466 record_alignment (bss_section
, 2);
470 obstack_init (&mempool
);
473 extern int debug_codeselection
;
474 debug_codeselection
= 1;
480 /* Perform the main parsing, and assembly of the input here. Also,
481 call the required routines for alignment and fixups here.
482 This is called for every line that contains real assembly code. */
485 md_assemble (char *line
)
488 extern char *current_inputline
;
490 struct bfin_insn
*tmp_insn
;
492 static size_t buffer_len
= 0;
496 if (len
+ 2 > buffer_len
)
499 free (current_inputline
);
500 buffer_len
= len
+ 40;
501 current_inputline
= xmalloc (buffer_len
);
503 memcpy (current_inputline
, line
, len
);
504 current_inputline
[len
] = ';';
505 current_inputline
[len
+ 1] = '\0';
507 state
= parse (current_inputline
);
508 if (state
== NO_INSN_GENERATED
)
511 for (insn_size
= 0, tmp_insn
= insn
; tmp_insn
; tmp_insn
= tmp_insn
->next
)
512 if (!tmp_insn
->reloc
|| !tmp_insn
->exp
->symbol
)
516 toP
= frag_more (insn_size
);
518 last_insn_size
= insn_size
;
525 if (insn
->reloc
&& insn
->exp
->symbol
)
527 char *prev_toP
= toP
- 2;
530 case BFD_RELOC_BFIN_24_PCREL_JUMP_L
:
531 case BFD_RELOC_24_PCREL
:
532 case BFD_RELOC_BFIN_16_LOW
:
533 case BFD_RELOC_BFIN_16_HIGH
:
540 /* Following if condition checks for the arithmetic relocations.
541 If the case then it doesn't required to generate the code.
542 It has been assumed that, their ID will be contiguous. */
543 if ((BFD_ARELOC_BFIN_PUSH
<= insn
->reloc
544 && BFD_ARELOC_BFIN_COMP
>= insn
->reloc
)
545 || insn
->reloc
== BFD_RELOC_BFIN_16_IMM
)
549 if (insn
->reloc
== BFD_ARELOC_BFIN_CONST
550 || insn
->reloc
== BFD_ARELOC_BFIN_PUSH
)
554 (prev_toP
- frag_now
->fr_literal
),
555 size
, insn
->exp
->symbol
, insn
->exp
->value
,
556 insn
->pcrel
, insn
->reloc
);
560 md_number_to_chars (toP
, insn
->value
, 2);
566 printf (" %02x%02x", ((unsigned char *) &insn
->value
)[0],
567 ((unsigned char *) &insn
->value
)[1]);
573 dwarf2_emit_insn (insn_size
);
576 while (*line
++ != '\0')
578 bump_line_counters ();
581 /* Parse one line of instructions, and generate opcode for it.
582 To parse the line, YACC and LEX are used, because the instruction set
583 syntax doesn't confirm to the AT&T assembly syntax.
584 To call a YACC & LEX generated parser, we must provide the input via
585 a FILE stream, otherwise stdin is used by default. Below the input
586 to the function will be put into a temporary file, then the generated
587 parser uses the temporary file for parsing. */
593 YY_BUFFER_STATE buffstate
;
595 buffstate
= yy_scan_string (line
);
597 /* our lex requires setting the start state to keyword
598 every line as the first word may be a keyword.
599 Fixes a bug where we could not have keywords as labels. */
602 /* Call yyparse here. */
604 if (state
== SEMANTIC_ERROR
)
606 as_bad (_("Parse failed."));
610 yy_delete_buffer (buffstate
);
614 /* We need to handle various expressions properly.
615 Such as, [SP--] = 34, concerned by md_assemble(). */
618 md_operand (expressionS
* expressionP
)
620 if (*input_line_pointer
== '[')
622 as_tsktsk ("We found a '['!");
623 input_line_pointer
++;
624 expression (expressionP
);
628 /* Handle undefined symbols. */
630 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
632 return (symbolS
*) 0;
636 md_estimate_size_before_relax (fragS
* fragP ATTRIBUTE_UNUSED
,
637 segT segment ATTRIBUTE_UNUSED
)
642 /* Convert from target byte order to host byte order. */
645 md_chars_to_number (char *val
, int n
)
649 for (retval
= 0; n
--;)
658 md_apply_fix (fixS
*fixP
, valueT
*valueP
, segT seg ATTRIBUTE_UNUSED
)
660 char *where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
662 long value
= *valueP
;
665 switch (fixP
->fx_r_type
)
667 case BFD_RELOC_BFIN_GOT
:
668 case BFD_RELOC_BFIN_GOT17M4
:
669 case BFD_RELOC_BFIN_FUNCDESC_GOT17M4
:
670 fixP
->fx_no_overflow
= 1;
671 newval
= md_chars_to_number (where
, 2);
672 newval
|= 0x0 & 0x7f;
673 md_number_to_chars (where
, newval
, 2);
676 case BFD_RELOC_BFIN_10_PCREL
:
679 if (value
< -1024 || value
> 1022)
680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
681 _("pcrel too far BFD_RELOC_BFIN_10"));
683 /* 11 bit offset even numbered, so we remove right bit. */
685 newval
= md_chars_to_number (where
, 2);
686 newval
|= value
& 0x03ff;
687 md_number_to_chars (where
, newval
, 2);
690 case BFD_RELOC_BFIN_12_PCREL_JUMP
:
691 case BFD_RELOC_BFIN_12_PCREL_JUMP_S
:
692 case BFD_RELOC_12_PCREL
:
696 if (value
< -4096 || value
> 4094)
697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("pcrel too far BFD_RELOC_BFIN_12"));
698 /* 13 bit offset even numbered, so we remove right bit. */
700 newval
= md_chars_to_number (where
, 2);
701 newval
|= value
& 0xfff;
702 md_number_to_chars (where
, newval
, 2);
705 case BFD_RELOC_BFIN_16_LOW
:
706 case BFD_RELOC_BFIN_16_HIGH
:
707 fixP
->fx_done
= FALSE
;
710 case BFD_RELOC_BFIN_24_PCREL_JUMP_L
:
711 case BFD_RELOC_BFIN_24_PCREL_CALL_X
:
712 case BFD_RELOC_24_PCREL
:
716 if (value
< -16777216 || value
> 16777214)
717 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("pcrel too far BFD_RELOC_BFIN_24"));
719 /* 25 bit offset even numbered, so we remove right bit. */
723 md_number_to_chars (where
- 2, value
>> 16, 1);
724 md_number_to_chars (where
, value
, 1);
725 md_number_to_chars (where
+ 1, value
>> 8, 1);
728 case BFD_RELOC_BFIN_5_PCREL
: /* LSETUP (a, b) : "a" */
731 if (value
< 4 || value
> 30)
732 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("pcrel too far BFD_RELOC_BFIN_5"));
734 newval
= md_chars_to_number (where
, 1);
735 newval
= (newval
& 0xf0) | (value
& 0xf);
736 md_number_to_chars (where
, newval
, 1);
739 case BFD_RELOC_BFIN_11_PCREL
: /* LSETUP (a, b) : "b" */
743 if (value
< 4 || value
> 2046)
744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("pcrel too far BFD_RELOC_BFIN_11_PCREL"));
745 /* 11 bit unsigned even, so we remove right bit. */
747 newval
= md_chars_to_number (where
, 2);
748 newval
|= value
& 0x03ff;
749 md_number_to_chars (where
, newval
, 2);
753 if (value
< -0x80 || value
>= 0x7f)
754 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("rel too far BFD_RELOC_8"));
755 md_number_to_chars (where
, value
, 1);
758 case BFD_RELOC_BFIN_16_IMM
:
760 if (value
< -0x8000 || value
>= 0x7fff)
761 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("rel too far BFD_RELOC_16"));
762 md_number_to_chars (where
, value
, 2);
766 md_number_to_chars (where
, value
, 4);
769 case BFD_RELOC_BFIN_PLTPC
:
770 md_number_to_chars (where
, value
, 2);
773 case BFD_RELOC_BFIN_FUNCDESC
:
774 case BFD_RELOC_VTABLE_INHERIT
:
775 case BFD_RELOC_VTABLE_ENTRY
:
776 fixP
->fx_done
= FALSE
;
780 if ((BFD_ARELOC_BFIN_PUSH
> fixP
->fx_r_type
) || (BFD_ARELOC_BFIN_COMP
< fixP
->fx_r_type
))
782 fprintf (stderr
, "Relocation %d not handled in gas." " Contact support.\n", fixP
->fx_r_type
);
788 fixP
->fx_done
= TRUE
;
792 /* Round up a section size to the appropriate boundary. */
794 md_section_align (segment
, size
)
798 int boundary
= bfd_get_section_alignment (stdoutput
, segment
);
799 return ((size
+ (1 << boundary
) - 1) & (-1 << boundary
));
804 md_atof (int type
, char * litP
, int * sizeP
)
806 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
810 /* If while processing a fixup, a reloc really needs to be created
811 then it is done here. */
814 tc_gen_reloc (seg
, fixp
)
815 asection
*seg ATTRIBUTE_UNUSED
;
820 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
821 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
822 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
823 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
825 reloc
->addend
= fixp
->fx_offset
;
826 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
828 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
830 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
831 /* xgettext:c-format. */
832 _("reloc %d not supported by object file format"),
833 (int) fixp
->fx_r_type
);
843 /* The location from which a PC relative jump should be calculated,
844 given a PC relative reloc. */
847 md_pcrel_from_section (fixP
, sec
)
851 if (fixP
->fx_addsy
!= (symbolS
*) NULL
852 && (!S_IS_DEFINED (fixP
->fx_addsy
)
853 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
855 /* The symbol is undefined (or is defined but not in this section).
856 Let the linker figure it out. */
859 return fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
862 /* Return true if the fix can be handled by GAS, false if it must
863 be passed through to the linker. */
866 bfin_fix_adjustable (fixS
*fixP
)
868 switch (fixP
->fx_r_type
)
870 /* Adjust_reloc_syms doesn't know about the GOT. */
871 case BFD_RELOC_BFIN_GOT
:
872 case BFD_RELOC_BFIN_PLTPC
:
873 /* We need the symbol name for the VTABLE entries. */
874 case BFD_RELOC_VTABLE_INHERIT
:
875 case BFD_RELOC_VTABLE_ENTRY
:
883 /* Special extra functions that help bfin-parse.y perform its job. */
885 struct obstack mempool
;
888 conscode (INSTR_T head
, INSTR_T tail
)
897 conctcode (INSTR_T head
, INSTR_T tail
)
899 INSTR_T temp
= (head
);
910 note_reloc (INSTR_T code
, Expr_Node
* symbol
, int reloc
, int pcrel
)
912 /* Assert that the symbol is not an operator. */
913 gas_assert (symbol
->type
== Expr_Node_Reloc
);
915 return note_reloc1 (code
, symbol
->value
.s_value
, reloc
, pcrel
);
920 note_reloc1 (INSTR_T code
, const char *symbol
, int reloc
, int pcrel
)
923 code
->exp
= mkexpr (0, symbol_find_or_make (symbol
));
929 note_reloc2 (INSTR_T code
, const char *symbol
, int reloc
, int value
, int pcrel
)
932 code
->exp
= mkexpr (value
, symbol_find_or_make (symbol
));
938 gencode (unsigned long x
)
940 INSTR_T cell
= obstack_alloc (&mempool
, sizeof (struct bfin_insn
));
941 memset (cell
, 0, sizeof (struct bfin_insn
));
953 return obstack_alloc (&mempool
, n
);
957 Expr_Node_Create (Expr_Node_Type type
,
958 Expr_Node_Value value
,
959 Expr_Node
*Left_Child
,
960 Expr_Node
*Right_Child
)
964 Expr_Node
*node
= (Expr_Node
*) allocate (sizeof (Expr_Node
));
967 node
->Left_Child
= Left_Child
;
968 node
->Right_Child
= Right_Child
;
972 static const char *con
= ".__constant";
973 static const char *op
= ".__operator";
974 static INSTR_T
Expr_Node_Gen_Reloc_R (Expr_Node
* head
);
975 INSTR_T
Expr_Node_Gen_Reloc (Expr_Node
*head
, int parent_reloc
);
978 Expr_Node_Gen_Reloc (Expr_Node
* head
, int parent_reloc
)
980 /* Top level reloction expression generator VDSP style.
981 If the relocation is just by itself, generate one item
982 else generate this convoluted expression. */
984 INSTR_T note
= NULL_CODE
;
985 INSTR_T note1
= NULL_CODE
;
986 int pcrel
= 1; /* Is the parent reloc pcrelative?
987 This calculation here and HOWTO should match. */
991 /* If it's 32 bit quantity then 16bit code needs to be added. */
994 if (head
->type
== Expr_Node_Constant
)
996 /* If note1 is not null code, we have to generate a right
997 aligned value for the constant. Otherwise the reloc is
998 a part of the basic command and the yacc file
1000 value
= head
->value
.i_value
;
1002 switch (parent_reloc
)
1004 /* Some relocations will need to allocate extra words. */
1005 case BFD_RELOC_BFIN_16_IMM
:
1006 case BFD_RELOC_BFIN_16_LOW
:
1007 case BFD_RELOC_BFIN_16_HIGH
:
1008 note1
= conscode (gencode (value
), NULL_CODE
);
1011 case BFD_RELOC_BFIN_PLTPC
:
1012 note1
= conscode (gencode (value
), NULL_CODE
);
1016 case BFD_RELOC_BFIN_GOT
:
1017 case BFD_RELOC_BFIN_GOT17M4
:
1018 case BFD_RELOC_BFIN_FUNCDESC_GOT17M4
:
1019 note1
= conscode (gencode (value
), NULL_CODE
);
1022 case BFD_RELOC_24_PCREL
:
1023 case BFD_RELOC_BFIN_24_PCREL_JUMP_L
:
1024 case BFD_RELOC_BFIN_24_PCREL_CALL_X
:
1025 /* These offsets are even numbered pcrel. */
1026 note1
= conscode (gencode (value
>> 1), NULL_CODE
);
1032 if (head
->type
== Expr_Node_Constant
)
1034 else if (head
->type
== Expr_Node_Reloc
)
1036 note
= note_reloc1 (gencode (0), head
->value
.s_value
, parent_reloc
, pcrel
);
1037 if (note1
!= NULL_CODE
)
1038 note
= conscode (note1
, note
);
1040 else if (head
->type
== Expr_Node_Binop
1041 && (head
->value
.op_value
== Expr_Op_Type_Add
1042 || head
->value
.op_value
== Expr_Op_Type_Sub
)
1043 && head
->Left_Child
->type
== Expr_Node_Reloc
1044 && head
->Right_Child
->type
== Expr_Node_Constant
)
1046 int val
= head
->Right_Child
->value
.i_value
;
1047 if (head
->value
.op_value
== Expr_Op_Type_Sub
)
1049 note
= conscode (note_reloc2 (gencode (0), head
->Left_Child
->value
.s_value
,
1050 parent_reloc
, val
, 0),
1052 if (note1
!= NULL_CODE
)
1053 note
= conscode (note1
, note
);
1057 /* Call the recursive function. */
1058 note
= note_reloc1 (gencode (0), op
, parent_reloc
, pcrel
);
1059 if (note1
!= NULL_CODE
)
1060 note
= conscode (note1
, note
);
1061 note
= conctcode (Expr_Node_Gen_Reloc_R (head
), note
);
1067 Expr_Node_Gen_Reloc_R (Expr_Node
* head
)
1075 case Expr_Node_Constant
:
1076 note
= conscode (note_reloc2 (gencode (0), con
, BFD_ARELOC_BFIN_CONST
, head
->value
.i_value
, 0), NULL_CODE
);
1078 case Expr_Node_Reloc
:
1079 note
= conscode (note_reloc (gencode (0), head
, BFD_ARELOC_BFIN_PUSH
, 0), NULL_CODE
);
1081 case Expr_Node_Binop
:
1082 note1
= conctcode (Expr_Node_Gen_Reloc_R (head
->Left_Child
), Expr_Node_Gen_Reloc_R (head
->Right_Child
));
1083 switch (head
->value
.op_value
)
1085 case Expr_Op_Type_Add
:
1086 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_ADD
, 0), NULL_CODE
));
1088 case Expr_Op_Type_Sub
:
1089 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_SUB
, 0), NULL_CODE
));
1091 case Expr_Op_Type_Mult
:
1092 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_MULT
, 0), NULL_CODE
));
1094 case Expr_Op_Type_Div
:
1095 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_DIV
, 0), NULL_CODE
));
1097 case Expr_Op_Type_Mod
:
1098 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_MOD
, 0), NULL_CODE
));
1100 case Expr_Op_Type_Lshift
:
1101 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_LSHIFT
, 0), NULL_CODE
));
1103 case Expr_Op_Type_Rshift
:
1104 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_RSHIFT
, 0), NULL_CODE
));
1106 case Expr_Op_Type_BAND
:
1107 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_AND
, 0), NULL_CODE
));
1109 case Expr_Op_Type_BOR
:
1110 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_OR
, 0), NULL_CODE
));
1112 case Expr_Op_Type_BXOR
:
1113 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_XOR
, 0), NULL_CODE
));
1115 case Expr_Op_Type_LAND
:
1116 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_LAND
, 0), NULL_CODE
));
1118 case Expr_Op_Type_LOR
:
1119 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_LOR
, 0), NULL_CODE
));
1122 fprintf (stderr
, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__
, __LINE__
);
1127 case Expr_Node_Unop
:
1128 note1
= conscode (Expr_Node_Gen_Reloc_R (head
->Left_Child
), NULL_CODE
);
1129 switch (head
->value
.op_value
)
1131 case Expr_Op_Type_NEG
:
1132 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_NEG
, 0), NULL_CODE
));
1134 case Expr_Op_Type_COMP
:
1135 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_COMP
, 0), NULL_CODE
));
1138 fprintf (stderr
, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__
, __LINE__
);
1142 fprintf (stderr
, "%s:%d:Unknown node expression found during " "arithmetic relocation generation", __FILE__
, __LINE__
);
1147 /* Blackfin opcode generation. */
1149 /* These functions are called by the generated parser
1150 (from bfin-parse.y), the register type classification
1151 happens in bfin-lex.l. */
1153 #include "bfin-aux.h"
1154 #include "opcode/bfin.h"
1156 #define INIT(t) t c_code = init_##t
1157 #define ASSIGN(x) c_code.opcode |= ((x & c_code.mask_##x)<<c_code.bits_##x)
1158 #define ASSIGNF(x,f) c_code.opcode |= ((x & c_code.mask_##f)<<c_code.bits_##f)
1159 #define ASSIGN_R(x) c_code.opcode |= (((x ? (x->regno & CODE_MASK) : 0) & c_code.mask_##x)<<c_code.bits_##x)
1161 #define HI(x) ((x >> 16) & 0xffff)
1162 #define LO(x) ((x ) & 0xffff)
1164 #define GROUP(x) ((x->regno & CLASS_MASK) >> 4)
1166 #define GEN_OPCODE32() \
1167 conscode (gencode (HI (c_code.opcode)), \
1168 conscode (gencode (LO (c_code.opcode)), NULL_CODE))
1170 #define GEN_OPCODE16() \
1171 conscode (gencode (c_code.opcode), NULL_CODE)
1174 /* 32 BIT INSTRUCTIONS. */
1177 /* DSP32 instruction generation. */
1180 bfin_gen_dsp32mac (int op1
, int MM
, int mmod
, int w1
, int P
,
1181 int h01
, int h11
, int h00
, int h10
, int op0
,
1182 REG_T dst
, REG_T src0
, REG_T src1
, int w0
)
1198 /* If we have full reg assignments, mask out LSB to encode
1199 single or simultaneous even/odd register moves. */
1209 return GEN_OPCODE32 ();
1213 bfin_gen_dsp32mult (int op1
, int MM
, int mmod
, int w1
, int P
,
1214 int h01
, int h11
, int h00
, int h10
, int op0
,
1215 REG_T dst
, REG_T src0
, REG_T src1
, int w0
)
1240 return GEN_OPCODE32 ();
1244 bfin_gen_dsp32alu (int HL
, int aopcde
, int aop
, int s
, int x
,
1245 REG_T dst0
, REG_T dst1
, REG_T src0
, REG_T src1
)
1259 return GEN_OPCODE32 ();
1263 bfin_gen_dsp32shift (int sopcde
, REG_T dst0
, REG_T src0
,
1264 REG_T src1
, int sop
, int HLs
)
1276 return GEN_OPCODE32 ();
1280 bfin_gen_dsp32shiftimm (int sopcde
, REG_T dst0
, int immag
,
1281 REG_T src1
, int sop
, int HLs
)
1283 INIT (DSP32ShiftImm
);
1293 return GEN_OPCODE32 ();
1299 bfin_gen_loopsetup (Expr_Node
* psoffset
, REG_T c
, int rop
,
1300 Expr_Node
* peoffset
, REG_T reg
)
1302 int soffset
, eoffset
;
1305 soffset
= (EXPR_VALUE (psoffset
) >> 1);
1307 eoffset
= (EXPR_VALUE (peoffset
) >> 1);
1314 conscode (gencode (HI (c_code
.opcode
)),
1315 conctcode (Expr_Node_Gen_Reloc (psoffset
, BFD_RELOC_BFIN_5_PCREL
),
1316 conctcode (gencode (LO (c_code
.opcode
)), Expr_Node_Gen_Reloc (peoffset
, BFD_RELOC_BFIN_11_PCREL
))));
1323 bfin_gen_calla (Expr_Node
* addr
, int S
)
1331 case 0 : rel
= BFD_RELOC_BFIN_24_PCREL_JUMP_L
; break;
1332 case 1 : rel
= BFD_RELOC_24_PCREL
; break;
1333 case 2 : rel
= BFD_RELOC_BFIN_PLTPC
; break;
1339 val
= EXPR_VALUE (addr
) >> 1;
1340 high_val
= val
>> 16;
1342 return conscode (gencode (HI (c_code
.opcode
) | (high_val
& 0xff)),
1343 Expr_Node_Gen_Reloc (addr
, rel
));
1347 bfin_gen_linkage (int R
, int framesize
)
1354 return GEN_OPCODE32 ();
1358 /* Load and Store. */
1361 bfin_gen_ldimmhalf (REG_T reg
, int H
, int S
, int Z
, Expr_Node
* phword
, int rel
)
1364 unsigned val
= EXPR_VALUE (phword
);
1372 grp
= (GROUP (reg
));
1376 return conscode (gencode (HI (c_code
.opcode
)), Expr_Node_Gen_Reloc (phword
, BFD_RELOC_BFIN_16_IMM
));
1380 return conscode (gencode (HI (c_code
.opcode
)), Expr_Node_Gen_Reloc (phword
, IS_H (*reg
) ? BFD_RELOC_BFIN_16_HIGH
: BFD_RELOC_BFIN_16_LOW
));
1387 return GEN_OPCODE32 ();
1391 bfin_gen_ldstidxi (REG_T ptr
, REG_T reg
, int W
, int sz
, int Z
, Expr_Node
* poffset
)
1395 if (!IS_PREG (*ptr
) || (!IS_DREG (*reg
) && !Z
))
1397 fprintf (stderr
, "Warning: possible mixup of Preg/Dreg\n");
1408 if (poffset
->type
!= Expr_Node_Constant
)
1410 /* a GOT relocation such as R0 = [P5 + symbol@GOT] */
1411 /* distinguish between R0 = [P5 + symbol@GOT] and
1412 P5 = [P5 + _current_shared_library_p5_offset_]
1414 if (poffset
->type
== Expr_Node_Reloc
1415 && !strcmp (poffset
->value
.s_value
,
1416 "_current_shared_library_p5_offset_"))
1418 return conscode (gencode (HI (c_code
.opcode
)),
1419 Expr_Node_Gen_Reloc(poffset
, BFD_RELOC_16
));
1421 else if (poffset
->type
!= Expr_Node_GOT_Reloc
)
1424 return conscode (gencode (HI (c_code
.opcode
)),
1425 Expr_Node_Gen_Reloc(poffset
->Left_Child
,
1426 poffset
->value
.i_value
));
1432 { /* load/store access size */
1433 case 0: /* 32 bit */
1434 value
= EXPR_VALUE (poffset
) >> 2;
1436 case 1: /* 16 bit */
1437 value
= EXPR_VALUE (poffset
) >> 1;
1440 value
= EXPR_VALUE (poffset
);
1446 offset
= (value
& 0xffff);
1448 return GEN_OPCODE32 ();
1454 bfin_gen_ldst (REG_T ptr
, REG_T reg
, int aop
, int sz
, int Z
, int W
)
1458 if (!IS_PREG (*ptr
) || (!IS_DREG (*reg
) && !Z
))
1460 fprintf (stderr
, "Warning: possible mixup of Preg/Dreg\n");
1471 return GEN_OPCODE16 ();
1475 bfin_gen_ldstii (REG_T ptr
, REG_T reg
, Expr_Node
* poffset
, int W
, int opc
)
1481 if (!IS_PREG (*ptr
))
1483 fprintf (stderr
, "Warning: possible mixup of Preg/Dreg\n");
1491 value
= EXPR_VALUE (poffset
) >> 1;
1495 value
= EXPR_VALUE (poffset
) >> 2;
1507 return GEN_OPCODE16 ();
1511 bfin_gen_ldstiifp (REG_T sreg
, Expr_Node
* poffset
, int W
)
1513 /* Set bit 4 if it's a Preg. */
1514 int reg
= (sreg
->regno
& CODE_MASK
) | (IS_PREG (*sreg
) ? 0x8 : 0x0);
1515 int offset
= ((~(EXPR_VALUE (poffset
) >> 2)) & 0x1f) + 1;
1521 return GEN_OPCODE16 ();
1525 bfin_gen_ldstpmod (REG_T ptr
, REG_T reg
, int aop
, int W
, REG_T idx
)
1535 return GEN_OPCODE16 ();
1539 bfin_gen_dspldst (REG_T i
, REG_T reg
, int aop
, int W
, int m
)
1549 return GEN_OPCODE16 ();
1553 bfin_gen_logi2op (int opc
, int src
, int dst
)
1561 return GEN_OPCODE16 ();
1565 bfin_gen_brcc (int T
, int B
, Expr_Node
* poffset
)
1572 offset
= ((EXPR_VALUE (poffset
) >> 1));
1574 return conscode (gencode (c_code
.opcode
), Expr_Node_Gen_Reloc (poffset
, BFD_RELOC_BFIN_10_PCREL
));
1578 bfin_gen_ujump (Expr_Node
* poffset
)
1583 offset
= ((EXPR_VALUE (poffset
) >> 1));
1586 return conscode (gencode (c_code
.opcode
),
1587 Expr_Node_Gen_Reloc (
1588 poffset
, BFD_RELOC_BFIN_12_PCREL_JUMP_S
));
1592 bfin_gen_alu2op (REG_T dst
, REG_T src
, int opc
)
1600 return GEN_OPCODE16 ();
1604 bfin_gen_compi2opd (REG_T dst
, int src
, int opc
)
1612 return GEN_OPCODE16 ();
1616 bfin_gen_compi2opp (REG_T dst
, int src
, int opc
)
1624 return GEN_OPCODE16 ();
1628 bfin_gen_dagmodik (REG_T i
, int opc
)
1635 return GEN_OPCODE16 ();
1639 bfin_gen_dagmodim (REG_T i
, REG_T m
, int opc
, int br
)
1648 return GEN_OPCODE16 ();
1652 bfin_gen_ptr2op (REG_T dst
, REG_T src
, int opc
)
1660 return GEN_OPCODE16 ();
1664 bfin_gen_comp3op (REG_T src0
, REG_T src1
, REG_T dst
, int opc
)
1673 return GEN_OPCODE16 ();
1677 bfin_gen_ccflag (REG_T x
, int y
, int opc
, int I
, int G
)
1687 return GEN_OPCODE16 ();
1691 bfin_gen_ccmv (REG_T src
, REG_T dst
, int T
)
1704 return GEN_OPCODE16 ();
1708 bfin_gen_cc2stat (int cbit
, int opc
, int D
)
1716 return GEN_OPCODE16 ();
1720 bfin_gen_regmv (REG_T src
, REG_T dst
)
1733 return GEN_OPCODE16 ();
1737 bfin_gen_cc2dreg (int opc
, REG_T reg
)
1744 return GEN_OPCODE16 ();
1748 bfin_gen_progctrl (int prgfunc
, int poprnd
)
1755 return GEN_OPCODE16 ();
1759 bfin_gen_cactrl (REG_T reg
, int a
, int opc
)
1767 return GEN_OPCODE16 ();
1771 bfin_gen_pushpopmultiple (int dr
, int pr
, int d
, int p
, int W
)
1773 INIT (PushPopMultiple
);
1781 return GEN_OPCODE16 ();
1785 bfin_gen_pushpopreg (REG_T reg
, int W
)
1791 grp
= (GROUP (reg
));
1795 return GEN_OPCODE16 ();
1798 /* Pseudo Debugging Support. */
1801 bfin_gen_pseudodbg (int fn
, int reg
, int grp
)
1809 return GEN_OPCODE16 ();
1813 bfin_gen_pseudodbg_assert (int dbgop
, REG_T regtest
, int expected
)
1816 INIT (PseudoDbg_Assert
);
1820 grp
= GROUP (regtest
);
1824 return GEN_OPCODE32 ();
1828 bfin_gen_pseudochr (int ch
)
1834 return GEN_OPCODE16 ();
1837 /* Multiple instruction generation. */
1840 bfin_gen_multi_instr (INSTR_T dsp32
, INSTR_T dsp16_grp1
, INSTR_T dsp16_grp2
)
1844 /* If it's a 0, convert into MNOP. */
1848 SET_MULTI_INSTRUCTION_BIT (dsp32
);
1852 dsp32
= gencode (0xc803);
1853 walk
= gencode (0x1800);
1859 dsp16_grp1
= gencode (0x0000);
1864 dsp16_grp2
= gencode (0x0000);
1867 walk
->next
= dsp16_grp1
;
1868 dsp16_grp1
->next
= dsp16_grp2
;
1869 dsp16_grp2
->next
= NULL_CODE
;
1875 bfin_gen_loop (Expr_Node
*exp
, REG_T reg
, int rop
, REG_T preg
)
1877 const char *loopsym
;
1878 char *lbeginsym
, *lendsym
;
1879 Expr_Node_Value lbeginval
, lendval
;
1880 Expr_Node
*lbegin
, *lend
;
1883 loopsym
= exp
->value
.s_value
;
1884 lbeginsym
= (char *) xmalloc (strlen (loopsym
) + strlen ("__BEGIN") + 5);
1885 lendsym
= (char *) xmalloc (strlen (loopsym
) + strlen ("__END") + 5);
1890 strcat (lbeginsym
, "L$L$");
1891 strcat (lbeginsym
, loopsym
);
1892 strcat (lbeginsym
, "__BEGIN");
1894 strcat (lendsym
, "L$L$");
1895 strcat (lendsym
, loopsym
);
1896 strcat (lendsym
, "__END");
1898 lbeginval
.s_value
= lbeginsym
;
1899 lendval
.s_value
= lendsym
;
1901 lbegin
= Expr_Node_Create (Expr_Node_Reloc
, lbeginval
, NULL
, NULL
);
1902 lend
= Expr_Node_Create (Expr_Node_Reloc
, lendval
, NULL
, NULL
);
1904 sym
= symbol_find(loopsym
);
1905 if (!S_IS_LOCAL (sym
) || (S_IS_LOCAL (sym
) && !symbol_used_p (sym
)))
1906 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
1908 return bfin_gen_loopsetup (lbegin
, reg
, rop
, lend
, preg
);
1912 bfin_loop_attempt_create_label (Expr_Node
*exp
, int is_begin
)
1915 name
= fb_label_name (exp
->value
.i_value
, is_begin
);
1916 exp
->value
.s_value
= xstrdup (name
);
1917 exp
->type
= Expr_Node_Reloc
;
1921 bfin_loop_beginend (Expr_Node
*exp
, int begin
)
1923 const char *loopsym
;
1926 const char *suffix
= begin
? "__BEGIN" : "__END";
1928 loopsym
= exp
->value
.s_value
;
1929 label_name
= (char *) xmalloc (strlen (loopsym
) + strlen (suffix
) + 5);
1933 strcat (label_name
, "L$L$");
1934 strcat (label_name
, loopsym
);
1935 strcat (label_name
, suffix
);
1937 linelabel
= colon (label_name
);
1939 /* LOOP_END follows the last instruction in the loop.
1940 Adjust label address. */
1942 ((struct local_symbol
*) linelabel
)->lsy_value
-= last_insn_size
;
1946 bfin_eol_in_insn (char *line
)
1948 /* Allow a new-line to appear in the middle of a multi-issue instruction. */
1955 /* A semi-colon followed by a newline is always the end of a line. */
1956 if (line
[-1] == ';')
1959 if (line
[-1] == '|')
1962 /* If the || is on the next line, there might be leading whitespace. */
1964 while (*temp
== ' ' || *temp
== '\t') temp
++;
1973 bfin_start_label (char *s
, char *ptr
)
1977 if (*s
== '(' || *s
== '[')
1986 bfin_force_relocation (struct fix
*fixp
)
1988 if (fixp
->fx_r_type
==BFD_RELOC_BFIN_16_LOW
1989 || fixp
->fx_r_type
== BFD_RELOC_BFIN_16_HIGH
)
1992 return generic_force_reloc (fixp
);
1995 /* This is a stripped down version of the disassembler. The only thing it
1996 does is return a mask of registers modified by an instruction. Only
1997 instructions that can occur in a parallel-issue bundle are handled, and
1998 only the registers that can cause a conflict are recorded. */
2000 #define DREG_MASK(n) (0x101 << (n))
2001 #define DREGH_MASK(n) (0x100 << (n))
2002 #define DREGL_MASK(n) (0x001 << (n))
2003 #define IREG_MASK(n) (1 << ((n) + 16))
2006 decode_ProgCtrl_0 (int iw0
)
2014 decode_LDSTpmod_0 (int iw0
)
2017 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2018 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
2019 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2020 int W
= ((iw0
>> LDSTpmod_W_bits
) & LDSTpmod_W_mask
);
2021 int aop
= ((iw0
>> LDSTpmod_aop_bits
) & LDSTpmod_aop_mask
);
2022 int idx
= ((iw0
>> LDSTpmod_idx_bits
) & LDSTpmod_idx_mask
);
2023 int ptr
= ((iw0
>> LDSTpmod_ptr_bits
) & LDSTpmod_ptr_mask
);
2024 int reg
= ((iw0
>> LDSTpmod_reg_bits
) & LDSTpmod_reg_mask
);
2026 if (aop
== 1 && W
== 0 && idx
== ptr
)
2027 return DREGL_MASK (reg
);
2028 else if (aop
== 2 && W
== 0 && idx
== ptr
)
2029 return DREGH_MASK (reg
);
2030 else if (aop
== 1 && W
== 1 && idx
== ptr
)
2032 else if (aop
== 2 && W
== 1 && idx
== ptr
)
2034 else if (aop
== 0 && W
== 0)
2035 return DREG_MASK (reg
);
2036 else if (aop
== 1 && W
== 0)
2037 return DREGL_MASK (reg
);
2038 else if (aop
== 2 && W
== 0)
2039 return DREGH_MASK (reg
);
2040 else if (aop
== 3 && W
== 0)
2041 return DREG_MASK (reg
);
2042 else if (aop
== 3 && W
== 1)
2043 return DREG_MASK (reg
);
2044 else if (aop
== 0 && W
== 1)
2046 else if (aop
== 1 && W
== 1)
2048 else if (aop
== 2 && W
== 1)
2057 decode_dagMODim_0 (int iw0
)
2060 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2061 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2062 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2063 int i
= ((iw0
>> DagMODim_i_bits
) & DagMODim_i_mask
);
2064 int opc
= ((iw0
>> DagMODim_op_bits
) & DagMODim_op_mask
);
2066 if (opc
== 0 || opc
== 1)
2067 return IREG_MASK (i
);
2075 decode_dagMODik_0 (int iw0
)
2078 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2079 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2080 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2081 int i
= ((iw0
>> DagMODik_i_bits
) & DagMODik_i_mask
);
2082 return IREG_MASK (i
);
2087 decode_dspLDST_0 (int iw0
)
2090 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2091 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2092 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2093 int i
= ((iw0
>> DspLDST_i_bits
) & DspLDST_i_mask
);
2094 int m
= ((iw0
>> DspLDST_m_bits
) & DspLDST_m_mask
);
2095 int W
= ((iw0
>> DspLDST_W_bits
) & DspLDST_W_mask
);
2096 int aop
= ((iw0
>> DspLDST_aop_bits
) & DspLDST_aop_mask
);
2097 int reg
= ((iw0
>> DspLDST_reg_bits
) & DspLDST_reg_mask
);
2099 if (aop
== 0 && W
== 0 && m
== 0)
2100 return DREG_MASK (reg
) | IREG_MASK (i
);
2101 else if (aop
== 0 && W
== 0 && m
== 1)
2102 return DREGL_MASK (reg
) | IREG_MASK (i
);
2103 else if (aop
== 0 && W
== 0 && m
== 2)
2104 return DREGH_MASK (reg
) | IREG_MASK (i
);
2105 else if (aop
== 1 && W
== 0 && m
== 0)
2106 return DREG_MASK (reg
) | IREG_MASK (i
);
2107 else if (aop
== 1 && W
== 0 && m
== 1)
2108 return DREGL_MASK (reg
) | IREG_MASK (i
);
2109 else if (aop
== 1 && W
== 0 && m
== 2)
2110 return DREGH_MASK (reg
) | IREG_MASK (i
);
2111 else if (aop
== 2 && W
== 0 && m
== 0)
2112 return DREG_MASK (reg
);
2113 else if (aop
== 2 && W
== 0 && m
== 1)
2114 return DREGL_MASK (reg
);
2115 else if (aop
== 2 && W
== 0 && m
== 2)
2116 return DREGH_MASK (reg
);
2117 else if (aop
== 0 && W
== 1 && m
== 0)
2118 return IREG_MASK (i
);
2119 else if (aop
== 0 && W
== 1 && m
== 1)
2120 return IREG_MASK (i
);
2121 else if (aop
== 0 && W
== 1 && m
== 2)
2122 return IREG_MASK (i
);
2123 else if (aop
== 1 && W
== 1 && m
== 0)
2124 return IREG_MASK (i
);
2125 else if (aop
== 1 && W
== 1 && m
== 1)
2126 return IREG_MASK (i
);
2127 else if (aop
== 1 && W
== 1 && m
== 2)
2128 return IREG_MASK (i
);
2129 else if (aop
== 2 && W
== 1 && m
== 0)
2131 else if (aop
== 2 && W
== 1 && m
== 1)
2133 else if (aop
== 2 && W
== 1 && m
== 2)
2135 else if (aop
== 3 && W
== 0)
2136 return DREG_MASK (reg
) | IREG_MASK (i
);
2137 else if (aop
== 3 && W
== 1)
2138 return IREG_MASK (i
);
2145 decode_LDST_0 (int iw0
)
2148 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2149 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2150 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2151 int Z
= ((iw0
>> LDST_Z_bits
) & LDST_Z_mask
);
2152 int W
= ((iw0
>> LDST_W_bits
) & LDST_W_mask
);
2153 int sz
= ((iw0
>> LDST_sz_bits
) & LDST_sz_mask
);
2154 int aop
= ((iw0
>> LDST_aop_bits
) & LDST_aop_mask
);
2155 int reg
= ((iw0
>> LDST_reg_bits
) & LDST_reg_mask
);
2157 if (aop
== 0 && sz
== 0 && Z
== 0 && W
== 0)
2158 return DREG_MASK (reg
);
2159 else if (aop
== 0 && sz
== 0 && Z
== 1 && W
== 0)
2161 else if (aop
== 0 && sz
== 1 && Z
== 0 && W
== 0)
2162 return DREG_MASK (reg
);
2163 else if (aop
== 0 && sz
== 1 && Z
== 1 && W
== 0)
2164 return DREG_MASK (reg
);
2165 else if (aop
== 0 && sz
== 2 && Z
== 0 && W
== 0)
2166 return DREG_MASK (reg
);
2167 else if (aop
== 0 && sz
== 2 && Z
== 1 && W
== 0)
2168 return DREG_MASK (reg
);
2169 else if (aop
== 1 && sz
== 0 && Z
== 0 && W
== 0)
2170 return DREG_MASK (reg
);
2171 else if (aop
== 1 && sz
== 0 && Z
== 1 && W
== 0)
2173 else if (aop
== 1 && sz
== 1 && Z
== 0 && W
== 0)
2174 return DREG_MASK (reg
);
2175 else if (aop
== 1 && sz
== 1 && Z
== 1 && W
== 0)
2176 return DREG_MASK (reg
);
2177 else if (aop
== 1 && sz
== 2 && Z
== 0 && W
== 0)
2178 return DREG_MASK (reg
);
2179 else if (aop
== 1 && sz
== 2 && Z
== 1 && W
== 0)
2180 return DREG_MASK (reg
);
2181 else if (aop
== 2 && sz
== 0 && Z
== 0 && W
== 0)
2182 return DREG_MASK (reg
);
2183 else if (aop
== 2 && sz
== 0 && Z
== 1 && W
== 0)
2185 else if (aop
== 2 && sz
== 1 && Z
== 0 && W
== 0)
2186 return DREG_MASK (reg
);
2187 else if (aop
== 2 && sz
== 1 && Z
== 1 && W
== 0)
2188 return DREG_MASK (reg
);
2189 else if (aop
== 2 && sz
== 2 && Z
== 0 && W
== 0)
2190 return DREG_MASK (reg
);
2191 else if (aop
== 2 && sz
== 2 && Z
== 1 && W
== 0)
2192 return DREG_MASK (reg
);
2193 else if (aop
== 0 && sz
== 0 && Z
== 0 && W
== 1)
2195 else if (aop
== 0 && sz
== 0 && Z
== 1 && W
== 1)
2197 else if (aop
== 0 && sz
== 1 && Z
== 0 && W
== 1)
2199 else if (aop
== 0 && sz
== 2 && Z
== 0 && W
== 1)
2201 else if (aop
== 1 && sz
== 0 && Z
== 0 && W
== 1)
2203 else if (aop
== 1 && sz
== 0 && Z
== 1 && W
== 1)
2205 else if (aop
== 1 && sz
== 1 && Z
== 0 && W
== 1)
2207 else if (aop
== 1 && sz
== 2 && Z
== 0 && W
== 1)
2209 else if (aop
== 2 && sz
== 0 && Z
== 0 && W
== 1)
2211 else if (aop
== 2 && sz
== 0 && Z
== 1 && W
== 1)
2213 else if (aop
== 2 && sz
== 1 && Z
== 0 && W
== 1)
2215 else if (aop
== 2 && sz
== 2 && Z
== 0 && W
== 1)
2222 decode_LDSTiiFP_0 (int iw0
)
2225 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2226 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2227 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2228 int reg
= ((iw0
>> LDSTiiFP_reg_bits
) & LDSTiiFP_reg_mask
);
2229 int W
= ((iw0
>> LDSTiiFP_W_bits
) & LDSTiiFP_W_mask
);
2232 return reg
< 8 ? DREG_MASK (reg
) : 0;
2238 decode_LDSTii_0 (int iw0
)
2241 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2242 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2243 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2244 int reg
= ((iw0
>> LDSTii_reg_bit
) & LDSTii_reg_mask
);
2245 int opc
= ((iw0
>> LDSTii_op_bit
) & LDSTii_op_mask
);
2246 int W
= ((iw0
>> LDSTii_W_bit
) & LDSTii_W_mask
);
2248 if (W
== 0 && opc
!= 3)
2249 return DREG_MASK (reg
);
2250 else if (W
== 0 && opc
== 3)
2252 else if (W
== 1 && opc
== 0)
2254 else if (W
== 1 && opc
== 1)
2256 else if (W
== 1 && opc
== 3)
2263 decode_dsp32mac_0 (int iw0
, int iw1
)
2267 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2268 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2269 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2270 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2271 int op1
= ((iw0
>> (DSP32Mac_op1_bits
- 16)) & DSP32Mac_op1_mask
);
2272 int w1
= ((iw0
>> (DSP32Mac_w1_bits
- 16)) & DSP32Mac_w1_mask
);
2273 int P
= ((iw0
>> (DSP32Mac_p_bits
- 16)) & DSP32Mac_p_mask
);
2274 int mmod
= ((iw0
>> (DSP32Mac_mmod_bits
- 16)) & DSP32Mac_mmod_mask
);
2275 int w0
= ((iw1
>> DSP32Mac_w0_bits
) & DSP32Mac_w0_mask
);
2276 int MM
= ((iw1
>> DSP32Mac_MM_bits
) & DSP32Mac_MM_mask
);
2277 int dst
= ((iw1
>> DSP32Mac_dst_bits
) & DSP32Mac_dst_mask
);
2278 int op0
= ((iw1
>> DSP32Mac_op0_bits
) & DSP32Mac_op0_mask
);
2280 if (w0
== 0 && w1
== 0 && op1
== 3 && op0
== 3)
2286 if ((w1
|| w0
) && mmod
== M_W32
)
2289 if (((1 << mmod
) & (P
? 0x131b : 0x1b5f)) == 0)
2292 if (w1
== 1 || op1
!= 3)
2297 return DREG_MASK (dst
+ 1);
2299 return DREGH_MASK (dst
);
2303 if (w0
== 1 || op0
!= 3)
2308 return DREG_MASK (dst
);
2310 return DREGL_MASK (dst
);
2318 decode_dsp32mult_0 (int iw0
, int iw1
)
2321 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2322 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
2323 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2324 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2325 int w1
= ((iw0
>> (DSP32Mac_w1_bits
- 16)) & DSP32Mac_w1_mask
);
2326 int P
= ((iw0
>> (DSP32Mac_p_bits
- 16)) & DSP32Mac_p_mask
);
2327 int mmod
= ((iw0
>> (DSP32Mac_mmod_bits
- 16)) & DSP32Mac_mmod_mask
);
2328 int w0
= ((iw1
>> DSP32Mac_w0_bits
) & DSP32Mac_w0_mask
);
2329 int dst
= ((iw1
>> DSP32Mac_dst_bits
) & DSP32Mac_dst_mask
);
2332 if (w1
== 0 && w0
== 0)
2335 if (((1 << mmod
) & (P
? 0x313 : 0x1b57)) == 0)
2341 return DREG_MASK (dst
| 1);
2343 return DREGH_MASK (dst
);
2349 return DREG_MASK (dst
);
2351 return DREGL_MASK (dst
);
2358 decode_dsp32alu_0 (int iw0
, int iw1
)
2361 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2362 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
2363 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
2364 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2365 int s
= ((iw1
>> DSP32Alu_s_bits
) & DSP32Alu_s_mask
);
2366 int x
= ((iw1
>> DSP32Alu_x_bits
) & DSP32Alu_x_mask
);
2367 int aop
= ((iw1
>> DSP32Alu_aop_bits
) & DSP32Alu_aop_mask
);
2368 int dst0
= ((iw1
>> DSP32Alu_dst0_bits
) & DSP32Alu_dst0_mask
);
2369 int dst1
= ((iw1
>> DSP32Alu_dst1_bits
) & DSP32Alu_dst1_mask
);
2370 int HL
= ((iw0
>> (DSP32Alu_HL_bits
- 16)) & DSP32Alu_HL_mask
);
2371 int aopcde
= ((iw0
>> (DSP32Alu_aopcde_bits
- 16)) & DSP32Alu_aopcde_mask
);
2373 if (aop
== 0 && aopcde
== 9 && s
== 0)
2375 else if (aop
== 2 && aopcde
== 9 && HL
== 0 && s
== 0)
2377 else if (aop
>= x
* 2 && aopcde
== 5)
2378 return HL
? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2379 else if (HL
== 0 && aopcde
== 2)
2380 return DREGL_MASK (dst0
);
2381 else if (HL
== 1 && aopcde
== 2)
2382 return DREGH_MASK (dst0
);
2383 else if (HL
== 0 && aopcde
== 3)
2384 return DREGL_MASK (dst0
);
2385 else if (HL
== 1 && aopcde
== 3)
2386 return DREGH_MASK (dst0
);
2388 else if (aop
== 0 && aopcde
== 9 && s
== 1)
2390 else if (aop
== 1 && aopcde
== 9 && s
== 0)
2392 else if (aop
== 2 && aopcde
== 9 && s
== 1)
2394 else if (aop
== 3 && aopcde
== 9 && s
== 0)
2396 else if (aopcde
== 8)
2398 else if (aop
== 0 && aopcde
== 11)
2399 return DREG_MASK (dst0
);
2400 else if (aop
== 1 && aopcde
== 11)
2401 return HL
? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2402 else if (aopcde
== 11)
2404 else if (aopcde
== 22)
2405 return DREG_MASK (dst0
);
2407 else if ((aop
== 0 || aop
== 1) && aopcde
== 14)
2409 else if (aop
== 3 && HL
== 0 && aopcde
== 14)
2412 else if (aop
== 3 && HL
== 0 && aopcde
== 15)
2413 return DREG_MASK (dst0
);
2415 else if (aop
== 1 && aopcde
== 16)
2418 else if (aop
== 0 && aopcde
== 16)
2421 else if (aop
== 3 && HL
== 0 && aopcde
== 16)
2424 else if (aop
== 3 && HL
== 0 && aopcde
== 7)
2425 return DREG_MASK (dst0
);
2426 else if ((aop
== 0 || aop
== 1 || aop
== 2) && aopcde
== 7)
2427 return DREG_MASK (dst0
);
2429 else if (aop
== 0 && aopcde
== 12)
2430 return DREG_MASK (dst0
);
2431 else if (aop
== 1 && aopcde
== 12)
2432 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2433 else if (aop
== 3 && aopcde
== 12)
2434 return HL
? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2436 else if (aopcde
== 0)
2437 return DREG_MASK (dst0
);
2438 else if (aopcde
== 1)
2439 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2441 else if (aop
== 0 && aopcde
== 10)
2442 return DREGL_MASK (dst0
);
2443 else if (aop
== 1 && aopcde
== 10)
2444 return DREGL_MASK (dst0
);
2446 else if ((aop
== 1 || aop
== 0) && aopcde
== 4)
2447 return DREG_MASK (dst0
);
2448 else if (aop
== 2 && aopcde
== 4)
2449 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2451 else if (aop
== 0 && aopcde
== 17)
2452 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2453 else if (aop
== 1 && aopcde
== 17)
2454 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2455 else if (aop
== 0 && aopcde
== 18)
2457 else if (aop
== 3 && aopcde
== 18)
2460 else if ((aop
== 0 || aop
== 1 || aop
== 2) && aopcde
== 6)
2461 return DREG_MASK (dst0
);
2463 else if ((aop
== 0 || aop
== 1) && aopcde
== 20)
2464 return DREG_MASK (dst0
);
2466 else if ((aop
== 0 || aop
== 1) && aopcde
== 21)
2467 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2469 else if (aop
== 0 && aopcde
== 23 && HL
== 1)
2470 return DREG_MASK (dst0
);
2471 else if (aop
== 0 && aopcde
== 23 && HL
== 0)
2472 return DREG_MASK (dst0
);
2474 else if (aop
== 0 && aopcde
== 24)
2475 return DREG_MASK (dst0
);
2476 else if (aop
== 1 && aopcde
== 24)
2477 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2478 else if (aopcde
== 13)
2479 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2487 decode_dsp32shift_0 (int iw0
, int iw1
)
2490 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2491 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
2492 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
2493 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2494 int HLs
= ((iw1
>> DSP32Shift_HLs_bits
) & DSP32Shift_HLs_mask
);
2495 int sop
= ((iw1
>> DSP32Shift_sop_bits
) & DSP32Shift_sop_mask
);
2496 int src0
= ((iw1
>> DSP32Shift_src0_bits
) & DSP32Shift_src0_mask
);
2497 int src1
= ((iw1
>> DSP32Shift_src1_bits
) & DSP32Shift_src1_mask
);
2498 int dst0
= ((iw1
>> DSP32Shift_dst0_bits
) & DSP32Shift_dst0_mask
);
2499 int sopcde
= ((iw0
>> (DSP32Shift_sopcde_bits
- 16)) & DSP32Shift_sopcde_mask
);
2501 if (sop
== 0 && sopcde
== 0)
2502 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2503 else if (sop
== 1 && sopcde
== 0)
2504 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2505 else if (sop
== 2 && sopcde
== 0)
2506 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2507 else if (sop
== 0 && sopcde
== 3)
2509 else if (sop
== 1 && sopcde
== 3)
2511 else if (sop
== 2 && sopcde
== 3)
2513 else if (sop
== 3 && sopcde
== 3)
2514 return DREG_MASK (dst0
);
2515 else if (sop
== 0 && sopcde
== 1)
2516 return DREG_MASK (dst0
);
2517 else if (sop
== 1 && sopcde
== 1)
2518 return DREG_MASK (dst0
);
2519 else if (sop
== 2 && sopcde
== 1)
2520 return DREG_MASK (dst0
);
2521 else if (sopcde
== 2)
2522 return DREG_MASK (dst0
);
2523 else if (sopcde
== 4)
2524 return DREG_MASK (dst0
);
2525 else if (sop
== 0 && sopcde
== 5)
2526 return DREGL_MASK (dst0
);
2527 else if (sop
== 1 && sopcde
== 5)
2528 return DREGL_MASK (dst0
);
2529 else if (sop
== 2 && sopcde
== 5)
2530 return DREGL_MASK (dst0
);
2531 else if (sop
== 0 && sopcde
== 6)
2532 return DREGL_MASK (dst0
);
2533 else if (sop
== 1 && sopcde
== 6)
2534 return DREGL_MASK (dst0
);
2535 else if (sop
== 3 && sopcde
== 6)
2536 return DREGL_MASK (dst0
);
2537 else if (sop
== 0 && sopcde
== 7)
2538 return DREGL_MASK (dst0
);
2539 else if (sop
== 1 && sopcde
== 7)
2540 return DREGL_MASK (dst0
);
2541 else if (sop
== 2 && sopcde
== 7)
2542 return DREGL_MASK (dst0
);
2543 else if (sop
== 3 && sopcde
== 7)
2544 return DREGL_MASK (dst0
);
2545 else if (sop
== 0 && sopcde
== 8)
2546 return DREG_MASK (src0
) | DREG_MASK (src1
);
2549 OUTS (outf
, "BITMUX (");
2550 OUTS (outf
, dregs (src0
));
2552 OUTS (outf
, dregs (src1
));
2553 OUTS (outf
, ", A0) (ASR)");
2556 else if (sop
== 1 && sopcde
== 8)
2557 return DREG_MASK (src0
) | DREG_MASK (src1
);
2560 OUTS (outf
, "BITMUX (");
2561 OUTS (outf
, dregs (src0
));
2563 OUTS (outf
, dregs (src1
));
2564 OUTS (outf
, ", A0) (ASL)");
2567 else if (sopcde
== 9)
2568 return sop
< 2 ? DREGL_MASK (dst0
) : DREG_MASK (dst0
);
2569 else if (sopcde
== 10)
2570 return DREG_MASK (dst0
);
2571 else if (sop
== 0 && sopcde
== 11)
2572 return DREGL_MASK (dst0
);
2573 else if (sop
== 1 && sopcde
== 11)
2574 return DREGL_MASK (dst0
);
2575 else if (sop
== 0 && sopcde
== 12)
2577 else if (sop
== 1 && sopcde
== 12)
2578 return DREGL_MASK (dst0
);
2579 else if (sop
== 0 && sopcde
== 13)
2580 return DREG_MASK (dst0
);
2581 else if (sop
== 1 && sopcde
== 13)
2582 return DREG_MASK (dst0
);
2583 else if (sop
== 2 && sopcde
== 13)
2584 return DREG_MASK (dst0
);
2590 decode_dsp32shiftimm_0 (int iw0
, int iw1
)
2593 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2594 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
2595 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
2596 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2597 int sop
= ((iw1
>> DSP32ShiftImm_sop_bits
) & DSP32ShiftImm_sop_mask
);
2598 int bit8
= ((iw1
>> 8) & 0x1);
2599 int dst0
= ((iw1
>> DSP32ShiftImm_dst0_bits
) & DSP32ShiftImm_dst0_mask
);
2600 int sopcde
= ((iw0
>> (DSP32ShiftImm_sopcde_bits
- 16)) & DSP32ShiftImm_sopcde_mask
);
2601 int HLs
= ((iw1
>> DSP32ShiftImm_HLs_bits
) & DSP32ShiftImm_HLs_mask
);
2604 if (sop
== 0 && sopcde
== 0)
2605 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2606 else if (sop
== 1 && sopcde
== 0 && bit8
== 0)
2607 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2608 else if (sop
== 1 && sopcde
== 0 && bit8
== 1)
2609 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2610 else if (sop
== 2 && sopcde
== 0 && bit8
== 0)
2611 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2612 else if (sop
== 2 && sopcde
== 0 && bit8
== 1)
2613 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2614 else if (sop
== 2 && sopcde
== 3 && HLs
== 1)
2616 else if (sop
== 0 && sopcde
== 3 && HLs
== 0 && bit8
== 0)
2618 else if (sop
== 0 && sopcde
== 3 && HLs
== 0 && bit8
== 1)
2620 else if (sop
== 0 && sopcde
== 3 && HLs
== 1 && bit8
== 0)
2622 else if (sop
== 0 && sopcde
== 3 && HLs
== 1 && bit8
== 1)
2624 else if (sop
== 1 && sopcde
== 3 && HLs
== 0)
2626 else if (sop
== 1 && sopcde
== 3 && HLs
== 1)
2628 else if (sop
== 2 && sopcde
== 3 && HLs
== 0)
2630 else if (sop
== 1 && sopcde
== 1 && bit8
== 0)
2631 return DREG_MASK (dst0
);
2632 else if (sop
== 1 && sopcde
== 1 && bit8
== 1)
2633 return DREG_MASK (dst0
);
2634 else if (sop
== 2 && sopcde
== 1 && bit8
== 1)
2635 return DREG_MASK (dst0
);
2636 else if (sop
== 2 && sopcde
== 1 && bit8
== 0)
2637 return DREG_MASK (dst0
);
2638 else if (sop
== 0 && sopcde
== 1)
2639 return DREG_MASK (dst0
);
2640 else if (sop
== 1 && sopcde
== 2)
2641 return DREG_MASK (dst0
);
2642 else if (sop
== 2 && sopcde
== 2 && bit8
== 1)
2643 return DREG_MASK (dst0
);
2644 else if (sop
== 2 && sopcde
== 2 && bit8
== 0)
2645 return DREG_MASK (dst0
);
2646 else if (sop
== 3 && sopcde
== 2)
2647 return DREG_MASK (dst0
);
2648 else if (sop
== 0 && sopcde
== 2)
2649 return DREG_MASK (dst0
);
2655 insn_regmask (int iw0
, int iw1
)
2657 if ((iw0
& 0xf7ff) == 0xc003 && iw1
== 0x1800)
2658 return 0; /* MNOP */
2659 else if ((iw0
& 0xff00) == 0x0000)
2660 return decode_ProgCtrl_0 (iw0
);
2661 else if ((iw0
& 0xffc0) == 0x0240)
2663 else if ((iw0
& 0xff80) == 0x0100)
2665 else if ((iw0
& 0xfe00) == 0x0400)
2667 else if ((iw0
& 0xfe00) == 0x0600)
2669 else if ((iw0
& 0xf800) == 0x0800)
2671 else if ((iw0
& 0xffe0) == 0x0200)
2673 else if ((iw0
& 0xff00) == 0x0300)
2675 else if ((iw0
& 0xf000) == 0x1000)
2677 else if ((iw0
& 0xf000) == 0x2000)
2679 else if ((iw0
& 0xf000) == 0x3000)
2681 else if ((iw0
& 0xfc00) == 0x4000)
2683 else if ((iw0
& 0xfe00) == 0x4400)
2685 else if ((iw0
& 0xf800) == 0x4800)
2687 else if ((iw0
& 0xf000) == 0x5000)
2689 else if ((iw0
& 0xf800) == 0x6000)
2691 else if ((iw0
& 0xf800) == 0x6800)
2693 else if ((iw0
& 0xf000) == 0x8000)
2694 return decode_LDSTpmod_0 (iw0
);
2695 else if ((iw0
& 0xff60) == 0x9e60)
2696 return decode_dagMODim_0 (iw0
);
2697 else if ((iw0
& 0xfff0) == 0x9f60)
2698 return decode_dagMODik_0 (iw0
);
2699 else if ((iw0
& 0xfc00) == 0x9c00)
2700 return decode_dspLDST_0 (iw0
);
2701 else if ((iw0
& 0xf000) == 0x9000)
2702 return decode_LDST_0 (iw0
);
2703 else if ((iw0
& 0xfc00) == 0xb800)
2704 return decode_LDSTiiFP_0 (iw0
);
2705 else if ((iw0
& 0xe000) == 0xA000)
2706 return decode_LDSTii_0 (iw0
);
2707 else if ((iw0
& 0xff80) == 0xe080 && (iw1
& 0x0C00) == 0x0000)
2709 else if ((iw0
& 0xff00) == 0xe100 && (iw1
& 0x0000) == 0x0000)
2711 else if ((iw0
& 0xfe00) == 0xe200 && (iw1
& 0x0000) == 0x0000)
2713 else if ((iw0
& 0xfc00) == 0xe400 && (iw1
& 0x0000) == 0x0000)
2715 else if ((iw0
& 0xfffe) == 0xe800 && (iw1
& 0x0000) == 0x0000)
2717 else if ((iw0
& 0xf600) == 0xc000 && (iw1
& 0x0000) == 0x0000)
2718 return decode_dsp32mac_0 (iw0
, iw1
);
2719 else if ((iw0
& 0xf600) == 0xc200 && (iw1
& 0x0000) == 0x0000)
2720 return decode_dsp32mult_0 (iw0
, iw1
);
2721 else if ((iw0
& 0xf7c0) == 0xc400 && (iw1
& 0x0000) == 0x0000)
2722 return decode_dsp32alu_0 (iw0
, iw1
);
2723 else if ((iw0
& 0xf780) == 0xc600 && (iw1
& 0x01c0) == 0x0000)
2724 return decode_dsp32shift_0 (iw0
, iw1
);
2725 else if ((iw0
& 0xf780) == 0xc680 && (iw1
& 0x0000) == 0x0000)
2726 return decode_dsp32shiftimm_0 (iw0
, iw1
);
2727 else if ((iw0
& 0xff00) == 0xf800)
2729 else if ((iw0
& 0xFFC0) == 0xf000 && (iw1
& 0x0000) == 0x0000)