1 /* tc-crx.c -- Assembler code for the CRX CPU core.
2 Copyright (C) 2004-2020 Free Software Foundation, Inc.
4 Contributed by Tomer Levi, NSC, Israel.
5 Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
6 Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
8 This file is part of GAS, the GNU Assembler.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the
22 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
26 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
28 #include "dwarf2dbg.h"
29 #include "opcode/crx.h"
32 /* Word is considered here as a 16-bit unsigned short int. */
35 /* Register is 4-bit size. */
38 /* Maximum size of a single instruction (in words). */
39 #define INSN_MAX_SIZE 3
41 /* Maximum bits which may be set in a `mask16' operand. */
42 #define MAX_REGS_IN_MASK16 8
44 /* Utility macros for string comparison. */
45 #define streq(a, b) (strcmp (a, b) == 0)
46 #define strneq(a, b, c) (strncmp (a, b, c) == 0)
48 /* Assign a number NUM, shifted by SHIFT bytes, into a location
49 pointed by index BYTE of array 'output_opcode'. */
50 #define CRX_PRINT(BYTE, NUM, SHIFT) output_opcode[BYTE] |= (NUM << SHIFT)
55 OP_LEGAL
= 0, /* Legal operand. */
56 OP_OUT_OF_RANGE
, /* Operand not within permitted range. */
57 OP_NOT_EVEN
, /* Operand is Odd number, should be even. */
58 OP_ILLEGAL_DISPU4
, /* Operand is not within DISPU4 range. */
59 OP_ILLEGAL_CST4
, /* Operand is not within CST4 range. */
60 OP_NOT_UPPER_64KB
/* Operand is not within the upper 64KB
61 (0xFFFF0000-0xFFFFFFFF). */
65 /* Opcode mnemonics hash table. */
66 static htab_t crx_inst_hash
;
67 /* CRX registers hash table. */
68 static htab_t reg_hash
;
69 /* CRX coprocessor registers hash table. */
70 static htab_t copreg_hash
;
71 /* Current instruction we're assembling. */
72 static const inst
*instruction
;
74 /* Global variables. */
76 /* Array to hold an instruction encoding. */
77 static long output_opcode
[2];
79 /* Nonzero means a relocatable symbol. */
80 static int relocatable
;
82 /* A copy of the original instruction (used in error messages). */
83 static char ins_parse
[MAX_INST_LEN
];
85 /* The current processed argument number. */
86 static int cur_arg_num
;
88 /* Generic assembler global variables which must be defined by all targets. */
90 /* Characters which always start a comment. */
91 const char comment_chars
[] = "#";
93 /* Characters which start a comment at the beginning of a line. */
94 const char line_comment_chars
[] = "#";
96 /* This array holds machine specific line separator characters. */
97 const char line_separator_chars
[] = ";";
99 /* Chars that can be used to separate mant from exp in floating point nums. */
100 const char EXP_CHARS
[] = "eE";
102 /* Chars that mean this number is a floating point constant as in 0f12.456 */
103 const char FLT_CHARS
[] = "f'";
105 /* Target-specific multicharacter options, not const-declared at usage. */
106 const char *md_shortopts
= "";
107 struct option md_longopts
[] =
109 {NULL
, no_argument
, NULL
, 0}
111 size_t md_longopts_size
= sizeof (md_longopts
);
113 /* This table describes all the machine specific pseudo-ops
114 the assembler has to support. The fields are:
115 *** Pseudo-op name without dot.
116 *** Function to call to execute this pseudo-op.
117 *** Integer arg to pass to the function. */
119 const pseudo_typeS md_pseudo_table
[] =
121 /* In CRX machine, align is in bytes (not a ptwo boundary). */
122 {"align", s_align_bytes
, 0},
126 /* CRX relaxation table. */
127 const relax_typeS md_relax_table
[] =
130 {0xfa, -0x100, 2, 1}, /* 8 */
131 {0xfffe, -0x10000, 4, 2}, /* 16 */
132 {0xfffffffe, -0xfffffffe, 6, 0}, /* 32 */
135 {0xfffe, -0x10000, 4, 4}, /* 16 */
136 {0xfffffffe, -0xfffffffe, 6, 0}, /* 32 */
139 {0xfe, -0x100, 4, 6}, /* 8 */
140 {0xfffffe, -0x1000000, 6, 0} /* 24 */
143 static void reset_vars (char *);
144 static reg
get_register (char *);
145 static copreg
get_copregister (char *);
146 static argtype
get_optype (operand_type
);
147 static int get_opbits (operand_type
);
148 static int get_opflags (operand_type
);
149 static int get_number_of_operands (void);
150 static void parse_operand (char *, ins
*);
151 static int gettrap (const char *);
152 static void handle_LoadStor (const char *);
153 static int get_cinv_parameters (const char *);
154 static long getconstant (long, int);
155 static op_err
check_range (long *, int, unsigned int, int);
156 static int getreg_image (int);
157 static void parse_operands (ins
*, char *);
158 static void parse_insn (ins
*, char *);
159 static void print_operand (int, int, argument
*);
160 static void print_constant (int, int, argument
*);
161 static int exponent2scale (int);
162 static void mask_reg (int, unsigned short *);
163 static void process_label_constant (char *, ins
*);
164 static void set_operand (char *, ins
*);
165 static char * preprocess_reglist (char *, int *);
166 static int assemble_insn (char *, ins
*);
167 static void print_insn (ins
*);
168 static void warn_if_needed (ins
*);
169 static int adjust_if_needed (ins
*);
171 /* Return the bit size for a given operand. */
174 get_opbits (operand_type op
)
177 return crx_optab
[op
].bit_size
;
182 /* Return the argument type of a given operand. */
185 get_optype (operand_type op
)
188 return crx_optab
[op
].arg_type
;
193 /* Return the flags of a given operand. */
196 get_opflags (operand_type op
)
199 return crx_optab
[op
].flags
;
204 /* Get the core processor register 'reg_name'. */
207 get_register (char *reg_name
)
209 const reg_entry
*rreg
;
211 rreg
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name
);
214 return rreg
->value
.reg_val
;
219 /* Get the coprocessor register 'copreg_name'. */
222 get_copregister (char *copreg_name
)
224 const reg_entry
*coreg
;
226 coreg
= (const reg_entry
*) str_hash_find (copreg_hash
, copreg_name
);
229 return coreg
->value
.copreg_val
;
231 return nullcopregister
;
234 /* Round up a section size to the appropriate boundary. */
237 md_section_align (segT seg
, valueT val
)
239 /* Round .text section to a multiple of 2. */
240 if (seg
== text_section
)
241 return (val
+ 1) & ~1;
245 /* Parse an operand that is machine-specific (remove '*'). */
248 md_operand (expressionS
* exp
)
250 char c
= *input_line_pointer
;
255 input_line_pointer
++;
263 /* Reset global variables before parsing a new instruction. */
266 reset_vars (char *op
)
268 cur_arg_num
= relocatable
= 0;
269 memset (& output_opcode
, '\0', sizeof (output_opcode
));
271 /* Save a copy of the original OP (used in error messages). */
272 strncpy (ins_parse
, op
, sizeof ins_parse
- 1);
273 ins_parse
[sizeof ins_parse
- 1] = 0;
276 /* This macro decides whether a particular reloc is an entry in a
277 switch table. It is used when relaxing, because the linker needs
278 to know about all such entries so that it can adjust them if
281 #define SWITCH_TABLE(fix) \
282 ( (fix)->fx_addsy != NULL \
283 && (fix)->fx_subsy != NULL \
284 && S_GET_SEGMENT ((fix)->fx_addsy) == \
285 S_GET_SEGMENT ((fix)->fx_subsy) \
286 && S_GET_SEGMENT (fix->fx_addsy) != undefined_section \
287 && ( (fix)->fx_r_type == BFD_RELOC_CRX_NUM8 \
288 || (fix)->fx_r_type == BFD_RELOC_CRX_NUM16 \
289 || (fix)->fx_r_type == BFD_RELOC_CRX_NUM32))
291 /* See whether we need to force a relocation into the output file.
292 This is used to force out switch and PC relative relocations when
296 crx_force_relocation (fixS
*fix
)
298 if (generic_force_reloc (fix
) || SWITCH_TABLE (fix
))
304 /* Generate a relocation entry for a fixup. */
307 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
* fixP
)
311 reloc
= XNEW (arelent
);
312 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
313 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
314 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
315 reloc
->addend
= fixP
->fx_offset
;
317 if (fixP
->fx_subsy
!= NULL
)
319 if (SWITCH_TABLE (fixP
))
321 /* Keep the current difference in the addend. */
322 reloc
->addend
= (S_GET_VALUE (fixP
->fx_addsy
)
323 - S_GET_VALUE (fixP
->fx_subsy
) + fixP
->fx_offset
);
325 switch (fixP
->fx_r_type
)
327 case BFD_RELOC_CRX_NUM8
:
328 fixP
->fx_r_type
= BFD_RELOC_CRX_SWITCH8
;
330 case BFD_RELOC_CRX_NUM16
:
331 fixP
->fx_r_type
= BFD_RELOC_CRX_SWITCH16
;
333 case BFD_RELOC_CRX_NUM32
:
334 fixP
->fx_r_type
= BFD_RELOC_CRX_SWITCH32
;
343 /* We only resolve difference expressions in the same section. */
344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
345 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
346 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "0",
347 segment_name (fixP
->fx_addsy
348 ? S_GET_SEGMENT (fixP
->fx_addsy
)
350 S_GET_NAME (fixP
->fx_subsy
),
351 segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)));
355 gas_assert ((int) fixP
->fx_r_type
> 0);
356 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
358 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
360 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
361 _("internal error: reloc %d (`%s') not supported by object file format"),
363 bfd_get_reloc_code_name (fixP
->fx_r_type
));
366 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
371 /* Prepare machine-dependent frags for relaxation. */
374 md_estimate_size_before_relax (fragS
*fragp
, asection
*seg
)
376 /* If symbol is undefined or located in a different section,
377 select the largest supported relocation. */
378 relax_substateT subtype
;
379 relax_substateT rlx_state
[] = {0, 2,
383 for (subtype
= 0; subtype
< ARRAY_SIZE (rlx_state
); subtype
+= 2)
385 if (fragp
->fr_subtype
== rlx_state
[subtype
]
386 && (!S_IS_DEFINED (fragp
->fr_symbol
)
387 || seg
!= S_GET_SEGMENT (fragp
->fr_symbol
)))
389 fragp
->fr_subtype
= rlx_state
[subtype
+ 1];
394 if (fragp
->fr_subtype
>= ARRAY_SIZE (md_relax_table
))
397 return md_relax_table
[fragp
->fr_subtype
].rlx_length
;
401 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, fragS
*fragP
)
403 /* 'opcode' points to the start of the instruction, whether
404 we need to change the instruction's fixed encoding. */
405 char *opcode
= &fragP
->fr_literal
[0] + fragP
->fr_fix
;
406 bfd_reloc_code_real_type reloc
;
408 subseg_change (sec
, 0);
410 switch (fragP
->fr_subtype
)
413 reloc
= BFD_RELOC_CRX_REL8
;
417 reloc
= BFD_RELOC_CRX_REL16
;
421 reloc
= BFD_RELOC_CRX_REL32
;
424 reloc
= BFD_RELOC_CRX_REL16
;
428 reloc
= BFD_RELOC_CRX_REL32
;
431 reloc
= BFD_RELOC_CRX_REL8_CMP
;
435 reloc
= BFD_RELOC_CRX_REL24
;
442 fix_new (fragP
, fragP
->fr_fix
,
443 bfd_get_reloc_size (bfd_reloc_type_lookup (stdoutput
, reloc
)),
444 fragP
->fr_symbol
, fragP
->fr_offset
, 1, reloc
);
446 fragP
->fr_fix
+= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
449 /* Process machine-dependent command line options. Called once for
450 each option on the command line that the machine-independent part of
451 GAS does not understand. */
454 md_parse_option (int c ATTRIBUTE_UNUSED
, const char *arg ATTRIBUTE_UNUSED
)
459 /* Machine-dependent usage-output. */
462 md_show_usage (FILE *stream ATTRIBUTE_UNUSED
)
468 md_atof (int type
, char *litP
, int *sizeP
)
470 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
473 /* Apply a fixS (fixup of an instruction or data that we didn't have
474 enough info to complete immediately) to the data in a frag.
475 Since linkrelax is nonzero and TC_LINKRELAX_FIXUP is defined to disable
476 relaxation of debug sections, this function is called only when
477 fixuping relocations of debug sections. */
480 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
483 char *buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
486 switch (fixP
->fx_r_type
)
488 case BFD_RELOC_CRX_NUM8
:
489 bfd_put_8 (stdoutput
, (unsigned char) val
, buf
);
491 case BFD_RELOC_CRX_NUM16
:
492 bfd_put_16 (stdoutput
, val
, buf
);
494 case BFD_RELOC_CRX_NUM32
:
495 bfd_put_32 (stdoutput
, val
, buf
);
498 /* We shouldn't ever get here because linkrelax is nonzero. */
505 if (fixP
->fx_addsy
== NULL
506 && fixP
->fx_pcrel
== 0)
509 if (fixP
->fx_pcrel
== 1
510 && fixP
->fx_addsy
!= NULL
511 && S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
515 /* The location from which a PC relative jump should be calculated,
516 given a PC relative reloc. */
519 md_pcrel_from (fixS
*fixp
)
521 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
524 /* This function is called once, at assembler startup time. This should
525 set up all the tables, etc that the MD part of the assembler needs. */
532 /* Set up a hash table for the instructions. */
533 crx_inst_hash
= str_htab_create ();
535 while (crx_instruction
[i
].mnemonic
!= NULL
)
537 const char *mnemonic
= crx_instruction
[i
].mnemonic
;
539 if (str_hash_insert (crx_inst_hash
, mnemonic
, &crx_instruction
[i
], 0))
540 as_fatal (_("duplicate %s"), mnemonic
);
542 /* Insert unique names into hash table. The CRX instruction set
543 has many identical opcode names that have different opcodes based
544 on the operands. This hash table then provides a quick index to
545 the first opcode with a particular name in the opcode table. */
550 while (crx_instruction
[i
].mnemonic
!= NULL
551 && streq (crx_instruction
[i
].mnemonic
, mnemonic
));
554 /* Initialize reg_hash hash table. */
555 reg_hash
= str_htab_create ();
557 const reg_entry
*regtab
;
559 for (regtab
= crx_regtab
;
560 regtab
< (crx_regtab
+ NUMREGS
); regtab
++)
561 if (str_hash_insert (reg_hash
, regtab
->name
, regtab
, 0) != NULL
)
562 as_fatal (_("duplicate %s"), regtab
->name
);
565 /* Initialize copreg_hash hash table. */
566 copreg_hash
= str_htab_create ();
568 const reg_entry
*copregtab
;
570 for (copregtab
= crx_copregtab
; copregtab
< (crx_copregtab
+ NUMCOPREGS
);
572 if (str_hash_insert (copreg_hash
, copregtab
->name
, copregtab
, 0) != NULL
)
573 as_fatal (_("duplicate %s"), copregtab
->name
);
575 /* Set linkrelax here to avoid fixups in most sections. */
579 /* Process constants (immediate/absolute)
580 and labels (jump targets/Memory locations). */
583 process_label_constant (char *str
, ins
* crx_ins
)
585 char *saved_input_line_pointer
;
586 argument
*cur_arg
= &crx_ins
->arg
[cur_arg_num
]; /* Current argument. */
588 saved_input_line_pointer
= input_line_pointer
;
589 input_line_pointer
= str
;
591 expression (&crx_ins
->exp
);
593 switch (crx_ins
->exp
.X_op
)
597 /* Missing or bad expr becomes absolute 0. */
598 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
600 crx_ins
->exp
.X_op
= O_constant
;
601 crx_ins
->exp
.X_add_number
= 0;
602 crx_ins
->exp
.X_add_symbol
= (symbolS
*) 0;
603 crx_ins
->exp
.X_op_symbol
= (symbolS
*) 0;
607 cur_arg
->X_op
= O_constant
;
608 cur_arg
->constant
= crx_ins
->exp
.X_add_number
;
614 cur_arg
->X_op
= O_symbol
;
615 crx_ins
->rtype
= BFD_RELOC_NONE
;
618 switch (cur_arg
->type
)
621 if (IS_INSN_TYPE (LD_STOR_INS_INC
))
622 crx_ins
->rtype
= BFD_RELOC_CRX_REGREL12
;
623 else if (IS_INSN_TYPE (CSTBIT_INS
)
624 || IS_INSN_TYPE (STOR_IMM_INS
))
625 crx_ins
->rtype
= BFD_RELOC_CRX_REGREL28
;
627 crx_ins
->rtype
= BFD_RELOC_CRX_REGREL32
;
631 crx_ins
->rtype
= BFD_RELOC_CRX_REGREL22
;
635 if (IS_INSN_MNEMONIC ("bal") || IS_INSN_TYPE (DCR_BRANCH_INS
))
636 crx_ins
->rtype
= BFD_RELOC_CRX_REL16
;
637 else if (IS_INSN_TYPE (BRANCH_INS
))
638 crx_ins
->rtype
= BFD_RELOC_CRX_REL8
;
639 else if (IS_INSN_TYPE (LD_STOR_INS
) || IS_INSN_TYPE (STOR_IMM_INS
)
640 || IS_INSN_TYPE (CSTBIT_INS
))
641 crx_ins
->rtype
= BFD_RELOC_CRX_ABS32
;
642 else if (IS_INSN_TYPE (BRANCH_NEQ_INS
))
643 crx_ins
->rtype
= BFD_RELOC_CRX_REL4
;
644 else if (IS_INSN_TYPE (CMPBR_INS
) || IS_INSN_TYPE (COP_BRANCH_INS
))
645 crx_ins
->rtype
= BFD_RELOC_CRX_REL8_CMP
;
649 if (IS_INSN_TYPE (ARITH_INS
))
650 crx_ins
->rtype
= BFD_RELOC_CRX_IMM32
;
651 else if (IS_INSN_TYPE (ARITH_BYTE_INS
))
652 crx_ins
->rtype
= BFD_RELOC_CRX_IMM16
;
660 cur_arg
->X_op
= crx_ins
->exp
.X_op
;
664 input_line_pointer
= saved_input_line_pointer
;
668 /* Get the values of the scale to be encoded -
669 used for the scaled index mode of addressing. */
672 exponent2scale (int val
)
676 /* If 'val' is 0, the following 'for' will be an endless loop. */
680 for (exponent
= 0; (val
!= 1); val
>>= 1, exponent
++)
686 /* Parsing different types of operands
687 -> constants Immediate/Absolute/Relative numbers
688 -> Labels Relocatable symbols
689 -> (rbase) Register base
690 -> disp(rbase) Register relative
691 -> disp(rbase)+ Post-increment mode
692 -> disp(rbase,ridx,scl) Register index mode */
695 set_operand (char *operand
, ins
* crx_ins
)
697 char *operandS
; /* Pointer to start of sub-operand. */
698 char *operandE
; /* Pointer to end of sub-operand. */
702 argument
*cur_arg
= &crx_ins
->arg
[cur_arg_num
]; /* Current argument. */
704 /* Initialize pointers. */
705 operandS
= operandE
= operand
;
707 switch (cur_arg
->type
)
709 case arg_sc
: /* Case *+0x18. */
710 case arg_ic
: /* Case $0x18. */
713 case arg_c
: /* Case 0x18. */
715 process_label_constant (operandS
, crx_ins
);
717 if (cur_arg
->type
!= arg_ic
)
718 cur_arg
->type
= arg_c
;
721 case arg_icr
: /* Case $0x18(r1). */
723 case arg_cr
: /* Case 0x18(r1). */
724 /* Set displacement constant. */
725 while (*operandE
!= '(')
728 process_label_constant (operandS
, crx_ins
);
731 case arg_rbase
: /* Case (r1). */
733 /* Set register base. */
734 while (*operandE
!= ')')
737 if ((cur_arg
->r
= get_register (operandS
)) == nullregister
)
738 as_bad (_("Illegal register `%s' in instruction `%s'"),
739 operandS
, ins_parse
);
741 if (cur_arg
->type
!= arg_rbase
)
742 cur_arg
->type
= arg_cr
;
746 /* Set displacement constant. */
747 while (*operandE
!= '(')
750 process_label_constant (operandS
, crx_ins
);
751 operandS
= ++operandE
;
753 /* Set register base. */
754 while ((*operandE
!= ',') && (! ISSPACE (*operandE
)))
757 if ((cur_arg
->r
= get_register (operandS
)) == nullregister
)
758 as_bad (_("Illegal register `%s' in instruction `%s'"),
759 operandS
, ins_parse
);
761 /* Skip leading white space. */
762 while (ISSPACE (*operandE
))
766 /* Set register index. */
767 while ((*operandE
!= ')') && (*operandE
!= ','))
772 if ((cur_arg
->i_r
= get_register (operandS
)) == nullregister
)
773 as_bad (_("Illegal register `%s' in instruction `%s'"),
774 operandS
, ins_parse
);
776 /* Skip leading white space. */
777 while (ISSPACE (*operandE
))
786 while (*operandE
!= ')')
790 /* Preprocess the scale string. */
791 input_save
= input_line_pointer
;
792 input_line_pointer
= operandS
;
794 input_line_pointer
= input_save
;
796 scale_val
= scale
.X_add_number
;
798 /* Check if the scale value is legal. */
799 if (scale_val
!= 1 && scale_val
!= 2
800 && scale_val
!= 4 && scale_val
!= 8)
801 as_bad (_("Illegal Scale - `%d'"), scale_val
);
803 cur_arg
->scale
= exponent2scale (scale_val
);
812 /* Parse a single operand.
813 operand - Current operand to parse.
814 crx_ins - Current assembled instruction. */
817 parse_operand (char *operand
, ins
* crx_ins
)
820 argument
*cur_arg
= &crx_ins
->arg
[cur_arg_num
]; /* Current argument. */
822 /* Initialize the type to NULL before parsing. */
823 cur_arg
->type
= nullargs
;
825 /* Check whether this is a general processor register. */
826 if ((ret_val
= get_register (operand
)) != nullregister
)
828 cur_arg
->type
= arg_r
;
829 cur_arg
->r
= ret_val
;
830 cur_arg
->X_op
= O_register
;
834 /* Check whether this is a core [special] coprocessor register. */
835 if ((ret_val
= get_copregister (operand
)) != nullcopregister
)
837 cur_arg
->type
= arg_copr
;
839 cur_arg
->type
= arg_copsr
;
840 cur_arg
->cr
= ret_val
;
841 cur_arg
->X_op
= O_register
;
845 /* Deal with special characters. */
849 if (strchr (operand
, '(') != NULL
)
850 cur_arg
->type
= arg_icr
;
852 cur_arg
->type
= arg_ic
;
857 cur_arg
->type
= arg_sc
;
862 cur_arg
->type
= arg_rbase
;
870 if (strchr (operand
, '(') != NULL
)
872 if (strchr (operand
, ',') != NULL
873 && (strchr (operand
, ',') > strchr (operand
, '(')))
874 cur_arg
->type
= arg_idxr
;
876 cur_arg
->type
= arg_cr
;
879 cur_arg
->type
= arg_c
;
882 /* Parse an operand according to its type. */
884 cur_arg
->constant
= 0;
885 set_operand (operand
, crx_ins
);
888 /* Parse the various operands. Each operand is then analyzed to fillup
889 the fields in the crx_ins data structure. */
892 parse_operands (ins
* crx_ins
, char *operands
)
894 char *operandS
; /* Operands string. */
895 char *operandH
, *operandT
; /* Single operand head/tail pointers. */
896 int allocated
= 0; /* Indicates a new operands string was allocated. */
897 char *operand
[MAX_OPERANDS
]; /* Separating the operands. */
898 int op_num
= 0; /* Current operand number we are parsing. */
899 int bracket_flag
= 0; /* Indicates a bracket '(' was found. */
900 int sq_bracket_flag
= 0; /* Indicates a square bracket '[' was found. */
902 /* Preprocess the list of registers, if necessary. */
903 operandS
= operandH
= operandT
= (INST_HAS_REG_LIST
) ?
904 preprocess_reglist (operands
, &allocated
) : operands
;
906 while (*operandT
!= '\0')
908 if (*operandT
== ',' && bracket_flag
!= 1 && sq_bracket_flag
!= 1)
911 operand
[op_num
++] = strdup (operandH
);
916 if (*operandT
== ' ')
917 as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse
);
919 if (*operandT
== '(')
921 else if (*operandT
== '[')
924 if (*operandT
== ')')
929 as_fatal (_("Missing matching brackets : `%s'"), ins_parse
);
931 else if (*operandT
== ']')
936 as_fatal (_("Missing matching brackets : `%s'"), ins_parse
);
939 if (bracket_flag
== 1 && *operandT
== ')')
941 else if (sq_bracket_flag
== 1 && *operandT
== ']')
947 /* Adding the last operand. */
948 operand
[op_num
++] = strdup (operandH
);
949 crx_ins
->nargs
= op_num
;
951 /* Verifying correct syntax of operands (all brackets should be closed). */
952 if (bracket_flag
|| sq_bracket_flag
)
953 as_fatal (_("Missing matching brackets : `%s'"), ins_parse
);
955 /* Now we parse each operand separately. */
956 for (op_num
= 0; op_num
< crx_ins
->nargs
; op_num
++)
958 cur_arg_num
= op_num
;
959 parse_operand (operand
[op_num
], crx_ins
);
960 free (operand
[op_num
]);
967 /* Get the trap index in dispatch table, given its name.
968 This routine is used by assembling the 'excp' instruction. */
971 gettrap (const char *s
)
973 const trap_entry
*trap
;
975 for (trap
= crx_traps
; trap
< (crx_traps
+ NUMTRAPS
); trap
++)
976 if (strcasecmp (trap
->name
, s
) == 0)
979 as_bad (_("Unknown exception: `%s'"), s
);
983 /* Post-Increment instructions, as well as Store-Immediate instructions, are a
984 sub-group within load/stor instruction groups.
985 Therefore, when parsing a Post-Increment/Store-Immediate insn, we have to
986 advance the instruction pointer to the start of that sub-group (that is, up
987 to the first instruction of that type).
988 Otherwise, the insn will be mistakenly identified as of type LD_STOR_INS. */
991 handle_LoadStor (const char *operands
)
993 /* Post-Increment instructions precede Store-Immediate instructions in
994 CRX instruction table, hence they are handled before.
995 This synchronization should be kept. */
997 /* Assuming Post-Increment insn has the following format :
998 'MNEMONIC DISP(REG)+, REG' (e.g. 'loadw 12(r5)+, r6').
999 LD_STOR_INS_INC are the only store insns containing a plus sign (+). */
1000 if (strstr (operands
, ")+") != NULL
)
1002 while (! IS_INSN_TYPE (LD_STOR_INS_INC
))
1007 /* Assuming Store-Immediate insn has the following format :
1008 'MNEMONIC $DISP, ...' (e.g. 'storb $1, 12(r5)').
1009 STOR_IMM_INS are the only store insns containing a dollar sign ($). */
1010 if (strstr (operands
, "$") != NULL
)
1011 while (! IS_INSN_TYPE (STOR_IMM_INS
))
1015 /* Top level module where instruction parsing starts.
1016 crx_ins - data structure holds some information.
1017 operands - holds the operands part of the whole instruction. */
1020 parse_insn (ins
*insn
, char *operands
)
1024 /* Handle instructions with no operands. */
1025 for (i
= 0; crx_no_op_insn
[i
] != NULL
; i
++)
1027 if (streq (crx_no_op_insn
[i
], instruction
->mnemonic
))
1034 /* Handle 'excp'/'cinv' instructions. */
1035 if (IS_INSN_MNEMONIC ("excp") || IS_INSN_MNEMONIC ("cinv"))
1038 insn
->arg
[0].type
= arg_ic
;
1039 insn
->arg
[0].constant
= IS_INSN_MNEMONIC ("excp") ?
1040 gettrap (operands
) : get_cinv_parameters (operands
);
1041 insn
->arg
[0].X_op
= O_constant
;
1045 /* Handle load/stor unique instructions before parsing. */
1046 if (IS_INSN_TYPE (LD_STOR_INS
))
1047 handle_LoadStor (operands
);
1049 if (operands
!= NULL
)
1050 parse_operands (insn
, operands
);
1053 /* Cinv instruction requires special handling. */
1056 get_cinv_parameters (const char *operand
)
1058 const char *p
= operand
;
1059 int d_used
= 0, i_used
= 0, u_used
= 0, b_used
= 0;
1063 if (*p
== ',' || *p
== ' ')
1075 as_bad (_("Illegal `cinv' parameter: `%c'"), *p
);
1078 return ((b_used
? 8 : 0)
1081 + (u_used
? 1 : 0));
1084 /* Retrieve the opcode image of a given register.
1085 If the register is illegal for the current instruction,
1089 getreg_image (int r
)
1091 const reg_entry
*rreg
;
1093 int is_procreg
= 0; /* Nonzero means argument should be processor reg. */
1095 if (((IS_INSN_MNEMONIC ("mtpr")) && (cur_arg_num
== 1))
1096 || ((IS_INSN_MNEMONIC ("mfpr")) && (cur_arg_num
== 0)) )
1099 /* Check whether the register is in registers table. */
1101 rreg
= &crx_regtab
[r
];
1102 /* Check whether the register is in coprocessor registers table. */
1103 else if (r
< (int) MAX_COPREG
)
1104 rreg
= &crx_copregtab
[r
-MAX_REG
];
1105 /* Register not found. */
1108 as_bad (_("Unknown register: `%d'"), r
);
1112 reg_name
= rreg
->name
;
1114 /* Issue a error message when register is illegal. */
1116 as_bad (_("Illegal register (`%s') in instruction: `%s'"), \
1117 reg_name, ins_parse);
1122 if (is_procreg
|| (instruction
->flags
& USER_REG
))
1128 case CRX_CFG_REGTYPE
:
1143 case CRX_CS_REGTYPE
:
1155 /* Routine used to represent integer X using NBITS bits. */
1158 getconstant (long x
, int nbits
)
1160 return x
& ((((1U << (nbits
- 1)) - 1) << 1) | 1);
1163 /* Print a constant value to 'output_opcode':
1164 ARG holds the operand's type and value.
1165 SHIFT represents the location of the operand to be print into.
1166 NBITS determines the size (in bits) of the constant. */
1169 print_constant (int nbits
, int shift
, argument
*arg
)
1171 unsigned long mask
= 0;
1173 long constant
= getconstant (arg
->constant
, nbits
);
1181 /* mask the upper part of the constant, that is, the bits
1182 going to the lowest byte of output_opcode[0].
1183 The upper part of output_opcode[1] is always filled,
1184 therefore it is always masked with 0xFFFF. */
1185 mask
= (1 << (nbits
- 16)) - 1;
1186 /* Divide the constant between two consecutive words :
1188 +---------+---------+---------+---------+
1189 | | X X X X | X X X X | |
1190 +---------+---------+---------+---------+
1191 output_opcode[0] output_opcode[1] */
1193 CRX_PRINT (0, (constant
>> WORD_SHIFT
) & mask
, 0);
1194 CRX_PRINT (1, (constant
& 0xFFFF), WORD_SHIFT
);
1199 /* Special case - in arg_cr, the SHIFT represents the location
1200 of the REGISTER, not the constant, which is itself not shifted. */
1201 if (arg
->type
== arg_cr
)
1203 CRX_PRINT (0, constant
, 0);
1207 /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
1208 always filling the upper part of output_opcode[1]. If we mistakenly
1209 write it to output_opcode[0], the constant prefix (that is, 'match')
1212 +---------+---------+---------+---------+
1213 | 'match' | | X X X X | |
1214 +---------+---------+---------+---------+
1215 output_opcode[0] output_opcode[1] */
1217 if ((instruction
->size
> 2) && (shift
== WORD_SHIFT
))
1218 CRX_PRINT (1, constant
, WORD_SHIFT
);
1220 CRX_PRINT (0, constant
, shift
);
1224 CRX_PRINT (0, constant
, shift
);
1229 /* Print an operand to 'output_opcode', which later on will be
1230 printed to the object file:
1231 ARG holds the operand's type, size and value.
1232 SHIFT represents the printing location of operand.
1233 NBITS determines the size (in bits) of a constant operand. */
1236 print_operand (int nbits
, int shift
, argument
*arg
)
1241 CRX_PRINT (0, getreg_image (arg
->r
), shift
);
1245 if (arg
->cr
< c0
|| arg
->cr
> c15
)
1246 as_bad (_("Illegal co-processor register in instruction `%s'"),
1248 CRX_PRINT (0, getreg_image (arg
->cr
), shift
);
1252 if (arg
->cr
< cs0
|| arg
->cr
> cs15
)
1253 as_bad (_("Illegal co-processor special register in instruction `%s'"),
1255 CRX_PRINT (0, getreg_image (arg
->cr
), shift
);
1260 +--------------------------------+
1261 | r_base | r_idx | scl| disp |
1262 +--------------------------------+ */
1263 CRX_PRINT (0, getreg_image (arg
->r
), 12);
1264 CRX_PRINT (0, getreg_image (arg
->i_r
), 8);
1265 CRX_PRINT (0, arg
->scale
, 6);
1269 print_constant (nbits
, shift
, arg
);
1273 CRX_PRINT (0, getreg_image (arg
->r
), shift
);
1277 /* case base_cst4. */
1278 if (instruction
->flags
& DISPU4MAP
)
1279 print_constant (nbits
, shift
+ REG_SIZE
, arg
);
1281 /* rbase_disps<NN> and other such cases. */
1282 print_constant (nbits
, shift
, arg
);
1283 /* Add the register argument to the output_opcode. */
1284 CRX_PRINT (0, getreg_image (arg
->r
), shift
);
1292 /* Retrieve the number of operands for the current assembled instruction. */
1295 get_number_of_operands (void)
1299 for (i
= 0; instruction
->operands
[i
].op_type
&& i
< MAX_OPERANDS
; i
++)
1304 /* Verify that the number NUM can be represented in BITS bits (that is,
1305 within its permitted range), based on the instruction's FLAGS.
1306 If UPDATE is nonzero, update the value of NUM if necessary.
1307 Return OP_LEGAL upon success, actual error type upon failure. */
1310 check_range (long *num
, int bits
, int unsigned flags
, int update
)
1313 op_err retval
= OP_LEGAL
;
1315 uint32_t upper_64kb
= 0xffff0000;
1316 uint32_t value
= *num
;
1318 /* Verify operand value is even. */
1319 if (flags
& OP_EVEN
)
1325 if (flags
& OP_UPPER_64KB
)
1327 /* Check if value is to be mapped to upper 64 KB memory area. */
1328 if ((value
& upper_64kb
) == upper_64kb
)
1330 value
-= upper_64kb
;
1335 return OP_NOT_UPPER_64KB
;
1338 if (flags
& OP_SHIFT
)
1340 /* All OP_SHIFT args are also OP_SIGNED, so we want to keep the
1341 sign. However, right shift of a signed type with a negative
1342 value is implementation defined. See ISO C 6.5.7. So we use
1343 an unsigned type and sign extend afterwards. */
1345 value
= (value
^ 0x40000000) - 0x40000000;
1349 else if (flags
& OP_SHIFT_DEC
)
1351 value
= (value
>> 1) - 1;
1358 /* 0x7e and 0x7f are reserved escape sequences of dispe9. */
1359 if (value
== 0x7e || value
== 0x7f)
1360 return OP_OUT_OF_RANGE
;
1363 if (flags
& OP_DISPU4
)
1367 uint32_t mul
= (instruction
->flags
& DISPUB4
? 1
1368 : instruction
->flags
& DISPUW4
? 2
1369 : instruction
->flags
& DISPUD4
? 4
1372 for (bin
= 0; bin
< crx_cst4_maps
; bin
++)
1374 if (value
== mul
* bin
)
1383 retval
= OP_ILLEGAL_DISPU4
;
1385 else if (flags
& OP_CST4
)
1389 for (bin
= 0; bin
< crx_cst4_maps
; bin
++)
1391 if (value
== (uint32_t) crx_cst4_map
[bin
])
1400 retval
= OP_ILLEGAL_CST4
;
1402 else if (flags
& OP_SIGNED
)
1405 max
= max
<< (bits
- 1);
1407 max
= ((max
- 1) << 1) | 1;
1409 retval
= OP_OUT_OF_RANGE
;
1411 else if (flags
& OP_UNSIGNED
)
1414 max
= max
<< (bits
- 1);
1415 max
= ((max
- 1) << 1) | 1;
1417 retval
= OP_OUT_OF_RANGE
;
1422 /* Assemble a single instruction:
1423 INSN is already parsed (that is, all operand values and types are set).
1424 For instruction to be assembled, we need to find an appropriate template in
1425 the instruction table, meeting the following conditions:
1426 1: Has the same number of operands.
1427 2: Has the same operand types.
1428 3: Each operand size is sufficient to represent the instruction's values.
1429 Returns 1 upon success, 0 upon failure. */
1432 assemble_insn (char *mnemonic
, ins
*insn
)
1434 /* Type of each operand in the current template. */
1435 argtype cur_type
[MAX_OPERANDS
];
1436 /* Size (in bits) of each operand in the current template. */
1437 unsigned int cur_size
[MAX_OPERANDS
];
1438 /* Flags of each operand in the current template. */
1439 unsigned int cur_flags
[MAX_OPERANDS
];
1440 /* Instruction type to match. */
1441 unsigned int ins_type
;
1442 /* Boolean flag to mark whether a match was found. */
1445 /* Nonzero if an instruction with same number of operands was found. */
1446 int found_same_number_of_operands
= 0;
1447 /* Nonzero if an instruction with same argument types was found. */
1448 int found_same_argument_types
= 0;
1449 /* Nonzero if a constant was found within the required range. */
1450 int found_const_within_range
= 0;
1451 /* Argument number of an operand with invalid type. */
1452 int invalid_optype
= -1;
1453 /* Argument number of an operand with invalid constant value. */
1454 int invalid_const
= -1;
1455 /* Operand error (used for issuing various constant error messages). */
1456 op_err op_error
, const_err
= OP_LEGAL
;
1458 /* Retrieve data (based on FUNC) for each operand of a given instruction. */
1459 #define GET_CURRENT_DATA(FUNC, ARRAY) \
1460 for (i = 0; i < insn->nargs; i++) \
1461 ARRAY[i] = FUNC (instruction->operands[i].op_type)
1463 #define GET_CURRENT_TYPE GET_CURRENT_DATA(get_optype, cur_type)
1464 #define GET_CURRENT_SIZE GET_CURRENT_DATA(get_opbits, cur_size)
1465 #define GET_CURRENT_FLAGS GET_CURRENT_DATA(get_opflags, cur_flags)
1467 /* Instruction has no operands -> only copy the constant opcode. */
1468 if (insn
->nargs
== 0)
1470 output_opcode
[0] = BIN (instruction
->match
, instruction
->match_bits
);
1474 /* In some case, same mnemonic can appear with different instruction types.
1475 For example, 'storb' is supported with 3 different types :
1476 LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
1477 We assume that when reaching this point, the instruction type was
1478 pre-determined. We need to make sure that the type stays the same
1479 during a search for matching instruction. */
1480 ins_type
= CRX_INS_TYPE(instruction
->flags
);
1482 while (/* Check that match is still not found. */
1484 /* Check we didn't get to end of table. */
1485 && instruction
->mnemonic
!= NULL
1486 /* Check that the actual mnemonic is still available. */
1487 && IS_INSN_MNEMONIC (mnemonic
)
1488 /* Check that the instruction type wasn't changed. */
1489 && IS_INSN_TYPE(ins_type
))
1491 /* Check whether number of arguments is legal. */
1492 if (get_number_of_operands () != insn
->nargs
)
1494 found_same_number_of_operands
= 1;
1496 /* Initialize arrays with data of each operand in current template. */
1501 /* Check for type compatibility. */
1502 for (i
= 0; i
< insn
->nargs
; i
++)
1504 if (cur_type
[i
] != insn
->arg
[i
].type
)
1506 if (invalid_optype
== -1)
1507 invalid_optype
= i
+ 1;
1511 found_same_argument_types
= 1;
1513 for (i
= 0; i
< insn
->nargs
; i
++)
1515 /* Reverse the operand indices for certain opcodes:
1518 Other index -->> stays the same. */
1519 int j
= instruction
->flags
& REVERSE_MATCH
?
1524 /* Only check range - don't update the constant's value, since the
1525 current instruction may not be the last we try to match.
1526 The constant's value will be updated later, right before printing
1527 it to the object file. */
1528 if ((insn
->arg
[j
].X_op
== O_constant
)
1529 && (op_error
= check_range (&insn
->arg
[j
].constant
, cur_size
[j
],
1532 if (invalid_const
== -1)
1534 invalid_const
= j
+ 1;
1535 const_err
= op_error
;
1539 /* For symbols, we make sure the relocation size (which was already
1540 determined) is sufficient. */
1541 else if ((insn
->arg
[j
].X_op
== O_symbol
)
1542 && ((bfd_reloc_type_lookup (stdoutput
, insn
->rtype
))->bitsize
1546 found_const_within_range
= 1;
1548 /* If we got till here -> Full match is found. */
1552 /* Try again with next instruction. */
1559 /* We haven't found a match - instruction can't be assembled. */
1560 if (!found_same_number_of_operands
)
1561 as_bad (_("Incorrect number of operands"));
1562 else if (!found_same_argument_types
)
1563 as_bad (_("Illegal type of operand (arg %d)"), invalid_optype
);
1564 else if (!found_const_within_range
)
1568 case OP_OUT_OF_RANGE
:
1569 as_bad (_("Operand out of range (arg %d)"), invalid_const
);
1572 as_bad (_("Operand has odd displacement (arg %d)"), invalid_const
);
1574 case OP_ILLEGAL_DISPU4
:
1575 as_bad (_("Invalid DISPU4 operand value (arg %d)"), invalid_const
);
1577 case OP_ILLEGAL_CST4
:
1578 as_bad (_("Invalid CST4 operand value (arg %d)"), invalid_const
);
1580 case OP_NOT_UPPER_64KB
:
1581 as_bad (_("Operand value is not within upper 64 KB (arg %d)"),
1585 as_bad (_("Illegal operand (arg %d)"), invalid_const
);
1593 /* Full match - print the encoding to output file. */
1595 /* Make further checking (such that couldn't be made earlier).
1596 Warn the user if necessary. */
1597 warn_if_needed (insn
);
1599 /* Check whether we need to adjust the instruction pointer. */
1600 if (adjust_if_needed (insn
))
1601 /* If instruction pointer was adjusted, we need to update
1602 the size of the current template operands. */
1605 for (i
= 0; i
< insn
->nargs
; i
++)
1607 int j
= instruction
->flags
& REVERSE_MATCH
?
1612 /* This time, update constant value before printing it. */
1613 if ((insn
->arg
[j
].X_op
== O_constant
)
1614 && (check_range (&insn
->arg
[j
].constant
, cur_size
[j
],
1615 cur_flags
[j
], 1) != OP_LEGAL
))
1616 as_fatal (_("Illegal operand (arg %d)"), j
+1);
1619 /* First, copy the instruction's opcode. */
1620 output_opcode
[0] = BIN (instruction
->match
, instruction
->match_bits
);
1622 for (i
= 0; i
< insn
->nargs
; i
++)
1625 print_operand (cur_size
[i
], instruction
->operands
[i
].shift
,
1633 /* Bunch of error checking.
1634 The checks are made after a matching instruction was found. */
1637 warn_if_needed (ins
*insn
)
1639 /* If the post-increment address mode is used and the load/store
1640 source register is the same as rbase, the result of the
1641 instruction is undefined. */
1642 if (IS_INSN_TYPE (LD_STOR_INS_INC
))
1644 /* Enough to verify that one of the arguments is a simple reg. */
1645 if ((insn
->arg
[0].type
== arg_r
) || (insn
->arg
[1].type
== arg_r
))
1646 if (insn
->arg
[0].r
== insn
->arg
[1].r
)
1647 as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
1651 /* Some instruction assume the stack pointer as rptr operand.
1652 Issue an error when the register to be loaded is also SP. */
1653 if (instruction
->flags
& NO_SP
)
1655 if (getreg_image (insn
->arg
[0].r
) == getreg_image (sp
))
1656 as_bad (_("`%s' has undefined result"), ins_parse
);
1659 /* If the rptr register is specified as one of the registers to be loaded,
1660 the final contents of rptr are undefined. Thus, we issue an error. */
1661 if (instruction
->flags
& NO_RPTR
)
1663 if ((1 << getreg_image (insn
->arg
[0].r
)) & insn
->arg
[1].constant
)
1664 as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
1665 getreg_image (insn
->arg
[0].r
));
1669 /* In some cases, we need to adjust the instruction pointer although a
1670 match was already found. Here, we gather all these cases.
1671 Returns 1 if instruction pointer was adjusted, otherwise 0. */
1674 adjust_if_needed (ins
*insn
)
1678 /* Special check for 'addub $0, r0' instruction -
1679 The opcode '0000 0000 0000 0000' is not allowed. */
1680 if (IS_INSN_MNEMONIC ("addub"))
1682 if ((instruction
->operands
[0].op_type
== cst4
)
1683 && instruction
->operands
[1].op_type
== regr
)
1685 if (insn
->arg
[0].constant
== 0 && insn
->arg
[1].r
== r0
)
1693 /* Optimization: Omit a zero displacement in bit operations,
1694 saving 2-byte encoding space (e.g., 'cbitw $8, 0(r1)'). */
1695 if (IS_INSN_TYPE (CSTBIT_INS
))
1697 if ((instruction
->operands
[1].op_type
== rbase_disps12
)
1698 && (insn
->arg
[1].X_op
== O_constant
)
1699 && (insn
->arg
[1].constant
== 0))
1709 /* Set the appropriate bit for register 'r' in 'mask'.
1710 This indicates that this register is loaded or stored by
1714 mask_reg (int r
, unsigned short int *mask
)
1716 if ((reg
)r
> (reg
)sp
)
1718 as_bad (_("Invalid register in register list"));
1725 /* Preprocess register list - create a 16-bit mask with one bit for each
1726 of the 16 general purpose registers. If a bit is set, it indicates
1727 that this register is loaded or stored by the instruction. */
1730 preprocess_reglist (char *param
, int *allocated
)
1732 char reg_name
[MAX_REGNAME_LEN
]; /* Current parsed register name. */
1733 char *regP
; /* Pointer to 'reg_name' string. */
1734 int reg_counter
= 0; /* Count number of parsed registers. */
1735 unsigned short int mask
= 0; /* Mask for 16 general purpose registers. */
1736 char *new_param
; /* New created operands string. */
1737 char *paramP
= param
; /* Pointer to original operands string. */
1738 char maskstring
[10]; /* Array to print the mask as a string. */
1739 int hi_found
= 0, lo_found
= 0; /* Boolean flags for hi/lo registers. */
1743 /* If 'param' is already in form of a number, no need to preprocess. */
1744 if (strchr (paramP
, '{') == NULL
)
1747 /* Verifying correct syntax of operand. */
1748 if (strchr (paramP
, '}') == NULL
)
1749 as_fatal (_("Missing matching brackets : `%s'"), ins_parse
);
1751 while (*paramP
++ != '{');
1753 new_param
= XCNEWVEC (char, MAX_INST_LEN
);
1755 strncpy (new_param
, param
, paramP
- param
- 1);
1757 while (*paramP
!= '}')
1760 memset (®_name
, '\0', sizeof (reg_name
));
1762 while (ISALNUM (*paramP
))
1765 strncpy (reg_name
, regP
, paramP
- regP
);
1767 /* Coprocessor register c<N>. */
1768 if (IS_INSN_TYPE (COP_REG_INS
))
1770 if (((cr
= get_copregister (reg_name
)) == nullcopregister
)
1771 || (crx_copregtab
[cr
-MAX_REG
].type
!= CRX_C_REGTYPE
))
1772 as_fatal (_("Illegal register `%s' in cop-register list"), reg_name
);
1773 mask_reg (getreg_image (cr
- c0
), &mask
);
1775 /* Coprocessor Special register cs<N>. */
1776 else if (IS_INSN_TYPE (COPS_REG_INS
))
1778 if (((cr
= get_copregister (reg_name
)) == nullcopregister
)
1779 || (crx_copregtab
[cr
-MAX_REG
].type
!= CRX_CS_REGTYPE
))
1780 as_fatal (_("Illegal register `%s' in cop-special-register list"),
1782 mask_reg (getreg_image (cr
- cs0
), &mask
);
1784 /* User register u<N>. */
1785 else if (instruction
->flags
& USER_REG
)
1787 if (streq(reg_name
, "uhi"))
1792 else if (streq(reg_name
, "ulo"))
1797 else if (((r
= get_register (reg_name
)) == nullregister
)
1798 || (crx_regtab
[r
].type
!= CRX_U_REGTYPE
))
1799 as_fatal (_("Illegal register `%s' in user register list"), reg_name
);
1801 mask_reg (getreg_image (r
- u0
), &mask
);
1803 /* General purpose register r<N>. */
1806 if (streq(reg_name
, "hi"))
1811 else if (streq(reg_name
, "lo"))
1816 else if (((r
= get_register (reg_name
)) == nullregister
)
1817 || (crx_regtab
[r
].type
!= CRX_R_REGTYPE
))
1818 as_fatal (_("Illegal register `%s' in register list"), reg_name
);
1820 mask_reg (getreg_image (r
- r0
), &mask
);
1823 if (++reg_counter
> MAX_REGS_IN_MASK16
)
1824 as_bad (_("Maximum %d bits may be set in `mask16' operand"),
1825 MAX_REGS_IN_MASK16
);
1828 while (!ISALNUM (*paramP
) && *paramP
!= '}')
1832 if (*++paramP
!= '\0')
1833 as_warn (_("rest of line ignored; first ignored character is `%c'"),
1836 switch (hi_found
+ lo_found
)
1839 /* At least one register should be specified. */
1841 as_bad (_("Illegal `mask16' operand, operation is undefined - `%s'"),
1846 /* HI can't be specified without LO (and vise-versa). */
1847 as_bad (_("HI/LO registers should be specified together"));
1851 /* HI/LO registers mustn't be masked with additional registers. */
1853 as_bad (_("HI/LO registers should be specified without additional registers"));
1859 sprintf (maskstring
, "$0x%x", mask
);
1860 strcat (new_param
, maskstring
);
1864 /* Print the instruction.
1865 Handle also cases where the instruction is relaxable/relocatable. */
1868 print_insn (ins
*insn
)
1870 unsigned int i
, j
, insn_size
;
1872 unsigned short words
[4];
1875 /* Arrange the insn encodings in a WORD size array. */
1876 for (i
= 0, j
= 0; i
< 2; i
++)
1878 words
[j
++] = (output_opcode
[i
] >> 16) & 0xFFFF;
1879 words
[j
++] = output_opcode
[i
] & 0xFFFF;
1882 /* Handle relaxation. */
1883 if ((instruction
->flags
& RELAXABLE
) && relocatable
)
1887 /* Write the maximal instruction size supported. */
1888 insn_size
= INSN_MAX_SIZE
;
1891 if (IS_INSN_TYPE (BRANCH_INS
))
1894 else if (IS_INSN_TYPE (DCR_BRANCH_INS
) || IS_INSN_MNEMONIC ("bal"))
1897 else if (IS_INSN_TYPE (CMPBR_INS
) || IS_INSN_TYPE (COP_BRANCH_INS
))
1902 this_frag
= frag_var (rs_machine_dependent
, insn_size
* 2,
1904 insn
->exp
.X_add_symbol
,
1905 insn
->exp
.X_add_number
,
1910 insn_size
= instruction
->size
;
1911 this_frag
= frag_more (insn_size
* 2);
1913 /* Handle relocation. */
1914 if ((relocatable
) && (insn
->rtype
!= BFD_RELOC_NONE
))
1916 reloc_howto_type
*reloc_howto
;
1919 reloc_howto
= bfd_reloc_type_lookup (stdoutput
, insn
->rtype
);
1924 size
= bfd_get_reloc_size (reloc_howto
);
1926 if (size
< 1 || size
> 4)
1929 fix_new_exp (frag_now
, this_frag
- frag_now
->fr_literal
,
1930 size
, &insn
->exp
, reloc_howto
->pc_relative
,
1935 /* Verify a 2-byte code alignment. */
1936 addr_mod
= frag_now_fix () & 1;
1937 if (frag_now
->has_code
&& frag_now
->insn_addr
!= addr_mod
)
1938 as_bad (_("instruction address is not a multiple of 2"));
1939 frag_now
->insn_addr
= addr_mod
;
1940 frag_now
->has_code
= 1;
1942 /* Write the instruction encoding to frag. */
1943 for (i
= 0; i
< insn_size
; i
++)
1945 md_number_to_chars (this_frag
, (valueT
) words
[i
], 2);
1950 /* This is the guts of the machine-dependent assembler. OP points to a
1951 machine dependent instruction. This function is supposed to emit
1952 the frags/bytes it assembles to. */
1955 md_assemble (char *op
)
1961 /* Reset global variables for a new instruction. */
1964 /* Strip the mnemonic. */
1965 for (param
= op
; *param
!= 0 && !ISSPACE (*param
); param
++)
1970 /* Find the instruction. */
1971 instruction
= (const inst
*) str_hash_find (crx_inst_hash
, op
);
1972 if (instruction
== NULL
)
1974 as_bad (_("Unknown opcode: `%s'"), op
);
1979 /* Tie dwarf2 debug info to the address at the start of the insn. */
1980 dwarf2_emit_insn (0);
1982 /* Parse the instruction's operands. */
1983 parse_insn (&crx_ins
, param
);
1985 /* Assemble the instruction - return upon failure. */
1986 if (assemble_insn (op
, &crx_ins
) == 0)
1992 /* Print the instruction. */
1994 print_insn (&crx_ins
);