1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
2 Copyright (C) 1996, 97, 98, 99, 2000 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
25 #include "opcode/d10v.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "O";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
37 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
38 && (X)->X_op_symbol != NULL \
39 && symbol_constant_p ((X)->X_op_symbol) \
40 && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
41 #define AT_WORD_RIGHT_SHIFT 2
44 #define MAX_INSN_FIXUPS (5)
51 bfd_reloc_code_real_type reloc
;
54 typedef struct _fixups
57 struct d10v_fixup fix
[MAX_INSN_FIXUPS
];
61 static Fixups FixUps
[2];
62 static Fixups
*fixups
;
64 static int do_not_ignore_hash
= 0;
66 typedef int packing_type
;
67 #define PACK_UNSPEC (0) /* Packing order not specified. */
68 #define PACK_PARALLEL (1) /* "||" */
69 #define PACK_LEFT_RIGHT (2) /* "->" */
70 #define PACK_RIGHT_LEFT (3) /* "<-" */
71 static packing_type etype
= PACK_UNSPEC
; /* Used by d10v_cleanup. */
73 /* True if instruction swapping warnings should be inhibited. */
74 static unsigned char flag_warn_suppress_instructionswap
; /* --nowarnswap */
76 /* Local functions. */
77 static int reg_name_search
PARAMS ((char *name
));
78 static int register_name
PARAMS ((expressionS
*expressionP
));
79 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
80 static int postfix
PARAMS ((char *p
));
81 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d10v_operand
*op
));
82 static int get_operands
PARAMS ((expressionS exp
[]));
83 static struct d10v_opcode
*find_opcode
PARAMS ((struct d10v_opcode
*opcode
, expressionS ops
[]));
84 static unsigned long build_insn
PARAMS ((struct d10v_opcode
*opcode
, expressionS
*opers
, unsigned long insn
));
85 static void write_long
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
86 static void write_1_short
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
87 static int write_2_short
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
88 struct d10v_opcode
*opcode2
, unsigned long insn2
, packing_type exec_type
, Fixups
*fx
));
89 static unsigned long do_assemble
PARAMS ((char *str
, struct d10v_opcode
**opcode
));
90 static unsigned long d10v_insert_operand
PARAMS (( unsigned long insn
, int op_type
,
91 offsetT value
, int left
, fixS
*fix
));
92 static int parallel_ok
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
93 struct d10v_opcode
*opcode2
, unsigned long insn2
,
94 packing_type exec_type
));
95 static symbolS
* find_symbol_matching_register
PARAMS ((expressionS
*));
97 struct option md_longopts
[] =
99 #define OPTION_NOWARNSWAP (OPTION_MD_BASE)
100 {"nowarnswap", no_argument
, NULL
, OPTION_NOWARNSWAP
},
101 {NULL
, no_argument
, NULL
, 0}
104 size_t md_longopts_size
= sizeof (md_longopts
);
106 static void d10v_dot_word
PARAMS ((int));
108 /* The target specific pseudo-ops which we support. */
109 const pseudo_typeS md_pseudo_table
[] =
111 { "word", d10v_dot_word
, 2 },
115 /* Opcode hash table. */
116 static struct hash_control
*d10v_hash
;
118 /* Do a binary search of the d10v_predefined_registers array to see if
119 NAME is a valid regiter name. Return the register number from the
120 array on success, or -1 on failure. */
123 reg_name_search (name
)
126 int middle
, low
, high
;
130 high
= d10v_reg_name_cnt () - 1;
134 middle
= (low
+ high
) / 2;
135 cmp
= strcasecmp (name
, d10v_predefined_registers
[middle
].name
);
141 return d10v_predefined_registers
[middle
].value
;
147 /* Check the string at input_line_pointer
148 to see if it is a valid register name. */
151 register_name (expressionP
)
152 expressionS
*expressionP
;
155 char c
, *p
= input_line_pointer
;
158 && *p
!= '\n' && *p
!= '\r' && *p
!= ',' && *p
!= ' ' && *p
!= ')')
165 /* Look to see if it's in the register table. */
166 reg_number
= reg_name_search (input_line_pointer
);
169 expressionP
->X_op
= O_register
;
170 /* Temporarily store a pointer to the string here. */
171 expressionP
->X_op_symbol
= (symbolS
*) input_line_pointer
;
172 expressionP
->X_add_number
= reg_number
;
173 input_line_pointer
= p
;
182 check_range (num
, bits
, flags
)
190 /* Don't bother checking 16-bit values. */
194 if (flags
& OPERAND_SHIFT
)
196 /* All special shift operands are unsigned and <= 16.
197 We allow 0 for now. */
204 if (flags
& OPERAND_SIGNED
)
206 /* Signed 3-bit integers are restricted to the (-2, 3) range. */
207 if (flags
& RESTRICTED_NUM3
)
209 if ((long) num
< -2 || (long) num
> 3)
214 max
= (1 << (bits
- 1)) - 1;
215 min
= - (1 << (bits
- 1));
216 if (((long) num
> max
) || ((long) num
< min
))
222 max
= (1 << bits
) - 1;
224 if ((num
> max
) || (num
< min
))
231 md_show_usage (stream
)
234 fprintf (stream
, _("D10V options:\n\
235 -O optimize. Will do some operations in parallel.\n"));
239 md_parse_option (c
, arg
)
246 /* Optimize. Will attempt to parallelize operations. */
249 case OPTION_NOWARNSWAP
:
250 flag_warn_suppress_instructionswap
= 1;
259 md_undefined_symbol (name
)
265 /* Turn a string in input_line_pointer into a floating point constant
266 of type TYPE, and store the appropriate bytes in *LITP. The number
267 of LITTLENUMS emitted is stored in *SIZEP. An error message is
268 returned, or NULL on OK. */
271 md_atof (type
, litP
, sizeP
)
277 LITTLENUM_TYPE words
[4];
291 return _("bad call to md_atof");
294 t
= atof_ieee (input_line_pointer
, type
, words
);
296 input_line_pointer
= t
;
300 for (i
= 0; i
< prec
; i
++)
302 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
309 md_convert_frag (abfd
, sec
, fragP
)
318 md_section_align (seg
, addr
)
322 int align
= bfd_get_section_alignment (stdoutput
, seg
);
323 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
329 char *prev_name
= "";
330 struct d10v_opcode
*opcode
;
331 d10v_hash
= hash_new ();
333 /* Insert unique names into hash table. The D10v instruction set
334 has many identical opcode names that have different opcodes based
335 on the operands. This hash table then provides a quick index to
336 the first opcode with a particular name in the opcode table. */
338 for (opcode
= (struct d10v_opcode
*) d10v_opcodes
; opcode
->name
; opcode
++)
340 if (strcmp (prev_name
, opcode
->name
))
342 prev_name
= (char *) opcode
->name
;
343 hash_insert (d10v_hash
, opcode
->name
, (char *) opcode
);
348 FixUps
[0].next
= &FixUps
[1];
349 FixUps
[1].next
= &FixUps
[0];
352 /* Remove the postincrement or postdecrement operator ( '+' or '-' )
353 from an expression. */
359 while (*p
!= '-' && *p
!= '+')
361 if (*p
== 0 || *p
== '\n' || *p
== '\r')
380 static bfd_reloc_code_real_type
382 struct d10v_operand
*op
;
389 if (op
->flags
& OPERAND_ADDR
)
392 return (BFD_RELOC_D10V_10_PCREL_R
);
394 return (BFD_RELOC_D10V_18_PCREL
);
397 return (BFD_RELOC_16
);
400 /* Parse a string of operands. Return an array of expressions. */
406 char *p
= input_line_pointer
;
413 while (*p
== ' ' || *p
== '\t' || *p
== ',')
415 if (*p
== 0 || *p
== '\n' || *p
== '\r')
423 exp
[numops
].X_op
= O_absent
;
427 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
432 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
436 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
445 /* Just skip the trailing paren. */
450 input_line_pointer
= p
;
452 /* Check to see if it might be a register name. */
453 if (!register_name (&exp
[numops
]))
455 /* Parse as an expression. */
458 /* Any expression that involves the indirect addressing
459 cannot also involve immediate addressing. Therefore
460 the use of the hash character is illegal. */
461 int save
= do_not_ignore_hash
;
462 do_not_ignore_hash
= 1;
464 expression (&exp
[numops
]);
466 do_not_ignore_hash
= save
;
469 expression (&exp
[numops
]);
472 if (strncasecmp (input_line_pointer
, "@word", 5) == 0)
474 input_line_pointer
+= 5;
475 if (exp
[numops
].X_op
== O_register
)
477 /* If it looked like a register name but was followed by
478 "@word" then it was really a symbol, so change it to
480 exp
[numops
].X_op
= O_symbol
;
481 exp
[numops
].X_add_symbol
=
482 symbol_find_or_make ((char *) exp
[numops
].X_op_symbol
);
485 /* Check for identifier@word+constant. */
486 if (*input_line_pointer
== '-' || *input_line_pointer
== '+')
488 char *orig_line
= input_line_pointer
;
490 expression (&new_exp
);
491 exp
[numops
].X_add_number
= new_exp
.X_add_number
;
494 /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */
497 memset (&new_exp
, 0, sizeof new_exp
);
498 new_exp
.X_add_number
= AT_WORD_RIGHT_SHIFT
;
499 new_exp
.X_op
= O_constant
;
500 new_exp
.X_unsigned
= 1;
501 exp
[numops
].X_op_symbol
= make_expr_symbol (&new_exp
);
502 exp
[numops
].X_op
= O_right_shift
;
505 know (AT_WORD_P (&exp
[numops
]));
508 if (exp
[numops
].X_op
== O_illegal
)
509 as_bad (_("illegal operand"));
510 else if (exp
[numops
].X_op
== O_absent
)
511 as_bad (_("missing operand"));
514 p
= input_line_pointer
;
519 case -1: /* Postdecrement mode. */
520 exp
[numops
].X_op
= O_absent
;
521 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
523 case 1: /* Postincrement mode. */
524 exp
[numops
].X_op
= O_absent
;
525 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
529 exp
[numops
].X_op
= 0;
534 d10v_insert_operand (insn
, op_type
, value
, left
, fix
)
543 shift
= d10v_operands
[op_type
].shift
;
547 bits
= d10v_operands
[op_type
].bits
;
549 /* Truncate to the proper number of bits. */
550 if (check_range (value
, bits
, d10v_operands
[op_type
].flags
))
551 as_bad_where (fix
->fx_file
, fix
->fx_line
,
552 _("operand out of range: %d"), value
);
554 value
&= 0x7FFFFFFF >> (31 - bits
);
555 insn
|= (value
<< shift
);
560 /* Take a pointer to the opcode entry in the opcode table and the
561 array of operand expressions. Return the instruction. */
564 build_insn (opcode
, opers
, insn
)
565 struct d10v_opcode
*opcode
;
569 int i
, bits
, shift
, flags
, format
;
570 unsigned long number
;
572 /* The insn argument is only used for the DIVS kludge. */
577 insn
= opcode
->opcode
;
578 format
= opcode
->format
;
581 for (i
= 0; opcode
->operands
[i
]; i
++)
583 flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
584 bits
= d10v_operands
[opcode
->operands
[i
]].bits
;
585 shift
= d10v_operands
[opcode
->operands
[i
]].shift
;
586 number
= opers
[i
].X_add_number
;
588 if (flags
& OPERAND_REG
)
590 number
&= REGISTER_MASK
;
591 if (format
== LONG_L
)
595 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
)
597 /* Now create a fixup. */
599 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
600 as_fatal (_("too many fixups"));
602 if (AT_WORD_P (&opers
[i
]))
604 /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD). */
605 fixups
->fix
[fixups
->fc
].reloc
= BFD_RELOC_D10V_18
;
606 opers
[i
].X_op
= O_symbol
;
607 opers
[i
].X_op_symbol
= NULL
; /* Should free it. */
608 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
609 that, it is aligned with the symbol's value. Later,
610 BFD_RELOC_D10V_18 will right shift (symbol_value +
612 number
<<= AT_WORD_RIGHT_SHIFT
;
613 opers
[i
].X_add_number
= number
;
616 fixups
->fix
[fixups
->fc
].reloc
=
617 get_reloc ((struct d10v_operand
*) &d10v_operands
[opcode
->operands
[i
]]);
619 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_16
||
620 fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D10V_18
)
621 fixups
->fix
[fixups
->fc
].size
= 2;
623 fixups
->fix
[fixups
->fc
].size
= 4;
625 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
626 fixups
->fix
[fixups
->fc
].operand
= opcode
->operands
[i
];
627 fixups
->fix
[fixups
->fc
].pcrel
=
628 (flags
& OPERAND_ADDR
) ? true : false;
632 /* Truncate to the proper number of bits. */
633 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
634 as_bad (_("operand out of range: %d"), number
);
635 number
&= 0x7FFFFFFF >> (31 - bits
);
636 insn
= insn
| (number
<< shift
);
639 /* kludge: for DIVS, we need to put the operands in twice */
640 /* on the second pass, format is changed to LONG_R to force
641 the second set of operands to not be shifted over 15. */
642 if ((opcode
->opcode
== OPCODE_DIVS
) && (format
== LONG_L
))
643 insn
= build_insn (opcode
, opers
, insn
);
648 /* Write out a long form instruction. */
651 write_long (opcode
, insn
, fx
)
652 struct d10v_opcode
*opcode
;
657 char *f
= frag_more (4);
660 number_to_chars_bigendian (f
, insn
, 4);
662 for (i
= 0; i
< fx
->fc
; i
++)
664 if (fx
->fix
[i
].reloc
)
666 where
= f
- frag_now
->fr_literal
;
667 if (fx
->fix
[i
].size
== 2)
670 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
671 fx
->fix
[i
].operand
|= 4096;
673 fix_new_exp (frag_now
,
678 fx
->fix
[i
].operand
|2048);
684 /* Write out a short form instruction by itself. */
687 write_1_short (opcode
, insn
, fx
)
688 struct d10v_opcode
*opcode
;
692 char *f
= frag_more (4);
695 if (opcode
->exec_type
& PARONLY
)
696 as_fatal (_("Instruction must be executed in parallel with another instruction."));
698 /* The other container needs to be NOP. */
699 /* According to 4.3.1: for FM=00, sub-instructions performed only
700 by IU cannot be encoded in L-container. */
701 if (opcode
->unit
== IU
)
702 insn
|= FM00
| (NOP
<< 15); /* Right container. */
704 insn
= FM00
| (insn
<< 15) | NOP
; /* Left container. */
706 number_to_chars_bigendian (f
, insn
, 4);
707 for (i
= 0; i
< fx
->fc
; i
++)
709 if (fx
->fix
[i
].reloc
)
711 where
= f
- frag_now
->fr_literal
;
712 if (fx
->fix
[i
].size
== 2)
715 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
716 fx
->fix
[i
].operand
|= 4096;
718 /* If it's an R reloc, we may have to switch it to L. */
719 if ((fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
)
720 && (opcode
->unit
!= IU
))
721 fx
->fix
[i
].operand
|= 1024;
723 fix_new_exp (frag_now
,
728 fx
->fix
[i
].operand
|2048);
734 /* Expects two short instructions.
735 If possible, writes out both as a single packed instruction.
736 Otherwise, writes out the first one, packed with a NOP.
737 Returns number of instructions not written out. */
740 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
741 struct d10v_opcode
*opcode1
, *opcode2
;
742 unsigned long insn1
, insn2
;
743 packing_type exec_type
;
750 if ((exec_type
!= PACK_PARALLEL
)
751 && ((opcode1
->exec_type
& PARONLY
) || (opcode2
->exec_type
& PARONLY
)))
752 as_fatal (_("Instruction must be executed in parallel"));
754 if ((opcode1
->format
& LONG_OPCODE
) || (opcode2
->format
& LONG_OPCODE
))
755 as_fatal (_("Long instructions may not be combined."));
759 case PACK_UNSPEC
: /* Order not specified. */
760 if (opcode1
->exec_type
& ALONE
)
762 /* Case of a short branch on a separate GAS line.
764 write_1_short (opcode1
, insn1
, fx
->next
);
768 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
771 if (opcode1
->unit
== IU
)
772 insn
= FM00
| (insn2
<< 15) | insn1
;
773 else if (opcode2
->unit
== MU
)
774 insn
= FM00
| (insn2
<< 15) | insn1
;
777 insn
= FM00
| (insn1
<< 15) | insn2
;
778 /* Advance over dummy fixup since packed insn1 in L. */
782 else if (opcode1
->unit
== IU
)
783 /* Reverse sequential with IU opcode1 on right and done first. */
784 insn
= FM10
| (insn2
<< 15) | insn1
;
787 /* Sequential with non-IU opcode1 on left and done first. */
788 insn
= FM01
| (insn1
<< 15) | insn2
;
789 /* Advance over dummy fixup since packed insn1 in L. */
795 if (opcode1
->exec_type
& SEQ
|| opcode2
->exec_type
& SEQ
)
797 (_("One of these instructions may not be executed in parallel."));
798 if (opcode1
->unit
== IU
)
800 if (opcode2
->unit
== IU
)
801 as_fatal (_("Two IU instructions may not be executed in parallel"));
802 if (!flag_warn_suppress_instructionswap
)
803 as_warn (_("Swapping instruction order"));
804 insn
= FM00
| (insn2
<< 15) | insn1
;
806 else if (opcode2
->unit
== MU
)
808 if (opcode1
->unit
== MU
)
809 as_fatal (_("Two MU instructions may not be executed in parallel"));
810 if (!flag_warn_suppress_instructionswap
)
811 as_warn (_("Swapping instruction order"));
812 insn
= FM00
| (insn2
<< 15) | insn1
;
816 insn
= FM00
| (insn1
<< 15) | insn2
;
817 /* Advance over dummy fixup since packed insn1 in L. */
822 case PACK_LEFT_RIGHT
:
823 if (opcode1
->unit
!= IU
)
824 insn
= FM01
| (insn1
<< 15) | insn2
;
825 else if (opcode2
->unit
== MU
|| opcode2
->unit
== EITHER
)
827 if (!flag_warn_suppress_instructionswap
)
828 as_warn (_("Swapping instruction order"));
829 insn
= FM10
| (insn2
<< 15) | insn1
;
832 as_fatal (_("IU instruction may not be in the left container"));
833 if (opcode1
->exec_type
& ALONE
)
834 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
835 /* Advance over dummy fixup. */
839 case PACK_RIGHT_LEFT
:
840 if (opcode2
->unit
!= MU
)
841 insn
= FM10
| (insn1
<< 15) | insn2
;
842 else if (opcode1
->unit
== IU
|| opcode1
->unit
== EITHER
)
844 if (!flag_warn_suppress_instructionswap
)
845 as_warn (_("Swapping instruction order"));
846 insn
= FM01
| (insn2
<< 15) | insn1
;
849 as_fatal (_("MU instruction may not be in the right container"));
850 if (opcode2
->exec_type
& ALONE
)
851 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
852 /* Advance over dummy fixup. */
857 as_fatal (_("unknown execution type passed to write_2_short()"));
861 number_to_chars_bigendian (f
, insn
, 4);
863 /* Process fixup chains.
864 Note that the packing code above advanced fx conditionally.
865 dlindsay@cygnus.com: There's something subtle going on here involving
866 _dummy_first_bfd_reloc_code_real. This is related to the
867 difference between BFD_RELOC_D10V_10_PCREL_R and _L, ie whether
868 a fixup is done in the L or R container. A bug in this code
869 can pass Plum Hall fine, yet still affect hand-written assembler. */
871 for (j
= 0; j
< 2; j
++)
873 for (i
= 0; i
< fx
->fc
; i
++)
875 if (fx
->fix
[i
].reloc
)
877 where
= f
- frag_now
->fr_literal
;
878 if (fx
->fix
[i
].size
== 2)
881 if ((fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (j
== 0))
882 fx
->fix
[i
].operand
|= 1024;
884 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
885 fx
->fix
[i
].operand
|= 4096;
887 fix_new_exp (frag_now
,
892 fx
->fix
[i
].operand
|2048);
901 /* Check 2 instructions and determine if they can be safely
902 executed in parallel. Return 1 if they can be. */
905 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
906 struct d10v_opcode
*op1
, *op2
;
907 unsigned long insn1
, insn2
;
908 packing_type exec_type
;
910 int i
, j
, flags
, mask
, shift
, regno
;
911 unsigned long ins
, mod
[2], used
[2];
912 struct d10v_opcode
*op
;
914 if ((op1
->exec_type
& SEQ
) != 0 || (op2
->exec_type
& SEQ
) != 0
915 || (op1
->exec_type
& PAR
) == 0 || (op2
->exec_type
& PAR
) == 0
916 || (op1
->unit
== BOTH
) || (op2
->unit
== BOTH
)
917 || (op1
->unit
== IU
&& op2
->unit
== IU
)
918 || (op1
->unit
== MU
&& op2
->unit
== MU
))
921 /* If this is auto parallization, and either instruction is a branch,
923 if (exec_type
== PACK_UNSPEC
924 && (op1
->exec_type
& ALONE
|| op2
->exec_type
& ALONE
))
927 /* The idea here is to create two sets of bitmasks (mod and used)
928 which indicate which registers are modified or used by each
929 instruction. The operation can only be done in parallel if
930 instruction 1 and instruction 2 modify different registers, and
931 the first instruction does not modify registers that the second
932 is using (The second instruction can modify registers that the
933 first is using as they are only written back after the first
934 instruction has completed). Accesses to control registers, PSW,
935 and memory are treated as accesses to a single register. So if
936 both instructions write memory or if the first instruction writes
937 memory and the second reads, then they cannot be done in
938 parallel. Likewise, if the first instruction mucks with the psw
939 and the second reads the PSW (which includes C, F0, and F1), then
940 they cannot operate safely in parallel. */
942 /* The bitmasks (mod and used) look like this (bit 31 = MSB). */
945 /* cr (not psw) 18 */
949 for (j
= 0; j
< 2; j
++)
961 mod
[j
] = used
[j
] = 0;
962 if (op
->exec_type
& BRANCH_LINK
)
965 for (i
= 0; op
->operands
[i
]; i
++)
967 flags
= d10v_operands
[op
->operands
[i
]].flags
;
968 shift
= d10v_operands
[op
->operands
[i
]].shift
;
969 mask
= 0x7FFFFFFF >> (31 - d10v_operands
[op
->operands
[i
]].bits
);
970 if (flags
& OPERAND_REG
)
972 regno
= (ins
>> shift
) & mask
;
973 if (flags
& (OPERAND_ACC0
| OPERAND_ACC1
))
975 else if (flags
& OPERAND_CONTROL
) /* mvtc or mvfc. */
982 else if (flags
& (OPERAND_FFLAG
| OPERAND_CFLAG
))
985 if (flags
& OPERAND_DEST
)
987 mod
[j
] |= 1 << regno
;
988 if (flags
& OPERAND_EVEN
)
989 mod
[j
] |= 1 << (regno
+ 1);
993 used
[j
] |= 1 << regno
;
994 if (flags
& OPERAND_EVEN
)
995 used
[j
] |= 1 << (regno
+ 1);
997 /* Auto inc/dec also modifies the register. */
998 if (op
->operands
[i
+ 1] != 0
999 && (d10v_operands
[op
->operands
[i
+ 1]].flags
1000 & (OPERAND_PLUS
| OPERAND_MINUS
)) != 0)
1001 mod
[j
] |= 1 << regno
;
1004 else if (flags
& OPERAND_ATMINUS
)
1006 /* SP implicitly used/modified. */
1011 if (op
->exec_type
& RMEM
)
1013 else if (op
->exec_type
& WMEM
)
1015 else if (op
->exec_type
& RF0
)
1017 else if (op
->exec_type
& WF0
)
1019 else if (op
->exec_type
& WCAR
)
1022 if ((mod
[0] & mod
[1]) == 0 && (mod
[0] & used
[1]) == 0)
1027 /* This is the main entry point for the machine-dependent assembler.
1028 STR points to a machine-dependent instruction. This function is
1029 supposed to emit the frags/bytes it assembles to. For the D10V, it
1030 mostly handles the special VLIW parsing and packing and leaves the
1031 difficult stuff to do_assemble(). */
1033 static unsigned long prev_insn
;
1034 static struct d10v_opcode
*prev_opcode
= 0;
1035 static subsegT prev_subseg
;
1036 static segT prev_seg
= 0;;
1042 /* etype is saved extype. For multi-line instructions. */
1044 packing_type extype
= PACK_UNSPEC
; /* Parallel, etc. */
1046 struct d10v_opcode
*opcode
;
1050 if (etype
== PACK_UNSPEC
)
1052 /* Look for the special multiple instruction separators. */
1053 str2
= strstr (str
, "||");
1055 extype
= PACK_PARALLEL
;
1058 str2
= strstr (str
, "->");
1060 extype
= PACK_LEFT_RIGHT
;
1063 str2
= strstr (str
, "<-");
1065 extype
= PACK_RIGHT_LEFT
;
1068 /* STR2 points to the separator, if there is one. */
1073 /* If two instructions are present and we already have one saved,
1074 then first write out the saved one. */
1077 /* Assemble first instruction and save it. */
1078 prev_insn
= do_assemble (str
, &prev_opcode
);
1079 if (prev_insn
== -1)
1080 as_fatal (_("can't find opcode "));
1081 fixups
= fixups
->next
;
1086 insn
= do_assemble (str
, &opcode
);
1089 if (extype
!= PACK_UNSPEC
)
1094 as_fatal (_("can't find opcode "));
1097 if (etype
!= PACK_UNSPEC
)
1100 etype
= PACK_UNSPEC
;
1103 /* If this is a long instruction, write it and any previous short
1105 if (opcode
->format
& LONG_OPCODE
)
1107 if (extype
!= PACK_UNSPEC
)
1108 as_fatal (_("Unable to mix instructions as specified"));
1110 write_long (opcode
, insn
, fixups
);
1117 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1121 && (write_2_short (prev_opcode
, prev_insn
, opcode
, insn
, extype
, fixups
) == 0))
1123 /* No instructions saved. */
1128 if (extype
!= PACK_UNSPEC
)
1129 as_fatal (_("Unable to mix instructions as specified"));
1130 /* Save last instruction so it may be packed on next pass. */
1131 prev_opcode
= opcode
;
1134 prev_subseg
= now_subseg
;
1135 fixups
= fixups
->next
;
1139 /* Assemble a single instruction.
1140 Return an opcode, or -1 (an invalid opcode) on error. */
1142 static unsigned long
1143 do_assemble (str
, opcode
)
1145 struct d10v_opcode
**opcode
;
1147 unsigned char *op_start
, *save
;
1148 unsigned char *op_end
;
1151 expressionS myops
[6];
1154 /* Drop leading whitespace. */
1158 /* Find the opcode end. */
1159 for (op_start
= op_end
= (unsigned char *) (str
);
1162 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1165 name
[nlen
] = tolower (op_start
[nlen
]);
1173 /* Find the first opcode with the proper name. */
1174 *opcode
= (struct d10v_opcode
*) hash_find (d10v_hash
, name
);
1175 if (*opcode
== NULL
)
1176 as_fatal (_("unknown opcode: %s"), name
);
1178 save
= input_line_pointer
;
1179 input_line_pointer
= op_end
;
1180 *opcode
= find_opcode (*opcode
, myops
);
1183 input_line_pointer
= save
;
1185 insn
= build_insn ((*opcode
), myops
, 0);
1189 /* Find the symbol which has the same name as the register in EXP. */
1192 find_symbol_matching_register (exp
)
1197 if (exp
->X_op
!= O_register
)
1200 /* Find the name of the register. */
1201 for (i
= d10v_reg_name_cnt (); i
--;)
1202 if (d10v_predefined_registers
[i
].value
== exp
->X_add_number
)
1208 /* Now see if a symbol has been defined with the same name. */
1209 return symbol_find (d10v_predefined_registers
[i
].name
);
1212 /* Get a pointer to an entry in the opcode table.
1213 The function must look at all opcodes with the same name and use
1214 the operands to choose the correct opcode. */
1216 static struct d10v_opcode
*
1217 find_opcode (opcode
, myops
)
1218 struct d10v_opcode
*opcode
;
1219 expressionS myops
[];
1222 struct d10v_opcode
*next_opcode
;
1224 /* Get all the operands and save them as expressions. */
1225 get_operands (myops
);
1227 /* Now see if the operand is a fake. If so, find the correct size
1228 instruction, if possible. */
1229 if (opcode
->format
== OPCODE_FAKE
)
1231 int opnum
= opcode
->operands
[0];
1234 if (myops
[opnum
].X_op
== O_register
)
1236 myops
[opnum
].X_op
= O_symbol
;
1237 myops
[opnum
].X_add_symbol
=
1238 symbol_find_or_make ((char *) myops
[opnum
].X_op_symbol
);
1239 myops
[opnum
].X_add_number
= 0;
1240 myops
[opnum
].X_op_symbol
= NULL
;
1243 next_opcode
= opcode
+ 1;
1245 /* If the first operand is supposed to be a register, make sure
1246 we got a valid one. */
1247 flags
= d10v_operands
[next_opcode
->operands
[0]].flags
;
1248 if (flags
& OPERAND_REG
)
1250 int X_op
= myops
[0].X_op
;
1251 int num
= myops
[0].X_add_number
;
1253 if (X_op
!= O_register
1255 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1256 | OPERAND_FFLAG
| OPERAND_CFLAG
| OPERAND_CONTROL
)))
1258 as_bad (_("bad opcode or operands"));
1263 if (myops
[opnum
].X_op
== O_constant
1264 || (myops
[opnum
].X_op
== O_symbol
1265 && S_IS_DEFINED (myops
[opnum
].X_add_symbol
)
1266 && (S_GET_SEGMENT (myops
[opnum
].X_add_symbol
) == now_seg
)))
1268 for (i
= 0; opcode
->operands
[i
+ 1]; i
++)
1270 int bits
= d10v_operands
[next_opcode
->operands
[opnum
]].bits
;
1271 int flags
= d10v_operands
[next_opcode
->operands
[opnum
]].flags
;
1272 if (flags
& OPERAND_ADDR
)
1275 if (myops
[opnum
].X_op
== O_constant
)
1277 if (!check_range (myops
[opnum
].X_add_number
, bits
, flags
))
1284 unsigned long current_position
;
1285 unsigned long symbol_position
;
1286 unsigned long value
;
1287 boolean found_symbol
;
1289 /* Calculate the address of the current instruction
1290 and the address of the symbol. Do this by summing
1291 the offsets of previous frags until we reach the
1292 frag containing the symbol, and the current frag. */
1293 sym_frag
= symbol_get_frag (myops
[opnum
].X_add_symbol
);
1294 found_symbol
= false;
1297 obstack_next_free (&frchain_now
->frch_obstack
)
1298 - frag_now
->fr_literal
;
1299 symbol_position
= S_GET_VALUE (myops
[opnum
].X_add_symbol
);
1301 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1303 current_position
+= f
->fr_fix
+ f
->fr_offset
;
1306 found_symbol
= true;
1309 symbol_position
+= f
->fr_fix
+ f
->fr_offset
;
1312 value
= symbol_position
;
1314 if (flags
& OPERAND_ADDR
)
1315 value
-= current_position
;
1317 if (AT_WORD_P (&myops
[opnum
]))
1322 if (!check_range (value
, bits
, flags
))
1326 else if (!check_range (value
, bits
, flags
))
1331 as_fatal (_("value out of range"));
1335 /* Not a constant, so use a long instruction. */
1342 /* Now search the opcode table table for one with operands
1343 that matches what we've got. */
1347 for (i
= 0; opcode
->operands
[i
]; i
++)
1349 int flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
1350 int X_op
= myops
[i
].X_op
;
1351 int num
= myops
[i
].X_add_number
;
1359 if (flags
& OPERAND_REG
)
1361 if ((X_op
!= O_register
)
1363 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1364 | OPERAND_FFLAG
| OPERAND_CFLAG
1365 | OPERAND_CONTROL
)))
1372 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
1373 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
1374 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
1375 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
1376 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || ((num
!= OPERAND_ATSIGN
) && (num
!= OPERAND_ATPAR
)))))
1382 /* Unfortunatly, for the indirect operand in
1383 instructions such as ``ldb r1, @(c,r14)'' this
1384 function can be passed X_op == O_register (because
1385 'c' is a valid register name). However we cannot
1386 just ignore the case when X_op == O_register but
1387 flags & OPERAND_REG is null, so we check to see if a
1388 symbol of the same name as the register exists. If
1389 the symbol does exist, then the parser was unable to
1390 distinguish the two cases and we fix things here.
1393 if (!(flags
& OPERAND_REG
) && (X_op
== O_register
))
1395 symbolS
*sym
= find_symbol_matching_register (&myops
[i
]);
1399 myops
[i
].X_op
= X_op
= O_symbol
;
1400 myops
[i
].X_add_symbol
= sym
;
1404 (_("illegal operand - register name found where none expected"));
1408 /* We're only done if the operands matched so far AND there
1409 are no more to check. */
1410 if (match
&& myops
[i
].X_op
== 0)
1415 next_opcode
= opcode
+ 1;
1417 if (next_opcode
->opcode
== 0)
1420 if (strcmp (next_opcode
->name
, opcode
->name
))
1423 opcode
= next_opcode
;
1429 as_bad (_("bad opcode or operands"));
1433 /* Check that all registers that are required to be even are.
1434 Also, if any operands were marked as registers, but were really symbols,
1436 for (i
= 0; opcode
->operands
[i
]; i
++)
1438 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_EVEN
) &&
1439 (myops
[i
].X_add_number
& 1))
1440 as_fatal (_("Register number must be EVEN"));
1441 if (myops
[i
].X_op
== O_register
)
1443 if (!(d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_REG
))
1445 myops
[i
].X_op
= O_symbol
;
1446 myops
[i
].X_add_symbol
=
1447 symbol_find_or_make ((char *) myops
[i
].X_op_symbol
);
1448 myops
[i
].X_add_number
= 0;
1449 myops
[i
].X_op_symbol
= NULL
;
1456 /* If while processing a fixup, a reloc really needs to be created.
1457 Then it is done here. */
1460 tc_gen_reloc (seg
, fixp
)
1465 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1466 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1467 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1468 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1469 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1470 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1472 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1473 _("reloc %d not supported by object file format"),
1474 (int) fixp
->fx_r_type
);
1478 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1479 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1480 reloc
->address
= fixp
->fx_offset
;
1482 reloc
->addend
= fixp
->fx_addnumber
;
1488 md_estimate_size_before_relax (fragp
, seg
)
1497 md_pcrel_from_section (fixp
, sec
)
1501 if (fixp
->fx_addsy
!= (symbolS
*) NULL
1502 && (!S_IS_DEFINED (fixp
->fx_addsy
)
1503 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1505 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1509 md_apply_fix3 (fixp
, valuep
, seg
)
1520 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1525 else if (fixp
->fx_pcrel
)
1529 value
= fixp
->fx_offset
;
1530 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1532 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1533 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1536 /* We don't actually support subtracting a symbol. */
1537 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1538 _("expression too complex"));
1543 op_type
= fixp
->fx_r_type
;
1550 fixp
->fx_r_type
= BFD_RELOC_D10V_10_PCREL_L
;
1553 else if (op_type
& 4096)
1556 fixp
->fx_r_type
= BFD_RELOC_D10V_18
;
1560 get_reloc ((struct d10v_operand
*) &d10v_operands
[op_type
]);
1563 /* Fetch the instruction, insert the fully resolved operand
1564 value, and stuff the instruction back again. */
1565 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1566 insn
= bfd_getb32 ((unsigned char *) where
);
1568 switch (fixp
->fx_r_type
)
1570 case BFD_RELOC_D10V_10_PCREL_L
:
1571 case BFD_RELOC_D10V_10_PCREL_R
:
1572 case BFD_RELOC_D10V_18_PCREL
:
1573 case BFD_RELOC_D10V_18
:
1574 /* Instruction addresses are always right-shifted by 2. */
1575 value
>>= AT_WORD_RIGHT_SHIFT
;
1576 if (fixp
->fx_size
== 2)
1577 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1580 struct d10v_opcode
*rep
, *repi
;
1582 rep
= (struct d10v_opcode
*) hash_find (d10v_hash
, "rep");
1583 repi
= (struct d10v_opcode
*) hash_find (d10v_hash
, "repi");
1584 if ((insn
& FM11
) == FM11
1585 && ((repi
!= NULL
&& (insn
& repi
->mask
) == repi
->opcode
)
1586 || (rep
!= NULL
&& (insn
& rep
->mask
) == rep
->opcode
))
1589 (_("line %d: rep or repi must include at least 4 instructions"),
1592 d10v_insert_operand (insn
, op_type
, (offsetT
) value
, left
, fixp
);
1593 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1597 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1600 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1603 case BFD_RELOC_VTABLE_INHERIT
:
1604 case BFD_RELOC_VTABLE_ENTRY
:
1609 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1610 fixp
->fx_line
, fixp
->fx_r_type
);
1615 /* Called after the assembler has finished parsing the input file or
1616 after a label is defined. Because the D10V assembler sometimes
1617 saves short instructions to see if it can package them with the
1618 next instruction, there may be a short instruction that still needs
1621 NOTE: accesses a global, etype.
1622 NOTE: invoked by various macros such as md_cleanup: see. */
1630 if (prev_opcode
&& etype
== PACK_UNSPEC
)
1633 subseg
= now_subseg
;
1635 subseg_set (prev_seg
, prev_subseg
);
1636 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
1637 subseg_set (seg
, subseg
);
1643 /* Like normal .word, except support @word. */
1644 /* Clobbers input_line_pointer, checks end-of-line. */
1647 d10v_dot_word (nbytes
)
1648 register int nbytes
; /* 1=.byte, 2=.word, 4=.long */
1651 bfd_reloc_code_real_type reloc
;
1655 if (is_it_end_of_statement ())
1657 demand_empty_rest_of_line ();
1664 if (!strncasecmp (input_line_pointer
, "@word", 5))
1666 exp
.X_add_number
= 0;
1667 input_line_pointer
+= 5;
1670 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
1671 &exp
, 0, BFD_RELOC_D10V_18
);
1674 emit_expr (&exp
, 2);
1676 while (*input_line_pointer
++ == ',');
1678 input_line_pointer
--; /* Put terminator back into stream. */
1679 demand_empty_rest_of_line ();
1682 /* Mitsubishi asked that we support some old syntax that apparently
1683 had immediate operands starting with '#'. This is in some of their
1684 sample code but is not documented (although it appears in some
1685 examples in their assembler manual). For now, we'll solve this
1686 compatibility problem by simply ignoring any '#' at the beginning
1689 /* Operands that begin with '#' should fall through to here. */
1693 md_operand (expressionP
)
1694 expressionS
*expressionP
;
1696 if (*input_line_pointer
== '#' && ! do_not_ignore_hash
)
1698 input_line_pointer
++;
1699 expression (expressionP
);
1704 d10v_fix_adjustable (fixP
)
1707 if (fixP
->fx_addsy
== NULL
)
1710 /* Prevent all adjustments to global symbols. */
1711 if (S_IS_EXTERN (fixP
->fx_addsy
))
1713 if (S_IS_WEAK (fixP
->fx_addsy
))
1716 /* We need the symbol name for the VTABLE entries. */
1717 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1718 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1725 d10v_force_relocation (fixp
)
1728 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1729 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)