1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
3 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d10v.h"
29 const char comment_chars
[] = ";";
30 const char line_comment_chars
[] = "#";
31 const char line_separator_chars
[] = "";
32 const char *md_shortopts
= "O";
33 const char EXP_CHARS
[] = "eE";
34 const char FLT_CHARS
[] = "dD";
38 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
39 && (X)->X_op_symbol != NULL \
40 && (X)->X_op_symbol->sy_value.X_op == O_constant \
41 && (X)->X_op_symbol->sy_value.X_add_number == AT_WORD_RIGHT_SHIFT)
42 #define AT_WORD_RIGHT_SHIFT 2
46 #define MAX_INSN_FIXUPS (5)
53 bfd_reloc_code_real_type reloc
;
56 typedef struct _fixups
59 struct d10v_fixup fix
[MAX_INSN_FIXUPS
];
63 static Fixups FixUps
[2];
64 static Fixups
*fixups
;
66 static int do_not_ignore_hash
= 0;
68 /* True if instruction swapping warnings should be inhibited. */
69 static unsigned char flag_warn_suppress_instructionswap
; /* --nowarnswap */
72 static int reg_name_search
PARAMS ((char *name
));
73 static int register_name
PARAMS ((expressionS
*expressionP
));
74 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
75 static int postfix
PARAMS ((char *p
));
76 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d10v_operand
*op
));
77 static int get_operands
PARAMS ((expressionS exp
[]));
78 static struct d10v_opcode
*find_opcode
PARAMS ((struct d10v_opcode
*opcode
, expressionS ops
[]));
79 static unsigned long build_insn
PARAMS ((struct d10v_opcode
*opcode
, expressionS
*opers
, unsigned long insn
));
80 static void write_long
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
81 static void write_1_short
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
82 static int write_2_short
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
83 struct d10v_opcode
*opcode2
, unsigned long insn2
, int exec_type
, Fixups
*fx
));
84 static unsigned long do_assemble
PARAMS ((char *str
, struct d10v_opcode
**opcode
));
85 static unsigned long d10v_insert_operand
PARAMS (( unsigned long insn
, int op_type
,
86 offsetT value
, int left
, fixS
*fix
));
87 static int parallel_ok
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
88 struct d10v_opcode
*opcode2
, unsigned long insn2
,
90 static symbolS
* find_symbol_matching_register
PARAMS ((expressionS
*));
92 struct option md_longopts
[] =
94 #define OPTION_NOWARNSWAP (OPTION_MD_BASE)
95 {"nowarnswap", no_argument
, NULL
, OPTION_NOWARNSWAP
},
96 {NULL
, no_argument
, NULL
, 0}
98 size_t md_longopts_size
= sizeof(md_longopts
);
100 static void d10v_dot_word
PARAMS ((int));
102 /* The target specific pseudo-ops which we support. */
103 const pseudo_typeS md_pseudo_table
[] =
105 { "word", d10v_dot_word
, 2 },
109 /* Opcode hash table. */
110 static struct hash_control
*d10v_hash
;
112 /* reg_name_search does a binary search of the d10v_predefined_registers
113 array to see if "name" is a valid regiter name. Returns the register
114 number from the array on success, or -1 on failure. */
117 reg_name_search (name
)
120 int middle
, low
, high
;
124 high
= d10v_reg_name_cnt() - 1;
128 middle
= (low
+ high
) / 2;
129 cmp
= strcasecmp (name
, d10v_predefined_registers
[middle
].name
);
135 return d10v_predefined_registers
[middle
].value
;
141 /* register_name() checks the string at input_line_pointer
142 to see if it is a valid register name */
145 register_name (expressionP
)
146 expressionS
*expressionP
;
149 char c
, *p
= input_line_pointer
;
151 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
158 /* look to see if it's in the register table */
159 reg_number
= reg_name_search (input_line_pointer
);
162 expressionP
->X_op
= O_register
;
163 /* temporarily store a pointer to the string here */
164 expressionP
->X_op_symbol
= (symbolS
*)input_line_pointer
;
165 expressionP
->X_add_number
= reg_number
;
166 input_line_pointer
= p
;
176 check_range (num
, bits
, flags
)
184 /* don't bother checking 16-bit values */
188 if (flags
& OPERAND_SHIFT
)
190 /* all special shift operands are unsigned */
191 /* and <= 16. We allow 0 for now. */
198 if (flags
& OPERAND_SIGNED
)
200 max
= (1 << (bits
- 1))-1;
201 min
= - (1 << (bits
- 1));
202 if (((long)num
> max
) || ((long)num
< min
))
207 max
= (1 << bits
) - 1;
209 if ((num
> max
) || (num
< min
))
217 md_show_usage (stream
)
220 fprintf(stream
, _("D10V options:\n\
221 -O optimize. Will do some operations in parallel.\n"));
225 md_parse_option (c
, arg
)
232 /* Optimize. Will attempt to parallelize operations */
235 case OPTION_NOWARNSWAP
:
236 flag_warn_suppress_instructionswap
= 1;
245 md_undefined_symbol (name
)
251 /* Turn a string in input_line_pointer into a floating point constant of type
252 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
253 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
256 md_atof (type
, litP
, sizeP
)
262 LITTLENUM_TYPE words
[4];
276 return _("bad call to md_atof");
279 t
= atof_ieee (input_line_pointer
, type
, words
);
281 input_line_pointer
= t
;
285 for (i
= 0; i
< prec
; i
++)
287 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
294 md_convert_frag (abfd
, sec
, fragP
)
303 md_section_align (seg
, addr
)
307 int align
= bfd_get_section_alignment (stdoutput
, seg
);
308 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
315 char *prev_name
= "";
316 struct d10v_opcode
*opcode
;
317 d10v_hash
= hash_new();
319 /* Insert unique names into hash table. The D10v instruction set
320 has many identical opcode names that have different opcodes based
321 on the operands. This hash table then provides a quick index to
322 the first opcode with a particular name in the opcode table. */
324 for (opcode
= (struct d10v_opcode
*)d10v_opcodes
; opcode
->name
; opcode
++)
326 if (strcmp (prev_name
, opcode
->name
))
328 prev_name
= (char *)opcode
->name
;
329 hash_insert (d10v_hash
, opcode
->name
, (char *) opcode
);
334 FixUps
[0].next
= &FixUps
[1];
335 FixUps
[1].next
= &FixUps
[0];
339 /* this function removes the postincrement or postdecrement
340 operator ( '+' or '-' ) from an expression */
342 static int postfix (p
)
345 while (*p
!= '-' && *p
!= '+')
347 if (*p
==0 || *p
=='\n' || *p
=='\r')
367 static bfd_reloc_code_real_type
369 struct d10v_operand
*op
;
376 if (op
->flags
& OPERAND_ADDR
)
379 return (BFD_RELOC_D10V_10_PCREL_R
);
381 return (BFD_RELOC_D10V_18_PCREL
);
384 return (BFD_RELOC_16
);
388 /* get_operands parses a string of operands and returns
389 an array of expressions */
395 char *p
= input_line_pointer
;
402 while (*p
== ' ' || *p
== '\t' || *p
== ',')
404 if (*p
==0 || *p
=='\n' || *p
=='\r')
412 exp
[numops
].X_op
= O_absent
;
416 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
421 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
425 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
434 /* just skip the trailing paren */
439 input_line_pointer
= p
;
441 /* check to see if it might be a register name */
442 if (!register_name (&exp
[numops
]))
444 /* parse as an expression */
447 /* Any expression that involves the indirect addressing
448 cannot also involve immediate addressing. Therefore
449 the use of the hash character is illegal. */
450 int save
= do_not_ignore_hash
;
451 do_not_ignore_hash
= 1;
453 expression (&exp
[numops
]);
455 do_not_ignore_hash
= save
;
458 expression (&exp
[numops
]);
461 if (strncasecmp (input_line_pointer
, "@word", 5) == 0)
463 input_line_pointer
+= 5;
464 if (exp
[numops
].X_op
== O_register
)
466 /* if it looked like a register name but was followed by
467 "@word" then it was really a symbol, so change it to
469 exp
[numops
].X_op
= O_symbol
;
470 exp
[numops
].X_add_symbol
= symbol_find_or_make ((char *)exp
[numops
].X_op_symbol
);
473 /* check for identifier@word+constant */
474 if (*input_line_pointer
== '-' || *input_line_pointer
== '+')
476 char *orig_line
= input_line_pointer
;
478 expression (&new_exp
);
479 exp
[numops
].X_add_number
= new_exp
.X_add_number
;
482 /* convert expr into a right shift by AT_WORD_RIGHT_SHIFT */
485 memset (&new_exp
, 0, sizeof new_exp
);
486 new_exp
.X_add_number
= AT_WORD_RIGHT_SHIFT
;
487 new_exp
.X_op
= O_constant
;
488 new_exp
.X_unsigned
= 1;
489 exp
[numops
].X_op_symbol
= make_expr_symbol (&new_exp
);
490 exp
[numops
].X_op
= O_right_shift
;
493 know (AT_WORD_P (&exp
[numops
]));
496 if (exp
[numops
].X_op
== O_illegal
)
497 as_bad (_("illegal operand"));
498 else if (exp
[numops
].X_op
== O_absent
)
499 as_bad (_("missing operand"));
502 p
= input_line_pointer
;
507 case -1: /* postdecrement mode */
508 exp
[numops
].X_op
= O_absent
;
509 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
511 case 1: /* postincrement mode */
512 exp
[numops
].X_op
= O_absent
;
513 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
517 exp
[numops
].X_op
= 0;
522 d10v_insert_operand (insn
, op_type
, value
, left
, fix
)
531 shift
= d10v_operands
[op_type
].shift
;
535 bits
= d10v_operands
[op_type
].bits
;
537 /* truncate to the proper number of bits */
538 if (check_range (value
, bits
, d10v_operands
[op_type
].flags
))
539 as_bad_where (fix
->fx_file
, fix
->fx_line
, _("operand out of range: %d"), value
);
541 value
&= 0x7FFFFFFF >> (31 - bits
);
542 insn
|= (value
<< shift
);
548 /* build_insn takes a pointer to the opcode entry in the opcode table
549 and the array of operand expressions and returns the instruction */
552 build_insn (opcode
, opers
, insn
)
553 struct d10v_opcode
*opcode
;
557 int i
, bits
, shift
, flags
, format
;
558 unsigned long number
;
560 /* the insn argument is only used for the DIVS kludge */
565 insn
= opcode
->opcode
;
566 format
= opcode
->format
;
569 for (i
=0;opcode
->operands
[i
];i
++)
571 flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
572 bits
= d10v_operands
[opcode
->operands
[i
]].bits
;
573 shift
= d10v_operands
[opcode
->operands
[i
]].shift
;
574 number
= opers
[i
].X_add_number
;
576 if (flags
& OPERAND_REG
)
578 number
&= REGISTER_MASK
;
579 if (format
== LONG_L
)
583 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
)
585 /* now create a fixup */
587 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
588 as_fatal (_("too many fixups"));
590 if (AT_WORD_P (&opers
[i
]))
592 /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD) */
593 fixups
->fix
[fixups
->fc
].reloc
= BFD_RELOC_D10V_18
;
594 opers
[i
].X_op
= O_symbol
;
595 opers
[i
].X_op_symbol
= NULL
; /* Should free it */
596 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
597 that, it is aligned with the symbol's value. Later,
598 BFD_RELOC_D10V_18 will right shift (symbol_value +
600 number
<<= AT_WORD_RIGHT_SHIFT
;
601 opers
[i
].X_add_number
= number
;
604 fixups
->fix
[fixups
->fc
].reloc
=
605 get_reloc((struct d10v_operand
*)&d10v_operands
[opcode
->operands
[i
]]);
607 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_16
||
608 fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D10V_18
)
609 fixups
->fix
[fixups
->fc
].size
= 2;
611 fixups
->fix
[fixups
->fc
].size
= 4;
613 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
614 fixups
->fix
[fixups
->fc
].operand
= opcode
->operands
[i
];
615 fixups
->fix
[fixups
->fc
].pcrel
= (flags
& OPERAND_ADDR
) ? true : false;
619 /* truncate to the proper number of bits */
620 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
621 as_bad (_("operand out of range: %d"),number
);
622 number
&= 0x7FFFFFFF >> (31 - bits
);
623 insn
= insn
| (number
<< shift
);
626 /* kludge: for DIVS, we need to put the operands in twice */
627 /* on the second pass, format is changed to LONG_R to force */
628 /* the second set of operands to not be shifted over 15 */
629 if ((opcode
->opcode
== OPCODE_DIVS
) && (format
==LONG_L
))
630 insn
= build_insn (opcode
, opers
, insn
);
635 /* write out a long form instruction */
637 write_long (opcode
, insn
, fx
)
638 struct d10v_opcode
*opcode
;
643 char *f
= frag_more(4);
646 number_to_chars_bigendian (f
, insn
, 4);
648 for (i
=0; i
< fx
->fc
; i
++)
650 if (fx
->fix
[i
].reloc
)
652 where
= f
- frag_now
->fr_literal
;
653 if (fx
->fix
[i
].size
== 2)
656 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
657 fx
->fix
[i
].operand
|= 4096;
659 fix_new_exp (frag_now
,
664 fx
->fix
[i
].operand
|2048);
671 /* write out a short form instruction by itself */
673 write_1_short (opcode
, insn
, fx
)
674 struct d10v_opcode
*opcode
;
678 char *f
= frag_more(4);
681 if (opcode
->exec_type
& PARONLY
)
682 as_fatal (_("Instruction must be executed in parallel with another instruction."));
684 /* the other container needs to be NOP */
685 /* according to 4.3.1: for FM=00, sub-instructions performed only
686 by IU cannot be encoded in L-container. */
687 if (opcode
->unit
== IU
)
688 insn
|= FM00
| (NOP
<< 15); /* right container */
690 insn
= FM00
| (insn
<< 15) | NOP
; /* left container */
692 number_to_chars_bigendian (f
, insn
, 4);
693 for (i
=0; i
< fx
->fc
; i
++)
695 if (fx
->fix
[i
].reloc
)
697 where
= f
- frag_now
->fr_literal
;
698 if (fx
->fix
[i
].size
== 2)
701 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
702 fx
->fix
[i
].operand
|= 4096;
704 /* if it's an R reloc, we may have to switch it to L */
705 if ( (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (opcode
->unit
!= IU
) )
706 fx
->fix
[i
].operand
|= 1024;
708 fix_new_exp (frag_now
,
713 fx
->fix
[i
].operand
|2048);
719 /* write out a short form instruction if possible */
720 /* return number of instructions not written out */
722 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
723 struct d10v_opcode
*opcode1
, *opcode2
;
724 unsigned long insn1
, insn2
;
732 if ( (exec_type
!= 1) && ((opcode1
->exec_type
& PARONLY
)
733 || (opcode2
->exec_type
& PARONLY
)))
734 as_fatal (_("Instruction must be executed in parallel"));
736 if ( (opcode1
->format
& LONG_OPCODE
) || (opcode2
->format
& LONG_OPCODE
))
737 as_fatal (_("Long instructions may not be combined."));
739 if(opcode1
->exec_type
& BRANCH_LINK
&& exec_type
== 0)
741 /* Instructions paired with a subroutine call are executed before the
742 subroutine, so don't do these pairings unless explicitly requested. */
743 write_1_short (opcode1
, insn1
, fx
->next
);
749 case 0: /* order not specified */
750 if ( Optimizing
&& parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
753 if (opcode1
->unit
== IU
)
754 insn
= FM00
| (insn2
<< 15) | insn1
;
755 else if (opcode2
->unit
== MU
)
756 insn
= FM00
| (insn2
<< 15) | insn1
;
759 insn
= FM00
| (insn1
<< 15) | insn2
;
763 else if (opcode1
->unit
== IU
)
765 /* reverse sequential */
766 insn
= FM10
| (insn2
<< 15) | insn1
;
771 insn
= FM01
| (insn1
<< 15) | insn2
;
775 case 1: /* parallel */
776 if (opcode1
->exec_type
& SEQ
|| opcode2
->exec_type
& SEQ
)
777 as_fatal (_("One of these instructions may not be executed in parallel."));
779 if (opcode1
->unit
== IU
)
781 if (opcode2
->unit
== IU
)
782 as_fatal (_("Two IU instructions may not be executed in parallel"));
783 if (!flag_warn_suppress_instructionswap
)
784 as_warn (_("Swapping instruction order"));
785 insn
= FM00
| (insn2
<< 15) | insn1
;
787 else if (opcode2
->unit
== MU
)
789 if (opcode1
->unit
== MU
)
790 as_fatal (_("Two MU instructions may not be executed in parallel"));
791 if (!flag_warn_suppress_instructionswap
)
792 as_warn (_("Swapping instruction order"));
793 insn
= FM00
| (insn2
<< 15) | insn1
;
797 insn
= FM00
| (insn1
<< 15) | insn2
;
801 case 2: /* sequential */
802 if (opcode1
->unit
!= IU
)
803 insn
= FM01
| (insn1
<< 15) | insn2
;
804 else if (opcode2
->unit
== MU
|| opcode2
->unit
== EITHER
)
806 if (!flag_warn_suppress_instructionswap
)
807 as_warn (_("Swapping instruction order"));
808 insn
= FM10
| (insn2
<< 15) | insn1
;
811 as_fatal (_("IU instruction may not be in the left container"));
814 case 3: /* reverse sequential */
815 if (opcode2
->unit
!= MU
)
816 insn
= FM10
| (insn1
<< 15) | insn2
;
817 else if (opcode1
->unit
== IU
|| opcode1
->unit
== EITHER
)
819 if (!flag_warn_suppress_instructionswap
)
820 as_warn (_("Swapping instruction order"));
821 insn
= FM01
| (insn2
<< 15) | insn1
;
824 as_fatal (_("MU instruction may not be in the right container"));
828 as_fatal (_("unknown execution type passed to write_2_short()"));
832 number_to_chars_bigendian (f
, insn
, 4);
836 for (i
=0; i
< fx
->fc
; i
++)
838 if (fx
->fix
[i
].reloc
)
840 where
= f
- frag_now
->fr_literal
;
841 if (fx
->fix
[i
].size
== 2)
844 if ( (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (j
== 0) )
845 fx
->fix
[i
].operand
|= 1024;
847 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
848 fx
->fix
[i
].operand
|= 4096;
850 fix_new_exp (frag_now
,
855 fx
->fix
[i
].operand
|2048);
865 /* Check 2 instructions and determine if they can be safely */
866 /* executed in parallel. Returns 1 if they can be. */
868 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
869 struct d10v_opcode
*op1
, *op2
;
870 unsigned long insn1
, insn2
;
873 int i
, j
, flags
, mask
, shift
, regno
;
874 unsigned long ins
, mod
[2], used
[2];
875 struct d10v_opcode
*op
;
877 if ((op1
->exec_type
& SEQ
) != 0 || (op2
->exec_type
& SEQ
) != 0
878 || (op1
->exec_type
& PAR
) == 0 || (op2
->exec_type
& PAR
) == 0
879 || (op1
->unit
== BOTH
) || (op2
->unit
== BOTH
)
880 || (op1
->unit
== IU
&& op2
->unit
== IU
)
881 || (op1
->unit
== MU
&& op2
->unit
== MU
))
884 /* If the first instruction is a branch and this is auto parallazation,
885 don't combine with any second instruction. */
886 if (exec_type
== 0 && (op1
->exec_type
& BRANCH
) != 0)
889 /* The idea here is to create two sets of bitmasks (mod and used)
890 which indicate which registers are modified or used by each
891 instruction. The operation can only be done in parallel if
892 instruction 1 and instruction 2 modify different registers, and
893 the first instruction does not modify registers that the second
894 is using (The second instruction can modify registers that the
895 first is using as they are only written back after the first
896 instruction has completed). Accesses to control registers, PSW,
897 and memory are treated as accesses to a single register. So if
898 both instructions write memory or if the first instruction writes
899 memory and the second reads, then they cannot be done in
900 parallel. Likewise, if the first instruction mucks with the psw
901 and the second reads the PSW (which includes C, F0, and F1), then
902 they cannot operate safely in parallel. */
904 /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
907 /* cr (not psw) 18 */
923 mod
[j
] = used
[j
] = 0;
924 if (op
->exec_type
& BRANCH_LINK
)
927 for (i
= 0; op
->operands
[i
]; i
++)
929 flags
= d10v_operands
[op
->operands
[i
]].flags
;
930 shift
= d10v_operands
[op
->operands
[i
]].shift
;
931 mask
= 0x7FFFFFFF >> (31 - d10v_operands
[op
->operands
[i
]].bits
);
932 if (flags
& OPERAND_REG
)
934 regno
= (ins
>> shift
) & mask
;
935 if (flags
& (OPERAND_ACC0
|OPERAND_ACC1
))
937 else if (flags
& OPERAND_CONTROL
) /* mvtc or mvfc */
944 else if (flags
& (OPERAND_FFLAG
|OPERAND_CFLAG
))
947 if ( flags
& OPERAND_DEST
)
949 mod
[j
] |= 1 << regno
;
950 if (flags
& OPERAND_EVEN
)
951 mod
[j
] |= 1 << (regno
+ 1);
955 used
[j
] |= 1 << regno
;
956 if (flags
& OPERAND_EVEN
)
957 used
[j
] |= 1 << (regno
+ 1);
959 /* Auto inc/dec also modifies the register. */
960 if (op
->operands
[i
+1] != 0
961 && (d10v_operands
[op
->operands
[i
+1]].flags
962 & (OPERAND_PLUS
| OPERAND_MINUS
)) != 0)
963 mod
[j
] |= 1 << regno
;
966 else if (flags
& OPERAND_ATMINUS
)
968 /* SP implicitly used/modified */
973 if (op
->exec_type
& RMEM
)
975 else if (op
->exec_type
& WMEM
)
977 else if (op
->exec_type
& RF0
)
979 else if (op
->exec_type
& WF0
)
981 else if (op
->exec_type
& WCAR
)
984 if ((mod
[0] & mod
[1]) == 0 && (mod
[0] & used
[1]) == 0)
990 /* This is the main entry point for the machine-dependent assembler. str points to a
991 machine-dependent instruction. This function is supposed to emit the frags/bytes
992 it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing
993 and leaves the difficult stuff to do_assemble().
996 static unsigned long prev_insn
;
997 static struct d10v_opcode
*prev_opcode
= 0;
998 static subsegT prev_subseg
;
999 static segT prev_seg
= 0;;
1000 static int etype
= 0; /* saved extype. used for multiline instructions */
1006 struct d10v_opcode
* opcode
;
1008 int extype
= 0; /* execution type; parallel, etc */
1013 /* look for the special multiple instruction separators */
1014 str2
= strstr (str
, "||");
1019 str2
= strstr (str
, "->");
1024 str2
= strstr (str
, "<-");
1029 /* str2 points to the separator, if one */
1034 /* if two instructions are present and we already have one saved
1035 then first write it out */
1038 /* assemble first instruction and save it */
1039 prev_insn
= do_assemble (str
, &prev_opcode
);
1040 if (prev_insn
== -1)
1041 as_fatal (_("can't find opcode "));
1042 fixups
= fixups
->next
;
1047 insn
= do_assemble (str
, &opcode
);
1055 as_fatal (_("can't find opcode "));
1064 /* if this is a long instruction, write it and any previous short instruction */
1065 if (opcode
->format
& LONG_OPCODE
)
1068 as_fatal (_("Unable to mix instructions as specified"));
1070 write_long (opcode
, insn
, fixups
);
1075 if (prev_opcode
&& prev_seg
&& ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1078 if (prev_opcode
&& (write_2_short (prev_opcode
, prev_insn
, opcode
, insn
, extype
, fixups
) == 0))
1080 /* no instructions saved */
1086 as_fatal (_("Unable to mix instructions as specified"));
1087 /* save off last instruction so it may be packed on next pass */
1088 prev_opcode
= opcode
;
1091 prev_subseg
= now_subseg
;
1092 fixups
= fixups
->next
;
1097 /* do_assemble assembles a single instruction and returns an opcode */
1098 /* it returns -1 (an invalid opcode) on error */
1100 static unsigned long
1101 do_assemble (str
, opcode
)
1103 struct d10v_opcode
**opcode
;
1105 unsigned char *op_start
, *save
;
1106 unsigned char *op_end
;
1109 expressionS myops
[6];
1112 /* Drop leading whitespace. */
1116 /* Find the opcode end. */
1117 for (op_start
= op_end
= (unsigned char *) (str
);
1120 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1123 name
[nlen
] = tolower (op_start
[nlen
]);
1131 /* Find the first opcode with the proper name. */
1132 *opcode
= (struct d10v_opcode
*)hash_find (d10v_hash
, name
);
1133 if (*opcode
== NULL
)
1134 as_fatal (_("unknown opcode: %s"),name
);
1136 save
= input_line_pointer
;
1137 input_line_pointer
= op_end
;
1138 *opcode
= find_opcode (*opcode
, myops
);
1141 input_line_pointer
= save
;
1143 insn
= build_insn ((*opcode
), myops
, 0);
1147 /* Find the symbol which has the same name as the register in the given expression. */
1149 find_symbol_matching_register (exp
)
1154 if (exp
->X_op
!= O_register
)
1157 /* Find the name of the register. */
1158 for (i
= d10v_reg_name_cnt (); i
--;)
1159 if (d10v_predefined_registers
[i
].value
== exp
->X_add_number
)
1165 /* Now see if a symbol has been defined with the same name. */
1166 return symbol_find (d10v_predefined_registers
[i
].name
);
1170 /* find_opcode() gets a pointer to an entry in the opcode table. */
1171 /* It must look at all opcodes with the same name and use the operands */
1172 /* to choose the correct opcode. */
1174 static struct d10v_opcode
*
1175 find_opcode (opcode
, myops
)
1176 struct d10v_opcode
*opcode
;
1177 expressionS myops
[];
1180 struct d10v_opcode
*next_opcode
;
1182 /* get all the operands and save them as expressions */
1183 get_operands (myops
);
1185 /* now see if the operand is a fake. If so, find the correct size */
1186 /* instruction, if possible */
1187 if (opcode
->format
== OPCODE_FAKE
)
1189 int opnum
= opcode
->operands
[0];
1192 if (myops
[opnum
].X_op
== O_register
)
1194 myops
[opnum
].X_op
= O_symbol
;
1195 myops
[opnum
].X_add_symbol
= symbol_find_or_make ((char *)myops
[opnum
].X_op_symbol
);
1196 myops
[opnum
].X_add_number
= 0;
1197 myops
[opnum
].X_op_symbol
= NULL
;
1200 next_opcode
=opcode
+1;
1202 /* If the first operand is supposed to be a register, make sure
1203 we got a valid one. */
1204 flags
= d10v_operands
[next_opcode
->operands
[0]].flags
;
1205 if (flags
& OPERAND_REG
)
1207 int X_op
= myops
[0].X_op
;
1208 int num
= myops
[0].X_add_number
;
1210 if (X_op
!= O_register
1212 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1213 | OPERAND_FFLAG
| OPERAND_CFLAG
| OPERAND_CONTROL
)))
1215 as_bad (_("bad opcode or operands"));
1220 if (myops
[opnum
].X_op
== O_constant
|| (myops
[opnum
].X_op
== O_symbol
&&
1221 S_IS_DEFINED(myops
[opnum
].X_add_symbol
) &&
1222 (S_GET_SEGMENT(myops
[opnum
].X_add_symbol
) == now_seg
)))
1224 for (i
=0; opcode
->operands
[i
+1]; i
++)
1226 int bits
= d10v_operands
[next_opcode
->operands
[opnum
]].bits
;
1227 int flags
= d10v_operands
[next_opcode
->operands
[opnum
]].flags
;
1228 if (flags
& OPERAND_ADDR
)
1230 if (myops
[opnum
].X_op
== O_constant
)
1232 if (!check_range (myops
[opnum
].X_add_number
, bits
, flags
))
1239 /* calculate the current address by running through the previous frags */
1240 /* and adding our current offset */
1241 for (value
= 0, f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1242 value
+= f
->fr_fix
+ f
->fr_offset
;
1244 if (flags
& OPERAND_ADDR
)
1245 value
= S_GET_VALUE(myops
[opnum
].X_add_symbol
) - value
-
1246 (obstack_next_free(&frchain_now
->frch_obstack
) - frag_now
->fr_literal
);
1248 value
= S_GET_VALUE(myops
[opnum
].X_add_symbol
);
1250 if (AT_WORD_P (&myops
[opnum
]))
1255 if (!check_range (value
, bits
, flags
))
1259 else if (!check_range (value
, bits
, flags
))
1264 as_fatal (_("value out of range"));
1268 /* not a constant, so use a long instruction */
1275 /* now search the opcode table table for one with operands */
1276 /* that matches what we've got */
1280 for (i
= 0; opcode
->operands
[i
]; i
++)
1282 int flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
1283 int X_op
= myops
[i
].X_op
;
1284 int num
= myops
[i
].X_add_number
;
1292 if (flags
& OPERAND_REG
)
1294 if ((X_op
!= O_register
)
1296 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1297 | OPERAND_FFLAG
| OPERAND_CFLAG
1298 | OPERAND_CONTROL
)))
1305 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
1306 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
1307 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
1308 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
1309 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATSIGN
))))
1315 /* Unfortunatly, for the indirect operand in instructions such as
1316 ``ldb r1, @(c,r14)'' this function can be passed X_op == O_register
1317 (because 'c' is a valid register name). However we cannot just
1318 ignore the case when X_op == O_register but flags & OPERAND_REG is
1319 null, so we check to see if a symbol of the same name as the register
1320 exists. If the symbol does exist, then the parser was unable to
1321 distinguish the two cases and we fix things here. (Ref: PR14826) */
1323 if (!(flags
& OPERAND_REG
) && (X_op
== O_register
))
1327 sym
= find_symbol_matching_register (& myops
[i
]);
1331 myops
[i
].X_op
== X_op
== O_symbol
;
1332 myops
[i
].X_add_symbol
= sym
;
1336 (_("illegal operand - register name found where none expected"));
1340 /* We're only done if the operands matched so far AND there
1341 are no more to check. */
1342 if (match
&& myops
[i
].X_op
== 0)
1347 next_opcode
= opcode
+ 1;
1349 if (next_opcode
->opcode
== 0)
1352 if (strcmp (next_opcode
->name
, opcode
->name
))
1355 opcode
= next_opcode
;
1361 as_bad (_("bad opcode or operands"));
1365 /* Check that all registers that are required to be even are. */
1366 /* Also, if any operands were marked as registers, but were really symbols */
1367 /* fix that here. */
1368 for (i
=0; opcode
->operands
[i
]; i
++)
1370 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_EVEN
) &&
1371 (myops
[i
].X_add_number
& 1))
1372 as_fatal (_("Register number must be EVEN"));
1373 if (myops
[i
].X_op
== O_register
)
1375 if (!(d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_REG
))
1377 myops
[i
].X_op
= O_symbol
;
1378 myops
[i
].X_add_symbol
= symbol_find_or_make ((char *)myops
[i
].X_op_symbol
);
1379 myops
[i
].X_add_number
= 0;
1380 myops
[i
].X_op_symbol
= NULL
;
1387 /* if while processing a fixup, a reloc really needs to be created */
1388 /* then it is done here */
1391 tc_gen_reloc (seg
, fixp
)
1396 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1397 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1398 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1399 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1400 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1402 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1403 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1407 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1408 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1409 reloc
->address
= fixp
->fx_offset
;
1411 reloc
->addend
= fixp
->fx_addnumber
;
1417 md_estimate_size_before_relax (fragp
, seg
)
1426 md_pcrel_from_section (fixp
, sec
)
1430 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1431 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1433 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1437 md_apply_fix3 (fixp
, valuep
, seg
)
1448 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1453 else if (fixp
->fx_pcrel
)
1457 value
= fixp
->fx_offset
;
1458 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1460 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1461 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1464 /* We don't actually support subtracting a symbol. */
1465 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1466 _("expression too complex"));
1471 op_type
= fixp
->fx_r_type
;
1478 fixp
->fx_r_type
= BFD_RELOC_D10V_10_PCREL_L
;
1481 else if (op_type
& 4096)
1484 fixp
->fx_r_type
= BFD_RELOC_D10V_18
;
1487 fixp
->fx_r_type
= get_reloc((struct d10v_operand
*)&d10v_operands
[op_type
]);
1490 /* Fetch the instruction, insert the fully resolved operand
1491 value, and stuff the instruction back again. */
1492 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1493 insn
= bfd_getb32 ((unsigned char *) where
);
1495 switch (fixp
->fx_r_type
)
1497 case BFD_RELOC_D10V_10_PCREL_L
:
1498 case BFD_RELOC_D10V_10_PCREL_R
:
1499 case BFD_RELOC_D10V_18_PCREL
:
1500 case BFD_RELOC_D10V_18
:
1501 /* instruction addresses are always right-shifted by 2 */
1502 value
>>= AT_WORD_RIGHT_SHIFT
;
1503 if (fixp
->fx_size
== 2)
1504 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1507 struct d10v_opcode
*rep
, *repi
;
1509 rep
= (struct d10v_opcode
*) hash_find (d10v_hash
, "rep");
1510 repi
= (struct d10v_opcode
*) hash_find (d10v_hash
, "repi");
1511 if ((insn
& FM11
) == FM11
1512 && (repi
!= NULL
&& (insn
& repi
->mask
) == repi
->opcode
1513 || rep
!= NULL
&& (insn
& rep
->mask
) == rep
->opcode
)
1516 (_("line %d: rep or repi must include at least 4 instructions"),
1518 insn
= d10v_insert_operand (insn
, op_type
, (offsetT
)value
, left
, fixp
);
1519 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1523 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1526 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1529 case BFD_RELOC_VTABLE_INHERIT
:
1530 case BFD_RELOC_VTABLE_ENTRY
:
1535 as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp
->fx_line
,fixp
->fx_r_type
);
1540 /* d10v_cleanup() is called after the assembler has finished parsing the input
1541 file or after a label is defined. Because the D10V assembler sometimes saves short
1542 instructions to see if it can package them with the next instruction, there may
1543 be a short instruction that still needs written. */
1550 if (prev_opcode
&& etype
== 0)
1553 subseg
= now_subseg
;
1555 subseg_set (prev_seg
, prev_subseg
);
1556 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
1557 subseg_set (seg
, subseg
);
1563 /* Like normal .word, except support @word */
1564 /* clobbers input_line_pointer, checks end-of-line. */
1566 d10v_dot_word (nbytes
)
1567 register int nbytes
; /* 1=.byte, 2=.word, 4=.long */
1570 bfd_reloc_code_real_type reloc
;
1574 if (is_it_end_of_statement ())
1576 demand_empty_rest_of_line ();
1583 if (!strncasecmp (input_line_pointer
, "@word", 5))
1585 exp
.X_add_number
= 0;
1586 input_line_pointer
+= 5;
1589 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
1590 &exp
, 0, BFD_RELOC_D10V_18
);
1593 emit_expr (&exp
, 2);
1595 while (*input_line_pointer
++ == ',');
1597 input_line_pointer
--; /* Put terminator back into stream. */
1598 demand_empty_rest_of_line ();
1602 /* Mitsubishi asked that we support some old syntax that apparently */
1603 /* had immediate operands starting with '#'. This is in some of their */
1604 /* sample code but is not documented (although it appears in some */
1605 /* examples in their assembler manual). For now, we'll solve this */
1606 /* compatibility problem by simply ignoring any '#' at the beginning */
1607 /* of an operand. */
1609 /* operands that begin with '#' should fall through to here */
1613 md_operand (expressionP
)
1614 expressionS
*expressionP
;
1616 if (*input_line_pointer
== '#' && ! do_not_ignore_hash
)
1618 input_line_pointer
++;
1619 expression (expressionP
);
1624 d10v_fix_adjustable (fixP
)
1628 if (fixP
->fx_addsy
== NULL
)
1631 /* Prevent all adjustments to global symbols. */
1632 if (S_IS_EXTERN (fixP
->fx_addsy
))
1634 if (S_IS_WEAK (fixP
->fx_addsy
))
1637 /* We need the symbol name for the VTABLE entries */
1638 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1639 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1646 d10v_force_relocation (fixp
)
1649 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1650 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)