1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
3 Copyright (C) 1996 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d10v.h"
29 const char comment_chars
[] = ";";
30 const char line_comment_chars
[] = "#";
31 const char line_separator_chars
[] = "";
32 const char *md_shortopts
= "O";
33 const char EXP_CHARS
[] = "eE";
34 const char FLT_CHARS
[] = "dD";
41 #define MAX_INSN_FIXUPS (5)
48 bfd_reloc_code_real_type reloc
;
51 typedef struct _fixups
54 struct d10v_fixup fix
[MAX_INSN_FIXUPS
];
58 static Fixups FixUps
[2];
59 static Fixups
*fixups
;
62 static int reg_name_search
PARAMS ((char *name
));
63 static int register_name
PARAMS ((expressionS
*expressionP
));
64 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
65 static int postfix
PARAMS ((char *p
));
66 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d10v_operand
*op
));
67 static int get_operands
PARAMS ((expressionS exp
[]));
68 static struct d10v_opcode
*find_opcode
PARAMS ((struct d10v_opcode
*opcode
, expressionS ops
[]));
69 static unsigned long build_insn
PARAMS ((struct d10v_opcode
*opcode
, expressionS
*opers
, unsigned long insn
));
70 static void write_long
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
71 static void write_1_short
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
72 static int write_2_short
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
73 struct d10v_opcode
*opcode2
, unsigned long insn2
, int exec_type
, Fixups
*fx
));
74 static unsigned long do_assemble
PARAMS ((char *str
, struct d10v_opcode
**opcode
));
75 static unsigned long d10v_insert_operand
PARAMS (( unsigned long insn
, int op_type
,
76 offsetT value
, int left
, fixS
*fix
));
77 static int parallel_ok
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
78 struct d10v_opcode
*opcode2
, unsigned long insn2
));
81 struct option md_longopts
[] = {
82 {NULL
, no_argument
, NULL
, 0}
84 size_t md_longopts_size
= sizeof(md_longopts
);
86 static void d10v_dot_word
PARAMS ((int));
88 /* The target specific pseudo-ops which we support. */
89 const pseudo_typeS md_pseudo_table
[] =
91 { "word", d10v_dot_word
, 2 },
95 /* Opcode hash table. */
96 static struct hash_control
*d10v_hash
;
98 /* reg_name_search does a binary search of the pre_defined_registers
99 array to see if "name" is a valid regiter name. Returns the register
100 number from the array on success, or -1 on failure. */
103 reg_name_search (name
)
106 int middle
, low
, high
;
110 high
= reg_name_cnt() - 1;
114 middle
= (low
+ high
) / 2;
115 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
121 return pre_defined_registers
[middle
].value
;
127 /* register_name() checks the string at input_line_pointer
128 to see if it is a valid register name */
131 register_name (expressionP
)
132 expressionS
*expressionP
;
135 char c
, *p
= input_line_pointer
;
137 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
144 /* look to see if it's in the register table */
145 reg_number
= reg_name_search (input_line_pointer
);
148 expressionP
->X_op
= O_register
;
149 /* temporarily store a pointer to the string here */
150 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
151 expressionP
->X_add_number
= reg_number
;
152 input_line_pointer
= p
;
162 check_range (num
, bits
, flags
)
170 /* don't bother checking 16-bit values */
174 if (flags
& OPERAND_SHIFT
)
176 /* all special shift operands are unsigned */
177 /* and <= 16. We allow 0 for now. */
184 if (flags
& OPERAND_SIGNED
)
186 max
= (1 << (bits
- 1))-1;
187 min
= - (1 << (bits
- 1));
188 if (((long)num
> max
) || ((long)num
< min
))
193 max
= (1 << bits
) - 1;
195 if ((num
> max
) || (num
< min
))
203 md_show_usage (stream
)
206 fprintf(stream
, "D10V options:\n\
207 -O optimize. Will do some operations in parallel.\n");
211 md_parse_option (c
, arg
)
218 /* Optimize. Will attempt to parallelize operations */
228 md_undefined_symbol (name
)
234 /* Turn a string in input_line_pointer into a floating point constant of type
235 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
236 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
239 md_atof (type
, litP
, sizeP
)
245 LITTLENUM_TYPE words
[4];
259 return "bad call to md_atof";
262 t
= atof_ieee (input_line_pointer
, type
, words
);
264 input_line_pointer
= t
;
268 for (i
= 0; i
< prec
; i
++)
270 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
277 md_convert_frag (abfd
, sec
, fragP
)
282 printf ("call to md_convert_frag \n");
287 md_section_align (seg
, addr
)
291 int align
= bfd_get_section_alignment (stdoutput
, seg
);
292 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
299 char *prev_name
= "";
300 struct d10v_opcode
*opcode
;
301 d10v_hash
= hash_new();
303 /* Insert unique names into hash table. The D10v instruction set
304 has many identical opcode names that have different opcodes based
305 on the operands. This hash table then provides a quick index to
306 the first opcode with a particular name in the opcode table. */
308 for (opcode
= (struct d10v_opcode
*)d10v_opcodes
; opcode
->name
; opcode
++)
310 if (strcmp (prev_name
, opcode
->name
))
312 prev_name
= (char *)opcode
->name
;
313 hash_insert (d10v_hash
, opcode
->name
, (char *) opcode
);
318 FixUps
[0].next
= &FixUps
[1];
319 FixUps
[1].next
= &FixUps
[0];
323 /* this function removes the postincrement or postdecrement
324 operator ( '+' or '-' ) from an expression */
326 static int postfix (p
)
329 while (*p
!= '-' && *p
!= '+')
331 if (*p
==0 || *p
=='\n' || *p
=='\r')
351 static bfd_reloc_code_real_type
353 struct d10v_operand
*op
;
357 /* printf("get_reloc: bits=%d address=%d\n",bits,op->flags & OPERAND_ADDR); */
361 if (op
->flags
& OPERAND_ADDR
)
364 return (BFD_RELOC_D10V_10_PCREL_R
);
366 return (BFD_RELOC_D10V_18_PCREL
);
369 return (BFD_RELOC_16
);
373 /* get_operands parses a string of operands and returns
374 an array of expressions */
380 char *p
= input_line_pointer
;
386 while (*p
== ' ' || *p
== '\t' || *p
== ',')
388 if (*p
==0 || *p
=='\n' || *p
=='\r')
394 exp
[numops
].X_op
= O_absent
;
398 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
403 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
407 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
416 /* just skip the trailing paren */
421 input_line_pointer
= p
;
423 /* check to see if it might be a register name */
424 if (!register_name (&exp
[numops
]))
426 /* parse as an expression */
427 expression (&exp
[numops
]);
430 if (!strncasecmp (input_line_pointer
, "@word", 5))
432 if (exp
[numops
].X_op
== O_register
)
434 /* if it looked like a register name but was followed by "@word" */
435 /* then it was really a symbol, so change it to one */
436 exp
[numops
].X_op
= O_symbol
;
437 exp
[numops
].X_add_symbol
= symbol_find_or_make ((char *)exp
[numops
].X_op_symbol
);
438 exp
[numops
].X_op_symbol
= NULL
;
440 exp
[numops
].X_add_number
= AT_WORD
;
441 input_line_pointer
+= 5;
444 if (exp
[numops
].X_op
== O_illegal
)
445 as_bad ("illegal operand");
446 else if (exp
[numops
].X_op
== O_absent
)
447 as_bad ("missing operand");
450 p
= input_line_pointer
;
455 case -1: /* postdecrement mode */
456 exp
[numops
].X_op
= O_absent
;
457 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
459 case 1: /* postincrement mode */
460 exp
[numops
].X_op
= O_absent
;
461 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
465 exp
[numops
].X_op
= 0;
470 d10v_insert_operand (insn
, op_type
, value
, left
, fix
)
479 shift
= d10v_operands
[op_type
].shift
;
483 bits
= d10v_operands
[op_type
].bits
;
485 /* truncate to the proper number of bits */
486 if (check_range (value
, bits
, d10v_operands
[op_type
].flags
))
487 as_bad_where (fix
->fx_file
, fix
->fx_line
, "operand out of range: %d", value
);
489 value
&= 0x7FFFFFFF >> (31 - bits
);
490 insn
|= (value
<< shift
);
496 /* build_insn takes a pointer to the opcode entry in the opcode table
497 and the array of operand expressions and returns the instruction */
500 build_insn (opcode
, opers
, insn
)
501 struct d10v_opcode
*opcode
;
505 int i
, bits
, shift
, flags
, format
;
508 /* the insn argument is only used for the DIVS kludge */
513 insn
= opcode
->opcode
;
514 format
= opcode
->format
;
517 for (i
=0;opcode
->operands
[i
];i
++)
519 flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
520 bits
= d10v_operands
[opcode
->operands
[i
]].bits
;
521 shift
= d10v_operands
[opcode
->operands
[i
]].shift
;
522 number
= opers
[i
].X_add_number
;
524 if (flags
& OPERAND_REG
)
526 number
&= REGISTER_MASK
;
527 if (format
== LONG_L
)
531 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
)
533 /* now create a fixup */
536 printf("need a fixup: ");
537 print_expr_1(stdout,&opers[i]);
541 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
542 as_fatal ("too many fixups");
544 if (opers
[i
].X_op
== O_symbol
&& number
== AT_WORD
)
546 number
= opers
[i
].X_add_number
= 0;
547 fixups
->fix
[fixups
->fc
].reloc
= BFD_RELOC_D10V_18
;
549 fixups
->fix
[fixups
->fc
].reloc
=
550 get_reloc((struct d10v_operand
*)&d10v_operands
[opcode
->operands
[i
]]);
552 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_16
||
553 fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D10V_18
)
554 fixups
->fix
[fixups
->fc
].size
= 2;
556 fixups
->fix
[fixups
->fc
].size
= 4;
558 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
559 fixups
->fix
[fixups
->fc
].operand
= opcode
->operands
[i
];
560 fixups
->fix
[fixups
->fc
].pcrel
= (flags
& OPERAND_ADDR
) ? true : false;
564 /* truncate to the proper number of bits */
565 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
566 as_bad("operand out of range: %d",number
);
567 number
&= 0x7FFFFFFF >> (31 - bits
);
568 insn
= insn
| (number
<< shift
);
571 /* kludge: for DIVS, we need to put the operands in twice */
572 /* on the second pass, format is changed to LONG_R to force */
573 /* the second set of operands to not be shifted over 15 */
574 if ((opcode
->opcode
== OPCODE_DIVS
) && (format
==LONG_L
))
575 insn
= build_insn (opcode
, opers
, insn
);
580 /* write out a long form instruction */
582 write_long (opcode
, insn
, fx
)
583 struct d10v_opcode
*opcode
;
588 char *f
= frag_more(4);
591 /* printf("INSN: %08x\n",insn); */
592 number_to_chars_bigendian (f
, insn
, 4);
594 for (i
=0; i
< fx
->fc
; i
++)
596 if (fx
->fix
[i
].reloc
)
598 where
= f
- frag_now
->fr_literal
;
599 if (fx
->fix
[i
].size
== 2)
602 printf("fix_new_exp: where:%x size:%d\n ",where,fx->fix[i].size);
603 print_expr_1(stdout,&(fx->fix[i].exp));
607 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
608 fx
->fix
[i
].operand
|= 4096;
610 fix_new_exp (frag_now
,
615 fx
->fix
[i
].operand
|2048);
622 /* write out a short form instruction by itself */
624 write_1_short (opcode
, insn
, fx
)
625 struct d10v_opcode
*opcode
;
629 char *f
= frag_more(4);
632 if (opcode
->exec_type
& PARONLY
)
633 as_fatal ("Instruction must be executed in parallel with another instruction.");
635 /* the other container needs to be NOP */
636 /* according to 4.3.1: for FM=00, sub-instructions performed only
637 by IU cannot be encoded in L-container. */
638 if (opcode
->unit
== IU
)
639 insn
|= FM00
| (NOP
<< 15); /* right container */
641 insn
= FM00
| (insn
<< 15) | NOP
; /* left container */
643 /* printf("INSN: %08x\n",insn); */
644 number_to_chars_bigendian (f
, insn
, 4);
645 for (i
=0; i
< fx
->fc
; i
++)
647 if (fx
->fix
[i
].reloc
)
649 where
= f
- frag_now
->fr_literal
;
650 if (fx
->fix
[i
].size
== 2)
654 printf("fix_new_exp: where:%x size:%d\n ",where, fx->fix[i].size);
655 print_expr_1(stdout,&(fx->fix[i].exp));
659 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
660 fx
->fix
[i
].operand
|= 4096;
662 /* if it's an R reloc, we may have to switch it to L */
663 if ( (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (opcode
->unit
!= IU
) )
664 fx
->fix
[i
].operand
|= 1024;
666 fix_new_exp (frag_now
,
671 fx
->fix
[i
].operand
|2048);
677 /* write out a short form instruction if possible */
678 /* return number of instructions not written out */
680 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
681 struct d10v_opcode
*opcode1
, *opcode2
;
682 unsigned long insn1
, insn2
;
690 if ( (exec_type
!= 1) && ((opcode1
->exec_type
& PARONLY
)
691 || (opcode2
->exec_type
& PARONLY
)))
692 as_fatal("Instruction must be executed in parallel");
694 if ( (opcode1
->format
& LONG_OPCODE
) || (opcode2
->format
& LONG_OPCODE
))
695 as_fatal ("Long instructions may not be combined.");
697 if(opcode1
->exec_type
& BRANCH_LINK
&& opcode2
->exec_type
!= PARONLY
)
699 /* subroutines must be called from 32-bit boundaries */
700 /* so the return address will be correct */
701 write_1_short (opcode1
, insn1
, fx
->next
);
707 case 0: /* order not specified */
708 if ( Optimizing
&& parallel_ok (opcode1
, insn1
, opcode2
, insn2
))
711 if (opcode1
->unit
== IU
)
712 insn
= FM00
| (insn2
<< 15) | insn1
;
713 else if (opcode2
->unit
== MU
)
714 insn
= FM00
| (insn2
<< 15) | insn1
;
717 insn
= FM00
| (insn1
<< 15) | insn2
;
721 else if (opcode1
->unit
== IU
)
723 /* reverse sequential */
724 insn
= FM10
| (insn2
<< 15) | insn1
;
729 insn
= FM01
| (insn1
<< 15) | insn2
;
733 case 1: /* parallel */
734 if (opcode1
->exec_type
& SEQ
|| opcode2
->exec_type
& SEQ
)
735 as_fatal ("One of these instructions may not be executed in parallel.");
737 if ( !parallel_ok (opcode1
, insn1
, opcode2
, insn2
)
738 && (opcode1
->exec_type
& PARONLY
) == 0
739 && (opcode2
->exec_type
& PARONLY
) == 0)
740 as_fatal ("Two instructions may not be executed in parallel with each other.");
742 if (opcode1
->unit
== IU
)
744 if (opcode2
->unit
== IU
)
745 as_fatal ("Two IU instructions may not be executed in parallel");
746 as_warn ("Swapping instruction order");
747 insn
= FM00
| (insn2
<< 15) | insn1
;
749 else if (opcode2
->unit
== MU
)
751 if (opcode1
->unit
== MU
)
752 as_fatal ("Two MU instructions may not be executed in parallel");
753 as_warn ("Swapping instruction order");
754 insn
= FM00
| (insn2
<< 15) | insn1
;
758 insn
= FM00
| (insn1
<< 15) | insn2
;
762 case 2: /* sequential */
763 if (opcode1
->unit
== IU
)
764 as_fatal ("IU instruction may not be in the left container");
765 insn
= FM01
| (insn1
<< 15) | insn2
;
768 case 3: /* reverse sequential */
769 if (opcode2
->unit
== MU
)
770 as_fatal ("MU instruction may not be in the right container");
771 insn
= FM10
| (insn1
<< 15) | insn2
;
775 as_fatal("unknown execution type passed to write_2_short()");
778 /* printf("INSN: %08x\n",insn); */
780 number_to_chars_bigendian (f
, insn
, 4);
784 for (i
=0; i
< fx
->fc
; i
++)
786 if (fx
->fix
[i
].reloc
)
788 where
= f
- frag_now
->fr_literal
;
789 if (fx
->fix
[i
].size
== 2)
792 if ( (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (j
== 0) )
793 fx
->fix
[i
].operand
|= 1024;
795 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
796 fx
->fix
[i
].operand
|= 4096;
799 printf("fix_new_exp: where:%x reloc:%d\n ",where,fx->fix[i].operand);
800 print_expr_1(stdout,&(fx->fix[i].exp));
804 fix_new_exp (frag_now
,
809 fx
->fix
[i
].operand
|2048);
819 /* Check 2 instructions and determine if they can be safely */
820 /* executed in parallel. Returns 1 if they can be. */
822 parallel_ok (op1
, insn1
, op2
, insn2
)
823 struct d10v_opcode
*op1
, *op2
;
824 unsigned long insn1
, insn2
;
826 int i
, j
, flags
, mask
, shift
, regno
;
827 unsigned long ins
, mod
[2], used
[2];
828 struct d10v_opcode
*op
;
830 if ((op1
->exec_type
& SEQ
) != 0 || (op2
->exec_type
& SEQ
) != 0
831 || (op1
->exec_type
& PAR
) == 0 || (op2
->exec_type
& PAR
) == 0
832 || (op1
->unit
== BOTH
) || (op2
->unit
== BOTH
)
833 || (op1
->unit
== IU
&& op2
->unit
== IU
)
834 || (op1
->unit
== MU
&& op2
->unit
== MU
))
837 /* The idea here is to create two sets of bitmasks (mod and used) */
838 /* which indicate which registers are modified or used by each instruction. */
839 /* The operation can only be done in parallel if instruction 1 and instruction 2 */
840 /* modify different registers, and neither instruction modifies any registers */
841 /* the other is using. Accesses to control registers, PSW, and memory are treated */
842 /* as accesses to a single register. So if both instructions write memory or one */
843 /* instruction writes memory and the other reads, then they cannot be done in parallel. */
844 /* Likewise, if one instruction mucks with the psw and the other reads the PSW */
845 /* (which includes C, F0, and F1), then they cannot operate safely in parallel. */
847 /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
850 /* cr (not psw) 18 */
866 mod
[j
] = used
[j
] = 0;
867 if (op
->exec_type
& BRANCH_LINK
)
870 for (i
= 0; op
->operands
[i
]; i
++)
872 flags
= d10v_operands
[op
->operands
[i
]].flags
;
873 shift
= d10v_operands
[op
->operands
[i
]].shift
;
874 mask
= 0x7FFFFFFF >> (31 - d10v_operands
[op
->operands
[i
]].bits
);
875 if (flags
& OPERAND_REG
)
877 regno
= (ins
>> shift
) & mask
;
878 if (flags
& OPERAND_ACC
)
880 else if (flags
& OPERAND_CONTROL
) /* mvtc or mvfc */
887 else if (flags
& OPERAND_FLAG
)
890 if ( flags
& OPERAND_DEST
)
892 mod
[j
] |= 1 << regno
;
893 if (flags
& OPERAND_EVEN
)
894 mod
[j
] |= 1 << (regno
+ 1);
898 used
[j
] |= 1 << regno
;
899 if (flags
& OPERAND_EVEN
)
900 used
[j
] |= 1 << (regno
+ 1);
904 if (op
->exec_type
& RMEM
)
906 else if (op
->exec_type
& WMEM
)
908 else if (op
->exec_type
& RF0
)
910 else if (op
->exec_type
& WF0
)
912 else if (op
->exec_type
& WCAR
)
915 if ((mod
[0] & mod
[1]) == 0 && (mod
[0] & used
[1]) == 0 && (mod
[1] & used
[0]) == 0)
921 /* This is the main entry point for the machine-dependent assembler. str points to a
922 machine-dependent instruction. This function is supposed to emit the frags/bytes
923 it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing
924 and leaves the difficult stuff to do_assemble().
927 static unsigned long prev_insn
;
928 static struct d10v_opcode
*prev_opcode
= 0;
929 static subsegT prev_subseg
;
930 static segT prev_seg
;
936 struct d10v_opcode
*opcode
;
938 int extype
=0; /* execution type; parallel, etc */
939 static int etype
=0; /* saved extype. used for multiline instructions */
942 /* printf("md_assemble: str=%s\n",str); */
946 /* look for the special multiple instruction separators */
947 str2
= strstr (str
, "||");
952 str2
= strstr (str
, "->");
957 str2
= strstr (str
, "<-");
962 /* str2 points to the separator, if one */
967 /* if two instructions are present and we already have one saved
968 then first write it out */
970 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
972 /* assemble first instruction and save it */
973 prev_insn
= do_assemble (str
, &prev_opcode
);
975 as_fatal ("can't find opcode ");
976 fixups
= fixups
->next
;
981 insn
= do_assemble (str
, &opcode
);
989 as_fatal ("can't find opcode ");
998 /* if this is a long instruction, write it and any previous short instruction */
999 if (opcode
->format
& LONG_OPCODE
)
1002 as_fatal("Unable to mix instructions as specified");
1005 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
1008 write_long (opcode
, insn
, fixups
);
1013 if (prev_opcode
&& (write_2_short (prev_opcode
, prev_insn
, opcode
, insn
, extype
, fixups
) == 0))
1015 /* no instructions saved */
1021 as_fatal("Unable to mix instructions as specified");
1022 /* save off last instruction so it may be packed on next pass */
1023 prev_opcode
= opcode
;
1026 prev_subseg
= now_subseg
;
1027 fixups
= fixups
->next
;
1032 /* do_assemble assembles a single instruction and returns an opcode */
1033 /* it returns -1 (an invalid opcode) on error */
1035 static unsigned long
1036 do_assemble (str
, opcode
)
1038 struct d10v_opcode
**opcode
;
1040 unsigned char *op_start
, *save
;
1041 unsigned char *op_end
;
1044 expressionS myops
[6];
1047 /* printf("do_assemble: str=%s\n",str); */
1049 /* Drop leading whitespace */
1053 /* find the opcode end */
1054 for (op_start
= op_end
= (unsigned char *) (str
);
1057 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1060 name
[nlen
] = op_start
[nlen
];
1068 /* find the first opcode with the proper name */
1069 *opcode
= (struct d10v_opcode
*)hash_find (d10v_hash
, name
);
1070 if (*opcode
== NULL
)
1071 as_fatal ("unknown opcode: %s",name
);
1073 save
= input_line_pointer
;
1074 input_line_pointer
= op_end
;
1075 *opcode
= find_opcode (*opcode
, myops
);
1078 input_line_pointer
= save
;
1080 insn
= build_insn ((*opcode
), myops
, 0);
1081 /* printf("sub-insn = %lx\n",insn); */
1085 /* find_opcode() gets a pointer to an entry in the opcode table. */
1086 /* It must look at all opcodes with the same name and use the operands */
1087 /* to choose the correct opcode. */
1089 static struct d10v_opcode
*
1090 find_opcode (opcode
, myops
)
1091 struct d10v_opcode
*opcode
;
1092 expressionS myops
[];
1094 int i
, match
, done
, numops
;
1095 struct d10v_opcode
*next_opcode
;
1097 /* get all the operands and save them as expressions */
1098 numops
= get_operands (myops
);
1100 /* now see if the operand is a fake. If so, find the correct size */
1101 /* instruction, if possible */
1102 if (opcode
->format
== OPCODE_FAKE
)
1104 int opnum
= opcode
->operands
[0];
1106 if (myops
[opnum
].X_op
== O_register
)
1108 myops
[opnum
].X_op
= O_symbol
;
1109 myops
[opnum
].X_add_symbol
= symbol_find_or_make ((char *)myops
[opnum
].X_op_symbol
);
1110 myops
[opnum
].X_add_number
= 0;
1111 myops
[opnum
].X_op_symbol
= NULL
;
1114 if (myops
[opnum
].X_op
== O_constant
|| (myops
[opnum
].X_op
== O_symbol
&&
1115 S_IS_DEFINED(myops
[opnum
].X_add_symbol
) &&
1116 (S_GET_SEGMENT(myops
[opnum
].X_add_symbol
) == now_seg
)))
1118 next_opcode
=opcode
+1;
1119 for (i
=0; opcode
->operands
[i
+1]; i
++)
1121 int bits
= d10v_operands
[next_opcode
->operands
[opnum
]].bits
;
1122 int flags
= d10v_operands
[next_opcode
->operands
[opnum
]].flags
;
1123 if (flags
& OPERAND_ADDR
)
1125 if (myops
[opnum
].X_op
== O_constant
)
1127 if (!check_range (myops
[opnum
].X_add_number
, bits
, flags
))
1134 /* calculate the current address by running through the previous frags */
1135 /* and adding our current offset */
1136 for (value
= 0, f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1139 if (flags
& OPERAND_ADDR
)
1140 value
= S_GET_VALUE(myops
[opnum
].X_add_symbol
) - value
-
1141 (obstack_next_free(&frchain_now
->frch_obstack
) - frag_now
->fr_literal
);
1143 value
= S_GET_VALUE(myops
[opnum
].X_add_symbol
);
1145 if (myops
[opnum
].X_add_number
== AT_WORD
)
1150 if (!check_range (value
, bits
, flags
))
1154 else if (!check_range (value
, bits
, flags
))
1159 as_fatal ("value out of range");
1163 /* not a constant, so use a long instruction */
1170 /* now search the opcode table table for one with operands */
1171 /* that matches what we've got */
1175 for (i
= 0; opcode
->operands
[i
]; i
++)
1177 int flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
1178 int X_op
= myops
[i
].X_op
;
1179 int num
= myops
[i
].X_add_number
;
1187 if (flags
& OPERAND_REG
)
1189 if ((X_op
!= O_register
) ||
1190 ((flags
& OPERAND_ACC
) != (num
& OPERAND_ACC
)) ||
1191 ((flags
& OPERAND_FLAG
) != (num
& OPERAND_FLAG
)) ||
1192 ((flags
& OPERAND_CONTROL
) != (num
& OPERAND_CONTROL
)))
1199 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
1200 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
1201 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
1202 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
1203 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATSIGN
))))
1209 /* we're only done if the operands matched so far AND there
1210 are no more to check */
1211 if (match
&& myops
[i
].X_op
==0)
1216 next_opcode
= opcode
+1;
1217 if (next_opcode
->opcode
== 0)
1219 if (strcmp(next_opcode
->name
, opcode
->name
))
1221 opcode
= next_opcode
;
1227 as_bad ("bad opcode or operands");
1231 /* Check that all registers that are required to be even are. */
1232 /* Also, if any operands were marked as registers, but were really symbols */
1233 /* fix that here. */
1234 for (i
=0; opcode
->operands
[i
]; i
++)
1236 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_EVEN
) &&
1237 (myops
[i
].X_add_number
& 1))
1238 as_fatal("Register number must be EVEN");
1239 if (myops
[i
].X_op
== O_register
)
1241 if (!(d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_REG
))
1243 myops
[i
].X_op
= O_symbol
;
1244 myops
[i
].X_add_symbol
= symbol_find_or_make ((char *)myops
[i
].X_op_symbol
);
1245 myops
[i
].X_add_number
= 0;
1246 myops
[i
].X_op_symbol
= NULL
;
1253 /* if while processing a fixup, a reloc really needs to be created */
1254 /* then it is done here */
1257 tc_gen_reloc (seg
, fixp
)
1262 reloc
= (arelent
*) bfd_alloc_by_size_t (stdoutput
, sizeof (arelent
));
1263 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1264 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1265 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1266 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1268 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1269 "reloc %d not supported by object file format", (int)fixp
->fx_r_type
);
1272 reloc
->addend
= fixp
->fx_addnumber
;
1273 /* printf("tc_gen_reloc: addr=%x addend=%x\n", reloc->address, reloc->addend); */
1278 md_estimate_size_before_relax (fragp
, seg
)
1287 md_pcrel_from_section (fixp
, sec
)
1291 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& !S_IS_DEFINED (fixp
->fx_addsy
))
1293 /* printf("pcrel_from_section: %x\n", fixp->fx_frag->fr_address + fixp->fx_where); */
1294 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1298 md_apply_fix3 (fixp
, valuep
, seg
)
1309 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1314 else if (fixp
->fx_pcrel
)
1318 value
= fixp
->fx_offset
;
1319 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1321 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1322 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1325 /* We don't actually support subtracting a symbol. */
1326 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1327 "expression too complex");
1332 /* printf("md_apply_fix: value=0x%x type=0x%x where=0x%x size=%d line=%d\n", value, fixp->fx_r_type,fixp->fx_where,fixp->fx_size, fixp->fx_line); */
1334 op_type
= fixp
->fx_r_type
;
1341 fixp
->fx_r_type
= BFD_RELOC_D10V_10_PCREL_L
;
1344 else if (op_type
& 4096)
1347 fixp
->fx_r_type
= BFD_RELOC_D10V_18
;
1350 fixp
->fx_r_type
= get_reloc((struct d10v_operand
*)&d10v_operands
[op_type
]);
1353 /* Fetch the instruction, insert the fully resolved operand
1354 value, and stuff the instruction back again. */
1355 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1356 insn
= bfd_getb32 ((unsigned char *) where
);
1358 switch (fixp
->fx_r_type
)
1360 case BFD_RELOC_D10V_10_PCREL_L
:
1361 case BFD_RELOC_D10V_10_PCREL_R
:
1362 case BFD_RELOC_D10V_18_PCREL
:
1363 case BFD_RELOC_D10V_18
:
1364 /* instruction addresses are always right-shifted by 2 */
1366 if (fixp
->fx_size
== 2)
1367 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1370 /* printf(" insn=%x value=%x where=%x pcrel=%x\n",insn,value,fixp->fx_where,fixp->fx_pcrel); */
1371 insn
= d10v_insert_operand (insn
, op_type
, (offsetT
)value
, left
, fixp
);
1372 /* printf(" new insn=%x\n",insn); */
1373 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1377 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1380 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1383 as_fatal ("line %d: unknown relocation type: 0x%x",fixp
->fx_line
,fixp
->fx_r_type
);
1389 /* d10v_cleanup() is called after the assembler has finished parsing the input
1390 file or after a label is defined. Because the D10V assembler sometimes saves short
1391 instructions to see if it can package them with the next instruction, there may
1392 be a short instruction that still needs written. */
1400 if ( prev_opcode
&& (done
|| (now_seg
== prev_seg
) && (now_subseg
== prev_subseg
)))
1403 subseg
= now_subseg
;
1404 subseg_set (prev_seg
, prev_subseg
);
1405 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
1406 subseg_set (seg
, subseg
);
1412 /* Like normal .word, except support @word */
1413 /* clobbers input_line_pointer, checks end-of-line. */
1415 d10v_dot_word (nbytes
)
1416 register int nbytes
; /* 1=.byte, 2=.word, 4=.long */
1419 bfd_reloc_code_real_type reloc
;
1423 if (is_it_end_of_statement ())
1425 demand_empty_rest_of_line ();
1432 if (!strncasecmp (input_line_pointer
, "@word", 5))
1434 exp
.X_add_number
= 0;
1435 input_line_pointer
+= 5;
1438 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
1439 &exp
, 0, BFD_RELOC_D10V_18
);
1442 emit_expr (&exp
, 2);
1444 while (*input_line_pointer
++ == ',');
1446 input_line_pointer
--; /* Put terminator back into stream. */
1447 demand_empty_rest_of_line ();
1451 /* Mitsubishi asked that we support some old syntax that apparently */
1452 /* had immediate operands starting with '#'. This is in some of their */
1453 /* sample code but is not documented (although it appears in some */
1454 /* examples in their assembler manual). For now, we'll solve this */
1455 /* compatibility problem by simply ignoring any '#' at the beginning */
1456 /* of an operand. */
1458 /* operands that begin with '#' should fall through to here */
1462 md_operand (expressionP
)
1463 expressionS
*expressionP
;
1465 if (*input_line_pointer
== '#')
1467 input_line_pointer
++;
1468 expression (expressionP
);