1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
3 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d10v.h"
29 const char comment_chars
[] = ";";
30 const char line_comment_chars
[] = "#";
31 const char line_separator_chars
[] = "";
32 const char *md_shortopts
= "O";
33 const char EXP_CHARS
[] = "eE";
34 const char FLT_CHARS
[] = "dD";
38 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
39 && (X)->X_op_symbol != NULL \
40 && (X)->X_op_symbol->sy_value.X_op == O_constant \
41 && (X)->X_op_symbol->sy_value.X_add_number == AT_WORD_RIGHT_SHIFT)
42 #define AT_WORD_RIGHT_SHIFT 2
46 #define MAX_INSN_FIXUPS (5)
53 bfd_reloc_code_real_type reloc
;
56 typedef struct _fixups
59 struct d10v_fixup fix
[MAX_INSN_FIXUPS
];
63 static Fixups FixUps
[2];
64 static Fixups
*fixups
;
66 /* True if instruction swapping warnings should be inhibited. */
67 static unsigned char flag_warn_suppress_instructionswap
; /* --nowarnswap */
70 static int reg_name_search
PARAMS ((char *name
));
71 static int register_name
PARAMS ((expressionS
*expressionP
));
72 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
73 static int postfix
PARAMS ((char *p
));
74 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d10v_operand
*op
));
75 static int get_operands
PARAMS ((expressionS exp
[]));
76 static struct d10v_opcode
*find_opcode
PARAMS ((struct d10v_opcode
*opcode
, expressionS ops
[]));
77 static unsigned long build_insn
PARAMS ((struct d10v_opcode
*opcode
, expressionS
*opers
, unsigned long insn
));
78 static void write_long
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
79 static void write_1_short
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
80 static int write_2_short
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
81 struct d10v_opcode
*opcode2
, unsigned long insn2
, int exec_type
, Fixups
*fx
));
82 static unsigned long do_assemble
PARAMS ((char *str
, struct d10v_opcode
**opcode
));
83 static unsigned long d10v_insert_operand
PARAMS (( unsigned long insn
, int op_type
,
84 offsetT value
, int left
, fixS
*fix
));
85 static int parallel_ok
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
86 struct d10v_opcode
*opcode2
, unsigned long insn2
,
89 struct option md_longopts
[] = {
90 #define OPTION_NOWARNSWAP (OPTION_MD_BASE)
91 {"nowarnswap", no_argument
, NULL
, OPTION_NOWARNSWAP
},
92 {NULL
, no_argument
, NULL
, 0}
94 size_t md_longopts_size
= sizeof(md_longopts
);
96 static void d10v_dot_word
PARAMS ((int));
98 /* The target specific pseudo-ops which we support. */
99 const pseudo_typeS md_pseudo_table
[] =
101 { "word", d10v_dot_word
, 2 },
105 /* Opcode hash table. */
106 static struct hash_control
*d10v_hash
;
108 /* reg_name_search does a binary search of the d10v_predefined_registers
109 array to see if "name" is a valid regiter name. Returns the register
110 number from the array on success, or -1 on failure. */
113 reg_name_search (name
)
116 int middle
, low
, high
;
120 high
= d10v_reg_name_cnt() - 1;
124 middle
= (low
+ high
) / 2;
125 cmp
= strcasecmp (name
, d10v_predefined_registers
[middle
].name
);
131 return d10v_predefined_registers
[middle
].value
;
137 /* register_name() checks the string at input_line_pointer
138 to see if it is a valid register name */
141 register_name (expressionP
)
142 expressionS
*expressionP
;
145 char c
, *p
= input_line_pointer
;
147 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
154 /* look to see if it's in the register table */
155 reg_number
= reg_name_search (input_line_pointer
);
158 expressionP
->X_op
= O_register
;
159 /* temporarily store a pointer to the string here */
160 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
161 expressionP
->X_add_number
= reg_number
;
162 input_line_pointer
= p
;
172 check_range (num
, bits
, flags
)
180 /* don't bother checking 16-bit values */
184 if (flags
& OPERAND_SHIFT
)
186 /* all special shift operands are unsigned */
187 /* and <= 16. We allow 0 for now. */
194 if (flags
& OPERAND_SIGNED
)
196 max
= (1 << (bits
- 1))-1;
197 min
= - (1 << (bits
- 1));
198 if (((long)num
> max
) || ((long)num
< min
))
203 max
= (1 << bits
) - 1;
205 if ((num
> max
) || (num
< min
))
213 md_show_usage (stream
)
216 fprintf(stream
, _("D10V options:\n\
217 -O optimize. Will do some operations in parallel.\n"));
221 md_parse_option (c
, arg
)
228 /* Optimize. Will attempt to parallelize operations */
231 case OPTION_NOWARNSWAP
:
232 flag_warn_suppress_instructionswap
= 1;
241 md_undefined_symbol (name
)
247 /* Turn a string in input_line_pointer into a floating point constant of type
248 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
249 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
252 md_atof (type
, litP
, sizeP
)
258 LITTLENUM_TYPE words
[4];
272 return _("bad call to md_atof");
275 t
= atof_ieee (input_line_pointer
, type
, words
);
277 input_line_pointer
= t
;
281 for (i
= 0; i
< prec
; i
++)
283 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
290 md_convert_frag (abfd
, sec
, fragP
)
299 md_section_align (seg
, addr
)
303 int align
= bfd_get_section_alignment (stdoutput
, seg
);
304 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
311 char *prev_name
= "";
312 struct d10v_opcode
*opcode
;
313 d10v_hash
= hash_new();
315 /* Insert unique names into hash table. The D10v instruction set
316 has many identical opcode names that have different opcodes based
317 on the operands. This hash table then provides a quick index to
318 the first opcode with a particular name in the opcode table. */
320 for (opcode
= (struct d10v_opcode
*)d10v_opcodes
; opcode
->name
; opcode
++)
322 if (strcmp (prev_name
, opcode
->name
))
324 prev_name
= (char *)opcode
->name
;
325 hash_insert (d10v_hash
, opcode
->name
, (char *) opcode
);
330 FixUps
[0].next
= &FixUps
[1];
331 FixUps
[1].next
= &FixUps
[0];
335 /* this function removes the postincrement or postdecrement
336 operator ( '+' or '-' ) from an expression */
338 static int postfix (p
)
341 while (*p
!= '-' && *p
!= '+')
343 if (*p
==0 || *p
=='\n' || *p
=='\r')
363 static bfd_reloc_code_real_type
365 struct d10v_operand
*op
;
372 if (op
->flags
& OPERAND_ADDR
)
375 return (BFD_RELOC_D10V_10_PCREL_R
);
377 return (BFD_RELOC_D10V_18_PCREL
);
380 return (BFD_RELOC_16
);
384 /* get_operands parses a string of operands and returns
385 an array of expressions */
391 char *p
= input_line_pointer
;
397 while (*p
== ' ' || *p
== '\t' || *p
== ',')
399 if (*p
==0 || *p
=='\n' || *p
=='\r')
405 exp
[numops
].X_op
= O_absent
;
409 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
414 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
418 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
427 /* just skip the trailing paren */
432 input_line_pointer
= p
;
434 /* check to see if it might be a register name */
435 if (!register_name (&exp
[numops
]))
437 /* parse as an expression */
438 expression (&exp
[numops
]);
441 if (strncasecmp (input_line_pointer
, "@word", 5) == 0)
443 input_line_pointer
+= 5;
444 if (exp
[numops
].X_op
== O_register
)
446 /* if it looked like a register name but was followed by
447 "@word" then it was really a symbol, so change it to
449 exp
[numops
].X_op
= O_symbol
;
450 exp
[numops
].X_add_symbol
= symbol_find_or_make ((char *)exp
[numops
].X_op_symbol
);
453 /* check for identifier@word+constant */
454 if (*input_line_pointer
== '-' || *input_line_pointer
== '+')
456 char *orig_line
= input_line_pointer
;
458 expression (&new_exp
);
459 exp
[numops
].X_add_number
= new_exp
.X_add_number
;
462 /* convert expr into a right shift by AT_WORD_RIGHT_SHIFT */
465 memset (&new_exp
, 0, sizeof new_exp
);
466 new_exp
.X_add_number
= AT_WORD_RIGHT_SHIFT
;
467 new_exp
.X_op
= O_constant
;
468 new_exp
.X_unsigned
= 1;
469 exp
[numops
].X_op_symbol
= make_expr_symbol (&new_exp
);
470 exp
[numops
].X_op
= O_right_shift
;
473 know (AT_WORD_P (&exp
[numops
]));
476 if (exp
[numops
].X_op
== O_illegal
)
477 as_bad (_("illegal operand"));
478 else if (exp
[numops
].X_op
== O_absent
)
479 as_bad (_("missing operand"));
482 p
= input_line_pointer
;
487 case -1: /* postdecrement mode */
488 exp
[numops
].X_op
= O_absent
;
489 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
491 case 1: /* postincrement mode */
492 exp
[numops
].X_op
= O_absent
;
493 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
497 exp
[numops
].X_op
= 0;
502 d10v_insert_operand (insn
, op_type
, value
, left
, fix
)
511 shift
= d10v_operands
[op_type
].shift
;
515 bits
= d10v_operands
[op_type
].bits
;
517 /* truncate to the proper number of bits */
518 if (check_range (value
, bits
, d10v_operands
[op_type
].flags
))
519 as_bad_where (fix
->fx_file
, fix
->fx_line
, _("operand out of range: %d"), value
);
521 value
&= 0x7FFFFFFF >> (31 - bits
);
522 insn
|= (value
<< shift
);
528 /* build_insn takes a pointer to the opcode entry in the opcode table
529 and the array of operand expressions and returns the instruction */
532 build_insn (opcode
, opers
, insn
)
533 struct d10v_opcode
*opcode
;
537 int i
, bits
, shift
, flags
, format
;
538 unsigned long number
;
540 /* the insn argument is only used for the DIVS kludge */
545 insn
= opcode
->opcode
;
546 format
= opcode
->format
;
549 for (i
=0;opcode
->operands
[i
];i
++)
551 flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
552 bits
= d10v_operands
[opcode
->operands
[i
]].bits
;
553 shift
= d10v_operands
[opcode
->operands
[i
]].shift
;
554 number
= opers
[i
].X_add_number
;
556 if (flags
& OPERAND_REG
)
558 number
&= REGISTER_MASK
;
559 if (format
== LONG_L
)
563 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
)
565 /* now create a fixup */
567 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
568 as_fatal (_("too many fixups"));
570 if (AT_WORD_P (&opers
[i
]))
572 /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD) */
573 fixups
->fix
[fixups
->fc
].reloc
= BFD_RELOC_D10V_18
;
574 opers
[i
].X_op
= O_symbol
;
575 opers
[i
].X_op_symbol
= NULL
; /* Should free it */
576 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
577 that, it is aligned with the symbol's value. Later,
578 BFD_RELOC_D10V_18 will right shift (symbol_value +
580 number
<<= AT_WORD_RIGHT_SHIFT
;
581 opers
[i
].X_add_number
= number
;
584 fixups
->fix
[fixups
->fc
].reloc
=
585 get_reloc((struct d10v_operand
*)&d10v_operands
[opcode
->operands
[i
]]);
587 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_16
||
588 fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D10V_18
)
589 fixups
->fix
[fixups
->fc
].size
= 2;
591 fixups
->fix
[fixups
->fc
].size
= 4;
593 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
594 fixups
->fix
[fixups
->fc
].operand
= opcode
->operands
[i
];
595 fixups
->fix
[fixups
->fc
].pcrel
= (flags
& OPERAND_ADDR
) ? true : false;
599 /* truncate to the proper number of bits */
600 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
601 as_bad(_("operand out of range: %d"),number
);
602 number
&= 0x7FFFFFFF >> (31 - bits
);
603 insn
= insn
| (number
<< shift
);
606 /* kludge: for DIVS, we need to put the operands in twice */
607 /* on the second pass, format is changed to LONG_R to force */
608 /* the second set of operands to not be shifted over 15 */
609 if ((opcode
->opcode
== OPCODE_DIVS
) && (format
==LONG_L
))
610 insn
= build_insn (opcode
, opers
, insn
);
615 /* write out a long form instruction */
617 write_long (opcode
, insn
, fx
)
618 struct d10v_opcode
*opcode
;
623 char *f
= frag_more(4);
626 number_to_chars_bigendian (f
, insn
, 4);
628 for (i
=0; i
< fx
->fc
; i
++)
630 if (fx
->fix
[i
].reloc
)
632 where
= f
- frag_now
->fr_literal
;
633 if (fx
->fix
[i
].size
== 2)
636 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
637 fx
->fix
[i
].operand
|= 4096;
639 fix_new_exp (frag_now
,
644 fx
->fix
[i
].operand
|2048);
651 /* write out a short form instruction by itself */
653 write_1_short (opcode
, insn
, fx
)
654 struct d10v_opcode
*opcode
;
658 char *f
= frag_more(4);
661 if (opcode
->exec_type
& PARONLY
)
662 as_fatal (_("Instruction must be executed in parallel with another instruction."));
664 /* the other container needs to be NOP */
665 /* according to 4.3.1: for FM=00, sub-instructions performed only
666 by IU cannot be encoded in L-container. */
667 if (opcode
->unit
== IU
)
668 insn
|= FM00
| (NOP
<< 15); /* right container */
670 insn
= FM00
| (insn
<< 15) | NOP
; /* left container */
672 number_to_chars_bigendian (f
, insn
, 4);
673 for (i
=0; i
< fx
->fc
; i
++)
675 if (fx
->fix
[i
].reloc
)
677 where
= f
- frag_now
->fr_literal
;
678 if (fx
->fix
[i
].size
== 2)
681 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
682 fx
->fix
[i
].operand
|= 4096;
684 /* if it's an R reloc, we may have to switch it to L */
685 if ( (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (opcode
->unit
!= IU
) )
686 fx
->fix
[i
].operand
|= 1024;
688 fix_new_exp (frag_now
,
693 fx
->fix
[i
].operand
|2048);
699 /* write out a short form instruction if possible */
700 /* return number of instructions not written out */
702 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
703 struct d10v_opcode
*opcode1
, *opcode2
;
704 unsigned long insn1
, insn2
;
712 if ( (exec_type
!= 1) && ((opcode1
->exec_type
& PARONLY
)
713 || (opcode2
->exec_type
& PARONLY
)))
714 as_fatal(_("Instruction must be executed in parallel"));
716 if ( (opcode1
->format
& LONG_OPCODE
) || (opcode2
->format
& LONG_OPCODE
))
717 as_fatal (_("Long instructions may not be combined."));
719 if(opcode1
->exec_type
& BRANCH_LINK
&& exec_type
== 0)
721 /* Instructions paired with a subroutine call are executed before the
722 subroutine, so don't do these pairings unless explicitly requested. */
723 write_1_short (opcode1
, insn1
, fx
->next
);
729 case 0: /* order not specified */
730 if ( Optimizing
&& parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
733 if (opcode1
->unit
== IU
)
734 insn
= FM00
| (insn2
<< 15) | insn1
;
735 else if (opcode2
->unit
== MU
)
736 insn
= FM00
| (insn2
<< 15) | insn1
;
739 insn
= FM00
| (insn1
<< 15) | insn2
;
743 else if (opcode1
->unit
== IU
)
745 /* reverse sequential */
746 insn
= FM10
| (insn2
<< 15) | insn1
;
751 insn
= FM01
| (insn1
<< 15) | insn2
;
755 case 1: /* parallel */
756 if (opcode1
->exec_type
& SEQ
|| opcode2
->exec_type
& SEQ
)
757 as_fatal (_("One of these instructions may not be executed in parallel."));
759 if (opcode1
->unit
== IU
)
761 if (opcode2
->unit
== IU
)
762 as_fatal (_("Two IU instructions may not be executed in parallel"));
763 if (!flag_warn_suppress_instructionswap
)
764 as_warn (_("Swapping instruction order"));
765 insn
= FM00
| (insn2
<< 15) | insn1
;
767 else if (opcode2
->unit
== MU
)
769 if (opcode1
->unit
== MU
)
770 as_fatal (_("Two MU instructions may not be executed in parallel"));
771 if (!flag_warn_suppress_instructionswap
)
772 as_warn (_("Swapping instruction order"));
773 insn
= FM00
| (insn2
<< 15) | insn1
;
777 insn
= FM00
| (insn1
<< 15) | insn2
;
781 case 2: /* sequential */
782 if (opcode1
->unit
!= IU
)
783 insn
= FM01
| (insn1
<< 15) | insn2
;
784 else if (opcode2
->unit
== MU
|| opcode2
->unit
== EITHER
)
786 if (!flag_warn_suppress_instructionswap
)
787 as_warn (_("Swapping instruction order"));
788 insn
= FM10
| (insn2
<< 15) | insn1
;
791 as_fatal (_("IU instruction may not be in the left container"));
794 case 3: /* reverse sequential */
795 if (opcode2
->unit
!= MU
)
796 insn
= FM10
| (insn1
<< 15) | insn2
;
797 else if (opcode1
->unit
== IU
|| opcode1
->unit
== EITHER
)
799 if (!flag_warn_suppress_instructionswap
)
800 as_warn (_("Swapping instruction order"));
801 insn
= FM01
| (insn2
<< 15) | insn1
;
804 as_fatal (_("MU instruction may not be in the right container"));
808 as_fatal(_("unknown execution type passed to write_2_short()"));
812 number_to_chars_bigendian (f
, insn
, 4);
816 for (i
=0; i
< fx
->fc
; i
++)
818 if (fx
->fix
[i
].reloc
)
820 where
= f
- frag_now
->fr_literal
;
821 if (fx
->fix
[i
].size
== 2)
824 if ( (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (j
== 0) )
825 fx
->fix
[i
].operand
|= 1024;
827 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
828 fx
->fix
[i
].operand
|= 4096;
830 fix_new_exp (frag_now
,
835 fx
->fix
[i
].operand
|2048);
845 /* Check 2 instructions and determine if they can be safely */
846 /* executed in parallel. Returns 1 if they can be. */
848 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
849 struct d10v_opcode
*op1
, *op2
;
850 unsigned long insn1
, insn2
;
853 int i
, j
, flags
, mask
, shift
, regno
;
854 unsigned long ins
, mod
[2], used
[2];
855 struct d10v_opcode
*op
;
857 if ((op1
->exec_type
& SEQ
) != 0 || (op2
->exec_type
& SEQ
) != 0
858 || (op1
->exec_type
& PAR
) == 0 || (op2
->exec_type
& PAR
) == 0
859 || (op1
->unit
== BOTH
) || (op2
->unit
== BOTH
)
860 || (op1
->unit
== IU
&& op2
->unit
== IU
)
861 || (op1
->unit
== MU
&& op2
->unit
== MU
))
864 /* If the first instruction is a branch and this is auto parallazation,
865 don't combine with any second instruction. */
866 if (exec_type
== 0 && (op1
->exec_type
& BRANCH
) != 0)
869 /* The idea here is to create two sets of bitmasks (mod and used)
870 which indicate which registers are modified or used by each
871 instruction. The operation can only be done in parallel if
872 instruction 1 and instruction 2 modify different registers, and
873 the first instruction does not modify registers that the second
874 is using (The second instruction can modify registers that the
875 first is using as they are only written back after the first
876 instruction has completed). Accesses to control registers, PSW,
877 and memory are treated as accesses to a single register. So if
878 both instructions write memory or if the first instruction writes
879 memory and the second reads, then they cannot be done in
880 parallel. Likewise, if the first instruction mucks with the psw
881 and the second reads the PSW (which includes C, F0, and F1), then
882 they cannot operate safely in parallel. */
884 /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
887 /* cr (not psw) 18 */
903 mod
[j
] = used
[j
] = 0;
904 if (op
->exec_type
& BRANCH_LINK
)
907 for (i
= 0; op
->operands
[i
]; i
++)
909 flags
= d10v_operands
[op
->operands
[i
]].flags
;
910 shift
= d10v_operands
[op
->operands
[i
]].shift
;
911 mask
= 0x7FFFFFFF >> (31 - d10v_operands
[op
->operands
[i
]].bits
);
912 if (flags
& OPERAND_REG
)
914 regno
= (ins
>> shift
) & mask
;
915 if (flags
& (OPERAND_ACC0
|OPERAND_ACC1
))
917 else if (flags
& OPERAND_CONTROL
) /* mvtc or mvfc */
924 else if (flags
& (OPERAND_FFLAG
|OPERAND_CFLAG
))
927 if ( flags
& OPERAND_DEST
)
929 mod
[j
] |= 1 << regno
;
930 if (flags
& OPERAND_EVEN
)
931 mod
[j
] |= 1 << (regno
+ 1);
935 used
[j
] |= 1 << regno
;
936 if (flags
& OPERAND_EVEN
)
937 used
[j
] |= 1 << (regno
+ 1);
939 /* Auto inc/dec also modifies the register. */
940 if (op
->operands
[i
+1] != 0
941 && (d10v_operands
[op
->operands
[i
+1]].flags
942 & (OPERAND_PLUS
| OPERAND_MINUS
)) != 0)
943 mod
[j
] |= 1 << regno
;
946 else if (flags
& OPERAND_ATMINUS
)
948 /* SP implicitly used/modified */
953 if (op
->exec_type
& RMEM
)
955 else if (op
->exec_type
& WMEM
)
957 else if (op
->exec_type
& RF0
)
959 else if (op
->exec_type
& WF0
)
961 else if (op
->exec_type
& WCAR
)
964 if ((mod
[0] & mod
[1]) == 0 && (mod
[0] & used
[1]) == 0)
970 /* This is the main entry point for the machine-dependent assembler. str points to a
971 machine-dependent instruction. This function is supposed to emit the frags/bytes
972 it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing
973 and leaves the difficult stuff to do_assemble().
976 static unsigned long prev_insn
;
977 static struct d10v_opcode
*prev_opcode
= 0;
978 static subsegT prev_subseg
;
979 static segT prev_seg
= 0;;
985 struct d10v_opcode
*opcode
;
987 int extype
=0; /* execution type; parallel, etc */
988 static int etype
=0; /* saved extype. used for multiline instructions */
993 /* look for the special multiple instruction separators */
994 str2
= strstr (str
, "||");
999 str2
= strstr (str
, "->");
1004 str2
= strstr (str
, "<-");
1009 /* str2 points to the separator, if one */
1014 /* if two instructions are present and we already have one saved
1015 then first write it out */
1018 /* assemble first instruction and save it */
1019 prev_insn
= do_assemble (str
, &prev_opcode
);
1020 if (prev_insn
== -1)
1021 as_fatal (_("can't find opcode "));
1022 fixups
= fixups
->next
;
1027 insn
= do_assemble (str
, &opcode
);
1035 as_fatal (_("can't find opcode "));
1044 /* if this is a long instruction, write it and any previous short instruction */
1045 if (opcode
->format
& LONG_OPCODE
)
1048 as_fatal(_("Unable to mix instructions as specified"));
1050 write_long (opcode
, insn
, fixups
);
1055 if (prev_opcode
&& prev_seg
&& ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1058 if (prev_opcode
&& (write_2_short (prev_opcode
, prev_insn
, opcode
, insn
, extype
, fixups
) == 0))
1060 /* no instructions saved */
1066 as_fatal(_("Unable to mix instructions as specified"));
1067 /* save off last instruction so it may be packed on next pass */
1068 prev_opcode
= opcode
;
1071 prev_subseg
= now_subseg
;
1072 fixups
= fixups
->next
;
1077 /* do_assemble assembles a single instruction and returns an opcode */
1078 /* it returns -1 (an invalid opcode) on error */
1080 static unsigned long
1081 do_assemble (str
, opcode
)
1083 struct d10v_opcode
**opcode
;
1085 unsigned char *op_start
, *save
;
1086 unsigned char *op_end
;
1089 expressionS myops
[6];
1092 /* Drop leading whitespace */
1096 /* find the opcode end */
1097 for (op_start
= op_end
= (unsigned char *) (str
);
1100 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1103 name
[nlen
] = tolower(op_start
[nlen
]);
1111 /* find the first opcode with the proper name */
1112 *opcode
= (struct d10v_opcode
*)hash_find (d10v_hash
, name
);
1113 if (*opcode
== NULL
)
1114 as_fatal (_("unknown opcode: %s"),name
);
1116 save
= input_line_pointer
;
1117 input_line_pointer
= op_end
;
1118 *opcode
= find_opcode (*opcode
, myops
);
1121 input_line_pointer
= save
;
1123 insn
= build_insn ((*opcode
), myops
, 0);
1127 /* find_opcode() gets a pointer to an entry in the opcode table. */
1128 /* It must look at all opcodes with the same name and use the operands */
1129 /* to choose the correct opcode. */
1131 static struct d10v_opcode
*
1132 find_opcode (opcode
, myops
)
1133 struct d10v_opcode
*opcode
;
1134 expressionS myops
[];
1137 struct d10v_opcode
*next_opcode
;
1139 /* get all the operands and save them as expressions */
1140 get_operands (myops
);
1142 /* now see if the operand is a fake. If so, find the correct size */
1143 /* instruction, if possible */
1144 if (opcode
->format
== OPCODE_FAKE
)
1146 int opnum
= opcode
->operands
[0];
1149 if (myops
[opnum
].X_op
== O_register
)
1151 myops
[opnum
].X_op
= O_symbol
;
1152 myops
[opnum
].X_add_symbol
= symbol_find_or_make ((char *)myops
[opnum
].X_op_symbol
);
1153 myops
[opnum
].X_add_number
= 0;
1154 myops
[opnum
].X_op_symbol
= NULL
;
1157 next_opcode
=opcode
+1;
1159 /* If the first operand is supposed to be a register, make sure
1160 we got a valid one. */
1161 flags
= d10v_operands
[next_opcode
->operands
[0]].flags
;
1162 if (flags
& OPERAND_REG
)
1164 int X_op
= myops
[0].X_op
;
1165 int num
= myops
[0].X_add_number
;
1167 if (X_op
!= O_register
1169 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1170 | OPERAND_FFLAG
| OPERAND_CFLAG
| OPERAND_CONTROL
)))
1172 as_bad (_("bad opcode or operands"));
1177 if (myops
[opnum
].X_op
== O_constant
|| (myops
[opnum
].X_op
== O_symbol
&&
1178 S_IS_DEFINED(myops
[opnum
].X_add_symbol
) &&
1179 (S_GET_SEGMENT(myops
[opnum
].X_add_symbol
) == now_seg
)))
1181 for (i
=0; opcode
->operands
[i
+1]; i
++)
1183 int bits
= d10v_operands
[next_opcode
->operands
[opnum
]].bits
;
1184 int flags
= d10v_operands
[next_opcode
->operands
[opnum
]].flags
;
1185 if (flags
& OPERAND_ADDR
)
1187 if (myops
[opnum
].X_op
== O_constant
)
1189 if (!check_range (myops
[opnum
].X_add_number
, bits
, flags
))
1196 /* calculate the current address by running through the previous frags */
1197 /* and adding our current offset */
1198 for (value
= 0, f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1199 value
+= f
->fr_fix
+ f
->fr_offset
;
1201 if (flags
& OPERAND_ADDR
)
1202 value
= S_GET_VALUE(myops
[opnum
].X_add_symbol
) - value
-
1203 (obstack_next_free(&frchain_now
->frch_obstack
) - frag_now
->fr_literal
);
1205 value
= S_GET_VALUE(myops
[opnum
].X_add_symbol
);
1207 if (AT_WORD_P (&myops
[opnum
]))
1212 if (!check_range (value
, bits
, flags
))
1216 else if (!check_range (value
, bits
, flags
))
1221 as_fatal (_("value out of range"));
1225 /* not a constant, so use a long instruction */
1232 /* now search the opcode table table for one with operands */
1233 /* that matches what we've got */
1237 for (i
= 0; opcode
->operands
[i
]; i
++)
1239 int flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
1240 int X_op
= myops
[i
].X_op
;
1241 int num
= myops
[i
].X_add_number
;
1249 if (flags
& OPERAND_REG
)
1251 if ((X_op
!= O_register
)
1253 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1254 | OPERAND_FFLAG
| OPERAND_CFLAG
1255 | OPERAND_CONTROL
)))
1262 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
1263 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
1264 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
1265 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
1266 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATSIGN
))))
1272 /* we're only done if the operands matched so far AND there
1273 are no more to check */
1274 if (match
&& myops
[i
].X_op
==0)
1279 next_opcode
= opcode
+1;
1280 if (next_opcode
->opcode
== 0)
1282 if (strcmp(next_opcode
->name
, opcode
->name
))
1284 opcode
= next_opcode
;
1290 as_bad (_("bad opcode or operands"));
1294 /* Check that all registers that are required to be even are. */
1295 /* Also, if any operands were marked as registers, but were really symbols */
1296 /* fix that here. */
1297 for (i
=0; opcode
->operands
[i
]; i
++)
1299 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_EVEN
) &&
1300 (myops
[i
].X_add_number
& 1))
1301 as_fatal(_("Register number must be EVEN"));
1302 if (myops
[i
].X_op
== O_register
)
1304 if (!(d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_REG
))
1306 myops
[i
].X_op
= O_symbol
;
1307 myops
[i
].X_add_symbol
= symbol_find_or_make ((char *)myops
[i
].X_op_symbol
);
1308 myops
[i
].X_add_number
= 0;
1309 myops
[i
].X_op_symbol
= NULL
;
1316 /* if while processing a fixup, a reloc really needs to be created */
1317 /* then it is done here */
1320 tc_gen_reloc (seg
, fixp
)
1325 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1326 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1327 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1328 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1329 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1331 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1332 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1335 reloc
->addend
= fixp
->fx_addnumber
;
1340 md_estimate_size_before_relax (fragp
, seg
)
1349 md_pcrel_from_section (fixp
, sec
)
1353 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1354 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1356 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1360 md_apply_fix3 (fixp
, valuep
, seg
)
1371 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1376 else if (fixp
->fx_pcrel
)
1380 value
= fixp
->fx_offset
;
1381 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1383 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1384 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1387 /* We don't actually support subtracting a symbol. */
1388 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1389 _("expression too complex"));
1394 op_type
= fixp
->fx_r_type
;
1401 fixp
->fx_r_type
= BFD_RELOC_D10V_10_PCREL_L
;
1404 else if (op_type
& 4096)
1407 fixp
->fx_r_type
= BFD_RELOC_D10V_18
;
1410 fixp
->fx_r_type
= get_reloc((struct d10v_operand
*)&d10v_operands
[op_type
]);
1413 /* Fetch the instruction, insert the fully resolved operand
1414 value, and stuff the instruction back again. */
1415 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1416 insn
= bfd_getb32 ((unsigned char *) where
);
1418 switch (fixp
->fx_r_type
)
1420 case BFD_RELOC_D10V_10_PCREL_L
:
1421 case BFD_RELOC_D10V_10_PCREL_R
:
1422 case BFD_RELOC_D10V_18_PCREL
:
1423 case BFD_RELOC_D10V_18
:
1424 /* instruction addresses are always right-shifted by 2 */
1425 value
>>= AT_WORD_RIGHT_SHIFT
;
1426 if (fixp
->fx_size
== 2)
1427 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1430 insn
= d10v_insert_operand (insn
, op_type
, (offsetT
)value
, left
, fixp
);
1431 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1435 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1438 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1441 as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp
->fx_line
,fixp
->fx_r_type
);
1446 /* d10v_cleanup() is called after the assembler has finished parsing the input
1447 file or after a label is defined. Because the D10V assembler sometimes saves short
1448 instructions to see if it can package them with the next instruction, there may
1449 be a short instruction that still needs written. */
1459 subseg
= now_subseg
;
1460 subseg_set (prev_seg
, prev_subseg
);
1461 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
1462 subseg_set (seg
, subseg
);
1468 /* Like normal .word, except support @word */
1469 /* clobbers input_line_pointer, checks end-of-line. */
1471 d10v_dot_word (nbytes
)
1472 register int nbytes
; /* 1=.byte, 2=.word, 4=.long */
1475 bfd_reloc_code_real_type reloc
;
1479 if (is_it_end_of_statement ())
1481 demand_empty_rest_of_line ();
1488 if (!strncasecmp (input_line_pointer
, "@word", 5))
1490 exp
.X_add_number
= 0;
1491 input_line_pointer
+= 5;
1494 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
1495 &exp
, 0, BFD_RELOC_D10V_18
);
1498 emit_expr (&exp
, 2);
1500 while (*input_line_pointer
++ == ',');
1502 input_line_pointer
--; /* Put terminator back into stream. */
1503 demand_empty_rest_of_line ();
1507 /* Mitsubishi asked that we support some old syntax that apparently */
1508 /* had immediate operands starting with '#'. This is in some of their */
1509 /* sample code but is not documented (although it appears in some */
1510 /* examples in their assembler manual). For now, we'll solve this */
1511 /* compatibility problem by simply ignoring any '#' at the beginning */
1512 /* of an operand. */
1514 /* operands that begin with '#' should fall through to here */
1518 md_operand (expressionP
)
1519 expressionS
*expressionP
;
1521 if (*input_line_pointer
== '#')
1523 input_line_pointer
++;
1524 expression (expressionP
);