1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
2 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
25 #include "opcode/d10v.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "O";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
37 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
38 && (X)->X_op_symbol != NULL \
39 && symbol_constant_p ((X)->X_op_symbol) \
40 && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
41 #define AT_WORD_RIGHT_SHIFT 2
45 #define MAX_INSN_FIXUPS (5)
52 bfd_reloc_code_real_type reloc
;
55 typedef struct _fixups
58 struct d10v_fixup fix
[MAX_INSN_FIXUPS
];
62 static Fixups FixUps
[2];
63 static Fixups
*fixups
;
65 static int do_not_ignore_hash
= 0;
67 /* True if instruction swapping warnings should be inhibited. */
68 static unsigned char flag_warn_suppress_instructionswap
; /* --nowarnswap */
71 static int reg_name_search
PARAMS ((char *name
));
72 static int register_name
PARAMS ((expressionS
*expressionP
));
73 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
74 static int postfix
PARAMS ((char *p
));
75 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d10v_operand
*op
));
76 static int get_operands
PARAMS ((expressionS exp
[]));
77 static struct d10v_opcode
*find_opcode
PARAMS ((struct d10v_opcode
*opcode
, expressionS ops
[]));
78 static unsigned long build_insn
PARAMS ((struct d10v_opcode
*opcode
, expressionS
*opers
, unsigned long insn
));
79 static void write_long
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
80 static void write_1_short
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
81 static int write_2_short
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
82 struct d10v_opcode
*opcode2
, unsigned long insn2
, int exec_type
, Fixups
*fx
));
83 static unsigned long do_assemble
PARAMS ((char *str
, struct d10v_opcode
**opcode
));
84 static unsigned long d10v_insert_operand
PARAMS (( unsigned long insn
, int op_type
,
85 offsetT value
, int left
, fixS
*fix
));
86 static int parallel_ok
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
87 struct d10v_opcode
*opcode2
, unsigned long insn2
,
89 static symbolS
* find_symbol_matching_register
PARAMS ((expressionS
*));
91 struct option md_longopts
[] =
93 #define OPTION_NOWARNSWAP (OPTION_MD_BASE)
94 {"nowarnswap", no_argument
, NULL
, OPTION_NOWARNSWAP
},
95 {NULL
, no_argument
, NULL
, 0}
97 size_t md_longopts_size
= sizeof(md_longopts
);
99 static void d10v_dot_word
PARAMS ((int));
101 /* The target specific pseudo-ops which we support. */
102 const pseudo_typeS md_pseudo_table
[] =
104 { "word", d10v_dot_word
, 2 },
108 /* Opcode hash table. */
109 static struct hash_control
*d10v_hash
;
111 /* reg_name_search does a binary search of the d10v_predefined_registers
112 array to see if "name" is a valid regiter name. Returns the register
113 number from the array on success, or -1 on failure. */
116 reg_name_search (name
)
119 int middle
, low
, high
;
123 high
= d10v_reg_name_cnt() - 1;
127 middle
= (low
+ high
) / 2;
128 cmp
= strcasecmp (name
, d10v_predefined_registers
[middle
].name
);
134 return d10v_predefined_registers
[middle
].value
;
140 /* register_name() checks the string at input_line_pointer
141 to see if it is a valid register name */
144 register_name (expressionP
)
145 expressionS
*expressionP
;
148 char c
, *p
= input_line_pointer
;
150 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
157 /* look to see if it's in the register table */
158 reg_number
= reg_name_search (input_line_pointer
);
161 expressionP
->X_op
= O_register
;
162 /* temporarily store a pointer to the string here */
163 expressionP
->X_op_symbol
= (symbolS
*)input_line_pointer
;
164 expressionP
->X_add_number
= reg_number
;
165 input_line_pointer
= p
;
175 check_range (num
, bits
, flags
)
183 /* don't bother checking 16-bit values */
187 if (flags
& OPERAND_SHIFT
)
189 /* all special shift operands are unsigned */
190 /* and <= 16. We allow 0 for now. */
197 if (flags
& OPERAND_SIGNED
)
199 /* Signed 3-bit integers are restricted to the (-2, 3) range */
200 if (flags
& RESTRICTED_NUM3
)
202 if ((long) num
< -2 || (long) num
> 3)
207 max
= (1 << (bits
- 1)) - 1;
208 min
= - (1 << (bits
- 1));
209 if (((long) num
> max
) || ((long) num
< min
))
215 max
= (1 << bits
) - 1;
217 if ((num
> max
) || (num
< min
))
225 md_show_usage (stream
)
228 fprintf(stream
, _("D10V options:\n\
229 -O optimize. Will do some operations in parallel.\n"));
233 md_parse_option (c
, arg
)
240 /* Optimize. Will attempt to parallelize operations */
243 case OPTION_NOWARNSWAP
:
244 flag_warn_suppress_instructionswap
= 1;
253 md_undefined_symbol (name
)
259 /* Turn a string in input_line_pointer into a floating point constant of type
260 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
261 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
264 md_atof (type
, litP
, sizeP
)
270 LITTLENUM_TYPE words
[4];
284 return _("bad call to md_atof");
287 t
= atof_ieee (input_line_pointer
, type
, words
);
289 input_line_pointer
= t
;
293 for (i
= 0; i
< prec
; i
++)
295 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
302 md_convert_frag (abfd
, sec
, fragP
)
311 md_section_align (seg
, addr
)
315 int align
= bfd_get_section_alignment (stdoutput
, seg
);
316 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
323 char *prev_name
= "";
324 struct d10v_opcode
*opcode
;
325 d10v_hash
= hash_new();
327 /* Insert unique names into hash table. The D10v instruction set
328 has many identical opcode names that have different opcodes based
329 on the operands. This hash table then provides a quick index to
330 the first opcode with a particular name in the opcode table. */
332 for (opcode
= (struct d10v_opcode
*)d10v_opcodes
; opcode
->name
; opcode
++)
334 if (strcmp (prev_name
, opcode
->name
))
336 prev_name
= (char *)opcode
->name
;
337 hash_insert (d10v_hash
, opcode
->name
, (char *) opcode
);
342 FixUps
[0].next
= &FixUps
[1];
343 FixUps
[1].next
= &FixUps
[0];
347 /* this function removes the postincrement or postdecrement
348 operator ( '+' or '-' ) from an expression */
350 static int postfix (p
)
353 while (*p
!= '-' && *p
!= '+')
355 if (*p
==0 || *p
=='\n' || *p
=='\r')
375 static bfd_reloc_code_real_type
377 struct d10v_operand
*op
;
384 if (op
->flags
& OPERAND_ADDR
)
387 return (BFD_RELOC_D10V_10_PCREL_R
);
389 return (BFD_RELOC_D10V_18_PCREL
);
392 return (BFD_RELOC_16
);
396 /* get_operands parses a string of operands and returns
397 an array of expressions */
403 char *p
= input_line_pointer
;
410 while (*p
== ' ' || *p
== '\t' || *p
== ',')
412 if (*p
==0 || *p
=='\n' || *p
=='\r')
420 exp
[numops
].X_op
= O_absent
;
424 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
429 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
433 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
442 /* just skip the trailing paren */
447 input_line_pointer
= p
;
449 /* check to see if it might be a register name */
450 if (!register_name (&exp
[numops
]))
452 /* parse as an expression */
455 /* Any expression that involves the indirect addressing
456 cannot also involve immediate addressing. Therefore
457 the use of the hash character is illegal. */
458 int save
= do_not_ignore_hash
;
459 do_not_ignore_hash
= 1;
461 expression (&exp
[numops
]);
463 do_not_ignore_hash
= save
;
466 expression (&exp
[numops
]);
469 if (strncasecmp (input_line_pointer
, "@word", 5) == 0)
471 input_line_pointer
+= 5;
472 if (exp
[numops
].X_op
== O_register
)
474 /* if it looked like a register name but was followed by
475 "@word" then it was really a symbol, so change it to
477 exp
[numops
].X_op
= O_symbol
;
478 exp
[numops
].X_add_symbol
= symbol_find_or_make ((char *)exp
[numops
].X_op_symbol
);
481 /* check for identifier@word+constant */
482 if (*input_line_pointer
== '-' || *input_line_pointer
== '+')
484 char *orig_line
= input_line_pointer
;
486 expression (&new_exp
);
487 exp
[numops
].X_add_number
= new_exp
.X_add_number
;
490 /* convert expr into a right shift by AT_WORD_RIGHT_SHIFT */
493 memset (&new_exp
, 0, sizeof new_exp
);
494 new_exp
.X_add_number
= AT_WORD_RIGHT_SHIFT
;
495 new_exp
.X_op
= O_constant
;
496 new_exp
.X_unsigned
= 1;
497 exp
[numops
].X_op_symbol
= make_expr_symbol (&new_exp
);
498 exp
[numops
].X_op
= O_right_shift
;
501 know (AT_WORD_P (&exp
[numops
]));
504 if (exp
[numops
].X_op
== O_illegal
)
505 as_bad (_("illegal operand"));
506 else if (exp
[numops
].X_op
== O_absent
)
507 as_bad (_("missing operand"));
510 p
= input_line_pointer
;
515 case -1: /* postdecrement mode */
516 exp
[numops
].X_op
= O_absent
;
517 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
519 case 1: /* postincrement mode */
520 exp
[numops
].X_op
= O_absent
;
521 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
525 exp
[numops
].X_op
= 0;
530 d10v_insert_operand (insn
, op_type
, value
, left
, fix
)
539 shift
= d10v_operands
[op_type
].shift
;
543 bits
= d10v_operands
[op_type
].bits
;
545 /* truncate to the proper number of bits */
546 if (check_range (value
, bits
, d10v_operands
[op_type
].flags
))
547 as_bad_where (fix
->fx_file
, fix
->fx_line
, _("operand out of range: %d"), value
);
549 value
&= 0x7FFFFFFF >> (31 - bits
);
550 insn
|= (value
<< shift
);
556 /* build_insn takes a pointer to the opcode entry in the opcode table
557 and the array of operand expressions and returns the instruction */
560 build_insn (opcode
, opers
, insn
)
561 struct d10v_opcode
*opcode
;
565 int i
, bits
, shift
, flags
, format
;
566 unsigned long number
;
568 /* the insn argument is only used for the DIVS kludge */
573 insn
= opcode
->opcode
;
574 format
= opcode
->format
;
577 for (i
=0;opcode
->operands
[i
];i
++)
579 flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
580 bits
= d10v_operands
[opcode
->operands
[i
]].bits
;
581 shift
= d10v_operands
[opcode
->operands
[i
]].shift
;
582 number
= opers
[i
].X_add_number
;
584 if (flags
& OPERAND_REG
)
586 number
&= REGISTER_MASK
;
587 if (format
== LONG_L
)
591 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
)
593 /* now create a fixup */
595 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
596 as_fatal (_("too many fixups"));
598 if (AT_WORD_P (&opers
[i
]))
600 /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD) */
601 fixups
->fix
[fixups
->fc
].reloc
= BFD_RELOC_D10V_18
;
602 opers
[i
].X_op
= O_symbol
;
603 opers
[i
].X_op_symbol
= NULL
; /* Should free it */
604 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
605 that, it is aligned with the symbol's value. Later,
606 BFD_RELOC_D10V_18 will right shift (symbol_value +
608 number
<<= AT_WORD_RIGHT_SHIFT
;
609 opers
[i
].X_add_number
= number
;
612 fixups
->fix
[fixups
->fc
].reloc
=
613 get_reloc((struct d10v_operand
*)&d10v_operands
[opcode
->operands
[i
]]);
615 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_16
||
616 fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D10V_18
)
617 fixups
->fix
[fixups
->fc
].size
= 2;
619 fixups
->fix
[fixups
->fc
].size
= 4;
621 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
622 fixups
->fix
[fixups
->fc
].operand
= opcode
->operands
[i
];
623 fixups
->fix
[fixups
->fc
].pcrel
= (flags
& OPERAND_ADDR
) ? true : false;
627 /* truncate to the proper number of bits */
628 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
629 as_bad (_("operand out of range: %d"),number
);
630 number
&= 0x7FFFFFFF >> (31 - bits
);
631 insn
= insn
| (number
<< shift
);
634 /* kludge: for DIVS, we need to put the operands in twice */
635 /* on the second pass, format is changed to LONG_R to force */
636 /* the second set of operands to not be shifted over 15 */
637 if ((opcode
->opcode
== OPCODE_DIVS
) && (format
==LONG_L
))
638 insn
= build_insn (opcode
, opers
, insn
);
643 /* write out a long form instruction */
645 write_long (opcode
, insn
, fx
)
646 struct d10v_opcode
*opcode
;
651 char *f
= frag_more(4);
654 number_to_chars_bigendian (f
, insn
, 4);
656 for (i
=0; i
< fx
->fc
; i
++)
658 if (fx
->fix
[i
].reloc
)
660 where
= f
- frag_now
->fr_literal
;
661 if (fx
->fix
[i
].size
== 2)
664 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
665 fx
->fix
[i
].operand
|= 4096;
667 fix_new_exp (frag_now
,
672 fx
->fix
[i
].operand
|2048);
679 /* write out a short form instruction by itself */
681 write_1_short (opcode
, insn
, fx
)
682 struct d10v_opcode
*opcode
;
686 char *f
= frag_more(4);
689 if (opcode
->exec_type
& PARONLY
)
690 as_fatal (_("Instruction must be executed in parallel with another instruction."));
692 /* the other container needs to be NOP */
693 /* according to 4.3.1: for FM=00, sub-instructions performed only
694 by IU cannot be encoded in L-container. */
695 if (opcode
->unit
== IU
)
696 insn
|= FM00
| (NOP
<< 15); /* right container */
698 insn
= FM00
| (insn
<< 15) | NOP
; /* left container */
700 number_to_chars_bigendian (f
, insn
, 4);
701 for (i
=0; i
< fx
->fc
; i
++)
703 if (fx
->fix
[i
].reloc
)
705 where
= f
- frag_now
->fr_literal
;
706 if (fx
->fix
[i
].size
== 2)
709 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
710 fx
->fix
[i
].operand
|= 4096;
712 /* if it's an R reloc, we may have to switch it to L */
713 if ( (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (opcode
->unit
!= IU
) )
714 fx
->fix
[i
].operand
|= 1024;
716 fix_new_exp (frag_now
,
721 fx
->fix
[i
].operand
|2048);
727 /* write out a short form instruction if possible */
728 /* return number of instructions not written out */
730 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
731 struct d10v_opcode
*opcode1
, *opcode2
;
732 unsigned long insn1
, insn2
;
740 if ( (exec_type
!= 1) && ((opcode1
->exec_type
& PARONLY
)
741 || (opcode2
->exec_type
& PARONLY
)))
742 as_fatal (_("Instruction must be executed in parallel"));
744 if ( (opcode1
->format
& LONG_OPCODE
) || (opcode2
->format
& LONG_OPCODE
))
745 as_fatal (_("Long instructions may not be combined."));
747 if(opcode1
->exec_type
& BRANCH_LINK
&& exec_type
== 0)
749 /* Instructions paired with a subroutine call are executed before the
750 subroutine, so don't do these pairings unless explicitly requested. */
751 write_1_short (opcode1
, insn1
, fx
->next
);
757 case 0: /* order not specified */
758 if ( Optimizing
&& parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
761 if (opcode1
->unit
== IU
)
762 insn
= FM00
| (insn2
<< 15) | insn1
;
763 else if (opcode2
->unit
== MU
)
764 insn
= FM00
| (insn2
<< 15) | insn1
;
767 insn
= FM00
| (insn1
<< 15) | insn2
;
771 else if (opcode1
->unit
== IU
)
773 /* reverse sequential */
774 insn
= FM10
| (insn2
<< 15) | insn1
;
779 insn
= FM01
| (insn1
<< 15) | insn2
;
783 case 1: /* parallel */
784 if (opcode1
->exec_type
& SEQ
|| opcode2
->exec_type
& SEQ
)
785 as_fatal (_("One of these instructions may not be executed in parallel."));
787 if (opcode1
->unit
== IU
)
789 if (opcode2
->unit
== IU
)
790 as_fatal (_("Two IU instructions may not be executed in parallel"));
791 if (!flag_warn_suppress_instructionswap
)
792 as_warn (_("Swapping instruction order"));
793 insn
= FM00
| (insn2
<< 15) | insn1
;
795 else if (opcode2
->unit
== MU
)
797 if (opcode1
->unit
== MU
)
798 as_fatal (_("Two MU instructions may not be executed in parallel"));
799 if (!flag_warn_suppress_instructionswap
)
800 as_warn (_("Swapping instruction order"));
801 insn
= FM00
| (insn2
<< 15) | insn1
;
805 insn
= FM00
| (insn1
<< 15) | insn2
;
809 case 2: /* sequential */
810 if (opcode1
->unit
!= IU
)
811 insn
= FM01
| (insn1
<< 15) | insn2
;
812 else if (opcode2
->unit
== MU
|| opcode2
->unit
== EITHER
)
814 if (!flag_warn_suppress_instructionswap
)
815 as_warn (_("Swapping instruction order"));
816 insn
= FM10
| (insn2
<< 15) | insn1
;
819 as_fatal (_("IU instruction may not be in the left container"));
822 case 3: /* reverse sequential */
823 if (opcode2
->unit
!= MU
)
824 insn
= FM10
| (insn1
<< 15) | insn2
;
825 else if (opcode1
->unit
== IU
|| opcode1
->unit
== EITHER
)
827 if (!flag_warn_suppress_instructionswap
)
828 as_warn (_("Swapping instruction order"));
829 insn
= FM01
| (insn2
<< 15) | insn1
;
832 as_fatal (_("MU instruction may not be in the right container"));
836 as_fatal (_("unknown execution type passed to write_2_short()"));
840 number_to_chars_bigendian (f
, insn
, 4);
844 for (i
=0; i
< fx
->fc
; i
++)
846 if (fx
->fix
[i
].reloc
)
848 where
= f
- frag_now
->fr_literal
;
849 if (fx
->fix
[i
].size
== 2)
852 if ( (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (j
== 0) )
853 fx
->fix
[i
].operand
|= 1024;
855 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
856 fx
->fix
[i
].operand
|= 4096;
858 fix_new_exp (frag_now
,
863 fx
->fix
[i
].operand
|2048);
873 /* Check 2 instructions and determine if they can be safely */
874 /* executed in parallel. Returns 1 if they can be. */
876 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
877 struct d10v_opcode
*op1
, *op2
;
878 unsigned long insn1
, insn2
;
881 int i
, j
, flags
, mask
, shift
, regno
;
882 unsigned long ins
, mod
[2], used
[2];
883 struct d10v_opcode
*op
;
885 if ((op1
->exec_type
& SEQ
) != 0 || (op2
->exec_type
& SEQ
) != 0
886 || (op1
->exec_type
& PAR
) == 0 || (op2
->exec_type
& PAR
) == 0
887 || (op1
->unit
== BOTH
) || (op2
->unit
== BOTH
)
888 || (op1
->unit
== IU
&& op2
->unit
== IU
)
889 || (op1
->unit
== MU
&& op2
->unit
== MU
))
892 /* If the first instruction is a branch and this is auto parallazation,
893 don't combine with any second instruction. */
894 if (exec_type
== 0 && (op1
->exec_type
& BRANCH
) != 0)
897 /* The idea here is to create two sets of bitmasks (mod and used)
898 which indicate which registers are modified or used by each
899 instruction. The operation can only be done in parallel if
900 instruction 1 and instruction 2 modify different registers, and
901 the first instruction does not modify registers that the second
902 is using (The second instruction can modify registers that the
903 first is using as they are only written back after the first
904 instruction has completed). Accesses to control registers, PSW,
905 and memory are treated as accesses to a single register. So if
906 both instructions write memory or if the first instruction writes
907 memory and the second reads, then they cannot be done in
908 parallel. Likewise, if the first instruction mucks with the psw
909 and the second reads the PSW (which includes C, F0, and F1), then
910 they cannot operate safely in parallel. */
912 /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
915 /* cr (not psw) 18 */
931 mod
[j
] = used
[j
] = 0;
932 if (op
->exec_type
& BRANCH_LINK
)
935 for (i
= 0; op
->operands
[i
]; i
++)
937 flags
= d10v_operands
[op
->operands
[i
]].flags
;
938 shift
= d10v_operands
[op
->operands
[i
]].shift
;
939 mask
= 0x7FFFFFFF >> (31 - d10v_operands
[op
->operands
[i
]].bits
);
940 if (flags
& OPERAND_REG
)
942 regno
= (ins
>> shift
) & mask
;
943 if (flags
& (OPERAND_ACC0
|OPERAND_ACC1
))
945 else if (flags
& OPERAND_CONTROL
) /* mvtc or mvfc */
952 else if (flags
& (OPERAND_FFLAG
|OPERAND_CFLAG
))
955 if ( flags
& OPERAND_DEST
)
957 mod
[j
] |= 1 << regno
;
958 if (flags
& OPERAND_EVEN
)
959 mod
[j
] |= 1 << (regno
+ 1);
963 used
[j
] |= 1 << regno
;
964 if (flags
& OPERAND_EVEN
)
965 used
[j
] |= 1 << (regno
+ 1);
967 /* Auto inc/dec also modifies the register. */
968 if (op
->operands
[i
+1] != 0
969 && (d10v_operands
[op
->operands
[i
+1]].flags
970 & (OPERAND_PLUS
| OPERAND_MINUS
)) != 0)
971 mod
[j
] |= 1 << regno
;
974 else if (flags
& OPERAND_ATMINUS
)
976 /* SP implicitly used/modified */
981 if (op
->exec_type
& RMEM
)
983 else if (op
->exec_type
& WMEM
)
985 else if (op
->exec_type
& RF0
)
987 else if (op
->exec_type
& WF0
)
989 else if (op
->exec_type
& WCAR
)
992 if ((mod
[0] & mod
[1]) == 0 && (mod
[0] & used
[1]) == 0)
998 /* This is the main entry point for the machine-dependent assembler. str points to a
999 machine-dependent instruction. This function is supposed to emit the frags/bytes
1000 it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing
1001 and leaves the difficult stuff to do_assemble().
1004 static unsigned long prev_insn
;
1005 static struct d10v_opcode
*prev_opcode
= 0;
1006 static subsegT prev_subseg
;
1007 static segT prev_seg
= 0;;
1008 static int etype
= 0; /* saved extype. used for multiline instructions */
1014 struct d10v_opcode
* opcode
;
1016 int extype
= 0; /* execution type; parallel, etc */
1021 /* look for the special multiple instruction separators */
1022 str2
= strstr (str
, "||");
1027 str2
= strstr (str
, "->");
1032 str2
= strstr (str
, "<-");
1037 /* str2 points to the separator, if one */
1042 /* if two instructions are present and we already have one saved
1043 then first write it out */
1046 /* assemble first instruction and save it */
1047 prev_insn
= do_assemble (str
, &prev_opcode
);
1048 if (prev_insn
== -1)
1049 as_fatal (_("can't find opcode "));
1050 fixups
= fixups
->next
;
1055 insn
= do_assemble (str
, &opcode
);
1063 as_fatal (_("can't find opcode "));
1072 /* if this is a long instruction, write it and any previous short instruction */
1073 if (opcode
->format
& LONG_OPCODE
)
1076 as_fatal (_("Unable to mix instructions as specified"));
1078 write_long (opcode
, insn
, fixups
);
1083 if (prev_opcode
&& prev_seg
&& ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1086 if (prev_opcode
&& (write_2_short (prev_opcode
, prev_insn
, opcode
, insn
, extype
, fixups
) == 0))
1088 /* no instructions saved */
1094 as_fatal (_("Unable to mix instructions as specified"));
1095 /* save off last instruction so it may be packed on next pass */
1096 prev_opcode
= opcode
;
1099 prev_subseg
= now_subseg
;
1100 fixups
= fixups
->next
;
1105 /* do_assemble assembles a single instruction and returns an opcode */
1106 /* it returns -1 (an invalid opcode) on error */
1108 static unsigned long
1109 do_assemble (str
, opcode
)
1111 struct d10v_opcode
**opcode
;
1113 unsigned char *op_start
, *save
;
1114 unsigned char *op_end
;
1117 expressionS myops
[6];
1120 /* Drop leading whitespace. */
1124 /* Find the opcode end. */
1125 for (op_start
= op_end
= (unsigned char *) (str
);
1128 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1131 name
[nlen
] = tolower (op_start
[nlen
]);
1139 /* Find the first opcode with the proper name. */
1140 *opcode
= (struct d10v_opcode
*)hash_find (d10v_hash
, name
);
1141 if (*opcode
== NULL
)
1142 as_fatal (_("unknown opcode: %s"),name
);
1144 save
= input_line_pointer
;
1145 input_line_pointer
= op_end
;
1146 *opcode
= find_opcode (*opcode
, myops
);
1149 input_line_pointer
= save
;
1151 insn
= build_insn ((*opcode
), myops
, 0);
1155 /* Find the symbol which has the same name as the register in the given expression. */
1157 find_symbol_matching_register (exp
)
1162 if (exp
->X_op
!= O_register
)
1165 /* Find the name of the register. */
1166 for (i
= d10v_reg_name_cnt (); i
--;)
1167 if (d10v_predefined_registers
[i
].value
== exp
->X_add_number
)
1173 /* Now see if a symbol has been defined with the same name. */
1174 return symbol_find (d10v_predefined_registers
[i
].name
);
1178 /* find_opcode() gets a pointer to an entry in the opcode table. */
1179 /* It must look at all opcodes with the same name and use the operands */
1180 /* to choose the correct opcode. */
1182 static struct d10v_opcode
*
1183 find_opcode (opcode
, myops
)
1184 struct d10v_opcode
*opcode
;
1185 expressionS myops
[];
1188 struct d10v_opcode
*next_opcode
;
1190 /* get all the operands and save them as expressions */
1191 get_operands (myops
);
1193 /* now see if the operand is a fake. If so, find the correct size */
1194 /* instruction, if possible */
1195 if (opcode
->format
== OPCODE_FAKE
)
1197 int opnum
= opcode
->operands
[0];
1200 if (myops
[opnum
].X_op
== O_register
)
1202 myops
[opnum
].X_op
= O_symbol
;
1203 myops
[opnum
].X_add_symbol
= symbol_find_or_make ((char *)myops
[opnum
].X_op_symbol
);
1204 myops
[opnum
].X_add_number
= 0;
1205 myops
[opnum
].X_op_symbol
= NULL
;
1208 next_opcode
=opcode
+1;
1210 /* If the first operand is supposed to be a register, make sure
1211 we got a valid one. */
1212 flags
= d10v_operands
[next_opcode
->operands
[0]].flags
;
1213 if (flags
& OPERAND_REG
)
1215 int X_op
= myops
[0].X_op
;
1216 int num
= myops
[0].X_add_number
;
1218 if (X_op
!= O_register
1220 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1221 | OPERAND_FFLAG
| OPERAND_CFLAG
| OPERAND_CONTROL
)))
1223 as_bad (_("bad opcode or operands"));
1228 if (myops
[opnum
].X_op
== O_constant
|| (myops
[opnum
].X_op
== O_symbol
&&
1229 S_IS_DEFINED(myops
[opnum
].X_add_symbol
) &&
1230 (S_GET_SEGMENT(myops
[opnum
].X_add_symbol
) == now_seg
)))
1232 for (i
=0; opcode
->operands
[i
+1]; i
++)
1234 int bits
= d10v_operands
[next_opcode
->operands
[opnum
]].bits
;
1235 int flags
= d10v_operands
[next_opcode
->operands
[opnum
]].flags
;
1236 if (flags
& OPERAND_ADDR
)
1238 if (myops
[opnum
].X_op
== O_constant
)
1240 if (!check_range (myops
[opnum
].X_add_number
, bits
, flags
))
1247 /* calculate the current address by running through the previous frags */
1248 /* and adding our current offset */
1249 for (value
= 0, f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1250 value
+= f
->fr_fix
+ f
->fr_offset
;
1252 if (flags
& OPERAND_ADDR
)
1253 value
= S_GET_VALUE(myops
[opnum
].X_add_symbol
) - value
-
1254 (obstack_next_free(&frchain_now
->frch_obstack
) - frag_now
->fr_literal
);
1256 value
+= S_GET_VALUE(myops
[opnum
].X_add_symbol
);
1258 if (AT_WORD_P (&myops
[opnum
]))
1263 if (!check_range (value
, bits
, flags
))
1267 else if (!check_range (value
, bits
, flags
))
1272 as_fatal (_("value out of range"));
1276 /* not a constant, so use a long instruction */
1283 /* now search the opcode table table for one with operands */
1284 /* that matches what we've got */
1288 for (i
= 0; opcode
->operands
[i
]; i
++)
1290 int flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
1291 int X_op
= myops
[i
].X_op
;
1292 int num
= myops
[i
].X_add_number
;
1300 if (flags
& OPERAND_REG
)
1302 if ((X_op
!= O_register
)
1304 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1305 | OPERAND_FFLAG
| OPERAND_CFLAG
1306 | OPERAND_CONTROL
)))
1313 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
1314 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
1315 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
1316 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
1317 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || ((num
!= OPERAND_ATSIGN
) && (num
!= OPERAND_ATPAR
)))))
1323 /* Unfortunatly, for the indirect operand in instructions such as
1324 ``ldb r1, @(c,r14)'' this function can be passed X_op == O_register
1325 (because 'c' is a valid register name). However we cannot just
1326 ignore the case when X_op == O_register but flags & OPERAND_REG is
1327 null, so we check to see if a symbol of the same name as the register
1328 exists. If the symbol does exist, then the parser was unable to
1329 distinguish the two cases and we fix things here. (Ref: PR14826) */
1331 if (!(flags
& OPERAND_REG
) && (X_op
== O_register
))
1335 sym
= find_symbol_matching_register (& myops
[i
]);
1339 myops
[i
].X_op
== X_op
== O_symbol
;
1340 myops
[i
].X_add_symbol
= sym
;
1344 (_("illegal operand - register name found where none expected"));
1348 /* We're only done if the operands matched so far AND there
1349 are no more to check. */
1350 if (match
&& myops
[i
].X_op
== 0)
1355 next_opcode
= opcode
+ 1;
1357 if (next_opcode
->opcode
== 0)
1360 if (strcmp (next_opcode
->name
, opcode
->name
))
1363 opcode
= next_opcode
;
1369 as_bad (_("bad opcode or operands"));
1373 /* Check that all registers that are required to be even are. */
1374 /* Also, if any operands were marked as registers, but were really symbols */
1375 /* fix that here. */
1376 for (i
=0; opcode
->operands
[i
]; i
++)
1378 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_EVEN
) &&
1379 (myops
[i
].X_add_number
& 1))
1380 as_fatal (_("Register number must be EVEN"));
1381 if (myops
[i
].X_op
== O_register
)
1383 if (!(d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_REG
))
1385 myops
[i
].X_op
= O_symbol
;
1386 myops
[i
].X_add_symbol
= symbol_find_or_make ((char *)myops
[i
].X_op_symbol
);
1387 myops
[i
].X_add_number
= 0;
1388 myops
[i
].X_op_symbol
= NULL
;
1395 /* if while processing a fixup, a reloc really needs to be created */
1396 /* then it is done here */
1399 tc_gen_reloc (seg
, fixp
)
1404 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1405 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1406 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1407 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1408 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1409 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1411 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1412 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1416 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1417 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1418 reloc
->address
= fixp
->fx_offset
;
1420 reloc
->addend
= fixp
->fx_addnumber
;
1426 md_estimate_size_before_relax (fragp
, seg
)
1435 md_pcrel_from_section (fixp
, sec
)
1439 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1440 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1442 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1446 md_apply_fix3 (fixp
, valuep
, seg
)
1457 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1462 else if (fixp
->fx_pcrel
)
1466 value
= fixp
->fx_offset
;
1467 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1469 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1470 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1473 /* We don't actually support subtracting a symbol. */
1474 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1475 _("expression too complex"));
1480 op_type
= fixp
->fx_r_type
;
1487 fixp
->fx_r_type
= BFD_RELOC_D10V_10_PCREL_L
;
1490 else if (op_type
& 4096)
1493 fixp
->fx_r_type
= BFD_RELOC_D10V_18
;
1496 fixp
->fx_r_type
= get_reloc((struct d10v_operand
*)&d10v_operands
[op_type
]);
1499 /* Fetch the instruction, insert the fully resolved operand
1500 value, and stuff the instruction back again. */
1501 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1502 insn
= bfd_getb32 ((unsigned char *) where
);
1504 switch (fixp
->fx_r_type
)
1506 case BFD_RELOC_D10V_10_PCREL_L
:
1507 case BFD_RELOC_D10V_10_PCREL_R
:
1508 case BFD_RELOC_D10V_18_PCREL
:
1509 case BFD_RELOC_D10V_18
:
1510 /* instruction addresses are always right-shifted by 2 */
1511 value
>>= AT_WORD_RIGHT_SHIFT
;
1512 if (fixp
->fx_size
== 2)
1513 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1516 struct d10v_opcode
*rep
, *repi
;
1518 rep
= (struct d10v_opcode
*) hash_find (d10v_hash
, "rep");
1519 repi
= (struct d10v_opcode
*) hash_find (d10v_hash
, "repi");
1520 if ((insn
& FM11
) == FM11
1521 && (repi
!= NULL
&& (insn
& repi
->mask
) == repi
->opcode
1522 || rep
!= NULL
&& (insn
& rep
->mask
) == rep
->opcode
)
1525 (_("line %d: rep or repi must include at least 4 instructions"),
1527 insn
= d10v_insert_operand (insn
, op_type
, (offsetT
)value
, left
, fixp
);
1528 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1532 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1535 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1538 case BFD_RELOC_VTABLE_INHERIT
:
1539 case BFD_RELOC_VTABLE_ENTRY
:
1544 as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp
->fx_line
,fixp
->fx_r_type
);
1549 /* d10v_cleanup() is called after the assembler has finished parsing the input
1550 file or after a label is defined. Because the D10V assembler sometimes saves short
1551 instructions to see if it can package them with the next instruction, there may
1552 be a short instruction that still needs written. */
1559 if (prev_opcode
&& etype
== 0)
1562 subseg
= now_subseg
;
1564 subseg_set (prev_seg
, prev_subseg
);
1565 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
1566 subseg_set (seg
, subseg
);
1572 /* Like normal .word, except support @word */
1573 /* clobbers input_line_pointer, checks end-of-line. */
1575 d10v_dot_word (nbytes
)
1576 register int nbytes
; /* 1=.byte, 2=.word, 4=.long */
1579 bfd_reloc_code_real_type reloc
;
1583 if (is_it_end_of_statement ())
1585 demand_empty_rest_of_line ();
1592 if (!strncasecmp (input_line_pointer
, "@word", 5))
1594 exp
.X_add_number
= 0;
1595 input_line_pointer
+= 5;
1598 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
1599 &exp
, 0, BFD_RELOC_D10V_18
);
1602 emit_expr (&exp
, 2);
1604 while (*input_line_pointer
++ == ',');
1606 input_line_pointer
--; /* Put terminator back into stream. */
1607 demand_empty_rest_of_line ();
1611 /* Mitsubishi asked that we support some old syntax that apparently */
1612 /* had immediate operands starting with '#'. This is in some of their */
1613 /* sample code but is not documented (although it appears in some */
1614 /* examples in their assembler manual). For now, we'll solve this */
1615 /* compatibility problem by simply ignoring any '#' at the beginning */
1616 /* of an operand. */
1618 /* operands that begin with '#' should fall through to here */
1622 md_operand (expressionP
)
1623 expressionS
*expressionP
;
1625 if (*input_line_pointer
== '#' && ! do_not_ignore_hash
)
1627 input_line_pointer
++;
1628 expression (expressionP
);
1633 d10v_fix_adjustable (fixP
)
1637 if (fixP
->fx_addsy
== NULL
)
1640 /* Prevent all adjustments to global symbols. */
1641 if (S_IS_EXTERN (fixP
->fx_addsy
))
1643 if (S_IS_WEAK (fixP
->fx_addsy
))
1646 /* We need the symbol name for the VTABLE entries */
1647 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1648 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1655 d10v_force_relocation (fixp
)
1658 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1659 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)