1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
2 Copyright (C) 1996-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
19 Boston, MA 02110-1301, USA. */
22 #include "safe-ctype.h"
24 #include "opcode/d10v.h"
26 #include "dwarf2dbg.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "O";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
37 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
38 && (X)->X_op_symbol != NULL \
39 && symbol_constant_p ((X)->X_op_symbol) \
40 && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
41 #define AT_WORD_RIGHT_SHIFT 2
44 #define MAX_INSN_FIXUPS 5
52 bfd_reloc_code_real_type reloc
;
55 typedef struct _fixups
58 struct d10v_fixup fix
[MAX_INSN_FIXUPS
];
62 static Fixups FixUps
[2];
63 static Fixups
*fixups
;
65 static int do_not_ignore_hash
= 0;
67 typedef int packing_type
;
68 #define PACK_UNSPEC (0) /* Packing order not specified. */
69 #define PACK_PARALLEL (1) /* "||" */
70 #define PACK_LEFT_RIGHT (2) /* "->" */
71 #define PACK_RIGHT_LEFT (3) /* "<-" */
72 static packing_type etype
= PACK_UNSPEC
; /* Used by d10v_cleanup. */
74 /* TRUE if instruction swapping warnings should be inhibited.
76 static bfd_boolean flag_warn_suppress_instructionswap
;
78 /* TRUE if instruction packing should be performed when --gstabs is specified.
79 --gstabs-packing, --no-gstabs-packing. */
80 static bfd_boolean flag_allow_gstabs_packing
= 1;
82 /* Local functions. */
86 OPTION_NOWARNSWAP
= OPTION_MD_BASE
,
88 OPTION_NOGSTABSPACKING
91 struct option md_longopts
[] =
93 {"nowarnswap", no_argument
, NULL
, OPTION_NOWARNSWAP
},
94 {"gstabspacking", no_argument
, NULL
, OPTION_GSTABSPACKING
},
95 {"gstabs-packing", no_argument
, NULL
, OPTION_GSTABSPACKING
},
96 {"nogstabspacking", no_argument
, NULL
, OPTION_NOGSTABSPACKING
},
97 {"no-gstabs-packing", no_argument
, NULL
, OPTION_NOGSTABSPACKING
},
98 {NULL
, no_argument
, NULL
, 0}
101 size_t md_longopts_size
= sizeof (md_longopts
);
103 /* Opcode hash table. */
104 static struct hash_control
*d10v_hash
;
106 /* Do a binary search of the d10v_predefined_registers array to see if
107 NAME is a valid regiter name. Return the register number from the
108 array on success, or -1 on failure. */
111 reg_name_search (char *name
)
113 int middle
, low
, high
;
117 high
= d10v_reg_name_cnt () - 1;
121 middle
= (low
+ high
) / 2;
122 cmp
= strcasecmp (name
, d10v_predefined_registers
[middle
].name
);
128 return d10v_predefined_registers
[middle
].value
;
134 /* Check the string at input_line_pointer
135 to see if it is a valid register name. */
138 register_name (expressionS
*expressionP
)
141 char c
, *p
= input_line_pointer
;
144 && *p
!= '\n' && *p
!= '\r' && *p
!= ',' && *p
!= ' ' && *p
!= ')')
151 /* Look to see if it's in the register table. */
152 reg_number
= reg_name_search (input_line_pointer
);
155 expressionP
->X_op
= O_register
;
156 /* Temporarily store a pointer to the string here. */
157 expressionP
->X_op_symbol
= (symbolS
*) input_line_pointer
;
158 expressionP
->X_add_number
= reg_number
;
159 input_line_pointer
= p
;
168 check_range (unsigned long num
, int bits
, int flags
)
173 /* Don't bother checking 16-bit values. */
177 if (flags
& OPERAND_SHIFT
)
179 /* All special shift operands are unsigned and <= 16.
180 We allow 0 for now. */
187 if (flags
& OPERAND_SIGNED
)
189 /* Signed 3-bit integers are restricted to the (-2, 3) range. */
190 if (flags
& RESTRICTED_NUM3
)
192 if ((long) num
< -2 || (long) num
> 3)
197 max
= (1 << (bits
- 1)) - 1;
198 min
= - (1 << (bits
- 1));
199 if (((long) num
> max
) || ((long) num
< min
))
205 max
= (1 << bits
) - 1;
207 if (((long) num
> max
) || ((long) num
< min
))
214 md_show_usage (FILE *stream
)
216 fprintf (stream
, _("D10V options:\n\
217 -O Optimize. Will do some operations in parallel.\n\
218 --gstabs-packing Pack adjacent short instructions together even\n\
219 when --gstabs is specified. On by default.\n\
220 --no-gstabs-packing If --gstabs is specified, do not pack adjacent\n\
221 instructions together.\n"));
225 md_parse_option (int c
, char *arg ATTRIBUTE_UNUSED
)
230 /* Optimize. Will attempt to parallelize operations. */
233 case OPTION_NOWARNSWAP
:
234 flag_warn_suppress_instructionswap
= 1;
236 case OPTION_GSTABSPACKING
:
237 flag_allow_gstabs_packing
= 1;
239 case OPTION_NOGSTABSPACKING
:
240 flag_allow_gstabs_packing
= 0;
249 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
255 md_atof (int type
, char *litP
, int *sizeP
)
257 return ieee_md_atof (type
, litP
, sizeP
, TRUE
);
261 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
262 asection
*sec ATTRIBUTE_UNUSED
,
263 fragS
*fragP ATTRIBUTE_UNUSED
)
269 md_section_align (asection
*seg
, valueT addr
)
271 int align
= bfd_get_section_alignment (stdoutput
, seg
);
272 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
278 char *prev_name
= "";
279 struct d10v_opcode
*opcode
;
280 d10v_hash
= hash_new ();
282 /* Insert unique names into hash table. The D10v instruction set
283 has many identical opcode names that have different opcodes based
284 on the operands. This hash table then provides a quick index to
285 the first opcode with a particular name in the opcode table. */
287 for (opcode
= (struct d10v_opcode
*) d10v_opcodes
; opcode
->name
; opcode
++)
289 if (strcmp (prev_name
, opcode
->name
))
291 prev_name
= (char *) opcode
->name
;
292 hash_insert (d10v_hash
, opcode
->name
, (char *) opcode
);
297 FixUps
[0].next
= &FixUps
[1];
298 FixUps
[1].next
= &FixUps
[0];
301 /* Remove the postincrement or postdecrement operator ( '+' or '-' )
302 from an expression. */
307 while (*p
!= '-' && *p
!= '+')
309 if (*p
== 0 || *p
== '\n' || *p
== '\r')
328 static bfd_reloc_code_real_type
329 get_reloc (struct d10v_operand
*op
)
336 if (op
->flags
& OPERAND_ADDR
)
339 return BFD_RELOC_D10V_10_PCREL_R
;
341 return BFD_RELOC_D10V_18_PCREL
;
347 /* Parse a string of operands. Return an array of expressions. */
350 get_operands (expressionS exp
[])
352 char *p
= input_line_pointer
;
359 while (*p
== ' ' || *p
== '\t' || *p
== ',')
361 if (*p
== 0 || *p
== '\n' || *p
== '\r')
369 exp
[numops
].X_op
= O_absent
;
373 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
378 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
382 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
386 exp
[numops
].X_op
= O_absent
;
387 exp
[numops
].X_add_number
= OPERAND_PLUS
;
398 /* Just skip the trailing paren. */
403 input_line_pointer
= p
;
405 /* Check to see if it might be a register name. */
406 if (!register_name (&exp
[numops
]))
408 /* Parse as an expression. */
411 /* Any expression that involves the indirect addressing
412 cannot also involve immediate addressing. Therefore
413 the use of the hash character is illegal. */
414 int save
= do_not_ignore_hash
;
415 do_not_ignore_hash
= 1;
417 expression (&exp
[numops
]);
419 do_not_ignore_hash
= save
;
422 expression (&exp
[numops
]);
425 if (strncasecmp (input_line_pointer
, "@word", 5) == 0)
427 input_line_pointer
+= 5;
428 if (exp
[numops
].X_op
== O_register
)
430 /* If it looked like a register name but was followed by
431 "@word" then it was really a symbol, so change it to
433 exp
[numops
].X_op
= O_symbol
;
434 exp
[numops
].X_add_symbol
=
435 symbol_find_or_make ((char *) exp
[numops
].X_op_symbol
);
438 /* Check for identifier@word+constant. */
439 if (*input_line_pointer
== '-' || *input_line_pointer
== '+')
442 expression (&new_exp
);
443 exp
[numops
].X_add_number
= new_exp
.X_add_number
;
446 /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */
449 memset (&new_exp
, 0, sizeof new_exp
);
450 new_exp
.X_add_number
= AT_WORD_RIGHT_SHIFT
;
451 new_exp
.X_op
= O_constant
;
452 new_exp
.X_unsigned
= 1;
453 exp
[numops
].X_op_symbol
= make_expr_symbol (&new_exp
);
454 exp
[numops
].X_op
= O_right_shift
;
457 know (AT_WORD_P (&exp
[numops
]));
460 if (exp
[numops
].X_op
== O_illegal
)
461 as_bad (_("illegal operand"));
462 else if (exp
[numops
].X_op
== O_absent
)
463 as_bad (_("missing operand"));
466 p
= input_line_pointer
;
471 case -1: /* Postdecrement mode. */
472 exp
[numops
].X_op
= O_absent
;
473 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
475 case 1: /* Postincrement mode. */
476 exp
[numops
].X_op
= O_absent
;
477 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
481 exp
[numops
].X_op
= 0;
486 d10v_insert_operand (unsigned long insn
,
494 shift
= d10v_operands
[op_type
].shift
;
498 bits
= d10v_operands
[op_type
].bits
;
500 /* Truncate to the proper number of bits. */
501 if (check_range (value
, bits
, d10v_operands
[op_type
].flags
))
502 as_bad_where (fix
->fx_file
, fix
->fx_line
,
503 _("operand out of range: %ld"), (long) value
);
505 value
&= 0x7FFFFFFF >> (31 - bits
);
506 insn
|= (value
<< shift
);
511 /* Take a pointer to the opcode entry in the opcode table and the
512 array of operand expressions. Return the instruction. */
515 build_insn (struct d10v_opcode
*opcode
,
519 int i
, bits
, shift
, flags
, format
;
520 unsigned long number
;
522 /* The insn argument is only used for the DIVS kludge. */
527 insn
= opcode
->opcode
;
528 format
= opcode
->format
;
531 for (i
= 0; opcode
->operands
[i
]; i
++)
533 flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
534 bits
= d10v_operands
[opcode
->operands
[i
]].bits
;
535 shift
= d10v_operands
[opcode
->operands
[i
]].shift
;
536 number
= opers
[i
].X_add_number
;
538 if (flags
& OPERAND_REG
)
540 number
&= REGISTER_MASK
;
541 if (format
== LONG_L
)
545 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
)
547 /* Now create a fixup. */
549 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
550 as_fatal (_("too many fixups"));
552 if (AT_WORD_P (&opers
[i
]))
554 /* Recognize XXX>>1+N aka XXX@word+N as special (AT_WORD). */
555 fixups
->fix
[fixups
->fc
].reloc
= BFD_RELOC_D10V_18
;
556 opers
[i
].X_op
= O_symbol
;
557 opers
[i
].X_op_symbol
= NULL
; /* Should free it. */
558 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
559 that, it is aligned with the symbol's value. Later,
560 BFD_RELOC_D10V_18 will right shift (symbol_value +
562 number
<<= AT_WORD_RIGHT_SHIFT
;
563 opers
[i
].X_add_number
= number
;
567 fixups
->fix
[fixups
->fc
].reloc
=
568 get_reloc ((struct d10v_operand
*) &d10v_operands
[opcode
->operands
[i
]]);
570 /* Check that an immediate was passed to ops that expect one. */
571 if ((flags
& OPERAND_NUM
)
572 && (fixups
->fix
[fixups
->fc
].reloc
== 0))
573 as_bad (_("operand is not an immediate"));
576 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_16
||
577 fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D10V_18
)
578 fixups
->fix
[fixups
->fc
].size
= 2;
580 fixups
->fix
[fixups
->fc
].size
= 4;
582 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
583 fixups
->fix
[fixups
->fc
].operand
= opcode
->operands
[i
];
584 fixups
->fix
[fixups
->fc
].pcrel
=
585 (flags
& OPERAND_ADDR
) ? TRUE
: FALSE
;
589 /* Truncate to the proper number of bits. */
590 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
591 as_bad (_("operand out of range: %lu"), number
);
592 number
&= 0x7FFFFFFF >> (31 - bits
);
593 insn
= insn
| (number
<< shift
);
596 /* kludge: for DIVS, we need to put the operands in twice on the second
597 pass, format is changed to LONG_R to force the second set of operands
598 to not be shifted over 15. */
599 if ((opcode
->opcode
== OPCODE_DIVS
) && (format
== LONG_L
))
600 insn
= build_insn (opcode
, opers
, insn
);
605 /* Write out a long form instruction. */
608 write_long (unsigned long insn
, Fixups
*fx
)
611 char *f
= frag_more (4);
613 dwarf2_emit_insn (4);
615 number_to_chars_bigendian (f
, insn
, 4);
617 for (i
= 0; i
< fx
->fc
; i
++)
619 if (fx
->fix
[i
].reloc
)
621 where
= f
- frag_now
->fr_literal
;
622 if (fx
->fix
[i
].size
== 2)
625 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
626 fx
->fix
[i
].operand
|= 4096;
628 fix_new_exp (frag_now
,
633 fx
->fix
[i
].operand
|2048);
639 /* Write out a short form instruction by itself. */
642 write_1_short (struct d10v_opcode
*opcode
,
646 char *f
= frag_more (4);
649 dwarf2_emit_insn (4);
650 if (opcode
->exec_type
& PARONLY
)
651 as_fatal (_("Instruction must be executed in parallel with another instruction."));
653 /* The other container needs to be NOP.
654 According to 4.3.1: for FM=00, sub-instructions performed only by IU
655 cannot be encoded in L-container. */
656 if (opcode
->unit
== IU
)
657 insn
|= FM00
| (NOP
<< 15); /* Right container. */
659 insn
= FM00
| (insn
<< 15) | NOP
; /* Left container. */
661 number_to_chars_bigendian (f
, insn
, 4);
662 for (i
= 0; i
< fx
->fc
; i
++)
664 if (fx
->fix
[i
].reloc
)
666 where
= f
- frag_now
->fr_literal
;
667 if (fx
->fix
[i
].size
== 2)
670 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
671 fx
->fix
[i
].operand
|= 4096;
673 /* If it's an R reloc, we may have to switch it to L. */
674 if ((fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
)
675 && (opcode
->unit
!= IU
))
676 fx
->fix
[i
].operand
|= 1024;
678 fix_new_exp (frag_now
,
683 fx
->fix
[i
].operand
|2048);
689 /* Determine if there are any resource conflicts among two manually
690 parallelized instructions. Some of this was lifted from parallel_ok. */
693 check_resource_conflict (struct d10v_opcode
*op1
,
695 struct d10v_opcode
*op2
,
698 int i
, j
, flags
, mask
, shift
, regno
;
699 unsigned long ins
, mod
[2];
700 struct d10v_opcode
*op
;
702 if ((op1
->exec_type
& SEQ
)
703 || ! ((op1
->exec_type
& PAR
) || (op1
->exec_type
& PARONLY
)))
705 as_warn (_("packing conflict: %s must dispatch sequentially"),
710 if ((op2
->exec_type
& SEQ
)
711 || ! ((op2
->exec_type
& PAR
) || (op2
->exec_type
& PARONLY
)))
713 as_warn (_("packing conflict: %s must dispatch sequentially"),
718 /* See if both instructions write to the same resource.
720 The idea here is to create two sets of bitmasks (mod and used) which
721 indicate which registers are modified or used by each instruction.
722 The operation can only be done in parallel if neither instruction
723 modifies the same register. Accesses to control registers and memory
724 are treated as accesses to a single register. So if both instructions
725 write memory or if the first instruction writes memory and the second
726 reads, then they cannot be done in parallel. We treat reads to the PSW
727 (which includes C, F0, and F1) in isolation. So simultaneously writing
728 C and F0 in two different sub-instructions is permitted. */
730 /* The bitmasks (mod and used) look like this (bit 31 = MSB).
739 for (j
= 0; j
< 2; j
++)
752 if (op
->exec_type
& BRANCH_LINK
)
755 for (i
= 0; op
->operands
[i
]; i
++)
757 flags
= d10v_operands
[op
->operands
[i
]].flags
;
758 shift
= d10v_operands
[op
->operands
[i
]].shift
;
759 mask
= 0x7FFFFFFF >> (31 - d10v_operands
[op
->operands
[i
]].bits
);
760 if (flags
& OPERAND_REG
)
762 regno
= (ins
>> shift
) & mask
;
763 if (flags
& (OPERAND_ACC0
| OPERAND_ACC1
))
765 else if (flags
& OPERAND_CONTROL
) /* mvtc or mvfc */
772 else if (flags
& OPERAND_FFLAG
)
774 else if (flags
& OPERAND_CFLAG
)
777 if (flags
& OPERAND_DEST
778 /* Auto inc/dec also modifies the register. */
779 || (op
->operands
[i
+ 1] != 0
780 && (d10v_operands
[op
->operands
[i
+ 1]].flags
781 & (OPERAND_PLUS
| OPERAND_MINUS
)) != 0))
783 mod
[j
] |= 1 << regno
;
784 if (flags
& OPERAND_EVEN
)
785 mod
[j
] |= 1 << (regno
+ 1);
788 else if (flags
& OPERAND_ATMINUS
)
790 /* SP implicitly used/modified. */
795 if (op
->exec_type
& WMEM
)
797 else if (op
->exec_type
& WF0
)
799 else if (op
->exec_type
& WCAR
)
803 if ((mod
[0] & mod
[1]) == 0)
810 for (j
= 0; j
<= 15; j
++)
812 as_warn (_("resource conflict (R%d)"), j
);
813 for (j
= 16; j
<= 17; j
++)
815 as_warn (_("resource conflict (A%d)"), j
- 16);
817 as_warn (_("resource conflict (PSW)"));
819 as_warn (_("resource conflict (C flag)"));
821 as_warn (_("resource conflict (F flag)"));
825 /* Check 2 instructions and determine if they can be safely
826 executed in parallel. Return 1 if they can be. */
829 parallel_ok (struct d10v_opcode
*op1
,
831 struct d10v_opcode
*op2
,
833 packing_type exec_type
)
835 int i
, j
, flags
, mask
, shift
, regno
;
836 unsigned long ins
, mod
[2], used
[2];
837 struct d10v_opcode
*op
;
839 if ((op1
->exec_type
& SEQ
) != 0 || (op2
->exec_type
& SEQ
) != 0
840 || (op1
->exec_type
& PAR
) == 0 || (op2
->exec_type
& PAR
) == 0
841 || (op1
->unit
== BOTH
) || (op2
->unit
== BOTH
)
842 || (op1
->unit
== IU
&& op2
->unit
== IU
)
843 || (op1
->unit
== MU
&& op2
->unit
== MU
))
846 /* If this is auto parallelization, and the first instruction is a
847 branch or should not be packed, then don't parallelize. */
848 if (exec_type
== PACK_UNSPEC
849 && (op1
->exec_type
& (ALONE
| BRANCH
)))
852 /* The idea here is to create two sets of bitmasks (mod and used)
853 which indicate which registers are modified or used by each
854 instruction. The operation can only be done in parallel if
855 instruction 1 and instruction 2 modify different registers, and
856 the first instruction does not modify registers that the second
857 is using (The second instruction can modify registers that the
858 first is using as they are only written back after the first
859 instruction has completed). Accesses to control registers, PSW,
860 and memory are treated as accesses to a single register. So if
861 both instructions write memory or if the first instruction writes
862 memory and the second reads, then they cannot be done in
863 parallel. Likewise, if the first instruction mucks with the psw
864 and the second reads the PSW (which includes C, F0, and F1), then
865 they cannot operate safely in parallel. */
867 /* The bitmasks (mod and used) look like this (bit 31 = MSB).
874 for (j
= 0; j
< 2; j
++)
886 mod
[j
] = used
[j
] = 0;
887 if (op
->exec_type
& BRANCH_LINK
)
890 for (i
= 0; op
->operands
[i
]; i
++)
892 flags
= d10v_operands
[op
->operands
[i
]].flags
;
893 shift
= d10v_operands
[op
->operands
[i
]].shift
;
894 mask
= 0x7FFFFFFF >> (31 - d10v_operands
[op
->operands
[i
]].bits
);
895 if (flags
& OPERAND_REG
)
897 regno
= (ins
>> shift
) & mask
;
898 if (flags
& (OPERAND_ACC0
| OPERAND_ACC1
))
900 else if (flags
& OPERAND_CONTROL
) /* mvtc or mvfc. */
907 else if (flags
& (OPERAND_FFLAG
| OPERAND_CFLAG
))
910 if (flags
& OPERAND_DEST
)
912 mod
[j
] |= 1 << regno
;
913 if (flags
& OPERAND_EVEN
)
914 mod
[j
] |= 1 << (regno
+ 1);
918 used
[j
] |= 1 << regno
;
919 if (flags
& OPERAND_EVEN
)
920 used
[j
] |= 1 << (regno
+ 1);
922 /* Auto inc/dec also modifies the register. */
923 if (op
->operands
[i
+ 1] != 0
924 && (d10v_operands
[op
->operands
[i
+ 1]].flags
925 & (OPERAND_PLUS
| OPERAND_MINUS
)) != 0)
926 mod
[j
] |= 1 << regno
;
929 else if (flags
& OPERAND_ATMINUS
)
931 /* SP implicitly used/modified. */
936 if (op
->exec_type
& RMEM
)
938 else if (op
->exec_type
& WMEM
)
940 else if (op
->exec_type
& RF0
)
942 else if (op
->exec_type
& WF0
)
944 else if (op
->exec_type
& WCAR
)
947 if ((mod
[0] & mod
[1]) == 0 && (mod
[0] & used
[1]) == 0)
952 /* Expects two short instructions.
953 If possible, writes out both as a single packed instruction.
954 Otherwise, writes out the first one, packed with a NOP.
955 Returns number of instructions not written out. */
958 write_2_short (struct d10v_opcode
*opcode1
,
960 struct d10v_opcode
*opcode2
,
962 packing_type exec_type
,
969 if ((exec_type
!= PACK_PARALLEL
)
970 && ((opcode1
->exec_type
& PARONLY
) || (opcode2
->exec_type
& PARONLY
)))
971 as_fatal (_("Instruction must be executed in parallel"));
973 if ((opcode1
->format
& LONG_OPCODE
) || (opcode2
->format
& LONG_OPCODE
))
974 as_fatal (_("Long instructions may not be combined."));
978 case PACK_UNSPEC
: /* Order not specified. */
979 if (opcode1
->exec_type
& ALONE
)
981 /* Case of a short branch on a separate GAS line. Pack with NOP. */
982 write_1_short (opcode1
, insn1
, fx
->next
);
986 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
989 if (opcode1
->unit
== IU
)
990 insn
= FM00
| (insn2
<< 15) | insn1
;
991 else if (opcode2
->unit
== MU
)
992 insn
= FM00
| (insn2
<< 15) | insn1
;
994 insn
= FM00
| (insn1
<< 15) | insn2
;
996 else if (opcode1
->unit
== IU
)
997 /* Reverse sequential with IU opcode1 on right and done first. */
998 insn
= FM10
| (insn2
<< 15) | insn1
;
1000 /* Sequential with non-IU opcode1 on left and done first. */
1001 insn
= FM01
| (insn1
<< 15) | insn2
;
1005 if (opcode1
->exec_type
& SEQ
|| opcode2
->exec_type
& SEQ
)
1007 (_("One of these instructions may not be executed in parallel."));
1008 if (opcode1
->unit
== IU
)
1010 if (opcode2
->unit
== IU
)
1011 as_fatal (_("Two IU instructions may not be executed in parallel"));
1012 if (!flag_warn_suppress_instructionswap
)
1013 as_warn (_("Swapping instruction order"));
1014 insn
= FM00
| (insn2
<< 15) | insn1
;
1016 else if (opcode2
->unit
== MU
)
1018 if (opcode1
->unit
== MU
)
1019 as_fatal (_("Two MU instructions may not be executed in parallel"));
1020 if (!flag_warn_suppress_instructionswap
)
1021 as_warn (_("Swapping instruction order"));
1022 insn
= FM00
| (insn2
<< 15) | insn1
;
1025 insn
= FM00
| (insn1
<< 15) | insn2
;
1026 check_resource_conflict (opcode1
, insn1
, opcode2
, insn2
);
1029 case PACK_LEFT_RIGHT
:
1030 if (opcode1
->unit
!= IU
)
1031 insn
= FM01
| (insn1
<< 15) | insn2
;
1032 else if (opcode2
->unit
== MU
|| opcode2
->unit
== EITHER
)
1034 if (!flag_warn_suppress_instructionswap
)
1035 as_warn (_("Swapping instruction order"));
1036 insn
= FM10
| (insn2
<< 15) | insn1
;
1039 as_fatal (_("IU instruction may not be in the left container"));
1040 if (opcode1
->exec_type
& ALONE
)
1041 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
1044 case PACK_RIGHT_LEFT
:
1045 if (opcode2
->unit
!= MU
)
1046 insn
= FM10
| (insn1
<< 15) | insn2
;
1047 else if (opcode1
->unit
== IU
|| opcode1
->unit
== EITHER
)
1049 if (!flag_warn_suppress_instructionswap
)
1050 as_warn (_("Swapping instruction order"));
1051 insn
= FM01
| (insn2
<< 15) | insn1
;
1054 as_fatal (_("MU instruction may not be in the right container"));
1055 if (opcode2
->exec_type
& ALONE
)
1056 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
1060 as_fatal (_("unknown execution type passed to write_2_short()"));
1064 dwarf2_emit_insn (4);
1065 number_to_chars_bigendian (f
, insn
, 4);
1067 /* Process fixup chains. fx refers to insn2 when j == 0, and to
1068 insn1 when j == 1. Yes, it's reversed. */
1070 for (j
= 0; j
< 2; j
++)
1072 for (i
= 0; i
< fx
->fc
; i
++)
1074 if (fx
->fix
[i
].reloc
)
1076 where
= f
- frag_now
->fr_literal
;
1077 if (fx
->fix
[i
].size
== 2)
1080 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
1081 /* A BFD_RELOC_D10V_10_PCREL_R relocation applied to
1082 the instruction in the L container has to be
1083 adjusted to BDF_RELOC_D10V_10_PCREL_L. When
1084 j==0, we're processing insn2's operands, so we
1085 want to mark the operand if insn2 is *not* in the
1086 R container. When j==1, we're processing insn1's
1087 operands, so we want to mark the operand if insn2
1088 *is* in the R container. Note that, if two
1089 instructions are identical, we're never going to
1090 swap them, so the test is safe. */
1091 && j
== ((insn
& 0x7fff) == insn2
))
1092 fx
->fix
[i
].operand
|= 1024;
1094 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
1095 fx
->fix
[i
].operand
|= 4096;
1097 fix_new_exp (frag_now
,
1102 fx
->fix
[i
].operand
|2048);
1111 /* This is the main entry point for the machine-dependent assembler.
1112 str points to a machine-dependent instruction. This function is
1113 supposed to emit the frags/bytes it assembles to. For the D10V, it
1114 mostly handles the special VLIW parsing and packing and leaves the
1115 difficult stuff to do_assemble(). */
1117 static unsigned long prev_insn
;
1118 static struct d10v_opcode
*prev_opcode
= 0;
1119 static subsegT prev_subseg
;
1120 static segT prev_seg
= 0;
1122 /* Find the symbol which has the same name as the register in exp. */
1125 find_symbol_matching_register (expressionS
*exp
)
1129 if (exp
->X_op
!= O_register
)
1132 /* Find the name of the register. */
1133 for (i
= d10v_reg_name_cnt (); i
--;)
1134 if (d10v_predefined_registers
[i
].value
== exp
->X_add_number
)
1140 /* Now see if a symbol has been defined with the same name. */
1141 return symbol_find (d10v_predefined_registers
[i
].name
);
1144 /* Get a pointer to an entry in the opcode table.
1145 The function must look at all opcodes with the same name and use
1146 the operands to choose the correct opcode. */
1148 static struct d10v_opcode
*
1149 find_opcode (struct d10v_opcode
*opcode
, expressionS myops
[])
1152 struct d10v_opcode
*next_opcode
;
1154 /* Get all the operands and save them as expressions. */
1155 get_operands (myops
);
1157 /* Now see if the operand is a fake. If so, find the correct size
1158 instruction, if possible. */
1159 if (opcode
->format
== OPCODE_FAKE
)
1161 int opnum
= opcode
->operands
[0];
1164 if (myops
[opnum
].X_op
== O_register
)
1166 myops
[opnum
].X_op
= O_symbol
;
1167 myops
[opnum
].X_add_symbol
=
1168 symbol_find_or_make ((char *) myops
[opnum
].X_op_symbol
);
1169 myops
[opnum
].X_add_number
= 0;
1170 myops
[opnum
].X_op_symbol
= NULL
;
1173 next_opcode
= opcode
+ 1;
1175 /* If the first operand is supposed to be a register, make sure
1176 we got a valid one. */
1177 flags
= d10v_operands
[next_opcode
->operands
[0]].flags
;
1178 if (flags
& OPERAND_REG
)
1180 int X_op
= myops
[0].X_op
;
1181 int num
= myops
[0].X_add_number
;
1183 if (X_op
!= O_register
1185 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1186 | OPERAND_FFLAG
| OPERAND_CFLAG
| OPERAND_CONTROL
))
1187 || ((flags
& OPERAND_SP
) && ! (num
& OPERAND_SP
)))
1189 as_bad (_("bad opcode or operands"));
1194 if (myops
[opnum
].X_op
== O_constant
1195 || (myops
[opnum
].X_op
== O_symbol
1196 && S_IS_DEFINED (myops
[opnum
].X_add_symbol
)
1197 && (S_GET_SEGMENT (myops
[opnum
].X_add_symbol
) == now_seg
)))
1199 for (i
= 0; opcode
->operands
[i
+ 1]; i
++)
1201 int bits
= d10v_operands
[next_opcode
->operands
[opnum
]].bits
;
1203 flags
= d10v_operands
[next_opcode
->operands
[opnum
]].flags
;
1205 if (flags
& OPERAND_ADDR
)
1208 if (myops
[opnum
].X_op
== O_constant
)
1210 if (!check_range (myops
[opnum
].X_add_number
, bits
, flags
))
1217 unsigned long current_position
;
1218 unsigned long symbol_position
;
1219 unsigned long value
;
1220 bfd_boolean found_symbol
;
1222 /* Calculate the address of the current instruction
1223 and the address of the symbol. Do this by summing
1224 the offsets of previous frags until we reach the
1225 frag containing the symbol, and the current frag. */
1226 sym_frag
= symbol_get_frag (myops
[opnum
].X_add_symbol
);
1227 found_symbol
= FALSE
;
1230 obstack_next_free (&frchain_now
->frch_obstack
)
1231 - frag_now
->fr_literal
;
1232 symbol_position
= S_GET_VALUE (myops
[opnum
].X_add_symbol
);
1234 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1236 current_position
+= f
->fr_fix
+ f
->fr_offset
;
1239 found_symbol
= TRUE
;
1242 symbol_position
+= f
->fr_fix
+ f
->fr_offset
;
1245 value
= symbol_position
;
1247 if (flags
& OPERAND_ADDR
)
1248 value
-= current_position
;
1250 if (AT_WORD_P (&myops
[opnum
]))
1255 if (!check_range (value
, bits
, flags
))
1259 else if (!check_range (value
, bits
, flags
))
1265 if (opcode
->operands
[i
+ 1] == 0)
1266 as_fatal (_("value out of range"));
1268 opcode
= next_opcode
;
1271 /* Not a constant, so use a long instruction. */
1277 /* Now search the opcode table table for one with operands
1278 that matches what we've got. */
1282 for (i
= 0; opcode
->operands
[i
]; i
++)
1284 int flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
1285 int X_op
= myops
[i
].X_op
;
1286 int num
= myops
[i
].X_add_number
;
1294 if (flags
& OPERAND_REG
)
1296 if ((X_op
!= O_register
)
1298 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1299 | OPERAND_FFLAG
| OPERAND_CFLAG
1301 || ((flags
& OPERAND_SP
) && ! (num
& OPERAND_SP
)))
1308 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
1309 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
1310 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
1311 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
1312 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || ((num
!= OPERAND_ATSIGN
) && (num
!= OPERAND_ATPAR
)))))
1318 /* Unfortunately, for the indirect operand in instructions such
1319 as ``ldb r1, @(c,r14)'' this function can be passed
1320 X_op == O_register (because 'c' is a valid register name).
1321 However we cannot just ignore the case when X_op == O_register
1322 but flags & OPERAND_REG is null, so we check to see if a symbol
1323 of the same name as the register exists. If the symbol does
1324 exist, then the parser was unable to distinguish the two cases
1325 and we fix things here. (Ref: PR14826) */
1327 if (!(flags
& OPERAND_REG
) && (X_op
== O_register
))
1331 sym
= find_symbol_matching_register (& myops
[i
]);
1335 myops
[i
].X_op
= X_op
= O_symbol
;
1336 myops
[i
].X_add_symbol
= sym
;
1340 (_("illegal operand - register name found where none expected"));
1344 /* We're only done if the operands matched so far AND there
1345 are no more to check. */
1346 if (match
&& myops
[i
].X_op
== 0)
1351 next_opcode
= opcode
+ 1;
1353 if (next_opcode
->opcode
== 0)
1356 if (strcmp (next_opcode
->name
, opcode
->name
))
1359 opcode
= next_opcode
;
1364 as_bad (_("bad opcode or operands"));
1368 /* Check that all registers that are required to be even are.
1369 Also, if any operands were marked as registers, but were really symbols,
1371 for (i
= 0; opcode
->operands
[i
]; i
++)
1373 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_EVEN
) &&
1374 (myops
[i
].X_add_number
& 1))
1375 as_fatal (_("Register number must be EVEN"));
1376 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_NOSP
)
1377 && (myops
[i
].X_add_number
& OPERAND_SP
))
1378 as_bad (_("Unsupported use of sp"));
1379 if (myops
[i
].X_op
== O_register
)
1381 if (!(d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_REG
))
1383 myops
[i
].X_op
= O_symbol
;
1384 myops
[i
].X_add_symbol
=
1385 symbol_find_or_make ((char *) myops
[i
].X_op_symbol
);
1386 myops
[i
].X_add_number
= 0;
1387 myops
[i
].X_op_symbol
= NULL
;
1390 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_CONTROL
)
1391 && (myops
[i
].X_add_number
== OPERAND_CONTROL
+ 4
1392 || myops
[i
].X_add_number
== OPERAND_CONTROL
+ 5
1393 || myops
[i
].X_add_number
== OPERAND_CONTROL
+ 6
1394 || myops
[i
].X_add_number
== OPERAND_CONTROL
+ 12
1395 || myops
[i
].X_add_number
== OPERAND_CONTROL
+ 13
1396 || myops
[i
].X_add_number
== OPERAND_CONTROL
+ 15))
1397 as_warn (_("cr%ld is a reserved control register"),
1398 myops
[i
].X_add_number
- OPERAND_CONTROL
);
1403 /* Assemble a single instruction.
1404 Return an opcode, or -1 (an invalid opcode) on error. */
1406 static unsigned long
1407 do_assemble (char *str
, struct d10v_opcode
**opcode
)
1409 unsigned char *op_start
, *op_end
;
1413 expressionS myops
[6];
1415 /* Drop leading whitespace. */
1419 /* Find the opcode end. */
1420 for (op_start
= op_end
= (unsigned char *) str
;
1421 *op_end
&& !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1424 name
[nlen
] = TOLOWER (op_start
[nlen
]);
1426 if (nlen
== sizeof (name
) - 1)
1434 /* Find the first opcode with the proper name. */
1435 *opcode
= (struct d10v_opcode
*) hash_find (d10v_hash
, name
);
1436 if (*opcode
== NULL
)
1439 save
= input_line_pointer
;
1440 input_line_pointer
= (char *) op_end
;
1441 *opcode
= find_opcode (*opcode
, myops
);
1444 input_line_pointer
= save
;
1446 return build_insn ((*opcode
), myops
, 0);
1449 /* If while processing a fixup, a reloc really needs to be created.
1450 Then it is done here. */
1453 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
, fixS
*fixp
)
1456 reloc
= xmalloc (sizeof (arelent
));
1457 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
1458 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1459 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1460 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1461 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1463 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1464 _("reloc %d not supported by object file format"),
1465 (int) fixp
->fx_r_type
);
1469 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1470 reloc
->address
= fixp
->fx_offset
;
1478 md_estimate_size_before_relax (fragS
*fragp ATTRIBUTE_UNUSED
,
1479 asection
*seg ATTRIBUTE_UNUSED
)
1486 md_pcrel_from_section (fixS
*fixp
, segT sec
)
1488 if (fixp
->fx_addsy
!= (symbolS
*) NULL
1489 && (!S_IS_DEFINED (fixp
->fx_addsy
)
1490 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1492 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1496 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
1504 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
1507 /* We don't actually support subtracting a symbol. */
1508 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
1509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
1511 op_type
= fixP
->fx_r_type
;
1518 fixP
->fx_r_type
= BFD_RELOC_D10V_10_PCREL_L
;
1521 else if (op_type
& 4096)
1524 fixP
->fx_r_type
= BFD_RELOC_D10V_18
;
1528 get_reloc ((struct d10v_operand
*) &d10v_operands
[op_type
]);
1531 /* Fetch the instruction, insert the fully resolved operand
1532 value, and stuff the instruction back again. */
1533 where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
1534 insn
= bfd_getb32 ((unsigned char *) where
);
1536 switch (fixP
->fx_r_type
)
1538 case BFD_RELOC_D10V_10_PCREL_L
:
1539 case BFD_RELOC_D10V_10_PCREL_R
:
1540 case BFD_RELOC_D10V_18_PCREL
:
1541 /* If the fix is relative to a global symbol, not a section
1542 symbol, then ignore the offset.
1543 XXX - Do we have to worry about branches to a symbol + offset ? */
1544 if (fixP
->fx_addsy
!= NULL
1545 && S_IS_EXTERNAL (fixP
->fx_addsy
) )
1547 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
1548 segment_info_type
*segf
= seg_info(fseg
);
1550 if ( segf
&& segf
->sym
!= fixP
->fx_addsy
)
1554 case BFD_RELOC_D10V_18
:
1555 /* Instruction addresses are always right-shifted by 2. */
1556 value
>>= AT_WORD_RIGHT_SHIFT
;
1557 if (fixP
->fx_size
== 2)
1558 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1561 struct d10v_opcode
*rep
, *repi
;
1563 rep
= (struct d10v_opcode
*) hash_find (d10v_hash
, "rep");
1564 repi
= (struct d10v_opcode
*) hash_find (d10v_hash
, "repi");
1565 if ((insn
& FM11
) == FM11
1567 && (insn
& repi
->mask
) == (unsigned) repi
->opcode
)
1569 && (insn
& rep
->mask
) == (unsigned) rep
->opcode
))
1572 (_("line %d: rep or repi must include at least 4 instructions"),
1575 d10v_insert_operand (insn
, op_type
, (offsetT
) value
, left
, fixP
);
1576 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1580 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1583 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1586 case BFD_RELOC_VTABLE_INHERIT
:
1587 case BFD_RELOC_VTABLE_ENTRY
:
1592 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1593 fixP
->fx_line
, fixP
->fx_r_type
);
1597 /* d10v_cleanup() is called after the assembler has finished parsing
1598 the input file, when a label is read from the input file, or when a
1599 stab directive is output. Because the D10V assembler sometimes
1600 saves short instructions to see if it can package them with the
1601 next instruction, there may be a short instruction that still needs
1604 NOTE: accesses a global, etype.
1605 NOTE: invoked by various macros such as md_cleanup: see. */
1613 /* If cleanup was invoked because the assembler encountered, e.g., a
1614 user label, we write out the pending instruction, if any. If it
1615 was invoked because the assembler is outputting a piece of line
1616 debugging information, though, we write out the pending
1617 instruction only if the --no-gstabs-packing command line switch
1618 has been specified. */
1620 && etype
== PACK_UNSPEC
1621 && (! outputting_stabs_line_debug
|| ! flag_allow_gstabs_packing
))
1624 subseg
= now_subseg
;
1627 subseg_set (prev_seg
, prev_subseg
);
1629 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
1630 subseg_set (seg
, subseg
);
1637 d10v_frob_label (symbolS
*lab
)
1640 symbol_set_frag (lab
, frag_now
);
1641 S_SET_VALUE (lab
, (valueT
) frag_now_fix ());
1642 dwarf2_emit_label (lab
);
1645 /* Like normal .word, except support @word.
1646 Clobbers input_line_pointer, checks end-of-line. */
1649 d10v_dot_word (int dummy ATTRIBUTE_UNUSED
)
1654 if (is_it_end_of_statement ())
1656 demand_empty_rest_of_line ();
1663 if (!strncasecmp (input_line_pointer
, "@word", 5))
1665 exp
.X_add_number
= 0;
1666 input_line_pointer
+= 5;
1669 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
1670 &exp
, 0, BFD_RELOC_D10V_18
);
1673 emit_expr (&exp
, 2);
1675 while (*input_line_pointer
++ == ',');
1677 input_line_pointer
--; /* Put terminator back into stream. */
1678 demand_empty_rest_of_line ();
1681 /* Mitsubishi asked that we support some old syntax that apparently
1682 had immediate operands starting with '#'. This is in some of their
1683 sample code but is not documented (although it appears in some
1684 examples in their assembler manual). For now, we'll solve this
1685 compatibility problem by simply ignoring any '#' at the beginning
1688 /* Operands that begin with '#' should fall through to here.
1692 md_operand (expressionS
*expressionP
)
1694 if (*input_line_pointer
== '#' && ! do_not_ignore_hash
)
1696 input_line_pointer
++;
1697 expression (expressionP
);
1702 d10v_fix_adjustable (fixS
*fixP
)
1704 /* We need the symbol name for the VTABLE entries. */
1705 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1706 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1712 /* The target specific pseudo-ops which we support. */
1713 const pseudo_typeS md_pseudo_table
[] =
1715 { "word", d10v_dot_word
, 2 },
1720 md_assemble (char *str
)
1722 /* etype is saved extype. For multi-line instructions. */
1723 packing_type extype
= PACK_UNSPEC
; /* Parallel, etc. */
1724 struct d10v_opcode
*opcode
;
1728 if (etype
== PACK_UNSPEC
)
1730 /* Look for the special multiple instruction separators. */
1731 str2
= strstr (str
, "||");
1733 extype
= PACK_PARALLEL
;
1736 str2
= strstr (str
, "->");
1738 extype
= PACK_LEFT_RIGHT
;
1741 str2
= strstr (str
, "<-");
1743 extype
= PACK_RIGHT_LEFT
;
1747 /* str2 points to the separator, if there is one. */
1752 /* If two instructions are present and we already have one saved,
1753 then first write out the saved one. */
1756 /* Assemble first instruction and save it. */
1757 prev_insn
= do_assemble (str
, &prev_opcode
);
1759 prev_subseg
= now_subseg
;
1760 if (prev_insn
== (unsigned long) -1)
1761 as_fatal (_("can't find previous opcode "));
1762 fixups
= fixups
->next
;
1767 insn
= do_assemble (str
, &opcode
);
1768 if (insn
== (unsigned long) -1)
1770 if (extype
!= PACK_UNSPEC
)
1773 as_bad (_("could not assemble: %s"), str
);
1777 if (etype
!= PACK_UNSPEC
)
1780 etype
= PACK_UNSPEC
;
1783 /* If this is a long instruction, write it and any previous short
1785 if (opcode
->format
& LONG_OPCODE
)
1787 if (extype
!= PACK_UNSPEC
)
1788 as_fatal (_("Unable to mix instructions as specified"));
1790 write_long (insn
, fixups
);
1797 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1801 && (0 == write_2_short (prev_opcode
, prev_insn
, opcode
, insn
, extype
,
1804 /* No instructions saved. */
1809 if (extype
!= PACK_UNSPEC
)
1810 as_fatal (_("Unable to mix instructions as specified"));
1811 /* Save last instruction so it may be packed on next pass. */
1812 prev_opcode
= opcode
;
1815 prev_subseg
= now_subseg
;
1816 fixups
= fixups
->next
;