1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
3 Copyright (C) 1996 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d10v.h"
29 const char comment_chars
[] = "#;";
30 const char line_comment_chars
[] = "#";
31 const char line_separator_chars
[] = "";
32 const char *md_shortopts
= "";
33 const char EXP_CHARS
[] = "eE";
34 const char FLT_CHARS
[] = "dD";
38 #define MAX_INSN_FIXUPS (5)
42 bfd_reloc_code_real_type reloc
;
45 typedef struct _fixups
48 struct d10v_fixup fix
[MAX_INSN_FIXUPS
];
52 static Fixups FixUps
[2];
53 static Fixups
*fixups
;
56 static int reg_name_search
PARAMS ((char *name
));
57 static int register_name
PARAMS ((expressionS
*expressionP
));
58 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
59 static int postfix
PARAMS ((char *p
));
60 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d10v_operand
*op
));
61 static int get_operands
PARAMS ((expressionS exp
[]));
62 static unsigned long build_insn
PARAMS ((struct d10v_opcode
*opcode
, expressionS
*opers
, unsigned long insn
));
63 static void write_long
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
64 static void write_1_short
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
65 static int write_2_short
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
66 struct d10v_opcode
*opcode2
, unsigned long insn2
, int exec_type
, Fixups
*fx
));
67 static unsigned long do_assemble
PARAMS ((char *str
, struct d10v_opcode
**opcode
));
68 static unsigned long d10v_insert_operand
PARAMS (( unsigned long insn
, int op_type
,
69 offsetT value
, int left
));
72 struct option md_longopts
[] = {
73 {NULL
, no_argument
, NULL
, 0}
75 size_t md_longopts_size
= sizeof(md_longopts
);
77 /* The target specific pseudo-ops which we support. */
78 const pseudo_typeS md_pseudo_table
[] =
83 /* Opcode hash table. */
84 static struct hash_control
*d10v_hash
;
86 /* reg_name_search does a binary search of the pre_defined_registers
87 array to see if "name" is a valid regiter name. Returns the register
88 number from the array on success, or -1 on failure. */
91 reg_name_search (name
)
94 int middle
, low
, high
;
98 high
= reg_name_cnt() - 1;
102 middle
= (low
+ high
) / 2;
103 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
109 return pre_defined_registers
[middle
].value
;
115 /* register_name() checks the string at input_line_pointer
116 to see if it is a valid register name */
119 register_name (expressionP
)
120 expressionS
*expressionP
;
123 char c
, *p
= input_line_pointer
;
125 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
132 /* look to see if it's in the register table */
133 reg_number
= reg_name_search (input_line_pointer
);
136 expressionP
->X_op
= O_register
;
137 /* temporarily store a pointer to the string here */
138 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
139 expressionP
->X_add_number
= reg_number
;
140 input_line_pointer
= p
;
150 check_range (num
, bits
, flags
)
158 /* don't bother checking 16-bit values */
162 if (flags
& OPERAND_SHIFT
)
164 /* all special shift operands are unsigned */
165 /* and <= 16. We allow 0 for now. */
172 if (flags
& OPERAND_SIGNED
)
174 max
= (1 << (bits
- 1))-1;
175 min
= - (1 << (bits
- 1));
176 if (((long)num
> max
) || ((long)num
< min
))
181 max
= (1 << bits
) - 1;
183 if ((num
> max
) || (num
< min
))
191 md_show_usage (stream
)
194 fprintf(stream
, "D10V options:\n\
199 md_parse_option (c
, arg
)
207 md_undefined_symbol (name
)
214 md_atof (type
, litp
, sizep
)
223 md_convert_frag (abfd
, sec
, fragP
)
228 printf ("call to md_convert_frag \n");
233 md_section_align (seg
, addr
)
237 int align
= bfd_get_section_alignment (stdoutput
, seg
);
238 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
245 char *prev_name
= "";
246 struct d10v_opcode
*opcode
;
247 d10v_hash
= hash_new();
249 /* Insert unique names into hash table. The D10v instruction set
250 has many identical opcode names that have different opcodes based
251 on the operands. This hash table then provides a quick index to
252 the first opcode with a particular name in the opcode table. */
254 for (opcode
= (struct d10v_opcode
*)d10v_opcodes
; opcode
->name
; opcode
++)
256 if (strcmp (prev_name
, opcode
->name
))
258 prev_name
= (char *)opcode
->name
;
259 hash_insert (d10v_hash
, opcode
->name
, (char *) opcode
);
264 FixUps
[0].next
= &FixUps
[1];
265 FixUps
[1].next
= &FixUps
[0];
269 /* this function removes the postincrement or postdecrement
270 operator ( '+' or '-' ) from an expression */
272 static int postfix (p
)
275 while (*p
!= '-' && *p
!= '+')
277 if (*p
==0 || *p
=='\n' || *p
=='\r')
297 static bfd_reloc_code_real_type
299 struct d10v_operand
*op
;
303 /* printf("get_reloc: bits=%d address=%d\n",bits,op->flags & OPERAND_ADDR); */
307 if (op
->flags
& OPERAND_ADDR
)
310 return (BFD_RELOC_D10V_10_PCREL_R
);
312 return (BFD_RELOC_D10V_18_PCREL
);
315 return (BFD_RELOC_16
);
318 /* get_operands parses a string of operands and returns
319 an array of expressions */
325 char *p
= input_line_pointer
;
331 while (*p
== ' ' || *p
== '\t' || *p
== ',')
333 if (*p
==0 || *p
=='\n' || *p
=='\r')
339 exp
[numops
].X_op
= O_absent
;
343 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
348 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
352 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
361 /* just skip the trailing paren */
366 input_line_pointer
= p
;
369 /* check to see if it might be a register name */
370 if (!register_name (&exp
[numops
]))
372 /* parse as an expression */
373 expression (&exp
[numops
]);
376 if (exp
[numops
].X_op
== O_illegal
)
377 as_bad ("illegal operand");
378 else if (exp
[numops
].X_op
== O_absent
)
379 as_bad ("missing operand");
382 p
= input_line_pointer
;
387 case -1: /* postdecrement mode */
388 exp
[numops
].X_op
= O_absent
;
389 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
391 case 1: /* postincrement mode */
392 exp
[numops
].X_op
= O_absent
;
393 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
397 exp
[numops
].X_op
= 0;
402 d10v_insert_operand (insn
, op_type
, value
, left
)
410 shift
= d10v_operands
[op_type
].shift
;
414 bits
= d10v_operands
[op_type
].bits
;
416 /* truncate to the proper number of bits */
417 if (check_range (value
, bits
, d10v_operands
[op_type
].flags
))
418 as_bad("operand out of range: %d",value
);
420 value
&= 0x7FFFFFFF >> (31 - bits
);
421 insn
|= (value
<< shift
);
427 /* build_insn takes a pointer to the opcode entry in the opcode table
428 and the array of operand expressions and returns the instruction */
431 build_insn (opcode
, opers
, insn
)
432 struct d10v_opcode
*opcode
;
436 int i
, bits
, shift
, flags
, format
;
439 /* the insn argument is only used for the DIVS kludge */
444 insn
= opcode
->opcode
;
445 format
= opcode
->format
;
448 for (i
=0;opcode
->operands
[i
];i
++)
450 flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
451 bits
= d10v_operands
[opcode
->operands
[i
]].bits
;
452 shift
= d10v_operands
[opcode
->operands
[i
]].shift
;
453 number
= opers
[i
].X_add_number
;
455 if (flags
& OPERAND_REG
)
457 number
&= REGISTER_MASK
;
458 if (format
== LONG_L
)
462 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
)
464 /* now create a fixup */
467 printf("need a fixup: ");
468 print_expr_1(stdout,&opers[i]);
472 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
473 as_fatal ("too many fixups");
474 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
476 /* put the operand number here for now. We can look up
477 the reloc type and/or fixup the instruction in md_apply_fix() */
478 fixups
->fix
[fixups
->fc
].reloc
= opcode
->operands
[i
];
482 /* truncate to the proper number of bits */
483 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
484 as_bad("operand out of range: %d",number
);
485 number
&= 0x7FFFFFFF >> (31 - bits
);
486 insn
= insn
| (number
<< shift
);
489 /* kludge: for DIVS, we need to put the operands in twice */
490 /* on the second pass, format is changed to LONG_R to force */
491 /* the second set of operands to not be shifted over 15 */
492 if ((opcode
->opcode
== OPCODE_DIVS
) && (format
==LONG_L
))
493 insn
= build_insn (opcode
, opers
, insn
);
498 /* write out a long form instruction */
500 write_long (opcode
, insn
, fx
)
501 struct d10v_opcode
*opcode
;
506 char *f
= frag_more(4);
509 /* printf("INSN: %08x\n",insn); */
510 number_to_chars_bigendian (f
, insn
, 4);
512 for (i
=0; i
< fx
->fc
; i
++)
514 if (get_reloc((struct d10v_operand
*)&d10v_operands
[fx
->fix
[i
].reloc
]))
517 printf("fix_new_exp: where:%x size:4\n ",f - frag_now->fr_literal);
518 print_expr_1(stdout,&(fx->fix[i].exp));
522 fix_new_exp (frag_now
,
523 f
- frag_now
->fr_literal
,
534 /* write out a short form instruction by itself */
536 write_1_short (opcode
, insn
, fx
)
537 struct d10v_opcode
*opcode
;
541 char *f
= frag_more(4);
544 if (opcode
->exec_type
== PARONLY
)
545 as_fatal ("Instruction must be executed in parallel with another instruction.");
547 /* the other container needs to be NOP */
548 /* according to 4.3.1: for FM=00, sub-instructions performed only
549 by IU cannot be encoded in L-container. */
550 if (opcode
->unit
== IU
)
551 insn
|= FM00
| (NOP
<< 15); /* right container */
553 insn
= FM00
| (insn
<< 15) | NOP
; /* left container */
555 /* printf("INSN: %08x\n",insn); */
556 number_to_chars_bigendian (f
, insn
, 4);
557 for (i
=0; i
< fx
->fc
; i
++)
559 bfd_reloc_code_real_type reloc
;
560 reloc
= get_reloc((struct d10v_operand
*)&d10v_operands
[fx
->fix
[i
].reloc
]);
564 printf("fix_new_exp: where:%x size:4\n ",f - frag_now->fr_literal);
565 print_expr_1(stdout,&(fx->fix[i].exp));
569 /* if it's an R reloc, we may have to switch it to L */
570 if ( (reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (opcode
->unit
!= IU
) )
571 fx
->fix
[i
].reloc
|= 1024;
573 fix_new_exp (frag_now
,
574 f
- frag_now
->fr_literal
,
584 /* write out a short form instruction if possible */
585 /* return number of instructions not written out */
587 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
588 struct d10v_opcode
*opcode1
, *opcode2
;
589 unsigned long insn1
, insn2
;
597 if ( (exec_type
!= 1) && ((opcode1
->exec_type
== PARONLY
)
598 || (opcode2
->exec_type
== PARONLY
)))
599 as_fatal("Instruction must be executed in parallel");
601 if ( (opcode1
->format
& LONG_OPCODE
) || (opcode2
->format
& LONG_OPCODE
))
602 as_fatal ("Long instructions may not be combined.");
604 if(opcode1
->exec_type
== BRANCH_LINK
)
606 /* subroutines must be called from 32-bit boundaries */
607 /* so the return address will be correct */
608 write_1_short (opcode1
, insn1
, fx
->next
);
615 if (opcode1
->unit
== IU
)
617 /* reverse sequential */
618 insn
= FM10
| (insn2
<< 15) | insn1
;
622 insn
= FM01
| (insn1
<< 15) | insn2
;
626 case 1: /* parallel */
627 if (opcode1
->exec_type
== SEQ
|| opcode2
->exec_type
== SEQ
)
628 as_fatal ("One of these instructions may not be executed in parallel.");
630 if (opcode1
->unit
== IU
)
632 if (opcode2
->unit
== IU
)
633 as_fatal ("Two IU instructions may not be executed in parallel");
634 as_warn ("Swapping instruction order");
635 insn
= FM00
| (insn2
<< 15) | insn1
;
638 else if (opcode2
->unit
== MU
)
640 if (opcode1
->unit
== MU
)
641 as_fatal ("Two MU instructions may not be executed in parallel");
642 as_warn ("Swapping instruction order");
643 insn
= FM00
| (insn2
<< 15) | insn1
;
647 insn
= FM00
| (insn1
<< 15) | insn2
;
650 case 2: /* sequential */
651 if (opcode1
->unit
== IU
)
652 as_fatal ("IU instruction may not be in the left container");
653 insn
= FM01
| (insn1
<< 15) | insn2
;
656 case 3: /* reverse sequential */
657 if (opcode2
->unit
== MU
)
658 as_fatal ("MU instruction may not be in the right container");
659 insn
= FM10
| (insn1
<< 15) | insn2
;
662 as_fatal("unknown execution type passed to write_2_short()");
665 /* printf("INSN: %08x\n",insn); */
667 number_to_chars_bigendian (f
, insn
, 4);
671 bfd_reloc_code_real_type reloc
;
672 for (i
=0; i
< fx
->fc
; i
++)
674 reloc
= get_reloc((struct d10v_operand
*)&d10v_operands
[fx
->fix
[i
].reloc
]);
677 if ( (reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (j
== 0) )
678 fx
->fix
[i
].reloc
|= 1024;
681 printf("fix_new_exp: where:%x reloc:%d\n ",f - frag_now->fr_literal,fx->fix[i].reloc);
682 print_expr_1(stdout,&(fx->fix[i].exp));
685 fix_new_exp (frag_now
,
686 f
- frag_now
->fr_literal
,
701 /* This is the main entry point for the machine-dependent assembler. str points to a
702 machine-dependent instruction. This function is supposed to emit the frags/bytes
703 it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing
704 and leaves the difficult stuff to do_assemble().
707 static unsigned long prev_insn
;
708 static struct d10v_opcode
*prev_opcode
= 0;
709 static subsegT prev_subseg
;
710 static segT prev_seg
;
716 struct d10v_opcode
*opcode
;
718 int extype
=0; /* execution type; parallel, etc */
719 static int etype
=0; /* saved extype. used for multiline instructions */
722 /* printf("md_assemble: str=%s\n",str); */
726 /* look for the special multiple instruction separators */
727 str2
= strstr (str
, "||");
732 str2
= strstr (str
, "->");
737 str2
= strstr (str
, "<-");
742 /* str2 points to the separator, if one */
747 /* if two instructions are present and we already have one saved
748 then first write it out */
750 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
752 /* assemble first instruction and save it */
753 prev_insn
= do_assemble (str
, &prev_opcode
);
755 as_fatal ("can't find opcode ");
756 fixups
= fixups
->next
;
761 insn
= do_assemble (str
, &opcode
);
769 as_fatal ("can't find opcode ");
778 /* if this is a long instruction, write it and any previous short instruction */
779 if (opcode
->format
& LONG_OPCODE
)
782 as_fatal("Unable to mix instructions as specified");
785 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
788 write_long (opcode
, insn
, fixups
);
793 if (prev_opcode
&& (write_2_short (prev_opcode
, prev_insn
, opcode
, insn
, extype
, fixups
) == 0))
795 /* no instructions saved */
801 as_fatal("Unable to mix instructions as specified");
802 /* save off last instruction so it may be packed on next pass */
803 prev_opcode
= opcode
;
806 prev_subseg
= now_subseg
;
807 fixups
= fixups
->next
;
812 /* do_assemble assembles a single instruction and returns an opcode */
813 /* it returns -1 (an invalid opcode) on error */
816 do_assemble (str
, opcode
)
818 struct d10v_opcode
**opcode
;
820 struct d10v_opcode
*next_opcode
;
821 unsigned char *op_start
, *save
;
822 unsigned char *op_end
;
824 int nlen
= 0, i
, match
, numops
;
825 expressionS myops
[6];
828 /* printf("do_assemble: str=%s\n",str); */
830 /* Drop leading whitespace */
834 /* find the opcode end */
835 for (op_start
= op_end
= (unsigned char *) (str
);
838 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
841 name
[nlen
] = op_start
[nlen
];
849 /* find the first opcode with the proper name */
850 *opcode
= (struct d10v_opcode
*)hash_find (d10v_hash
, name
);
852 as_fatal ("unknown opcode: %s",name
);
854 save
= input_line_pointer
;
855 input_line_pointer
= op_end
;
857 /* get all the operands and save them as expressions */
858 numops
= get_operands (myops
);
860 /* now see if the operand is a fake. If so, find the correct size */
861 /* instruction, if possible */
863 if ((*opcode
)->format
== OPCODE_FAKE
)
865 int opnum
= (*opcode
)->operands
[0];
866 if (myops
[opnum
].X_op
== O_constant
)
868 next_opcode
=(*opcode
)+1;
869 for (i
=0; (*opcode
)->operands
[i
+1]; i
++)
871 int bits
= d10v_operands
[next_opcode
->operands
[opnum
]].bits
;
872 int flags
= d10v_operands
[next_opcode
->operands
[opnum
]].flags
;
873 if (!check_range (myops
[opnum
].X_add_number
, bits
, flags
))
883 /* not a constant, so use a long instruction */
884 next_opcode
= (*opcode
)+2;
888 *opcode
= next_opcode
;
890 as_fatal ("value out of range");
894 /* now search the opcode table table for one with operands */
895 /* that matches what we've got */
899 for (i
= 0; (*opcode
)->operands
[i
]; i
++)
901 int flags
= d10v_operands
[(*opcode
)->operands
[i
]].flags
;
902 int X_op
= myops
[i
].X_op
;
903 int num
= myops
[i
].X_add_number
;
911 if (flags
& OPERAND_REG
)
913 if ((X_op
!= O_register
) ||
914 ((flags
& OPERAND_ACC
) != (num
& OPERAND_ACC
)) ||
915 ((flags
& OPERAND_FLAG
) != (num
& OPERAND_FLAG
)) ||
916 ((flags
& OPERAND_CONTROL
) != (num
& OPERAND_CONTROL
)))
923 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
924 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
925 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
926 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
927 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATSIGN
))))
935 /* we're only done if the operands matched AND there
936 are no more to check */
937 if (match
&& myops
[i
].X_op
==0)
940 next_opcode
= (*opcode
)+1;
941 if (next_opcode
->opcode
== 0)
943 if (strcmp(next_opcode
->name
, (*opcode
)->name
))
945 (*opcode
) = next_opcode
;
951 as_bad ("bad opcode or operands");
955 /* Check that all registers that are required to be even are. */
956 /* Also, if any operands were marked as registers, but were really symbols */
958 for (i
=0; (*opcode
)->operands
[i
]; i
++)
960 if ((d10v_operands
[(*opcode
)->operands
[i
]].flags
& OPERAND_EVEN
) &&
961 (myops
[i
].X_add_number
& 1))
962 as_fatal("Register number must be EVEN");
963 if (myops
[i
].X_op
== O_register
)
965 if (!(d10v_operands
[(*opcode
)->operands
[i
]].flags
& OPERAND_REG
))
967 myops
[i
].X_op
= O_symbol
;
968 myops
[i
].X_add_symbol
= symbol_find_or_make ((char *)myops
[i
].X_op_symbol
);
969 myops
[i
].X_add_number
= 0;
970 myops
[i
].X_op_symbol
= NULL
;
975 input_line_pointer
= save
;
977 /* at this point, we have "opcode" pointing to the opcode entry in the
978 d10v opcode table, with myops filled out with the operands. */
979 insn
= build_insn ((*opcode
), myops
, 0);
980 /* printf("sub-insn = %lx\n",insn); */
986 /* if while processing a fixup, a reloc really needs to be created */
987 /* then it is done here */
990 tc_gen_reloc (seg
, fixp
)
995 reloc
= (arelent
*) bfd_alloc_by_size_t (stdoutput
, sizeof (arelent
));
996 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
997 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
998 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
999 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1001 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1002 "reloc %d not supported by object file format", (int)fixp
->fx_r_type
);
1005 reloc
->addend
= fixp
->fx_addnumber
;
1006 /* printf("tc_gen_reloc: addr=%x addend=%x\n", reloc->address, reloc->addend); */
1011 md_estimate_size_before_relax (fragp
, seg
)
1020 md_pcrel_from_section (fixp
, sec
)
1025 /* return fixp->fx_frag->fr_address + fixp->fx_where; */
1029 md_apply_fix3 (fixp
, valuep
, seg
)
1040 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1045 else if (fixp
->fx_pcrel
)
1049 value
= fixp
->fx_offset
;
1050 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1052 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1053 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1056 /* We don't actually support subtracting a symbol. */
1057 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1058 "expression too complex");
1063 /* printf("md_apply_fix: value=0x%x type=%d\n", value, fixp->fx_r_type); */
1065 op_type
= fixp
->fx_r_type
;
1069 fixp
->fx_r_type
= BFD_RELOC_D10V_10_PCREL_L
;
1073 fixp
->fx_r_type
= get_reloc((struct d10v_operand
*)&d10v_operands
[op_type
]);
1075 /* Fetch the instruction, insert the fully resolved operand
1076 value, and stuff the instruction back again. */
1077 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1078 insn
= bfd_getb32 ((unsigned char *) where
);
1080 switch (fixp
->fx_r_type
)
1082 case BFD_RELOC_D10V_10_PCREL_L
:
1083 case BFD_RELOC_D10V_10_PCREL_R
:
1084 case BFD_RELOC_D10V_18_PCREL
:
1085 /* instruction addresses are always right-shifted by 2
1087 if (!fixp
->fx_pcrel
)
1088 value
-= fixp
->fx_where
;
1093 /* printf(" insn=%x value=%x where=%x pcrel=%x\n",insn,value,fixp->fx_where,fixp->fx_pcrel); */
1095 insn
= d10v_insert_operand (insn
, op_type
, (offsetT
)value
, left
);
1097 /* printf(" new insn=%x\n",insn); */
1099 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1104 fixp
->fx_addnumber
= value
;
1109 /* d10v_cleanup() is called after the assembler has finished parsing the input
1110 file or after a label is defined. Because the D10V assembler sometimes saves short
1111 instructions to see if it can package them with the next instruction, there may
1112 be a short instruction that still needs written. */
1120 if ( prev_opcode
&& (done
|| (now_seg
== prev_seg
) && (now_subseg
== prev_subseg
)))
1123 subseg
= now_subseg
;
1124 subseg_set (prev_seg
, prev_subseg
);
1125 write_1_short (prev_opcode
, prev_insn
, fixups
);
1126 subseg_set (seg
, subseg
);