1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
2 Copyright (C) 1997, 1998, 1999, 2000 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
25 #include "opcode/d30v.h"
27 const char comment_chars
[] = ";";
28 const char line_comment_chars
[] = "#";
29 const char line_separator_chars
[] = "";
30 const char *md_shortopts
= "OnNcC";
31 const char EXP_CHARS
[] = "eE";
32 const char FLT_CHARS
[] = "dD";
42 #define NOP_MULTIPLY 1
44 static int warn_nops
= 0;
45 static int Optimizing
= 0;
46 static int warn_register_name_conflicts
= 1;
52 typedef enum _exec_type
54 EXEC_UNKNOWN
, /* no order specified */
55 EXEC_PARALLEL
, /* done in parallel (FM=00) */
56 EXEC_SEQ
, /* sequential (FM=01) */
57 EXEC_REVSEQ
/* reverse sequential (FM=10) */
61 #define MAX_INSN_FIXUPS (5)
68 bfd_reloc_code_real_type reloc
;
71 typedef struct _fixups
74 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
78 static Fixups FixUps
[2];
79 static Fixups
*fixups
;
81 /* Whether current and previous instruction are word multiply insns. */
82 static int cur_mul32_p
= 0;
83 static int prev_mul32_p
= 0;
85 /* The flag_explicitly_parallel is true iff the instruction being assembled
86 has been explicitly written as a parallel short-instruction pair by the
87 human programmer. It is used in parallel_ok() to distinguish between
88 those dangerous parallelizations attempted by the human, which are to be
89 allowed, and those attempted by the assembler, which are not. It is set
90 from md_assemble(). */
91 static int flag_explicitly_parallel
= 0;
92 static int flag_xp_state
= 0;
94 /* Whether current and previous left sub-instruction disables
95 execution of right sub-instruction. */
96 static int cur_left_kills_right_p
= 0;
97 static int prev_left_kills_right_p
= 0;
99 /* The known current alignment of the current section. */
100 static int d30v_current_align
;
101 static segT d30v_current_align_seg
;
103 /* The last seen label in the current section. This is used to auto-align
104 labels preceeding instructions. */
105 static symbolS
*d30v_last_label
;
108 #define NOP_LEFT ((long long) NOP << 32)
109 #define NOP_RIGHT ((long long) NOP)
110 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
112 /* local functions */
113 static int reg_name_search
PARAMS ((char *name
));
114 static int register_name
PARAMS ((expressionS
*expressionP
));
115 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
116 static int postfix
PARAMS ((char *p
));
117 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
118 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
119 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
,
120 expressionS ops
[],int fsize
, int cmp_hack
));
121 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
122 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
123 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
,
124 Fixups
*fx
, int use_sequential
));
125 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
126 struct d30v_insn
*opcode2
, long long insn2
, exec_type_enum exec_type
, Fixups
*fx
));
127 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
,
128 int shortp
, int is_parallel
));
129 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
130 struct d30v_insn
*opcode2
, unsigned long insn2
,
131 exec_type_enum exec_type
));
132 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
133 static void check_size
PARAMS ((long value
, int bits
, char *file
, int line
));
134 static void d30v_align
PARAMS ((int, char *, symbolS
*));
135 static void s_d30v_align
PARAMS ((int));
136 static void s_d30v_text
PARAMS ((int));
137 static void s_d30v_data
PARAMS ((int));
138 static void s_d30v_section
PARAMS ((int));
140 struct option md_longopts
[] = {
141 {NULL
, no_argument
, NULL
, 0}
143 size_t md_longopts_size
= sizeof(md_longopts
);
146 /* The target specific pseudo-ops which we support. */
147 const pseudo_typeS md_pseudo_table
[] =
150 { "hword", cons
, 2 },
151 { "align", s_d30v_align
, 0 },
152 { "text", s_d30v_text
, 0 },
153 { "data", s_d30v_data
, 0 },
154 { "section", s_d30v_section
, 0 },
155 { "section.s", s_d30v_section
, 0 },
156 { "sect", s_d30v_section
, 0 },
157 { "sect.s", s_d30v_section
, 0 },
161 /* Opcode hash table. */
162 static struct hash_control
*d30v_hash
;
164 /* reg_name_search does a binary search of the pre_defined_registers
165 array to see if "name" is a valid regiter name. Returns the register
166 number from the array on success, or -1 on failure. */
169 reg_name_search (name
)
172 int middle
, low
, high
;
176 high
= reg_name_cnt () - 1;
180 middle
= (low
+ high
) / 2;
181 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
188 if (symbol_find (name
) != NULL
)
190 if (warn_register_name_conflicts
)
191 as_warn (_("Register name %s conflicts with symbol of the same name"),
195 return pre_defined_registers
[middle
].value
;
203 /* register_name() checks the string at input_line_pointer
204 to see if it is a valid register name. */
207 register_name (expressionP
)
208 expressionS
*expressionP
;
211 char c
, *p
= input_line_pointer
;
213 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
220 /* look to see if it's in the register table */
221 reg_number
= reg_name_search (input_line_pointer
);
224 expressionP
->X_op
= O_register
;
225 /* temporarily store a pointer to the string here */
226 expressionP
->X_op_symbol
= (symbolS
*)input_line_pointer
;
227 expressionP
->X_add_number
= reg_number
;
228 input_line_pointer
= p
;
238 check_range (num
, bits
, flags
)
245 /* Don't bother checking 32-bit values. */
248 if (sizeof(unsigned long) * CHAR_BIT
== 32)
251 /* We don't record signed or unsigned for 32-bit quantities.
253 min
= -((unsigned long)1 << (bits
- 1));
254 max
= ((unsigned long)1 << bits
) - 1;
255 return (long)num
< min
|| (long)num
> max
;
258 if (flags
& OPERAND_SHIFT
)
260 /* We know that all shifts are right by three bits.... */
262 if (flags
& OPERAND_SIGNED
)
263 num
= (unsigned long) ( (long) num
>= 0)
264 ? ( ((long) num
) >> 3 )
265 : ( (num
>> 3) | ~(~(unsigned long)0 >> 3) );
270 if (flags
& OPERAND_SIGNED
)
272 max
= ((unsigned long)1 << (bits
- 1)) - 1;
273 min
= - ((unsigned long)1 << (bits
- 1));
274 return (long)num
> max
|| (long)num
< min
;
278 max
= ((unsigned long)1 << bits
) - 1;
280 return num
> max
|| num
< min
;
286 md_show_usage (stream
)
289 fprintf (stream
, _("\nD30V options:\n\
290 -O Make adjacent short instructions parallel if possible.\n\
291 -n Warn about all NOPs inserted by the assembler.\n\
292 -N Warn about NOPs inserted after word multiplies.\n\
293 -c Warn about symbols whoes names match register names.\n\
294 -C Opposite of -C. -c is the default.\n"));
298 md_parse_option (c
, arg
)
304 /* Optimize. Will attempt to parallelize operations */
309 /* Warn about all NOPS that the assembler inserts. */
314 /* Warn about the NOPS that the assembler inserts because of the
317 warn_nops
= NOP_MULTIPLY
;
321 warn_register_name_conflicts
= 1;
325 warn_register_name_conflicts
= 0;
335 md_undefined_symbol (name
)
341 /* Turn a string in input_line_pointer into a floating point constant of type
342 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
343 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
346 md_atof (type
, litP
, sizeP
)
352 LITTLENUM_TYPE words
[4];
366 return _("bad call to md_atof");
369 t
= atof_ieee (input_line_pointer
, type
, words
);
371 input_line_pointer
= t
;
375 for (i
= 0; i
< prec
; i
++)
377 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
384 md_convert_frag (abfd
, sec
, fragP
)
393 md_section_align (seg
, addr
)
397 int align
= bfd_get_section_alignment (stdoutput
, seg
);
398 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
405 struct d30v_opcode
* opcode
;
406 d30v_hash
= hash_new ();
408 /* Insert opcode names into a hash table. */
409 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
410 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
413 FixUps
[0].next
= &FixUps
[1];
414 FixUps
[1].next
= &FixUps
[0];
416 d30v_current_align_seg
= now_seg
;
420 /* this function removes the postincrement or postdecrement
421 operator ( '+' or '-' ) from an expression */
423 static int postfix (p
)
426 while (*p
!= '-' && *p
!= '+')
428 if (*p
==0 || *p
=='\n' || *p
=='\r' || *p
==' ' || *p
==',')
448 static bfd_reloc_code_real_type
449 get_reloc (op
, rel_flag
)
450 struct d30v_operand
*op
;
456 if (op
->flags
& OPERAND_SHIFT
)
457 return BFD_RELOC_D30V_9_PCREL
;
459 return BFD_RELOC_D30V_6
;
462 if (!(op
->flags
& OPERAND_SHIFT
))
463 as_warn (_("unexpected 12-bit reloc type"));
464 if (rel_flag
== RELOC_PCREL
)
465 return BFD_RELOC_D30V_15_PCREL
;
467 return BFD_RELOC_D30V_15
;
469 if (!(op
->flags
& OPERAND_SHIFT
))
470 as_warn (_("unexpected 18-bit reloc type"));
471 if (rel_flag
== RELOC_PCREL
)
472 return BFD_RELOC_D30V_21_PCREL
;
474 return BFD_RELOC_D30V_21
;
476 if (rel_flag
== RELOC_PCREL
)
477 return BFD_RELOC_D30V_32_PCREL
;
479 return BFD_RELOC_D30V_32
;
485 /* get_operands parses a string of operands and returns
486 an array of expressions */
489 get_operands (exp
, cmp_hack
)
493 char *p
= input_line_pointer
;
499 exp
[numops
].X_op
= O_absent
;
500 exp
[numops
++].X_add_number
= cmp_hack
- 1;
505 while (*p
== ' ' || *p
== '\t' || *p
== ',')
507 if (*p
==0 || *p
=='\n' || *p
=='\r')
513 exp
[numops
].X_op
= O_absent
;
517 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
523 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
527 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
536 /* just skip the trailing paren */
541 input_line_pointer
= p
;
543 /* check to see if it might be a register name */
544 if (!register_name (&exp
[numops
]))
546 /* parse as an expression */
547 expression (&exp
[numops
]);
550 if (exp
[numops
].X_op
== O_illegal
)
551 as_bad (_("illegal operand"));
552 else if (exp
[numops
].X_op
== O_absent
)
553 as_bad (_("missing operand"));
556 p
= input_line_pointer
;
560 case -1: /* postdecrement mode */
561 exp
[numops
].X_op
= O_absent
;
562 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
564 case 1: /* postincrement mode */
565 exp
[numops
].X_op
= O_absent
;
566 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
572 exp
[numops
].X_op
= 0;
576 /* build_insn generates the instruction. It does everything */
577 /* but write the FM bits. */
580 build_insn (opcode
, opers
)
581 struct d30v_insn
*opcode
;
584 int i
, length
, bits
, shift
, flags
;
585 unsigned long number
, id
=0;
587 struct d30v_opcode
*op
= opcode
->op
;
588 struct d30v_format
*form
= opcode
->form
;
590 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
592 for (i
=0; form
->operands
[i
]; i
++)
594 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
596 /* must be a register or number */
597 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
598 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
601 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
602 if (flags
& OPERAND_SHIFT
)
605 length
= d30v_operand_table
[form
->operands
[i
]].length
;
606 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
607 if (opers
[i
].X_op
!= O_symbol
)
608 number
= opers
[i
].X_add_number
;
611 if (flags
& OPERAND_REG
)
613 /* check for mvfsys or mvtsys control registers */
614 if (flags
& OPERAND_CONTROL
&& (number
& 0x7f) > MAX_CONTROL_REG
)
617 id
= (number
& 0x7f) - MAX_CONTROL_REG
;
620 else if (number
& OPERAND_FLAG
)
622 id
= 3; /* number is a flag register */
626 else if (flags
& OPERAND_SPECIAL
)
631 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
633 /* now create a fixup */
635 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
636 as_fatal (_("too many fixups"));
638 fixups
->fix
[fixups
->fc
].reloc
=
639 get_reloc ((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
640 fixups
->fix
[fixups
->fc
].size
= 4;
641 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
642 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
643 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D30V_9_PCREL
)
644 fixups
->fix
[fixups
->fc
].pcrel
= RELOC_PCREL
;
646 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
650 /* truncate to the proper number of bits */
651 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
652 as_bad (_("operand out of range: %d"),number
);
654 number
&= 0x7FFFFFFF >> (31 - bits
);
655 if (flags
& OPERAND_SHIFT
)
659 /* it's a LONG instruction */
660 insn
|= ((number
& 0xffffffff) >> 26); /* top 6 bits */
661 insn
<<= 32; /* shift the first word over */
662 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
663 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
666 insn
|= number
<< shift
;
672 /* write out a long form instruction */
674 write_long (opcode
, insn
, fx
)
675 struct d30v_insn
*opcode
;
680 char *f
= frag_more (8);
683 d30v_number_to_chars (f
, insn
, 8);
685 for (i
=0; i
< fx
->fc
; i
++)
687 if (fx
->fix
[i
].reloc
)
689 where
= f
- frag_now
->fr_literal
;
690 fix_new_exp (frag_now
,
702 /* Write out a short form instruction by itself. */
704 write_1_short (opcode
, insn
, fx
, use_sequential
)
705 struct d30v_insn
*opcode
;
710 char *f
= frag_more (8);
713 if (warn_nops
== NOP_ALL
)
714 as_warn (_("%s NOP inserted"), use_sequential
?
715 _("sequential") : _("parallel"));
717 /* The other container needs to be NOP. */
720 /* Use a sequential NOP rather than a parallel one,
721 as the current instruction is a FLAG_MUL32 type one
722 and the next instruction is a load. */
724 /* According to 4.3.1: for FM=01, sub-instructions performed
725 only by IU cannot be encoded in L-container. */
727 if (opcode
->op
->unit
== IU
)
728 insn
|= FM10
| NOP_LEFT
; /* right then left */
730 insn
= FM01
| (insn
<< 32) | NOP_RIGHT
; /* left then right */
734 /* According to 4.3.1: for FM=00, sub-instructions performed
735 only by IU cannot be encoded in L-container. */
737 if (opcode
->op
->unit
== IU
)
738 insn
|= FM00
| NOP_LEFT
; /* right container */
740 insn
= FM00
| (insn
<< 32) | NOP_RIGHT
; /* left container */
743 d30v_number_to_chars (f
, insn
, 8);
745 for (i
=0; i
< fx
->fc
; i
++)
747 if (fx
->fix
[i
].reloc
)
749 where
= f
- frag_now
->fr_literal
;
750 fix_new_exp (frag_now
,
761 /* Write out a short form instruction if possible.
762 Return number of instructions not written out. */
764 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
765 struct d30v_insn
*opcode1
, *opcode2
;
766 long long insn1
, insn2
;
767 exec_type_enum exec_type
;
770 long long insn
= NOP2
;
774 if (exec_type
== EXEC_SEQ
775 && (opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
))
776 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0)
777 && ((opcode1
->ecc
== ECC_AL
) || ! Optimizing
))
779 /* Unconditional, non-delayed branches kill instructions in
780 the right bin. Conditional branches don't always but if
781 we are not optimizing, then we have been asked to produce
782 an error about such constructs. For the purposes of this
783 test, subroutine calls are considered to be branches. */
784 write_1_short (opcode1
, insn1
, fx
->next
, false);
788 /* Note: we do not have to worry about subroutine calls occuring
789 in the right hand container. The return address is always
790 aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
794 case EXEC_UNKNOWN
: /* Order not specified. */
796 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
)
797 && ! ( (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
798 || opcode1
->op
->unit
== MU
)
800 ( opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
801 || opcode2
->op
->unit
== MU
)))
804 exec_type
= EXEC_PARALLEL
;
806 if (opcode1
->op
->unit
== IU
807 || opcode2
->op
->unit
== MU
808 || opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
809 insn
= FM00
| (insn2
<< 32) | insn1
;
812 insn
= FM00
| (insn1
<< 32) | insn2
;
816 else if ((opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)
817 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0))
818 || opcode1
->op
->flags_used
& FLAG_RP
)
820 /* We must emit (non-delayed) branch type instructions
821 on their own with nothing in the right container. */
822 /* We must treat repeat instructions likewise, since the
823 following instruction has to be separate from the repeat
824 in order to be repeated. */
825 write_1_short (opcode1
, insn1
, fx
->next
, false);
828 else if (prev_left_kills_right_p
)
830 /* The left instruction kils the right slot, so we
831 must leave it empty. */
832 write_1_short (opcode1
, insn1
, fx
->next
, false);
835 else if (opcode1
->op
->unit
== IU
)
837 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
839 /* Case 103810 is a request from Mitsubishi that opcodes
840 with EITHER_BUT_PREFER_MU should not be executed in
841 reverse sequential order. */
842 write_1_short (opcode1
, insn1
, fx
->next
, false);
846 /* reverse sequential */
847 insn
= FM10
| (insn2
<< 32) | insn1
;
848 exec_type
= EXEC_REVSEQ
;
853 insn
= FM01
| (insn1
<< 32) | insn2
;
855 exec_type
= EXEC_SEQ
;
859 case EXEC_PARALLEL
: /* parallel */
860 flag_explicitly_parallel
= flag_xp_state
;
861 if (! parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
862 as_bad (_("Instructions may not be executed in parallel"));
863 else if (opcode1
->op
->unit
== IU
)
865 if (opcode2
->op
->unit
== IU
)
866 as_bad (_("Two IU instructions may not be executed in parallel"));
867 as_warn (_("Swapping instruction order"));
868 insn
= FM00
| (insn2
<< 32) | insn1
;
870 else if (opcode2
->op
->unit
== MU
)
872 if (opcode1
->op
->unit
== MU
)
873 as_bad (_("Two MU instructions may not be executed in parallel"));
874 else if (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
)
875 as_warn (_("Executing %s in IU may not work"), opcode1
->op
->name
);
876 as_warn (_("Swapping instruction order"));
877 insn
= FM00
| (insn2
<< 32) | insn1
;
881 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
882 as_warn (_("Executing %s in IU in parallel with %s may not work"),
883 opcode1
->op
->name
, opcode2
->op
->name
);
885 insn
= FM00
| (insn1
<< 32) | insn2
;
888 flag_explicitly_parallel
= 0;
891 case EXEC_SEQ
: /* sequential */
892 if (opcode1
->op
->unit
== IU
)
893 as_bad (_("IU instruction may not be in the left container"));
894 if (prev_left_kills_right_p
)
895 as_bad (_("special left instruction `%s' kills instruction "
896 "`%s' in right container"),
897 opcode1
->op
->name
, opcode2
->op
->name
);
898 insn
= FM01
| (insn1
<< 32) | insn2
;
902 case EXEC_REVSEQ
: /* reverse sequential */
903 if (opcode2
->op
->unit
== MU
)
904 as_bad (_("MU instruction may not be in the right container"));
905 if (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
906 || opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
907 as_warn (_("Executing %s in reverse serial with %s may not work"),
908 opcode1
->op
->name
, opcode2
->op
->name
);
909 insn
= FM10
| (insn1
<< 32) | insn2
;
914 as_fatal (_("unknown execution type passed to write_2_short()"));
917 /* printf ("writing out %llx\n",insn); */
919 d30v_number_to_chars (f
, insn
, 8);
921 /* If the previous instruction was a 32-bit multiply but it is put into a
922 parallel container, mark the current instruction as being a 32-bit
924 if (prev_mul32_p
&& exec_type
== EXEC_PARALLEL
)
929 for (i
=0; i
< fx
->fc
; i
++)
931 if (fx
->fix
[i
].reloc
)
933 where
= (f
- frag_now
->fr_literal
) + 4*j
;
935 fix_new_exp (frag_now
,
952 /* Check 2 instructions and determine if they can be safely */
953 /* executed in parallel. Returns 1 if they can be. */
955 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
956 struct d30v_insn
*op1
, *op2
;
957 unsigned long insn1
, insn2
;
958 exec_type_enum exec_type
;
960 int i
, j
, shift
, regno
, bits
, ecc
;
961 unsigned long flags
, mask
, flags_set1
, flags_set2
, flags_used1
, flags_used2
;
962 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3], flag_reg
[2];
963 struct d30v_format
*f
;
964 struct d30v_opcode
*op
;
966 /* section 4.3: both instructions must not be IU or MU only */
967 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
968 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
971 /* first instruction must not be a jump to safely optimize, unless this
972 is an explicit parallel operation. */
973 if (exec_type
!= EXEC_PARALLEL
974 && (op1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)))
977 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
978 then it is safe to allow the two to be done as parallel ops, since only
979 one will ever be executed at a time. */
980 if ((op1
->ecc
== ECC_TX
&& op2
->ecc
== ECC_FX
)
981 || (op1
->ecc
== ECC_FX
&& op2
->ecc
== ECC_TX
)
982 || (op1
->ecc
== ECC_XT
&& op2
->ecc
== ECC_XF
)
983 || (op1
->ecc
== ECC_XF
&& op2
->ecc
== ECC_XT
))
988 [2] a0, a1, flag registers */
990 for (j
= 0; j
< 2; j
++)
1007 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
1008 used_reg
[j
][0] = used_reg
[j
][1] = 0;
1010 if (flag_explicitly_parallel
)
1012 /* For human specified parallel instructions we have been asked
1013 to ignore the possibility that both instructions could modify
1014 bits in the PSW, so we initialise the mod & used arrays to 0.
1015 We have been asked, however, to refuse to allow parallel
1016 instructions which explicitly set the same flag register,
1017 eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test
1018 for the use of a flag register and set a bit in the mod or used
1019 array appropriately. */
1026 mod_reg
[j
][2] = (op
->flags_set
& FLAG_ALL
);
1027 used_reg
[j
][2] = (op
->flags_used
& FLAG_ALL
);
1030 /* BSR/JSR always sets R62 */
1031 if (op
->flags_used
& FLAG_JSR
)
1032 mod_reg
[j
][1] = (1L << (62-32));
1034 /* conditional execution affects the flags_used */
1039 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_0
;
1044 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_1
;
1049 used_reg
[j
][2] |= flag_reg
[j
] = (FLAG_0
| FLAG_1
);
1053 for (i
= 0; f
->operands
[i
]; i
++)
1055 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
1056 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
1057 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
1061 mask
= 0x7FFFFFFF >> (31 - bits
);
1063 if ((flags
& OPERAND_PLUS
) || (flags
& OPERAND_MINUS
))
1065 /* this is a post-increment or post-decrement */
1066 /* the previous register needs to be marked as modified */
1068 shift
= 12 - d30v_operand_table
[f
->operands
[i
-1]].position
;
1069 regno
= (ins
>> shift
) & 0x3f;
1071 mod_reg
[j
][1] |= 1L << (regno
- 32);
1073 mod_reg
[j
][0] |= 1L << regno
;
1075 else if (flags
& OPERAND_REG
)
1077 regno
= (ins
>> shift
) & mask
;
1078 /* the memory write functions don't have a destination register */
1079 if ((flags
& OPERAND_DEST
) && !(op
->flags_set
& FLAG_MEM
))
1081 /* MODIFIED registers and flags */
1082 if (flags
& OPERAND_ACC
)
1085 mod_reg
[j
][2] |= FLAG_A0
;
1086 else if (regno
== 1)
1087 mod_reg
[j
][2] |= FLAG_A1
;
1091 else if (flags
& OPERAND_FLAG
)
1092 mod_reg
[j
][2] |= 1L << regno
;
1093 else if (!(flags
& OPERAND_CONTROL
))
1097 /* need to check if there are two destination */
1098 /* registers, for example ld2w */
1099 if (flags
& OPERAND_2REG
)
1104 for (r
= regno
; r
<= regno
+ z
; r
++)
1107 mod_reg
[j
][1] |= 1L << (r
- 32);
1109 mod_reg
[j
][0] |= 1L << r
;
1115 /* USED, but not modified registers and flags */
1116 if (flags
& OPERAND_ACC
)
1119 used_reg
[j
][2] |= FLAG_A0
;
1120 else if (regno
== 1)
1121 used_reg
[j
][2] |= FLAG_A1
;
1125 else if (flags
& OPERAND_FLAG
)
1126 used_reg
[j
][2] |= 1L << regno
;
1127 else if (!(flags
& OPERAND_CONTROL
))
1131 /* need to check if there are two source */
1132 /* registers, for example st2w */
1133 if (flags
& OPERAND_2REG
)
1138 for (r
= regno
; r
<= regno
+ z
; r
++)
1141 used_reg
[j
][1] |= 1L << (r
- 32);
1143 used_reg
[j
][0] |= 1L << r
;
1151 flags_set1
= op1
->op
->flags_set
;
1152 flags_set2
= op2
->op
->flags_set
;
1153 flags_used1
= op1
->op
->flags_used
;
1154 flags_used2
= op2
->op
->flags_used
;
1156 /* Check for illegal combinations with ADDppp/SUBppp. */
1157 if (((flags_set1
& FLAG_NOT_WITH_ADDSUBppp
) != 0
1158 && (flags_used2
& FLAG_ADDSUBppp
) != 0)
1159 || ((flags_set2
& FLAG_NOT_WITH_ADDSUBppp
) != 0
1160 && (flags_used1
& FLAG_ADDSUBppp
) != 0))
1163 /* Load instruction combined with half-word multiply is illegal. */
1164 if (((flags_used1
& FLAG_MEM
) != 0 && (flags_used2
& FLAG_MUL16
))
1165 || ((flags_used2
& FLAG_MEM
) != 0 && (flags_used1
& FLAG_MUL16
)))
1168 /* Specifically allow add || add by removing carry, overflow bits dependency.
1169 This is safe, even if an addc follows since the IU takes the argument in
1170 the right container, and it writes its results last.
1171 However, don't paralellize add followed by addc or sub followed by
1174 if (mod_reg
[0][2] == FLAG_CVVA
&& mod_reg
[1][2] == FLAG_CVVA
1175 && (used_reg
[0][2] & ~flag_reg
[0]) == 0
1176 && (used_reg
[1][2] & ~flag_reg
[1]) == 0
1177 && op1
->op
->unit
== EITHER
&& op2
->op
->unit
== EITHER
)
1179 mod_reg
[0][2] = mod_reg
[1][2] = 0;
1182 for (j
= 0; j
< 3; j
++)
1184 /* If the second instruction depends on the first, we obviously
1185 cannot parallelize. Note, the mod flag implies use, so
1186 check that as well. */
1187 /* If flag_explicitly_parallel is set, then the case of the
1188 second instruction using a register the first instruction
1189 modifies is assumed to be okay; we trust the human. We
1190 don't trust the human if both instructions modify the same
1191 register but we do trust the human if they modify the same
1193 /* We have now been requested not to trust the human if the
1194 instructions modify the same flag registers either. */
1195 if (flag_explicitly_parallel
)
1197 if ((mod_reg
[0][j
] & mod_reg
[1][j
]) != 0)
1201 if ((mod_reg
[0][j
] & (mod_reg
[1][j
] | used_reg
[1][j
])) != 0)
1209 /* This is the main entry point for the machine-dependent assembler. str points to a
1210 machine-dependent instruction. This function is supposed to emit the frags/bytes
1211 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
1212 and leaves the difficult stuff to do_assemble(). */
1214 static long long prev_insn
= -1;
1215 static struct d30v_insn prev_opcode
;
1216 static subsegT prev_subseg
;
1217 static segT prev_seg
= 0;
1223 struct d30v_insn opcode
;
1225 exec_type_enum extype
= EXEC_UNKNOWN
; /* execution type; parallel, etc */
1226 static exec_type_enum etype
= EXEC_UNKNOWN
; /* saved extype. used for multiline instructions */
1229 if ((prev_insn
!= -1) && prev_seg
1230 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1231 d30v_cleanup (false);
1233 if (d30v_current_align
< 3)
1234 d30v_align (3, NULL
, d30v_last_label
);
1235 else if (d30v_current_align
> 3)
1236 d30v_current_align
= 3;
1237 d30v_last_label
= NULL
;
1239 flag_explicitly_parallel
= 0;
1241 if (etype
== EXEC_UNKNOWN
)
1243 /* look for the special multiple instruction separators */
1244 str2
= strstr (str
, "||");
1247 extype
= EXEC_PARALLEL
;
1252 str2
= strstr (str
, "->");
1257 str2
= strstr (str
, "<-");
1259 extype
= EXEC_REVSEQ
;
1262 /* str2 points to the separator, if one */
1267 /* if two instructions are present and we already have one saved
1268 then first write it out */
1269 d30v_cleanup (false);
1271 /* Assemble first instruction and save it. */
1272 prev_insn
= do_assemble (str
, &prev_opcode
, 1, 0);
1273 if (prev_insn
== -1)
1274 as_bad (_("Cannot assemble instruction"));
1275 if (prev_opcode
.form
!= NULL
&& prev_opcode
.form
->form
>= LONG
)
1276 as_bad (_("First opcode is long. Unable to mix instructions as specified."));
1277 fixups
= fixups
->next
;
1280 prev_subseg
= now_subseg
;
1284 insn
= do_assemble (str
, &opcode
,
1285 (extype
!= EXEC_UNKNOWN
|| etype
!= EXEC_UNKNOWN
),
1286 extype
== EXEC_PARALLEL
);
1289 if (extype
!= EXEC_UNKNOWN
)
1291 as_bad (_("Cannot assemble instruction"));
1295 if (etype
!= EXEC_UNKNOWN
)
1298 etype
= EXEC_UNKNOWN
;
1301 /* Word multiply instructions must not be followed by either a load or a
1302 16-bit multiply instruction in the next cycle. */
1303 if ( (extype
!= EXEC_REVSEQ
)
1305 && (opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1307 /* However, load and multiply should able to be combined in a parallel
1308 operation, so check for that first. */
1310 && (opcode
.op
->flags_used
& FLAG_MEM
)
1311 && opcode
.form
->form
< LONG
1312 && (extype
== EXEC_PARALLEL
|| (Optimizing
&& extype
== EXEC_UNKNOWN
))
1313 && parallel_ok (&prev_opcode
, (long)prev_insn
,
1314 &opcode
, (long)insn
, extype
)
1315 && write_2_short (&prev_opcode
, (long)prev_insn
,
1316 &opcode
, (long)insn
, extype
, fixups
) == 0)
1318 /* no instructions saved */
1324 /* Can't parallelize, flush previous instruction and emit a word of NOPS,
1325 unless the previous instruction is a NOP, in which case just flush it,
1326 as this will generate a word of NOPs for us. */
1328 if (prev_insn
!= -1 && (strcmp (prev_opcode
.op
->name
, "nop") == 0))
1329 d30v_cleanup (false);
1334 if (prev_insn
!= -1)
1335 d30v_cleanup (true);
1339 d30v_number_to_chars (f
, NOP2
, 8);
1341 if (warn_nops
== NOP_ALL
|| warn_nops
== NOP_MULTIPLY
)
1343 if (opcode
.op
->flags_used
& FLAG_MEM
)
1344 as_warn (_("word of NOPs added between word multiply and load"));
1346 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1351 extype
= EXEC_UNKNOWN
;
1354 else if ( (extype
== EXEC_REVSEQ
)
1356 && (prev_opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1358 /* Can't parallelize, flush current instruction and add a sequential NOP. */
1359 write_1_short (& opcode
, (long) insn
, fixups
->next
->next
, true);
1361 /* Make the previous instruction the current one. */
1362 extype
= EXEC_UNKNOWN
;
1365 now_subseg
= prev_subseg
;
1367 cur_mul32_p
= prev_mul32_p
;
1369 memcpy (&opcode
, &prev_opcode
, sizeof (prev_opcode
));
1372 /* If this is a long instruction, write it and any previous short instruction. */
1373 if (opcode
.form
->form
>= LONG
)
1375 if (extype
!= EXEC_UNKNOWN
)
1376 as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
1377 d30v_cleanup (false);
1378 write_long (& opcode
, insn
, fixups
);
1381 else if ((prev_insn
!= -1)
1383 (& prev_opcode
, (long) prev_insn
, & opcode
,
1384 (long) insn
, extype
, fixups
) == 0))
1386 /* No instructions saved. */
1391 if (extype
!= EXEC_UNKNOWN
)
1392 as_bad (_("Unable to mix instructions as specified"));
1394 /* Save off last instruction so it may be packed on next pass. */
1395 memcpy (&prev_opcode
, &opcode
, sizeof (prev_opcode
));
1398 prev_subseg
= now_subseg
;
1399 fixups
= fixups
->next
;
1400 prev_mul32_p
= cur_mul32_p
;
1405 /* do_assemble assembles a single instruction and returns an opcode */
1406 /* it returns -1 (an invalid opcode) on error */
1408 #define NAME_BUF_LEN 20
1411 do_assemble (str
, opcode
, shortp
, is_parallel
)
1413 struct d30v_insn
*opcode
;
1417 unsigned char * op_start
;
1418 unsigned char * save
;
1419 unsigned char * op_end
;
1420 char name
[NAME_BUF_LEN
];
1423 int fsize
= (shortp
? FORCE_SHORT
: 0);
1424 expressionS myops
[6];
1427 /* Drop leading whitespace */
1428 while (* str
== ' ')
1431 /* find the opcode end */
1432 for (op_start
= op_end
= (unsigned char *) (str
);
1434 && nlen
< (NAME_BUF_LEN
- 1)
1436 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1439 name
[nlen
] = tolower (op_start
[nlen
]);
1448 /* if there is an execution condition code, handle it */
1452 while ( (i
< ECC_MAX
) && strncasecmp (d30v_ecc_names
[i
], op_end
+ 1, 2))
1458 strncpy (tmp
, op_end
+ 1, 2);
1460 as_bad (_("unknown condition code: %s"),tmp
);
1463 /* printf ("condition code=%d\n",i); */
1468 opcode
->ecc
= ECC_AL
;
1471 /* CMP and CMPU change their name based on condition codes */
1472 if (!strncmp (name
, "cmp", 3))
1475 char **str
= (char **)d30v_cc_names
;
1481 for (i
=1; *str
&& strncmp (*str
, & name
[p
], 2); i
++, str
++)
1484 /* cmpu only supports some condition codes */
1490 as_bad (_("cmpu doesn't support condition code %s"),&name
[p
]);
1497 as_bad (_("unknown condition code: %s"),&name
[p
]);
1506 /* printf("cmp_hack=%d\n",cmp_hack); */
1508 /* need to look for .s or .l */
1509 if (name
[nlen
-2] == '.')
1511 switch (name
[nlen
-1])
1514 fsize
= FORCE_SHORT
;
1523 /* find the first opcode with the proper name */
1524 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1525 if (opcode
->op
== NULL
)
1527 as_bad (_("unknown opcode: %s"),name
);
1531 save
= input_line_pointer
;
1532 input_line_pointer
= op_end
;
1533 while (!(opcode
->form
= find_format (opcode
->op
, myops
, fsize
, cmp_hack
)))
1536 if (opcode
->op
->name
== NULL
|| strcmp (opcode
->op
->name
, name
))
1538 as_bad (_("operands for opcode `%s' do not match any valid format"), name
);
1542 input_line_pointer
= save
;
1544 insn
= build_insn (opcode
, myops
);
1546 /* Propigate multiply status */
1549 if (is_parallel
&& prev_mul32_p
)
1553 prev_mul32_p
= cur_mul32_p
;
1554 cur_mul32_p
= (opcode
->op
->flags_used
& FLAG_MUL32
) != 0;
1558 /* Propagate left_kills_right status */
1561 prev_left_kills_right_p
= cur_left_kills_right_p
;
1563 if (opcode
->op
->flags_set
& FLAG_LKR
)
1565 cur_left_kills_right_p
= 1;
1567 if (strcmp (opcode
->op
->name
, "mvtsys") == 0)
1569 /* Left kills right for only mvtsys only for PSW/PSWH/PSWL/flags target. */
1570 if ((myops
[0].X_op
== O_register
) &&
1571 ((myops
[0].X_add_number
== OPERAND_CONTROL
) || /* psw */
1572 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+2) || /* pswh */
1573 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+1) || /* pswl */
1574 (myops
[0].X_add_number
== OPERAND_FLAG
+0) || /* f0 */
1575 (myops
[0].X_add_number
== OPERAND_FLAG
+1) || /* f1 */
1576 (myops
[0].X_add_number
== OPERAND_FLAG
+2) || /* f2 */
1577 (myops
[0].X_add_number
== OPERAND_FLAG
+3) || /* f3 */
1578 (myops
[0].X_add_number
== OPERAND_FLAG
+4) || /* f4 */
1579 (myops
[0].X_add_number
== OPERAND_FLAG
+5) || /* f5 */
1580 (myops
[0].X_add_number
== OPERAND_FLAG
+6) || /* f6 */
1581 (myops
[0].X_add_number
== OPERAND_FLAG
+7))) /* f7 */
1583 cur_left_kills_right_p
= 1;
1587 /* Other mvtsys target registers don't kill right instruction. */
1588 cur_left_kills_right_p
= 0;
1593 cur_left_kills_right_p
= 0;
1600 /* find_format() gets a pointer to an entry in the format table.
1601 It must look at all formats for an opcode and use the operands
1602 to choose the correct one. Returns NULL on error. */
1604 static struct d30v_format
*
1605 find_format (opcode
, myops
, fsize
, cmp_hack
)
1606 struct d30v_opcode
*opcode
;
1607 expressionS myops
[];
1611 int numops
, match
, index
, i
=0, j
, k
;
1612 struct d30v_format
*fm
;
1617 /* Get all the operands and save them as expressions. */
1618 numops
= get_operands (myops
, cmp_hack
);
1620 while ((index
= opcode
->format
[i
++]) != 0)
1622 if (fsize
== FORCE_SHORT
&& index
>= LONG
)
1625 if (fsize
== FORCE_LONG
&& index
< LONG
)
1628 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1630 while (fm
->form
== index
)
1633 /* Now check the operands for compatibility. */
1634 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1636 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1637 int bits
= d30v_operand_table
[fm
->operands
[j
]].bits
;
1638 int X_op
= myops
[j
].X_op
;
1639 int num
= myops
[j
].X_add_number
;
1641 if (flags
& OPERAND_SPECIAL
)
1643 else if (X_op
== O_illegal
)
1645 else if (flags
& OPERAND_REG
)
1647 if (X_op
!= O_register
1648 || ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
))
1649 || (!(flags
& OPERAND_ACC
) && (num
& OPERAND_ACC
))
1650 || ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
))
1651 || (!(flags
& (OPERAND_FLAG
| OPERAND_CONTROL
)) && (num
& OPERAND_FLAG
))
1652 || ((flags
& OPERAND_CONTROL
)
1653 && !(num
& (OPERAND_CONTROL
| OPERAND_FLAG
))))
1658 else if (((flags
& OPERAND_MINUS
)
1659 && (X_op
!= O_absent
|| num
!= OPERAND_MINUS
))
1660 || ((flags
& OPERAND_PLUS
)
1661 && (X_op
!= O_absent
|| num
!= OPERAND_PLUS
))
1662 || ((flags
& OPERAND_ATMINUS
)
1663 && (X_op
!= O_absent
|| num
!= OPERAND_ATMINUS
))
1664 || ((flags
& OPERAND_ATPAR
)
1665 && (X_op
!= O_absent
|| num
!= OPERAND_ATPAR
))
1666 || ((flags
& OPERAND_ATSIGN
)
1667 && (X_op
!= O_absent
|| num
!= OPERAND_ATSIGN
)))
1671 else if (flags
& OPERAND_NUM
)
1673 /* A number can be a constant or symbol expression. */
1675 /* If we have found a register name, but that name also
1676 matches a symbol, then re-parse the name as an expression. */
1677 if (X_op
== O_register
1678 && symbol_find ((char *) myops
[j
].X_op_symbol
))
1680 input_line_pointer
= (char *) myops
[j
].X_op_symbol
;
1681 expression (& myops
[j
]);
1684 /* Turn an expression into a symbol for later resolution. */
1685 if (X_op
!= O_absent
&& X_op
!= O_constant
1686 && X_op
!= O_symbol
&& X_op
!= O_register
1689 symbolS
*sym
= make_expr_symbol (&myops
[j
]);
1690 myops
[j
].X_op
= X_op
= O_symbol
;
1691 myops
[j
].X_add_symbol
= sym
;
1692 myops
[j
].X_add_number
= num
= 0;
1695 if (fm
->form
>= LONG
)
1697 /* If we're testing for a LONG format, either fits. */
1698 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1701 else if (fm
->form
< LONG
1702 && ((fsize
== FORCE_SHORT
&& X_op
== O_symbol
)
1703 || (fm
->form
== SHORT_D2
&& j
== 0)))
1705 /* This is the tricky part. Will the constant or symbol
1706 fit into the space in the current format? */
1707 else if (X_op
== O_constant
)
1709 if (check_range (num
, bits
, flags
))
1712 else if (X_op
== O_symbol
1713 && S_IS_DEFINED (myops
[j
].X_add_symbol
)
1714 && S_GET_SEGMENT (myops
[j
].X_add_symbol
) == now_seg
1715 && opcode
->reloc_flag
== RELOC_PCREL
)
1717 /* If the symbol is defined, see if the value will fit
1718 into the form we're considering. */
1722 /* Calculate the current address by running through the
1723 previous frags and adding our current offset. */
1725 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1726 value
+= f
->fr_fix
+ f
->fr_offset
;
1727 value
= (S_GET_VALUE (myops
[j
].X_add_symbol
) - value
1728 - (obstack_next_free (&frchain_now
->frch_obstack
)
1729 - frag_now
->fr_literal
));
1730 if (check_range (value
, bits
, flags
))
1737 /* printf("through the loop: match=%d\n",match); */
1738 /* We're only done if the operands matched so far AND there
1739 are no more to check. */
1740 if (match
&& myops
[j
].X_op
== 0)
1742 /* Final check - issue a warning if an odd numbered register
1743 is used as the first register in an instruction that reads
1744 or writes 2 registers. */
1746 for (j
= 0; fm
->operands
[j
]; j
++)
1747 if (myops
[j
].X_op
== O_register
1748 && (myops
[j
].X_add_number
& 1)
1749 && (d30v_operand_table
[fm
->operands
[j
]].flags
& OPERAND_2REG
))
1751 _("Odd numbered register used as target of multi-register instruction"));
1755 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1757 /* printf("trying another format: i=%d\n",i); */
1762 /* if while processing a fixup, a reloc really needs to be created */
1763 /* then it is done here */
1766 tc_gen_reloc (seg
, fixp
)
1771 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1772 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1773 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1774 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1775 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1776 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1778 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1779 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1782 reloc
->addend
= fixp
->fx_addnumber
;
1787 md_estimate_size_before_relax (fragp
, seg
)
1796 md_pcrel_from_section (fixp
, sec
)
1800 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1801 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1803 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1807 md_apply_fix3 (fixp
, valuep
, seg
)
1813 unsigned long insn
, insn2
;
1816 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1821 else if (fixp
->fx_pcrel
)
1825 value
= fixp
->fx_offset
;
1827 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1829 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1830 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1833 /* We don't actually support subtracting a symbol. */
1834 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1835 _("expression too complex"));
1840 /* Fetch the instruction, insert the fully resolved operand
1841 value, and stuff the instruction back again. */
1842 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1843 insn
= bfd_getb32 ((unsigned char *) where
);
1845 switch (fixp
->fx_r_type
)
1847 case BFD_RELOC_8
: /* Check for a bad .byte directive. */
1848 if (fixp
->fx_addsy
!= NULL
)
1849 as_bad (_("line %d: unable to place address of symbol '%s' into a byte"),
1850 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1851 else if (((unsigned)value
) > 0xff)
1852 as_bad (_("line %d: unable to place value %x into a byte"),
1853 fixp
->fx_line
, value
);
1855 * (unsigned char *) where
= value
;
1858 case BFD_RELOC_16
: /* Check for a bad .short directive. */
1859 if (fixp
->fx_addsy
!= NULL
)
1860 as_bad (_("line %d: unable to place address of symbol '%s' into a short"),
1861 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1862 else if (((unsigned)value
) > 0xffff)
1863 as_bad (_("line %d: unable to place value %x into a short"),
1864 fixp
->fx_line
, value
);
1866 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1869 case BFD_RELOC_64
: /* Check for a bad .quad directive. */
1870 if (fixp
->fx_addsy
!= NULL
)
1871 as_bad (_("line %d: unable to place address of symbol '%s' into a quad"),
1872 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1875 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1876 bfd_putb32 (0, ((unsigned char *) where
) + 4);
1880 case BFD_RELOC_D30V_6
:
1881 check_size (value
, 6, fixp
->fx_file
, fixp
->fx_line
);
1882 insn
|= value
& 0x3F;
1883 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1886 case BFD_RELOC_D30V_9_PCREL
:
1887 if (fixp
->fx_where
& 0x7)
1892 fixp
->fx_r_type
= BFD_RELOC_D30V_9_PCREL_R
;
1894 check_size (value
, 9, fixp
->fx_file
, fixp
->fx_line
);
1895 insn
|= ((value
>> 3) & 0x3F) << 12;
1896 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1899 case BFD_RELOC_D30V_15
:
1900 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1901 insn
|= (value
>> 3) & 0xFFF;
1902 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1905 case BFD_RELOC_D30V_15_PCREL
:
1906 if (fixp
->fx_where
& 0x7)
1911 fixp
->fx_r_type
= BFD_RELOC_D30V_15_PCREL_R
;
1913 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1914 insn
|= (value
>> 3) & 0xFFF;
1915 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1918 case BFD_RELOC_D30V_21
:
1919 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1920 insn
|= (value
>> 3) & 0x3FFFF;
1921 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1924 case BFD_RELOC_D30V_21_PCREL
:
1925 if (fixp
->fx_where
& 0x7)
1930 fixp
->fx_r_type
= BFD_RELOC_D30V_21_PCREL_R
;
1932 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1933 insn
|= (value
>> 3) & 0x3FFFF;
1934 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1937 case BFD_RELOC_D30V_32
:
1938 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1939 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1940 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1941 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1942 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1943 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1946 case BFD_RELOC_D30V_32_PCREL
:
1947 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1948 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1949 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1950 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1951 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1952 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1956 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1960 as_bad (_("line %d: unknown relocation type: 0x%x"),
1961 fixp
->fx_line
,fixp
->fx_r_type
);
1968 /* d30v_cleanup() is called after the assembler has finished parsing the input
1969 file or after a label is defined. Because the D30V assembler sometimes saves short
1970 instructions to see if it can package them with the next instruction, there may
1971 be a short instruction that still needs written. */
1973 d30v_cleanup (use_sequential
)
1979 if (prev_insn
!= -1)
1982 subseg
= now_subseg
;
1983 subseg_set (prev_seg
, prev_subseg
);
1984 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
, use_sequential
);
1985 subseg_set (seg
, subseg
);
1988 prev_mul32_p
= false;
1994 d30v_number_to_chars (buf
, value
, n
)
1995 char *buf
; /* Return 'nbytes' of chars here. */
1996 long long value
; /* The value of the bits. */
1997 int n
; /* Number of bytes in the output. */
2001 buf
[n
] = value
& 0xff;
2007 /* This function is called at the start of every line. */
2008 /* it checks to see if the first character is a '.' */
2009 /* which indicates the start of a pseudo-op. If it is, */
2010 /* then write out any unwritten instructions */
2015 char *c
= input_line_pointer
;
2017 while (isspace (*c
))
2021 d30v_cleanup (false);
2025 check_size (value
, bits
, file
, line
)
2038 max
= (1 << (bits
- 1)) - 1;
2041 as_bad_where (file
, line
, _("value too large to fit in %d bits"), bits
);
2046 /* d30v_frob_label() is called when after a label is recognized. */
2049 d30v_frob_label (lab
)
2052 /* Emit any pending instructions. */
2053 d30v_cleanup (false);
2055 /* Update the label's address with the current output pointer. */
2056 symbol_set_frag (lab
, frag_now
);
2057 S_SET_VALUE (lab
, (valueT
) frag_now_fix ());
2059 /* Record this label for future adjustment after we find out what
2060 kind of data it references, and the required alignment therewith. */
2061 d30v_last_label
= lab
;
2064 /* Hook into cons for capturing alignment changes. */
2067 d30v_cons_align (size
)
2073 while ((size
>>= 1) != 0)
2076 if (d30v_current_align
< log_size
)
2077 d30v_align (log_size
, (char *) NULL
, NULL
);
2078 else if (d30v_current_align
> log_size
)
2079 d30v_current_align
= log_size
;
2080 d30v_last_label
= NULL
;
2083 /* Called internally to handle all alignment needs. This takes care
2084 of eliding calls to frag_align if'n the cached current alignment
2085 says we've already got it, as well as taking care of the auto-aligning
2089 d30v_align (n
, pfill
, label
)
2094 /* The front end is prone to changing segments out from under us
2095 temporarily when -g is in effect. */
2096 int switched_seg_p
= (d30v_current_align_seg
!= now_seg
);
2098 /* Do not assume that if 'd30v_current_align >= n' and
2099 '! switched_seg_p' that it is safe to avoid performing
2100 this alignement request. The alignment of the current frag
2101 can be changed under our feet, for example by a .ascii
2102 directive in the source code. cf testsuite/gas/d30v/reloc.s */
2104 d30v_cleanup (false);
2109 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
2111 static char const nop
[4] = { 0x00, 0xf0, 0x00, 0x00 };
2113 /* First, make sure we're on a four-byte boundary, in case
2114 someone has been putting .byte values the text section. */
2115 if (d30v_current_align
< 2 || switched_seg_p
)
2116 frag_align (2, 0, 0);
2117 frag_align_pattern (n
, nop
, sizeof nop
, 0);
2120 frag_align (n
, 0, 0);
2123 frag_align (n
, *pfill
, 0);
2125 if (!switched_seg_p
)
2126 d30v_current_align
= n
;
2131 int label_seen
= false;
2132 struct frag
* old_frag
;
2136 assert (S_GET_SEGMENT (label
) == now_seg
);
2138 old_frag
= symbol_get_frag (label
);
2139 old_value
= S_GET_VALUE (label
);
2140 new_value
= (valueT
) frag_now_fix ();
2142 /* It is possible to have more than one label at a particular
2143 address, especially if debugging is enabled, so we must
2144 take care to adjust all the labels at this address in this
2145 fragment. To save time we search from the end of the symbol
2146 list, backwards, since the symbols we are interested in are
2147 almost certainly the ones that were most recently added.
2148 Also to save time we stop searching once we have seen at least
2149 one matching label, and we encounter a label that is no longer
2150 in the target fragment. Note, this search is guaranteed to
2151 find at least one match when sym == label, so no special case
2152 code is necessary. */
2153 for (sym
= symbol_lastP
; sym
!= NULL
; sym
= symbol_previous (sym
))
2155 if (symbol_get_frag (sym
) == old_frag
2156 && S_GET_VALUE (sym
) == old_value
)
2159 symbol_set_frag (sym
, frag_now
);
2160 S_SET_VALUE (sym
, new_value
);
2162 else if (label_seen
&& symbol_get_frag (sym
) != old_frag
)
2167 record_alignment (now_seg
, n
);
2170 /* Handle the .align pseudo-op. This aligns to a power of two. We
2171 hook here to latch the current alignment. */
2174 s_d30v_align (ignore
)
2178 char fill
, *pfill
= NULL
;
2179 long max_alignment
= 15;
2181 align
= get_absolute_expression ();
2182 if (align
> max_alignment
)
2184 align
= max_alignment
;
2185 as_warn (_("Alignment too large: %d assumed"), align
);
2189 as_warn (_("Alignment negative: 0 assumed"));
2193 if (*input_line_pointer
== ',')
2195 input_line_pointer
++;
2196 fill
= get_absolute_expression ();
2200 d30v_last_label
= NULL
;
2201 d30v_align (align
, pfill
, NULL
);
2203 demand_empty_rest_of_line ();
2206 /* Handle the .text pseudo-op. This is like the usual one, but it
2207 clears the saved last label and resets known alignment. */
2215 d30v_last_label
= NULL
;
2216 d30v_current_align
= 0;
2217 d30v_current_align_seg
= now_seg
;
2220 /* Handle the .data pseudo-op. This is like the usual one, but it
2221 clears the saved last label and resets known alignment. */
2228 d30v_last_label
= NULL
;
2229 d30v_current_align
= 0;
2230 d30v_current_align_seg
= now_seg
;
2233 /* Handle the .section pseudo-op. This is like the usual one, but it
2234 clears the saved last label and resets known alignment. */
2237 s_d30v_section (ignore
)
2240 obj_elf_section (ignore
);
2241 d30v_last_label
= NULL
;
2242 d30v_current_align
= 0;
2243 d30v_current_align_seg
= now_seg
;