1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
3 Copyright (C) 1997, 1998 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d30v.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "OnNcC";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
35 #define NOP_MULTIPLY 1
37 static int warn_nops
= 0;
38 static int Optimizing
= 0;
39 static int warn_register_name_conflicts
= 1;
45 typedef enum _exec_type
47 EXEC_UNKNOWN
, /* no order specified */
48 EXEC_PARALLEL
, /* done in parallel (FM=00) */
49 EXEC_SEQ
, /* sequential (FM=01) */
50 EXEC_REVSEQ
/* reverse sequential (FM=10) */
54 #define MAX_INSN_FIXUPS (5)
61 bfd_reloc_code_real_type reloc
;
64 typedef struct _fixups
67 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
71 static Fixups FixUps
[2];
72 static Fixups
*fixups
;
74 /* Whether current and previous instruction are word multiply insns. */
75 static int cur_mul32_p
= 0;
76 static int prev_mul32_p
= 0;
78 /* The flag_explicitly_parallel is true iff the instruction being assembled
79 has been explicitly written as a parallel short-instruction pair by the
80 human programmer. It is used in parallel_ok() to distinguish between
81 those dangerous parallelizations attempted by the human, which are to be
82 allowed, and those attempted by the assembler, which are not. It is set
83 from md_assemble(). */
84 static int flag_explicitly_parallel
= 0;
85 static int flag_xp_state
= 0;
87 /* Whether current and previous left sub-instruction disables
88 execution of right sub-instruction. */
89 static int cur_left_kills_right_p
= 0;
90 static int prev_left_kills_right_p
= 0;
92 /* The known current alignment of the current section. */
93 static int d30v_current_align
;
94 static segT d30v_current_align_seg
;
96 /* The last seen label in the current section. This is used to auto-align
97 labels preceeding instructions. */
98 static symbolS
*d30v_last_label
;
101 #define NOP_LEFT ((long long)NOP << 32)
102 #define NOP_RIGHT ((long long)NOP)
103 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
105 /* local functions */
106 static int reg_name_search
PARAMS ((char *name
));
107 static int register_name
PARAMS ((expressionS
*expressionP
));
108 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
109 static int postfix
PARAMS ((char *p
));
110 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
111 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
112 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
,
113 expressionS ops
[],int fsize
, int cmp_hack
));
114 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
115 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
116 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
,
117 Fixups
*fx
, int use_sequential
));
118 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
119 struct d30v_insn
*opcode2
, long long insn2
, exec_type_enum exec_type
, Fixups
*fx
));
120 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
,
121 int shortp
, int is_parallel
));
122 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
123 struct d30v_insn
*opcode2
, unsigned long insn2
,
124 exec_type_enum exec_type
));
125 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
126 static void check_size
PARAMS ((long value
, int bits
, char *file
, int line
));
127 static void d30v_align
PARAMS ((int, char *, symbolS
*));
128 static void s_d30v_align
PARAMS ((int));
129 static void s_d30v_text
PARAMS ((int));
130 static void s_d30v_data
PARAMS ((int));
131 static void s_d30v_section
PARAMS ((int));
133 struct option md_longopts
[] = {
134 {NULL
, no_argument
, NULL
, 0}
136 size_t md_longopts_size
= sizeof(md_longopts
);
139 /* The target specific pseudo-ops which we support. */
140 const pseudo_typeS md_pseudo_table
[] =
143 { "hword", cons
, 2 },
144 { "align", s_d30v_align
, 0 },
145 { "text", s_d30v_text
, 0 },
146 { "data", s_d30v_data
, 0 },
147 { "section", s_d30v_section
, 0 },
148 { "section.s", s_d30v_section
, 0 },
149 { "sect", s_d30v_section
, 0 },
150 { "sect.s", s_d30v_section
, 0 },
154 /* Opcode hash table. */
155 static struct hash_control
*d30v_hash
;
157 /* reg_name_search does a binary search of the pre_defined_registers
158 array to see if "name" is a valid regiter name. Returns the register
159 number from the array on success, or -1 on failure. */
162 reg_name_search (name
)
165 int middle
, low
, high
;
169 high
= reg_name_cnt () - 1;
173 middle
= (low
+ high
) / 2;
174 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
181 if (symbol_find (name
) != NULL
)
183 if (warn_register_name_conflicts
)
184 as_warn (_("Register name %s conflicts with symbol of the same name"),
188 return pre_defined_registers
[middle
].value
;
196 /* register_name() checks the string at input_line_pointer
197 to see if it is a valid register name. */
200 register_name (expressionP
)
201 expressionS
*expressionP
;
204 char c
, *p
= input_line_pointer
;
206 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
213 /* look to see if it's in the register table */
214 reg_number
= reg_name_search (input_line_pointer
);
217 expressionP
->X_op
= O_register
;
218 /* temporarily store a pointer to the string here */
219 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
220 expressionP
->X_add_number
= reg_number
;
221 input_line_pointer
= p
;
231 check_range (num
, bits
, flags
)
239 /* don't bother checking 32-bit values */
243 if (flags
& OPERAND_SHIFT
)
245 /* We know that all shifts are right by three bits.... */
247 if (flags
& OPERAND_SIGNED
)
248 num
= (unsigned long) (((/*signed*/ long) num
) >> 3);
253 if (flags
& OPERAND_SIGNED
)
255 max
= (1 << (bits
- 1))-1;
256 min
= - (1 << (bits
- 1));
257 if (((long)num
> max
) || ((long)num
< min
))
262 max
= (1 << bits
) - 1;
264 if ((num
> max
) || (num
< min
))
272 md_show_usage (stream
)
275 fprintf (stream
, _("\nD30V options:\n\
276 -O Make adjacent short instructions parallel if possible.\n\
277 -n Warn about all NOPs inserted by the assembler.\n\
278 -N Warn about NOPs inserted after word multiplies.\n\
279 -c Warn about symbols whoes names match register names.\n\
280 -C Opposite of -C. -c is the default.\n"));
284 md_parse_option (c
, arg
)
290 /* Optimize. Will attempt to parallelize operations */
295 /* Warn about all NOPS that the assembler inserts. */
300 /* Warn about the NOPS that the assembler inserts because of the
303 warn_nops
= NOP_MULTIPLY
;
307 warn_register_name_conflicts
= 1;
311 warn_register_name_conflicts
= 0;
321 md_undefined_symbol (name
)
327 /* Turn a string in input_line_pointer into a floating point constant of type
328 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
329 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
332 md_atof (type
, litP
, sizeP
)
338 LITTLENUM_TYPE words
[4];
352 return _("bad call to md_atof");
355 t
= atof_ieee (input_line_pointer
, type
, words
);
357 input_line_pointer
= t
;
361 for (i
= 0; i
< prec
; i
++)
363 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
370 md_convert_frag (abfd
, sec
, fragP
)
379 md_section_align (seg
, addr
)
383 int align
= bfd_get_section_alignment (stdoutput
, seg
);
384 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
391 struct d30v_opcode
*opcode
;
392 d30v_hash
= hash_new ();
394 /* Insert opcode names into a hash table. */
395 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
396 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
399 FixUps
[0].next
= &FixUps
[1];
400 FixUps
[1].next
= &FixUps
[0];
402 d30v_current_align_seg
= now_seg
;
406 /* this function removes the postincrement or postdecrement
407 operator ( '+' or '-' ) from an expression */
409 static int postfix (p
)
412 while (*p
!= '-' && *p
!= '+')
414 if (*p
==0 || *p
=='\n' || *p
=='\r' || *p
==' ' || *p
==',')
434 static bfd_reloc_code_real_type
435 get_reloc (op
, rel_flag
)
436 struct d30v_operand
*op
;
442 if (op
->flags
& OPERAND_SHIFT
)
443 return BFD_RELOC_D30V_9_PCREL
;
445 return BFD_RELOC_D30V_6
;
448 if (!(op
->flags
& OPERAND_SHIFT
))
449 as_warn (_("unexpected 12-bit reloc type"));
450 if (rel_flag
== RELOC_PCREL
)
451 return BFD_RELOC_D30V_15_PCREL
;
453 return BFD_RELOC_D30V_15
;
455 if (!(op
->flags
& OPERAND_SHIFT
))
456 as_warn (_("unexpected 18-bit reloc type"));
457 if (rel_flag
== RELOC_PCREL
)
458 return BFD_RELOC_D30V_21_PCREL
;
460 return BFD_RELOC_D30V_21
;
462 if (rel_flag
== RELOC_PCREL
)
463 return BFD_RELOC_D30V_32_PCREL
;
465 return BFD_RELOC_D30V_32
;
471 /* get_operands parses a string of operands and returns
472 an array of expressions */
475 get_operands (exp
, cmp_hack
)
479 char *p
= input_line_pointer
;
485 exp
[numops
].X_op
= O_absent
;
486 exp
[numops
++].X_add_number
= cmp_hack
- 1;
491 while (*p
== ' ' || *p
== '\t' || *p
== ',')
493 if (*p
==0 || *p
=='\n' || *p
=='\r')
499 exp
[numops
].X_op
= O_absent
;
503 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
509 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
513 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
522 /* just skip the trailing paren */
527 input_line_pointer
= p
;
529 /* check to see if it might be a register name */
530 if (!register_name (&exp
[numops
]))
532 /* parse as an expression */
533 expression (&exp
[numops
]);
536 if (exp
[numops
].X_op
== O_illegal
)
537 as_bad (_("illegal operand"));
538 else if (exp
[numops
].X_op
== O_absent
)
539 as_bad (_("missing operand"));
542 p
= input_line_pointer
;
546 case -1: /* postdecrement mode */
547 exp
[numops
].X_op
= O_absent
;
548 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
550 case 1: /* postincrement mode */
551 exp
[numops
].X_op
= O_absent
;
552 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
558 exp
[numops
].X_op
= 0;
562 /* build_insn generates the instruction. It does everything */
563 /* but write the FM bits. */
566 build_insn (opcode
, opers
)
567 struct d30v_insn
*opcode
;
570 int i
, length
, bits
, shift
, flags
;
571 unsigned int number
, id
=0;
573 struct d30v_opcode
*op
= opcode
->op
;
574 struct d30v_format
*form
= opcode
->form
;
576 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
578 for (i
=0; form
->operands
[i
]; i
++)
580 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
582 /* must be a register or number */
583 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
584 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
587 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
588 if (flags
& OPERAND_SHIFT
)
591 length
= d30v_operand_table
[form
->operands
[i
]].length
;
592 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
593 if (opers
[i
].X_op
!= O_symbol
)
594 number
= opers
[i
].X_add_number
;
597 if (flags
& OPERAND_REG
)
599 /* check for mvfsys or mvtsys control registers */
600 if (flags
& OPERAND_CONTROL
&& (number
& 0x7f) > MAX_CONTROL_REG
)
603 id
= (number
& 0x7f) - MAX_CONTROL_REG
;
606 else if (number
& OPERAND_FLAG
)
608 id
= 3; /* number is a flag register */
612 else if (flags
& OPERAND_SPECIAL
)
617 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
619 /* now create a fixup */
621 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
622 as_fatal (_("too many fixups"));
624 fixups
->fix
[fixups
->fc
].reloc
=
625 get_reloc ((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
626 fixups
->fix
[fixups
->fc
].size
= 4;
627 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
628 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
629 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D30V_9_PCREL
)
630 fixups
->fix
[fixups
->fc
].pcrel
= RELOC_PCREL
;
632 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
636 /* truncate to the proper number of bits */
637 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
638 as_bad (_("operand out of range: %d"),number
);
640 number
&= 0x7FFFFFFF >> (31 - bits
);
641 if (flags
& OPERAND_SHIFT
)
645 /* it's a LONG instruction */
646 insn
|= (number
>> 26); /* top 6 bits */
647 insn
<<= 32; /* shift the first word over */
648 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
649 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
652 insn
|= number
<< shift
;
658 /* write out a long form instruction */
660 write_long (opcode
, insn
, fx
)
661 struct d30v_insn
*opcode
;
666 char *f
= frag_more (8);
669 d30v_number_to_chars (f
, insn
, 8);
671 for (i
=0; i
< fx
->fc
; i
++)
673 if (fx
->fix
[i
].reloc
)
675 where
= f
- frag_now
->fr_literal
;
676 fix_new_exp (frag_now
,
688 /* Write out a short form instruction by itself. */
690 write_1_short (opcode
, insn
, fx
, use_sequential
)
691 struct d30v_insn
*opcode
;
696 char *f
= frag_more (8);
699 if (warn_nops
== NOP_ALL
)
700 as_warn (_("%s NOP inserted"), use_sequential
?
701 _("sequential") : _("parallel"));
703 /* The other container needs to be NOP. */
706 /* Use a sequential NOP rather than a parallel one,
707 as the current instruction is a FLAG_MUL32 type one
708 and the next instruction is a load. */
710 /* According to 4.3.1: for FM=01, sub-instructions performed
711 only by IU cannot be encoded in L-container. */
713 if (opcode
->op
->unit
== IU
)
714 insn
|= FM10
| NOP_LEFT
; /* right then left */
716 insn
= FM01
| (insn
<< 32) | NOP_RIGHT
; /* left then right */
720 /* According to 4.3.1: for FM=00, sub-instructions performed
721 only by IU cannot be encoded in L-container. */
723 if (opcode
->op
->unit
== IU
)
724 insn
|= FM00
| NOP_LEFT
; /* right container */
726 insn
= FM00
| (insn
<< 32) | NOP_RIGHT
; /* left container */
729 d30v_number_to_chars (f
, insn
, 8);
731 for (i
=0; i
< fx
->fc
; i
++)
733 if (fx
->fix
[i
].reloc
)
735 where
= f
- frag_now
->fr_literal
;
736 fix_new_exp (frag_now
,
747 /* Write out a short form instruction if possible; */
748 /* return number of instructions not written out. */
750 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
751 struct d30v_insn
*opcode1
, *opcode2
;
752 long long insn1
, insn2
;
753 exec_type_enum exec_type
;
756 long long insn
= NOP2
;
760 if (exec_type
== EXEC_SEQ
761 && (opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
))
762 && ((opcode1
->ecc
== ECC_AL
) || ! Optimizing
))
764 /* Unconditional branches kill instructions in the right bin.
765 Conditional branches don't always but if we are not
766 optimizing, then we want to produce an error about such
767 constructs. For the purposes of this test, subroutine
768 calls are considered to be branches. */
769 write_1_short (opcode1
, insn1
, fx
->next
, false);
773 /* Note: we do not have to worry about subroutine calls occuring
774 in the right hand container. The return address is always
775 aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
779 case EXEC_UNKNOWN
: /* Order not specified. */
781 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
)
782 && ! ( (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
783 || opcode1
->op
->unit
== MU
)
785 ( opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
786 || opcode2
->op
->unit
== MU
)))
789 exec_type
= EXEC_PARALLEL
;
791 if (opcode1
->op
->unit
== IU
792 || opcode2
->op
->unit
== MU
793 || opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
794 insn
= FM00
| (insn2
<< 32) | insn1
;
797 insn
= FM00
| (insn1
<< 32) | insn2
;
801 else if (opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)
802 && ((opcode1
->ecc
== ECC_AL
) || ! Optimizing
))
804 /* We must emit branch type instruction on its own with
805 nothing in the right container. */
806 write_1_short (opcode1
, insn1
, fx
->next
, false);
809 else if (opcode1
->op
->unit
== IU
810 || (opcode1
->op
->unit
== EITHER
811 && opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
))
813 /* reverse sequential */
814 insn
= FM10
| (insn2
<< 32) | insn1
;
815 exec_type
= EXEC_REVSEQ
;
820 insn
= FM01
| (insn1
<< 32) | insn2
;
822 exec_type
= EXEC_SEQ
;
826 case EXEC_PARALLEL
: /* parallel */
827 flag_explicitly_parallel
= flag_xp_state
;
828 if (! parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
829 as_fatal (_("Instructions may not be executed in parallel"));
830 else if (opcode1
->op
->unit
== IU
)
832 if (opcode2
->op
->unit
== IU
)
833 as_fatal (_("Two IU instructions may not be executed in parallel"));
834 as_warn (_("Swapping instruction order"));
835 insn
= FM00
| (insn2
<< 32) | insn1
;
837 else if (opcode2
->op
->unit
== MU
)
839 if (opcode1
->op
->unit
== MU
)
840 as_fatal (_("Two MU instructions may not be executed in parallel"));
841 else if (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
)
842 as_warn (_("Executing %s in IU may not work"), opcode1
->op
->name
);
843 as_warn (_("Swapping instruction order"));
844 insn
= FM00
| (insn2
<< 32) | insn1
;
848 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
849 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
851 insn
= FM00
| (insn1
<< 32) | insn2
;
854 flag_explicitly_parallel
= 0;
857 case EXEC_SEQ
: /* sequential */
858 if (opcode1
->op
->unit
== IU
)
859 as_fatal (_("IU instruction may not be in the left container"));
860 if (prev_left_kills_right_p
)
861 as_warn (_("special left instruction `%s' kills instruction "
862 "`%s' in right container"),
863 opcode1
->op
->name
, opcode2
->op
->name
);
864 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
865 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
866 insn
= FM01
| (insn1
<< 32) | insn2
;
870 case EXEC_REVSEQ
: /* reverse sequential */
871 if (opcode2
->op
->unit
== MU
)
872 as_fatal (_("MU instruction may not be in the right container"));
873 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
874 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
875 insn
= FM10
| (insn1
<< 32) | insn2
;
880 as_fatal (_("unknown execution type passed to write_2_short()"));
883 /* printf ("writing out %llx\n",insn); */
885 d30v_number_to_chars (f
, insn
, 8);
887 /* If the previous instruction was a 32-bit multiply but it is put into a
888 parallel container, mark the current instruction as being a 32-bit
890 if (prev_mul32_p
&& exec_type
== EXEC_PARALLEL
)
895 for (i
=0; i
< fx
->fc
; i
++)
897 if (fx
->fix
[i
].reloc
)
899 where
= (f
- frag_now
->fr_literal
) + 4*j
;
901 fix_new_exp (frag_now
,
918 /* Check 2 instructions and determine if they can be safely */
919 /* executed in parallel. Returns 1 if they can be. */
921 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
922 struct d30v_insn
*op1
, *op2
;
923 unsigned long insn1
, insn2
;
924 exec_type_enum exec_type
;
926 int i
, j
, shift
, regno
, bits
, ecc
;
927 unsigned long flags
, mask
, flags_set1
, flags_set2
, flags_used1
, flags_used2
;
928 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3], flag_reg
[2];
929 struct d30v_format
*f
;
930 struct d30v_opcode
*op
;
932 /* section 4.3: both instructions must not be IU or MU only */
933 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
934 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
937 /* first instruction must not be a jump to safely optimize, unless this
938 is an explicit parallel operation. */
939 if (exec_type
!= EXEC_PARALLEL
940 && (op1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)))
943 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
944 then it is safe to allow the two to be done as parallel ops, since only
945 one will ever be executed at a time. */
946 if ((op1
->ecc
== ECC_TX
&& op2
->ecc
== ECC_FX
)
947 || (op1
->ecc
== ECC_FX
&& op2
->ecc
== ECC_TX
)
948 || (op1
->ecc
== ECC_XT
&& op2
->ecc
== ECC_XF
)
949 || (op1
->ecc
== ECC_XF
&& op2
->ecc
== ECC_XT
))
954 [2] a0, a1, flag registers */
956 for (j
= 0; j
< 2; j
++)
973 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
974 mod_reg
[j
][2] = (op
->flags_set
& FLAG_ALL
);
975 used_reg
[j
][0] = used_reg
[j
][1] = 0;
976 used_reg
[j
][2] = (op
->flags_used
& FLAG_ALL
);
978 /* BSR/JSR always sets R62 */
979 if (op
->flags_used
& FLAG_JSR
)
980 mod_reg
[j
][1] = (1L << (62-32));
982 /* conditional execution affects the flags_used */
987 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_0
;
992 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_1
;
997 used_reg
[j
][2] |= flag_reg
[j
] = (FLAG_0
| FLAG_1
);
1001 for (i
= 0; f
->operands
[i
]; i
++)
1003 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
1004 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
1005 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
1009 mask
= 0x7FFFFFFF >> (31 - bits
);
1011 if ((flags
& OPERAND_PLUS
) || (flags
& OPERAND_MINUS
))
1013 /* this is a post-increment or post-decrement */
1014 /* the previous register needs to be marked as modified */
1016 shift
= 12 - d30v_operand_table
[f
->operands
[i
-1]].position
;
1017 regno
= (ins
>> shift
) & 0x3f;
1019 mod_reg
[j
][1] |= 1L << (regno
- 32);
1021 mod_reg
[j
][0] |= 1L << regno
;
1023 else if (flags
& OPERAND_REG
)
1025 regno
= (ins
>> shift
) & mask
;
1026 /* the memory write functions don't have a destination register */
1027 if ((flags
& OPERAND_DEST
) && !(op
->flags_set
& FLAG_MEM
))
1029 /* MODIFIED registers and flags */
1030 if (flags
& OPERAND_ACC
)
1033 mod_reg
[j
][2] |= FLAG_A0
;
1034 else if (regno
== 1)
1035 mod_reg
[j
][2] |= FLAG_A1
;
1039 else if (flags
& OPERAND_FLAG
)
1040 mod_reg
[j
][2] |= 1L << regno
;
1041 else if (!(flags
& OPERAND_CONTROL
))
1045 /* need to check if there are two destination */
1046 /* registers, for example ld2w */
1047 if (flags
& OPERAND_2REG
)
1052 for (r
= regno
; r
<= regno
+ z
; r
++)
1055 mod_reg
[j
][1] |= 1L << (r
- 32);
1057 mod_reg
[j
][0] |= 1L << r
;
1063 /* USED, but not modified registers and flags */
1064 if (flags
& OPERAND_ACC
)
1067 used_reg
[j
][2] |= FLAG_A0
;
1068 else if (regno
== 1)
1069 used_reg
[j
][2] |= FLAG_A1
;
1073 else if (flags
& OPERAND_FLAG
)
1074 used_reg
[j
][2] |= 1L << regno
;
1075 else if (!(flags
& OPERAND_CONTROL
))
1079 /* need to check if there are two source */
1080 /* registers, for example st2w */
1081 if (flags
& OPERAND_2REG
)
1086 for (r
= regno
; r
<= regno
+ z
; r
++)
1089 used_reg
[j
][1] |= 1L << (r
- 32);
1091 used_reg
[j
][0] |= 1L << r
;
1099 flags_set1
= op1
->op
->flags_set
;
1100 flags_set2
= op2
->op
->flags_set
;
1101 flags_used1
= op1
->op
->flags_used
;
1102 flags_used2
= op2
->op
->flags_used
;
1104 /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */
1105 if (((flags_set1
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1106 && (flags_used2
& FLAG_ADDSUBppp
) != 0)
1107 || ((flags_set2
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1108 && (flags_used1
& FLAG_ADDSUBppp
) != 0))
1111 /* Load instruction combined with half-word multiply is illegal. */
1112 if (((flags_used1
& FLAG_MEM
) != 0 && (flags_used2
& FLAG_MUL16
))
1113 || ((flags_used2
& FLAG_MEM
) != 0 && (flags_used1
& FLAG_MUL16
)))
1116 /* Specifically allow add || add by removing carry, overflow bits dependency.
1117 This is safe, even if an addc follows since the IU takes the argument in
1118 the right container, and it writes its results last.
1119 However, don't paralellize add followed by addc or sub followed by
1122 if (mod_reg
[0][2] == FLAG_CVVA
&& mod_reg
[1][2] == FLAG_CVVA
1123 && (used_reg
[0][2] & ~flag_reg
[0]) == 0
1124 && (used_reg
[1][2] & ~flag_reg
[1]) == 0
1125 && op1
->op
->unit
== EITHER
&& op2
->op
->unit
== EITHER
)
1127 mod_reg
[0][2] = mod_reg
[1][2] = 0;
1130 for (j
= 0; j
< 3; j
++)
1132 /* If the second instruction depends on the first, we obviously
1133 cannot parallelize. Note, the mod flag implies use, so
1134 check that as well. */
1135 /* If flag_explicitly_parallel is set, then the case of the
1136 second instruction using a register the first instruction
1137 modifies is assumed to be okay; we trust the human. We
1138 don't trust the human if both instructions modify the same
1139 register but we do trust the human if they modify the same
1141 if (flag_explicitly_parallel
)
1143 if ((j
< 2) && (mod_reg
[0][j
] & mod_reg
[1][j
]) != 0)
1147 if ((mod_reg
[0][j
] & (mod_reg
[1][j
] | used_reg
[1][j
])) != 0)
1155 /* This is the main entry point for the machine-dependent assembler. str points to a
1156 machine-dependent instruction. This function is supposed to emit the frags/bytes
1157 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
1158 and leaves the difficult stuff to do_assemble(). */
1160 static long long prev_insn
= -1;
1161 static struct d30v_insn prev_opcode
;
1162 static subsegT prev_subseg
;
1163 static segT prev_seg
= 0;
1169 struct d30v_insn opcode
;
1171 exec_type_enum extype
= EXEC_UNKNOWN
; /* execution type; parallel, etc */
1172 static exec_type_enum etype
= EXEC_UNKNOWN
; /* saved extype. used for multiline instructions */
1175 if ((prev_insn
!= -1) && prev_seg
1176 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1177 d30v_cleanup (false);
1179 if (d30v_current_align
< 3)
1180 d30v_align (3, NULL
, d30v_last_label
);
1181 else if (d30v_current_align
> 3)
1182 d30v_current_align
= 3;
1183 d30v_last_label
= NULL
;
1185 flag_explicitly_parallel
= 0;
1187 if (etype
== EXEC_UNKNOWN
)
1189 /* look for the special multiple instruction separators */
1190 str2
= strstr (str
, "||");
1193 extype
= EXEC_PARALLEL
;
1198 str2
= strstr (str
, "->");
1203 str2
= strstr (str
, "<-");
1205 extype
= EXEC_REVSEQ
;
1208 /* str2 points to the separator, if one */
1213 /* if two instructions are present and we already have one saved
1214 then first write it out */
1215 d30v_cleanup (false);
1217 /* Assemble first instruction and save it. */
1218 prev_insn
= do_assemble (str
, &prev_opcode
, 1, 0);
1219 if (prev_insn
== -1)
1220 as_fatal (_("Cannot assemble instruction"));
1221 if (prev_opcode
.form
->form
>= LONG
)
1222 as_fatal (_("First opcode is long. Unable to mix instructions as specified."));
1223 fixups
= fixups
->next
;
1226 prev_subseg
= now_subseg
;
1230 insn
= do_assemble (str
, &opcode
,
1231 (extype
!= EXEC_UNKNOWN
|| etype
!= EXEC_UNKNOWN
),
1232 extype
== EXEC_PARALLEL
);
1235 if (extype
!= EXEC_UNKNOWN
)
1240 as_fatal (_("Cannot assemble instruction"));
1243 if (etype
!= EXEC_UNKNOWN
)
1246 etype
= EXEC_UNKNOWN
;
1249 /* Word multiply instructions must not be followed by either a load or a
1250 16-bit multiply instruction in the next cycle. */
1251 if ( (extype
!= EXEC_REVSEQ
)
1253 && (opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1255 /* However, load and multiply should able to be combined in a parallel
1256 operation, so check for that first. */
1258 && (opcode
.op
->flags_used
& FLAG_MEM
)
1259 && opcode
.form
->form
< LONG
1260 && (extype
== EXEC_PARALLEL
|| (Optimizing
&& extype
== EXEC_UNKNOWN
))
1261 && parallel_ok (&prev_opcode
, (long)prev_insn
,
1262 &opcode
, (long)insn
, extype
)
1263 && write_2_short (&prev_opcode
, (long)prev_insn
,
1264 &opcode
, (long)insn
, extype
, fixups
) == 0)
1266 /* no instructions saved */
1272 /* Can't parallelize, flush previous instruction and emit a word of NOPS,
1273 unless the previous instruction is a NOP, in which case just flush it,
1274 as this will generate a word of NOPs for us. */
1276 if (prev_insn
!= -1 && (strcmp (prev_opcode
.op
->name
, "nop") == 0))
1277 d30v_cleanup (false);
1282 if (prev_insn
!= -1)
1283 d30v_cleanup (true);
1287 d30v_number_to_chars (f
, NOP2
, 8);
1289 if (warn_nops
== NOP_ALL
|| warn_nops
== NOP_MULTIPLY
)
1291 if (opcode
.op
->flags_used
& FLAG_MEM
)
1292 as_warn (_("word of NOPs added between word multiply and load"));
1294 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1299 extype
= EXEC_UNKNOWN
;
1302 else if ( (extype
== EXEC_REVSEQ
)
1304 && (prev_opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1306 /* Can't parallelize, flush current instruction and add a sequential NOP. */
1307 write_1_short (& opcode
, (long) insn
, fixups
->next
->next
, true);
1309 /* Make the previous instruction the current one. */
1310 extype
= EXEC_UNKNOWN
;
1313 now_subseg
= prev_subseg
;
1315 cur_mul32_p
= prev_mul32_p
;
1317 memcpy (&opcode
, &prev_opcode
, sizeof (prev_opcode
));
1320 /* If this is a long instruction, write it and any previous short instruction. */
1321 if (opcode
.form
->form
>= LONG
)
1323 if (extype
!= EXEC_UNKNOWN
)
1324 as_fatal (_("Instruction uses long version, so it cannot be mixed as specified"));
1325 d30v_cleanup (false);
1326 write_long (& opcode
, insn
, fixups
);
1329 else if ((prev_insn
!= -1) &&
1331 (& prev_opcode
, (long) prev_insn
, & opcode
, (long) insn
, extype
, fixups
) == 0))
1333 /* No instructions saved. */
1338 if (extype
!= EXEC_UNKNOWN
)
1339 as_fatal (_("Unable to mix instructions as specified"));
1341 /* Save off last instruction so it may be packed on next pass. */
1342 memcpy (&prev_opcode
, &opcode
, sizeof (prev_opcode
));
1345 prev_subseg
= now_subseg
;
1346 fixups
= fixups
->next
;
1347 prev_mul32_p
= cur_mul32_p
;
1352 /* do_assemble assembles a single instruction and returns an opcode */
1353 /* it returns -1 (an invalid opcode) on error */
1356 do_assemble (str
, opcode
, shortp
, is_parallel
)
1358 struct d30v_insn
*opcode
;
1362 unsigned char *op_start
, *save
;
1363 unsigned char *op_end
;
1365 int cmp_hack
, nlen
= 0, fsize
= (shortp
? FORCE_SHORT
: 0);
1366 expressionS myops
[6];
1369 /* Drop leading whitespace */
1373 /* find the opcode end */
1374 for (op_start
= op_end
= (unsigned char *) (str
);
1378 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1381 name
[nlen
] = tolower (op_start
[nlen
]);
1390 /* if there is an execution condition code, handle it */
1394 while ( (i
< ECC_MAX
) && strncasecmp (d30v_ecc_names
[i
], op_end
+ 1, 2))
1400 strncpy (tmp
, op_end
+ 1, 2);
1402 as_fatal (_("unknown condition code: %s"),tmp
);
1405 /* printf("condition code=%d\n",i); */
1410 opcode
->ecc
= ECC_AL
;
1413 /* CMP and CMPU change their name based on condition codes */
1414 if (!strncmp (name
, "cmp", 3))
1417 char **str
= (char **)d30v_cc_names
;
1423 for (i
=1; *str
&& strncmp (*str
, & name
[p
], 2); i
++, str
++)
1426 /* cmpu only supports some condition codes */
1432 as_fatal (_("cmpu doesn't support condition code %s"),&name
[p
]);
1439 as_fatal (_("unknown condition code: %s"),&name
[p
]);
1448 /* printf("cmp_hack=%d\n",cmp_hack); */
1450 /* need to look for .s or .l */
1451 if (name
[nlen
-2] == '.')
1453 switch (name
[nlen
-1])
1456 fsize
= FORCE_SHORT
;
1465 /* find the first opcode with the proper name */
1466 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1467 if (opcode
->op
== NULL
)
1468 as_fatal (_("unknown opcode: %s"),name
);
1470 save
= input_line_pointer
;
1471 input_line_pointer
= op_end
;
1472 while (!(opcode
->form
= find_format (opcode
->op
, myops
, fsize
, cmp_hack
)))
1475 if (strcmp (opcode
->op
->name
, name
))
1476 as_fatal (_("operands for opcode `%s' do not match any valid format"), name
);
1478 input_line_pointer
= save
;
1480 insn
= build_insn (opcode
, myops
);
1482 /* Propigate multiply status */
1485 if (is_parallel
&& prev_mul32_p
)
1489 prev_mul32_p
= cur_mul32_p
;
1490 cur_mul32_p
= (opcode
->op
->flags_used
& FLAG_MUL32
) != 0;
1494 /* Propagate left_kills_right status */
1497 prev_left_kills_right_p
= cur_left_kills_right_p
;
1499 if (opcode
->op
->flags_set
& FLAG_LKR
)
1501 cur_left_kills_right_p
= 1;
1503 if (strcmp (opcode
->op
->name
, "mvtsys") == 0)
1505 /* Left kills right for only mvtsys only for PSW/PSWH/PSWL/flags target. */
1506 if ((myops
[0].X_op
== O_register
) &&
1507 ((myops
[0].X_add_number
== OPERAND_CONTROL
) || /* psw */
1508 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+2) || /* pswh */
1509 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+1) || /* pswl */
1510 (myops
[0].X_add_number
== OPERAND_FLAG
+0) || /* f0 */
1511 (myops
[0].X_add_number
== OPERAND_FLAG
+1) || /* f1 */
1512 (myops
[0].X_add_number
== OPERAND_FLAG
+2) || /* f2 */
1513 (myops
[0].X_add_number
== OPERAND_FLAG
+3) || /* f3 */
1514 (myops
[0].X_add_number
== OPERAND_FLAG
+4) || /* f4 */
1515 (myops
[0].X_add_number
== OPERAND_FLAG
+5) || /* f5 */
1516 (myops
[0].X_add_number
== OPERAND_FLAG
+6) || /* f6 */
1517 (myops
[0].X_add_number
== OPERAND_FLAG
+7))) /* f7 */
1519 cur_left_kills_right_p
= 1;
1523 /* Other mvtsys target registers don't kill right instruction. */
1524 cur_left_kills_right_p
= 0;
1529 cur_left_kills_right_p
= 0;
1537 /* find_format() gets a pointer to an entry in the format table.
1538 It must look at all formats for an opcode and use the operands
1539 to choose the correct one. Returns NULL on error. */
1541 static struct d30v_format
*
1542 find_format (opcode
, myops
, fsize
, cmp_hack
)
1543 struct d30v_opcode
*opcode
;
1544 expressionS myops
[];
1548 int numops
, match
, index
, i
=0, j
, k
;
1549 struct d30v_format
*fm
;
1551 /* Get all the operands and save them as expressions. */
1552 numops
= get_operands (myops
, cmp_hack
);
1554 while ((index
= opcode
->format
[i
++]) != 0)
1556 if (fsize
== FORCE_SHORT
&& index
>= LONG
)
1559 if (fsize
== FORCE_LONG
&& index
< LONG
)
1562 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1564 while (fm
->form
== index
)
1567 /* Now check the operands for compatibility. */
1568 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1570 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1571 int bits
= d30v_operand_table
[fm
->operands
[j
]].bits
;
1572 int X_op
= myops
[j
].X_op
;
1573 int num
= myops
[j
].X_add_number
;
1575 if (flags
& OPERAND_SPECIAL
)
1577 else if (X_op
== O_illegal
)
1579 else if (flags
& OPERAND_REG
)
1581 if (X_op
!= O_register
1582 || ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
))
1583 || (!(flags
& OPERAND_ACC
) && (num
& OPERAND_ACC
))
1584 || ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
))
1585 || (!(flags
& OPERAND_FLAG
) && (num
& OPERAND_FLAG
))
1586 || ((flags
& OPERAND_CONTROL
)
1587 && !(num
& (OPERAND_CONTROL
| OPERAND_FLAG
))))
1592 else if (((flags
& OPERAND_MINUS
)
1593 && (X_op
!= O_absent
|| num
!= OPERAND_MINUS
))
1594 || ((flags
& OPERAND_PLUS
)
1595 && (X_op
!= O_absent
|| num
!= OPERAND_PLUS
))
1596 || ((flags
& OPERAND_ATMINUS
)
1597 && (X_op
!= O_absent
|| num
!= OPERAND_ATMINUS
))
1598 || ((flags
& OPERAND_ATPAR
)
1599 && (X_op
!= O_absent
|| num
!= OPERAND_ATPAR
))
1600 || ((flags
& OPERAND_ATSIGN
)
1601 && (X_op
!= O_absent
|| num
!= OPERAND_ATSIGN
)))
1605 else if (flags
& OPERAND_NUM
)
1607 /* A number can be a constant or symbol expression. */
1609 /* If we have found a register name, but that name also
1610 matches a symbol, then re-parse the name as an expression. */
1611 if (X_op
== O_register
1612 && symbol_find ((char *) myops
[j
].X_op_symbol
))
1614 input_line_pointer
= (char *) myops
[j
].X_op_symbol
;
1615 expression (& myops
[j
]);
1618 /* Turn an expression into a symbol for later resolution. */
1619 if (X_op
!= O_absent
&& X_op
!= O_constant
1620 && X_op
!= O_symbol
&& X_op
!= O_register
1623 symbolS
*sym
= make_expr_symbol (&myops
[j
]);
1624 myops
[j
].X_op
= X_op
= O_symbol
;
1625 myops
[j
].X_add_symbol
= sym
;
1626 myops
[j
].X_add_number
= num
= 0;
1629 if (fm
->form
>= LONG
)
1631 /* If we're testing for a LONG format, either fits. */
1632 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1635 else if (fm
->form
< LONG
1636 && ((fsize
== FORCE_SHORT
&& X_op
== O_symbol
)
1637 || (fm
->form
== SHORT_D2
&& j
== 0)))
1639 /* This is the tricky part. Will the constant or symbol
1640 fit into the space in the current format? */
1641 else if (X_op
== O_constant
)
1643 if (check_range (num
, bits
, flags
))
1646 else if (X_op
== O_symbol
1647 && S_IS_DEFINED (myops
[j
].X_add_symbol
)
1648 && S_GET_SEGMENT (myops
[j
].X_add_symbol
) == now_seg
1649 && opcode
->reloc_flag
== RELOC_PCREL
)
1651 /* If the symbol is defined, see if the value will fit
1652 into the form we're considering. */
1656 /* Calculate the current address by running through the
1657 previous frags and adding our current offset. */
1659 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1660 value
+= f
->fr_fix
+ f
->fr_offset
;
1661 value
= (S_GET_VALUE (myops
[j
].X_add_symbol
) - value
1662 - (obstack_next_free (&frchain_now
->frch_obstack
)
1663 - frag_now
->fr_literal
));
1664 if (check_range (value
, bits
, flags
))
1671 /* printf("through the loop: match=%d\n",match); */
1672 /* We're only done if the operands matched so far AND there
1673 are no more to check. */
1674 if (match
&& myops
[j
].X_op
== 0)
1676 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1678 /* printf("trying another format: i=%d\n",i); */
1683 /* if while processing a fixup, a reloc really needs to be created */
1684 /* then it is done here */
1687 tc_gen_reloc (seg
, fixp
)
1692 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1693 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1694 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1695 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1696 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1698 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1699 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1702 reloc
->addend
= fixp
->fx_addnumber
;
1707 md_estimate_size_before_relax (fragp
, seg
)
1716 md_pcrel_from_section (fixp
, sec
)
1720 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1721 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1723 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1727 md_apply_fix3 (fixp
, valuep
, seg
)
1733 unsigned long insn
, insn2
;
1736 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1741 else if (fixp
->fx_pcrel
)
1747 value
= fixp
->fx_offset
;
1748 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1750 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1751 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1754 /* We don't actually support subtracting a symbol. */
1755 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1756 _("expression too complex"));
1761 /* Fetch the instruction, insert the fully resolved operand
1762 value, and stuff the instruction back again. */
1763 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1764 insn
= bfd_getb32 ((unsigned char *) where
);
1766 switch (fixp
->fx_r_type
)
1769 /* Caused by a bad .byte directive. */
1770 as_fatal (_("line %d: unable to place address of symbol '%s' into a byte"),
1771 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1775 /* Caused by a bad .short directive. */
1776 as_fatal (_("line %d: unable to place address of symbol '%s' into a short"),
1777 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1781 /* Caused by a bad .quad directive. */
1782 as_fatal (_("line %d: unable to place address of symbol '%s' into a .quad"),
1783 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1786 case BFD_RELOC_D30V_6
:
1787 check_size (value
, 6, fixp
->fx_file
, fixp
->fx_line
);
1788 insn
|= value
& 0x3F;
1789 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1792 case BFD_RELOC_D30V_9_PCREL
:
1793 if (fixp
->fx_where
& 0x7)
1798 fixp
->fx_r_type
= BFD_RELOC_D30V_9_PCREL_R
;
1800 check_size (value
, 9, fixp
->fx_file
, fixp
->fx_line
);
1801 insn
|= ((value
>> 3) & 0x3F) << 12;
1802 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1805 case BFD_RELOC_D30V_15
:
1806 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1807 insn
|= (value
>> 3) & 0xFFF;
1808 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1811 case BFD_RELOC_D30V_15_PCREL
:
1812 if (fixp
->fx_where
& 0x7)
1817 fixp
->fx_r_type
= BFD_RELOC_D30V_15_PCREL_R
;
1819 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1820 insn
|= (value
>> 3) & 0xFFF;
1821 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1824 case BFD_RELOC_D30V_21
:
1825 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1826 insn
|= (value
>> 3) & 0x3FFFF;
1827 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1830 case BFD_RELOC_D30V_21_PCREL
:
1831 if (fixp
->fx_where
& 0x7)
1836 fixp
->fx_r_type
= BFD_RELOC_D30V_21_PCREL_R
;
1838 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1839 insn
|= (value
>> 3) & 0x3FFFF;
1840 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1843 case BFD_RELOC_D30V_32
:
1844 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1845 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1846 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1847 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1848 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1849 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1852 case BFD_RELOC_D30V_32_PCREL
:
1853 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1854 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1855 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1856 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1857 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1858 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1862 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1866 as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp
->fx_line
,fixp
->fx_r_type
);
1872 /* d30v_cleanup() is called after the assembler has finished parsing the input
1873 file or after a label is defined. Because the D30V assembler sometimes saves short
1874 instructions to see if it can package them with the next instruction, there may
1875 be a short instruction that still needs written. */
1877 d30v_cleanup (use_sequential
)
1883 if (prev_insn
!= -1)
1886 subseg
= now_subseg
;
1887 subseg_set (prev_seg
, prev_subseg
);
1888 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
, use_sequential
);
1889 subseg_set (seg
, subseg
);
1892 prev_mul32_p
= false;
1898 d30v_number_to_chars (buf
, value
, n
)
1899 char *buf
; /* Return 'nbytes' of chars here. */
1900 long long value
; /* The value of the bits. */
1901 int n
; /* Number of bytes in the output. */
1905 buf
[n
] = value
& 0xff;
1911 /* This function is called at the start of every line. */
1912 /* it checks to see if the first character is a '.' */
1913 /* which indicates the start of a pseudo-op. If it is, */
1914 /* then write out any unwritten instructions */
1919 char *c
= input_line_pointer
;
1921 while (isspace (*c
))
1925 d30v_cleanup (false);
1929 check_size (value
, bits
, file
, line
)
1942 max
= (1 << (bits
- 1)) - 1;
1945 as_bad_where (file
, line
, _("value too large to fit in %d bits"), bits
);
1950 /* d30v_frob_label() is called when after a label is recognized. */
1953 d30v_frob_label (lab
)
1956 /* Emit any pending instructions. */
1957 d30v_cleanup (false);
1959 /* Update the label's address with the current output pointer. */
1960 lab
->sy_frag
= frag_now
;
1961 S_SET_VALUE (lab
, (valueT
) frag_now_fix ());
1963 /* Record this label for future adjustment after we find out what
1964 kind of data it references, and the required alignment therewith. */
1965 d30v_last_label
= lab
;
1968 /* Hook into cons for capturing alignment changes. */
1971 d30v_cons_align (size
)
1977 while ((size
>>= 1) != 0)
1980 if (d30v_current_align
< log_size
)
1981 d30v_align (log_size
, (char *) NULL
, NULL
);
1982 else if (d30v_current_align
> log_size
)
1983 d30v_current_align
= log_size
;
1984 d30v_last_label
= NULL
;
1987 /* Called internally to handle all alignment needs. This takes care
1988 of eliding calls to frag_align if'n the cached current alignment
1989 says we've already got it, as well as taking care of the auto-aligning
1993 d30v_align (n
, pfill
, label
)
1998 /* The front end is prone to changing segments out from under us
1999 temporarily when -g is in effect. */
2000 int switched_seg_p
= (d30v_current_align_seg
!= now_seg
);
2002 /* Do not assume that if 'd30v_current_align >= n' and
2003 '! switched_seg_p' that it is safe to avoid performing
2004 this alignement request. The alignment of the current frag
2005 can be changed under our feet, for example by a .ascii
2006 directive in the source code. cf testsuite/gas/d30v/reloc.s */
2008 d30v_cleanup (false);
2013 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
2015 static char const nop
[4] = { 0x00, 0xf0, 0x00, 0x00 };
2017 /* First, make sure we're on a four-byte boundary, in case
2018 someone has been putting .byte values the text section. */
2019 if (d30v_current_align
< 2 || switched_seg_p
)
2020 frag_align (2, 0, 0);
2021 frag_align_pattern (n
, nop
, sizeof nop
, 0);
2024 frag_align (n
, 0, 0);
2027 frag_align (n
, *pfill
, 0);
2029 if (!switched_seg_p
)
2030 d30v_current_align
= n
;
2035 int label_seen
= false;
2036 struct frag
* old_frag
;
2040 assert (S_GET_SEGMENT (label
) == now_seg
);
2042 old_frag
= label
->sy_frag
;
2043 old_value
= S_GET_VALUE (label
);
2044 new_value
= (valueT
) frag_now_fix ();
2046 /* It is possible to have more than one label at a particular
2047 address, especially if debugging is enabled, so we must
2048 take care to adjust all the labels at this address in this
2049 fragment. To save time we search from the end of the symbol
2050 list, backwards, since the symbols we are interested in are
2051 almost certainly the ones that were most recently added.
2052 Also to save time we stop searching once we have seen at least
2053 one matching label, and we encounter a label that is no longer
2054 in the target fragment. Note, this search is guaranteed to
2055 find at least one match when sym == label, so no special case
2056 code is necessary. */
2057 for (sym
= symbol_lastP
; sym
!= NULL
; sym
= sym
->sy_previous
)
2059 if (sym
->sy_frag
== old_frag
&& S_GET_VALUE (sym
) == old_value
)
2062 sym
->sy_frag
= frag_now
;
2063 S_SET_VALUE (sym
, new_value
);
2065 else if (label_seen
&& sym
->sy_frag
!= old_frag
)
2070 record_alignment (now_seg
, n
);
2073 /* Handle the .align pseudo-op. This aligns to a power of two. We
2074 hook here to latch the current alignment. */
2077 s_d30v_align (ignore
)
2081 char fill
, *pfill
= NULL
;
2082 long max_alignment
= 15;
2084 align
= get_absolute_expression ();
2085 if (align
> max_alignment
)
2087 align
= max_alignment
;
2088 as_warn (_("Alignment too large: %d assumed"), align
);
2092 as_warn (_("Alignment negative: 0 assumed"));
2096 if (*input_line_pointer
== ',')
2098 input_line_pointer
++;
2099 fill
= get_absolute_expression ();
2103 d30v_last_label
= NULL
;
2104 d30v_align (align
, pfill
, NULL
);
2106 demand_empty_rest_of_line ();
2109 /* Handle the .text pseudo-op. This is like the usual one, but it
2110 clears the saved last label and resets known alignment. */
2118 d30v_last_label
= NULL
;
2119 d30v_current_align
= 0;
2120 d30v_current_align_seg
= now_seg
;
2123 /* Handle the .data pseudo-op. This is like the usual one, but it
2124 clears the saved last label and resets known alignment. */
2131 d30v_last_label
= NULL
;
2132 d30v_current_align
= 0;
2133 d30v_current_align_seg
= now_seg
;
2136 /* Handle the .section pseudo-op. This is like the usual one, but it
2137 clears the saved last label and resets known alignment. */
2140 s_d30v_section (ignore
)
2143 obj_elf_section (ignore
);
2144 d30v_last_label
= NULL
;
2145 d30v_current_align
= 0;
2146 d30v_current_align_seg
= now_seg
;