1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
3 Copyright (C) 1997, 1998 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d30v.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "OnN";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
35 #define NOP_MULTIPLY 1
37 static int warn_nops
= 0;
38 static int Optimizing
= 0;
44 typedef enum _exec_type
46 EXEC_UNKNOWN
, /* no order specified */
47 EXEC_PARALLEL
, /* done in parallel (FM=00) */
48 EXEC_SEQ
, /* sequential (FM=01) */
49 EXEC_REVSEQ
/* reverse sequential (FM=10) */
53 #define MAX_INSN_FIXUPS (5)
60 bfd_reloc_code_real_type reloc
;
63 typedef struct _fixups
66 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
70 static Fixups FixUps
[2];
71 static Fixups
*fixups
;
73 /* Whether current and previous instruction is a word multiply. */
77 /* The flag_explicitly_parallel is true iff the instruction being assembled
78 has been explicitly written as a parallel short-instruction pair by the
79 human programmer. It is used in parallel_ok() to distinguish between
80 those dangerous parallelizations attempted by the human, which are to be
81 allowed, and those attempted by the assembler, which are not. It is set
82 from md_assemble(). */
83 static int flag_explicitly_parallel
= 0;
84 static int flag_xp_state
= 0;
87 #define NOP_LEFT ((long long)NOP << 32)
88 #define NOP_RIGHT ((long long)NOP)
89 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
92 static int reg_name_search
PARAMS ((char *name
));
93 static int register_name
PARAMS ((expressionS
*expressionP
));
94 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
95 static int postfix
PARAMS ((char *p
));
96 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
97 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
98 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
,
99 expressionS ops
[],int fsize
, int cmp_hack
));
100 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
101 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
102 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
103 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
104 struct d30v_insn
*opcode2
, long long insn2
, exec_type_enum exec_type
, Fixups
*fx
));
105 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
));
106 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
107 struct d30v_insn
*opcode2
, unsigned long insn2
,
108 exec_type_enum exec_type
));
109 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
110 static void check_size
PARAMS ((long value
, int bits
, char *file
, int line
));
112 struct option md_longopts
[] = {
113 {NULL
, no_argument
, NULL
, 0}
115 size_t md_longopts_size
= sizeof(md_longopts
);
118 /* The target specific pseudo-ops which we support. */
119 const pseudo_typeS md_pseudo_table
[] =
122 { "hword", cons
, 2 },
126 /* Opcode hash table. */
127 static struct hash_control
*d30v_hash
;
129 /* reg_name_search does a binary search of the pre_defined_registers
130 array to see if "name" is a valid regiter name. Returns the register
131 number from the array on success, or -1 on failure. */
134 reg_name_search (name
)
137 int middle
, low
, high
;
141 high
= reg_name_cnt() - 1;
145 middle
= (low
+ high
) / 2;
146 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
152 return pre_defined_registers
[middle
].value
;
158 /* register_name() checks the string at input_line_pointer
159 to see if it is a valid register name */
162 register_name (expressionP
)
163 expressionS
*expressionP
;
166 char c
, *p
= input_line_pointer
;
168 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
175 /* look to see if it's in the register table */
176 reg_number
= reg_name_search (input_line_pointer
);
179 expressionP
->X_op
= O_register
;
180 /* temporarily store a pointer to the string here */
181 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
182 expressionP
->X_add_number
= reg_number
;
183 input_line_pointer
= p
;
193 check_range (num
, bits
, flags
)
201 /* don't bother checking 32-bit values */
205 if (flags
& OPERAND_SIGNED
)
207 max
= (1 << (bits
- 1))-1;
208 min
= - (1 << (bits
- 1));
209 if (((long)num
> max
) || ((long)num
< min
))
214 max
= (1 << bits
) - 1;
216 if ((num
> max
) || (num
< min
))
224 md_show_usage (stream
)
227 fprintf(stream
, (_
"\nD30V options:\n\
228 -O Make adjacent short instructions parallel if possible.\n\
229 -n Warn about all NOPs inserted by the assembler.\n\
230 -N Warn about NOPs inserted after word multiplies.\n"));
234 md_parse_option (c
, arg
)
240 /* Optimize. Will attempt to parallelize operations */
245 /* Warn about all NOPS that the assembler inserts. */
250 /* Warn about the NOPS that the assembler inserts because of the
253 warn_nops
= NOP_MULTIPLY
;
263 md_undefined_symbol (name
)
269 /* Turn a string in input_line_pointer into a floating point constant of type
270 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
271 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
274 md_atof (type
, litP
, sizeP
)
280 LITTLENUM_TYPE words
[4];
294 return _("bad call to md_atof");
297 t
= atof_ieee (input_line_pointer
, type
, words
);
299 input_line_pointer
= t
;
303 for (i
= 0; i
< prec
; i
++)
305 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
312 md_convert_frag (abfd
, sec
, fragP
)
321 md_section_align (seg
, addr
)
325 int align
= bfd_get_section_alignment (stdoutput
, seg
);
326 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
333 struct d30v_opcode
*opcode
;
334 d30v_hash
= hash_new();
336 /* Insert opcode names into a hash table. */
337 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
338 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
341 FixUps
[0].next
= &FixUps
[1];
342 FixUps
[1].next
= &FixUps
[0];
346 /* this function removes the postincrement or postdecrement
347 operator ( '+' or '-' ) from an expression */
349 static int postfix (p
)
352 while (*p
!= '-' && *p
!= '+')
354 if (*p
==0 || *p
=='\n' || *p
=='\r' || *p
==' ' || *p
==',')
374 static bfd_reloc_code_real_type
375 get_reloc (op
, rel_flag
)
376 struct d30v_operand
*op
;
382 if (op
->flags
& OPERAND_SHIFT
)
383 return BFD_RELOC_D30V_9_PCREL
;
385 return BFD_RELOC_D30V_6
;
388 if (!(op
->flags
& OPERAND_SHIFT
))
389 as_warn(_("unexpected 12-bit reloc type"));
390 if (rel_flag
== RELOC_PCREL
)
391 return BFD_RELOC_D30V_15_PCREL
;
393 return BFD_RELOC_D30V_15
;
395 if (!(op
->flags
& OPERAND_SHIFT
))
396 as_warn(_("unexpected 18-bit reloc type"));
397 if (rel_flag
== RELOC_PCREL
)
398 return BFD_RELOC_D30V_21_PCREL
;
400 return BFD_RELOC_D30V_21
;
402 if (rel_flag
== RELOC_PCREL
)
403 return BFD_RELOC_D30V_32_PCREL
;
405 return BFD_RELOC_D30V_32
;
411 /* get_operands parses a string of operands and returns
412 an array of expressions */
415 get_operands (exp
, cmp_hack
)
419 char *p
= input_line_pointer
;
425 exp
[numops
].X_op
= O_absent
;
426 exp
[numops
++].X_add_number
= cmp_hack
- 1;
431 while (*p
== ' ' || *p
== '\t' || *p
== ',')
433 if (*p
==0 || *p
=='\n' || *p
=='\r')
439 exp
[numops
].X_op
= O_absent
;
443 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
449 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
453 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
462 /* just skip the trailing paren */
467 input_line_pointer
= p
;
469 /* check to see if it might be a register name */
470 if (!register_name (&exp
[numops
]))
472 /* parse as an expression */
473 expression (&exp
[numops
]);
476 if (exp
[numops
].X_op
== O_illegal
)
477 as_bad (_("illegal operand"));
478 else if (exp
[numops
].X_op
== O_absent
)
479 as_bad (_("missing operand"));
482 p
= input_line_pointer
;
486 case -1: /* postdecrement mode */
487 exp
[numops
].X_op
= O_absent
;
488 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
490 case 1: /* postincrement mode */
491 exp
[numops
].X_op
= O_absent
;
492 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
498 exp
[numops
].X_op
= 0;
502 /* build_insn generates the instruction. It does everything */
503 /* but write the FM bits. */
506 build_insn (opcode
, opers
)
507 struct d30v_insn
*opcode
;
510 int i
, length
, bits
, shift
, flags
;
511 unsigned int number
, id
=0;
513 struct d30v_opcode
*op
= opcode
->op
;
514 struct d30v_format
*form
= opcode
->form
;
516 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
518 for (i
=0; form
->operands
[i
]; i
++)
520 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
522 /* must be a register or number */
523 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
524 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
527 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
528 if (flags
& OPERAND_SHIFT
)
531 length
= d30v_operand_table
[form
->operands
[i
]].length
;
532 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
533 if (opers
[i
].X_op
!= O_symbol
)
534 number
= opers
[i
].X_add_number
;
537 if (flags
& OPERAND_REG
)
539 /* check for mvfsys or mvtsys control registers */
540 if (flags
& OPERAND_CONTROL
&& (number
& 0x7f) > MAX_CONTROL_REG
)
543 id
= (number
& 0x7f) - MAX_CONTROL_REG
;
546 else if (number
& OPERAND_FLAG
)
548 id
= 3; /* number is a flag register */
552 else if (flags
& OPERAND_SPECIAL
)
557 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
559 /* now create a fixup */
561 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
562 as_fatal (_("too many fixups"));
564 fixups
->fix
[fixups
->fc
].reloc
=
565 get_reloc((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
566 fixups
->fix
[fixups
->fc
].size
= 4;
567 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
568 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
569 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D30V_9_PCREL
)
570 fixups
->fix
[fixups
->fc
].pcrel
= RELOC_PCREL
;
572 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
576 /* truncate to the proper number of bits */
577 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
578 as_bad(_("operand out of range: %d"),number
);
580 number
&= 0x7FFFFFFF >> (31 - bits
);
581 if (flags
& OPERAND_SHIFT
)
585 /* it's a LONG instruction */
586 insn
|= (number
>> 26); /* top 6 bits */
587 insn
<<= 32; /* shift the first word over */
588 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
589 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
592 insn
|= number
<< shift
;
598 /* write out a long form instruction */
600 write_long (opcode
, insn
, fx
)
601 struct d30v_insn
*opcode
;
606 char *f
= frag_more(8);
609 d30v_number_to_chars (f
, insn
, 8);
611 for (i
=0; i
< fx
->fc
; i
++)
613 if (fx
->fix
[i
].reloc
)
615 where
= f
- frag_now
->fr_literal
;
616 fix_new_exp (frag_now
,
628 /* write out a short form instruction by itself */
630 write_1_short (opcode
, insn
, fx
)
631 struct d30v_insn
*opcode
;
635 char *f
= frag_more(8);
638 if (warn_nops
== NOP_ALL
)
639 as_warn (_("NOP inserted"));
641 /* the other container needs to be NOP */
642 /* according to 4.3.1: for FM=00, sub-instructions performed only
643 by IU cannot be encoded in L-container. */
644 if (opcode
->op
->unit
== IU
)
645 insn
|= FM00
| NOP_LEFT
; /* right container */
647 insn
= FM00
| (insn
<< 32) | NOP_RIGHT
; /* left container */
649 d30v_number_to_chars (f
, insn
, 8);
651 for (i
=0; i
< fx
->fc
; i
++)
653 if (fx
->fix
[i
].reloc
)
655 where
= f
- frag_now
->fr_literal
;
656 fix_new_exp (frag_now
,
667 /* write out a short form instruction if possible */
668 /* return number of instructions not written out */
670 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
671 struct d30v_insn
*opcode1
, *opcode2
;
672 long long insn1
, insn2
;
673 exec_type_enum exec_type
;
676 long long insn
= NOP2
;
680 if(exec_type
!= EXEC_PARALLEL
&&
681 ((opcode1
->op
->flags_used
& (FLAG_JSR
| FLAG_DELAY
)) == FLAG_JSR
))
683 /* subroutines must be called from 32-bit boundaries */
684 /* so the return address will be correct */
685 write_1_short (opcode1
, insn1
, fx
->next
);
691 case EXEC_UNKNOWN
: /* order not specified */
692 if (Optimizing
&& parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
695 exec_type
= EXEC_PARALLEL
;
696 if (opcode1
->op
->unit
== IU
)
697 insn
= FM00
| (insn2
<< 32) | insn1
;
698 else if (opcode2
->op
->unit
== MU
)
699 insn
= FM00
| (insn2
<< 32) | insn1
;
702 insn
= FM00
| (insn1
<< 32) | insn2
;
706 else if (opcode1
->op
->unit
== IU
)
708 /* reverse sequential */
709 insn
= FM10
| (insn2
<< 32) | insn1
;
710 exec_type
= EXEC_REVSEQ
;
715 insn
= FM01
| (insn1
<< 32) | insn2
;
717 exec_type
= EXEC_SEQ
;
721 case EXEC_PARALLEL
: /* parallel */
722 flag_explicitly_parallel
= flag_xp_state
;
723 if (! parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
724 as_fatal (_("Instructions may not be executed in parallel"));
725 else if (opcode1
->op
->unit
== IU
)
727 if (opcode2
->op
->unit
== IU
)
728 as_fatal (_("Two IU instructions may not be executed in parallel"));
729 as_warn (_("Swapping instruction order"));
730 insn
= FM00
| (insn2
<< 32) | insn1
;
732 else if (opcode2
->op
->unit
== MU
)
734 if (opcode1
->op
->unit
== MU
)
735 as_fatal (_("Two MU instructions may not be executed in parallel"));
736 as_warn (_("Swapping instruction order"));
737 insn
= FM00
| (insn2
<< 32) | insn1
;
741 insn
= FM00
| (insn1
<< 32) | insn2
;
744 flag_explicitly_parallel
= 0;
747 case EXEC_SEQ
: /* sequential */
748 if (opcode1
->op
->unit
== IU
)
749 as_fatal (_("IU instruction may not be in the left container"));
750 insn
= FM01
| (insn1
<< 32) | insn2
;
754 case EXEC_REVSEQ
: /* reverse sequential */
755 if (opcode2
->op
->unit
== MU
)
756 as_fatal (_("MU instruction may not be in the right container"));
757 insn
= FM10
| (insn1
<< 32) | insn2
;
762 as_fatal(_("unknown execution type passed to write_2_short()"));
765 /* printf("writing out %llx\n",insn); */
767 d30v_number_to_chars (f
, insn
, 8);
769 /* If the previous instruction was a 32-bit multiply but it is put into a
770 parallel container, mark the current instruction as being a 32-bit
772 if (prev_mul32_p
&& exec_type
== EXEC_PARALLEL
)
777 for (i
=0; i
< fx
->fc
; i
++)
779 if (fx
->fix
[i
].reloc
)
781 where
= (f
- frag_now
->fr_literal
) + 4*j
;
783 fix_new_exp (frag_now
,
798 /* Check 2 instructions and determine if they can be safely */
799 /* executed in parallel. Returns 1 if they can be. */
801 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
802 struct d30v_insn
*op1
, *op2
;
803 unsigned long insn1
, insn2
;
804 exec_type_enum exec_type
;
806 int i
, j
, shift
, regno
, bits
, ecc
;
807 unsigned long flags
, mask
, flags_set1
, flags_set2
, flags_used1
, flags_used2
;
808 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3], flag_reg
[2];
809 struct d30v_format
*f
;
810 struct d30v_opcode
*op
;
812 /* section 4.3: both instructions must not be IU or MU only */
813 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
814 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
817 /* first instruction must not be a jump to safely optimize, unless this
818 is an explicit parallel operation. */
819 if (exec_type
!= EXEC_PARALLEL
820 && (op1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)))
823 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
824 then it is safe to allow the two to be done as parallel ops, since only
825 one will ever be executed at a time. */
826 if ((op1
->ecc
== ECC_TX
&& op2
->ecc
== ECC_FX
)
827 || (op1
->ecc
== ECC_FX
&& op2
->ecc
== ECC_TX
)
828 || (op1
->ecc
== ECC_XT
&& op2
->ecc
== ECC_XF
)
829 || (op1
->ecc
== ECC_XF
&& op2
->ecc
== ECC_XT
))
834 [2] a0, a1, flag registers */
836 for (j
= 0; j
< 2; j
++)
853 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
854 mod_reg
[j
][2] = (op
->flags_set
& FLAG_ALL
);
855 used_reg
[j
][0] = used_reg
[j
][1] = 0;
856 used_reg
[j
][2] = (op
->flags_used
& FLAG_ALL
);
858 /* BSR/JSR always sets R62 */
859 if (op
->flags_used
& FLAG_JSR
)
860 mod_reg
[j
][1] = (1L << (62-32));
862 /* conditional execution affects the flags_used */
867 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_0
;
872 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_1
;
877 used_reg
[j
][2] |= flag_reg
[j
] = (FLAG_0
| FLAG_1
);
881 for (i
= 0; f
->operands
[i
]; i
++)
883 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
884 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
885 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
889 mask
= 0x7FFFFFFF >> (31 - bits
);
891 if ((flags
& OPERAND_PLUS
) || (flags
& OPERAND_MINUS
))
893 /* this is a post-increment or post-decrement */
894 /* the previous register needs to be marked as modified */
896 shift
= 12 - d30v_operand_table
[f
->operands
[i
-1]].position
;
897 regno
= (ins
>> shift
) & 0x3f;
899 mod_reg
[j
][1] |= 1L << (regno
- 32);
901 mod_reg
[j
][0] |= 1L << regno
;
903 else if (flags
& OPERAND_REG
)
905 regno
= (ins
>> shift
) & mask
;
906 /* the memory write functions don't have a destination register */
907 if ((flags
& OPERAND_DEST
) && !(op
->flags_set
& FLAG_MEM
))
909 /* MODIFIED registers and flags */
910 if (flags
& OPERAND_ACC
)
913 mod_reg
[j
][2] |= FLAG_A0
;
915 mod_reg
[j
][2] |= FLAG_A1
;
919 else if (flags
& OPERAND_FLAG
)
920 mod_reg
[j
][2] |= 1L << regno
;
921 else if (!(flags
& OPERAND_CONTROL
))
925 /* need to check if there are two destination */
926 /* registers, for example ld2w */
927 if (flags
& OPERAND_2REG
)
932 for (r
= regno
; r
<= regno
+ z
; r
++)
935 mod_reg
[j
][1] |= 1L << (r
- 32);
937 mod_reg
[j
][0] |= 1L << r
;
943 /* USED, but not modified registers and flags */
944 if (flags
& OPERAND_ACC
)
947 used_reg
[j
][2] |= FLAG_A0
;
949 used_reg
[j
][2] |= FLAG_A1
;
953 else if (flags
& OPERAND_FLAG
)
954 used_reg
[j
][2] |= 1L << regno
;
955 else if (!(flags
& OPERAND_CONTROL
))
959 /* need to check if there are two source */
960 /* registers, for example st2w */
961 if (flags
& OPERAND_2REG
)
966 for (r
= regno
; r
<= regno
+ z
; r
++)
969 used_reg
[j
][1] |= 1L << (r
- 32);
971 used_reg
[j
][0] |= 1L << r
;
979 flags_set1
= op1
->op
->flags_set
;
980 flags_set2
= op2
->op
->flags_set
;
981 flags_used1
= op1
->op
->flags_used
;
982 flags_used2
= op2
->op
->flags_used
;
984 /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */
985 if (((flags_set1
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
986 && (flags_used2
& FLAG_ADDSUBppp
) != 0)
987 || ((flags_set2
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
988 && (flags_used1
& FLAG_ADDSUBppp
) != 0))
991 /* Load instruction combined with half-word multiply is illegal. */
992 if (((flags_used1
& FLAG_MEM
) != 0 && (flags_used2
& FLAG_MUL16
))
993 || ((flags_used2
& FLAG_MEM
) != 0 && (flags_used1
& FLAG_MUL16
)))
996 /* Specifically allow add || add by removing carry, overflow bits dependency.
997 This is safe, even if an addc follows since the IU takes the argument in
998 the right container, and it writes its results last.
999 However, don't paralellize add followed by addc or sub followed by
1002 if (mod_reg
[0][2] == FLAG_CVVA
&& mod_reg
[1][2] == FLAG_CVVA
1003 && (used_reg
[0][2] & ~flag_reg
[0]) == 0
1004 && (used_reg
[1][2] & ~flag_reg
[1]) == 0
1005 && op1
->op
->unit
== EITHER
&& op2
->op
->unit
== EITHER
)
1007 mod_reg
[0][2] = mod_reg
[1][2] = 0;
1010 for(j
= 0; j
< 3; j
++)
1012 /* If the second instruction depends on the first, we obviously
1013 cannot parallelize. Note, the mod flag implies use, so
1014 check that as well. */
1015 /* If flag_explicitly_parallel is set, then the case of the
1016 second instruction using a register the first instruction
1017 modifies is assumed to be okay; we trust the human. We
1018 don't trust the human if both instructions modify the same
1019 register but we do trust the human if they modify the same
1021 if (flag_explicitly_parallel
)
1023 if ((j
< 2) && (mod_reg
[0][j
] & mod_reg
[1][j
]) != 0)
1027 if ((mod_reg
[0][j
] & (mod_reg
[1][j
] | used_reg
[1][j
])) != 0)
1036 /* This is the main entry point for the machine-dependent assembler. str points to a
1037 machine-dependent instruction. This function is supposed to emit the frags/bytes
1038 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
1039 and leaves the difficult stuff to do_assemble(). */
1041 static long long prev_insn
= -1;
1042 static struct d30v_insn prev_opcode
;
1043 static subsegT prev_subseg
;
1044 static segT prev_seg
= 0;
1050 struct d30v_insn opcode
;
1052 exec_type_enum extype
= EXEC_UNKNOWN
; /* execution type; parallel, etc */
1053 static exec_type_enum etype
= EXEC_UNKNOWN
; /* saved extype. used for multiline instructions */
1056 if ( (prev_insn
!= -1) && prev_seg
&& ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1059 flag_explicitly_parallel
= 0;
1061 if (etype
== EXEC_UNKNOWN
)
1063 /* look for the special multiple instruction separators */
1064 str2
= strstr (str
, "||");
1067 extype
= EXEC_PARALLEL
;
1072 str2
= strstr (str
, "->");
1077 str2
= strstr (str
, "<-");
1079 extype
= EXEC_REVSEQ
;
1082 /* str2 points to the separator, if one */
1087 /* if two instructions are present and we already have one saved
1088 then first write it out */
1091 /* assemble first instruction and save it */
1092 prev_insn
= do_assemble (str
, &prev_opcode
);
1093 if (prev_insn
== -1)
1094 as_fatal (_("cannot assemble instruction "));
1095 if (prev_opcode
.form
->form
>= LONG
)
1096 as_fatal (_("First opcode is long. Unable to mix instructions as specified."));
1097 fixups
= fixups
->next
;
1102 insn
= do_assemble (str
, &opcode
);
1110 as_fatal (_("cannot assemble instruction "));
1119 /* Word multiply instructions must not be followed by either a load or a
1120 16-bit multiply instruction in the next cycle. */
1121 if (prev_mul32_p
&& (opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1123 /* However, load and multiply should able to be combined in a parallel
1124 operation, so check for that first. */
1127 && (opcode
.op
->flags_used
& FLAG_MEM
)
1128 && opcode
.form
->form
< LONG
1129 && (extype
== EXEC_PARALLEL
|| (Optimizing
&& extype
== EXEC_UNKNOWN
))
1130 && parallel_ok (&prev_opcode
, (long)prev_insn
,
1131 &opcode
, (long)insn
, extype
)
1132 && write_2_short (&prev_opcode
, (long)prev_insn
,
1133 &opcode
, (long)insn
, extype
, fixups
) == 0)
1135 /* no instructions saved */
1140 /* Can't parallelize, flush current instruction and emit a word of NOPS */
1147 d30v_number_to_chars (f
, NOP2
, 8);
1148 if (warn_nops
== NOP_ALL
|| warn_nops
== NOP_MULTIPLY
)
1150 if ((opcode
.op
->flags_used
& FLAG_MEM
))
1151 as_warn (_("word of NOPs added between word multiply and load"));
1153 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1158 /* if this is a long instruction, write it and any previous short instruction */
1159 if (opcode
.form
->form
>= LONG
)
1162 as_fatal(_("Unable to mix instructions as specified"));
1164 write_long (&opcode
, insn
, fixups
);
1169 if ((prev_insn
!= -1) &&
1170 (write_2_short (&prev_opcode
, (long)prev_insn
, &opcode
, (long)insn
, extype
, fixups
) == 0))
1172 /* no instructions saved */
1179 as_fatal(_("Unable to mix instructions as specified"));
1180 /* save off last instruction so it may be packed on next pass */
1181 memcpy(&prev_opcode
, &opcode
, sizeof(prev_opcode
));
1184 prev_subseg
= now_subseg
;
1185 fixups
= fixups
->next
;
1190 /* do_assemble assembles a single instruction and returns an opcode */
1191 /* it returns -1 (an invalid opcode) on error */
1194 do_assemble (str
, opcode
)
1196 struct d30v_insn
*opcode
;
1198 unsigned char *op_start
, *save
;
1199 unsigned char *op_end
;
1201 int cmp_hack
, nlen
= 0, fsize
= 0;
1202 expressionS myops
[6];
1205 /* Drop leading whitespace */
1209 /* find the opcode end */
1210 for (op_start
= op_end
= (unsigned char *) (str
);
1214 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1217 name
[nlen
] = tolower(op_start
[nlen
]);
1226 /* if there is an execution condition code, handle it */
1230 while ( (i
< ECC_MAX
) && strncasecmp(d30v_ecc_names
[i
],op_end
+1,2))
1236 strncpy(tmp
,op_end
+1,2);
1238 as_fatal (_("unknown condition code: %s"),tmp
);
1241 /* printf("condition code=%d\n",i); */
1246 opcode
->ecc
= ECC_AL
;
1249 /* CMP and CMPU change their name based on condition codes */
1250 if (!strncmp(name
,"cmp",3))
1253 char **str
= (char **)d30v_cc_names
;
1259 for(i
=1; *str
&& strncmp(*str
,&name
[p
],2); i
++, str
++)
1262 /* cmpu only supports some condition codes */
1268 as_fatal (_("cmpu doesn't support condition code %s"),&name
[p
]);
1275 as_fatal (_("unknown condition code: %s"),&name
[p
]);
1284 /* printf("cmp_hack=%d\n",cmp_hack); */
1286 /* need to look for .s or .l */
1287 if (name
[nlen
-2] == '.')
1289 switch (name
[nlen
-1])
1292 fsize
= FORCE_SHORT
;
1301 /* find the first opcode with the proper name */
1302 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1303 if (opcode
->op
== NULL
)
1304 as_fatal (_("unknown opcode: %s"),name
);
1306 save
= input_line_pointer
;
1307 input_line_pointer
= op_end
;
1308 while (!(opcode
->form
= find_format (opcode
->op
, myops
, fsize
, cmp_hack
)))
1311 if (strcmp(opcode
->op
->name
,name
))
1314 input_line_pointer
= save
;
1316 insn
= build_insn (opcode
, myops
);
1318 /* Propigate multiply status */
1321 prev_mul32_p
= cur_mul32_p
;
1322 cur_mul32_p
= (opcode
->op
->flags_used
& FLAG_MUL32
) != 0;
1329 /* find_format() gets a pointer to an entry in the format table. */
1330 /* It must look at all formats for an opcode and use the operands */
1331 /* to choose the correct one. Returns NULL on error. */
1333 static struct d30v_format
*
1334 find_format (opcode
, myops
, fsize
, cmp_hack
)
1335 struct d30v_opcode
*opcode
;
1336 expressionS myops
[];
1340 int numops
, match
, index
, i
=0, j
, k
;
1341 struct d30v_format
*fm
;
1343 /* get all the operands and save them as expressions */
1344 numops
= get_operands (myops
, cmp_hack
);
1346 while ((index
= opcode
->format
[i
++]) != 0)
1348 if ((fsize
== FORCE_SHORT
) && (index
>= LONG
))
1351 if ((fsize
== FORCE_LONG
) && (index
< LONG
))
1354 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1356 while (fm
->form
== index
)
1359 /* now check the operands for compatibility */
1360 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1362 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1363 int X_op
= myops
[j
].X_op
;
1364 int num
= myops
[j
].X_add_number
;
1366 if ( flags
& OPERAND_SPECIAL
)
1370 else if (flags
& OPERAND_REG
)
1372 if ((X_op
!= O_register
)
1373 || ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
))
1374 || ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
))
1375 || ((flags
& OPERAND_CONTROL
)
1376 && !(num
& (OPERAND_CONTROL
| OPERAND_FLAG
))))
1382 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
)))
1383 || ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
)))
1384 || ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
)))
1385 || ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
)))
1386 || ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATSIGN
))))
1390 else if (flags
& OPERAND_NUM
)
1392 /* a number can be a constant or symbol expression */
1393 if (fm
->form
>= LONG
)
1395 /* If we're testing for a LONG format, either fits */
1396 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1399 else if ((fm
->form
< LONG
) && (((fsize
== FORCE_SHORT
) && (X_op
== O_symbol
)) ||
1400 (fm
->form
== SHORT_D2
&& j
== 0)))
1402 /* This is the tricky part. Will the constant or symbol */
1403 /* fit into the space in the current format? */
1404 else if (X_op
== O_constant
)
1406 if (check_range (num
, d30v_operand_table
[fm
->operands
[j
]].bits
, flags
))
1409 else if (X_op
== O_symbol
&& S_IS_DEFINED(myops
[j
].X_add_symbol
) &&
1410 (S_GET_SEGMENT(myops
[j
].X_add_symbol
) == now_seg
) &&
1411 opcode
->reloc_flag
== RELOC_PCREL
)
1413 /* if the symbol is defined, see if the value will fit */
1414 /* into the form we're considering */
1417 /* calculate the current address by running through the previous frags */
1418 /* and adding our current offset */
1419 for (value
= 0, f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1420 value
+= f
->fr_fix
+ f
->fr_offset
;
1421 value
= S_GET_VALUE(myops
[j
].X_add_symbol
) - value
-
1422 (obstack_next_free(&frchain_now
->frch_obstack
) - frag_now
->fr_literal
);
1423 if (check_range (value
, d30v_operand_table
[fm
->operands
[j
]].bits
, flags
))
1430 /* printf("through the loop: match=%d\n",match); */
1431 /* we're only done if the operands matched so far AND there
1432 are no more to check */
1433 if (match
&& myops
[j
].X_op
==0)
1436 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1438 /* printf("trying another format: i=%d\n",i); */
1443 /* if while processing a fixup, a reloc really needs to be created */
1444 /* then it is done here */
1447 tc_gen_reloc (seg
, fixp
)
1452 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1453 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1454 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1455 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1456 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1458 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1459 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1462 reloc
->addend
= fixp
->fx_addnumber
;
1467 md_estimate_size_before_relax (fragp
, seg
)
1476 md_pcrel_from_section (fixp
, sec
)
1480 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1481 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1483 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1487 md_apply_fix3 (fixp
, valuep
, seg
)
1493 unsigned long insn
, insn2
;
1496 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1501 else if (fixp
->fx_pcrel
)
1507 value
= fixp
->fx_offset
;
1508 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1510 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1511 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1514 /* We don't actually support subtracting a symbol. */
1515 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1516 _("expression too complex"));
1521 /* Fetch the instruction, insert the fully resolved operand
1522 value, and stuff the instruction back again. */
1523 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1524 insn
= bfd_getb32 ((unsigned char *) where
);
1526 switch (fixp
->fx_r_type
)
1528 case BFD_RELOC_D30V_6
:
1529 check_size (value
, 6, fixp
->fx_file
, fixp
->fx_line
);
1530 insn
|= value
& 0x3F;
1531 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1534 case BFD_RELOC_D30V_9_PCREL
:
1535 if (fixp
->fx_where
& 0x7)
1540 fixp
->fx_r_type
= BFD_RELOC_D30V_9_PCREL_R
;
1542 check_size (value
, 9, fixp
->fx_file
, fixp
->fx_line
);
1543 insn
|= ((value
>> 3) & 0x3F) << 12;
1544 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1547 case BFD_RELOC_D30V_15
:
1548 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1549 insn
|= (value
>> 3) & 0xFFF;
1550 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1553 case BFD_RELOC_D30V_15_PCREL
:
1554 if (fixp
->fx_where
& 0x7)
1559 fixp
->fx_r_type
= BFD_RELOC_D30V_15_PCREL_R
;
1561 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1562 insn
|= (value
>> 3) & 0xFFF;
1563 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1566 case BFD_RELOC_D30V_21
:
1567 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1568 insn
|= (value
>> 3) & 0x3FFFF;
1569 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1572 case BFD_RELOC_D30V_21_PCREL
:
1573 if (fixp
->fx_where
& 0x7)
1578 fixp
->fx_r_type
= BFD_RELOC_D30V_21_PCREL_R
;
1580 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1581 insn
|= (value
>> 3) & 0x3FFFF;
1582 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1585 case BFD_RELOC_D30V_32
:
1586 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1587 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1588 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1589 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1590 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1591 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1594 case BFD_RELOC_D30V_32_PCREL
:
1595 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1596 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1597 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1598 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1599 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1600 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1604 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1608 as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp
->fx_line
,fixp
->fx_r_type
);
1614 /* d30v_cleanup() is called after the assembler has finished parsing the input
1615 file or after a label is defined. Because the D30V assembler sometimes saves short
1616 instructions to see if it can package them with the next instruction, there may
1617 be a short instruction that still needs written. */
1624 if (prev_insn
!= -1)
1627 subseg
= now_subseg
;
1628 subseg_set (prev_seg
, prev_subseg
);
1629 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
);
1630 subseg_set (seg
, subseg
);
1638 d30v_number_to_chars (buf
, value
, n
)
1639 char *buf
; /* Return 'nbytes' of chars here. */
1640 long long value
; /* The value of the bits. */
1641 int n
; /* Number of bytes in the output. */
1645 buf
[n
] = value
& 0xff;
1651 /* This function is called at the start of every line. */
1652 /* it checks to see if the first character is a '.' */
1653 /* which indicates the start of a pseudo-op. If it is, */
1654 /* then write out any unwritten instructions */
1659 char *c
= input_line_pointer
;
1669 check_size (value
, bits
, file
, line
)
1682 max
= (1 << (bits
- 1)) - 1;
1685 as_bad_where (file
, line
,"value too large to fit in %d bits",bits
);