1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
3 Copyright (C) 1997 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d30v.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "O";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
38 #define MAX_INSN_FIXUPS (5)
45 bfd_reloc_code_real_type reloc
;
48 typedef struct _fixups
51 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
55 static Fixups FixUps
[2];
56 static Fixups
*fixups
;
59 static int reg_name_search
PARAMS ((char *name
));
60 static int register_name
PARAMS ((expressionS
*expressionP
));
61 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
62 static int postfix
PARAMS ((char *p
));
63 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
64 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
65 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
, expressionS ops
[],
67 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
68 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
69 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
70 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
71 struct d30v_insn
*opcode2
, long long insn2
, int exec_type
, Fixups
*fx
));
72 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
));
73 static unsigned long d30v_insert_operand
PARAMS (( unsigned long insn
, int op_type
,
74 offsetT value
, int left
, fixS
*fix
));
75 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
76 struct d30v_insn
*opcode2
, unsigned long insn2
,
78 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
80 struct option md_longopts
[] = {
81 {NULL
, no_argument
, NULL
, 0}
83 size_t md_longopts_size
= sizeof(md_longopts
);
86 /* The target specific pseudo-ops which we support. */
87 const pseudo_typeS md_pseudo_table
[] =
92 /* Opcode hash table. */
93 static struct hash_control
*d30v_hash
;
95 /* reg_name_search does a binary search of the pre_defined_registers
96 array to see if "name" is a valid regiter name. Returns the register
97 number from the array on success, or -1 on failure. */
100 reg_name_search (name
)
103 int middle
, low
, high
;
107 high
= reg_name_cnt() - 1;
111 middle
= (low
+ high
) / 2;
112 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
118 return pre_defined_registers
[middle
].value
;
124 /* register_name() checks the string at input_line_pointer
125 to see if it is a valid register name */
128 register_name (expressionP
)
129 expressionS
*expressionP
;
132 char c
, *p
= input_line_pointer
;
134 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
141 /* look to see if it's in the register table */
142 reg_number
= reg_name_search (input_line_pointer
);
145 expressionP
->X_op
= O_register
;
146 /* temporarily store a pointer to the string here */
147 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
148 expressionP
->X_add_number
= reg_number
;
149 input_line_pointer
= p
;
159 check_range (num
, bits
, flags
)
167 /* don't bother checking 32-bit values */
171 if (flags
& OPERAND_SIGNED
)
173 max
= (1 << (bits
- 1))-1;
174 min
= - (1 << (bits
- 1));
175 if (((long)num
> max
) || ((long)num
< min
))
180 max
= (1 << bits
) - 1;
182 if ((num
> max
) || (num
< min
))
190 md_show_usage (stream
)
193 fprintf(stream
, "D30V options:\n\
194 -O optimize. Will do some operations in parallel.\n");
198 md_parse_option (c
, arg
)
205 /* Optimize. Will attempt to parallelize operations */
215 md_undefined_symbol (name
)
221 /* Turn a string in input_line_pointer into a floating point constant of type
222 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
223 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
226 md_atof (type
, litP
, sizeP
)
232 LITTLENUM_TYPE words
[4];
246 return "bad call to md_atof";
249 t
= atof_ieee (input_line_pointer
, type
, words
);
251 input_line_pointer
= t
;
255 for (i
= 0; i
< prec
; i
++)
257 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
264 md_convert_frag (abfd
, sec
, fragP
)
273 md_section_align (seg
, addr
)
277 int align
= bfd_get_section_alignment (stdoutput
, seg
);
278 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
285 struct d30v_opcode
*opcode
;
286 d30v_hash
= hash_new();
288 /* Insert opcode names into a hash table. */
289 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
290 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
293 FixUps
[0].next
= &FixUps
[1];
294 FixUps
[1].next
= &FixUps
[0];
298 /* this function removes the postincrement or postdecrement
299 operator ( '+' or '-' ) from an expression */
301 static int postfix (p
)
304 while (*p
!= '-' && *p
!= '+')
306 if (*p
==0 || *p
=='\n' || *p
=='\r')
326 static bfd_reloc_code_real_type
327 get_reloc (op
, rel_flag
)
328 struct d30v_operand
*op
;
334 return BFD_RELOC_D30V_6
;
336 if (!(op
->flags
& OPERAND_SHIFT
))
337 as_warn("unexpected 12-bit reloc type");
338 if (rel_flag
== RELOC_PCREL
)
339 return BFD_RELOC_D30V_15_PCREL
;
341 return BFD_RELOC_D30V_15
;
343 if (!(op
->flags
& OPERAND_SHIFT
))
344 as_warn("unexpected 18-bit reloc type");
345 if (rel_flag
== RELOC_PCREL
)
346 return BFD_RELOC_D30V_21_PCREL
;
348 return BFD_RELOC_D30V_21
;
350 if (rel_flag
== RELOC_PCREL
)
351 return BFD_RELOC_D30V_32_PCREL
;
353 return BFD_RELOC_D30V_32
;
359 /* get_operands parses a string of operands and returns
360 an array of expressions */
363 get_operands (exp
, cmp_hack
)
367 char *p
= input_line_pointer
;
373 exp
[numops
].X_op
= O_absent
;
374 exp
[numops
++].X_add_number
= cmp_hack
- 1;
379 while (*p
== ' ' || *p
== '\t' || *p
== ',')
381 if (*p
==0 || *p
=='\n' || *p
=='\r')
387 exp
[numops
].X_op
= O_absent
;
391 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
397 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
401 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
410 /* just skip the trailing paren */
415 input_line_pointer
= p
;
417 /* check to see if it might be a register name */
418 if (!register_name (&exp
[numops
]))
420 /* parse as an expression */
421 expression (&exp
[numops
]);
424 if (exp
[numops
].X_op
== O_illegal
)
425 as_bad ("illegal operand");
426 else if (exp
[numops
].X_op
== O_absent
)
427 as_bad ("missing operand");
430 p
= input_line_pointer
;
434 case -1: /* postdecrement mode */
435 exp
[numops
].X_op
= O_absent
;
436 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
438 case 1: /* postincrement mode */
439 exp
[numops
].X_op
= O_absent
;
440 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
446 exp
[numops
].X_op
= 0;
450 /* build_insn generates the instruction. It does everything */
451 /* but write the FM bits. */
454 build_insn (opcode
, opers
)
455 struct d30v_insn
*opcode
;
458 int i
, length
, bits
, shift
, flags
, format
;
459 unsigned int number
, id
=0;
461 struct d30v_opcode
*op
= opcode
->op
;
462 struct d30v_format
*form
= opcode
->form
;
464 /* printf("ecc=%x op1=%x op2=%x mod=%x\n",opcode->ecc,op->op1,op->op2,form->modifier); */
465 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
466 /* printf("insn=%llx\n",insn); */
467 for (i
=0; form
->operands
[i
]; i
++)
469 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
472 /* must be a register or number */
473 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
474 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
477 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
478 length
= d30v_operand_table
[form
->operands
[i
]].length
;
479 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
480 number
= opers
[i
].X_add_number
;
481 if (flags
& OPERAND_REG
)
483 /* now check for mvfsys or mvtsys control registers */
484 if (flags
& OPERAND_CONTROL
&& (number
& 0x3f) > MAX_CONTROL_REG
)
487 id
= (number
& 0x3f) - MAX_CONTROL_REG
;
490 else if (number
& OPERAND_FLAG
)
492 id
= 3; /* number is a flag register */
496 else if (flags
& OPERAND_SPECIAL
)
502 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
504 /* now create a fixup */
506 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
507 as_fatal ("too many fixups");
509 fixups
->fix
[fixups
->fc
].reloc
=
510 get_reloc((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
511 fixups
->fix
[fixups
->fc
].size
= 4;
512 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
513 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
514 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
518 /* truncate to the proper number of bits */
520 if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
521 as_bad("operand out of range: %d",number);
522 number &= 0x7FFFFFFF >> (31 - bits);
527 /* it's a LONG instruction */
528 insn
|= (number
>> 26); /* top 6 bits */
529 insn
<<= 32; /* shift the first word over */
530 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
531 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
534 insn
|= number
<< shift
;
540 /* write out a long form instruction */
542 write_long (opcode
, insn
, fx
)
543 struct d30v_insn
*opcode
;
548 char *f
= frag_more(8);
551 d30v_number_to_chars (f
, insn
, 8);
553 for (i
=0; i
< fx
->fc
; i
++)
555 if (fx
->fix
[i
].reloc
)
557 where
= f
- frag_now
->fr_literal
;
558 fix_new_exp (frag_now
,
570 /* write out a short form instruction by itself */
572 write_1_short (opcode
, insn
, fx
)
573 struct d30v_insn
*opcode
;
577 char *f
= frag_more(8);
580 /* the other container needs to be NOP */
581 /* according to 4.3.1: for FM=00, sub-instructions performed only
582 by IU cannot be encoded in L-container. */
583 if (opcode
->op
->unit
== IU
)
584 insn
|= FM00
| ((long long)NOP
<< 32); /* right container */
586 insn
= FM00
| (insn
<< 32) | (long long)NOP
; /* left container */
588 d30v_number_to_chars (f
, insn
, 8);
590 for (i
=0; i
< fx
->fc
; i
++)
592 if (fx
->fix
[i
].reloc
)
594 where
= f
- frag_now
->fr_literal
;
595 fix_new_exp (frag_now
,
606 /* write out a short form instruction if possible */
607 /* return number of instructions not written out */
609 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
610 struct d30v_insn
*opcode1
, *opcode2
;
611 long long insn1
, insn2
;
619 if(exec_type
!= 1 && (opcode1
->op
->flags_used
== FLAG_JSR
))
621 /* subroutines must be called from 32-bit boundaries */
622 /* so the return address will be correct */
623 write_1_short (opcode1
, insn1
, fx
->next
);
629 case 0: /* order not specified */
630 if ( Optimizing
&& parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
633 if (opcode1
->op
->unit
== IU
)
634 insn
= FM00
| (insn2
<< 32) | insn1
;
635 else if (opcode2
->op
->unit
== MU
)
636 insn
= FM00
| (insn2
<< 32) | insn1
;
639 insn
= FM00
| (insn1
<< 32) | insn2
;
643 else if (opcode1
->op
->unit
== IU
)
645 /* reverse sequential */
646 insn
= FM10
| (insn2
<< 32) | insn1
;
651 insn
= FM01
| (insn1
<< 32) | insn2
;
655 case 1: /* parallel */
656 if (opcode1
->op
->unit
== IU
)
658 if (opcode2
->op
->unit
== IU
)
659 as_fatal ("Two IU instructions may not be executed in parallel");
660 as_warn ("Swapping instruction order");
661 insn
= FM00
| (insn2
<< 32) | insn1
;
663 else if (opcode2
->op
->unit
== MU
)
665 if (opcode1
->op
->unit
== MU
)
666 as_fatal ("Two MU instructions may not be executed in parallel");
667 as_warn ("Swapping instruction order");
668 insn
= FM00
| (insn2
<< 32) | insn1
;
672 insn
= FM00
| (insn1
<< 32) | insn2
;
676 case 2: /* sequential */
677 if (opcode1
->op
->unit
== IU
)
678 as_fatal ("IU instruction may not be in the left container");
679 insn
= FM01
| (insn1
<< 32) | insn2
;
682 case 3: /* reverse sequential */
683 if (opcode2
->op
->unit
== MU
)
684 as_fatal ("MU instruction may not be in the right container");
685 insn
= FM10
| (insn1
<< 32) | insn2
;
689 as_fatal("unknown execution type passed to write_2_short()");
692 /* printf("writing out %llx\n",insn); */
694 d30v_number_to_chars (f
, insn
, 8);
698 for (i
=0; i
< fx
->fc
; i
++)
700 if (fx
->fix
[i
].reloc
)
702 where
= (f
- frag_now
->fr_literal
) + 4*j
;
704 fix_new_exp (frag_now
,
719 /* Check 2 instructions and determine if they can be safely */
720 /* executed in parallel. Returns 1 if they can be. */
722 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
723 struct d30v_insn
*op1
, *op2
;
724 unsigned long insn1
, insn2
;
727 int i
, j
, flags
, mask
, shift
, regno
, bits
;
728 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3];
729 struct d30v_format
*f
;
730 struct d30v_opcode
*op
;
732 /* section 4.3: both instructions must not be IU or MU only */
733 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
734 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
743 for (j
= 0; j
< 2; j
++)
757 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
758 mod_reg
[j
][2] = op
->flags_set
;
759 used_reg
[j
][0] = used_reg
[j
][1] = 0;
760 used_reg
[j
][2] = op
->flags_used
;
761 for (i
= 0; f
->operands
[i
]; i
++)
763 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
764 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
765 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
769 mask
= 0x7FFFFFFF >> (31 - bits
);
770 if (flags
& OPERAND_REG
)
772 regno
= (ins
>> shift
) & mask
;
773 if (flags
& OPERAND_DEST
)
775 if (flags
& OPERAND_ACC
)
776 mod_reg
[j
][2] = 1 << (regno
+16);
777 else if (flags
& OPERAND_FLAG
)
778 mod_reg
[j
][2] = 1 << regno
;
779 else if (!(flags
& OPERAND_CONTROL
))
782 mod_reg
[j
][1] = 1 << (regno
- 32);
784 mod_reg
[j
][0] = 1 << regno
;
789 if (flags
& OPERAND_ACC
)
790 used_reg
[j
][2] = 1 << (regno
+16);
791 else if (flags
& OPERAND_FLAG
)
792 used_reg
[j
][2] = 1 << regno
;
793 else if (!(flags
& OPERAND_CONTROL
))
796 used_reg
[j
][1] = 1 << (regno
- 32);
798 used_reg
[j
][0] = 1 << regno
;
805 for(j
= 0; j
< 3; j
++)
806 if ((mod_reg
[0][j
] & mod_reg
[1][j
])
807 || (mod_reg
[0][j
] & used_reg
[1][j
])
808 || (mod_reg
[1][j
] & used_reg
[0][j
]))
816 /* This is the main entry point for the machine-dependent assembler. str points to a
817 machine-dependent instruction. This function is supposed to emit the frags/bytes
818 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
819 and leaves the difficult stuff to do_assemble().
822 static long long prev_insn
= -1;
823 static struct d30v_insn prev_opcode
;
824 static subsegT prev_subseg
;
825 static segT prev_seg
= 0;
831 struct d30v_insn opcode
;
833 int extype
=0; /* execution type; parallel, etc */
834 static int etype
=0; /* saved extype. used for multiline instructions */
839 /* look for the special multiple instruction separators */
840 str2
= strstr (str
, "||");
845 str2
= strstr (str
, "->");
850 str2
= strstr (str
, "<-");
855 /* str2 points to the separator, if one */
860 /* if two instructions are present and we already have one saved
861 then first write it out */
864 /* assemble first instruction and save it */
865 prev_insn
= do_assemble (str
, &prev_opcode
);
867 as_fatal ("can't find opcode ");
868 fixups
= fixups
->next
;
873 insn
= do_assemble (str
, &opcode
);
881 as_fatal ("can't find opcode ");
890 /* if this is a long instruction, write it and any previous short instruction */
891 if (opcode
.form
->form
>= LONG
)
894 as_fatal("Unable to mix instructions as specified");
896 write_long (&opcode
, insn
, fixups
);
901 if ( (prev_insn
!= -1) && prev_seg
&& ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
904 if ( (prev_insn
!= -1) &&
905 (write_2_short (&prev_opcode
, (long)prev_insn
, &opcode
, (long)insn
, extype
, fixups
) == 0))
907 /* no instructions saved */
913 as_fatal("Unable to mix instructions as specified");
914 /* save off last instruction so it may be packed on next pass */
915 memcpy( &prev_opcode
, &opcode
, sizeof(prev_opcode
));
918 prev_subseg
= now_subseg
;
919 fixups
= fixups
->next
;
924 /* do_assemble assembles a single instruction and returns an opcode */
925 /* it returns -1 (an invalid opcode) on error */
928 do_assemble (str
, opcode
)
930 struct d30v_insn
*opcode
;
932 unsigned char *op_start
, *save
;
933 unsigned char *op_end
;
935 int cmp_hack
, nlen
= 0;
936 expressionS myops
[6];
939 /* Drop leading whitespace */
943 /* find the opcode end */
944 for (op_start
= op_end
= (unsigned char *) (str
);
948 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
951 name
[nlen
] = tolower(op_start
[nlen
]);
960 /* if there is an execution condition code, handle it */
964 while ( (i
< ECC_MAX
) && strncasecmp(d30v_ecc_names
[i
],op_end
+1,2))
970 strncpy(tmp
,op_end
+1,2);
972 as_fatal ("unknown condition code: %s",tmp
);
975 /* printf("condition code=%d\n",i); */
980 opcode
->ecc
= ECC_AL
;
983 /* CMP and CMPU change their name based on condition codes */
984 if (!strncmp(name
,"cmp",3))
987 char **str
= (char **)d30v_cc_names
;
993 for(i
=1; *str
&& strncmp(*str
,&name
[p
],2); i
++, *str
++)
999 as_fatal ("unknown condition code: %s",&name
[p
]);
1008 /* printf("cmp_hack=%d\n",cmp_hack); */
1010 /* find the first opcode with the proper name */
1011 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1012 if (opcode
->op
== NULL
)
1013 as_fatal ("unknown opcode: %s",name
);
1015 save
= input_line_pointer
;
1016 input_line_pointer
= op_end
;
1017 while (!(opcode
->form
= find_format (opcode
->op
, myops
, cmp_hack
)))
1020 if (strcmp(opcode
->op
->name
,name
))
1023 input_line_pointer
= save
;
1025 insn
= build_insn (opcode
, myops
);
1030 /* find_format() gets a pointer to an entry in the format table. */
1031 /* It must look at all formats for an opcode and use the operands */
1032 /* to choose the correct one. Returns NULL on error. */
1034 static struct d30v_format
*
1035 find_format (opcode
, myops
, cmp_hack
)
1036 struct d30v_opcode
*opcode
;
1037 expressionS myops
[];
1040 int numops
, match
, index
, i
=0, j
, k
;
1041 struct d30v_format
*fm
;
1042 struct d30v_operand
*op
;
1044 /* get all the operands and save them as expressions */
1045 numops
= get_operands (myops
, cmp_hack
);
1047 while (index
= opcode
->format
[i
++])
1049 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1051 while (fm
->form
== index
)
1054 /* now check the operands for compatibility */
1055 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1057 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1058 int X_op
= myops
[j
].X_op
;
1059 int num
= myops
[j
].X_add_number
;
1061 if ( flags
& OPERAND_SPECIAL
)
1065 else if (flags
& OPERAND_REG
)
1067 if ((X_op
!= O_register
) ||
1068 ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
)) ||
1069 ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
)) ||
1070 (flags
& OPERAND_CONTROL
&& !(num
& OPERAND_CONTROL
| num
& OPERAND_FLAG
)))
1076 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
1077 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
1078 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
1079 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
1080 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATSIGN
))))
1084 else if (flags
& OPERAND_NUM
)
1086 /* a number can be a constant or symbol expression */
1087 if (fm
->form
>= LONG
)
1089 /* If we're testing for a LONG format, either fits */
1090 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1093 /* This is the tricky part. Will the constant or symbol */
1094 /* fit into the space in the current format? */
1095 else if (X_op
== O_constant
)
1097 if (check_range (num
, d30v_operand_table
[fm
->operands
[j
]].bits
, flags
))
1100 else if (X_op
== O_symbol
&& S_IS_DEFINED(myops
[j
].X_add_symbol
) &&
1101 (S_GET_SEGMENT(myops
[j
].X_add_symbol
) == now_seg
))
1103 /* if the symbol is defined, see if the value will fit */
1104 /* into the form we're considering */
1107 /* calculate the current address by running through the previous frags */
1108 /* and adding our current offset */
1109 for (value
= 0, f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1110 value
+= f
->fr_fix
+ f
->fr_offset
;
1111 if (opcode
->reloc_flag
== RELOC_PCREL
)
1112 value
= S_GET_VALUE(myops
[j
].X_add_symbol
) - value
-
1113 (obstack_next_free(&frchain_now
->frch_obstack
) - frag_now
->fr_literal
);
1115 value
= S_GET_VALUE(myops
[j
].X_add_symbol
);
1116 if (check_range (value
, d30v_operand_table
[fm
->operands
[j
]].bits
, flags
))
1123 /* printf("through the loop: match=%d\n",match); */
1124 /* we're only done if the operands matched so far AND there
1125 are no more to check */
1126 if (match
&& myops
[j
].X_op
==0)
1129 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1131 /* printf("trying another format: i=%d\n",i); */
1136 /* if while processing a fixup, a reloc really needs to be created */
1137 /* then it is done here */
1140 tc_gen_reloc (seg
, fixp
)
1145 reloc
= (arelent
*) bfd_alloc_by_size_t (stdoutput
, sizeof (arelent
));
1146 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1147 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1148 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1149 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1151 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1152 "reloc %d not supported by object file format", (int)fixp
->fx_r_type
);
1155 reloc
->addend
= fixp
->fx_addnumber
;
1160 md_estimate_size_before_relax (fragp
, seg
)
1169 md_pcrel_from_section (fixp
, sec
)
1173 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& !S_IS_DEFINED (fixp
->fx_addsy
))
1175 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1179 md_apply_fix3 (fixp
, valuep
, seg
)
1185 unsigned long insn
, insn2
;
1190 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1195 else if (!S_IS_DEFINED(fixp
->fx_addsy
))
1197 else if (fixp
->fx_pcrel
)
1203 value
= fixp
->fx_offset
;
1204 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1206 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1207 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1210 /* We don't actually support subtracting a symbol. */
1211 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1212 "expression too complex");
1217 /* Fetch the instruction, insert the fully resolved operand
1218 value, and stuff the instruction back again. */
1219 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1220 insn
= bfd_getb32 ((unsigned char *) where
);
1222 switch (fixp
->fx_r_type
)
1224 case BFD_RELOC_D30V_6
:
1225 insn
|= value
& 0x3F;
1226 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1228 case BFD_RELOC_D30V_15
:
1229 insn
|= (value
>> 3) & 0xFFF;
1230 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1232 case BFD_RELOC_D30V_15_PCREL
:
1233 if ((long)fixp
->fx_where
& 0x7)
1235 insn
|= (value
>> 3) & 0xFFF;
1236 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1238 case BFD_RELOC_D30V_21
:
1239 insn
|= (value
>> 3) & 0x3FFFF;
1240 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1242 case BFD_RELOC_D30V_21_PCREL
:
1243 if ((long)fixp
->fx_where
& 0x7)
1245 insn
|= (value
>> 3) & 0x3FFFF;
1246 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1248 case BFD_RELOC_D30V_32
:
1249 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1250 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1251 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1252 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1253 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1254 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1256 case BFD_RELOC_D30V_32_PCREL
:
1257 if ((long)fixp
->fx_where
& 0x7)
1259 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1260 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1261 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1262 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1263 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1264 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1267 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1270 as_fatal ("line %d: unknown relocation type: 0x%x",fixp
->fx_line
,fixp
->fx_r_type
);
1277 /* d30v_cleanup() is called after the assembler has finished parsing the input
1278 file or after a label is defined. Because the D30V assembler sometimes saves short
1279 instructions to see if it can package them with the next instruction, there may
1280 be a short instruction that still needs written. */
1287 if (prev_insn
!= -1)
1290 subseg
= now_subseg
;
1291 subseg_set (prev_seg
, prev_subseg
);
1292 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
);
1293 subseg_set (seg
, subseg
);
1301 d30v_number_to_chars (buf
, value
, n
)
1302 char *buf
; /* Return 'nbytes' of chars here. */
1303 long long value
; /* The value of the bits. */
1304 int n
; /* Number of bytes in the output. */
1308 buf
[n
] = value
& 0xff;