1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
3 Copyright (C) 1997, 1998 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d30v.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "OnNcC";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
35 #define NOP_MULTIPLY 1
37 static int warn_nops
= 0;
38 static int Optimizing
= 0;
39 static int warn_register_name_conflicts
= 1;
45 typedef enum _exec_type
47 EXEC_UNKNOWN
, /* no order specified */
48 EXEC_PARALLEL
, /* done in parallel (FM=00) */
49 EXEC_SEQ
, /* sequential (FM=01) */
50 EXEC_REVSEQ
/* reverse sequential (FM=10) */
54 #define MAX_INSN_FIXUPS (5)
61 bfd_reloc_code_real_type reloc
;
64 typedef struct _fixups
67 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
71 static Fixups FixUps
[2];
72 static Fixups
*fixups
;
74 /* Whether current and previous instruction are word multiply insns. */
75 static int cur_mul32_p
= 0;
76 static int prev_mul32_p
= 0;
78 /* The flag_explicitly_parallel is true iff the instruction being assembled
79 has been explicitly written as a parallel short-instruction pair by the
80 human programmer. It is used in parallel_ok() to distinguish between
81 those dangerous parallelizations attempted by the human, which are to be
82 allowed, and those attempted by the assembler, which are not. It is set
83 from md_assemble(). */
84 static int flag_explicitly_parallel
= 0;
85 static int flag_xp_state
= 0;
87 /* Whether current and previous left sub-instruction disables
88 execution of right sub-instruction. */
89 static int cur_left_kills_right_p
= 0;
90 static int prev_left_kills_right_p
= 0;
92 /* The known current alignment of the current section. */
93 static int d30v_current_align
;
94 static segT d30v_current_align_seg
;
96 /* The last seen label in the current section. This is used to auto-align
97 labels preceeding instructions. */
98 static symbolS
*d30v_last_label
;
101 #define NOP_LEFT ((long long) NOP << 32)
102 #define NOP_RIGHT ((long long) NOP)
103 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
105 /* local functions */
106 static int reg_name_search
PARAMS ((char *name
));
107 static int register_name
PARAMS ((expressionS
*expressionP
));
108 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
109 static int postfix
PARAMS ((char *p
));
110 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
111 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
112 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
,
113 expressionS ops
[],int fsize
, int cmp_hack
));
114 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
115 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
116 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
,
117 Fixups
*fx
, int use_sequential
));
118 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
119 struct d30v_insn
*opcode2
, long long insn2
, exec_type_enum exec_type
, Fixups
*fx
));
120 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
,
121 int shortp
, int is_parallel
));
122 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
123 struct d30v_insn
*opcode2
, unsigned long insn2
,
124 exec_type_enum exec_type
));
125 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
126 static void check_size
PARAMS ((long value
, int bits
, char *file
, int line
));
127 static void d30v_align
PARAMS ((int, char *, symbolS
*));
128 static void s_d30v_align
PARAMS ((int));
129 static void s_d30v_text
PARAMS ((int));
130 static void s_d30v_data
PARAMS ((int));
131 static void s_d30v_section
PARAMS ((int));
133 struct option md_longopts
[] = {
134 {NULL
, no_argument
, NULL
, 0}
136 size_t md_longopts_size
= sizeof(md_longopts
);
139 /* The target specific pseudo-ops which we support. */
140 const pseudo_typeS md_pseudo_table
[] =
143 { "hword", cons
, 2 },
144 { "align", s_d30v_align
, 0 },
145 { "text", s_d30v_text
, 0 },
146 { "data", s_d30v_data
, 0 },
147 { "section", s_d30v_section
, 0 },
148 { "section.s", s_d30v_section
, 0 },
149 { "sect", s_d30v_section
, 0 },
150 { "sect.s", s_d30v_section
, 0 },
154 /* Opcode hash table. */
155 static struct hash_control
*d30v_hash
;
157 /* reg_name_search does a binary search of the pre_defined_registers
158 array to see if "name" is a valid regiter name. Returns the register
159 number from the array on success, or -1 on failure. */
162 reg_name_search (name
)
165 int middle
, low
, high
;
169 high
= reg_name_cnt () - 1;
173 middle
= (low
+ high
) / 2;
174 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
181 if (symbol_find (name
) != NULL
)
183 if (warn_register_name_conflicts
)
184 as_warn (_("Register name %s conflicts with symbol of the same name"),
188 return pre_defined_registers
[middle
].value
;
196 /* register_name() checks the string at input_line_pointer
197 to see if it is a valid register name. */
200 register_name (expressionP
)
201 expressionS
*expressionP
;
204 char c
, *p
= input_line_pointer
;
206 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
213 /* look to see if it's in the register table */
214 reg_number
= reg_name_search (input_line_pointer
);
217 expressionP
->X_op
= O_register
;
218 /* temporarily store a pointer to the string here */
219 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
220 expressionP
->X_add_number
= reg_number
;
221 input_line_pointer
= p
;
231 check_range (num
, bits
, flags
)
239 /* don't bother checking 32-bit values */
243 if (flags
& OPERAND_SHIFT
)
245 /* We know that all shifts are right by three bits.... */
247 if (flags
& OPERAND_SIGNED
)
248 num
= (unsigned long) (((/*signed*/ long) num
) >> 3);
253 if (flags
& OPERAND_SIGNED
)
255 max
= (1 << (bits
- 1))-1;
256 min
= - (1 << (bits
- 1));
257 if (((long)num
> max
) || ((long)num
< min
))
262 max
= (1 << bits
) - 1;
264 if ((num
> max
) || (num
< min
))
273 md_show_usage (stream
)
276 fprintf (stream
, _("\nD30V options:\n\
277 -O Make adjacent short instructions parallel if possible.\n\
278 -n Warn about all NOPs inserted by the assembler.\n\
279 -N Warn about NOPs inserted after word multiplies.\n\
280 -c Warn about symbols whoes names match register names.\n\
281 -C Opposite of -C. -c is the default.\n"));
285 md_parse_option (c
, arg
)
291 /* Optimize. Will attempt to parallelize operations */
296 /* Warn about all NOPS that the assembler inserts. */
301 /* Warn about the NOPS that the assembler inserts because of the
304 warn_nops
= NOP_MULTIPLY
;
308 warn_register_name_conflicts
= 1;
312 warn_register_name_conflicts
= 0;
322 md_undefined_symbol (name
)
328 /* Turn a string in input_line_pointer into a floating point constant of type
329 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
330 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
333 md_atof (type
, litP
, sizeP
)
339 LITTLENUM_TYPE words
[4];
353 return _("bad call to md_atof");
356 t
= atof_ieee (input_line_pointer
, type
, words
);
358 input_line_pointer
= t
;
362 for (i
= 0; i
< prec
; i
++)
364 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
371 md_convert_frag (abfd
, sec
, fragP
)
380 md_section_align (seg
, addr
)
384 int align
= bfd_get_section_alignment (stdoutput
, seg
);
385 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
392 struct d30v_opcode
* opcode
;
393 d30v_hash
= hash_new ();
395 /* Insert opcode names into a hash table. */
396 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
397 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
400 FixUps
[0].next
= &FixUps
[1];
401 FixUps
[1].next
= &FixUps
[0];
403 d30v_current_align_seg
= now_seg
;
407 /* this function removes the postincrement or postdecrement
408 operator ( '+' or '-' ) from an expression */
410 static int postfix (p
)
413 while (*p
!= '-' && *p
!= '+')
415 if (*p
==0 || *p
=='\n' || *p
=='\r' || *p
==' ' || *p
==',')
435 static bfd_reloc_code_real_type
436 get_reloc (op
, rel_flag
)
437 struct d30v_operand
*op
;
443 if (op
->flags
& OPERAND_SHIFT
)
444 return BFD_RELOC_D30V_9_PCREL
;
446 return BFD_RELOC_D30V_6
;
449 if (!(op
->flags
& OPERAND_SHIFT
))
450 as_warn (_("unexpected 12-bit reloc type"));
451 if (rel_flag
== RELOC_PCREL
)
452 return BFD_RELOC_D30V_15_PCREL
;
454 return BFD_RELOC_D30V_15
;
456 if (!(op
->flags
& OPERAND_SHIFT
))
457 as_warn (_("unexpected 18-bit reloc type"));
458 if (rel_flag
== RELOC_PCREL
)
459 return BFD_RELOC_D30V_21_PCREL
;
461 return BFD_RELOC_D30V_21
;
463 if (rel_flag
== RELOC_PCREL
)
464 return BFD_RELOC_D30V_32_PCREL
;
466 return BFD_RELOC_D30V_32
;
472 /* get_operands parses a string of operands and returns
473 an array of expressions */
476 get_operands (exp
, cmp_hack
)
480 char *p
= input_line_pointer
;
486 exp
[numops
].X_op
= O_absent
;
487 exp
[numops
++].X_add_number
= cmp_hack
- 1;
492 while (*p
== ' ' || *p
== '\t' || *p
== ',')
494 if (*p
==0 || *p
=='\n' || *p
=='\r')
500 exp
[numops
].X_op
= O_absent
;
504 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
510 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
514 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
523 /* just skip the trailing paren */
528 input_line_pointer
= p
;
530 /* check to see if it might be a register name */
531 if (!register_name (&exp
[numops
]))
533 /* parse as an expression */
534 expression (&exp
[numops
]);
537 if (exp
[numops
].X_op
== O_illegal
)
538 as_bad (_("illegal operand"));
539 else if (exp
[numops
].X_op
== O_absent
)
540 as_bad (_("missing operand"));
543 p
= input_line_pointer
;
547 case -1: /* postdecrement mode */
548 exp
[numops
].X_op
= O_absent
;
549 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
551 case 1: /* postincrement mode */
552 exp
[numops
].X_op
= O_absent
;
553 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
559 exp
[numops
].X_op
= 0;
563 /* build_insn generates the instruction. It does everything */
564 /* but write the FM bits. */
567 build_insn (opcode
, opers
)
568 struct d30v_insn
*opcode
;
571 int i
, length
, bits
, shift
, flags
;
572 unsigned int number
, id
=0;
574 struct d30v_opcode
*op
= opcode
->op
;
575 struct d30v_format
*form
= opcode
->form
;
577 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
579 for (i
=0; form
->operands
[i
]; i
++)
581 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
583 /* must be a register or number */
584 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
585 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
588 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
589 if (flags
& OPERAND_SHIFT
)
592 length
= d30v_operand_table
[form
->operands
[i
]].length
;
593 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
594 if (opers
[i
].X_op
!= O_symbol
)
595 number
= opers
[i
].X_add_number
;
598 if (flags
& OPERAND_REG
)
600 /* check for mvfsys or mvtsys control registers */
601 if (flags
& OPERAND_CONTROL
&& (number
& 0x7f) > MAX_CONTROL_REG
)
604 id
= (number
& 0x7f) - MAX_CONTROL_REG
;
607 else if (number
& OPERAND_FLAG
)
609 id
= 3; /* number is a flag register */
613 else if (flags
& OPERAND_SPECIAL
)
618 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
620 /* now create a fixup */
622 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
623 as_fatal (_("too many fixups"));
625 fixups
->fix
[fixups
->fc
].reloc
=
626 get_reloc ((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
627 fixups
->fix
[fixups
->fc
].size
= 4;
628 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
629 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
630 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D30V_9_PCREL
)
631 fixups
->fix
[fixups
->fc
].pcrel
= RELOC_PCREL
;
633 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
637 /* truncate to the proper number of bits */
638 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
639 as_bad (_("operand out of range: %d"),number
);
641 number
&= 0x7FFFFFFF >> (31 - bits
);
642 if (flags
& OPERAND_SHIFT
)
646 /* it's a LONG instruction */
647 insn
|= (number
>> 26); /* top 6 bits */
648 insn
<<= 32; /* shift the first word over */
649 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
650 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
653 insn
|= number
<< shift
;
659 /* write out a long form instruction */
661 write_long (opcode
, insn
, fx
)
662 struct d30v_insn
*opcode
;
667 char *f
= frag_more (8);
670 d30v_number_to_chars (f
, insn
, 8);
672 for (i
=0; i
< fx
->fc
; i
++)
674 if (fx
->fix
[i
].reloc
)
676 where
= f
- frag_now
->fr_literal
;
677 fix_new_exp (frag_now
,
689 /* Write out a short form instruction by itself. */
691 write_1_short (opcode
, insn
, fx
, use_sequential
)
692 struct d30v_insn
*opcode
;
697 char *f
= frag_more (8);
700 if (warn_nops
== NOP_ALL
)
701 as_warn (_("%s NOP inserted"), use_sequential
?
702 _("sequential") : _("parallel"));
704 /* The other container needs to be NOP. */
707 /* Use a sequential NOP rather than a parallel one,
708 as the current instruction is a FLAG_MUL32 type one
709 and the next instruction is a load. */
711 /* According to 4.3.1: for FM=01, sub-instructions performed
712 only by IU cannot be encoded in L-container. */
714 if (opcode
->op
->unit
== IU
)
715 insn
|= FM10
| NOP_LEFT
; /* right then left */
717 insn
= FM01
| (insn
<< 32) | NOP_RIGHT
; /* left then right */
721 /* According to 4.3.1: for FM=00, sub-instructions performed
722 only by IU cannot be encoded in L-container. */
724 if (opcode
->op
->unit
== IU
)
725 insn
|= FM00
| NOP_LEFT
; /* right container */
727 insn
= FM00
| (insn
<< 32) | NOP_RIGHT
; /* left container */
730 d30v_number_to_chars (f
, insn
, 8);
732 for (i
=0; i
< fx
->fc
; i
++)
734 if (fx
->fix
[i
].reloc
)
736 where
= f
- frag_now
->fr_literal
;
737 fix_new_exp (frag_now
,
748 /* Write out a short form instruction if possible.
749 Return number of instructions not written out. */
751 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
752 struct d30v_insn
*opcode1
, *opcode2
;
753 long long insn1
, insn2
;
754 exec_type_enum exec_type
;
757 long long insn
= NOP2
;
761 if (exec_type
== EXEC_SEQ
762 && (opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
))
763 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0)
764 && ((opcode1
->ecc
== ECC_AL
) || ! Optimizing
))
766 /* Unconditional, non-delayed branches kill instructions in
767 the right bin. Conditional branches don't always but if
768 we are not optimizing, then we have been asked to produce
769 an error about such constructs. For the purposes of this
770 test, subroutine calls are considered to be branches. */
771 write_1_short (opcode1
, insn1
, fx
->next
, false);
775 /* Note: we do not have to worry about subroutine calls occuring
776 in the right hand container. The return address is always
777 aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
781 case EXEC_UNKNOWN
: /* Order not specified. */
783 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
)
784 && ! ( (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
785 || opcode1
->op
->unit
== MU
)
787 ( opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
788 || opcode2
->op
->unit
== MU
)))
791 exec_type
= EXEC_PARALLEL
;
793 if (opcode1
->op
->unit
== IU
794 || opcode2
->op
->unit
== MU
795 || opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
796 insn
= FM00
| (insn2
<< 32) | insn1
;
799 insn
= FM00
| (insn1
<< 32) | insn2
;
803 else if (opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)
804 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0)
805 && ((opcode1
->ecc
== ECC_AL
) || ! Optimizing
))
807 /* We must emit (non-delayed) branch type instructions
808 on their own with nothing in the right container. */
809 write_1_short (opcode1
, insn1
, fx
->next
, false);
812 else if (opcode1
->op
->unit
== IU
813 || (opcode1
->op
->unit
== EITHER
814 && opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
))
816 /* reverse sequential */
817 insn
= FM10
| (insn2
<< 32) | insn1
;
818 exec_type
= EXEC_REVSEQ
;
823 insn
= FM01
| (insn1
<< 32) | insn2
;
825 exec_type
= EXEC_SEQ
;
829 case EXEC_PARALLEL
: /* parallel */
830 flag_explicitly_parallel
= flag_xp_state
;
831 if (! parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
832 as_bad (_("Instructions may not be executed in parallel"));
833 else if (opcode1
->op
->unit
== IU
)
835 if (opcode2
->op
->unit
== IU
)
836 as_bad (_("Two IU instructions may not be executed in parallel"));
837 as_warn (_("Swapping instruction order"));
838 insn
= FM00
| (insn2
<< 32) | insn1
;
840 else if (opcode2
->op
->unit
== MU
)
842 if (opcode1
->op
->unit
== MU
)
843 as_bad (_("Two MU instructions may not be executed in parallel"));
844 else if (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
)
845 as_warn (_("Executing %s in IU may not work"), opcode1
->op
->name
);
846 as_warn (_("Swapping instruction order"));
847 insn
= FM00
| (insn2
<< 32) | insn1
;
851 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
852 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
854 insn
= FM00
| (insn1
<< 32) | insn2
;
857 flag_explicitly_parallel
= 0;
860 case EXEC_SEQ
: /* sequential */
861 if (opcode1
->op
->unit
== IU
)
862 as_bad (_("IU instruction may not be in the left container"));
863 if (prev_left_kills_right_p
)
864 as_bad (_("special left instruction `%s' kills instruction "
865 "`%s' in right container"),
866 opcode1
->op
->name
, opcode2
->op
->name
);
867 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
868 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
869 insn
= FM01
| (insn1
<< 32) | insn2
;
873 case EXEC_REVSEQ
: /* reverse sequential */
874 if (opcode2
->op
->unit
== MU
)
875 as_bad (_("MU instruction may not be in the right container"));
876 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
877 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
878 insn
= FM10
| (insn1
<< 32) | insn2
;
883 as_fatal (_("unknown execution type passed to write_2_short()"));
886 /* printf ("writing out %llx\n",insn); */
888 d30v_number_to_chars (f
, insn
, 8);
890 /* If the previous instruction was a 32-bit multiply but it is put into a
891 parallel container, mark the current instruction as being a 32-bit
893 if (prev_mul32_p
&& exec_type
== EXEC_PARALLEL
)
898 for (i
=0; i
< fx
->fc
; i
++)
900 if (fx
->fix
[i
].reloc
)
902 where
= (f
- frag_now
->fr_literal
) + 4*j
;
904 fix_new_exp (frag_now
,
921 /* Check 2 instructions and determine if they can be safely */
922 /* executed in parallel. Returns 1 if they can be. */
924 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
925 struct d30v_insn
*op1
, *op2
;
926 unsigned long insn1
, insn2
;
927 exec_type_enum exec_type
;
929 int i
, j
, shift
, regno
, bits
, ecc
;
930 unsigned long flags
, mask
, flags_set1
, flags_set2
, flags_used1
, flags_used2
;
931 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3], flag_reg
[2];
932 struct d30v_format
*f
;
933 struct d30v_opcode
*op
;
935 /* section 4.3: both instructions must not be IU or MU only */
936 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
937 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
940 /* first instruction must not be a jump to safely optimize, unless this
941 is an explicit parallel operation. */
942 if (exec_type
!= EXEC_PARALLEL
943 && (op1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)))
946 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
947 then it is safe to allow the two to be done as parallel ops, since only
948 one will ever be executed at a time. */
949 if ((op1
->ecc
== ECC_TX
&& op2
->ecc
== ECC_FX
)
950 || (op1
->ecc
== ECC_FX
&& op2
->ecc
== ECC_TX
)
951 || (op1
->ecc
== ECC_XT
&& op2
->ecc
== ECC_XF
)
952 || (op1
->ecc
== ECC_XF
&& op2
->ecc
== ECC_XT
))
957 [2] a0, a1, flag registers */
959 for (j
= 0; j
< 2; j
++)
976 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
977 mod_reg
[j
][2] = (op
->flags_set
& FLAG_ALL
);
978 used_reg
[j
][0] = used_reg
[j
][1] = 0;
979 used_reg
[j
][2] = (op
->flags_used
& FLAG_ALL
);
981 /* BSR/JSR always sets R62 */
982 if (op
->flags_used
& FLAG_JSR
)
983 mod_reg
[j
][1] = (1L << (62-32));
985 /* conditional execution affects the flags_used */
990 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_0
;
995 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_1
;
1000 used_reg
[j
][2] |= flag_reg
[j
] = (FLAG_0
| FLAG_1
);
1004 for (i
= 0; f
->operands
[i
]; i
++)
1006 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
1007 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
1008 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
1012 mask
= 0x7FFFFFFF >> (31 - bits
);
1014 if ((flags
& OPERAND_PLUS
) || (flags
& OPERAND_MINUS
))
1016 /* this is a post-increment or post-decrement */
1017 /* the previous register needs to be marked as modified */
1019 shift
= 12 - d30v_operand_table
[f
->operands
[i
-1]].position
;
1020 regno
= (ins
>> shift
) & 0x3f;
1022 mod_reg
[j
][1] |= 1L << (regno
- 32);
1024 mod_reg
[j
][0] |= 1L << regno
;
1026 else if (flags
& OPERAND_REG
)
1028 regno
= (ins
>> shift
) & mask
;
1029 /* the memory write functions don't have a destination register */
1030 if ((flags
& OPERAND_DEST
) && !(op
->flags_set
& FLAG_MEM
))
1032 /* MODIFIED registers and flags */
1033 if (flags
& OPERAND_ACC
)
1036 mod_reg
[j
][2] |= FLAG_A0
;
1037 else if (regno
== 1)
1038 mod_reg
[j
][2] |= FLAG_A1
;
1042 else if (flags
& OPERAND_FLAG
)
1043 mod_reg
[j
][2] |= 1L << regno
;
1044 else if (!(flags
& OPERAND_CONTROL
))
1048 /* need to check if there are two destination */
1049 /* registers, for example ld2w */
1050 if (flags
& OPERAND_2REG
)
1055 for (r
= regno
; r
<= regno
+ z
; r
++)
1058 mod_reg
[j
][1] |= 1L << (r
- 32);
1060 mod_reg
[j
][0] |= 1L << r
;
1066 /* USED, but not modified registers and flags */
1067 if (flags
& OPERAND_ACC
)
1070 used_reg
[j
][2] |= FLAG_A0
;
1071 else if (regno
== 1)
1072 used_reg
[j
][2] |= FLAG_A1
;
1076 else if (flags
& OPERAND_FLAG
)
1077 used_reg
[j
][2] |= 1L << regno
;
1078 else if (!(flags
& OPERAND_CONTROL
))
1082 /* need to check if there are two source */
1083 /* registers, for example st2w */
1084 if (flags
& OPERAND_2REG
)
1089 for (r
= regno
; r
<= regno
+ z
; r
++)
1092 used_reg
[j
][1] |= 1L << (r
- 32);
1094 used_reg
[j
][0] |= 1L << r
;
1102 flags_set1
= op1
->op
->flags_set
;
1103 flags_set2
= op2
->op
->flags_set
;
1104 flags_used1
= op1
->op
->flags_used
;
1105 flags_used2
= op2
->op
->flags_used
;
1107 /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */
1108 if (((flags_set1
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1109 && (flags_used2
& FLAG_ADDSUBppp
) != 0)
1110 || ((flags_set2
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1111 && (flags_used1
& FLAG_ADDSUBppp
) != 0))
1114 /* Load instruction combined with half-word multiply is illegal. */
1115 if (((flags_used1
& FLAG_MEM
) != 0 && (flags_used2
& FLAG_MUL16
))
1116 || ((flags_used2
& FLAG_MEM
) != 0 && (flags_used1
& FLAG_MUL16
)))
1119 /* Specifically allow add || add by removing carry, overflow bits dependency.
1120 This is safe, even if an addc follows since the IU takes the argument in
1121 the right container, and it writes its results last.
1122 However, don't paralellize add followed by addc or sub followed by
1125 if (mod_reg
[0][2] == FLAG_CVVA
&& mod_reg
[1][2] == FLAG_CVVA
1126 && (used_reg
[0][2] & ~flag_reg
[0]) == 0
1127 && (used_reg
[1][2] & ~flag_reg
[1]) == 0
1128 && op1
->op
->unit
== EITHER
&& op2
->op
->unit
== EITHER
)
1130 mod_reg
[0][2] = mod_reg
[1][2] = 0;
1133 for (j
= 0; j
< 3; j
++)
1135 /* If the second instruction depends on the first, we obviously
1136 cannot parallelize. Note, the mod flag implies use, so
1137 check that as well. */
1138 /* If flag_explicitly_parallel is set, then the case of the
1139 second instruction using a register the first instruction
1140 modifies is assumed to be okay; we trust the human. We
1141 don't trust the human if both instructions modify the same
1142 register but we do trust the human if they modify the same
1144 /* We have now been requested not to trust the human if the
1145 instructions modify the same flag registers either. */
1146 if (flag_explicitly_parallel
)
1148 if ((mod_reg
[0][j
] & mod_reg
[1][j
]) != 0)
1152 if ((mod_reg
[0][j
] & (mod_reg
[1][j
] | used_reg
[1][j
])) != 0)
1160 /* This is the main entry point for the machine-dependent assembler. str points to a
1161 machine-dependent instruction. This function is supposed to emit the frags/bytes
1162 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
1163 and leaves the difficult stuff to do_assemble(). */
1165 static long long prev_insn
= -1;
1166 static struct d30v_insn prev_opcode
;
1167 static subsegT prev_subseg
;
1168 static segT prev_seg
= 0;
1174 struct d30v_insn opcode
;
1176 exec_type_enum extype
= EXEC_UNKNOWN
; /* execution type; parallel, etc */
1177 static exec_type_enum etype
= EXEC_UNKNOWN
; /* saved extype. used for multiline instructions */
1180 if ((prev_insn
!= -1) && prev_seg
1181 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1182 d30v_cleanup (false);
1184 if (d30v_current_align
< 3)
1185 d30v_align (3, NULL
, d30v_last_label
);
1186 else if (d30v_current_align
> 3)
1187 d30v_current_align
= 3;
1188 d30v_last_label
= NULL
;
1190 flag_explicitly_parallel
= 0;
1192 if (etype
== EXEC_UNKNOWN
)
1194 /* look for the special multiple instruction separators */
1195 str2
= strstr (str
, "||");
1198 extype
= EXEC_PARALLEL
;
1203 str2
= strstr (str
, "->");
1208 str2
= strstr (str
, "<-");
1210 extype
= EXEC_REVSEQ
;
1213 /* str2 points to the separator, if one */
1218 /* if two instructions are present and we already have one saved
1219 then first write it out */
1220 d30v_cleanup (false);
1222 /* Assemble first instruction and save it. */
1223 prev_insn
= do_assemble (str
, &prev_opcode
, 1, 0);
1224 if (prev_insn
== -1)
1225 as_bad (_("Cannot assemble instruction"));
1226 if (prev_opcode
.form
->form
>= LONG
)
1227 as_bad (_("First opcode is long. Unable to mix instructions as specified."));
1228 fixups
= fixups
->next
;
1231 prev_subseg
= now_subseg
;
1235 insn
= do_assemble (str
, &opcode
,
1236 (extype
!= EXEC_UNKNOWN
|| etype
!= EXEC_UNKNOWN
),
1237 extype
== EXEC_PARALLEL
);
1240 if (extype
!= EXEC_UNKNOWN
)
1245 as_bad (_("Cannot assemble instruction"));
1248 if (etype
!= EXEC_UNKNOWN
)
1251 etype
= EXEC_UNKNOWN
;
1254 /* Word multiply instructions must not be followed by either a load or a
1255 16-bit multiply instruction in the next cycle. */
1256 if ( (extype
!= EXEC_REVSEQ
)
1258 && (opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1260 /* However, load and multiply should able to be combined in a parallel
1261 operation, so check for that first. */
1263 && (opcode
.op
->flags_used
& FLAG_MEM
)
1264 && opcode
.form
->form
< LONG
1265 && (extype
== EXEC_PARALLEL
|| (Optimizing
&& extype
== EXEC_UNKNOWN
))
1266 && parallel_ok (&prev_opcode
, (long)prev_insn
,
1267 &opcode
, (long)insn
, extype
)
1268 && write_2_short (&prev_opcode
, (long)prev_insn
,
1269 &opcode
, (long)insn
, extype
, fixups
) == 0)
1271 /* no instructions saved */
1277 /* Can't parallelize, flush previous instruction and emit a word of NOPS,
1278 unless the previous instruction is a NOP, in which case just flush it,
1279 as this will generate a word of NOPs for us. */
1281 if (prev_insn
!= -1 && (strcmp (prev_opcode
.op
->name
, "nop") == 0))
1282 d30v_cleanup (false);
1287 if (prev_insn
!= -1)
1288 d30v_cleanup (true);
1292 d30v_number_to_chars (f
, NOP2
, 8);
1294 if (warn_nops
== NOP_ALL
|| warn_nops
== NOP_MULTIPLY
)
1296 if (opcode
.op
->flags_used
& FLAG_MEM
)
1297 as_warn (_("word of NOPs added between word multiply and load"));
1299 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1304 extype
= EXEC_UNKNOWN
;
1307 else if ( (extype
== EXEC_REVSEQ
)
1309 && (prev_opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1311 /* Can't parallelize, flush current instruction and add a sequential NOP. */
1312 write_1_short (& opcode
, (long) insn
, fixups
->next
->next
, true);
1314 /* Make the previous instruction the current one. */
1315 extype
= EXEC_UNKNOWN
;
1318 now_subseg
= prev_subseg
;
1320 cur_mul32_p
= prev_mul32_p
;
1322 memcpy (&opcode
, &prev_opcode
, sizeof (prev_opcode
));
1325 /* If this is a long instruction, write it and any previous short instruction. */
1326 if (opcode
.form
->form
>= LONG
)
1328 if (extype
!= EXEC_UNKNOWN
)
1329 as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
1330 d30v_cleanup (false);
1331 write_long (& opcode
, insn
, fixups
);
1334 else if ((prev_insn
!= -1)
1336 (& prev_opcode
, (long) prev_insn
, & opcode
,
1337 (long) insn
, extype
, fixups
) == 0))
1339 /* No instructions saved. */
1344 if (extype
!= EXEC_UNKNOWN
)
1345 as_bad (_("Unable to mix instructions as specified"));
1347 /* Save off last instruction so it may be packed on next pass. */
1348 memcpy (&prev_opcode
, &opcode
, sizeof (prev_opcode
));
1351 prev_subseg
= now_subseg
;
1352 fixups
= fixups
->next
;
1353 prev_mul32_p
= cur_mul32_p
;
1358 /* do_assemble assembles a single instruction and returns an opcode */
1359 /* it returns -1 (an invalid opcode) on error */
1362 do_assemble (str
, opcode
, shortp
, is_parallel
)
1364 struct d30v_insn
*opcode
;
1368 unsigned char *op_start
, *save
;
1369 unsigned char *op_end
;
1371 int cmp_hack
, nlen
= 0, fsize
= (shortp
? FORCE_SHORT
: 0);
1372 expressionS myops
[6];
1375 /* Drop leading whitespace */
1379 /* find the opcode end */
1380 for (op_start
= op_end
= (unsigned char *) (str
);
1384 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1387 name
[nlen
] = tolower (op_start
[nlen
]);
1396 /* if there is an execution condition code, handle it */
1400 while ( (i
< ECC_MAX
) && strncasecmp (d30v_ecc_names
[i
], op_end
+ 1, 2))
1406 strncpy (tmp
, op_end
+ 1, 2);
1408 as_bad (_("unknown condition code: %s"),tmp
);
1411 /* printf ("condition code=%d\n",i); */
1416 opcode
->ecc
= ECC_AL
;
1419 /* CMP and CMPU change their name based on condition codes */
1420 if (!strncmp (name
, "cmp", 3))
1423 char **str
= (char **)d30v_cc_names
;
1429 for (i
=1; *str
&& strncmp (*str
, & name
[p
], 2); i
++, str
++)
1432 /* cmpu only supports some condition codes */
1438 as_bad (_("cmpu doesn't support condition code %s"),&name
[p
]);
1445 as_bad (_("unknown condition code: %s"),&name
[p
]);
1454 /* printf("cmp_hack=%d\n",cmp_hack); */
1456 /* need to look for .s or .l */
1457 if (name
[nlen
-2] == '.')
1459 switch (name
[nlen
-1])
1462 fsize
= FORCE_SHORT
;
1471 /* find the first opcode with the proper name */
1472 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1473 if (opcode
->op
== NULL
)
1474 as_bad (_("unknown opcode: %s"),name
);
1476 save
= input_line_pointer
;
1477 input_line_pointer
= op_end
;
1478 while (!(opcode
->form
= find_format (opcode
->op
, myops
, fsize
, cmp_hack
)))
1481 if (strcmp (opcode
->op
->name
, name
))
1482 as_bad (_("operands for opcode `%s' do not match any valid format"), name
);
1484 input_line_pointer
= save
;
1486 insn
= build_insn (opcode
, myops
);
1488 /* Propigate multiply status */
1491 if (is_parallel
&& prev_mul32_p
)
1495 prev_mul32_p
= cur_mul32_p
;
1496 cur_mul32_p
= (opcode
->op
->flags_used
& FLAG_MUL32
) != 0;
1500 /* Propagate left_kills_right status */
1503 prev_left_kills_right_p
= cur_left_kills_right_p
;
1505 if (opcode
->op
->flags_set
& FLAG_LKR
)
1507 cur_left_kills_right_p
= 1;
1509 if (strcmp (opcode
->op
->name
, "mvtsys") == 0)
1511 /* Left kills right for only mvtsys only for PSW/PSWH/PSWL/flags target. */
1512 if ((myops
[0].X_op
== O_register
) &&
1513 ((myops
[0].X_add_number
== OPERAND_CONTROL
) || /* psw */
1514 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+2) || /* pswh */
1515 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+1) || /* pswl */
1516 (myops
[0].X_add_number
== OPERAND_FLAG
+0) || /* f0 */
1517 (myops
[0].X_add_number
== OPERAND_FLAG
+1) || /* f1 */
1518 (myops
[0].X_add_number
== OPERAND_FLAG
+2) || /* f2 */
1519 (myops
[0].X_add_number
== OPERAND_FLAG
+3) || /* f3 */
1520 (myops
[0].X_add_number
== OPERAND_FLAG
+4) || /* f4 */
1521 (myops
[0].X_add_number
== OPERAND_FLAG
+5) || /* f5 */
1522 (myops
[0].X_add_number
== OPERAND_FLAG
+6) || /* f6 */
1523 (myops
[0].X_add_number
== OPERAND_FLAG
+7))) /* f7 */
1525 cur_left_kills_right_p
= 1;
1529 /* Other mvtsys target registers don't kill right instruction. */
1530 cur_left_kills_right_p
= 0;
1535 cur_left_kills_right_p
= 0;
1543 /* find_format() gets a pointer to an entry in the format table.
1544 It must look at all formats for an opcode and use the operands
1545 to choose the correct one. Returns NULL on error. */
1547 static struct d30v_format
*
1548 find_format (opcode
, myops
, fsize
, cmp_hack
)
1549 struct d30v_opcode
*opcode
;
1550 expressionS myops
[];
1554 int numops
, match
, index
, i
=0, j
, k
;
1555 struct d30v_format
*fm
;
1557 /* Get all the operands and save them as expressions. */
1558 numops
= get_operands (myops
, cmp_hack
);
1560 while ((index
= opcode
->format
[i
++]) != 0)
1562 if (fsize
== FORCE_SHORT
&& index
>= LONG
)
1565 if (fsize
== FORCE_LONG
&& index
< LONG
)
1568 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1570 while (fm
->form
== index
)
1573 /* Now check the operands for compatibility. */
1574 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1576 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1577 int bits
= d30v_operand_table
[fm
->operands
[j
]].bits
;
1578 int X_op
= myops
[j
].X_op
;
1579 int num
= myops
[j
].X_add_number
;
1581 if (flags
& OPERAND_SPECIAL
)
1583 else if (X_op
== O_illegal
)
1585 else if (flags
& OPERAND_REG
)
1587 if (X_op
!= O_register
1588 || ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
))
1589 || (!(flags
& OPERAND_ACC
) && (num
& OPERAND_ACC
))
1590 || ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
))
1591 || (!(flags
& (OPERAND_FLAG
| OPERAND_CONTROL
)) && (num
& OPERAND_FLAG
))
1592 || ((flags
& OPERAND_CONTROL
)
1593 && !(num
& (OPERAND_CONTROL
| OPERAND_FLAG
))))
1598 else if (((flags
& OPERAND_MINUS
)
1599 && (X_op
!= O_absent
|| num
!= OPERAND_MINUS
))
1600 || ((flags
& OPERAND_PLUS
)
1601 && (X_op
!= O_absent
|| num
!= OPERAND_PLUS
))
1602 || ((flags
& OPERAND_ATMINUS
)
1603 && (X_op
!= O_absent
|| num
!= OPERAND_ATMINUS
))
1604 || ((flags
& OPERAND_ATPAR
)
1605 && (X_op
!= O_absent
|| num
!= OPERAND_ATPAR
))
1606 || ((flags
& OPERAND_ATSIGN
)
1607 && (X_op
!= O_absent
|| num
!= OPERAND_ATSIGN
)))
1611 else if (flags
& OPERAND_NUM
)
1613 /* A number can be a constant or symbol expression. */
1615 /* If we have found a register name, but that name also
1616 matches a symbol, then re-parse the name as an expression. */
1617 if (X_op
== O_register
1618 && symbol_find ((char *) myops
[j
].X_op_symbol
))
1620 input_line_pointer
= (char *) myops
[j
].X_op_symbol
;
1621 expression (& myops
[j
]);
1624 /* Turn an expression into a symbol for later resolution. */
1625 if (X_op
!= O_absent
&& X_op
!= O_constant
1626 && X_op
!= O_symbol
&& X_op
!= O_register
1629 symbolS
*sym
= make_expr_symbol (&myops
[j
]);
1630 myops
[j
].X_op
= X_op
= O_symbol
;
1631 myops
[j
].X_add_symbol
= sym
;
1632 myops
[j
].X_add_number
= num
= 0;
1635 if (fm
->form
>= LONG
)
1637 /* If we're testing for a LONG format, either fits. */
1638 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1641 else if (fm
->form
< LONG
1642 && ((fsize
== FORCE_SHORT
&& X_op
== O_symbol
)
1643 || (fm
->form
== SHORT_D2
&& j
== 0)))
1645 /* This is the tricky part. Will the constant or symbol
1646 fit into the space in the current format? */
1647 else if (X_op
== O_constant
)
1649 if (check_range (num
, bits
, flags
))
1652 else if (X_op
== O_symbol
1653 && S_IS_DEFINED (myops
[j
].X_add_symbol
)
1654 && S_GET_SEGMENT (myops
[j
].X_add_symbol
) == now_seg
1655 && opcode
->reloc_flag
== RELOC_PCREL
)
1657 /* If the symbol is defined, see if the value will fit
1658 into the form we're considering. */
1662 /* Calculate the current address by running through the
1663 previous frags and adding our current offset. */
1665 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1666 value
+= f
->fr_fix
+ f
->fr_offset
;
1667 value
= (S_GET_VALUE (myops
[j
].X_add_symbol
) - value
1668 - (obstack_next_free (&frchain_now
->frch_obstack
)
1669 - frag_now
->fr_literal
));
1670 if (check_range (value
, bits
, flags
))
1677 /* printf("through the loop: match=%d\n",match); */
1678 /* We're only done if the operands matched so far AND there
1679 are no more to check. */
1680 if (match
&& myops
[j
].X_op
== 0)
1682 /* Final check - issue a warning if an odd numbered register
1683 is used as the first register in an instruction that reads
1684 or writes 2 registers. */
1686 for (j
= 0; fm
->operands
[j
]; j
++)
1687 if (myops
[j
].X_op
== O_register
1688 && (myops
[j
].X_add_number
& 1)
1689 && (d30v_operand_table
[fm
->operands
[j
]].flags
& OPERAND_2REG
))
1691 _("Odd numbered register used as target of multi-register instruction"));
1695 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1697 /* printf("trying another format: i=%d\n",i); */
1702 /* if while processing a fixup, a reloc really needs to be created */
1703 /* then it is done here */
1706 tc_gen_reloc (seg
, fixp
)
1711 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1712 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1713 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1714 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1715 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1717 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1718 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1721 reloc
->addend
= fixp
->fx_addnumber
;
1726 md_estimate_size_before_relax (fragp
, seg
)
1735 md_pcrel_from_section (fixp
, sec
)
1739 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1740 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1742 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1746 md_apply_fix3 (fixp
, valuep
, seg
)
1752 unsigned long insn
, insn2
;
1755 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1760 else if (fixp
->fx_pcrel
)
1764 value
= fixp
->fx_offset
;
1766 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1768 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1769 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1772 /* We don't actually support subtracting a symbol. */
1773 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1774 _("expression too complex"));
1779 /* Fetch the instruction, insert the fully resolved operand
1780 value, and stuff the instruction back again. */
1781 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1782 insn
= bfd_getb32 ((unsigned char *) where
);
1784 switch (fixp
->fx_r_type
)
1786 case BFD_RELOC_8
: /* Caused by a bad .byte directive. */
1789 case BFD_RELOC_16
: /* Caused by a bad .short directive. */
1792 case BFD_RELOC_64
: /* Caused by a bad .quad directive. */
1796 size
= (fixp
->fx_r_type
== BFD_RELOC_8
) ? _("byte")
1797 : (fixp
->fx_r_type
== BFD_RELOC_16
) ? _("short")
1800 if (fixp
->fx_addsy
== NULL
)
1801 as_bad (_("line %d: unable to place address into a %s"),
1802 fixp
->fx_line
, size
);
1804 as_bad (_("line %d: unable to place address of symbol '%s' into a %s"),
1806 S_GET_NAME (fixp
->fx_addsy
),
1811 case BFD_RELOC_D30V_6
:
1812 check_size (value
, 6, fixp
->fx_file
, fixp
->fx_line
);
1813 insn
|= value
& 0x3F;
1814 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1817 case BFD_RELOC_D30V_9_PCREL
:
1818 if (fixp
->fx_where
& 0x7)
1823 fixp
->fx_r_type
= BFD_RELOC_D30V_9_PCREL_R
;
1825 check_size (value
, 9, fixp
->fx_file
, fixp
->fx_line
);
1826 insn
|= ((value
>> 3) & 0x3F) << 12;
1827 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1830 case BFD_RELOC_D30V_15
:
1831 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1832 insn
|= (value
>> 3) & 0xFFF;
1833 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1836 case BFD_RELOC_D30V_15_PCREL
:
1837 if (fixp
->fx_where
& 0x7)
1842 fixp
->fx_r_type
= BFD_RELOC_D30V_15_PCREL_R
;
1844 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1845 insn
|= (value
>> 3) & 0xFFF;
1846 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1849 case BFD_RELOC_D30V_21
:
1850 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1851 insn
|= (value
>> 3) & 0x3FFFF;
1852 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1855 case BFD_RELOC_D30V_21_PCREL
:
1856 if (fixp
->fx_where
& 0x7)
1861 fixp
->fx_r_type
= BFD_RELOC_D30V_21_PCREL_R
;
1863 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1864 insn
|= (value
>> 3) & 0x3FFFF;
1865 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1868 case BFD_RELOC_D30V_32
:
1869 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1870 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1871 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1872 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1873 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1874 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1877 case BFD_RELOC_D30V_32_PCREL
:
1878 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1879 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1880 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1881 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1882 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1883 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1887 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1891 as_bad (_("line %d: unknown relocation type: 0x%x"),
1892 fixp
->fx_line
,fixp
->fx_r_type
);
1899 /* d30v_cleanup() is called after the assembler has finished parsing the input
1900 file or after a label is defined. Because the D30V assembler sometimes saves short
1901 instructions to see if it can package them with the next instruction, there may
1902 be a short instruction that still needs written. */
1904 d30v_cleanup (use_sequential
)
1910 if (prev_insn
!= -1)
1913 subseg
= now_subseg
;
1914 subseg_set (prev_seg
, prev_subseg
);
1915 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
, use_sequential
);
1916 subseg_set (seg
, subseg
);
1919 prev_mul32_p
= false;
1925 d30v_number_to_chars (buf
, value
, n
)
1926 char *buf
; /* Return 'nbytes' of chars here. */
1927 long long value
; /* The value of the bits. */
1928 int n
; /* Number of bytes in the output. */
1932 buf
[n
] = value
& 0xff;
1938 /* This function is called at the start of every line. */
1939 /* it checks to see if the first character is a '.' */
1940 /* which indicates the start of a pseudo-op. If it is, */
1941 /* then write out any unwritten instructions */
1946 char *c
= input_line_pointer
;
1948 while (isspace (*c
))
1952 d30v_cleanup (false);
1956 check_size (value
, bits
, file
, line
)
1969 max
= (1 << (bits
- 1)) - 1;
1972 as_bad_where (file
, line
, _("value too large to fit in %d bits"), bits
);
1977 /* d30v_frob_label() is called when after a label is recognized. */
1980 d30v_frob_label (lab
)
1983 /* Emit any pending instructions. */
1984 d30v_cleanup (false);
1986 /* Update the label's address with the current output pointer. */
1987 lab
->sy_frag
= frag_now
;
1988 S_SET_VALUE (lab
, (valueT
) frag_now_fix ());
1990 /* Record this label for future adjustment after we find out what
1991 kind of data it references, and the required alignment therewith. */
1992 d30v_last_label
= lab
;
1995 /* Hook into cons for capturing alignment changes. */
1998 d30v_cons_align (size
)
2004 while ((size
>>= 1) != 0)
2007 if (d30v_current_align
< log_size
)
2008 d30v_align (log_size
, (char *) NULL
, NULL
);
2009 else if (d30v_current_align
> log_size
)
2010 d30v_current_align
= log_size
;
2011 d30v_last_label
= NULL
;
2014 /* Called internally to handle all alignment needs. This takes care
2015 of eliding calls to frag_align if'n the cached current alignment
2016 says we've already got it, as well as taking care of the auto-aligning
2020 d30v_align (n
, pfill
, label
)
2025 /* The front end is prone to changing segments out from under us
2026 temporarily when -g is in effect. */
2027 int switched_seg_p
= (d30v_current_align_seg
!= now_seg
);
2029 /* Do not assume that if 'd30v_current_align >= n' and
2030 '! switched_seg_p' that it is safe to avoid performing
2031 this alignement request. The alignment of the current frag
2032 can be changed under our feet, for example by a .ascii
2033 directive in the source code. cf testsuite/gas/d30v/reloc.s */
2035 d30v_cleanup (false);
2040 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
2042 static char const nop
[4] = { 0x00, 0xf0, 0x00, 0x00 };
2044 /* First, make sure we're on a four-byte boundary, in case
2045 someone has been putting .byte values the text section. */
2046 if (d30v_current_align
< 2 || switched_seg_p
)
2047 frag_align (2, 0, 0);
2048 frag_align_pattern (n
, nop
, sizeof nop
, 0);
2051 frag_align (n
, 0, 0);
2054 frag_align (n
, *pfill
, 0);
2056 if (!switched_seg_p
)
2057 d30v_current_align
= n
;
2062 int label_seen
= false;
2063 struct frag
* old_frag
;
2067 assert (S_GET_SEGMENT (label
) == now_seg
);
2069 old_frag
= label
->sy_frag
;
2070 old_value
= S_GET_VALUE (label
);
2071 new_value
= (valueT
) frag_now_fix ();
2073 /* It is possible to have more than one label at a particular
2074 address, especially if debugging is enabled, so we must
2075 take care to adjust all the labels at this address in this
2076 fragment. To save time we search from the end of the symbol
2077 list, backwards, since the symbols we are interested in are
2078 almost certainly the ones that were most recently added.
2079 Also to save time we stop searching once we have seen at least
2080 one matching label, and we encounter a label that is no longer
2081 in the target fragment. Note, this search is guaranteed to
2082 find at least one match when sym == label, so no special case
2083 code is necessary. */
2084 for (sym
= symbol_lastP
; sym
!= NULL
; sym
= sym
->sy_previous
)
2086 if (sym
->sy_frag
== old_frag
&& S_GET_VALUE (sym
) == old_value
)
2089 sym
->sy_frag
= frag_now
;
2090 S_SET_VALUE (sym
, new_value
);
2092 else if (label_seen
&& sym
->sy_frag
!= old_frag
)
2097 record_alignment (now_seg
, n
);
2100 /* Handle the .align pseudo-op. This aligns to a power of two. We
2101 hook here to latch the current alignment. */
2104 s_d30v_align (ignore
)
2108 char fill
, *pfill
= NULL
;
2109 long max_alignment
= 15;
2111 align
= get_absolute_expression ();
2112 if (align
> max_alignment
)
2114 align
= max_alignment
;
2115 as_warn (_("Alignment too large: %d assumed"), align
);
2119 as_warn (_("Alignment negative: 0 assumed"));
2123 if (*input_line_pointer
== ',')
2125 input_line_pointer
++;
2126 fill
= get_absolute_expression ();
2130 d30v_last_label
= NULL
;
2131 d30v_align (align
, pfill
, NULL
);
2133 demand_empty_rest_of_line ();
2136 /* Handle the .text pseudo-op. This is like the usual one, but it
2137 clears the saved last label and resets known alignment. */
2145 d30v_last_label
= NULL
;
2146 d30v_current_align
= 0;
2147 d30v_current_align_seg
= now_seg
;
2150 /* Handle the .data pseudo-op. This is like the usual one, but it
2151 clears the saved last label and resets known alignment. */
2158 d30v_last_label
= NULL
;
2159 d30v_current_align
= 0;
2160 d30v_current_align_seg
= now_seg
;
2163 /* Handle the .section pseudo-op. This is like the usual one, but it
2164 clears the saved last label and resets known alignment. */
2167 s_d30v_section (ignore
)
2170 obj_elf_section (ignore
);
2171 d30v_last_label
= NULL
;
2172 d30v_current_align
= 0;
2173 d30v_current_align_seg
= now_seg
;