1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
3 Copyright (C) 1997, 1998 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d30v.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "OnNcC";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
35 #define NOP_MULTIPLY 1
37 static int warn_nops
= 0;
38 static int Optimizing
= 0;
39 static int warn_register_name_conflicts
= 1;
45 typedef enum _exec_type
47 EXEC_UNKNOWN
, /* no order specified */
48 EXEC_PARALLEL
, /* done in parallel (FM=00) */
49 EXEC_SEQ
, /* sequential (FM=01) */
50 EXEC_REVSEQ
/* reverse sequential (FM=10) */
54 #define MAX_INSN_FIXUPS (5)
61 bfd_reloc_code_real_type reloc
;
64 typedef struct _fixups
67 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
71 static Fixups FixUps
[2];
72 static Fixups
*fixups
;
74 /* Whether current and previous instruction are word multiply insns. */
75 static int cur_mul32_p
= 0;
76 static int prev_mul32_p
= 0;
78 /* The flag_explicitly_parallel is true iff the instruction being assembled
79 has been explicitly written as a parallel short-instruction pair by the
80 human programmer. It is used in parallel_ok() to distinguish between
81 those dangerous parallelizations attempted by the human, which are to be
82 allowed, and those attempted by the assembler, which are not. It is set
83 from md_assemble(). */
84 static int flag_explicitly_parallel
= 0;
85 static int flag_xp_state
= 0;
87 /* Whether current and previous left sub-instruction disables
88 execution of right sub-instruction. */
89 static int cur_left_kills_right_p
= 0;
90 static int prev_left_kills_right_p
= 0;
92 /* The known current alignment of the current section. */
93 static int d30v_current_align
;
94 static segT d30v_current_align_seg
;
96 /* The last seen label in the current section. This is used to auto-align
97 labels preceeding instructions. */
98 static symbolS
*d30v_last_label
;
101 #define NOP_LEFT ((long long)NOP << 32)
102 #define NOP_RIGHT ((long long)NOP)
103 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
105 /* local functions */
106 static int reg_name_search
PARAMS ((char *name
));
107 static int register_name
PARAMS ((expressionS
*expressionP
));
108 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
109 static int postfix
PARAMS ((char *p
));
110 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
111 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
112 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
,
113 expressionS ops
[],int fsize
, int cmp_hack
));
114 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
115 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
116 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
,
117 Fixups
*fx
, int use_sequential
));
118 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
119 struct d30v_insn
*opcode2
, long long insn2
, exec_type_enum exec_type
, Fixups
*fx
));
120 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
,
121 int shortp
, int is_parallel
));
122 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
123 struct d30v_insn
*opcode2
, unsigned long insn2
,
124 exec_type_enum exec_type
));
125 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
126 static void check_size
PARAMS ((long value
, int bits
, char *file
, int line
));
127 static void d30v_align
PARAMS ((int, char *, symbolS
*));
128 static void s_d30v_align
PARAMS ((int));
129 static void s_d30v_text
PARAMS ((int));
130 static void s_d30v_data
PARAMS ((int));
131 static void s_d30v_section
PARAMS ((int));
133 struct option md_longopts
[] = {
134 {NULL
, no_argument
, NULL
, 0}
136 size_t md_longopts_size
= sizeof(md_longopts
);
139 /* The target specific pseudo-ops which we support. */
140 const pseudo_typeS md_pseudo_table
[] =
143 { "hword", cons
, 2 },
144 { "align", s_d30v_align
, 0 },
145 { "text", s_d30v_text
, 0 },
146 { "data", s_d30v_data
, 0 },
147 { "section", s_d30v_section
, 0 },
148 { "section.s", s_d30v_section
, 0 },
149 { "sect", s_d30v_section
, 0 },
150 { "sect.s", s_d30v_section
, 0 },
154 /* Opcode hash table. */
155 static struct hash_control
*d30v_hash
;
157 /* reg_name_search does a binary search of the pre_defined_registers
158 array to see if "name" is a valid regiter name. Returns the register
159 number from the array on success, or -1 on failure. */
162 reg_name_search (name
)
165 int middle
, low
, high
;
169 high
= reg_name_cnt () - 1;
173 middle
= (low
+ high
) / 2;
174 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
181 if (symbol_find (name
) != NULL
)
183 if (warn_register_name_conflicts
)
184 as_warn (_("Register name %s conflicts with symbol of the same name"),
188 return pre_defined_registers
[middle
].value
;
196 /* register_name() checks the string at input_line_pointer
197 to see if it is a valid register name. */
200 register_name (expressionP
)
201 expressionS
*expressionP
;
204 char c
, *p
= input_line_pointer
;
206 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
213 /* look to see if it's in the register table */
214 reg_number
= reg_name_search (input_line_pointer
);
217 expressionP
->X_op
= O_register
;
218 /* temporarily store a pointer to the string here */
219 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
220 expressionP
->X_add_number
= reg_number
;
221 input_line_pointer
= p
;
231 check_range (num
, bits
, flags
)
239 /* don't bother checking 32-bit values */
243 if (flags
& OPERAND_SHIFT
)
245 /* We know that all shifts are right by three bits.... */
247 if (flags
& OPERAND_SIGNED
)
248 num
= (unsigned long) (((/*signed*/ long) num
) >> 3);
253 if (flags
& OPERAND_SIGNED
)
255 max
= (1 << (bits
- 1))-1;
256 min
= - (1 << (bits
- 1));
257 if (((long)num
> max
) || ((long)num
< min
))
262 max
= (1 << bits
) - 1;
264 if ((num
> max
) || (num
< min
))
272 md_show_usage (stream
)
275 fprintf (stream
, _("\nD30V options:\n\
276 -O Make adjacent short instructions parallel if possible.\n\
277 -n Warn about all NOPs inserted by the assembler.\n\
278 -N Warn about NOPs inserted after word multiplies.\n\
279 -c Warn about symbols whoes names match register names.\n\
280 -C Opposite of -C. -c is the default.\n"));
284 md_parse_option (c
, arg
)
290 /* Optimize. Will attempt to parallelize operations */
295 /* Warn about all NOPS that the assembler inserts. */
300 /* Warn about the NOPS that the assembler inserts because of the
303 warn_nops
= NOP_MULTIPLY
;
307 warn_register_name_conflicts
= 1;
311 warn_register_name_conflicts
= 0;
321 md_undefined_symbol (name
)
327 /* Turn a string in input_line_pointer into a floating point constant of type
328 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
329 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
332 md_atof (type
, litP
, sizeP
)
338 LITTLENUM_TYPE words
[4];
352 return _("bad call to md_atof");
355 t
= atof_ieee (input_line_pointer
, type
, words
);
357 input_line_pointer
= t
;
361 for (i
= 0; i
< prec
; i
++)
363 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
370 md_convert_frag (abfd
, sec
, fragP
)
379 md_section_align (seg
, addr
)
383 int align
= bfd_get_section_alignment (stdoutput
, seg
);
384 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
391 struct d30v_opcode
*opcode
;
392 d30v_hash
= hash_new ();
394 /* Insert opcode names into a hash table. */
395 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
396 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
399 FixUps
[0].next
= &FixUps
[1];
400 FixUps
[1].next
= &FixUps
[0];
402 d30v_current_align_seg
= now_seg
;
406 /* this function removes the postincrement or postdecrement
407 operator ( '+' or '-' ) from an expression */
409 static int postfix (p
)
412 while (*p
!= '-' && *p
!= '+')
414 if (*p
==0 || *p
=='\n' || *p
=='\r' || *p
==' ' || *p
==',')
434 static bfd_reloc_code_real_type
435 get_reloc (op
, rel_flag
)
436 struct d30v_operand
*op
;
442 if (op
->flags
& OPERAND_SHIFT
)
443 return BFD_RELOC_D30V_9_PCREL
;
445 return BFD_RELOC_D30V_6
;
448 if (!(op
->flags
& OPERAND_SHIFT
))
449 as_warn (_("unexpected 12-bit reloc type"));
450 if (rel_flag
== RELOC_PCREL
)
451 return BFD_RELOC_D30V_15_PCREL
;
453 return BFD_RELOC_D30V_15
;
455 if (!(op
->flags
& OPERAND_SHIFT
))
456 as_warn (_("unexpected 18-bit reloc type"));
457 if (rel_flag
== RELOC_PCREL
)
458 return BFD_RELOC_D30V_21_PCREL
;
460 return BFD_RELOC_D30V_21
;
462 if (rel_flag
== RELOC_PCREL
)
463 return BFD_RELOC_D30V_32_PCREL
;
465 return BFD_RELOC_D30V_32
;
471 /* get_operands parses a string of operands and returns
472 an array of expressions */
475 get_operands (exp
, cmp_hack
)
479 char *p
= input_line_pointer
;
485 exp
[numops
].X_op
= O_absent
;
486 exp
[numops
++].X_add_number
= cmp_hack
- 1;
491 while (*p
== ' ' || *p
== '\t' || *p
== ',')
493 if (*p
==0 || *p
=='\n' || *p
=='\r')
499 exp
[numops
].X_op
= O_absent
;
503 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
509 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
513 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
522 /* just skip the trailing paren */
527 input_line_pointer
= p
;
529 /* check to see if it might be a register name */
530 if (!register_name (&exp
[numops
]))
532 /* parse as an expression */
533 expression (&exp
[numops
]);
536 if (exp
[numops
].X_op
== O_illegal
)
537 as_bad (_("illegal operand"));
538 else if (exp
[numops
].X_op
== O_absent
)
539 as_bad (_("missing operand"));
542 p
= input_line_pointer
;
546 case -1: /* postdecrement mode */
547 exp
[numops
].X_op
= O_absent
;
548 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
550 case 1: /* postincrement mode */
551 exp
[numops
].X_op
= O_absent
;
552 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
558 exp
[numops
].X_op
= 0;
562 /* build_insn generates the instruction. It does everything */
563 /* but write the FM bits. */
566 build_insn (opcode
, opers
)
567 struct d30v_insn
*opcode
;
570 int i
, length
, bits
, shift
, flags
;
571 unsigned int number
, id
=0;
573 struct d30v_opcode
*op
= opcode
->op
;
574 struct d30v_format
*form
= opcode
->form
;
576 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
578 for (i
=0; form
->operands
[i
]; i
++)
580 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
582 /* must be a register or number */
583 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
584 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
587 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
588 if (flags
& OPERAND_SHIFT
)
591 length
= d30v_operand_table
[form
->operands
[i
]].length
;
592 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
593 if (opers
[i
].X_op
!= O_symbol
)
594 number
= opers
[i
].X_add_number
;
597 if (flags
& OPERAND_REG
)
599 /* check for mvfsys or mvtsys control registers */
600 if (flags
& OPERAND_CONTROL
&& (number
& 0x7f) > MAX_CONTROL_REG
)
603 id
= (number
& 0x7f) - MAX_CONTROL_REG
;
606 else if (number
& OPERAND_FLAG
)
608 id
= 3; /* number is a flag register */
612 else if (flags
& OPERAND_SPECIAL
)
617 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
619 /* now create a fixup */
621 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
622 as_fatal (_("too many fixups"));
624 fixups
->fix
[fixups
->fc
].reloc
=
625 get_reloc ((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
626 fixups
->fix
[fixups
->fc
].size
= 4;
627 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
628 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
629 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D30V_9_PCREL
)
630 fixups
->fix
[fixups
->fc
].pcrel
= RELOC_PCREL
;
632 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
636 /* truncate to the proper number of bits */
637 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
638 as_bad (_("operand out of range: %d"),number
);
640 number
&= 0x7FFFFFFF >> (31 - bits
);
641 if (flags
& OPERAND_SHIFT
)
645 /* it's a LONG instruction */
646 insn
|= (number
>> 26); /* top 6 bits */
647 insn
<<= 32; /* shift the first word over */
648 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
649 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
652 insn
|= number
<< shift
;
658 /* write out a long form instruction */
660 write_long (opcode
, insn
, fx
)
661 struct d30v_insn
*opcode
;
666 char *f
= frag_more (8);
669 d30v_number_to_chars (f
, insn
, 8);
671 for (i
=0; i
< fx
->fc
; i
++)
673 if (fx
->fix
[i
].reloc
)
675 where
= f
- frag_now
->fr_literal
;
676 fix_new_exp (frag_now
,
688 /* Write out a short form instruction by itself. */
690 write_1_short (opcode
, insn
, fx
, use_sequential
)
691 struct d30v_insn
*opcode
;
696 char *f
= frag_more (8);
699 if (warn_nops
== NOP_ALL
)
700 as_warn (_("%s NOP inserted"), use_sequential
?
701 _("sequential") : _("parallel"));
703 /* The other container needs to be NOP. */
706 /* Use a sequential NOP rather than a parallel one,
707 as the current instruction is a FLAG_MUL32 type one
708 and the next instruction is a load. */
710 /* According to 4.3.1: for FM=01, sub-instructions performed
711 only by IU cannot be encoded in L-container. */
713 if (opcode
->op
->unit
== IU
)
714 insn
|= FM10
| NOP_LEFT
; /* right then left */
716 insn
= FM01
| (insn
<< 32) | NOP_RIGHT
; /* left then right */
720 /* According to 4.3.1: for FM=00, sub-instructions performed
721 only by IU cannot be encoded in L-container. */
723 if (opcode
->op
->unit
== IU
)
724 insn
|= FM00
| NOP_LEFT
; /* right container */
726 insn
= FM00
| (insn
<< 32) | NOP_RIGHT
; /* left container */
729 d30v_number_to_chars (f
, insn
, 8);
731 for (i
=0; i
< fx
->fc
; i
++)
733 if (fx
->fix
[i
].reloc
)
735 where
= f
- frag_now
->fr_literal
;
736 fix_new_exp (frag_now
,
747 /* Write out a short form instruction if possible; */
748 /* return number of instructions not written out. */
750 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
751 struct d30v_insn
*opcode1
, *opcode2
;
752 long long insn1
, insn2
;
753 exec_type_enum exec_type
;
756 long long insn
= NOP2
;
760 if (exec_type
== EXEC_SEQ
761 && (opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
))
762 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0)
763 && ((opcode1
->ecc
== ECC_AL
) || ! Optimizing
))
765 /* Unconditional, non-delayed branches kill instructions in
766 the right bin. Conditional branches don't always but if
767 we are not optimizing, then we have been asked to produce
768 an error about such constructs. For the purposes of this
769 test, subroutine calls are considered to be branches. */
770 write_1_short (opcode1
, insn1
, fx
->next
, false);
774 /* Note: we do not have to worry about subroutine calls occuring
775 in the right hand container. The return address is always
776 aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
780 case EXEC_UNKNOWN
: /* Order not specified. */
782 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
)
783 && ! ( (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
784 || opcode1
->op
->unit
== MU
)
786 ( opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
787 || opcode2
->op
->unit
== MU
)))
790 exec_type
= EXEC_PARALLEL
;
792 if (opcode1
->op
->unit
== IU
793 || opcode2
->op
->unit
== MU
794 || opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
795 insn
= FM00
| (insn2
<< 32) | insn1
;
798 insn
= FM00
| (insn1
<< 32) | insn2
;
802 else if (opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)
803 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0)
804 && ((opcode1
->ecc
== ECC_AL
) || ! Optimizing
))
806 /* We must emit (non-delayed) branch type instructions
807 on their own with nothing in the right container. */
808 write_1_short (opcode1
, insn1
, fx
->next
, false);
811 else if (opcode1
->op
->unit
== IU
812 || (opcode1
->op
->unit
== EITHER
813 && opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
))
815 /* reverse sequential */
816 insn
= FM10
| (insn2
<< 32) | insn1
;
817 exec_type
= EXEC_REVSEQ
;
822 insn
= FM01
| (insn1
<< 32) | insn2
;
824 exec_type
= EXEC_SEQ
;
828 case EXEC_PARALLEL
: /* parallel */
829 flag_explicitly_parallel
= flag_xp_state
;
830 if (! parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
831 as_fatal (_("Instructions may not be executed in parallel"));
832 else if (opcode1
->op
->unit
== IU
)
834 if (opcode2
->op
->unit
== IU
)
835 as_fatal (_("Two IU instructions may not be executed in parallel"));
836 as_warn (_("Swapping instruction order"));
837 insn
= FM00
| (insn2
<< 32) | insn1
;
839 else if (opcode2
->op
->unit
== MU
)
841 if (opcode1
->op
->unit
== MU
)
842 as_fatal (_("Two MU instructions may not be executed in parallel"));
843 else if (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
)
844 as_warn (_("Executing %s in IU may not work"), opcode1
->op
->name
);
845 as_warn (_("Swapping instruction order"));
846 insn
= FM00
| (insn2
<< 32) | insn1
;
850 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
851 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
853 insn
= FM00
| (insn1
<< 32) | insn2
;
856 flag_explicitly_parallel
= 0;
859 case EXEC_SEQ
: /* sequential */
860 if (opcode1
->op
->unit
== IU
)
861 as_fatal (_("IU instruction may not be in the left container"));
862 if (prev_left_kills_right_p
)
863 as_warn (_("special left instruction `%s' kills instruction "
864 "`%s' in right container"),
865 opcode1
->op
->name
, opcode2
->op
->name
);
866 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
867 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
868 insn
= FM01
| (insn1
<< 32) | insn2
;
872 case EXEC_REVSEQ
: /* reverse sequential */
873 if (opcode2
->op
->unit
== MU
)
874 as_fatal (_("MU instruction may not be in the right container"));
875 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
876 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
877 insn
= FM10
| (insn1
<< 32) | insn2
;
882 as_fatal (_("unknown execution type passed to write_2_short()"));
885 /* printf ("writing out %llx\n",insn); */
887 d30v_number_to_chars (f
, insn
, 8);
889 /* If the previous instruction was a 32-bit multiply but it is put into a
890 parallel container, mark the current instruction as being a 32-bit
892 if (prev_mul32_p
&& exec_type
== EXEC_PARALLEL
)
897 for (i
=0; i
< fx
->fc
; i
++)
899 if (fx
->fix
[i
].reloc
)
901 where
= (f
- frag_now
->fr_literal
) + 4*j
;
903 fix_new_exp (frag_now
,
920 /* Check 2 instructions and determine if they can be safely */
921 /* executed in parallel. Returns 1 if they can be. */
923 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
924 struct d30v_insn
*op1
, *op2
;
925 unsigned long insn1
, insn2
;
926 exec_type_enum exec_type
;
928 int i
, j
, shift
, regno
, bits
, ecc
;
929 unsigned long flags
, mask
, flags_set1
, flags_set2
, flags_used1
, flags_used2
;
930 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3], flag_reg
[2];
931 struct d30v_format
*f
;
932 struct d30v_opcode
*op
;
934 /* section 4.3: both instructions must not be IU or MU only */
935 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
936 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
939 /* first instruction must not be a jump to safely optimize, unless this
940 is an explicit parallel operation. */
941 if (exec_type
!= EXEC_PARALLEL
942 && (op1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)))
945 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
946 then it is safe to allow the two to be done as parallel ops, since only
947 one will ever be executed at a time. */
948 if ((op1
->ecc
== ECC_TX
&& op2
->ecc
== ECC_FX
)
949 || (op1
->ecc
== ECC_FX
&& op2
->ecc
== ECC_TX
)
950 || (op1
->ecc
== ECC_XT
&& op2
->ecc
== ECC_XF
)
951 || (op1
->ecc
== ECC_XF
&& op2
->ecc
== ECC_XT
))
956 [2] a0, a1, flag registers */
958 for (j
= 0; j
< 2; j
++)
975 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
976 mod_reg
[j
][2] = (op
->flags_set
& FLAG_ALL
);
977 used_reg
[j
][0] = used_reg
[j
][1] = 0;
978 used_reg
[j
][2] = (op
->flags_used
& FLAG_ALL
);
980 /* BSR/JSR always sets R62 */
981 if (op
->flags_used
& FLAG_JSR
)
982 mod_reg
[j
][1] = (1L << (62-32));
984 /* conditional execution affects the flags_used */
989 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_0
;
994 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_1
;
999 used_reg
[j
][2] |= flag_reg
[j
] = (FLAG_0
| FLAG_1
);
1003 for (i
= 0; f
->operands
[i
]; i
++)
1005 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
1006 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
1007 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
1011 mask
= 0x7FFFFFFF >> (31 - bits
);
1013 if ((flags
& OPERAND_PLUS
) || (flags
& OPERAND_MINUS
))
1015 /* this is a post-increment or post-decrement */
1016 /* the previous register needs to be marked as modified */
1018 shift
= 12 - d30v_operand_table
[f
->operands
[i
-1]].position
;
1019 regno
= (ins
>> shift
) & 0x3f;
1021 mod_reg
[j
][1] |= 1L << (regno
- 32);
1023 mod_reg
[j
][0] |= 1L << regno
;
1025 else if (flags
& OPERAND_REG
)
1027 regno
= (ins
>> shift
) & mask
;
1028 /* the memory write functions don't have a destination register */
1029 if ((flags
& OPERAND_DEST
) && !(op
->flags_set
& FLAG_MEM
))
1031 /* MODIFIED registers and flags */
1032 if (flags
& OPERAND_ACC
)
1035 mod_reg
[j
][2] |= FLAG_A0
;
1036 else if (regno
== 1)
1037 mod_reg
[j
][2] |= FLAG_A1
;
1041 else if (flags
& OPERAND_FLAG
)
1042 mod_reg
[j
][2] |= 1L << regno
;
1043 else if (!(flags
& OPERAND_CONTROL
))
1047 /* need to check if there are two destination */
1048 /* registers, for example ld2w */
1049 if (flags
& OPERAND_2REG
)
1054 for (r
= regno
; r
<= regno
+ z
; r
++)
1057 mod_reg
[j
][1] |= 1L << (r
- 32);
1059 mod_reg
[j
][0] |= 1L << r
;
1065 /* USED, but not modified registers and flags */
1066 if (flags
& OPERAND_ACC
)
1069 used_reg
[j
][2] |= FLAG_A0
;
1070 else if (regno
== 1)
1071 used_reg
[j
][2] |= FLAG_A1
;
1075 else if (flags
& OPERAND_FLAG
)
1076 used_reg
[j
][2] |= 1L << regno
;
1077 else if (!(flags
& OPERAND_CONTROL
))
1081 /* need to check if there are two source */
1082 /* registers, for example st2w */
1083 if (flags
& OPERAND_2REG
)
1088 for (r
= regno
; r
<= regno
+ z
; r
++)
1091 used_reg
[j
][1] |= 1L << (r
- 32);
1093 used_reg
[j
][0] |= 1L << r
;
1101 flags_set1
= op1
->op
->flags_set
;
1102 flags_set2
= op2
->op
->flags_set
;
1103 flags_used1
= op1
->op
->flags_used
;
1104 flags_used2
= op2
->op
->flags_used
;
1106 /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */
1107 if (((flags_set1
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1108 && (flags_used2
& FLAG_ADDSUBppp
) != 0)
1109 || ((flags_set2
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1110 && (flags_used1
& FLAG_ADDSUBppp
) != 0))
1113 /* Load instruction combined with half-word multiply is illegal. */
1114 if (((flags_used1
& FLAG_MEM
) != 0 && (flags_used2
& FLAG_MUL16
))
1115 || ((flags_used2
& FLAG_MEM
) != 0 && (flags_used1
& FLAG_MUL16
)))
1118 /* Specifically allow add || add by removing carry, overflow bits dependency.
1119 This is safe, even if an addc follows since the IU takes the argument in
1120 the right container, and it writes its results last.
1121 However, don't paralellize add followed by addc or sub followed by
1124 if (mod_reg
[0][2] == FLAG_CVVA
&& mod_reg
[1][2] == FLAG_CVVA
1125 && (used_reg
[0][2] & ~flag_reg
[0]) == 0
1126 && (used_reg
[1][2] & ~flag_reg
[1]) == 0
1127 && op1
->op
->unit
== EITHER
&& op2
->op
->unit
== EITHER
)
1129 mod_reg
[0][2] = mod_reg
[1][2] = 0;
1132 for (j
= 0; j
< 3; j
++)
1134 /* If the second instruction depends on the first, we obviously
1135 cannot parallelize. Note, the mod flag implies use, so
1136 check that as well. */
1137 /* If flag_explicitly_parallel is set, then the case of the
1138 second instruction using a register the first instruction
1139 modifies is assumed to be okay; we trust the human. We
1140 don't trust the human if both instructions modify the same
1141 register but we do trust the human if they modify the same
1143 if (flag_explicitly_parallel
)
1145 if ((j
< 2) && (mod_reg
[0][j
] & mod_reg
[1][j
]) != 0)
1149 if ((mod_reg
[0][j
] & (mod_reg
[1][j
] | used_reg
[1][j
])) != 0)
1157 /* This is the main entry point for the machine-dependent assembler. str points to a
1158 machine-dependent instruction. This function is supposed to emit the frags/bytes
1159 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
1160 and leaves the difficult stuff to do_assemble(). */
1162 static long long prev_insn
= -1;
1163 static struct d30v_insn prev_opcode
;
1164 static subsegT prev_subseg
;
1165 static segT prev_seg
= 0;
1171 struct d30v_insn opcode
;
1173 exec_type_enum extype
= EXEC_UNKNOWN
; /* execution type; parallel, etc */
1174 static exec_type_enum etype
= EXEC_UNKNOWN
; /* saved extype. used for multiline instructions */
1177 if ((prev_insn
!= -1) && prev_seg
1178 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1179 d30v_cleanup (false);
1181 if (d30v_current_align
< 3)
1182 d30v_align (3, NULL
, d30v_last_label
);
1183 else if (d30v_current_align
> 3)
1184 d30v_current_align
= 3;
1185 d30v_last_label
= NULL
;
1187 flag_explicitly_parallel
= 0;
1189 if (etype
== EXEC_UNKNOWN
)
1191 /* look for the special multiple instruction separators */
1192 str2
= strstr (str
, "||");
1195 extype
= EXEC_PARALLEL
;
1200 str2
= strstr (str
, "->");
1205 str2
= strstr (str
, "<-");
1207 extype
= EXEC_REVSEQ
;
1210 /* str2 points to the separator, if one */
1215 /* if two instructions are present and we already have one saved
1216 then first write it out */
1217 d30v_cleanup (false);
1219 /* Assemble first instruction and save it. */
1220 prev_insn
= do_assemble (str
, &prev_opcode
, 1, 0);
1221 if (prev_insn
== -1)
1222 as_fatal (_("Cannot assemble instruction"));
1223 if (prev_opcode
.form
->form
>= LONG
)
1224 as_fatal (_("First opcode is long. Unable to mix instructions as specified."));
1225 fixups
= fixups
->next
;
1228 prev_subseg
= now_subseg
;
1232 insn
= do_assemble (str
, &opcode
,
1233 (extype
!= EXEC_UNKNOWN
|| etype
!= EXEC_UNKNOWN
),
1234 extype
== EXEC_PARALLEL
);
1237 if (extype
!= EXEC_UNKNOWN
)
1242 as_fatal (_("Cannot assemble instruction"));
1245 if (etype
!= EXEC_UNKNOWN
)
1248 etype
= EXEC_UNKNOWN
;
1251 /* Word multiply instructions must not be followed by either a load or a
1252 16-bit multiply instruction in the next cycle. */
1253 if ( (extype
!= EXEC_REVSEQ
)
1255 && (opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1257 /* However, load and multiply should able to be combined in a parallel
1258 operation, so check for that first. */
1260 && (opcode
.op
->flags_used
& FLAG_MEM
)
1261 && opcode
.form
->form
< LONG
1262 && (extype
== EXEC_PARALLEL
|| (Optimizing
&& extype
== EXEC_UNKNOWN
))
1263 && parallel_ok (&prev_opcode
, (long)prev_insn
,
1264 &opcode
, (long)insn
, extype
)
1265 && write_2_short (&prev_opcode
, (long)prev_insn
,
1266 &opcode
, (long)insn
, extype
, fixups
) == 0)
1268 /* no instructions saved */
1274 /* Can't parallelize, flush previous instruction and emit a word of NOPS,
1275 unless the previous instruction is a NOP, in which case just flush it,
1276 as this will generate a word of NOPs for us. */
1278 if (prev_insn
!= -1 && (strcmp (prev_opcode
.op
->name
, "nop") == 0))
1279 d30v_cleanup (false);
1284 if (prev_insn
!= -1)
1285 d30v_cleanup (true);
1289 d30v_number_to_chars (f
, NOP2
, 8);
1291 if (warn_nops
== NOP_ALL
|| warn_nops
== NOP_MULTIPLY
)
1293 if (opcode
.op
->flags_used
& FLAG_MEM
)
1294 as_warn (_("word of NOPs added between word multiply and load"));
1296 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1301 extype
= EXEC_UNKNOWN
;
1304 else if ( (extype
== EXEC_REVSEQ
)
1306 && (prev_opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1308 /* Can't parallelize, flush current instruction and add a sequential NOP. */
1309 write_1_short (& opcode
, (long) insn
, fixups
->next
->next
, true);
1311 /* Make the previous instruction the current one. */
1312 extype
= EXEC_UNKNOWN
;
1315 now_subseg
= prev_subseg
;
1317 cur_mul32_p
= prev_mul32_p
;
1319 memcpy (&opcode
, &prev_opcode
, sizeof (prev_opcode
));
1322 /* If this is a long instruction, write it and any previous short instruction. */
1323 if (opcode
.form
->form
>= LONG
)
1325 if (extype
!= EXEC_UNKNOWN
)
1326 as_fatal (_("Instruction uses long version, so it cannot be mixed as specified"));
1327 d30v_cleanup (false);
1328 write_long (& opcode
, insn
, fixups
);
1331 else if ((prev_insn
!= -1) &&
1333 (& prev_opcode
, (long) prev_insn
, & opcode
, (long) insn
, extype
, fixups
) == 0))
1335 /* No instructions saved. */
1340 if (extype
!= EXEC_UNKNOWN
)
1341 as_fatal (_("Unable to mix instructions as specified"));
1343 /* Save off last instruction so it may be packed on next pass. */
1344 memcpy (&prev_opcode
, &opcode
, sizeof (prev_opcode
));
1347 prev_subseg
= now_subseg
;
1348 fixups
= fixups
->next
;
1349 prev_mul32_p
= cur_mul32_p
;
1354 /* do_assemble assembles a single instruction and returns an opcode */
1355 /* it returns -1 (an invalid opcode) on error */
1358 do_assemble (str
, opcode
, shortp
, is_parallel
)
1360 struct d30v_insn
*opcode
;
1364 unsigned char *op_start
, *save
;
1365 unsigned char *op_end
;
1367 int cmp_hack
, nlen
= 0, fsize
= (shortp
? FORCE_SHORT
: 0);
1368 expressionS myops
[6];
1371 /* Drop leading whitespace */
1375 /* find the opcode end */
1376 for (op_start
= op_end
= (unsigned char *) (str
);
1380 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1383 name
[nlen
] = tolower (op_start
[nlen
]);
1392 /* if there is an execution condition code, handle it */
1396 while ( (i
< ECC_MAX
) && strncasecmp (d30v_ecc_names
[i
], op_end
+ 1, 2))
1402 strncpy (tmp
, op_end
+ 1, 2);
1404 as_fatal (_("unknown condition code: %s"),tmp
);
1407 /* printf("condition code=%d\n",i); */
1412 opcode
->ecc
= ECC_AL
;
1415 /* CMP and CMPU change their name based on condition codes */
1416 if (!strncmp (name
, "cmp", 3))
1419 char **str
= (char **)d30v_cc_names
;
1425 for (i
=1; *str
&& strncmp (*str
, & name
[p
], 2); i
++, str
++)
1428 /* cmpu only supports some condition codes */
1434 as_fatal (_("cmpu doesn't support condition code %s"),&name
[p
]);
1441 as_fatal (_("unknown condition code: %s"),&name
[p
]);
1450 /* printf("cmp_hack=%d\n",cmp_hack); */
1452 /* need to look for .s or .l */
1453 if (name
[nlen
-2] == '.')
1455 switch (name
[nlen
-1])
1458 fsize
= FORCE_SHORT
;
1467 /* find the first opcode with the proper name */
1468 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1469 if (opcode
->op
== NULL
)
1470 as_fatal (_("unknown opcode: %s"),name
);
1472 save
= input_line_pointer
;
1473 input_line_pointer
= op_end
;
1474 while (!(opcode
->form
= find_format (opcode
->op
, myops
, fsize
, cmp_hack
)))
1477 if (strcmp (opcode
->op
->name
, name
))
1478 as_fatal (_("operands for opcode `%s' do not match any valid format"), name
);
1480 input_line_pointer
= save
;
1482 insn
= build_insn (opcode
, myops
);
1484 /* Propigate multiply status */
1487 if (is_parallel
&& prev_mul32_p
)
1491 prev_mul32_p
= cur_mul32_p
;
1492 cur_mul32_p
= (opcode
->op
->flags_used
& FLAG_MUL32
) != 0;
1496 /* Propagate left_kills_right status */
1499 prev_left_kills_right_p
= cur_left_kills_right_p
;
1501 if (opcode
->op
->flags_set
& FLAG_LKR
)
1503 cur_left_kills_right_p
= 1;
1505 if (strcmp (opcode
->op
->name
, "mvtsys") == 0)
1507 /* Left kills right for only mvtsys only for PSW/PSWH/PSWL/flags target. */
1508 if ((myops
[0].X_op
== O_register
) &&
1509 ((myops
[0].X_add_number
== OPERAND_CONTROL
) || /* psw */
1510 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+2) || /* pswh */
1511 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+1) || /* pswl */
1512 (myops
[0].X_add_number
== OPERAND_FLAG
+0) || /* f0 */
1513 (myops
[0].X_add_number
== OPERAND_FLAG
+1) || /* f1 */
1514 (myops
[0].X_add_number
== OPERAND_FLAG
+2) || /* f2 */
1515 (myops
[0].X_add_number
== OPERAND_FLAG
+3) || /* f3 */
1516 (myops
[0].X_add_number
== OPERAND_FLAG
+4) || /* f4 */
1517 (myops
[0].X_add_number
== OPERAND_FLAG
+5) || /* f5 */
1518 (myops
[0].X_add_number
== OPERAND_FLAG
+6) || /* f6 */
1519 (myops
[0].X_add_number
== OPERAND_FLAG
+7))) /* f7 */
1521 cur_left_kills_right_p
= 1;
1525 /* Other mvtsys target registers don't kill right instruction. */
1526 cur_left_kills_right_p
= 0;
1531 cur_left_kills_right_p
= 0;
1539 /* find_format() gets a pointer to an entry in the format table.
1540 It must look at all formats for an opcode and use the operands
1541 to choose the correct one. Returns NULL on error. */
1543 static struct d30v_format
*
1544 find_format (opcode
, myops
, fsize
, cmp_hack
)
1545 struct d30v_opcode
*opcode
;
1546 expressionS myops
[];
1550 int numops
, match
, index
, i
=0, j
, k
;
1551 struct d30v_format
*fm
;
1553 /* Get all the operands and save them as expressions. */
1554 numops
= get_operands (myops
, cmp_hack
);
1556 while ((index
= opcode
->format
[i
++]) != 0)
1558 if (fsize
== FORCE_SHORT
&& index
>= LONG
)
1561 if (fsize
== FORCE_LONG
&& index
< LONG
)
1564 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1566 while (fm
->form
== index
)
1569 /* Now check the operands for compatibility. */
1570 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1572 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1573 int bits
= d30v_operand_table
[fm
->operands
[j
]].bits
;
1574 int X_op
= myops
[j
].X_op
;
1575 int num
= myops
[j
].X_add_number
;
1577 if (flags
& OPERAND_SPECIAL
)
1579 else if (X_op
== O_illegal
)
1581 else if (flags
& OPERAND_REG
)
1583 if (X_op
!= O_register
1584 || ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
))
1585 || (!(flags
& OPERAND_ACC
) && (num
& OPERAND_ACC
))
1586 || ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
))
1587 || (!(flags
& OPERAND_FLAG
) && (num
& OPERAND_FLAG
))
1588 || ((flags
& OPERAND_CONTROL
)
1589 && !(num
& (OPERAND_CONTROL
| OPERAND_FLAG
))))
1594 else if (((flags
& OPERAND_MINUS
)
1595 && (X_op
!= O_absent
|| num
!= OPERAND_MINUS
))
1596 || ((flags
& OPERAND_PLUS
)
1597 && (X_op
!= O_absent
|| num
!= OPERAND_PLUS
))
1598 || ((flags
& OPERAND_ATMINUS
)
1599 && (X_op
!= O_absent
|| num
!= OPERAND_ATMINUS
))
1600 || ((flags
& OPERAND_ATPAR
)
1601 && (X_op
!= O_absent
|| num
!= OPERAND_ATPAR
))
1602 || ((flags
& OPERAND_ATSIGN
)
1603 && (X_op
!= O_absent
|| num
!= OPERAND_ATSIGN
)))
1607 else if (flags
& OPERAND_NUM
)
1609 /* A number can be a constant or symbol expression. */
1611 /* If we have found a register name, but that name also
1612 matches a symbol, then re-parse the name as an expression. */
1613 if (X_op
== O_register
1614 && symbol_find ((char *) myops
[j
].X_op_symbol
))
1616 input_line_pointer
= (char *) myops
[j
].X_op_symbol
;
1617 expression (& myops
[j
]);
1620 /* Turn an expression into a symbol for later resolution. */
1621 if (X_op
!= O_absent
&& X_op
!= O_constant
1622 && X_op
!= O_symbol
&& X_op
!= O_register
1625 symbolS
*sym
= make_expr_symbol (&myops
[j
]);
1626 myops
[j
].X_op
= X_op
= O_symbol
;
1627 myops
[j
].X_add_symbol
= sym
;
1628 myops
[j
].X_add_number
= num
= 0;
1631 if (fm
->form
>= LONG
)
1633 /* If we're testing for a LONG format, either fits. */
1634 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1637 else if (fm
->form
< LONG
1638 && ((fsize
== FORCE_SHORT
&& X_op
== O_symbol
)
1639 || (fm
->form
== SHORT_D2
&& j
== 0)))
1641 /* This is the tricky part. Will the constant or symbol
1642 fit into the space in the current format? */
1643 else if (X_op
== O_constant
)
1645 if (check_range (num
, bits
, flags
))
1648 else if (X_op
== O_symbol
1649 && S_IS_DEFINED (myops
[j
].X_add_symbol
)
1650 && S_GET_SEGMENT (myops
[j
].X_add_symbol
) == now_seg
1651 && opcode
->reloc_flag
== RELOC_PCREL
)
1653 /* If the symbol is defined, see if the value will fit
1654 into the form we're considering. */
1658 /* Calculate the current address by running through the
1659 previous frags and adding our current offset. */
1661 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1662 value
+= f
->fr_fix
+ f
->fr_offset
;
1663 value
= (S_GET_VALUE (myops
[j
].X_add_symbol
) - value
1664 - (obstack_next_free (&frchain_now
->frch_obstack
)
1665 - frag_now
->fr_literal
));
1666 if (check_range (value
, bits
, flags
))
1673 /* printf("through the loop: match=%d\n",match); */
1674 /* We're only done if the operands matched so far AND there
1675 are no more to check. */
1676 if (match
&& myops
[j
].X_op
== 0)
1678 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1680 /* printf("trying another format: i=%d\n",i); */
1685 /* if while processing a fixup, a reloc really needs to be created */
1686 /* then it is done here */
1689 tc_gen_reloc (seg
, fixp
)
1694 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1695 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1696 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1697 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1698 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1700 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1701 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1704 reloc
->addend
= fixp
->fx_addnumber
;
1709 md_estimate_size_before_relax (fragp
, seg
)
1718 md_pcrel_from_section (fixp
, sec
)
1722 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1723 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1725 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1729 md_apply_fix3 (fixp
, valuep
, seg
)
1735 unsigned long insn
, insn2
;
1738 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1743 else if (fixp
->fx_pcrel
)
1747 value
= fixp
->fx_offset
;
1749 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1751 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1752 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1755 /* We don't actually support subtracting a symbol. */
1756 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1757 _("expression too complex"));
1762 /* Fetch the instruction, insert the fully resolved operand
1763 value, and stuff the instruction back again. */
1764 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1765 insn
= bfd_getb32 ((unsigned char *) where
);
1767 switch (fixp
->fx_r_type
)
1769 case BFD_RELOC_8
: /* Caused by a bad .byte directive. */
1772 case BFD_RELOC_16
: /* Caused by a bad .short directive. */
1775 case BFD_RELOC_64
: /* Caused by a bad .quad directive. */
1779 size
= (fixp
->fx_r_type
== BFD_RELOC_8
) ? _("byte")
1780 : (fixp
->fx_r_type
== BFD_RELOC_16
) ? _("short")
1783 if (fixp
->fx_addsy
== NULL
)
1784 as_bad (_("line %d: unable to place address into a %s"),
1785 fixp
->fx_line
, size
);
1787 as_bad (_("line %d: unable to place address of symbol '%s' into a %s"),
1789 S_GET_NAME (fixp
->fx_addsy
),
1794 case BFD_RELOC_D30V_6
:
1795 check_size (value
, 6, fixp
->fx_file
, fixp
->fx_line
);
1796 insn
|= value
& 0x3F;
1797 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1800 case BFD_RELOC_D30V_9_PCREL
:
1801 if (fixp
->fx_where
& 0x7)
1806 fixp
->fx_r_type
= BFD_RELOC_D30V_9_PCREL_R
;
1808 check_size (value
, 9, fixp
->fx_file
, fixp
->fx_line
);
1809 insn
|= ((value
>> 3) & 0x3F) << 12;
1810 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1813 case BFD_RELOC_D30V_15
:
1814 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1815 insn
|= (value
>> 3) & 0xFFF;
1816 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1819 case BFD_RELOC_D30V_15_PCREL
:
1820 if (fixp
->fx_where
& 0x7)
1825 fixp
->fx_r_type
= BFD_RELOC_D30V_15_PCREL_R
;
1827 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1828 insn
|= (value
>> 3) & 0xFFF;
1829 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1832 case BFD_RELOC_D30V_21
:
1833 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1834 insn
|= (value
>> 3) & 0x3FFFF;
1835 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1838 case BFD_RELOC_D30V_21_PCREL
:
1839 if (fixp
->fx_where
& 0x7)
1844 fixp
->fx_r_type
= BFD_RELOC_D30V_21_PCREL_R
;
1846 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1847 insn
|= (value
>> 3) & 0x3FFFF;
1848 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1851 case BFD_RELOC_D30V_32
:
1852 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1853 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1854 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1855 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1856 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1857 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1860 case BFD_RELOC_D30V_32_PCREL
:
1861 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1862 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1863 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1864 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1865 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1866 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1870 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1874 as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp
->fx_line
,fixp
->fx_r_type
);
1880 /* d30v_cleanup() is called after the assembler has finished parsing the input
1881 file or after a label is defined. Because the D30V assembler sometimes saves short
1882 instructions to see if it can package them with the next instruction, there may
1883 be a short instruction that still needs written. */
1885 d30v_cleanup (use_sequential
)
1891 if (prev_insn
!= -1)
1894 subseg
= now_subseg
;
1895 subseg_set (prev_seg
, prev_subseg
);
1896 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
, use_sequential
);
1897 subseg_set (seg
, subseg
);
1900 prev_mul32_p
= false;
1906 d30v_number_to_chars (buf
, value
, n
)
1907 char *buf
; /* Return 'nbytes' of chars here. */
1908 long long value
; /* The value of the bits. */
1909 int n
; /* Number of bytes in the output. */
1913 buf
[n
] = value
& 0xff;
1919 /* This function is called at the start of every line. */
1920 /* it checks to see if the first character is a '.' */
1921 /* which indicates the start of a pseudo-op. If it is, */
1922 /* then write out any unwritten instructions */
1927 char *c
= input_line_pointer
;
1929 while (isspace (*c
))
1933 d30v_cleanup (false);
1937 check_size (value
, bits
, file
, line
)
1950 max
= (1 << (bits
- 1)) - 1;
1953 as_bad_where (file
, line
, _("value too large to fit in %d bits"), bits
);
1958 /* d30v_frob_label() is called when after a label is recognized. */
1961 d30v_frob_label (lab
)
1964 /* Emit any pending instructions. */
1965 d30v_cleanup (false);
1967 /* Update the label's address with the current output pointer. */
1968 lab
->sy_frag
= frag_now
;
1969 S_SET_VALUE (lab
, (valueT
) frag_now_fix ());
1971 /* Record this label for future adjustment after we find out what
1972 kind of data it references, and the required alignment therewith. */
1973 d30v_last_label
= lab
;
1976 /* Hook into cons for capturing alignment changes. */
1979 d30v_cons_align (size
)
1985 while ((size
>>= 1) != 0)
1988 if (d30v_current_align
< log_size
)
1989 d30v_align (log_size
, (char *) NULL
, NULL
);
1990 else if (d30v_current_align
> log_size
)
1991 d30v_current_align
= log_size
;
1992 d30v_last_label
= NULL
;
1995 /* Called internally to handle all alignment needs. This takes care
1996 of eliding calls to frag_align if'n the cached current alignment
1997 says we've already got it, as well as taking care of the auto-aligning
2001 d30v_align (n
, pfill
, label
)
2006 /* The front end is prone to changing segments out from under us
2007 temporarily when -g is in effect. */
2008 int switched_seg_p
= (d30v_current_align_seg
!= now_seg
);
2010 /* Do not assume that if 'd30v_current_align >= n' and
2011 '! switched_seg_p' that it is safe to avoid performing
2012 this alignement request. The alignment of the current frag
2013 can be changed under our feet, for example by a .ascii
2014 directive in the source code. cf testsuite/gas/d30v/reloc.s */
2016 d30v_cleanup (false);
2021 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
2023 static char const nop
[4] = { 0x00, 0xf0, 0x00, 0x00 };
2025 /* First, make sure we're on a four-byte boundary, in case
2026 someone has been putting .byte values the text section. */
2027 if (d30v_current_align
< 2 || switched_seg_p
)
2028 frag_align (2, 0, 0);
2029 frag_align_pattern (n
, nop
, sizeof nop
, 0);
2032 frag_align (n
, 0, 0);
2035 frag_align (n
, *pfill
, 0);
2037 if (!switched_seg_p
)
2038 d30v_current_align
= n
;
2043 int label_seen
= false;
2044 struct frag
* old_frag
;
2048 assert (S_GET_SEGMENT (label
) == now_seg
);
2050 old_frag
= label
->sy_frag
;
2051 old_value
= S_GET_VALUE (label
);
2052 new_value
= (valueT
) frag_now_fix ();
2054 /* It is possible to have more than one label at a particular
2055 address, especially if debugging is enabled, so we must
2056 take care to adjust all the labels at this address in this
2057 fragment. To save time we search from the end of the symbol
2058 list, backwards, since the symbols we are interested in are
2059 almost certainly the ones that were most recently added.
2060 Also to save time we stop searching once we have seen at least
2061 one matching label, and we encounter a label that is no longer
2062 in the target fragment. Note, this search is guaranteed to
2063 find at least one match when sym == label, so no special case
2064 code is necessary. */
2065 for (sym
= symbol_lastP
; sym
!= NULL
; sym
= sym
->sy_previous
)
2067 if (sym
->sy_frag
== old_frag
&& S_GET_VALUE (sym
) == old_value
)
2070 sym
->sy_frag
= frag_now
;
2071 S_SET_VALUE (sym
, new_value
);
2073 else if (label_seen
&& sym
->sy_frag
!= old_frag
)
2078 record_alignment (now_seg
, n
);
2081 /* Handle the .align pseudo-op. This aligns to a power of two. We
2082 hook here to latch the current alignment. */
2085 s_d30v_align (ignore
)
2089 char fill
, *pfill
= NULL
;
2090 long max_alignment
= 15;
2092 align
= get_absolute_expression ();
2093 if (align
> max_alignment
)
2095 align
= max_alignment
;
2096 as_warn (_("Alignment too large: %d assumed"), align
);
2100 as_warn (_("Alignment negative: 0 assumed"));
2104 if (*input_line_pointer
== ',')
2106 input_line_pointer
++;
2107 fill
= get_absolute_expression ();
2111 d30v_last_label
= NULL
;
2112 d30v_align (align
, pfill
, NULL
);
2114 demand_empty_rest_of_line ();
2117 /* Handle the .text pseudo-op. This is like the usual one, but it
2118 clears the saved last label and resets known alignment. */
2126 d30v_last_label
= NULL
;
2127 d30v_current_align
= 0;
2128 d30v_current_align_seg
= now_seg
;
2131 /* Handle the .data pseudo-op. This is like the usual one, but it
2132 clears the saved last label and resets known alignment. */
2139 d30v_last_label
= NULL
;
2140 d30v_current_align
= 0;
2141 d30v_current_align_seg
= now_seg
;
2144 /* Handle the .section pseudo-op. This is like the usual one, but it
2145 clears the saved last label and resets known alignment. */
2148 s_d30v_section (ignore
)
2151 obj_elf_section (ignore
);
2152 d30v_last_label
= NULL
;
2153 d30v_current_align
= 0;
2154 d30v_current_align_seg
= now_seg
;