1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
2 Copyright 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
23 #include "safe-ctype.h"
25 #include "opcode/d30v.h"
27 const char comment_chars
[] = ";";
28 const char line_comment_chars
[] = "#";
29 const char line_separator_chars
[] = "";
30 const char *md_shortopts
= "OnNcC";
31 const char EXP_CHARS
[] = "eE";
32 const char FLT_CHARS
[] = "dD";
42 #define NOP_MULTIPLY 1
44 static int warn_nops
= 0;
45 static int Optimizing
= 0;
46 static int warn_register_name_conflicts
= 1;
52 typedef enum _exec_type
54 EXEC_UNKNOWN
, /* no order specified */
55 EXEC_PARALLEL
, /* done in parallel (FM=00) */
56 EXEC_SEQ
, /* sequential (FM=01) */
57 EXEC_REVSEQ
/* reverse sequential (FM=10) */
61 #define MAX_INSN_FIXUPS (5)
68 bfd_reloc_code_real_type reloc
;
71 typedef struct _fixups
74 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
78 static Fixups FixUps
[2];
79 static Fixups
*fixups
;
81 /* Whether current and previous instruction are word multiply insns. */
82 static int cur_mul32_p
= 0;
83 static int prev_mul32_p
= 0;
85 /* The flag_explicitly_parallel is true iff the instruction being assembled
86 has been explicitly written as a parallel short-instruction pair by the
87 human programmer. It is used in parallel_ok () to distinguish between
88 those dangerous parallelizations attempted by the human, which are to be
89 allowed, and those attempted by the assembler, which are not. It is set
90 from md_assemble (). */
91 static int flag_explicitly_parallel
= 0;
92 static int flag_xp_state
= 0;
94 /* Whether current and previous left sub-instruction disables
95 execution of right sub-instruction. */
96 static int cur_left_kills_right_p
= 0;
97 static int prev_left_kills_right_p
= 0;
99 /* The known current alignment of the current section. */
100 static int d30v_current_align
;
101 static segT d30v_current_align_seg
;
103 /* The last seen label in the current section. This is used to auto-align
104 labels preceding instructions. */
105 static symbolS
*d30v_last_label
;
108 #define NOP_LEFT ((long long) NOP << 32)
109 #define NOP_RIGHT ((long long) NOP)
110 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
112 /* Local functions. */
113 static int reg_name_search
PARAMS ((char *name
));
114 static int register_name
PARAMS ((expressionS
*expressionP
));
115 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
116 static int postfix
PARAMS ((char *p
));
117 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
118 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
119 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
,
120 expressionS ops
[],int fsize
, int cmp_hack
));
121 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
122 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
123 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
,
124 Fixups
*fx
, int use_sequential
));
125 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
126 struct d30v_insn
*opcode2
, long long insn2
, exec_type_enum exec_type
, Fixups
*fx
));
127 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
,
128 int shortp
, int is_parallel
));
129 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
130 struct d30v_insn
*opcode2
, unsigned long insn2
,
131 exec_type_enum exec_type
));
132 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
133 static void check_size
PARAMS ((long value
, int bits
, char *file
, int line
));
134 static void d30v_align
PARAMS ((int, char *, symbolS
*));
135 static void s_d30v_align
PARAMS ((int));
136 static void s_d30v_text
PARAMS ((int));
137 static void s_d30v_data
PARAMS ((int));
138 static void s_d30v_section
PARAMS ((int));
140 struct option md_longopts
[] =
142 {NULL
, no_argument
, NULL
, 0}
145 size_t md_longopts_size
= sizeof (md_longopts
);
147 /* The target specific pseudo-ops which we support. */
148 const pseudo_typeS md_pseudo_table
[] =
151 { "hword", cons
, 2 },
152 { "align", s_d30v_align
, 0 },
153 { "text", s_d30v_text
, 0 },
154 { "data", s_d30v_data
, 0 },
155 { "section", s_d30v_section
, 0 },
156 { "section.s", s_d30v_section
, 0 },
157 { "sect", s_d30v_section
, 0 },
158 { "sect.s", s_d30v_section
, 0 },
162 /* Opcode hash table. */
163 static struct hash_control
*d30v_hash
;
165 /* Do a binary search of the pre_defined_registers array to see if
166 NAME is a valid regiter name. Return the register number from the
167 array on success, or -1 on failure. */
170 reg_name_search (name
)
173 int middle
, low
, high
;
177 high
= reg_name_cnt () - 1;
181 middle
= (low
+ high
) / 2;
182 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
189 if (symbol_find (name
) != NULL
)
191 if (warn_register_name_conflicts
)
192 as_warn (_("Register name %s conflicts with symbol of the same name"),
196 return pre_defined_registers
[middle
].value
;
204 /* Check the string at input_line_pointer to see if it is a valid
208 register_name (expressionP
)
209 expressionS
*expressionP
;
212 char c
, *p
= input_line_pointer
;
214 while (*p
&& *p
!= '\n' && *p
!= '\r' && *p
!= ',' && *p
!= ' ' && *p
!= ')')
221 /* Look to see if it's in the register table. */
222 reg_number
= reg_name_search (input_line_pointer
);
225 expressionP
->X_op
= O_register
;
226 /* Temporarily store a pointer to the string here. */
227 expressionP
->X_op_symbol
= (symbolS
*) input_line_pointer
;
228 expressionP
->X_add_number
= reg_number
;
229 input_line_pointer
= p
;
238 check_range (num
, bits
, flags
)
245 /* Don't bother checking 32-bit values. */
248 if (sizeof (unsigned long) * CHAR_BIT
== 32)
251 /* We don't record signed or unsigned for 32-bit quantities.
253 min
= -((unsigned long) 1 << (bits
- 1));
254 max
= ((unsigned long) 1 << bits
) - 1;
255 return (long) num
< min
|| (long) num
> max
;
258 if (flags
& OPERAND_SHIFT
)
260 /* We know that all shifts are right by three bits. */
263 if (flags
& OPERAND_SIGNED
)
265 unsigned long sign_bit
= ((unsigned long) -1L >> 4) + 1;
266 num
= (num
^ sign_bit
) - sign_bit
;
270 if (flags
& OPERAND_SIGNED
)
272 max
= ((unsigned long) 1 << (bits
- 1)) - 1;
273 min
= - ((unsigned long) 1 << (bits
- 1));
274 return (long) num
> max
|| (long) num
< min
;
278 max
= ((unsigned long) 1 << bits
) - 1;
279 return num
> (unsigned long) max
;
284 md_show_usage (stream
)
287 fprintf (stream
, _("\nD30V options:\n\
288 -O Make adjacent short instructions parallel if possible.\n\
289 -n Warn about all NOPs inserted by the assembler.\n\
290 -N Warn about NOPs inserted after word multiplies.\n\
291 -c Warn about symbols whoes names match register names.\n\
292 -C Opposite of -C. -c is the default.\n"));
296 md_parse_option (c
, arg
)
298 char *arg ATTRIBUTE_UNUSED
;
302 /* Optimize. Will attempt to parallelize operations. */
307 /* Warn about all NOPS that the assembler inserts. */
312 /* Warn about the NOPS that the assembler inserts because of the
315 warn_nops
= NOP_MULTIPLY
;
319 warn_register_name_conflicts
= 1;
323 warn_register_name_conflicts
= 0;
333 md_undefined_symbol (name
)
334 char *name ATTRIBUTE_UNUSED
;
339 /* Turn a string in input_line_pointer into a floating point constant
340 of type TYPE, and store the appropriate bytes in *LITP. The number
341 of LITTLENUMS emitted is stored in *SIZEP. An error message is
342 returned, or NULL on OK. */
345 md_atof (type
, litP
, sizeP
)
351 LITTLENUM_TYPE words
[4];
365 return _("bad call to md_atof");
368 t
= atof_ieee (input_line_pointer
, type
, words
);
370 input_line_pointer
= t
;
374 for (i
= 0; i
< prec
; i
++)
376 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
383 md_convert_frag (abfd
, sec
, fragP
)
384 bfd
*abfd ATTRIBUTE_UNUSED
;
385 asection
*sec ATTRIBUTE_UNUSED
;
386 fragS
*fragP ATTRIBUTE_UNUSED
;
392 md_section_align (seg
, addr
)
396 int align
= bfd_get_section_alignment (stdoutput
, seg
);
397 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
403 struct d30v_opcode
*opcode
;
404 d30v_hash
= hash_new ();
406 /* Insert opcode names into a hash table. */
407 for (opcode
= (struct d30v_opcode
*) d30v_opcode_table
; opcode
->name
; opcode
++)
408 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
411 FixUps
[0].next
= &FixUps
[1];
412 FixUps
[1].next
= &FixUps
[0];
414 d30v_current_align_seg
= now_seg
;
417 /* Remove the postincrement or postdecrement operator ( '+' or '-' )
418 from an expression. */
424 while (*p
!= '-' && *p
!= '+')
426 if (*p
== 0 || *p
== '\n' || *p
== '\r' || *p
== ' ' || *p
== ',')
446 static bfd_reloc_code_real_type
447 get_reloc (op
, rel_flag
)
448 struct d30v_operand
*op
;
454 if (op
->flags
& OPERAND_SHIFT
)
455 return BFD_RELOC_D30V_9_PCREL
;
457 return BFD_RELOC_D30V_6
;
460 if (!(op
->flags
& OPERAND_SHIFT
))
461 as_warn (_("unexpected 12-bit reloc type"));
462 if (rel_flag
== RELOC_PCREL
)
463 return BFD_RELOC_D30V_15_PCREL
;
465 return BFD_RELOC_D30V_15
;
467 if (!(op
->flags
& OPERAND_SHIFT
))
468 as_warn (_("unexpected 18-bit reloc type"));
469 if (rel_flag
== RELOC_PCREL
)
470 return BFD_RELOC_D30V_21_PCREL
;
472 return BFD_RELOC_D30V_21
;
474 if (rel_flag
== RELOC_PCREL
)
475 return BFD_RELOC_D30V_32_PCREL
;
477 return BFD_RELOC_D30V_32
;
483 /* Parse a string of operands and return an array of expressions. */
486 get_operands (exp
, cmp_hack
)
490 char *p
= input_line_pointer
;
496 exp
[numops
].X_op
= O_absent
;
497 exp
[numops
++].X_add_number
= cmp_hack
- 1;
502 while (*p
== ' ' || *p
== '\t' || *p
== ',')
505 if (*p
== 0 || *p
== '\n' || *p
== '\r')
511 exp
[numops
].X_op
= O_absent
;
515 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
521 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
525 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
534 /* Just skip the trailing paren. */
539 input_line_pointer
= p
;
541 /* Check to see if it might be a register name. */
542 if (!register_name (&exp
[numops
]))
544 /* Parse as an expression. */
545 expression (&exp
[numops
]);
548 if (exp
[numops
].X_op
== O_illegal
)
549 as_bad (_("illegal operand"));
550 else if (exp
[numops
].X_op
== O_absent
)
551 as_bad (_("missing operand"));
554 p
= input_line_pointer
;
559 /* Postdecrement mode. */
560 exp
[numops
].X_op
= O_absent
;
561 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
564 /* Postincrement mode. */
565 exp
[numops
].X_op
= O_absent
;
566 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
572 exp
[numops
].X_op
= 0;
577 /* Generate the instruction.
578 It does everything but write the FM bits. */
581 build_insn (opcode
, opers
)
582 struct d30v_insn
*opcode
;
585 int i
, length
, bits
, shift
, flags
;
586 unsigned long number
, id
= 0;
588 struct d30v_opcode
*op
= opcode
->op
;
589 struct d30v_format
*form
= opcode
->form
;
592 opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
594 for (i
= 0; form
->operands
[i
]; i
++)
596 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
598 /* Must be a register or number. */
599 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
)
600 && !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
603 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
604 if (flags
& OPERAND_SHIFT
)
607 length
= d30v_operand_table
[form
->operands
[i
]].length
;
608 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
609 if (opers
[i
].X_op
!= O_symbol
)
610 number
= opers
[i
].X_add_number
;
613 if (flags
& OPERAND_REG
)
615 /* Check for mvfsys or mvtsys control registers. */
616 if (flags
& OPERAND_CONTROL
&& (number
& 0x7f) > MAX_CONTROL_REG
)
619 id
= (number
& 0x7f) - MAX_CONTROL_REG
;
622 else if (number
& OPERAND_FLAG
)
624 /* NUMBER is a flag register. */
629 else if (flags
& OPERAND_SPECIAL
)
634 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
635 && !(flags
& OPERAND_NAME
))
637 /* Now create a fixup. */
638 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
639 as_fatal (_("too many fixups"));
641 fixups
->fix
[fixups
->fc
].reloc
=
642 get_reloc ((struct d30v_operand
*) &d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
643 fixups
->fix
[fixups
->fc
].size
= 4;
644 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
645 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
646 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D30V_9_PCREL
)
647 fixups
->fix
[fixups
->fc
].pcrel
= RELOC_PCREL
;
649 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
653 /* Truncate to the proper number of bits. */
654 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
655 as_bad (_("operand out of range: %ld"), number
);
657 number
&= 0x7FFFFFFF >> (31 - bits
);
658 if (flags
& OPERAND_SHIFT
)
662 /* It's a LONG instruction. */
663 insn
|= ((number
& 0xffffffff) >> 26); /* top 6 bits */
664 insn
<<= 32; /* shift the first word over */
665 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
666 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
669 insn
|= number
<< shift
;
675 /* Write out a long form instruction. */
678 write_long (opcode
, insn
, fx
)
679 struct d30v_insn
*opcode ATTRIBUTE_UNUSED
;
684 char *f
= frag_more (8);
687 d30v_number_to_chars (f
, insn
, 8);
689 for (i
= 0; i
< fx
->fc
; i
++)
691 if (fx
->fix
[i
].reloc
)
693 where
= f
- frag_now
->fr_literal
;
694 fix_new_exp (frag_now
,
706 /* Write out a short form instruction by itself. */
709 write_1_short (opcode
, insn
, fx
, use_sequential
)
710 struct d30v_insn
*opcode
;
715 char *f
= frag_more (8);
718 if (warn_nops
== NOP_ALL
)
719 as_warn (_("%s NOP inserted"), use_sequential
?
720 _("sequential") : _("parallel"));
722 /* The other container needs to be NOP. */
725 /* Use a sequential NOP rather than a parallel one,
726 as the current instruction is a FLAG_MUL32 type one
727 and the next instruction is a load. */
729 /* According to 4.3.1: for FM=01, sub-instructions performed
730 only by IU cannot be encoded in L-container. */
732 if (opcode
->op
->unit
== IU
)
733 /* Right then left. */
734 insn
|= FM10
| NOP_LEFT
;
736 /* Left then right. */
737 insn
= FM01
| (insn
<< 32) | NOP_RIGHT
;
741 /* According to 4.3.1: for FM=00, sub-instructions performed
742 only by IU cannot be encoded in L-container. */
744 if (opcode
->op
->unit
== IU
)
745 /* Right container. */
746 insn
|= FM00
| NOP_LEFT
;
748 /* Left container. */
749 insn
= FM00
| (insn
<< 32) | NOP_RIGHT
;
752 d30v_number_to_chars (f
, insn
, 8);
754 for (i
= 0; i
< fx
->fc
; i
++)
756 if (fx
->fix
[i
].reloc
)
758 where
= f
- frag_now
->fr_literal
;
759 fix_new_exp (frag_now
,
771 /* Write out a short form instruction if possible.
772 Return number of instructions not written out. */
775 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
776 struct d30v_insn
*opcode1
, *opcode2
;
777 long long insn1
, insn2
;
778 exec_type_enum exec_type
;
781 long long insn
= NOP2
;
785 if (exec_type
== EXEC_SEQ
786 && (opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
))
787 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0)
788 && ((opcode1
->ecc
== ECC_AL
) || ! Optimizing
))
790 /* Unconditional, non-delayed branches kill instructions in
791 the right bin. Conditional branches don't always but if
792 we are not optimizing, then we have been asked to produce
793 an error about such constructs. For the purposes of this
794 test, subroutine calls are considered to be branches. */
795 write_1_short (opcode1
, insn1
, fx
->next
, FALSE
);
799 /* Note: we do not have to worry about subroutine calls occurring
800 in the right hand container. The return address is always
801 aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
804 case EXEC_UNKNOWN
: /* Order not specified. */
806 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
)
807 && ! ( (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
808 || opcode1
->op
->unit
== MU
)
810 ( opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
811 || opcode2
->op
->unit
== MU
)))
814 exec_type
= EXEC_PARALLEL
;
816 if (opcode1
->op
->unit
== IU
817 || opcode2
->op
->unit
== MU
818 || opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
819 insn
= FM00
| (insn2
<< 32) | insn1
;
822 insn
= FM00
| (insn1
<< 32) | insn2
;
826 else if ((opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)
827 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0))
828 || opcode1
->op
->flags_used
& FLAG_RP
)
830 /* We must emit (non-delayed) branch type instructions
831 on their own with nothing in the right container. */
832 /* We must treat repeat instructions likewise, since the
833 following instruction has to be separate from the repeat
834 in order to be repeated. */
835 write_1_short (opcode1
, insn1
, fx
->next
, FALSE
);
838 else if (prev_left_kills_right_p
)
840 /* The left instruction kils the right slot, so we
841 must leave it empty. */
842 write_1_short (opcode1
, insn1
, fx
->next
, FALSE
);
845 else if (opcode1
->op
->unit
== IU
)
847 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
849 /* Case 103810 is a request from Mitsubishi that opcodes
850 with EITHER_BUT_PREFER_MU should not be executed in
851 reverse sequential order. */
852 write_1_short (opcode1
, insn1
, fx
->next
, FALSE
);
856 /* Reverse sequential. */
857 insn
= FM10
| (insn2
<< 32) | insn1
;
858 exec_type
= EXEC_REVSEQ
;
863 insn
= FM01
| (insn1
<< 32) | insn2
;
865 exec_type
= EXEC_SEQ
;
869 case EXEC_PARALLEL
: /* Parallel. */
870 flag_explicitly_parallel
= flag_xp_state
;
871 if (! parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
872 as_bad (_("Instructions may not be executed in parallel"));
873 else if (opcode1
->op
->unit
== IU
)
875 if (opcode2
->op
->unit
== IU
)
876 as_bad (_("Two IU instructions may not be executed in parallel"));
877 as_warn (_("Swapping instruction order"));
878 insn
= FM00
| (insn2
<< 32) | insn1
;
880 else if (opcode2
->op
->unit
== MU
)
882 if (opcode1
->op
->unit
== MU
)
883 as_bad (_("Two MU instructions may not be executed in parallel"));
884 else if (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
)
885 as_warn (_("Executing %s in IU may not work"), opcode1
->op
->name
);
886 as_warn (_("Swapping instruction order"));
887 insn
= FM00
| (insn2
<< 32) | insn1
;
891 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
892 as_warn (_("Executing %s in IU may not work in parallel execution"),
895 insn
= FM00
| (insn1
<< 32) | insn2
;
898 flag_explicitly_parallel
= 0;
901 case EXEC_SEQ
: /* Sequential. */
902 if (opcode1
->op
->unit
== IU
)
903 as_bad (_("IU instruction may not be in the left container"));
904 if (prev_left_kills_right_p
)
905 as_bad (_("special left instruction `%s' kills instruction "
906 "`%s' in right container"),
907 opcode1
->op
->name
, opcode2
->op
->name
);
908 insn
= FM01
| (insn1
<< 32) | insn2
;
912 case EXEC_REVSEQ
: /* Reverse sequential. */
913 if (opcode2
->op
->unit
== MU
)
914 as_bad (_("MU instruction may not be in the right container"));
915 if (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
)
916 as_warn (_("Executing %s in reverse serial with %s may not work"),
917 opcode1
->op
->name
, opcode2
->op
->name
);
918 else if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
919 as_warn (_("Executing %s in IU in reverse serial may not work"),
921 insn
= FM10
| (insn1
<< 32) | insn2
;
926 as_fatal (_("unknown execution type passed to write_2_short()"));
930 d30v_number_to_chars (f
, insn
, 8);
932 /* If the previous instruction was a 32-bit multiply but it is put into a
933 parallel container, mark the current instruction as being a 32-bit
935 if (prev_mul32_p
&& exec_type
== EXEC_PARALLEL
)
938 for (j
= 0; j
< 2; j
++)
940 for (i
= 0; i
< fx
->fc
; i
++)
942 if (fx
->fix
[i
].reloc
)
944 where
= (f
- frag_now
->fr_literal
) + 4 * j
;
946 fix_new_exp (frag_now
,
962 /* Check 2 instructions and determine if they can be safely
963 executed in parallel. Return 1 if they can be. */
966 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
967 struct d30v_insn
*op1
, *op2
;
968 unsigned long insn1
, insn2
;
969 exec_type_enum exec_type
;
971 int i
, j
, shift
, regno
, bits
, ecc
;
972 unsigned long flags
, mask
, flags_set1
, flags_set2
, flags_used1
, flags_used2
;
973 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3], flag_reg
[2];
974 struct d30v_format
*f
;
975 struct d30v_opcode
*op
;
977 /* Section 4.3: Both instructions must not be IU or MU only. */
978 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
979 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
982 /* First instruction must not be a jump to safely optimize, unless this
983 is an explicit parallel operation. */
984 if (exec_type
!= EXEC_PARALLEL
985 && (op1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)))
988 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
989 then it is safe to allow the two to be done as parallel ops, since only
990 one will ever be executed at a time. */
991 if ((op1
->ecc
== ECC_TX
&& op2
->ecc
== ECC_FX
)
992 || (op1
->ecc
== ECC_FX
&& op2
->ecc
== ECC_TX
)
993 || (op1
->ecc
== ECC_XT
&& op2
->ecc
== ECC_XF
)
994 || (op1
->ecc
== ECC_XF
&& op2
->ecc
== ECC_XT
))
999 [2] a0, a1, flag registers. */
1000 for (j
= 0; j
< 2; j
++)
1018 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
1019 used_reg
[j
][0] = used_reg
[j
][1] = 0;
1021 if (flag_explicitly_parallel
)
1023 /* For human specified parallel instructions we have been asked
1024 to ignore the possibility that both instructions could modify
1025 bits in the PSW, so we initialise the mod & used arrays to 0.
1026 We have been asked, however, to refuse to allow parallel
1027 instructions which explicitly set the same flag register,
1028 eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test
1029 for the use of a flag register and set a bit in the mod or used
1030 array appropriately. */
1036 mod_reg
[j
][2] = (op
->flags_set
& FLAG_ALL
);
1037 used_reg
[j
][2] = (op
->flags_used
& FLAG_ALL
);
1040 /* BSR/JSR always sets R62. */
1041 if (op
->flags_used
& FLAG_JSR
)
1042 mod_reg
[j
][1] = (1L << (62 - 32));
1044 /* Conditional execution affects the flags_used. */
1049 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_0
;
1054 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_1
;
1059 used_reg
[j
][2] |= flag_reg
[j
] = (FLAG_0
| FLAG_1
);
1063 for (i
= 0; f
->operands
[i
]; i
++)
1065 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
1066 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
1067 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
1071 mask
= 0x7FFFFFFF >> (31 - bits
);
1073 if ((flags
& OPERAND_PLUS
) || (flags
& OPERAND_MINUS
))
1075 /* This is a post-increment or post-decrement.
1076 The previous register needs to be marked as modified. */
1077 shift
= 12 - d30v_operand_table
[f
->operands
[i
- 1]].position
;
1078 regno
= (ins
>> shift
) & 0x3f;
1080 mod_reg
[j
][1] |= 1L << (regno
- 32);
1082 mod_reg
[j
][0] |= 1L << regno
;
1084 else if (flags
& OPERAND_REG
)
1086 regno
= (ins
>> shift
) & mask
;
1087 /* The memory write functions don't have a destination
1089 if ((flags
& OPERAND_DEST
) && !(op
->flags_set
& FLAG_MEM
))
1091 /* MODIFIED registers and flags. */
1092 if (flags
& OPERAND_ACC
)
1095 mod_reg
[j
][2] |= FLAG_A0
;
1096 else if (regno
== 1)
1097 mod_reg
[j
][2] |= FLAG_A1
;
1101 else if (flags
& OPERAND_FLAG
)
1102 mod_reg
[j
][2] |= 1L << regno
;
1103 else if (!(flags
& OPERAND_CONTROL
))
1107 /* Need to check if there are two destination
1108 registers, for example ld2w. */
1109 if (flags
& OPERAND_2REG
)
1114 for (r
= regno
; r
<= regno
+ z
; r
++)
1117 mod_reg
[j
][1] |= 1L << (r
- 32);
1119 mod_reg
[j
][0] |= 1L << r
;
1125 /* USED, but not modified registers and flags. */
1126 if (flags
& OPERAND_ACC
)
1129 used_reg
[j
][2] |= FLAG_A0
;
1130 else if (regno
== 1)
1131 used_reg
[j
][2] |= FLAG_A1
;
1135 else if (flags
& OPERAND_FLAG
)
1136 used_reg
[j
][2] |= 1L << regno
;
1137 else if (!(flags
& OPERAND_CONTROL
))
1141 /* Need to check if there are two source
1142 registers, for example st2w. */
1143 if (flags
& OPERAND_2REG
)
1148 for (r
= regno
; r
<= regno
+ z
; r
++)
1151 used_reg
[j
][1] |= 1L << (r
- 32);
1153 used_reg
[j
][0] |= 1L << r
;
1161 flags_set1
= op1
->op
->flags_set
;
1162 flags_set2
= op2
->op
->flags_set
;
1163 flags_used1
= op1
->op
->flags_used
;
1164 flags_used2
= op2
->op
->flags_used
;
1166 /* Check for illegal combinations with ADDppp/SUBppp. */
1167 if (((flags_set1
& FLAG_NOT_WITH_ADDSUBppp
) != 0
1168 && (flags_used2
& FLAG_ADDSUBppp
) != 0)
1169 || ((flags_set2
& FLAG_NOT_WITH_ADDSUBppp
) != 0
1170 && (flags_used1
& FLAG_ADDSUBppp
) != 0))
1173 /* Load instruction combined with half-word multiply is illegal. */
1174 if (((flags_used1
& FLAG_MEM
) != 0 && (flags_used2
& FLAG_MUL16
))
1175 || ((flags_used2
& FLAG_MEM
) != 0 && (flags_used1
& FLAG_MUL16
)))
1178 /* Specifically allow add || add by removing carry, overflow bits dependency.
1179 This is safe, even if an addc follows since the IU takes the argument in
1180 the right container, and it writes its results last.
1181 However, don't paralellize add followed by addc or sub followed by
1183 if (mod_reg
[0][2] == FLAG_CVVA
&& mod_reg
[1][2] == FLAG_CVVA
1184 && (used_reg
[0][2] & ~flag_reg
[0]) == 0
1185 && (used_reg
[1][2] & ~flag_reg
[1]) == 0
1186 && op1
->op
->unit
== EITHER
&& op2
->op
->unit
== EITHER
)
1188 mod_reg
[0][2] = mod_reg
[1][2] = 0;
1191 for (j
= 0; j
< 3; j
++)
1193 /* If the second instruction depends on the first, we obviously
1194 cannot parallelize. Note, the mod flag implies use, so
1195 check that as well. */
1196 /* If flag_explicitly_parallel is set, then the case of the
1197 second instruction using a register the first instruction
1198 modifies is assumed to be okay; we trust the human. We
1199 don't trust the human if both instructions modify the same
1200 register but we do trust the human if they modify the same
1202 /* We have now been requested not to trust the human if the
1203 instructions modify the same flag registers either. */
1204 if (flag_explicitly_parallel
)
1206 if ((mod_reg
[0][j
] & mod_reg
[1][j
]) != 0)
1210 if ((mod_reg
[0][j
] & (mod_reg
[1][j
] | used_reg
[1][j
])) != 0)
1217 /* This is the main entry point for the machine-dependent assembler.
1218 STR points to a machine-dependent instruction. This function is
1219 supposed to emit the frags/bytes it assembles to. For the D30V, it
1220 mostly handles the special VLIW parsing and packing and leaves the
1221 difficult stuff to do_assemble (). */
1223 static long long prev_insn
= -1;
1224 static struct d30v_insn prev_opcode
;
1225 static subsegT prev_subseg
;
1226 static segT prev_seg
= 0;
1232 struct d30v_insn opcode
;
1234 /* Execution type; parallel, etc. */
1235 exec_type_enum extype
= EXEC_UNKNOWN
;
1236 /* Saved extype. Used for multiline instructions. */
1237 static exec_type_enum etype
= EXEC_UNKNOWN
;
1240 if ((prev_insn
!= -1) && prev_seg
1241 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1242 d30v_cleanup (FALSE
);
1244 if (d30v_current_align
< 3)
1245 d30v_align (3, NULL
, d30v_last_label
);
1246 else if (d30v_current_align
> 3)
1247 d30v_current_align
= 3;
1248 d30v_last_label
= NULL
;
1250 flag_explicitly_parallel
= 0;
1252 if (etype
== EXEC_UNKNOWN
)
1254 /* Look for the special multiple instruction separators. */
1255 str2
= strstr (str
, "||");
1258 extype
= EXEC_PARALLEL
;
1263 str2
= strstr (str
, "->");
1268 str2
= strstr (str
, "<-");
1270 extype
= EXEC_REVSEQ
;
1274 /* STR2 points to the separator, if one. */
1279 /* If two instructions are present and we already have one saved,
1280 then first write it out. */
1281 d30v_cleanup (FALSE
);
1283 /* Assemble first instruction and save it. */
1284 prev_insn
= do_assemble (str
, &prev_opcode
, 1, 0);
1285 if (prev_insn
== -1)
1286 as_bad (_("Cannot assemble instruction"));
1287 if (prev_opcode
.form
!= NULL
&& prev_opcode
.form
->form
>= LONG
)
1288 as_bad (_("First opcode is long. Unable to mix instructions as specified."));
1289 fixups
= fixups
->next
;
1292 prev_subseg
= now_subseg
;
1296 insn
= do_assemble (str
, &opcode
,
1297 (extype
!= EXEC_UNKNOWN
|| etype
!= EXEC_UNKNOWN
),
1298 extype
== EXEC_PARALLEL
);
1301 if (extype
!= EXEC_UNKNOWN
)
1303 as_bad (_("Cannot assemble instruction"));
1307 if (etype
!= EXEC_UNKNOWN
)
1310 etype
= EXEC_UNKNOWN
;
1313 /* Word multiply instructions must not be followed by either a load or a
1314 16-bit multiply instruction in the next cycle. */
1315 if ( (extype
!= EXEC_REVSEQ
)
1317 && (opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1319 /* However, load and multiply should able to be combined in a parallel
1320 operation, so check for that first. */
1322 && (opcode
.op
->flags_used
& FLAG_MEM
)
1323 && opcode
.form
->form
< LONG
1324 && (extype
== EXEC_PARALLEL
|| (Optimizing
&& extype
== EXEC_UNKNOWN
))
1325 && parallel_ok (&prev_opcode
, (long) prev_insn
,
1326 &opcode
, (long) insn
, extype
)
1327 && write_2_short (&prev_opcode
, (long) prev_insn
,
1328 &opcode
, (long) insn
, extype
, fixups
) == 0)
1330 /* No instructions saved. */
1336 /* Can't parallelize, flush previous instruction and emit a
1337 word of NOPS, unless the previous instruction is a NOP,
1338 in which case just flush it, as this will generate a word
1341 if (prev_insn
!= -1 && (strcmp (prev_opcode
.op
->name
, "nop") == 0))
1342 d30v_cleanup (FALSE
);
1347 if (prev_insn
!= -1)
1348 d30v_cleanup (TRUE
);
1352 d30v_number_to_chars (f
, NOP2
, 8);
1354 if (warn_nops
== NOP_ALL
|| warn_nops
== NOP_MULTIPLY
)
1356 if (opcode
.op
->flags_used
& FLAG_MEM
)
1357 as_warn (_("word of NOPs added between word multiply and load"));
1359 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1364 extype
= EXEC_UNKNOWN
;
1367 else if ( (extype
== EXEC_REVSEQ
)
1369 && (prev_opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1371 /* Can't parallelize, flush current instruction and add a
1373 write_1_short (&opcode
, (long) insn
, fixups
->next
->next
, TRUE
);
1375 /* Make the previous instruction the current one. */
1376 extype
= EXEC_UNKNOWN
;
1379 now_subseg
= prev_subseg
;
1381 cur_mul32_p
= prev_mul32_p
;
1383 memcpy (&opcode
, &prev_opcode
, sizeof (prev_opcode
));
1386 /* If this is a long instruction, write it and any previous short
1388 if (opcode
.form
->form
>= LONG
)
1390 if (extype
!= EXEC_UNKNOWN
)
1391 as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
1392 d30v_cleanup (FALSE
);
1393 write_long (&opcode
, insn
, fixups
);
1396 else if ((prev_insn
!= -1)
1398 (&prev_opcode
, (long) prev_insn
, &opcode
,
1399 (long) insn
, extype
, fixups
) == 0))
1401 /* No instructions saved. */
1406 if (extype
!= EXEC_UNKNOWN
)
1407 as_bad (_("Unable to mix instructions as specified"));
1409 /* Save off last instruction so it may be packed on next pass. */
1410 memcpy (&prev_opcode
, &opcode
, sizeof (prev_opcode
));
1413 prev_subseg
= now_subseg
;
1414 fixups
= fixups
->next
;
1415 prev_mul32_p
= cur_mul32_p
;
1419 /* Assemble a single instruction and return an opcode.
1420 Return -1 (an invalid opcode) on error. */
1422 #define NAME_BUF_LEN 20
1425 do_assemble (str
, opcode
, shortp
, is_parallel
)
1427 struct d30v_insn
*opcode
;
1431 unsigned char *op_start
;
1432 unsigned char *save
;
1433 unsigned char *op_end
;
1434 char name
[NAME_BUF_LEN
];
1437 int fsize
= (shortp
? FORCE_SHORT
: 0);
1438 expressionS myops
[6];
1441 /* Drop leading whitespace. */
1445 /* Find the opcode end. */
1446 for (op_start
= op_end
= (unsigned char *) (str
);
1448 && nlen
< (NAME_BUF_LEN
- 1)
1450 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1453 name
[nlen
] = TOLOWER (op_start
[nlen
]);
1462 /* If there is an execution condition code, handle it. */
1466 while ((i
< ECC_MAX
) && strncasecmp (d30v_ecc_names
[i
], op_end
+ 1, 2))
1472 strncpy (tmp
, op_end
+ 1, 2);
1474 as_bad (_("unknown condition code: %s"), tmp
);
1481 opcode
->ecc
= ECC_AL
;
1483 /* CMP and CMPU change their name based on condition codes. */
1484 if (!strncmp (name
, "cmp", 3))
1487 char **str
= (char **) d30v_cc_names
;
1493 for (i
= 1; *str
&& strncmp (*str
, &name
[p
], 2); i
++, str
++)
1496 /* cmpu only supports some condition codes. */
1502 as_bad (_("cmpu doesn't support condition code %s"), &name
[p
]);
1509 as_bad (_("unknown condition code: %s"), &name
[p
]);
1518 /* Need to look for .s or .l. */
1519 if (name
[nlen
- 2] == '.')
1521 switch (name
[nlen
- 1])
1524 fsize
= FORCE_SHORT
;
1533 /* Find the first opcode with the proper name. */
1534 opcode
->op
= (struct d30v_opcode
*) hash_find (d30v_hash
, name
);
1535 if (opcode
->op
== NULL
)
1537 as_bad (_("unknown opcode: %s"), name
);
1541 save
= input_line_pointer
;
1542 input_line_pointer
= op_end
;
1543 while (!(opcode
->form
= find_format (opcode
->op
, myops
, fsize
, cmp_hack
)))
1546 if (opcode
->op
->name
== NULL
|| strcmp (opcode
->op
->name
, name
))
1548 as_bad (_("operands for opcode `%s' do not match any valid format"),
1553 input_line_pointer
= save
;
1555 insn
= build_insn (opcode
, myops
);
1557 /* Propagate multiply status. */
1560 if (is_parallel
&& prev_mul32_p
)
1564 prev_mul32_p
= cur_mul32_p
;
1565 cur_mul32_p
= (opcode
->op
->flags_used
& FLAG_MUL32
) != 0;
1569 /* Propagate left_kills_right status. */
1572 prev_left_kills_right_p
= cur_left_kills_right_p
;
1574 if (opcode
->op
->flags_set
& FLAG_LKR
)
1576 cur_left_kills_right_p
= 1;
1578 if (strcmp (opcode
->op
->name
, "mvtsys") == 0)
1580 /* Left kills right for only mvtsys only for
1581 PSW/PSWH/PSWL/flags target. */
1582 if ((myops
[0].X_op
== O_register
) &&
1583 ((myops
[0].X_add_number
== OPERAND_CONTROL
) || /* psw */
1584 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+2) || /* pswh */
1585 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+1) || /* pswl */
1586 (myops
[0].X_add_number
== OPERAND_FLAG
+0) || /* f0 */
1587 (myops
[0].X_add_number
== OPERAND_FLAG
+1) || /* f1 */
1588 (myops
[0].X_add_number
== OPERAND_FLAG
+2) || /* f2 */
1589 (myops
[0].X_add_number
== OPERAND_FLAG
+3) || /* f3 */
1590 (myops
[0].X_add_number
== OPERAND_FLAG
+4) || /* f4 */
1591 (myops
[0].X_add_number
== OPERAND_FLAG
+5) || /* f5 */
1592 (myops
[0].X_add_number
== OPERAND_FLAG
+6) || /* f6 */
1593 (myops
[0].X_add_number
== OPERAND_FLAG
+7))) /* f7 */
1595 cur_left_kills_right_p
= 1;
1599 /* Other mvtsys target registers don't kill right
1601 cur_left_kills_right_p
= 0;
1606 cur_left_kills_right_p
= 0;
1612 /* Get a pointer to an entry in the format table.
1613 It must look at all formats for an opcode and use the operands
1614 to choose the correct one. Return NULL on error. */
1616 static struct d30v_format
*
1617 find_format (opcode
, myops
, fsize
, cmp_hack
)
1618 struct d30v_opcode
*opcode
;
1619 expressionS myops
[];
1623 int numops
, match
, index
, i
= 0, j
, k
;
1624 struct d30v_format
*fm
;
1629 /* Get all the operands and save them as expressions. */
1630 numops
= get_operands (myops
, cmp_hack
);
1632 while ((index
= opcode
->format
[i
++]) != 0)
1634 if (fsize
== FORCE_SHORT
&& index
>= LONG
)
1637 if (fsize
== FORCE_LONG
&& index
< LONG
)
1640 fm
= (struct d30v_format
*) &d30v_format_table
[index
];
1642 while (fm
->form
== index
)
1645 /* Now check the operands for compatibility. */
1646 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1648 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1649 int bits
= d30v_operand_table
[fm
->operands
[j
]].bits
;
1650 int X_op
= myops
[j
].X_op
;
1651 int num
= myops
[j
].X_add_number
;
1653 if (flags
& OPERAND_SPECIAL
)
1655 else if (X_op
== O_illegal
)
1657 else if (flags
& OPERAND_REG
)
1659 if (X_op
!= O_register
1660 || ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
))
1661 || (!(flags
& OPERAND_ACC
) && (num
& OPERAND_ACC
))
1662 || ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
))
1663 || (!(flags
& (OPERAND_FLAG
| OPERAND_CONTROL
)) && (num
& OPERAND_FLAG
))
1664 || ((flags
& OPERAND_CONTROL
)
1665 && !(num
& (OPERAND_CONTROL
| OPERAND_FLAG
))))
1670 else if (((flags
& OPERAND_MINUS
)
1671 && (X_op
!= O_absent
|| num
!= OPERAND_MINUS
))
1672 || ((flags
& OPERAND_PLUS
)
1673 && (X_op
!= O_absent
|| num
!= OPERAND_PLUS
))
1674 || ((flags
& OPERAND_ATMINUS
)
1675 && (X_op
!= O_absent
|| num
!= OPERAND_ATMINUS
))
1676 || ((flags
& OPERAND_ATPAR
)
1677 && (X_op
!= O_absent
|| num
!= OPERAND_ATPAR
))
1678 || ((flags
& OPERAND_ATSIGN
)
1679 && (X_op
!= O_absent
|| num
!= OPERAND_ATSIGN
)))
1683 else if (flags
& OPERAND_NUM
)
1685 /* A number can be a constant or symbol expression. */
1687 /* If we have found a register name, but that name
1688 also matches a symbol, then re-parse the name as
1690 if (X_op
== O_register
1691 && symbol_find ((char *) myops
[j
].X_op_symbol
))
1693 input_line_pointer
= (char *) myops
[j
].X_op_symbol
;
1694 expression (&myops
[j
]);
1697 /* Turn an expression into a symbol for later resolution. */
1698 if (X_op
!= O_absent
&& X_op
!= O_constant
1699 && X_op
!= O_symbol
&& X_op
!= O_register
1702 symbolS
*sym
= make_expr_symbol (&myops
[j
]);
1703 myops
[j
].X_op
= X_op
= O_symbol
;
1704 myops
[j
].X_add_symbol
= sym
;
1705 myops
[j
].X_add_number
= num
= 0;
1708 if (fm
->form
>= LONG
)
1710 /* If we're testing for a LONG format, either fits. */
1711 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1714 else if (fm
->form
< LONG
1715 && ((fsize
== FORCE_SHORT
&& X_op
== O_symbol
)
1716 || (fm
->form
== SHORT_D2
&& j
== 0)))
1719 /* This is the tricky part. Will the constant or symbol
1720 fit into the space in the current format? */
1721 else if (X_op
== O_constant
)
1723 if (check_range (num
, bits
, flags
))
1726 else if (X_op
== O_symbol
1727 && S_IS_DEFINED (myops
[j
].X_add_symbol
)
1728 && S_GET_SEGMENT (myops
[j
].X_add_symbol
) == now_seg
1729 && opcode
->reloc_flag
== RELOC_PCREL
)
1731 /* If the symbol is defined, see if the value will fit
1732 into the form we're considering. */
1736 /* Calculate the current address by running through the
1737 previous frags and adding our current offset. */
1739 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1740 value
+= f
->fr_fix
+ f
->fr_offset
;
1741 value
= (S_GET_VALUE (myops
[j
].X_add_symbol
) - value
1742 - (obstack_next_free (&frchain_now
->frch_obstack
)
1743 - frag_now
->fr_literal
));
1744 if (check_range (value
, bits
, flags
))
1751 /* We're only done if the operands matched so far AND there
1752 are no more to check. */
1753 if (match
&& myops
[j
].X_op
== 0)
1755 /* Final check - issue a warning if an odd numbered register
1756 is used as the first register in an instruction that reads
1757 or writes 2 registers. */
1759 for (j
= 0; fm
->operands
[j
]; j
++)
1760 if (myops
[j
].X_op
== O_register
1761 && (myops
[j
].X_add_number
& 1)
1762 && (d30v_operand_table
[fm
->operands
[j
]].flags
& OPERAND_2REG
))
1763 as_warn (_("Odd numbered register used as target of multi-register instruction"));
1767 fm
= (struct d30v_format
*) &d30v_format_table
[++k
];
1773 /* If while processing a fixup, a reloc really needs to be created,
1774 then it is done here. */
1777 tc_gen_reloc (seg
, fixp
)
1778 asection
*seg ATTRIBUTE_UNUSED
;
1782 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1783 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1784 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1785 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1786 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1787 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1789 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1790 _("reloc %d not supported by object file format"),
1791 (int) fixp
->fx_r_type
);
1800 md_estimate_size_before_relax (fragp
, seg
)
1801 fragS
*fragp ATTRIBUTE_UNUSED
;
1802 asection
*seg ATTRIBUTE_UNUSED
;
1809 md_pcrel_from_section (fixp
, sec
)
1813 if (fixp
->fx_addsy
!= (symbolS
*) NULL
1814 && (!S_IS_DEFINED (fixp
->fx_addsy
)
1815 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1817 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1821 md_apply_fix3 (fixP
, valP
, seg
)
1824 segT seg ATTRIBUTE_UNUSED
;
1827 unsigned long insn
, insn2
;
1830 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
1833 /* We don't support subtracting a symbol. */
1834 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
1835 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
1837 /* Fetch the instruction, insert the fully resolved operand
1838 value, and stuff the instruction back again. */
1839 where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
1840 insn
= bfd_getb32 ((unsigned char *) where
);
1842 switch (fixP
->fx_r_type
)
1844 case BFD_RELOC_8
: /* Check for a bad .byte directive. */
1845 if (fixP
->fx_addsy
!= NULL
)
1846 as_bad (_("line %d: unable to place address of symbol '%s' into a byte"),
1847 fixP
->fx_line
, S_GET_NAME (fixP
->fx_addsy
));
1848 else if (((unsigned)value
) > 0xff)
1849 as_bad (_("line %d: unable to place value %lx into a byte"),
1850 fixP
->fx_line
, value
);
1852 *(unsigned char *) where
= value
;
1855 case BFD_RELOC_16
: /* Check for a bad .short directive. */
1856 if (fixP
->fx_addsy
!= NULL
)
1857 as_bad (_("line %d: unable to place address of symbol '%s' into a short"),
1858 fixP
->fx_line
, S_GET_NAME (fixP
->fx_addsy
));
1859 else if (((unsigned)value
) > 0xffff)
1860 as_bad (_("line %d: unable to place value %lx into a short"),
1861 fixP
->fx_line
, value
);
1863 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1866 case BFD_RELOC_64
: /* Check for a bad .quad directive. */
1867 if (fixP
->fx_addsy
!= NULL
)
1868 as_bad (_("line %d: unable to place address of symbol '%s' into a quad"),
1869 fixP
->fx_line
, S_GET_NAME (fixP
->fx_addsy
));
1872 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1873 bfd_putb32 (0, ((unsigned char *) where
) + 4);
1877 case BFD_RELOC_D30V_6
:
1878 check_size (value
, 6, fixP
->fx_file
, fixP
->fx_line
);
1879 insn
|= value
& 0x3F;
1880 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1883 case BFD_RELOC_D30V_9_PCREL
:
1884 if (fixP
->fx_where
& 0x7)
1889 fixP
->fx_r_type
= BFD_RELOC_D30V_9_PCREL_R
;
1891 check_size (value
, 9, fixP
->fx_file
, fixP
->fx_line
);
1892 insn
|= ((value
>> 3) & 0x3F) << 12;
1893 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1896 case BFD_RELOC_D30V_15
:
1897 check_size (value
, 15, fixP
->fx_file
, fixP
->fx_line
);
1898 insn
|= (value
>> 3) & 0xFFF;
1899 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1902 case BFD_RELOC_D30V_15_PCREL
:
1903 if (fixP
->fx_where
& 0x7)
1908 fixP
->fx_r_type
= BFD_RELOC_D30V_15_PCREL_R
;
1910 check_size (value
, 15, fixP
->fx_file
, fixP
->fx_line
);
1911 insn
|= (value
>> 3) & 0xFFF;
1912 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1915 case BFD_RELOC_D30V_21
:
1916 check_size (value
, 21, fixP
->fx_file
, fixP
->fx_line
);
1917 insn
|= (value
>> 3) & 0x3FFFF;
1918 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1921 case BFD_RELOC_D30V_21_PCREL
:
1922 if (fixP
->fx_where
& 0x7)
1927 fixP
->fx_r_type
= BFD_RELOC_D30V_21_PCREL_R
;
1929 check_size (value
, 21, fixP
->fx_file
, fixP
->fx_line
);
1930 insn
|= (value
>> 3) & 0x3FFFF;
1931 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1934 case BFD_RELOC_D30V_32
:
1935 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1936 insn
|= (value
>> 26) & 0x3F; /* Top 6 bits. */
1937 insn2
|= ((value
& 0x03FC0000) << 2); /* Next 8 bits. */
1938 insn2
|= value
& 0x0003FFFF; /* Bottom 18 bits. */
1939 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1940 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1943 case BFD_RELOC_D30V_32_PCREL
:
1944 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1945 insn
|= (value
>> 26) & 0x3F; /* Top 6 bits. */
1946 insn2
|= ((value
& 0x03FC0000) << 2); /* Next 8 bits. */
1947 insn2
|= value
& 0x0003FFFF; /* Bottom 18 bits. */
1948 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1949 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1953 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1957 as_bad (_("line %d: unknown relocation type: 0x%x"),
1958 fixP
->fx_line
, fixP
->fx_r_type
);
1962 /* Called after the assembler has finished parsing the input file or
1963 after a label is defined. Because the D30V assembler sometimes
1964 saves short instructions to see if it can package them with the
1965 next instruction, there may be a short instruction that still needs
1969 d30v_cleanup (use_sequential
)
1975 if (prev_insn
!= -1)
1978 subseg
= now_subseg
;
1979 subseg_set (prev_seg
, prev_subseg
);
1980 write_1_short (&prev_opcode
, (long) prev_insn
, fixups
->next
,
1982 subseg_set (seg
, subseg
);
1985 prev_mul32_p
= FALSE
;
1992 d30v_number_to_chars (buf
, value
, n
)
1993 char *buf
; /* Return 'nbytes' of chars here. */
1994 long long value
; /* The value of the bits. */
1995 int n
; /* Number of bytes in the output. */
1999 buf
[n
] = value
& 0xff;
2004 /* This function is called at the start of every line. It checks to
2005 see if the first character is a '.', which indicates the start of a
2006 pseudo-op. If it is, then write out any unwritten instructions. */
2011 char *c
= input_line_pointer
;
2013 while (ISSPACE (*c
))
2017 d30v_cleanup (FALSE
);
2021 check_size (value
, bits
, file
, line
)
2034 max
= (1 << (bits
- 1)) - 1;
2037 as_bad_where (file
, line
, _("value too large to fit in %d bits"), bits
);
2040 /* d30v_frob_label() is called when after a label is recognized. */
2043 d30v_frob_label (lab
)
2046 /* Emit any pending instructions. */
2047 d30v_cleanup (FALSE
);
2049 /* Update the label's address with the current output pointer. */
2050 symbol_set_frag (lab
, frag_now
);
2051 S_SET_VALUE (lab
, (valueT
) frag_now_fix ());
2053 /* Record this label for future adjustment after we find out what
2054 kind of data it references, and the required alignment therewith. */
2055 d30v_last_label
= lab
;
2058 /* Hook into cons for capturing alignment changes. */
2061 d30v_cons_align (size
)
2067 while ((size
>>= 1) != 0)
2070 if (d30v_current_align
< log_size
)
2071 d30v_align (log_size
, (char *) NULL
, NULL
);
2072 else if (d30v_current_align
> log_size
)
2073 d30v_current_align
= log_size
;
2074 d30v_last_label
= NULL
;
2077 /* Called internally to handle all alignment needs. This takes care
2078 of eliding calls to frag_align if'n the cached current alignment
2079 says we've already got it, as well as taking care of the auto-aligning
2083 d30v_align (n
, pfill
, label
)
2088 /* The front end is prone to changing segments out from under us
2089 temporarily when -g is in effect. */
2090 int switched_seg_p
= (d30v_current_align_seg
!= now_seg
);
2092 /* Do not assume that if 'd30v_current_align >= n' and
2093 '! switched_seg_p' that it is safe to avoid performing
2094 this alignment request. The alignment of the current frag
2095 can be changed under our feet, for example by a .ascii
2096 directive in the source code. cf testsuite/gas/d30v/reloc.s */
2097 d30v_cleanup (FALSE
);
2102 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
2104 static char const nop
[4] = { 0x00, 0xf0, 0x00, 0x00 };
2106 /* First, make sure we're on a four-byte boundary, in case
2107 someone has been putting .byte values the text section. */
2108 if (d30v_current_align
< 2 || switched_seg_p
)
2109 frag_align (2, 0, 0);
2110 frag_align_pattern (n
, nop
, sizeof nop
, 0);
2113 frag_align (n
, 0, 0);
2116 frag_align (n
, *pfill
, 0);
2118 if (!switched_seg_p
)
2119 d30v_current_align
= n
;
2124 int label_seen
= FALSE
;
2125 struct frag
*old_frag
;
2129 assert (S_GET_SEGMENT (label
) == now_seg
);
2131 old_frag
= symbol_get_frag (label
);
2132 old_value
= S_GET_VALUE (label
);
2133 new_value
= (valueT
) frag_now_fix ();
2135 /* It is possible to have more than one label at a particular
2136 address, especially if debugging is enabled, so we must
2137 take care to adjust all the labels at this address in this
2138 fragment. To save time we search from the end of the symbol
2139 list, backwards, since the symbols we are interested in are
2140 almost certainly the ones that were most recently added.
2141 Also to save time we stop searching once we have seen at least
2142 one matching label, and we encounter a label that is no longer
2143 in the target fragment. Note, this search is guaranteed to
2144 find at least one match when sym == label, so no special case
2145 code is necessary. */
2146 for (sym
= symbol_lastP
; sym
!= NULL
; sym
= symbol_previous (sym
))
2148 if (symbol_get_frag (sym
) == old_frag
2149 && S_GET_VALUE (sym
) == old_value
)
2152 symbol_set_frag (sym
, frag_now
);
2153 S_SET_VALUE (sym
, new_value
);
2155 else if (label_seen
&& symbol_get_frag (sym
) != old_frag
)
2160 record_alignment (now_seg
, n
);
2163 /* Handle the .align pseudo-op. This aligns to a power of two. We
2164 hook here to latch the current alignment. */
2167 s_d30v_align (ignore
)
2168 int ignore ATTRIBUTE_UNUSED
;
2171 char fill
, *pfill
= NULL
;
2172 long max_alignment
= 15;
2174 align
= get_absolute_expression ();
2175 if (align
> max_alignment
)
2177 align
= max_alignment
;
2178 as_warn (_("Alignment too large: %d assumed"), align
);
2182 as_warn (_("Alignment negative: 0 assumed"));
2186 if (*input_line_pointer
== ',')
2188 input_line_pointer
++;
2189 fill
= get_absolute_expression ();
2193 d30v_last_label
= NULL
;
2194 d30v_align (align
, pfill
, NULL
);
2196 demand_empty_rest_of_line ();
2199 /* Handle the .text pseudo-op. This is like the usual one, but it
2200 clears the saved last label and resets known alignment. */
2208 d30v_last_label
= NULL
;
2209 d30v_current_align
= 0;
2210 d30v_current_align_seg
= now_seg
;
2213 /* Handle the .data pseudo-op. This is like the usual one, but it
2214 clears the saved last label and resets known alignment. */
2221 d30v_last_label
= NULL
;
2222 d30v_current_align
= 0;
2223 d30v_current_align_seg
= now_seg
;
2226 /* Handle the .section pseudo-op. This is like the usual one, but it
2227 clears the saved last label and resets known alignment. */
2230 s_d30v_section (ignore
)
2233 obj_elf_section (ignore
);
2234 d30v_last_label
= NULL
;
2235 d30v_current_align
= 0;
2236 d30v_current_align_seg
= now_seg
;