1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
3 Copyright (C) 1997, 1998 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d30v.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "OnNcC";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
35 #define NOP_MULTIPLY 1
37 static int warn_nops
= 0;
38 static int Optimizing
= 0;
39 static int warn_register_name_conflicts
= 1;
45 typedef enum _exec_type
47 EXEC_UNKNOWN
, /* no order specified */
48 EXEC_PARALLEL
, /* done in parallel (FM=00) */
49 EXEC_SEQ
, /* sequential (FM=01) */
50 EXEC_REVSEQ
/* reverse sequential (FM=10) */
54 #define MAX_INSN_FIXUPS (5)
61 bfd_reloc_code_real_type reloc
;
64 typedef struct _fixups
67 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
71 static Fixups FixUps
[2];
72 static Fixups
*fixups
;
74 /* Whether current and previous instruction are word multiply insns. */
75 static int cur_mul32_p
= 0;
76 static int prev_mul32_p
= 0;
78 /* The flag_explicitly_parallel is true iff the instruction being assembled
79 has been explicitly written as a parallel short-instruction pair by the
80 human programmer. It is used in parallel_ok() to distinguish between
81 those dangerous parallelizations attempted by the human, which are to be
82 allowed, and those attempted by the assembler, which are not. It is set
83 from md_assemble(). */
84 static int flag_explicitly_parallel
= 0;
85 static int flag_xp_state
= 0;
87 /* Whether current and previous left sub-instruction disables
88 execution of right sub-instruction. */
89 static int cur_left_kills_right_p
= 0;
90 static int prev_left_kills_right_p
= 0;
92 /* The known current alignment of the current section. */
93 static int d30v_current_align
;
94 static segT d30v_current_align_seg
;
96 /* The last seen label in the current section. This is used to auto-align
97 labels preceeding instructions. */
98 static symbolS
*d30v_last_label
;
101 #define NOP_LEFT ((long long)NOP << 32)
102 #define NOP_RIGHT ((long long)NOP)
103 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
105 /* local functions */
106 static int reg_name_search
PARAMS ((char *name
));
107 static int register_name
PARAMS ((expressionS
*expressionP
));
108 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
109 static int postfix
PARAMS ((char *p
));
110 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
111 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
112 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
,
113 expressionS ops
[],int fsize
, int cmp_hack
));
114 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
115 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
116 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
,
117 Fixups
*fx
, int use_sequential
));
118 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
119 struct d30v_insn
*opcode2
, long long insn2
, exec_type_enum exec_type
, Fixups
*fx
));
120 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
,
121 int shortp
, int is_parallel
));
122 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
123 struct d30v_insn
*opcode2
, unsigned long insn2
,
124 exec_type_enum exec_type
));
125 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
126 static void check_size
PARAMS ((long value
, int bits
, char *file
, int line
));
127 static void d30v_align
PARAMS ((int, char *, symbolS
*));
128 static void s_d30v_align
PARAMS ((int));
129 static void s_d30v_text
PARAMS ((int));
130 static void s_d30v_data
PARAMS ((int));
131 static void s_d30v_section
PARAMS ((int));
133 struct option md_longopts
[] = {
134 {NULL
, no_argument
, NULL
, 0}
136 size_t md_longopts_size
= sizeof(md_longopts
);
139 /* The target specific pseudo-ops which we support. */
140 const pseudo_typeS md_pseudo_table
[] =
143 { "hword", cons
, 2 },
144 { "align", s_d30v_align
, 0 },
145 { "text", s_d30v_text
, 0 },
146 { "data", s_d30v_data
, 0 },
147 { "section", s_d30v_section
, 0 },
148 { "section.s", s_d30v_section
, 0 },
149 { "sect", s_d30v_section
, 0 },
150 { "sect.s", s_d30v_section
, 0 },
154 /* Opcode hash table. */
155 static struct hash_control
*d30v_hash
;
157 /* reg_name_search does a binary search of the pre_defined_registers
158 array to see if "name" is a valid regiter name. Returns the register
159 number from the array on success, or -1 on failure. */
162 reg_name_search (name
)
165 int middle
, low
, high
;
169 high
= reg_name_cnt () - 1;
171 if (symbol_find (name
) != NULL
)
173 if (warn_register_name_conflicts
)
174 as_warn ("Register name %s conflicts with symbol of the same name",
180 middle
= (low
+ high
) / 2;
181 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
187 return pre_defined_registers
[middle
].value
;
194 /* register_name() checks the string at input_line_pointer
195 to see if it is a valid register name */
198 register_name (expressionP
)
199 expressionS
*expressionP
;
202 char c
, *p
= input_line_pointer
;
204 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
211 /* look to see if it's in the register table */
212 reg_number
= reg_name_search (input_line_pointer
);
215 expressionP
->X_op
= O_register
;
216 /* temporarily store a pointer to the string here */
217 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
218 expressionP
->X_add_number
= reg_number
;
219 input_line_pointer
= p
;
229 check_range (num
, bits
, flags
)
237 /* don't bother checking 32-bit values */
241 if (flags
& OPERAND_SHIFT
)
243 /* We know that all shifts are right by three bits.... */
245 if (flags
& OPERAND_SIGNED
)
246 num
= (unsigned long) (((/*signed*/ long) num
) >> 3);
251 if (flags
& OPERAND_SIGNED
)
253 max
= (1 << (bits
- 1))-1;
254 min
= - (1 << (bits
- 1));
255 if (((long)num
> max
) || ((long)num
< min
))
260 max
= (1 << bits
) - 1;
262 if ((num
> max
) || (num
< min
))
270 md_show_usage (stream
)
273 fprintf (stream
, _("\nD30V options:\n\
274 -O Make adjacent short instructions parallel if possible.\n\
275 -n Warn about all NOPs inserted by the assembler.\n\
276 -N Warn about NOPs inserted after word multiplies.\n\
277 -c Warn about symbols whoes names match register names.\n\
278 -C Opposite of -C. -c is the default.\n"));
282 md_parse_option (c
, arg
)
288 /* Optimize. Will attempt to parallelize operations */
293 /* Warn about all NOPS that the assembler inserts. */
298 /* Warn about the NOPS that the assembler inserts because of the
301 warn_nops
= NOP_MULTIPLY
;
305 warn_register_name_conflicts
= 1;
309 warn_register_name_conflicts
= 0;
319 md_undefined_symbol (name
)
325 /* Turn a string in input_line_pointer into a floating point constant of type
326 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
327 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
330 md_atof (type
, litP
, sizeP
)
336 LITTLENUM_TYPE words
[4];
350 return _("bad call to md_atof");
353 t
= atof_ieee (input_line_pointer
, type
, words
);
355 input_line_pointer
= t
;
359 for (i
= 0; i
< prec
; i
++)
361 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
368 md_convert_frag (abfd
, sec
, fragP
)
377 md_section_align (seg
, addr
)
381 int align
= bfd_get_section_alignment (stdoutput
, seg
);
382 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
389 struct d30v_opcode
*opcode
;
390 d30v_hash
= hash_new ();
392 /* Insert opcode names into a hash table. */
393 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
394 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
397 FixUps
[0].next
= &FixUps
[1];
398 FixUps
[1].next
= &FixUps
[0];
400 d30v_current_align_seg
= now_seg
;
404 /* this function removes the postincrement or postdecrement
405 operator ( '+' or '-' ) from an expression */
407 static int postfix (p
)
410 while (*p
!= '-' && *p
!= '+')
412 if (*p
==0 || *p
=='\n' || *p
=='\r' || *p
==' ' || *p
==',')
432 static bfd_reloc_code_real_type
433 get_reloc (op
, rel_flag
)
434 struct d30v_operand
*op
;
440 if (op
->flags
& OPERAND_SHIFT
)
441 return BFD_RELOC_D30V_9_PCREL
;
443 return BFD_RELOC_D30V_6
;
446 if (!(op
->flags
& OPERAND_SHIFT
))
447 as_warn (_("unexpected 12-bit reloc type"));
448 if (rel_flag
== RELOC_PCREL
)
449 return BFD_RELOC_D30V_15_PCREL
;
451 return BFD_RELOC_D30V_15
;
453 if (!(op
->flags
& OPERAND_SHIFT
))
454 as_warn (_("unexpected 18-bit reloc type"));
455 if (rel_flag
== RELOC_PCREL
)
456 return BFD_RELOC_D30V_21_PCREL
;
458 return BFD_RELOC_D30V_21
;
460 if (rel_flag
== RELOC_PCREL
)
461 return BFD_RELOC_D30V_32_PCREL
;
463 return BFD_RELOC_D30V_32
;
469 /* get_operands parses a string of operands and returns
470 an array of expressions */
473 get_operands (exp
, cmp_hack
)
477 char *p
= input_line_pointer
;
483 exp
[numops
].X_op
= O_absent
;
484 exp
[numops
++].X_add_number
= cmp_hack
- 1;
489 while (*p
== ' ' || *p
== '\t' || *p
== ',')
491 if (*p
==0 || *p
=='\n' || *p
=='\r')
497 exp
[numops
].X_op
= O_absent
;
501 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
507 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
511 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
520 /* just skip the trailing paren */
525 input_line_pointer
= p
;
527 /* check to see if it might be a register name */
528 if (!register_name (&exp
[numops
]))
530 /* parse as an expression */
531 expression (&exp
[numops
]);
534 if (exp
[numops
].X_op
== O_illegal
)
535 as_bad (_("illegal operand"));
536 else if (exp
[numops
].X_op
== O_absent
)
537 as_bad (_("missing operand"));
540 p
= input_line_pointer
;
544 case -1: /* postdecrement mode */
545 exp
[numops
].X_op
= O_absent
;
546 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
548 case 1: /* postincrement mode */
549 exp
[numops
].X_op
= O_absent
;
550 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
556 exp
[numops
].X_op
= 0;
560 /* build_insn generates the instruction. It does everything */
561 /* but write the FM bits. */
564 build_insn (opcode
, opers
)
565 struct d30v_insn
*opcode
;
568 int i
, length
, bits
, shift
, flags
;
569 unsigned int number
, id
=0;
571 struct d30v_opcode
*op
= opcode
->op
;
572 struct d30v_format
*form
= opcode
->form
;
574 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
576 for (i
=0; form
->operands
[i
]; i
++)
578 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
580 /* must be a register or number */
581 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
582 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
585 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
586 if (flags
& OPERAND_SHIFT
)
589 length
= d30v_operand_table
[form
->operands
[i
]].length
;
590 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
591 if (opers
[i
].X_op
!= O_symbol
)
592 number
= opers
[i
].X_add_number
;
595 if (flags
& OPERAND_REG
)
597 /* check for mvfsys or mvtsys control registers */
598 if (flags
& OPERAND_CONTROL
&& (number
& 0x7f) > MAX_CONTROL_REG
)
601 id
= (number
& 0x7f) - MAX_CONTROL_REG
;
604 else if (number
& OPERAND_FLAG
)
606 id
= 3; /* number is a flag register */
610 else if (flags
& OPERAND_SPECIAL
)
615 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
617 /* now create a fixup */
619 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
620 as_fatal (_("too many fixups"));
622 fixups
->fix
[fixups
->fc
].reloc
=
623 get_reloc ((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
624 fixups
->fix
[fixups
->fc
].size
= 4;
625 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
626 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
627 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D30V_9_PCREL
)
628 fixups
->fix
[fixups
->fc
].pcrel
= RELOC_PCREL
;
630 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
634 /* truncate to the proper number of bits */
635 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
636 as_bad (_("operand out of range: %d"),number
);
638 number
&= 0x7FFFFFFF >> (31 - bits
);
639 if (flags
& OPERAND_SHIFT
)
643 /* it's a LONG instruction */
644 insn
|= (number
>> 26); /* top 6 bits */
645 insn
<<= 32; /* shift the first word over */
646 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
647 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
650 insn
|= number
<< shift
;
656 /* write out a long form instruction */
658 write_long (opcode
, insn
, fx
)
659 struct d30v_insn
*opcode
;
664 char *f
= frag_more (8);
667 d30v_number_to_chars (f
, insn
, 8);
669 for (i
=0; i
< fx
->fc
; i
++)
671 if (fx
->fix
[i
].reloc
)
673 where
= f
- frag_now
->fr_literal
;
674 fix_new_exp (frag_now
,
686 /* Write out a short form instruction by itself. */
688 write_1_short (opcode
, insn
, fx
, use_sequential
)
689 struct d30v_insn
*opcode
;
694 char *f
= frag_more (8);
697 if (warn_nops
== NOP_ALL
)
698 as_warn (_("%s NOP inserted"), use_sequential
?
699 _("sequential") : _("parallel"));
701 /* The other container needs to be NOP. */
704 /* Use a sequential NOP rather than a parallel one,
705 as the current instruction is a FLAG_MUL32 type one
706 and the next instruction is a load. */
708 /* According to 4.3.1: for FM=01, sub-instructions performed
709 only by IU cannot be encoded in L-container. */
711 if (opcode
->op
->unit
== IU
)
712 insn
|= FM10
| NOP_LEFT
; /* right then left */
714 insn
= FM01
| (insn
<< 32) | NOP_RIGHT
; /* left then right */
718 /* According to 4.3.1: for FM=00, sub-instructions performed
719 only by IU cannot be encoded in L-container. */
721 if (opcode
->op
->unit
== IU
)
722 insn
|= FM00
| NOP_LEFT
; /* right container */
724 insn
= FM00
| (insn
<< 32) | NOP_RIGHT
; /* left container */
727 d30v_number_to_chars (f
, insn
, 8);
729 for (i
=0; i
< fx
->fc
; i
++)
731 if (fx
->fix
[i
].reloc
)
733 where
= f
- frag_now
->fr_literal
;
734 fix_new_exp (frag_now
,
745 /* Write out a short form instruction if possible; */
746 /* return number of instructions not written out. */
748 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
749 struct d30v_insn
*opcode1
, *opcode2
;
750 long long insn1
, insn2
;
751 exec_type_enum exec_type
;
754 long long insn
= NOP2
;
758 if (exec_type
!= EXEC_PARALLEL
&&
759 ((opcode1
->op
->flags_used
& (FLAG_JSR
| FLAG_DELAY
)) == FLAG_JSR
))
761 /* subroutines must be called from 32-bit boundaries */
762 /* so the return address will be correct */
763 write_1_short (opcode1
, insn1
, fx
->next
, false);
769 case EXEC_UNKNOWN
: /* order not specified */
771 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
)
772 && ! ( (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
773 || opcode1
->op
->unit
== MU
)
775 ( opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
776 || opcode2
->op
->unit
== MU
)))
779 exec_type
= EXEC_PARALLEL
;
781 if (opcode1
->op
->unit
== IU
782 || opcode2
->op
->unit
== MU
783 || opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
784 insn
= FM00
| (insn2
<< 32) | insn1
;
787 insn
= FM00
| (insn1
<< 32) | insn2
;
791 else if (opcode1
->op
->unit
== IU
792 || (opcode1
->op
->unit
== EITHER
793 && opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
))
795 /* reverse sequential */
796 insn
= FM10
| (insn2
<< 32) | insn1
;
797 exec_type
= EXEC_REVSEQ
;
802 insn
= FM01
| (insn1
<< 32) | insn2
;
804 exec_type
= EXEC_SEQ
;
808 case EXEC_PARALLEL
: /* parallel */
809 flag_explicitly_parallel
= flag_xp_state
;
810 if (! parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
811 as_fatal (_("Instructions may not be executed in parallel"));
812 else if (opcode1
->op
->unit
== IU
)
814 if (opcode2
->op
->unit
== IU
)
815 as_fatal (_("Two IU instructions may not be executed in parallel"));
816 as_warn (_("Swapping instruction order"));
817 insn
= FM00
| (insn2
<< 32) | insn1
;
819 else if (opcode2
->op
->unit
== MU
)
821 if (opcode1
->op
->unit
== MU
)
822 as_fatal (_("Two MU instructions may not be executed in parallel"));
823 else if (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
)
824 as_warn (_("Executing %s in IU may not work", opcode1
->op
->name
));
825 as_warn (_("Swapping instruction order"));
826 insn
= FM00
| (insn2
<< 32) | insn1
;
830 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
831 as_warn ("Executing %s in IU may not work", opcode2
->op
->name
);
833 insn
= FM00
| (insn1
<< 32) | insn2
;
836 flag_explicitly_parallel
= 0;
839 case EXEC_SEQ
: /* sequential */
840 if (opcode1
->op
->unit
== IU
)
841 as_fatal (_("IU instruction may not be in the left container"));
842 if (prev_left_kills_right_p
)
843 as_warn (_("special left instruction `%s' kills instruction "
844 "`%s' in right container"),
845 opcode1
->op
->name
, opcode2
->op
->name
);
846 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
847 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
848 insn
= FM01
| (insn1
<< 32) | insn2
;
852 case EXEC_REVSEQ
: /* reverse sequential */
853 if (opcode2
->op
->unit
== MU
)
854 as_fatal (_("MU instruction may not be in the right container"));
855 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
856 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
857 insn
= FM10
| (insn1
<< 32) | insn2
;
862 as_fatal (_("unknown execution type passed to write_2_short()"));
865 /* printf("writing out %llx\n",insn); */
867 d30v_number_to_chars (f
, insn
, 8);
869 /* If the previous instruction was a 32-bit multiply but it is put into a
870 parallel container, mark the current instruction as being a 32-bit
872 if (prev_mul32_p
&& exec_type
== EXEC_PARALLEL
)
877 for (i
=0; i
< fx
->fc
; i
++)
879 if (fx
->fix
[i
].reloc
)
881 where
= (f
- frag_now
->fr_literal
) + 4*j
;
883 fix_new_exp (frag_now
,
900 /* Check 2 instructions and determine if they can be safely */
901 /* executed in parallel. Returns 1 if they can be. */
903 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
904 struct d30v_insn
*op1
, *op2
;
905 unsigned long insn1
, insn2
;
906 exec_type_enum exec_type
;
908 int i
, j
, shift
, regno
, bits
, ecc
;
909 unsigned long flags
, mask
, flags_set1
, flags_set2
, flags_used1
, flags_used2
;
910 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3], flag_reg
[2];
911 struct d30v_format
*f
;
912 struct d30v_opcode
*op
;
914 /* section 4.3: both instructions must not be IU or MU only */
915 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
916 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
919 /* first instruction must not be a jump to safely optimize, unless this
920 is an explicit parallel operation. */
921 if (exec_type
!= EXEC_PARALLEL
922 && (op1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)))
925 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
926 then it is safe to allow the two to be done as parallel ops, since only
927 one will ever be executed at a time. */
928 if ((op1
->ecc
== ECC_TX
&& op2
->ecc
== ECC_FX
)
929 || (op1
->ecc
== ECC_FX
&& op2
->ecc
== ECC_TX
)
930 || (op1
->ecc
== ECC_XT
&& op2
->ecc
== ECC_XF
)
931 || (op1
->ecc
== ECC_XF
&& op2
->ecc
== ECC_XT
))
936 [2] a0, a1, flag registers */
938 for (j
= 0; j
< 2; j
++)
955 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
956 mod_reg
[j
][2] = (op
->flags_set
& FLAG_ALL
);
957 used_reg
[j
][0] = used_reg
[j
][1] = 0;
958 used_reg
[j
][2] = (op
->flags_used
& FLAG_ALL
);
960 /* BSR/JSR always sets R62 */
961 if (op
->flags_used
& FLAG_JSR
)
962 mod_reg
[j
][1] = (1L << (62-32));
964 /* conditional execution affects the flags_used */
969 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_0
;
974 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_1
;
979 used_reg
[j
][2] |= flag_reg
[j
] = (FLAG_0
| FLAG_1
);
983 for (i
= 0; f
->operands
[i
]; i
++)
985 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
986 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
987 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
991 mask
= 0x7FFFFFFF >> (31 - bits
);
993 if ((flags
& OPERAND_PLUS
) || (flags
& OPERAND_MINUS
))
995 /* this is a post-increment or post-decrement */
996 /* the previous register needs to be marked as modified */
998 shift
= 12 - d30v_operand_table
[f
->operands
[i
-1]].position
;
999 regno
= (ins
>> shift
) & 0x3f;
1001 mod_reg
[j
][1] |= 1L << (regno
- 32);
1003 mod_reg
[j
][0] |= 1L << regno
;
1005 else if (flags
& OPERAND_REG
)
1007 regno
= (ins
>> shift
) & mask
;
1008 /* the memory write functions don't have a destination register */
1009 if ((flags
& OPERAND_DEST
) && !(op
->flags_set
& FLAG_MEM
))
1011 /* MODIFIED registers and flags */
1012 if (flags
& OPERAND_ACC
)
1015 mod_reg
[j
][2] |= FLAG_A0
;
1016 else if (regno
== 1)
1017 mod_reg
[j
][2] |= FLAG_A1
;
1021 else if (flags
& OPERAND_FLAG
)
1022 mod_reg
[j
][2] |= 1L << regno
;
1023 else if (!(flags
& OPERAND_CONTROL
))
1027 /* need to check if there are two destination */
1028 /* registers, for example ld2w */
1029 if (flags
& OPERAND_2REG
)
1034 for (r
= regno
; r
<= regno
+ z
; r
++)
1037 mod_reg
[j
][1] |= 1L << (r
- 32);
1039 mod_reg
[j
][0] |= 1L << r
;
1045 /* USED, but not modified registers and flags */
1046 if (flags
& OPERAND_ACC
)
1049 used_reg
[j
][2] |= FLAG_A0
;
1050 else if (regno
== 1)
1051 used_reg
[j
][2] |= FLAG_A1
;
1055 else if (flags
& OPERAND_FLAG
)
1056 used_reg
[j
][2] |= 1L << regno
;
1057 else if (!(flags
& OPERAND_CONTROL
))
1061 /* need to check if there are two source */
1062 /* registers, for example st2w */
1063 if (flags
& OPERAND_2REG
)
1068 for (r
= regno
; r
<= regno
+ z
; r
++)
1071 used_reg
[j
][1] |= 1L << (r
- 32);
1073 used_reg
[j
][0] |= 1L << r
;
1081 flags_set1
= op1
->op
->flags_set
;
1082 flags_set2
= op2
->op
->flags_set
;
1083 flags_used1
= op1
->op
->flags_used
;
1084 flags_used2
= op2
->op
->flags_used
;
1086 /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */
1087 if (((flags_set1
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1088 && (flags_used2
& FLAG_ADDSUBppp
) != 0)
1089 || ((flags_set2
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1090 && (flags_used1
& FLAG_ADDSUBppp
) != 0))
1093 /* Load instruction combined with half-word multiply is illegal. */
1094 if (((flags_used1
& FLAG_MEM
) != 0 && (flags_used2
& FLAG_MUL16
))
1095 || ((flags_used2
& FLAG_MEM
) != 0 && (flags_used1
& FLAG_MUL16
)))
1098 /* Specifically allow add || add by removing carry, overflow bits dependency.
1099 This is safe, even if an addc follows since the IU takes the argument in
1100 the right container, and it writes its results last.
1101 However, don't paralellize add followed by addc or sub followed by
1104 if (mod_reg
[0][2] == FLAG_CVVA
&& mod_reg
[1][2] == FLAG_CVVA
1105 && (used_reg
[0][2] & ~flag_reg
[0]) == 0
1106 && (used_reg
[1][2] & ~flag_reg
[1]) == 0
1107 && op1
->op
->unit
== EITHER
&& op2
->op
->unit
== EITHER
)
1109 mod_reg
[0][2] = mod_reg
[1][2] = 0;
1112 for (j
= 0; j
< 3; j
++)
1114 /* If the second instruction depends on the first, we obviously
1115 cannot parallelize. Note, the mod flag implies use, so
1116 check that as well. */
1117 /* If flag_explicitly_parallel is set, then the case of the
1118 second instruction using a register the first instruction
1119 modifies is assumed to be okay; we trust the human. We
1120 don't trust the human if both instructions modify the same
1121 register but we do trust the human if they modify the same
1123 if (flag_explicitly_parallel
)
1125 if ((j
< 2) && (mod_reg
[0][j
] & mod_reg
[1][j
]) != 0)
1129 if ((mod_reg
[0][j
] & (mod_reg
[1][j
] | used_reg
[1][j
])) != 0)
1137 /* This is the main entry point for the machine-dependent assembler. str points to a
1138 machine-dependent instruction. This function is supposed to emit the frags/bytes
1139 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
1140 and leaves the difficult stuff to do_assemble(). */
1142 static long long prev_insn
= -1;
1143 static struct d30v_insn prev_opcode
;
1144 static subsegT prev_subseg
;
1145 static segT prev_seg
= 0;
1151 struct d30v_insn opcode
;
1153 exec_type_enum extype
= EXEC_UNKNOWN
; /* execution type; parallel, etc */
1154 static exec_type_enum etype
= EXEC_UNKNOWN
; /* saved extype. used for multiline instructions */
1157 if ((prev_insn
!= -1) && prev_seg
1158 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1159 d30v_cleanup (false);
1161 if (d30v_current_align
< 3)
1162 d30v_align (3, NULL
, d30v_last_label
);
1163 else if (d30v_current_align
> 3)
1164 d30v_current_align
= 3;
1165 d30v_last_label
= NULL
;
1167 flag_explicitly_parallel
= 0;
1169 if (etype
== EXEC_UNKNOWN
)
1171 /* look for the special multiple instruction separators */
1172 str2
= strstr (str
, "||");
1175 extype
= EXEC_PARALLEL
;
1180 str2
= strstr (str
, "->");
1185 str2
= strstr (str
, "<-");
1187 extype
= EXEC_REVSEQ
;
1190 /* str2 points to the separator, if one */
1195 /* if two instructions are present and we already have one saved
1196 then first write it out */
1197 d30v_cleanup (false);
1199 /* Assemble first instruction and save it. */
1200 prev_insn
= do_assemble (str
, &prev_opcode
, 1, 0);
1201 if (prev_insn
== -1)
1202 as_fatal (_("Cannot assemble instruction"));
1203 if (prev_opcode
.form
->form
>= LONG
)
1204 as_fatal (_("First opcode is long. Unable to mix instructions as specified."));
1205 fixups
= fixups
->next
;
1208 prev_subseg
= now_subseg
;
1212 insn
= do_assemble (str
, &opcode
,
1213 (extype
!= EXEC_UNKNOWN
|| etype
!= EXEC_UNKNOWN
),
1214 extype
== EXEC_PARALLEL
);
1217 if (extype
!= EXEC_UNKNOWN
)
1222 as_fatal (_("Cannot assemble instruction"));
1225 if (etype
!= EXEC_UNKNOWN
)
1228 etype
= EXEC_UNKNOWN
;
1231 /* Word multiply instructions must not be followed by either a load or a
1232 16-bit multiply instruction in the next cycle. */
1233 if ( (extype
!= EXEC_REVSEQ
)
1235 && (opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1237 /* However, load and multiply should able to be combined in a parallel
1238 operation, so check for that first. */
1240 && (opcode
.op
->flags_used
& FLAG_MEM
)
1241 && opcode
.form
->form
< LONG
1242 && (extype
== EXEC_PARALLEL
|| (Optimizing
&& extype
== EXEC_UNKNOWN
))
1243 && parallel_ok (&prev_opcode
, (long)prev_insn
,
1244 &opcode
, (long)insn
, extype
)
1245 && write_2_short (&prev_opcode
, (long)prev_insn
,
1246 &opcode
, (long)insn
, extype
, fixups
) == 0)
1248 /* no instructions saved */
1254 /* Can't parallelize, flush previous instruction and emit a word of NOPS,
1255 unless the previous instruction is a NOP, in which case just flush it,
1256 as this will generate a word of NOPs for us. */
1258 if (prev_insn
!= -1 && (strcmp (prev_opcode
.op
->name
, "nop") == 0))
1259 d30v_cleanup (false);
1264 if (prev_insn
!= -1)
1265 d30v_cleanup (true);
1269 d30v_number_to_chars (f
, NOP2
, 8);
1271 if (warn_nops
== NOP_ALL
|| warn_nops
== NOP_MULTIPLY
)
1273 if (opcode
.op
->flags_used
& FLAG_MEM
)
1274 as_warn (_("word of NOPs added between word multiply and load"));
1276 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1281 extype
= EXEC_UNKNOWN
;
1284 else if ( (extype
== EXEC_REVSEQ
)
1286 && (prev_opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1288 /* Can't parallelize, flush current instruction and add a sequential NOP. */
1289 write_1_short (& opcode
, (long) insn
, fixups
->next
->next
, true);
1291 /* Make the previous instruction the current one. */
1292 extype
= EXEC_UNKNOWN
;
1295 now_subseg
= prev_subseg
;
1297 cur_mul32_p
= prev_mul32_p
;
1299 memcpy (&opcode
, &prev_opcode
, sizeof (prev_opcode
));
1302 /* If this is a long instruction, write it and any previous short instruction. */
1303 if (opcode
.form
->form
>= LONG
)
1305 if (extype
!= EXEC_UNKNOWN
)
1306 as_fatal (_("Instruction uses long version, so it cannot be mixed as specified"));
1307 d30v_cleanup (false);
1308 write_long (& opcode
, insn
, fixups
);
1311 else if ((prev_insn
!= -1) &&
1313 (& prev_opcode
, (long) prev_insn
, & opcode
, (long) insn
, extype
, fixups
) == 0))
1315 /* No instructions saved. */
1320 if (extype
!= EXEC_UNKNOWN
)
1321 as_fatal (_("Unable to mix instructions as specified"));
1323 /* Save off last instruction so it may be packed on next pass. */
1324 memcpy (&prev_opcode
, &opcode
, sizeof (prev_opcode
));
1327 prev_subseg
= now_subseg
;
1328 fixups
= fixups
->next
;
1329 prev_mul32_p
= cur_mul32_p
;
1334 /* do_assemble assembles a single instruction and returns an opcode */
1335 /* it returns -1 (an invalid opcode) on error */
1338 do_assemble (str
, opcode
, shortp
, is_parallel
)
1340 struct d30v_insn
*opcode
;
1344 unsigned char *op_start
, *save
;
1345 unsigned char *op_end
;
1347 int cmp_hack
, nlen
= 0, fsize
= (shortp
? FORCE_SHORT
: 0);
1348 expressionS myops
[6];
1351 /* Drop leading whitespace */
1355 /* find the opcode end */
1356 for (op_start
= op_end
= (unsigned char *) (str
);
1360 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1363 name
[nlen
] = tolower (op_start
[nlen
]);
1372 /* if there is an execution condition code, handle it */
1376 while ( (i
< ECC_MAX
) && strncasecmp (d30v_ecc_names
[i
], op_end
+ 1, 2))
1382 strncpy (tmp
, op_end
+ 1, 2);
1384 as_fatal (_("unknown condition code: %s"),tmp
);
1387 /* printf("condition code=%d\n",i); */
1392 opcode
->ecc
= ECC_AL
;
1395 /* CMP and CMPU change their name based on condition codes */
1396 if (!strncmp (name
, "cmp", 3))
1399 char **str
= (char **)d30v_cc_names
;
1405 for (i
=1; *str
&& strncmp (*str
, & name
[p
], 2); i
++, str
++)
1408 /* cmpu only supports some condition codes */
1414 as_fatal (_("cmpu doesn't support condition code %s"),&name
[p
]);
1421 as_fatal (_("unknown condition code: %s"),&name
[p
]);
1430 /* printf("cmp_hack=%d\n",cmp_hack); */
1432 /* need to look for .s or .l */
1433 if (name
[nlen
-2] == '.')
1435 switch (name
[nlen
-1])
1438 fsize
= FORCE_SHORT
;
1447 /* find the first opcode with the proper name */
1448 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1449 if (opcode
->op
== NULL
)
1450 as_fatal (_("unknown opcode: %s"),name
);
1452 save
= input_line_pointer
;
1453 input_line_pointer
= op_end
;
1454 while (!(opcode
->form
= find_format (opcode
->op
, myops
, fsize
, cmp_hack
)))
1457 if (strcmp (opcode
->op
->name
, name
))
1458 as_fatal (_("operands for opcode `%s' do not match any valid format"), name
);
1460 input_line_pointer
= save
;
1462 insn
= build_insn (opcode
, myops
);
1464 /* Propigate multiply status */
1467 if (is_parallel
&& prev_mul32_p
)
1471 prev_mul32_p
= cur_mul32_p
;
1472 cur_mul32_p
= (opcode
->op
->flags_used
& FLAG_MUL32
) != 0;
1476 /* Propagate left_kills_right status */
1479 prev_left_kills_right_p
= cur_left_kills_right_p
;
1481 if (opcode
->op
->flags_set
& FLAG_LKR
)
1483 cur_left_kills_right_p
= 1;
1485 if (strcmp (opcode
->op
->name
, "mvtsys") == 0)
1487 /* Left kills right for only mvtsys only for PSW/PSWH/PSWL/flags target. */
1488 if ((myops
[0].X_op
== O_register
) &&
1489 ((myops
[0].X_add_number
== OPERAND_CONTROL
) || /* psw */
1490 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+2) || /* pswh */
1491 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+1) || /* pswl */
1492 (myops
[0].X_add_number
== OPERAND_FLAG
+0) || /* f0 */
1493 (myops
[0].X_add_number
== OPERAND_FLAG
+1) || /* f1 */
1494 (myops
[0].X_add_number
== OPERAND_FLAG
+2) || /* f2 */
1495 (myops
[0].X_add_number
== OPERAND_FLAG
+3) || /* f3 */
1496 (myops
[0].X_add_number
== OPERAND_FLAG
+4) || /* f4 */
1497 (myops
[0].X_add_number
== OPERAND_FLAG
+5) || /* f5 */
1498 (myops
[0].X_add_number
== OPERAND_FLAG
+6) || /* f6 */
1499 (myops
[0].X_add_number
== OPERAND_FLAG
+7))) /* f7 */
1501 cur_left_kills_right_p
= 1;
1505 /* Other mvtsys target registers don't kill right instruction. */
1506 cur_left_kills_right_p
= 0;
1511 cur_left_kills_right_p
= 0;
1519 /* find_format() gets a pointer to an entry in the format table.
1520 It must look at all formats for an opcode and use the operands
1521 to choose the correct one. Returns NULL on error. */
1523 static struct d30v_format
*
1524 find_format (opcode
, myops
, fsize
, cmp_hack
)
1525 struct d30v_opcode
*opcode
;
1526 expressionS myops
[];
1530 int numops
, match
, index
, i
=0, j
, k
;
1531 struct d30v_format
*fm
;
1533 /* Get all the operands and save them as expressions. */
1534 numops
= get_operands (myops
, cmp_hack
);
1536 while ((index
= opcode
->format
[i
++]) != 0)
1538 if (fsize
== FORCE_SHORT
&& index
>= LONG
)
1541 if (fsize
== FORCE_LONG
&& index
< LONG
)
1544 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1546 while (fm
->form
== index
)
1549 /* Now check the operands for compatibility. */
1550 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1552 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1553 int bits
= d30v_operand_table
[fm
->operands
[j
]].bits
;
1554 int X_op
= myops
[j
].X_op
;
1555 int num
= myops
[j
].X_add_number
;
1557 if (flags
& OPERAND_SPECIAL
)
1559 else if (X_op
== O_illegal
)
1561 else if (flags
& OPERAND_REG
)
1563 if (X_op
!= O_register
1564 || ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
))
1565 || (!(flags
& OPERAND_ACC
) && (num
& OPERAND_ACC
))
1566 || ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
))
1567 || (!(flags
& OPERAND_FLAG
) && (num
& OPERAND_FLAG
))
1568 || ((flags
& OPERAND_CONTROL
)
1569 && !(num
& (OPERAND_CONTROL
| OPERAND_FLAG
))))
1574 else if (((flags
& OPERAND_MINUS
)
1575 && (X_op
!= O_absent
|| num
!= OPERAND_MINUS
))
1576 || ((flags
& OPERAND_PLUS
)
1577 && (X_op
!= O_absent
|| num
!= OPERAND_PLUS
))
1578 || ((flags
& OPERAND_ATMINUS
)
1579 && (X_op
!= O_absent
|| num
!= OPERAND_ATMINUS
))
1580 || ((flags
& OPERAND_ATPAR
)
1581 && (X_op
!= O_absent
|| num
!= OPERAND_ATPAR
))
1582 || ((flags
& OPERAND_ATSIGN
)
1583 && (X_op
!= O_absent
|| num
!= OPERAND_ATSIGN
)))
1587 else if (flags
& OPERAND_NUM
)
1589 /* A number can be a constant or symbol expression. */
1591 /* If we have found a register name, but that name also
1592 matches a symbol, then re-parse the name as an expression. */
1593 if (X_op
== O_register
1594 && symbol_find ((char *) myops
[j
].X_op_symbol
))
1596 input_line_pointer
= (char *) myops
[j
].X_op_symbol
;
1597 expression (& myops
[j
]);
1600 /* Turn an expression into a symbol for later resolution. */
1601 if (X_op
!= O_absent
&& X_op
!= O_constant
1602 && X_op
!= O_symbol
&& X_op
!= O_register
1605 symbolS
*sym
= make_expr_symbol (&myops
[j
]);
1606 myops
[j
].X_op
= X_op
= O_symbol
;
1607 myops
[j
].X_add_symbol
= sym
;
1608 myops
[j
].X_add_number
= num
= 0;
1611 if (fm
->form
>= LONG
)
1613 /* If we're testing for a LONG format, either fits. */
1614 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1617 else if (fm
->form
< LONG
1618 && ((fsize
== FORCE_SHORT
&& X_op
== O_symbol
)
1619 || (fm
->form
== SHORT_D2
&& j
== 0)))
1621 /* This is the tricky part. Will the constant or symbol
1622 fit into the space in the current format? */
1623 else if (X_op
== O_constant
)
1625 if (check_range (num
, bits
, flags
))
1628 else if (X_op
== O_symbol
1629 && S_IS_DEFINED (myops
[j
].X_add_symbol
)
1630 && S_GET_SEGMENT (myops
[j
].X_add_symbol
) == now_seg
1631 && opcode
->reloc_flag
== RELOC_PCREL
)
1633 /* If the symbol is defined, see if the value will fit
1634 into the form we're considering. */
1638 /* Calculate the current address by running through the
1639 previous frags and adding our current offset. */
1641 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1642 value
+= f
->fr_fix
+ f
->fr_offset
;
1643 value
= (S_GET_VALUE (myops
[j
].X_add_symbol
) - value
1644 - (obstack_next_free (&frchain_now
->frch_obstack
)
1645 - frag_now
->fr_literal
));
1646 if (check_range (value
, bits
, flags
))
1653 /* printf("through the loop: match=%d\n",match); */
1654 /* We're only done if the operands matched so far AND there
1655 are no more to check. */
1656 if (match
&& myops
[j
].X_op
== 0)
1658 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1660 /* printf("trying another format: i=%d\n",i); */
1665 /* if while processing a fixup, a reloc really needs to be created */
1666 /* then it is done here */
1669 tc_gen_reloc (seg
, fixp
)
1674 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1675 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1676 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1677 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1678 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1680 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1681 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1684 reloc
->addend
= fixp
->fx_addnumber
;
1689 md_estimate_size_before_relax (fragp
, seg
)
1698 md_pcrel_from_section (fixp
, sec
)
1702 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1703 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1705 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1709 md_apply_fix3 (fixp
, valuep
, seg
)
1715 unsigned long insn
, insn2
;
1718 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1723 else if (fixp
->fx_pcrel
)
1729 value
= fixp
->fx_offset
;
1730 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1732 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1733 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1736 /* We don't actually support subtracting a symbol. */
1737 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1738 _("expression too complex"));
1743 /* Fetch the instruction, insert the fully resolved operand
1744 value, and stuff the instruction back again. */
1745 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1746 insn
= bfd_getb32 ((unsigned char *) where
);
1748 switch (fixp
->fx_r_type
)
1751 /* Caused by a bad .byte directive. */
1752 as_fatal (_("line %d: unable to place address of symbol '%s' into a byte"),
1753 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1757 /* Caused by a bad .short directive. */
1758 as_fatal (_("line %d: unable to place address of symbol '%s' into a short"),
1759 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1763 /* Caused by a bad .quad directive. */
1764 as_fatal (_("line %d: unable to place address of symbol '%s' into a .quad"),
1765 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1768 case BFD_RELOC_D30V_6
:
1769 check_size (value
, 6, fixp
->fx_file
, fixp
->fx_line
);
1770 insn
|= value
& 0x3F;
1771 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1774 case BFD_RELOC_D30V_9_PCREL
:
1775 if (fixp
->fx_where
& 0x7)
1780 fixp
->fx_r_type
= BFD_RELOC_D30V_9_PCREL_R
;
1782 check_size (value
, 9, fixp
->fx_file
, fixp
->fx_line
);
1783 insn
|= ((value
>> 3) & 0x3F) << 12;
1784 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1787 case BFD_RELOC_D30V_15
:
1788 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1789 insn
|= (value
>> 3) & 0xFFF;
1790 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1793 case BFD_RELOC_D30V_15_PCREL
:
1794 if (fixp
->fx_where
& 0x7)
1799 fixp
->fx_r_type
= BFD_RELOC_D30V_15_PCREL_R
;
1801 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1802 insn
|= (value
>> 3) & 0xFFF;
1803 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1806 case BFD_RELOC_D30V_21
:
1807 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1808 insn
|= (value
>> 3) & 0x3FFFF;
1809 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1812 case BFD_RELOC_D30V_21_PCREL
:
1813 if (fixp
->fx_where
& 0x7)
1818 fixp
->fx_r_type
= BFD_RELOC_D30V_21_PCREL_R
;
1820 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1821 insn
|= (value
>> 3) & 0x3FFFF;
1822 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1825 case BFD_RELOC_D30V_32
:
1826 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1827 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1828 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1829 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1830 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1831 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1834 case BFD_RELOC_D30V_32_PCREL
:
1835 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1836 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1837 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1838 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1839 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1840 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1844 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1848 as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp
->fx_line
,fixp
->fx_r_type
);
1854 /* d30v_cleanup() is called after the assembler has finished parsing the input
1855 file or after a label is defined. Because the D30V assembler sometimes saves short
1856 instructions to see if it can package them with the next instruction, there may
1857 be a short instruction that still needs written. */
1859 d30v_cleanup (use_sequential
)
1865 if (prev_insn
!= -1)
1868 subseg
= now_subseg
;
1869 subseg_set (prev_seg
, prev_subseg
);
1870 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
, use_sequential
);
1871 subseg_set (seg
, subseg
);
1874 prev_mul32_p
= false;
1880 d30v_number_to_chars (buf
, value
, n
)
1881 char *buf
; /* Return 'nbytes' of chars here. */
1882 long long value
; /* The value of the bits. */
1883 int n
; /* Number of bytes in the output. */
1887 buf
[n
] = value
& 0xff;
1893 /* This function is called at the start of every line. */
1894 /* it checks to see if the first character is a '.' */
1895 /* which indicates the start of a pseudo-op. If it is, */
1896 /* then write out any unwritten instructions */
1901 char *c
= input_line_pointer
;
1903 while (isspace (*c
))
1907 d30v_cleanup (false);
1911 check_size (value
, bits
, file
, line
)
1924 max
= (1 << (bits
- 1)) - 1;
1927 as_bad_where (file
, line
, _("value too large to fit in %d bits"), bits
);
1932 /* d30v_frob_label() is called when after a label is recognized. */
1935 d30v_frob_label (lab
)
1938 /* Emit any pending instructions. */
1939 d30v_cleanup (false);
1941 /* Update the label's address with the current output pointer. */
1942 lab
->sy_frag
= frag_now
;
1943 S_SET_VALUE (lab
, (valueT
) frag_now_fix ());
1945 /* Record this label for future adjustment after we find out what
1946 kind of data it references, and the required alignment therewith. */
1947 d30v_last_label
= lab
;
1950 /* Hook into cons for capturing alignment changes. */
1953 d30v_cons_align (size
)
1959 while ((size
>>= 1) != 0)
1962 if (d30v_current_align
< log_size
)
1963 d30v_align (log_size
, (char *) NULL
, NULL
);
1964 else if (d30v_current_align
> log_size
)
1965 d30v_current_align
= log_size
;
1966 d30v_last_label
= NULL
;
1969 /* Called internally to handle all alignment needs. This takes care
1970 of eliding calls to frag_align if'n the cached current alignment
1971 says we've already got it, as well as taking care of the auto-aligning
1975 d30v_align (n
, pfill
, label
)
1980 /* The front end is prone to changing segments out from under us
1981 temporarily when -g is in effect. */
1982 int switched_seg_p
= (d30v_current_align_seg
!= now_seg
);
1984 /* Do not assume that if 'd30v_current_align >= n' and
1985 '! switched_seg_p' that it is safe to avoid performing
1986 this alignement request. The alignment of the current frag
1987 can be changed under our feet, for example by a .ascii
1988 directive in the source code. cf testsuite/gas/d30v/reloc.s */
1990 d30v_cleanup (false);
1995 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
1997 static char const nop
[4] = { 0x00, 0xf0, 0x00, 0x00 };
1999 /* First, make sure we're on a four-byte boundary, in case
2000 someone has been putting .byte values the text section. */
2001 if (d30v_current_align
< 2 || switched_seg_p
)
2002 frag_align (2, 0, 0);
2003 frag_align_pattern (n
, nop
, sizeof nop
, 0);
2006 frag_align (n
, 0, 0);
2009 frag_align (n
, *pfill
, 0);
2011 if (!switched_seg_p
)
2012 d30v_current_align
= n
;
2017 int label_seen
= false;
2018 struct frag
* old_frag
;
2022 assert (S_GET_SEGMENT (label
) == now_seg
);
2024 old_frag
= label
->sy_frag
;
2025 old_value
= S_GET_VALUE (label
);
2026 new_value
= (valueT
) frag_now_fix ();
2028 /* It is possible to have more than one label at a particular
2029 address, especially if debugging is enabled, so we must
2030 take care to adjust all the labels at this address in this
2031 fragment. To save time we search from the end of the symbol
2032 list, backwards, since the symbols we are interested in are
2033 almost certainly the ones that were most recently added.
2034 Also to save time we stop searching once we have seen at least
2035 one matching label, and we encounter a label that is no longer
2036 in the target fragment. Note, this search is guaranteed to
2037 find at least one match when sym == label, so no special case
2038 code is necessary. */
2039 for (sym
= symbol_lastP
; sym
!= NULL
; sym
= sym
->sy_previous
)
2041 if (sym
->sy_frag
== old_frag
&& S_GET_VALUE (sym
) == old_value
)
2044 sym
->sy_frag
= frag_now
;
2045 S_SET_VALUE (sym
, new_value
);
2047 else if (label_seen
&& sym
->sy_frag
!= old_frag
)
2052 record_alignment (now_seg
, n
);
2055 /* Handle the .align pseudo-op. This aligns to a power of two. We
2056 hook here to latch the current alignment. */
2059 s_d30v_align (ignore
)
2063 char fill
, *pfill
= NULL
;
2064 long max_alignment
= 15;
2066 align
= get_absolute_expression ();
2067 if (align
> max_alignment
)
2069 align
= max_alignment
;
2070 as_warn (_("Alignment too large: %d assumed"), align
);
2074 as_warn (_("Alignment negative: 0 assumed"));
2078 if (*input_line_pointer
== ',')
2080 input_line_pointer
++;
2081 fill
= get_absolute_expression ();
2085 d30v_last_label
= NULL
;
2086 d30v_align (align
, pfill
, NULL
);
2088 demand_empty_rest_of_line ();
2091 /* Handle the .text pseudo-op. This is like the usual one, but it
2092 clears the saved last label and resets known alignment. */
2100 d30v_last_label
= NULL
;
2101 d30v_current_align
= 0;
2102 d30v_current_align_seg
= now_seg
;
2105 /* Handle the .data pseudo-op. This is like the usual one, but it
2106 clears the saved last label and resets known alignment. */
2113 d30v_last_label
= NULL
;
2114 d30v_current_align
= 0;
2115 d30v_current_align_seg
= now_seg
;
2118 /* Handle the .section pseudo-op. This is like the usual one, but it
2119 clears the saved last label and resets known alignment. */
2122 s_d30v_section (ignore
)
2125 obj_elf_section (ignore
);
2126 d30v_last_label
= NULL
;
2127 d30v_current_align
= 0;
2128 d30v_current_align_seg
= now_seg
;