1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
3 Copyright (C) 1997, 1998 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d30v.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "OnN";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
35 #define NOP_MULTIPLY 1
37 static int warn_nops
= 0;
38 static int Optimizing
= 0;
44 typedef enum _exec_type
46 EXEC_UNKNOWN
, /* no order specified */
47 EXEC_PARALLEL
, /* done in parallel (FM=00) */
48 EXEC_SEQ
, /* sequential (FM=01) */
49 EXEC_REVSEQ
/* reverse sequential (FM=10) */
53 #define MAX_INSN_FIXUPS (5)
60 bfd_reloc_code_real_type reloc
;
63 typedef struct _fixups
66 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
70 static Fixups FixUps
[2];
71 static Fixups
*fixups
;
73 /* Whether current and previous instruction is a word multiply. */
74 static int cur_mul32_p
= 0;
75 static int prev_mul32_p
= 0;
77 /* The flag_explicitly_parallel is true iff the instruction being assembled
78 has been explicitly written as a parallel short-instruction pair by the
79 human programmer. It is used in parallel_ok() to distinguish between
80 those dangerous parallelizations attempted by the human, which are to be
81 allowed, and those attempted by the assembler, which are not. It is set
82 from md_assemble(). */
83 static int flag_explicitly_parallel
= 0;
84 static int flag_xp_state
= 0;
86 /* The known current alignment of the current section. */
87 static int d30v_current_align
;
88 static segT d30v_current_align_seg
;
90 /* The last seen label in the current section. This is used to auto-align
91 labels preceeding instructions. */
92 static symbolS
*d30v_last_label
;
95 #define NOP_LEFT ((long long)NOP << 32)
96 #define NOP_RIGHT ((long long)NOP)
97 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
100 static int reg_name_search
PARAMS ((char *name
));
101 static int register_name
PARAMS ((expressionS
*expressionP
));
102 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
103 static int postfix
PARAMS ((char *p
));
104 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
105 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
106 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
,
107 expressionS ops
[],int fsize
, int cmp_hack
));
108 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
109 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
110 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
111 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
112 struct d30v_insn
*opcode2
, long long insn2
, exec_type_enum exec_type
, Fixups
*fx
));
113 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
,
115 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
116 struct d30v_insn
*opcode2
, unsigned long insn2
,
117 exec_type_enum exec_type
));
118 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
119 static void check_size
PARAMS ((long value
, int bits
, char *file
, int line
));
120 static void d30v_align
PARAMS ((int, char *, symbolS
*));
121 static void s_d30v_align
PARAMS ((int));
122 static void s_d30v_text
PARAMS ((int));
123 static void s_d30v_data
PARAMS ((int));
124 static void s_d30v_section
PARAMS ((int));
126 struct option md_longopts
[] = {
127 {NULL
, no_argument
, NULL
, 0}
129 size_t md_longopts_size
= sizeof(md_longopts
);
132 /* The target specific pseudo-ops which we support. */
133 const pseudo_typeS md_pseudo_table
[] =
136 { "hword", cons
, 2 },
137 { "align", s_d30v_align
, 0 },
138 { "text", s_d30v_text
, 0 },
139 { "data", s_d30v_data
, 0 },
140 { "section", s_d30v_section
, 0 },
141 { "section.s", s_d30v_section
, 0 },
142 { "sect", s_d30v_section
, 0 },
143 { "sect.s", s_d30v_section
, 0 },
147 /* Opcode hash table. */
148 static struct hash_control
*d30v_hash
;
150 /* reg_name_search does a binary search of the pre_defined_registers
151 array to see if "name" is a valid regiter name. Returns the register
152 number from the array on success, or -1 on failure. */
155 reg_name_search (name
)
158 int middle
, low
, high
;
162 high
= reg_name_cnt() - 1;
166 middle
= (low
+ high
) / 2;
167 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
173 return pre_defined_registers
[middle
].value
;
179 /* register_name() checks the string at input_line_pointer
180 to see if it is a valid register name */
183 register_name (expressionP
)
184 expressionS
*expressionP
;
187 char c
, *p
= input_line_pointer
;
189 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
196 /* look to see if it's in the register table */
197 reg_number
= reg_name_search (input_line_pointer
);
200 expressionP
->X_op
= O_register
;
201 /* temporarily store a pointer to the string here */
202 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
203 expressionP
->X_add_number
= reg_number
;
204 input_line_pointer
= p
;
214 check_range (num
, bits
, flags
)
222 /* don't bother checking 32-bit values */
226 if (flags
& OPERAND_SIGNED
)
228 max
= (1 << (bits
- 1))-1;
229 min
= - (1 << (bits
- 1));
230 if (((long)num
> max
) || ((long)num
< min
))
235 max
= (1 << bits
) - 1;
237 if ((num
> max
) || (num
< min
))
245 md_show_usage (stream
)
248 fprintf(stream
, _("\nD30V options:\n\
249 -O Make adjacent short instructions parallel if possible.\n\
250 -n Warn about all NOPs inserted by the assembler.\n\
251 -N Warn about NOPs inserted after word multiplies.\n"));
255 md_parse_option (c
, arg
)
261 /* Optimize. Will attempt to parallelize operations */
266 /* Warn about all NOPS that the assembler inserts. */
271 /* Warn about the NOPS that the assembler inserts because of the
274 warn_nops
= NOP_MULTIPLY
;
284 md_undefined_symbol (name
)
290 /* Turn a string in input_line_pointer into a floating point constant of type
291 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
292 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
295 md_atof (type
, litP
, sizeP
)
301 LITTLENUM_TYPE words
[4];
315 return _("bad call to md_atof");
318 t
= atof_ieee (input_line_pointer
, type
, words
);
320 input_line_pointer
= t
;
324 for (i
= 0; i
< prec
; i
++)
326 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
333 md_convert_frag (abfd
, sec
, fragP
)
342 md_section_align (seg
, addr
)
346 int align
= bfd_get_section_alignment (stdoutput
, seg
);
347 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
354 struct d30v_opcode
*opcode
;
355 d30v_hash
= hash_new();
357 /* Insert opcode names into a hash table. */
358 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
359 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
362 FixUps
[0].next
= &FixUps
[1];
363 FixUps
[1].next
= &FixUps
[0];
365 d30v_current_align_seg
= now_seg
;
369 /* this function removes the postincrement or postdecrement
370 operator ( '+' or '-' ) from an expression */
372 static int postfix (p
)
375 while (*p
!= '-' && *p
!= '+')
377 if (*p
==0 || *p
=='\n' || *p
=='\r' || *p
==' ' || *p
==',')
397 static bfd_reloc_code_real_type
398 get_reloc (op
, rel_flag
)
399 struct d30v_operand
*op
;
405 if (op
->flags
& OPERAND_SHIFT
)
406 return BFD_RELOC_D30V_9_PCREL
;
408 return BFD_RELOC_D30V_6
;
411 if (!(op
->flags
& OPERAND_SHIFT
))
412 as_warn(_("unexpected 12-bit reloc type"));
413 if (rel_flag
== RELOC_PCREL
)
414 return BFD_RELOC_D30V_15_PCREL
;
416 return BFD_RELOC_D30V_15
;
418 if (!(op
->flags
& OPERAND_SHIFT
))
419 as_warn(_("unexpected 18-bit reloc type"));
420 if (rel_flag
== RELOC_PCREL
)
421 return BFD_RELOC_D30V_21_PCREL
;
423 return BFD_RELOC_D30V_21
;
425 if (rel_flag
== RELOC_PCREL
)
426 return BFD_RELOC_D30V_32_PCREL
;
428 return BFD_RELOC_D30V_32
;
434 /* get_operands parses a string of operands and returns
435 an array of expressions */
438 get_operands (exp
, cmp_hack
)
442 char *p
= input_line_pointer
;
448 exp
[numops
].X_op
= O_absent
;
449 exp
[numops
++].X_add_number
= cmp_hack
- 1;
454 while (*p
== ' ' || *p
== '\t' || *p
== ',')
456 if (*p
==0 || *p
=='\n' || *p
=='\r')
462 exp
[numops
].X_op
= O_absent
;
466 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
472 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
476 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
485 /* just skip the trailing paren */
490 input_line_pointer
= p
;
492 /* check to see if it might be a register name */
493 if (!register_name (&exp
[numops
]))
495 /* parse as an expression */
496 expression (&exp
[numops
]);
499 if (exp
[numops
].X_op
== O_illegal
)
500 as_bad (_("illegal operand"));
501 else if (exp
[numops
].X_op
== O_absent
)
502 as_bad (_("missing operand"));
505 p
= input_line_pointer
;
509 case -1: /* postdecrement mode */
510 exp
[numops
].X_op
= O_absent
;
511 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
513 case 1: /* postincrement mode */
514 exp
[numops
].X_op
= O_absent
;
515 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
521 exp
[numops
].X_op
= 0;
525 /* build_insn generates the instruction. It does everything */
526 /* but write the FM bits. */
529 build_insn (opcode
, opers
)
530 struct d30v_insn
*opcode
;
533 int i
, length
, bits
, shift
, flags
;
534 unsigned int number
, id
=0;
536 struct d30v_opcode
*op
= opcode
->op
;
537 struct d30v_format
*form
= opcode
->form
;
539 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
541 for (i
=0; form
->operands
[i
]; i
++)
543 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
545 /* must be a register or number */
546 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
547 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
550 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
551 if (flags
& OPERAND_SHIFT
)
554 length
= d30v_operand_table
[form
->operands
[i
]].length
;
555 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
556 if (opers
[i
].X_op
!= O_symbol
)
557 number
= opers
[i
].X_add_number
;
560 if (flags
& OPERAND_REG
)
562 /* check for mvfsys or mvtsys control registers */
563 if (flags
& OPERAND_CONTROL
&& (number
& 0x7f) > MAX_CONTROL_REG
)
566 id
= (number
& 0x7f) - MAX_CONTROL_REG
;
569 else if (number
& OPERAND_FLAG
)
571 id
= 3; /* number is a flag register */
575 else if (flags
& OPERAND_SPECIAL
)
580 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
582 /* now create a fixup */
584 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
585 as_fatal (_("too many fixups"));
587 fixups
->fix
[fixups
->fc
].reloc
=
588 get_reloc((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
589 fixups
->fix
[fixups
->fc
].size
= 4;
590 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
591 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
592 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D30V_9_PCREL
)
593 fixups
->fix
[fixups
->fc
].pcrel
= RELOC_PCREL
;
595 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
599 /* truncate to the proper number of bits */
600 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
601 as_bad(_("operand out of range: %d"),number
);
603 number
&= 0x7FFFFFFF >> (31 - bits
);
604 if (flags
& OPERAND_SHIFT
)
608 /* it's a LONG instruction */
609 insn
|= (number
>> 26); /* top 6 bits */
610 insn
<<= 32; /* shift the first word over */
611 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
612 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
615 insn
|= number
<< shift
;
621 /* write out a long form instruction */
623 write_long (opcode
, insn
, fx
)
624 struct d30v_insn
*opcode
;
629 char *f
= frag_more(8);
632 d30v_number_to_chars (f
, insn
, 8);
634 for (i
=0; i
< fx
->fc
; i
++)
636 if (fx
->fix
[i
].reloc
)
638 where
= f
- frag_now
->fr_literal
;
639 fix_new_exp (frag_now
,
651 /* write out a short form instruction by itself */
653 write_1_short (opcode
, insn
, fx
)
654 struct d30v_insn
*opcode
;
658 char *f
= frag_more(8);
661 if (warn_nops
== NOP_ALL
)
662 as_warn (_("NOP inserted"));
664 /* the other container needs to be NOP */
665 /* according to 4.3.1: for FM=00, sub-instructions performed only
666 by IU cannot be encoded in L-container. */
667 if (opcode
->op
->unit
== IU
)
668 insn
|= FM00
| NOP_LEFT
; /* right container */
670 insn
= FM00
| (insn
<< 32) | NOP_RIGHT
; /* left container */
672 d30v_number_to_chars (f
, insn
, 8);
674 for (i
=0; i
< fx
->fc
; i
++)
676 if (fx
->fix
[i
].reloc
)
678 where
= f
- frag_now
->fr_literal
;
679 fix_new_exp (frag_now
,
690 /* write out a short form instruction if possible */
691 /* return number of instructions not written out */
693 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
694 struct d30v_insn
*opcode1
, *opcode2
;
695 long long insn1
, insn2
;
696 exec_type_enum exec_type
;
699 long long insn
= NOP2
;
703 if(exec_type
!= EXEC_PARALLEL
&&
704 ((opcode1
->op
->flags_used
& (FLAG_JSR
| FLAG_DELAY
)) == FLAG_JSR
))
706 /* subroutines must be called from 32-bit boundaries */
707 /* so the return address will be correct */
708 write_1_short (opcode1
, insn1
, fx
->next
);
714 case EXEC_UNKNOWN
: /* order not specified */
715 if (Optimizing
&& parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
718 exec_type
= EXEC_PARALLEL
;
719 if (opcode1
->op
->unit
== IU
)
720 insn
= FM00
| (insn2
<< 32) | insn1
;
721 else if (opcode2
->op
->unit
== MU
)
722 insn
= FM00
| (insn2
<< 32) | insn1
;
725 insn
= FM00
| (insn1
<< 32) | insn2
;
729 else if (opcode1
->op
->unit
== IU
)
731 /* reverse sequential */
732 insn
= FM10
| (insn2
<< 32) | insn1
;
733 exec_type
= EXEC_REVSEQ
;
738 insn
= FM01
| (insn1
<< 32) | insn2
;
740 exec_type
= EXEC_SEQ
;
744 case EXEC_PARALLEL
: /* parallel */
745 flag_explicitly_parallel
= flag_xp_state
;
746 if (! parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
747 as_fatal (_("Instructions may not be executed in parallel"));
748 else if (opcode1
->op
->unit
== IU
)
750 if (opcode2
->op
->unit
== IU
)
751 as_fatal (_("Two IU instructions may not be executed in parallel"));
752 as_warn (_("Swapping instruction order"));
753 insn
= FM00
| (insn2
<< 32) | insn1
;
755 else if (opcode2
->op
->unit
== MU
)
757 if (opcode1
->op
->unit
== MU
)
758 as_fatal (_("Two MU instructions may not be executed in parallel"));
759 as_warn (_("Swapping instruction order"));
760 insn
= FM00
| (insn2
<< 32) | insn1
;
764 insn
= FM00
| (insn1
<< 32) | insn2
;
767 flag_explicitly_parallel
= 0;
770 case EXEC_SEQ
: /* sequential */
771 if (opcode1
->op
->unit
== IU
)
772 as_fatal (_("IU instruction may not be in the left container"));
773 insn
= FM01
| (insn1
<< 32) | insn2
;
777 case EXEC_REVSEQ
: /* reverse sequential */
778 if (opcode2
->op
->unit
== MU
)
779 as_fatal (_("MU instruction may not be in the right container"));
780 insn
= FM10
| (insn1
<< 32) | insn2
;
785 as_fatal(_("unknown execution type passed to write_2_short()"));
788 /* printf("writing out %llx\n",insn); */
790 d30v_number_to_chars (f
, insn
, 8);
792 /* If the previous instruction was a 32-bit multiply but it is put into a
793 parallel container, mark the current instruction as being a 32-bit
795 if (prev_mul32_p
&& exec_type
== EXEC_PARALLEL
)
800 for (i
=0; i
< fx
->fc
; i
++)
802 if (fx
->fix
[i
].reloc
)
804 where
= (f
- frag_now
->fr_literal
) + 4*j
;
806 fix_new_exp (frag_now
,
821 /* Check 2 instructions and determine if they can be safely */
822 /* executed in parallel. Returns 1 if they can be. */
824 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
825 struct d30v_insn
*op1
, *op2
;
826 unsigned long insn1
, insn2
;
827 exec_type_enum exec_type
;
829 int i
, j
, shift
, regno
, bits
, ecc
;
830 unsigned long flags
, mask
, flags_set1
, flags_set2
, flags_used1
, flags_used2
;
831 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3], flag_reg
[2];
832 struct d30v_format
*f
;
833 struct d30v_opcode
*op
;
835 /* section 4.3: both instructions must not be IU or MU only */
836 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
837 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
840 /* first instruction must not be a jump to safely optimize, unless this
841 is an explicit parallel operation. */
842 if (exec_type
!= EXEC_PARALLEL
843 && (op1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)))
846 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
847 then it is safe to allow the two to be done as parallel ops, since only
848 one will ever be executed at a time. */
849 if ((op1
->ecc
== ECC_TX
&& op2
->ecc
== ECC_FX
)
850 || (op1
->ecc
== ECC_FX
&& op2
->ecc
== ECC_TX
)
851 || (op1
->ecc
== ECC_XT
&& op2
->ecc
== ECC_XF
)
852 || (op1
->ecc
== ECC_XF
&& op2
->ecc
== ECC_XT
))
857 [2] a0, a1, flag registers */
859 for (j
= 0; j
< 2; j
++)
876 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
877 mod_reg
[j
][2] = (op
->flags_set
& FLAG_ALL
);
878 used_reg
[j
][0] = used_reg
[j
][1] = 0;
879 used_reg
[j
][2] = (op
->flags_used
& FLAG_ALL
);
881 /* BSR/JSR always sets R62 */
882 if (op
->flags_used
& FLAG_JSR
)
883 mod_reg
[j
][1] = (1L << (62-32));
885 /* conditional execution affects the flags_used */
890 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_0
;
895 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_1
;
900 used_reg
[j
][2] |= flag_reg
[j
] = (FLAG_0
| FLAG_1
);
904 for (i
= 0; f
->operands
[i
]; i
++)
906 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
907 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
908 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
912 mask
= 0x7FFFFFFF >> (31 - bits
);
914 if ((flags
& OPERAND_PLUS
) || (flags
& OPERAND_MINUS
))
916 /* this is a post-increment or post-decrement */
917 /* the previous register needs to be marked as modified */
919 shift
= 12 - d30v_operand_table
[f
->operands
[i
-1]].position
;
920 regno
= (ins
>> shift
) & 0x3f;
922 mod_reg
[j
][1] |= 1L << (regno
- 32);
924 mod_reg
[j
][0] |= 1L << regno
;
926 else if (flags
& OPERAND_REG
)
928 regno
= (ins
>> shift
) & mask
;
929 /* the memory write functions don't have a destination register */
930 if ((flags
& OPERAND_DEST
) && !(op
->flags_set
& FLAG_MEM
))
932 /* MODIFIED registers and flags */
933 if (flags
& OPERAND_ACC
)
936 mod_reg
[j
][2] |= FLAG_A0
;
938 mod_reg
[j
][2] |= FLAG_A1
;
942 else if (flags
& OPERAND_FLAG
)
943 mod_reg
[j
][2] |= 1L << regno
;
944 else if (!(flags
& OPERAND_CONTROL
))
948 /* need to check if there are two destination */
949 /* registers, for example ld2w */
950 if (flags
& OPERAND_2REG
)
955 for (r
= regno
; r
<= regno
+ z
; r
++)
958 mod_reg
[j
][1] |= 1L << (r
- 32);
960 mod_reg
[j
][0] |= 1L << r
;
966 /* USED, but not modified registers and flags */
967 if (flags
& OPERAND_ACC
)
970 used_reg
[j
][2] |= FLAG_A0
;
972 used_reg
[j
][2] |= FLAG_A1
;
976 else if (flags
& OPERAND_FLAG
)
977 used_reg
[j
][2] |= 1L << regno
;
978 else if (!(flags
& OPERAND_CONTROL
))
982 /* need to check if there are two source */
983 /* registers, for example st2w */
984 if (flags
& OPERAND_2REG
)
989 for (r
= regno
; r
<= regno
+ z
; r
++)
992 used_reg
[j
][1] |= 1L << (r
- 32);
994 used_reg
[j
][0] |= 1L << r
;
1002 flags_set1
= op1
->op
->flags_set
;
1003 flags_set2
= op2
->op
->flags_set
;
1004 flags_used1
= op1
->op
->flags_used
;
1005 flags_used2
= op2
->op
->flags_used
;
1007 /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */
1008 if (((flags_set1
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1009 && (flags_used2
& FLAG_ADDSUBppp
) != 0)
1010 || ((flags_set2
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1011 && (flags_used1
& FLAG_ADDSUBppp
) != 0))
1014 /* Load instruction combined with half-word multiply is illegal. */
1015 if (((flags_used1
& FLAG_MEM
) != 0 && (flags_used2
& FLAG_MUL16
))
1016 || ((flags_used2
& FLAG_MEM
) != 0 && (flags_used1
& FLAG_MUL16
)))
1019 /* Specifically allow add || add by removing carry, overflow bits dependency.
1020 This is safe, even if an addc follows since the IU takes the argument in
1021 the right container, and it writes its results last.
1022 However, don't paralellize add followed by addc or sub followed by
1025 if (mod_reg
[0][2] == FLAG_CVVA
&& mod_reg
[1][2] == FLAG_CVVA
1026 && (used_reg
[0][2] & ~flag_reg
[0]) == 0
1027 && (used_reg
[1][2] & ~flag_reg
[1]) == 0
1028 && op1
->op
->unit
== EITHER
&& op2
->op
->unit
== EITHER
)
1030 mod_reg
[0][2] = mod_reg
[1][2] = 0;
1033 for(j
= 0; j
< 3; j
++)
1035 /* If the second instruction depends on the first, we obviously
1036 cannot parallelize. Note, the mod flag implies use, so
1037 check that as well. */
1038 /* If flag_explicitly_parallel is set, then the case of the
1039 second instruction using a register the first instruction
1040 modifies is assumed to be okay; we trust the human. We
1041 don't trust the human if both instructions modify the same
1042 register but we do trust the human if they modify the same
1044 if (flag_explicitly_parallel
)
1046 if ((j
< 2) && (mod_reg
[0][j
] & mod_reg
[1][j
]) != 0)
1050 if ((mod_reg
[0][j
] & (mod_reg
[1][j
] | used_reg
[1][j
])) != 0)
1059 /* This is the main entry point for the machine-dependent assembler. str points to a
1060 machine-dependent instruction. This function is supposed to emit the frags/bytes
1061 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
1062 and leaves the difficult stuff to do_assemble(). */
1064 static long long prev_insn
= -1;
1065 static struct d30v_insn prev_opcode
;
1066 static subsegT prev_subseg
;
1067 static segT prev_seg
= 0;
1073 struct d30v_insn opcode
;
1075 exec_type_enum extype
= EXEC_UNKNOWN
; /* execution type; parallel, etc */
1076 static exec_type_enum etype
= EXEC_UNKNOWN
; /* saved extype. used for multiline instructions */
1079 if ((prev_insn
!= -1) && prev_seg
1080 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1083 if (d30v_current_align
< 3)
1084 d30v_align (3, NULL
, d30v_last_label
);
1085 else if (d30v_current_align
> 3)
1086 d30v_current_align
= 3;
1087 d30v_last_label
= NULL
;
1089 flag_explicitly_parallel
= 0;
1091 if (etype
== EXEC_UNKNOWN
)
1093 /* look for the special multiple instruction separators */
1094 str2
= strstr (str
, "||");
1097 extype
= EXEC_PARALLEL
;
1102 str2
= strstr (str
, "->");
1107 str2
= strstr (str
, "<-");
1109 extype
= EXEC_REVSEQ
;
1112 /* str2 points to the separator, if one */
1117 /* if two instructions are present and we already have one saved
1118 then first write it out */
1121 /* assemble first instruction and save it */
1122 prev_insn
= do_assemble (str
, &prev_opcode
, 1);
1123 if (prev_insn
== -1)
1124 as_fatal (_("Cannot assemble instruction"));
1125 if (prev_opcode
.form
->form
>= LONG
)
1126 as_fatal (_("First opcode is long. Unable to mix instructions as specified."));
1127 fixups
= fixups
->next
;
1132 insn
= do_assemble (str
, &opcode
,
1133 (extype
!= EXEC_UNKNOWN
|| etype
!= EXEC_UNKNOWN
));
1136 if (extype
!= EXEC_UNKNOWN
)
1141 as_fatal (_("Cannot assemble instruction"));
1144 if (etype
!= EXEC_UNKNOWN
)
1147 etype
= EXEC_UNKNOWN
;
1150 /* Word multiply instructions must not be followed by either a load or a
1151 16-bit multiply instruction in the next cycle. */
1152 if (prev_mul32_p
&& (opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1154 /* However, load and multiply should able to be combined in a parallel
1155 operation, so check for that first. */
1158 && (opcode
.op
->flags_used
& FLAG_MEM
)
1159 && opcode
.form
->form
< LONG
1160 && (extype
== EXEC_PARALLEL
|| (Optimizing
&& extype
== EXEC_UNKNOWN
))
1161 && parallel_ok (&prev_opcode
, (long)prev_insn
,
1162 &opcode
, (long)insn
, extype
)
1163 && write_2_short (&prev_opcode
, (long)prev_insn
,
1164 &opcode
, (long)insn
, extype
, fixups
) == 0)
1166 /* no instructions saved */
1171 /* Can't parallelize, flush current instruction and emit a word of NOPS */
1178 d30v_number_to_chars (f
, NOP2
, 8);
1179 if (warn_nops
== NOP_ALL
|| warn_nops
== NOP_MULTIPLY
)
1181 if (opcode
.op
->flags_used
& FLAG_MEM
)
1182 as_warn (_("word of NOPs added between word multiply and load"));
1184 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1189 /* if this is a long instruction, write it and any previous short instruction */
1190 if (opcode
.form
->form
>= LONG
)
1193 as_fatal(_("Unable to mix instructions as specified"));
1195 write_long (&opcode
, insn
, fixups
);
1200 if ((prev_insn
!= -1) &&
1201 (write_2_short (&prev_opcode
, (long)prev_insn
, &opcode
, (long)insn
, extype
, fixups
) == 0))
1203 /* no instructions saved */
1210 as_fatal(_("Unable to mix instructions as specified"));
1211 /* save off last instruction so it may be packed on next pass */
1212 memcpy(&prev_opcode
, &opcode
, sizeof(prev_opcode
));
1215 prev_subseg
= now_subseg
;
1216 fixups
= fixups
->next
;
1221 /* do_assemble assembles a single instruction and returns an opcode */
1222 /* it returns -1 (an invalid opcode) on error */
1225 do_assemble (str
, opcode
, shortp
)
1227 struct d30v_insn
*opcode
;
1230 unsigned char *op_start
, *save
;
1231 unsigned char *op_end
;
1233 int cmp_hack
, nlen
= 0, fsize
= (shortp
? FORCE_SHORT
: 0);
1234 expressionS myops
[6];
1237 /* Drop leading whitespace */
1241 /* find the opcode end */
1242 for (op_start
= op_end
= (unsigned char *) (str
);
1246 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1249 name
[nlen
] = tolower(op_start
[nlen
]);
1258 /* if there is an execution condition code, handle it */
1262 while ( (i
< ECC_MAX
) && strncasecmp(d30v_ecc_names
[i
],op_end
+1,2))
1268 strncpy(tmp
,op_end
+1,2);
1270 as_fatal (_("unknown condition code: %s"),tmp
);
1273 /* printf("condition code=%d\n",i); */
1278 opcode
->ecc
= ECC_AL
;
1281 /* CMP and CMPU change their name based on condition codes */
1282 if (!strncmp(name
,"cmp",3))
1285 char **str
= (char **)d30v_cc_names
;
1291 for(i
=1; *str
&& strncmp(*str
,&name
[p
],2); i
++, str
++)
1294 /* cmpu only supports some condition codes */
1300 as_fatal (_("cmpu doesn't support condition code %s"),&name
[p
]);
1307 as_fatal (_("unknown condition code: %s"),&name
[p
]);
1316 /* printf("cmp_hack=%d\n",cmp_hack); */
1318 /* need to look for .s or .l */
1319 if (name
[nlen
-2] == '.')
1321 switch (name
[nlen
-1])
1324 fsize
= FORCE_SHORT
;
1333 /* find the first opcode with the proper name */
1334 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1335 if (opcode
->op
== NULL
)
1336 as_fatal (_("unknown opcode: %s"),name
);
1338 save
= input_line_pointer
;
1339 input_line_pointer
= op_end
;
1340 while (!(opcode
->form
= find_format (opcode
->op
, myops
, fsize
, cmp_hack
)))
1343 if (strcmp(opcode
->op
->name
,name
))
1344 as_fatal (_("operands for opcode `%s' do not match any valid format"), name
);
1346 input_line_pointer
= save
;
1348 insn
= build_insn (opcode
, myops
);
1350 /* Propigate multiply status */
1353 prev_mul32_p
= cur_mul32_p
;
1354 cur_mul32_p
= (opcode
->op
->flags_used
& FLAG_MUL32
) != 0;
1361 /* find_format() gets a pointer to an entry in the format table.
1362 It must look at all formats for an opcode and use the operands
1363 to choose the correct one. Returns NULL on error. */
1365 static struct d30v_format
*
1366 find_format (opcode
, myops
, fsize
, cmp_hack
)
1367 struct d30v_opcode
*opcode
;
1368 expressionS myops
[];
1372 int numops
, match
, index
, i
=0, j
, k
;
1373 struct d30v_format
*fm
;
1375 /* Get all the operands and save them as expressions. */
1376 numops
= get_operands (myops
, cmp_hack
);
1378 while ((index
= opcode
->format
[i
++]) != 0)
1380 if (fsize
== FORCE_SHORT
&& index
>= LONG
)
1383 if (fsize
== FORCE_LONG
&& index
< LONG
)
1386 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1388 while (fm
->form
== index
)
1391 /* Now check the operands for compatibility. */
1392 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1394 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1395 int bits
= d30v_operand_table
[fm
->operands
[j
]].bits
;
1396 int X_op
= myops
[j
].X_op
;
1397 int num
= myops
[j
].X_add_number
;
1399 if (flags
& OPERAND_SPECIAL
)
1401 else if (X_op
== O_illegal
)
1403 else if (flags
& OPERAND_REG
)
1405 if (X_op
!= O_register
1406 || ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
))
1407 || ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
))
1408 || ((flags
& OPERAND_CONTROL
)
1409 && !(num
& (OPERAND_CONTROL
| OPERAND_FLAG
))))
1414 else if (((flags
& OPERAND_MINUS
)
1415 && (X_op
!= O_absent
|| num
!= OPERAND_MINUS
))
1416 || ((flags
& OPERAND_PLUS
)
1417 && (X_op
!= O_absent
|| num
!= OPERAND_PLUS
))
1418 || ((flags
& OPERAND_ATMINUS
)
1419 && (X_op
!= O_absent
|| num
!= OPERAND_ATMINUS
))
1420 || ((flags
& OPERAND_ATPAR
)
1421 && (X_op
!= O_absent
|| num
!= OPERAND_ATPAR
))
1422 || ((flags
& OPERAND_ATSIGN
)
1423 && (X_op
!= O_absent
|| num
!= OPERAND_ATSIGN
)))
1427 else if (flags
& OPERAND_NUM
)
1429 /* A number can be a constant or symbol expression. */
1431 /* Turn an expression into a symbol for later resolution. */
1432 if (X_op
!= O_absent
&& X_op
!= O_constant
1433 && X_op
!= O_symbol
&& X_op
!= O_register
1436 symbolS
*sym
= make_expr_symbol (&myops
[j
]);
1437 myops
[j
].X_op
= X_op
= O_symbol
;
1438 myops
[j
].X_add_symbol
= sym
;
1439 myops
[j
].X_add_number
= num
= 0;
1442 if (fm
->form
>= LONG
)
1444 /* If we're testing for a LONG format, either fits. */
1445 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1448 else if (fm
->form
< LONG
1449 && ((fsize
== FORCE_SHORT
&& X_op
== O_symbol
)
1450 || (fm
->form
== SHORT_D2
&& j
== 0)))
1452 /* This is the tricky part. Will the constant or symbol
1453 fit into the space in the current format? */
1454 else if (X_op
== O_constant
)
1456 if (check_range (num
, bits
, flags
))
1459 else if (X_op
== O_symbol
1460 && S_IS_DEFINED(myops
[j
].X_add_symbol
)
1461 && S_GET_SEGMENT(myops
[j
].X_add_symbol
) == now_seg
1462 && opcode
->reloc_flag
== RELOC_PCREL
)
1464 /* If the symbol is defined, see if the value will fit
1465 into the form we're considering. */
1469 /* Calculate the current address by running through the
1470 previous frags and adding our current offset. */
1472 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1473 value
+= f
->fr_fix
+ f
->fr_offset
;
1474 value
= (S_GET_VALUE(myops
[j
].X_add_symbol
) - value
1475 - (obstack_next_free(&frchain_now
->frch_obstack
)
1476 - frag_now
->fr_literal
));
1477 if (check_range (value
, bits
, flags
))
1484 /* printf("through the loop: match=%d\n",match); */
1485 /* We're only done if the operands matched so far AND there
1486 are no more to check. */
1487 if (match
&& myops
[j
].X_op
== 0)
1489 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1491 /* printf("trying another format: i=%d\n",i); */
1496 /* if while processing a fixup, a reloc really needs to be created */
1497 /* then it is done here */
1500 tc_gen_reloc (seg
, fixp
)
1505 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1506 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1507 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1508 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1509 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1511 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1512 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1515 reloc
->addend
= fixp
->fx_addnumber
;
1520 md_estimate_size_before_relax (fragp
, seg
)
1529 md_pcrel_from_section (fixp
, sec
)
1533 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1534 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1536 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1540 md_apply_fix3 (fixp
, valuep
, seg
)
1546 unsigned long insn
, insn2
;
1549 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1554 else if (fixp
->fx_pcrel
)
1560 value
= fixp
->fx_offset
;
1561 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1563 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1564 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1567 /* We don't actually support subtracting a symbol. */
1568 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1569 _("expression too complex"));
1574 /* Fetch the instruction, insert the fully resolved operand
1575 value, and stuff the instruction back again. */
1576 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1577 insn
= bfd_getb32 ((unsigned char *) where
);
1579 switch (fixp
->fx_r_type
)
1581 case BFD_RELOC_D30V_6
:
1582 check_size (value
, 6, fixp
->fx_file
, fixp
->fx_line
);
1583 insn
|= value
& 0x3F;
1584 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1587 case BFD_RELOC_D30V_9_PCREL
:
1588 if (fixp
->fx_where
& 0x7)
1593 fixp
->fx_r_type
= BFD_RELOC_D30V_9_PCREL_R
;
1595 check_size (value
, 9, fixp
->fx_file
, fixp
->fx_line
);
1596 insn
|= ((value
>> 3) & 0x3F) << 12;
1597 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1600 case BFD_RELOC_D30V_15
:
1601 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1602 insn
|= (value
>> 3) & 0xFFF;
1603 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1606 case BFD_RELOC_D30V_15_PCREL
:
1607 if (fixp
->fx_where
& 0x7)
1612 fixp
->fx_r_type
= BFD_RELOC_D30V_15_PCREL_R
;
1614 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1615 insn
|= (value
>> 3) & 0xFFF;
1616 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1619 case BFD_RELOC_D30V_21
:
1620 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1621 insn
|= (value
>> 3) & 0x3FFFF;
1622 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1625 case BFD_RELOC_D30V_21_PCREL
:
1626 if (fixp
->fx_where
& 0x7)
1631 fixp
->fx_r_type
= BFD_RELOC_D30V_21_PCREL_R
;
1633 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1634 insn
|= (value
>> 3) & 0x3FFFF;
1635 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1638 case BFD_RELOC_D30V_32
:
1639 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1640 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1641 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1642 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1643 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1644 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1647 case BFD_RELOC_D30V_32_PCREL
:
1648 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1649 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1650 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1651 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1652 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1653 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1657 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1661 as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp
->fx_line
,fixp
->fx_r_type
);
1667 /* d30v_cleanup() is called after the assembler has finished parsing the input
1668 file or after a label is defined. Because the D30V assembler sometimes saves short
1669 instructions to see if it can package them with the next instruction, there may
1670 be a short instruction that still needs written. */
1677 if (prev_insn
!= -1)
1680 subseg
= now_subseg
;
1681 subseg_set (prev_seg
, prev_subseg
);
1682 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
);
1683 subseg_set (seg
, subseg
);
1690 d30v_number_to_chars (buf
, value
, n
)
1691 char *buf
; /* Return 'nbytes' of chars here. */
1692 long long value
; /* The value of the bits. */
1693 int n
; /* Number of bytes in the output. */
1697 buf
[n
] = value
& 0xff;
1703 /* This function is called at the start of every line. */
1704 /* it checks to see if the first character is a '.' */
1705 /* which indicates the start of a pseudo-op. If it is, */
1706 /* then write out any unwritten instructions */
1711 char *c
= input_line_pointer
;
1721 check_size (value
, bits
, file
, line
)
1734 max
= (1 << (bits
- 1)) - 1;
1737 as_bad_where (file
, line
, _("value too large to fit in %d bits"), bits
);
1742 /* d30v_frob_label() is called when after a label is recognized. */
1745 d30v_frob_label (lab
)
1748 /* Emit any pending instructions. */
1751 /* Update the label's address with the current output pointer. */
1752 lab
->sy_frag
= frag_now
;
1753 S_SET_VALUE (lab
, (valueT
) frag_now_fix ());
1755 /* Record this label for future adjustment after we find out what
1756 kind of data it references, and the required alignment therewith. */
1757 d30v_last_label
= lab
;
1760 /* Hook into cons for capturing alignment changes. */
1763 d30v_cons_align (size
)
1769 while ((size
>>= 1) != 0)
1772 if (d30v_current_align
< log_size
)
1773 d30v_align (log_size
, (char *) NULL
, NULL
);
1774 else if (d30v_current_align
> log_size
)
1775 d30v_current_align
= log_size
;
1776 d30v_last_label
= NULL
;
1779 /* Called internally to handle all alignment needs. This takes care
1780 of eliding calls to frag_align if'n the cached current alignment
1781 says we've already got it, as well as taking care of the auto-aligning
1785 d30v_align (n
, pfill
, label
)
1790 /* The front end is prone to changing segments out from under us
1791 temporarily when -g is in effect. */
1792 int switched_seg_p
= (d30v_current_align_seg
!= now_seg
);
1794 if (d30v_current_align
>= n
&& !switched_seg_p
)
1802 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
1804 static char const nop
[4] = { 0x00, 0xf0, 0x00, 0x00 };
1806 /* First, make sure we're on a four-byte boundary, in case
1807 someone has been putting .byte values the text section. */
1808 if (d30v_current_align
< 2 || switched_seg_p
)
1809 frag_align (2, 0, 0);
1810 frag_align_pattern (n
, nop
, sizeof nop
, 0);
1813 frag_align (n
, 0, 0);
1816 frag_align (n
, *pfill
, 0);
1818 if (!switched_seg_p
)
1819 d30v_current_align
= n
;
1823 assert (S_GET_SEGMENT (label
) == now_seg
);
1824 label
->sy_frag
= frag_now
;
1825 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
1828 record_alignment(now_seg
, n
);
1831 /* Handle the .align pseudo-op. This aligns to a power of two. We
1832 hook here to latch the current alignment. */
1835 s_d30v_align (ignore
)
1839 char fill
, *pfill
= NULL
;
1840 long max_alignment
= 15;
1842 align
= get_absolute_expression ();
1843 if (align
> max_alignment
)
1845 align
= max_alignment
;
1846 as_warn (_("Alignment too large: %d assumed"), align
);
1850 as_warn (_("Alignment negative: 0 assumed"));
1854 if (*input_line_pointer
== ',')
1856 input_line_pointer
++;
1857 fill
= get_absolute_expression ();
1861 d30v_last_label
= NULL
;
1862 d30v_align (align
, pfill
, NULL
);
1864 demand_empty_rest_of_line ();
1867 /* Handle the .text pseudo-op. This is like the usual one, but it
1868 clears the saved last label and resets known alignment. */
1876 d30v_last_label
= NULL
;
1877 d30v_current_align
= 0;
1878 d30v_current_align_seg
= now_seg
;
1881 /* Handle the .data pseudo-op. This is like the usual one, but it
1882 clears the saved last label and resets known alignment. */
1889 d30v_last_label
= NULL
;
1890 d30v_current_align
= 0;
1891 d30v_current_align_seg
= now_seg
;
1894 /* Handle the .section pseudo-op. This is like the usual one, but it
1895 clears the saved last label and resets known alignment. */
1898 s_d30v_section (ignore
)
1901 obj_elf_section (ignore
);
1902 d30v_last_label
= NULL
;
1903 d30v_current_align
= 0;
1904 d30v_current_align_seg
= now_seg
;