1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
2 Copyright (C) 1997, 1998, 1999, 2000 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
25 #include "opcode/d30v.h"
27 const char comment_chars
[] = ";";
28 const char line_comment_chars
[] = "#";
29 const char line_separator_chars
[] = "";
30 const char *md_shortopts
= "OnNcC";
31 const char EXP_CHARS
[] = "eE";
32 const char FLT_CHARS
[] = "dD";
42 #define NOP_MULTIPLY 1
44 static int warn_nops
= 0;
45 static int Optimizing
= 0;
46 static int warn_register_name_conflicts
= 1;
52 typedef enum _exec_type
54 EXEC_UNKNOWN
, /* no order specified */
55 EXEC_PARALLEL
, /* done in parallel (FM=00) */
56 EXEC_SEQ
, /* sequential (FM=01) */
57 EXEC_REVSEQ
/* reverse sequential (FM=10) */
61 #define MAX_INSN_FIXUPS (5)
68 bfd_reloc_code_real_type reloc
;
71 typedef struct _fixups
74 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
78 static Fixups FixUps
[2];
79 static Fixups
*fixups
;
81 /* Whether current and previous instruction are word multiply insns. */
82 static int cur_mul32_p
= 0;
83 static int prev_mul32_p
= 0;
85 /* The flag_explicitly_parallel is true iff the instruction being assembled
86 has been explicitly written as a parallel short-instruction pair by the
87 human programmer. It is used in parallel_ok() to distinguish between
88 those dangerous parallelizations attempted by the human, which are to be
89 allowed, and those attempted by the assembler, which are not. It is set
90 from md_assemble(). */
91 static int flag_explicitly_parallel
= 0;
92 static int flag_xp_state
= 0;
94 /* Whether current and previous left sub-instruction disables
95 execution of right sub-instruction. */
96 static int cur_left_kills_right_p
= 0;
97 static int prev_left_kills_right_p
= 0;
99 /* The known current alignment of the current section. */
100 static int d30v_current_align
;
101 static segT d30v_current_align_seg
;
103 /* The last seen label in the current section. This is used to auto-align
104 labels preceeding instructions. */
105 static symbolS
*d30v_last_label
;
108 #define NOP_LEFT ((long long) NOP << 32)
109 #define NOP_RIGHT ((long long) NOP)
110 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
112 /* local functions */
113 static int reg_name_search
PARAMS ((char *name
));
114 static int register_name
PARAMS ((expressionS
*expressionP
));
115 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
116 static int postfix
PARAMS ((char *p
));
117 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
118 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
119 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
,
120 expressionS ops
[],int fsize
, int cmp_hack
));
121 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
122 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
123 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
,
124 Fixups
*fx
, int use_sequential
));
125 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
126 struct d30v_insn
*opcode2
, long long insn2
, exec_type_enum exec_type
, Fixups
*fx
));
127 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
,
128 int shortp
, int is_parallel
));
129 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
130 struct d30v_insn
*opcode2
, unsigned long insn2
,
131 exec_type_enum exec_type
));
132 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
133 static void check_size
PARAMS ((long value
, int bits
, char *file
, int line
));
134 static void d30v_align
PARAMS ((int, char *, symbolS
*));
135 static void s_d30v_align
PARAMS ((int));
136 static void s_d30v_text
PARAMS ((int));
137 static void s_d30v_data
PARAMS ((int));
138 static void s_d30v_section
PARAMS ((int));
140 struct option md_longopts
[] = {
141 {NULL
, no_argument
, NULL
, 0}
143 size_t md_longopts_size
= sizeof(md_longopts
);
146 /* The target specific pseudo-ops which we support. */
147 const pseudo_typeS md_pseudo_table
[] =
150 { "hword", cons
, 2 },
151 { "align", s_d30v_align
, 0 },
152 { "text", s_d30v_text
, 0 },
153 { "data", s_d30v_data
, 0 },
154 { "section", s_d30v_section
, 0 },
155 { "section.s", s_d30v_section
, 0 },
156 { "sect", s_d30v_section
, 0 },
157 { "sect.s", s_d30v_section
, 0 },
161 /* Opcode hash table. */
162 static struct hash_control
*d30v_hash
;
164 /* reg_name_search does a binary search of the pre_defined_registers
165 array to see if "name" is a valid regiter name. Returns the register
166 number from the array on success, or -1 on failure. */
169 reg_name_search (name
)
172 int middle
, low
, high
;
176 high
= reg_name_cnt () - 1;
180 middle
= (low
+ high
) / 2;
181 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
188 if (symbol_find (name
) != NULL
)
190 if (warn_register_name_conflicts
)
191 as_warn (_("Register name %s conflicts with symbol of the same name"),
195 return pre_defined_registers
[middle
].value
;
203 /* register_name() checks the string at input_line_pointer
204 to see if it is a valid register name. */
207 register_name (expressionP
)
208 expressionS
*expressionP
;
211 char c
, *p
= input_line_pointer
;
213 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
220 /* look to see if it's in the register table */
221 reg_number
= reg_name_search (input_line_pointer
);
224 expressionP
->X_op
= O_register
;
225 /* temporarily store a pointer to the string here */
226 expressionP
->X_op_symbol
= (symbolS
*)input_line_pointer
;
227 expressionP
->X_add_number
= reg_number
;
228 input_line_pointer
= p
;
238 check_range (num
, bits
, flags
)
245 /* Don't bother checking 32-bit values. */
248 if (sizeof(unsigned long) * CHAR_BIT
== 32)
251 /* We don't record signed or unsigned for 32-bit quantities.
253 min
= -((unsigned long)1 << (bits
- 1));
254 max
= ((unsigned long)1 << bits
) - 1;
255 return (long)num
< min
|| (long)num
> max
;
258 if (flags
& OPERAND_SHIFT
)
260 /* We know that all shifts are right by three bits.... */
262 if (flags
& OPERAND_SIGNED
)
263 num
= (unsigned long) ( (long) num
>= 0)
264 ? ( ((long) num
) >> 3 )
265 : ( (num
>> 3) | ~(~(unsigned long)0 >> 3) );
270 if (flags
& OPERAND_SIGNED
)
272 max
= ((unsigned long)1 << (bits
- 1)) - 1;
273 min
= - ((unsigned long)1 << (bits
- 1));
274 return (long)num
> max
|| (long)num
< min
;
278 max
= ((unsigned long)1 << bits
) - 1;
280 return num
> max
|| num
< min
;
286 md_show_usage (stream
)
289 fprintf (stream
, _("\nD30V options:\n\
290 -O Make adjacent short instructions parallel if possible.\n\
291 -n Warn about all NOPs inserted by the assembler.\n\
292 -N Warn about NOPs inserted after word multiplies.\n\
293 -c Warn about symbols whoes names match register names.\n\
294 -C Opposite of -C. -c is the default.\n"));
298 md_parse_option (c
, arg
)
304 /* Optimize. Will attempt to parallelize operations */
309 /* Warn about all NOPS that the assembler inserts. */
314 /* Warn about the NOPS that the assembler inserts because of the
317 warn_nops
= NOP_MULTIPLY
;
321 warn_register_name_conflicts
= 1;
325 warn_register_name_conflicts
= 0;
335 md_undefined_symbol (name
)
341 /* Turn a string in input_line_pointer into a floating point constant of type
342 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
343 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
346 md_atof (type
, litP
, sizeP
)
352 LITTLENUM_TYPE words
[4];
366 return _("bad call to md_atof");
369 t
= atof_ieee (input_line_pointer
, type
, words
);
371 input_line_pointer
= t
;
375 for (i
= 0; i
< prec
; i
++)
377 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
384 md_convert_frag (abfd
, sec
, fragP
)
393 md_section_align (seg
, addr
)
397 int align
= bfd_get_section_alignment (stdoutput
, seg
);
398 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
405 struct d30v_opcode
* opcode
;
406 d30v_hash
= hash_new ();
408 /* Insert opcode names into a hash table. */
409 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
410 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
413 FixUps
[0].next
= &FixUps
[1];
414 FixUps
[1].next
= &FixUps
[0];
416 d30v_current_align_seg
= now_seg
;
420 /* this function removes the postincrement or postdecrement
421 operator ( '+' or '-' ) from an expression */
423 static int postfix (p
)
426 while (*p
!= '-' && *p
!= '+')
428 if (*p
==0 || *p
=='\n' || *p
=='\r' || *p
==' ' || *p
==',')
448 static bfd_reloc_code_real_type
449 get_reloc (op
, rel_flag
)
450 struct d30v_operand
*op
;
456 if (op
->flags
& OPERAND_SHIFT
)
457 return BFD_RELOC_D30V_9_PCREL
;
459 return BFD_RELOC_D30V_6
;
462 if (!(op
->flags
& OPERAND_SHIFT
))
463 as_warn (_("unexpected 12-bit reloc type"));
464 if (rel_flag
== RELOC_PCREL
)
465 return BFD_RELOC_D30V_15_PCREL
;
467 return BFD_RELOC_D30V_15
;
469 if (!(op
->flags
& OPERAND_SHIFT
))
470 as_warn (_("unexpected 18-bit reloc type"));
471 if (rel_flag
== RELOC_PCREL
)
472 return BFD_RELOC_D30V_21_PCREL
;
474 return BFD_RELOC_D30V_21
;
476 if (rel_flag
== RELOC_PCREL
)
477 return BFD_RELOC_D30V_32_PCREL
;
479 return BFD_RELOC_D30V_32
;
485 /* get_operands parses a string of operands and returns
486 an array of expressions */
489 get_operands (exp
, cmp_hack
)
493 char *p
= input_line_pointer
;
499 exp
[numops
].X_op
= O_absent
;
500 exp
[numops
++].X_add_number
= cmp_hack
- 1;
505 while (*p
== ' ' || *p
== '\t' || *p
== ',')
507 if (*p
==0 || *p
=='\n' || *p
=='\r')
513 exp
[numops
].X_op
= O_absent
;
517 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
523 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
527 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
536 /* just skip the trailing paren */
541 input_line_pointer
= p
;
543 /* check to see if it might be a register name */
544 if (!register_name (&exp
[numops
]))
546 /* parse as an expression */
547 expression (&exp
[numops
]);
550 if (exp
[numops
].X_op
== O_illegal
)
551 as_bad (_("illegal operand"));
552 else if (exp
[numops
].X_op
== O_absent
)
553 as_bad (_("missing operand"));
556 p
= input_line_pointer
;
560 case -1: /* postdecrement mode */
561 exp
[numops
].X_op
= O_absent
;
562 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
564 case 1: /* postincrement mode */
565 exp
[numops
].X_op
= O_absent
;
566 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
572 exp
[numops
].X_op
= 0;
576 /* build_insn generates the instruction. It does everything */
577 /* but write the FM bits. */
580 build_insn (opcode
, opers
)
581 struct d30v_insn
*opcode
;
584 int i
, length
, bits
, shift
, flags
;
585 unsigned long number
, id
=0;
587 struct d30v_opcode
*op
= opcode
->op
;
588 struct d30v_format
*form
= opcode
->form
;
590 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
592 for (i
=0; form
->operands
[i
]; i
++)
594 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
596 /* must be a register or number */
597 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
598 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
601 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
602 if (flags
& OPERAND_SHIFT
)
605 length
= d30v_operand_table
[form
->operands
[i
]].length
;
606 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
607 if (opers
[i
].X_op
!= O_symbol
)
608 number
= opers
[i
].X_add_number
;
611 if (flags
& OPERAND_REG
)
613 /* check for mvfsys or mvtsys control registers */
614 if (flags
& OPERAND_CONTROL
&& (number
& 0x7f) > MAX_CONTROL_REG
)
617 id
= (number
& 0x7f) - MAX_CONTROL_REG
;
620 else if (number
& OPERAND_FLAG
)
622 id
= 3; /* number is a flag register */
626 else if (flags
& OPERAND_SPECIAL
)
631 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
633 /* now create a fixup */
635 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
636 as_fatal (_("too many fixups"));
638 fixups
->fix
[fixups
->fc
].reloc
=
639 get_reloc ((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
640 fixups
->fix
[fixups
->fc
].size
= 4;
641 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
642 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
643 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D30V_9_PCREL
)
644 fixups
->fix
[fixups
->fc
].pcrel
= RELOC_PCREL
;
646 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
650 /* truncate to the proper number of bits */
651 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
652 as_bad (_("operand out of range: %d"),number
);
654 number
&= 0x7FFFFFFF >> (31 - bits
);
655 if (flags
& OPERAND_SHIFT
)
659 /* it's a LONG instruction */
660 insn
|= ((number
& 0xffffffff) >> 26); /* top 6 bits */
661 insn
<<= 32; /* shift the first word over */
662 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
663 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
666 insn
|= number
<< shift
;
672 /* write out a long form instruction */
674 write_long (opcode
, insn
, fx
)
675 struct d30v_insn
*opcode
;
680 char *f
= frag_more (8);
683 d30v_number_to_chars (f
, insn
, 8);
685 for (i
=0; i
< fx
->fc
; i
++)
687 if (fx
->fix
[i
].reloc
)
689 where
= f
- frag_now
->fr_literal
;
690 fix_new_exp (frag_now
,
702 /* Write out a short form instruction by itself. */
704 write_1_short (opcode
, insn
, fx
, use_sequential
)
705 struct d30v_insn
*opcode
;
710 char *f
= frag_more (8);
713 if (warn_nops
== NOP_ALL
)
714 as_warn (_("%s NOP inserted"), use_sequential
?
715 _("sequential") : _("parallel"));
717 /* The other container needs to be NOP. */
720 /* Use a sequential NOP rather than a parallel one,
721 as the current instruction is a FLAG_MUL32 type one
722 and the next instruction is a load. */
724 /* According to 4.3.1: for FM=01, sub-instructions performed
725 only by IU cannot be encoded in L-container. */
727 if (opcode
->op
->unit
== IU
)
728 insn
|= FM10
| NOP_LEFT
; /* right then left */
730 insn
= FM01
| (insn
<< 32) | NOP_RIGHT
; /* left then right */
734 /* According to 4.3.1: for FM=00, sub-instructions performed
735 only by IU cannot be encoded in L-container. */
737 if (opcode
->op
->unit
== IU
)
738 insn
|= FM00
| NOP_LEFT
; /* right container */
740 insn
= FM00
| (insn
<< 32) | NOP_RIGHT
; /* left container */
743 d30v_number_to_chars (f
, insn
, 8);
745 for (i
=0; i
< fx
->fc
; i
++)
747 if (fx
->fix
[i
].reloc
)
749 where
= f
- frag_now
->fr_literal
;
750 fix_new_exp (frag_now
,
761 /* Write out a short form instruction if possible.
762 Return number of instructions not written out. */
764 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
765 struct d30v_insn
*opcode1
, *opcode2
;
766 long long insn1
, insn2
;
767 exec_type_enum exec_type
;
770 long long insn
= NOP2
;
774 if (exec_type
== EXEC_SEQ
775 && (opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
))
776 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0)
777 && ((opcode1
->ecc
== ECC_AL
) || ! Optimizing
))
779 /* Unconditional, non-delayed branches kill instructions in
780 the right bin. Conditional branches don't always but if
781 we are not optimizing, then we have been asked to produce
782 an error about such constructs. For the purposes of this
783 test, subroutine calls are considered to be branches. */
784 write_1_short (opcode1
, insn1
, fx
->next
, false);
788 /* Note: we do not have to worry about subroutine calls occuring
789 in the right hand container. The return address is always
790 aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
794 case EXEC_UNKNOWN
: /* Order not specified. */
796 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
)
797 && ! ( (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
798 || opcode1
->op
->unit
== MU
)
800 ( opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
801 || opcode2
->op
->unit
== MU
)))
804 exec_type
= EXEC_PARALLEL
;
806 if (opcode1
->op
->unit
== IU
807 || opcode2
->op
->unit
== MU
808 || opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
809 insn
= FM00
| (insn2
<< 32) | insn1
;
812 insn
= FM00
| (insn1
<< 32) | insn2
;
816 else if ((opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)
817 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0))
818 || opcode1
->op
->flags_used
& FLAG_RP
)
820 /* We must emit (non-delayed) branch type instructions
821 on their own with nothing in the right container. */
822 /* We must treat repeat instructions likewise, since the
823 following instruction has to be separate from the repeat
824 in order to be repeated. */
825 write_1_short (opcode1
, insn1
, fx
->next
, false);
828 else if (prev_left_kills_right_p
)
830 /* The left instruction kils the right slot, so we
831 must leave it empty. */
832 write_1_short (opcode1
, insn1
, fx
->next
, false);
835 else if (opcode1
->op
->unit
== IU
)
837 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
839 /* Case 103810 is a request from Mitsubishi that opcodes
840 with EITHER_BUT_PREFER_MU should not be executed in
841 reverse sequential order. */
842 write_1_short (opcode1
, insn1
, fx
->next
, false);
846 /* reverse sequential */
847 insn
= FM10
| (insn2
<< 32) | insn1
;
848 exec_type
= EXEC_REVSEQ
;
853 insn
= FM01
| (insn1
<< 32) | insn2
;
855 exec_type
= EXEC_SEQ
;
859 case EXEC_PARALLEL
: /* parallel */
860 flag_explicitly_parallel
= flag_xp_state
;
861 if (! parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
862 as_bad (_("Instructions may not be executed in parallel"));
863 else if (opcode1
->op
->unit
== IU
)
865 if (opcode2
->op
->unit
== IU
)
866 as_bad (_("Two IU instructions may not be executed in parallel"));
867 as_warn (_("Swapping instruction order"));
868 insn
= FM00
| (insn2
<< 32) | insn1
;
870 else if (opcode2
->op
->unit
== MU
)
872 if (opcode1
->op
->unit
== MU
)
873 as_bad (_("Two MU instructions may not be executed in parallel"));
874 else if (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
)
875 as_warn (_("Executing %s in IU may not work"), opcode1
->op
->name
);
876 as_warn (_("Swapping instruction order"));
877 insn
= FM00
| (insn2
<< 32) | insn1
;
881 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
882 as_warn (_("Executing %s in IU may not work in parallel execution"),
885 insn
= FM00
| (insn1
<< 32) | insn2
;
888 flag_explicitly_parallel
= 0;
891 case EXEC_SEQ
: /* sequential */
892 if (opcode1
->op
->unit
== IU
)
893 as_bad (_("IU instruction may not be in the left container"));
894 if (prev_left_kills_right_p
)
895 as_bad (_("special left instruction `%s' kills instruction "
896 "`%s' in right container"),
897 opcode1
->op
->name
, opcode2
->op
->name
);
898 insn
= FM01
| (insn1
<< 32) | insn2
;
902 case EXEC_REVSEQ
: /* reverse sequential */
903 if (opcode2
->op
->unit
== MU
)
904 as_bad (_("MU instruction may not be in the right container"));
905 if (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
)
906 as_warn (_("Executing %s in reverse serial with %s may not work"),
907 opcode1
->op
->name
, opcode2
->op
->name
);
908 else if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
909 as_warn (_("Executing %s in IU in reverse serial may not work"),
911 insn
= FM10
| (insn1
<< 32) | insn2
;
916 as_fatal (_("unknown execution type passed to write_2_short()"));
919 /* printf ("writing out %llx\n",insn); */
921 d30v_number_to_chars (f
, insn
, 8);
923 /* If the previous instruction was a 32-bit multiply but it is put into a
924 parallel container, mark the current instruction as being a 32-bit
926 if (prev_mul32_p
&& exec_type
== EXEC_PARALLEL
)
931 for (i
=0; i
< fx
->fc
; i
++)
933 if (fx
->fix
[i
].reloc
)
935 where
= (f
- frag_now
->fr_literal
) + 4*j
;
937 fix_new_exp (frag_now
,
954 /* Check 2 instructions and determine if they can be safely */
955 /* executed in parallel. Returns 1 if they can be. */
957 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
958 struct d30v_insn
*op1
, *op2
;
959 unsigned long insn1
, insn2
;
960 exec_type_enum exec_type
;
962 int i
, j
, shift
, regno
, bits
, ecc
;
963 unsigned long flags
, mask
, flags_set1
, flags_set2
, flags_used1
, flags_used2
;
964 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3], flag_reg
[2];
965 struct d30v_format
*f
;
966 struct d30v_opcode
*op
;
968 /* section 4.3: both instructions must not be IU or MU only */
969 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
970 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
973 /* first instruction must not be a jump to safely optimize, unless this
974 is an explicit parallel operation. */
975 if (exec_type
!= EXEC_PARALLEL
976 && (op1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)))
979 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
980 then it is safe to allow the two to be done as parallel ops, since only
981 one will ever be executed at a time. */
982 if ((op1
->ecc
== ECC_TX
&& op2
->ecc
== ECC_FX
)
983 || (op1
->ecc
== ECC_FX
&& op2
->ecc
== ECC_TX
)
984 || (op1
->ecc
== ECC_XT
&& op2
->ecc
== ECC_XF
)
985 || (op1
->ecc
== ECC_XF
&& op2
->ecc
== ECC_XT
))
990 [2] a0, a1, flag registers */
992 for (j
= 0; j
< 2; j
++)
1009 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
1010 used_reg
[j
][0] = used_reg
[j
][1] = 0;
1012 if (flag_explicitly_parallel
)
1014 /* For human specified parallel instructions we have been asked
1015 to ignore the possibility that both instructions could modify
1016 bits in the PSW, so we initialise the mod & used arrays to 0.
1017 We have been asked, however, to refuse to allow parallel
1018 instructions which explicitly set the same flag register,
1019 eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test
1020 for the use of a flag register and set a bit in the mod or used
1021 array appropriately. */
1028 mod_reg
[j
][2] = (op
->flags_set
& FLAG_ALL
);
1029 used_reg
[j
][2] = (op
->flags_used
& FLAG_ALL
);
1032 /* BSR/JSR always sets R62 */
1033 if (op
->flags_used
& FLAG_JSR
)
1034 mod_reg
[j
][1] = (1L << (62-32));
1036 /* conditional execution affects the flags_used */
1041 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_0
;
1046 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_1
;
1051 used_reg
[j
][2] |= flag_reg
[j
] = (FLAG_0
| FLAG_1
);
1055 for (i
= 0; f
->operands
[i
]; i
++)
1057 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
1058 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
1059 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
1063 mask
= 0x7FFFFFFF >> (31 - bits
);
1065 if ((flags
& OPERAND_PLUS
) || (flags
& OPERAND_MINUS
))
1067 /* this is a post-increment or post-decrement */
1068 /* the previous register needs to be marked as modified */
1070 shift
= 12 - d30v_operand_table
[f
->operands
[i
-1]].position
;
1071 regno
= (ins
>> shift
) & 0x3f;
1073 mod_reg
[j
][1] |= 1L << (regno
- 32);
1075 mod_reg
[j
][0] |= 1L << regno
;
1077 else if (flags
& OPERAND_REG
)
1079 regno
= (ins
>> shift
) & mask
;
1080 /* the memory write functions don't have a destination register */
1081 if ((flags
& OPERAND_DEST
) && !(op
->flags_set
& FLAG_MEM
))
1083 /* MODIFIED registers and flags */
1084 if (flags
& OPERAND_ACC
)
1087 mod_reg
[j
][2] |= FLAG_A0
;
1088 else if (regno
== 1)
1089 mod_reg
[j
][2] |= FLAG_A1
;
1093 else if (flags
& OPERAND_FLAG
)
1094 mod_reg
[j
][2] |= 1L << regno
;
1095 else if (!(flags
& OPERAND_CONTROL
))
1099 /* need to check if there are two destination */
1100 /* registers, for example ld2w */
1101 if (flags
& OPERAND_2REG
)
1106 for (r
= regno
; r
<= regno
+ z
; r
++)
1109 mod_reg
[j
][1] |= 1L << (r
- 32);
1111 mod_reg
[j
][0] |= 1L << r
;
1117 /* USED, but not modified registers and flags */
1118 if (flags
& OPERAND_ACC
)
1121 used_reg
[j
][2] |= FLAG_A0
;
1122 else if (regno
== 1)
1123 used_reg
[j
][2] |= FLAG_A1
;
1127 else if (flags
& OPERAND_FLAG
)
1128 used_reg
[j
][2] |= 1L << regno
;
1129 else if (!(flags
& OPERAND_CONTROL
))
1133 /* need to check if there are two source */
1134 /* registers, for example st2w */
1135 if (flags
& OPERAND_2REG
)
1140 for (r
= regno
; r
<= regno
+ z
; r
++)
1143 used_reg
[j
][1] |= 1L << (r
- 32);
1145 used_reg
[j
][0] |= 1L << r
;
1153 flags_set1
= op1
->op
->flags_set
;
1154 flags_set2
= op2
->op
->flags_set
;
1155 flags_used1
= op1
->op
->flags_used
;
1156 flags_used2
= op2
->op
->flags_used
;
1158 /* Check for illegal combinations with ADDppp/SUBppp. */
1159 if (((flags_set1
& FLAG_NOT_WITH_ADDSUBppp
) != 0
1160 && (flags_used2
& FLAG_ADDSUBppp
) != 0)
1161 || ((flags_set2
& FLAG_NOT_WITH_ADDSUBppp
) != 0
1162 && (flags_used1
& FLAG_ADDSUBppp
) != 0))
1165 /* Load instruction combined with half-word multiply is illegal. */
1166 if (((flags_used1
& FLAG_MEM
) != 0 && (flags_used2
& FLAG_MUL16
))
1167 || ((flags_used2
& FLAG_MEM
) != 0 && (flags_used1
& FLAG_MUL16
)))
1170 /* Specifically allow add || add by removing carry, overflow bits dependency.
1171 This is safe, even if an addc follows since the IU takes the argument in
1172 the right container, and it writes its results last.
1173 However, don't paralellize add followed by addc or sub followed by
1176 if (mod_reg
[0][2] == FLAG_CVVA
&& mod_reg
[1][2] == FLAG_CVVA
1177 && (used_reg
[0][2] & ~flag_reg
[0]) == 0
1178 && (used_reg
[1][2] & ~flag_reg
[1]) == 0
1179 && op1
->op
->unit
== EITHER
&& op2
->op
->unit
== EITHER
)
1181 mod_reg
[0][2] = mod_reg
[1][2] = 0;
1184 for (j
= 0; j
< 3; j
++)
1186 /* If the second instruction depends on the first, we obviously
1187 cannot parallelize. Note, the mod flag implies use, so
1188 check that as well. */
1189 /* If flag_explicitly_parallel is set, then the case of the
1190 second instruction using a register the first instruction
1191 modifies is assumed to be okay; we trust the human. We
1192 don't trust the human if both instructions modify the same
1193 register but we do trust the human if they modify the same
1195 /* We have now been requested not to trust the human if the
1196 instructions modify the same flag registers either. */
1197 if (flag_explicitly_parallel
)
1199 if ((mod_reg
[0][j
] & mod_reg
[1][j
]) != 0)
1203 if ((mod_reg
[0][j
] & (mod_reg
[1][j
] | used_reg
[1][j
])) != 0)
1211 /* This is the main entry point for the machine-dependent assembler. str points to a
1212 machine-dependent instruction. This function is supposed to emit the frags/bytes
1213 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
1214 and leaves the difficult stuff to do_assemble(). */
1216 static long long prev_insn
= -1;
1217 static struct d30v_insn prev_opcode
;
1218 static subsegT prev_subseg
;
1219 static segT prev_seg
= 0;
1225 struct d30v_insn opcode
;
1227 exec_type_enum extype
= EXEC_UNKNOWN
; /* execution type; parallel, etc */
1228 static exec_type_enum etype
= EXEC_UNKNOWN
; /* saved extype. used for multiline instructions */
1231 if ((prev_insn
!= -1) && prev_seg
1232 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1233 d30v_cleanup (false);
1235 if (d30v_current_align
< 3)
1236 d30v_align (3, NULL
, d30v_last_label
);
1237 else if (d30v_current_align
> 3)
1238 d30v_current_align
= 3;
1239 d30v_last_label
= NULL
;
1241 flag_explicitly_parallel
= 0;
1243 if (etype
== EXEC_UNKNOWN
)
1245 /* look for the special multiple instruction separators */
1246 str2
= strstr (str
, "||");
1249 extype
= EXEC_PARALLEL
;
1254 str2
= strstr (str
, "->");
1259 str2
= strstr (str
, "<-");
1261 extype
= EXEC_REVSEQ
;
1264 /* str2 points to the separator, if one */
1269 /* if two instructions are present and we already have one saved
1270 then first write it out */
1271 d30v_cleanup (false);
1273 /* Assemble first instruction and save it. */
1274 prev_insn
= do_assemble (str
, &prev_opcode
, 1, 0);
1275 if (prev_insn
== -1)
1276 as_bad (_("Cannot assemble instruction"));
1277 if (prev_opcode
.form
!= NULL
&& prev_opcode
.form
->form
>= LONG
)
1278 as_bad (_("First opcode is long. Unable to mix instructions as specified."));
1279 fixups
= fixups
->next
;
1282 prev_subseg
= now_subseg
;
1286 insn
= do_assemble (str
, &opcode
,
1287 (extype
!= EXEC_UNKNOWN
|| etype
!= EXEC_UNKNOWN
),
1288 extype
== EXEC_PARALLEL
);
1291 if (extype
!= EXEC_UNKNOWN
)
1293 as_bad (_("Cannot assemble instruction"));
1297 if (etype
!= EXEC_UNKNOWN
)
1300 etype
= EXEC_UNKNOWN
;
1303 /* Word multiply instructions must not be followed by either a load or a
1304 16-bit multiply instruction in the next cycle. */
1305 if ( (extype
!= EXEC_REVSEQ
)
1307 && (opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1309 /* However, load and multiply should able to be combined in a parallel
1310 operation, so check for that first. */
1312 && (opcode
.op
->flags_used
& FLAG_MEM
)
1313 && opcode
.form
->form
< LONG
1314 && (extype
== EXEC_PARALLEL
|| (Optimizing
&& extype
== EXEC_UNKNOWN
))
1315 && parallel_ok (&prev_opcode
, (long)prev_insn
,
1316 &opcode
, (long)insn
, extype
)
1317 && write_2_short (&prev_opcode
, (long)prev_insn
,
1318 &opcode
, (long)insn
, extype
, fixups
) == 0)
1320 /* no instructions saved */
1326 /* Can't parallelize, flush previous instruction and emit a word of NOPS,
1327 unless the previous instruction is a NOP, in which case just flush it,
1328 as this will generate a word of NOPs for us. */
1330 if (prev_insn
!= -1 && (strcmp (prev_opcode
.op
->name
, "nop") == 0))
1331 d30v_cleanup (false);
1336 if (prev_insn
!= -1)
1337 d30v_cleanup (true);
1341 d30v_number_to_chars (f
, NOP2
, 8);
1343 if (warn_nops
== NOP_ALL
|| warn_nops
== NOP_MULTIPLY
)
1345 if (opcode
.op
->flags_used
& FLAG_MEM
)
1346 as_warn (_("word of NOPs added between word multiply and load"));
1348 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1353 extype
= EXEC_UNKNOWN
;
1356 else if ( (extype
== EXEC_REVSEQ
)
1358 && (prev_opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1360 /* Can't parallelize, flush current instruction and add a sequential NOP. */
1361 write_1_short (& opcode
, (long) insn
, fixups
->next
->next
, true);
1363 /* Make the previous instruction the current one. */
1364 extype
= EXEC_UNKNOWN
;
1367 now_subseg
= prev_subseg
;
1369 cur_mul32_p
= prev_mul32_p
;
1371 memcpy (&opcode
, &prev_opcode
, sizeof (prev_opcode
));
1374 /* If this is a long instruction, write it and any previous short instruction. */
1375 if (opcode
.form
->form
>= LONG
)
1377 if (extype
!= EXEC_UNKNOWN
)
1378 as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
1379 d30v_cleanup (false);
1380 write_long (& opcode
, insn
, fixups
);
1383 else if ((prev_insn
!= -1)
1385 (& prev_opcode
, (long) prev_insn
, & opcode
,
1386 (long) insn
, extype
, fixups
) == 0))
1388 /* No instructions saved. */
1393 if (extype
!= EXEC_UNKNOWN
)
1394 as_bad (_("Unable to mix instructions as specified"));
1396 /* Save off last instruction so it may be packed on next pass. */
1397 memcpy (&prev_opcode
, &opcode
, sizeof (prev_opcode
));
1400 prev_subseg
= now_subseg
;
1401 fixups
= fixups
->next
;
1402 prev_mul32_p
= cur_mul32_p
;
1407 /* do_assemble assembles a single instruction and returns an opcode */
1408 /* it returns -1 (an invalid opcode) on error */
1410 #define NAME_BUF_LEN 20
1413 do_assemble (str
, opcode
, shortp
, is_parallel
)
1415 struct d30v_insn
*opcode
;
1419 unsigned char * op_start
;
1420 unsigned char * save
;
1421 unsigned char * op_end
;
1422 char name
[NAME_BUF_LEN
];
1425 int fsize
= (shortp
? FORCE_SHORT
: 0);
1426 expressionS myops
[6];
1429 /* Drop leading whitespace */
1430 while (* str
== ' ')
1433 /* find the opcode end */
1434 for (op_start
= op_end
= (unsigned char *) (str
);
1436 && nlen
< (NAME_BUF_LEN
- 1)
1438 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1441 name
[nlen
] = tolower (op_start
[nlen
]);
1450 /* if there is an execution condition code, handle it */
1454 while ( (i
< ECC_MAX
) && strncasecmp (d30v_ecc_names
[i
], op_end
+ 1, 2))
1460 strncpy (tmp
, op_end
+ 1, 2);
1462 as_bad (_("unknown condition code: %s"),tmp
);
1465 /* printf ("condition code=%d\n",i); */
1470 opcode
->ecc
= ECC_AL
;
1473 /* CMP and CMPU change their name based on condition codes */
1474 if (!strncmp (name
, "cmp", 3))
1477 char **str
= (char **)d30v_cc_names
;
1483 for (i
=1; *str
&& strncmp (*str
, & name
[p
], 2); i
++, str
++)
1486 /* cmpu only supports some condition codes */
1492 as_bad (_("cmpu doesn't support condition code %s"),&name
[p
]);
1499 as_bad (_("unknown condition code: %s"),&name
[p
]);
1508 /* printf("cmp_hack=%d\n",cmp_hack); */
1510 /* need to look for .s or .l */
1511 if (name
[nlen
-2] == '.')
1513 switch (name
[nlen
-1])
1516 fsize
= FORCE_SHORT
;
1525 /* find the first opcode with the proper name */
1526 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1527 if (opcode
->op
== NULL
)
1529 as_bad (_("unknown opcode: %s"),name
);
1533 save
= input_line_pointer
;
1534 input_line_pointer
= op_end
;
1535 while (!(opcode
->form
= find_format (opcode
->op
, myops
, fsize
, cmp_hack
)))
1538 if (opcode
->op
->name
== NULL
|| strcmp (opcode
->op
->name
, name
))
1540 as_bad (_("operands for opcode `%s' do not match any valid format"), name
);
1544 input_line_pointer
= save
;
1546 insn
= build_insn (opcode
, myops
);
1548 /* Propigate multiply status */
1551 if (is_parallel
&& prev_mul32_p
)
1555 prev_mul32_p
= cur_mul32_p
;
1556 cur_mul32_p
= (opcode
->op
->flags_used
& FLAG_MUL32
) != 0;
1560 /* Propagate left_kills_right status */
1563 prev_left_kills_right_p
= cur_left_kills_right_p
;
1565 if (opcode
->op
->flags_set
& FLAG_LKR
)
1567 cur_left_kills_right_p
= 1;
1569 if (strcmp (opcode
->op
->name
, "mvtsys") == 0)
1571 /* Left kills right for only mvtsys only for PSW/PSWH/PSWL/flags target. */
1572 if ((myops
[0].X_op
== O_register
) &&
1573 ((myops
[0].X_add_number
== OPERAND_CONTROL
) || /* psw */
1574 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+2) || /* pswh */
1575 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+1) || /* pswl */
1576 (myops
[0].X_add_number
== OPERAND_FLAG
+0) || /* f0 */
1577 (myops
[0].X_add_number
== OPERAND_FLAG
+1) || /* f1 */
1578 (myops
[0].X_add_number
== OPERAND_FLAG
+2) || /* f2 */
1579 (myops
[0].X_add_number
== OPERAND_FLAG
+3) || /* f3 */
1580 (myops
[0].X_add_number
== OPERAND_FLAG
+4) || /* f4 */
1581 (myops
[0].X_add_number
== OPERAND_FLAG
+5) || /* f5 */
1582 (myops
[0].X_add_number
== OPERAND_FLAG
+6) || /* f6 */
1583 (myops
[0].X_add_number
== OPERAND_FLAG
+7))) /* f7 */
1585 cur_left_kills_right_p
= 1;
1589 /* Other mvtsys target registers don't kill right instruction. */
1590 cur_left_kills_right_p
= 0;
1595 cur_left_kills_right_p
= 0;
1602 /* find_format() gets a pointer to an entry in the format table.
1603 It must look at all formats for an opcode and use the operands
1604 to choose the correct one. Returns NULL on error. */
1606 static struct d30v_format
*
1607 find_format (opcode
, myops
, fsize
, cmp_hack
)
1608 struct d30v_opcode
*opcode
;
1609 expressionS myops
[];
1613 int numops
, match
, index
, i
=0, j
, k
;
1614 struct d30v_format
*fm
;
1619 /* Get all the operands and save them as expressions. */
1620 numops
= get_operands (myops
, cmp_hack
);
1622 while ((index
= opcode
->format
[i
++]) != 0)
1624 if (fsize
== FORCE_SHORT
&& index
>= LONG
)
1627 if (fsize
== FORCE_LONG
&& index
< LONG
)
1630 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1632 while (fm
->form
== index
)
1635 /* Now check the operands for compatibility. */
1636 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1638 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1639 int bits
= d30v_operand_table
[fm
->operands
[j
]].bits
;
1640 int X_op
= myops
[j
].X_op
;
1641 int num
= myops
[j
].X_add_number
;
1643 if (flags
& OPERAND_SPECIAL
)
1645 else if (X_op
== O_illegal
)
1647 else if (flags
& OPERAND_REG
)
1649 if (X_op
!= O_register
1650 || ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
))
1651 || (!(flags
& OPERAND_ACC
) && (num
& OPERAND_ACC
))
1652 || ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
))
1653 || (!(flags
& (OPERAND_FLAG
| OPERAND_CONTROL
)) && (num
& OPERAND_FLAG
))
1654 || ((flags
& OPERAND_CONTROL
)
1655 && !(num
& (OPERAND_CONTROL
| OPERAND_FLAG
))))
1660 else if (((flags
& OPERAND_MINUS
)
1661 && (X_op
!= O_absent
|| num
!= OPERAND_MINUS
))
1662 || ((flags
& OPERAND_PLUS
)
1663 && (X_op
!= O_absent
|| num
!= OPERAND_PLUS
))
1664 || ((flags
& OPERAND_ATMINUS
)
1665 && (X_op
!= O_absent
|| num
!= OPERAND_ATMINUS
))
1666 || ((flags
& OPERAND_ATPAR
)
1667 && (X_op
!= O_absent
|| num
!= OPERAND_ATPAR
))
1668 || ((flags
& OPERAND_ATSIGN
)
1669 && (X_op
!= O_absent
|| num
!= OPERAND_ATSIGN
)))
1673 else if (flags
& OPERAND_NUM
)
1675 /* A number can be a constant or symbol expression. */
1677 /* If we have found a register name, but that name also
1678 matches a symbol, then re-parse the name as an expression. */
1679 if (X_op
== O_register
1680 && symbol_find ((char *) myops
[j
].X_op_symbol
))
1682 input_line_pointer
= (char *) myops
[j
].X_op_symbol
;
1683 expression (& myops
[j
]);
1686 /* Turn an expression into a symbol for later resolution. */
1687 if (X_op
!= O_absent
&& X_op
!= O_constant
1688 && X_op
!= O_symbol
&& X_op
!= O_register
1691 symbolS
*sym
= make_expr_symbol (&myops
[j
]);
1692 myops
[j
].X_op
= X_op
= O_symbol
;
1693 myops
[j
].X_add_symbol
= sym
;
1694 myops
[j
].X_add_number
= num
= 0;
1697 if (fm
->form
>= LONG
)
1699 /* If we're testing for a LONG format, either fits. */
1700 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1703 else if (fm
->form
< LONG
1704 && ((fsize
== FORCE_SHORT
&& X_op
== O_symbol
)
1705 || (fm
->form
== SHORT_D2
&& j
== 0)))
1707 /* This is the tricky part. Will the constant or symbol
1708 fit into the space in the current format? */
1709 else if (X_op
== O_constant
)
1711 if (check_range (num
, bits
, flags
))
1714 else if (X_op
== O_symbol
1715 && S_IS_DEFINED (myops
[j
].X_add_symbol
)
1716 && S_GET_SEGMENT (myops
[j
].X_add_symbol
) == now_seg
1717 && opcode
->reloc_flag
== RELOC_PCREL
)
1719 /* If the symbol is defined, see if the value will fit
1720 into the form we're considering. */
1724 /* Calculate the current address by running through the
1725 previous frags and adding our current offset. */
1727 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1728 value
+= f
->fr_fix
+ f
->fr_offset
;
1729 value
= (S_GET_VALUE (myops
[j
].X_add_symbol
) - value
1730 - (obstack_next_free (&frchain_now
->frch_obstack
)
1731 - frag_now
->fr_literal
));
1732 if (check_range (value
, bits
, flags
))
1739 /* printf("through the loop: match=%d\n",match); */
1740 /* We're only done if the operands matched so far AND there
1741 are no more to check. */
1742 if (match
&& myops
[j
].X_op
== 0)
1744 /* Final check - issue a warning if an odd numbered register
1745 is used as the first register in an instruction that reads
1746 or writes 2 registers. */
1748 for (j
= 0; fm
->operands
[j
]; j
++)
1749 if (myops
[j
].X_op
== O_register
1750 && (myops
[j
].X_add_number
& 1)
1751 && (d30v_operand_table
[fm
->operands
[j
]].flags
& OPERAND_2REG
))
1753 _("Odd numbered register used as target of multi-register instruction"));
1757 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1759 /* printf("trying another format: i=%d\n",i); */
1764 /* if while processing a fixup, a reloc really needs to be created */
1765 /* then it is done here */
1768 tc_gen_reloc (seg
, fixp
)
1773 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1774 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1775 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1776 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1777 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1778 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1780 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1781 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1784 reloc
->addend
= fixp
->fx_addnumber
;
1789 md_estimate_size_before_relax (fragp
, seg
)
1798 md_pcrel_from_section (fixp
, sec
)
1802 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1803 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1805 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1809 md_apply_fix3 (fixp
, valuep
, seg
)
1815 unsigned long insn
, insn2
;
1818 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1823 else if (fixp
->fx_pcrel
)
1827 value
= fixp
->fx_offset
;
1829 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1831 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1832 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1835 /* We don't actually support subtracting a symbol. */
1836 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1837 _("expression too complex"));
1842 /* Fetch the instruction, insert the fully resolved operand
1843 value, and stuff the instruction back again. */
1844 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1845 insn
= bfd_getb32 ((unsigned char *) where
);
1847 switch (fixp
->fx_r_type
)
1849 case BFD_RELOC_8
: /* Check for a bad .byte directive. */
1850 if (fixp
->fx_addsy
!= NULL
)
1851 as_bad (_("line %d: unable to place address of symbol '%s' into a byte"),
1852 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1853 else if (((unsigned)value
) > 0xff)
1854 as_bad (_("line %d: unable to place value %x into a byte"),
1855 fixp
->fx_line
, value
);
1857 * (unsigned char *) where
= value
;
1860 case BFD_RELOC_16
: /* Check for a bad .short directive. */
1861 if (fixp
->fx_addsy
!= NULL
)
1862 as_bad (_("line %d: unable to place address of symbol '%s' into a short"),
1863 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1864 else if (((unsigned)value
) > 0xffff)
1865 as_bad (_("line %d: unable to place value %x into a short"),
1866 fixp
->fx_line
, value
);
1868 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1871 case BFD_RELOC_64
: /* Check for a bad .quad directive. */
1872 if (fixp
->fx_addsy
!= NULL
)
1873 as_bad (_("line %d: unable to place address of symbol '%s' into a quad"),
1874 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1877 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1878 bfd_putb32 (0, ((unsigned char *) where
) + 4);
1882 case BFD_RELOC_D30V_6
:
1883 check_size (value
, 6, fixp
->fx_file
, fixp
->fx_line
);
1884 insn
|= value
& 0x3F;
1885 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1888 case BFD_RELOC_D30V_9_PCREL
:
1889 if (fixp
->fx_where
& 0x7)
1894 fixp
->fx_r_type
= BFD_RELOC_D30V_9_PCREL_R
;
1896 check_size (value
, 9, fixp
->fx_file
, fixp
->fx_line
);
1897 insn
|= ((value
>> 3) & 0x3F) << 12;
1898 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1901 case BFD_RELOC_D30V_15
:
1902 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1903 insn
|= (value
>> 3) & 0xFFF;
1904 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1907 case BFD_RELOC_D30V_15_PCREL
:
1908 if (fixp
->fx_where
& 0x7)
1913 fixp
->fx_r_type
= BFD_RELOC_D30V_15_PCREL_R
;
1915 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1916 insn
|= (value
>> 3) & 0xFFF;
1917 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1920 case BFD_RELOC_D30V_21
:
1921 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1922 insn
|= (value
>> 3) & 0x3FFFF;
1923 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1926 case BFD_RELOC_D30V_21_PCREL
:
1927 if (fixp
->fx_where
& 0x7)
1932 fixp
->fx_r_type
= BFD_RELOC_D30V_21_PCREL_R
;
1934 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1935 insn
|= (value
>> 3) & 0x3FFFF;
1936 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1939 case BFD_RELOC_D30V_32
:
1940 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1941 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1942 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1943 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1944 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1945 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1948 case BFD_RELOC_D30V_32_PCREL
:
1949 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1950 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1951 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1952 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1953 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1954 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1958 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1962 as_bad (_("line %d: unknown relocation type: 0x%x"),
1963 fixp
->fx_line
,fixp
->fx_r_type
);
1970 /* d30v_cleanup() is called after the assembler has finished parsing the input
1971 file or after a label is defined. Because the D30V assembler sometimes saves short
1972 instructions to see if it can package them with the next instruction, there may
1973 be a short instruction that still needs written. */
1975 d30v_cleanup (use_sequential
)
1981 if (prev_insn
!= -1)
1984 subseg
= now_subseg
;
1985 subseg_set (prev_seg
, prev_subseg
);
1986 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
, use_sequential
);
1987 subseg_set (seg
, subseg
);
1990 prev_mul32_p
= false;
1996 d30v_number_to_chars (buf
, value
, n
)
1997 char *buf
; /* Return 'nbytes' of chars here. */
1998 long long value
; /* The value of the bits. */
1999 int n
; /* Number of bytes in the output. */
2003 buf
[n
] = value
& 0xff;
2009 /* This function is called at the start of every line. */
2010 /* it checks to see if the first character is a '.' */
2011 /* which indicates the start of a pseudo-op. If it is, */
2012 /* then write out any unwritten instructions */
2017 char *c
= input_line_pointer
;
2019 while (isspace (*c
))
2023 d30v_cleanup (false);
2027 check_size (value
, bits
, file
, line
)
2040 max
= (1 << (bits
- 1)) - 1;
2043 as_bad_where (file
, line
, _("value too large to fit in %d bits"), bits
);
2048 /* d30v_frob_label() is called when after a label is recognized. */
2051 d30v_frob_label (lab
)
2054 /* Emit any pending instructions. */
2055 d30v_cleanup (false);
2057 /* Update the label's address with the current output pointer. */
2058 symbol_set_frag (lab
, frag_now
);
2059 S_SET_VALUE (lab
, (valueT
) frag_now_fix ());
2061 /* Record this label for future adjustment after we find out what
2062 kind of data it references, and the required alignment therewith. */
2063 d30v_last_label
= lab
;
2066 /* Hook into cons for capturing alignment changes. */
2069 d30v_cons_align (size
)
2075 while ((size
>>= 1) != 0)
2078 if (d30v_current_align
< log_size
)
2079 d30v_align (log_size
, (char *) NULL
, NULL
);
2080 else if (d30v_current_align
> log_size
)
2081 d30v_current_align
= log_size
;
2082 d30v_last_label
= NULL
;
2085 /* Called internally to handle all alignment needs. This takes care
2086 of eliding calls to frag_align if'n the cached current alignment
2087 says we've already got it, as well as taking care of the auto-aligning
2091 d30v_align (n
, pfill
, label
)
2096 /* The front end is prone to changing segments out from under us
2097 temporarily when -g is in effect. */
2098 int switched_seg_p
= (d30v_current_align_seg
!= now_seg
);
2100 /* Do not assume that if 'd30v_current_align >= n' and
2101 '! switched_seg_p' that it is safe to avoid performing
2102 this alignement request. The alignment of the current frag
2103 can be changed under our feet, for example by a .ascii
2104 directive in the source code. cf testsuite/gas/d30v/reloc.s */
2106 d30v_cleanup (false);
2111 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
2113 static char const nop
[4] = { 0x00, 0xf0, 0x00, 0x00 };
2115 /* First, make sure we're on a four-byte boundary, in case
2116 someone has been putting .byte values the text section. */
2117 if (d30v_current_align
< 2 || switched_seg_p
)
2118 frag_align (2, 0, 0);
2119 frag_align_pattern (n
, nop
, sizeof nop
, 0);
2122 frag_align (n
, 0, 0);
2125 frag_align (n
, *pfill
, 0);
2127 if (!switched_seg_p
)
2128 d30v_current_align
= n
;
2133 int label_seen
= false;
2134 struct frag
* old_frag
;
2138 assert (S_GET_SEGMENT (label
) == now_seg
);
2140 old_frag
= symbol_get_frag (label
);
2141 old_value
= S_GET_VALUE (label
);
2142 new_value
= (valueT
) frag_now_fix ();
2144 /* It is possible to have more than one label at a particular
2145 address, especially if debugging is enabled, so we must
2146 take care to adjust all the labels at this address in this
2147 fragment. To save time we search from the end of the symbol
2148 list, backwards, since the symbols we are interested in are
2149 almost certainly the ones that were most recently added.
2150 Also to save time we stop searching once we have seen at least
2151 one matching label, and we encounter a label that is no longer
2152 in the target fragment. Note, this search is guaranteed to
2153 find at least one match when sym == label, so no special case
2154 code is necessary. */
2155 for (sym
= symbol_lastP
; sym
!= NULL
; sym
= symbol_previous (sym
))
2157 if (symbol_get_frag (sym
) == old_frag
2158 && S_GET_VALUE (sym
) == old_value
)
2161 symbol_set_frag (sym
, frag_now
);
2162 S_SET_VALUE (sym
, new_value
);
2164 else if (label_seen
&& symbol_get_frag (sym
) != old_frag
)
2169 record_alignment (now_seg
, n
);
2172 /* Handle the .align pseudo-op. This aligns to a power of two. We
2173 hook here to latch the current alignment. */
2176 s_d30v_align (ignore
)
2180 char fill
, *pfill
= NULL
;
2181 long max_alignment
= 15;
2183 align
= get_absolute_expression ();
2184 if (align
> max_alignment
)
2186 align
= max_alignment
;
2187 as_warn (_("Alignment too large: %d assumed"), align
);
2191 as_warn (_("Alignment negative: 0 assumed"));
2195 if (*input_line_pointer
== ',')
2197 input_line_pointer
++;
2198 fill
= get_absolute_expression ();
2202 d30v_last_label
= NULL
;
2203 d30v_align (align
, pfill
, NULL
);
2205 demand_empty_rest_of_line ();
2208 /* Handle the .text pseudo-op. This is like the usual one, but it
2209 clears the saved last label and resets known alignment. */
2217 d30v_last_label
= NULL
;
2218 d30v_current_align
= 0;
2219 d30v_current_align_seg
= now_seg
;
2222 /* Handle the .data pseudo-op. This is like the usual one, but it
2223 clears the saved last label and resets known alignment. */
2230 d30v_last_label
= NULL
;
2231 d30v_current_align
= 0;
2232 d30v_current_align_seg
= now_seg
;
2235 /* Handle the .section pseudo-op. This is like the usual one, but it
2236 clears the saved last label and resets known alignment. */
2239 s_d30v_section (ignore
)
2242 obj_elf_section (ignore
);
2243 d30v_last_label
= NULL
;
2244 d30v_current_align
= 0;
2245 d30v_current_align_seg
= now_seg
;