1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
3 Copyright (C) 1997 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d30v.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "O";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
38 #define MAX_INSN_FIXUPS (5)
45 bfd_reloc_code_real_type reloc
;
48 typedef struct _fixups
51 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
55 static Fixups FixUps
[2];
56 static Fixups
*fixups
;
59 static int reg_name_search
PARAMS ((char *name
));
60 static int register_name
PARAMS ((expressionS
*expressionP
));
61 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
62 static int postfix
PARAMS ((char *p
));
63 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
64 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
65 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
, expressionS ops
[],
67 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
68 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
69 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
70 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
71 struct d30v_insn
*opcode2
, long long insn2
, int exec_type
, Fixups
*fx
));
72 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
));
73 static unsigned long d30v_insert_operand
PARAMS (( unsigned long insn
, int op_type
,
74 offsetT value
, int left
, fixS
*fix
));
75 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
76 struct d30v_insn
*opcode2
, unsigned long insn2
,
78 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
80 struct option md_longopts
[] = {
81 {NULL
, no_argument
, NULL
, 0}
83 size_t md_longopts_size
= sizeof(md_longopts
);
86 /* The target specific pseudo-ops which we support. */
87 const pseudo_typeS md_pseudo_table
[] =
92 /* Opcode hash table. */
93 static struct hash_control
*d30v_hash
;
95 /* reg_name_search does a binary search of the pre_defined_registers
96 array to see if "name" is a valid regiter name. Returns the register
97 number from the array on success, or -1 on failure. */
100 reg_name_search (name
)
103 int middle
, low
, high
;
107 high
= reg_name_cnt() - 1;
111 middle
= (low
+ high
) / 2;
112 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
118 return pre_defined_registers
[middle
].value
;
124 /* register_name() checks the string at input_line_pointer
125 to see if it is a valid register name */
128 register_name (expressionP
)
129 expressionS
*expressionP
;
132 char c
, *p
= input_line_pointer
;
134 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
141 /* look to see if it's in the register table */
142 reg_number
= reg_name_search (input_line_pointer
);
145 expressionP
->X_op
= O_register
;
146 /* temporarily store a pointer to the string here */
147 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
148 expressionP
->X_add_number
= reg_number
;
149 input_line_pointer
= p
;
159 check_range (num
, bits
, flags
)
167 /* don't bother checking 32-bit values */
171 if (flags
& OPERAND_SIGNED
)
173 max
= (1 << (bits
- 1))-1;
174 min
= - (1 << (bits
- 1));
175 if (((long)num
> max
) || ((long)num
< min
))
180 max
= (1 << bits
) - 1;
182 if ((num
> max
) || (num
< min
))
190 md_show_usage (stream
)
193 fprintf(stream
, "D30V options:\n\
194 -O optimize. Will do some operations in parallel.\n");
198 md_parse_option (c
, arg
)
205 /* Optimize. Will attempt to parallelize operations */
215 md_undefined_symbol (name
)
221 /* Turn a string in input_line_pointer into a floating point constant of type
222 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
223 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
226 md_atof (type
, litP
, sizeP
)
232 LITTLENUM_TYPE words
[4];
246 return "bad call to md_atof";
249 t
= atof_ieee (input_line_pointer
, type
, words
);
251 input_line_pointer
= t
;
255 for (i
= 0; i
< prec
; i
++)
257 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
264 md_convert_frag (abfd
, sec
, fragP
)
273 md_section_align (seg
, addr
)
277 int align
= bfd_get_section_alignment (stdoutput
, seg
);
278 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
285 struct d30v_opcode
*opcode
;
286 d30v_hash
= hash_new();
288 /* Insert opcode names into a hash table. */
289 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
290 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
293 FixUps
[0].next
= &FixUps
[1];
294 FixUps
[1].next
= &FixUps
[0];
298 /* this function removes the postincrement or postdecrement
299 operator ( '+' or '-' ) from an expression */
301 static int postfix (p
)
304 while (*p
!= '-' && *p
!= '+')
306 if (*p
==0 || *p
=='\n' || *p
=='\r')
326 static bfd_reloc_code_real_type
327 get_reloc (op
, rel_flag
)
328 struct d30v_operand
*op
;
334 return BFD_RELOC_D30V_6
;
336 if (!(op
->flags
& OPERAND_SHIFT
))
337 as_warn("unexpected 12-bit reloc type");
338 if (rel_flag
== RELOC_PCREL
)
339 return BFD_RELOC_D30V_15_PCREL
;
341 return BFD_RELOC_D30V_15
;
343 if (!(op
->flags
& OPERAND_SHIFT
))
344 as_warn("unexpected 18-bit reloc type");
345 if (rel_flag
== RELOC_PCREL
)
346 return BFD_RELOC_D30V_21_PCREL
;
348 return BFD_RELOC_D30V_21
;
350 if (rel_flag
== RELOC_PCREL
)
351 return BFD_RELOC_D30V_32_PCREL
;
353 return BFD_RELOC_D30V_32
;
359 /* get_operands parses a string of operands and returns
360 an array of expressions */
363 get_operands (exp
, cmp_hack
)
367 char *p
= input_line_pointer
;
373 exp
[numops
].X_op
= O_absent
;
374 exp
[numops
++].X_add_number
= cmp_hack
- 1;
379 while (*p
== ' ' || *p
== '\t' || *p
== ',')
381 if (*p
==0 || *p
=='\n' || *p
=='\r')
387 exp
[numops
].X_op
= O_absent
;
391 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
397 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
401 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
410 /* just skip the trailing paren */
415 input_line_pointer
= p
;
417 /* check to see if it might be a register name */
418 if (!register_name (&exp
[numops
]))
420 /* parse as an expression */
421 expression (&exp
[numops
]);
424 if (exp
[numops
].X_op
== O_illegal
)
425 as_bad ("illegal operand");
426 else if (exp
[numops
].X_op
== O_absent
)
427 as_bad ("missing operand");
430 p
= input_line_pointer
;
434 case -1: /* postdecrement mode */
435 exp
[numops
].X_op
= O_absent
;
436 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
438 case 1: /* postincrement mode */
439 exp
[numops
].X_op
= O_absent
;
440 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
446 exp
[numops
].X_op
= 0;
452 d30v_insert_operand (insn
, op_type
, value
, left
, fix
)
461 shift
= d30v_operands
[op_type
].shift
;
465 bits
= d30v_operands
[op_type
].bits
;
467 /* truncate to the proper number of bits */
468 if (check_range (value
, bits
, d30v_operands
[op_type
].flags
))
469 as_bad_where (fix
->fx_file
, fix
->fx_line
, "operand out of range: %d", value
);
471 value
&= 0x7FFFFFFF >> (31 - bits
);
472 insn
|= (value
<< shift
);
478 /* build_insn generates the instruction. It does everything */
479 /* but write the FM bits. */
482 build_insn (opcode
, opers
)
483 struct d30v_insn
*opcode
;
486 int i
, length
, bits
, shift
, flags
, format
;
487 unsigned int number
, id
=0;
489 struct d30v_opcode
*op
= opcode
->op
;
490 struct d30v_format
*form
= opcode
->form
;
492 /* printf("ecc=%x op1=%x op2=%x mod=%x\n",opcode->ecc,op->op1,op->op2,form->modifier); */
493 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
494 /* printf("insn=%llx\n",insn); */
495 for (i
=0; form
->operands
[i
]; i
++)
497 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
500 /* must be a register or number */
501 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
502 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
505 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
506 length
= d30v_operand_table
[form
->operands
[i
]].length
;
507 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
508 number
= opers
[i
].X_add_number
;
509 if (flags
& OPERAND_REG
)
511 /* now check for mvfsys or mvtsys control registers */
512 if (flags
& OPERAND_CONTROL
&& (number
& 0x3f) > MAX_CONTROL_REG
)
515 id
= (number
& 0x3f) - MAX_CONTROL_REG
;
518 else if (number
& OPERAND_FLAG
)
520 id
= 3; /* number is a flag register */
524 else if (flags
& OPERAND_SPECIAL
)
529 if (Optimizing
) printf("bits=%d length=%d shift=%d number=%x\n",bits
,length
,shift
,number
);
531 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
533 /* now create a fixup */
535 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
536 as_fatal ("too many fixups");
538 fixups
->fix
[fixups
->fc
].reloc
=
539 get_reloc((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
540 fixups
->fix
[fixups
->fc
].size
= 4;
541 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
542 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
543 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
544 if (Optimizing
) printf("fixup %d: reloc=%d operand=%d\n",fixups
->fc
,fixups
->fix
[fixups
->fc
].reloc
,form
->operands
[i
]);
548 /* truncate to the proper number of bits */
550 if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
551 as_bad("operand out of range: %d",number);
552 number &= 0x7FFFFFFF >> (31 - bits);
557 /* it's a LONG instruction */
558 insn
|= (number
>> 26); /* top 6 bits */
559 insn
<<= 32; /* shift the first word over */
560 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
561 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
564 insn
|= number
<< shift
;
570 /* write out a long form instruction */
572 write_long (opcode
, insn
, fx
)
573 struct d30v_insn
*opcode
;
578 char *f
= frag_more(8);
581 d30v_number_to_chars (f
, insn
, 8);
583 for (i
=0; i
< fx
->fc
; i
++)
585 if (fx
->fix
[i
].reloc
)
587 where
= f
- frag_now
->fr_literal
;
588 if (Optimizing
) printf("write_L: reloc at %x\n",where
);
589 fix_new_exp (frag_now
,
601 /* write out a short form instruction by itself */
603 write_1_short (opcode
, insn
, fx
)
604 struct d30v_insn
*opcode
;
608 char *f
= frag_more(8);
611 /* the other container needs to be NOP */
612 /* according to 4.3.1: for FM=00, sub-instructions performed only
613 by IU cannot be encoded in L-container. */
614 if (opcode
->op
->unit
== IU
)
615 insn
|= FM00
| ((long long)NOP
<< 32); /* right container */
617 insn
= FM00
| (insn
<< 32) | (long long)NOP
; /* left container */
619 d30v_number_to_chars (f
, insn
, 8);
621 for (i
=0; i
< fx
->fc
; i
++)
623 if (fx
->fix
[i
].reloc
)
625 where
= f
- frag_now
->fr_literal
;
626 if (Optimizing
) printf("write_1: reloc at %x\n",where
);
627 fix_new_exp (frag_now
,
638 /* write out a short form instruction if possible */
639 /* return number of instructions not written out */
641 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
642 struct d30v_insn
*opcode1
, *opcode2
;
643 long long insn1
, insn2
;
651 if (Optimizing
) printf("write_2_short: %llx %llx exec=%d\n",insn1
,insn2
,exec_type
);
653 if(exec_type
!= 1 && (opcode1
->op
->flags_used
== FLAG_JSR
))
655 /* subroutines must be called from 32-bit boundaries */
656 /* so the return address will be correct */
657 write_1_short (opcode1
, insn1
, fx
->next
);
663 case 0: /* order not specified */
664 if ( Optimizing
&& parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
667 if (opcode1
->op
->unit
== IU
)
668 insn
= FM00
| (insn2
<< 32) | insn1
;
669 else if (opcode2
->op
->unit
== MU
)
670 insn
= FM00
| (insn2
<< 32) | insn1
;
673 insn
= FM00
| (insn1
<< 32) | insn2
;
677 else if (opcode1
->op
->unit
== IU
)
679 /* reverse sequential */
680 insn
= FM10
| (insn2
<< 32) | insn1
;
685 insn
= FM01
| (insn1
<< 32) | insn2
;
689 case 1: /* parallel */
690 if (opcode1
->op
->unit
== IU
)
692 if (opcode2
->op
->unit
== IU
)
693 as_fatal ("Two IU instructions may not be executed in parallel");
694 as_warn ("Swapping instruction order");
695 insn
= FM00
| (insn2
<< 32) | insn1
;
697 else if (opcode2
->op
->unit
== MU
)
699 if (opcode1
->op
->unit
== MU
)
700 as_fatal ("Two MU instructions may not be executed in parallel");
701 as_warn ("Swapping instruction order");
702 insn
= FM00
| (insn2
<< 32) | insn1
;
706 insn
= FM00
| (insn1
<< 32) | insn2
;
710 case 2: /* sequential */
711 if (opcode1
->op
->unit
== IU
)
712 as_fatal ("IU instruction may not be in the left container");
713 insn
= FM01
| (insn1
<< 32) | insn2
;
716 case 3: /* reverse sequential */
717 if (opcode2
->op
->unit
== MU
)
718 as_fatal ("MU instruction may not be in the right container");
719 insn
= FM10
| (insn1
<< 32) | insn2
;
723 as_fatal("unknown execution type passed to write_2_short()");
726 /* printf("writing out %llx\n",insn); */
728 d30v_number_to_chars (f
, insn
, 8);
732 for (i
=0; i
< fx
->fc
; i
++)
734 if (fx
->fix
[i
].reloc
)
736 where
= (f
- frag_now
->fr_literal
) + 4*j
;
738 if (Optimizing
) printf("write_2: reloc at %x\n",where
);
739 fix_new_exp (frag_now
,
754 /* Check 2 instructions and determine if they can be safely */
755 /* executed in parallel. Returns 1 if they can be. */
757 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
758 struct d30v_insn
*op1
, *op2
;
759 unsigned long insn1
, insn2
;
763 int i
, j
, flags
, mask
, shift
, regno
;
764 unsigned long ins
, mod
[2], used
[2];
765 struct d30v_insn
*op
;
767 if ((op1
->exec_type
& SEQ
) != 0 || (op2
->exec_type
& SEQ
) != 0
768 || (op1
->exec_type
& PAR
) == 0 || (op2
->exec_type
& PAR
) == 0
769 || (op1
->unit
== BOTH
) || (op2
->unit
== BOTH
)
770 || (op1
->unit
== IU
&& op2
->unit
== IU
)
771 || (op1
->unit
== MU
&& op2
->unit
== MU
))
774 /* If the first instruction is a branch and this is auto parallazation,
775 don't combine with any second instruction. */
776 if (exec_type
== 0 && (op1
->exec_type
& BRANCH
) != 0)
779 /* The idea here is to create two sets of bitmasks (mod and used) */
780 /* which indicate which registers are modified or used by each instruction. */
781 /* The operation can only be done in parallel if instruction 1 and instruction 2 */
782 /* modify different registers, and neither instruction modifies any registers */
783 /* the other is using. Accesses to control registers, PSW, and memory are treated */
784 /* as accesses to a single register. So if both instructions write memory or one */
785 /* instruction writes memory and the other reads, then they cannot be done in parallel. */
786 /* Likewise, if one instruction mucks with the psw and the other reads the PSW */
787 /* (which includes C, F0, and F1), then they cannot operate safely in parallel. */
789 /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
792 /* cr (not psw) 18 */
808 mod
[j
] = used
[j
] = 0;
809 if (op
->exec_type
& BRANCH_LINK
)
812 for (i
= 0; op
->operands
[i
]; i
++)
814 flags
= d30v_operands
[op
->operands
[i
]].flags
;
815 shift
= d30v_operands
[op
->operands
[i
]].shift
;
816 mask
= 0x7FFFFFFF >> (31 - d30v_operands
[op
->operands
[i
]].bits
);
817 if (flags
& OPERAND_REG
)
819 regno
= (ins
>> shift
) & mask
;
820 if (flags
& OPERAND_ACC
)
822 else if (flags
& OPERAND_CONTROL
) /* mvtc or mvfc */
829 else if (flags
& OPERAND_FLAG
)
832 if ( flags
& OPERAND_DEST
)
834 mod
[j
] |= 1 << regno
;
835 if (flags
& OPERAND_EVEN
)
836 mod
[j
] |= 1 << (regno
+ 1);
840 used
[j
] |= 1 << regno
;
841 if (flags
& OPERAND_EVEN
)
842 used
[j
] |= 1 << (regno
+ 1);
846 if (op
->exec_type
& RMEM
)
848 else if (op
->exec_type
& WMEM
)
850 else if (op
->exec_type
& RF0
)
852 else if (op
->exec_type
& WF0
)
854 else if (op
->exec_type
& WCAR
)
857 if ((mod
[0] & mod
[1]) == 0 && (mod
[0] & used
[1]) == 0 && (mod
[1] & used
[0]) == 0)
865 /* This is the main entry point for the machine-dependent assembler. str points to a
866 machine-dependent instruction. This function is supposed to emit the frags/bytes
867 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
868 and leaves the difficult stuff to do_assemble().
871 static long long prev_insn
= -1;
872 static struct d30v_insn prev_opcode
;
873 static subsegT prev_subseg
;
874 static segT prev_seg
= 0;
880 struct d30v_insn opcode
;
882 int extype
=0; /* execution type; parallel, etc */
883 static int etype
=0; /* saved extype. used for multiline instructions */
888 /* look for the special multiple instruction separators */
889 str2
= strstr (str
, "||");
894 str2
= strstr (str
, "->");
899 str2
= strstr (str
, "<-");
904 /* str2 points to the separator, if one */
909 /* if two instructions are present and we already have one saved
910 then first write it out */
913 /* assemble first instruction and save it */
914 prev_insn
= do_assemble (str
, &prev_opcode
);
916 as_fatal ("can't find opcode ");
917 fixups
= fixups
->next
;
922 insn
= do_assemble (str
, &opcode
);
930 as_fatal ("can't find opcode ");
939 /* if this is a long instruction, write it and any previous short instruction */
940 if (opcode
.form
->form
>= LONG
)
943 as_fatal("Unable to mix instructions as specified");
945 write_long (&opcode
, insn
, fixups
);
950 if ( (prev_insn
!= -1) && prev_seg
&& ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
953 if ( (prev_insn
!= -1) &&
954 (write_2_short (&prev_opcode
, (long)prev_insn
, &opcode
, (long)insn
, extype
, fixups
) == 0))
956 /* no instructions saved */
962 as_fatal("Unable to mix instructions as specified");
963 /* save off last instruction so it may be packed on next pass */
964 memcpy( &prev_opcode
, &opcode
, sizeof(prev_opcode
));
967 prev_subseg
= now_subseg
;
968 fixups
= fixups
->next
;
973 /* do_assemble assembles a single instruction and returns an opcode */
974 /* it returns -1 (an invalid opcode) on error */
977 do_assemble (str
, opcode
)
979 struct d30v_insn
*opcode
;
981 unsigned char *op_start
, *save
;
982 unsigned char *op_end
;
984 int cmp_hack
, nlen
= 0;
985 expressionS myops
[6];
988 if (Optimizing
) printf("do_assemble %s\n",str
);
990 /* Drop leading whitespace */
994 /* find the opcode end */
995 for (op_start
= op_end
= (unsigned char *) (str
);
999 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1002 name
[nlen
] = tolower(op_start
[nlen
]);
1011 /* if there is an execution condition code, handle it */
1015 while ( (i
< ECC_MAX
) && strncasecmp(d30v_ecc_names
[i
],op_end
+1,2))
1021 strncpy(tmp
,op_end
+1,2);
1023 as_fatal ("unknown condition code: %s",tmp
);
1026 /* printf("condition code=%d\n",i); */
1031 opcode
->ecc
= ECC_AL
;
1034 /* CMP and CMPU change their name based on condition codes */
1035 if (!strncmp(name
,"cmp",3))
1038 char **str
= (char **)d30v_cc_names
;
1044 for(i
=1; *str
&& strncmp(*str
,&name
[p
],2); i
++, *str
++)
1050 as_fatal ("unknown condition code: %s",&name
[p
]);
1059 /* printf("cmp_hack=%d\n",cmp_hack); */
1061 /* find the first opcode with the proper name */
1062 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1063 if (opcode
->op
== NULL
)
1064 as_fatal ("unknown opcode: %s",name
);
1066 save
= input_line_pointer
;
1067 input_line_pointer
= op_end
;
1068 while (!(opcode
->form
= find_format (opcode
->op
, myops
, cmp_hack
)))
1071 if (strcmp(opcode
->op
->name
,name
))
1074 input_line_pointer
= save
;
1076 insn
= build_insn (opcode
, myops
);
1077 if (Optimizing
) printf("insn=%llx\n",insn
);
1082 /* find_format() gets a pointer to an entry in the format table. */
1083 /* It must look at all formats for an opcode and use the operands */
1084 /* to choose the correct one. Returns NULL on error. */
1086 static struct d30v_format
*
1087 find_format (opcode
, myops
, cmp_hack
)
1088 struct d30v_opcode
*opcode
;
1089 expressionS myops
[];
1092 int numops
, match
, index
, i
=0, j
, k
;
1093 struct d30v_format
*fm
;
1094 struct d30v_operand
*op
;
1096 if (Optimizing
) printf("find_format: %s\n",opcode
->name
);
1098 /* get all the operands and save them as expressions */
1099 numops
= get_operands (myops
, cmp_hack
);
1101 while (index
= opcode
->format
[i
++])
1103 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1105 while (fm
->form
== index
)
1108 /* now check the operands for compatibility */
1109 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1111 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1112 int X_op
= myops
[j
].X_op
;
1113 int num
= myops
[j
].X_add_number
;
1115 if (Optimizing
) printf("form=%d mod=%d opnum=%d flags=%x X_op=%d num=%d\n",index
,fm
->modifier
,j
,flags
,X_op
,num
);
1116 if ( flags
& OPERAND_SPECIAL
)
1120 else if (flags
& OPERAND_REG
)
1122 if ((X_op
!= O_register
) ||
1123 ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
)) ||
1124 ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
)) ||
1125 (flags
& OPERAND_CONTROL
&& !(num
& OPERAND_CONTROL
| num
& OPERAND_FLAG
)))
1128 if (Optimizing
) printf("failed 1\n");
1132 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
1133 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
1134 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
1135 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
1136 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATSIGN
))))
1138 if (Optimizing
) printf("failed 2\n");
1141 else if (flags
& OPERAND_NUM
)
1143 /* a number can be a constant or symbol expression */
1144 if (fm
->form
>= LONG
)
1146 /* If we're testing for a LONG format, either fits */
1147 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1150 /* This is the tricky part. Will the constant or symbol */
1151 /* fit into the space in the current format? */
1152 else if (X_op
== O_constant
)
1154 if (check_range (num
, d30v_operand_table
[fm
->operands
[j
]].bits
, flags
))
1157 else if (X_op
== O_symbol
&& S_IS_DEFINED(myops
[j
].X_add_symbol
) &&
1158 (S_GET_SEGMENT(myops
[j
].X_add_symbol
) == now_seg
))
1160 /* if the symbol is defined, see if the value will fit */
1161 /* into the form we're considering */
1164 /* calculate the current address by running through the previous frags */
1165 /* and adding our current offset */
1166 for (value
= 0, f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1167 value
+= f
->fr_fix
+ f
->fr_offset
;
1168 if (Optimizing
) printf("offset=%d (0x%x) value=%d (0x%x)\n",value
,value
,
1169 S_GET_VALUE(myops
[j
].X_add_symbol
),S_GET_VALUE(myops
[j
].X_add_symbol
) );
1170 if (opcode
->reloc_flag
== RELOC_PCREL
)
1171 value
= S_GET_VALUE(myops
[j
].X_add_symbol
) - value
-
1172 (obstack_next_free(&frchain_now
->frch_obstack
) - frag_now
->fr_literal
);
1174 value
= S_GET_VALUE(myops
[j
].X_add_symbol
);
1175 if (Optimizing
) printf("symbol value=%d (0x%x) reloc=%d\n",value
,value
,opcode
->reloc_flag
);
1176 if (check_range (value
, d30v_operand_table
[fm
->operands
[j
]].bits
, flags
))
1178 if (Optimizing
) printf("match=%d\n",match
);
1184 /* printf("through the loop: match=%d\n",match); */
1185 /* we're only done if the operands matched so far AND there
1186 are no more to check */
1187 if (match
&& myops
[j
].X_op
==0)
1190 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1192 /* printf("trying another format: i=%d\n",i); */
1197 /* if while processing a fixup, a reloc really needs to be created */
1198 /* then it is done here */
1201 tc_gen_reloc (seg
, fixp
)
1206 reloc
= (arelent
*) bfd_alloc_by_size_t (stdoutput
, sizeof (arelent
));
1207 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1208 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1209 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1210 if (Optimizing
) printf("tc_gen_reloc: addr=%x howto=%x\n",reloc
->address
,reloc
->howto
);
1211 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1213 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1214 "reloc %d not supported by object file format", (int)fixp
->fx_r_type
);
1217 reloc
->addend
= fixp
->fx_addnumber
;
1222 md_estimate_size_before_relax (fragp
, seg
)
1231 md_pcrel_from_section (fixp
, sec
)
1235 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& !S_IS_DEFINED (fixp
->fx_addsy
))
1237 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1241 md_apply_fix3 (fixp
, valuep
, seg
)
1247 unsigned long insn
, insn2
;
1252 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1257 else if (!S_IS_DEFINED(fixp
->fx_addsy
))
1259 else if (fixp
->fx_pcrel
)
1262 if (Optimizing
) printf("value=0x%lx\n",value
);
1265 value
= fixp
->fx_offset
;
1266 if (Optimizing
) printf("Value=0x%lx\n",value
);
1267 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1269 if (Optimizing
) printf("subsy != NULL\n");
1270 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1271 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1274 /* We don't actually support subtracting a symbol. */
1275 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1276 "expression too complex");
1281 /* Fetch the instruction, insert the fully resolved operand
1282 value, and stuff the instruction back again. */
1283 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1284 insn
= bfd_getb32 ((unsigned char *) where
);
1286 if (Optimizing
) printf("md_apply_fix3: type=%ld where=%lx insn=%lx value=%lx\n",fixp
->fx_r_type
,where
,insn
,value
);
1287 switch (fixp
->fx_r_type
)
1289 case BFD_RELOC_D30V_6
:
1290 if (Optimizing
) printf("BFD_RELOC_D30V_6\n");
1291 insn
|= value
& 0x3F;
1292 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1294 case BFD_RELOC_D30V_15
:
1295 if (Optimizing
) printf("BFD_RELOC_D30V_15\n");
1296 insn
|= (value
>> 3) & 0xFFF;
1297 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1299 case BFD_RELOC_D30V_15_PCREL
:
1300 if ((long)fixp
->fx_where
& 0x7)
1302 if (Optimizing
) printf("BFD_RELOC_D30V_15_PCREL\n");
1303 insn
|= (value
>> 3) & 0xFFF;
1304 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1306 case BFD_RELOC_D30V_21
:
1307 if (Optimizing
) printf("BFD_RELOC_D30V_21\n");
1308 insn
|= (value
>> 3) & 0x3FFFF;
1309 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1311 case BFD_RELOC_D30V_21_PCREL
:
1312 if ((long)fixp
->fx_where
& 0x7)
1314 if (Optimizing
) printf("BFD_RELOC_D30V_21_PCREL: insn=%lx value=%lx\n",insn
,(long)value
);
1315 insn
|= (value
>> 3) & 0x3FFFF;
1316 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1318 case BFD_RELOC_D30V_32
:
1319 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1320 if (Optimizing
) printf("BFD_RELOC_D30V_32: insn=0x%08x%08x\n",(int)insn
,(int)insn2
);
1321 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1322 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1323 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1324 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1325 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1327 case BFD_RELOC_D30V_32_PCREL
:
1328 if ((long)fixp
->fx_where
& 0x7)
1330 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1331 if (Optimizing
) printf("BFD_RELOC_D30V_32_PCREL: insn=0x%08x%08x\n",(int)insn
,(int)insn2
);
1332 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1333 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1334 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1335 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1336 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1339 if (Optimizing
) printf("BFD_RELOC_32: insn=0x%08x value=0x%x\n",(int)insn
,(int)value
);
1340 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1343 as_fatal ("line %d: unknown relocation type: 0x%x",fixp
->fx_line
,fixp
->fx_r_type
);
1350 /* d30v_cleanup() is called after the assembler has finished parsing the input
1351 file or after a label is defined. Because the D30V assembler sometimes saves short
1352 instructions to see if it can package them with the next instruction, there may
1353 be a short instruction that still needs written. */
1360 if (prev_insn
!= -1)
1363 subseg
= now_subseg
;
1364 subseg_set (prev_seg
, prev_subseg
);
1365 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
);
1366 subseg_set (seg
, subseg
);
1374 d30v_number_to_chars (buf
, value
, n
)
1375 char *buf
; /* Return 'nbytes' of chars here. */
1376 long long value
; /* The value of the bits. */
1377 int n
; /* Number of bytes in the output. */
1381 buf
[n
] = value
& 0xff;