1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
3 Copyright (C) 1997, 1998 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d30v.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "OnNcC";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
35 #define NOP_MULTIPLY 1
37 static int warn_nops
= 0;
38 static int Optimizing
= 0;
39 static int warn_register_name_conflicts
= 1;
45 typedef enum _exec_type
47 EXEC_UNKNOWN
, /* no order specified */
48 EXEC_PARALLEL
, /* done in parallel (FM=00) */
49 EXEC_SEQ
, /* sequential (FM=01) */
50 EXEC_REVSEQ
/* reverse sequential (FM=10) */
54 #define MAX_INSN_FIXUPS (5)
61 bfd_reloc_code_real_type reloc
;
64 typedef struct _fixups
67 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
71 static Fixups FixUps
[2];
72 static Fixups
*fixups
;
74 /* Whether current and previous instruction is a word multiply. */
75 static int cur_mul32_p
= 0;
76 static int prev_mul32_p
= 0;
78 /* The flag_explicitly_parallel is true iff the instruction being assembled
79 has been explicitly written as a parallel short-instruction pair by the
80 human programmer. It is used in parallel_ok() to distinguish between
81 those dangerous parallelizations attempted by the human, which are to be
82 allowed, and those attempted by the assembler, which are not. It is set
83 from md_assemble(). */
84 static int flag_explicitly_parallel
= 0;
85 static int flag_xp_state
= 0;
87 /* Whether current and previous left sub-instruction disables
88 execution of right sub-instruction. */
89 static int cur_left_kills_right_p
= 0;
90 static int prev_left_kills_right_p
= 0;
92 /* The known current alignment of the current section. */
93 static int d30v_current_align
;
94 static segT d30v_current_align_seg
;
96 /* The last seen label in the current section. This is used to auto-align
97 labels preceeding instructions. */
98 static symbolS
*d30v_last_label
;
101 #define NOP_LEFT ((long long)NOP << 32)
102 #define NOP_RIGHT ((long long)NOP)
103 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
105 /* local functions */
106 static int reg_name_search
PARAMS ((char *name
));
107 static int register_name
PARAMS ((expressionS
*expressionP
));
108 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
109 static int postfix
PARAMS ((char *p
));
110 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
111 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
112 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
,
113 expressionS ops
[],int fsize
, int cmp_hack
));
114 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
115 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
116 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
,
117 Fixups
*fx
, int use_sequential
));
118 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
119 struct d30v_insn
*opcode2
, long long insn2
, exec_type_enum exec_type
, Fixups
*fx
));
120 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
,
121 int shortp
, int is_parallel
));
122 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
123 struct d30v_insn
*opcode2
, unsigned long insn2
,
124 exec_type_enum exec_type
));
125 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
126 static void check_size
PARAMS ((long value
, int bits
, char *file
, int line
));
127 static void d30v_align
PARAMS ((int, char *, symbolS
*));
128 static void s_d30v_align
PARAMS ((int));
129 static void s_d30v_text
PARAMS ((int));
130 static void s_d30v_data
PARAMS ((int));
131 static void s_d30v_section
PARAMS ((int));
133 struct option md_longopts
[] = {
134 {NULL
, no_argument
, NULL
, 0}
136 size_t md_longopts_size
= sizeof(md_longopts
);
139 /* The target specific pseudo-ops which we support. */
140 const pseudo_typeS md_pseudo_table
[] =
143 { "hword", cons
, 2 },
144 { "align", s_d30v_align
, 0 },
145 { "text", s_d30v_text
, 0 },
146 { "data", s_d30v_data
, 0 },
147 { "section", s_d30v_section
, 0 },
148 { "section.s", s_d30v_section
, 0 },
149 { "sect", s_d30v_section
, 0 },
150 { "sect.s", s_d30v_section
, 0 },
154 /* Opcode hash table. */
155 static struct hash_control
*d30v_hash
;
157 /* reg_name_search does a binary search of the pre_defined_registers
158 array to see if "name" is a valid regiter name. Returns the register
159 number from the array on success, or -1 on failure. */
162 reg_name_search (name
)
165 int middle
, low
, high
;
169 high
= reg_name_cnt () - 1;
171 if (symbol_find (name
) != NULL
)
173 if (warn_register_name_conflicts
)
174 as_warn ("Register name %s conflicts with symbol of the same name",
180 middle
= (low
+ high
) / 2;
181 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
187 return pre_defined_registers
[middle
].value
;
194 /* register_name() checks the string at input_line_pointer
195 to see if it is a valid register name */
198 register_name (expressionP
)
199 expressionS
*expressionP
;
202 char c
, *p
= input_line_pointer
;
204 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
211 /* look to see if it's in the register table */
212 reg_number
= reg_name_search (input_line_pointer
);
215 expressionP
->X_op
= O_register
;
216 /* temporarily store a pointer to the string here */
217 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
218 expressionP
->X_add_number
= reg_number
;
219 input_line_pointer
= p
;
229 check_range (num
, bits
, flags
)
237 /* don't bother checking 32-bit values */
241 if (flags
& OPERAND_SHIFT
)
243 /* We know that all shifts are right by three bits.... */
245 if (flags
& OPERAND_SIGNED
)
246 num
= (unsigned long) (((/*signed*/ long) num
) >> 3);
251 if (flags
& OPERAND_SIGNED
)
253 max
= (1 << (bits
- 1))-1;
254 min
= - (1 << (bits
- 1));
255 if (((long)num
> max
) || ((long)num
< min
))
260 max
= (1 << bits
) - 1;
262 if ((num
> max
) || (num
< min
))
270 md_show_usage (stream
)
273 fprintf (stream
, _("\nD30V options:\n\
274 -O Make adjacent short instructions parallel if possible.\n\
275 -n Warn about all NOPs inserted by the assembler.\n\
276 -N Warn about NOPs inserted after word multiplies.\n\
277 -c Warn about symbols whoes names match register names.\n\
278 -C Opposite of -C. -c is the default.\n"));
282 md_parse_option (c
, arg
)
288 /* Optimize. Will attempt to parallelize operations */
293 /* Warn about all NOPS that the assembler inserts. */
298 /* Warn about the NOPS that the assembler inserts because of the
301 warn_nops
= NOP_MULTIPLY
;
305 warn_register_name_conflicts
= 1;
309 warn_register_name_conflicts
= 0;
319 md_undefined_symbol (name
)
325 /* Turn a string in input_line_pointer into a floating point constant of type
326 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
327 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
330 md_atof (type
, litP
, sizeP
)
336 LITTLENUM_TYPE words
[4];
350 return _("bad call to md_atof");
353 t
= atof_ieee (input_line_pointer
, type
, words
);
355 input_line_pointer
= t
;
359 for (i
= 0; i
< prec
; i
++)
361 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
368 md_convert_frag (abfd
, sec
, fragP
)
377 md_section_align (seg
, addr
)
381 int align
= bfd_get_section_alignment (stdoutput
, seg
);
382 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
389 struct d30v_opcode
*opcode
;
390 d30v_hash
= hash_new ();
392 /* Insert opcode names into a hash table. */
393 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
394 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
397 FixUps
[0].next
= &FixUps
[1];
398 FixUps
[1].next
= &FixUps
[0];
400 d30v_current_align_seg
= now_seg
;
404 /* this function removes the postincrement or postdecrement
405 operator ( '+' or '-' ) from an expression */
407 static int postfix (p
)
410 while (*p
!= '-' && *p
!= '+')
412 if (*p
==0 || *p
=='\n' || *p
=='\r' || *p
==' ' || *p
==',')
432 static bfd_reloc_code_real_type
433 get_reloc (op
, rel_flag
)
434 struct d30v_operand
*op
;
440 if (op
->flags
& OPERAND_SHIFT
)
441 return BFD_RELOC_D30V_9_PCREL
;
443 return BFD_RELOC_D30V_6
;
446 if (!(op
->flags
& OPERAND_SHIFT
))
447 as_warn (_("unexpected 12-bit reloc type"));
448 if (rel_flag
== RELOC_PCREL
)
449 return BFD_RELOC_D30V_15_PCREL
;
451 return BFD_RELOC_D30V_15
;
453 if (!(op
->flags
& OPERAND_SHIFT
))
454 as_warn (_("unexpected 18-bit reloc type"));
455 if (rel_flag
== RELOC_PCREL
)
456 return BFD_RELOC_D30V_21_PCREL
;
458 return BFD_RELOC_D30V_21
;
460 if (rel_flag
== RELOC_PCREL
)
461 return BFD_RELOC_D30V_32_PCREL
;
463 return BFD_RELOC_D30V_32
;
469 /* get_operands parses a string of operands and returns
470 an array of expressions */
473 get_operands (exp
, cmp_hack
)
477 char *p
= input_line_pointer
;
483 exp
[numops
].X_op
= O_absent
;
484 exp
[numops
++].X_add_number
= cmp_hack
- 1;
489 while (*p
== ' ' || *p
== '\t' || *p
== ',')
491 if (*p
==0 || *p
=='\n' || *p
=='\r')
497 exp
[numops
].X_op
= O_absent
;
501 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
507 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
511 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
520 /* just skip the trailing paren */
525 input_line_pointer
= p
;
527 /* check to see if it might be a register name */
528 if (!register_name (&exp
[numops
]))
530 /* parse as an expression */
531 expression (&exp
[numops
]);
534 if (exp
[numops
].X_op
== O_illegal
)
535 as_bad (_("illegal operand"));
536 else if (exp
[numops
].X_op
== O_absent
)
537 as_bad (_("missing operand"));
540 p
= input_line_pointer
;
544 case -1: /* postdecrement mode */
545 exp
[numops
].X_op
= O_absent
;
546 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
548 case 1: /* postincrement mode */
549 exp
[numops
].X_op
= O_absent
;
550 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
556 exp
[numops
].X_op
= 0;
560 /* build_insn generates the instruction. It does everything */
561 /* but write the FM bits. */
564 build_insn (opcode
, opers
)
565 struct d30v_insn
*opcode
;
568 int i
, length
, bits
, shift
, flags
;
569 unsigned int number
, id
=0;
571 struct d30v_opcode
*op
= opcode
->op
;
572 struct d30v_format
*form
= opcode
->form
;
574 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
576 for (i
=0; form
->operands
[i
]; i
++)
578 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
580 /* must be a register or number */
581 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
582 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
585 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
586 if (flags
& OPERAND_SHIFT
)
589 length
= d30v_operand_table
[form
->operands
[i
]].length
;
590 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
591 if (opers
[i
].X_op
!= O_symbol
)
592 number
= opers
[i
].X_add_number
;
595 if (flags
& OPERAND_REG
)
597 /* check for mvfsys or mvtsys control registers */
598 if (flags
& OPERAND_CONTROL
&& (number
& 0x7f) > MAX_CONTROL_REG
)
601 id
= (number
& 0x7f) - MAX_CONTROL_REG
;
604 else if (number
& OPERAND_FLAG
)
606 id
= 3; /* number is a flag register */
610 else if (flags
& OPERAND_SPECIAL
)
615 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
617 /* now create a fixup */
619 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
620 as_fatal (_("too many fixups"));
622 fixups
->fix
[fixups
->fc
].reloc
=
623 get_reloc ((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
624 fixups
->fix
[fixups
->fc
].size
= 4;
625 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
626 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
627 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D30V_9_PCREL
)
628 fixups
->fix
[fixups
->fc
].pcrel
= RELOC_PCREL
;
630 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
634 /* truncate to the proper number of bits */
635 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
636 as_bad (_("operand out of range: %d"),number
);
638 number
&= 0x7FFFFFFF >> (31 - bits
);
639 if (flags
& OPERAND_SHIFT
)
643 /* it's a LONG instruction */
644 insn
|= (number
>> 26); /* top 6 bits */
645 insn
<<= 32; /* shift the first word over */
646 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
647 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
650 insn
|= number
<< shift
;
656 /* write out a long form instruction */
658 write_long (opcode
, insn
, fx
)
659 struct d30v_insn
*opcode
;
664 char *f
= frag_more (8);
667 d30v_number_to_chars (f
, insn
, 8);
669 for (i
=0; i
< fx
->fc
; i
++)
671 if (fx
->fix
[i
].reloc
)
673 where
= f
- frag_now
->fr_literal
;
674 fix_new_exp (frag_now
,
686 /* Write out a short form instruction by itself. */
688 write_1_short (opcode
, insn
, fx
, use_sequential
)
689 struct d30v_insn
*opcode
;
694 char *f
= frag_more (8);
697 if (warn_nops
== NOP_ALL
)
698 as_warn (_("%s NOP inserted"), use_sequential
?
699 _("sequential") : _("parallel"));
701 /* The other container needs to be NOP. */
704 /* Use a sequential NOP rather than a parallel one,
705 as the current instruction is a FLAG_MUL32 type one
706 and the next instruction is a load. */
708 /* According to 4.3.1: for FM=01, sub-instructions performed
709 only by IU cannot be encoded in L-container. */
711 if (opcode
->op
->unit
== IU
)
712 insn
|= FM10
| NOP_LEFT
; /* right then left */
714 insn
= FM01
| (insn
<< 32) | NOP_RIGHT
; /* left then right */
718 /* According to 4.3.1: for FM=00, sub-instructions performed
719 only by IU cannot be encoded in L-container. */
721 if (opcode
->op
->unit
== IU
)
722 insn
|= FM00
| NOP_LEFT
; /* right container */
724 insn
= FM00
| (insn
<< 32) | NOP_RIGHT
; /* left container */
727 d30v_number_to_chars (f
, insn
, 8);
729 for (i
=0; i
< fx
->fc
; i
++)
731 if (fx
->fix
[i
].reloc
)
733 where
= f
- frag_now
->fr_literal
;
734 fix_new_exp (frag_now
,
745 /* write out a short form instruction if possible */
746 /* return number of instructions not written out */
748 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
749 struct d30v_insn
*opcode1
, *opcode2
;
750 long long insn1
, insn2
;
751 exec_type_enum exec_type
;
754 long long insn
= NOP2
;
758 if (exec_type
!= EXEC_PARALLEL
&&
759 ((opcode1
->op
->flags_used
& (FLAG_JSR
| FLAG_DELAY
)) == FLAG_JSR
))
761 /* subroutines must be called from 32-bit boundaries */
762 /* so the return address will be correct */
763 write_1_short (opcode1
, insn1
, fx
->next
, false);
769 case EXEC_UNKNOWN
: /* order not specified */
770 if (Optimizing
&& parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
773 exec_type
= EXEC_PARALLEL
;
774 if (opcode1
->op
->unit
== IU
)
775 insn
= FM00
| (insn2
<< 32) | insn1
;
776 else if (opcode2
->op
->unit
== MU
)
777 insn
= FM00
| (insn2
<< 32) | insn1
;
780 insn
= FM00
| (insn1
<< 32) | insn2
;
784 else if (opcode1
->op
->unit
== IU
)
786 /* reverse sequential */
787 insn
= FM10
| (insn2
<< 32) | insn1
;
788 exec_type
= EXEC_REVSEQ
;
793 insn
= FM01
| (insn1
<< 32) | insn2
;
795 exec_type
= EXEC_SEQ
;
799 case EXEC_PARALLEL
: /* parallel */
800 flag_explicitly_parallel
= flag_xp_state
;
801 if (! parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
802 as_fatal (_("Instructions may not be executed in parallel"));
803 else if (opcode1
->op
->unit
== IU
)
805 if (opcode2
->op
->unit
== IU
)
806 as_fatal (_("Two IU instructions may not be executed in parallel"));
807 as_warn (_("Swapping instruction order"));
808 insn
= FM00
| (insn2
<< 32) | insn1
;
810 else if (opcode2
->op
->unit
== MU
)
812 if (opcode1
->op
->unit
== MU
)
813 as_fatal (_("Two MU instructions may not be executed in parallel"));
814 as_warn (_("Swapping instruction order"));
815 insn
= FM00
| (insn2
<< 32) | insn1
;
819 insn
= FM00
| (insn1
<< 32) | insn2
;
822 flag_explicitly_parallel
= 0;
825 case EXEC_SEQ
: /* sequential */
826 if (opcode1
->op
->unit
== IU
)
827 as_fatal (_("IU instruction may not be in the left container"));
828 if (prev_left_kills_right_p
)
829 as_warn (_("special left instruction `%s' kills instruction "
830 "`%s' in right container"),
831 opcode1
->op
->name
, opcode2
->op
->name
);
832 insn
= FM01
| (insn1
<< 32) | insn2
;
836 case EXEC_REVSEQ
: /* reverse sequential */
837 if (opcode2
->op
->unit
== MU
)
838 as_fatal (_("MU instruction may not be in the right container"));
839 insn
= FM10
| (insn1
<< 32) | insn2
;
844 as_fatal (_("unknown execution type passed to write_2_short()"));
847 /* printf("writing out %llx\n",insn); */
849 d30v_number_to_chars (f
, insn
, 8);
851 /* If the previous instruction was a 32-bit multiply but it is put into a
852 parallel container, mark the current instruction as being a 32-bit
854 if (prev_mul32_p
&& exec_type
== EXEC_PARALLEL
)
859 for (i
=0; i
< fx
->fc
; i
++)
861 if (fx
->fix
[i
].reloc
)
863 where
= (f
- frag_now
->fr_literal
) + 4*j
;
865 fix_new_exp (frag_now
,
880 /* Check 2 instructions and determine if they can be safely */
881 /* executed in parallel. Returns 1 if they can be. */
883 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
884 struct d30v_insn
*op1
, *op2
;
885 unsigned long insn1
, insn2
;
886 exec_type_enum exec_type
;
888 int i
, j
, shift
, regno
, bits
, ecc
;
889 unsigned long flags
, mask
, flags_set1
, flags_set2
, flags_used1
, flags_used2
;
890 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3], flag_reg
[2];
891 struct d30v_format
*f
;
892 struct d30v_opcode
*op
;
894 /* section 4.3: both instructions must not be IU or MU only */
895 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
896 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
899 /* first instruction must not be a jump to safely optimize, unless this
900 is an explicit parallel operation. */
901 if (exec_type
!= EXEC_PARALLEL
902 && (op1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)))
905 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
906 then it is safe to allow the two to be done as parallel ops, since only
907 one will ever be executed at a time. */
908 if ((op1
->ecc
== ECC_TX
&& op2
->ecc
== ECC_FX
)
909 || (op1
->ecc
== ECC_FX
&& op2
->ecc
== ECC_TX
)
910 || (op1
->ecc
== ECC_XT
&& op2
->ecc
== ECC_XF
)
911 || (op1
->ecc
== ECC_XF
&& op2
->ecc
== ECC_XT
))
916 [2] a0, a1, flag registers */
918 for (j
= 0; j
< 2; j
++)
935 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
936 mod_reg
[j
][2] = (op
->flags_set
& FLAG_ALL
);
937 used_reg
[j
][0] = used_reg
[j
][1] = 0;
938 used_reg
[j
][2] = (op
->flags_used
& FLAG_ALL
);
940 /* BSR/JSR always sets R62 */
941 if (op
->flags_used
& FLAG_JSR
)
942 mod_reg
[j
][1] = (1L << (62-32));
944 /* conditional execution affects the flags_used */
949 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_0
;
954 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_1
;
959 used_reg
[j
][2] |= flag_reg
[j
] = (FLAG_0
| FLAG_1
);
963 for (i
= 0; f
->operands
[i
]; i
++)
965 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
966 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
967 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
971 mask
= 0x7FFFFFFF >> (31 - bits
);
973 if ((flags
& OPERAND_PLUS
) || (flags
& OPERAND_MINUS
))
975 /* this is a post-increment or post-decrement */
976 /* the previous register needs to be marked as modified */
978 shift
= 12 - d30v_operand_table
[f
->operands
[i
-1]].position
;
979 regno
= (ins
>> shift
) & 0x3f;
981 mod_reg
[j
][1] |= 1L << (regno
- 32);
983 mod_reg
[j
][0] |= 1L << regno
;
985 else if (flags
& OPERAND_REG
)
987 regno
= (ins
>> shift
) & mask
;
988 /* the memory write functions don't have a destination register */
989 if ((flags
& OPERAND_DEST
) && !(op
->flags_set
& FLAG_MEM
))
991 /* MODIFIED registers and flags */
992 if (flags
& OPERAND_ACC
)
995 mod_reg
[j
][2] |= FLAG_A0
;
997 mod_reg
[j
][2] |= FLAG_A1
;
1001 else if (flags
& OPERAND_FLAG
)
1002 mod_reg
[j
][2] |= 1L << regno
;
1003 else if (!(flags
& OPERAND_CONTROL
))
1007 /* need to check if there are two destination */
1008 /* registers, for example ld2w */
1009 if (flags
& OPERAND_2REG
)
1014 for (r
= regno
; r
<= regno
+ z
; r
++)
1017 mod_reg
[j
][1] |= 1L << (r
- 32);
1019 mod_reg
[j
][0] |= 1L << r
;
1025 /* USED, but not modified registers and flags */
1026 if (flags
& OPERAND_ACC
)
1029 used_reg
[j
][2] |= FLAG_A0
;
1030 else if (regno
== 1)
1031 used_reg
[j
][2] |= FLAG_A1
;
1035 else if (flags
& OPERAND_FLAG
)
1036 used_reg
[j
][2] |= 1L << regno
;
1037 else if (!(flags
& OPERAND_CONTROL
))
1041 /* need to check if there are two source */
1042 /* registers, for example st2w */
1043 if (flags
& OPERAND_2REG
)
1048 for (r
= regno
; r
<= regno
+ z
; r
++)
1051 used_reg
[j
][1] |= 1L << (r
- 32);
1053 used_reg
[j
][0] |= 1L << r
;
1061 flags_set1
= op1
->op
->flags_set
;
1062 flags_set2
= op2
->op
->flags_set
;
1063 flags_used1
= op1
->op
->flags_used
;
1064 flags_used2
= op2
->op
->flags_used
;
1066 /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */
1067 if (((flags_set1
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1068 && (flags_used2
& FLAG_ADDSUBppp
) != 0)
1069 || ((flags_set2
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1070 && (flags_used1
& FLAG_ADDSUBppp
) != 0))
1073 /* Load instruction combined with half-word multiply is illegal. */
1074 if (((flags_used1
& FLAG_MEM
) != 0 && (flags_used2
& FLAG_MUL16
))
1075 || ((flags_used2
& FLAG_MEM
) != 0 && (flags_used1
& FLAG_MUL16
)))
1078 /* Specifically allow add || add by removing carry, overflow bits dependency.
1079 This is safe, even if an addc follows since the IU takes the argument in
1080 the right container, and it writes its results last.
1081 However, don't paralellize add followed by addc or sub followed by
1084 if (mod_reg
[0][2] == FLAG_CVVA
&& mod_reg
[1][2] == FLAG_CVVA
1085 && (used_reg
[0][2] & ~flag_reg
[0]) == 0
1086 && (used_reg
[1][2] & ~flag_reg
[1]) == 0
1087 && op1
->op
->unit
== EITHER
&& op2
->op
->unit
== EITHER
)
1089 mod_reg
[0][2] = mod_reg
[1][2] = 0;
1092 for (j
= 0; j
< 3; j
++)
1094 /* If the second instruction depends on the first, we obviously
1095 cannot parallelize. Note, the mod flag implies use, so
1096 check that as well. */
1097 /* If flag_explicitly_parallel is set, then the case of the
1098 second instruction using a register the first instruction
1099 modifies is assumed to be okay; we trust the human. We
1100 don't trust the human if both instructions modify the same
1101 register but we do trust the human if they modify the same
1103 if (flag_explicitly_parallel
)
1105 if ((j
< 2) && (mod_reg
[0][j
] & mod_reg
[1][j
]) != 0)
1109 if ((mod_reg
[0][j
] & (mod_reg
[1][j
] | used_reg
[1][j
])) != 0)
1118 /* This is the main entry point for the machine-dependent assembler. str points to a
1119 machine-dependent instruction. This function is supposed to emit the frags/bytes
1120 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
1121 and leaves the difficult stuff to do_assemble(). */
1123 static long long prev_insn
= -1;
1124 static struct d30v_insn prev_opcode
;
1125 static subsegT prev_subseg
;
1126 static segT prev_seg
= 0;
1132 struct d30v_insn opcode
;
1134 exec_type_enum extype
= EXEC_UNKNOWN
; /* execution type; parallel, etc */
1135 static exec_type_enum etype
= EXEC_UNKNOWN
; /* saved extype. used for multiline instructions */
1138 if ((prev_insn
!= -1) && prev_seg
1139 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1140 d30v_cleanup (false);
1142 if (d30v_current_align
< 3)
1143 d30v_align (3, NULL
, d30v_last_label
);
1144 else if (d30v_current_align
> 3)
1145 d30v_current_align
= 3;
1146 d30v_last_label
= NULL
;
1148 flag_explicitly_parallel
= 0;
1150 if (etype
== EXEC_UNKNOWN
)
1152 /* look for the special multiple instruction separators */
1153 str2
= strstr (str
, "||");
1156 extype
= EXEC_PARALLEL
;
1161 str2
= strstr (str
, "->");
1166 str2
= strstr (str
, "<-");
1168 extype
= EXEC_REVSEQ
;
1171 /* str2 points to the separator, if one */
1176 /* if two instructions are present and we already have one saved
1177 then first write it out */
1178 d30v_cleanup (false);
1180 /* assemble first instruction and save it */
1181 prev_insn
= do_assemble (str
, &prev_opcode
, 1, 0);
1182 if (prev_insn
== -1)
1183 as_fatal (_("Cannot assemble instruction"));
1184 if (prev_opcode
.form
->form
>= LONG
)
1185 as_fatal (_("First opcode is long. Unable to mix instructions as specified."));
1186 fixups
= fixups
->next
;
1189 prev_subseg
= now_subseg
;
1193 insn
= do_assemble (str
, &opcode
,
1194 (extype
!= EXEC_UNKNOWN
|| etype
!= EXEC_UNKNOWN
),
1195 extype
== EXEC_PARALLEL
);
1198 if (extype
!= EXEC_UNKNOWN
)
1203 as_fatal (_("Cannot assemble instruction"));
1206 if (etype
!= EXEC_UNKNOWN
)
1209 etype
= EXEC_UNKNOWN
;
1212 /* Word multiply instructions must not be followed by either a load or a
1213 16-bit multiply instruction in the next cycle. */
1214 if ( (extype
!= EXEC_REVSEQ
)
1216 && (opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1218 /* However, load and multiply should able to be combined in a parallel
1219 operation, so check for that first. */
1221 && (opcode
.op
->flags_used
& FLAG_MEM
)
1222 && opcode
.form
->form
< LONG
1223 && (extype
== EXEC_PARALLEL
|| (Optimizing
&& extype
== EXEC_UNKNOWN
))
1224 && parallel_ok (&prev_opcode
, (long)prev_insn
,
1225 &opcode
, (long)insn
, extype
)
1226 && write_2_short (&prev_opcode
, (long)prev_insn
,
1227 &opcode
, (long)insn
, extype
, fixups
) == 0)
1229 /* no instructions saved */
1235 /* Can't parallelize, flush previous instruction and emit a word of NOPS,
1236 unless the previous instruction is a NOP, in which case just flush it,
1237 as this will generate a word of NOPs for us. */
1239 if (prev_insn
!= -1 && (strcmp (prev_opcode
.op
->name
, "nop") == 0))
1240 d30v_cleanup (false);
1245 if (prev_insn
!= -1)
1246 d30v_cleanup (true);
1250 d30v_number_to_chars (f
, NOP2
, 8);
1252 if (warn_nops
== NOP_ALL
|| warn_nops
== NOP_MULTIPLY
)
1254 if (opcode
.op
->flags_used
& FLAG_MEM
)
1255 as_warn (_("word of NOPs added between word multiply and load"));
1257 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1262 extype
= EXEC_UNKNOWN
;
1265 else if ( (extype
== EXEC_REVSEQ
)
1267 && (prev_opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1269 /* Can't parallelize, flush current instruction and add a sequential NOP. */
1270 write_1_short (& opcode
, (long) insn
, fixups
->next
->next
, true);
1272 /* Make the previous instruction the current one. */
1273 extype
= EXEC_UNKNOWN
;
1276 now_subseg
= prev_subseg
;
1278 cur_mul32_p
= prev_mul32_p
;
1280 memcpy (&opcode
, &prev_opcode
, sizeof (prev_opcode
));
1283 /* If this is a long instruction, write it and any previous short instruction. */
1284 if (opcode
.form
->form
>= LONG
)
1286 if (extype
!= EXEC_UNKNOWN
)
1287 as_fatal (_("Unable to mix instructions as specified"));
1288 d30v_cleanup (false);
1289 write_long (&opcode
, insn
, fixups
);
1292 else if ((prev_insn
!= -1) &&
1293 (write_2_short (&prev_opcode
, (long)prev_insn
, &opcode
, (long)insn
, extype
, fixups
) == 0))
1295 /* No instructions saved. */
1300 if (extype
!= EXEC_UNKNOWN
)
1301 as_fatal (_("Unable to mix instructions as specified"));
1303 /* Save off last instruction so it may be packed on next pass. */
1304 memcpy (&prev_opcode
, &opcode
, sizeof (prev_opcode
));
1307 prev_subseg
= now_subseg
;
1308 fixups
= fixups
->next
;
1313 /* do_assemble assembles a single instruction and returns an opcode */
1314 /* it returns -1 (an invalid opcode) on error */
1317 do_assemble (str
, opcode
, shortp
, is_parallel
)
1319 struct d30v_insn
*opcode
;
1323 unsigned char *op_start
, *save
;
1324 unsigned char *op_end
;
1326 int cmp_hack
, nlen
= 0, fsize
= (shortp
? FORCE_SHORT
: 0);
1327 expressionS myops
[6];
1330 /* Drop leading whitespace */
1334 /* find the opcode end */
1335 for (op_start
= op_end
= (unsigned char *) (str
);
1339 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1342 name
[nlen
] = tolower (op_start
[nlen
]);
1351 /* if there is an execution condition code, handle it */
1355 while ( (i
< ECC_MAX
) && strncasecmp (d30v_ecc_names
[i
],op_end
+1,2))
1361 strncpy (tmp
,op_end
+1,2);
1363 as_fatal (_("unknown condition code: %s"),tmp
);
1366 /* printf("condition code=%d\n",i); */
1371 opcode
->ecc
= ECC_AL
;
1374 /* CMP and CMPU change their name based on condition codes */
1375 if (!strncmp (name
,"cmp",3))
1378 char **str
= (char **)d30v_cc_names
;
1384 for (i
=1; *str
&& strncmp (*str
,&name
[p
],2); i
++, str
++)
1387 /* cmpu only supports some condition codes */
1393 as_fatal (_("cmpu doesn't support condition code %s"),&name
[p
]);
1400 as_fatal (_("unknown condition code: %s"),&name
[p
]);
1409 /* printf("cmp_hack=%d\n",cmp_hack); */
1411 /* need to look for .s or .l */
1412 if (name
[nlen
-2] == '.')
1414 switch (name
[nlen
-1])
1417 fsize
= FORCE_SHORT
;
1426 /* find the first opcode with the proper name */
1427 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1428 if (opcode
->op
== NULL
)
1429 as_fatal (_("unknown opcode: %s"),name
);
1431 save
= input_line_pointer
;
1432 input_line_pointer
= op_end
;
1433 while (!(opcode
->form
= find_format (opcode
->op
, myops
, fsize
, cmp_hack
)))
1436 if (strcmp (opcode
->op
->name
,name
))
1437 as_fatal (_("operands for opcode `%s' do not match any valid format"), name
);
1439 input_line_pointer
= save
;
1441 insn
= build_insn (opcode
, myops
);
1443 /* Propigate multiply status */
1446 if (is_parallel
&& prev_mul32_p
)
1450 prev_mul32_p
= cur_mul32_p
;
1451 cur_mul32_p
= (opcode
->op
->flags_used
& FLAG_MUL32
) != 0;
1455 /* Propagate left_kills_right status */
1458 prev_left_kills_right_p
= cur_left_kills_right_p
;
1460 if (opcode
->op
->flags_set
& FLAG_LKR
)
1462 cur_left_kills_right_p
= 1;
1464 if (strcmp (opcode
->op
->name
, "mvtsys") == 0)
1466 /* Left kills right for only mvtsys only for PSW/PSWH/PSWL/flags target. */
1467 if ((myops
[0].X_op
== O_register
) &&
1468 ((myops
[0].X_add_number
== OPERAND_CONTROL
) || /* psw */
1469 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+2) || /* pswh */
1470 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+1) || /* pswl */
1471 (myops
[0].X_add_number
== OPERAND_FLAG
+0) || /* f0 */
1472 (myops
[0].X_add_number
== OPERAND_FLAG
+1) || /* f1 */
1473 (myops
[0].X_add_number
== OPERAND_FLAG
+2) || /* f2 */
1474 (myops
[0].X_add_number
== OPERAND_FLAG
+3) || /* f3 */
1475 (myops
[0].X_add_number
== OPERAND_FLAG
+4) || /* f4 */
1476 (myops
[0].X_add_number
== OPERAND_FLAG
+5) || /* f5 */
1477 (myops
[0].X_add_number
== OPERAND_FLAG
+6) || /* f6 */
1478 (myops
[0].X_add_number
== OPERAND_FLAG
+7))) /* f7 */
1480 cur_left_kills_right_p
= 1;
1484 /* Other mvtsys target registers don't kill right instruction. */
1485 cur_left_kills_right_p
= 0;
1490 cur_left_kills_right_p
= 0;
1498 /* find_format() gets a pointer to an entry in the format table.
1499 It must look at all formats for an opcode and use the operands
1500 to choose the correct one. Returns NULL on error. */
1502 static struct d30v_format
*
1503 find_format (opcode
, myops
, fsize
, cmp_hack
)
1504 struct d30v_opcode
*opcode
;
1505 expressionS myops
[];
1509 int numops
, match
, index
, i
=0, j
, k
;
1510 struct d30v_format
*fm
;
1512 /* Get all the operands and save them as expressions. */
1513 numops
= get_operands (myops
, cmp_hack
);
1515 while ((index
= opcode
->format
[i
++]) != 0)
1517 if (fsize
== FORCE_SHORT
&& index
>= LONG
)
1520 if (fsize
== FORCE_LONG
&& index
< LONG
)
1523 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1525 while (fm
->form
== index
)
1528 /* Now check the operands for compatibility. */
1529 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1531 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1532 int bits
= d30v_operand_table
[fm
->operands
[j
]].bits
;
1533 int X_op
= myops
[j
].X_op
;
1534 int num
= myops
[j
].X_add_number
;
1536 if (flags
& OPERAND_SPECIAL
)
1538 else if (X_op
== O_illegal
)
1540 else if (flags
& OPERAND_REG
)
1542 if (X_op
!= O_register
1543 || ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
))
1544 || (!(flags
& OPERAND_ACC
) && (num
& OPERAND_ACC
))
1545 || ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
))
1546 || (!(flags
& OPERAND_FLAG
) && (num
& OPERAND_FLAG
))
1547 || ((flags
& OPERAND_CONTROL
)
1548 && !(num
& (OPERAND_CONTROL
| OPERAND_FLAG
))))
1553 else if (((flags
& OPERAND_MINUS
)
1554 && (X_op
!= O_absent
|| num
!= OPERAND_MINUS
))
1555 || ((flags
& OPERAND_PLUS
)
1556 && (X_op
!= O_absent
|| num
!= OPERAND_PLUS
))
1557 || ((flags
& OPERAND_ATMINUS
)
1558 && (X_op
!= O_absent
|| num
!= OPERAND_ATMINUS
))
1559 || ((flags
& OPERAND_ATPAR
)
1560 && (X_op
!= O_absent
|| num
!= OPERAND_ATPAR
))
1561 || ((flags
& OPERAND_ATSIGN
)
1562 && (X_op
!= O_absent
|| num
!= OPERAND_ATSIGN
)))
1566 else if (flags
& OPERAND_NUM
)
1568 /* A number can be a constant or symbol expression. */
1570 /* If we have found a register name, but that name also
1571 matches a symbol, then re-parse the name as an expression. */
1572 if (X_op
== O_register
1573 && symbol_find ((char *) myops
[j
].X_op_symbol
))
1575 input_line_pointer
= (char *) myops
[j
].X_op_symbol
;
1576 expression (& myops
[j
]);
1579 /* Turn an expression into a symbol for later resolution. */
1580 if (X_op
!= O_absent
&& X_op
!= O_constant
1581 && X_op
!= O_symbol
&& X_op
!= O_register
1584 symbolS
*sym
= make_expr_symbol (&myops
[j
]);
1585 myops
[j
].X_op
= X_op
= O_symbol
;
1586 myops
[j
].X_add_symbol
= sym
;
1587 myops
[j
].X_add_number
= num
= 0;
1590 if (fm
->form
>= LONG
)
1592 /* If we're testing for a LONG format, either fits. */
1593 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1596 else if (fm
->form
< LONG
1597 && ((fsize
== FORCE_SHORT
&& X_op
== O_symbol
)
1598 || (fm
->form
== SHORT_D2
&& j
== 0)))
1600 /* This is the tricky part. Will the constant or symbol
1601 fit into the space in the current format? */
1602 else if (X_op
== O_constant
)
1604 if (check_range (num
, bits
, flags
))
1607 else if (X_op
== O_symbol
1608 && S_IS_DEFINED (myops
[j
].X_add_symbol
)
1609 && S_GET_SEGMENT (myops
[j
].X_add_symbol
) == now_seg
1610 && opcode
->reloc_flag
== RELOC_PCREL
)
1612 /* If the symbol is defined, see if the value will fit
1613 into the form we're considering. */
1617 /* Calculate the current address by running through the
1618 previous frags and adding our current offset. */
1620 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1621 value
+= f
->fr_fix
+ f
->fr_offset
;
1622 value
= (S_GET_VALUE (myops
[j
].X_add_symbol
) - value
1623 - (obstack_next_free (&frchain_now
->frch_obstack
)
1624 - frag_now
->fr_literal
));
1625 if (check_range (value
, bits
, flags
))
1632 /* printf("through the loop: match=%d\n",match); */
1633 /* We're only done if the operands matched so far AND there
1634 are no more to check. */
1635 if (match
&& myops
[j
].X_op
== 0)
1637 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1639 /* printf("trying another format: i=%d\n",i); */
1644 /* if while processing a fixup, a reloc really needs to be created */
1645 /* then it is done here */
1648 tc_gen_reloc (seg
, fixp
)
1653 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1654 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1655 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1656 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1657 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1659 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1660 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1663 reloc
->addend
= fixp
->fx_addnumber
;
1668 md_estimate_size_before_relax (fragp
, seg
)
1677 md_pcrel_from_section (fixp
, sec
)
1681 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1682 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1684 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1688 md_apply_fix3 (fixp
, valuep
, seg
)
1694 unsigned long insn
, insn2
;
1697 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1702 else if (fixp
->fx_pcrel
)
1708 value
= fixp
->fx_offset
;
1709 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1711 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1712 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1715 /* We don't actually support subtracting a symbol. */
1716 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1717 _("expression too complex"));
1722 /* Fetch the instruction, insert the fully resolved operand
1723 value, and stuff the instruction back again. */
1724 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1725 insn
= bfd_getb32 ((unsigned char *) where
);
1727 switch (fixp
->fx_r_type
)
1730 /* Caused by a bad .byte directive. */
1731 as_fatal (_("line %d: unable to place address of symbol '%s' into a byte"),
1732 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1736 /* Caused by a bad .short directive. */
1737 as_fatal (_("line %d: unable to place address of symbol '%s' into a short"),
1738 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1742 /* Caused by a bad .quad directive. */
1743 as_fatal (_("line %d: unable to place address of symbol '%s' into a .quad"),
1744 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1747 case BFD_RELOC_D30V_6
:
1748 check_size (value
, 6, fixp
->fx_file
, fixp
->fx_line
);
1749 insn
|= value
& 0x3F;
1750 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1753 case BFD_RELOC_D30V_9_PCREL
:
1754 if (fixp
->fx_where
& 0x7)
1759 fixp
->fx_r_type
= BFD_RELOC_D30V_9_PCREL_R
;
1761 check_size (value
, 9, fixp
->fx_file
, fixp
->fx_line
);
1762 insn
|= ((value
>> 3) & 0x3F) << 12;
1763 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1766 case BFD_RELOC_D30V_15
:
1767 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1768 insn
|= (value
>> 3) & 0xFFF;
1769 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1772 case BFD_RELOC_D30V_15_PCREL
:
1773 if (fixp
->fx_where
& 0x7)
1778 fixp
->fx_r_type
= BFD_RELOC_D30V_15_PCREL_R
;
1780 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1781 insn
|= (value
>> 3) & 0xFFF;
1782 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1785 case BFD_RELOC_D30V_21
:
1786 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1787 insn
|= (value
>> 3) & 0x3FFFF;
1788 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1791 case BFD_RELOC_D30V_21_PCREL
:
1792 if (fixp
->fx_where
& 0x7)
1797 fixp
->fx_r_type
= BFD_RELOC_D30V_21_PCREL_R
;
1799 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1800 insn
|= (value
>> 3) & 0x3FFFF;
1801 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1804 case BFD_RELOC_D30V_32
:
1805 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1806 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1807 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1808 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1809 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1810 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1813 case BFD_RELOC_D30V_32_PCREL
:
1814 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1815 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1816 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1817 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1818 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1819 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1823 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1827 as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp
->fx_line
,fixp
->fx_r_type
);
1833 /* d30v_cleanup() is called after the assembler has finished parsing the input
1834 file or after a label is defined. Because the D30V assembler sometimes saves short
1835 instructions to see if it can package them with the next instruction, there may
1836 be a short instruction that still needs written. */
1838 d30v_cleanup (use_sequential
)
1844 if (prev_insn
!= -1)
1847 subseg
= now_subseg
;
1848 subseg_set (prev_seg
, prev_subseg
);
1849 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
, use_sequential
);
1850 subseg_set (seg
, subseg
);
1853 prev_mul32_p
= false;
1859 d30v_number_to_chars (buf
, value
, n
)
1860 char *buf
; /* Return 'nbytes' of chars here. */
1861 long long value
; /* The value of the bits. */
1862 int n
; /* Number of bytes in the output. */
1866 buf
[n
] = value
& 0xff;
1872 /* This function is called at the start of every line. */
1873 /* it checks to see if the first character is a '.' */
1874 /* which indicates the start of a pseudo-op. If it is, */
1875 /* then write out any unwritten instructions */
1880 char *c
= input_line_pointer
;
1882 while (isspace (*c
))
1886 d30v_cleanup (false);
1890 check_size (value
, bits
, file
, line
)
1903 max
= (1 << (bits
- 1)) - 1;
1906 as_bad_where (file
, line
, _("value too large to fit in %d bits"), bits
);
1911 /* d30v_frob_label() is called when after a label is recognized. */
1914 d30v_frob_label (lab
)
1917 /* Emit any pending instructions. */
1918 d30v_cleanup (false);
1920 /* Update the label's address with the current output pointer. */
1921 lab
->sy_frag
= frag_now
;
1922 S_SET_VALUE (lab
, (valueT
) frag_now_fix ());
1924 /* Record this label for future adjustment after we find out what
1925 kind of data it references, and the required alignment therewith. */
1926 d30v_last_label
= lab
;
1929 /* Hook into cons for capturing alignment changes. */
1932 d30v_cons_align (size
)
1938 while ((size
>>= 1) != 0)
1941 if (d30v_current_align
< log_size
)
1942 d30v_align (log_size
, (char *) NULL
, NULL
);
1943 else if (d30v_current_align
> log_size
)
1944 d30v_current_align
= log_size
;
1945 d30v_last_label
= NULL
;
1948 /* Called internally to handle all alignment needs. This takes care
1949 of eliding calls to frag_align if'n the cached current alignment
1950 says we've already got it, as well as taking care of the auto-aligning
1954 d30v_align (n
, pfill
, label
)
1959 /* The front end is prone to changing segments out from under us
1960 temporarily when -g is in effect. */
1961 int switched_seg_p
= (d30v_current_align_seg
!= now_seg
);
1963 /* Do not assume that if 'd30v_current_align >= n' and
1964 '! switched_seg_p' that it is safe to avoid performing
1965 this alignement request. The alignment of the current frag
1966 can be changed under our feet, for example by a .ascii
1967 directive in the source code. cf testsuite/gas/d30v/reloc.s */
1969 d30v_cleanup (false);
1974 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
1976 static char const nop
[4] = { 0x00, 0xf0, 0x00, 0x00 };
1978 /* First, make sure we're on a four-byte boundary, in case
1979 someone has been putting .byte values the text section. */
1980 if (d30v_current_align
< 2 || switched_seg_p
)
1981 frag_align (2, 0, 0);
1982 frag_align_pattern (n
, nop
, sizeof nop
, 0);
1985 frag_align (n
, 0, 0);
1988 frag_align (n
, *pfill
, 0);
1990 if (!switched_seg_p
)
1991 d30v_current_align
= n
;
1996 int label_seen
= false;
1997 struct frag
* old_frag
;
2001 assert (S_GET_SEGMENT (label
) == now_seg
);
2003 old_frag
= label
->sy_frag
;
2004 old_value
= S_GET_VALUE (label
);
2005 new_value
= (valueT
) frag_now_fix ();
2007 /* It is possible to have more than one label at a particular
2008 address, especially if debugging is enabled, so we must
2009 take care to adjust all the labels at this address in this
2010 fragment. To save time we search from the end of the symbol
2011 list, backwards, since the symbols we are interested in are
2012 almost certainly the ones that were most recently added.
2013 Also to save time we stop searching once we have seen at least
2014 one matching label, and we encounter a label that is no longer
2015 in the target fragment. Note, this search is guaranteed to
2016 find at least one match when sym == label, so no special case
2017 code is necessary. */
2018 for (sym
= symbol_lastP
; sym
!= NULL
; sym
= sym
->sy_previous
)
2020 if (sym
->sy_frag
== old_frag
&& S_GET_VALUE (sym
) == old_value
)
2023 sym
->sy_frag
= frag_now
;
2024 S_SET_VALUE (sym
, new_value
);
2026 else if (label_seen
&& sym
->sy_frag
!= old_frag
)
2031 record_alignment (now_seg
, n
);
2034 /* Handle the .align pseudo-op. This aligns to a power of two. We
2035 hook here to latch the current alignment. */
2038 s_d30v_align (ignore
)
2042 char fill
, *pfill
= NULL
;
2043 long max_alignment
= 15;
2045 align
= get_absolute_expression ();
2046 if (align
> max_alignment
)
2048 align
= max_alignment
;
2049 as_warn (_("Alignment too large: %d assumed"), align
);
2053 as_warn (_("Alignment negative: 0 assumed"));
2057 if (*input_line_pointer
== ',')
2059 input_line_pointer
++;
2060 fill
= get_absolute_expression ();
2064 d30v_last_label
= NULL
;
2065 d30v_align (align
, pfill
, NULL
);
2067 demand_empty_rest_of_line ();
2070 /* Handle the .text pseudo-op. This is like the usual one, but it
2071 clears the saved last label and resets known alignment. */
2079 d30v_last_label
= NULL
;
2080 d30v_current_align
= 0;
2081 d30v_current_align_seg
= now_seg
;
2084 /* Handle the .data pseudo-op. This is like the usual one, but it
2085 clears the saved last label and resets known alignment. */
2092 d30v_last_label
= NULL
;
2093 d30v_current_align
= 0;
2094 d30v_current_align_seg
= now_seg
;
2097 /* Handle the .section pseudo-op. This is like the usual one, but it
2098 clears the saved last label and resets known alignment. */
2101 s_d30v_section (ignore
)
2104 obj_elf_section (ignore
);
2105 d30v_last_label
= NULL
;
2106 d30v_current_align
= 0;
2107 d30v_current_align_seg
= now_seg
;