1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
3 Copyright (C) 1997, 1998 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d30v.h"
28 const char comment_chars
[] = ";";
29 const char line_comment_chars
[] = "#";
30 const char line_separator_chars
[] = "";
31 const char *md_shortopts
= "OnN";
32 const char EXP_CHARS
[] = "eE";
33 const char FLT_CHARS
[] = "dD";
35 #define NOP_MULTIPLY 1
37 static int warn_nops
= 0;
38 static int Optimizing
= 0;
44 typedef enum _exec_type
46 EXEC_UNKNOWN
, /* no order specified */
47 EXEC_PARALLEL
, /* done in parallel (FM=00) */
48 EXEC_SEQ
, /* sequential (FM=01) */
49 EXEC_REVSEQ
/* reverse sequential (FM=10) */
53 #define MAX_INSN_FIXUPS (5)
60 bfd_reloc_code_real_type reloc
;
63 typedef struct _fixups
66 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
70 static Fixups FixUps
[2];
71 static Fixups
*fixups
;
73 /* Whether current and previous instruction is a word multiply. */
77 /* The flag_explicitly_parallel is true iff the instruction being assembled
78 has been explicitly written as a parallel short-instruction pair by the
79 human programmer. It is used in parallel_ok() to distinguish between
80 those dangerous parallelizations attempted by the human, which are to be
81 allowed, and those attempted by the assembler, which are not. It is set
82 from md_assemble(). */
83 static int flag_explicitly_parallel
= 0;
84 static int flag_xp_state
= 0;
87 #define NOP_LEFT ((long long)NOP << 32)
88 #define NOP_RIGHT ((long long)NOP)
89 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
92 static int reg_name_search
PARAMS ((char *name
));
93 static int register_name
PARAMS ((expressionS
*expressionP
));
94 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
95 static int postfix
PARAMS ((char *p
));
96 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
97 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
98 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
,
99 expressionS ops
[],int fsize
, int cmp_hack
));
100 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
101 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
102 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
103 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
104 struct d30v_insn
*opcode2
, long long insn2
, exec_type_enum exec_type
, Fixups
*fx
));
105 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
,
107 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
108 struct d30v_insn
*opcode2
, unsigned long insn2
,
109 exec_type_enum exec_type
));
110 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
111 static void check_size
PARAMS ((long value
, int bits
, char *file
, int line
));
113 struct option md_longopts
[] = {
114 {NULL
, no_argument
, NULL
, 0}
116 size_t md_longopts_size
= sizeof(md_longopts
);
119 /* The target specific pseudo-ops which we support. */
120 const pseudo_typeS md_pseudo_table
[] =
123 { "hword", cons
, 2 },
127 /* Opcode hash table. */
128 static struct hash_control
*d30v_hash
;
130 /* reg_name_search does a binary search of the pre_defined_registers
131 array to see if "name" is a valid regiter name. Returns the register
132 number from the array on success, or -1 on failure. */
135 reg_name_search (name
)
138 int middle
, low
, high
;
142 high
= reg_name_cnt() - 1;
146 middle
= (low
+ high
) / 2;
147 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
153 return pre_defined_registers
[middle
].value
;
159 /* register_name() checks the string at input_line_pointer
160 to see if it is a valid register name */
163 register_name (expressionP
)
164 expressionS
*expressionP
;
167 char c
, *p
= input_line_pointer
;
169 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
176 /* look to see if it's in the register table */
177 reg_number
= reg_name_search (input_line_pointer
);
180 expressionP
->X_op
= O_register
;
181 /* temporarily store a pointer to the string here */
182 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
183 expressionP
->X_add_number
= reg_number
;
184 input_line_pointer
= p
;
194 check_range (num
, bits
, flags
)
202 /* don't bother checking 32-bit values */
206 if (flags
& OPERAND_SIGNED
)
208 max
= (1 << (bits
- 1))-1;
209 min
= - (1 << (bits
- 1));
210 if (((long)num
> max
) || ((long)num
< min
))
215 max
= (1 << bits
) - 1;
217 if ((num
> max
) || (num
< min
))
225 md_show_usage (stream
)
228 fprintf(stream
, (_("\nD30V options:\n\
229 -O Make adjacent short instructions parallel if possible.\n\
230 -n Warn about all NOPs inserted by the assembler.\n\
231 -N Warn about NOPs inserted after word multiplies.\n")));
235 md_parse_option (c
, arg
)
241 /* Optimize. Will attempt to parallelize operations */
246 /* Warn about all NOPS that the assembler inserts. */
251 /* Warn about the NOPS that the assembler inserts because of the
254 warn_nops
= NOP_MULTIPLY
;
264 md_undefined_symbol (name
)
270 /* Turn a string in input_line_pointer into a floating point constant of type
271 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
272 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
275 md_atof (type
, litP
, sizeP
)
281 LITTLENUM_TYPE words
[4];
295 return _("bad call to md_atof");
298 t
= atof_ieee (input_line_pointer
, type
, words
);
300 input_line_pointer
= t
;
304 for (i
= 0; i
< prec
; i
++)
306 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
313 md_convert_frag (abfd
, sec
, fragP
)
322 md_section_align (seg
, addr
)
326 int align
= bfd_get_section_alignment (stdoutput
, seg
);
327 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
334 struct d30v_opcode
*opcode
;
335 d30v_hash
= hash_new();
337 /* Insert opcode names into a hash table. */
338 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
339 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
342 FixUps
[0].next
= &FixUps
[1];
343 FixUps
[1].next
= &FixUps
[0];
347 /* this function removes the postincrement or postdecrement
348 operator ( '+' or '-' ) from an expression */
350 static int postfix (p
)
353 while (*p
!= '-' && *p
!= '+')
355 if (*p
==0 || *p
=='\n' || *p
=='\r' || *p
==' ' || *p
==',')
375 static bfd_reloc_code_real_type
376 get_reloc (op
, rel_flag
)
377 struct d30v_operand
*op
;
383 if (op
->flags
& OPERAND_SHIFT
)
384 return BFD_RELOC_D30V_9_PCREL
;
386 return BFD_RELOC_D30V_6
;
389 if (!(op
->flags
& OPERAND_SHIFT
))
390 as_warn(_("unexpected 12-bit reloc type"));
391 if (rel_flag
== RELOC_PCREL
)
392 return BFD_RELOC_D30V_15_PCREL
;
394 return BFD_RELOC_D30V_15
;
396 if (!(op
->flags
& OPERAND_SHIFT
))
397 as_warn(_("unexpected 18-bit reloc type"));
398 if (rel_flag
== RELOC_PCREL
)
399 return BFD_RELOC_D30V_21_PCREL
;
401 return BFD_RELOC_D30V_21
;
403 if (rel_flag
== RELOC_PCREL
)
404 return BFD_RELOC_D30V_32_PCREL
;
406 return BFD_RELOC_D30V_32
;
412 /* get_operands parses a string of operands and returns
413 an array of expressions */
416 get_operands (exp
, cmp_hack
)
420 char *p
= input_line_pointer
;
426 exp
[numops
].X_op
= O_absent
;
427 exp
[numops
++].X_add_number
= cmp_hack
- 1;
432 while (*p
== ' ' || *p
== '\t' || *p
== ',')
434 if (*p
==0 || *p
=='\n' || *p
=='\r')
440 exp
[numops
].X_op
= O_absent
;
444 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
450 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
454 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
463 /* just skip the trailing paren */
468 input_line_pointer
= p
;
470 /* check to see if it might be a register name */
471 if (!register_name (&exp
[numops
]))
473 /* parse as an expression */
474 expression (&exp
[numops
]);
477 if (exp
[numops
].X_op
== O_illegal
)
478 as_bad (_("illegal operand"));
479 else if (exp
[numops
].X_op
== O_absent
)
480 as_bad (_("missing operand"));
483 p
= input_line_pointer
;
487 case -1: /* postdecrement mode */
488 exp
[numops
].X_op
= O_absent
;
489 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
491 case 1: /* postincrement mode */
492 exp
[numops
].X_op
= O_absent
;
493 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
499 exp
[numops
].X_op
= 0;
503 /* build_insn generates the instruction. It does everything */
504 /* but write the FM bits. */
507 build_insn (opcode
, opers
)
508 struct d30v_insn
*opcode
;
511 int i
, length
, bits
, shift
, flags
;
512 unsigned int number
, id
=0;
514 struct d30v_opcode
*op
= opcode
->op
;
515 struct d30v_format
*form
= opcode
->form
;
517 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
519 for (i
=0; form
->operands
[i
]; i
++)
521 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
523 /* must be a register or number */
524 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
525 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
528 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
529 if (flags
& OPERAND_SHIFT
)
532 length
= d30v_operand_table
[form
->operands
[i
]].length
;
533 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
534 if (opers
[i
].X_op
!= O_symbol
)
535 number
= opers
[i
].X_add_number
;
538 if (flags
& OPERAND_REG
)
540 /* check for mvfsys or mvtsys control registers */
541 if (flags
& OPERAND_CONTROL
&& (number
& 0x7f) > MAX_CONTROL_REG
)
544 id
= (number
& 0x7f) - MAX_CONTROL_REG
;
547 else if (number
& OPERAND_FLAG
)
549 id
= 3; /* number is a flag register */
553 else if (flags
& OPERAND_SPECIAL
)
558 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
560 /* now create a fixup */
562 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
563 as_fatal (_("too many fixups"));
565 fixups
->fix
[fixups
->fc
].reloc
=
566 get_reloc((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
567 fixups
->fix
[fixups
->fc
].size
= 4;
568 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
569 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
570 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D30V_9_PCREL
)
571 fixups
->fix
[fixups
->fc
].pcrel
= RELOC_PCREL
;
573 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
577 /* truncate to the proper number of bits */
578 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
579 as_bad(_("operand out of range: %d"),number
);
581 number
&= 0x7FFFFFFF >> (31 - bits
);
582 if (flags
& OPERAND_SHIFT
)
586 /* it's a LONG instruction */
587 insn
|= (number
>> 26); /* top 6 bits */
588 insn
<<= 32; /* shift the first word over */
589 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
590 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
593 insn
|= number
<< shift
;
599 /* write out a long form instruction */
601 write_long (opcode
, insn
, fx
)
602 struct d30v_insn
*opcode
;
607 char *f
= frag_more(8);
610 d30v_number_to_chars (f
, insn
, 8);
612 for (i
=0; i
< fx
->fc
; i
++)
614 if (fx
->fix
[i
].reloc
)
616 where
= f
- frag_now
->fr_literal
;
617 fix_new_exp (frag_now
,
629 /* write out a short form instruction by itself */
631 write_1_short (opcode
, insn
, fx
)
632 struct d30v_insn
*opcode
;
636 char *f
= frag_more(8);
639 if (warn_nops
== NOP_ALL
)
640 as_warn (_("NOP inserted"));
642 /* the other container needs to be NOP */
643 /* according to 4.3.1: for FM=00, sub-instructions performed only
644 by IU cannot be encoded in L-container. */
645 if (opcode
->op
->unit
== IU
)
646 insn
|= FM00
| NOP_LEFT
; /* right container */
648 insn
= FM00
| (insn
<< 32) | NOP_RIGHT
; /* left container */
650 d30v_number_to_chars (f
, insn
, 8);
652 for (i
=0; i
< fx
->fc
; i
++)
654 if (fx
->fix
[i
].reloc
)
656 where
= f
- frag_now
->fr_literal
;
657 fix_new_exp (frag_now
,
668 /* write out a short form instruction if possible */
669 /* return number of instructions not written out */
671 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
672 struct d30v_insn
*opcode1
, *opcode2
;
673 long long insn1
, insn2
;
674 exec_type_enum exec_type
;
677 long long insn
= NOP2
;
681 if(exec_type
!= EXEC_PARALLEL
&&
682 ((opcode1
->op
->flags_used
& (FLAG_JSR
| FLAG_DELAY
)) == FLAG_JSR
))
684 /* subroutines must be called from 32-bit boundaries */
685 /* so the return address will be correct */
686 write_1_short (opcode1
, insn1
, fx
->next
);
692 case EXEC_UNKNOWN
: /* order not specified */
693 if (Optimizing
&& parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
696 exec_type
= EXEC_PARALLEL
;
697 if (opcode1
->op
->unit
== IU
)
698 insn
= FM00
| (insn2
<< 32) | insn1
;
699 else if (opcode2
->op
->unit
== MU
)
700 insn
= FM00
| (insn2
<< 32) | insn1
;
703 insn
= FM00
| (insn1
<< 32) | insn2
;
707 else if (opcode1
->op
->unit
== IU
)
709 /* reverse sequential */
710 insn
= FM10
| (insn2
<< 32) | insn1
;
711 exec_type
= EXEC_REVSEQ
;
716 insn
= FM01
| (insn1
<< 32) | insn2
;
718 exec_type
= EXEC_SEQ
;
722 case EXEC_PARALLEL
: /* parallel */
723 flag_explicitly_parallel
= flag_xp_state
;
724 if (! parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
725 as_fatal (_("Instructions may not be executed in parallel"));
726 else if (opcode1
->op
->unit
== IU
)
728 if (opcode2
->op
->unit
== IU
)
729 as_fatal (_("Two IU instructions may not be executed in parallel"));
730 as_warn (_("Swapping instruction order"));
731 insn
= FM00
| (insn2
<< 32) | insn1
;
733 else if (opcode2
->op
->unit
== MU
)
735 if (opcode1
->op
->unit
== MU
)
736 as_fatal (_("Two MU instructions may not be executed in parallel"));
737 as_warn (_("Swapping instruction order"));
738 insn
= FM00
| (insn2
<< 32) | insn1
;
742 insn
= FM00
| (insn1
<< 32) | insn2
;
745 flag_explicitly_parallel
= 0;
748 case EXEC_SEQ
: /* sequential */
749 if (opcode1
->op
->unit
== IU
)
750 as_fatal (_("IU instruction may not be in the left container"));
751 insn
= FM01
| (insn1
<< 32) | insn2
;
755 case EXEC_REVSEQ
: /* reverse sequential */
756 if (opcode2
->op
->unit
== MU
)
757 as_fatal (_("MU instruction may not be in the right container"));
758 insn
= FM10
| (insn1
<< 32) | insn2
;
763 as_fatal(_("unknown execution type passed to write_2_short()"));
766 /* printf("writing out %llx\n",insn); */
768 d30v_number_to_chars (f
, insn
, 8);
770 /* If the previous instruction was a 32-bit multiply but it is put into a
771 parallel container, mark the current instruction as being a 32-bit
773 if (prev_mul32_p
&& exec_type
== EXEC_PARALLEL
)
778 for (i
=0; i
< fx
->fc
; i
++)
780 if (fx
->fix
[i
].reloc
)
782 where
= (f
- frag_now
->fr_literal
) + 4*j
;
784 fix_new_exp (frag_now
,
799 /* Check 2 instructions and determine if they can be safely */
800 /* executed in parallel. Returns 1 if they can be. */
802 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
803 struct d30v_insn
*op1
, *op2
;
804 unsigned long insn1
, insn2
;
805 exec_type_enum exec_type
;
807 int i
, j
, shift
, regno
, bits
, ecc
;
808 unsigned long flags
, mask
, flags_set1
, flags_set2
, flags_used1
, flags_used2
;
809 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3], flag_reg
[2];
810 struct d30v_format
*f
;
811 struct d30v_opcode
*op
;
813 /* section 4.3: both instructions must not be IU or MU only */
814 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
815 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
818 /* first instruction must not be a jump to safely optimize, unless this
819 is an explicit parallel operation. */
820 if (exec_type
!= EXEC_PARALLEL
821 && (op1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)))
824 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
825 then it is safe to allow the two to be done as parallel ops, since only
826 one will ever be executed at a time. */
827 if ((op1
->ecc
== ECC_TX
&& op2
->ecc
== ECC_FX
)
828 || (op1
->ecc
== ECC_FX
&& op2
->ecc
== ECC_TX
)
829 || (op1
->ecc
== ECC_XT
&& op2
->ecc
== ECC_XF
)
830 || (op1
->ecc
== ECC_XF
&& op2
->ecc
== ECC_XT
))
835 [2] a0, a1, flag registers */
837 for (j
= 0; j
< 2; j
++)
854 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
855 mod_reg
[j
][2] = (op
->flags_set
& FLAG_ALL
);
856 used_reg
[j
][0] = used_reg
[j
][1] = 0;
857 used_reg
[j
][2] = (op
->flags_used
& FLAG_ALL
);
859 /* BSR/JSR always sets R62 */
860 if (op
->flags_used
& FLAG_JSR
)
861 mod_reg
[j
][1] = (1L << (62-32));
863 /* conditional execution affects the flags_used */
868 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_0
;
873 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_1
;
878 used_reg
[j
][2] |= flag_reg
[j
] = (FLAG_0
| FLAG_1
);
882 for (i
= 0; f
->operands
[i
]; i
++)
884 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
885 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
886 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
890 mask
= 0x7FFFFFFF >> (31 - bits
);
892 if ((flags
& OPERAND_PLUS
) || (flags
& OPERAND_MINUS
))
894 /* this is a post-increment or post-decrement */
895 /* the previous register needs to be marked as modified */
897 shift
= 12 - d30v_operand_table
[f
->operands
[i
-1]].position
;
898 regno
= (ins
>> shift
) & 0x3f;
900 mod_reg
[j
][1] |= 1L << (regno
- 32);
902 mod_reg
[j
][0] |= 1L << regno
;
904 else if (flags
& OPERAND_REG
)
906 regno
= (ins
>> shift
) & mask
;
907 /* the memory write functions don't have a destination register */
908 if ((flags
& OPERAND_DEST
) && !(op
->flags_set
& FLAG_MEM
))
910 /* MODIFIED registers and flags */
911 if (flags
& OPERAND_ACC
)
914 mod_reg
[j
][2] |= FLAG_A0
;
916 mod_reg
[j
][2] |= FLAG_A1
;
920 else if (flags
& OPERAND_FLAG
)
921 mod_reg
[j
][2] |= 1L << regno
;
922 else if (!(flags
& OPERAND_CONTROL
))
926 /* need to check if there are two destination */
927 /* registers, for example ld2w */
928 if (flags
& OPERAND_2REG
)
933 for (r
= regno
; r
<= regno
+ z
; r
++)
936 mod_reg
[j
][1] |= 1L << (r
- 32);
938 mod_reg
[j
][0] |= 1L << r
;
944 /* USED, but not modified registers and flags */
945 if (flags
& OPERAND_ACC
)
948 used_reg
[j
][2] |= FLAG_A0
;
950 used_reg
[j
][2] |= FLAG_A1
;
954 else if (flags
& OPERAND_FLAG
)
955 used_reg
[j
][2] |= 1L << regno
;
956 else if (!(flags
& OPERAND_CONTROL
))
960 /* need to check if there are two source */
961 /* registers, for example st2w */
962 if (flags
& OPERAND_2REG
)
967 for (r
= regno
; r
<= regno
+ z
; r
++)
970 used_reg
[j
][1] |= 1L << (r
- 32);
972 used_reg
[j
][0] |= 1L << r
;
980 flags_set1
= op1
->op
->flags_set
;
981 flags_set2
= op2
->op
->flags_set
;
982 flags_used1
= op1
->op
->flags_used
;
983 flags_used2
= op2
->op
->flags_used
;
985 /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */
986 if (((flags_set1
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
987 && (flags_used2
& FLAG_ADDSUBppp
) != 0)
988 || ((flags_set2
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
989 && (flags_used1
& FLAG_ADDSUBppp
) != 0))
992 /* Load instruction combined with half-word multiply is illegal. */
993 if (((flags_used1
& FLAG_MEM
) != 0 && (flags_used2
& FLAG_MUL16
))
994 || ((flags_used2
& FLAG_MEM
) != 0 && (flags_used1
& FLAG_MUL16
)))
997 /* Specifically allow add || add by removing carry, overflow bits dependency.
998 This is safe, even if an addc follows since the IU takes the argument in
999 the right container, and it writes its results last.
1000 However, don't paralellize add followed by addc or sub followed by
1003 if (mod_reg
[0][2] == FLAG_CVVA
&& mod_reg
[1][2] == FLAG_CVVA
1004 && (used_reg
[0][2] & ~flag_reg
[0]) == 0
1005 && (used_reg
[1][2] & ~flag_reg
[1]) == 0
1006 && op1
->op
->unit
== EITHER
&& op2
->op
->unit
== EITHER
)
1008 mod_reg
[0][2] = mod_reg
[1][2] = 0;
1011 for(j
= 0; j
< 3; j
++)
1013 /* If the second instruction depends on the first, we obviously
1014 cannot parallelize. Note, the mod flag implies use, so
1015 check that as well. */
1016 /* If flag_explicitly_parallel is set, then the case of the
1017 second instruction using a register the first instruction
1018 modifies is assumed to be okay; we trust the human. We
1019 don't trust the human if both instructions modify the same
1020 register but we do trust the human if they modify the same
1022 if (flag_explicitly_parallel
)
1024 if ((j
< 2) && (mod_reg
[0][j
] & mod_reg
[1][j
]) != 0)
1028 if ((mod_reg
[0][j
] & (mod_reg
[1][j
] | used_reg
[1][j
])) != 0)
1037 /* This is the main entry point for the machine-dependent assembler. str points to a
1038 machine-dependent instruction. This function is supposed to emit the frags/bytes
1039 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
1040 and leaves the difficult stuff to do_assemble(). */
1042 static long long prev_insn
= -1;
1043 static struct d30v_insn prev_opcode
;
1044 static subsegT prev_subseg
;
1045 static segT prev_seg
= 0;
1051 struct d30v_insn opcode
;
1053 exec_type_enum extype
= EXEC_UNKNOWN
; /* execution type; parallel, etc */
1054 static exec_type_enum etype
= EXEC_UNKNOWN
; /* saved extype. used for multiline instructions */
1057 if ( (prev_insn
!= -1) && prev_seg
&& ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1060 flag_explicitly_parallel
= 0;
1062 if (etype
== EXEC_UNKNOWN
)
1064 /* look for the special multiple instruction separators */
1065 str2
= strstr (str
, "||");
1068 extype
= EXEC_PARALLEL
;
1073 str2
= strstr (str
, "->");
1078 str2
= strstr (str
, "<-");
1080 extype
= EXEC_REVSEQ
;
1083 /* str2 points to the separator, if one */
1088 /* if two instructions are present and we already have one saved
1089 then first write it out */
1092 /* assemble first instruction and save it */
1093 prev_insn
= do_assemble (str
, &prev_opcode
, 1);
1094 if (prev_insn
== -1)
1095 as_fatal (_("cannot assemble instruction "));
1096 if (prev_opcode
.form
->form
>= LONG
)
1097 as_fatal (_("First opcode is long. Unable to mix instructions as specified."));
1098 fixups
= fixups
->next
;
1103 insn
= do_assemble (str
, &opcode
,
1104 (extype
!= EXEC_UNKNOWN
|| etype
!= EXEC_UNKNOWN
));
1107 if (extype
!= EXEC_UNKNOWN
)
1112 as_fatal (_("cannot assemble instruction "));
1115 if (etype
!= EXEC_UNKNOWN
)
1118 etype
= EXEC_UNKNOWN
;
1121 /* Word multiply instructions must not be followed by either a load or a
1122 16-bit multiply instruction in the next cycle. */
1123 if (prev_mul32_p
&& (opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1125 /* However, load and multiply should able to be combined in a parallel
1126 operation, so check for that first. */
1129 && (opcode
.op
->flags_used
& FLAG_MEM
)
1130 && opcode
.form
->form
< LONG
1131 && (extype
== EXEC_PARALLEL
|| (Optimizing
&& extype
== EXEC_UNKNOWN
))
1132 && parallel_ok (&prev_opcode
, (long)prev_insn
,
1133 &opcode
, (long)insn
, extype
)
1134 && write_2_short (&prev_opcode
, (long)prev_insn
,
1135 &opcode
, (long)insn
, extype
, fixups
) == 0)
1137 /* no instructions saved */
1142 /* Can't parallelize, flush current instruction and emit a word of NOPS */
1149 d30v_number_to_chars (f
, NOP2
, 8);
1150 if (warn_nops
== NOP_ALL
|| warn_nops
== NOP_MULTIPLY
)
1152 if ((opcode
.op
->flags_used
& FLAG_MEM
))
1153 as_warn (_("word of NOPs added between word multiply and load"));
1155 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1160 /* if this is a long instruction, write it and any previous short instruction */
1161 if (opcode
.form
->form
>= LONG
)
1164 as_fatal(_("Unable to mix instructions as specified"));
1166 write_long (&opcode
, insn
, fixups
);
1171 if ((prev_insn
!= -1) &&
1172 (write_2_short (&prev_opcode
, (long)prev_insn
, &opcode
, (long)insn
, extype
, fixups
) == 0))
1174 /* no instructions saved */
1181 as_fatal(_("Unable to mix instructions as specified"));
1182 /* save off last instruction so it may be packed on next pass */
1183 memcpy(&prev_opcode
, &opcode
, sizeof(prev_opcode
));
1186 prev_subseg
= now_subseg
;
1187 fixups
= fixups
->next
;
1192 /* do_assemble assembles a single instruction and returns an opcode */
1193 /* it returns -1 (an invalid opcode) on error */
1196 do_assemble (str
, opcode
, shortp
)
1198 struct d30v_insn
*opcode
;
1201 unsigned char *op_start
, *save
;
1202 unsigned char *op_end
;
1204 int cmp_hack
, nlen
= 0, fsize
= (shortp
? FORCE_SHORT
: 0);
1205 expressionS myops
[6];
1208 /* Drop leading whitespace */
1212 /* find the opcode end */
1213 for (op_start
= op_end
= (unsigned char *) (str
);
1217 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1220 name
[nlen
] = tolower(op_start
[nlen
]);
1229 /* if there is an execution condition code, handle it */
1233 while ( (i
< ECC_MAX
) && strncasecmp(d30v_ecc_names
[i
],op_end
+1,2))
1239 strncpy(tmp
,op_end
+1,2);
1241 as_fatal (_("unknown condition code: %s"),tmp
);
1244 /* printf("condition code=%d\n",i); */
1249 opcode
->ecc
= ECC_AL
;
1252 /* CMP and CMPU change their name based on condition codes */
1253 if (!strncmp(name
,"cmp",3))
1256 char **str
= (char **)d30v_cc_names
;
1262 for(i
=1; *str
&& strncmp(*str
,&name
[p
],2); i
++, str
++)
1265 /* cmpu only supports some condition codes */
1271 as_fatal (_("cmpu doesn't support condition code %s"),&name
[p
]);
1278 as_fatal (_("unknown condition code: %s"),&name
[p
]);
1287 /* printf("cmp_hack=%d\n",cmp_hack); */
1289 /* need to look for .s or .l */
1290 if (name
[nlen
-2] == '.')
1292 switch (name
[nlen
-1])
1295 fsize
= FORCE_SHORT
;
1304 /* find the first opcode with the proper name */
1305 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1306 if (opcode
->op
== NULL
)
1307 as_fatal (_("unknown opcode: %s"),name
);
1309 save
= input_line_pointer
;
1310 input_line_pointer
= op_end
;
1311 while (!(opcode
->form
= find_format (opcode
->op
, myops
, fsize
, cmp_hack
)))
1314 if (strcmp(opcode
->op
->name
,name
))
1317 input_line_pointer
= save
;
1319 insn
= build_insn (opcode
, myops
);
1321 /* Propigate multiply status */
1324 prev_mul32_p
= cur_mul32_p
;
1325 cur_mul32_p
= (opcode
->op
->flags_used
& FLAG_MUL32
) != 0;
1332 /* find_format() gets a pointer to an entry in the format table. */
1333 /* It must look at all formats for an opcode and use the operands */
1334 /* to choose the correct one. Returns NULL on error. */
1336 static struct d30v_format
*
1337 find_format (opcode
, myops
, fsize
, cmp_hack
)
1338 struct d30v_opcode
*opcode
;
1339 expressionS myops
[];
1343 int numops
, match
, index
, i
=0, j
, k
;
1344 struct d30v_format
*fm
;
1346 /* get all the operands and save them as expressions */
1347 numops
= get_operands (myops
, cmp_hack
);
1349 while ((index
= opcode
->format
[i
++]) != 0)
1351 if ((fsize
== FORCE_SHORT
) && (index
>= LONG
))
1354 if ((fsize
== FORCE_LONG
) && (index
< LONG
))
1357 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1359 while (fm
->form
== index
)
1362 /* now check the operands for compatibility */
1363 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1365 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1366 int X_op
= myops
[j
].X_op
;
1367 int num
= myops
[j
].X_add_number
;
1369 if ( flags
& OPERAND_SPECIAL
)
1373 else if (flags
& OPERAND_REG
)
1375 if ((X_op
!= O_register
)
1376 || ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
))
1377 || ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
))
1378 || ((flags
& OPERAND_CONTROL
)
1379 && !(num
& (OPERAND_CONTROL
| OPERAND_FLAG
))))
1385 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
)))
1386 || ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
)))
1387 || ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
)))
1388 || ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
)))
1389 || ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATSIGN
))))
1393 else if (flags
& OPERAND_NUM
)
1395 /* a number can be a constant or symbol expression */
1396 if (fm
->form
>= LONG
)
1398 /* If we're testing for a LONG format, either fits */
1399 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1402 else if ((fm
->form
< LONG
) && (((fsize
== FORCE_SHORT
) && (X_op
== O_symbol
)) ||
1403 (fm
->form
== SHORT_D2
&& j
== 0)))
1405 /* This is the tricky part. Will the constant or symbol */
1406 /* fit into the space in the current format? */
1407 else if (X_op
== O_constant
)
1409 if (check_range (num
, d30v_operand_table
[fm
->operands
[j
]].bits
, flags
))
1412 else if (X_op
== O_symbol
&& S_IS_DEFINED(myops
[j
].X_add_symbol
) &&
1413 (S_GET_SEGMENT(myops
[j
].X_add_symbol
) == now_seg
) &&
1414 opcode
->reloc_flag
== RELOC_PCREL
)
1416 /* if the symbol is defined, see if the value will fit */
1417 /* into the form we're considering */
1420 /* calculate the current address by running through the previous frags */
1421 /* and adding our current offset */
1422 for (value
= 0, f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1423 value
+= f
->fr_fix
+ f
->fr_offset
;
1424 value
= S_GET_VALUE(myops
[j
].X_add_symbol
) - value
-
1425 (obstack_next_free(&frchain_now
->frch_obstack
) - frag_now
->fr_literal
);
1426 if (check_range (value
, d30v_operand_table
[fm
->operands
[j
]].bits
, flags
))
1433 /* printf("through the loop: match=%d\n",match); */
1434 /* we're only done if the operands matched so far AND there
1435 are no more to check */
1436 if (match
&& myops
[j
].X_op
==0)
1439 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1441 /* printf("trying another format: i=%d\n",i); */
1446 /* if while processing a fixup, a reloc really needs to be created */
1447 /* then it is done here */
1450 tc_gen_reloc (seg
, fixp
)
1455 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1456 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1457 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1458 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1459 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1461 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1462 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1465 reloc
->addend
= fixp
->fx_addnumber
;
1470 md_estimate_size_before_relax (fragp
, seg
)
1479 md_pcrel_from_section (fixp
, sec
)
1483 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1484 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1486 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1490 md_apply_fix3 (fixp
, valuep
, seg
)
1496 unsigned long insn
, insn2
;
1499 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1504 else if (fixp
->fx_pcrel
)
1510 value
= fixp
->fx_offset
;
1511 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1513 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1514 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1517 /* We don't actually support subtracting a symbol. */
1518 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1519 _("expression too complex"));
1524 /* Fetch the instruction, insert the fully resolved operand
1525 value, and stuff the instruction back again. */
1526 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1527 insn
= bfd_getb32 ((unsigned char *) where
);
1529 switch (fixp
->fx_r_type
)
1531 case BFD_RELOC_D30V_6
:
1532 check_size (value
, 6, fixp
->fx_file
, fixp
->fx_line
);
1533 insn
|= value
& 0x3F;
1534 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1537 case BFD_RELOC_D30V_9_PCREL
:
1538 if (fixp
->fx_where
& 0x7)
1543 fixp
->fx_r_type
= BFD_RELOC_D30V_9_PCREL_R
;
1545 check_size (value
, 9, fixp
->fx_file
, fixp
->fx_line
);
1546 insn
|= ((value
>> 3) & 0x3F) << 12;
1547 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1550 case BFD_RELOC_D30V_15
:
1551 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1552 insn
|= (value
>> 3) & 0xFFF;
1553 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1556 case BFD_RELOC_D30V_15_PCREL
:
1557 if (fixp
->fx_where
& 0x7)
1562 fixp
->fx_r_type
= BFD_RELOC_D30V_15_PCREL_R
;
1564 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1565 insn
|= (value
>> 3) & 0xFFF;
1566 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1569 case BFD_RELOC_D30V_21
:
1570 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1571 insn
|= (value
>> 3) & 0x3FFFF;
1572 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1575 case BFD_RELOC_D30V_21_PCREL
:
1576 if (fixp
->fx_where
& 0x7)
1581 fixp
->fx_r_type
= BFD_RELOC_D30V_21_PCREL_R
;
1583 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1584 insn
|= (value
>> 3) & 0x3FFFF;
1585 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1588 case BFD_RELOC_D30V_32
:
1589 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1590 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1591 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1592 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1593 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1594 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1597 case BFD_RELOC_D30V_32_PCREL
:
1598 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1599 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1600 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1601 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1602 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1603 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1607 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1611 as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp
->fx_line
,fixp
->fx_r_type
);
1617 /* d30v_cleanup() is called after the assembler has finished parsing the input
1618 file or after a label is defined. Because the D30V assembler sometimes saves short
1619 instructions to see if it can package them with the next instruction, there may
1620 be a short instruction that still needs written. */
1627 if (prev_insn
!= -1)
1630 subseg
= now_subseg
;
1631 subseg_set (prev_seg
, prev_subseg
);
1632 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
);
1633 subseg_set (seg
, subseg
);
1641 d30v_number_to_chars (buf
, value
, n
)
1642 char *buf
; /* Return 'nbytes' of chars here. */
1643 long long value
; /* The value of the bits. */
1644 int n
; /* Number of bytes in the output. */
1648 buf
[n
] = value
& 0xff;
1654 /* This function is called at the start of every line. */
1655 /* it checks to see if the first character is a '.' */
1656 /* which indicates the start of a pseudo-op. If it is, */
1657 /* then write out any unwritten instructions */
1662 char *c
= input_line_pointer
;
1672 check_size (value
, bits
, file
, line
)
1685 max
= (1 << (bits
- 1)) - 1;
1688 as_bad_where (file
, line
,"value too large to fit in %d bits",bits
);