1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
2 Copyright (C) 1997, 1998, 1999 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
25 #include "opcode/d30v.h"
27 const char comment_chars
[] = ";";
28 const char line_comment_chars
[] = "#";
29 const char line_separator_chars
[] = "";
30 const char *md_shortopts
= "OnNcC";
31 const char EXP_CHARS
[] = "eE";
32 const char FLT_CHARS
[] = "dD";
34 #define NOP_MULTIPLY 1
36 static int warn_nops
= 0;
37 static int Optimizing
= 0;
38 static int warn_register_name_conflicts
= 1;
44 typedef enum _exec_type
46 EXEC_UNKNOWN
, /* no order specified */
47 EXEC_PARALLEL
, /* done in parallel (FM=00) */
48 EXEC_SEQ
, /* sequential (FM=01) */
49 EXEC_REVSEQ
/* reverse sequential (FM=10) */
53 #define MAX_INSN_FIXUPS (5)
60 bfd_reloc_code_real_type reloc
;
63 typedef struct _fixups
66 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
70 static Fixups FixUps
[2];
71 static Fixups
*fixups
;
73 /* Whether current and previous instruction are word multiply insns. */
74 static int cur_mul32_p
= 0;
75 static int prev_mul32_p
= 0;
77 /* The flag_explicitly_parallel is true iff the instruction being assembled
78 has been explicitly written as a parallel short-instruction pair by the
79 human programmer. It is used in parallel_ok() to distinguish between
80 those dangerous parallelizations attempted by the human, which are to be
81 allowed, and those attempted by the assembler, which are not. It is set
82 from md_assemble(). */
83 static int flag_explicitly_parallel
= 0;
84 static int flag_xp_state
= 0;
86 /* Whether current and previous left sub-instruction disables
87 execution of right sub-instruction. */
88 static int cur_left_kills_right_p
= 0;
89 static int prev_left_kills_right_p
= 0;
91 /* The known current alignment of the current section. */
92 static int d30v_current_align
;
93 static segT d30v_current_align_seg
;
95 /* The last seen label in the current section. This is used to auto-align
96 labels preceeding instructions. */
97 static symbolS
*d30v_last_label
;
100 #define NOP_LEFT ((long long) NOP << 32)
101 #define NOP_RIGHT ((long long) NOP)
102 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
104 /* local functions */
105 static int reg_name_search
PARAMS ((char *name
));
106 static int register_name
PARAMS ((expressionS
*expressionP
));
107 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
108 static int postfix
PARAMS ((char *p
));
109 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
110 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
111 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
,
112 expressionS ops
[],int fsize
, int cmp_hack
));
113 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
114 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
115 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
,
116 Fixups
*fx
, int use_sequential
));
117 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
118 struct d30v_insn
*opcode2
, long long insn2
, exec_type_enum exec_type
, Fixups
*fx
));
119 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
,
120 int shortp
, int is_parallel
));
121 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
122 struct d30v_insn
*opcode2
, unsigned long insn2
,
123 exec_type_enum exec_type
));
124 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
125 static void check_size
PARAMS ((long value
, int bits
, char *file
, int line
));
126 static void d30v_align
PARAMS ((int, char *, symbolS
*));
127 static void s_d30v_align
PARAMS ((int));
128 static void s_d30v_text
PARAMS ((int));
129 static void s_d30v_data
PARAMS ((int));
130 static void s_d30v_section
PARAMS ((int));
132 struct option md_longopts
[] = {
133 {NULL
, no_argument
, NULL
, 0}
135 size_t md_longopts_size
= sizeof(md_longopts
);
138 /* The target specific pseudo-ops which we support. */
139 const pseudo_typeS md_pseudo_table
[] =
142 { "hword", cons
, 2 },
143 { "align", s_d30v_align
, 0 },
144 { "text", s_d30v_text
, 0 },
145 { "data", s_d30v_data
, 0 },
146 { "section", s_d30v_section
, 0 },
147 { "section.s", s_d30v_section
, 0 },
148 { "sect", s_d30v_section
, 0 },
149 { "sect.s", s_d30v_section
, 0 },
153 /* Opcode hash table. */
154 static struct hash_control
*d30v_hash
;
156 /* reg_name_search does a binary search of the pre_defined_registers
157 array to see if "name" is a valid regiter name. Returns the register
158 number from the array on success, or -1 on failure. */
161 reg_name_search (name
)
164 int middle
, low
, high
;
168 high
= reg_name_cnt () - 1;
172 middle
= (low
+ high
) / 2;
173 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
180 if (symbol_find (name
) != NULL
)
182 if (warn_register_name_conflicts
)
183 as_warn (_("Register name %s conflicts with symbol of the same name"),
187 return pre_defined_registers
[middle
].value
;
195 /* register_name() checks the string at input_line_pointer
196 to see if it is a valid register name. */
199 register_name (expressionP
)
200 expressionS
*expressionP
;
203 char c
, *p
= input_line_pointer
;
205 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
212 /* look to see if it's in the register table */
213 reg_number
= reg_name_search (input_line_pointer
);
216 expressionP
->X_op
= O_register
;
217 /* temporarily store a pointer to the string here */
218 expressionP
->X_op_symbol
= (symbolS
*)input_line_pointer
;
219 expressionP
->X_add_number
= reg_number
;
220 input_line_pointer
= p
;
230 check_range (num
, bits
, flags
)
238 /* don't bother checking 32-bit values */
242 if (flags
& OPERAND_SHIFT
)
244 /* We know that all shifts are right by three bits.... */
246 if (flags
& OPERAND_SIGNED
)
247 num
= (unsigned long) (((/*signed*/ long) num
) >> 3);
252 if (flags
& OPERAND_SIGNED
)
254 max
= (1 << (bits
- 1))-1;
255 min
= - (1 << (bits
- 1));
256 if (((long)num
> max
) || ((long)num
< min
))
261 max
= (1 << bits
) - 1;
263 if ((num
> max
) || (num
< min
))
272 md_show_usage (stream
)
275 fprintf (stream
, _("\nD30V options:\n\
276 -O Make adjacent short instructions parallel if possible.\n\
277 -n Warn about all NOPs inserted by the assembler.\n\
278 -N Warn about NOPs inserted after word multiplies.\n\
279 -c Warn about symbols whoes names match register names.\n\
280 -C Opposite of -C. -c is the default.\n"));
284 md_parse_option (c
, arg
)
290 /* Optimize. Will attempt to parallelize operations */
295 /* Warn about all NOPS that the assembler inserts. */
300 /* Warn about the NOPS that the assembler inserts because of the
303 warn_nops
= NOP_MULTIPLY
;
307 warn_register_name_conflicts
= 1;
311 warn_register_name_conflicts
= 0;
321 md_undefined_symbol (name
)
327 /* Turn a string in input_line_pointer into a floating point constant of type
328 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
329 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
332 md_atof (type
, litP
, sizeP
)
338 LITTLENUM_TYPE words
[4];
352 return _("bad call to md_atof");
355 t
= atof_ieee (input_line_pointer
, type
, words
);
357 input_line_pointer
= t
;
361 for (i
= 0; i
< prec
; i
++)
363 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
370 md_convert_frag (abfd
, sec
, fragP
)
379 md_section_align (seg
, addr
)
383 int align
= bfd_get_section_alignment (stdoutput
, seg
);
384 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
391 struct d30v_opcode
* opcode
;
392 d30v_hash
= hash_new ();
394 /* Insert opcode names into a hash table. */
395 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
396 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
399 FixUps
[0].next
= &FixUps
[1];
400 FixUps
[1].next
= &FixUps
[0];
402 d30v_current_align_seg
= now_seg
;
406 /* this function removes the postincrement or postdecrement
407 operator ( '+' or '-' ) from an expression */
409 static int postfix (p
)
412 while (*p
!= '-' && *p
!= '+')
414 if (*p
==0 || *p
=='\n' || *p
=='\r' || *p
==' ' || *p
==',')
434 static bfd_reloc_code_real_type
435 get_reloc (op
, rel_flag
)
436 struct d30v_operand
*op
;
442 if (op
->flags
& OPERAND_SHIFT
)
443 return BFD_RELOC_D30V_9_PCREL
;
445 return BFD_RELOC_D30V_6
;
448 if (!(op
->flags
& OPERAND_SHIFT
))
449 as_warn (_("unexpected 12-bit reloc type"));
450 if (rel_flag
== RELOC_PCREL
)
451 return BFD_RELOC_D30V_15_PCREL
;
453 return BFD_RELOC_D30V_15
;
455 if (!(op
->flags
& OPERAND_SHIFT
))
456 as_warn (_("unexpected 18-bit reloc type"));
457 if (rel_flag
== RELOC_PCREL
)
458 return BFD_RELOC_D30V_21_PCREL
;
460 return BFD_RELOC_D30V_21
;
462 if (rel_flag
== RELOC_PCREL
)
463 return BFD_RELOC_D30V_32_PCREL
;
465 return BFD_RELOC_D30V_32
;
471 /* get_operands parses a string of operands and returns
472 an array of expressions */
475 get_operands (exp
, cmp_hack
)
479 char *p
= input_line_pointer
;
485 exp
[numops
].X_op
= O_absent
;
486 exp
[numops
++].X_add_number
= cmp_hack
- 1;
491 while (*p
== ' ' || *p
== '\t' || *p
== ',')
493 if (*p
==0 || *p
=='\n' || *p
=='\r')
499 exp
[numops
].X_op
= O_absent
;
503 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
509 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
513 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
522 /* just skip the trailing paren */
527 input_line_pointer
= p
;
529 /* check to see if it might be a register name */
530 if (!register_name (&exp
[numops
]))
532 /* parse as an expression */
533 expression (&exp
[numops
]);
536 if (exp
[numops
].X_op
== O_illegal
)
537 as_bad (_("illegal operand"));
538 else if (exp
[numops
].X_op
== O_absent
)
539 as_bad (_("missing operand"));
542 p
= input_line_pointer
;
546 case -1: /* postdecrement mode */
547 exp
[numops
].X_op
= O_absent
;
548 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
550 case 1: /* postincrement mode */
551 exp
[numops
].X_op
= O_absent
;
552 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
558 exp
[numops
].X_op
= 0;
562 /* build_insn generates the instruction. It does everything */
563 /* but write the FM bits. */
566 build_insn (opcode
, opers
)
567 struct d30v_insn
*opcode
;
570 int i
, length
, bits
, shift
, flags
;
571 unsigned int number
, id
=0;
573 struct d30v_opcode
*op
= opcode
->op
;
574 struct d30v_format
*form
= opcode
->form
;
576 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
578 for (i
=0; form
->operands
[i
]; i
++)
580 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
582 /* must be a register or number */
583 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
584 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
587 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
588 if (flags
& OPERAND_SHIFT
)
591 length
= d30v_operand_table
[form
->operands
[i
]].length
;
592 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
593 if (opers
[i
].X_op
!= O_symbol
)
594 number
= opers
[i
].X_add_number
;
597 if (flags
& OPERAND_REG
)
599 /* check for mvfsys or mvtsys control registers */
600 if (flags
& OPERAND_CONTROL
&& (number
& 0x7f) > MAX_CONTROL_REG
)
603 id
= (number
& 0x7f) - MAX_CONTROL_REG
;
606 else if (number
& OPERAND_FLAG
)
608 id
= 3; /* number is a flag register */
612 else if (flags
& OPERAND_SPECIAL
)
617 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
619 /* now create a fixup */
621 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
622 as_fatal (_("too many fixups"));
624 fixups
->fix
[fixups
->fc
].reloc
=
625 get_reloc ((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
626 fixups
->fix
[fixups
->fc
].size
= 4;
627 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
628 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
629 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D30V_9_PCREL
)
630 fixups
->fix
[fixups
->fc
].pcrel
= RELOC_PCREL
;
632 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
636 /* truncate to the proper number of bits */
637 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
638 as_bad (_("operand out of range: %d"),number
);
640 number
&= 0x7FFFFFFF >> (31 - bits
);
641 if (flags
& OPERAND_SHIFT
)
645 /* it's a LONG instruction */
646 insn
|= (number
>> 26); /* top 6 bits */
647 insn
<<= 32; /* shift the first word over */
648 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
649 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
652 insn
|= number
<< shift
;
658 /* write out a long form instruction */
660 write_long (opcode
, insn
, fx
)
661 struct d30v_insn
*opcode
;
666 char *f
= frag_more (8);
669 d30v_number_to_chars (f
, insn
, 8);
671 for (i
=0; i
< fx
->fc
; i
++)
673 if (fx
->fix
[i
].reloc
)
675 where
= f
- frag_now
->fr_literal
;
676 fix_new_exp (frag_now
,
688 /* Write out a short form instruction by itself. */
690 write_1_short (opcode
, insn
, fx
, use_sequential
)
691 struct d30v_insn
*opcode
;
696 char *f
= frag_more (8);
699 if (warn_nops
== NOP_ALL
)
700 as_warn (_("%s NOP inserted"), use_sequential
?
701 _("sequential") : _("parallel"));
703 /* The other container needs to be NOP. */
706 /* Use a sequential NOP rather than a parallel one,
707 as the current instruction is a FLAG_MUL32 type one
708 and the next instruction is a load. */
710 /* According to 4.3.1: for FM=01, sub-instructions performed
711 only by IU cannot be encoded in L-container. */
713 if (opcode
->op
->unit
== IU
)
714 insn
|= FM10
| NOP_LEFT
; /* right then left */
716 insn
= FM01
| (insn
<< 32) | NOP_RIGHT
; /* left then right */
720 /* According to 4.3.1: for FM=00, sub-instructions performed
721 only by IU cannot be encoded in L-container. */
723 if (opcode
->op
->unit
== IU
)
724 insn
|= FM00
| NOP_LEFT
; /* right container */
726 insn
= FM00
| (insn
<< 32) | NOP_RIGHT
; /* left container */
729 d30v_number_to_chars (f
, insn
, 8);
731 for (i
=0; i
< fx
->fc
; i
++)
733 if (fx
->fix
[i
].reloc
)
735 where
= f
- frag_now
->fr_literal
;
736 fix_new_exp (frag_now
,
747 /* Write out a short form instruction if possible.
748 Return number of instructions not written out. */
750 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
751 struct d30v_insn
*opcode1
, *opcode2
;
752 long long insn1
, insn2
;
753 exec_type_enum exec_type
;
756 long long insn
= NOP2
;
760 if (exec_type
== EXEC_SEQ
761 && (opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
))
762 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0)
763 && ((opcode1
->ecc
== ECC_AL
) || ! Optimizing
))
765 /* Unconditional, non-delayed branches kill instructions in
766 the right bin. Conditional branches don't always but if
767 we are not optimizing, then we have been asked to produce
768 an error about such constructs. For the purposes of this
769 test, subroutine calls are considered to be branches. */
770 write_1_short (opcode1
, insn1
, fx
->next
, false);
774 /* Note: we do not have to worry about subroutine calls occuring
775 in the right hand container. The return address is always
776 aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
780 case EXEC_UNKNOWN
: /* Order not specified. */
782 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
)
783 && ! ( (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
784 || opcode1
->op
->unit
== MU
)
786 ( opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
787 || opcode2
->op
->unit
== MU
)))
790 exec_type
= EXEC_PARALLEL
;
792 if (opcode1
->op
->unit
== IU
793 || opcode2
->op
->unit
== MU
794 || opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
795 insn
= FM00
| (insn2
<< 32) | insn1
;
798 insn
= FM00
| (insn1
<< 32) | insn2
;
802 else if (opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)
803 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0)
804 && ((opcode1
->ecc
== ECC_AL
) || ! Optimizing
))
806 /* We must emit (non-delayed) branch type instructions
807 on their own with nothing in the right container. */
808 write_1_short (opcode1
, insn1
, fx
->next
, false);
811 else if (prev_left_kills_right_p
)
813 /* The left instruction kils the right slot, so we
814 must leave it empty. */
815 write_1_short (opcode1
, insn1
, fx
->next
, false);
818 else if (opcode1
->op
->unit
== IU
819 || (opcode1
->op
->unit
== EITHER
820 && opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
))
822 /* reverse sequential */
823 insn
= FM10
| (insn2
<< 32) | insn1
;
824 exec_type
= EXEC_REVSEQ
;
829 insn
= FM01
| (insn1
<< 32) | insn2
;
831 exec_type
= EXEC_SEQ
;
835 case EXEC_PARALLEL
: /* parallel */
836 flag_explicitly_parallel
= flag_xp_state
;
837 if (! parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
838 as_bad (_("Instructions may not be executed in parallel"));
839 else if (opcode1
->op
->unit
== IU
)
841 if (opcode2
->op
->unit
== IU
)
842 as_bad (_("Two IU instructions may not be executed in parallel"));
843 as_warn (_("Swapping instruction order"));
844 insn
= FM00
| (insn2
<< 32) | insn1
;
846 else if (opcode2
->op
->unit
== MU
)
848 if (opcode1
->op
->unit
== MU
)
849 as_bad (_("Two MU instructions may not be executed in parallel"));
850 else if (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
)
851 as_warn (_("Executing %s in IU may not work"), opcode1
->op
->name
);
852 as_warn (_("Swapping instruction order"));
853 insn
= FM00
| (insn2
<< 32) | insn1
;
857 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
858 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
860 insn
= FM00
| (insn1
<< 32) | insn2
;
863 flag_explicitly_parallel
= 0;
866 case EXEC_SEQ
: /* sequential */
867 if (opcode1
->op
->unit
== IU
)
868 as_bad (_("IU instruction may not be in the left container"));
869 if (prev_left_kills_right_p
)
870 as_bad (_("special left instruction `%s' kills instruction "
871 "`%s' in right container"),
872 opcode1
->op
->name
, opcode2
->op
->name
);
873 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
874 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
875 insn
= FM01
| (insn1
<< 32) | insn2
;
879 case EXEC_REVSEQ
: /* reverse sequential */
880 if (opcode2
->op
->unit
== MU
)
881 as_bad (_("MU instruction may not be in the right container"));
882 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
883 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
884 insn
= FM10
| (insn1
<< 32) | insn2
;
889 as_fatal (_("unknown execution type passed to write_2_short()"));
892 /* printf ("writing out %llx\n",insn); */
894 d30v_number_to_chars (f
, insn
, 8);
896 /* If the previous instruction was a 32-bit multiply but it is put into a
897 parallel container, mark the current instruction as being a 32-bit
899 if (prev_mul32_p
&& exec_type
== EXEC_PARALLEL
)
904 for (i
=0; i
< fx
->fc
; i
++)
906 if (fx
->fix
[i
].reloc
)
908 where
= (f
- frag_now
->fr_literal
) + 4*j
;
910 fix_new_exp (frag_now
,
927 /* Check 2 instructions and determine if they can be safely */
928 /* executed in parallel. Returns 1 if they can be. */
930 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
931 struct d30v_insn
*op1
, *op2
;
932 unsigned long insn1
, insn2
;
933 exec_type_enum exec_type
;
935 int i
, j
, shift
, regno
, bits
, ecc
;
936 unsigned long flags
, mask
, flags_set1
, flags_set2
, flags_used1
, flags_used2
;
937 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3], flag_reg
[2];
938 struct d30v_format
*f
;
939 struct d30v_opcode
*op
;
941 /* section 4.3: both instructions must not be IU or MU only */
942 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
943 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
946 /* first instruction must not be a jump to safely optimize, unless this
947 is an explicit parallel operation. */
948 if (exec_type
!= EXEC_PARALLEL
949 && (op1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)))
952 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
953 then it is safe to allow the two to be done as parallel ops, since only
954 one will ever be executed at a time. */
955 if ((op1
->ecc
== ECC_TX
&& op2
->ecc
== ECC_FX
)
956 || (op1
->ecc
== ECC_FX
&& op2
->ecc
== ECC_TX
)
957 || (op1
->ecc
== ECC_XT
&& op2
->ecc
== ECC_XF
)
958 || (op1
->ecc
== ECC_XF
&& op2
->ecc
== ECC_XT
))
963 [2] a0, a1, flag registers */
965 for (j
= 0; j
< 2; j
++)
982 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
983 used_reg
[j
][0] = used_reg
[j
][1] = 0;
985 if (flag_explicitly_parallel
)
987 /* For human specified parallel instructions we have been asked
988 to ignore the possibility that both instructions could modify
989 bits in the PSW, so we initialise the mod & used arrays to 0.
990 We have been asked, however, to refuse to allow parallel
991 instructions which explicitly set the same flag register,
992 eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test
993 for the use of a flag register and set a bit in the mod or used
994 array appropriately. */
1001 mod_reg
[j
][2] = (op
->flags_set
& FLAG_ALL
);
1002 used_reg
[j
][2] = (op
->flags_used
& FLAG_ALL
);
1005 /* BSR/JSR always sets R62 */
1006 if (op
->flags_used
& FLAG_JSR
)
1007 mod_reg
[j
][1] = (1L << (62-32));
1009 /* conditional execution affects the flags_used */
1014 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_0
;
1019 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_1
;
1024 used_reg
[j
][2] |= flag_reg
[j
] = (FLAG_0
| FLAG_1
);
1028 for (i
= 0; f
->operands
[i
]; i
++)
1030 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
1031 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
1032 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
1036 mask
= 0x7FFFFFFF >> (31 - bits
);
1038 if ((flags
& OPERAND_PLUS
) || (flags
& OPERAND_MINUS
))
1040 /* this is a post-increment or post-decrement */
1041 /* the previous register needs to be marked as modified */
1043 shift
= 12 - d30v_operand_table
[f
->operands
[i
-1]].position
;
1044 regno
= (ins
>> shift
) & 0x3f;
1046 mod_reg
[j
][1] |= 1L << (regno
- 32);
1048 mod_reg
[j
][0] |= 1L << regno
;
1050 else if (flags
& OPERAND_REG
)
1052 regno
= (ins
>> shift
) & mask
;
1053 /* the memory write functions don't have a destination register */
1054 if ((flags
& OPERAND_DEST
) && !(op
->flags_set
& FLAG_MEM
))
1056 /* MODIFIED registers and flags */
1057 if (flags
& OPERAND_ACC
)
1060 mod_reg
[j
][2] |= FLAG_A0
;
1061 else if (regno
== 1)
1062 mod_reg
[j
][2] |= FLAG_A1
;
1066 else if (flags
& OPERAND_FLAG
)
1067 mod_reg
[j
][2] |= 1L << regno
;
1068 else if (!(flags
& OPERAND_CONTROL
))
1072 /* need to check if there are two destination */
1073 /* registers, for example ld2w */
1074 if (flags
& OPERAND_2REG
)
1079 for (r
= regno
; r
<= regno
+ z
; r
++)
1082 mod_reg
[j
][1] |= 1L << (r
- 32);
1084 mod_reg
[j
][0] |= 1L << r
;
1090 /* USED, but not modified registers and flags */
1091 if (flags
& OPERAND_ACC
)
1094 used_reg
[j
][2] |= FLAG_A0
;
1095 else if (regno
== 1)
1096 used_reg
[j
][2] |= FLAG_A1
;
1100 else if (flags
& OPERAND_FLAG
)
1101 used_reg
[j
][2] |= 1L << regno
;
1102 else if (!(flags
& OPERAND_CONTROL
))
1106 /* need to check if there are two source */
1107 /* registers, for example st2w */
1108 if (flags
& OPERAND_2REG
)
1113 for (r
= regno
; r
<= regno
+ z
; r
++)
1116 used_reg
[j
][1] |= 1L << (r
- 32);
1118 used_reg
[j
][0] |= 1L << r
;
1126 flags_set1
= op1
->op
->flags_set
;
1127 flags_set2
= op2
->op
->flags_set
;
1128 flags_used1
= op1
->op
->flags_used
;
1129 flags_used2
= op2
->op
->flags_used
;
1131 /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */
1132 if (((flags_set1
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1133 && (flags_used2
& FLAG_ADDSUBppp
) != 0)
1134 || ((flags_set2
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1135 && (flags_used1
& FLAG_ADDSUBppp
) != 0))
1138 /* Load instruction combined with half-word multiply is illegal. */
1139 if (((flags_used1
& FLAG_MEM
) != 0 && (flags_used2
& FLAG_MUL16
))
1140 || ((flags_used2
& FLAG_MEM
) != 0 && (flags_used1
& FLAG_MUL16
)))
1143 /* Specifically allow add || add by removing carry, overflow bits dependency.
1144 This is safe, even if an addc follows since the IU takes the argument in
1145 the right container, and it writes its results last.
1146 However, don't paralellize add followed by addc or sub followed by
1149 if (mod_reg
[0][2] == FLAG_CVVA
&& mod_reg
[1][2] == FLAG_CVVA
1150 && (used_reg
[0][2] & ~flag_reg
[0]) == 0
1151 && (used_reg
[1][2] & ~flag_reg
[1]) == 0
1152 && op1
->op
->unit
== EITHER
&& op2
->op
->unit
== EITHER
)
1154 mod_reg
[0][2] = mod_reg
[1][2] = 0;
1157 for (j
= 0; j
< 3; j
++)
1159 /* If the second instruction depends on the first, we obviously
1160 cannot parallelize. Note, the mod flag implies use, so
1161 check that as well. */
1162 /* If flag_explicitly_parallel is set, then the case of the
1163 second instruction using a register the first instruction
1164 modifies is assumed to be okay; we trust the human. We
1165 don't trust the human if both instructions modify the same
1166 register but we do trust the human if they modify the same
1168 /* We have now been requested not to trust the human if the
1169 instructions modify the same flag registers either. */
1170 if (flag_explicitly_parallel
)
1172 if ((mod_reg
[0][j
] & mod_reg
[1][j
]) != 0)
1176 if ((mod_reg
[0][j
] & (mod_reg
[1][j
] | used_reg
[1][j
])) != 0)
1184 /* This is the main entry point for the machine-dependent assembler. str points to a
1185 machine-dependent instruction. This function is supposed to emit the frags/bytes
1186 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
1187 and leaves the difficult stuff to do_assemble(). */
1189 static long long prev_insn
= -1;
1190 static struct d30v_insn prev_opcode
;
1191 static subsegT prev_subseg
;
1192 static segT prev_seg
= 0;
1198 struct d30v_insn opcode
;
1200 exec_type_enum extype
= EXEC_UNKNOWN
; /* execution type; parallel, etc */
1201 static exec_type_enum etype
= EXEC_UNKNOWN
; /* saved extype. used for multiline instructions */
1204 if ((prev_insn
!= -1) && prev_seg
1205 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1206 d30v_cleanup (false);
1208 if (d30v_current_align
< 3)
1209 d30v_align (3, NULL
, d30v_last_label
);
1210 else if (d30v_current_align
> 3)
1211 d30v_current_align
= 3;
1212 d30v_last_label
= NULL
;
1214 flag_explicitly_parallel
= 0;
1216 if (etype
== EXEC_UNKNOWN
)
1218 /* look for the special multiple instruction separators */
1219 str2
= strstr (str
, "||");
1222 extype
= EXEC_PARALLEL
;
1227 str2
= strstr (str
, "->");
1232 str2
= strstr (str
, "<-");
1234 extype
= EXEC_REVSEQ
;
1237 /* str2 points to the separator, if one */
1242 /* if two instructions are present and we already have one saved
1243 then first write it out */
1244 d30v_cleanup (false);
1246 /* Assemble first instruction and save it. */
1247 prev_insn
= do_assemble (str
, &prev_opcode
, 1, 0);
1248 if (prev_insn
== -1)
1249 as_bad (_("Cannot assemble instruction"));
1250 if (prev_opcode
.form
!= NULL
&& prev_opcode
.form
->form
>= LONG
)
1251 as_bad (_("First opcode is long. Unable to mix instructions as specified."));
1252 fixups
= fixups
->next
;
1255 prev_subseg
= now_subseg
;
1259 insn
= do_assemble (str
, &opcode
,
1260 (extype
!= EXEC_UNKNOWN
|| etype
!= EXEC_UNKNOWN
),
1261 extype
== EXEC_PARALLEL
);
1264 if (extype
!= EXEC_UNKNOWN
)
1266 as_bad (_("Cannot assemble instruction"));
1270 if (etype
!= EXEC_UNKNOWN
)
1273 etype
= EXEC_UNKNOWN
;
1276 /* Word multiply instructions must not be followed by either a load or a
1277 16-bit multiply instruction in the next cycle. */
1278 if ( (extype
!= EXEC_REVSEQ
)
1280 && (opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1282 /* However, load and multiply should able to be combined in a parallel
1283 operation, so check for that first. */
1285 && (opcode
.op
->flags_used
& FLAG_MEM
)
1286 && opcode
.form
->form
< LONG
1287 && (extype
== EXEC_PARALLEL
|| (Optimizing
&& extype
== EXEC_UNKNOWN
))
1288 && parallel_ok (&prev_opcode
, (long)prev_insn
,
1289 &opcode
, (long)insn
, extype
)
1290 && write_2_short (&prev_opcode
, (long)prev_insn
,
1291 &opcode
, (long)insn
, extype
, fixups
) == 0)
1293 /* no instructions saved */
1299 /* Can't parallelize, flush previous instruction and emit a word of NOPS,
1300 unless the previous instruction is a NOP, in which case just flush it,
1301 as this will generate a word of NOPs for us. */
1303 if (prev_insn
!= -1 && (strcmp (prev_opcode
.op
->name
, "nop") == 0))
1304 d30v_cleanup (false);
1309 if (prev_insn
!= -1)
1310 d30v_cleanup (true);
1314 d30v_number_to_chars (f
, NOP2
, 8);
1316 if (warn_nops
== NOP_ALL
|| warn_nops
== NOP_MULTIPLY
)
1318 if (opcode
.op
->flags_used
& FLAG_MEM
)
1319 as_warn (_("word of NOPs added between word multiply and load"));
1321 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1326 extype
= EXEC_UNKNOWN
;
1329 else if ( (extype
== EXEC_REVSEQ
)
1331 && (prev_opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1333 /* Can't parallelize, flush current instruction and add a sequential NOP. */
1334 write_1_short (& opcode
, (long) insn
, fixups
->next
->next
, true);
1336 /* Make the previous instruction the current one. */
1337 extype
= EXEC_UNKNOWN
;
1340 now_subseg
= prev_subseg
;
1342 cur_mul32_p
= prev_mul32_p
;
1344 memcpy (&opcode
, &prev_opcode
, sizeof (prev_opcode
));
1347 /* If this is a long instruction, write it and any previous short instruction. */
1348 if (opcode
.form
->form
>= LONG
)
1350 if (extype
!= EXEC_UNKNOWN
)
1351 as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
1352 d30v_cleanup (false);
1353 write_long (& opcode
, insn
, fixups
);
1356 else if ((prev_insn
!= -1)
1358 (& prev_opcode
, (long) prev_insn
, & opcode
,
1359 (long) insn
, extype
, fixups
) == 0))
1361 /* No instructions saved. */
1366 if (extype
!= EXEC_UNKNOWN
)
1367 as_bad (_("Unable to mix instructions as specified"));
1369 /* Save off last instruction so it may be packed on next pass. */
1370 memcpy (&prev_opcode
, &opcode
, sizeof (prev_opcode
));
1373 prev_subseg
= now_subseg
;
1374 fixups
= fixups
->next
;
1375 prev_mul32_p
= cur_mul32_p
;
1380 /* do_assemble assembles a single instruction and returns an opcode */
1381 /* it returns -1 (an invalid opcode) on error */
1383 #define NAME_BUF_LEN 20
1386 do_assemble (str
, opcode
, shortp
, is_parallel
)
1388 struct d30v_insn
*opcode
;
1392 unsigned char * op_start
;
1393 unsigned char * save
;
1394 unsigned char * op_end
;
1395 char name
[NAME_BUF_LEN
];
1398 int fsize
= (shortp
? FORCE_SHORT
: 0);
1399 expressionS myops
[6];
1402 /* Drop leading whitespace */
1403 while (* str
== ' ')
1406 /* find the opcode end */
1407 for (op_start
= op_end
= (unsigned char *) (str
);
1409 && nlen
< (NAME_BUF_LEN
- 1)
1411 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1414 name
[nlen
] = tolower (op_start
[nlen
]);
1423 /* if there is an execution condition code, handle it */
1427 while ( (i
< ECC_MAX
) && strncasecmp (d30v_ecc_names
[i
], op_end
+ 1, 2))
1433 strncpy (tmp
, op_end
+ 1, 2);
1435 as_bad (_("unknown condition code: %s"),tmp
);
1438 /* printf ("condition code=%d\n",i); */
1443 opcode
->ecc
= ECC_AL
;
1446 /* CMP and CMPU change their name based on condition codes */
1447 if (!strncmp (name
, "cmp", 3))
1450 char **str
= (char **)d30v_cc_names
;
1456 for (i
=1; *str
&& strncmp (*str
, & name
[p
], 2); i
++, str
++)
1459 /* cmpu only supports some condition codes */
1465 as_bad (_("cmpu doesn't support condition code %s"),&name
[p
]);
1472 as_bad (_("unknown condition code: %s"),&name
[p
]);
1481 /* printf("cmp_hack=%d\n",cmp_hack); */
1483 /* need to look for .s or .l */
1484 if (name
[nlen
-2] == '.')
1486 switch (name
[nlen
-1])
1489 fsize
= FORCE_SHORT
;
1498 /* find the first opcode with the proper name */
1499 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1500 if (opcode
->op
== NULL
)
1502 as_bad (_("unknown opcode: %s"),name
);
1506 save
= input_line_pointer
;
1507 input_line_pointer
= op_end
;
1508 while (!(opcode
->form
= find_format (opcode
->op
, myops
, fsize
, cmp_hack
)))
1511 if (opcode
->op
->name
== NULL
|| strcmp (opcode
->op
->name
, name
))
1513 as_bad (_("operands for opcode `%s' do not match any valid format"), name
);
1517 input_line_pointer
= save
;
1519 insn
= build_insn (opcode
, myops
);
1521 /* Propigate multiply status */
1524 if (is_parallel
&& prev_mul32_p
)
1528 prev_mul32_p
= cur_mul32_p
;
1529 cur_mul32_p
= (opcode
->op
->flags_used
& FLAG_MUL32
) != 0;
1533 /* Propagate left_kills_right status */
1536 prev_left_kills_right_p
= cur_left_kills_right_p
;
1538 if (opcode
->op
->flags_set
& FLAG_LKR
)
1540 cur_left_kills_right_p
= 1;
1542 if (strcmp (opcode
->op
->name
, "mvtsys") == 0)
1544 /* Left kills right for only mvtsys only for PSW/PSWH/PSWL/flags target. */
1545 if ((myops
[0].X_op
== O_register
) &&
1546 ((myops
[0].X_add_number
== OPERAND_CONTROL
) || /* psw */
1547 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+2) || /* pswh */
1548 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+1) || /* pswl */
1549 (myops
[0].X_add_number
== OPERAND_FLAG
+0) || /* f0 */
1550 (myops
[0].X_add_number
== OPERAND_FLAG
+1) || /* f1 */
1551 (myops
[0].X_add_number
== OPERAND_FLAG
+2) || /* f2 */
1552 (myops
[0].X_add_number
== OPERAND_FLAG
+3) || /* f3 */
1553 (myops
[0].X_add_number
== OPERAND_FLAG
+4) || /* f4 */
1554 (myops
[0].X_add_number
== OPERAND_FLAG
+5) || /* f5 */
1555 (myops
[0].X_add_number
== OPERAND_FLAG
+6) || /* f6 */
1556 (myops
[0].X_add_number
== OPERAND_FLAG
+7))) /* f7 */
1558 cur_left_kills_right_p
= 1;
1562 /* Other mvtsys target registers don't kill right instruction. */
1563 cur_left_kills_right_p
= 0;
1568 cur_left_kills_right_p
= 0;
1575 /* find_format() gets a pointer to an entry in the format table.
1576 It must look at all formats for an opcode and use the operands
1577 to choose the correct one. Returns NULL on error. */
1579 static struct d30v_format
*
1580 find_format (opcode
, myops
, fsize
, cmp_hack
)
1581 struct d30v_opcode
*opcode
;
1582 expressionS myops
[];
1586 int numops
, match
, index
, i
=0, j
, k
;
1587 struct d30v_format
*fm
;
1592 /* Get all the operands and save them as expressions. */
1593 numops
= get_operands (myops
, cmp_hack
);
1595 while ((index
= opcode
->format
[i
++]) != 0)
1597 if (fsize
== FORCE_SHORT
&& index
>= LONG
)
1600 if (fsize
== FORCE_LONG
&& index
< LONG
)
1603 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1605 while (fm
->form
== index
)
1608 /* Now check the operands for compatibility. */
1609 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1611 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1612 int bits
= d30v_operand_table
[fm
->operands
[j
]].bits
;
1613 int X_op
= myops
[j
].X_op
;
1614 int num
= myops
[j
].X_add_number
;
1616 if (flags
& OPERAND_SPECIAL
)
1618 else if (X_op
== O_illegal
)
1620 else if (flags
& OPERAND_REG
)
1622 if (X_op
!= O_register
1623 || ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
))
1624 || (!(flags
& OPERAND_ACC
) && (num
& OPERAND_ACC
))
1625 || ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
))
1626 || (!(flags
& (OPERAND_FLAG
| OPERAND_CONTROL
)) && (num
& OPERAND_FLAG
))
1627 || ((flags
& OPERAND_CONTROL
)
1628 && !(num
& (OPERAND_CONTROL
| OPERAND_FLAG
))))
1633 else if (((flags
& OPERAND_MINUS
)
1634 && (X_op
!= O_absent
|| num
!= OPERAND_MINUS
))
1635 || ((flags
& OPERAND_PLUS
)
1636 && (X_op
!= O_absent
|| num
!= OPERAND_PLUS
))
1637 || ((flags
& OPERAND_ATMINUS
)
1638 && (X_op
!= O_absent
|| num
!= OPERAND_ATMINUS
))
1639 || ((flags
& OPERAND_ATPAR
)
1640 && (X_op
!= O_absent
|| num
!= OPERAND_ATPAR
))
1641 || ((flags
& OPERAND_ATSIGN
)
1642 && (X_op
!= O_absent
|| num
!= OPERAND_ATSIGN
)))
1646 else if (flags
& OPERAND_NUM
)
1648 /* A number can be a constant or symbol expression. */
1650 /* If we have found a register name, but that name also
1651 matches a symbol, then re-parse the name as an expression. */
1652 if (X_op
== O_register
1653 && symbol_find ((char *) myops
[j
].X_op_symbol
))
1655 input_line_pointer
= (char *) myops
[j
].X_op_symbol
;
1656 expression (& myops
[j
]);
1659 /* Turn an expression into a symbol for later resolution. */
1660 if (X_op
!= O_absent
&& X_op
!= O_constant
1661 && X_op
!= O_symbol
&& X_op
!= O_register
1664 symbolS
*sym
= make_expr_symbol (&myops
[j
]);
1665 myops
[j
].X_op
= X_op
= O_symbol
;
1666 myops
[j
].X_add_symbol
= sym
;
1667 myops
[j
].X_add_number
= num
= 0;
1670 if (fm
->form
>= LONG
)
1672 /* If we're testing for a LONG format, either fits. */
1673 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1676 else if (fm
->form
< LONG
1677 && ((fsize
== FORCE_SHORT
&& X_op
== O_symbol
)
1678 || (fm
->form
== SHORT_D2
&& j
== 0)))
1680 /* This is the tricky part. Will the constant or symbol
1681 fit into the space in the current format? */
1682 else if (X_op
== O_constant
)
1684 if (check_range (num
, bits
, flags
))
1687 else if (X_op
== O_symbol
1688 && S_IS_DEFINED (myops
[j
].X_add_symbol
)
1689 && S_GET_SEGMENT (myops
[j
].X_add_symbol
) == now_seg
1690 && opcode
->reloc_flag
== RELOC_PCREL
)
1692 /* If the symbol is defined, see if the value will fit
1693 into the form we're considering. */
1697 /* Calculate the current address by running through the
1698 previous frags and adding our current offset. */
1700 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1701 value
+= f
->fr_fix
+ f
->fr_offset
;
1702 value
= (S_GET_VALUE (myops
[j
].X_add_symbol
) - value
1703 - (obstack_next_free (&frchain_now
->frch_obstack
)
1704 - frag_now
->fr_literal
));
1705 if (check_range (value
, bits
, flags
))
1712 /* printf("through the loop: match=%d\n",match); */
1713 /* We're only done if the operands matched so far AND there
1714 are no more to check. */
1715 if (match
&& myops
[j
].X_op
== 0)
1717 /* Final check - issue a warning if an odd numbered register
1718 is used as the first register in an instruction that reads
1719 or writes 2 registers. */
1721 for (j
= 0; fm
->operands
[j
]; j
++)
1722 if (myops
[j
].X_op
== O_register
1723 && (myops
[j
].X_add_number
& 1)
1724 && (d30v_operand_table
[fm
->operands
[j
]].flags
& OPERAND_2REG
))
1726 _("Odd numbered register used as target of multi-register instruction"));
1730 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1732 /* printf("trying another format: i=%d\n",i); */
1737 /* if while processing a fixup, a reloc really needs to be created */
1738 /* then it is done here */
1741 tc_gen_reloc (seg
, fixp
)
1746 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1747 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1748 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1749 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1750 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1751 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1753 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1754 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1757 reloc
->addend
= fixp
->fx_addnumber
;
1762 md_estimate_size_before_relax (fragp
, seg
)
1771 md_pcrel_from_section (fixp
, sec
)
1775 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1776 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1778 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1782 md_apply_fix3 (fixp
, valuep
, seg
)
1788 unsigned long insn
, insn2
;
1791 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1796 else if (fixp
->fx_pcrel
)
1800 value
= fixp
->fx_offset
;
1802 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1804 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1805 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1808 /* We don't actually support subtracting a symbol. */
1809 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1810 _("expression too complex"));
1815 /* Fetch the instruction, insert the fully resolved operand
1816 value, and stuff the instruction back again. */
1817 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1818 insn
= bfd_getb32 ((unsigned char *) where
);
1820 switch (fixp
->fx_r_type
)
1822 case BFD_RELOC_8
: /* Check for a bad .byte directive. */
1823 if (fixp
->fx_addsy
!= NULL
)
1824 as_bad (_("line %d: unable to place address of symbol '%s' into a byte"),
1825 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1826 else if (((unsigned)value
) > 0xff)
1827 as_bad (_("line %d: unable to place value %x into a byte"),
1828 fixp
->fx_line
, value
);
1830 * (unsigned char *) where
= value
;
1833 case BFD_RELOC_16
: /* Check for a bad .short directive. */
1834 if (fixp
->fx_addsy
!= NULL
)
1835 as_bad (_("line %d: unable to place address of symbol '%s' into a short"),
1836 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1837 else if (((unsigned)value
) > 0xffff)
1838 as_bad (_("line %d: unable to place value %x into a short"),
1839 fixp
->fx_line
, value
);
1841 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1844 case BFD_RELOC_64
: /* Check for a bad .quad directive. */
1845 if (fixp
->fx_addsy
!= NULL
)
1846 as_bad (_("line %d: unable to place address of symbol '%s' into a quad"),
1847 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1850 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1851 bfd_putb32 (0, ((unsigned char *) where
) + 4);
1855 case BFD_RELOC_D30V_6
:
1856 check_size (value
, 6, fixp
->fx_file
, fixp
->fx_line
);
1857 insn
|= value
& 0x3F;
1858 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1861 case BFD_RELOC_D30V_9_PCREL
:
1862 if (fixp
->fx_where
& 0x7)
1867 fixp
->fx_r_type
= BFD_RELOC_D30V_9_PCREL_R
;
1869 check_size (value
, 9, fixp
->fx_file
, fixp
->fx_line
);
1870 insn
|= ((value
>> 3) & 0x3F) << 12;
1871 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1874 case BFD_RELOC_D30V_15
:
1875 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1876 insn
|= (value
>> 3) & 0xFFF;
1877 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1880 case BFD_RELOC_D30V_15_PCREL
:
1881 if (fixp
->fx_where
& 0x7)
1886 fixp
->fx_r_type
= BFD_RELOC_D30V_15_PCREL_R
;
1888 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1889 insn
|= (value
>> 3) & 0xFFF;
1890 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1893 case BFD_RELOC_D30V_21
:
1894 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1895 insn
|= (value
>> 3) & 0x3FFFF;
1896 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1899 case BFD_RELOC_D30V_21_PCREL
:
1900 if (fixp
->fx_where
& 0x7)
1905 fixp
->fx_r_type
= BFD_RELOC_D30V_21_PCREL_R
;
1907 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1908 insn
|= (value
>> 3) & 0x3FFFF;
1909 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1912 case BFD_RELOC_D30V_32
:
1913 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1914 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1915 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1916 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1917 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1918 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1921 case BFD_RELOC_D30V_32_PCREL
:
1922 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1923 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1924 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1925 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1926 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1927 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1931 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1935 as_bad (_("line %d: unknown relocation type: 0x%x"),
1936 fixp
->fx_line
,fixp
->fx_r_type
);
1943 /* d30v_cleanup() is called after the assembler has finished parsing the input
1944 file or after a label is defined. Because the D30V assembler sometimes saves short
1945 instructions to see if it can package them with the next instruction, there may
1946 be a short instruction that still needs written. */
1948 d30v_cleanup (use_sequential
)
1954 if (prev_insn
!= -1)
1957 subseg
= now_subseg
;
1958 subseg_set (prev_seg
, prev_subseg
);
1959 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
, use_sequential
);
1960 subseg_set (seg
, subseg
);
1963 prev_mul32_p
= false;
1969 d30v_number_to_chars (buf
, value
, n
)
1970 char *buf
; /* Return 'nbytes' of chars here. */
1971 long long value
; /* The value of the bits. */
1972 int n
; /* Number of bytes in the output. */
1976 buf
[n
] = value
& 0xff;
1982 /* This function is called at the start of every line. */
1983 /* it checks to see if the first character is a '.' */
1984 /* which indicates the start of a pseudo-op. If it is, */
1985 /* then write out any unwritten instructions */
1990 char *c
= input_line_pointer
;
1992 while (isspace (*c
))
1996 d30v_cleanup (false);
2000 check_size (value
, bits
, file
, line
)
2013 max
= (1 << (bits
- 1)) - 1;
2016 as_bad_where (file
, line
, _("value too large to fit in %d bits"), bits
);
2021 /* d30v_frob_label() is called when after a label is recognized. */
2024 d30v_frob_label (lab
)
2027 /* Emit any pending instructions. */
2028 d30v_cleanup (false);
2030 /* Update the label's address with the current output pointer. */
2031 symbol_set_frag (lab
, frag_now
);
2032 S_SET_VALUE (lab
, (valueT
) frag_now_fix ());
2034 /* Record this label for future adjustment after we find out what
2035 kind of data it references, and the required alignment therewith. */
2036 d30v_last_label
= lab
;
2039 /* Hook into cons for capturing alignment changes. */
2042 d30v_cons_align (size
)
2048 while ((size
>>= 1) != 0)
2051 if (d30v_current_align
< log_size
)
2052 d30v_align (log_size
, (char *) NULL
, NULL
);
2053 else if (d30v_current_align
> log_size
)
2054 d30v_current_align
= log_size
;
2055 d30v_last_label
= NULL
;
2058 /* Called internally to handle all alignment needs. This takes care
2059 of eliding calls to frag_align if'n the cached current alignment
2060 says we've already got it, as well as taking care of the auto-aligning
2064 d30v_align (n
, pfill
, label
)
2069 /* The front end is prone to changing segments out from under us
2070 temporarily when -g is in effect. */
2071 int switched_seg_p
= (d30v_current_align_seg
!= now_seg
);
2073 /* Do not assume that if 'd30v_current_align >= n' and
2074 '! switched_seg_p' that it is safe to avoid performing
2075 this alignement request. The alignment of the current frag
2076 can be changed under our feet, for example by a .ascii
2077 directive in the source code. cf testsuite/gas/d30v/reloc.s */
2079 d30v_cleanup (false);
2084 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
2086 static char const nop
[4] = { 0x00, 0xf0, 0x00, 0x00 };
2088 /* First, make sure we're on a four-byte boundary, in case
2089 someone has been putting .byte values the text section. */
2090 if (d30v_current_align
< 2 || switched_seg_p
)
2091 frag_align (2, 0, 0);
2092 frag_align_pattern (n
, nop
, sizeof nop
, 0);
2095 frag_align (n
, 0, 0);
2098 frag_align (n
, *pfill
, 0);
2100 if (!switched_seg_p
)
2101 d30v_current_align
= n
;
2106 int label_seen
= false;
2107 struct frag
* old_frag
;
2111 assert (S_GET_SEGMENT (label
) == now_seg
);
2113 old_frag
= symbol_get_frag (label
);
2114 old_value
= S_GET_VALUE (label
);
2115 new_value
= (valueT
) frag_now_fix ();
2117 /* It is possible to have more than one label at a particular
2118 address, especially if debugging is enabled, so we must
2119 take care to adjust all the labels at this address in this
2120 fragment. To save time we search from the end of the symbol
2121 list, backwards, since the symbols we are interested in are
2122 almost certainly the ones that were most recently added.
2123 Also to save time we stop searching once we have seen at least
2124 one matching label, and we encounter a label that is no longer
2125 in the target fragment. Note, this search is guaranteed to
2126 find at least one match when sym == label, so no special case
2127 code is necessary. */
2128 for (sym
= symbol_lastP
; sym
!= NULL
; sym
= symbol_previous (sym
))
2130 if (symbol_get_frag (sym
) == old_frag
2131 && S_GET_VALUE (sym
) == old_value
)
2134 symbol_set_frag (sym
, frag_now
);
2135 S_SET_VALUE (sym
, new_value
);
2137 else if (label_seen
&& symbol_get_frag (sym
) != old_frag
)
2142 record_alignment (now_seg
, n
);
2145 /* Handle the .align pseudo-op. This aligns to a power of two. We
2146 hook here to latch the current alignment. */
2149 s_d30v_align (ignore
)
2153 char fill
, *pfill
= NULL
;
2154 long max_alignment
= 15;
2156 align
= get_absolute_expression ();
2157 if (align
> max_alignment
)
2159 align
= max_alignment
;
2160 as_warn (_("Alignment too large: %d assumed"), align
);
2164 as_warn (_("Alignment negative: 0 assumed"));
2168 if (*input_line_pointer
== ',')
2170 input_line_pointer
++;
2171 fill
= get_absolute_expression ();
2175 d30v_last_label
= NULL
;
2176 d30v_align (align
, pfill
, NULL
);
2178 demand_empty_rest_of_line ();
2181 /* Handle the .text pseudo-op. This is like the usual one, but it
2182 clears the saved last label and resets known alignment. */
2190 d30v_last_label
= NULL
;
2191 d30v_current_align
= 0;
2192 d30v_current_align_seg
= now_seg
;
2195 /* Handle the .data pseudo-op. This is like the usual one, but it
2196 clears the saved last label and resets known alignment. */
2203 d30v_last_label
= NULL
;
2204 d30v_current_align
= 0;
2205 d30v_current_align_seg
= now_seg
;
2208 /* Handle the .section pseudo-op. This is like the usual one, but it
2209 clears the saved last label and resets known alignment. */
2212 s_d30v_section (ignore
)
2215 obj_elf_section (ignore
);
2216 d30v_last_label
= NULL
;
2217 d30v_current_align
= 0;
2218 d30v_current_align_seg
= now_seg
;