1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 /* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
26 x86_64 support by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
32 #include "safe-ctype.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef INFER_ADDR_PREFIX
44 #define INFER_ADDR_PREFIX 1
48 #define DEFAULT_ARCH "i386"
53 #define INLINE __inline__
59 /* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
69 #define HLE_PREFIX REP_PREFIX
71 #define REX_PREFIX 6 /* must come last. */
72 #define MAX_PREFIXES 7 /* max prefixes per opcode */
74 /* we define the syntax here (modulo base,index,scale syntax) */
75 #define REGISTER_PREFIX '%'
76 #define IMMEDIATE_PREFIX '$'
77 #define ABSOLUTE_PREFIX '*'
79 /* these are the instruction mnemonic suffixes in AT&T syntax or
80 memory operand size in Intel syntax. */
81 #define WORD_MNEM_SUFFIX 'w'
82 #define BYTE_MNEM_SUFFIX 'b'
83 #define SHORT_MNEM_SUFFIX 's'
84 #define LONG_MNEM_SUFFIX 'l'
85 #define QWORD_MNEM_SUFFIX 'q'
86 #define XMMWORD_MNEM_SUFFIX 'x'
87 #define YMMWORD_MNEM_SUFFIX 'y'
88 /* Intel Syntax. Use a non-ascii letter since since it never appears
90 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
92 #define END_OF_INSN '\0'
95 'templates' is for grouping together 'template' structures for opcodes
96 of the same name. This is only used for storing the insns in the grand
97 ole hash table of insns.
98 The templates themselves start at START and range up to (but not including)
103 const insn_template
*start
;
104 const insn_template
*end
;
108 /* 386 operand encoding bytes: see 386 book for details of this. */
111 unsigned int regmem
; /* codes register or memory operand */
112 unsigned int reg
; /* codes register operand (or extended opcode) */
113 unsigned int mode
; /* how to interpret regmem & reg */
117 /* x86-64 extension prefix. */
118 typedef int rex_byte
;
120 /* 386 opcode byte to code indirect addressing. */
129 /* x86 arch names, types and features */
132 const char *name
; /* arch name */
133 unsigned int len
; /* arch string length */
134 enum processor_type type
; /* arch type */
135 i386_cpu_flags flags
; /* cpu feature flags */
136 unsigned int skip
; /* show_arch should skip this. */
137 unsigned int negated
; /* turn off indicated flags. */
141 static void update_code_flag (int, int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
152 static void signed_cons (int);
153 static char *output_invalid (int c
);
154 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
156 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
158 static int i386_att_operand (char *);
159 static int i386_intel_operand (char *, int);
160 static int i386_intel_simplify (expressionS
*);
161 static int i386_intel_parse_name (const char *, expressionS
*);
162 static const reg_entry
*parse_register (char *, char **);
163 static char *parse_insn (char *, char *);
164 static char *parse_operands (char *, const char *);
165 static void swap_operands (void);
166 static void swap_2_operands (int, int);
167 static void optimize_imm (void);
168 static void optimize_disp (void);
169 static const insn_template
*match_template (void);
170 static int check_string (void);
171 static int process_suffix (void);
172 static int check_byte_reg (void);
173 static int check_long_reg (void);
174 static int check_qword_reg (void);
175 static int check_word_reg (void);
176 static int finalize_imm (void);
177 static int process_operands (void);
178 static const seg_entry
*build_modrm_byte (void);
179 static void output_insn (void);
180 static void output_imm (fragS
*, offsetT
);
181 static void output_disp (fragS
*, offsetT
);
183 static void s_bss (int);
185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
186 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
189 static const char *default_arch
= DEFAULT_ARCH
;
194 /* VEX prefix is either 2 byte or 3 byte. */
195 unsigned char bytes
[3];
197 /* Destination or source register specifier. */
198 const reg_entry
*register_specifier
;
201 /* 'md_assemble ()' gathers together information and puts it into a
208 const reg_entry
*regs
;
213 operand_size_mismatch
,
214 operand_type_mismatch
,
215 register_type_mismatch
,
216 number_of_operands_mismatch
,
217 invalid_instruction_suffix
,
220 unsupported_with_intel_mnemonic
,
223 invalid_vsib_address
,
224 invalid_vector_register_set
,
225 unsupported_vector_index_register
230 /* TM holds the template for the insn were currently assembling. */
233 /* SUFFIX holds the instruction size suffix for byte, word, dword
234 or qword, if given. */
237 /* OPERANDS gives the number of given operands. */
238 unsigned int operands
;
240 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
241 of given register, displacement, memory operands and immediate
243 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
245 /* TYPES [i] is the type (see above #defines) which tells us how to
246 use OP[i] for the corresponding operand. */
247 i386_operand_type types
[MAX_OPERANDS
];
249 /* Displacement expression, immediate expression, or register for each
251 union i386_op op
[MAX_OPERANDS
];
253 /* Flags for operands. */
254 unsigned int flags
[MAX_OPERANDS
];
255 #define Operand_PCrel 1
257 /* Relocation type for operand */
258 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
260 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
261 the base index byte below. */
262 const reg_entry
*base_reg
;
263 const reg_entry
*index_reg
;
264 unsigned int log2_scale_factor
;
266 /* SEG gives the seg_entries of this insn. They are zero unless
267 explicit segment overrides are given. */
268 const seg_entry
*seg
[2];
270 /* PREFIX holds all the given prefix opcodes (usually null).
271 PREFIXES is the number of prefix opcodes. */
272 unsigned int prefixes
;
273 unsigned char prefix
[MAX_PREFIXES
];
275 /* RM and SIB are the modrm byte and the sib byte where the
276 addressing modes of this insn are encoded. */
282 /* Swap operand in encoding. */
283 unsigned int swap_operand
;
285 /* Prefer 8bit or 32bit displacement in encoding. */
288 disp_encoding_default
= 0,
293 /* Have HLE prefix. */
294 unsigned int have_hle
;
297 enum i386_error error
;
300 typedef struct _i386_insn i386_insn
;
302 /* List of chars besides those in app.c:symbol_chars that can start an
303 operand. Used to prevent the scrubber eating vital white-space. */
304 const char extra_symbol_chars
[] = "*%-(["
313 #if (defined (TE_I386AIX) \
314 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
315 && !defined (TE_GNU) \
316 && !defined (TE_LINUX) \
317 && !defined (TE_NACL) \
318 && !defined (TE_NETWARE) \
319 && !defined (TE_FreeBSD) \
320 && !defined (TE_DragonFly) \
321 && !defined (TE_NetBSD)))
322 /* This array holds the chars that always start a comment. If the
323 pre-processor is disabled, these aren't very useful. The option
324 --divide will remove '/' from this list. */
325 const char *i386_comment_chars
= "#/";
326 #define SVR4_COMMENT_CHARS 1
327 #define PREFIX_SEPARATOR '\\'
330 const char *i386_comment_chars
= "#";
331 #define PREFIX_SEPARATOR '/'
334 /* This array holds the chars that only start a comment at the beginning of
335 a line. If the line seems to have the form '# 123 filename'
336 .line and .file directives will appear in the pre-processed output.
337 Note that input_file.c hand checks for '#' at the beginning of the
338 first line of the input file. This is because the compiler outputs
339 #NO_APP at the beginning of its output.
340 Also note that comments started like this one will always work if
341 '/' isn't otherwise defined. */
342 const char line_comment_chars
[] = "#/";
344 const char line_separator_chars
[] = ";";
346 /* Chars that can be used to separate mant from exp in floating point
348 const char EXP_CHARS
[] = "eE";
350 /* Chars that mean this number is a floating point constant
353 const char FLT_CHARS
[] = "fFdDxX";
355 /* Tables for lexical analysis. */
356 static char mnemonic_chars
[256];
357 static char register_chars
[256];
358 static char operand_chars
[256];
359 static char identifier_chars
[256];
360 static char digit_chars
[256];
362 /* Lexical macros. */
363 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
364 #define is_operand_char(x) (operand_chars[(unsigned char) x])
365 #define is_register_char(x) (register_chars[(unsigned char) x])
366 #define is_space_char(x) ((x) == ' ')
367 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
368 #define is_digit_char(x) (digit_chars[(unsigned char) x])
370 /* All non-digit non-letter characters that may occur in an operand. */
371 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
373 /* md_assemble() always leaves the strings it's passed unaltered. To
374 effect this we maintain a stack of saved characters that we've smashed
375 with '\0's (indicating end of strings for various sub-fields of the
376 assembler instruction). */
377 static char save_stack
[32];
378 static char *save_stack_p
;
379 #define END_STRING_AND_SAVE(s) \
380 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
381 #define RESTORE_END_STRING(s) \
382 do { *(s) = *--save_stack_p; } while (0)
384 /* The instruction we're assembling. */
387 /* Possible templates for current insn. */
388 static const templates
*current_templates
;
390 /* Per instruction expressionS buffers: max displacements & immediates. */
391 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
392 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
394 /* Current operand we are working on. */
395 static int this_operand
= -1;
397 /* We support four different modes. FLAG_CODE variable is used to distinguish
405 static enum flag_code flag_code
;
406 static unsigned int object_64bit
;
407 static unsigned int disallow_64bit_reloc
;
408 static int use_rela_relocations
= 0;
410 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
411 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
412 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
414 /* The ELF ABI to use. */
422 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
425 /* The names used to print error messages. */
426 static const char *flag_code_names
[] =
433 /* 1 for intel syntax,
435 static int intel_syntax
= 0;
437 /* 1 for intel mnemonic,
438 0 if att mnemonic. */
439 static int intel_mnemonic
= !SYSV386_COMPAT
;
441 /* 1 if support old (<= 2.8.1) versions of gcc. */
442 static int old_gcc
= OLDGCC_COMPAT
;
444 /* 1 if pseudo registers are permitted. */
445 static int allow_pseudo_reg
= 0;
447 /* 1 if register prefix % not required. */
448 static int allow_naked_reg
= 0;
450 /* 1 if pseudo index register, eiz/riz, is allowed . */
451 static int allow_index_reg
= 0;
453 static enum check_kind
459 sse_check
, operand_check
= check_warning
;
461 /* Register prefix used for error message. */
462 static const char *register_prefix
= "%";
464 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
465 leave, push, and pop instructions so that gcc has the same stack
466 frame as in 32 bit mode. */
467 static char stackop_size
= '\0';
469 /* Non-zero to optimize code alignment. */
470 int optimize_align_code
= 1;
472 /* Non-zero to quieten some warnings. */
473 static int quiet_warnings
= 0;
476 static const char *cpu_arch_name
= NULL
;
477 static char *cpu_sub_arch_name
= NULL
;
479 /* CPU feature flags. */
480 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
482 /* If we have selected a cpu we are generating instructions for. */
483 static int cpu_arch_tune_set
= 0;
485 /* Cpu we are generating instructions for. */
486 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
488 /* CPU feature flags of cpu we are generating instructions for. */
489 static i386_cpu_flags cpu_arch_tune_flags
;
491 /* CPU instruction set architecture used. */
492 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
494 /* CPU feature flags of instruction set architecture used. */
495 i386_cpu_flags cpu_arch_isa_flags
;
497 /* If set, conditional jumps are not automatically promoted to handle
498 larger than a byte offset. */
499 static unsigned int no_cond_jump_promotion
= 0;
501 /* Encode SSE instructions with VEX prefix. */
502 static unsigned int sse2avx
;
504 /* Encode scalar AVX instructions with specific vector length. */
511 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
512 static symbolS
*GOT_symbol
;
514 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
515 unsigned int x86_dwarf2_return_column
;
517 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
518 int x86_cie_data_alignment
;
520 /* Interface to relax_segment.
521 There are 3 major relax states for 386 jump insns because the
522 different types of jumps add different sizes to frags when we're
523 figuring out what sort of jump to choose to reach a given label. */
526 #define UNCOND_JUMP 0
528 #define COND_JUMP86 2
533 #define SMALL16 (SMALL | CODE16)
535 #define BIG16 (BIG | CODE16)
539 #define INLINE __inline__
545 #define ENCODE_RELAX_STATE(type, size) \
546 ((relax_substateT) (((type) << 2) | (size)))
547 #define TYPE_FROM_RELAX_STATE(s) \
549 #define DISP_SIZE_FROM_RELAX_STATE(s) \
550 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
552 /* This table is used by relax_frag to promote short jumps to long
553 ones where necessary. SMALL (short) jumps may be promoted to BIG
554 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
555 don't allow a short jump in a 32 bit code segment to be promoted to
556 a 16 bit offset jump because it's slower (requires data size
557 prefix), and doesn't work, unless the destination is in the bottom
558 64k of the code segment (The top 16 bits of eip are zeroed). */
560 const relax_typeS md_relax_table
[] =
563 1) most positive reach of this state,
564 2) most negative reach of this state,
565 3) how many bytes this mode will have in the variable part of the frag
566 4) which index into the table to try if we can't fit into this one. */
568 /* UNCOND_JUMP states. */
569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
570 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
571 /* dword jmp adds 4 bytes to frag:
572 0 extra opcode bytes, 4 displacement bytes. */
574 /* word jmp adds 2 byte2 to frag:
575 0 extra opcode bytes, 2 displacement bytes. */
578 /* COND_JUMP states. */
579 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
580 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
581 /* dword conditionals adds 5 bytes to frag:
582 1 extra opcode byte, 4 displacement bytes. */
584 /* word conditionals add 3 bytes to frag:
585 1 extra opcode byte, 2 displacement bytes. */
588 /* COND_JUMP86 states. */
589 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
590 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
591 /* dword conditionals adds 5 bytes to frag:
592 1 extra opcode byte, 4 displacement bytes. */
594 /* word conditionals add 4 bytes to frag:
595 1 displacement byte and a 3 byte long branch insn. */
599 static const arch_entry cpu_arch
[] =
601 /* Do not replace the first two entries - i386_target_format()
602 relies on them being there in this order. */
603 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
604 CPU_GENERIC32_FLAGS
, 0, 0 },
605 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
606 CPU_GENERIC64_FLAGS
, 0, 0 },
607 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
608 CPU_NONE_FLAGS
, 0, 0 },
609 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
610 CPU_I186_FLAGS
, 0, 0 },
611 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
612 CPU_I286_FLAGS
, 0, 0 },
613 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
614 CPU_I386_FLAGS
, 0, 0 },
615 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
616 CPU_I486_FLAGS
, 0, 0 },
617 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
618 CPU_I586_FLAGS
, 0, 0 },
619 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
620 CPU_I686_FLAGS
, 0, 0 },
621 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
622 CPU_I586_FLAGS
, 0, 0 },
623 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
624 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
625 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
626 CPU_P2_FLAGS
, 0, 0 },
627 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
628 CPU_P3_FLAGS
, 0, 0 },
629 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
630 CPU_P4_FLAGS
, 0, 0 },
631 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
632 CPU_CORE_FLAGS
, 0, 0 },
633 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
634 CPU_NOCONA_FLAGS
, 0, 0 },
635 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
636 CPU_CORE_FLAGS
, 1, 0 },
637 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
638 CPU_CORE_FLAGS
, 0, 0 },
639 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
640 CPU_CORE2_FLAGS
, 1, 0 },
641 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
642 CPU_CORE2_FLAGS
, 0, 0 },
643 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
644 CPU_COREI7_FLAGS
, 0, 0 },
645 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
646 CPU_L1OM_FLAGS
, 0, 0 },
647 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
648 CPU_K1OM_FLAGS
, 0, 0 },
649 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
650 CPU_K6_FLAGS
, 0, 0 },
651 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
652 CPU_K6_2_FLAGS
, 0, 0 },
653 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
654 CPU_ATHLON_FLAGS
, 0, 0 },
655 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
656 CPU_K8_FLAGS
, 1, 0 },
657 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
658 CPU_K8_FLAGS
, 0, 0 },
659 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
660 CPU_K8_FLAGS
, 0, 0 },
661 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
662 CPU_AMDFAM10_FLAGS
, 0, 0 },
663 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
664 CPU_BDVER1_FLAGS
, 0, 0 },
665 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
666 CPU_BDVER2_FLAGS
, 0, 0 },
667 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
668 CPU_BTVER1_FLAGS
, 0, 0 },
669 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
670 CPU_BTVER2_FLAGS
, 0, 0 },
671 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
672 CPU_8087_FLAGS
, 0, 0 },
673 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
674 CPU_287_FLAGS
, 0, 0 },
675 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
676 CPU_387_FLAGS
, 0, 0 },
677 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
678 CPU_ANY87_FLAGS
, 0, 1 },
679 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
680 CPU_MMX_FLAGS
, 0, 0 },
681 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
682 CPU_3DNOWA_FLAGS
, 0, 1 },
683 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
684 CPU_SSE_FLAGS
, 0, 0 },
685 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
686 CPU_SSE2_FLAGS
, 0, 0 },
687 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
688 CPU_SSE3_FLAGS
, 0, 0 },
689 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
690 CPU_SSSE3_FLAGS
, 0, 0 },
691 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
692 CPU_SSE4_1_FLAGS
, 0, 0 },
693 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
694 CPU_SSE4_2_FLAGS
, 0, 0 },
695 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
696 CPU_SSE4_2_FLAGS
, 0, 0 },
697 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
698 CPU_ANY_SSE_FLAGS
, 0, 1 },
699 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
700 CPU_AVX_FLAGS
, 0, 0 },
701 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
702 CPU_AVX2_FLAGS
, 0, 0 },
703 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
704 CPU_ANY_AVX_FLAGS
, 0, 1 },
705 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
706 CPU_VMX_FLAGS
, 0, 0 },
707 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
708 CPU_VMFUNC_FLAGS
, 0, 0 },
709 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
710 CPU_SMX_FLAGS
, 0, 0 },
711 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
712 CPU_XSAVE_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
714 CPU_XSAVEOPT_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
716 CPU_AES_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
718 CPU_PCLMUL_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
720 CPU_PCLMUL_FLAGS
, 1, 0 },
721 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
722 CPU_FSGSBASE_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
724 CPU_RDRND_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
726 CPU_F16C_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
728 CPU_BMI2_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
730 CPU_FMA_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
732 CPU_FMA4_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
734 CPU_XOP_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
736 CPU_LWP_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
738 CPU_MOVBE_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
740 CPU_CX16_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
742 CPU_EPT_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
744 CPU_LZCNT_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
746 CPU_HLE_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
748 CPU_RTM_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
750 CPU_INVPCID_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
752 CPU_CLFLUSH_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
754 CPU_NOP_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
756 CPU_SYSCALL_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
758 CPU_RDTSCP_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
760 CPU_3DNOW_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
762 CPU_3DNOWA_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
764 CPU_PADLOCK_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
766 CPU_SVME_FLAGS
, 1, 0 },
767 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
768 CPU_SVME_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
770 CPU_SSE4A_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
772 CPU_ABM_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
774 CPU_BMI_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
776 CPU_TBM_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
778 CPU_ADX_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
780 CPU_RDSEED_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
782 CPU_PRFCHW_FLAGS
, 0, 0 },
786 /* Like s_lcomm_internal in gas/read.c but the alignment string
787 is allowed to be optional. */
790 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
797 && *input_line_pointer
== ',')
799 align
= parse_align (needs_align
- 1);
801 if (align
== (addressT
) -1)
816 bss_alloc (symbolP
, size
, align
);
821 pe_lcomm (int needs_align
)
823 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
827 const pseudo_typeS md_pseudo_table
[] =
829 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
830 {"align", s_align_bytes
, 0},
832 {"align", s_align_ptwo
, 0},
834 {"arch", set_cpu_arch
, 0},
838 {"lcomm", pe_lcomm
, 1},
840 {"ffloat", float_cons
, 'f'},
841 {"dfloat", float_cons
, 'd'},
842 {"tfloat", float_cons
, 'x'},
844 {"slong", signed_cons
, 4},
845 {"noopt", s_ignore
, 0},
846 {"optim", s_ignore
, 0},
847 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
848 {"code16", set_code_flag
, CODE_16BIT
},
849 {"code32", set_code_flag
, CODE_32BIT
},
850 {"code64", set_code_flag
, CODE_64BIT
},
851 {"intel_syntax", set_intel_syntax
, 1},
852 {"att_syntax", set_intel_syntax
, 0},
853 {"intel_mnemonic", set_intel_mnemonic
, 1},
854 {"att_mnemonic", set_intel_mnemonic
, 0},
855 {"allow_index_reg", set_allow_index_reg
, 1},
856 {"disallow_index_reg", set_allow_index_reg
, 0},
857 {"sse_check", set_check
, 0},
858 {"operand_check", set_check
, 1},
859 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
860 {"largecomm", handle_large_common
, 0},
862 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
863 {"loc", dwarf2_directive_loc
, 0},
864 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
867 {"secrel32", pe_directive_secrel
, 0},
872 /* For interface with expression (). */
873 extern char *input_line_pointer
;
875 /* Hash table for instruction mnemonic lookup. */
876 static struct hash_control
*op_hash
;
878 /* Hash table for register lookup. */
879 static struct hash_control
*reg_hash
;
882 i386_align_code (fragS
*fragP
, int count
)
884 /* Various efficient no-op patterns for aligning code labels.
885 Note: Don't try to assemble the instructions in the comments.
886 0L and 0w are not legal. */
887 static const char f32_1
[] =
889 static const char f32_2
[] =
890 {0x66,0x90}; /* xchg %ax,%ax */
891 static const char f32_3
[] =
892 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
893 static const char f32_4
[] =
894 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
895 static const char f32_5
[] =
897 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
898 static const char f32_6
[] =
899 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
900 static const char f32_7
[] =
901 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
902 static const char f32_8
[] =
904 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
905 static const char f32_9
[] =
906 {0x89,0xf6, /* movl %esi,%esi */
907 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
908 static const char f32_10
[] =
909 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
910 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
911 static const char f32_11
[] =
912 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
913 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
914 static const char f32_12
[] =
915 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
916 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
917 static const char f32_13
[] =
918 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
919 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
920 static const char f32_14
[] =
921 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
922 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
923 static const char f16_3
[] =
924 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
925 static const char f16_4
[] =
926 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
927 static const char f16_5
[] =
929 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
930 static const char f16_6
[] =
931 {0x89,0xf6, /* mov %si,%si */
932 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
933 static const char f16_7
[] =
934 {0x8d,0x74,0x00, /* lea 0(%si),%si */
935 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
936 static const char f16_8
[] =
937 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
938 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
939 static const char jump_31
[] =
940 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
941 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
942 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
943 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
944 static const char *const f32_patt
[] = {
945 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
946 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
948 static const char *const f16_patt
[] = {
949 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
952 static const char alt_3
[] =
954 /* nopl 0(%[re]ax) */
955 static const char alt_4
[] =
956 {0x0f,0x1f,0x40,0x00};
957 /* nopl 0(%[re]ax,%[re]ax,1) */
958 static const char alt_5
[] =
959 {0x0f,0x1f,0x44,0x00,0x00};
960 /* nopw 0(%[re]ax,%[re]ax,1) */
961 static const char alt_6
[] =
962 {0x66,0x0f,0x1f,0x44,0x00,0x00};
963 /* nopl 0L(%[re]ax) */
964 static const char alt_7
[] =
965 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
966 /* nopl 0L(%[re]ax,%[re]ax,1) */
967 static const char alt_8
[] =
968 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
969 /* nopw 0L(%[re]ax,%[re]ax,1) */
970 static const char alt_9
[] =
971 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
972 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
973 static const char alt_10
[] =
974 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
976 nopw %cs:0L(%[re]ax,%[re]ax,1) */
977 static const char alt_long_11
[] =
979 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
982 nopw %cs:0L(%[re]ax,%[re]ax,1) */
983 static const char alt_long_12
[] =
986 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
990 nopw %cs:0L(%[re]ax,%[re]ax,1) */
991 static const char alt_long_13
[] =
995 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1000 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1001 static const char alt_long_14
[] =
1006 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1012 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1013 static const char alt_long_15
[] =
1019 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1020 /* nopl 0(%[re]ax,%[re]ax,1)
1021 nopw 0(%[re]ax,%[re]ax,1) */
1022 static const char alt_short_11
[] =
1023 {0x0f,0x1f,0x44,0x00,0x00,
1024 0x66,0x0f,0x1f,0x44,0x00,0x00};
1025 /* nopw 0(%[re]ax,%[re]ax,1)
1026 nopw 0(%[re]ax,%[re]ax,1) */
1027 static const char alt_short_12
[] =
1028 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1029 0x66,0x0f,0x1f,0x44,0x00,0x00};
1030 /* nopw 0(%[re]ax,%[re]ax,1)
1032 static const char alt_short_13
[] =
1033 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1034 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1037 static const char alt_short_14
[] =
1038 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1039 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1041 nopl 0L(%[re]ax,%[re]ax,1) */
1042 static const char alt_short_15
[] =
1043 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1044 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1045 static const char *const alt_short_patt
[] = {
1046 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1047 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1048 alt_short_14
, alt_short_15
1050 static const char *const alt_long_patt
[] = {
1051 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1052 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1053 alt_long_14
, alt_long_15
1056 /* Only align for at least a positive non-zero boundary. */
1057 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1060 /* We need to decide which NOP sequence to use for 32bit and
1061 64bit. When -mtune= is used:
1063 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1064 PROCESSOR_GENERIC32, f32_patt will be used.
1065 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1066 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1067 PROCESSOR_GENERIC64, alt_long_patt will be used.
1068 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1069 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1072 When -mtune= isn't used, alt_long_patt will be used if
1073 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1076 When -march= or .arch is used, we can't use anything beyond
1077 cpu_arch_isa_flags. */
1079 if (flag_code
== CODE_16BIT
)
1083 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1085 /* Adjust jump offset. */
1086 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1089 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1090 f16_patt
[count
- 1], count
);
1094 const char *const *patt
= NULL
;
1096 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1098 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1099 switch (cpu_arch_tune
)
1101 case PROCESSOR_UNKNOWN
:
1102 /* We use cpu_arch_isa_flags to check if we SHOULD
1103 optimize with nops. */
1104 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1105 patt
= alt_long_patt
;
1109 case PROCESSOR_PENTIUM4
:
1110 case PROCESSOR_NOCONA
:
1111 case PROCESSOR_CORE
:
1112 case PROCESSOR_CORE2
:
1113 case PROCESSOR_COREI7
:
1114 case PROCESSOR_L1OM
:
1115 case PROCESSOR_K1OM
:
1116 case PROCESSOR_GENERIC64
:
1117 patt
= alt_long_patt
;
1120 case PROCESSOR_ATHLON
:
1122 case PROCESSOR_AMDFAM10
:
1125 patt
= alt_short_patt
;
1127 case PROCESSOR_I386
:
1128 case PROCESSOR_I486
:
1129 case PROCESSOR_PENTIUM
:
1130 case PROCESSOR_PENTIUMPRO
:
1131 case PROCESSOR_GENERIC32
:
1138 switch (fragP
->tc_frag_data
.tune
)
1140 case PROCESSOR_UNKNOWN
:
1141 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1142 PROCESSOR_UNKNOWN. */
1146 case PROCESSOR_I386
:
1147 case PROCESSOR_I486
:
1148 case PROCESSOR_PENTIUM
:
1150 case PROCESSOR_ATHLON
:
1152 case PROCESSOR_AMDFAM10
:
1155 case PROCESSOR_GENERIC32
:
1156 /* We use cpu_arch_isa_flags to check if we CAN optimize
1158 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1159 patt
= alt_short_patt
;
1163 case PROCESSOR_PENTIUMPRO
:
1164 case PROCESSOR_PENTIUM4
:
1165 case PROCESSOR_NOCONA
:
1166 case PROCESSOR_CORE
:
1167 case PROCESSOR_CORE2
:
1168 case PROCESSOR_COREI7
:
1169 case PROCESSOR_L1OM
:
1170 case PROCESSOR_K1OM
:
1171 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1172 patt
= alt_long_patt
;
1176 case PROCESSOR_GENERIC64
:
1177 patt
= alt_long_patt
;
1182 if (patt
== f32_patt
)
1184 /* If the padding is less than 15 bytes, we use the normal
1185 ones. Otherwise, we use a jump instruction and adjust
1189 /* For 64bit, the limit is 3 bytes. */
1190 if (flag_code
== CODE_64BIT
1191 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1196 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1197 patt
[count
- 1], count
);
1200 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1202 /* Adjust jump offset. */
1203 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1208 /* Maximum length of an instruction is 15 byte. If the
1209 padding is greater than 15 bytes and we don't use jump,
1210 we have to break it into smaller pieces. */
1211 int padding
= count
;
1212 while (padding
> 15)
1215 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1220 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1221 patt
[padding
- 1], padding
);
1224 fragP
->fr_var
= count
;
1228 operand_type_all_zero (const union i386_operand_type
*x
)
1230 switch (ARRAY_SIZE(x
->array
))
1239 return !x
->array
[0];
1246 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1248 switch (ARRAY_SIZE(x
->array
))
1263 operand_type_equal (const union i386_operand_type
*x
,
1264 const union i386_operand_type
*y
)
1266 switch (ARRAY_SIZE(x
->array
))
1269 if (x
->array
[2] != y
->array
[2])
1272 if (x
->array
[1] != y
->array
[1])
1275 return x
->array
[0] == y
->array
[0];
1283 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1285 switch (ARRAY_SIZE(x
->array
))
1294 return !x
->array
[0];
1301 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1303 switch (ARRAY_SIZE(x
->array
))
1318 cpu_flags_equal (const union i386_cpu_flags
*x
,
1319 const union i386_cpu_flags
*y
)
1321 switch (ARRAY_SIZE(x
->array
))
1324 if (x
->array
[2] != y
->array
[2])
1327 if (x
->array
[1] != y
->array
[1])
1330 return x
->array
[0] == y
->array
[0];
1338 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1340 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1341 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1344 static INLINE i386_cpu_flags
1345 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1347 switch (ARRAY_SIZE (x
.array
))
1350 x
.array
[2] &= y
.array
[2];
1352 x
.array
[1] &= y
.array
[1];
1354 x
.array
[0] &= y
.array
[0];
1362 static INLINE i386_cpu_flags
1363 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1365 switch (ARRAY_SIZE (x
.array
))
1368 x
.array
[2] |= y
.array
[2];
1370 x
.array
[1] |= y
.array
[1];
1372 x
.array
[0] |= y
.array
[0];
1380 static INLINE i386_cpu_flags
1381 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1383 switch (ARRAY_SIZE (x
.array
))
1386 x
.array
[2] &= ~y
.array
[2];
1388 x
.array
[1] &= ~y
.array
[1];
1390 x
.array
[0] &= ~y
.array
[0];
1398 #define CPU_FLAGS_ARCH_MATCH 0x1
1399 #define CPU_FLAGS_64BIT_MATCH 0x2
1400 #define CPU_FLAGS_AES_MATCH 0x4
1401 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1402 #define CPU_FLAGS_AVX_MATCH 0x10
1404 #define CPU_FLAGS_32BIT_MATCH \
1405 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1406 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1407 #define CPU_FLAGS_PERFECT_MATCH \
1408 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1410 /* Return CPU flags match bits. */
1413 cpu_flags_match (const insn_template
*t
)
1415 i386_cpu_flags x
= t
->cpu_flags
;
1416 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1418 x
.bitfield
.cpu64
= 0;
1419 x
.bitfield
.cpuno64
= 0;
1421 if (cpu_flags_all_zero (&x
))
1423 /* This instruction is available on all archs. */
1424 match
|= CPU_FLAGS_32BIT_MATCH
;
1428 /* This instruction is available only on some archs. */
1429 i386_cpu_flags cpu
= cpu_arch_flags
;
1431 cpu
.bitfield
.cpu64
= 0;
1432 cpu
.bitfield
.cpuno64
= 0;
1433 cpu
= cpu_flags_and (x
, cpu
);
1434 if (!cpu_flags_all_zero (&cpu
))
1436 if (x
.bitfield
.cpuavx
)
1438 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1439 if (cpu
.bitfield
.cpuavx
)
1441 /* Check SSE2AVX. */
1442 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1444 match
|= (CPU_FLAGS_ARCH_MATCH
1445 | CPU_FLAGS_AVX_MATCH
);
1447 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1448 match
|= CPU_FLAGS_AES_MATCH
;
1450 if (!x
.bitfield
.cpupclmul
1451 || cpu
.bitfield
.cpupclmul
)
1452 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1456 match
|= CPU_FLAGS_ARCH_MATCH
;
1459 match
|= CPU_FLAGS_32BIT_MATCH
;
1465 static INLINE i386_operand_type
1466 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1468 switch (ARRAY_SIZE (x
.array
))
1471 x
.array
[2] &= y
.array
[2];
1473 x
.array
[1] &= y
.array
[1];
1475 x
.array
[0] &= y
.array
[0];
1483 static INLINE i386_operand_type
1484 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1486 switch (ARRAY_SIZE (x
.array
))
1489 x
.array
[2] |= y
.array
[2];
1491 x
.array
[1] |= y
.array
[1];
1493 x
.array
[0] |= y
.array
[0];
1501 static INLINE i386_operand_type
1502 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1504 switch (ARRAY_SIZE (x
.array
))
1507 x
.array
[2] ^= y
.array
[2];
1509 x
.array
[1] ^= y
.array
[1];
1511 x
.array
[0] ^= y
.array
[0];
1519 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1520 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1521 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1522 static const i386_operand_type inoutportreg
1523 = OPERAND_TYPE_INOUTPORTREG
;
1524 static const i386_operand_type reg16_inoutportreg
1525 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1526 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1527 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1528 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1529 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1530 static const i386_operand_type anydisp
1531 = OPERAND_TYPE_ANYDISP
;
1532 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1533 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1534 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1535 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1536 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1537 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1538 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1539 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1540 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1541 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1542 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1543 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1554 operand_type_check (i386_operand_type t
, enum operand_type c
)
1559 return (t
.bitfield
.reg8
1562 || t
.bitfield
.reg64
);
1565 return (t
.bitfield
.imm8
1569 || t
.bitfield
.imm32s
1570 || t
.bitfield
.imm64
);
1573 return (t
.bitfield
.disp8
1574 || t
.bitfield
.disp16
1575 || t
.bitfield
.disp32
1576 || t
.bitfield
.disp32s
1577 || t
.bitfield
.disp64
);
1580 return (t
.bitfield
.disp8
1581 || t
.bitfield
.disp16
1582 || t
.bitfield
.disp32
1583 || t
.bitfield
.disp32s
1584 || t
.bitfield
.disp64
1585 || t
.bitfield
.baseindex
);
1594 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1595 operand J for instruction template T. */
1598 match_reg_size (const insn_template
*t
, unsigned int j
)
1600 return !((i
.types
[j
].bitfield
.byte
1601 && !t
->operand_types
[j
].bitfield
.byte
)
1602 || (i
.types
[j
].bitfield
.word
1603 && !t
->operand_types
[j
].bitfield
.word
)
1604 || (i
.types
[j
].bitfield
.dword
1605 && !t
->operand_types
[j
].bitfield
.dword
)
1606 || (i
.types
[j
].bitfield
.qword
1607 && !t
->operand_types
[j
].bitfield
.qword
));
1610 /* Return 1 if there is no conflict in any size on operand J for
1611 instruction template T. */
1614 match_mem_size (const insn_template
*t
, unsigned int j
)
1616 return (match_reg_size (t
, j
)
1617 && !((i
.types
[j
].bitfield
.unspecified
1618 && !t
->operand_types
[j
].bitfield
.unspecified
)
1619 || (i
.types
[j
].bitfield
.fword
1620 && !t
->operand_types
[j
].bitfield
.fword
)
1621 || (i
.types
[j
].bitfield
.tbyte
1622 && !t
->operand_types
[j
].bitfield
.tbyte
)
1623 || (i
.types
[j
].bitfield
.xmmword
1624 && !t
->operand_types
[j
].bitfield
.xmmword
)
1625 || (i
.types
[j
].bitfield
.ymmword
1626 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1629 /* Return 1 if there is no size conflict on any operands for
1630 instruction template T. */
1633 operand_size_match (const insn_template
*t
)
1638 /* Don't check jump instructions. */
1639 if (t
->opcode_modifier
.jump
1640 || t
->opcode_modifier
.jumpbyte
1641 || t
->opcode_modifier
.jumpdword
1642 || t
->opcode_modifier
.jumpintersegment
)
1645 /* Check memory and accumulator operand size. */
1646 for (j
= 0; j
< i
.operands
; j
++)
1648 if (t
->operand_types
[j
].bitfield
.anysize
)
1651 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1657 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1666 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1669 i
.error
= operand_size_mismatch
;
1673 /* Check reverse. */
1674 gas_assert (i
.operands
== 2);
1677 for (j
= 0; j
< 2; j
++)
1679 if (t
->operand_types
[j
].bitfield
.acc
1680 && !match_reg_size (t
, j
? 0 : 1))
1683 if (i
.types
[j
].bitfield
.mem
1684 && !match_mem_size (t
, j
? 0 : 1))
1692 operand_type_match (i386_operand_type overlap
,
1693 i386_operand_type given
)
1695 i386_operand_type temp
= overlap
;
1697 temp
.bitfield
.jumpabsolute
= 0;
1698 temp
.bitfield
.unspecified
= 0;
1699 temp
.bitfield
.byte
= 0;
1700 temp
.bitfield
.word
= 0;
1701 temp
.bitfield
.dword
= 0;
1702 temp
.bitfield
.fword
= 0;
1703 temp
.bitfield
.qword
= 0;
1704 temp
.bitfield
.tbyte
= 0;
1705 temp
.bitfield
.xmmword
= 0;
1706 temp
.bitfield
.ymmword
= 0;
1707 if (operand_type_all_zero (&temp
))
1710 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1711 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1715 i
.error
= operand_type_mismatch
;
1719 /* If given types g0 and g1 are registers they must be of the same type
1720 unless the expected operand type register overlap is null.
1721 Note that Acc in a template matches every size of reg. */
1724 operand_type_register_match (i386_operand_type m0
,
1725 i386_operand_type g0
,
1726 i386_operand_type t0
,
1727 i386_operand_type m1
,
1728 i386_operand_type g1
,
1729 i386_operand_type t1
)
1731 if (!operand_type_check (g0
, reg
))
1734 if (!operand_type_check (g1
, reg
))
1737 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1738 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1739 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1740 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1743 if (m0
.bitfield
.acc
)
1745 t0
.bitfield
.reg8
= 1;
1746 t0
.bitfield
.reg16
= 1;
1747 t0
.bitfield
.reg32
= 1;
1748 t0
.bitfield
.reg64
= 1;
1751 if (m1
.bitfield
.acc
)
1753 t1
.bitfield
.reg8
= 1;
1754 t1
.bitfield
.reg16
= 1;
1755 t1
.bitfield
.reg32
= 1;
1756 t1
.bitfield
.reg64
= 1;
1759 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1760 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1761 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1762 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1765 i
.error
= register_type_mismatch
;
1770 static INLINE
unsigned int
1771 register_number (const reg_entry
*r
)
1773 unsigned int nr
= r
->reg_num
;
1775 if (r
->reg_flags
& RegRex
)
1781 static INLINE
unsigned int
1782 mode_from_disp_size (i386_operand_type t
)
1784 if (t
.bitfield
.disp8
)
1786 else if (t
.bitfield
.disp16
1787 || t
.bitfield
.disp32
1788 || t
.bitfield
.disp32s
)
1795 fits_in_signed_byte (offsetT num
)
1797 return (num
>= -128) && (num
<= 127);
1801 fits_in_unsigned_byte (offsetT num
)
1803 return (num
& 0xff) == num
;
1807 fits_in_unsigned_word (offsetT num
)
1809 return (num
& 0xffff) == num
;
1813 fits_in_signed_word (offsetT num
)
1815 return (-32768 <= num
) && (num
<= 32767);
1819 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1824 return (!(((offsetT
) -1 << 31) & num
)
1825 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1827 } /* fits_in_signed_long() */
1830 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1835 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1837 } /* fits_in_unsigned_long() */
1840 fits_in_imm4 (offsetT num
)
1842 return (num
& 0xf) == num
;
1845 static i386_operand_type
1846 smallest_imm_type (offsetT num
)
1848 i386_operand_type t
;
1850 operand_type_set (&t
, 0);
1851 t
.bitfield
.imm64
= 1;
1853 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1855 /* This code is disabled on the 486 because all the Imm1 forms
1856 in the opcode table are slower on the i486. They're the
1857 versions with the implicitly specified single-position
1858 displacement, which has another syntax if you really want to
1860 t
.bitfield
.imm1
= 1;
1861 t
.bitfield
.imm8
= 1;
1862 t
.bitfield
.imm8s
= 1;
1863 t
.bitfield
.imm16
= 1;
1864 t
.bitfield
.imm32
= 1;
1865 t
.bitfield
.imm32s
= 1;
1867 else if (fits_in_signed_byte (num
))
1869 t
.bitfield
.imm8
= 1;
1870 t
.bitfield
.imm8s
= 1;
1871 t
.bitfield
.imm16
= 1;
1872 t
.bitfield
.imm32
= 1;
1873 t
.bitfield
.imm32s
= 1;
1875 else if (fits_in_unsigned_byte (num
))
1877 t
.bitfield
.imm8
= 1;
1878 t
.bitfield
.imm16
= 1;
1879 t
.bitfield
.imm32
= 1;
1880 t
.bitfield
.imm32s
= 1;
1882 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1884 t
.bitfield
.imm16
= 1;
1885 t
.bitfield
.imm32
= 1;
1886 t
.bitfield
.imm32s
= 1;
1888 else if (fits_in_signed_long (num
))
1890 t
.bitfield
.imm32
= 1;
1891 t
.bitfield
.imm32s
= 1;
1893 else if (fits_in_unsigned_long (num
))
1894 t
.bitfield
.imm32
= 1;
1900 offset_in_range (offsetT val
, int size
)
1906 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1907 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1908 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1910 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1916 /* If BFD64, sign extend val for 32bit address mode. */
1917 if (flag_code
!= CODE_64BIT
1918 || i
.prefix
[ADDR_PREFIX
])
1919 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1920 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1923 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1925 char buf1
[40], buf2
[40];
1927 sprint_value (buf1
, val
);
1928 sprint_value (buf2
, val
& mask
);
1929 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1943 a. PREFIX_EXIST if attempting to add a prefix where one from the
1944 same class already exists.
1945 b. PREFIX_LOCK if lock prefix is added.
1946 c. PREFIX_REP if rep/repne prefix is added.
1947 d. PREFIX_OTHER if other prefix is added.
1950 static enum PREFIX_GROUP
1951 add_prefix (unsigned int prefix
)
1953 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1956 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1957 && flag_code
== CODE_64BIT
)
1959 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1960 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1961 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1972 case CS_PREFIX_OPCODE
:
1973 case DS_PREFIX_OPCODE
:
1974 case ES_PREFIX_OPCODE
:
1975 case FS_PREFIX_OPCODE
:
1976 case GS_PREFIX_OPCODE
:
1977 case SS_PREFIX_OPCODE
:
1981 case REPNE_PREFIX_OPCODE
:
1982 case REPE_PREFIX_OPCODE
:
1987 case LOCK_PREFIX_OPCODE
:
1996 case ADDR_PREFIX_OPCODE
:
2000 case DATA_PREFIX_OPCODE
:
2004 if (i
.prefix
[q
] != 0)
2012 i
.prefix
[q
] |= prefix
;
2015 as_bad (_("same type of prefix used twice"));
2021 update_code_flag (int value
, int check
)
2023 PRINTF_LIKE ((*as_error
));
2025 flag_code
= (enum flag_code
) value
;
2026 if (flag_code
== CODE_64BIT
)
2028 cpu_arch_flags
.bitfield
.cpu64
= 1;
2029 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2033 cpu_arch_flags
.bitfield
.cpu64
= 0;
2034 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2036 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2039 as_error
= as_fatal
;
2042 (*as_error
) (_("64bit mode not supported on `%s'."),
2043 cpu_arch_name
? cpu_arch_name
: default_arch
);
2045 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2048 as_error
= as_fatal
;
2051 (*as_error
) (_("32bit mode not supported on `%s'."),
2052 cpu_arch_name
? cpu_arch_name
: default_arch
);
2054 stackop_size
= '\0';
2058 set_code_flag (int value
)
2060 update_code_flag (value
, 0);
2064 set_16bit_gcc_code_flag (int new_code_flag
)
2066 flag_code
= (enum flag_code
) new_code_flag
;
2067 if (flag_code
!= CODE_16BIT
)
2069 cpu_arch_flags
.bitfield
.cpu64
= 0;
2070 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2071 stackop_size
= LONG_MNEM_SUFFIX
;
2075 set_intel_syntax (int syntax_flag
)
2077 /* Find out if register prefixing is specified. */
2078 int ask_naked_reg
= 0;
2081 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2083 char *string
= input_line_pointer
;
2084 int e
= get_symbol_end ();
2086 if (strcmp (string
, "prefix") == 0)
2088 else if (strcmp (string
, "noprefix") == 0)
2091 as_bad (_("bad argument to syntax directive."));
2092 *input_line_pointer
= e
;
2094 demand_empty_rest_of_line ();
2096 intel_syntax
= syntax_flag
;
2098 if (ask_naked_reg
== 0)
2099 allow_naked_reg
= (intel_syntax
2100 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2102 allow_naked_reg
= (ask_naked_reg
< 0);
2104 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2106 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2107 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2108 register_prefix
= allow_naked_reg
? "" : "%";
2112 set_intel_mnemonic (int mnemonic_flag
)
2114 intel_mnemonic
= mnemonic_flag
;
2118 set_allow_index_reg (int flag
)
2120 allow_index_reg
= flag
;
2124 set_check (int what
)
2126 enum check_kind
*kind
;
2131 kind
= &operand_check
;
2142 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2144 char *string
= input_line_pointer
;
2145 int e
= get_symbol_end ();
2147 if (strcmp (string
, "none") == 0)
2149 else if (strcmp (string
, "warning") == 0)
2150 *kind
= check_warning
;
2151 else if (strcmp (string
, "error") == 0)
2152 *kind
= check_error
;
2154 as_bad (_("bad argument to %s_check directive."), str
);
2155 *input_line_pointer
= e
;
2158 as_bad (_("missing argument for %s_check directive"), str
);
2160 demand_empty_rest_of_line ();
2164 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2165 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2167 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2168 static const char *arch
;
2170 /* Intel LIOM is only supported on ELF. */
2176 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2177 use default_arch. */
2178 arch
= cpu_arch_name
;
2180 arch
= default_arch
;
2183 /* If we are targeting Intel L1OM, we must enable it. */
2184 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2185 || new_flag
.bitfield
.cpul1om
)
2188 /* If we are targeting Intel K1OM, we must enable it. */
2189 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2190 || new_flag
.bitfield
.cpuk1om
)
2193 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2198 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2202 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2204 char *string
= input_line_pointer
;
2205 int e
= get_symbol_end ();
2207 i386_cpu_flags flags
;
2209 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2211 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2213 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2217 cpu_arch_name
= cpu_arch
[j
].name
;
2218 cpu_sub_arch_name
= NULL
;
2219 cpu_arch_flags
= cpu_arch
[j
].flags
;
2220 if (flag_code
== CODE_64BIT
)
2222 cpu_arch_flags
.bitfield
.cpu64
= 1;
2223 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2227 cpu_arch_flags
.bitfield
.cpu64
= 0;
2228 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2230 cpu_arch_isa
= cpu_arch
[j
].type
;
2231 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2232 if (!cpu_arch_tune_set
)
2234 cpu_arch_tune
= cpu_arch_isa
;
2235 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2240 if (!cpu_arch
[j
].negated
)
2241 flags
= cpu_flags_or (cpu_arch_flags
,
2244 flags
= cpu_flags_and_not (cpu_arch_flags
,
2246 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2248 if (cpu_sub_arch_name
)
2250 char *name
= cpu_sub_arch_name
;
2251 cpu_sub_arch_name
= concat (name
,
2253 (const char *) NULL
);
2257 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2258 cpu_arch_flags
= flags
;
2259 cpu_arch_isa_flags
= flags
;
2261 *input_line_pointer
= e
;
2262 demand_empty_rest_of_line ();
2266 if (j
>= ARRAY_SIZE (cpu_arch
))
2267 as_bad (_("no such architecture: `%s'"), string
);
2269 *input_line_pointer
= e
;
2272 as_bad (_("missing cpu architecture"));
2274 no_cond_jump_promotion
= 0;
2275 if (*input_line_pointer
== ','
2276 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2278 char *string
= ++input_line_pointer
;
2279 int e
= get_symbol_end ();
2281 if (strcmp (string
, "nojumps") == 0)
2282 no_cond_jump_promotion
= 1;
2283 else if (strcmp (string
, "jumps") == 0)
2286 as_bad (_("no such architecture modifier: `%s'"), string
);
2288 *input_line_pointer
= e
;
2291 demand_empty_rest_of_line ();
2294 enum bfd_architecture
2297 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2299 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2300 || flag_code
!= CODE_64BIT
)
2301 as_fatal (_("Intel L1OM is 64bit ELF only"));
2302 return bfd_arch_l1om
;
2304 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2306 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2307 || flag_code
!= CODE_64BIT
)
2308 as_fatal (_("Intel K1OM is 64bit ELF only"));
2309 return bfd_arch_k1om
;
2312 return bfd_arch_i386
;
2318 if (!strncmp (default_arch
, "x86_64", 6))
2320 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2322 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2323 || default_arch
[6] != '\0')
2324 as_fatal (_("Intel L1OM is 64bit ELF only"));
2325 return bfd_mach_l1om
;
2327 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2329 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2330 || default_arch
[6] != '\0')
2331 as_fatal (_("Intel K1OM is 64bit ELF only"));
2332 return bfd_mach_k1om
;
2334 else if (default_arch
[6] == '\0')
2335 return bfd_mach_x86_64
;
2337 return bfd_mach_x64_32
;
2339 else if (!strcmp (default_arch
, "i386"))
2340 return bfd_mach_i386_i386
;
2342 as_fatal (_("unknown architecture"));
2348 const char *hash_err
;
2350 /* Initialize op_hash hash table. */
2351 op_hash
= hash_new ();
2354 const insn_template
*optab
;
2355 templates
*core_optab
;
2357 /* Setup for loop. */
2359 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2360 core_optab
->start
= optab
;
2365 if (optab
->name
== NULL
2366 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2368 /* different name --> ship out current template list;
2369 add to hash table; & begin anew. */
2370 core_optab
->end
= optab
;
2371 hash_err
= hash_insert (op_hash
,
2373 (void *) core_optab
);
2376 as_fatal (_("internal Error: Can't hash %s: %s"),
2380 if (optab
->name
== NULL
)
2382 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2383 core_optab
->start
= optab
;
2388 /* Initialize reg_hash hash table. */
2389 reg_hash
= hash_new ();
2391 const reg_entry
*regtab
;
2392 unsigned int regtab_size
= i386_regtab_size
;
2394 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2396 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2398 as_fatal (_("internal Error: Can't hash %s: %s"),
2404 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2409 for (c
= 0; c
< 256; c
++)
2414 mnemonic_chars
[c
] = c
;
2415 register_chars
[c
] = c
;
2416 operand_chars
[c
] = c
;
2418 else if (ISLOWER (c
))
2420 mnemonic_chars
[c
] = c
;
2421 register_chars
[c
] = c
;
2422 operand_chars
[c
] = c
;
2424 else if (ISUPPER (c
))
2426 mnemonic_chars
[c
] = TOLOWER (c
);
2427 register_chars
[c
] = mnemonic_chars
[c
];
2428 operand_chars
[c
] = c
;
2431 if (ISALPHA (c
) || ISDIGIT (c
))
2432 identifier_chars
[c
] = c
;
2435 identifier_chars
[c
] = c
;
2436 operand_chars
[c
] = c
;
2441 identifier_chars
['@'] = '@';
2444 identifier_chars
['?'] = '?';
2445 operand_chars
['?'] = '?';
2447 digit_chars
['-'] = '-';
2448 mnemonic_chars
['_'] = '_';
2449 mnemonic_chars
['-'] = '-';
2450 mnemonic_chars
['.'] = '.';
2451 identifier_chars
['_'] = '_';
2452 identifier_chars
['.'] = '.';
2454 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2455 operand_chars
[(unsigned char) *p
] = *p
;
2458 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2461 record_alignment (text_section
, 2);
2462 record_alignment (data_section
, 2);
2463 record_alignment (bss_section
, 2);
2467 if (flag_code
== CODE_64BIT
)
2469 #if defined (OBJ_COFF) && defined (TE_PE)
2470 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2473 x86_dwarf2_return_column
= 16;
2475 x86_cie_data_alignment
= -8;
2479 x86_dwarf2_return_column
= 8;
2480 x86_cie_data_alignment
= -4;
2485 i386_print_statistics (FILE *file
)
2487 hash_print_statistics (file
, "i386 opcode", op_hash
);
2488 hash_print_statistics (file
, "i386 register", reg_hash
);
2493 /* Debugging routines for md_assemble. */
2494 static void pte (insn_template
*);
2495 static void pt (i386_operand_type
);
2496 static void pe (expressionS
*);
2497 static void ps (symbolS
*);
2500 pi (char *line
, i386_insn
*x
)
2504 fprintf (stdout
, "%s: template ", line
);
2506 fprintf (stdout
, " address: base %s index %s scale %x\n",
2507 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2508 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2509 x
->log2_scale_factor
);
2510 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2511 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2512 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2513 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2514 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2515 (x
->rex
& REX_W
) != 0,
2516 (x
->rex
& REX_R
) != 0,
2517 (x
->rex
& REX_X
) != 0,
2518 (x
->rex
& REX_B
) != 0);
2519 for (j
= 0; j
< x
->operands
; j
++)
2521 fprintf (stdout
, " #%d: ", j
+ 1);
2523 fprintf (stdout
, "\n");
2524 if (x
->types
[j
].bitfield
.reg8
2525 || x
->types
[j
].bitfield
.reg16
2526 || x
->types
[j
].bitfield
.reg32
2527 || x
->types
[j
].bitfield
.reg64
2528 || x
->types
[j
].bitfield
.regmmx
2529 || x
->types
[j
].bitfield
.regxmm
2530 || x
->types
[j
].bitfield
.regymm
2531 || x
->types
[j
].bitfield
.sreg2
2532 || x
->types
[j
].bitfield
.sreg3
2533 || x
->types
[j
].bitfield
.control
2534 || x
->types
[j
].bitfield
.debug
2535 || x
->types
[j
].bitfield
.test
)
2536 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2537 if (operand_type_check (x
->types
[j
], imm
))
2539 if (operand_type_check (x
->types
[j
], disp
))
2540 pe (x
->op
[j
].disps
);
2545 pte (insn_template
*t
)
2548 fprintf (stdout
, " %d operands ", t
->operands
);
2549 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2550 if (t
->extension_opcode
!= None
)
2551 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2552 if (t
->opcode_modifier
.d
)
2553 fprintf (stdout
, "D");
2554 if (t
->opcode_modifier
.w
)
2555 fprintf (stdout
, "W");
2556 fprintf (stdout
, "\n");
2557 for (j
= 0; j
< t
->operands
; j
++)
2559 fprintf (stdout
, " #%d type ", j
+ 1);
2560 pt (t
->operand_types
[j
]);
2561 fprintf (stdout
, "\n");
2568 fprintf (stdout
, " operation %d\n", e
->X_op
);
2569 fprintf (stdout
, " add_number %ld (%lx)\n",
2570 (long) e
->X_add_number
, (long) e
->X_add_number
);
2571 if (e
->X_add_symbol
)
2573 fprintf (stdout
, " add_symbol ");
2574 ps (e
->X_add_symbol
);
2575 fprintf (stdout
, "\n");
2579 fprintf (stdout
, " op_symbol ");
2580 ps (e
->X_op_symbol
);
2581 fprintf (stdout
, "\n");
2588 fprintf (stdout
, "%s type %s%s",
2590 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2591 segment_name (S_GET_SEGMENT (s
)));
2594 static struct type_name
2596 i386_operand_type mask
;
2599 const type_names
[] =
2601 { OPERAND_TYPE_REG8
, "r8" },
2602 { OPERAND_TYPE_REG16
, "r16" },
2603 { OPERAND_TYPE_REG32
, "r32" },
2604 { OPERAND_TYPE_REG64
, "r64" },
2605 { OPERAND_TYPE_IMM8
, "i8" },
2606 { OPERAND_TYPE_IMM8
, "i8s" },
2607 { OPERAND_TYPE_IMM16
, "i16" },
2608 { OPERAND_TYPE_IMM32
, "i32" },
2609 { OPERAND_TYPE_IMM32S
, "i32s" },
2610 { OPERAND_TYPE_IMM64
, "i64" },
2611 { OPERAND_TYPE_IMM1
, "i1" },
2612 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2613 { OPERAND_TYPE_DISP8
, "d8" },
2614 { OPERAND_TYPE_DISP16
, "d16" },
2615 { OPERAND_TYPE_DISP32
, "d32" },
2616 { OPERAND_TYPE_DISP32S
, "d32s" },
2617 { OPERAND_TYPE_DISP64
, "d64" },
2618 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2619 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2620 { OPERAND_TYPE_CONTROL
, "control reg" },
2621 { OPERAND_TYPE_TEST
, "test reg" },
2622 { OPERAND_TYPE_DEBUG
, "debug reg" },
2623 { OPERAND_TYPE_FLOATREG
, "FReg" },
2624 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2625 { OPERAND_TYPE_SREG2
, "SReg2" },
2626 { OPERAND_TYPE_SREG3
, "SReg3" },
2627 { OPERAND_TYPE_ACC
, "Acc" },
2628 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2629 { OPERAND_TYPE_REGMMX
, "rMMX" },
2630 { OPERAND_TYPE_REGXMM
, "rXMM" },
2631 { OPERAND_TYPE_REGYMM
, "rYMM" },
2632 { OPERAND_TYPE_ESSEG
, "es" },
2636 pt (i386_operand_type t
)
2639 i386_operand_type a
;
2641 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2643 a
= operand_type_and (t
, type_names
[j
].mask
);
2644 if (!operand_type_all_zero (&a
))
2645 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2650 #endif /* DEBUG386 */
2652 static bfd_reloc_code_real_type
2653 reloc (unsigned int size
,
2656 bfd_reloc_code_real_type other
)
2658 if (other
!= NO_RELOC
)
2660 reloc_howto_type
*rel
;
2665 case BFD_RELOC_X86_64_GOT32
:
2666 return BFD_RELOC_X86_64_GOT64
;
2668 case BFD_RELOC_X86_64_PLTOFF64
:
2669 return BFD_RELOC_X86_64_PLTOFF64
;
2671 case BFD_RELOC_X86_64_GOTPC32
:
2672 other
= BFD_RELOC_X86_64_GOTPC64
;
2674 case BFD_RELOC_X86_64_GOTPCREL
:
2675 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2677 case BFD_RELOC_X86_64_TPOFF32
:
2678 other
= BFD_RELOC_X86_64_TPOFF64
;
2680 case BFD_RELOC_X86_64_DTPOFF32
:
2681 other
= BFD_RELOC_X86_64_DTPOFF64
;
2687 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2688 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2691 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2693 as_bad (_("unknown relocation (%u)"), other
);
2694 else if (size
!= bfd_get_reloc_size (rel
))
2695 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2696 bfd_get_reloc_size (rel
),
2698 else if (pcrel
&& !rel
->pc_relative
)
2699 as_bad (_("non-pc-relative relocation for pc-relative field"));
2700 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2702 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2704 as_bad (_("relocated field and relocation type differ in signedness"));
2713 as_bad (_("there are no unsigned pc-relative relocations"));
2716 case 1: return BFD_RELOC_8_PCREL
;
2717 case 2: return BFD_RELOC_16_PCREL
;
2718 case 4: return BFD_RELOC_32_PCREL
;
2719 case 8: return BFD_RELOC_64_PCREL
;
2721 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2728 case 4: return BFD_RELOC_X86_64_32S
;
2733 case 1: return BFD_RELOC_8
;
2734 case 2: return BFD_RELOC_16
;
2735 case 4: return BFD_RELOC_32
;
2736 case 8: return BFD_RELOC_64
;
2738 as_bad (_("cannot do %s %u byte relocation"),
2739 sign
> 0 ? "signed" : "unsigned", size
);
2745 /* Here we decide which fixups can be adjusted to make them relative to
2746 the beginning of the section instead of the symbol. Basically we need
2747 to make sure that the dynamic relocations are done correctly, so in
2748 some cases we force the original symbol to be used. */
2751 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2753 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2757 /* Don't adjust pc-relative references to merge sections in 64-bit
2759 if (use_rela_relocations
2760 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2764 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2765 and changed later by validate_fix. */
2766 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2767 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2770 /* adjust_reloc_syms doesn't know about the GOT. */
2771 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2772 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2773 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2774 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2775 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2776 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2777 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2778 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2779 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2780 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2781 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2782 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2783 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2784 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2785 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2786 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2787 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2788 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2789 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2790 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2791 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2792 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2793 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2794 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2795 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2796 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2797 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2798 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2805 intel_float_operand (const char *mnemonic
)
2807 /* Note that the value returned is meaningful only for opcodes with (memory)
2808 operands, hence the code here is free to improperly handle opcodes that
2809 have no operands (for better performance and smaller code). */
2811 if (mnemonic
[0] != 'f')
2812 return 0; /* non-math */
2814 switch (mnemonic
[1])
2816 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2817 the fs segment override prefix not currently handled because no
2818 call path can make opcodes without operands get here */
2820 return 2 /* integer op */;
2822 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2823 return 3; /* fldcw/fldenv */
2826 if (mnemonic
[2] != 'o' /* fnop */)
2827 return 3; /* non-waiting control op */
2830 if (mnemonic
[2] == 's')
2831 return 3; /* frstor/frstpm */
2834 if (mnemonic
[2] == 'a')
2835 return 3; /* fsave */
2836 if (mnemonic
[2] == 't')
2838 switch (mnemonic
[3])
2840 case 'c': /* fstcw */
2841 case 'd': /* fstdw */
2842 case 'e': /* fstenv */
2843 case 's': /* fsts[gw] */
2849 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2850 return 0; /* fxsave/fxrstor are not really math ops */
2857 /* Build the VEX prefix. */
2860 build_vex_prefix (const insn_template
*t
)
2862 unsigned int register_specifier
;
2863 unsigned int implied_prefix
;
2864 unsigned int vector_length
;
2866 /* Check register specifier. */
2867 if (i
.vex
.register_specifier
)
2868 register_specifier
= ~register_number (i
.vex
.register_specifier
) & 0xf;
2870 register_specifier
= 0xf;
2872 /* Use 2-byte VEX prefix by swappping destination and source
2875 && i
.operands
== i
.reg_operands
2876 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2877 && i
.tm
.opcode_modifier
.s
2880 unsigned int xchg
= i
.operands
- 1;
2881 union i386_op temp_op
;
2882 i386_operand_type temp_type
;
2884 temp_type
= i
.types
[xchg
];
2885 i
.types
[xchg
] = i
.types
[0];
2886 i
.types
[0] = temp_type
;
2887 temp_op
= i
.op
[xchg
];
2888 i
.op
[xchg
] = i
.op
[0];
2891 gas_assert (i
.rm
.mode
== 3);
2895 i
.rm
.regmem
= i
.rm
.reg
;
2898 /* Use the next insn. */
2902 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2903 vector_length
= avxscalar
;
2905 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2907 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2912 case DATA_PREFIX_OPCODE
:
2915 case REPE_PREFIX_OPCODE
:
2918 case REPNE_PREFIX_OPCODE
:
2925 /* Use 2-byte VEX prefix if possible. */
2926 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2927 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
2928 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2930 /* 2-byte VEX prefix. */
2934 i
.vex
.bytes
[0] = 0xc5;
2936 /* Check the REX.R bit. */
2937 r
= (i
.rex
& REX_R
) ? 0 : 1;
2938 i
.vex
.bytes
[1] = (r
<< 7
2939 | register_specifier
<< 3
2940 | vector_length
<< 2
2945 /* 3-byte VEX prefix. */
2950 switch (i
.tm
.opcode_modifier
.vexopcode
)
2954 i
.vex
.bytes
[0] = 0xc4;
2958 i
.vex
.bytes
[0] = 0xc4;
2962 i
.vex
.bytes
[0] = 0xc4;
2966 i
.vex
.bytes
[0] = 0x8f;
2970 i
.vex
.bytes
[0] = 0x8f;
2974 i
.vex
.bytes
[0] = 0x8f;
2980 /* The high 3 bits of the second VEX byte are 1's compliment
2981 of RXB bits from REX. */
2982 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2984 /* Check the REX.W bit. */
2985 w
= (i
.rex
& REX_W
) ? 1 : 0;
2986 if (i
.tm
.opcode_modifier
.vexw
)
2991 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2995 i
.vex
.bytes
[2] = (w
<< 7
2996 | register_specifier
<< 3
2997 | vector_length
<< 2
3003 process_immext (void)
3007 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3010 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3011 with an opcode suffix which is coded in the same place as an
3012 8-bit immediate field would be.
3013 Here we check those operands and remove them afterwards. */
3016 for (x
= 0; x
< i
.operands
; x
++)
3017 if (register_number (i
.op
[x
].regs
) != x
)
3018 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3019 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3025 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3026 which is coded in the same place as an 8-bit immediate field
3027 would be. Here we fake an 8-bit immediate operand from the
3028 opcode suffix stored in tm.extension_opcode.
3030 AVX instructions also use this encoding, for some of
3031 3 argument instructions. */
3033 gas_assert (i
.imm_operands
== 0
3035 || (i
.tm
.opcode_modifier
.vex
3036 && i
.operands
<= 4)));
3038 exp
= &im_expressions
[i
.imm_operands
++];
3039 i
.op
[i
.operands
].imms
= exp
;
3040 i
.types
[i
.operands
] = imm8
;
3042 exp
->X_op
= O_constant
;
3043 exp
->X_add_number
= i
.tm
.extension_opcode
;
3044 i
.tm
.extension_opcode
= None
;
3051 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3056 if (i
.prefix
[HLE_PREFIX
] == XACQUIRE_PREFIX_OPCODE
)
3057 as_bad (_("invalid instruction `%s' after `xacquire'"),
3060 as_bad (_("invalid instruction `%s' after `xrelease'"),
3064 if (i
.prefix
[LOCK_PREFIX
])
3066 if (i
.prefix
[HLE_PREFIX
] == XACQUIRE_PREFIX_OPCODE
)
3067 as_bad (_("missing `lock' with `xacquire'"));
3069 as_bad (_("missing `lock' with `xrelease'"));
3073 case HLEPrefixRelease
:
3074 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3076 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3080 if (i
.mem_operands
== 0
3081 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3083 as_bad (_("memory destination needed for instruction `%s'"
3084 " after `xrelease'"), i
.tm
.name
);
3091 /* This is the guts of the machine-dependent assembler. LINE points to a
3092 machine dependent instruction. This function is supposed to emit
3093 the frags/bytes it assembles to. */
3096 md_assemble (char *line
)
3099 char mnemonic
[MAX_MNEM_SIZE
];
3100 const insn_template
*t
;
3102 /* Initialize globals. */
3103 memset (&i
, '\0', sizeof (i
));
3104 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3105 i
.reloc
[j
] = NO_RELOC
;
3106 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3107 memset (im_expressions
, '\0', sizeof (im_expressions
));
3108 save_stack_p
= save_stack
;
3110 /* First parse an instruction mnemonic & call i386_operand for the operands.
3111 We assume that the scrubber has arranged it so that line[0] is the valid
3112 start of a (possibly prefixed) mnemonic. */
3114 line
= parse_insn (line
, mnemonic
);
3118 line
= parse_operands (line
, mnemonic
);
3123 /* Now we've parsed the mnemonic into a set of templates, and have the
3124 operands at hand. */
3126 /* All intel opcodes have reversed operands except for "bound" and
3127 "enter". We also don't reverse intersegment "jmp" and "call"
3128 instructions with 2 immediate operands so that the immediate segment
3129 precedes the offset, as it does when in AT&T mode. */
3132 && (strcmp (mnemonic
, "bound") != 0)
3133 && (strcmp (mnemonic
, "invlpga") != 0)
3134 && !(operand_type_check (i
.types
[0], imm
)
3135 && operand_type_check (i
.types
[1], imm
)))
3138 /* The order of the immediates should be reversed
3139 for 2 immediates extrq and insertq instructions */
3140 if (i
.imm_operands
== 2
3141 && (strcmp (mnemonic
, "extrq") == 0
3142 || strcmp (mnemonic
, "insertq") == 0))
3143 swap_2_operands (0, 1);
3148 /* Don't optimize displacement for movabs since it only takes 64bit
3151 && i
.disp_encoding
!= disp_encoding_32bit
3152 && (flag_code
!= CODE_64BIT
3153 || strcmp (mnemonic
, "movabs") != 0))
3156 /* Next, we find a template that matches the given insn,
3157 making sure the overlap of the given operands types is consistent
3158 with the template operand types. */
3160 if (!(t
= match_template ()))
3163 if (sse_check
!= check_none
3164 && !i
.tm
.opcode_modifier
.noavx
3165 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3166 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3167 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3168 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3169 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3170 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3172 (sse_check
== check_warning
3174 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3177 /* Zap movzx and movsx suffix. The suffix has been set from
3178 "word ptr" or "byte ptr" on the source operand in Intel syntax
3179 or extracted from mnemonic in AT&T syntax. But we'll use
3180 the destination register to choose the suffix for encoding. */
3181 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3183 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3184 there is no suffix, the default will be byte extension. */
3185 if (i
.reg_operands
!= 2
3188 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3193 if (i
.tm
.opcode_modifier
.fwait
)
3194 if (!add_prefix (FWAIT_OPCODE
))
3197 /* Check for lock without a lockable instruction. Destination operand
3198 must be memory unless it is xchg (0x86). */
3199 if (i
.prefix
[LOCK_PREFIX
]
3200 && (!i
.tm
.opcode_modifier
.islockable
3201 || i
.mem_operands
== 0
3202 || (i
.tm
.base_opcode
!= 0x86
3203 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3205 as_bad (_("expecting lockable instruction after `lock'"));
3209 /* Check if HLE prefix is OK. */
3210 if (i
.have_hle
&& !check_hle ())
3213 /* Check string instruction segment overrides. */
3214 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3216 if (!check_string ())
3218 i
.disp_operands
= 0;
3221 if (!process_suffix ())
3224 /* Update operand types. */
3225 for (j
= 0; j
< i
.operands
; j
++)
3226 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3228 /* Make still unresolved immediate matches conform to size of immediate
3229 given in i.suffix. */
3230 if (!finalize_imm ())
3233 if (i
.types
[0].bitfield
.imm1
)
3234 i
.imm_operands
= 0; /* kludge for shift insns. */
3236 /* We only need to check those implicit registers for instructions
3237 with 3 operands or less. */
3238 if (i
.operands
<= 3)
3239 for (j
= 0; j
< i
.operands
; j
++)
3240 if (i
.types
[j
].bitfield
.inoutportreg
3241 || i
.types
[j
].bitfield
.shiftcount
3242 || i
.types
[j
].bitfield
.acc
3243 || i
.types
[j
].bitfield
.floatacc
)
3246 /* ImmExt should be processed after SSE2AVX. */
3247 if (!i
.tm
.opcode_modifier
.sse2avx
3248 && i
.tm
.opcode_modifier
.immext
)
3251 /* For insns with operands there are more diddles to do to the opcode. */
3254 if (!process_operands ())
3257 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3259 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3260 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3263 if (i
.tm
.opcode_modifier
.vex
)
3264 build_vex_prefix (t
);
3266 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3267 instructions may define INT_OPCODE as well, so avoid this corner
3268 case for those instructions that use MODRM. */
3269 if (i
.tm
.base_opcode
== INT_OPCODE
3270 && !i
.tm
.opcode_modifier
.modrm
3271 && i
.op
[0].imms
->X_add_number
== 3)
3273 i
.tm
.base_opcode
= INT3_OPCODE
;
3277 if ((i
.tm
.opcode_modifier
.jump
3278 || i
.tm
.opcode_modifier
.jumpbyte
3279 || i
.tm
.opcode_modifier
.jumpdword
)
3280 && i
.op
[0].disps
->X_op
== O_constant
)
3282 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3283 the absolute address given by the constant. Since ix86 jumps and
3284 calls are pc relative, we need to generate a reloc. */
3285 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3286 i
.op
[0].disps
->X_op
= O_symbol
;
3289 if (i
.tm
.opcode_modifier
.rex64
)
3292 /* For 8 bit registers we need an empty rex prefix. Also if the
3293 instruction already has a prefix, we need to convert old
3294 registers to new ones. */
3296 if ((i
.types
[0].bitfield
.reg8
3297 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3298 || (i
.types
[1].bitfield
.reg8
3299 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3300 || ((i
.types
[0].bitfield
.reg8
3301 || i
.types
[1].bitfield
.reg8
)
3306 i
.rex
|= REX_OPCODE
;
3307 for (x
= 0; x
< 2; x
++)
3309 /* Look for 8 bit operand that uses old registers. */
3310 if (i
.types
[x
].bitfield
.reg8
3311 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3313 /* In case it is "hi" register, give up. */
3314 if (i
.op
[x
].regs
->reg_num
> 3)
3315 as_bad (_("can't encode register '%s%s' in an "
3316 "instruction requiring REX prefix."),
3317 register_prefix
, i
.op
[x
].regs
->reg_name
);
3319 /* Otherwise it is equivalent to the extended register.
3320 Since the encoding doesn't change this is merely
3321 cosmetic cleanup for debug output. */
3323 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3329 add_prefix (REX_OPCODE
| i
.rex
);
3331 /* We are ready to output the insn. */
3336 parse_insn (char *line
, char *mnemonic
)
3339 char *token_start
= l
;
3342 const insn_template
*t
;
3345 /* Non-zero if we found a prefix only acceptable with string insns. */
3346 const char *expecting_string_instruction
= NULL
;
3351 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3356 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3358 as_bad (_("no such instruction: `%s'"), token_start
);
3363 if (!is_space_char (*l
)
3364 && *l
!= END_OF_INSN
3366 || (*l
!= PREFIX_SEPARATOR
3369 as_bad (_("invalid character %s in mnemonic"),
3370 output_invalid (*l
));
3373 if (token_start
== l
)
3375 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3376 as_bad (_("expecting prefix; got nothing"));
3378 as_bad (_("expecting mnemonic; got nothing"));
3382 /* Look up instruction (or prefix) via hash table. */
3383 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3385 if (*l
!= END_OF_INSN
3386 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3387 && current_templates
3388 && current_templates
->start
->opcode_modifier
.isprefix
)
3390 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3392 as_bad ((flag_code
!= CODE_64BIT
3393 ? _("`%s' is only supported in 64-bit mode")
3394 : _("`%s' is not supported in 64-bit mode")),
3395 current_templates
->start
->name
);
3398 /* If we are in 16-bit mode, do not allow addr16 or data16.
3399 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3400 if ((current_templates
->start
->opcode_modifier
.size16
3401 || current_templates
->start
->opcode_modifier
.size32
)
3402 && flag_code
!= CODE_64BIT
3403 && (current_templates
->start
->opcode_modifier
.size32
3404 ^ (flag_code
== CODE_16BIT
)))
3406 as_bad (_("redundant %s prefix"),
3407 current_templates
->start
->name
);
3410 /* Add prefix, checking for repeated prefixes. */
3411 switch (add_prefix (current_templates
->start
->base_opcode
))
3416 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3419 expecting_string_instruction
= current_templates
->start
->name
;
3424 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3431 if (!current_templates
)
3433 /* Check if we should swap operand or force 32bit displacement in
3435 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3437 else if (mnem_p
- 3 == dot_p
3440 i
.disp_encoding
= disp_encoding_8bit
;
3441 else if (mnem_p
- 4 == dot_p
3445 i
.disp_encoding
= disp_encoding_32bit
;
3450 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3453 if (!current_templates
)
3456 /* See if we can get a match by trimming off a suffix. */
3459 case WORD_MNEM_SUFFIX
:
3460 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3461 i
.suffix
= SHORT_MNEM_SUFFIX
;
3463 case BYTE_MNEM_SUFFIX
:
3464 case QWORD_MNEM_SUFFIX
:
3465 i
.suffix
= mnem_p
[-1];
3467 current_templates
= (const templates
*) hash_find (op_hash
,
3470 case SHORT_MNEM_SUFFIX
:
3471 case LONG_MNEM_SUFFIX
:
3474 i
.suffix
= mnem_p
[-1];
3476 current_templates
= (const templates
*) hash_find (op_hash
,
3485 if (intel_float_operand (mnemonic
) == 1)
3486 i
.suffix
= SHORT_MNEM_SUFFIX
;
3488 i
.suffix
= LONG_MNEM_SUFFIX
;
3490 current_templates
= (const templates
*) hash_find (op_hash
,
3495 if (!current_templates
)
3497 as_bad (_("no such instruction: `%s'"), token_start
);
3502 if (current_templates
->start
->opcode_modifier
.jump
3503 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3505 /* Check for a branch hint. We allow ",pt" and ",pn" for
3506 predict taken and predict not taken respectively.
3507 I'm not sure that branch hints actually do anything on loop
3508 and jcxz insns (JumpByte) for current Pentium4 chips. They
3509 may work in the future and it doesn't hurt to accept them
3511 if (l
[0] == ',' && l
[1] == 'p')
3515 if (!add_prefix (DS_PREFIX_OPCODE
))
3519 else if (l
[2] == 'n')
3521 if (!add_prefix (CS_PREFIX_OPCODE
))
3527 /* Any other comma loses. */
3530 as_bad (_("invalid character %s in mnemonic"),
3531 output_invalid (*l
));
3535 /* Check if instruction is supported on specified architecture. */
3537 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3539 supported
|= cpu_flags_match (t
);
3540 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3544 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3546 as_bad (flag_code
== CODE_64BIT
3547 ? _("`%s' is not supported in 64-bit mode")
3548 : _("`%s' is only supported in 64-bit mode"),
3549 current_templates
->start
->name
);
3552 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3554 as_bad (_("`%s' is not supported on `%s%s'"),
3555 current_templates
->start
->name
,
3556 cpu_arch_name
? cpu_arch_name
: default_arch
,
3557 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3562 if (!cpu_arch_flags
.bitfield
.cpui386
3563 && (flag_code
!= CODE_16BIT
))
3565 as_warn (_("use .code16 to ensure correct addressing mode"));
3568 /* Check for rep/repne without a string (or other allowed) instruction. */
3569 if (expecting_string_instruction
)
3571 static templates override
;
3573 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3574 if (t
->opcode_modifier
.repprefixok
)
3576 if (t
>= current_templates
->end
)
3578 as_bad (_("expecting string instruction after `%s'"),
3579 expecting_string_instruction
);
3582 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3583 if (!t
->opcode_modifier
.repprefixok
)
3586 current_templates
= &override
;
3593 parse_operands (char *l
, const char *mnemonic
)
3597 /* 1 if operand is pending after ','. */
3598 unsigned int expecting_operand
= 0;
3600 /* Non-zero if operand parens not balanced. */
3601 unsigned int paren_not_balanced
;
3603 while (*l
!= END_OF_INSN
)
3605 /* Skip optional white space before operand. */
3606 if (is_space_char (*l
))
3608 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3610 as_bad (_("invalid character %s before operand %d"),
3611 output_invalid (*l
),
3615 token_start
= l
; /* after white space */
3616 paren_not_balanced
= 0;
3617 while (paren_not_balanced
|| *l
!= ',')
3619 if (*l
== END_OF_INSN
)
3621 if (paren_not_balanced
)
3624 as_bad (_("unbalanced parenthesis in operand %d."),
3627 as_bad (_("unbalanced brackets in operand %d."),
3632 break; /* we are done */
3634 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3636 as_bad (_("invalid character %s in operand %d"),
3637 output_invalid (*l
),
3644 ++paren_not_balanced
;
3646 --paren_not_balanced
;
3651 ++paren_not_balanced
;
3653 --paren_not_balanced
;
3657 if (l
!= token_start
)
3658 { /* Yes, we've read in another operand. */
3659 unsigned int operand_ok
;
3660 this_operand
= i
.operands
++;
3661 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3662 if (i
.operands
> MAX_OPERANDS
)
3664 as_bad (_("spurious operands; (%d operands/instruction max)"),
3668 /* Now parse operand adding info to 'i' as we go along. */
3669 END_STRING_AND_SAVE (l
);
3673 i386_intel_operand (token_start
,
3674 intel_float_operand (mnemonic
));
3676 operand_ok
= i386_att_operand (token_start
);
3678 RESTORE_END_STRING (l
);
3684 if (expecting_operand
)
3686 expecting_operand_after_comma
:
3687 as_bad (_("expecting operand after ','; got nothing"));
3692 as_bad (_("expecting operand before ','; got nothing"));
3697 /* Now *l must be either ',' or END_OF_INSN. */
3700 if (*++l
== END_OF_INSN
)
3702 /* Just skip it, if it's \n complain. */
3703 goto expecting_operand_after_comma
;
3705 expecting_operand
= 1;
3712 swap_2_operands (int xchg1
, int xchg2
)
3714 union i386_op temp_op
;
3715 i386_operand_type temp_type
;
3716 enum bfd_reloc_code_real temp_reloc
;
3718 temp_type
= i
.types
[xchg2
];
3719 i
.types
[xchg2
] = i
.types
[xchg1
];
3720 i
.types
[xchg1
] = temp_type
;
3721 temp_op
= i
.op
[xchg2
];
3722 i
.op
[xchg2
] = i
.op
[xchg1
];
3723 i
.op
[xchg1
] = temp_op
;
3724 temp_reloc
= i
.reloc
[xchg2
];
3725 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3726 i
.reloc
[xchg1
] = temp_reloc
;
3730 swap_operands (void)
3736 swap_2_operands (1, i
.operands
- 2);
3739 swap_2_operands (0, i
.operands
- 1);
3745 if (i
.mem_operands
== 2)
3747 const seg_entry
*temp_seg
;
3748 temp_seg
= i
.seg
[0];
3749 i
.seg
[0] = i
.seg
[1];
3750 i
.seg
[1] = temp_seg
;
3754 /* Try to ensure constant immediates are represented in the smallest
3759 char guess_suffix
= 0;
3763 guess_suffix
= i
.suffix
;
3764 else if (i
.reg_operands
)
3766 /* Figure out a suffix from the last register operand specified.
3767 We can't do this properly yet, ie. excluding InOutPortReg,
3768 but the following works for instructions with immediates.
3769 In any case, we can't set i.suffix yet. */
3770 for (op
= i
.operands
; --op
>= 0;)
3771 if (i
.types
[op
].bitfield
.reg8
)
3773 guess_suffix
= BYTE_MNEM_SUFFIX
;
3776 else if (i
.types
[op
].bitfield
.reg16
)
3778 guess_suffix
= WORD_MNEM_SUFFIX
;
3781 else if (i
.types
[op
].bitfield
.reg32
)
3783 guess_suffix
= LONG_MNEM_SUFFIX
;
3786 else if (i
.types
[op
].bitfield
.reg64
)
3788 guess_suffix
= QWORD_MNEM_SUFFIX
;
3792 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3793 guess_suffix
= WORD_MNEM_SUFFIX
;
3795 for (op
= i
.operands
; --op
>= 0;)
3796 if (operand_type_check (i
.types
[op
], imm
))
3798 switch (i
.op
[op
].imms
->X_op
)
3801 /* If a suffix is given, this operand may be shortened. */
3802 switch (guess_suffix
)
3804 case LONG_MNEM_SUFFIX
:
3805 i
.types
[op
].bitfield
.imm32
= 1;
3806 i
.types
[op
].bitfield
.imm64
= 1;
3808 case WORD_MNEM_SUFFIX
:
3809 i
.types
[op
].bitfield
.imm16
= 1;
3810 i
.types
[op
].bitfield
.imm32
= 1;
3811 i
.types
[op
].bitfield
.imm32s
= 1;
3812 i
.types
[op
].bitfield
.imm64
= 1;
3814 case BYTE_MNEM_SUFFIX
:
3815 i
.types
[op
].bitfield
.imm8
= 1;
3816 i
.types
[op
].bitfield
.imm8s
= 1;
3817 i
.types
[op
].bitfield
.imm16
= 1;
3818 i
.types
[op
].bitfield
.imm32
= 1;
3819 i
.types
[op
].bitfield
.imm32s
= 1;
3820 i
.types
[op
].bitfield
.imm64
= 1;
3824 /* If this operand is at most 16 bits, convert it
3825 to a signed 16 bit number before trying to see
3826 whether it will fit in an even smaller size.
3827 This allows a 16-bit operand such as $0xffe0 to
3828 be recognised as within Imm8S range. */
3829 if ((i
.types
[op
].bitfield
.imm16
)
3830 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3832 i
.op
[op
].imms
->X_add_number
=
3833 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3835 if ((i
.types
[op
].bitfield
.imm32
)
3836 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3839 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3840 ^ ((offsetT
) 1 << 31))
3841 - ((offsetT
) 1 << 31));
3844 = operand_type_or (i
.types
[op
],
3845 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3847 /* We must avoid matching of Imm32 templates when 64bit
3848 only immediate is available. */
3849 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3850 i
.types
[op
].bitfield
.imm32
= 0;
3857 /* Symbols and expressions. */
3859 /* Convert symbolic operand to proper sizes for matching, but don't
3860 prevent matching a set of insns that only supports sizes other
3861 than those matching the insn suffix. */
3863 i386_operand_type mask
, allowed
;
3864 const insn_template
*t
;
3866 operand_type_set (&mask
, 0);
3867 operand_type_set (&allowed
, 0);
3869 for (t
= current_templates
->start
;
3870 t
< current_templates
->end
;
3872 allowed
= operand_type_or (allowed
,
3873 t
->operand_types
[op
]);
3874 switch (guess_suffix
)
3876 case QWORD_MNEM_SUFFIX
:
3877 mask
.bitfield
.imm64
= 1;
3878 mask
.bitfield
.imm32s
= 1;
3880 case LONG_MNEM_SUFFIX
:
3881 mask
.bitfield
.imm32
= 1;
3883 case WORD_MNEM_SUFFIX
:
3884 mask
.bitfield
.imm16
= 1;
3886 case BYTE_MNEM_SUFFIX
:
3887 mask
.bitfield
.imm8
= 1;
3892 allowed
= operand_type_and (mask
, allowed
);
3893 if (!operand_type_all_zero (&allowed
))
3894 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3901 /* Try to use the smallest displacement type too. */
3903 optimize_disp (void)
3907 for (op
= i
.operands
; --op
>= 0;)
3908 if (operand_type_check (i
.types
[op
], disp
))
3910 if (i
.op
[op
].disps
->X_op
== O_constant
)
3912 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3914 if (i
.types
[op
].bitfield
.disp16
3915 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3917 /* If this operand is at most 16 bits, convert
3918 to a signed 16 bit number and don't use 64bit
3920 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3921 i
.types
[op
].bitfield
.disp64
= 0;
3923 if (i
.types
[op
].bitfield
.disp32
3924 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3926 /* If this operand is at most 32 bits, convert
3927 to a signed 32 bit number and don't use 64bit
3929 op_disp
&= (((offsetT
) 2 << 31) - 1);
3930 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3931 i
.types
[op
].bitfield
.disp64
= 0;
3933 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3935 i
.types
[op
].bitfield
.disp8
= 0;
3936 i
.types
[op
].bitfield
.disp16
= 0;
3937 i
.types
[op
].bitfield
.disp32
= 0;
3938 i
.types
[op
].bitfield
.disp32s
= 0;
3939 i
.types
[op
].bitfield
.disp64
= 0;
3943 else if (flag_code
== CODE_64BIT
)
3945 if (fits_in_signed_long (op_disp
))
3947 i
.types
[op
].bitfield
.disp64
= 0;
3948 i
.types
[op
].bitfield
.disp32s
= 1;
3950 if (i
.prefix
[ADDR_PREFIX
]
3951 && fits_in_unsigned_long (op_disp
))
3952 i
.types
[op
].bitfield
.disp32
= 1;
3954 if ((i
.types
[op
].bitfield
.disp32
3955 || i
.types
[op
].bitfield
.disp32s
3956 || i
.types
[op
].bitfield
.disp16
)
3957 && fits_in_signed_byte (op_disp
))
3958 i
.types
[op
].bitfield
.disp8
= 1;
3960 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3961 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3963 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3964 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3965 i
.types
[op
].bitfield
.disp8
= 0;
3966 i
.types
[op
].bitfield
.disp16
= 0;
3967 i
.types
[op
].bitfield
.disp32
= 0;
3968 i
.types
[op
].bitfield
.disp32s
= 0;
3969 i
.types
[op
].bitfield
.disp64
= 0;
3972 /* We only support 64bit displacement on constants. */
3973 i
.types
[op
].bitfield
.disp64
= 0;
3977 /* Check if operands are valid for the instruction. */
3980 check_VecOperands (const insn_template
*t
)
3982 /* Without VSIB byte, we can't have a vector register for index. */
3983 if (!t
->opcode_modifier
.vecsib
3985 && (i
.index_reg
->reg_type
.bitfield
.regxmm
3986 || i
.index_reg
->reg_type
.bitfield
.regymm
))
3988 i
.error
= unsupported_vector_index_register
;
3992 /* For VSIB byte, we need a vector register for index, and all vector
3993 registers must be distinct. */
3994 if (t
->opcode_modifier
.vecsib
)
3997 || !((t
->opcode_modifier
.vecsib
== VecSIB128
3998 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
3999 || (t
->opcode_modifier
.vecsib
== VecSIB256
4000 && i
.index_reg
->reg_type
.bitfield
.regymm
)))
4002 i
.error
= invalid_vsib_address
;
4006 gas_assert (i
.reg_operands
== 2);
4007 gas_assert (i
.types
[0].bitfield
.regxmm
4008 || i
.types
[0].bitfield
.regymm
);
4009 gas_assert (i
.types
[2].bitfield
.regxmm
4010 || i
.types
[2].bitfield
.regymm
);
4012 if (operand_check
== check_none
)
4014 if (register_number (i
.op
[0].regs
) != register_number (i
.index_reg
)
4015 && register_number (i
.op
[2].regs
) != register_number (i
.index_reg
)
4016 && register_number (i
.op
[0].regs
) != register_number (i
.op
[2].regs
))
4018 if (operand_check
== check_error
)
4020 i
.error
= invalid_vector_register_set
;
4023 as_warn (_("mask, index, and destination registers should be distinct"));
4029 /* Check if operands are valid for the instruction. Update VEX
4033 VEX_check_operands (const insn_template
*t
)
4035 if (!t
->opcode_modifier
.vex
)
4038 /* Only check VEX_Imm4, which must be the first operand. */
4039 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4041 if (i
.op
[0].imms
->X_op
!= O_constant
4042 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4048 /* Turn off Imm8 so that update_imm won't complain. */
4049 i
.types
[0] = vec_imm4
;
4055 static const insn_template
*
4056 match_template (void)
4058 /* Points to template once we've found it. */
4059 const insn_template
*t
;
4060 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4061 i386_operand_type overlap4
;
4062 unsigned int found_reverse_match
;
4063 i386_opcode_modifier suffix_check
;
4064 i386_operand_type operand_types
[MAX_OPERANDS
];
4065 int addr_prefix_disp
;
4067 unsigned int found_cpu_match
;
4068 unsigned int check_register
;
4069 enum i386_error specific_error
= 0;
4071 #if MAX_OPERANDS != 5
4072 # error "MAX_OPERANDS must be 5."
4075 found_reverse_match
= 0;
4076 addr_prefix_disp
= -1;
4078 memset (&suffix_check
, 0, sizeof (suffix_check
));
4079 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4080 suffix_check
.no_bsuf
= 1;
4081 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4082 suffix_check
.no_wsuf
= 1;
4083 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4084 suffix_check
.no_ssuf
= 1;
4085 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4086 suffix_check
.no_lsuf
= 1;
4087 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4088 suffix_check
.no_qsuf
= 1;
4089 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4090 suffix_check
.no_ldsuf
= 1;
4092 /* Must have right number of operands. */
4093 i
.error
= number_of_operands_mismatch
;
4095 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4097 addr_prefix_disp
= -1;
4099 if (i
.operands
!= t
->operands
)
4102 /* Check processor support. */
4103 i
.error
= unsupported
;
4104 found_cpu_match
= (cpu_flags_match (t
)
4105 == CPU_FLAGS_PERFECT_MATCH
);
4106 if (!found_cpu_match
)
4109 /* Check old gcc support. */
4110 i
.error
= old_gcc_only
;
4111 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4114 /* Check AT&T mnemonic. */
4115 i
.error
= unsupported_with_intel_mnemonic
;
4116 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4119 /* Check AT&T/Intel syntax. */
4120 i
.error
= unsupported_syntax
;
4121 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4122 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4125 /* Check the suffix, except for some instructions in intel mode. */
4126 i
.error
= invalid_instruction_suffix
;
4127 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4128 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4129 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4130 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4131 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4132 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4133 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4136 if (!operand_size_match (t
))
4139 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4140 operand_types
[j
] = t
->operand_types
[j
];
4142 /* In general, don't allow 64-bit operands in 32-bit mode. */
4143 if (i
.suffix
== QWORD_MNEM_SUFFIX
4144 && flag_code
!= CODE_64BIT
4146 ? (!t
->opcode_modifier
.ignoresize
4147 && !intel_float_operand (t
->name
))
4148 : intel_float_operand (t
->name
) != 2)
4149 && ((!operand_types
[0].bitfield
.regmmx
4150 && !operand_types
[0].bitfield
.regxmm
4151 && !operand_types
[0].bitfield
.regymm
)
4152 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4153 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4154 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
4155 && (t
->base_opcode
!= 0x0fc7
4156 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4159 /* In general, don't allow 32-bit operands on pre-386. */
4160 else if (i
.suffix
== LONG_MNEM_SUFFIX
4161 && !cpu_arch_flags
.bitfield
.cpui386
4163 ? (!t
->opcode_modifier
.ignoresize
4164 && !intel_float_operand (t
->name
))
4165 : intel_float_operand (t
->name
) != 2)
4166 && ((!operand_types
[0].bitfield
.regmmx
4167 && !operand_types
[0].bitfield
.regxmm
)
4168 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4169 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4172 /* Do not verify operands when there are none. */
4176 /* We've found a match; break out of loop. */
4180 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4181 into Disp32/Disp16/Disp32 operand. */
4182 if (i
.prefix
[ADDR_PREFIX
] != 0)
4184 /* There should be only one Disp operand. */
4188 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4190 if (operand_types
[j
].bitfield
.disp16
)
4192 addr_prefix_disp
= j
;
4193 operand_types
[j
].bitfield
.disp32
= 1;
4194 operand_types
[j
].bitfield
.disp16
= 0;
4200 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4202 if (operand_types
[j
].bitfield
.disp32
)
4204 addr_prefix_disp
= j
;
4205 operand_types
[j
].bitfield
.disp32
= 0;
4206 operand_types
[j
].bitfield
.disp16
= 1;
4212 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4214 if (operand_types
[j
].bitfield
.disp64
)
4216 addr_prefix_disp
= j
;
4217 operand_types
[j
].bitfield
.disp64
= 0;
4218 operand_types
[j
].bitfield
.disp32
= 1;
4226 /* We check register size if needed. */
4227 check_register
= t
->opcode_modifier
.checkregsize
;
4228 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4229 switch (t
->operands
)
4232 if (!operand_type_match (overlap0
, i
.types
[0]))
4236 /* xchg %eax, %eax is a special case. It is an aliase for nop
4237 only in 32bit mode and we can use opcode 0x90. In 64bit
4238 mode, we can't use 0x90 for xchg %eax, %eax since it should
4239 zero-extend %eax to %rax. */
4240 if (flag_code
== CODE_64BIT
4241 && t
->base_opcode
== 0x90
4242 && operand_type_equal (&i
.types
[0], &acc32
)
4243 && operand_type_equal (&i
.types
[1], &acc32
))
4247 /* If we swap operand in encoding, we either match
4248 the next one or reverse direction of operands. */
4249 if (t
->opcode_modifier
.s
)
4251 else if (t
->opcode_modifier
.d
)
4256 /* If we swap operand in encoding, we match the next one. */
4257 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4261 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4262 if (!operand_type_match (overlap0
, i
.types
[0])
4263 || !operand_type_match (overlap1
, i
.types
[1])
4265 && !operand_type_register_match (overlap0
, i
.types
[0],
4267 overlap1
, i
.types
[1],
4270 /* Check if other direction is valid ... */
4271 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4275 /* Try reversing direction of operands. */
4276 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4277 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4278 if (!operand_type_match (overlap0
, i
.types
[0])
4279 || !operand_type_match (overlap1
, i
.types
[1])
4281 && !operand_type_register_match (overlap0
,
4288 /* Does not match either direction. */
4291 /* found_reverse_match holds which of D or FloatDR
4293 if (t
->opcode_modifier
.d
)
4294 found_reverse_match
= Opcode_D
;
4295 else if (t
->opcode_modifier
.floatd
)
4296 found_reverse_match
= Opcode_FloatD
;
4298 found_reverse_match
= 0;
4299 if (t
->opcode_modifier
.floatr
)
4300 found_reverse_match
|= Opcode_FloatR
;
4304 /* Found a forward 2 operand match here. */
4305 switch (t
->operands
)
4308 overlap4
= operand_type_and (i
.types
[4],
4311 overlap3
= operand_type_and (i
.types
[3],
4314 overlap2
= operand_type_and (i
.types
[2],
4319 switch (t
->operands
)
4322 if (!operand_type_match (overlap4
, i
.types
[4])
4323 || !operand_type_register_match (overlap3
,
4331 if (!operand_type_match (overlap3
, i
.types
[3])
4333 && !operand_type_register_match (overlap2
,
4341 /* Here we make use of the fact that there are no
4342 reverse match 3 operand instructions, and all 3
4343 operand instructions only need to be checked for
4344 register consistency between operands 2 and 3. */
4345 if (!operand_type_match (overlap2
, i
.types
[2])
4347 && !operand_type_register_match (overlap1
,
4357 /* Found either forward/reverse 2, 3 or 4 operand match here:
4358 slip through to break. */
4360 if (!found_cpu_match
)
4362 found_reverse_match
= 0;
4366 /* Check if vector and VEX operands are valid. */
4367 if (check_VecOperands (t
) || VEX_check_operands (t
))
4369 specific_error
= i
.error
;
4373 /* We've found a match; break out of loop. */
4377 if (t
== current_templates
->end
)
4379 /* We found no match. */
4380 const char *err_msg
;
4381 switch (specific_error
? specific_error
: i
.error
)
4385 case operand_size_mismatch
:
4386 err_msg
= _("operand size mismatch");
4388 case operand_type_mismatch
:
4389 err_msg
= _("operand type mismatch");
4391 case register_type_mismatch
:
4392 err_msg
= _("register type mismatch");
4394 case number_of_operands_mismatch
:
4395 err_msg
= _("number of operands mismatch");
4397 case invalid_instruction_suffix
:
4398 err_msg
= _("invalid instruction suffix");
4401 err_msg
= _("constant doesn't fit in 4 bits");
4404 err_msg
= _("only supported with old gcc");
4406 case unsupported_with_intel_mnemonic
:
4407 err_msg
= _("unsupported with Intel mnemonic");
4409 case unsupported_syntax
:
4410 err_msg
= _("unsupported syntax");
4413 as_bad (_("unsupported instruction `%s'"),
4414 current_templates
->start
->name
);
4416 case invalid_vsib_address
:
4417 err_msg
= _("invalid VSIB address");
4419 case invalid_vector_register_set
:
4420 err_msg
= _("mask, index, and destination registers must be distinct");
4422 case unsupported_vector_index_register
:
4423 err_msg
= _("unsupported vector index register");
4426 as_bad (_("%s for `%s'"), err_msg
,
4427 current_templates
->start
->name
);
4431 if (!quiet_warnings
)
4434 && (i
.types
[0].bitfield
.jumpabsolute
4435 != operand_types
[0].bitfield
.jumpabsolute
))
4437 as_warn (_("indirect %s without `*'"), t
->name
);
4440 if (t
->opcode_modifier
.isprefix
4441 && t
->opcode_modifier
.ignoresize
)
4443 /* Warn them that a data or address size prefix doesn't
4444 affect assembly of the next line of code. */
4445 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4449 /* Copy the template we found. */
4452 if (addr_prefix_disp
!= -1)
4453 i
.tm
.operand_types
[addr_prefix_disp
]
4454 = operand_types
[addr_prefix_disp
];
4456 if (found_reverse_match
)
4458 /* If we found a reverse match we must alter the opcode
4459 direction bit. found_reverse_match holds bits to change
4460 (different for int & float insns). */
4462 i
.tm
.base_opcode
^= found_reverse_match
;
4464 i
.tm
.operand_types
[0] = operand_types
[1];
4465 i
.tm
.operand_types
[1] = operand_types
[0];
4474 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4475 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4477 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4479 as_bad (_("`%s' operand %d must use `%ses' segment"),
4485 /* There's only ever one segment override allowed per instruction.
4486 This instruction possibly has a legal segment override on the
4487 second operand, so copy the segment to where non-string
4488 instructions store it, allowing common code. */
4489 i
.seg
[0] = i
.seg
[1];
4491 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4493 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4495 as_bad (_("`%s' operand %d must use `%ses' segment"),
4506 process_suffix (void)
4508 /* If matched instruction specifies an explicit instruction mnemonic
4510 if (i
.tm
.opcode_modifier
.size16
)
4511 i
.suffix
= WORD_MNEM_SUFFIX
;
4512 else if (i
.tm
.opcode_modifier
.size32
)
4513 i
.suffix
= LONG_MNEM_SUFFIX
;
4514 else if (i
.tm
.opcode_modifier
.size64
)
4515 i
.suffix
= QWORD_MNEM_SUFFIX
;
4516 else if (i
.reg_operands
)
4518 /* If there's no instruction mnemonic suffix we try to invent one
4519 based on register operands. */
4522 /* We take i.suffix from the last register operand specified,
4523 Destination register type is more significant than source
4524 register type. crc32 in SSE4.2 prefers source register
4526 if (i
.tm
.base_opcode
== 0xf20f38f1)
4528 if (i
.types
[0].bitfield
.reg16
)
4529 i
.suffix
= WORD_MNEM_SUFFIX
;
4530 else if (i
.types
[0].bitfield
.reg32
)
4531 i
.suffix
= LONG_MNEM_SUFFIX
;
4532 else if (i
.types
[0].bitfield
.reg64
)
4533 i
.suffix
= QWORD_MNEM_SUFFIX
;
4535 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4537 if (i
.types
[0].bitfield
.reg8
)
4538 i
.suffix
= BYTE_MNEM_SUFFIX
;
4545 if (i
.tm
.base_opcode
== 0xf20f38f1
4546 || i
.tm
.base_opcode
== 0xf20f38f0)
4548 /* We have to know the operand size for crc32. */
4549 as_bad (_("ambiguous memory operand size for `%s`"),
4554 for (op
= i
.operands
; --op
>= 0;)
4555 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4557 if (i
.types
[op
].bitfield
.reg8
)
4559 i
.suffix
= BYTE_MNEM_SUFFIX
;
4562 else if (i
.types
[op
].bitfield
.reg16
)
4564 i
.suffix
= WORD_MNEM_SUFFIX
;
4567 else if (i
.types
[op
].bitfield
.reg32
)
4569 i
.suffix
= LONG_MNEM_SUFFIX
;
4572 else if (i
.types
[op
].bitfield
.reg64
)
4574 i
.suffix
= QWORD_MNEM_SUFFIX
;
4580 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4583 && i
.tm
.opcode_modifier
.ignoresize
4584 && i
.tm
.opcode_modifier
.no_bsuf
)
4586 else if (!check_byte_reg ())
4589 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4592 && i
.tm
.opcode_modifier
.ignoresize
4593 && i
.tm
.opcode_modifier
.no_lsuf
)
4595 else if (!check_long_reg ())
4598 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4601 && i
.tm
.opcode_modifier
.ignoresize
4602 && i
.tm
.opcode_modifier
.no_qsuf
)
4604 else if (!check_qword_reg ())
4607 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4610 && i
.tm
.opcode_modifier
.ignoresize
4611 && i
.tm
.opcode_modifier
.no_wsuf
)
4613 else if (!check_word_reg ())
4616 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4617 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4619 /* Skip if the instruction has x/y suffix. match_template
4620 should check if it is a valid suffix. */
4622 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4623 /* Do nothing if the instruction is going to ignore the prefix. */
4628 else if (i
.tm
.opcode_modifier
.defaultsize
4630 /* exclude fldenv/frstor/fsave/fstenv */
4631 && i
.tm
.opcode_modifier
.no_ssuf
)
4633 i
.suffix
= stackop_size
;
4635 else if (intel_syntax
4637 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4638 || i
.tm
.opcode_modifier
.jumpbyte
4639 || i
.tm
.opcode_modifier
.jumpintersegment
4640 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4641 && i
.tm
.extension_opcode
<= 3)))
4646 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4648 i
.suffix
= QWORD_MNEM_SUFFIX
;
4652 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4653 i
.suffix
= LONG_MNEM_SUFFIX
;
4656 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4657 i
.suffix
= WORD_MNEM_SUFFIX
;
4666 if (i
.tm
.opcode_modifier
.w
)
4668 as_bad (_("no instruction mnemonic suffix given and "
4669 "no register operands; can't size instruction"));
4675 unsigned int suffixes
;
4677 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4678 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4680 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4682 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4684 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4686 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4689 /* There are more than suffix matches. */
4690 if (i
.tm
.opcode_modifier
.w
4691 || ((suffixes
& (suffixes
- 1))
4692 && !i
.tm
.opcode_modifier
.defaultsize
4693 && !i
.tm
.opcode_modifier
.ignoresize
))
4695 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4701 /* Change the opcode based on the operand size given by i.suffix;
4702 We don't need to change things for byte insns. */
4705 && i
.suffix
!= BYTE_MNEM_SUFFIX
4706 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4707 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4709 /* It's not a byte, select word/dword operation. */
4710 if (i
.tm
.opcode_modifier
.w
)
4712 if (i
.tm
.opcode_modifier
.shortform
)
4713 i
.tm
.base_opcode
|= 8;
4715 i
.tm
.base_opcode
|= 1;
4718 /* Now select between word & dword operations via the operand
4719 size prefix, except for instructions that will ignore this
4721 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4723 /* The address size override prefix changes the size of the
4725 if ((flag_code
== CODE_32BIT
4726 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4727 || (flag_code
!= CODE_32BIT
4728 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4729 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4732 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4733 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4734 && !i
.tm
.opcode_modifier
.ignoresize
4735 && !i
.tm
.opcode_modifier
.floatmf
4736 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4737 || (flag_code
== CODE_64BIT
4738 && i
.tm
.opcode_modifier
.jumpbyte
)))
4740 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4742 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4743 prefix
= ADDR_PREFIX_OPCODE
;
4745 if (!add_prefix (prefix
))
4749 /* Set mode64 for an operand. */
4750 if (i
.suffix
== QWORD_MNEM_SUFFIX
4751 && flag_code
== CODE_64BIT
4752 && !i
.tm
.opcode_modifier
.norex64
)
4754 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4755 need rex64. cmpxchg8b is also a special case. */
4756 if (! (i
.operands
== 2
4757 && i
.tm
.base_opcode
== 0x90
4758 && i
.tm
.extension_opcode
== None
4759 && operand_type_equal (&i
.types
[0], &acc64
)
4760 && operand_type_equal (&i
.types
[1], &acc64
))
4761 && ! (i
.operands
== 1
4762 && i
.tm
.base_opcode
== 0xfc7
4763 && i
.tm
.extension_opcode
== 1
4764 && !operand_type_check (i
.types
[0], reg
)
4765 && operand_type_check (i
.types
[0], anymem
)))
4769 /* Size floating point instruction. */
4770 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4771 if (i
.tm
.opcode_modifier
.floatmf
)
4772 i
.tm
.base_opcode
^= 4;
4779 check_byte_reg (void)
4783 for (op
= i
.operands
; --op
>= 0;)
4785 /* If this is an eight bit register, it's OK. If it's the 16 or
4786 32 bit version of an eight bit register, we will just use the
4787 low portion, and that's OK too. */
4788 if (i
.types
[op
].bitfield
.reg8
)
4791 /* I/O port address operands are OK too. */
4792 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4795 /* crc32 doesn't generate this warning. */
4796 if (i
.tm
.base_opcode
== 0xf20f38f0)
4799 if ((i
.types
[op
].bitfield
.reg16
4800 || i
.types
[op
].bitfield
.reg32
4801 || i
.types
[op
].bitfield
.reg64
)
4802 && i
.op
[op
].regs
->reg_num
< 4
4803 /* Prohibit these changes in 64bit mode, since the lowering
4804 would be more complicated. */
4805 && flag_code
!= CODE_64BIT
)
4807 #if REGISTER_WARNINGS
4808 if (!quiet_warnings
)
4809 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4811 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4812 ? REGNAM_AL
- REGNAM_AX
4813 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4815 i
.op
[op
].regs
->reg_name
,
4820 /* Any other register is bad. */
4821 if (i
.types
[op
].bitfield
.reg16
4822 || i
.types
[op
].bitfield
.reg32
4823 || i
.types
[op
].bitfield
.reg64
4824 || i
.types
[op
].bitfield
.regmmx
4825 || i
.types
[op
].bitfield
.regxmm
4826 || i
.types
[op
].bitfield
.regymm
4827 || i
.types
[op
].bitfield
.sreg2
4828 || i
.types
[op
].bitfield
.sreg3
4829 || i
.types
[op
].bitfield
.control
4830 || i
.types
[op
].bitfield
.debug
4831 || i
.types
[op
].bitfield
.test
4832 || i
.types
[op
].bitfield
.floatreg
4833 || i
.types
[op
].bitfield
.floatacc
)
4835 as_bad (_("`%s%s' not allowed with `%s%c'"),
4837 i
.op
[op
].regs
->reg_name
,
4847 check_long_reg (void)
4851 for (op
= i
.operands
; --op
>= 0;)
4852 /* Reject eight bit registers, except where the template requires
4853 them. (eg. movzb) */
4854 if (i
.types
[op
].bitfield
.reg8
4855 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4856 || i
.tm
.operand_types
[op
].bitfield
.reg32
4857 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4859 as_bad (_("`%s%s' not allowed with `%s%c'"),
4861 i
.op
[op
].regs
->reg_name
,
4866 /* Warn if the e prefix on a general reg is missing. */
4867 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4868 && i
.types
[op
].bitfield
.reg16
4869 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4870 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4872 /* Prohibit these changes in the 64bit mode, since the
4873 lowering is more complicated. */
4874 if (flag_code
== CODE_64BIT
)
4876 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4877 register_prefix
, i
.op
[op
].regs
->reg_name
,
4881 #if REGISTER_WARNINGS
4883 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4885 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4887 i
.op
[op
].regs
->reg_name
,
4891 /* Warn if the r prefix on a general reg is missing. */
4892 else if (i
.types
[op
].bitfield
.reg64
4893 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4894 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4897 && i
.tm
.opcode_modifier
.toqword
4898 && !i
.types
[0].bitfield
.regxmm
)
4900 /* Convert to QWORD. We want REX byte. */
4901 i
.suffix
= QWORD_MNEM_SUFFIX
;
4905 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4906 register_prefix
, i
.op
[op
].regs
->reg_name
,
4915 check_qword_reg (void)
4919 for (op
= i
.operands
; --op
>= 0; )
4920 /* Reject eight bit registers, except where the template requires
4921 them. (eg. movzb) */
4922 if (i
.types
[op
].bitfield
.reg8
4923 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4924 || i
.tm
.operand_types
[op
].bitfield
.reg32
4925 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4927 as_bad (_("`%s%s' not allowed with `%s%c'"),
4929 i
.op
[op
].regs
->reg_name
,
4934 /* Warn if the e prefix on a general reg is missing. */
4935 else if ((i
.types
[op
].bitfield
.reg16
4936 || i
.types
[op
].bitfield
.reg32
)
4937 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4938 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4940 /* Prohibit these changes in the 64bit mode, since the
4941 lowering is more complicated. */
4943 && i
.tm
.opcode_modifier
.todword
4944 && !i
.types
[0].bitfield
.regxmm
)
4946 /* Convert to DWORD. We don't want REX byte. */
4947 i
.suffix
= LONG_MNEM_SUFFIX
;
4951 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4952 register_prefix
, i
.op
[op
].regs
->reg_name
,
4961 check_word_reg (void)
4964 for (op
= i
.operands
; --op
>= 0;)
4965 /* Reject eight bit registers, except where the template requires
4966 them. (eg. movzb) */
4967 if (i
.types
[op
].bitfield
.reg8
4968 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4969 || i
.tm
.operand_types
[op
].bitfield
.reg32
4970 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4972 as_bad (_("`%s%s' not allowed with `%s%c'"),
4974 i
.op
[op
].regs
->reg_name
,
4979 /* Warn if the e prefix on a general reg is present. */
4980 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4981 && i
.types
[op
].bitfield
.reg32
4982 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4983 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4985 /* Prohibit these changes in the 64bit mode, since the
4986 lowering is more complicated. */
4987 if (flag_code
== CODE_64BIT
)
4989 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4990 register_prefix
, i
.op
[op
].regs
->reg_name
,
4995 #if REGISTER_WARNINGS
4996 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4998 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5000 i
.op
[op
].regs
->reg_name
,
5008 update_imm (unsigned int j
)
5010 i386_operand_type overlap
= i
.types
[j
];
5011 if ((overlap
.bitfield
.imm8
5012 || overlap
.bitfield
.imm8s
5013 || overlap
.bitfield
.imm16
5014 || overlap
.bitfield
.imm32
5015 || overlap
.bitfield
.imm32s
5016 || overlap
.bitfield
.imm64
)
5017 && !operand_type_equal (&overlap
, &imm8
)
5018 && !operand_type_equal (&overlap
, &imm8s
)
5019 && !operand_type_equal (&overlap
, &imm16
)
5020 && !operand_type_equal (&overlap
, &imm32
)
5021 && !operand_type_equal (&overlap
, &imm32s
)
5022 && !operand_type_equal (&overlap
, &imm64
))
5026 i386_operand_type temp
;
5028 operand_type_set (&temp
, 0);
5029 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5031 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5032 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5034 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5035 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5036 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5038 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5039 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5042 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5045 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5046 || operand_type_equal (&overlap
, &imm16_32
)
5047 || operand_type_equal (&overlap
, &imm16_32s
))
5049 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5054 if (!operand_type_equal (&overlap
, &imm8
)
5055 && !operand_type_equal (&overlap
, &imm8s
)
5056 && !operand_type_equal (&overlap
, &imm16
)
5057 && !operand_type_equal (&overlap
, &imm32
)
5058 && !operand_type_equal (&overlap
, &imm32s
)
5059 && !operand_type_equal (&overlap
, &imm64
))
5061 as_bad (_("no instruction mnemonic suffix given; "
5062 "can't determine immediate size"));
5066 i
.types
[j
] = overlap
;
5076 /* Update the first 2 immediate operands. */
5077 n
= i
.operands
> 2 ? 2 : i
.operands
;
5080 for (j
= 0; j
< n
; j
++)
5081 if (update_imm (j
) == 0)
5084 /* The 3rd operand can't be immediate operand. */
5085 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5092 bad_implicit_operand (int xmm
)
5094 const char *ireg
= xmm
? "xmm0" : "ymm0";
5097 as_bad (_("the last operand of `%s' must be `%s%s'"),
5098 i
.tm
.name
, register_prefix
, ireg
);
5100 as_bad (_("the first operand of `%s' must be `%s%s'"),
5101 i
.tm
.name
, register_prefix
, ireg
);
5106 process_operands (void)
5108 /* Default segment register this instruction will use for memory
5109 accesses. 0 means unknown. This is only for optimizing out
5110 unnecessary segment overrides. */
5111 const seg_entry
*default_seg
= 0;
5113 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5115 unsigned int dupl
= i
.operands
;
5116 unsigned int dest
= dupl
- 1;
5119 /* The destination must be an xmm register. */
5120 gas_assert (i
.reg_operands
5121 && MAX_OPERANDS
> dupl
5122 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5124 if (i
.tm
.opcode_modifier
.firstxmm0
)
5126 /* The first operand is implicit and must be xmm0. */
5127 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5128 if (register_number (i
.op
[0].regs
) != 0)
5129 return bad_implicit_operand (1);
5131 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5133 /* Keep xmm0 for instructions with VEX prefix and 3
5139 /* We remove the first xmm0 and keep the number of
5140 operands unchanged, which in fact duplicates the
5142 for (j
= 1; j
< i
.operands
; j
++)
5144 i
.op
[j
- 1] = i
.op
[j
];
5145 i
.types
[j
- 1] = i
.types
[j
];
5146 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5150 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5152 gas_assert ((MAX_OPERANDS
- 1) > dupl
5153 && (i
.tm
.opcode_modifier
.vexsources
5156 /* Add the implicit xmm0 for instructions with VEX prefix
5158 for (j
= i
.operands
; j
> 0; j
--)
5160 i
.op
[j
] = i
.op
[j
- 1];
5161 i
.types
[j
] = i
.types
[j
- 1];
5162 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5165 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5166 i
.types
[0] = regxmm
;
5167 i
.tm
.operand_types
[0] = regxmm
;
5170 i
.reg_operands
+= 2;
5175 i
.op
[dupl
] = i
.op
[dest
];
5176 i
.types
[dupl
] = i
.types
[dest
];
5177 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5186 i
.op
[dupl
] = i
.op
[dest
];
5187 i
.types
[dupl
] = i
.types
[dest
];
5188 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5191 if (i
.tm
.opcode_modifier
.immext
)
5194 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5198 /* The first operand is implicit and must be xmm0/ymm0. */
5199 gas_assert (i
.reg_operands
5200 && (operand_type_equal (&i
.types
[0], ®xmm
)
5201 || operand_type_equal (&i
.types
[0], ®ymm
)));
5202 if (register_number (i
.op
[0].regs
) != 0)
5203 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5205 for (j
= 1; j
< i
.operands
; j
++)
5207 i
.op
[j
- 1] = i
.op
[j
];
5208 i
.types
[j
- 1] = i
.types
[j
];
5210 /* We need to adjust fields in i.tm since they are used by
5211 build_modrm_byte. */
5212 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5219 else if (i
.tm
.opcode_modifier
.regkludge
)
5221 /* The imul $imm, %reg instruction is converted into
5222 imul $imm, %reg, %reg, and the clr %reg instruction
5223 is converted into xor %reg, %reg. */
5225 unsigned int first_reg_op
;
5227 if (operand_type_check (i
.types
[0], reg
))
5231 /* Pretend we saw the extra register operand. */
5232 gas_assert (i
.reg_operands
== 1
5233 && i
.op
[first_reg_op
+ 1].regs
== 0);
5234 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5235 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5240 if (i
.tm
.opcode_modifier
.shortform
)
5242 if (i
.types
[0].bitfield
.sreg2
5243 || i
.types
[0].bitfield
.sreg3
)
5245 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5246 && i
.op
[0].regs
->reg_num
== 1)
5248 as_bad (_("you can't `pop %scs'"), register_prefix
);
5251 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5252 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5257 /* The register or float register operand is in operand
5261 if (i
.types
[0].bitfield
.floatreg
5262 || operand_type_check (i
.types
[0], reg
))
5266 /* Register goes in low 3 bits of opcode. */
5267 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5268 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5270 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5272 /* Warn about some common errors, but press on regardless.
5273 The first case can be generated by gcc (<= 2.8.1). */
5274 if (i
.operands
== 2)
5276 /* Reversed arguments on faddp, fsubp, etc. */
5277 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5278 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5279 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5283 /* Extraneous `l' suffix on fp insn. */
5284 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5285 register_prefix
, i
.op
[0].regs
->reg_name
);
5290 else if (i
.tm
.opcode_modifier
.modrm
)
5292 /* The opcode is completed (modulo i.tm.extension_opcode which
5293 must be put into the modrm byte). Now, we make the modrm and
5294 index base bytes based on all the info we've collected. */
5296 default_seg
= build_modrm_byte ();
5298 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5302 else if (i
.tm
.opcode_modifier
.isstring
)
5304 /* For the string instructions that allow a segment override
5305 on one of their operands, the default segment is ds. */
5309 if (i
.tm
.base_opcode
== 0x8d /* lea */
5312 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5314 /* If a segment was explicitly specified, and the specified segment
5315 is not the default, use an opcode prefix to select it. If we
5316 never figured out what the default segment is, then default_seg
5317 will be zero at this point, and the specified segment prefix will
5319 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5321 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5327 static const seg_entry
*
5328 build_modrm_byte (void)
5330 const seg_entry
*default_seg
= 0;
5331 unsigned int source
, dest
;
5334 /* The first operand of instructions with VEX prefix and 3 sources
5335 must be VEX_Imm4. */
5336 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5339 unsigned int nds
, reg_slot
;
5342 if (i
.tm
.opcode_modifier
.veximmext
5343 && i
.tm
.opcode_modifier
.immext
)
5345 dest
= i
.operands
- 2;
5346 gas_assert (dest
== 3);
5349 dest
= i
.operands
- 1;
5352 /* There are 2 kinds of instructions:
5353 1. 5 operands: 4 register operands or 3 register operands
5354 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5355 VexW0 or VexW1. The destination must be either XMM or YMM
5357 2. 4 operands: 4 register operands or 3 register operands
5358 plus 1 memory operand, VexXDS, and VexImmExt */
5359 gas_assert ((i
.reg_operands
== 4
5360 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5361 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5362 && (i
.tm
.opcode_modifier
.veximmext
5363 || (i
.imm_operands
== 1
5364 && i
.types
[0].bitfield
.vec_imm4
5365 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5366 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5367 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5368 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5370 if (i
.imm_operands
== 0)
5372 /* When there is no immediate operand, generate an 8bit
5373 immediate operand to encode the first operand. */
5374 exp
= &im_expressions
[i
.imm_operands
++];
5375 i
.op
[i
.operands
].imms
= exp
;
5376 i
.types
[i
.operands
] = imm8
;
5378 /* If VexW1 is set, the first operand is the source and
5379 the second operand is encoded in the immediate operand. */
5380 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5391 /* FMA swaps REG and NDS. */
5392 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5400 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5402 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5404 exp
->X_op
= O_constant
;
5405 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5409 unsigned int imm_slot
;
5411 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5413 /* If VexW0 is set, the third operand is the source and
5414 the second operand is encoded in the immediate
5421 /* VexW1 is set, the second operand is the source and
5422 the third operand is encoded in the immediate
5428 if (i
.tm
.opcode_modifier
.immext
)
5430 /* When ImmExt is set, the immdiate byte is the last
5432 imm_slot
= i
.operands
- 1;
5440 /* Turn on Imm8 so that output_imm will generate it. */
5441 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5444 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5446 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5448 i
.op
[imm_slot
].imms
->X_add_number
5449 |= register_number (i
.op
[reg_slot
].regs
) << 4;
5452 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5453 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5455 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5460 /* i.reg_operands MUST be the number of real register operands;
5461 implicit registers do not count. If there are 3 register
5462 operands, it must be a instruction with VexNDS. For a
5463 instruction with VexNDD, the destination register is encoded
5464 in VEX prefix. If there are 4 register operands, it must be
5465 a instruction with VEX prefix and 3 sources. */
5466 if (i
.mem_operands
== 0
5467 && ((i
.reg_operands
== 2
5468 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5469 || (i
.reg_operands
== 3
5470 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5471 || (i
.reg_operands
== 4 && vex_3_sources
)))
5479 /* When there are 3 operands, one of them may be immediate,
5480 which may be the first or the last operand. Otherwise,
5481 the first operand must be shift count register (cl) or it
5482 is an instruction with VexNDS. */
5483 gas_assert (i
.imm_operands
== 1
5484 || (i
.imm_operands
== 0
5485 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5486 || i
.types
[0].bitfield
.shiftcount
)));
5487 if (operand_type_check (i
.types
[0], imm
)
5488 || i
.types
[0].bitfield
.shiftcount
)
5494 /* When there are 4 operands, the first two must be 8bit
5495 immediate operands. The source operand will be the 3rd
5498 For instructions with VexNDS, if the first operand
5499 an imm8, the source operand is the 2nd one. If the last
5500 operand is imm8, the source operand is the first one. */
5501 gas_assert ((i
.imm_operands
== 2
5502 && i
.types
[0].bitfield
.imm8
5503 && i
.types
[1].bitfield
.imm8
)
5504 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5505 && i
.imm_operands
== 1
5506 && (i
.types
[0].bitfield
.imm8
5507 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5508 if (i
.imm_operands
== 2)
5512 if (i
.types
[0].bitfield
.imm8
)
5528 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5530 /* For instructions with VexNDS, the register-only
5531 source operand must be 32/64bit integer, XMM or
5532 YMM register. It is encoded in VEX prefix. We
5533 need to clear RegMem bit before calling
5534 operand_type_equal. */
5536 i386_operand_type op
;
5539 /* Check register-only source operand when two source
5540 operands are swapped. */
5541 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
5542 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
5550 op
= i
.tm
.operand_types
[vvvv
];
5551 op
.bitfield
.regmem
= 0;
5552 if ((dest
+ 1) >= i
.operands
5553 || (op
.bitfield
.reg32
!= 1
5554 && !op
.bitfield
.reg64
!= 1
5555 && !operand_type_equal (&op
, ®xmm
)
5556 && !operand_type_equal (&op
, ®ymm
)))
5558 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
5564 /* One of the register operands will be encoded in the i.tm.reg
5565 field, the other in the combined i.tm.mode and i.tm.regmem
5566 fields. If no form of this instruction supports a memory
5567 destination operand, then we assume the source operand may
5568 sometimes be a memory operand and so we need to store the
5569 destination in the i.rm.reg field. */
5570 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5571 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5573 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5574 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5575 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5577 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5582 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5583 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5584 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5586 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5589 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5591 if (!i
.types
[0].bitfield
.control
5592 && !i
.types
[1].bitfield
.control
)
5594 i
.rex
&= ~(REX_R
| REX_B
);
5595 add_prefix (LOCK_PREFIX_OPCODE
);
5599 { /* If it's not 2 reg operands... */
5604 unsigned int fake_zero_displacement
= 0;
5607 for (op
= 0; op
< i
.operands
; op
++)
5608 if (operand_type_check (i
.types
[op
], anymem
))
5610 gas_assert (op
< i
.operands
);
5612 if (i
.tm
.opcode_modifier
.vecsib
)
5614 if (i
.index_reg
->reg_num
== RegEiz
5615 || i
.index_reg
->reg_num
== RegRiz
)
5618 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5621 i
.sib
.base
= NO_BASE_REGISTER
;
5622 i
.sib
.scale
= i
.log2_scale_factor
;
5623 i
.types
[op
].bitfield
.disp8
= 0;
5624 i
.types
[op
].bitfield
.disp16
= 0;
5625 i
.types
[op
].bitfield
.disp64
= 0;
5626 if (flag_code
!= CODE_64BIT
)
5628 /* Must be 32 bit */
5629 i
.types
[op
].bitfield
.disp32
= 1;
5630 i
.types
[op
].bitfield
.disp32s
= 0;
5634 i
.types
[op
].bitfield
.disp32
= 0;
5635 i
.types
[op
].bitfield
.disp32s
= 1;
5638 i
.sib
.index
= i
.index_reg
->reg_num
;
5639 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5645 if (i
.base_reg
== 0)
5648 if (!i
.disp_operands
)
5650 fake_zero_displacement
= 1;
5651 /* Instructions with VSIB byte need 32bit displacement
5652 if there is no base register. */
5653 if (i
.tm
.opcode_modifier
.vecsib
)
5654 i
.types
[op
].bitfield
.disp32
= 1;
5656 if (i
.index_reg
== 0)
5658 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5659 /* Operand is just <disp> */
5660 if (flag_code
== CODE_64BIT
)
5662 /* 64bit mode overwrites the 32bit absolute
5663 addressing by RIP relative addressing and
5664 absolute addressing is encoded by one of the
5665 redundant SIB forms. */
5666 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5667 i
.sib
.base
= NO_BASE_REGISTER
;
5668 i
.sib
.index
= NO_INDEX_REGISTER
;
5669 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5670 ? disp32s
: disp32
);
5672 else if ((flag_code
== CODE_16BIT
)
5673 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5675 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5676 i
.types
[op
] = disp16
;
5680 i
.rm
.regmem
= NO_BASE_REGISTER
;
5681 i
.types
[op
] = disp32
;
5684 else if (!i
.tm
.opcode_modifier
.vecsib
)
5686 /* !i.base_reg && i.index_reg */
5687 if (i
.index_reg
->reg_num
== RegEiz
5688 || i
.index_reg
->reg_num
== RegRiz
)
5689 i
.sib
.index
= NO_INDEX_REGISTER
;
5691 i
.sib
.index
= i
.index_reg
->reg_num
;
5692 i
.sib
.base
= NO_BASE_REGISTER
;
5693 i
.sib
.scale
= i
.log2_scale_factor
;
5694 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5695 i
.types
[op
].bitfield
.disp8
= 0;
5696 i
.types
[op
].bitfield
.disp16
= 0;
5697 i
.types
[op
].bitfield
.disp64
= 0;
5698 if (flag_code
!= CODE_64BIT
)
5700 /* Must be 32 bit */
5701 i
.types
[op
].bitfield
.disp32
= 1;
5702 i
.types
[op
].bitfield
.disp32s
= 0;
5706 i
.types
[op
].bitfield
.disp32
= 0;
5707 i
.types
[op
].bitfield
.disp32s
= 1;
5709 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5713 /* RIP addressing for 64bit mode. */
5714 else if (i
.base_reg
->reg_num
== RegRip
||
5715 i
.base_reg
->reg_num
== RegEip
)
5717 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5718 i
.rm
.regmem
= NO_BASE_REGISTER
;
5719 i
.types
[op
].bitfield
.disp8
= 0;
5720 i
.types
[op
].bitfield
.disp16
= 0;
5721 i
.types
[op
].bitfield
.disp32
= 0;
5722 i
.types
[op
].bitfield
.disp32s
= 1;
5723 i
.types
[op
].bitfield
.disp64
= 0;
5724 i
.flags
[op
] |= Operand_PCrel
;
5725 if (! i
.disp_operands
)
5726 fake_zero_displacement
= 1;
5728 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5730 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5731 switch (i
.base_reg
->reg_num
)
5734 if (i
.index_reg
== 0)
5736 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5737 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5741 if (i
.index_reg
== 0)
5744 if (operand_type_check (i
.types
[op
], disp
) == 0)
5746 /* fake (%bp) into 0(%bp) */
5747 i
.types
[op
].bitfield
.disp8
= 1;
5748 fake_zero_displacement
= 1;
5751 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5752 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5754 default: /* (%si) -> 4 or (%di) -> 5 */
5755 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5757 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5759 else /* i.base_reg and 32/64 bit mode */
5761 if (flag_code
== CODE_64BIT
5762 && operand_type_check (i
.types
[op
], disp
))
5764 i386_operand_type temp
;
5765 operand_type_set (&temp
, 0);
5766 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5768 if (i
.prefix
[ADDR_PREFIX
] == 0)
5769 i
.types
[op
].bitfield
.disp32s
= 1;
5771 i
.types
[op
].bitfield
.disp32
= 1;
5774 if (!i
.tm
.opcode_modifier
.vecsib
)
5775 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5776 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5778 i
.sib
.base
= i
.base_reg
->reg_num
;
5779 /* x86-64 ignores REX prefix bit here to avoid decoder
5781 if (!(i
.base_reg
->reg_flags
& RegRex
)
5782 && (i
.base_reg
->reg_num
== EBP_REG_NUM
5783 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
5785 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
5787 fake_zero_displacement
= 1;
5788 i
.types
[op
].bitfield
.disp8
= 1;
5790 i
.sib
.scale
= i
.log2_scale_factor
;
5791 if (i
.index_reg
== 0)
5793 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5794 /* <disp>(%esp) becomes two byte modrm with no index
5795 register. We've already stored the code for esp
5796 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5797 Any base register besides %esp will not use the
5798 extra modrm byte. */
5799 i
.sib
.index
= NO_INDEX_REGISTER
;
5801 else if (!i
.tm
.opcode_modifier
.vecsib
)
5803 if (i
.index_reg
->reg_num
== RegEiz
5804 || i
.index_reg
->reg_num
== RegRiz
)
5805 i
.sib
.index
= NO_INDEX_REGISTER
;
5807 i
.sib
.index
= i
.index_reg
->reg_num
;
5808 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5809 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5814 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5815 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5819 if (!fake_zero_displacement
5823 fake_zero_displacement
= 1;
5824 if (i
.disp_encoding
== disp_encoding_8bit
)
5825 i
.types
[op
].bitfield
.disp8
= 1;
5827 i
.types
[op
].bitfield
.disp32
= 1;
5829 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5833 if (fake_zero_displacement
)
5835 /* Fakes a zero displacement assuming that i.types[op]
5836 holds the correct displacement size. */
5839 gas_assert (i
.op
[op
].disps
== 0);
5840 exp
= &disp_expressions
[i
.disp_operands
++];
5841 i
.op
[op
].disps
= exp
;
5842 exp
->X_op
= O_constant
;
5843 exp
->X_add_number
= 0;
5844 exp
->X_add_symbol
= (symbolS
*) 0;
5845 exp
->X_op_symbol
= (symbolS
*) 0;
5853 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5855 if (operand_type_check (i
.types
[0], imm
))
5856 i
.vex
.register_specifier
= NULL
;
5859 /* VEX.vvvv encodes one of the sources when the first
5860 operand is not an immediate. */
5861 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5862 i
.vex
.register_specifier
= i
.op
[0].regs
;
5864 i
.vex
.register_specifier
= i
.op
[1].regs
;
5867 /* Destination is a XMM register encoded in the ModRM.reg
5869 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5870 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5873 /* ModRM.rm and VEX.B encodes the other source. */
5874 if (!i
.mem_operands
)
5878 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5879 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5881 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5883 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5887 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5889 i
.vex
.register_specifier
= i
.op
[2].regs
;
5890 if (!i
.mem_operands
)
5893 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5894 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5898 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5899 (if any) based on i.tm.extension_opcode. Again, we must be
5900 careful to make sure that segment/control/debug/test/MMX
5901 registers are coded into the i.rm.reg field. */
5902 else if (i
.reg_operands
)
5905 unsigned int vex_reg
= ~0;
5907 for (op
= 0; op
< i
.operands
; op
++)
5908 if (i
.types
[op
].bitfield
.reg8
5909 || i
.types
[op
].bitfield
.reg16
5910 || i
.types
[op
].bitfield
.reg32
5911 || i
.types
[op
].bitfield
.reg64
5912 || i
.types
[op
].bitfield
.regmmx
5913 || i
.types
[op
].bitfield
.regxmm
5914 || i
.types
[op
].bitfield
.regymm
5915 || i
.types
[op
].bitfield
.sreg2
5916 || i
.types
[op
].bitfield
.sreg3
5917 || i
.types
[op
].bitfield
.control
5918 || i
.types
[op
].bitfield
.debug
5919 || i
.types
[op
].bitfield
.test
)
5924 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5926 /* For instructions with VexNDS, the register-only
5927 source operand is encoded in VEX prefix. */
5928 gas_assert (mem
!= (unsigned int) ~0);
5933 gas_assert (op
< i
.operands
);
5937 /* Check register-only source operand when two source
5938 operands are swapped. */
5939 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
5940 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
5944 gas_assert (mem
== (vex_reg
+ 1)
5945 && op
< i
.operands
);
5950 gas_assert (vex_reg
< i
.operands
);
5954 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5956 /* For instructions with VexNDD, the register destination
5957 is encoded in VEX prefix. */
5958 if (i
.mem_operands
== 0)
5960 /* There is no memory operand. */
5961 gas_assert ((op
+ 2) == i
.operands
);
5966 /* There are only 2 operands. */
5967 gas_assert (op
< 2 && i
.operands
== 2);
5972 gas_assert (op
< i
.operands
);
5974 if (vex_reg
!= (unsigned int) ~0)
5976 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
5978 if (type
->bitfield
.reg32
!= 1
5979 && type
->bitfield
.reg64
!= 1
5980 && !operand_type_equal (type
, ®xmm
)
5981 && !operand_type_equal (type
, ®ymm
))
5984 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5987 /* Don't set OP operand twice. */
5990 /* If there is an extension opcode to put here, the
5991 register number must be put into the regmem field. */
5992 if (i
.tm
.extension_opcode
!= None
)
5994 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5995 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6000 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6001 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6006 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6007 must set it to 3 to indicate this is a register operand
6008 in the regmem field. */
6009 if (!i
.mem_operands
)
6013 /* Fill in i.rm.reg field with extension opcode (if any). */
6014 if (i
.tm
.extension_opcode
!= None
)
6015 i
.rm
.reg
= i
.tm
.extension_opcode
;
6021 output_branch (void)
6027 relax_substateT subtype
;
6031 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6032 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6035 if (i
.prefix
[DATA_PREFIX
] != 0)
6041 /* Pentium4 branch hints. */
6042 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6043 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6048 if (i
.prefix
[REX_PREFIX
] != 0)
6054 if (i
.prefixes
!= 0 && !intel_syntax
)
6055 as_warn (_("skipping prefixes on this instruction"));
6057 /* It's always a symbol; End frag & setup for relax.
6058 Make sure there is enough room in this frag for the largest
6059 instruction we may generate in md_convert_frag. This is 2
6060 bytes for the opcode and room for the prefix and largest
6062 frag_grow (prefix
+ 2 + 4);
6063 /* Prefix and 1 opcode byte go in fr_fix. */
6064 p
= frag_more (prefix
+ 1);
6065 if (i
.prefix
[DATA_PREFIX
] != 0)
6066 *p
++ = DATA_PREFIX_OPCODE
;
6067 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6068 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6069 *p
++ = i
.prefix
[SEG_PREFIX
];
6070 if (i
.prefix
[REX_PREFIX
] != 0)
6071 *p
++ = i
.prefix
[REX_PREFIX
];
6072 *p
= i
.tm
.base_opcode
;
6074 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6075 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6076 else if (cpu_arch_flags
.bitfield
.cpui386
)
6077 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6079 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6082 sym
= i
.op
[0].disps
->X_add_symbol
;
6083 off
= i
.op
[0].disps
->X_add_number
;
6085 if (i
.op
[0].disps
->X_op
!= O_constant
6086 && i
.op
[0].disps
->X_op
!= O_symbol
)
6088 /* Handle complex expressions. */
6089 sym
= make_expr_symbol (i
.op
[0].disps
);
6093 /* 1 possible extra opcode + 4 byte displacement go in var part.
6094 Pass reloc in fr_var. */
6095 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6105 if (i
.tm
.opcode_modifier
.jumpbyte
)
6107 /* This is a loop or jecxz type instruction. */
6109 if (i
.prefix
[ADDR_PREFIX
] != 0)
6111 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6114 /* Pentium4 branch hints. */
6115 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6116 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6118 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6127 if (flag_code
== CODE_16BIT
)
6130 if (i
.prefix
[DATA_PREFIX
] != 0)
6132 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6142 if (i
.prefix
[REX_PREFIX
] != 0)
6144 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6148 if (i
.prefixes
!= 0 && !intel_syntax
)
6149 as_warn (_("skipping prefixes on this instruction"));
6151 p
= frag_more (i
.tm
.opcode_length
+ size
);
6152 switch (i
.tm
.opcode_length
)
6155 *p
++ = i
.tm
.base_opcode
>> 8;
6157 *p
++ = i
.tm
.base_opcode
;
6163 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6164 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6166 /* All jumps handled here are signed, but don't use a signed limit
6167 check for 32 and 16 bit jumps as we want to allow wrap around at
6168 4G and 64k respectively. */
6170 fixP
->fx_signed
= 1;
6174 output_interseg_jump (void)
6182 if (flag_code
== CODE_16BIT
)
6186 if (i
.prefix
[DATA_PREFIX
] != 0)
6192 if (i
.prefix
[REX_PREFIX
] != 0)
6202 if (i
.prefixes
!= 0 && !intel_syntax
)
6203 as_warn (_("skipping prefixes on this instruction"));
6205 /* 1 opcode; 2 segment; offset */
6206 p
= frag_more (prefix
+ 1 + 2 + size
);
6208 if (i
.prefix
[DATA_PREFIX
] != 0)
6209 *p
++ = DATA_PREFIX_OPCODE
;
6211 if (i
.prefix
[REX_PREFIX
] != 0)
6212 *p
++ = i
.prefix
[REX_PREFIX
];
6214 *p
++ = i
.tm
.base_opcode
;
6215 if (i
.op
[1].imms
->X_op
== O_constant
)
6217 offsetT n
= i
.op
[1].imms
->X_add_number
;
6220 && !fits_in_unsigned_word (n
)
6221 && !fits_in_signed_word (n
))
6223 as_bad (_("16-bit jump out of range"));
6226 md_number_to_chars (p
, n
, size
);
6229 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6230 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6231 if (i
.op
[0].imms
->X_op
!= O_constant
)
6232 as_bad (_("can't handle non absolute segment in `%s'"),
6234 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6240 fragS
*insn_start_frag
;
6241 offsetT insn_start_off
;
6243 /* Tie dwarf2 debug info to the address at the start of the insn.
6244 We can't do this after the insn has been output as the current
6245 frag may have been closed off. eg. by frag_var. */
6246 dwarf2_emit_insn (0);
6248 insn_start_frag
= frag_now
;
6249 insn_start_off
= frag_now_fix ();
6252 if (i
.tm
.opcode_modifier
.jump
)
6254 else if (i
.tm
.opcode_modifier
.jumpbyte
6255 || i
.tm
.opcode_modifier
.jumpdword
)
6257 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6258 output_interseg_jump ();
6261 /* Output normal instructions here. */
6265 unsigned int prefix
;
6267 /* Since the VEX prefix contains the implicit prefix, we don't
6268 need the explicit prefix. */
6269 if (!i
.tm
.opcode_modifier
.vex
)
6271 switch (i
.tm
.opcode_length
)
6274 if (i
.tm
.base_opcode
& 0xff000000)
6276 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6281 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6283 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6284 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6287 if (prefix
!= REPE_PREFIX_OPCODE
6288 || (i
.prefix
[REP_PREFIX
]
6289 != REPE_PREFIX_OPCODE
))
6290 add_prefix (prefix
);
6293 add_prefix (prefix
);
6302 /* The prefix bytes. */
6303 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6305 FRAG_APPEND_1_CHAR (*q
);
6309 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6314 /* REX byte is encoded in VEX prefix. */
6318 FRAG_APPEND_1_CHAR (*q
);
6321 /* There should be no other prefixes for instructions
6326 /* Now the VEX prefix. */
6327 p
= frag_more (i
.vex
.length
);
6328 for (j
= 0; j
< i
.vex
.length
; j
++)
6329 p
[j
] = i
.vex
.bytes
[j
];
6332 /* Now the opcode; be careful about word order here! */
6333 if (i
.tm
.opcode_length
== 1)
6335 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6339 switch (i
.tm
.opcode_length
)
6343 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6353 /* Put out high byte first: can't use md_number_to_chars! */
6354 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6355 *p
= i
.tm
.base_opcode
& 0xff;
6358 /* Now the modrm byte and sib byte (if present). */
6359 if (i
.tm
.opcode_modifier
.modrm
)
6361 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6364 /* If i.rm.regmem == ESP (4)
6365 && i.rm.mode != (Register mode)
6367 ==> need second modrm byte. */
6368 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6370 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6371 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6373 | i
.sib
.scale
<< 6));
6376 if (i
.disp_operands
)
6377 output_disp (insn_start_frag
, insn_start_off
);
6380 output_imm (insn_start_frag
, insn_start_off
);
6386 pi ("" /*line*/, &i
);
6388 #endif /* DEBUG386 */
6391 /* Return the size of the displacement operand N. */
6394 disp_size (unsigned int n
)
6397 if (i
.types
[n
].bitfield
.disp64
)
6399 else if (i
.types
[n
].bitfield
.disp8
)
6401 else if (i
.types
[n
].bitfield
.disp16
)
6406 /* Return the size of the immediate operand N. */
6409 imm_size (unsigned int n
)
6412 if (i
.types
[n
].bitfield
.imm64
)
6414 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6416 else if (i
.types
[n
].bitfield
.imm16
)
6422 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6427 for (n
= 0; n
< i
.operands
; n
++)
6429 if (operand_type_check (i
.types
[n
], disp
))
6431 if (i
.op
[n
].disps
->X_op
== O_constant
)
6433 int size
= disp_size (n
);
6436 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6438 p
= frag_more (size
);
6439 md_number_to_chars (p
, val
, size
);
6443 enum bfd_reloc_code_real reloc_type
;
6444 int size
= disp_size (n
);
6445 int sign
= i
.types
[n
].bitfield
.disp32s
;
6446 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6448 /* We can't have 8 bit displacement here. */
6449 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6451 /* The PC relative address is computed relative
6452 to the instruction boundary, so in case immediate
6453 fields follows, we need to adjust the value. */
6454 if (pcrel
&& i
.imm_operands
)
6459 for (n1
= 0; n1
< i
.operands
; n1
++)
6460 if (operand_type_check (i
.types
[n1
], imm
))
6462 /* Only one immediate is allowed for PC
6463 relative address. */
6464 gas_assert (sz
== 0);
6466 i
.op
[n
].disps
->X_add_number
-= sz
;
6468 /* We should find the immediate. */
6469 gas_assert (sz
!= 0);
6472 p
= frag_more (size
);
6473 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6475 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6476 && (((reloc_type
== BFD_RELOC_32
6477 || reloc_type
== BFD_RELOC_X86_64_32S
6478 || (reloc_type
== BFD_RELOC_64
6480 && (i
.op
[n
].disps
->X_op
== O_symbol
6481 || (i
.op
[n
].disps
->X_op
== O_add
6482 && ((symbol_get_value_expression
6483 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6485 || reloc_type
== BFD_RELOC_32_PCREL
))
6489 if (insn_start_frag
== frag_now
)
6490 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6495 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6496 for (fr
= insn_start_frag
->fr_next
;
6497 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6499 add
+= p
- frag_now
->fr_literal
;
6504 reloc_type
= BFD_RELOC_386_GOTPC
;
6505 i
.op
[n
].imms
->X_add_number
+= add
;
6507 else if (reloc_type
== BFD_RELOC_64
)
6508 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6510 /* Don't do the adjustment for x86-64, as there
6511 the pcrel addressing is relative to the _next_
6512 insn, and that is taken care of in other code. */
6513 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6515 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6516 i
.op
[n
].disps
, pcrel
, reloc_type
);
6523 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6528 for (n
= 0; n
< i
.operands
; n
++)
6530 if (operand_type_check (i
.types
[n
], imm
))
6532 if (i
.op
[n
].imms
->X_op
== O_constant
)
6534 int size
= imm_size (n
);
6537 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6539 p
= frag_more (size
);
6540 md_number_to_chars (p
, val
, size
);
6544 /* Not absolute_section.
6545 Need a 32-bit fixup (don't support 8bit
6546 non-absolute imms). Try to support other
6548 enum bfd_reloc_code_real reloc_type
;
6549 int size
= imm_size (n
);
6552 if (i
.types
[n
].bitfield
.imm32s
6553 && (i
.suffix
== QWORD_MNEM_SUFFIX
6554 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6559 p
= frag_more (size
);
6560 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6562 /* This is tough to explain. We end up with this one if we
6563 * have operands that look like
6564 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6565 * obtain the absolute address of the GOT, and it is strongly
6566 * preferable from a performance point of view to avoid using
6567 * a runtime relocation for this. The actual sequence of
6568 * instructions often look something like:
6573 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6575 * The call and pop essentially return the absolute address
6576 * of the label .L66 and store it in %ebx. The linker itself
6577 * will ultimately change the first operand of the addl so
6578 * that %ebx points to the GOT, but to keep things simple, the
6579 * .o file must have this operand set so that it generates not
6580 * the absolute address of .L66, but the absolute address of
6581 * itself. This allows the linker itself simply treat a GOTPC
6582 * relocation as asking for a pcrel offset to the GOT to be
6583 * added in, and the addend of the relocation is stored in the
6584 * operand field for the instruction itself.
6586 * Our job here is to fix the operand so that it would add
6587 * the correct offset so that %ebx would point to itself. The
6588 * thing that is tricky is that .-.L66 will point to the
6589 * beginning of the instruction, so we need to further modify
6590 * the operand so that it will point to itself. There are
6591 * other cases where you have something like:
6593 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6595 * and here no correction would be required. Internally in
6596 * the assembler we treat operands of this form as not being
6597 * pcrel since the '.' is explicitly mentioned, and I wonder
6598 * whether it would simplify matters to do it this way. Who
6599 * knows. In earlier versions of the PIC patches, the
6600 * pcrel_adjust field was used to store the correction, but
6601 * since the expression is not pcrel, I felt it would be
6602 * confusing to do it this way. */
6604 if ((reloc_type
== BFD_RELOC_32
6605 || reloc_type
== BFD_RELOC_X86_64_32S
6606 || reloc_type
== BFD_RELOC_64
)
6608 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6609 && (i
.op
[n
].imms
->X_op
== O_symbol
6610 || (i
.op
[n
].imms
->X_op
== O_add
6611 && ((symbol_get_value_expression
6612 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6617 if (insn_start_frag
== frag_now
)
6618 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6623 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6624 for (fr
= insn_start_frag
->fr_next
;
6625 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6627 add
+= p
- frag_now
->fr_literal
;
6631 reloc_type
= BFD_RELOC_386_GOTPC
;
6633 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6635 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6636 i
.op
[n
].imms
->X_add_number
+= add
;
6638 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6639 i
.op
[n
].imms
, 0, reloc_type
);
6645 /* x86_cons_fix_new is called via the expression parsing code when a
6646 reloc is needed. We use this hook to get the correct .got reloc. */
6647 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6648 static int cons_sign
= -1;
6651 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6654 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6656 got_reloc
= NO_RELOC
;
6659 if (exp
->X_op
== O_secrel
)
6661 exp
->X_op
= O_symbol
;
6662 r
= BFD_RELOC_32_SECREL
;
6666 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6669 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
6670 purpose of the `.dc.a' internal pseudo-op. */
6673 x86_address_bytes (void)
6675 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
6677 return stdoutput
->arch_info
->bits_per_address
/ 8;
6680 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6682 # define lex_got(reloc, adjust, types) NULL
6684 /* Parse operands of the form
6685 <symbol>@GOTOFF+<nnn>
6686 and similar .plt or .got references.
6688 If we find one, set up the correct relocation in RELOC and copy the
6689 input string, minus the `@GOTOFF' into a malloc'd buffer for
6690 parsing by the calling routine. Return this buffer, and if ADJUST
6691 is non-null set it to the length of the string we removed from the
6692 input line. Otherwise return NULL. */
6694 lex_got (enum bfd_reloc_code_real
*rel
,
6696 i386_operand_type
*types
)
6698 /* Some of the relocations depend on the size of what field is to
6699 be relocated. But in our callers i386_immediate and i386_displacement
6700 we don't yet know the operand size (this will be set by insn
6701 matching). Hence we record the word32 relocation here,
6702 and adjust the reloc according to the real size in reloc(). */
6703 static const struct {
6706 const enum bfd_reloc_code_real rel
[2];
6707 const i386_operand_type types64
;
6709 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6710 BFD_RELOC_X86_64_PLTOFF64
},
6711 OPERAND_TYPE_IMM64
},
6712 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6713 BFD_RELOC_X86_64_PLT32
},
6714 OPERAND_TYPE_IMM32_32S_DISP32
},
6715 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6716 BFD_RELOC_X86_64_GOTPLT64
},
6717 OPERAND_TYPE_IMM64_DISP64
},
6718 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6719 BFD_RELOC_X86_64_GOTOFF64
},
6720 OPERAND_TYPE_IMM64_DISP64
},
6721 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6722 BFD_RELOC_X86_64_GOTPCREL
},
6723 OPERAND_TYPE_IMM32_32S_DISP32
},
6724 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6725 BFD_RELOC_X86_64_TLSGD
},
6726 OPERAND_TYPE_IMM32_32S_DISP32
},
6727 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6728 _dummy_first_bfd_reloc_code_real
},
6729 OPERAND_TYPE_NONE
},
6730 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6731 BFD_RELOC_X86_64_TLSLD
},
6732 OPERAND_TYPE_IMM32_32S_DISP32
},
6733 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6734 BFD_RELOC_X86_64_GOTTPOFF
},
6735 OPERAND_TYPE_IMM32_32S_DISP32
},
6736 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6737 BFD_RELOC_X86_64_TPOFF32
},
6738 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6739 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6740 _dummy_first_bfd_reloc_code_real
},
6741 OPERAND_TYPE_NONE
},
6742 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6743 BFD_RELOC_X86_64_DTPOFF32
},
6744 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6745 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6746 _dummy_first_bfd_reloc_code_real
},
6747 OPERAND_TYPE_NONE
},
6748 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6749 _dummy_first_bfd_reloc_code_real
},
6750 OPERAND_TYPE_NONE
},
6751 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6752 BFD_RELOC_X86_64_GOT32
},
6753 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6754 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6755 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6756 OPERAND_TYPE_IMM32_32S_DISP32
},
6757 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6758 BFD_RELOC_X86_64_TLSDESC_CALL
},
6759 OPERAND_TYPE_IMM32_32S_DISP32
},
6764 #if defined (OBJ_MAYBE_ELF)
6769 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6770 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6773 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6775 int len
= gotrel
[j
].len
;
6776 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6778 if (gotrel
[j
].rel
[object_64bit
] != 0)
6781 char *tmpbuf
, *past_reloc
;
6783 *rel
= gotrel
[j
].rel
[object_64bit
];
6789 if (flag_code
!= CODE_64BIT
)
6791 types
->bitfield
.imm32
= 1;
6792 types
->bitfield
.disp32
= 1;
6795 *types
= gotrel
[j
].types64
;
6798 if (GOT_symbol
== NULL
)
6799 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6801 /* The length of the first part of our input line. */
6802 first
= cp
- input_line_pointer
;
6804 /* The second part goes from after the reloc token until
6805 (and including) an end_of_line char or comma. */
6806 past_reloc
= cp
+ 1 + len
;
6808 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6810 second
= cp
+ 1 - past_reloc
;
6812 /* Allocate and copy string. The trailing NUL shouldn't
6813 be necessary, but be safe. */
6814 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6815 memcpy (tmpbuf
, input_line_pointer
, first
);
6816 if (second
!= 0 && *past_reloc
!= ' ')
6817 /* Replace the relocation token with ' ', so that
6818 errors like foo@GOTOFF1 will be detected. */
6819 tmpbuf
[first
++] = ' ';
6820 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6821 tmpbuf
[first
+ second
] = '\0';
6825 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6826 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6831 /* Might be a symbol version string. Don't as_bad here. */
6840 /* Parse operands of the form
6841 <symbol>@SECREL32+<nnn>
6843 If we find one, set up the correct relocation in RELOC and copy the
6844 input string, minus the `@SECREL32' into a malloc'd buffer for
6845 parsing by the calling routine. Return this buffer, and if ADJUST
6846 is non-null set it to the length of the string we removed from the
6847 input line. Otherwise return NULL.
6849 This function is copied from the ELF version above adjusted for PE targets. */
6852 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
6853 int *adjust ATTRIBUTE_UNUSED
,
6854 i386_operand_type
*types ATTRIBUTE_UNUSED
)
6860 const enum bfd_reloc_code_real rel
[2];
6861 const i386_operand_type types64
;
6865 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
6866 BFD_RELOC_32_SECREL
},
6867 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6873 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6874 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6877 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6879 int len
= gotrel
[j
].len
;
6881 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6883 if (gotrel
[j
].rel
[object_64bit
] != 0)
6886 char *tmpbuf
, *past_reloc
;
6888 *rel
= gotrel
[j
].rel
[object_64bit
];
6894 if (flag_code
!= CODE_64BIT
)
6896 types
->bitfield
.imm32
= 1;
6897 types
->bitfield
.disp32
= 1;
6900 *types
= gotrel
[j
].types64
;
6903 /* The length of the first part of our input line. */
6904 first
= cp
- input_line_pointer
;
6906 /* The second part goes from after the reloc token until
6907 (and including) an end_of_line char or comma. */
6908 past_reloc
= cp
+ 1 + len
;
6910 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6912 second
= cp
+ 1 - past_reloc
;
6914 /* Allocate and copy string. The trailing NUL shouldn't
6915 be necessary, but be safe. */
6916 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6917 memcpy (tmpbuf
, input_line_pointer
, first
);
6918 if (second
!= 0 && *past_reloc
!= ' ')
6919 /* Replace the relocation token with ' ', so that
6920 errors like foo@SECLREL321 will be detected. */
6921 tmpbuf
[first
++] = ' ';
6922 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6923 tmpbuf
[first
+ second
] = '\0';
6927 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6928 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6933 /* Might be a symbol version string. Don't as_bad here. */
6940 x86_cons (expressionS
*exp
, int size
)
6942 intel_syntax
= -intel_syntax
;
6945 if (size
== 4 || (object_64bit
&& size
== 8))
6947 /* Handle @GOTOFF and the like in an expression. */
6949 char *gotfree_input_line
;
6952 save
= input_line_pointer
;
6953 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6954 if (gotfree_input_line
)
6955 input_line_pointer
= gotfree_input_line
;
6959 if (gotfree_input_line
)
6961 /* expression () has merrily parsed up to the end of line,
6962 or a comma - in the wrong buffer. Transfer how far
6963 input_line_pointer has moved to the right buffer. */
6964 input_line_pointer
= (save
6965 + (input_line_pointer
- gotfree_input_line
)
6967 free (gotfree_input_line
);
6968 if (exp
->X_op
== O_constant
6969 || exp
->X_op
== O_absent
6970 || exp
->X_op
== O_illegal
6971 || exp
->X_op
== O_register
6972 || exp
->X_op
== O_big
)
6974 char c
= *input_line_pointer
;
6975 *input_line_pointer
= 0;
6976 as_bad (_("missing or invalid expression `%s'"), save
);
6977 *input_line_pointer
= c
;
6984 intel_syntax
= -intel_syntax
;
6987 i386_intel_simplify (exp
);
6991 signed_cons (int size
)
6993 if (flag_code
== CODE_64BIT
)
7001 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7008 if (exp
.X_op
== O_symbol
)
7009 exp
.X_op
= O_secrel
;
7011 emit_expr (&exp
, 4);
7013 while (*input_line_pointer
++ == ',');
7015 input_line_pointer
--;
7016 demand_empty_rest_of_line ();
7021 i386_immediate (char *imm_start
)
7023 char *save_input_line_pointer
;
7024 char *gotfree_input_line
;
7027 i386_operand_type types
;
7029 operand_type_set (&types
, ~0);
7031 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7033 as_bad (_("at most %d immediate operands are allowed"),
7034 MAX_IMMEDIATE_OPERANDS
);
7038 exp
= &im_expressions
[i
.imm_operands
++];
7039 i
.op
[this_operand
].imms
= exp
;
7041 if (is_space_char (*imm_start
))
7044 save_input_line_pointer
= input_line_pointer
;
7045 input_line_pointer
= imm_start
;
7047 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7048 if (gotfree_input_line
)
7049 input_line_pointer
= gotfree_input_line
;
7051 exp_seg
= expression (exp
);
7054 if (*input_line_pointer
)
7055 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7057 input_line_pointer
= save_input_line_pointer
;
7058 if (gotfree_input_line
)
7060 free (gotfree_input_line
);
7062 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7063 exp
->X_op
= O_illegal
;
7066 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7070 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7071 i386_operand_type types
, const char *imm_start
)
7073 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7076 as_bad (_("missing or invalid immediate expression `%s'"),
7080 else if (exp
->X_op
== O_constant
)
7082 /* Size it properly later. */
7083 i
.types
[this_operand
].bitfield
.imm64
= 1;
7084 /* If not 64bit, sign extend val. */
7085 if (flag_code
!= CODE_64BIT
7086 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7088 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7090 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7091 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7092 && exp_seg
!= absolute_section
7093 && exp_seg
!= text_section
7094 && exp_seg
!= data_section
7095 && exp_seg
!= bss_section
7096 && exp_seg
!= undefined_section
7097 && !bfd_is_com_section (exp_seg
))
7099 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7103 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7106 as_bad (_("illegal immediate register operand %s"), imm_start
);
7111 /* This is an address. The size of the address will be
7112 determined later, depending on destination register,
7113 suffix, or the default for the section. */
7114 i
.types
[this_operand
].bitfield
.imm8
= 1;
7115 i
.types
[this_operand
].bitfield
.imm16
= 1;
7116 i
.types
[this_operand
].bitfield
.imm32
= 1;
7117 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7118 i
.types
[this_operand
].bitfield
.imm64
= 1;
7119 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7127 i386_scale (char *scale
)
7130 char *save
= input_line_pointer
;
7132 input_line_pointer
= scale
;
7133 val
= get_absolute_expression ();
7138 i
.log2_scale_factor
= 0;
7141 i
.log2_scale_factor
= 1;
7144 i
.log2_scale_factor
= 2;
7147 i
.log2_scale_factor
= 3;
7151 char sep
= *input_line_pointer
;
7153 *input_line_pointer
= '\0';
7154 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7156 *input_line_pointer
= sep
;
7157 input_line_pointer
= save
;
7161 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
7163 as_warn (_("scale factor of %d without an index register"),
7164 1 << i
.log2_scale_factor
);
7165 i
.log2_scale_factor
= 0;
7167 scale
= input_line_pointer
;
7168 input_line_pointer
= save
;
7173 i386_displacement (char *disp_start
, char *disp_end
)
7177 char *save_input_line_pointer
;
7178 char *gotfree_input_line
;
7180 i386_operand_type bigdisp
, types
= anydisp
;
7183 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
7185 as_bad (_("at most %d displacement operands are allowed"),
7186 MAX_MEMORY_OPERANDS
);
7190 operand_type_set (&bigdisp
, 0);
7191 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
7192 || (!current_templates
->start
->opcode_modifier
.jump
7193 && !current_templates
->start
->opcode_modifier
.jumpdword
))
7195 bigdisp
.bitfield
.disp32
= 1;
7196 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7197 if (flag_code
== CODE_64BIT
)
7201 bigdisp
.bitfield
.disp32s
= 1;
7202 bigdisp
.bitfield
.disp64
= 1;
7205 else if ((flag_code
== CODE_16BIT
) ^ override
)
7207 bigdisp
.bitfield
.disp32
= 0;
7208 bigdisp
.bitfield
.disp16
= 1;
7213 /* For PC-relative branches, the width of the displacement
7214 is dependent upon data size, not address size. */
7215 override
= (i
.prefix
[DATA_PREFIX
] != 0);
7216 if (flag_code
== CODE_64BIT
)
7218 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
7219 bigdisp
.bitfield
.disp16
= 1;
7222 bigdisp
.bitfield
.disp32
= 1;
7223 bigdisp
.bitfield
.disp32s
= 1;
7229 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
7231 : LONG_MNEM_SUFFIX
));
7232 bigdisp
.bitfield
.disp32
= 1;
7233 if ((flag_code
== CODE_16BIT
) ^ override
)
7235 bigdisp
.bitfield
.disp32
= 0;
7236 bigdisp
.bitfield
.disp16
= 1;
7240 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7243 exp
= &disp_expressions
[i
.disp_operands
];
7244 i
.op
[this_operand
].disps
= exp
;
7246 save_input_line_pointer
= input_line_pointer
;
7247 input_line_pointer
= disp_start
;
7248 END_STRING_AND_SAVE (disp_end
);
7250 #ifndef GCC_ASM_O_HACK
7251 #define GCC_ASM_O_HACK 0
7254 END_STRING_AND_SAVE (disp_end
+ 1);
7255 if (i
.types
[this_operand
].bitfield
.baseIndex
7256 && displacement_string_end
[-1] == '+')
7258 /* This hack is to avoid a warning when using the "o"
7259 constraint within gcc asm statements.
7262 #define _set_tssldt_desc(n,addr,limit,type) \
7263 __asm__ __volatile__ ( \
7265 "movw %w1,2+%0\n\t" \
7267 "movb %b1,4+%0\n\t" \
7268 "movb %4,5+%0\n\t" \
7269 "movb $0,6+%0\n\t" \
7270 "movb %h1,7+%0\n\t" \
7272 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7274 This works great except that the output assembler ends
7275 up looking a bit weird if it turns out that there is
7276 no offset. You end up producing code that looks like:
7289 So here we provide the missing zero. */
7291 *displacement_string_end
= '0';
7294 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7295 if (gotfree_input_line
)
7296 input_line_pointer
= gotfree_input_line
;
7298 exp_seg
= expression (exp
);
7301 if (*input_line_pointer
)
7302 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7304 RESTORE_END_STRING (disp_end
+ 1);
7306 input_line_pointer
= save_input_line_pointer
;
7307 if (gotfree_input_line
)
7309 free (gotfree_input_line
);
7311 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7312 exp
->X_op
= O_illegal
;
7315 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
7317 RESTORE_END_STRING (disp_end
);
7323 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7324 i386_operand_type types
, const char *disp_start
)
7326 i386_operand_type bigdisp
;
7329 /* We do this to make sure that the section symbol is in
7330 the symbol table. We will ultimately change the relocation
7331 to be relative to the beginning of the section. */
7332 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
7333 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
7334 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7336 if (exp
->X_op
!= O_symbol
)
7339 if (S_IS_LOCAL (exp
->X_add_symbol
)
7340 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
7341 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
7342 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
7343 exp
->X_op
= O_subtract
;
7344 exp
->X_op_symbol
= GOT_symbol
;
7345 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
7346 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
7347 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7348 i
.reloc
[this_operand
] = BFD_RELOC_64
;
7350 i
.reloc
[this_operand
] = BFD_RELOC_32
;
7353 else if (exp
->X_op
== O_absent
7354 || exp
->X_op
== O_illegal
7355 || exp
->X_op
== O_big
)
7358 as_bad (_("missing or invalid displacement expression `%s'"),
7363 else if (flag_code
== CODE_64BIT
7364 && !i
.prefix
[ADDR_PREFIX
]
7365 && exp
->X_op
== O_constant
)
7367 /* Since displacement is signed extended to 64bit, don't allow
7368 disp32 and turn off disp32s if they are out of range. */
7369 i
.types
[this_operand
].bitfield
.disp32
= 0;
7370 if (!fits_in_signed_long (exp
->X_add_number
))
7372 i
.types
[this_operand
].bitfield
.disp32s
= 0;
7373 if (i
.types
[this_operand
].bitfield
.baseindex
)
7375 as_bad (_("0x%lx out range of signed 32bit displacement"),
7376 (long) exp
->X_add_number
);
7382 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7383 else if (exp
->X_op
!= O_constant
7384 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
7385 && exp_seg
!= absolute_section
7386 && exp_seg
!= text_section
7387 && exp_seg
!= data_section
7388 && exp_seg
!= bss_section
7389 && exp_seg
!= undefined_section
7390 && !bfd_is_com_section (exp_seg
))
7392 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7397 /* Check if this is a displacement only operand. */
7398 bigdisp
= i
.types
[this_operand
];
7399 bigdisp
.bitfield
.disp8
= 0;
7400 bigdisp
.bitfield
.disp16
= 0;
7401 bigdisp
.bitfield
.disp32
= 0;
7402 bigdisp
.bitfield
.disp32s
= 0;
7403 bigdisp
.bitfield
.disp64
= 0;
7404 if (operand_type_all_zero (&bigdisp
))
7405 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7411 /* Make sure the memory operand we've been dealt is valid.
7412 Return 1 on success, 0 on a failure. */
7415 i386_index_check (const char *operand_string
)
7418 const char *kind
= "base/index";
7419 #if INFER_ADDR_PREFIX
7425 if (current_templates
->start
->opcode_modifier
.isstring
7426 && !current_templates
->start
->opcode_modifier
.immext
7427 && (current_templates
->end
[-1].opcode_modifier
.isstring
7430 /* Memory operands of string insns are special in that they only allow
7431 a single register (rDI, rSI, or rBX) as their memory address. */
7432 unsigned int expected
;
7434 kind
= "string address";
7436 if (current_templates
->start
->opcode_modifier
.w
)
7438 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
7440 if (!type
.bitfield
.baseindex
7441 || ((!i
.mem_operands
!= !intel_syntax
)
7442 && current_templates
->end
[-1].operand_types
[1]
7443 .bitfield
.baseindex
))
7444 type
= current_templates
->end
[-1].operand_types
[1];
7445 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
7448 expected
= 3 /* rBX */;
7450 if (!i
.base_reg
|| i
.index_reg
7451 || operand_type_check (i
.types
[this_operand
], disp
))
7453 else if (!(flag_code
== CODE_64BIT
7454 ? i
.prefix
[ADDR_PREFIX
]
7455 ? i
.base_reg
->reg_type
.bitfield
.reg32
7456 : i
.base_reg
->reg_type
.bitfield
.reg64
7457 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7458 ? i
.base_reg
->reg_type
.bitfield
.reg32
7459 : i
.base_reg
->reg_type
.bitfield
.reg16
))
7461 else if (register_number (i
.base_reg
) != expected
)
7468 for (j
= 0; j
< i386_regtab_size
; ++j
)
7469 if ((flag_code
== CODE_64BIT
7470 ? i
.prefix
[ADDR_PREFIX
]
7471 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7472 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7473 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7474 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7475 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7476 && register_number(i386_regtab
+ j
) == expected
)
7478 gas_assert (j
< i386_regtab_size
);
7479 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7481 intel_syntax
? '[' : '(',
7483 i386_regtab
[j
].reg_name
,
7484 intel_syntax
? ']' : ')');
7488 else if (flag_code
== CODE_64BIT
)
7491 && ((i
.prefix
[ADDR_PREFIX
] == 0
7492 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7493 || (i
.prefix
[ADDR_PREFIX
]
7494 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7496 || i
.base_reg
->reg_num
!=
7497 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7499 && !(i
.index_reg
->reg_type
.bitfield
.regxmm
7500 || i
.index_reg
->reg_type
.bitfield
.regymm
)
7501 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7502 || (i
.prefix
[ADDR_PREFIX
] == 0
7503 && i
.index_reg
->reg_num
!= RegRiz
7504 && !i
.index_reg
->reg_type
.bitfield
.reg64
7506 || (i
.prefix
[ADDR_PREFIX
]
7507 && i
.index_reg
->reg_num
!= RegEiz
7508 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7513 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7517 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7518 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7520 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7521 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7523 && i
.base_reg
->reg_num
< 6
7524 && i
.index_reg
->reg_num
>= 6
7525 && i
.log2_scale_factor
== 0))))
7532 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7534 && !i
.index_reg
->reg_type
.bitfield
.regxmm
7535 && !i
.index_reg
->reg_type
.bitfield
.regymm
7536 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7537 && i
.index_reg
->reg_num
!= RegEiz
)
7538 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7544 #if INFER_ADDR_PREFIX
7545 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7547 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7549 /* Change the size of any displacement too. At most one of
7550 Disp16 or Disp32 is set.
7551 FIXME. There doesn't seem to be any real need for separate
7552 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7553 Removing them would probably clean up the code quite a lot. */
7554 if (flag_code
!= CODE_64BIT
7555 && (i
.types
[this_operand
].bitfield
.disp16
7556 || i
.types
[this_operand
].bitfield
.disp32
))
7557 i
.types
[this_operand
]
7558 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7563 as_bad (_("`%s' is not a valid %s expression"),
7568 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7570 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7571 ? flag_code
== CODE_32BIT
7580 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7584 i386_att_operand (char *operand_string
)
7588 char *op_string
= operand_string
;
7590 if (is_space_char (*op_string
))
7593 /* We check for an absolute prefix (differentiating,
7594 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7595 if (*op_string
== ABSOLUTE_PREFIX
)
7598 if (is_space_char (*op_string
))
7600 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7603 /* Check if operand is a register. */
7604 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7606 i386_operand_type temp
;
7608 /* Check for a segment override by searching for ':' after a
7609 segment register. */
7611 if (is_space_char (*op_string
))
7613 if (*op_string
== ':'
7614 && (r
->reg_type
.bitfield
.sreg2
7615 || r
->reg_type
.bitfield
.sreg3
))
7620 i
.seg
[i
.mem_operands
] = &es
;
7623 i
.seg
[i
.mem_operands
] = &cs
;
7626 i
.seg
[i
.mem_operands
] = &ss
;
7629 i
.seg
[i
.mem_operands
] = &ds
;
7632 i
.seg
[i
.mem_operands
] = &fs
;
7635 i
.seg
[i
.mem_operands
] = &gs
;
7639 /* Skip the ':' and whitespace. */
7641 if (is_space_char (*op_string
))
7644 if (!is_digit_char (*op_string
)
7645 && !is_identifier_char (*op_string
)
7646 && *op_string
!= '('
7647 && *op_string
!= ABSOLUTE_PREFIX
)
7649 as_bad (_("bad memory operand `%s'"), op_string
);
7652 /* Handle case of %es:*foo. */
7653 if (*op_string
== ABSOLUTE_PREFIX
)
7656 if (is_space_char (*op_string
))
7658 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7660 goto do_memory_reference
;
7664 as_bad (_("junk `%s' after register"), op_string
);
7668 temp
.bitfield
.baseindex
= 0;
7669 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7671 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7672 i
.op
[this_operand
].regs
= r
;
7675 else if (*op_string
== REGISTER_PREFIX
)
7677 as_bad (_("bad register name `%s'"), op_string
);
7680 else if (*op_string
== IMMEDIATE_PREFIX
)
7683 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7685 as_bad (_("immediate operand illegal with absolute jump"));
7688 if (!i386_immediate (op_string
))
7691 else if (is_digit_char (*op_string
)
7692 || is_identifier_char (*op_string
)
7693 || *op_string
== '(')
7695 /* This is a memory reference of some sort. */
7698 /* Start and end of displacement string expression (if found). */
7699 char *displacement_string_start
;
7700 char *displacement_string_end
;
7702 do_memory_reference
:
7703 if ((i
.mem_operands
== 1
7704 && !current_templates
->start
->opcode_modifier
.isstring
)
7705 || i
.mem_operands
== 2)
7707 as_bad (_("too many memory references for `%s'"),
7708 current_templates
->start
->name
);
7712 /* Check for base index form. We detect the base index form by
7713 looking for an ')' at the end of the operand, searching
7714 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7716 base_string
= op_string
+ strlen (op_string
);
7719 if (is_space_char (*base_string
))
7722 /* If we only have a displacement, set-up for it to be parsed later. */
7723 displacement_string_start
= op_string
;
7724 displacement_string_end
= base_string
+ 1;
7726 if (*base_string
== ')')
7729 unsigned int parens_balanced
= 1;
7730 /* We've already checked that the number of left & right ()'s are
7731 equal, so this loop will not be infinite. */
7735 if (*base_string
== ')')
7737 if (*base_string
== '(')
7740 while (parens_balanced
);
7742 temp_string
= base_string
;
7744 /* Skip past '(' and whitespace. */
7746 if (is_space_char (*base_string
))
7749 if (*base_string
== ','
7750 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7753 displacement_string_end
= temp_string
;
7755 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7759 base_string
= end_op
;
7760 if (is_space_char (*base_string
))
7764 /* There may be an index reg or scale factor here. */
7765 if (*base_string
== ',')
7768 if (is_space_char (*base_string
))
7771 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7774 base_string
= end_op
;
7775 if (is_space_char (*base_string
))
7777 if (*base_string
== ',')
7780 if (is_space_char (*base_string
))
7783 else if (*base_string
!= ')')
7785 as_bad (_("expecting `,' or `)' "
7786 "after index register in `%s'"),
7791 else if (*base_string
== REGISTER_PREFIX
)
7793 end_op
= strchr (base_string
, ',');
7796 as_bad (_("bad register name `%s'"), base_string
);
7800 /* Check for scale factor. */
7801 if (*base_string
!= ')')
7803 char *end_scale
= i386_scale (base_string
);
7808 base_string
= end_scale
;
7809 if (is_space_char (*base_string
))
7811 if (*base_string
!= ')')
7813 as_bad (_("expecting `)' "
7814 "after scale factor in `%s'"),
7819 else if (!i
.index_reg
)
7821 as_bad (_("expecting index register or scale factor "
7822 "after `,'; got '%c'"),
7827 else if (*base_string
!= ')')
7829 as_bad (_("expecting `,' or `)' "
7830 "after base register in `%s'"),
7835 else if (*base_string
== REGISTER_PREFIX
)
7837 end_op
= strchr (base_string
, ',');
7840 as_bad (_("bad register name `%s'"), base_string
);
7845 /* If there's an expression beginning the operand, parse it,
7846 assuming displacement_string_start and
7847 displacement_string_end are meaningful. */
7848 if (displacement_string_start
!= displacement_string_end
)
7850 if (!i386_displacement (displacement_string_start
,
7851 displacement_string_end
))
7855 /* Special case for (%dx) while doing input/output op. */
7857 && operand_type_equal (&i
.base_reg
->reg_type
,
7858 ®16_inoutportreg
)
7860 && i
.log2_scale_factor
== 0
7861 && i
.seg
[i
.mem_operands
] == 0
7862 && !operand_type_check (i
.types
[this_operand
], disp
))
7864 i
.types
[this_operand
] = inoutportreg
;
7868 if (i386_index_check (operand_string
) == 0)
7870 i
.types
[this_operand
].bitfield
.mem
= 1;
7875 /* It's not a memory operand; argh! */
7876 as_bad (_("invalid char %s beginning operand %d `%s'"),
7877 output_invalid (*op_string
),
7882 return 1; /* Normal return. */
7885 /* Calculate the maximum variable size (i.e., excluding fr_fix)
7886 that an rs_machine_dependent frag may reach. */
7889 i386_frag_max_var (fragS
*frag
)
7891 /* The only relaxable frags are for jumps.
7892 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
7893 gas_assert (frag
->fr_type
== rs_machine_dependent
);
7894 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
7897 /* md_estimate_size_before_relax()
7899 Called just before relax() for rs_machine_dependent frags. The x86
7900 assembler uses these frags to handle variable size jump
7903 Any symbol that is now undefined will not become defined.
7904 Return the correct fr_subtype in the frag.
7905 Return the initial "guess for variable size of frag" to caller.
7906 The guess is actually the growth beyond the fixed part. Whatever
7907 we do to grow the fixed or variable part contributes to our
7911 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
7913 /* We've already got fragP->fr_subtype right; all we have to do is
7914 check for un-relaxable symbols. On an ELF system, we can't relax
7915 an externally visible symbol, because it may be overridden by a
7917 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7918 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7920 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7921 || S_IS_WEAK (fragP
->fr_symbol
)
7922 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7923 & BSF_GNU_INDIRECT_FUNCTION
))))
7925 #if defined (OBJ_COFF) && defined (TE_PE)
7926 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7927 && S_IS_WEAK (fragP
->fr_symbol
))
7931 /* Symbol is undefined in this segment, or we need to keep a
7932 reloc so that weak symbols can be overridden. */
7933 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7934 enum bfd_reloc_code_real reloc_type
;
7935 unsigned char *opcode
;
7938 if (fragP
->fr_var
!= NO_RELOC
)
7939 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7941 reloc_type
= BFD_RELOC_16_PCREL
;
7943 reloc_type
= BFD_RELOC_32_PCREL
;
7945 old_fr_fix
= fragP
->fr_fix
;
7946 opcode
= (unsigned char *) fragP
->fr_opcode
;
7948 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7951 /* Make jmp (0xeb) a (d)word displacement jump. */
7953 fragP
->fr_fix
+= size
;
7954 fix_new (fragP
, old_fr_fix
, size
,
7956 fragP
->fr_offset
, 1,
7962 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7964 /* Negate the condition, and branch past an
7965 unconditional jump. */
7968 /* Insert an unconditional jump. */
7970 /* We added two extra opcode bytes, and have a two byte
7972 fragP
->fr_fix
+= 2 + 2;
7973 fix_new (fragP
, old_fr_fix
+ 2, 2,
7975 fragP
->fr_offset
, 1,
7982 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7987 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7989 fragP
->fr_offset
, 1,
7991 fixP
->fx_signed
= 1;
7995 /* This changes the byte-displacement jump 0x7N
7996 to the (d)word-displacement jump 0x0f,0x8N. */
7997 opcode
[1] = opcode
[0] + 0x10;
7998 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7999 /* We've added an opcode byte. */
8000 fragP
->fr_fix
+= 1 + size
;
8001 fix_new (fragP
, old_fr_fix
+ 1, size
,
8003 fragP
->fr_offset
, 1,
8008 BAD_CASE (fragP
->fr_subtype
);
8012 return fragP
->fr_fix
- old_fr_fix
;
8015 /* Guess size depending on current relax state. Initially the relax
8016 state will correspond to a short jump and we return 1, because
8017 the variable part of the frag (the branch offset) is one byte
8018 long. However, we can relax a section more than once and in that
8019 case we must either set fr_subtype back to the unrelaxed state,
8020 or return the value for the appropriate branch. */
8021 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8024 /* Called after relax() is finished.
8026 In: Address of frag.
8027 fr_type == rs_machine_dependent.
8028 fr_subtype is what the address relaxed to.
8030 Out: Any fixSs and constants are set up.
8031 Caller will turn frag into a ".space 0". */
8034 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8037 unsigned char *opcode
;
8038 unsigned char *where_to_put_displacement
= NULL
;
8039 offsetT target_address
;
8040 offsetT opcode_address
;
8041 unsigned int extension
= 0;
8042 offsetT displacement_from_opcode_start
;
8044 opcode
= (unsigned char *) fragP
->fr_opcode
;
8046 /* Address we want to reach in file space. */
8047 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8049 /* Address opcode resides at in file space. */
8050 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8052 /* Displacement from opcode start to fill into instruction. */
8053 displacement_from_opcode_start
= target_address
- opcode_address
;
8055 if ((fragP
->fr_subtype
& BIG
) == 0)
8057 /* Don't have to change opcode. */
8058 extension
= 1; /* 1 opcode + 1 displacement */
8059 where_to_put_displacement
= &opcode
[1];
8063 if (no_cond_jump_promotion
8064 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8065 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8066 _("long jump required"));
8068 switch (fragP
->fr_subtype
)
8070 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
8071 extension
= 4; /* 1 opcode + 4 displacement */
8073 where_to_put_displacement
= &opcode
[1];
8076 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
8077 extension
= 2; /* 1 opcode + 2 displacement */
8079 where_to_put_displacement
= &opcode
[1];
8082 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
8083 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
8084 extension
= 5; /* 2 opcode + 4 displacement */
8085 opcode
[1] = opcode
[0] + 0x10;
8086 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8087 where_to_put_displacement
= &opcode
[2];
8090 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
8091 extension
= 3; /* 2 opcode + 2 displacement */
8092 opcode
[1] = opcode
[0] + 0x10;
8093 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8094 where_to_put_displacement
= &opcode
[2];
8097 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
8102 where_to_put_displacement
= &opcode
[3];
8106 BAD_CASE (fragP
->fr_subtype
);
8111 /* If size if less then four we are sure that the operand fits,
8112 but if it's 4, then it could be that the displacement is larger
8114 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
8116 && ((addressT
) (displacement_from_opcode_start
- extension
8117 + ((addressT
) 1 << 31))
8118 > (((addressT
) 2 << 31) - 1)))
8120 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
8121 _("jump target out of range"));
8122 /* Make us emit 0. */
8123 displacement_from_opcode_start
= extension
;
8125 /* Now put displacement after opcode. */
8126 md_number_to_chars ((char *) where_to_put_displacement
,
8127 (valueT
) (displacement_from_opcode_start
- extension
),
8128 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
8129 fragP
->fr_fix
+= extension
;
8132 /* Apply a fixup (fixP) to segment data, once it has been determined
8133 by our caller that we have all the info we need to fix it up.
8135 Parameter valP is the pointer to the value of the bits.
8137 On the 386, immediates, displacements, and data pointers are all in
8138 the same (little-endian) format, so we don't need to care about which
8142 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
8144 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8145 valueT value
= *valP
;
8147 #if !defined (TE_Mach)
8150 switch (fixP
->fx_r_type
)
8156 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
8159 case BFD_RELOC_X86_64_32S
:
8160 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
8163 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
8166 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
8171 if (fixP
->fx_addsy
!= NULL
8172 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
8173 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
8174 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
8175 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
8176 && !use_rela_relocations
)
8178 /* This is a hack. There should be a better way to handle this.
8179 This covers for the fact that bfd_install_relocation will
8180 subtract the current location (for partial_inplace, PC relative
8181 relocations); see more below. */
8185 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
8188 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8193 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
8196 || (symbol_section_p (fixP
->fx_addsy
)
8197 && sym_seg
!= absolute_section
))
8198 && !generic_force_reloc (fixP
))
8200 /* Yes, we add the values in twice. This is because
8201 bfd_install_relocation subtracts them out again. I think
8202 bfd_install_relocation is broken, but I don't dare change
8204 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8208 #if defined (OBJ_COFF) && defined (TE_PE)
8209 /* For some reason, the PE format does not store a
8210 section address offset for a PC relative symbol. */
8211 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
8212 || S_IS_WEAK (fixP
->fx_addsy
))
8213 value
+= md_pcrel_from (fixP
);
8216 #if defined (OBJ_COFF) && defined (TE_PE)
8217 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8219 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8223 /* Fix a few things - the dynamic linker expects certain values here,
8224 and we must not disappoint it. */
8225 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8226 if (IS_ELF
&& fixP
->fx_addsy
)
8227 switch (fixP
->fx_r_type
)
8229 case BFD_RELOC_386_PLT32
:
8230 case BFD_RELOC_X86_64_PLT32
:
8231 /* Make the jump instruction point to the address of the operand. At
8232 runtime we merely add the offset to the actual PLT entry. */
8236 case BFD_RELOC_386_TLS_GD
:
8237 case BFD_RELOC_386_TLS_LDM
:
8238 case BFD_RELOC_386_TLS_IE_32
:
8239 case BFD_RELOC_386_TLS_IE
:
8240 case BFD_RELOC_386_TLS_GOTIE
:
8241 case BFD_RELOC_386_TLS_GOTDESC
:
8242 case BFD_RELOC_X86_64_TLSGD
:
8243 case BFD_RELOC_X86_64_TLSLD
:
8244 case BFD_RELOC_X86_64_GOTTPOFF
:
8245 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8246 value
= 0; /* Fully resolved at runtime. No addend. */
8248 case BFD_RELOC_386_TLS_LE
:
8249 case BFD_RELOC_386_TLS_LDO_32
:
8250 case BFD_RELOC_386_TLS_LE_32
:
8251 case BFD_RELOC_X86_64_DTPOFF32
:
8252 case BFD_RELOC_X86_64_DTPOFF64
:
8253 case BFD_RELOC_X86_64_TPOFF32
:
8254 case BFD_RELOC_X86_64_TPOFF64
:
8255 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8258 case BFD_RELOC_386_TLS_DESC_CALL
:
8259 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8260 value
= 0; /* Fully resolved at runtime. No addend. */
8261 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8265 case BFD_RELOC_386_GOT32
:
8266 case BFD_RELOC_X86_64_GOT32
:
8267 value
= 0; /* Fully resolved at runtime. No addend. */
8270 case BFD_RELOC_VTABLE_INHERIT
:
8271 case BFD_RELOC_VTABLE_ENTRY
:
8278 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
8280 #endif /* !defined (TE_Mach) */
8282 /* Are we finished with this relocation now? */
8283 if (fixP
->fx_addsy
== NULL
)
8285 #if defined (OBJ_COFF) && defined (TE_PE)
8286 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8289 /* Remember value for tc_gen_reloc. */
8290 fixP
->fx_addnumber
= value
;
8291 /* Clear out the frag for now. */
8295 else if (use_rela_relocations
)
8297 fixP
->fx_no_overflow
= 1;
8298 /* Remember value for tc_gen_reloc. */
8299 fixP
->fx_addnumber
= value
;
8303 md_number_to_chars (p
, value
, fixP
->fx_size
);
8307 md_atof (int type
, char *litP
, int *sizeP
)
8309 /* This outputs the LITTLENUMs in REVERSE order;
8310 in accord with the bigendian 386. */
8311 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
8314 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
8317 output_invalid (int c
)
8320 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8323 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8324 "(0x%x)", (unsigned char) c
);
8325 return output_invalid_buf
;
8328 /* REG_STRING starts *before* REGISTER_PREFIX. */
8330 static const reg_entry
*
8331 parse_real_register (char *reg_string
, char **end_op
)
8333 char *s
= reg_string
;
8335 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
8338 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8339 if (*s
== REGISTER_PREFIX
)
8342 if (is_space_char (*s
))
8346 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
8348 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
8349 return (const reg_entry
*) NULL
;
8353 /* For naked regs, make sure that we are not dealing with an identifier.
8354 This prevents confusing an identifier like `eax_var' with register
8356 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
8357 return (const reg_entry
*) NULL
;
8361 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
8363 /* Handle floating point regs, allowing spaces in the (i) part. */
8364 if (r
== i386_regtab
/* %st is first entry of table */)
8366 if (is_space_char (*s
))
8371 if (is_space_char (*s
))
8373 if (*s
>= '0' && *s
<= '7')
8377 if (is_space_char (*s
))
8382 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
8387 /* We have "%st(" then garbage. */
8388 return (const reg_entry
*) NULL
;
8392 if (r
== NULL
|| allow_pseudo_reg
)
8395 if (operand_type_all_zero (&r
->reg_type
))
8396 return (const reg_entry
*) NULL
;
8398 if ((r
->reg_type
.bitfield
.reg32
8399 || r
->reg_type
.bitfield
.sreg3
8400 || r
->reg_type
.bitfield
.control
8401 || r
->reg_type
.bitfield
.debug
8402 || r
->reg_type
.bitfield
.test
)
8403 && !cpu_arch_flags
.bitfield
.cpui386
)
8404 return (const reg_entry
*) NULL
;
8406 if (r
->reg_type
.bitfield
.floatreg
8407 && !cpu_arch_flags
.bitfield
.cpu8087
8408 && !cpu_arch_flags
.bitfield
.cpu287
8409 && !cpu_arch_flags
.bitfield
.cpu387
)
8410 return (const reg_entry
*) NULL
;
8412 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
8413 return (const reg_entry
*) NULL
;
8415 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
8416 return (const reg_entry
*) NULL
;
8418 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
8419 return (const reg_entry
*) NULL
;
8421 /* Don't allow fake index register unless allow_index_reg isn't 0. */
8422 if (!allow_index_reg
8423 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
8424 return (const reg_entry
*) NULL
;
8426 if (((r
->reg_flags
& (RegRex64
| RegRex
))
8427 || r
->reg_type
.bitfield
.reg64
)
8428 && (!cpu_arch_flags
.bitfield
.cpulm
8429 || !operand_type_equal (&r
->reg_type
, &control
))
8430 && flag_code
!= CODE_64BIT
)
8431 return (const reg_entry
*) NULL
;
8433 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
8434 return (const reg_entry
*) NULL
;
8439 /* REG_STRING starts *before* REGISTER_PREFIX. */
8441 static const reg_entry
*
8442 parse_register (char *reg_string
, char **end_op
)
8446 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
8447 r
= parse_real_register (reg_string
, end_op
);
8452 char *save
= input_line_pointer
;
8456 input_line_pointer
= reg_string
;
8457 c
= get_symbol_end ();
8458 symbolP
= symbol_find (reg_string
);
8459 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
8461 const expressionS
*e
= symbol_get_value_expression (symbolP
);
8463 know (e
->X_op
== O_register
);
8464 know (e
->X_add_number
>= 0
8465 && (valueT
) e
->X_add_number
< i386_regtab_size
);
8466 r
= i386_regtab
+ e
->X_add_number
;
8467 *end_op
= input_line_pointer
;
8469 *input_line_pointer
= c
;
8470 input_line_pointer
= save
;
8476 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8479 char *end
= input_line_pointer
;
8482 r
= parse_register (name
, &input_line_pointer
);
8483 if (r
&& end
<= input_line_pointer
)
8485 *nextcharP
= *input_line_pointer
;
8486 *input_line_pointer
= 0;
8487 e
->X_op
= O_register
;
8488 e
->X_add_number
= r
- i386_regtab
;
8491 input_line_pointer
= end
;
8493 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8497 md_operand (expressionS
*e
)
8502 switch (*input_line_pointer
)
8504 case REGISTER_PREFIX
:
8505 r
= parse_real_register (input_line_pointer
, &end
);
8508 e
->X_op
= O_register
;
8509 e
->X_add_number
= r
- i386_regtab
;
8510 input_line_pointer
= end
;
8515 gas_assert (intel_syntax
);
8516 end
= input_line_pointer
++;
8518 if (*input_line_pointer
== ']')
8520 ++input_line_pointer
;
8521 e
->X_op_symbol
= make_expr_symbol (e
);
8522 e
->X_add_symbol
= NULL
;
8523 e
->X_add_number
= 0;
8529 input_line_pointer
= end
;
8536 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8537 const char *md_shortopts
= "kVQ:sqn";
8539 const char *md_shortopts
= "qn";
8542 #define OPTION_32 (OPTION_MD_BASE + 0)
8543 #define OPTION_64 (OPTION_MD_BASE + 1)
8544 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8545 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8546 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8547 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8548 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8549 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8550 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8551 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8552 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8553 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8554 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
8555 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
8556 #define OPTION_X32 (OPTION_MD_BASE + 14)
8558 struct option md_longopts
[] =
8560 {"32", no_argument
, NULL
, OPTION_32
},
8561 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8562 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8563 {"64", no_argument
, NULL
, OPTION_64
},
8565 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8566 {"x32", no_argument
, NULL
, OPTION_X32
},
8568 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8569 {"march", required_argument
, NULL
, OPTION_MARCH
},
8570 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8571 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8572 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8573 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8574 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8575 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8576 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8577 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8578 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
8579 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8580 {NULL
, no_argument
, NULL
, 0}
8582 size_t md_longopts_size
= sizeof (md_longopts
);
8585 md_parse_option (int c
, char *arg
)
8593 optimize_align_code
= 0;
8600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8601 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8602 should be emitted or not. FIXME: Not implemented. */
8606 /* -V: SVR4 argument to print version ID. */
8608 print_version_id ();
8611 /* -k: Ignore for FreeBSD compatibility. */
8616 /* -s: On i386 Solaris, this tells the native assembler to use
8617 .stab instead of .stab.excl. We always use .stab anyhow. */
8620 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8621 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8624 const char **list
, **l
;
8626 list
= bfd_target_list ();
8627 for (l
= list
; *l
!= NULL
; l
++)
8628 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8629 || strcmp (*l
, "coff-x86-64") == 0
8630 || strcmp (*l
, "pe-x86-64") == 0
8631 || strcmp (*l
, "pei-x86-64") == 0
8632 || strcmp (*l
, "mach-o-x86-64") == 0)
8634 default_arch
= "x86_64";
8638 as_fatal (_("no compiled in support for x86_64"));
8644 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8648 const char **list
, **l
;
8650 list
= bfd_target_list ();
8651 for (l
= list
; *l
!= NULL
; l
++)
8652 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
8654 default_arch
= "x86_64:32";
8658 as_fatal (_("no compiled in support for 32bit x86_64"));
8662 as_fatal (_("32bit x86_64 is only supported for ELF"));
8667 default_arch
= "i386";
8671 #ifdef SVR4_COMMENT_CHARS
8676 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8678 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8682 i386_comment_chars
= n
;
8688 arch
= xstrdup (arg
);
8692 as_fatal (_("invalid -march= option: `%s'"), arg
);
8693 next
= strchr (arch
, '+');
8696 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8698 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8701 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8704 cpu_arch_name
= cpu_arch
[j
].name
;
8705 cpu_sub_arch_name
= NULL
;
8706 cpu_arch_flags
= cpu_arch
[j
].flags
;
8707 cpu_arch_isa
= cpu_arch
[j
].type
;
8708 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8709 if (!cpu_arch_tune_set
)
8711 cpu_arch_tune
= cpu_arch_isa
;
8712 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8716 else if (*cpu_arch
[j
].name
== '.'
8717 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8719 /* ISA entension. */
8720 i386_cpu_flags flags
;
8722 if (!cpu_arch
[j
].negated
)
8723 flags
= cpu_flags_or (cpu_arch_flags
,
8726 flags
= cpu_flags_and_not (cpu_arch_flags
,
8728 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8730 if (cpu_sub_arch_name
)
8732 char *name
= cpu_sub_arch_name
;
8733 cpu_sub_arch_name
= concat (name
,
8735 (const char *) NULL
);
8739 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8740 cpu_arch_flags
= flags
;
8741 cpu_arch_isa_flags
= flags
;
8747 if (j
>= ARRAY_SIZE (cpu_arch
))
8748 as_fatal (_("invalid -march= option: `%s'"), arg
);
8752 while (next
!= NULL
);
8757 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8758 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8760 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8762 cpu_arch_tune_set
= 1;
8763 cpu_arch_tune
= cpu_arch
[j
].type
;
8764 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8768 if (j
>= ARRAY_SIZE (cpu_arch
))
8769 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8772 case OPTION_MMNEMONIC
:
8773 if (strcasecmp (arg
, "att") == 0)
8775 else if (strcasecmp (arg
, "intel") == 0)
8778 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
8781 case OPTION_MSYNTAX
:
8782 if (strcasecmp (arg
, "att") == 0)
8784 else if (strcasecmp (arg
, "intel") == 0)
8787 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
8790 case OPTION_MINDEX_REG
:
8791 allow_index_reg
= 1;
8794 case OPTION_MNAKED_REG
:
8795 allow_naked_reg
= 1;
8798 case OPTION_MOLD_GCC
:
8802 case OPTION_MSSE2AVX
:
8806 case OPTION_MSSE_CHECK
:
8807 if (strcasecmp (arg
, "error") == 0)
8808 sse_check
= check_error
;
8809 else if (strcasecmp (arg
, "warning") == 0)
8810 sse_check
= check_warning
;
8811 else if (strcasecmp (arg
, "none") == 0)
8812 sse_check
= check_none
;
8814 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
8817 case OPTION_MOPERAND_CHECK
:
8818 if (strcasecmp (arg
, "error") == 0)
8819 operand_check
= check_error
;
8820 else if (strcasecmp (arg
, "warning") == 0)
8821 operand_check
= check_warning
;
8822 else if (strcasecmp (arg
, "none") == 0)
8823 operand_check
= check_none
;
8825 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
8828 case OPTION_MAVXSCALAR
:
8829 if (strcasecmp (arg
, "128") == 0)
8831 else if (strcasecmp (arg
, "256") == 0)
8834 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
8843 #define MESSAGE_TEMPLATE \
8847 show_arch (FILE *stream
, int ext
, int check
)
8849 static char message
[] = MESSAGE_TEMPLATE
;
8850 char *start
= message
+ 27;
8852 int size
= sizeof (MESSAGE_TEMPLATE
);
8859 left
= size
- (start
- message
);
8860 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8862 /* Should it be skipped? */
8863 if (cpu_arch
[j
].skip
)
8866 name
= cpu_arch
[j
].name
;
8867 len
= cpu_arch
[j
].len
;
8870 /* It is an extension. Skip if we aren't asked to show it. */
8881 /* It is an processor. Skip if we show only extension. */
8884 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8886 /* It is an impossible processor - skip. */
8890 /* Reserve 2 spaces for ", " or ",\0" */
8893 /* Check if there is any room. */
8901 p
= mempcpy (p
, name
, len
);
8905 /* Output the current message now and start a new one. */
8908 fprintf (stream
, "%s\n", message
);
8910 left
= size
- (start
- message
) - len
- 2;
8912 gas_assert (left
>= 0);
8914 p
= mempcpy (p
, name
, len
);
8919 fprintf (stream
, "%s\n", message
);
8923 md_show_usage (FILE *stream
)
8925 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8926 fprintf (stream
, _("\
8928 -V print assembler version number\n\
8931 fprintf (stream
, _("\
8932 -n Do not optimize code alignment\n\
8933 -q quieten some warnings\n"));
8934 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8935 fprintf (stream
, _("\
8938 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8939 || defined (TE_PE) || defined (TE_PEP))
8940 fprintf (stream
, _("\
8941 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
8943 #ifdef SVR4_COMMENT_CHARS
8944 fprintf (stream
, _("\
8945 --divide do not treat `/' as a comment character\n"));
8947 fprintf (stream
, _("\
8948 --divide ignored\n"));
8950 fprintf (stream
, _("\
8951 -march=CPU[,+EXTENSION...]\n\
8952 generate code for CPU and EXTENSION, CPU is one of:\n"));
8953 show_arch (stream
, 0, 1);
8954 fprintf (stream
, _("\
8955 EXTENSION is combination of:\n"));
8956 show_arch (stream
, 1, 0);
8957 fprintf (stream
, _("\
8958 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8959 show_arch (stream
, 0, 0);
8960 fprintf (stream
, _("\
8961 -msse2avx encode SSE instructions with VEX prefix\n"));
8962 fprintf (stream
, _("\
8963 -msse-check=[none|error|warning]\n\
8964 check SSE instructions\n"));
8965 fprintf (stream
, _("\
8966 -moperand-check=[none|error|warning]\n\
8967 check operand combinations for validity\n"));
8968 fprintf (stream
, _("\
8969 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8971 fprintf (stream
, _("\
8972 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8973 fprintf (stream
, _("\
8974 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8975 fprintf (stream
, _("\
8976 -mindex-reg support pseudo index registers\n"));
8977 fprintf (stream
, _("\
8978 -mnaked-reg don't require `%%' prefix for registers\n"));
8979 fprintf (stream
, _("\
8980 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8983 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8984 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8985 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8987 /* Pick the target format to use. */
8990 i386_target_format (void)
8992 if (!strncmp (default_arch
, "x86_64", 6))
8994 update_code_flag (CODE_64BIT
, 1);
8995 if (default_arch
[6] == '\0')
8996 x86_elf_abi
= X86_64_ABI
;
8998 x86_elf_abi
= X86_64_X32_ABI
;
9000 else if (!strcmp (default_arch
, "i386"))
9001 update_code_flag (CODE_32BIT
, 1);
9003 as_fatal (_("unknown architecture"));
9005 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
9006 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9007 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
9008 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9010 switch (OUTPUT_FLAVOR
)
9012 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
9013 case bfd_target_aout_flavour
:
9014 return AOUT_TARGET_FORMAT
;
9016 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9017 # if defined (TE_PE) || defined (TE_PEP)
9018 case bfd_target_coff_flavour
:
9019 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
9020 # elif defined (TE_GO32)
9021 case bfd_target_coff_flavour
:
9024 case bfd_target_coff_flavour
:
9028 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9029 case bfd_target_elf_flavour
:
9033 switch (x86_elf_abi
)
9036 format
= ELF_TARGET_FORMAT
;
9039 use_rela_relocations
= 1;
9041 format
= ELF_TARGET_FORMAT64
;
9043 case X86_64_X32_ABI
:
9044 use_rela_relocations
= 1;
9046 disallow_64bit_reloc
= 1;
9047 format
= ELF_TARGET_FORMAT32
;
9050 if (cpu_arch_isa
== PROCESSOR_L1OM
)
9052 if (x86_elf_abi
!= X86_64_ABI
)
9053 as_fatal (_("Intel L1OM is 64bit only"));
9054 return ELF_TARGET_L1OM_FORMAT
;
9056 if (cpu_arch_isa
== PROCESSOR_K1OM
)
9058 if (x86_elf_abi
!= X86_64_ABI
)
9059 as_fatal (_("Intel K1OM is 64bit only"));
9060 return ELF_TARGET_K1OM_FORMAT
;
9066 #if defined (OBJ_MACH_O)
9067 case bfd_target_mach_o_flavour
:
9068 if (flag_code
== CODE_64BIT
)
9070 use_rela_relocations
= 1;
9072 return "mach-o-x86-64";
9075 return "mach-o-i386";
9083 #endif /* OBJ_MAYBE_ more than one */
9085 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
9087 i386_elf_emit_arch_note (void)
9089 if (IS_ELF
&& cpu_arch_name
!= NULL
)
9092 asection
*seg
= now_seg
;
9093 subsegT subseg
= now_subseg
;
9094 Elf_Internal_Note i_note
;
9095 Elf_External_Note e_note
;
9096 asection
*note_secp
;
9099 /* Create the .note section. */
9100 note_secp
= subseg_new (".note", 0);
9101 bfd_set_section_flags (stdoutput
,
9103 SEC_HAS_CONTENTS
| SEC_READONLY
);
9105 /* Process the arch string. */
9106 len
= strlen (cpu_arch_name
);
9108 i_note
.namesz
= len
+ 1;
9110 i_note
.type
= NT_ARCH
;
9111 p
= frag_more (sizeof (e_note
.namesz
));
9112 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
9113 p
= frag_more (sizeof (e_note
.descsz
));
9114 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
9115 p
= frag_more (sizeof (e_note
.type
));
9116 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
9117 p
= frag_more (len
+ 1);
9118 strcpy (p
, cpu_arch_name
);
9120 frag_align (2, 0, 0);
9122 subseg_set (seg
, subseg
);
9128 md_undefined_symbol (char *name
)
9130 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
9131 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
9132 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
9133 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
9137 if (symbol_find (name
))
9138 as_bad (_("GOT already in symbol table"));
9139 GOT_symbol
= symbol_new (name
, undefined_section
,
9140 (valueT
) 0, &zero_address_frag
);
9147 /* Round up a section size to the appropriate boundary. */
9150 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
9152 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9153 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
9155 /* For a.out, force the section size to be aligned. If we don't do
9156 this, BFD will align it for us, but it will not write out the
9157 final bytes of the section. This may be a bug in BFD, but it is
9158 easier to fix it here since that is how the other a.out targets
9162 align
= bfd_get_section_alignment (stdoutput
, segment
);
9163 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
9170 /* On the i386, PC-relative offsets are relative to the start of the
9171 next instruction. That is, the address of the offset, plus its
9172 size, since the offset is always the last part of the insn. */
9175 md_pcrel_from (fixS
*fixP
)
9177 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9183 s_bss (int ignore ATTRIBUTE_UNUSED
)
9187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9189 obj_elf_section_change_hook ();
9191 temp
= get_absolute_expression ();
9192 subseg_set (bss_section
, (subsegT
) temp
);
9193 demand_empty_rest_of_line ();
9199 i386_validate_fix (fixS
*fixp
)
9201 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
9203 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
9207 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
9212 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
9214 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
9221 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
9224 bfd_reloc_code_real_type code
;
9226 switch (fixp
->fx_r_type
)
9228 case BFD_RELOC_X86_64_PLT32
:
9229 case BFD_RELOC_X86_64_GOT32
:
9230 case BFD_RELOC_X86_64_GOTPCREL
:
9231 case BFD_RELOC_386_PLT32
:
9232 case BFD_RELOC_386_GOT32
:
9233 case BFD_RELOC_386_GOTOFF
:
9234 case BFD_RELOC_386_GOTPC
:
9235 case BFD_RELOC_386_TLS_GD
:
9236 case BFD_RELOC_386_TLS_LDM
:
9237 case BFD_RELOC_386_TLS_LDO_32
:
9238 case BFD_RELOC_386_TLS_IE_32
:
9239 case BFD_RELOC_386_TLS_IE
:
9240 case BFD_RELOC_386_TLS_GOTIE
:
9241 case BFD_RELOC_386_TLS_LE_32
:
9242 case BFD_RELOC_386_TLS_LE
:
9243 case BFD_RELOC_386_TLS_GOTDESC
:
9244 case BFD_RELOC_386_TLS_DESC_CALL
:
9245 case BFD_RELOC_X86_64_TLSGD
:
9246 case BFD_RELOC_X86_64_TLSLD
:
9247 case BFD_RELOC_X86_64_DTPOFF32
:
9248 case BFD_RELOC_X86_64_DTPOFF64
:
9249 case BFD_RELOC_X86_64_GOTTPOFF
:
9250 case BFD_RELOC_X86_64_TPOFF32
:
9251 case BFD_RELOC_X86_64_TPOFF64
:
9252 case BFD_RELOC_X86_64_GOTOFF64
:
9253 case BFD_RELOC_X86_64_GOTPC32
:
9254 case BFD_RELOC_X86_64_GOT64
:
9255 case BFD_RELOC_X86_64_GOTPCREL64
:
9256 case BFD_RELOC_X86_64_GOTPC64
:
9257 case BFD_RELOC_X86_64_GOTPLT64
:
9258 case BFD_RELOC_X86_64_PLTOFF64
:
9259 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9260 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9262 case BFD_RELOC_VTABLE_ENTRY
:
9263 case BFD_RELOC_VTABLE_INHERIT
:
9265 case BFD_RELOC_32_SECREL
:
9267 code
= fixp
->fx_r_type
;
9269 case BFD_RELOC_X86_64_32S
:
9270 if (!fixp
->fx_pcrel
)
9272 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
9273 code
= fixp
->fx_r_type
;
9279 switch (fixp
->fx_size
)
9282 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9283 _("can not do %d byte pc-relative relocation"),
9285 code
= BFD_RELOC_32_PCREL
;
9287 case 1: code
= BFD_RELOC_8_PCREL
; break;
9288 case 2: code
= BFD_RELOC_16_PCREL
; break;
9289 case 4: code
= BFD_RELOC_32_PCREL
; break;
9291 case 8: code
= BFD_RELOC_64_PCREL
; break;
9297 switch (fixp
->fx_size
)
9300 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9301 _("can not do %d byte relocation"),
9303 code
= BFD_RELOC_32
;
9305 case 1: code
= BFD_RELOC_8
; break;
9306 case 2: code
= BFD_RELOC_16
; break;
9307 case 4: code
= BFD_RELOC_32
; break;
9309 case 8: code
= BFD_RELOC_64
; break;
9316 if ((code
== BFD_RELOC_32
9317 || code
== BFD_RELOC_32_PCREL
9318 || code
== BFD_RELOC_X86_64_32S
)
9320 && fixp
->fx_addsy
== GOT_symbol
)
9323 code
= BFD_RELOC_386_GOTPC
;
9325 code
= BFD_RELOC_X86_64_GOTPC32
;
9327 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
9329 && fixp
->fx_addsy
== GOT_symbol
)
9331 code
= BFD_RELOC_X86_64_GOTPC64
;
9334 rel
= (arelent
*) xmalloc (sizeof (arelent
));
9335 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9336 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9338 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9340 if (!use_rela_relocations
)
9342 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9343 vtable entry to be used in the relocation's section offset. */
9344 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9345 rel
->address
= fixp
->fx_offset
;
9346 #if defined (OBJ_COFF) && defined (TE_PE)
9347 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
9348 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
9353 /* Use the rela in 64bit mode. */
9356 if (disallow_64bit_reloc
)
9359 case BFD_RELOC_X86_64_DTPOFF64
:
9360 case BFD_RELOC_X86_64_TPOFF64
:
9361 case BFD_RELOC_64_PCREL
:
9362 case BFD_RELOC_X86_64_GOTOFF64
:
9363 case BFD_RELOC_X86_64_GOT64
:
9364 case BFD_RELOC_X86_64_GOTPCREL64
:
9365 case BFD_RELOC_X86_64_GOTPC64
:
9366 case BFD_RELOC_X86_64_GOTPLT64
:
9367 case BFD_RELOC_X86_64_PLTOFF64
:
9368 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9369 _("cannot represent relocation type %s in x32 mode"),
9370 bfd_get_reloc_code_name (code
));
9376 if (!fixp
->fx_pcrel
)
9377 rel
->addend
= fixp
->fx_offset
;
9381 case BFD_RELOC_X86_64_PLT32
:
9382 case BFD_RELOC_X86_64_GOT32
:
9383 case BFD_RELOC_X86_64_GOTPCREL
:
9384 case BFD_RELOC_X86_64_TLSGD
:
9385 case BFD_RELOC_X86_64_TLSLD
:
9386 case BFD_RELOC_X86_64_GOTTPOFF
:
9387 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9388 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9389 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
9392 rel
->addend
= (section
->vma
9394 + fixp
->fx_addnumber
9395 + md_pcrel_from (fixp
));
9400 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9401 if (rel
->howto
== NULL
)
9403 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9404 _("cannot represent relocation type %s"),
9405 bfd_get_reloc_code_name (code
));
9406 /* Set howto to a garbage value so that we can keep going. */
9407 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
9408 gas_assert (rel
->howto
!= NULL
);
9414 #include "tc-i386-intel.c"
9417 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9419 int saved_naked_reg
;
9420 char saved_register_dot
;
9422 saved_naked_reg
= allow_naked_reg
;
9423 allow_naked_reg
= 1;
9424 saved_register_dot
= register_chars
['.'];
9425 register_chars
['.'] = '.';
9426 allow_pseudo_reg
= 1;
9427 expression_and_evaluate (exp
);
9428 allow_pseudo_reg
= 0;
9429 register_chars
['.'] = saved_register_dot
;
9430 allow_naked_reg
= saved_naked_reg
;
9432 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9434 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9436 exp
->X_op
= O_constant
;
9437 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9438 .dw2_regnum
[flag_code
>> 1];
9441 exp
->X_op
= O_illegal
;
9446 tc_x86_frame_initial_instructions (void)
9448 static unsigned int sp_regno
[2];
9450 if (!sp_regno
[flag_code
>> 1])
9452 char *saved_input
= input_line_pointer
;
9453 char sp
[][4] = {"esp", "rsp"};
9456 input_line_pointer
= sp
[flag_code
>> 1];
9457 tc_x86_parse_to_dw2regnum (&exp
);
9458 gas_assert (exp
.X_op
== O_constant
);
9459 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9460 input_line_pointer
= saved_input
;
9463 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9464 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9468 x86_dwarf2_addr_size (void)
9470 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9471 if (x86_elf_abi
== X86_64_X32_ABI
)
9474 return bfd_arch_bits_per_address (stdoutput
) / 8;
9478 i386_elf_section_type (const char *str
, size_t len
)
9480 if (flag_code
== CODE_64BIT
9481 && len
== sizeof ("unwind") - 1
9482 && strncmp (str
, "unwind", 6) == 0)
9483 return SHT_X86_64_UNWIND
;
9490 i386_solaris_fix_up_eh_frame (segT sec
)
9492 if (flag_code
== CODE_64BIT
)
9493 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
9499 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9503 exp
.X_op
= O_secrel
;
9504 exp
.X_add_symbol
= symbol
;
9505 exp
.X_add_number
= 0;
9506 emit_expr (&exp
, size
);
9510 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9511 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9514 x86_64_section_letter (int letter
, char **ptr_msg
)
9516 if (flag_code
== CODE_64BIT
)
9519 return SHF_X86_64_LARGE
;
9521 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
9524 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
9529 x86_64_section_word (char *str
, size_t len
)
9531 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9532 return SHF_X86_64_LARGE
;
9538 handle_large_common (int small ATTRIBUTE_UNUSED
)
9540 if (flag_code
!= CODE_64BIT
)
9542 s_comm_internal (0, elf_common_parse
);
9543 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9547 static segT lbss_section
;
9548 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9549 asection
*saved_bss_section
= bss_section
;
9551 if (lbss_section
== NULL
)
9553 flagword applicable
;
9555 subsegT subseg
= now_subseg
;
9557 /* The .lbss section is for local .largecomm symbols. */
9558 lbss_section
= subseg_new (".lbss", 0);
9559 applicable
= bfd_applicable_section_flags (stdoutput
);
9560 bfd_set_section_flags (stdoutput
, lbss_section
,
9561 applicable
& SEC_ALLOC
);
9562 seg_info (lbss_section
)->bss
= 1;
9564 subseg_set (seg
, subseg
);
9567 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9568 bss_section
= lbss_section
;
9570 s_comm_internal (0, elf_common_parse
);
9572 elf_com_section_ptr
= saved_com_section_ptr
;
9573 bss_section
= saved_bss_section
;
9576 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */