1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (void);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes
;
332 unsigned char prefix
[MAX_PREFIXES
];
334 /* RM and SIB are the modrm byte and the sib byte where the
335 addressing modes of this insn are encoded. */
342 /* Masking attributes. */
343 struct Mask_Operation
*mask
;
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation
*rounding
;
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation
*broadcast
;
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift
;
354 /* Swap operand in encoding. */
355 unsigned int swap_operand
;
357 /* Prefer 8bit or 32bit displacement in encoding. */
360 disp_encoding_default
= 0,
366 const char *rep_prefix
;
369 const char *hle_prefix
;
371 /* Have BND prefix. */
372 const char *bnd_prefix
;
374 /* Need VREX to support upper 16 registers. */
378 enum i386_error error
;
381 typedef struct _i386_insn i386_insn
;
383 /* Link RC type with corresponding string, that'll be looked for in
392 static const struct RC_name RC_NamesTable
[] =
394 { rne
, STRING_COMMA_LEN ("rn-sae") },
395 { rd
, STRING_COMMA_LEN ("rd-sae") },
396 { ru
, STRING_COMMA_LEN ("ru-sae") },
397 { rz
, STRING_COMMA_LEN ("rz-sae") },
398 { saeonly
, STRING_COMMA_LEN ("sae") },
401 /* List of chars besides those in app.c:symbol_chars that can start an
402 operand. Used to prevent the scrubber eating vital white-space. */
403 const char extra_symbol_chars
[] = "*%-([{"
412 #if (defined (TE_I386AIX) \
413 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
414 && !defined (TE_GNU) \
415 && !defined (TE_LINUX) \
416 && !defined (TE_NACL) \
417 && !defined (TE_NETWARE) \
418 && !defined (TE_FreeBSD) \
419 && !defined (TE_DragonFly) \
420 && !defined (TE_NetBSD)))
421 /* This array holds the chars that always start a comment. If the
422 pre-processor is disabled, these aren't very useful. The option
423 --divide will remove '/' from this list. */
424 const char *i386_comment_chars
= "#/";
425 #define SVR4_COMMENT_CHARS 1
426 #define PREFIX_SEPARATOR '\\'
429 const char *i386_comment_chars
= "#";
430 #define PREFIX_SEPARATOR '/'
433 /* This array holds the chars that only start a comment at the beginning of
434 a line. If the line seems to have the form '# 123 filename'
435 .line and .file directives will appear in the pre-processed output.
436 Note that input_file.c hand checks for '#' at the beginning of the
437 first line of the input file. This is because the compiler outputs
438 #NO_APP at the beginning of its output.
439 Also note that comments started like this one will always work if
440 '/' isn't otherwise defined. */
441 const char line_comment_chars
[] = "#/";
443 const char line_separator_chars
[] = ";";
445 /* Chars that can be used to separate mant from exp in floating point
447 const char EXP_CHARS
[] = "eE";
449 /* Chars that mean this number is a floating point constant
452 const char FLT_CHARS
[] = "fFdDxX";
454 /* Tables for lexical analysis. */
455 static char mnemonic_chars
[256];
456 static char register_chars
[256];
457 static char operand_chars
[256];
458 static char identifier_chars
[256];
459 static char digit_chars
[256];
461 /* Lexical macros. */
462 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
463 #define is_operand_char(x) (operand_chars[(unsigned char) x])
464 #define is_register_char(x) (register_chars[(unsigned char) x])
465 #define is_space_char(x) ((x) == ' ')
466 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
467 #define is_digit_char(x) (digit_chars[(unsigned char) x])
469 /* All non-digit non-letter characters that may occur in an operand. */
470 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
472 /* md_assemble() always leaves the strings it's passed unaltered. To
473 effect this we maintain a stack of saved characters that we've smashed
474 with '\0's (indicating end of strings for various sub-fields of the
475 assembler instruction). */
476 static char save_stack
[32];
477 static char *save_stack_p
;
478 #define END_STRING_AND_SAVE(s) \
479 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
480 #define RESTORE_END_STRING(s) \
481 do { *(s) = *--save_stack_p; } while (0)
483 /* The instruction we're assembling. */
486 /* Possible templates for current insn. */
487 static const templates
*current_templates
;
489 /* Per instruction expressionS buffers: max displacements & immediates. */
490 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
491 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
493 /* Current operand we are working on. */
494 static int this_operand
= -1;
496 /* We support four different modes. FLAG_CODE variable is used to distinguish
504 static enum flag_code flag_code
;
505 static unsigned int object_64bit
;
506 static unsigned int disallow_64bit_reloc
;
507 static int use_rela_relocations
= 0;
509 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
510 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
511 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
513 /* The ELF ABI to use. */
521 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
524 #if defined (TE_PE) || defined (TE_PEP)
525 /* Use big object file format. */
526 static int use_big_obj
= 0;
529 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
530 /* 1 if generating code for a shared library. */
531 static int shared
= 0;
534 /* 1 for intel syntax,
536 static int intel_syntax
= 0;
538 /* 1 for intel mnemonic,
539 0 if att mnemonic. */
540 static int intel_mnemonic
= !SYSV386_COMPAT
;
542 /* 1 if support old (<= 2.8.1) versions of gcc. */
543 static int old_gcc
= OLDGCC_COMPAT
;
545 /* 1 if pseudo registers are permitted. */
546 static int allow_pseudo_reg
= 0;
548 /* 1 if register prefix % not required. */
549 static int allow_naked_reg
= 0;
551 /* 1 if the assembler should add BND prefix for all control-tranferring
552 instructions supporting it, even if this prefix wasn't specified
554 static int add_bnd_prefix
= 0;
556 /* 1 if pseudo index register, eiz/riz, is allowed . */
557 static int allow_index_reg
= 0;
559 /* 1 if the assembler should ignore LOCK prefix, even if it was
560 specified explicitly. */
561 static int omit_lock_prefix
= 0;
563 /* 1 if the assembler should encode lfence, mfence, and sfence as
564 "lock addl $0, (%{re}sp)". */
565 static int avoid_fence
= 0;
567 /* 1 if the assembler should generate relax relocations. */
569 static int generate_relax_relocations
570 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
572 static enum check_kind
578 sse_check
, operand_check
= check_warning
;
580 /* Register prefix used for error message. */
581 static const char *register_prefix
= "%";
583 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
584 leave, push, and pop instructions so that gcc has the same stack
585 frame as in 32 bit mode. */
586 static char stackop_size
= '\0';
588 /* Non-zero to optimize code alignment. */
589 int optimize_align_code
= 1;
591 /* Non-zero to quieten some warnings. */
592 static int quiet_warnings
= 0;
595 static const char *cpu_arch_name
= NULL
;
596 static char *cpu_sub_arch_name
= NULL
;
598 /* CPU feature flags. */
599 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
601 /* If we have selected a cpu we are generating instructions for. */
602 static int cpu_arch_tune_set
= 0;
604 /* Cpu we are generating instructions for. */
605 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
607 /* CPU feature flags of cpu we are generating instructions for. */
608 static i386_cpu_flags cpu_arch_tune_flags
;
610 /* CPU instruction set architecture used. */
611 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
613 /* CPU feature flags of instruction set architecture used. */
614 i386_cpu_flags cpu_arch_isa_flags
;
616 /* If set, conditional jumps are not automatically promoted to handle
617 larger than a byte offset. */
618 static unsigned int no_cond_jump_promotion
= 0;
620 /* Encode SSE instructions with VEX prefix. */
621 static unsigned int sse2avx
;
623 /* Encode scalar AVX instructions with specific vector length. */
630 /* Encode scalar EVEX LIG instructions with specific vector length. */
638 /* Encode EVEX WIG instructions with specific evex.w. */
645 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
646 static enum rc_type evexrcig
= rne
;
648 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
649 static symbolS
*GOT_symbol
;
651 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
652 unsigned int x86_dwarf2_return_column
;
654 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
655 int x86_cie_data_alignment
;
657 /* Interface to relax_segment.
658 There are 3 major relax states for 386 jump insns because the
659 different types of jumps add different sizes to frags when we're
660 figuring out what sort of jump to choose to reach a given label. */
663 #define UNCOND_JUMP 0
665 #define COND_JUMP86 2
670 #define SMALL16 (SMALL | CODE16)
672 #define BIG16 (BIG | CODE16)
676 #define INLINE __inline__
682 #define ENCODE_RELAX_STATE(type, size) \
683 ((relax_substateT) (((type) << 2) | (size)))
684 #define TYPE_FROM_RELAX_STATE(s) \
686 #define DISP_SIZE_FROM_RELAX_STATE(s) \
687 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
689 /* This table is used by relax_frag to promote short jumps to long
690 ones where necessary. SMALL (short) jumps may be promoted to BIG
691 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
692 don't allow a short jump in a 32 bit code segment to be promoted to
693 a 16 bit offset jump because it's slower (requires data size
694 prefix), and doesn't work, unless the destination is in the bottom
695 64k of the code segment (The top 16 bits of eip are zeroed). */
697 const relax_typeS md_relax_table
[] =
700 1) most positive reach of this state,
701 2) most negative reach of this state,
702 3) how many bytes this mode will have in the variable part of the frag
703 4) which index into the table to try if we can't fit into this one. */
705 /* UNCOND_JUMP states. */
706 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
707 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
708 /* dword jmp adds 4 bytes to frag:
709 0 extra opcode bytes, 4 displacement bytes. */
711 /* word jmp adds 2 byte2 to frag:
712 0 extra opcode bytes, 2 displacement bytes. */
715 /* COND_JUMP states. */
716 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
717 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
718 /* dword conditionals adds 5 bytes to frag:
719 1 extra opcode byte, 4 displacement bytes. */
721 /* word conditionals add 3 bytes to frag:
722 1 extra opcode byte, 2 displacement bytes. */
725 /* COND_JUMP86 states. */
726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
728 /* dword conditionals adds 5 bytes to frag:
729 1 extra opcode byte, 4 displacement bytes. */
731 /* word conditionals add 4 bytes to frag:
732 1 displacement byte and a 3 byte long branch insn. */
736 static const arch_entry cpu_arch
[] =
738 /* Do not replace the first two entries - i386_target_format()
739 relies on them being there in this order. */
740 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
741 CPU_GENERIC32_FLAGS
, 0 },
742 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
743 CPU_GENERIC64_FLAGS
, 0 },
744 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
746 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
748 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
750 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
752 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
754 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
756 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
758 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
760 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
761 CPU_PENTIUMPRO_FLAGS
, 0 },
762 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
764 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
766 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
768 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
770 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
771 CPU_NOCONA_FLAGS
, 0 },
772 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
774 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
776 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
777 CPU_CORE2_FLAGS
, 1 },
778 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
779 CPU_CORE2_FLAGS
, 0 },
780 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
781 CPU_COREI7_FLAGS
, 0 },
782 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
784 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
786 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
787 CPU_IAMCU_FLAGS
, 0 },
788 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
790 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
792 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
793 CPU_ATHLON_FLAGS
, 0 },
794 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
796 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
798 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
800 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
801 CPU_AMDFAM10_FLAGS
, 0 },
802 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
803 CPU_BDVER1_FLAGS
, 0 },
804 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
805 CPU_BDVER2_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
807 CPU_BDVER3_FLAGS
, 0 },
808 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
809 CPU_BDVER4_FLAGS
, 0 },
810 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
811 CPU_ZNVER1_FLAGS
, 0 },
812 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
813 CPU_BTVER1_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
815 CPU_BTVER2_FLAGS
, 0 },
816 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
818 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
820 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
822 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
824 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
826 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
828 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
830 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
831 CPU_SSSE3_FLAGS
, 0 },
832 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
833 CPU_SSE4_1_FLAGS
, 0 },
834 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
835 CPU_SSE4_2_FLAGS
, 0 },
836 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
837 CPU_SSE4_2_FLAGS
, 0 },
838 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
840 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
842 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
843 CPU_AVX512F_FLAGS
, 0 },
844 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
845 CPU_AVX512CD_FLAGS
, 0 },
846 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
847 CPU_AVX512ER_FLAGS
, 0 },
848 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
849 CPU_AVX512PF_FLAGS
, 0 },
850 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
851 CPU_AVX512DQ_FLAGS
, 0 },
852 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
853 CPU_AVX512BW_FLAGS
, 0 },
854 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
855 CPU_AVX512VL_FLAGS
, 0 },
856 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
858 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
859 CPU_VMFUNC_FLAGS
, 0 },
860 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
863 CPU_XSAVE_FLAGS
, 0 },
864 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
865 CPU_XSAVEOPT_FLAGS
, 0 },
866 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
867 CPU_XSAVEC_FLAGS
, 0 },
868 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
869 CPU_XSAVES_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
872 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
873 CPU_PCLMUL_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
875 CPU_PCLMUL_FLAGS
, 1 },
876 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
877 CPU_FSGSBASE_FLAGS
, 0 },
878 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
879 CPU_RDRND_FLAGS
, 0 },
880 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
882 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
884 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
886 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
888 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
890 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
892 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
893 CPU_MOVBE_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
899 CPU_LZCNT_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
905 CPU_INVPCID_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
907 CPU_CLFLUSH_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
911 CPU_SYSCALL_FLAGS
, 0 },
912 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
913 CPU_RDTSCP_FLAGS
, 0 },
914 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
915 CPU_3DNOW_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
917 CPU_3DNOWA_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
919 CPU_PADLOCK_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
925 CPU_SSE4A_FLAGS
, 0 },
926 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
932 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
935 CPU_RDSEED_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
937 CPU_PRFCHW_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
945 CPU_CLFLUSHOPT_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
947 CPU_PREFETCHWT1_FLAGS
, 0 },
948 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
950 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
952 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
953 CPU_PCOMMIT_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
955 CPU_AVX512IFMA_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
957 CPU_AVX512VBMI_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
959 CPU_CLZERO_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
961 CPU_MWAITX_FLAGS
, 0 },
962 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
963 CPU_OSPKE_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
965 CPU_RDPID_FLAGS
, 0 },
968 static const noarch_entry cpu_noarch
[] =
970 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
971 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
972 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
973 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
977 /* Like s_lcomm_internal in gas/read.c but the alignment string
978 is allowed to be optional. */
981 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
988 && *input_line_pointer
== ',')
990 align
= parse_align (needs_align
- 1);
992 if (align
== (addressT
) -1)
1007 bss_alloc (symbolP
, size
, align
);
1012 pe_lcomm (int needs_align
)
1014 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1018 const pseudo_typeS md_pseudo_table
[] =
1020 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1021 {"align", s_align_bytes
, 0},
1023 {"align", s_align_ptwo
, 0},
1025 {"arch", set_cpu_arch
, 0},
1029 {"lcomm", pe_lcomm
, 1},
1031 {"ffloat", float_cons
, 'f'},
1032 {"dfloat", float_cons
, 'd'},
1033 {"tfloat", float_cons
, 'x'},
1035 {"slong", signed_cons
, 4},
1036 {"noopt", s_ignore
, 0},
1037 {"optim", s_ignore
, 0},
1038 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1039 {"code16", set_code_flag
, CODE_16BIT
},
1040 {"code32", set_code_flag
, CODE_32BIT
},
1041 {"code64", set_code_flag
, CODE_64BIT
},
1042 {"intel_syntax", set_intel_syntax
, 1},
1043 {"att_syntax", set_intel_syntax
, 0},
1044 {"intel_mnemonic", set_intel_mnemonic
, 1},
1045 {"att_mnemonic", set_intel_mnemonic
, 0},
1046 {"allow_index_reg", set_allow_index_reg
, 1},
1047 {"disallow_index_reg", set_allow_index_reg
, 0},
1048 {"sse_check", set_check
, 0},
1049 {"operand_check", set_check
, 1},
1050 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1051 {"largecomm", handle_large_common
, 0},
1053 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1054 {"loc", dwarf2_directive_loc
, 0},
1055 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1058 {"secrel32", pe_directive_secrel
, 0},
1063 /* For interface with expression (). */
1064 extern char *input_line_pointer
;
1066 /* Hash table for instruction mnemonic lookup. */
1067 static struct hash_control
*op_hash
;
1069 /* Hash table for register lookup. */
1070 static struct hash_control
*reg_hash
;
1073 i386_align_code (fragS
*fragP
, int count
)
1075 /* Various efficient no-op patterns for aligning code labels.
1076 Note: Don't try to assemble the instructions in the comments.
1077 0L and 0w are not legal. */
1078 static const unsigned char f32_1
[] =
1080 static const unsigned char f32_2
[] =
1081 {0x66,0x90}; /* xchg %ax,%ax */
1082 static const unsigned char f32_3
[] =
1083 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1084 static const unsigned char f32_4
[] =
1085 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1086 static const unsigned char f32_5
[] =
1088 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1089 static const unsigned char f32_6
[] =
1090 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1091 static const unsigned char f32_7
[] =
1092 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1093 static const unsigned char f32_8
[] =
1095 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1096 static const unsigned char f32_9
[] =
1097 {0x89,0xf6, /* movl %esi,%esi */
1098 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1099 static const unsigned char f32_10
[] =
1100 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1101 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1102 static const unsigned char f32_11
[] =
1103 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1104 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1105 static const unsigned char f32_12
[] =
1106 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1107 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1108 static const unsigned char f32_13
[] =
1109 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1110 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1111 static const unsigned char f32_14
[] =
1112 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1113 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1114 static const unsigned char f16_3
[] =
1115 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1116 static const unsigned char f16_4
[] =
1117 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1118 static const unsigned char f16_5
[] =
1120 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1121 static const unsigned char f16_6
[] =
1122 {0x89,0xf6, /* mov %si,%si */
1123 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1124 static const unsigned char f16_7
[] =
1125 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1126 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1127 static const unsigned char f16_8
[] =
1128 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1129 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1130 static const unsigned char jump_31
[] =
1131 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1132 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1133 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1134 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1135 static const unsigned char *const f32_patt
[] = {
1136 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1137 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1139 static const unsigned char *const f16_patt
[] = {
1140 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1142 /* nopl (%[re]ax) */
1143 static const unsigned char alt_3
[] =
1145 /* nopl 0(%[re]ax) */
1146 static const unsigned char alt_4
[] =
1147 {0x0f,0x1f,0x40,0x00};
1148 /* nopl 0(%[re]ax,%[re]ax,1) */
1149 static const unsigned char alt_5
[] =
1150 {0x0f,0x1f,0x44,0x00,0x00};
1151 /* nopw 0(%[re]ax,%[re]ax,1) */
1152 static const unsigned char alt_6
[] =
1153 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1154 /* nopl 0L(%[re]ax) */
1155 static const unsigned char alt_7
[] =
1156 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1157 /* nopl 0L(%[re]ax,%[re]ax,1) */
1158 static const unsigned char alt_8
[] =
1159 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1160 /* nopw 0L(%[re]ax,%[re]ax,1) */
1161 static const unsigned char alt_9
[] =
1162 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1163 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1164 static const unsigned char alt_10
[] =
1165 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1166 static const unsigned char *const alt_patt
[] = {
1167 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1171 /* Only align for at least a positive non-zero boundary. */
1172 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1175 /* We need to decide which NOP sequence to use for 32bit and
1176 64bit. When -mtune= is used:
1178 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1179 PROCESSOR_GENERIC32, f32_patt will be used.
1180 2. For the rest, alt_patt will be used.
1182 When -mtune= isn't used, alt_patt will be used if
1183 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1186 When -march= or .arch is used, we can't use anything beyond
1187 cpu_arch_isa_flags. */
1189 if (flag_code
== CODE_16BIT
)
1193 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1195 /* Adjust jump offset. */
1196 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1199 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1200 f16_patt
[count
- 1], count
);
1204 const unsigned char *const *patt
= NULL
;
1206 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1208 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1209 switch (cpu_arch_tune
)
1211 case PROCESSOR_UNKNOWN
:
1212 /* We use cpu_arch_isa_flags to check if we SHOULD
1213 optimize with nops. */
1214 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1219 case PROCESSOR_PENTIUM4
:
1220 case PROCESSOR_NOCONA
:
1221 case PROCESSOR_CORE
:
1222 case PROCESSOR_CORE2
:
1223 case PROCESSOR_COREI7
:
1224 case PROCESSOR_L1OM
:
1225 case PROCESSOR_K1OM
:
1226 case PROCESSOR_GENERIC64
:
1228 case PROCESSOR_ATHLON
:
1230 case PROCESSOR_AMDFAM10
:
1232 case PROCESSOR_ZNVER
:
1236 case PROCESSOR_I386
:
1237 case PROCESSOR_I486
:
1238 case PROCESSOR_PENTIUM
:
1239 case PROCESSOR_PENTIUMPRO
:
1240 case PROCESSOR_IAMCU
:
1241 case PROCESSOR_GENERIC32
:
1248 switch (fragP
->tc_frag_data
.tune
)
1250 case PROCESSOR_UNKNOWN
:
1251 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1252 PROCESSOR_UNKNOWN. */
1256 case PROCESSOR_I386
:
1257 case PROCESSOR_I486
:
1258 case PROCESSOR_PENTIUM
:
1259 case PROCESSOR_IAMCU
:
1261 case PROCESSOR_ATHLON
:
1263 case PROCESSOR_AMDFAM10
:
1265 case PROCESSOR_ZNVER
:
1267 case PROCESSOR_GENERIC32
:
1268 /* We use cpu_arch_isa_flags to check if we CAN optimize
1270 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1275 case PROCESSOR_PENTIUMPRO
:
1276 case PROCESSOR_PENTIUM4
:
1277 case PROCESSOR_NOCONA
:
1278 case PROCESSOR_CORE
:
1279 case PROCESSOR_CORE2
:
1280 case PROCESSOR_COREI7
:
1281 case PROCESSOR_L1OM
:
1282 case PROCESSOR_K1OM
:
1283 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1288 case PROCESSOR_GENERIC64
:
1294 if (patt
== f32_patt
)
1296 /* If the padding is less than 15 bytes, we use the normal
1297 ones. Otherwise, we use a jump instruction and adjust
1301 /* For 64bit, the limit is 3 bytes. */
1302 if (flag_code
== CODE_64BIT
1303 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1308 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1309 patt
[count
- 1], count
);
1312 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1314 /* Adjust jump offset. */
1315 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1320 /* Maximum length of an instruction is 10 byte. If the
1321 padding is greater than 10 bytes and we don't use jump,
1322 we have to break it into smaller pieces. */
1323 int padding
= count
;
1324 while (padding
> 10)
1327 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1332 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1333 patt
[padding
- 1], padding
);
1336 fragP
->fr_var
= count
;
1340 operand_type_all_zero (const union i386_operand_type
*x
)
1342 switch (ARRAY_SIZE(x
->array
))
1351 return !x
->array
[0];
1358 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1360 switch (ARRAY_SIZE(x
->array
))
1375 operand_type_equal (const union i386_operand_type
*x
,
1376 const union i386_operand_type
*y
)
1378 switch (ARRAY_SIZE(x
->array
))
1381 if (x
->array
[2] != y
->array
[2])
1384 if (x
->array
[1] != y
->array
[1])
1387 return x
->array
[0] == y
->array
[0];
1395 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1397 switch (ARRAY_SIZE(x
->array
))
1406 return !x
->array
[0];
1413 cpu_flags_equal (const union i386_cpu_flags
*x
,
1414 const union i386_cpu_flags
*y
)
1416 switch (ARRAY_SIZE(x
->array
))
1419 if (x
->array
[2] != y
->array
[2])
1422 if (x
->array
[1] != y
->array
[1])
1425 return x
->array
[0] == y
->array
[0];
1433 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1435 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1436 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1439 static INLINE i386_cpu_flags
1440 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1442 switch (ARRAY_SIZE (x
.array
))
1445 x
.array
[2] &= y
.array
[2];
1447 x
.array
[1] &= y
.array
[1];
1449 x
.array
[0] &= y
.array
[0];
1457 static INLINE i386_cpu_flags
1458 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1460 switch (ARRAY_SIZE (x
.array
))
1463 x
.array
[2] |= y
.array
[2];
1465 x
.array
[1] |= y
.array
[1];
1467 x
.array
[0] |= y
.array
[0];
1475 static INLINE i386_cpu_flags
1476 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1478 switch (ARRAY_SIZE (x
.array
))
1481 x
.array
[2] &= ~y
.array
[2];
1483 x
.array
[1] &= ~y
.array
[1];
1485 x
.array
[0] &= ~y
.array
[0];
1494 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1496 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1498 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1499 i386_cpu_flags compat_flags
;
1500 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1501 return cpu_flags_all_zero (&compat_flags
);
1507 #define CPU_FLAGS_ARCH_MATCH 0x1
1508 #define CPU_FLAGS_64BIT_MATCH 0x2
1509 #define CPU_FLAGS_AES_MATCH 0x4
1510 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1511 #define CPU_FLAGS_AVX_MATCH 0x10
1513 #define CPU_FLAGS_32BIT_MATCH \
1514 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1515 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1516 #define CPU_FLAGS_PERFECT_MATCH \
1517 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1519 /* Return CPU flags match bits. */
1522 cpu_flags_match (const insn_template
*t
)
1524 i386_cpu_flags x
= t
->cpu_flags
;
1525 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1527 x
.bitfield
.cpu64
= 0;
1528 x
.bitfield
.cpuno64
= 0;
1530 if (cpu_flags_all_zero (&x
))
1532 /* This instruction is available on all archs. */
1533 match
|= CPU_FLAGS_32BIT_MATCH
;
1537 /* This instruction is available only on some archs. */
1538 i386_cpu_flags cpu
= cpu_arch_flags
;
1540 cpu
.bitfield
.cpu64
= 0;
1541 cpu
.bitfield
.cpuno64
= 0;
1542 cpu
= cpu_flags_and (x
, cpu
);
1543 if (!cpu_flags_all_zero (&cpu
))
1545 if (x
.bitfield
.cpuavx
)
1547 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1548 if (cpu
.bitfield
.cpuavx
)
1550 /* Check SSE2AVX. */
1551 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1553 match
|= (CPU_FLAGS_ARCH_MATCH
1554 | CPU_FLAGS_AVX_MATCH
);
1556 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1557 match
|= CPU_FLAGS_AES_MATCH
;
1559 if (!x
.bitfield
.cpupclmul
1560 || cpu
.bitfield
.cpupclmul
)
1561 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1565 match
|= CPU_FLAGS_ARCH_MATCH
;
1568 match
|= CPU_FLAGS_32BIT_MATCH
;
1574 static INLINE i386_operand_type
1575 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1577 switch (ARRAY_SIZE (x
.array
))
1580 x
.array
[2] &= y
.array
[2];
1582 x
.array
[1] &= y
.array
[1];
1584 x
.array
[0] &= y
.array
[0];
1592 static INLINE i386_operand_type
1593 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1595 switch (ARRAY_SIZE (x
.array
))
1598 x
.array
[2] |= y
.array
[2];
1600 x
.array
[1] |= y
.array
[1];
1602 x
.array
[0] |= y
.array
[0];
1610 static INLINE i386_operand_type
1611 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1613 switch (ARRAY_SIZE (x
.array
))
1616 x
.array
[2] ^= y
.array
[2];
1618 x
.array
[1] ^= y
.array
[1];
1620 x
.array
[0] ^= y
.array
[0];
1628 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1629 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1630 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1631 static const i386_operand_type inoutportreg
1632 = OPERAND_TYPE_INOUTPORTREG
;
1633 static const i386_operand_type reg16_inoutportreg
1634 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1635 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1636 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1637 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1638 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1639 static const i386_operand_type anydisp
1640 = OPERAND_TYPE_ANYDISP
;
1641 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1642 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1643 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1644 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1645 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1646 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1647 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1648 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1649 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1650 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1651 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1652 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1653 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1654 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1665 operand_type_check (i386_operand_type t
, enum operand_type c
)
1670 return (t
.bitfield
.reg8
1673 || t
.bitfield
.reg64
);
1676 return (t
.bitfield
.imm8
1680 || t
.bitfield
.imm32s
1681 || t
.bitfield
.imm64
);
1684 return (t
.bitfield
.disp8
1685 || t
.bitfield
.disp16
1686 || t
.bitfield
.disp32
1687 || t
.bitfield
.disp32s
1688 || t
.bitfield
.disp64
);
1691 return (t
.bitfield
.disp8
1692 || t
.bitfield
.disp16
1693 || t
.bitfield
.disp32
1694 || t
.bitfield
.disp32s
1695 || t
.bitfield
.disp64
1696 || t
.bitfield
.baseindex
);
1705 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1706 operand J for instruction template T. */
1709 match_reg_size (const insn_template
*t
, unsigned int j
)
1711 return !((i
.types
[j
].bitfield
.byte
1712 && !t
->operand_types
[j
].bitfield
.byte
)
1713 || (i
.types
[j
].bitfield
.word
1714 && !t
->operand_types
[j
].bitfield
.word
)
1715 || (i
.types
[j
].bitfield
.dword
1716 && !t
->operand_types
[j
].bitfield
.dword
)
1717 || (i
.types
[j
].bitfield
.qword
1718 && !t
->operand_types
[j
].bitfield
.qword
));
1721 /* Return 1 if there is no conflict in any size on operand J for
1722 instruction template T. */
1725 match_mem_size (const insn_template
*t
, unsigned int j
)
1727 return (match_reg_size (t
, j
)
1728 && !((i
.types
[j
].bitfield
.unspecified
1730 && !t
->operand_types
[j
].bitfield
.unspecified
)
1731 || (i
.types
[j
].bitfield
.fword
1732 && !t
->operand_types
[j
].bitfield
.fword
)
1733 || (i
.types
[j
].bitfield
.tbyte
1734 && !t
->operand_types
[j
].bitfield
.tbyte
)
1735 || (i
.types
[j
].bitfield
.xmmword
1736 && !t
->operand_types
[j
].bitfield
.xmmword
)
1737 || (i
.types
[j
].bitfield
.ymmword
1738 && !t
->operand_types
[j
].bitfield
.ymmword
)
1739 || (i
.types
[j
].bitfield
.zmmword
1740 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1743 /* Return 1 if there is no size conflict on any operands for
1744 instruction template T. */
1747 operand_size_match (const insn_template
*t
)
1752 /* Don't check jump instructions. */
1753 if (t
->opcode_modifier
.jump
1754 || t
->opcode_modifier
.jumpbyte
1755 || t
->opcode_modifier
.jumpdword
1756 || t
->opcode_modifier
.jumpintersegment
)
1759 /* Check memory and accumulator operand size. */
1760 for (j
= 0; j
< i
.operands
; j
++)
1762 if (t
->operand_types
[j
].bitfield
.anysize
)
1765 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1771 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1780 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1783 i
.error
= operand_size_mismatch
;
1787 /* Check reverse. */
1788 gas_assert (i
.operands
== 2);
1791 for (j
= 0; j
< 2; j
++)
1793 if (t
->operand_types
[j
].bitfield
.acc
1794 && !match_reg_size (t
, j
? 0 : 1))
1797 if (i
.types
[j
].bitfield
.mem
1798 && !match_mem_size (t
, j
? 0 : 1))
1806 operand_type_match (i386_operand_type overlap
,
1807 i386_operand_type given
)
1809 i386_operand_type temp
= overlap
;
1811 temp
.bitfield
.jumpabsolute
= 0;
1812 temp
.bitfield
.unspecified
= 0;
1813 temp
.bitfield
.byte
= 0;
1814 temp
.bitfield
.word
= 0;
1815 temp
.bitfield
.dword
= 0;
1816 temp
.bitfield
.fword
= 0;
1817 temp
.bitfield
.qword
= 0;
1818 temp
.bitfield
.tbyte
= 0;
1819 temp
.bitfield
.xmmword
= 0;
1820 temp
.bitfield
.ymmword
= 0;
1821 temp
.bitfield
.zmmword
= 0;
1822 if (operand_type_all_zero (&temp
))
1825 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1826 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1830 i
.error
= operand_type_mismatch
;
1834 /* If given types g0 and g1 are registers they must be of the same type
1835 unless the expected operand type register overlap is null.
1836 Note that Acc in a template matches every size of reg. */
1839 operand_type_register_match (i386_operand_type m0
,
1840 i386_operand_type g0
,
1841 i386_operand_type t0
,
1842 i386_operand_type m1
,
1843 i386_operand_type g1
,
1844 i386_operand_type t1
)
1846 if (!operand_type_check (g0
, reg
))
1849 if (!operand_type_check (g1
, reg
))
1852 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1853 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1854 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1855 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1858 if (m0
.bitfield
.acc
)
1860 t0
.bitfield
.reg8
= 1;
1861 t0
.bitfield
.reg16
= 1;
1862 t0
.bitfield
.reg32
= 1;
1863 t0
.bitfield
.reg64
= 1;
1866 if (m1
.bitfield
.acc
)
1868 t1
.bitfield
.reg8
= 1;
1869 t1
.bitfield
.reg16
= 1;
1870 t1
.bitfield
.reg32
= 1;
1871 t1
.bitfield
.reg64
= 1;
1874 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1875 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1876 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1877 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1880 i
.error
= register_type_mismatch
;
1885 static INLINE
unsigned int
1886 register_number (const reg_entry
*r
)
1888 unsigned int nr
= r
->reg_num
;
1890 if (r
->reg_flags
& RegRex
)
1893 if (r
->reg_flags
& RegVRex
)
1899 static INLINE
unsigned int
1900 mode_from_disp_size (i386_operand_type t
)
1902 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1904 else if (t
.bitfield
.disp16
1905 || t
.bitfield
.disp32
1906 || t
.bitfield
.disp32s
)
1913 fits_in_signed_byte (addressT num
)
1915 return num
+ 0x80 <= 0xff;
1919 fits_in_unsigned_byte (addressT num
)
1925 fits_in_unsigned_word (addressT num
)
1927 return num
<= 0xffff;
1931 fits_in_signed_word (addressT num
)
1933 return num
+ 0x8000 <= 0xffff;
1937 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1942 return num
+ 0x80000000 <= 0xffffffff;
1944 } /* fits_in_signed_long() */
1947 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1952 return num
<= 0xffffffff;
1954 } /* fits_in_unsigned_long() */
1957 fits_in_vec_disp8 (offsetT num
)
1959 int shift
= i
.memshift
;
1965 mask
= (1 << shift
) - 1;
1967 /* Return 0 if NUM isn't properly aligned. */
1971 /* Check if NUM will fit in 8bit after shift. */
1972 return fits_in_signed_byte (num
>> shift
);
1976 fits_in_imm4 (offsetT num
)
1978 return (num
& 0xf) == num
;
1981 static i386_operand_type
1982 smallest_imm_type (offsetT num
)
1984 i386_operand_type t
;
1986 operand_type_set (&t
, 0);
1987 t
.bitfield
.imm64
= 1;
1989 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1991 /* This code is disabled on the 486 because all the Imm1 forms
1992 in the opcode table are slower on the i486. They're the
1993 versions with the implicitly specified single-position
1994 displacement, which has another syntax if you really want to
1996 t
.bitfield
.imm1
= 1;
1997 t
.bitfield
.imm8
= 1;
1998 t
.bitfield
.imm8s
= 1;
1999 t
.bitfield
.imm16
= 1;
2000 t
.bitfield
.imm32
= 1;
2001 t
.bitfield
.imm32s
= 1;
2003 else if (fits_in_signed_byte (num
))
2005 t
.bitfield
.imm8
= 1;
2006 t
.bitfield
.imm8s
= 1;
2007 t
.bitfield
.imm16
= 1;
2008 t
.bitfield
.imm32
= 1;
2009 t
.bitfield
.imm32s
= 1;
2011 else if (fits_in_unsigned_byte (num
))
2013 t
.bitfield
.imm8
= 1;
2014 t
.bitfield
.imm16
= 1;
2015 t
.bitfield
.imm32
= 1;
2016 t
.bitfield
.imm32s
= 1;
2018 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2020 t
.bitfield
.imm16
= 1;
2021 t
.bitfield
.imm32
= 1;
2022 t
.bitfield
.imm32s
= 1;
2024 else if (fits_in_signed_long (num
))
2026 t
.bitfield
.imm32
= 1;
2027 t
.bitfield
.imm32s
= 1;
2029 else if (fits_in_unsigned_long (num
))
2030 t
.bitfield
.imm32
= 1;
2036 offset_in_range (offsetT val
, int size
)
2042 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2043 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2044 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2046 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2052 /* If BFD64, sign extend val for 32bit address mode. */
2053 if (flag_code
!= CODE_64BIT
2054 || i
.prefix
[ADDR_PREFIX
])
2055 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2056 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2059 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2061 char buf1
[40], buf2
[40];
2063 sprint_value (buf1
, val
);
2064 sprint_value (buf2
, val
& mask
);
2065 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2079 a. PREFIX_EXIST if attempting to add a prefix where one from the
2080 same class already exists.
2081 b. PREFIX_LOCK if lock prefix is added.
2082 c. PREFIX_REP if rep/repne prefix is added.
2083 d. PREFIX_OTHER if other prefix is added.
2086 static enum PREFIX_GROUP
2087 add_prefix (unsigned int prefix
)
2089 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2092 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2093 && flag_code
== CODE_64BIT
)
2095 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2096 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2097 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2108 case CS_PREFIX_OPCODE
:
2109 case DS_PREFIX_OPCODE
:
2110 case ES_PREFIX_OPCODE
:
2111 case FS_PREFIX_OPCODE
:
2112 case GS_PREFIX_OPCODE
:
2113 case SS_PREFIX_OPCODE
:
2117 case REPNE_PREFIX_OPCODE
:
2118 case REPE_PREFIX_OPCODE
:
2123 case LOCK_PREFIX_OPCODE
:
2132 case ADDR_PREFIX_OPCODE
:
2136 case DATA_PREFIX_OPCODE
:
2140 if (i
.prefix
[q
] != 0)
2148 i
.prefix
[q
] |= prefix
;
2151 as_bad (_("same type of prefix used twice"));
2157 update_code_flag (int value
, int check
)
2159 PRINTF_LIKE ((*as_error
));
2161 flag_code
= (enum flag_code
) value
;
2162 if (flag_code
== CODE_64BIT
)
2164 cpu_arch_flags
.bitfield
.cpu64
= 1;
2165 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2169 cpu_arch_flags
.bitfield
.cpu64
= 0;
2170 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2172 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2175 as_error
= as_fatal
;
2178 (*as_error
) (_("64bit mode not supported on `%s'."),
2179 cpu_arch_name
? cpu_arch_name
: default_arch
);
2181 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2184 as_error
= as_fatal
;
2187 (*as_error
) (_("32bit mode not supported on `%s'."),
2188 cpu_arch_name
? cpu_arch_name
: default_arch
);
2190 stackop_size
= '\0';
2194 set_code_flag (int value
)
2196 update_code_flag (value
, 0);
2200 set_16bit_gcc_code_flag (int new_code_flag
)
2202 flag_code
= (enum flag_code
) new_code_flag
;
2203 if (flag_code
!= CODE_16BIT
)
2205 cpu_arch_flags
.bitfield
.cpu64
= 0;
2206 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2207 stackop_size
= LONG_MNEM_SUFFIX
;
2211 set_intel_syntax (int syntax_flag
)
2213 /* Find out if register prefixing is specified. */
2214 int ask_naked_reg
= 0;
2217 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2220 int e
= get_symbol_name (&string
);
2222 if (strcmp (string
, "prefix") == 0)
2224 else if (strcmp (string
, "noprefix") == 0)
2227 as_bad (_("bad argument to syntax directive."));
2228 (void) restore_line_pointer (e
);
2230 demand_empty_rest_of_line ();
2232 intel_syntax
= syntax_flag
;
2234 if (ask_naked_reg
== 0)
2235 allow_naked_reg
= (intel_syntax
2236 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2238 allow_naked_reg
= (ask_naked_reg
< 0);
2240 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2242 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2243 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2244 register_prefix
= allow_naked_reg
? "" : "%";
2248 set_intel_mnemonic (int mnemonic_flag
)
2250 intel_mnemonic
= mnemonic_flag
;
2254 set_allow_index_reg (int flag
)
2256 allow_index_reg
= flag
;
2260 set_check (int what
)
2262 enum check_kind
*kind
;
2267 kind
= &operand_check
;
2278 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2281 int e
= get_symbol_name (&string
);
2283 if (strcmp (string
, "none") == 0)
2285 else if (strcmp (string
, "warning") == 0)
2286 *kind
= check_warning
;
2287 else if (strcmp (string
, "error") == 0)
2288 *kind
= check_error
;
2290 as_bad (_("bad argument to %s_check directive."), str
);
2291 (void) restore_line_pointer (e
);
2294 as_bad (_("missing argument for %s_check directive"), str
);
2296 demand_empty_rest_of_line ();
2300 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2301 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2303 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2304 static const char *arch
;
2306 /* Intel LIOM is only supported on ELF. */
2312 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2313 use default_arch. */
2314 arch
= cpu_arch_name
;
2316 arch
= default_arch
;
2319 /* If we are targeting Intel MCU, we must enable it. */
2320 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2321 || new_flag
.bitfield
.cpuiamcu
)
2324 /* If we are targeting Intel L1OM, we must enable it. */
2325 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2326 || new_flag
.bitfield
.cpul1om
)
2329 /* If we are targeting Intel K1OM, we must enable it. */
2330 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2331 || new_flag
.bitfield
.cpuk1om
)
2334 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2339 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2343 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2346 int e
= get_symbol_name (&string
);
2348 i386_cpu_flags flags
;
2350 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2352 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2354 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2358 cpu_arch_name
= cpu_arch
[j
].name
;
2359 cpu_sub_arch_name
= NULL
;
2360 cpu_arch_flags
= cpu_arch
[j
].flags
;
2361 if (flag_code
== CODE_64BIT
)
2363 cpu_arch_flags
.bitfield
.cpu64
= 1;
2364 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2368 cpu_arch_flags
.bitfield
.cpu64
= 0;
2369 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2371 cpu_arch_isa
= cpu_arch
[j
].type
;
2372 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2373 if (!cpu_arch_tune_set
)
2375 cpu_arch_tune
= cpu_arch_isa
;
2376 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2381 flags
= cpu_flags_or (cpu_arch_flags
,
2384 if (!valid_iamcu_cpu_flags (&flags
))
2385 as_fatal (_("`%s' isn't valid for Intel MCU"),
2387 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2389 if (cpu_sub_arch_name
)
2391 char *name
= cpu_sub_arch_name
;
2392 cpu_sub_arch_name
= concat (name
,
2394 (const char *) NULL
);
2398 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2399 cpu_arch_flags
= flags
;
2400 cpu_arch_isa_flags
= flags
;
2402 (void) restore_line_pointer (e
);
2403 demand_empty_rest_of_line ();
2408 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2410 /* Disable an ISA entension. */
2411 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2412 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2414 flags
= cpu_flags_and_not (cpu_arch_flags
,
2415 cpu_noarch
[j
].flags
);
2416 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2418 if (cpu_sub_arch_name
)
2420 char *name
= cpu_sub_arch_name
;
2421 cpu_sub_arch_name
= concat (name
, string
,
2422 (const char *) NULL
);
2426 cpu_sub_arch_name
= xstrdup (string
);
2427 cpu_arch_flags
= flags
;
2428 cpu_arch_isa_flags
= flags
;
2430 (void) restore_line_pointer (e
);
2431 demand_empty_rest_of_line ();
2435 j
= ARRAY_SIZE (cpu_arch
);
2438 if (j
>= ARRAY_SIZE (cpu_arch
))
2439 as_bad (_("no such architecture: `%s'"), string
);
2441 *input_line_pointer
= e
;
2444 as_bad (_("missing cpu architecture"));
2446 no_cond_jump_promotion
= 0;
2447 if (*input_line_pointer
== ','
2448 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2453 ++input_line_pointer
;
2454 e
= get_symbol_name (&string
);
2456 if (strcmp (string
, "nojumps") == 0)
2457 no_cond_jump_promotion
= 1;
2458 else if (strcmp (string
, "jumps") == 0)
2461 as_bad (_("no such architecture modifier: `%s'"), string
);
2463 (void) restore_line_pointer (e
);
2466 demand_empty_rest_of_line ();
2469 enum bfd_architecture
2472 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2474 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2475 || flag_code
!= CODE_64BIT
)
2476 as_fatal (_("Intel L1OM is 64bit ELF only"));
2477 return bfd_arch_l1om
;
2479 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2481 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2482 || flag_code
!= CODE_64BIT
)
2483 as_fatal (_("Intel K1OM is 64bit ELF only"));
2484 return bfd_arch_k1om
;
2486 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2488 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2489 || flag_code
== CODE_64BIT
)
2490 as_fatal (_("Intel MCU is 32bit ELF only"));
2491 return bfd_arch_iamcu
;
2494 return bfd_arch_i386
;
2500 if (!strncmp (default_arch
, "x86_64", 6))
2502 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2504 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2505 || default_arch
[6] != '\0')
2506 as_fatal (_("Intel L1OM is 64bit ELF only"));
2507 return bfd_mach_l1om
;
2509 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2511 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2512 || default_arch
[6] != '\0')
2513 as_fatal (_("Intel K1OM is 64bit ELF only"));
2514 return bfd_mach_k1om
;
2516 else if (default_arch
[6] == '\0')
2517 return bfd_mach_x86_64
;
2519 return bfd_mach_x64_32
;
2521 else if (!strcmp (default_arch
, "i386")
2522 || !strcmp (default_arch
, "iamcu"))
2524 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2526 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2527 as_fatal (_("Intel MCU is 32bit ELF only"));
2528 return bfd_mach_i386_iamcu
;
2531 return bfd_mach_i386_i386
;
2534 as_fatal (_("unknown architecture"));
2540 const char *hash_err
;
2542 /* Initialize op_hash hash table. */
2543 op_hash
= hash_new ();
2546 const insn_template
*optab
;
2547 templates
*core_optab
;
2549 /* Setup for loop. */
2551 core_optab
= XNEW (templates
);
2552 core_optab
->start
= optab
;
2557 if (optab
->name
== NULL
2558 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2560 /* different name --> ship out current template list;
2561 add to hash table; & begin anew. */
2562 core_optab
->end
= optab
;
2563 hash_err
= hash_insert (op_hash
,
2565 (void *) core_optab
);
2568 as_fatal (_("can't hash %s: %s"),
2572 if (optab
->name
== NULL
)
2574 core_optab
= XNEW (templates
);
2575 core_optab
->start
= optab
;
2580 /* Initialize reg_hash hash table. */
2581 reg_hash
= hash_new ();
2583 const reg_entry
*regtab
;
2584 unsigned int regtab_size
= i386_regtab_size
;
2586 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2588 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2590 as_fatal (_("can't hash %s: %s"),
2596 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2601 for (c
= 0; c
< 256; c
++)
2606 mnemonic_chars
[c
] = c
;
2607 register_chars
[c
] = c
;
2608 operand_chars
[c
] = c
;
2610 else if (ISLOWER (c
))
2612 mnemonic_chars
[c
] = c
;
2613 register_chars
[c
] = c
;
2614 operand_chars
[c
] = c
;
2616 else if (ISUPPER (c
))
2618 mnemonic_chars
[c
] = TOLOWER (c
);
2619 register_chars
[c
] = mnemonic_chars
[c
];
2620 operand_chars
[c
] = c
;
2622 else if (c
== '{' || c
== '}')
2623 operand_chars
[c
] = c
;
2625 if (ISALPHA (c
) || ISDIGIT (c
))
2626 identifier_chars
[c
] = c
;
2629 identifier_chars
[c
] = c
;
2630 operand_chars
[c
] = c
;
2635 identifier_chars
['@'] = '@';
2638 identifier_chars
['?'] = '?';
2639 operand_chars
['?'] = '?';
2641 digit_chars
['-'] = '-';
2642 mnemonic_chars
['_'] = '_';
2643 mnemonic_chars
['-'] = '-';
2644 mnemonic_chars
['.'] = '.';
2645 identifier_chars
['_'] = '_';
2646 identifier_chars
['.'] = '.';
2648 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2649 operand_chars
[(unsigned char) *p
] = *p
;
2652 if (flag_code
== CODE_64BIT
)
2654 #if defined (OBJ_COFF) && defined (TE_PE)
2655 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2658 x86_dwarf2_return_column
= 16;
2660 x86_cie_data_alignment
= -8;
2664 x86_dwarf2_return_column
= 8;
2665 x86_cie_data_alignment
= -4;
2670 i386_print_statistics (FILE *file
)
2672 hash_print_statistics (file
, "i386 opcode", op_hash
);
2673 hash_print_statistics (file
, "i386 register", reg_hash
);
2678 /* Debugging routines for md_assemble. */
2679 static void pte (insn_template
*);
2680 static void pt (i386_operand_type
);
2681 static void pe (expressionS
*);
2682 static void ps (symbolS
*);
2685 pi (char *line
, i386_insn
*x
)
2689 fprintf (stdout
, "%s: template ", line
);
2691 fprintf (stdout
, " address: base %s index %s scale %x\n",
2692 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2693 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2694 x
->log2_scale_factor
);
2695 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2696 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2697 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2698 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2699 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2700 (x
->rex
& REX_W
) != 0,
2701 (x
->rex
& REX_R
) != 0,
2702 (x
->rex
& REX_X
) != 0,
2703 (x
->rex
& REX_B
) != 0);
2704 for (j
= 0; j
< x
->operands
; j
++)
2706 fprintf (stdout
, " #%d: ", j
+ 1);
2708 fprintf (stdout
, "\n");
2709 if (x
->types
[j
].bitfield
.reg8
2710 || x
->types
[j
].bitfield
.reg16
2711 || x
->types
[j
].bitfield
.reg32
2712 || x
->types
[j
].bitfield
.reg64
2713 || x
->types
[j
].bitfield
.regmmx
2714 || x
->types
[j
].bitfield
.regxmm
2715 || x
->types
[j
].bitfield
.regymm
2716 || x
->types
[j
].bitfield
.regzmm
2717 || x
->types
[j
].bitfield
.sreg2
2718 || x
->types
[j
].bitfield
.sreg3
2719 || x
->types
[j
].bitfield
.control
2720 || x
->types
[j
].bitfield
.debug
2721 || x
->types
[j
].bitfield
.test
)
2722 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2723 if (operand_type_check (x
->types
[j
], imm
))
2725 if (operand_type_check (x
->types
[j
], disp
))
2726 pe (x
->op
[j
].disps
);
2731 pte (insn_template
*t
)
2734 fprintf (stdout
, " %d operands ", t
->operands
);
2735 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2736 if (t
->extension_opcode
!= None
)
2737 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2738 if (t
->opcode_modifier
.d
)
2739 fprintf (stdout
, "D");
2740 if (t
->opcode_modifier
.w
)
2741 fprintf (stdout
, "W");
2742 fprintf (stdout
, "\n");
2743 for (j
= 0; j
< t
->operands
; j
++)
2745 fprintf (stdout
, " #%d type ", j
+ 1);
2746 pt (t
->operand_types
[j
]);
2747 fprintf (stdout
, "\n");
2754 fprintf (stdout
, " operation %d\n", e
->X_op
);
2755 fprintf (stdout
, " add_number %ld (%lx)\n",
2756 (long) e
->X_add_number
, (long) e
->X_add_number
);
2757 if (e
->X_add_symbol
)
2759 fprintf (stdout
, " add_symbol ");
2760 ps (e
->X_add_symbol
);
2761 fprintf (stdout
, "\n");
2765 fprintf (stdout
, " op_symbol ");
2766 ps (e
->X_op_symbol
);
2767 fprintf (stdout
, "\n");
2774 fprintf (stdout
, "%s type %s%s",
2776 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2777 segment_name (S_GET_SEGMENT (s
)));
2780 static struct type_name
2782 i386_operand_type mask
;
2785 const type_names
[] =
2787 { OPERAND_TYPE_REG8
, "r8" },
2788 { OPERAND_TYPE_REG16
, "r16" },
2789 { OPERAND_TYPE_REG32
, "r32" },
2790 { OPERAND_TYPE_REG64
, "r64" },
2791 { OPERAND_TYPE_IMM8
, "i8" },
2792 { OPERAND_TYPE_IMM8
, "i8s" },
2793 { OPERAND_TYPE_IMM16
, "i16" },
2794 { OPERAND_TYPE_IMM32
, "i32" },
2795 { OPERAND_TYPE_IMM32S
, "i32s" },
2796 { OPERAND_TYPE_IMM64
, "i64" },
2797 { OPERAND_TYPE_IMM1
, "i1" },
2798 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2799 { OPERAND_TYPE_DISP8
, "d8" },
2800 { OPERAND_TYPE_DISP16
, "d16" },
2801 { OPERAND_TYPE_DISP32
, "d32" },
2802 { OPERAND_TYPE_DISP32S
, "d32s" },
2803 { OPERAND_TYPE_DISP64
, "d64" },
2804 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2805 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2806 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2807 { OPERAND_TYPE_CONTROL
, "control reg" },
2808 { OPERAND_TYPE_TEST
, "test reg" },
2809 { OPERAND_TYPE_DEBUG
, "debug reg" },
2810 { OPERAND_TYPE_FLOATREG
, "FReg" },
2811 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2812 { OPERAND_TYPE_SREG2
, "SReg2" },
2813 { OPERAND_TYPE_SREG3
, "SReg3" },
2814 { OPERAND_TYPE_ACC
, "Acc" },
2815 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2816 { OPERAND_TYPE_REGMMX
, "rMMX" },
2817 { OPERAND_TYPE_REGXMM
, "rXMM" },
2818 { OPERAND_TYPE_REGYMM
, "rYMM" },
2819 { OPERAND_TYPE_REGZMM
, "rZMM" },
2820 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2821 { OPERAND_TYPE_ESSEG
, "es" },
2825 pt (i386_operand_type t
)
2828 i386_operand_type a
;
2830 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2832 a
= operand_type_and (t
, type_names
[j
].mask
);
2833 if (!operand_type_all_zero (&a
))
2834 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2839 #endif /* DEBUG386 */
2841 static bfd_reloc_code_real_type
2842 reloc (unsigned int size
,
2845 bfd_reloc_code_real_type other
)
2847 if (other
!= NO_RELOC
)
2849 reloc_howto_type
*rel
;
2854 case BFD_RELOC_X86_64_GOT32
:
2855 return BFD_RELOC_X86_64_GOT64
;
2857 case BFD_RELOC_X86_64_GOTPLT64
:
2858 return BFD_RELOC_X86_64_GOTPLT64
;
2860 case BFD_RELOC_X86_64_PLTOFF64
:
2861 return BFD_RELOC_X86_64_PLTOFF64
;
2863 case BFD_RELOC_X86_64_GOTPC32
:
2864 other
= BFD_RELOC_X86_64_GOTPC64
;
2866 case BFD_RELOC_X86_64_GOTPCREL
:
2867 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2869 case BFD_RELOC_X86_64_TPOFF32
:
2870 other
= BFD_RELOC_X86_64_TPOFF64
;
2872 case BFD_RELOC_X86_64_DTPOFF32
:
2873 other
= BFD_RELOC_X86_64_DTPOFF64
;
2879 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2880 if (other
== BFD_RELOC_SIZE32
)
2883 other
= BFD_RELOC_SIZE64
;
2886 as_bad (_("there are no pc-relative size relocations"));
2892 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2893 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2896 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2898 as_bad (_("unknown relocation (%u)"), other
);
2899 else if (size
!= bfd_get_reloc_size (rel
))
2900 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2901 bfd_get_reloc_size (rel
),
2903 else if (pcrel
&& !rel
->pc_relative
)
2904 as_bad (_("non-pc-relative relocation for pc-relative field"));
2905 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2907 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2909 as_bad (_("relocated field and relocation type differ in signedness"));
2918 as_bad (_("there are no unsigned pc-relative relocations"));
2921 case 1: return BFD_RELOC_8_PCREL
;
2922 case 2: return BFD_RELOC_16_PCREL
;
2923 case 4: return BFD_RELOC_32_PCREL
;
2924 case 8: return BFD_RELOC_64_PCREL
;
2926 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2933 case 4: return BFD_RELOC_X86_64_32S
;
2938 case 1: return BFD_RELOC_8
;
2939 case 2: return BFD_RELOC_16
;
2940 case 4: return BFD_RELOC_32
;
2941 case 8: return BFD_RELOC_64
;
2943 as_bad (_("cannot do %s %u byte relocation"),
2944 sign
> 0 ? "signed" : "unsigned", size
);
2950 /* Here we decide which fixups can be adjusted to make them relative to
2951 the beginning of the section instead of the symbol. Basically we need
2952 to make sure that the dynamic relocations are done correctly, so in
2953 some cases we force the original symbol to be used. */
2956 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2958 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2962 /* Don't adjust pc-relative references to merge sections in 64-bit
2964 if (use_rela_relocations
2965 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2969 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2970 and changed later by validate_fix. */
2971 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2972 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2975 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2976 for size relocations. */
2977 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2978 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2979 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2980 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2981 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2982 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
2983 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2984 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2985 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2986 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2987 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2988 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2989 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2990 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2991 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2992 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2993 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2994 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2995 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2996 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
2997 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
2998 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2999 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3000 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3001 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3002 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3003 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3004 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3005 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3006 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3007 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3008 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3009 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3016 intel_float_operand (const char *mnemonic
)
3018 /* Note that the value returned is meaningful only for opcodes with (memory)
3019 operands, hence the code here is free to improperly handle opcodes that
3020 have no operands (for better performance and smaller code). */
3022 if (mnemonic
[0] != 'f')
3023 return 0; /* non-math */
3025 switch (mnemonic
[1])
3027 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3028 the fs segment override prefix not currently handled because no
3029 call path can make opcodes without operands get here */
3031 return 2 /* integer op */;
3033 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3034 return 3; /* fldcw/fldenv */
3037 if (mnemonic
[2] != 'o' /* fnop */)
3038 return 3; /* non-waiting control op */
3041 if (mnemonic
[2] == 's')
3042 return 3; /* frstor/frstpm */
3045 if (mnemonic
[2] == 'a')
3046 return 3; /* fsave */
3047 if (mnemonic
[2] == 't')
3049 switch (mnemonic
[3])
3051 case 'c': /* fstcw */
3052 case 'd': /* fstdw */
3053 case 'e': /* fstenv */
3054 case 's': /* fsts[gw] */
3060 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3061 return 0; /* fxsave/fxrstor are not really math ops */
3068 /* Build the VEX prefix. */
3071 build_vex_prefix (const insn_template
*t
)
3073 unsigned int register_specifier
;
3074 unsigned int implied_prefix
;
3075 unsigned int vector_length
;
3077 /* Check register specifier. */
3078 if (i
.vex
.register_specifier
)
3080 register_specifier
=
3081 ~register_number (i
.vex
.register_specifier
) & 0xf;
3082 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3085 register_specifier
= 0xf;
3087 /* Use 2-byte VEX prefix by swappping destination and source
3090 && i
.operands
== i
.reg_operands
3091 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3092 && i
.tm
.opcode_modifier
.s
3095 unsigned int xchg
= i
.operands
- 1;
3096 union i386_op temp_op
;
3097 i386_operand_type temp_type
;
3099 temp_type
= i
.types
[xchg
];
3100 i
.types
[xchg
] = i
.types
[0];
3101 i
.types
[0] = temp_type
;
3102 temp_op
= i
.op
[xchg
];
3103 i
.op
[xchg
] = i
.op
[0];
3106 gas_assert (i
.rm
.mode
== 3);
3110 i
.rm
.regmem
= i
.rm
.reg
;
3113 /* Use the next insn. */
3117 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3118 vector_length
= avxscalar
;
3120 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3122 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3127 case DATA_PREFIX_OPCODE
:
3130 case REPE_PREFIX_OPCODE
:
3133 case REPNE_PREFIX_OPCODE
:
3140 /* Use 2-byte VEX prefix if possible. */
3141 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3142 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3143 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3145 /* 2-byte VEX prefix. */
3149 i
.vex
.bytes
[0] = 0xc5;
3151 /* Check the REX.R bit. */
3152 r
= (i
.rex
& REX_R
) ? 0 : 1;
3153 i
.vex
.bytes
[1] = (r
<< 7
3154 | register_specifier
<< 3
3155 | vector_length
<< 2
3160 /* 3-byte VEX prefix. */
3165 switch (i
.tm
.opcode_modifier
.vexopcode
)
3169 i
.vex
.bytes
[0] = 0xc4;
3173 i
.vex
.bytes
[0] = 0xc4;
3177 i
.vex
.bytes
[0] = 0xc4;
3181 i
.vex
.bytes
[0] = 0x8f;
3185 i
.vex
.bytes
[0] = 0x8f;
3189 i
.vex
.bytes
[0] = 0x8f;
3195 /* The high 3 bits of the second VEX byte are 1's compliment
3196 of RXB bits from REX. */
3197 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3199 /* Check the REX.W bit. */
3200 w
= (i
.rex
& REX_W
) ? 1 : 0;
3201 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3204 i
.vex
.bytes
[2] = (w
<< 7
3205 | register_specifier
<< 3
3206 | vector_length
<< 2
3211 /* Build the EVEX prefix. */
3214 build_evex_prefix (void)
3216 unsigned int register_specifier
;
3217 unsigned int implied_prefix
;
3219 rex_byte vrex_used
= 0;
3221 /* Check register specifier. */
3222 if (i
.vex
.register_specifier
)
3224 gas_assert ((i
.vrex
& REX_X
) == 0);
3226 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3227 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3228 register_specifier
+= 8;
3229 /* The upper 16 registers are encoded in the fourth byte of the
3231 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3232 i
.vex
.bytes
[3] = 0x8;
3233 register_specifier
= ~register_specifier
& 0xf;
3237 register_specifier
= 0xf;
3239 /* Encode upper 16 vector index register in the fourth byte of
3241 if (!(i
.vrex
& REX_X
))
3242 i
.vex
.bytes
[3] = 0x8;
3247 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3252 case DATA_PREFIX_OPCODE
:
3255 case REPE_PREFIX_OPCODE
:
3258 case REPNE_PREFIX_OPCODE
:
3265 /* 4 byte EVEX prefix. */
3267 i
.vex
.bytes
[0] = 0x62;
3270 switch (i
.tm
.opcode_modifier
.vexopcode
)
3286 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3288 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3290 /* The fifth bit of the second EVEX byte is 1's compliment of the
3291 REX_R bit in VREX. */
3292 if (!(i
.vrex
& REX_R
))
3293 i
.vex
.bytes
[1] |= 0x10;
3297 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3299 /* When all operands are registers, the REX_X bit in REX is not
3300 used. We reuse it to encode the upper 16 registers, which is
3301 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3302 as 1's compliment. */
3303 if ((i
.vrex
& REX_B
))
3306 i
.vex
.bytes
[1] &= ~0x40;
3310 /* EVEX instructions shouldn't need the REX prefix. */
3311 i
.vrex
&= ~vrex_used
;
3312 gas_assert (i
.vrex
== 0);
3314 /* Check the REX.W bit. */
3315 w
= (i
.rex
& REX_W
) ? 1 : 0;
3316 if (i
.tm
.opcode_modifier
.vexw
)
3318 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3321 /* If w is not set it means we are dealing with WIG instruction. */
3324 if (evexwig
== evexw1
)
3328 /* Encode the U bit. */
3329 implied_prefix
|= 0x4;
3331 /* The third byte of the EVEX prefix. */
3332 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3334 /* The fourth byte of the EVEX prefix. */
3335 /* The zeroing-masking bit. */
3336 if (i
.mask
&& i
.mask
->zeroing
)
3337 i
.vex
.bytes
[3] |= 0x80;
3339 /* Don't always set the broadcast bit if there is no RC. */
3342 /* Encode the vector length. */
3343 unsigned int vec_length
;
3345 switch (i
.tm
.opcode_modifier
.evex
)
3347 case EVEXLIG
: /* LL' is ignored */
3348 vec_length
= evexlig
<< 5;
3351 vec_length
= 0 << 5;
3354 vec_length
= 1 << 5;
3357 vec_length
= 2 << 5;
3363 i
.vex
.bytes
[3] |= vec_length
;
3364 /* Encode the broadcast bit. */
3366 i
.vex
.bytes
[3] |= 0x10;
3370 if (i
.rounding
->type
!= saeonly
)
3371 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3373 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3376 if (i
.mask
&& i
.mask
->mask
)
3377 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3381 process_immext (void)
3385 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3388 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3389 with an opcode suffix which is coded in the same place as an
3390 8-bit immediate field would be.
3391 Here we check those operands and remove them afterwards. */
3394 for (x
= 0; x
< i
.operands
; x
++)
3395 if (register_number (i
.op
[x
].regs
) != x
)
3396 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3397 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3403 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3405 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3406 suffix which is coded in the same place as an 8-bit immediate
3408 Here we check those operands and remove them afterwards. */
3411 if (i
.operands
!= 3)
3414 for (x
= 0; x
< 2; x
++)
3415 if (register_number (i
.op
[x
].regs
) != x
)
3416 goto bad_register_operand
;
3418 /* Check for third operand for mwaitx/monitorx insn. */
3419 if (register_number (i
.op
[x
].regs
)
3420 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3422 bad_register_operand
:
3423 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3424 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3431 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3432 which is coded in the same place as an 8-bit immediate field
3433 would be. Here we fake an 8-bit immediate operand from the
3434 opcode suffix stored in tm.extension_opcode.
3436 AVX instructions also use this encoding, for some of
3437 3 argument instructions. */
3439 gas_assert (i
.imm_operands
<= 1
3441 || ((i
.tm
.opcode_modifier
.vex
3442 || i
.tm
.opcode_modifier
.evex
)
3443 && i
.operands
<= 4)));
3445 exp
= &im_expressions
[i
.imm_operands
++];
3446 i
.op
[i
.operands
].imms
= exp
;
3447 i
.types
[i
.operands
] = imm8
;
3449 exp
->X_op
= O_constant
;
3450 exp
->X_add_number
= i
.tm
.extension_opcode
;
3451 i
.tm
.extension_opcode
= None
;
3458 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3463 as_bad (_("invalid instruction `%s' after `%s'"),
3464 i
.tm
.name
, i
.hle_prefix
);
3467 if (i
.prefix
[LOCK_PREFIX
])
3469 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3473 case HLEPrefixRelease
:
3474 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3476 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3480 if (i
.mem_operands
== 0
3481 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3483 as_bad (_("memory destination needed for instruction `%s'"
3484 " after `xrelease'"), i
.tm
.name
);
3491 /* This is the guts of the machine-dependent assembler. LINE points to a
3492 machine dependent instruction. This function is supposed to emit
3493 the frags/bytes it assembles to. */
3496 md_assemble (char *line
)
3499 char mnemonic
[MAX_MNEM_SIZE
];
3500 const insn_template
*t
;
3502 /* Initialize globals. */
3503 memset (&i
, '\0', sizeof (i
));
3504 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3505 i
.reloc
[j
] = NO_RELOC
;
3506 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3507 memset (im_expressions
, '\0', sizeof (im_expressions
));
3508 save_stack_p
= save_stack
;
3510 /* First parse an instruction mnemonic & call i386_operand for the operands.
3511 We assume that the scrubber has arranged it so that line[0] is the valid
3512 start of a (possibly prefixed) mnemonic. */
3514 line
= parse_insn (line
, mnemonic
);
3518 line
= parse_operands (line
, mnemonic
);
3523 /* Now we've parsed the mnemonic into a set of templates, and have the
3524 operands at hand. */
3526 /* All intel opcodes have reversed operands except for "bound" and
3527 "enter". We also don't reverse intersegment "jmp" and "call"
3528 instructions with 2 immediate operands so that the immediate segment
3529 precedes the offset, as it does when in AT&T mode. */
3532 && (strcmp (mnemonic
, "bound") != 0)
3533 && (strcmp (mnemonic
, "invlpga") != 0)
3534 && !(operand_type_check (i
.types
[0], imm
)
3535 && operand_type_check (i
.types
[1], imm
)))
3538 /* The order of the immediates should be reversed
3539 for 2 immediates extrq and insertq instructions */
3540 if (i
.imm_operands
== 2
3541 && (strcmp (mnemonic
, "extrq") == 0
3542 || strcmp (mnemonic
, "insertq") == 0))
3543 swap_2_operands (0, 1);
3548 /* Don't optimize displacement for movabs since it only takes 64bit
3551 && i
.disp_encoding
!= disp_encoding_32bit
3552 && (flag_code
!= CODE_64BIT
3553 || strcmp (mnemonic
, "movabs") != 0))
3556 /* Next, we find a template that matches the given insn,
3557 making sure the overlap of the given operands types is consistent
3558 with the template operand types. */
3560 if (!(t
= match_template ()))
3563 if (sse_check
!= check_none
3564 && !i
.tm
.opcode_modifier
.noavx
3565 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3566 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3567 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3568 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3569 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3570 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3572 (sse_check
== check_warning
3574 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3577 /* Zap movzx and movsx suffix. The suffix has been set from
3578 "word ptr" or "byte ptr" on the source operand in Intel syntax
3579 or extracted from mnemonic in AT&T syntax. But we'll use
3580 the destination register to choose the suffix for encoding. */
3581 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3583 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3584 there is no suffix, the default will be byte extension. */
3585 if (i
.reg_operands
!= 2
3588 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3593 if (i
.tm
.opcode_modifier
.fwait
)
3594 if (!add_prefix (FWAIT_OPCODE
))
3597 /* Check if REP prefix is OK. */
3598 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3600 as_bad (_("invalid instruction `%s' after `%s'"),
3601 i
.tm
.name
, i
.rep_prefix
);
3605 /* Check for lock without a lockable instruction. Destination operand
3606 must be memory unless it is xchg (0x86). */
3607 if (i
.prefix
[LOCK_PREFIX
]
3608 && (!i
.tm
.opcode_modifier
.islockable
3609 || i
.mem_operands
== 0
3610 || (i
.tm
.base_opcode
!= 0x86
3611 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3613 as_bad (_("expecting lockable instruction after `lock'"));
3617 /* Check if HLE prefix is OK. */
3618 if (i
.hle_prefix
&& !check_hle ())
3621 /* Check BND prefix. */
3622 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3623 as_bad (_("expecting valid branch instruction after `bnd'"));
3625 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3626 && flag_code
== CODE_64BIT
3627 && i
.prefix
[ADDR_PREFIX
])
3628 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3630 /* Insert BND prefix. */
3632 && i
.tm
.opcode_modifier
.bndprefixok
3633 && !i
.prefix
[BND_PREFIX
])
3634 add_prefix (BND_PREFIX_OPCODE
);
3636 /* Check string instruction segment overrides. */
3637 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3639 if (!check_string ())
3641 i
.disp_operands
= 0;
3644 if (!process_suffix ())
3647 /* Update operand types. */
3648 for (j
= 0; j
< i
.operands
; j
++)
3649 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3651 /* Make still unresolved immediate matches conform to size of immediate
3652 given in i.suffix. */
3653 if (!finalize_imm ())
3656 if (i
.types
[0].bitfield
.imm1
)
3657 i
.imm_operands
= 0; /* kludge for shift insns. */
3659 /* We only need to check those implicit registers for instructions
3660 with 3 operands or less. */
3661 if (i
.operands
<= 3)
3662 for (j
= 0; j
< i
.operands
; j
++)
3663 if (i
.types
[j
].bitfield
.inoutportreg
3664 || i
.types
[j
].bitfield
.shiftcount
3665 || i
.types
[j
].bitfield
.acc
3666 || i
.types
[j
].bitfield
.floatacc
)
3669 /* ImmExt should be processed after SSE2AVX. */
3670 if (!i
.tm
.opcode_modifier
.sse2avx
3671 && i
.tm
.opcode_modifier
.immext
)
3674 /* For insns with operands there are more diddles to do to the opcode. */
3677 if (!process_operands ())
3680 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3682 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3683 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3686 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3688 if (flag_code
== CODE_16BIT
)
3690 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3695 if (i
.tm
.opcode_modifier
.vex
)
3696 build_vex_prefix (t
);
3698 build_evex_prefix ();
3701 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3702 instructions may define INT_OPCODE as well, so avoid this corner
3703 case for those instructions that use MODRM. */
3704 if (i
.tm
.base_opcode
== INT_OPCODE
3705 && !i
.tm
.opcode_modifier
.modrm
3706 && i
.op
[0].imms
->X_add_number
== 3)
3708 i
.tm
.base_opcode
= INT3_OPCODE
;
3712 if ((i
.tm
.opcode_modifier
.jump
3713 || i
.tm
.opcode_modifier
.jumpbyte
3714 || i
.tm
.opcode_modifier
.jumpdword
)
3715 && i
.op
[0].disps
->X_op
== O_constant
)
3717 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3718 the absolute address given by the constant. Since ix86 jumps and
3719 calls are pc relative, we need to generate a reloc. */
3720 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3721 i
.op
[0].disps
->X_op
= O_symbol
;
3724 if (i
.tm
.opcode_modifier
.rex64
)
3727 /* For 8 bit registers we need an empty rex prefix. Also if the
3728 instruction already has a prefix, we need to convert old
3729 registers to new ones. */
3731 if ((i
.types
[0].bitfield
.reg8
3732 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3733 || (i
.types
[1].bitfield
.reg8
3734 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3735 || ((i
.types
[0].bitfield
.reg8
3736 || i
.types
[1].bitfield
.reg8
)
3741 i
.rex
|= REX_OPCODE
;
3742 for (x
= 0; x
< 2; x
++)
3744 /* Look for 8 bit operand that uses old registers. */
3745 if (i
.types
[x
].bitfield
.reg8
3746 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3748 /* In case it is "hi" register, give up. */
3749 if (i
.op
[x
].regs
->reg_num
> 3)
3750 as_bad (_("can't encode register '%s%s' in an "
3751 "instruction requiring REX prefix."),
3752 register_prefix
, i
.op
[x
].regs
->reg_name
);
3754 /* Otherwise it is equivalent to the extended register.
3755 Since the encoding doesn't change this is merely
3756 cosmetic cleanup for debug output. */
3758 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3764 add_prefix (REX_OPCODE
| i
.rex
);
3766 /* We are ready to output the insn. */
3771 parse_insn (char *line
, char *mnemonic
)
3774 char *token_start
= l
;
3777 const insn_template
*t
;
3783 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3788 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3790 as_bad (_("no such instruction: `%s'"), token_start
);
3795 if (!is_space_char (*l
)
3796 && *l
!= END_OF_INSN
3798 || (*l
!= PREFIX_SEPARATOR
3801 as_bad (_("invalid character %s in mnemonic"),
3802 output_invalid (*l
));
3805 if (token_start
== l
)
3807 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3808 as_bad (_("expecting prefix; got nothing"));
3810 as_bad (_("expecting mnemonic; got nothing"));
3814 /* Look up instruction (or prefix) via hash table. */
3815 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3817 if (*l
!= END_OF_INSN
3818 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3819 && current_templates
3820 && current_templates
->start
->opcode_modifier
.isprefix
)
3822 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3824 as_bad ((flag_code
!= CODE_64BIT
3825 ? _("`%s' is only supported in 64-bit mode")
3826 : _("`%s' is not supported in 64-bit mode")),
3827 current_templates
->start
->name
);
3830 /* If we are in 16-bit mode, do not allow addr16 or data16.
3831 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3832 if ((current_templates
->start
->opcode_modifier
.size16
3833 || current_templates
->start
->opcode_modifier
.size32
)
3834 && flag_code
!= CODE_64BIT
3835 && (current_templates
->start
->opcode_modifier
.size32
3836 ^ (flag_code
== CODE_16BIT
)))
3838 as_bad (_("redundant %s prefix"),
3839 current_templates
->start
->name
);
3842 /* Add prefix, checking for repeated prefixes. */
3843 switch (add_prefix (current_templates
->start
->base_opcode
))
3848 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3849 i
.hle_prefix
= current_templates
->start
->name
;
3850 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3851 i
.bnd_prefix
= current_templates
->start
->name
;
3853 i
.rep_prefix
= current_templates
->start
->name
;
3858 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3865 if (!current_templates
)
3867 /* Check if we should swap operand or force 32bit displacement in
3869 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3871 else if (mnem_p
- 3 == dot_p
3874 i
.disp_encoding
= disp_encoding_8bit
;
3875 else if (mnem_p
- 4 == dot_p
3879 i
.disp_encoding
= disp_encoding_32bit
;
3884 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3887 if (!current_templates
)
3890 /* See if we can get a match by trimming off a suffix. */
3893 case WORD_MNEM_SUFFIX
:
3894 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3895 i
.suffix
= SHORT_MNEM_SUFFIX
;
3897 case BYTE_MNEM_SUFFIX
:
3898 case QWORD_MNEM_SUFFIX
:
3899 i
.suffix
= mnem_p
[-1];
3901 current_templates
= (const templates
*) hash_find (op_hash
,
3904 case SHORT_MNEM_SUFFIX
:
3905 case LONG_MNEM_SUFFIX
:
3908 i
.suffix
= mnem_p
[-1];
3910 current_templates
= (const templates
*) hash_find (op_hash
,
3919 if (intel_float_operand (mnemonic
) == 1)
3920 i
.suffix
= SHORT_MNEM_SUFFIX
;
3922 i
.suffix
= LONG_MNEM_SUFFIX
;
3924 current_templates
= (const templates
*) hash_find (op_hash
,
3929 if (!current_templates
)
3931 as_bad (_("no such instruction: `%s'"), token_start
);
3936 if (current_templates
->start
->opcode_modifier
.jump
3937 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3939 /* Check for a branch hint. We allow ",pt" and ",pn" for
3940 predict taken and predict not taken respectively.
3941 I'm not sure that branch hints actually do anything on loop
3942 and jcxz insns (JumpByte) for current Pentium4 chips. They
3943 may work in the future and it doesn't hurt to accept them
3945 if (l
[0] == ',' && l
[1] == 'p')
3949 if (!add_prefix (DS_PREFIX_OPCODE
))
3953 else if (l
[2] == 'n')
3955 if (!add_prefix (CS_PREFIX_OPCODE
))
3961 /* Any other comma loses. */
3964 as_bad (_("invalid character %s in mnemonic"),
3965 output_invalid (*l
));
3969 /* Check if instruction is supported on specified architecture. */
3971 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3973 supported
|= cpu_flags_match (t
);
3974 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3978 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3980 as_bad (flag_code
== CODE_64BIT
3981 ? _("`%s' is not supported in 64-bit mode")
3982 : _("`%s' is only supported in 64-bit mode"),
3983 current_templates
->start
->name
);
3986 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3988 as_bad (_("`%s' is not supported on `%s%s'"),
3989 current_templates
->start
->name
,
3990 cpu_arch_name
? cpu_arch_name
: default_arch
,
3991 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3996 if (!cpu_arch_flags
.bitfield
.cpui386
3997 && (flag_code
!= CODE_16BIT
))
3999 as_warn (_("use .code16 to ensure correct addressing mode"));
4006 parse_operands (char *l
, const char *mnemonic
)
4010 /* 1 if operand is pending after ','. */
4011 unsigned int expecting_operand
= 0;
4013 /* Non-zero if operand parens not balanced. */
4014 unsigned int paren_not_balanced
;
4016 while (*l
!= END_OF_INSN
)
4018 /* Skip optional white space before operand. */
4019 if (is_space_char (*l
))
4021 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4023 as_bad (_("invalid character %s before operand %d"),
4024 output_invalid (*l
),
4028 token_start
= l
; /* After white space. */
4029 paren_not_balanced
= 0;
4030 while (paren_not_balanced
|| *l
!= ',')
4032 if (*l
== END_OF_INSN
)
4034 if (paren_not_balanced
)
4037 as_bad (_("unbalanced parenthesis in operand %d."),
4040 as_bad (_("unbalanced brackets in operand %d."),
4045 break; /* we are done */
4047 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4049 as_bad (_("invalid character %s in operand %d"),
4050 output_invalid (*l
),
4057 ++paren_not_balanced
;
4059 --paren_not_balanced
;
4064 ++paren_not_balanced
;
4066 --paren_not_balanced
;
4070 if (l
!= token_start
)
4071 { /* Yes, we've read in another operand. */
4072 unsigned int operand_ok
;
4073 this_operand
= i
.operands
++;
4074 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4075 if (i
.operands
> MAX_OPERANDS
)
4077 as_bad (_("spurious operands; (%d operands/instruction max)"),
4081 /* Now parse operand adding info to 'i' as we go along. */
4082 END_STRING_AND_SAVE (l
);
4086 i386_intel_operand (token_start
,
4087 intel_float_operand (mnemonic
));
4089 operand_ok
= i386_att_operand (token_start
);
4091 RESTORE_END_STRING (l
);
4097 if (expecting_operand
)
4099 expecting_operand_after_comma
:
4100 as_bad (_("expecting operand after ','; got nothing"));
4105 as_bad (_("expecting operand before ','; got nothing"));
4110 /* Now *l must be either ',' or END_OF_INSN. */
4113 if (*++l
== END_OF_INSN
)
4115 /* Just skip it, if it's \n complain. */
4116 goto expecting_operand_after_comma
;
4118 expecting_operand
= 1;
4125 swap_2_operands (int xchg1
, int xchg2
)
4127 union i386_op temp_op
;
4128 i386_operand_type temp_type
;
4129 enum bfd_reloc_code_real temp_reloc
;
4131 temp_type
= i
.types
[xchg2
];
4132 i
.types
[xchg2
] = i
.types
[xchg1
];
4133 i
.types
[xchg1
] = temp_type
;
4134 temp_op
= i
.op
[xchg2
];
4135 i
.op
[xchg2
] = i
.op
[xchg1
];
4136 i
.op
[xchg1
] = temp_op
;
4137 temp_reloc
= i
.reloc
[xchg2
];
4138 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4139 i
.reloc
[xchg1
] = temp_reloc
;
4143 if (i
.mask
->operand
== xchg1
)
4144 i
.mask
->operand
= xchg2
;
4145 else if (i
.mask
->operand
== xchg2
)
4146 i
.mask
->operand
= xchg1
;
4150 if (i
.broadcast
->operand
== xchg1
)
4151 i
.broadcast
->operand
= xchg2
;
4152 else if (i
.broadcast
->operand
== xchg2
)
4153 i
.broadcast
->operand
= xchg1
;
4157 if (i
.rounding
->operand
== xchg1
)
4158 i
.rounding
->operand
= xchg2
;
4159 else if (i
.rounding
->operand
== xchg2
)
4160 i
.rounding
->operand
= xchg1
;
4165 swap_operands (void)
4171 swap_2_operands (1, i
.operands
- 2);
4174 swap_2_operands (0, i
.operands
- 1);
4180 if (i
.mem_operands
== 2)
4182 const seg_entry
*temp_seg
;
4183 temp_seg
= i
.seg
[0];
4184 i
.seg
[0] = i
.seg
[1];
4185 i
.seg
[1] = temp_seg
;
4189 /* Try to ensure constant immediates are represented in the smallest
4194 char guess_suffix
= 0;
4198 guess_suffix
= i
.suffix
;
4199 else if (i
.reg_operands
)
4201 /* Figure out a suffix from the last register operand specified.
4202 We can't do this properly yet, ie. excluding InOutPortReg,
4203 but the following works for instructions with immediates.
4204 In any case, we can't set i.suffix yet. */
4205 for (op
= i
.operands
; --op
>= 0;)
4206 if (i
.types
[op
].bitfield
.reg8
)
4208 guess_suffix
= BYTE_MNEM_SUFFIX
;
4211 else if (i
.types
[op
].bitfield
.reg16
)
4213 guess_suffix
= WORD_MNEM_SUFFIX
;
4216 else if (i
.types
[op
].bitfield
.reg32
)
4218 guess_suffix
= LONG_MNEM_SUFFIX
;
4221 else if (i
.types
[op
].bitfield
.reg64
)
4223 guess_suffix
= QWORD_MNEM_SUFFIX
;
4227 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4228 guess_suffix
= WORD_MNEM_SUFFIX
;
4230 for (op
= i
.operands
; --op
>= 0;)
4231 if (operand_type_check (i
.types
[op
], imm
))
4233 switch (i
.op
[op
].imms
->X_op
)
4236 /* If a suffix is given, this operand may be shortened. */
4237 switch (guess_suffix
)
4239 case LONG_MNEM_SUFFIX
:
4240 i
.types
[op
].bitfield
.imm32
= 1;
4241 i
.types
[op
].bitfield
.imm64
= 1;
4243 case WORD_MNEM_SUFFIX
:
4244 i
.types
[op
].bitfield
.imm16
= 1;
4245 i
.types
[op
].bitfield
.imm32
= 1;
4246 i
.types
[op
].bitfield
.imm32s
= 1;
4247 i
.types
[op
].bitfield
.imm64
= 1;
4249 case BYTE_MNEM_SUFFIX
:
4250 i
.types
[op
].bitfield
.imm8
= 1;
4251 i
.types
[op
].bitfield
.imm8s
= 1;
4252 i
.types
[op
].bitfield
.imm16
= 1;
4253 i
.types
[op
].bitfield
.imm32
= 1;
4254 i
.types
[op
].bitfield
.imm32s
= 1;
4255 i
.types
[op
].bitfield
.imm64
= 1;
4259 /* If this operand is at most 16 bits, convert it
4260 to a signed 16 bit number before trying to see
4261 whether it will fit in an even smaller size.
4262 This allows a 16-bit operand such as $0xffe0 to
4263 be recognised as within Imm8S range. */
4264 if ((i
.types
[op
].bitfield
.imm16
)
4265 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4267 i
.op
[op
].imms
->X_add_number
=
4268 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4271 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4272 if ((i
.types
[op
].bitfield
.imm32
)
4273 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4276 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4277 ^ ((offsetT
) 1 << 31))
4278 - ((offsetT
) 1 << 31));
4282 = operand_type_or (i
.types
[op
],
4283 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4285 /* We must avoid matching of Imm32 templates when 64bit
4286 only immediate is available. */
4287 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4288 i
.types
[op
].bitfield
.imm32
= 0;
4295 /* Symbols and expressions. */
4297 /* Convert symbolic operand to proper sizes for matching, but don't
4298 prevent matching a set of insns that only supports sizes other
4299 than those matching the insn suffix. */
4301 i386_operand_type mask
, allowed
;
4302 const insn_template
*t
;
4304 operand_type_set (&mask
, 0);
4305 operand_type_set (&allowed
, 0);
4307 for (t
= current_templates
->start
;
4308 t
< current_templates
->end
;
4310 allowed
= operand_type_or (allowed
,
4311 t
->operand_types
[op
]);
4312 switch (guess_suffix
)
4314 case QWORD_MNEM_SUFFIX
:
4315 mask
.bitfield
.imm64
= 1;
4316 mask
.bitfield
.imm32s
= 1;
4318 case LONG_MNEM_SUFFIX
:
4319 mask
.bitfield
.imm32
= 1;
4321 case WORD_MNEM_SUFFIX
:
4322 mask
.bitfield
.imm16
= 1;
4324 case BYTE_MNEM_SUFFIX
:
4325 mask
.bitfield
.imm8
= 1;
4330 allowed
= operand_type_and (mask
, allowed
);
4331 if (!operand_type_all_zero (&allowed
))
4332 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4339 /* Try to use the smallest displacement type too. */
4341 optimize_disp (void)
4345 for (op
= i
.operands
; --op
>= 0;)
4346 if (operand_type_check (i
.types
[op
], disp
))
4348 if (i
.op
[op
].disps
->X_op
== O_constant
)
4350 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4352 if (i
.types
[op
].bitfield
.disp16
4353 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4355 /* If this operand is at most 16 bits, convert
4356 to a signed 16 bit number and don't use 64bit
4358 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4359 i
.types
[op
].bitfield
.disp64
= 0;
4362 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4363 if (i
.types
[op
].bitfield
.disp32
4364 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4366 /* If this operand is at most 32 bits, convert
4367 to a signed 32 bit number and don't use 64bit
4369 op_disp
&= (((offsetT
) 2 << 31) - 1);
4370 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4371 i
.types
[op
].bitfield
.disp64
= 0;
4374 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4376 i
.types
[op
].bitfield
.disp8
= 0;
4377 i
.types
[op
].bitfield
.disp16
= 0;
4378 i
.types
[op
].bitfield
.disp32
= 0;
4379 i
.types
[op
].bitfield
.disp32s
= 0;
4380 i
.types
[op
].bitfield
.disp64
= 0;
4384 else if (flag_code
== CODE_64BIT
)
4386 if (fits_in_signed_long (op_disp
))
4388 i
.types
[op
].bitfield
.disp64
= 0;
4389 i
.types
[op
].bitfield
.disp32s
= 1;
4391 if (i
.prefix
[ADDR_PREFIX
]
4392 && fits_in_unsigned_long (op_disp
))
4393 i
.types
[op
].bitfield
.disp32
= 1;
4395 if ((i
.types
[op
].bitfield
.disp32
4396 || i
.types
[op
].bitfield
.disp32s
4397 || i
.types
[op
].bitfield
.disp16
)
4398 && fits_in_signed_byte (op_disp
))
4399 i
.types
[op
].bitfield
.disp8
= 1;
4401 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4402 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4404 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4405 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4406 i
.types
[op
].bitfield
.disp8
= 0;
4407 i
.types
[op
].bitfield
.disp16
= 0;
4408 i
.types
[op
].bitfield
.disp32
= 0;
4409 i
.types
[op
].bitfield
.disp32s
= 0;
4410 i
.types
[op
].bitfield
.disp64
= 0;
4413 /* We only support 64bit displacement on constants. */
4414 i
.types
[op
].bitfield
.disp64
= 0;
4418 /* Check if operands are valid for the instruction. */
4421 check_VecOperands (const insn_template
*t
)
4425 /* Without VSIB byte, we can't have a vector register for index. */
4426 if (!t
->opcode_modifier
.vecsib
4428 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4429 || i
.index_reg
->reg_type
.bitfield
.regymm
4430 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4432 i
.error
= unsupported_vector_index_register
;
4436 /* Check if default mask is allowed. */
4437 if (t
->opcode_modifier
.nodefmask
4438 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4440 i
.error
= no_default_mask
;
4444 /* For VSIB byte, we need a vector register for index, and all vector
4445 registers must be distinct. */
4446 if (t
->opcode_modifier
.vecsib
)
4449 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4450 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4451 || (t
->opcode_modifier
.vecsib
== VecSIB256
4452 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4453 || (t
->opcode_modifier
.vecsib
== VecSIB512
4454 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4456 i
.error
= invalid_vsib_address
;
4460 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4461 if (i
.reg_operands
== 2 && !i
.mask
)
4463 gas_assert (i
.types
[0].bitfield
.regxmm
4464 || i
.types
[0].bitfield
.regymm
);
4465 gas_assert (i
.types
[2].bitfield
.regxmm
4466 || i
.types
[2].bitfield
.regymm
);
4467 if (operand_check
== check_none
)
4469 if (register_number (i
.op
[0].regs
)
4470 != register_number (i
.index_reg
)
4471 && register_number (i
.op
[2].regs
)
4472 != register_number (i
.index_reg
)
4473 && register_number (i
.op
[0].regs
)
4474 != register_number (i
.op
[2].regs
))
4476 if (operand_check
== check_error
)
4478 i
.error
= invalid_vector_register_set
;
4481 as_warn (_("mask, index, and destination registers should be distinct"));
4483 else if (i
.reg_operands
== 1 && i
.mask
)
4485 if ((i
.types
[1].bitfield
.regymm
4486 || i
.types
[1].bitfield
.regzmm
)
4487 && (register_number (i
.op
[1].regs
)
4488 == register_number (i
.index_reg
)))
4490 if (operand_check
== check_error
)
4492 i
.error
= invalid_vector_register_set
;
4495 if (operand_check
!= check_none
)
4496 as_warn (_("index and destination registers should be distinct"));
4501 /* Check if broadcast is supported by the instruction and is applied
4502 to the memory operand. */
4505 int broadcasted_opnd_size
;
4507 /* Check if specified broadcast is supported in this instruction,
4508 and it's applied to memory operand of DWORD or QWORD type,
4509 depending on VecESize. */
4510 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4511 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4512 || (t
->opcode_modifier
.vecesize
== 0
4513 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4514 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4515 || (t
->opcode_modifier
.vecesize
== 1
4516 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4517 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4520 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4521 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4522 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4523 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4524 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4525 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4526 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4527 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4528 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4532 if ((broadcasted_opnd_size
== 256
4533 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4534 || (broadcasted_opnd_size
== 512
4535 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4538 i
.error
= unsupported_broadcast
;
4542 /* If broadcast is supported in this instruction, we need to check if
4543 operand of one-element size isn't specified without broadcast. */
4544 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4546 /* Find memory operand. */
4547 for (op
= 0; op
< i
.operands
; op
++)
4548 if (operand_type_check (i
.types
[op
], anymem
))
4550 gas_assert (op
< i
.operands
);
4551 /* Check size of the memory operand. */
4552 if ((t
->opcode_modifier
.vecesize
== 0
4553 && i
.types
[op
].bitfield
.dword
)
4554 || (t
->opcode_modifier
.vecesize
== 1
4555 && i
.types
[op
].bitfield
.qword
))
4557 i
.error
= broadcast_needed
;
4562 /* Check if requested masking is supported. */
4564 && (!t
->opcode_modifier
.masking
4566 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4568 i
.error
= unsupported_masking
;
4572 /* Check if masking is applied to dest operand. */
4573 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4575 i
.error
= mask_not_on_destination
;
4582 if ((i
.rounding
->type
!= saeonly
4583 && !t
->opcode_modifier
.staticrounding
)
4584 || (i
.rounding
->type
== saeonly
4585 && (t
->opcode_modifier
.staticrounding
4586 || !t
->opcode_modifier
.sae
)))
4588 i
.error
= unsupported_rc_sae
;
4591 /* If the instruction has several immediate operands and one of
4592 them is rounding, the rounding operand should be the last
4593 immediate operand. */
4594 if (i
.imm_operands
> 1
4595 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4597 i
.error
= rc_sae_operand_not_last_imm
;
4602 /* Check vector Disp8 operand. */
4603 if (t
->opcode_modifier
.disp8memshift
)
4606 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4608 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4610 for (op
= 0; op
< i
.operands
; op
++)
4611 if (operand_type_check (i
.types
[op
], disp
)
4612 && i
.op
[op
].disps
->X_op
== O_constant
)
4614 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4616 = (i
.disp_encoding
!= disp_encoding_32bit
4617 && fits_in_vec_disp8 (value
));
4618 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4621 i
.types
[op
].bitfield
.vec_disp8
= 1;
4624 /* Vector insn can only have Vec_Disp8/Disp32 in
4625 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4627 i
.types
[op
].bitfield
.disp8
= 0;
4628 if (flag_code
!= CODE_16BIT
)
4629 i
.types
[op
].bitfield
.disp16
= 0;
4632 else if (flag_code
!= CODE_16BIT
)
4634 /* One form of this instruction supports vector Disp8.
4635 Try vector Disp8 if we need to use Disp32. */
4636 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4638 i
.error
= try_vector_disp8
;
4650 /* Check if operands are valid for the instruction. Update VEX
4654 VEX_check_operands (const insn_template
*t
)
4656 /* VREX is only valid with EVEX prefix. */
4657 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4659 i
.error
= invalid_register_operand
;
4663 if (!t
->opcode_modifier
.vex
)
4666 /* Only check VEX_Imm4, which must be the first operand. */
4667 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4669 if (i
.op
[0].imms
->X_op
!= O_constant
4670 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4676 /* Turn off Imm8 so that update_imm won't complain. */
4677 i
.types
[0] = vec_imm4
;
4683 static const insn_template
*
4684 match_template (void)
4686 /* Points to template once we've found it. */
4687 const insn_template
*t
;
4688 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4689 i386_operand_type overlap4
;
4690 unsigned int found_reverse_match
;
4691 i386_opcode_modifier suffix_check
;
4692 i386_operand_type operand_types
[MAX_OPERANDS
];
4693 int addr_prefix_disp
;
4695 unsigned int found_cpu_match
;
4696 unsigned int check_register
;
4697 enum i386_error specific_error
= 0;
4699 #if MAX_OPERANDS != 5
4700 # error "MAX_OPERANDS must be 5."
4703 found_reverse_match
= 0;
4704 addr_prefix_disp
= -1;
4706 memset (&suffix_check
, 0, sizeof (suffix_check
));
4707 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4708 suffix_check
.no_bsuf
= 1;
4709 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4710 suffix_check
.no_wsuf
= 1;
4711 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4712 suffix_check
.no_ssuf
= 1;
4713 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4714 suffix_check
.no_lsuf
= 1;
4715 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4716 suffix_check
.no_qsuf
= 1;
4717 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4718 suffix_check
.no_ldsuf
= 1;
4720 /* Must have right number of operands. */
4721 i
.error
= number_of_operands_mismatch
;
4723 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4725 addr_prefix_disp
= -1;
4727 if (i
.operands
!= t
->operands
)
4730 /* Check processor support. */
4731 i
.error
= unsupported
;
4732 found_cpu_match
= (cpu_flags_match (t
)
4733 == CPU_FLAGS_PERFECT_MATCH
);
4734 if (!found_cpu_match
)
4737 /* Check old gcc support. */
4738 i
.error
= old_gcc_only
;
4739 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4742 /* Check AT&T mnemonic. */
4743 i
.error
= unsupported_with_intel_mnemonic
;
4744 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4747 /* Check AT&T/Intel syntax. */
4748 i
.error
= unsupported_syntax
;
4749 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4750 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4753 /* Check the suffix, except for some instructions in intel mode. */
4754 i
.error
= invalid_instruction_suffix
;
4755 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4756 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4757 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4758 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4759 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4760 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4761 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4764 if (!operand_size_match (t
))
4767 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4768 operand_types
[j
] = t
->operand_types
[j
];
4770 /* In general, don't allow 64-bit operands in 32-bit mode. */
4771 if (i
.suffix
== QWORD_MNEM_SUFFIX
4772 && flag_code
!= CODE_64BIT
4774 ? (!t
->opcode_modifier
.ignoresize
4775 && !intel_float_operand (t
->name
))
4776 : intel_float_operand (t
->name
) != 2)
4777 && ((!operand_types
[0].bitfield
.regmmx
4778 && !operand_types
[0].bitfield
.regxmm
4779 && !operand_types
[0].bitfield
.regymm
4780 && !operand_types
[0].bitfield
.regzmm
)
4781 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4782 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4783 && operand_types
[t
->operands
> 1].bitfield
.regymm
4784 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4785 && (t
->base_opcode
!= 0x0fc7
4786 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4789 /* In general, don't allow 32-bit operands on pre-386. */
4790 else if (i
.suffix
== LONG_MNEM_SUFFIX
4791 && !cpu_arch_flags
.bitfield
.cpui386
4793 ? (!t
->opcode_modifier
.ignoresize
4794 && !intel_float_operand (t
->name
))
4795 : intel_float_operand (t
->name
) != 2)
4796 && ((!operand_types
[0].bitfield
.regmmx
4797 && !operand_types
[0].bitfield
.regxmm
)
4798 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4799 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4802 /* Do not verify operands when there are none. */
4806 /* We've found a match; break out of loop. */
4810 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4811 into Disp32/Disp16/Disp32 operand. */
4812 if (i
.prefix
[ADDR_PREFIX
] != 0)
4814 /* There should be only one Disp operand. */
4818 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4820 if (operand_types
[j
].bitfield
.disp16
)
4822 addr_prefix_disp
= j
;
4823 operand_types
[j
].bitfield
.disp32
= 1;
4824 operand_types
[j
].bitfield
.disp16
= 0;
4830 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4832 if (operand_types
[j
].bitfield
.disp32
)
4834 addr_prefix_disp
= j
;
4835 operand_types
[j
].bitfield
.disp32
= 0;
4836 operand_types
[j
].bitfield
.disp16
= 1;
4842 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4844 if (operand_types
[j
].bitfield
.disp64
)
4846 addr_prefix_disp
= j
;
4847 operand_types
[j
].bitfield
.disp64
= 0;
4848 operand_types
[j
].bitfield
.disp32
= 1;
4856 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4857 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4860 /* We check register size if needed. */
4861 check_register
= t
->opcode_modifier
.checkregsize
;
4862 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4863 switch (t
->operands
)
4866 if (!operand_type_match (overlap0
, i
.types
[0]))
4870 /* xchg %eax, %eax is a special case. It is an aliase for nop
4871 only in 32bit mode and we can use opcode 0x90. In 64bit
4872 mode, we can't use 0x90 for xchg %eax, %eax since it should
4873 zero-extend %eax to %rax. */
4874 if (flag_code
== CODE_64BIT
4875 && t
->base_opcode
== 0x90
4876 && operand_type_equal (&i
.types
[0], &acc32
)
4877 && operand_type_equal (&i
.types
[1], &acc32
))
4881 /* If we swap operand in encoding, we either match
4882 the next one or reverse direction of operands. */
4883 if (t
->opcode_modifier
.s
)
4885 else if (t
->opcode_modifier
.d
)
4890 /* If we swap operand in encoding, we match the next one. */
4891 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4895 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4896 if (!operand_type_match (overlap0
, i
.types
[0])
4897 || !operand_type_match (overlap1
, i
.types
[1])
4899 && !operand_type_register_match (overlap0
, i
.types
[0],
4901 overlap1
, i
.types
[1],
4904 /* Check if other direction is valid ... */
4905 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4909 /* Try reversing direction of operands. */
4910 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4911 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4912 if (!operand_type_match (overlap0
, i
.types
[0])
4913 || !operand_type_match (overlap1
, i
.types
[1])
4915 && !operand_type_register_match (overlap0
,
4922 /* Does not match either direction. */
4925 /* found_reverse_match holds which of D or FloatDR
4927 if (t
->opcode_modifier
.d
)
4928 found_reverse_match
= Opcode_D
;
4929 else if (t
->opcode_modifier
.floatd
)
4930 found_reverse_match
= Opcode_FloatD
;
4932 found_reverse_match
= 0;
4933 if (t
->opcode_modifier
.floatr
)
4934 found_reverse_match
|= Opcode_FloatR
;
4938 /* Found a forward 2 operand match here. */
4939 switch (t
->operands
)
4942 overlap4
= operand_type_and (i
.types
[4],
4945 overlap3
= operand_type_and (i
.types
[3],
4948 overlap2
= operand_type_and (i
.types
[2],
4953 switch (t
->operands
)
4956 if (!operand_type_match (overlap4
, i
.types
[4])
4957 || !operand_type_register_match (overlap3
,
4965 if (!operand_type_match (overlap3
, i
.types
[3])
4967 && !operand_type_register_match (overlap2
,
4975 /* Here we make use of the fact that there are no
4976 reverse match 3 operand instructions, and all 3
4977 operand instructions only need to be checked for
4978 register consistency between operands 2 and 3. */
4979 if (!operand_type_match (overlap2
, i
.types
[2])
4981 && !operand_type_register_match (overlap1
,
4991 /* Found either forward/reverse 2, 3 or 4 operand match here:
4992 slip through to break. */
4994 if (!found_cpu_match
)
4996 found_reverse_match
= 0;
5000 /* Check if vector and VEX operands are valid. */
5001 if (check_VecOperands (t
) || VEX_check_operands (t
))
5003 specific_error
= i
.error
;
5007 /* We've found a match; break out of loop. */
5011 if (t
== current_templates
->end
)
5013 /* We found no match. */
5014 const char *err_msg
;
5015 switch (specific_error
? specific_error
: i
.error
)
5019 case operand_size_mismatch
:
5020 err_msg
= _("operand size mismatch");
5022 case operand_type_mismatch
:
5023 err_msg
= _("operand type mismatch");
5025 case register_type_mismatch
:
5026 err_msg
= _("register type mismatch");
5028 case number_of_operands_mismatch
:
5029 err_msg
= _("number of operands mismatch");
5031 case invalid_instruction_suffix
:
5032 err_msg
= _("invalid instruction suffix");
5035 err_msg
= _("constant doesn't fit in 4 bits");
5038 err_msg
= _("only supported with old gcc");
5040 case unsupported_with_intel_mnemonic
:
5041 err_msg
= _("unsupported with Intel mnemonic");
5043 case unsupported_syntax
:
5044 err_msg
= _("unsupported syntax");
5047 as_bad (_("unsupported instruction `%s'"),
5048 current_templates
->start
->name
);
5050 case invalid_vsib_address
:
5051 err_msg
= _("invalid VSIB address");
5053 case invalid_vector_register_set
:
5054 err_msg
= _("mask, index, and destination registers must be distinct");
5056 case unsupported_vector_index_register
:
5057 err_msg
= _("unsupported vector index register");
5059 case unsupported_broadcast
:
5060 err_msg
= _("unsupported broadcast");
5062 case broadcast_not_on_src_operand
:
5063 err_msg
= _("broadcast not on source memory operand");
5065 case broadcast_needed
:
5066 err_msg
= _("broadcast is needed for operand of such type");
5068 case unsupported_masking
:
5069 err_msg
= _("unsupported masking");
5071 case mask_not_on_destination
:
5072 err_msg
= _("mask not on destination operand");
5074 case no_default_mask
:
5075 err_msg
= _("default mask isn't allowed");
5077 case unsupported_rc_sae
:
5078 err_msg
= _("unsupported static rounding/sae");
5080 case rc_sae_operand_not_last_imm
:
5082 err_msg
= _("RC/SAE operand must precede immediate operands");
5084 err_msg
= _("RC/SAE operand must follow immediate operands");
5086 case invalid_register_operand
:
5087 err_msg
= _("invalid register operand");
5090 as_bad (_("%s for `%s'"), err_msg
,
5091 current_templates
->start
->name
);
5095 if (!quiet_warnings
)
5098 && (i
.types
[0].bitfield
.jumpabsolute
5099 != operand_types
[0].bitfield
.jumpabsolute
))
5101 as_warn (_("indirect %s without `*'"), t
->name
);
5104 if (t
->opcode_modifier
.isprefix
5105 && t
->opcode_modifier
.ignoresize
)
5107 /* Warn them that a data or address size prefix doesn't
5108 affect assembly of the next line of code. */
5109 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5113 /* Copy the template we found. */
5116 if (addr_prefix_disp
!= -1)
5117 i
.tm
.operand_types
[addr_prefix_disp
]
5118 = operand_types
[addr_prefix_disp
];
5120 if (found_reverse_match
)
5122 /* If we found a reverse match we must alter the opcode
5123 direction bit. found_reverse_match holds bits to change
5124 (different for int & float insns). */
5126 i
.tm
.base_opcode
^= found_reverse_match
;
5128 i
.tm
.operand_types
[0] = operand_types
[1];
5129 i
.tm
.operand_types
[1] = operand_types
[0];
5138 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5139 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5141 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5143 as_bad (_("`%s' operand %d must use `%ses' segment"),
5149 /* There's only ever one segment override allowed per instruction.
5150 This instruction possibly has a legal segment override on the
5151 second operand, so copy the segment to where non-string
5152 instructions store it, allowing common code. */
5153 i
.seg
[0] = i
.seg
[1];
5155 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5157 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5159 as_bad (_("`%s' operand %d must use `%ses' segment"),
5170 process_suffix (void)
5172 /* If matched instruction specifies an explicit instruction mnemonic
5174 if (i
.tm
.opcode_modifier
.size16
)
5175 i
.suffix
= WORD_MNEM_SUFFIX
;
5176 else if (i
.tm
.opcode_modifier
.size32
)
5177 i
.suffix
= LONG_MNEM_SUFFIX
;
5178 else if (i
.tm
.opcode_modifier
.size64
)
5179 i
.suffix
= QWORD_MNEM_SUFFIX
;
5180 else if (i
.reg_operands
)
5182 /* If there's no instruction mnemonic suffix we try to invent one
5183 based on register operands. */
5186 /* We take i.suffix from the last register operand specified,
5187 Destination register type is more significant than source
5188 register type. crc32 in SSE4.2 prefers source register
5190 if (i
.tm
.base_opcode
== 0xf20f38f1)
5192 if (i
.types
[0].bitfield
.reg16
)
5193 i
.suffix
= WORD_MNEM_SUFFIX
;
5194 else if (i
.types
[0].bitfield
.reg32
)
5195 i
.suffix
= LONG_MNEM_SUFFIX
;
5196 else if (i
.types
[0].bitfield
.reg64
)
5197 i
.suffix
= QWORD_MNEM_SUFFIX
;
5199 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5201 if (i
.types
[0].bitfield
.reg8
)
5202 i
.suffix
= BYTE_MNEM_SUFFIX
;
5209 if (i
.tm
.base_opcode
== 0xf20f38f1
5210 || i
.tm
.base_opcode
== 0xf20f38f0)
5212 /* We have to know the operand size for crc32. */
5213 as_bad (_("ambiguous memory operand size for `%s`"),
5218 for (op
= i
.operands
; --op
>= 0;)
5219 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5221 if (i
.types
[op
].bitfield
.reg8
)
5223 i
.suffix
= BYTE_MNEM_SUFFIX
;
5226 else if (i
.types
[op
].bitfield
.reg16
)
5228 i
.suffix
= WORD_MNEM_SUFFIX
;
5231 else if (i
.types
[op
].bitfield
.reg32
)
5233 i
.suffix
= LONG_MNEM_SUFFIX
;
5236 else if (i
.types
[op
].bitfield
.reg64
)
5238 i
.suffix
= QWORD_MNEM_SUFFIX
;
5244 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5247 && i
.tm
.opcode_modifier
.ignoresize
5248 && i
.tm
.opcode_modifier
.no_bsuf
)
5250 else if (!check_byte_reg ())
5253 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5256 && i
.tm
.opcode_modifier
.ignoresize
5257 && i
.tm
.opcode_modifier
.no_lsuf
)
5259 else if (!check_long_reg ())
5262 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5265 && i
.tm
.opcode_modifier
.ignoresize
5266 && i
.tm
.opcode_modifier
.no_qsuf
)
5268 else if (!check_qword_reg ())
5271 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5274 && i
.tm
.opcode_modifier
.ignoresize
5275 && i
.tm
.opcode_modifier
.no_wsuf
)
5277 else if (!check_word_reg ())
5280 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5281 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5282 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5284 /* Skip if the instruction has x/y/z suffix. match_template
5285 should check if it is a valid suffix. */
5287 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5288 /* Do nothing if the instruction is going to ignore the prefix. */
5293 else if (i
.tm
.opcode_modifier
.defaultsize
5295 /* exclude fldenv/frstor/fsave/fstenv */
5296 && i
.tm
.opcode_modifier
.no_ssuf
)
5298 i
.suffix
= stackop_size
;
5300 else if (intel_syntax
5302 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5303 || i
.tm
.opcode_modifier
.jumpbyte
5304 || i
.tm
.opcode_modifier
.jumpintersegment
5305 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5306 && i
.tm
.extension_opcode
<= 3)))
5311 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5313 i
.suffix
= QWORD_MNEM_SUFFIX
;
5317 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5318 i
.suffix
= LONG_MNEM_SUFFIX
;
5321 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5322 i
.suffix
= WORD_MNEM_SUFFIX
;
5331 if (i
.tm
.opcode_modifier
.w
)
5333 as_bad (_("no instruction mnemonic suffix given and "
5334 "no register operands; can't size instruction"));
5340 unsigned int suffixes
;
5342 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5343 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5345 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5347 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5349 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5351 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5354 /* There are more than suffix matches. */
5355 if (i
.tm
.opcode_modifier
.w
5356 || ((suffixes
& (suffixes
- 1))
5357 && !i
.tm
.opcode_modifier
.defaultsize
5358 && !i
.tm
.opcode_modifier
.ignoresize
))
5360 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5366 /* Change the opcode based on the operand size given by i.suffix;
5367 We don't need to change things for byte insns. */
5370 && i
.suffix
!= BYTE_MNEM_SUFFIX
5371 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5372 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5373 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5375 /* It's not a byte, select word/dword operation. */
5376 if (i
.tm
.opcode_modifier
.w
)
5378 if (i
.tm
.opcode_modifier
.shortform
)
5379 i
.tm
.base_opcode
|= 8;
5381 i
.tm
.base_opcode
|= 1;
5384 /* Now select between word & dword operations via the operand
5385 size prefix, except for instructions that will ignore this
5387 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5389 /* The address size override prefix changes the size of the
5391 if ((flag_code
== CODE_32BIT
5392 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5393 || (flag_code
!= CODE_32BIT
5394 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5395 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5398 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5399 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5400 && !i
.tm
.opcode_modifier
.ignoresize
5401 && !i
.tm
.opcode_modifier
.floatmf
5402 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5403 || (flag_code
== CODE_64BIT
5404 && i
.tm
.opcode_modifier
.jumpbyte
)))
5406 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5408 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5409 prefix
= ADDR_PREFIX_OPCODE
;
5411 if (!add_prefix (prefix
))
5415 /* Set mode64 for an operand. */
5416 if (i
.suffix
== QWORD_MNEM_SUFFIX
5417 && flag_code
== CODE_64BIT
5418 && !i
.tm
.opcode_modifier
.norex64
)
5420 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5421 need rex64. cmpxchg8b is also a special case. */
5422 if (! (i
.operands
== 2
5423 && i
.tm
.base_opcode
== 0x90
5424 && i
.tm
.extension_opcode
== None
5425 && operand_type_equal (&i
.types
[0], &acc64
)
5426 && operand_type_equal (&i
.types
[1], &acc64
))
5427 && ! (i
.operands
== 1
5428 && i
.tm
.base_opcode
== 0xfc7
5429 && i
.tm
.extension_opcode
== 1
5430 && !operand_type_check (i
.types
[0], reg
)
5431 && operand_type_check (i
.types
[0], anymem
)))
5435 /* Size floating point instruction. */
5436 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5437 if (i
.tm
.opcode_modifier
.floatmf
)
5438 i
.tm
.base_opcode
^= 4;
5445 check_byte_reg (void)
5449 for (op
= i
.operands
; --op
>= 0;)
5451 /* If this is an eight bit register, it's OK. If it's the 16 or
5452 32 bit version of an eight bit register, we will just use the
5453 low portion, and that's OK too. */
5454 if (i
.types
[op
].bitfield
.reg8
)
5457 /* I/O port address operands are OK too. */
5458 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5461 /* crc32 doesn't generate this warning. */
5462 if (i
.tm
.base_opcode
== 0xf20f38f0)
5465 if ((i
.types
[op
].bitfield
.reg16
5466 || i
.types
[op
].bitfield
.reg32
5467 || i
.types
[op
].bitfield
.reg64
)
5468 && i
.op
[op
].regs
->reg_num
< 4
5469 /* Prohibit these changes in 64bit mode, since the lowering
5470 would be more complicated. */
5471 && flag_code
!= CODE_64BIT
)
5473 #if REGISTER_WARNINGS
5474 if (!quiet_warnings
)
5475 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5477 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5478 ? REGNAM_AL
- REGNAM_AX
5479 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5481 i
.op
[op
].regs
->reg_name
,
5486 /* Any other register is bad. */
5487 if (i
.types
[op
].bitfield
.reg16
5488 || i
.types
[op
].bitfield
.reg32
5489 || i
.types
[op
].bitfield
.reg64
5490 || i
.types
[op
].bitfield
.regmmx
5491 || i
.types
[op
].bitfield
.regxmm
5492 || i
.types
[op
].bitfield
.regymm
5493 || i
.types
[op
].bitfield
.regzmm
5494 || i
.types
[op
].bitfield
.sreg2
5495 || i
.types
[op
].bitfield
.sreg3
5496 || i
.types
[op
].bitfield
.control
5497 || i
.types
[op
].bitfield
.debug
5498 || i
.types
[op
].bitfield
.test
5499 || i
.types
[op
].bitfield
.floatreg
5500 || i
.types
[op
].bitfield
.floatacc
)
5502 as_bad (_("`%s%s' not allowed with `%s%c'"),
5504 i
.op
[op
].regs
->reg_name
,
5514 check_long_reg (void)
5518 for (op
= i
.operands
; --op
>= 0;)
5519 /* Reject eight bit registers, except where the template requires
5520 them. (eg. movzb) */
5521 if (i
.types
[op
].bitfield
.reg8
5522 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5523 || i
.tm
.operand_types
[op
].bitfield
.reg32
5524 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5526 as_bad (_("`%s%s' not allowed with `%s%c'"),
5528 i
.op
[op
].regs
->reg_name
,
5533 /* Warn if the e prefix on a general reg is missing. */
5534 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5535 && i
.types
[op
].bitfield
.reg16
5536 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5537 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5539 /* Prohibit these changes in the 64bit mode, since the
5540 lowering is more complicated. */
5541 if (flag_code
== CODE_64BIT
)
5543 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5544 register_prefix
, i
.op
[op
].regs
->reg_name
,
5548 #if REGISTER_WARNINGS
5549 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5551 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5552 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5555 /* Warn if the r prefix on a general reg is present. */
5556 else if (i
.types
[op
].bitfield
.reg64
5557 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5558 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5561 && i
.tm
.opcode_modifier
.toqword
5562 && !i
.types
[0].bitfield
.regxmm
)
5564 /* Convert to QWORD. We want REX byte. */
5565 i
.suffix
= QWORD_MNEM_SUFFIX
;
5569 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5570 register_prefix
, i
.op
[op
].regs
->reg_name
,
5579 check_qword_reg (void)
5583 for (op
= i
.operands
; --op
>= 0; )
5584 /* Reject eight bit registers, except where the template requires
5585 them. (eg. movzb) */
5586 if (i
.types
[op
].bitfield
.reg8
5587 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5588 || i
.tm
.operand_types
[op
].bitfield
.reg32
5589 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5591 as_bad (_("`%s%s' not allowed with `%s%c'"),
5593 i
.op
[op
].regs
->reg_name
,
5598 /* Warn if the r prefix on a general reg is missing. */
5599 else if ((i
.types
[op
].bitfield
.reg16
5600 || i
.types
[op
].bitfield
.reg32
)
5601 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5602 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5604 /* Prohibit these changes in the 64bit mode, since the
5605 lowering is more complicated. */
5607 && i
.tm
.opcode_modifier
.todword
5608 && !i
.types
[0].bitfield
.regxmm
)
5610 /* Convert to DWORD. We don't want REX byte. */
5611 i
.suffix
= LONG_MNEM_SUFFIX
;
5615 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5616 register_prefix
, i
.op
[op
].regs
->reg_name
,
5625 check_word_reg (void)
5628 for (op
= i
.operands
; --op
>= 0;)
5629 /* Reject eight bit registers, except where the template requires
5630 them. (eg. movzb) */
5631 if (i
.types
[op
].bitfield
.reg8
5632 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5633 || i
.tm
.operand_types
[op
].bitfield
.reg32
5634 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5636 as_bad (_("`%s%s' not allowed with `%s%c'"),
5638 i
.op
[op
].regs
->reg_name
,
5643 /* Warn if the e or r prefix on a general reg is present. */
5644 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5645 && (i
.types
[op
].bitfield
.reg32
5646 || i
.types
[op
].bitfield
.reg64
)
5647 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5648 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5650 /* Prohibit these changes in the 64bit mode, since the
5651 lowering is more complicated. */
5652 if (flag_code
== CODE_64BIT
)
5654 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5655 register_prefix
, i
.op
[op
].regs
->reg_name
,
5659 #if REGISTER_WARNINGS
5660 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5662 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5663 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5670 update_imm (unsigned int j
)
5672 i386_operand_type overlap
= i
.types
[j
];
5673 if ((overlap
.bitfield
.imm8
5674 || overlap
.bitfield
.imm8s
5675 || overlap
.bitfield
.imm16
5676 || overlap
.bitfield
.imm32
5677 || overlap
.bitfield
.imm32s
5678 || overlap
.bitfield
.imm64
)
5679 && !operand_type_equal (&overlap
, &imm8
)
5680 && !operand_type_equal (&overlap
, &imm8s
)
5681 && !operand_type_equal (&overlap
, &imm16
)
5682 && !operand_type_equal (&overlap
, &imm32
)
5683 && !operand_type_equal (&overlap
, &imm32s
)
5684 && !operand_type_equal (&overlap
, &imm64
))
5688 i386_operand_type temp
;
5690 operand_type_set (&temp
, 0);
5691 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5693 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5694 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5696 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5697 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5698 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5700 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5701 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5704 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5707 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5708 || operand_type_equal (&overlap
, &imm16_32
)
5709 || operand_type_equal (&overlap
, &imm16_32s
))
5711 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5716 if (!operand_type_equal (&overlap
, &imm8
)
5717 && !operand_type_equal (&overlap
, &imm8s
)
5718 && !operand_type_equal (&overlap
, &imm16
)
5719 && !operand_type_equal (&overlap
, &imm32
)
5720 && !operand_type_equal (&overlap
, &imm32s
)
5721 && !operand_type_equal (&overlap
, &imm64
))
5723 as_bad (_("no instruction mnemonic suffix given; "
5724 "can't determine immediate size"));
5728 i
.types
[j
] = overlap
;
5738 /* Update the first 2 immediate operands. */
5739 n
= i
.operands
> 2 ? 2 : i
.operands
;
5742 for (j
= 0; j
< n
; j
++)
5743 if (update_imm (j
) == 0)
5746 /* The 3rd operand can't be immediate operand. */
5747 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5754 bad_implicit_operand (int xmm
)
5756 const char *ireg
= xmm
? "xmm0" : "ymm0";
5759 as_bad (_("the last operand of `%s' must be `%s%s'"),
5760 i
.tm
.name
, register_prefix
, ireg
);
5762 as_bad (_("the first operand of `%s' must be `%s%s'"),
5763 i
.tm
.name
, register_prefix
, ireg
);
5768 process_operands (void)
5770 /* Default segment register this instruction will use for memory
5771 accesses. 0 means unknown. This is only for optimizing out
5772 unnecessary segment overrides. */
5773 const seg_entry
*default_seg
= 0;
5775 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5777 unsigned int dupl
= i
.operands
;
5778 unsigned int dest
= dupl
- 1;
5781 /* The destination must be an xmm register. */
5782 gas_assert (i
.reg_operands
5783 && MAX_OPERANDS
> dupl
5784 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5786 if (i
.tm
.opcode_modifier
.firstxmm0
)
5788 /* The first operand is implicit and must be xmm0. */
5789 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5790 if (register_number (i
.op
[0].regs
) != 0)
5791 return bad_implicit_operand (1);
5793 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5795 /* Keep xmm0 for instructions with VEX prefix and 3
5801 /* We remove the first xmm0 and keep the number of
5802 operands unchanged, which in fact duplicates the
5804 for (j
= 1; j
< i
.operands
; j
++)
5806 i
.op
[j
- 1] = i
.op
[j
];
5807 i
.types
[j
- 1] = i
.types
[j
];
5808 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5812 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5814 gas_assert ((MAX_OPERANDS
- 1) > dupl
5815 && (i
.tm
.opcode_modifier
.vexsources
5818 /* Add the implicit xmm0 for instructions with VEX prefix
5820 for (j
= i
.operands
; j
> 0; j
--)
5822 i
.op
[j
] = i
.op
[j
- 1];
5823 i
.types
[j
] = i
.types
[j
- 1];
5824 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5827 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5828 i
.types
[0] = regxmm
;
5829 i
.tm
.operand_types
[0] = regxmm
;
5832 i
.reg_operands
+= 2;
5837 i
.op
[dupl
] = i
.op
[dest
];
5838 i
.types
[dupl
] = i
.types
[dest
];
5839 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5848 i
.op
[dupl
] = i
.op
[dest
];
5849 i
.types
[dupl
] = i
.types
[dest
];
5850 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5853 if (i
.tm
.opcode_modifier
.immext
)
5856 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5860 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5861 gas_assert (i
.reg_operands
5862 && (operand_type_equal (&i
.types
[0], ®xmm
)
5863 || operand_type_equal (&i
.types
[0], ®ymm
)
5864 || operand_type_equal (&i
.types
[0], ®zmm
)));
5865 if (register_number (i
.op
[0].regs
) != 0)
5866 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5868 for (j
= 1; j
< i
.operands
; j
++)
5870 i
.op
[j
- 1] = i
.op
[j
];
5871 i
.types
[j
- 1] = i
.types
[j
];
5873 /* We need to adjust fields in i.tm since they are used by
5874 build_modrm_byte. */
5875 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5882 else if (i
.tm
.opcode_modifier
.regkludge
)
5884 /* The imul $imm, %reg instruction is converted into
5885 imul $imm, %reg, %reg, and the clr %reg instruction
5886 is converted into xor %reg, %reg. */
5888 unsigned int first_reg_op
;
5890 if (operand_type_check (i
.types
[0], reg
))
5894 /* Pretend we saw the extra register operand. */
5895 gas_assert (i
.reg_operands
== 1
5896 && i
.op
[first_reg_op
+ 1].regs
== 0);
5897 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5898 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5903 if (i
.tm
.opcode_modifier
.shortform
)
5905 if (i
.types
[0].bitfield
.sreg2
5906 || i
.types
[0].bitfield
.sreg3
)
5908 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5909 && i
.op
[0].regs
->reg_num
== 1)
5911 as_bad (_("you can't `pop %scs'"), register_prefix
);
5914 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5915 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5920 /* The register or float register operand is in operand
5924 if (i
.types
[0].bitfield
.floatreg
5925 || operand_type_check (i
.types
[0], reg
))
5929 /* Register goes in low 3 bits of opcode. */
5930 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5931 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5933 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5935 /* Warn about some common errors, but press on regardless.
5936 The first case can be generated by gcc (<= 2.8.1). */
5937 if (i
.operands
== 2)
5939 /* Reversed arguments on faddp, fsubp, etc. */
5940 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5941 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5942 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5946 /* Extraneous `l' suffix on fp insn. */
5947 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5948 register_prefix
, i
.op
[0].regs
->reg_name
);
5953 else if (i
.tm
.opcode_modifier
.modrm
)
5955 /* The opcode is completed (modulo i.tm.extension_opcode which
5956 must be put into the modrm byte). Now, we make the modrm and
5957 index base bytes based on all the info we've collected. */
5959 default_seg
= build_modrm_byte ();
5961 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5965 else if (i
.tm
.opcode_modifier
.isstring
)
5967 /* For the string instructions that allow a segment override
5968 on one of their operands, the default segment is ds. */
5972 if (i
.tm
.base_opcode
== 0x8d /* lea */
5975 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5977 /* If a segment was explicitly specified, and the specified segment
5978 is not the default, use an opcode prefix to select it. If we
5979 never figured out what the default segment is, then default_seg
5980 will be zero at this point, and the specified segment prefix will
5982 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5984 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5990 static const seg_entry
*
5991 build_modrm_byte (void)
5993 const seg_entry
*default_seg
= 0;
5994 unsigned int source
, dest
;
5997 /* The first operand of instructions with VEX prefix and 3 sources
5998 must be VEX_Imm4. */
5999 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6002 unsigned int nds
, reg_slot
;
6005 if (i
.tm
.opcode_modifier
.veximmext
6006 && i
.tm
.opcode_modifier
.immext
)
6008 dest
= i
.operands
- 2;
6009 gas_assert (dest
== 3);
6012 dest
= i
.operands
- 1;
6015 /* There are 2 kinds of instructions:
6016 1. 5 operands: 4 register operands or 3 register operands
6017 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6018 VexW0 or VexW1. The destination must be either XMM, YMM or
6020 2. 4 operands: 4 register operands or 3 register operands
6021 plus 1 memory operand, VexXDS, and VexImmExt */
6022 gas_assert ((i
.reg_operands
== 4
6023 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6024 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6025 && (i
.tm
.opcode_modifier
.veximmext
6026 || (i
.imm_operands
== 1
6027 && i
.types
[0].bitfield
.vec_imm4
6028 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6029 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6030 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6031 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6032 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6034 if (i
.imm_operands
== 0)
6036 /* When there is no immediate operand, generate an 8bit
6037 immediate operand to encode the first operand. */
6038 exp
= &im_expressions
[i
.imm_operands
++];
6039 i
.op
[i
.operands
].imms
= exp
;
6040 i
.types
[i
.operands
] = imm8
;
6042 /* If VexW1 is set, the first operand is the source and
6043 the second operand is encoded in the immediate operand. */
6044 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6055 /* FMA swaps REG and NDS. */
6056 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6064 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6066 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6068 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6070 exp
->X_op
= O_constant
;
6071 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6072 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6076 unsigned int imm_slot
;
6078 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6080 /* If VexW0 is set, the third operand is the source and
6081 the second operand is encoded in the immediate
6088 /* VexW1 is set, the second operand is the source and
6089 the third operand is encoded in the immediate
6095 if (i
.tm
.opcode_modifier
.immext
)
6097 /* When ImmExt is set, the immdiate byte is the last
6099 imm_slot
= i
.operands
- 1;
6107 /* Turn on Imm8 so that output_imm will generate it. */
6108 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6111 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6113 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6115 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6117 i
.op
[imm_slot
].imms
->X_add_number
6118 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6119 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6122 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6123 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6125 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6127 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6132 /* i.reg_operands MUST be the number of real register operands;
6133 implicit registers do not count. If there are 3 register
6134 operands, it must be a instruction with VexNDS. For a
6135 instruction with VexNDD, the destination register is encoded
6136 in VEX prefix. If there are 4 register operands, it must be
6137 a instruction with VEX prefix and 3 sources. */
6138 if (i
.mem_operands
== 0
6139 && ((i
.reg_operands
== 2
6140 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6141 || (i
.reg_operands
== 3
6142 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6143 || (i
.reg_operands
== 4 && vex_3_sources
)))
6151 /* When there are 3 operands, one of them may be immediate,
6152 which may be the first or the last operand. Otherwise,
6153 the first operand must be shift count register (cl) or it
6154 is an instruction with VexNDS. */
6155 gas_assert (i
.imm_operands
== 1
6156 || (i
.imm_operands
== 0
6157 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6158 || i
.types
[0].bitfield
.shiftcount
)));
6159 if (operand_type_check (i
.types
[0], imm
)
6160 || i
.types
[0].bitfield
.shiftcount
)
6166 /* When there are 4 operands, the first two must be 8bit
6167 immediate operands. The source operand will be the 3rd
6170 For instructions with VexNDS, if the first operand
6171 an imm8, the source operand is the 2nd one. If the last
6172 operand is imm8, the source operand is the first one. */
6173 gas_assert ((i
.imm_operands
== 2
6174 && i
.types
[0].bitfield
.imm8
6175 && i
.types
[1].bitfield
.imm8
)
6176 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6177 && i
.imm_operands
== 1
6178 && (i
.types
[0].bitfield
.imm8
6179 || i
.types
[i
.operands
- 1].bitfield
.imm8
6181 if (i
.imm_operands
== 2)
6185 if (i
.types
[0].bitfield
.imm8
)
6192 if (i
.tm
.opcode_modifier
.evex
)
6194 /* For EVEX instructions, when there are 5 operands, the
6195 first one must be immediate operand. If the second one
6196 is immediate operand, the source operand is the 3th
6197 one. If the last one is immediate operand, the source
6198 operand is the 2nd one. */
6199 gas_assert (i
.imm_operands
== 2
6200 && i
.tm
.opcode_modifier
.sae
6201 && operand_type_check (i
.types
[0], imm
));
6202 if (operand_type_check (i
.types
[1], imm
))
6204 else if (operand_type_check (i
.types
[4], imm
))
6218 /* RC/SAE operand could be between DEST and SRC. That happens
6219 when one operand is GPR and the other one is XMM/YMM/ZMM
6221 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6224 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6226 /* For instructions with VexNDS, the register-only source
6227 operand must be 32/64bit integer, XMM, YMM or ZMM
6228 register. It is encoded in VEX prefix. We need to
6229 clear RegMem bit before calling operand_type_equal. */
6231 i386_operand_type op
;
6234 /* Check register-only source operand when two source
6235 operands are swapped. */
6236 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6237 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6245 op
= i
.tm
.operand_types
[vvvv
];
6246 op
.bitfield
.regmem
= 0;
6247 if ((dest
+ 1) >= i
.operands
6248 || (!op
.bitfield
.reg32
6249 && op
.bitfield
.reg64
6250 && !operand_type_equal (&op
, ®xmm
)
6251 && !operand_type_equal (&op
, ®ymm
)
6252 && !operand_type_equal (&op
, ®zmm
)
6253 && !operand_type_equal (&op
, ®mask
)))
6255 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6261 /* One of the register operands will be encoded in the i.tm.reg
6262 field, the other in the combined i.tm.mode and i.tm.regmem
6263 fields. If no form of this instruction supports a memory
6264 destination operand, then we assume the source operand may
6265 sometimes be a memory operand and so we need to store the
6266 destination in the i.rm.reg field. */
6267 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6268 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6270 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6271 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6272 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6274 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6276 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6278 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6283 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6284 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6285 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6287 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6289 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6291 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6294 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6296 if (!i
.types
[0].bitfield
.control
6297 && !i
.types
[1].bitfield
.control
)
6299 i
.rex
&= ~(REX_R
| REX_B
);
6300 add_prefix (LOCK_PREFIX_OPCODE
);
6304 { /* If it's not 2 reg operands... */
6309 unsigned int fake_zero_displacement
= 0;
6312 for (op
= 0; op
< i
.operands
; op
++)
6313 if (operand_type_check (i
.types
[op
], anymem
))
6315 gas_assert (op
< i
.operands
);
6317 if (i
.tm
.opcode_modifier
.vecsib
)
6319 if (i
.index_reg
->reg_num
== RegEiz
6320 || i
.index_reg
->reg_num
== RegRiz
)
6323 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6326 i
.sib
.base
= NO_BASE_REGISTER
;
6327 i
.sib
.scale
= i
.log2_scale_factor
;
6328 /* No Vec_Disp8 if there is no base. */
6329 i
.types
[op
].bitfield
.vec_disp8
= 0;
6330 i
.types
[op
].bitfield
.disp8
= 0;
6331 i
.types
[op
].bitfield
.disp16
= 0;
6332 i
.types
[op
].bitfield
.disp64
= 0;
6333 if (flag_code
!= CODE_64BIT
)
6335 /* Must be 32 bit */
6336 i
.types
[op
].bitfield
.disp32
= 1;
6337 i
.types
[op
].bitfield
.disp32s
= 0;
6341 i
.types
[op
].bitfield
.disp32
= 0;
6342 i
.types
[op
].bitfield
.disp32s
= 1;
6345 i
.sib
.index
= i
.index_reg
->reg_num
;
6346 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6348 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6354 if (i
.base_reg
== 0)
6357 if (!i
.disp_operands
)
6359 fake_zero_displacement
= 1;
6360 /* Instructions with VSIB byte need 32bit displacement
6361 if there is no base register. */
6362 if (i
.tm
.opcode_modifier
.vecsib
)
6363 i
.types
[op
].bitfield
.disp32
= 1;
6365 if (i
.index_reg
== 0)
6367 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6368 /* Operand is just <disp> */
6369 if (flag_code
== CODE_64BIT
)
6371 /* 64bit mode overwrites the 32bit absolute
6372 addressing by RIP relative addressing and
6373 absolute addressing is encoded by one of the
6374 redundant SIB forms. */
6375 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6376 i
.sib
.base
= NO_BASE_REGISTER
;
6377 i
.sib
.index
= NO_INDEX_REGISTER
;
6378 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6379 ? disp32s
: disp32
);
6381 else if ((flag_code
== CODE_16BIT
)
6382 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6384 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6385 i
.types
[op
] = disp16
;
6389 i
.rm
.regmem
= NO_BASE_REGISTER
;
6390 i
.types
[op
] = disp32
;
6393 else if (!i
.tm
.opcode_modifier
.vecsib
)
6395 /* !i.base_reg && i.index_reg */
6396 if (i
.index_reg
->reg_num
== RegEiz
6397 || i
.index_reg
->reg_num
== RegRiz
)
6398 i
.sib
.index
= NO_INDEX_REGISTER
;
6400 i
.sib
.index
= i
.index_reg
->reg_num
;
6401 i
.sib
.base
= NO_BASE_REGISTER
;
6402 i
.sib
.scale
= i
.log2_scale_factor
;
6403 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6404 /* No Vec_Disp8 if there is no base. */
6405 i
.types
[op
].bitfield
.vec_disp8
= 0;
6406 i
.types
[op
].bitfield
.disp8
= 0;
6407 i
.types
[op
].bitfield
.disp16
= 0;
6408 i
.types
[op
].bitfield
.disp64
= 0;
6409 if (flag_code
!= CODE_64BIT
)
6411 /* Must be 32 bit */
6412 i
.types
[op
].bitfield
.disp32
= 1;
6413 i
.types
[op
].bitfield
.disp32s
= 0;
6417 i
.types
[op
].bitfield
.disp32
= 0;
6418 i
.types
[op
].bitfield
.disp32s
= 1;
6420 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6424 /* RIP addressing for 64bit mode. */
6425 else if (i
.base_reg
->reg_num
== RegRip
||
6426 i
.base_reg
->reg_num
== RegEip
)
6428 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6429 i
.rm
.regmem
= NO_BASE_REGISTER
;
6430 i
.types
[op
].bitfield
.disp8
= 0;
6431 i
.types
[op
].bitfield
.disp16
= 0;
6432 i
.types
[op
].bitfield
.disp32
= 0;
6433 i
.types
[op
].bitfield
.disp32s
= 1;
6434 i
.types
[op
].bitfield
.disp64
= 0;
6435 i
.types
[op
].bitfield
.vec_disp8
= 0;
6436 i
.flags
[op
] |= Operand_PCrel
;
6437 if (! i
.disp_operands
)
6438 fake_zero_displacement
= 1;
6440 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6442 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6443 switch (i
.base_reg
->reg_num
)
6446 if (i
.index_reg
== 0)
6448 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6449 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6453 if (i
.index_reg
== 0)
6456 if (operand_type_check (i
.types
[op
], disp
) == 0)
6458 /* fake (%bp) into 0(%bp) */
6459 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6460 i
.types
[op
].bitfield
.vec_disp8
= 1;
6462 i
.types
[op
].bitfield
.disp8
= 1;
6463 fake_zero_displacement
= 1;
6466 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6467 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6469 default: /* (%si) -> 4 or (%di) -> 5 */
6470 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6472 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6474 else /* i.base_reg and 32/64 bit mode */
6476 if (flag_code
== CODE_64BIT
6477 && operand_type_check (i
.types
[op
], disp
))
6479 i386_operand_type temp
;
6480 operand_type_set (&temp
, 0);
6481 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6482 temp
.bitfield
.vec_disp8
6483 = i
.types
[op
].bitfield
.vec_disp8
;
6485 if (i
.prefix
[ADDR_PREFIX
] == 0)
6486 i
.types
[op
].bitfield
.disp32s
= 1;
6488 i
.types
[op
].bitfield
.disp32
= 1;
6491 if (!i
.tm
.opcode_modifier
.vecsib
)
6492 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6493 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6495 i
.sib
.base
= i
.base_reg
->reg_num
;
6496 /* x86-64 ignores REX prefix bit here to avoid decoder
6498 if (!(i
.base_reg
->reg_flags
& RegRex
)
6499 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6500 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6502 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6504 fake_zero_displacement
= 1;
6505 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6506 i
.types
[op
].bitfield
.vec_disp8
= 1;
6508 i
.types
[op
].bitfield
.disp8
= 1;
6510 i
.sib
.scale
= i
.log2_scale_factor
;
6511 if (i
.index_reg
== 0)
6513 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6514 /* <disp>(%esp) becomes two byte modrm with no index
6515 register. We've already stored the code for esp
6516 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6517 Any base register besides %esp will not use the
6518 extra modrm byte. */
6519 i
.sib
.index
= NO_INDEX_REGISTER
;
6521 else if (!i
.tm
.opcode_modifier
.vecsib
)
6523 if (i
.index_reg
->reg_num
== RegEiz
6524 || i
.index_reg
->reg_num
== RegRiz
)
6525 i
.sib
.index
= NO_INDEX_REGISTER
;
6527 i
.sib
.index
= i
.index_reg
->reg_num
;
6528 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6529 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6534 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6535 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6539 if (!fake_zero_displacement
6543 fake_zero_displacement
= 1;
6544 if (i
.disp_encoding
== disp_encoding_8bit
)
6545 i
.types
[op
].bitfield
.disp8
= 1;
6547 i
.types
[op
].bitfield
.disp32
= 1;
6549 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6553 if (fake_zero_displacement
)
6555 /* Fakes a zero displacement assuming that i.types[op]
6556 holds the correct displacement size. */
6559 gas_assert (i
.op
[op
].disps
== 0);
6560 exp
= &disp_expressions
[i
.disp_operands
++];
6561 i
.op
[op
].disps
= exp
;
6562 exp
->X_op
= O_constant
;
6563 exp
->X_add_number
= 0;
6564 exp
->X_add_symbol
= (symbolS
*) 0;
6565 exp
->X_op_symbol
= (symbolS
*) 0;
6573 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6575 if (operand_type_check (i
.types
[0], imm
))
6576 i
.vex
.register_specifier
= NULL
;
6579 /* VEX.vvvv encodes one of the sources when the first
6580 operand is not an immediate. */
6581 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6582 i
.vex
.register_specifier
= i
.op
[0].regs
;
6584 i
.vex
.register_specifier
= i
.op
[1].regs
;
6587 /* Destination is a XMM register encoded in the ModRM.reg
6589 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6590 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6593 /* ModRM.rm and VEX.B encodes the other source. */
6594 if (!i
.mem_operands
)
6598 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6599 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6601 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6603 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6607 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6609 i
.vex
.register_specifier
= i
.op
[2].regs
;
6610 if (!i
.mem_operands
)
6613 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6614 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6618 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6619 (if any) based on i.tm.extension_opcode. Again, we must be
6620 careful to make sure that segment/control/debug/test/MMX
6621 registers are coded into the i.rm.reg field. */
6622 else if (i
.reg_operands
)
6625 unsigned int vex_reg
= ~0;
6627 for (op
= 0; op
< i
.operands
; op
++)
6628 if (i
.types
[op
].bitfield
.reg8
6629 || i
.types
[op
].bitfield
.reg16
6630 || i
.types
[op
].bitfield
.reg32
6631 || i
.types
[op
].bitfield
.reg64
6632 || i
.types
[op
].bitfield
.regmmx
6633 || i
.types
[op
].bitfield
.regxmm
6634 || i
.types
[op
].bitfield
.regymm
6635 || i
.types
[op
].bitfield
.regbnd
6636 || i
.types
[op
].bitfield
.regzmm
6637 || i
.types
[op
].bitfield
.regmask
6638 || i
.types
[op
].bitfield
.sreg2
6639 || i
.types
[op
].bitfield
.sreg3
6640 || i
.types
[op
].bitfield
.control
6641 || i
.types
[op
].bitfield
.debug
6642 || i
.types
[op
].bitfield
.test
)
6647 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6649 /* For instructions with VexNDS, the register-only
6650 source operand is encoded in VEX prefix. */
6651 gas_assert (mem
!= (unsigned int) ~0);
6656 gas_assert (op
< i
.operands
);
6660 /* Check register-only source operand when two source
6661 operands are swapped. */
6662 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6663 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6667 gas_assert (mem
== (vex_reg
+ 1)
6668 && op
< i
.operands
);
6673 gas_assert (vex_reg
< i
.operands
);
6677 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6679 /* For instructions with VexNDD, the register destination
6680 is encoded in VEX prefix. */
6681 if (i
.mem_operands
== 0)
6683 /* There is no memory operand. */
6684 gas_assert ((op
+ 2) == i
.operands
);
6689 /* There are only 2 operands. */
6690 gas_assert (op
< 2 && i
.operands
== 2);
6695 gas_assert (op
< i
.operands
);
6697 if (vex_reg
!= (unsigned int) ~0)
6699 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6701 if (type
->bitfield
.reg32
!= 1
6702 && type
->bitfield
.reg64
!= 1
6703 && !operand_type_equal (type
, ®xmm
)
6704 && !operand_type_equal (type
, ®ymm
)
6705 && !operand_type_equal (type
, ®zmm
)
6706 && !operand_type_equal (type
, ®mask
))
6709 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6712 /* Don't set OP operand twice. */
6715 /* If there is an extension opcode to put here, the
6716 register number must be put into the regmem field. */
6717 if (i
.tm
.extension_opcode
!= None
)
6719 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6720 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6722 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6727 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6728 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6730 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6735 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6736 must set it to 3 to indicate this is a register operand
6737 in the regmem field. */
6738 if (!i
.mem_operands
)
6742 /* Fill in i.rm.reg field with extension opcode (if any). */
6743 if (i
.tm
.extension_opcode
!= None
)
6744 i
.rm
.reg
= i
.tm
.extension_opcode
;
6750 output_branch (void)
6756 relax_substateT subtype
;
6760 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6761 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6764 if (i
.prefix
[DATA_PREFIX
] != 0)
6770 /* Pentium4 branch hints. */
6771 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6772 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6777 if (i
.prefix
[REX_PREFIX
] != 0)
6783 /* BND prefixed jump. */
6784 if (i
.prefix
[BND_PREFIX
] != 0)
6786 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6790 if (i
.prefixes
!= 0 && !intel_syntax
)
6791 as_warn (_("skipping prefixes on this instruction"));
6793 /* It's always a symbol; End frag & setup for relax.
6794 Make sure there is enough room in this frag for the largest
6795 instruction we may generate in md_convert_frag. This is 2
6796 bytes for the opcode and room for the prefix and largest
6798 frag_grow (prefix
+ 2 + 4);
6799 /* Prefix and 1 opcode byte go in fr_fix. */
6800 p
= frag_more (prefix
+ 1);
6801 if (i
.prefix
[DATA_PREFIX
] != 0)
6802 *p
++ = DATA_PREFIX_OPCODE
;
6803 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6804 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6805 *p
++ = i
.prefix
[SEG_PREFIX
];
6806 if (i
.prefix
[REX_PREFIX
] != 0)
6807 *p
++ = i
.prefix
[REX_PREFIX
];
6808 *p
= i
.tm
.base_opcode
;
6810 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6811 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6812 else if (cpu_arch_flags
.bitfield
.cpui386
)
6813 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6815 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6818 sym
= i
.op
[0].disps
->X_add_symbol
;
6819 off
= i
.op
[0].disps
->X_add_number
;
6821 if (i
.op
[0].disps
->X_op
!= O_constant
6822 && i
.op
[0].disps
->X_op
!= O_symbol
)
6824 /* Handle complex expressions. */
6825 sym
= make_expr_symbol (i
.op
[0].disps
);
6829 /* 1 possible extra opcode + 4 byte displacement go in var part.
6830 Pass reloc in fr_var. */
6831 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6841 if (i
.tm
.opcode_modifier
.jumpbyte
)
6843 /* This is a loop or jecxz type instruction. */
6845 if (i
.prefix
[ADDR_PREFIX
] != 0)
6847 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6850 /* Pentium4 branch hints. */
6851 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6852 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6854 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6863 if (flag_code
== CODE_16BIT
)
6866 if (i
.prefix
[DATA_PREFIX
] != 0)
6868 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6878 if (i
.prefix
[REX_PREFIX
] != 0)
6880 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6884 /* BND prefixed jump. */
6885 if (i
.prefix
[BND_PREFIX
] != 0)
6887 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6891 if (i
.prefixes
!= 0 && !intel_syntax
)
6892 as_warn (_("skipping prefixes on this instruction"));
6894 p
= frag_more (i
.tm
.opcode_length
+ size
);
6895 switch (i
.tm
.opcode_length
)
6898 *p
++ = i
.tm
.base_opcode
>> 8;
6900 *p
++ = i
.tm
.base_opcode
;
6906 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6907 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6909 /* All jumps handled here are signed, but don't use a signed limit
6910 check for 32 and 16 bit jumps as we want to allow wrap around at
6911 4G and 64k respectively. */
6913 fixP
->fx_signed
= 1;
6917 output_interseg_jump (void)
6925 if (flag_code
== CODE_16BIT
)
6929 if (i
.prefix
[DATA_PREFIX
] != 0)
6935 if (i
.prefix
[REX_PREFIX
] != 0)
6945 if (i
.prefixes
!= 0 && !intel_syntax
)
6946 as_warn (_("skipping prefixes on this instruction"));
6948 /* 1 opcode; 2 segment; offset */
6949 p
= frag_more (prefix
+ 1 + 2 + size
);
6951 if (i
.prefix
[DATA_PREFIX
] != 0)
6952 *p
++ = DATA_PREFIX_OPCODE
;
6954 if (i
.prefix
[REX_PREFIX
] != 0)
6955 *p
++ = i
.prefix
[REX_PREFIX
];
6957 *p
++ = i
.tm
.base_opcode
;
6958 if (i
.op
[1].imms
->X_op
== O_constant
)
6960 offsetT n
= i
.op
[1].imms
->X_add_number
;
6963 && !fits_in_unsigned_word (n
)
6964 && !fits_in_signed_word (n
))
6966 as_bad (_("16-bit jump out of range"));
6969 md_number_to_chars (p
, n
, size
);
6972 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6973 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6974 if (i
.op
[0].imms
->X_op
!= O_constant
)
6975 as_bad (_("can't handle non absolute segment in `%s'"),
6977 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6983 fragS
*insn_start_frag
;
6984 offsetT insn_start_off
;
6986 /* Tie dwarf2 debug info to the address at the start of the insn.
6987 We can't do this after the insn has been output as the current
6988 frag may have been closed off. eg. by frag_var. */
6989 dwarf2_emit_insn (0);
6991 insn_start_frag
= frag_now
;
6992 insn_start_off
= frag_now_fix ();
6995 if (i
.tm
.opcode_modifier
.jump
)
6997 else if (i
.tm
.opcode_modifier
.jumpbyte
6998 || i
.tm
.opcode_modifier
.jumpdword
)
7000 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7001 output_interseg_jump ();
7004 /* Output normal instructions here. */
7008 unsigned int prefix
;
7011 && i
.tm
.base_opcode
== 0xfae
7013 && i
.imm_operands
== 1
7014 && (i
.op
[0].imms
->X_add_number
== 0xe8
7015 || i
.op
[0].imms
->X_add_number
== 0xf0
7016 || i
.op
[0].imms
->X_add_number
== 0xf8))
7018 /* Encode lfence, mfence, and sfence as
7019 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7020 offsetT val
= 0x240483f0ULL
;
7022 md_number_to_chars (p
, val
, 5);
7026 /* Some processors fail on LOCK prefix. This options makes
7027 assembler ignore LOCK prefix and serves as a workaround. */
7028 if (omit_lock_prefix
)
7030 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7032 i
.prefix
[LOCK_PREFIX
] = 0;
7035 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7036 don't need the explicit prefix. */
7037 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7039 switch (i
.tm
.opcode_length
)
7042 if (i
.tm
.base_opcode
& 0xff000000)
7044 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7049 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7051 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7052 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7055 if (prefix
!= REPE_PREFIX_OPCODE
7056 || (i
.prefix
[REP_PREFIX
]
7057 != REPE_PREFIX_OPCODE
))
7058 add_prefix (prefix
);
7061 add_prefix (prefix
);
7070 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7071 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7072 R_X86_64_GOTTPOFF relocation so that linker can safely
7073 perform IE->LE optimization. */
7074 if (x86_elf_abi
== X86_64_X32_ABI
7076 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7077 && i
.prefix
[REX_PREFIX
] == 0)
7078 add_prefix (REX_OPCODE
);
7081 /* The prefix bytes. */
7082 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7084 FRAG_APPEND_1_CHAR (*q
);
7088 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7093 /* REX byte is encoded in VEX prefix. */
7097 FRAG_APPEND_1_CHAR (*q
);
7100 /* There should be no other prefixes for instructions
7105 /* For EVEX instructions i.vrex should become 0 after
7106 build_evex_prefix. For VEX instructions upper 16 registers
7107 aren't available, so VREX should be 0. */
7110 /* Now the VEX prefix. */
7111 p
= frag_more (i
.vex
.length
);
7112 for (j
= 0; j
< i
.vex
.length
; j
++)
7113 p
[j
] = i
.vex
.bytes
[j
];
7116 /* Now the opcode; be careful about word order here! */
7117 if (i
.tm
.opcode_length
== 1)
7119 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7123 switch (i
.tm
.opcode_length
)
7127 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7128 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7132 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7142 /* Put out high byte first: can't use md_number_to_chars! */
7143 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7144 *p
= i
.tm
.base_opcode
& 0xff;
7147 /* Now the modrm byte and sib byte (if present). */
7148 if (i
.tm
.opcode_modifier
.modrm
)
7150 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7153 /* If i.rm.regmem == ESP (4)
7154 && i.rm.mode != (Register mode)
7156 ==> need second modrm byte. */
7157 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7159 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7160 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7162 | i
.sib
.scale
<< 6));
7165 if (i
.disp_operands
)
7166 output_disp (insn_start_frag
, insn_start_off
);
7169 output_imm (insn_start_frag
, insn_start_off
);
7175 pi ("" /*line*/, &i
);
7177 #endif /* DEBUG386 */
7180 /* Return the size of the displacement operand N. */
7183 disp_size (unsigned int n
)
7187 /* Vec_Disp8 has to be 8bit. */
7188 if (i
.types
[n
].bitfield
.vec_disp8
)
7190 else if (i
.types
[n
].bitfield
.disp64
)
7192 else if (i
.types
[n
].bitfield
.disp8
)
7194 else if (i
.types
[n
].bitfield
.disp16
)
7199 /* Return the size of the immediate operand N. */
7202 imm_size (unsigned int n
)
7205 if (i
.types
[n
].bitfield
.imm64
)
7207 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7209 else if (i
.types
[n
].bitfield
.imm16
)
7215 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7220 for (n
= 0; n
< i
.operands
; n
++)
7222 if (i
.types
[n
].bitfield
.vec_disp8
7223 || operand_type_check (i
.types
[n
], disp
))
7225 if (i
.op
[n
].disps
->X_op
== O_constant
)
7227 int size
= disp_size (n
);
7228 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7230 if (i
.types
[n
].bitfield
.vec_disp8
)
7232 val
= offset_in_range (val
, size
);
7233 p
= frag_more (size
);
7234 md_number_to_chars (p
, val
, size
);
7238 enum bfd_reloc_code_real reloc_type
;
7239 int size
= disp_size (n
);
7240 int sign
= i
.types
[n
].bitfield
.disp32s
;
7241 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7244 /* We can't have 8 bit displacement here. */
7245 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7247 /* The PC relative address is computed relative
7248 to the instruction boundary, so in case immediate
7249 fields follows, we need to adjust the value. */
7250 if (pcrel
&& i
.imm_operands
)
7255 for (n1
= 0; n1
< i
.operands
; n1
++)
7256 if (operand_type_check (i
.types
[n1
], imm
))
7258 /* Only one immediate is allowed for PC
7259 relative address. */
7260 gas_assert (sz
== 0);
7262 i
.op
[n
].disps
->X_add_number
-= sz
;
7264 /* We should find the immediate. */
7265 gas_assert (sz
!= 0);
7268 p
= frag_more (size
);
7269 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7271 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7272 && (((reloc_type
== BFD_RELOC_32
7273 || reloc_type
== BFD_RELOC_X86_64_32S
7274 || (reloc_type
== BFD_RELOC_64
7276 && (i
.op
[n
].disps
->X_op
== O_symbol
7277 || (i
.op
[n
].disps
->X_op
== O_add
7278 && ((symbol_get_value_expression
7279 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7281 || reloc_type
== BFD_RELOC_32_PCREL
))
7285 if (insn_start_frag
== frag_now
)
7286 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7291 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7292 for (fr
= insn_start_frag
->fr_next
;
7293 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7295 add
+= p
- frag_now
->fr_literal
;
7300 reloc_type
= BFD_RELOC_386_GOTPC
;
7301 i
.op
[n
].imms
->X_add_number
+= add
;
7303 else if (reloc_type
== BFD_RELOC_64
)
7304 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7306 /* Don't do the adjustment for x86-64, as there
7307 the pcrel addressing is relative to the _next_
7308 insn, and that is taken care of in other code. */
7309 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7311 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7312 size
, i
.op
[n
].disps
, pcrel
,
7314 /* Check for "call/jmp *mem", "mov mem, %reg",
7315 "test %reg, mem" and "binop mem, %reg" where binop
7316 is one of adc, add, and, cmp, or, sbb, sub, xor
7317 instructions. Always generate R_386_GOT32X for
7318 "sym*GOT" operand in 32-bit mode. */
7319 if ((generate_relax_relocations
7322 && i
.rm
.regmem
== 5))
7324 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7325 && ((i
.operands
== 1
7326 && i
.tm
.base_opcode
== 0xff
7327 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7329 && (i
.tm
.base_opcode
== 0x8b
7330 || i
.tm
.base_opcode
== 0x85
7331 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7335 fixP
->fx_tcbit
= i
.rex
!= 0;
7337 && (i
.base_reg
->reg_num
== RegRip
7338 || i
.base_reg
->reg_num
== RegEip
))
7339 fixP
->fx_tcbit2
= 1;
7342 fixP
->fx_tcbit2
= 1;
7350 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7355 for (n
= 0; n
< i
.operands
; n
++)
7357 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7358 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7361 if (operand_type_check (i
.types
[n
], imm
))
7363 if (i
.op
[n
].imms
->X_op
== O_constant
)
7365 int size
= imm_size (n
);
7368 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7370 p
= frag_more (size
);
7371 md_number_to_chars (p
, val
, size
);
7375 /* Not absolute_section.
7376 Need a 32-bit fixup (don't support 8bit
7377 non-absolute imms). Try to support other
7379 enum bfd_reloc_code_real reloc_type
;
7380 int size
= imm_size (n
);
7383 if (i
.types
[n
].bitfield
.imm32s
7384 && (i
.suffix
== QWORD_MNEM_SUFFIX
7385 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7390 p
= frag_more (size
);
7391 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7393 /* This is tough to explain. We end up with this one if we
7394 * have operands that look like
7395 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7396 * obtain the absolute address of the GOT, and it is strongly
7397 * preferable from a performance point of view to avoid using
7398 * a runtime relocation for this. The actual sequence of
7399 * instructions often look something like:
7404 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7406 * The call and pop essentially return the absolute address
7407 * of the label .L66 and store it in %ebx. The linker itself
7408 * will ultimately change the first operand of the addl so
7409 * that %ebx points to the GOT, but to keep things simple, the
7410 * .o file must have this operand set so that it generates not
7411 * the absolute address of .L66, but the absolute address of
7412 * itself. This allows the linker itself simply treat a GOTPC
7413 * relocation as asking for a pcrel offset to the GOT to be
7414 * added in, and the addend of the relocation is stored in the
7415 * operand field for the instruction itself.
7417 * Our job here is to fix the operand so that it would add
7418 * the correct offset so that %ebx would point to itself. The
7419 * thing that is tricky is that .-.L66 will point to the
7420 * beginning of the instruction, so we need to further modify
7421 * the operand so that it will point to itself. There are
7422 * other cases where you have something like:
7424 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7426 * and here no correction would be required. Internally in
7427 * the assembler we treat operands of this form as not being
7428 * pcrel since the '.' is explicitly mentioned, and I wonder
7429 * whether it would simplify matters to do it this way. Who
7430 * knows. In earlier versions of the PIC patches, the
7431 * pcrel_adjust field was used to store the correction, but
7432 * since the expression is not pcrel, I felt it would be
7433 * confusing to do it this way. */
7435 if ((reloc_type
== BFD_RELOC_32
7436 || reloc_type
== BFD_RELOC_X86_64_32S
7437 || reloc_type
== BFD_RELOC_64
)
7439 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7440 && (i
.op
[n
].imms
->X_op
== O_symbol
7441 || (i
.op
[n
].imms
->X_op
== O_add
7442 && ((symbol_get_value_expression
7443 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7448 if (insn_start_frag
== frag_now
)
7449 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7454 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7455 for (fr
= insn_start_frag
->fr_next
;
7456 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7458 add
+= p
- frag_now
->fr_literal
;
7462 reloc_type
= BFD_RELOC_386_GOTPC
;
7464 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7466 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7467 i
.op
[n
].imms
->X_add_number
+= add
;
7469 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7470 i
.op
[n
].imms
, 0, reloc_type
);
7476 /* x86_cons_fix_new is called via the expression parsing code when a
7477 reloc is needed. We use this hook to get the correct .got reloc. */
7478 static int cons_sign
= -1;
7481 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7482 expressionS
*exp
, bfd_reloc_code_real_type r
)
7484 r
= reloc (len
, 0, cons_sign
, r
);
7487 if (exp
->X_op
== O_secrel
)
7489 exp
->X_op
= O_symbol
;
7490 r
= BFD_RELOC_32_SECREL
;
7494 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7497 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7498 purpose of the `.dc.a' internal pseudo-op. */
7501 x86_address_bytes (void)
7503 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7505 return stdoutput
->arch_info
->bits_per_address
/ 8;
7508 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7510 # define lex_got(reloc, adjust, types) NULL
7512 /* Parse operands of the form
7513 <symbol>@GOTOFF+<nnn>
7514 and similar .plt or .got references.
7516 If we find one, set up the correct relocation in RELOC and copy the
7517 input string, minus the `@GOTOFF' into a malloc'd buffer for
7518 parsing by the calling routine. Return this buffer, and if ADJUST
7519 is non-null set it to the length of the string we removed from the
7520 input line. Otherwise return NULL. */
7522 lex_got (enum bfd_reloc_code_real
*rel
,
7524 i386_operand_type
*types
)
7526 /* Some of the relocations depend on the size of what field is to
7527 be relocated. But in our callers i386_immediate and i386_displacement
7528 we don't yet know the operand size (this will be set by insn
7529 matching). Hence we record the word32 relocation here,
7530 and adjust the reloc according to the real size in reloc(). */
7531 static const struct {
7534 const enum bfd_reloc_code_real rel
[2];
7535 const i386_operand_type types64
;
7537 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7538 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7540 OPERAND_TYPE_IMM32_64
},
7542 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7543 BFD_RELOC_X86_64_PLTOFF64
},
7544 OPERAND_TYPE_IMM64
},
7545 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7546 BFD_RELOC_X86_64_PLT32
},
7547 OPERAND_TYPE_IMM32_32S_DISP32
},
7548 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7549 BFD_RELOC_X86_64_GOTPLT64
},
7550 OPERAND_TYPE_IMM64_DISP64
},
7551 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7552 BFD_RELOC_X86_64_GOTOFF64
},
7553 OPERAND_TYPE_IMM64_DISP64
},
7554 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7555 BFD_RELOC_X86_64_GOTPCREL
},
7556 OPERAND_TYPE_IMM32_32S_DISP32
},
7557 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7558 BFD_RELOC_X86_64_TLSGD
},
7559 OPERAND_TYPE_IMM32_32S_DISP32
},
7560 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7561 _dummy_first_bfd_reloc_code_real
},
7562 OPERAND_TYPE_NONE
},
7563 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7564 BFD_RELOC_X86_64_TLSLD
},
7565 OPERAND_TYPE_IMM32_32S_DISP32
},
7566 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7567 BFD_RELOC_X86_64_GOTTPOFF
},
7568 OPERAND_TYPE_IMM32_32S_DISP32
},
7569 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7570 BFD_RELOC_X86_64_TPOFF32
},
7571 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7572 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7573 _dummy_first_bfd_reloc_code_real
},
7574 OPERAND_TYPE_NONE
},
7575 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7576 BFD_RELOC_X86_64_DTPOFF32
},
7577 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7578 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7579 _dummy_first_bfd_reloc_code_real
},
7580 OPERAND_TYPE_NONE
},
7581 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7582 _dummy_first_bfd_reloc_code_real
},
7583 OPERAND_TYPE_NONE
},
7584 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7585 BFD_RELOC_X86_64_GOT32
},
7586 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7587 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7588 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7589 OPERAND_TYPE_IMM32_32S_DISP32
},
7590 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7591 BFD_RELOC_X86_64_TLSDESC_CALL
},
7592 OPERAND_TYPE_IMM32_32S_DISP32
},
7597 #if defined (OBJ_MAYBE_ELF)
7602 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7603 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7606 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7608 int len
= gotrel
[j
].len
;
7609 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7611 if (gotrel
[j
].rel
[object_64bit
] != 0)
7614 char *tmpbuf
, *past_reloc
;
7616 *rel
= gotrel
[j
].rel
[object_64bit
];
7620 if (flag_code
!= CODE_64BIT
)
7622 types
->bitfield
.imm32
= 1;
7623 types
->bitfield
.disp32
= 1;
7626 *types
= gotrel
[j
].types64
;
7629 if (j
!= 0 && GOT_symbol
== NULL
)
7630 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7632 /* The length of the first part of our input line. */
7633 first
= cp
- input_line_pointer
;
7635 /* The second part goes from after the reloc token until
7636 (and including) an end_of_line char or comma. */
7637 past_reloc
= cp
+ 1 + len
;
7639 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7641 second
= cp
+ 1 - past_reloc
;
7643 /* Allocate and copy string. The trailing NUL shouldn't
7644 be necessary, but be safe. */
7645 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7646 memcpy (tmpbuf
, input_line_pointer
, first
);
7647 if (second
!= 0 && *past_reloc
!= ' ')
7648 /* Replace the relocation token with ' ', so that
7649 errors like foo@GOTOFF1 will be detected. */
7650 tmpbuf
[first
++] = ' ';
7652 /* Increment length by 1 if the relocation token is
7657 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7658 tmpbuf
[first
+ second
] = '\0';
7662 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7663 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7668 /* Might be a symbol version string. Don't as_bad here. */
7677 /* Parse operands of the form
7678 <symbol>@SECREL32+<nnn>
7680 If we find one, set up the correct relocation in RELOC and copy the
7681 input string, minus the `@SECREL32' into a malloc'd buffer for
7682 parsing by the calling routine. Return this buffer, and if ADJUST
7683 is non-null set it to the length of the string we removed from the
7684 input line. Otherwise return NULL.
7686 This function is copied from the ELF version above adjusted for PE targets. */
7689 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7690 int *adjust ATTRIBUTE_UNUSED
,
7691 i386_operand_type
*types
)
7697 const enum bfd_reloc_code_real rel
[2];
7698 const i386_operand_type types64
;
7702 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7703 BFD_RELOC_32_SECREL
},
7704 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7710 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7711 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7714 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7716 int len
= gotrel
[j
].len
;
7718 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7720 if (gotrel
[j
].rel
[object_64bit
] != 0)
7723 char *tmpbuf
, *past_reloc
;
7725 *rel
= gotrel
[j
].rel
[object_64bit
];
7731 if (flag_code
!= CODE_64BIT
)
7733 types
->bitfield
.imm32
= 1;
7734 types
->bitfield
.disp32
= 1;
7737 *types
= gotrel
[j
].types64
;
7740 /* The length of the first part of our input line. */
7741 first
= cp
- input_line_pointer
;
7743 /* The second part goes from after the reloc token until
7744 (and including) an end_of_line char or comma. */
7745 past_reloc
= cp
+ 1 + len
;
7747 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7749 second
= cp
+ 1 - past_reloc
;
7751 /* Allocate and copy string. The trailing NUL shouldn't
7752 be necessary, but be safe. */
7753 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7754 memcpy (tmpbuf
, input_line_pointer
, first
);
7755 if (second
!= 0 && *past_reloc
!= ' ')
7756 /* Replace the relocation token with ' ', so that
7757 errors like foo@SECLREL321 will be detected. */
7758 tmpbuf
[first
++] = ' ';
7759 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7760 tmpbuf
[first
+ second
] = '\0';
7764 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7765 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7770 /* Might be a symbol version string. Don't as_bad here. */
7776 bfd_reloc_code_real_type
7777 x86_cons (expressionS
*exp
, int size
)
7779 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7781 intel_syntax
= -intel_syntax
;
7784 if (size
== 4 || (object_64bit
&& size
== 8))
7786 /* Handle @GOTOFF and the like in an expression. */
7788 char *gotfree_input_line
;
7791 save
= input_line_pointer
;
7792 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7793 if (gotfree_input_line
)
7794 input_line_pointer
= gotfree_input_line
;
7798 if (gotfree_input_line
)
7800 /* expression () has merrily parsed up to the end of line,
7801 or a comma - in the wrong buffer. Transfer how far
7802 input_line_pointer has moved to the right buffer. */
7803 input_line_pointer
= (save
7804 + (input_line_pointer
- gotfree_input_line
)
7806 free (gotfree_input_line
);
7807 if (exp
->X_op
== O_constant
7808 || exp
->X_op
== O_absent
7809 || exp
->X_op
== O_illegal
7810 || exp
->X_op
== O_register
7811 || exp
->X_op
== O_big
)
7813 char c
= *input_line_pointer
;
7814 *input_line_pointer
= 0;
7815 as_bad (_("missing or invalid expression `%s'"), save
);
7816 *input_line_pointer
= c
;
7823 intel_syntax
= -intel_syntax
;
7826 i386_intel_simplify (exp
);
7832 signed_cons (int size
)
7834 if (flag_code
== CODE_64BIT
)
7842 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7849 if (exp
.X_op
== O_symbol
)
7850 exp
.X_op
= O_secrel
;
7852 emit_expr (&exp
, 4);
7854 while (*input_line_pointer
++ == ',');
7856 input_line_pointer
--;
7857 demand_empty_rest_of_line ();
7861 /* Handle Vector operations. */
7864 check_VecOperations (char *op_string
, char *op_end
)
7866 const reg_entry
*mask
;
7871 && (op_end
== NULL
|| op_string
< op_end
))
7874 if (*op_string
== '{')
7878 /* Check broadcasts. */
7879 if (strncmp (op_string
, "1to", 3) == 0)
7884 goto duplicated_vec_op
;
7887 if (*op_string
== '8')
7888 bcst_type
= BROADCAST_1TO8
;
7889 else if (*op_string
== '4')
7890 bcst_type
= BROADCAST_1TO4
;
7891 else if (*op_string
== '2')
7892 bcst_type
= BROADCAST_1TO2
;
7893 else if (*op_string
== '1'
7894 && *(op_string
+1) == '6')
7896 bcst_type
= BROADCAST_1TO16
;
7901 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7906 broadcast_op
.type
= bcst_type
;
7907 broadcast_op
.operand
= this_operand
;
7908 i
.broadcast
= &broadcast_op
;
7910 /* Check masking operation. */
7911 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7913 /* k0 can't be used for write mask. */
7914 if (mask
->reg_num
== 0)
7916 as_bad (_("`%s' can't be used for write mask"),
7923 mask_op
.mask
= mask
;
7924 mask_op
.zeroing
= 0;
7925 mask_op
.operand
= this_operand
;
7931 goto duplicated_vec_op
;
7933 i
.mask
->mask
= mask
;
7935 /* Only "{z}" is allowed here. No need to check
7936 zeroing mask explicitly. */
7937 if (i
.mask
->operand
!= this_operand
)
7939 as_bad (_("invalid write mask `%s'"), saved
);
7946 /* Check zeroing-flag for masking operation. */
7947 else if (*op_string
== 'z')
7951 mask_op
.mask
= NULL
;
7952 mask_op
.zeroing
= 1;
7953 mask_op
.operand
= this_operand
;
7958 if (i
.mask
->zeroing
)
7961 as_bad (_("duplicated `%s'"), saved
);
7965 i
.mask
->zeroing
= 1;
7967 /* Only "{%k}" is allowed here. No need to check mask
7968 register explicitly. */
7969 if (i
.mask
->operand
!= this_operand
)
7971 as_bad (_("invalid zeroing-masking `%s'"),
7980 goto unknown_vec_op
;
7982 if (*op_string
!= '}')
7984 as_bad (_("missing `}' in `%s'"), saved
);
7991 /* We don't know this one. */
7992 as_bad (_("unknown vector operation: `%s'"), saved
);
8000 i386_immediate (char *imm_start
)
8002 char *save_input_line_pointer
;
8003 char *gotfree_input_line
;
8006 i386_operand_type types
;
8008 operand_type_set (&types
, ~0);
8010 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8012 as_bad (_("at most %d immediate operands are allowed"),
8013 MAX_IMMEDIATE_OPERANDS
);
8017 exp
= &im_expressions
[i
.imm_operands
++];
8018 i
.op
[this_operand
].imms
= exp
;
8020 if (is_space_char (*imm_start
))
8023 save_input_line_pointer
= input_line_pointer
;
8024 input_line_pointer
= imm_start
;
8026 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8027 if (gotfree_input_line
)
8028 input_line_pointer
= gotfree_input_line
;
8030 exp_seg
= expression (exp
);
8034 /* Handle vector operations. */
8035 if (*input_line_pointer
== '{')
8037 input_line_pointer
= check_VecOperations (input_line_pointer
,
8039 if (input_line_pointer
== NULL
)
8043 if (*input_line_pointer
)
8044 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8046 input_line_pointer
= save_input_line_pointer
;
8047 if (gotfree_input_line
)
8049 free (gotfree_input_line
);
8051 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8052 exp
->X_op
= O_illegal
;
8055 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8059 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8060 i386_operand_type types
, const char *imm_start
)
8062 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8065 as_bad (_("missing or invalid immediate expression `%s'"),
8069 else if (exp
->X_op
== O_constant
)
8071 /* Size it properly later. */
8072 i
.types
[this_operand
].bitfield
.imm64
= 1;
8073 /* If not 64bit, sign extend val. */
8074 if (flag_code
!= CODE_64BIT
8075 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8077 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8079 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8080 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8081 && exp_seg
!= absolute_section
8082 && exp_seg
!= text_section
8083 && exp_seg
!= data_section
8084 && exp_seg
!= bss_section
8085 && exp_seg
!= undefined_section
8086 && !bfd_is_com_section (exp_seg
))
8088 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8092 else if (!intel_syntax
&& exp_seg
== reg_section
)
8095 as_bad (_("illegal immediate register operand %s"), imm_start
);
8100 /* This is an address. The size of the address will be
8101 determined later, depending on destination register,
8102 suffix, or the default for the section. */
8103 i
.types
[this_operand
].bitfield
.imm8
= 1;
8104 i
.types
[this_operand
].bitfield
.imm16
= 1;
8105 i
.types
[this_operand
].bitfield
.imm32
= 1;
8106 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8107 i
.types
[this_operand
].bitfield
.imm64
= 1;
8108 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8116 i386_scale (char *scale
)
8119 char *save
= input_line_pointer
;
8121 input_line_pointer
= scale
;
8122 val
= get_absolute_expression ();
8127 i
.log2_scale_factor
= 0;
8130 i
.log2_scale_factor
= 1;
8133 i
.log2_scale_factor
= 2;
8136 i
.log2_scale_factor
= 3;
8140 char sep
= *input_line_pointer
;
8142 *input_line_pointer
= '\0';
8143 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8145 *input_line_pointer
= sep
;
8146 input_line_pointer
= save
;
8150 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8152 as_warn (_("scale factor of %d without an index register"),
8153 1 << i
.log2_scale_factor
);
8154 i
.log2_scale_factor
= 0;
8156 scale
= input_line_pointer
;
8157 input_line_pointer
= save
;
8162 i386_displacement (char *disp_start
, char *disp_end
)
8166 char *save_input_line_pointer
;
8167 char *gotfree_input_line
;
8169 i386_operand_type bigdisp
, types
= anydisp
;
8172 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8174 as_bad (_("at most %d displacement operands are allowed"),
8175 MAX_MEMORY_OPERANDS
);
8179 operand_type_set (&bigdisp
, 0);
8180 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8181 || (!current_templates
->start
->opcode_modifier
.jump
8182 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8184 bigdisp
.bitfield
.disp32
= 1;
8185 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8186 if (flag_code
== CODE_64BIT
)
8190 bigdisp
.bitfield
.disp32s
= 1;
8191 bigdisp
.bitfield
.disp64
= 1;
8194 else if ((flag_code
== CODE_16BIT
) ^ override
)
8196 bigdisp
.bitfield
.disp32
= 0;
8197 bigdisp
.bitfield
.disp16
= 1;
8202 /* For PC-relative branches, the width of the displacement
8203 is dependent upon data size, not address size. */
8204 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8205 if (flag_code
== CODE_64BIT
)
8207 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8208 bigdisp
.bitfield
.disp16
= 1;
8211 bigdisp
.bitfield
.disp32
= 1;
8212 bigdisp
.bitfield
.disp32s
= 1;
8218 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8220 : LONG_MNEM_SUFFIX
));
8221 bigdisp
.bitfield
.disp32
= 1;
8222 if ((flag_code
== CODE_16BIT
) ^ override
)
8224 bigdisp
.bitfield
.disp32
= 0;
8225 bigdisp
.bitfield
.disp16
= 1;
8229 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8232 exp
= &disp_expressions
[i
.disp_operands
];
8233 i
.op
[this_operand
].disps
= exp
;
8235 save_input_line_pointer
= input_line_pointer
;
8236 input_line_pointer
= disp_start
;
8237 END_STRING_AND_SAVE (disp_end
);
8239 #ifndef GCC_ASM_O_HACK
8240 #define GCC_ASM_O_HACK 0
8243 END_STRING_AND_SAVE (disp_end
+ 1);
8244 if (i
.types
[this_operand
].bitfield
.baseIndex
8245 && displacement_string_end
[-1] == '+')
8247 /* This hack is to avoid a warning when using the "o"
8248 constraint within gcc asm statements.
8251 #define _set_tssldt_desc(n,addr,limit,type) \
8252 __asm__ __volatile__ ( \
8254 "movw %w1,2+%0\n\t" \
8256 "movb %b1,4+%0\n\t" \
8257 "movb %4,5+%0\n\t" \
8258 "movb $0,6+%0\n\t" \
8259 "movb %h1,7+%0\n\t" \
8261 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8263 This works great except that the output assembler ends
8264 up looking a bit weird if it turns out that there is
8265 no offset. You end up producing code that looks like:
8278 So here we provide the missing zero. */
8280 *displacement_string_end
= '0';
8283 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8284 if (gotfree_input_line
)
8285 input_line_pointer
= gotfree_input_line
;
8287 exp_seg
= expression (exp
);
8290 if (*input_line_pointer
)
8291 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8293 RESTORE_END_STRING (disp_end
+ 1);
8295 input_line_pointer
= save_input_line_pointer
;
8296 if (gotfree_input_line
)
8298 free (gotfree_input_line
);
8300 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8301 exp
->X_op
= O_illegal
;
8304 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8306 RESTORE_END_STRING (disp_end
);
8312 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8313 i386_operand_type types
, const char *disp_start
)
8315 i386_operand_type bigdisp
;
8318 /* We do this to make sure that the section symbol is in
8319 the symbol table. We will ultimately change the relocation
8320 to be relative to the beginning of the section. */
8321 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8322 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8323 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8325 if (exp
->X_op
!= O_symbol
)
8328 if (S_IS_LOCAL (exp
->X_add_symbol
)
8329 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8330 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8331 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8332 exp
->X_op
= O_subtract
;
8333 exp
->X_op_symbol
= GOT_symbol
;
8334 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8335 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8336 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8337 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8339 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8342 else if (exp
->X_op
== O_absent
8343 || exp
->X_op
== O_illegal
8344 || exp
->X_op
== O_big
)
8347 as_bad (_("missing or invalid displacement expression `%s'"),
8352 else if (flag_code
== CODE_64BIT
8353 && !i
.prefix
[ADDR_PREFIX
]
8354 && exp
->X_op
== O_constant
)
8356 /* Since displacement is signed extended to 64bit, don't allow
8357 disp32 and turn off disp32s if they are out of range. */
8358 i
.types
[this_operand
].bitfield
.disp32
= 0;
8359 if (!fits_in_signed_long (exp
->X_add_number
))
8361 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8362 if (i
.types
[this_operand
].bitfield
.baseindex
)
8364 as_bad (_("0x%lx out range of signed 32bit displacement"),
8365 (long) exp
->X_add_number
);
8371 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8372 else if (exp
->X_op
!= O_constant
8373 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8374 && exp_seg
!= absolute_section
8375 && exp_seg
!= text_section
8376 && exp_seg
!= data_section
8377 && exp_seg
!= bss_section
8378 && exp_seg
!= undefined_section
8379 && !bfd_is_com_section (exp_seg
))
8381 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8386 /* Check if this is a displacement only operand. */
8387 bigdisp
= i
.types
[this_operand
];
8388 bigdisp
.bitfield
.disp8
= 0;
8389 bigdisp
.bitfield
.disp16
= 0;
8390 bigdisp
.bitfield
.disp32
= 0;
8391 bigdisp
.bitfield
.disp32s
= 0;
8392 bigdisp
.bitfield
.disp64
= 0;
8393 if (operand_type_all_zero (&bigdisp
))
8394 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8400 /* Make sure the memory operand we've been dealt is valid.
8401 Return 1 on success, 0 on a failure. */
8404 i386_index_check (const char *operand_string
)
8406 const char *kind
= "base/index";
8407 enum flag_code addr_mode
;
8409 if (i
.prefix
[ADDR_PREFIX
])
8410 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8413 addr_mode
= flag_code
;
8415 #if INFER_ADDR_PREFIX
8416 if (i
.mem_operands
== 0)
8418 /* Infer address prefix from the first memory operand. */
8419 const reg_entry
*addr_reg
= i
.base_reg
;
8421 if (addr_reg
== NULL
)
8422 addr_reg
= i
.index_reg
;
8426 if (addr_reg
->reg_num
== RegEip
8427 || addr_reg
->reg_num
== RegEiz
8428 || addr_reg
->reg_type
.bitfield
.reg32
)
8429 addr_mode
= CODE_32BIT
;
8430 else if (flag_code
!= CODE_64BIT
8431 && addr_reg
->reg_type
.bitfield
.reg16
)
8432 addr_mode
= CODE_16BIT
;
8434 if (addr_mode
!= flag_code
)
8436 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8438 /* Change the size of any displacement too. At most one
8439 of Disp16 or Disp32 is set.
8440 FIXME. There doesn't seem to be any real need for
8441 separate Disp16 and Disp32 flags. The same goes for
8442 Imm16 and Imm32. Removing them would probably clean
8443 up the code quite a lot. */
8444 if (flag_code
!= CODE_64BIT
8445 && (i
.types
[this_operand
].bitfield
.disp16
8446 || i
.types
[this_operand
].bitfield
.disp32
))
8447 i
.types
[this_operand
]
8448 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8455 if (current_templates
->start
->opcode_modifier
.isstring
8456 && !current_templates
->start
->opcode_modifier
.immext
8457 && (current_templates
->end
[-1].opcode_modifier
.isstring
8460 /* Memory operands of string insns are special in that they only allow
8461 a single register (rDI, rSI, or rBX) as their memory address. */
8462 const reg_entry
*expected_reg
;
8463 static const char *di_si
[][2] =
8469 static const char *bx
[] = { "ebx", "bx", "rbx" };
8471 kind
= "string address";
8473 if (current_templates
->start
->opcode_modifier
.w
)
8475 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8477 if (!type
.bitfield
.baseindex
8478 || ((!i
.mem_operands
!= !intel_syntax
)
8479 && current_templates
->end
[-1].operand_types
[1]
8480 .bitfield
.baseindex
))
8481 type
= current_templates
->end
[-1].operand_types
[1];
8482 expected_reg
= hash_find (reg_hash
,
8483 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8487 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8489 if (i
.base_reg
!= expected_reg
8491 || operand_type_check (i
.types
[this_operand
], disp
))
8493 /* The second memory operand must have the same size as
8497 && !((addr_mode
== CODE_64BIT
8498 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8499 || (addr_mode
== CODE_32BIT
8500 ? i
.base_reg
->reg_type
.bitfield
.reg32
8501 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8504 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8506 intel_syntax
? '[' : '(',
8508 expected_reg
->reg_name
,
8509 intel_syntax
? ']' : ')');
8516 as_bad (_("`%s' is not a valid %s expression"),
8517 operand_string
, kind
);
8522 if (addr_mode
!= CODE_16BIT
)
8524 /* 32-bit/64-bit checks. */
8526 && (addr_mode
== CODE_64BIT
8527 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8528 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8530 || (i
.base_reg
->reg_num
8531 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8533 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8534 && !i
.index_reg
->reg_type
.bitfield
.regymm
8535 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8536 && ((addr_mode
== CODE_64BIT
8537 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8538 || i
.index_reg
->reg_num
== RegRiz
)
8539 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8540 || i
.index_reg
->reg_num
== RegEiz
))
8541 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8546 /* 16-bit checks. */
8548 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8549 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8551 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8552 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8554 && i
.base_reg
->reg_num
< 6
8555 && i
.index_reg
->reg_num
>= 6
8556 && i
.log2_scale_factor
== 0))))
8563 /* Handle vector immediates. */
8566 RC_SAE_immediate (const char *imm_start
)
8568 unsigned int match_found
, j
;
8569 const char *pstr
= imm_start
;
8577 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8579 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8583 rc_op
.type
= RC_NamesTable
[j
].type
;
8584 rc_op
.operand
= this_operand
;
8585 i
.rounding
= &rc_op
;
8589 as_bad (_("duplicated `%s'"), imm_start
);
8592 pstr
+= RC_NamesTable
[j
].len
;
8602 as_bad (_("Missing '}': '%s'"), imm_start
);
8605 /* RC/SAE immediate string should contain nothing more. */;
8608 as_bad (_("Junk after '}': '%s'"), imm_start
);
8612 exp
= &im_expressions
[i
.imm_operands
++];
8613 i
.op
[this_operand
].imms
= exp
;
8615 exp
->X_op
= O_constant
;
8616 exp
->X_add_number
= 0;
8617 exp
->X_add_symbol
= (symbolS
*) 0;
8618 exp
->X_op_symbol
= (symbolS
*) 0;
8620 i
.types
[this_operand
].bitfield
.imm8
= 1;
8624 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8628 i386_att_operand (char *operand_string
)
8632 char *op_string
= operand_string
;
8634 if (is_space_char (*op_string
))
8637 /* We check for an absolute prefix (differentiating,
8638 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8639 if (*op_string
== ABSOLUTE_PREFIX
)
8642 if (is_space_char (*op_string
))
8644 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8647 /* Check if operand is a register. */
8648 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8650 i386_operand_type temp
;
8652 /* Check for a segment override by searching for ':' after a
8653 segment register. */
8655 if (is_space_char (*op_string
))
8657 if (*op_string
== ':'
8658 && (r
->reg_type
.bitfield
.sreg2
8659 || r
->reg_type
.bitfield
.sreg3
))
8664 i
.seg
[i
.mem_operands
] = &es
;
8667 i
.seg
[i
.mem_operands
] = &cs
;
8670 i
.seg
[i
.mem_operands
] = &ss
;
8673 i
.seg
[i
.mem_operands
] = &ds
;
8676 i
.seg
[i
.mem_operands
] = &fs
;
8679 i
.seg
[i
.mem_operands
] = &gs
;
8683 /* Skip the ':' and whitespace. */
8685 if (is_space_char (*op_string
))
8688 if (!is_digit_char (*op_string
)
8689 && !is_identifier_char (*op_string
)
8690 && *op_string
!= '('
8691 && *op_string
!= ABSOLUTE_PREFIX
)
8693 as_bad (_("bad memory operand `%s'"), op_string
);
8696 /* Handle case of %es:*foo. */
8697 if (*op_string
== ABSOLUTE_PREFIX
)
8700 if (is_space_char (*op_string
))
8702 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8704 goto do_memory_reference
;
8707 /* Handle vector operations. */
8708 if (*op_string
== '{')
8710 op_string
= check_VecOperations (op_string
, NULL
);
8711 if (op_string
== NULL
)
8717 as_bad (_("junk `%s' after register"), op_string
);
8721 temp
.bitfield
.baseindex
= 0;
8722 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8724 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8725 i
.op
[this_operand
].regs
= r
;
8728 else if (*op_string
== REGISTER_PREFIX
)
8730 as_bad (_("bad register name `%s'"), op_string
);
8733 else if (*op_string
== IMMEDIATE_PREFIX
)
8736 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8738 as_bad (_("immediate operand illegal with absolute jump"));
8741 if (!i386_immediate (op_string
))
8744 else if (RC_SAE_immediate (operand_string
))
8746 /* If it is a RC or SAE immediate, do nothing. */
8749 else if (is_digit_char (*op_string
)
8750 || is_identifier_char (*op_string
)
8751 || *op_string
== '"'
8752 || *op_string
== '(')
8754 /* This is a memory reference of some sort. */
8757 /* Start and end of displacement string expression (if found). */
8758 char *displacement_string_start
;
8759 char *displacement_string_end
;
8762 do_memory_reference
:
8763 if ((i
.mem_operands
== 1
8764 && !current_templates
->start
->opcode_modifier
.isstring
)
8765 || i
.mem_operands
== 2)
8767 as_bad (_("too many memory references for `%s'"),
8768 current_templates
->start
->name
);
8772 /* Check for base index form. We detect the base index form by
8773 looking for an ')' at the end of the operand, searching
8774 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8776 base_string
= op_string
+ strlen (op_string
);
8778 /* Handle vector operations. */
8779 vop_start
= strchr (op_string
, '{');
8780 if (vop_start
&& vop_start
< base_string
)
8782 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8784 base_string
= vop_start
;
8788 if (is_space_char (*base_string
))
8791 /* If we only have a displacement, set-up for it to be parsed later. */
8792 displacement_string_start
= op_string
;
8793 displacement_string_end
= base_string
+ 1;
8795 if (*base_string
== ')')
8798 unsigned int parens_balanced
= 1;
8799 /* We've already checked that the number of left & right ()'s are
8800 equal, so this loop will not be infinite. */
8804 if (*base_string
== ')')
8806 if (*base_string
== '(')
8809 while (parens_balanced
);
8811 temp_string
= base_string
;
8813 /* Skip past '(' and whitespace. */
8815 if (is_space_char (*base_string
))
8818 if (*base_string
== ','
8819 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8822 displacement_string_end
= temp_string
;
8824 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8828 base_string
= end_op
;
8829 if (is_space_char (*base_string
))
8833 /* There may be an index reg or scale factor here. */
8834 if (*base_string
== ',')
8837 if (is_space_char (*base_string
))
8840 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8843 base_string
= end_op
;
8844 if (is_space_char (*base_string
))
8846 if (*base_string
== ',')
8849 if (is_space_char (*base_string
))
8852 else if (*base_string
!= ')')
8854 as_bad (_("expecting `,' or `)' "
8855 "after index register in `%s'"),
8860 else if (*base_string
== REGISTER_PREFIX
)
8862 end_op
= strchr (base_string
, ',');
8865 as_bad (_("bad register name `%s'"), base_string
);
8869 /* Check for scale factor. */
8870 if (*base_string
!= ')')
8872 char *end_scale
= i386_scale (base_string
);
8877 base_string
= end_scale
;
8878 if (is_space_char (*base_string
))
8880 if (*base_string
!= ')')
8882 as_bad (_("expecting `)' "
8883 "after scale factor in `%s'"),
8888 else if (!i
.index_reg
)
8890 as_bad (_("expecting index register or scale factor "
8891 "after `,'; got '%c'"),
8896 else if (*base_string
!= ')')
8898 as_bad (_("expecting `,' or `)' "
8899 "after base register in `%s'"),
8904 else if (*base_string
== REGISTER_PREFIX
)
8906 end_op
= strchr (base_string
, ',');
8909 as_bad (_("bad register name `%s'"), base_string
);
8914 /* If there's an expression beginning the operand, parse it,
8915 assuming displacement_string_start and
8916 displacement_string_end are meaningful. */
8917 if (displacement_string_start
!= displacement_string_end
)
8919 if (!i386_displacement (displacement_string_start
,
8920 displacement_string_end
))
8924 /* Special case for (%dx) while doing input/output op. */
8926 && operand_type_equal (&i
.base_reg
->reg_type
,
8927 ®16_inoutportreg
)
8929 && i
.log2_scale_factor
== 0
8930 && i
.seg
[i
.mem_operands
] == 0
8931 && !operand_type_check (i
.types
[this_operand
], disp
))
8933 i
.types
[this_operand
] = inoutportreg
;
8937 if (i386_index_check (operand_string
) == 0)
8939 i
.types
[this_operand
].bitfield
.mem
= 1;
8944 /* It's not a memory operand; argh! */
8945 as_bad (_("invalid char %s beginning operand %d `%s'"),
8946 output_invalid (*op_string
),
8951 return 1; /* Normal return. */
8954 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8955 that an rs_machine_dependent frag may reach. */
8958 i386_frag_max_var (fragS
*frag
)
8960 /* The only relaxable frags are for jumps.
8961 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8962 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8963 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8966 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8968 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
8970 /* STT_GNU_IFUNC symbol must go through PLT. */
8971 if ((symbol_get_bfdsym (fr_symbol
)->flags
8972 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8975 if (!S_IS_EXTERNAL (fr_symbol
))
8976 /* Symbol may be weak or local. */
8977 return !S_IS_WEAK (fr_symbol
);
8979 /* Global symbols with non-default visibility can't be preempted. */
8980 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
8983 if (fr_var
!= NO_RELOC
)
8984 switch ((enum bfd_reloc_code_real
) fr_var
)
8986 case BFD_RELOC_386_PLT32
:
8987 case BFD_RELOC_X86_64_PLT32
:
8988 /* Symbol with PLT relocatin may be preempted. */
8994 /* Global symbols with default visibility in a shared library may be
8995 preempted by another definition. */
9000 /* md_estimate_size_before_relax()
9002 Called just before relax() for rs_machine_dependent frags. The x86
9003 assembler uses these frags to handle variable size jump
9006 Any symbol that is now undefined will not become defined.
9007 Return the correct fr_subtype in the frag.
9008 Return the initial "guess for variable size of frag" to caller.
9009 The guess is actually the growth beyond the fixed part. Whatever
9010 we do to grow the fixed or variable part contributes to our
9014 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9016 /* We've already got fragP->fr_subtype right; all we have to do is
9017 check for un-relaxable symbols. On an ELF system, we can't relax
9018 an externally visible symbol, because it may be overridden by a
9020 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9021 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9023 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9026 #if defined (OBJ_COFF) && defined (TE_PE)
9027 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9028 && S_IS_WEAK (fragP
->fr_symbol
))
9032 /* Symbol is undefined in this segment, or we need to keep a
9033 reloc so that weak symbols can be overridden. */
9034 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9035 enum bfd_reloc_code_real reloc_type
;
9036 unsigned char *opcode
;
9039 if (fragP
->fr_var
!= NO_RELOC
)
9040 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9042 reloc_type
= BFD_RELOC_16_PCREL
;
9044 reloc_type
= BFD_RELOC_32_PCREL
;
9046 old_fr_fix
= fragP
->fr_fix
;
9047 opcode
= (unsigned char *) fragP
->fr_opcode
;
9049 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9052 /* Make jmp (0xeb) a (d)word displacement jump. */
9054 fragP
->fr_fix
+= size
;
9055 fix_new (fragP
, old_fr_fix
, size
,
9057 fragP
->fr_offset
, 1,
9063 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9065 /* Negate the condition, and branch past an
9066 unconditional jump. */
9069 /* Insert an unconditional jump. */
9071 /* We added two extra opcode bytes, and have a two byte
9073 fragP
->fr_fix
+= 2 + 2;
9074 fix_new (fragP
, old_fr_fix
+ 2, 2,
9076 fragP
->fr_offset
, 1,
9083 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9088 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9090 fragP
->fr_offset
, 1,
9092 fixP
->fx_signed
= 1;
9096 /* This changes the byte-displacement jump 0x7N
9097 to the (d)word-displacement jump 0x0f,0x8N. */
9098 opcode
[1] = opcode
[0] + 0x10;
9099 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9100 /* We've added an opcode byte. */
9101 fragP
->fr_fix
+= 1 + size
;
9102 fix_new (fragP
, old_fr_fix
+ 1, size
,
9104 fragP
->fr_offset
, 1,
9109 BAD_CASE (fragP
->fr_subtype
);
9113 return fragP
->fr_fix
- old_fr_fix
;
9116 /* Guess size depending on current relax state. Initially the relax
9117 state will correspond to a short jump and we return 1, because
9118 the variable part of the frag (the branch offset) is one byte
9119 long. However, we can relax a section more than once and in that
9120 case we must either set fr_subtype back to the unrelaxed state,
9121 or return the value for the appropriate branch. */
9122 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9125 /* Called after relax() is finished.
9127 In: Address of frag.
9128 fr_type == rs_machine_dependent.
9129 fr_subtype is what the address relaxed to.
9131 Out: Any fixSs and constants are set up.
9132 Caller will turn frag into a ".space 0". */
9135 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9138 unsigned char *opcode
;
9139 unsigned char *where_to_put_displacement
= NULL
;
9140 offsetT target_address
;
9141 offsetT opcode_address
;
9142 unsigned int extension
= 0;
9143 offsetT displacement_from_opcode_start
;
9145 opcode
= (unsigned char *) fragP
->fr_opcode
;
9147 /* Address we want to reach in file space. */
9148 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9150 /* Address opcode resides at in file space. */
9151 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9153 /* Displacement from opcode start to fill into instruction. */
9154 displacement_from_opcode_start
= target_address
- opcode_address
;
9156 if ((fragP
->fr_subtype
& BIG
) == 0)
9158 /* Don't have to change opcode. */
9159 extension
= 1; /* 1 opcode + 1 displacement */
9160 where_to_put_displacement
= &opcode
[1];
9164 if (no_cond_jump_promotion
9165 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9166 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9167 _("long jump required"));
9169 switch (fragP
->fr_subtype
)
9171 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9172 extension
= 4; /* 1 opcode + 4 displacement */
9174 where_to_put_displacement
= &opcode
[1];
9177 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9178 extension
= 2; /* 1 opcode + 2 displacement */
9180 where_to_put_displacement
= &opcode
[1];
9183 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9184 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9185 extension
= 5; /* 2 opcode + 4 displacement */
9186 opcode
[1] = opcode
[0] + 0x10;
9187 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9188 where_to_put_displacement
= &opcode
[2];
9191 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9192 extension
= 3; /* 2 opcode + 2 displacement */
9193 opcode
[1] = opcode
[0] + 0x10;
9194 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9195 where_to_put_displacement
= &opcode
[2];
9198 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9203 where_to_put_displacement
= &opcode
[3];
9207 BAD_CASE (fragP
->fr_subtype
);
9212 /* If size if less then four we are sure that the operand fits,
9213 but if it's 4, then it could be that the displacement is larger
9215 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9217 && ((addressT
) (displacement_from_opcode_start
- extension
9218 + ((addressT
) 1 << 31))
9219 > (((addressT
) 2 << 31) - 1)))
9221 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9222 _("jump target out of range"));
9223 /* Make us emit 0. */
9224 displacement_from_opcode_start
= extension
;
9226 /* Now put displacement after opcode. */
9227 md_number_to_chars ((char *) where_to_put_displacement
,
9228 (valueT
) (displacement_from_opcode_start
- extension
),
9229 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9230 fragP
->fr_fix
+= extension
;
9233 /* Apply a fixup (fixP) to segment data, once it has been determined
9234 by our caller that we have all the info we need to fix it up.
9236 Parameter valP is the pointer to the value of the bits.
9238 On the 386, immediates, displacements, and data pointers are all in
9239 the same (little-endian) format, so we don't need to care about which
9243 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9245 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9246 valueT value
= *valP
;
9248 #if !defined (TE_Mach)
9251 switch (fixP
->fx_r_type
)
9257 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9260 case BFD_RELOC_X86_64_32S
:
9261 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9264 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9267 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9272 if (fixP
->fx_addsy
!= NULL
9273 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9274 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9275 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9276 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9277 && !use_rela_relocations
)
9279 /* This is a hack. There should be a better way to handle this.
9280 This covers for the fact that bfd_install_relocation will
9281 subtract the current location (for partial_inplace, PC relative
9282 relocations); see more below. */
9286 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9289 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9291 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9294 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9297 || (symbol_section_p (fixP
->fx_addsy
)
9298 && sym_seg
!= absolute_section
))
9299 && !generic_force_reloc (fixP
))
9301 /* Yes, we add the values in twice. This is because
9302 bfd_install_relocation subtracts them out again. I think
9303 bfd_install_relocation is broken, but I don't dare change
9305 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9309 #if defined (OBJ_COFF) && defined (TE_PE)
9310 /* For some reason, the PE format does not store a
9311 section address offset for a PC relative symbol. */
9312 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9313 || S_IS_WEAK (fixP
->fx_addsy
))
9314 value
+= md_pcrel_from (fixP
);
9317 #if defined (OBJ_COFF) && defined (TE_PE)
9318 if (fixP
->fx_addsy
!= NULL
9319 && S_IS_WEAK (fixP
->fx_addsy
)
9320 /* PR 16858: Do not modify weak function references. */
9321 && ! fixP
->fx_pcrel
)
9323 #if !defined (TE_PEP)
9324 /* For x86 PE weak function symbols are neither PC-relative
9325 nor do they set S_IS_FUNCTION. So the only reliable way
9326 to detect them is to check the flags of their containing
9328 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9329 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9333 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9337 /* Fix a few things - the dynamic linker expects certain values here,
9338 and we must not disappoint it. */
9339 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9340 if (IS_ELF
&& fixP
->fx_addsy
)
9341 switch (fixP
->fx_r_type
)
9343 case BFD_RELOC_386_PLT32
:
9344 case BFD_RELOC_X86_64_PLT32
:
9345 /* Make the jump instruction point to the address of the operand. At
9346 runtime we merely add the offset to the actual PLT entry. */
9350 case BFD_RELOC_386_TLS_GD
:
9351 case BFD_RELOC_386_TLS_LDM
:
9352 case BFD_RELOC_386_TLS_IE_32
:
9353 case BFD_RELOC_386_TLS_IE
:
9354 case BFD_RELOC_386_TLS_GOTIE
:
9355 case BFD_RELOC_386_TLS_GOTDESC
:
9356 case BFD_RELOC_X86_64_TLSGD
:
9357 case BFD_RELOC_X86_64_TLSLD
:
9358 case BFD_RELOC_X86_64_GOTTPOFF
:
9359 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9360 value
= 0; /* Fully resolved at runtime. No addend. */
9362 case BFD_RELOC_386_TLS_LE
:
9363 case BFD_RELOC_386_TLS_LDO_32
:
9364 case BFD_RELOC_386_TLS_LE_32
:
9365 case BFD_RELOC_X86_64_DTPOFF32
:
9366 case BFD_RELOC_X86_64_DTPOFF64
:
9367 case BFD_RELOC_X86_64_TPOFF32
:
9368 case BFD_RELOC_X86_64_TPOFF64
:
9369 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9372 case BFD_RELOC_386_TLS_DESC_CALL
:
9373 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9374 value
= 0; /* Fully resolved at runtime. No addend. */
9375 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9379 case BFD_RELOC_VTABLE_INHERIT
:
9380 case BFD_RELOC_VTABLE_ENTRY
:
9387 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9389 #endif /* !defined (TE_Mach) */
9391 /* Are we finished with this relocation now? */
9392 if (fixP
->fx_addsy
== NULL
)
9394 #if defined (OBJ_COFF) && defined (TE_PE)
9395 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9398 /* Remember value for tc_gen_reloc. */
9399 fixP
->fx_addnumber
= value
;
9400 /* Clear out the frag for now. */
9404 else if (use_rela_relocations
)
9406 fixP
->fx_no_overflow
= 1;
9407 /* Remember value for tc_gen_reloc. */
9408 fixP
->fx_addnumber
= value
;
9412 md_number_to_chars (p
, value
, fixP
->fx_size
);
9416 md_atof (int type
, char *litP
, int *sizeP
)
9418 /* This outputs the LITTLENUMs in REVERSE order;
9419 in accord with the bigendian 386. */
9420 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9423 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9426 output_invalid (int c
)
9429 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9432 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9433 "(0x%x)", (unsigned char) c
);
9434 return output_invalid_buf
;
9437 /* REG_STRING starts *before* REGISTER_PREFIX. */
9439 static const reg_entry
*
9440 parse_real_register (char *reg_string
, char **end_op
)
9442 char *s
= reg_string
;
9444 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9447 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9448 if (*s
== REGISTER_PREFIX
)
9451 if (is_space_char (*s
))
9455 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9457 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9458 return (const reg_entry
*) NULL
;
9462 /* For naked regs, make sure that we are not dealing with an identifier.
9463 This prevents confusing an identifier like `eax_var' with register
9465 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9466 return (const reg_entry
*) NULL
;
9470 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9472 /* Handle floating point regs, allowing spaces in the (i) part. */
9473 if (r
== i386_regtab
/* %st is first entry of table */)
9475 if (is_space_char (*s
))
9480 if (is_space_char (*s
))
9482 if (*s
>= '0' && *s
<= '7')
9486 if (is_space_char (*s
))
9491 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9496 /* We have "%st(" then garbage. */
9497 return (const reg_entry
*) NULL
;
9501 if (r
== NULL
|| allow_pseudo_reg
)
9504 if (operand_type_all_zero (&r
->reg_type
))
9505 return (const reg_entry
*) NULL
;
9507 if ((r
->reg_type
.bitfield
.reg32
9508 || r
->reg_type
.bitfield
.sreg3
9509 || r
->reg_type
.bitfield
.control
9510 || r
->reg_type
.bitfield
.debug
9511 || r
->reg_type
.bitfield
.test
)
9512 && !cpu_arch_flags
.bitfield
.cpui386
)
9513 return (const reg_entry
*) NULL
;
9515 if (r
->reg_type
.bitfield
.floatreg
9516 && !cpu_arch_flags
.bitfield
.cpu8087
9517 && !cpu_arch_flags
.bitfield
.cpu287
9518 && !cpu_arch_flags
.bitfield
.cpu387
)
9519 return (const reg_entry
*) NULL
;
9521 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9522 return (const reg_entry
*) NULL
;
9524 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9525 return (const reg_entry
*) NULL
;
9527 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9528 return (const reg_entry
*) NULL
;
9530 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9531 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9532 return (const reg_entry
*) NULL
;
9534 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9535 if (!allow_index_reg
9536 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9537 return (const reg_entry
*) NULL
;
9539 /* Upper 16 vector register is only available with VREX in 64bit
9541 if ((r
->reg_flags
& RegVRex
))
9543 if (!cpu_arch_flags
.bitfield
.cpuvrex
9544 || flag_code
!= CODE_64BIT
)
9545 return (const reg_entry
*) NULL
;
9550 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9551 || r
->reg_type
.bitfield
.reg64
)
9552 && (!cpu_arch_flags
.bitfield
.cpulm
9553 || !operand_type_equal (&r
->reg_type
, &control
))
9554 && flag_code
!= CODE_64BIT
)
9555 return (const reg_entry
*) NULL
;
9557 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9558 return (const reg_entry
*) NULL
;
9563 /* REG_STRING starts *before* REGISTER_PREFIX. */
9565 static const reg_entry
*
9566 parse_register (char *reg_string
, char **end_op
)
9570 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9571 r
= parse_real_register (reg_string
, end_op
);
9576 char *save
= input_line_pointer
;
9580 input_line_pointer
= reg_string
;
9581 c
= get_symbol_name (®_string
);
9582 symbolP
= symbol_find (reg_string
);
9583 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9585 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9587 know (e
->X_op
== O_register
);
9588 know (e
->X_add_number
>= 0
9589 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9590 r
= i386_regtab
+ e
->X_add_number
;
9591 if ((r
->reg_flags
& RegVRex
))
9593 *end_op
= input_line_pointer
;
9595 *input_line_pointer
= c
;
9596 input_line_pointer
= save
;
9602 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9605 char *end
= input_line_pointer
;
9608 r
= parse_register (name
, &input_line_pointer
);
9609 if (r
&& end
<= input_line_pointer
)
9611 *nextcharP
= *input_line_pointer
;
9612 *input_line_pointer
= 0;
9613 e
->X_op
= O_register
;
9614 e
->X_add_number
= r
- i386_regtab
;
9617 input_line_pointer
= end
;
9619 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9623 md_operand (expressionS
*e
)
9628 switch (*input_line_pointer
)
9630 case REGISTER_PREFIX
:
9631 r
= parse_real_register (input_line_pointer
, &end
);
9634 e
->X_op
= O_register
;
9635 e
->X_add_number
= r
- i386_regtab
;
9636 input_line_pointer
= end
;
9641 gas_assert (intel_syntax
);
9642 end
= input_line_pointer
++;
9644 if (*input_line_pointer
== ']')
9646 ++input_line_pointer
;
9647 e
->X_op_symbol
= make_expr_symbol (e
);
9648 e
->X_add_symbol
= NULL
;
9649 e
->X_add_number
= 0;
9655 input_line_pointer
= end
;
9662 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9663 const char *md_shortopts
= "kVQ:sqn";
9665 const char *md_shortopts
= "qn";
9668 #define OPTION_32 (OPTION_MD_BASE + 0)
9669 #define OPTION_64 (OPTION_MD_BASE + 1)
9670 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9671 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9672 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9673 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9674 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9675 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9676 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9677 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9678 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9679 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9680 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9681 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9682 #define OPTION_X32 (OPTION_MD_BASE + 14)
9683 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9684 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9685 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9686 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9687 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9688 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9689 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9690 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9691 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9692 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9693 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9695 struct option md_longopts
[] =
9697 {"32", no_argument
, NULL
, OPTION_32
},
9698 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9699 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9700 {"64", no_argument
, NULL
, OPTION_64
},
9702 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9703 {"x32", no_argument
, NULL
, OPTION_X32
},
9704 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9706 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9707 {"march", required_argument
, NULL
, OPTION_MARCH
},
9708 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9709 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9710 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9711 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9712 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9713 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9714 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9715 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9716 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9717 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9718 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9719 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9720 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9721 # if defined (TE_PE) || defined (TE_PEP)
9722 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9724 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9725 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9726 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9727 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9728 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9729 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9730 {NULL
, no_argument
, NULL
, 0}
9732 size_t md_longopts_size
= sizeof (md_longopts
);
9735 md_parse_option (int c
, const char *arg
)
9738 char *arch
, *next
, *saved
;
9743 optimize_align_code
= 0;
9750 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9751 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9752 should be emitted or not. FIXME: Not implemented. */
9756 /* -V: SVR4 argument to print version ID. */
9758 print_version_id ();
9761 /* -k: Ignore for FreeBSD compatibility. */
9766 /* -s: On i386 Solaris, this tells the native assembler to use
9767 .stab instead of .stab.excl. We always use .stab anyhow. */
9770 case OPTION_MSHARED
:
9774 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9775 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9778 const char **list
, **l
;
9780 list
= bfd_target_list ();
9781 for (l
= list
; *l
!= NULL
; l
++)
9782 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9783 || strcmp (*l
, "coff-x86-64") == 0
9784 || strcmp (*l
, "pe-x86-64") == 0
9785 || strcmp (*l
, "pei-x86-64") == 0
9786 || strcmp (*l
, "mach-o-x86-64") == 0)
9788 default_arch
= "x86_64";
9792 as_fatal (_("no compiled in support for x86_64"));
9798 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9802 const char **list
, **l
;
9804 list
= bfd_target_list ();
9805 for (l
= list
; *l
!= NULL
; l
++)
9806 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9808 default_arch
= "x86_64:32";
9812 as_fatal (_("no compiled in support for 32bit x86_64"));
9816 as_fatal (_("32bit x86_64 is only supported for ELF"));
9821 default_arch
= "i386";
9825 #ifdef SVR4_COMMENT_CHARS
9830 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
9832 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9836 i386_comment_chars
= n
;
9842 saved
= xstrdup (arg
);
9844 /* Allow -march=+nosse. */
9850 as_fatal (_("invalid -march= option: `%s'"), arg
);
9851 next
= strchr (arch
, '+');
9854 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9856 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9859 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9862 cpu_arch_name
= cpu_arch
[j
].name
;
9863 cpu_sub_arch_name
= NULL
;
9864 cpu_arch_flags
= cpu_arch
[j
].flags
;
9865 cpu_arch_isa
= cpu_arch
[j
].type
;
9866 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9867 if (!cpu_arch_tune_set
)
9869 cpu_arch_tune
= cpu_arch_isa
;
9870 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9874 else if (*cpu_arch
[j
].name
== '.'
9875 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9877 /* ISA entension. */
9878 i386_cpu_flags flags
;
9880 flags
= cpu_flags_or (cpu_arch_flags
,
9883 if (!valid_iamcu_cpu_flags (&flags
))
9884 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9885 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9887 if (cpu_sub_arch_name
)
9889 char *name
= cpu_sub_arch_name
;
9890 cpu_sub_arch_name
= concat (name
,
9892 (const char *) NULL
);
9896 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9897 cpu_arch_flags
= flags
;
9898 cpu_arch_isa_flags
= flags
;
9904 if (j
>= ARRAY_SIZE (cpu_arch
))
9906 /* Disable an ISA entension. */
9907 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
9908 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
9910 i386_cpu_flags flags
;
9912 flags
= cpu_flags_and_not (cpu_arch_flags
,
9913 cpu_noarch
[j
].flags
);
9914 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9916 if (cpu_sub_arch_name
)
9918 char *name
= cpu_sub_arch_name
;
9919 cpu_sub_arch_name
= concat (arch
,
9920 (const char *) NULL
);
9924 cpu_sub_arch_name
= xstrdup (arch
);
9925 cpu_arch_flags
= flags
;
9926 cpu_arch_isa_flags
= flags
;
9931 if (j
>= ARRAY_SIZE (cpu_noarch
))
9932 j
= ARRAY_SIZE (cpu_arch
);
9935 if (j
>= ARRAY_SIZE (cpu_arch
))
9936 as_fatal (_("invalid -march= option: `%s'"), arg
);
9940 while (next
!= NULL
);
9946 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9947 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9949 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9951 cpu_arch_tune_set
= 1;
9952 cpu_arch_tune
= cpu_arch
[j
].type
;
9953 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9957 if (j
>= ARRAY_SIZE (cpu_arch
))
9958 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9961 case OPTION_MMNEMONIC
:
9962 if (strcasecmp (arg
, "att") == 0)
9964 else if (strcasecmp (arg
, "intel") == 0)
9967 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9970 case OPTION_MSYNTAX
:
9971 if (strcasecmp (arg
, "att") == 0)
9973 else if (strcasecmp (arg
, "intel") == 0)
9976 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9979 case OPTION_MINDEX_REG
:
9980 allow_index_reg
= 1;
9983 case OPTION_MNAKED_REG
:
9984 allow_naked_reg
= 1;
9987 case OPTION_MOLD_GCC
:
9991 case OPTION_MSSE2AVX
:
9995 case OPTION_MSSE_CHECK
:
9996 if (strcasecmp (arg
, "error") == 0)
9997 sse_check
= check_error
;
9998 else if (strcasecmp (arg
, "warning") == 0)
9999 sse_check
= check_warning
;
10000 else if (strcasecmp (arg
, "none") == 0)
10001 sse_check
= check_none
;
10003 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10006 case OPTION_MOPERAND_CHECK
:
10007 if (strcasecmp (arg
, "error") == 0)
10008 operand_check
= check_error
;
10009 else if (strcasecmp (arg
, "warning") == 0)
10010 operand_check
= check_warning
;
10011 else if (strcasecmp (arg
, "none") == 0)
10012 operand_check
= check_none
;
10014 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10017 case OPTION_MAVXSCALAR
:
10018 if (strcasecmp (arg
, "128") == 0)
10019 avxscalar
= vex128
;
10020 else if (strcasecmp (arg
, "256") == 0)
10021 avxscalar
= vex256
;
10023 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10026 case OPTION_MADD_BND_PREFIX
:
10027 add_bnd_prefix
= 1;
10030 case OPTION_MEVEXLIG
:
10031 if (strcmp (arg
, "128") == 0)
10032 evexlig
= evexl128
;
10033 else if (strcmp (arg
, "256") == 0)
10034 evexlig
= evexl256
;
10035 else if (strcmp (arg
, "512") == 0)
10036 evexlig
= evexl512
;
10038 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10041 case OPTION_MEVEXRCIG
:
10042 if (strcmp (arg
, "rne") == 0)
10044 else if (strcmp (arg
, "rd") == 0)
10046 else if (strcmp (arg
, "ru") == 0)
10048 else if (strcmp (arg
, "rz") == 0)
10051 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10054 case OPTION_MEVEXWIG
:
10055 if (strcmp (arg
, "0") == 0)
10057 else if (strcmp (arg
, "1") == 0)
10060 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10063 # if defined (TE_PE) || defined (TE_PEP)
10064 case OPTION_MBIG_OBJ
:
10069 case OPTION_MOMIT_LOCK_PREFIX
:
10070 if (strcasecmp (arg
, "yes") == 0)
10071 omit_lock_prefix
= 1;
10072 else if (strcasecmp (arg
, "no") == 0)
10073 omit_lock_prefix
= 0;
10075 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10078 case OPTION_MFENCE_AS_LOCK_ADD
:
10079 if (strcasecmp (arg
, "yes") == 0)
10081 else if (strcasecmp (arg
, "no") == 0)
10084 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10087 case OPTION_MRELAX_RELOCATIONS
:
10088 if (strcasecmp (arg
, "yes") == 0)
10089 generate_relax_relocations
= 1;
10090 else if (strcasecmp (arg
, "no") == 0)
10091 generate_relax_relocations
= 0;
10093 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10096 case OPTION_MAMD64
:
10097 cpu_arch_flags
.bitfield
.cpuamd64
= 1;
10098 cpu_arch_flags
.bitfield
.cpuintel64
= 0;
10099 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 1;
10100 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 0;
10103 case OPTION_MINTEL64
:
10104 cpu_arch_flags
.bitfield
.cpuamd64
= 0;
10105 cpu_arch_flags
.bitfield
.cpuintel64
= 1;
10106 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 0;
10107 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 1;
10116 #define MESSAGE_TEMPLATE \
10120 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10121 int *left_p
, const char *name
, int len
)
10123 int size
= sizeof (MESSAGE_TEMPLATE
);
10124 int left
= *left_p
;
10126 /* Reserve 2 spaces for ", " or ",\0" */
10129 /* Check if there is any room. */
10137 p
= mempcpy (p
, name
, len
);
10141 /* Output the current message now and start a new one. */
10144 fprintf (stream
, "%s\n", message
);
10146 left
= size
- (start
- message
) - len
- 2;
10148 gas_assert (left
>= 0);
10150 p
= mempcpy (p
, name
, len
);
10158 show_arch (FILE *stream
, int ext
, int check
)
10160 static char message
[] = MESSAGE_TEMPLATE
;
10161 char *start
= message
+ 27;
10163 int size
= sizeof (MESSAGE_TEMPLATE
);
10170 left
= size
- (start
- message
);
10171 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10173 /* Should it be skipped? */
10174 if (cpu_arch
[j
].skip
)
10177 name
= cpu_arch
[j
].name
;
10178 len
= cpu_arch
[j
].len
;
10181 /* It is an extension. Skip if we aren't asked to show it. */
10192 /* It is an processor. Skip if we show only extension. */
10195 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10197 /* It is an impossible processor - skip. */
10201 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10204 /* Display disabled extensions. */
10206 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10208 name
= cpu_noarch
[j
].name
;
10209 len
= cpu_noarch
[j
].len
;
10210 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10215 fprintf (stream
, "%s\n", message
);
10219 md_show_usage (FILE *stream
)
10221 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10222 fprintf (stream
, _("\
10224 -V print assembler version number\n\
10227 fprintf (stream
, _("\
10228 -n Do not optimize code alignment\n\
10229 -q quieten some warnings\n"));
10230 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10231 fprintf (stream
, _("\
10234 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10235 || defined (TE_PE) || defined (TE_PEP))
10236 fprintf (stream
, _("\
10237 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10239 #ifdef SVR4_COMMENT_CHARS
10240 fprintf (stream
, _("\
10241 --divide do not treat `/' as a comment character\n"));
10243 fprintf (stream
, _("\
10244 --divide ignored\n"));
10246 fprintf (stream
, _("\
10247 -march=CPU[,+EXTENSION...]\n\
10248 generate code for CPU and EXTENSION, CPU is one of:\n"));
10249 show_arch (stream
, 0, 1);
10250 fprintf (stream
, _("\
10251 EXTENSION is combination of:\n"));
10252 show_arch (stream
, 1, 0);
10253 fprintf (stream
, _("\
10254 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10255 show_arch (stream
, 0, 0);
10256 fprintf (stream
, _("\
10257 -msse2avx encode SSE instructions with VEX prefix\n"));
10258 fprintf (stream
, _("\
10259 -msse-check=[none|error|warning]\n\
10260 check SSE instructions\n"));
10261 fprintf (stream
, _("\
10262 -moperand-check=[none|error|warning]\n\
10263 check operand combinations for validity\n"));
10264 fprintf (stream
, _("\
10265 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10267 fprintf (stream
, _("\
10268 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10270 fprintf (stream
, _("\
10271 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10272 for EVEX.W bit ignored instructions\n"));
10273 fprintf (stream
, _("\
10274 -mevexrcig=[rne|rd|ru|rz]\n\
10275 encode EVEX instructions with specific EVEX.RC value\n\
10276 for SAE-only ignored instructions\n"));
10277 fprintf (stream
, _("\
10278 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10279 fprintf (stream
, _("\
10280 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10281 fprintf (stream
, _("\
10282 -mindex-reg support pseudo index registers\n"));
10283 fprintf (stream
, _("\
10284 -mnaked-reg don't require `%%' prefix for registers\n"));
10285 fprintf (stream
, _("\
10286 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10287 fprintf (stream
, _("\
10288 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10289 fprintf (stream
, _("\
10290 -mshared disable branch optimization for shared code\n"));
10291 # if defined (TE_PE) || defined (TE_PEP)
10292 fprintf (stream
, _("\
10293 -mbig-obj generate big object files\n"));
10295 fprintf (stream
, _("\
10296 -momit-lock-prefix=[no|yes]\n\
10297 strip all lock prefixes\n"));
10298 fprintf (stream
, _("\
10299 -mfence-as-lock-add=[no|yes]\n\
10300 encode lfence, mfence and sfence as\n\
10301 lock addl $0x0, (%%{re}sp)\n"));
10302 fprintf (stream
, _("\
10303 -mrelax-relocations=[no|yes]\n\
10304 generate relax relocations\n"));
10305 fprintf (stream
, _("\
10306 -mamd64 accept only AMD64 ISA\n"));
10307 fprintf (stream
, _("\
10308 -mintel64 accept only Intel64 ISA\n"));
10311 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10312 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10313 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10315 /* Pick the target format to use. */
10318 i386_target_format (void)
10320 if (!strncmp (default_arch
, "x86_64", 6))
10322 update_code_flag (CODE_64BIT
, 1);
10323 if (default_arch
[6] == '\0')
10324 x86_elf_abi
= X86_64_ABI
;
10326 x86_elf_abi
= X86_64_X32_ABI
;
10328 else if (!strcmp (default_arch
, "i386"))
10329 update_code_flag (CODE_32BIT
, 1);
10330 else if (!strcmp (default_arch
, "iamcu"))
10332 update_code_flag (CODE_32BIT
, 1);
10333 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10335 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10336 cpu_arch_name
= "iamcu";
10337 cpu_sub_arch_name
= NULL
;
10338 cpu_arch_flags
= iamcu_flags
;
10339 cpu_arch_isa
= PROCESSOR_IAMCU
;
10340 cpu_arch_isa_flags
= iamcu_flags
;
10341 if (!cpu_arch_tune_set
)
10343 cpu_arch_tune
= cpu_arch_isa
;
10344 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10348 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10352 as_fatal (_("unknown architecture"));
10354 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10355 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10356 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10357 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10359 switch (OUTPUT_FLAVOR
)
10361 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10362 case bfd_target_aout_flavour
:
10363 return AOUT_TARGET_FORMAT
;
10365 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10366 # if defined (TE_PE) || defined (TE_PEP)
10367 case bfd_target_coff_flavour
:
10368 if (flag_code
== CODE_64BIT
)
10369 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10372 # elif defined (TE_GO32)
10373 case bfd_target_coff_flavour
:
10374 return "coff-go32";
10376 case bfd_target_coff_flavour
:
10377 return "coff-i386";
10380 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10381 case bfd_target_elf_flavour
:
10383 const char *format
;
10385 switch (x86_elf_abi
)
10388 format
= ELF_TARGET_FORMAT
;
10391 use_rela_relocations
= 1;
10393 format
= ELF_TARGET_FORMAT64
;
10395 case X86_64_X32_ABI
:
10396 use_rela_relocations
= 1;
10398 disallow_64bit_reloc
= 1;
10399 format
= ELF_TARGET_FORMAT32
;
10402 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10404 if (x86_elf_abi
!= X86_64_ABI
)
10405 as_fatal (_("Intel L1OM is 64bit only"));
10406 return ELF_TARGET_L1OM_FORMAT
;
10408 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10410 if (x86_elf_abi
!= X86_64_ABI
)
10411 as_fatal (_("Intel K1OM is 64bit only"));
10412 return ELF_TARGET_K1OM_FORMAT
;
10414 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10416 if (x86_elf_abi
!= I386_ABI
)
10417 as_fatal (_("Intel MCU is 32bit only"));
10418 return ELF_TARGET_IAMCU_FORMAT
;
10424 #if defined (OBJ_MACH_O)
10425 case bfd_target_mach_o_flavour
:
10426 if (flag_code
== CODE_64BIT
)
10428 use_rela_relocations
= 1;
10430 return "mach-o-x86-64";
10433 return "mach-o-i386";
10441 #endif /* OBJ_MAYBE_ more than one */
10444 md_undefined_symbol (char *name
)
10446 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10447 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10448 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10449 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10453 if (symbol_find (name
))
10454 as_bad (_("GOT already in symbol table"));
10455 GOT_symbol
= symbol_new (name
, undefined_section
,
10456 (valueT
) 0, &zero_address_frag
);
10463 /* Round up a section size to the appropriate boundary. */
10466 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10468 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10469 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10471 /* For a.out, force the section size to be aligned. If we don't do
10472 this, BFD will align it for us, but it will not write out the
10473 final bytes of the section. This may be a bug in BFD, but it is
10474 easier to fix it here since that is how the other a.out targets
10478 align
= bfd_get_section_alignment (stdoutput
, segment
);
10479 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10486 /* On the i386, PC-relative offsets are relative to the start of the
10487 next instruction. That is, the address of the offset, plus its
10488 size, since the offset is always the last part of the insn. */
10491 md_pcrel_from (fixS
*fixP
)
10493 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10499 s_bss (int ignore ATTRIBUTE_UNUSED
)
10503 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10505 obj_elf_section_change_hook ();
10507 temp
= get_absolute_expression ();
10508 subseg_set (bss_section
, (subsegT
) temp
);
10509 demand_empty_rest_of_line ();
10515 i386_validate_fix (fixS
*fixp
)
10517 if (fixp
->fx_subsy
)
10519 if (fixp
->fx_subsy
== GOT_symbol
)
10521 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10525 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10526 if (fixp
->fx_tcbit2
)
10527 fixp
->fx_r_type
= (fixp
->fx_tcbit
10528 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10529 : BFD_RELOC_X86_64_GOTPCRELX
);
10532 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10537 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10539 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10541 fixp
->fx_subsy
= 0;
10544 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10545 else if (!object_64bit
)
10547 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10548 && fixp
->fx_tcbit2
)
10549 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10555 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10558 bfd_reloc_code_real_type code
;
10560 switch (fixp
->fx_r_type
)
10562 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10563 case BFD_RELOC_SIZE32
:
10564 case BFD_RELOC_SIZE64
:
10565 if (S_IS_DEFINED (fixp
->fx_addsy
)
10566 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10568 /* Resolve size relocation against local symbol to size of
10569 the symbol plus addend. */
10570 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10571 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10572 && !fits_in_unsigned_long (value
))
10573 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10574 _("symbol size computation overflow"));
10575 fixp
->fx_addsy
= NULL
;
10576 fixp
->fx_subsy
= NULL
;
10577 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10582 case BFD_RELOC_X86_64_PLT32
:
10583 case BFD_RELOC_X86_64_GOT32
:
10584 case BFD_RELOC_X86_64_GOTPCREL
:
10585 case BFD_RELOC_X86_64_GOTPCRELX
:
10586 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10587 case BFD_RELOC_386_PLT32
:
10588 case BFD_RELOC_386_GOT32
:
10589 case BFD_RELOC_386_GOT32X
:
10590 case BFD_RELOC_386_GOTOFF
:
10591 case BFD_RELOC_386_GOTPC
:
10592 case BFD_RELOC_386_TLS_GD
:
10593 case BFD_RELOC_386_TLS_LDM
:
10594 case BFD_RELOC_386_TLS_LDO_32
:
10595 case BFD_RELOC_386_TLS_IE_32
:
10596 case BFD_RELOC_386_TLS_IE
:
10597 case BFD_RELOC_386_TLS_GOTIE
:
10598 case BFD_RELOC_386_TLS_LE_32
:
10599 case BFD_RELOC_386_TLS_LE
:
10600 case BFD_RELOC_386_TLS_GOTDESC
:
10601 case BFD_RELOC_386_TLS_DESC_CALL
:
10602 case BFD_RELOC_X86_64_TLSGD
:
10603 case BFD_RELOC_X86_64_TLSLD
:
10604 case BFD_RELOC_X86_64_DTPOFF32
:
10605 case BFD_RELOC_X86_64_DTPOFF64
:
10606 case BFD_RELOC_X86_64_GOTTPOFF
:
10607 case BFD_RELOC_X86_64_TPOFF32
:
10608 case BFD_RELOC_X86_64_TPOFF64
:
10609 case BFD_RELOC_X86_64_GOTOFF64
:
10610 case BFD_RELOC_X86_64_GOTPC32
:
10611 case BFD_RELOC_X86_64_GOT64
:
10612 case BFD_RELOC_X86_64_GOTPCREL64
:
10613 case BFD_RELOC_X86_64_GOTPC64
:
10614 case BFD_RELOC_X86_64_GOTPLT64
:
10615 case BFD_RELOC_X86_64_PLTOFF64
:
10616 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10617 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10618 case BFD_RELOC_RVA
:
10619 case BFD_RELOC_VTABLE_ENTRY
:
10620 case BFD_RELOC_VTABLE_INHERIT
:
10622 case BFD_RELOC_32_SECREL
:
10624 code
= fixp
->fx_r_type
;
10626 case BFD_RELOC_X86_64_32S
:
10627 if (!fixp
->fx_pcrel
)
10629 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10630 code
= fixp
->fx_r_type
;
10634 if (fixp
->fx_pcrel
)
10636 switch (fixp
->fx_size
)
10639 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10640 _("can not do %d byte pc-relative relocation"),
10642 code
= BFD_RELOC_32_PCREL
;
10644 case 1: code
= BFD_RELOC_8_PCREL
; break;
10645 case 2: code
= BFD_RELOC_16_PCREL
; break;
10646 case 4: code
= BFD_RELOC_32_PCREL
; break;
10648 case 8: code
= BFD_RELOC_64_PCREL
; break;
10654 switch (fixp
->fx_size
)
10657 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10658 _("can not do %d byte relocation"),
10660 code
= BFD_RELOC_32
;
10662 case 1: code
= BFD_RELOC_8
; break;
10663 case 2: code
= BFD_RELOC_16
; break;
10664 case 4: code
= BFD_RELOC_32
; break;
10666 case 8: code
= BFD_RELOC_64
; break;
10673 if ((code
== BFD_RELOC_32
10674 || code
== BFD_RELOC_32_PCREL
10675 || code
== BFD_RELOC_X86_64_32S
)
10677 && fixp
->fx_addsy
== GOT_symbol
)
10680 code
= BFD_RELOC_386_GOTPC
;
10682 code
= BFD_RELOC_X86_64_GOTPC32
;
10684 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10686 && fixp
->fx_addsy
== GOT_symbol
)
10688 code
= BFD_RELOC_X86_64_GOTPC64
;
10691 rel
= XNEW (arelent
);
10692 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10693 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10695 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10697 if (!use_rela_relocations
)
10699 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10700 vtable entry to be used in the relocation's section offset. */
10701 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10702 rel
->address
= fixp
->fx_offset
;
10703 #if defined (OBJ_COFF) && defined (TE_PE)
10704 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10705 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10710 /* Use the rela in 64bit mode. */
10713 if (disallow_64bit_reloc
)
10716 case BFD_RELOC_X86_64_DTPOFF64
:
10717 case BFD_RELOC_X86_64_TPOFF64
:
10718 case BFD_RELOC_64_PCREL
:
10719 case BFD_RELOC_X86_64_GOTOFF64
:
10720 case BFD_RELOC_X86_64_GOT64
:
10721 case BFD_RELOC_X86_64_GOTPCREL64
:
10722 case BFD_RELOC_X86_64_GOTPC64
:
10723 case BFD_RELOC_X86_64_GOTPLT64
:
10724 case BFD_RELOC_X86_64_PLTOFF64
:
10725 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10726 _("cannot represent relocation type %s in x32 mode"),
10727 bfd_get_reloc_code_name (code
));
10733 if (!fixp
->fx_pcrel
)
10734 rel
->addend
= fixp
->fx_offset
;
10738 case BFD_RELOC_X86_64_PLT32
:
10739 case BFD_RELOC_X86_64_GOT32
:
10740 case BFD_RELOC_X86_64_GOTPCREL
:
10741 case BFD_RELOC_X86_64_GOTPCRELX
:
10742 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10743 case BFD_RELOC_X86_64_TLSGD
:
10744 case BFD_RELOC_X86_64_TLSLD
:
10745 case BFD_RELOC_X86_64_GOTTPOFF
:
10746 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10747 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10748 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10751 rel
->addend
= (section
->vma
10753 + fixp
->fx_addnumber
10754 + md_pcrel_from (fixp
));
10759 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10760 if (rel
->howto
== NULL
)
10762 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10763 _("cannot represent relocation type %s"),
10764 bfd_get_reloc_code_name (code
));
10765 /* Set howto to a garbage value so that we can keep going. */
10766 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10767 gas_assert (rel
->howto
!= NULL
);
10773 #include "tc-i386-intel.c"
10776 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10778 int saved_naked_reg
;
10779 char saved_register_dot
;
10781 saved_naked_reg
= allow_naked_reg
;
10782 allow_naked_reg
= 1;
10783 saved_register_dot
= register_chars
['.'];
10784 register_chars
['.'] = '.';
10785 allow_pseudo_reg
= 1;
10786 expression_and_evaluate (exp
);
10787 allow_pseudo_reg
= 0;
10788 register_chars
['.'] = saved_register_dot
;
10789 allow_naked_reg
= saved_naked_reg
;
10791 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10793 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10795 exp
->X_op
= O_constant
;
10796 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10797 .dw2_regnum
[flag_code
>> 1];
10800 exp
->X_op
= O_illegal
;
10805 tc_x86_frame_initial_instructions (void)
10807 static unsigned int sp_regno
[2];
10809 if (!sp_regno
[flag_code
>> 1])
10811 char *saved_input
= input_line_pointer
;
10812 char sp
[][4] = {"esp", "rsp"};
10815 input_line_pointer
= sp
[flag_code
>> 1];
10816 tc_x86_parse_to_dw2regnum (&exp
);
10817 gas_assert (exp
.X_op
== O_constant
);
10818 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10819 input_line_pointer
= saved_input
;
10822 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10823 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10827 x86_dwarf2_addr_size (void)
10829 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10830 if (x86_elf_abi
== X86_64_X32_ABI
)
10833 return bfd_arch_bits_per_address (stdoutput
) / 8;
10837 i386_elf_section_type (const char *str
, size_t len
)
10839 if (flag_code
== CODE_64BIT
10840 && len
== sizeof ("unwind") - 1
10841 && strncmp (str
, "unwind", 6) == 0)
10842 return SHT_X86_64_UNWIND
;
10849 i386_solaris_fix_up_eh_frame (segT sec
)
10851 if (flag_code
== CODE_64BIT
)
10852 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10858 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10862 exp
.X_op
= O_secrel
;
10863 exp
.X_add_symbol
= symbol
;
10864 exp
.X_add_number
= 0;
10865 emit_expr (&exp
, size
);
10869 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10870 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10873 x86_64_section_letter (int letter
, const char **ptr_msg
)
10875 if (flag_code
== CODE_64BIT
)
10878 return SHF_X86_64_LARGE
;
10880 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10883 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10888 x86_64_section_word (char *str
, size_t len
)
10890 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10891 return SHF_X86_64_LARGE
;
10897 handle_large_common (int small ATTRIBUTE_UNUSED
)
10899 if (flag_code
!= CODE_64BIT
)
10901 s_comm_internal (0, elf_common_parse
);
10902 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10906 static segT lbss_section
;
10907 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10908 asection
*saved_bss_section
= bss_section
;
10910 if (lbss_section
== NULL
)
10912 flagword applicable
;
10913 segT seg
= now_seg
;
10914 subsegT subseg
= now_subseg
;
10916 /* The .lbss section is for local .largecomm symbols. */
10917 lbss_section
= subseg_new (".lbss", 0);
10918 applicable
= bfd_applicable_section_flags (stdoutput
);
10919 bfd_set_section_flags (stdoutput
, lbss_section
,
10920 applicable
& SEC_ALLOC
);
10921 seg_info (lbss_section
)->bss
= 1;
10923 subseg_set (seg
, subseg
);
10926 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10927 bss_section
= lbss_section
;
10929 s_comm_internal (0, elf_common_parse
);
10931 elf_com_section_ptr
= saved_com_section_ptr
;
10932 bss_section
= saved_bss_section
;
10935 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */