1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
522 /* 1 if generating code for a shared library. */
523 static int shared
= 0;
526 /* 1 for intel syntax,
528 static int intel_syntax
= 0;
530 /* 1 for intel mnemonic,
531 0 if att mnemonic. */
532 static int intel_mnemonic
= !SYSV386_COMPAT
;
534 /* 1 if support old (<= 2.8.1) versions of gcc. */
535 static int old_gcc
= OLDGCC_COMPAT
;
537 /* 1 if pseudo registers are permitted. */
538 static int allow_pseudo_reg
= 0;
540 /* 1 if register prefix % not required. */
541 static int allow_naked_reg
= 0;
543 /* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
546 static int add_bnd_prefix
= 0;
548 /* 1 if pseudo index register, eiz/riz, is allowed . */
549 static int allow_index_reg
= 0;
551 /* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553 static int omit_lock_prefix
= 0;
555 static enum check_kind
561 sse_check
, operand_check
= check_warning
;
563 /* Register prefix used for error message. */
564 static const char *register_prefix
= "%";
566 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
567 leave, push, and pop instructions so that gcc has the same stack
568 frame as in 32 bit mode. */
569 static char stackop_size
= '\0';
571 /* Non-zero to optimize code alignment. */
572 int optimize_align_code
= 1;
574 /* Non-zero to quieten some warnings. */
575 static int quiet_warnings
= 0;
578 static const char *cpu_arch_name
= NULL
;
579 static char *cpu_sub_arch_name
= NULL
;
581 /* CPU feature flags. */
582 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
584 /* If we have selected a cpu we are generating instructions for. */
585 static int cpu_arch_tune_set
= 0;
587 /* Cpu we are generating instructions for. */
588 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
590 /* CPU feature flags of cpu we are generating instructions for. */
591 static i386_cpu_flags cpu_arch_tune_flags
;
593 /* CPU instruction set architecture used. */
594 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
596 /* CPU feature flags of instruction set architecture used. */
597 i386_cpu_flags cpu_arch_isa_flags
;
599 /* If set, conditional jumps are not automatically promoted to handle
600 larger than a byte offset. */
601 static unsigned int no_cond_jump_promotion
= 0;
603 /* Encode SSE instructions with VEX prefix. */
604 static unsigned int sse2avx
;
606 /* Encode scalar AVX instructions with specific vector length. */
613 /* Encode scalar EVEX LIG instructions with specific vector length. */
621 /* Encode EVEX WIG instructions with specific evex.w. */
628 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
629 static enum rc_type evexrcig
= rne
;
631 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
632 static symbolS
*GOT_symbol
;
634 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
635 unsigned int x86_dwarf2_return_column
;
637 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
638 int x86_cie_data_alignment
;
640 /* Interface to relax_segment.
641 There are 3 major relax states for 386 jump insns because the
642 different types of jumps add different sizes to frags when we're
643 figuring out what sort of jump to choose to reach a given label. */
646 #define UNCOND_JUMP 0
648 #define COND_JUMP86 2
653 #define SMALL16 (SMALL | CODE16)
655 #define BIG16 (BIG | CODE16)
659 #define INLINE __inline__
665 #define ENCODE_RELAX_STATE(type, size) \
666 ((relax_substateT) (((type) << 2) | (size)))
667 #define TYPE_FROM_RELAX_STATE(s) \
669 #define DISP_SIZE_FROM_RELAX_STATE(s) \
670 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
672 /* This table is used by relax_frag to promote short jumps to long
673 ones where necessary. SMALL (short) jumps may be promoted to BIG
674 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
675 don't allow a short jump in a 32 bit code segment to be promoted to
676 a 16 bit offset jump because it's slower (requires data size
677 prefix), and doesn't work, unless the destination is in the bottom
678 64k of the code segment (The top 16 bits of eip are zeroed). */
680 const relax_typeS md_relax_table
[] =
683 1) most positive reach of this state,
684 2) most negative reach of this state,
685 3) how many bytes this mode will have in the variable part of the frag
686 4) which index into the table to try if we can't fit into this one. */
688 /* UNCOND_JUMP states. */
689 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
691 /* dword jmp adds 4 bytes to frag:
692 0 extra opcode bytes, 4 displacement bytes. */
694 /* word jmp adds 2 byte2 to frag:
695 0 extra opcode bytes, 2 displacement bytes. */
698 /* COND_JUMP states. */
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
701 /* dword conditionals adds 5 bytes to frag:
702 1 extra opcode byte, 4 displacement bytes. */
704 /* word conditionals add 3 bytes to frag:
705 1 extra opcode byte, 2 displacement bytes. */
708 /* COND_JUMP86 states. */
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
711 /* dword conditionals adds 5 bytes to frag:
712 1 extra opcode byte, 4 displacement bytes. */
714 /* word conditionals add 4 bytes to frag:
715 1 displacement byte and a 3 byte long branch insn. */
719 static const arch_entry cpu_arch
[] =
721 /* Do not replace the first two entries - i386_target_format()
722 relies on them being there in this order. */
723 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
724 CPU_GENERIC32_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
726 CPU_GENERIC64_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
728 CPU_NONE_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
730 CPU_I186_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
732 CPU_I286_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
734 CPU_I386_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
736 CPU_I486_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
738 CPU_I586_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
740 CPU_I686_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
742 CPU_I586_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
744 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
746 CPU_P2_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
748 CPU_P3_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
750 CPU_P4_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
752 CPU_CORE_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
754 CPU_NOCONA_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
756 CPU_CORE_FLAGS
, 1, 0 },
757 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
758 CPU_CORE_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
760 CPU_CORE2_FLAGS
, 1, 0 },
761 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
762 CPU_CORE2_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
764 CPU_COREI7_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
766 CPU_L1OM_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
768 CPU_K1OM_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
770 CPU_IAMCU_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
772 CPU_K6_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
774 CPU_K6_2_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
776 CPU_ATHLON_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
778 CPU_K8_FLAGS
, 1, 0 },
779 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
780 CPU_K8_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
782 CPU_K8_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
784 CPU_AMDFAM10_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
786 CPU_BDVER1_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
788 CPU_BDVER2_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
790 CPU_BDVER3_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
792 CPU_BDVER4_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
794 CPU_ZNVER1_FLAGS
, 0, 0 },
795 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
796 CPU_BTVER1_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
798 CPU_BTVER2_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
800 CPU_8087_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
802 CPU_287_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
804 CPU_387_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
806 CPU_ANY87_FLAGS
, 0, 1 },
807 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
808 CPU_MMX_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
810 CPU_3DNOWA_FLAGS
, 0, 1 },
811 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
812 CPU_SSE_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
814 CPU_SSE2_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
816 CPU_SSE3_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
818 CPU_SSSE3_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
820 CPU_SSE4_1_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
822 CPU_SSE4_2_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
824 CPU_SSE4_2_FLAGS
, 0, 0 },
825 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
826 CPU_ANY_SSE_FLAGS
, 0, 1 },
827 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
828 CPU_AVX_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
830 CPU_AVX2_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
832 CPU_AVX512F_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
834 CPU_AVX512CD_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
836 CPU_AVX512ER_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
838 CPU_AVX512PF_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
840 CPU_AVX512DQ_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
842 CPU_AVX512BW_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
844 CPU_AVX512VL_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
846 CPU_ANY_AVX_FLAGS
, 0, 1 },
847 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
848 CPU_VMX_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
850 CPU_VMFUNC_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
852 CPU_SMX_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
854 CPU_XSAVE_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
856 CPU_XSAVEOPT_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
858 CPU_XSAVEC_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
860 CPU_XSAVES_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
862 CPU_AES_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
864 CPU_PCLMUL_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
866 CPU_PCLMUL_FLAGS
, 1, 0 },
867 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
868 CPU_FSGSBASE_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
870 CPU_RDRND_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
872 CPU_F16C_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
874 CPU_BMI2_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
876 CPU_FMA_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
878 CPU_FMA4_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
880 CPU_XOP_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
882 CPU_LWP_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
884 CPU_MOVBE_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
886 CPU_CX16_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
888 CPU_EPT_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
890 CPU_LZCNT_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
892 CPU_HLE_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
894 CPU_RTM_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
896 CPU_INVPCID_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
898 CPU_CLFLUSH_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
900 CPU_NOP_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
902 CPU_SYSCALL_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
904 CPU_RDTSCP_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
906 CPU_3DNOW_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
908 CPU_3DNOWA_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
910 CPU_PADLOCK_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
912 CPU_SVME_FLAGS
, 1, 0 },
913 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
914 CPU_SVME_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
916 CPU_SSE4A_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
918 CPU_ABM_FLAGS
, 0, 0 },
919 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
920 CPU_BMI_FLAGS
, 0, 0 },
921 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
922 CPU_TBM_FLAGS
, 0, 0 },
923 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
924 CPU_ADX_FLAGS
, 0, 0 },
925 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
926 CPU_RDSEED_FLAGS
, 0, 0 },
927 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
928 CPU_PRFCHW_FLAGS
, 0, 0 },
929 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
930 CPU_SMAP_FLAGS
, 0, 0 },
931 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
932 CPU_MPX_FLAGS
, 0, 0 },
933 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
934 CPU_SHA_FLAGS
, 0, 0 },
935 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
936 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
937 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
938 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
939 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
940 CPU_SE1_FLAGS
, 0, 0 },
941 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
942 CPU_CLWB_FLAGS
, 0, 0 },
943 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
944 CPU_PCOMMIT_FLAGS
, 0, 0 },
945 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
946 CPU_AVX512IFMA_FLAGS
, 0, 0 },
947 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
948 CPU_AVX512VBMI_FLAGS
, 0, 0 },
949 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
950 CPU_CLZERO_FLAGS
, 0, 0 },
951 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
952 CPU_MWAITX_FLAGS
, 0, 0 },
953 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
954 CPU_OSPKE_FLAGS
, 0, 0 },
958 /* Like s_lcomm_internal in gas/read.c but the alignment string
959 is allowed to be optional. */
962 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
969 && *input_line_pointer
== ',')
971 align
= parse_align (needs_align
- 1);
973 if (align
== (addressT
) -1)
988 bss_alloc (symbolP
, size
, align
);
993 pe_lcomm (int needs_align
)
995 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
999 const pseudo_typeS md_pseudo_table
[] =
1001 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1002 {"align", s_align_bytes
, 0},
1004 {"align", s_align_ptwo
, 0},
1006 {"arch", set_cpu_arch
, 0},
1010 {"lcomm", pe_lcomm
, 1},
1012 {"ffloat", float_cons
, 'f'},
1013 {"dfloat", float_cons
, 'd'},
1014 {"tfloat", float_cons
, 'x'},
1016 {"slong", signed_cons
, 4},
1017 {"noopt", s_ignore
, 0},
1018 {"optim", s_ignore
, 0},
1019 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1020 {"code16", set_code_flag
, CODE_16BIT
},
1021 {"code32", set_code_flag
, CODE_32BIT
},
1022 {"code64", set_code_flag
, CODE_64BIT
},
1023 {"intel_syntax", set_intel_syntax
, 1},
1024 {"att_syntax", set_intel_syntax
, 0},
1025 {"intel_mnemonic", set_intel_mnemonic
, 1},
1026 {"att_mnemonic", set_intel_mnemonic
, 0},
1027 {"allow_index_reg", set_allow_index_reg
, 1},
1028 {"disallow_index_reg", set_allow_index_reg
, 0},
1029 {"sse_check", set_check
, 0},
1030 {"operand_check", set_check
, 1},
1031 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1032 {"largecomm", handle_large_common
, 0},
1034 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1035 {"loc", dwarf2_directive_loc
, 0},
1036 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1039 {"secrel32", pe_directive_secrel
, 0},
1044 /* For interface with expression (). */
1045 extern char *input_line_pointer
;
1047 /* Hash table for instruction mnemonic lookup. */
1048 static struct hash_control
*op_hash
;
1050 /* Hash table for register lookup. */
1051 static struct hash_control
*reg_hash
;
1054 i386_align_code (fragS
*fragP
, int count
)
1056 /* Various efficient no-op patterns for aligning code labels.
1057 Note: Don't try to assemble the instructions in the comments.
1058 0L and 0w are not legal. */
1059 static const char f32_1
[] =
1061 static const char f32_2
[] =
1062 {0x66,0x90}; /* xchg %ax,%ax */
1063 static const char f32_3
[] =
1064 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1065 static const char f32_4
[] =
1066 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1067 static const char f32_5
[] =
1069 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1070 static const char f32_6
[] =
1071 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1072 static const char f32_7
[] =
1073 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1074 static const char f32_8
[] =
1076 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1077 static const char f32_9
[] =
1078 {0x89,0xf6, /* movl %esi,%esi */
1079 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1080 static const char f32_10
[] =
1081 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1082 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1083 static const char f32_11
[] =
1084 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1085 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1086 static const char f32_12
[] =
1087 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1088 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1089 static const char f32_13
[] =
1090 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1091 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1092 static const char f32_14
[] =
1093 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1094 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1095 static const char f16_3
[] =
1096 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1097 static const char f16_4
[] =
1098 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1099 static const char f16_5
[] =
1101 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1102 static const char f16_6
[] =
1103 {0x89,0xf6, /* mov %si,%si */
1104 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1105 static const char f16_7
[] =
1106 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1107 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1108 static const char f16_8
[] =
1109 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1110 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1111 static const char jump_31
[] =
1112 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1113 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1114 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1115 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1116 static const char *const f32_patt
[] = {
1117 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1118 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1120 static const char *const f16_patt
[] = {
1121 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1123 /* nopl (%[re]ax) */
1124 static const char alt_3
[] =
1126 /* nopl 0(%[re]ax) */
1127 static const char alt_4
[] =
1128 {0x0f,0x1f,0x40,0x00};
1129 /* nopl 0(%[re]ax,%[re]ax,1) */
1130 static const char alt_5
[] =
1131 {0x0f,0x1f,0x44,0x00,0x00};
1132 /* nopw 0(%[re]ax,%[re]ax,1) */
1133 static const char alt_6
[] =
1134 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1135 /* nopl 0L(%[re]ax) */
1136 static const char alt_7
[] =
1137 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1138 /* nopl 0L(%[re]ax,%[re]ax,1) */
1139 static const char alt_8
[] =
1140 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1141 /* nopw 0L(%[re]ax,%[re]ax,1) */
1142 static const char alt_9
[] =
1143 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1144 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1145 static const char alt_10
[] =
1146 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1147 static const char *const alt_patt
[] = {
1148 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1152 /* Only align for at least a positive non-zero boundary. */
1153 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1156 /* We need to decide which NOP sequence to use for 32bit and
1157 64bit. When -mtune= is used:
1159 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1160 PROCESSOR_GENERIC32, f32_patt will be used.
1161 2. For the rest, alt_patt will be used.
1163 When -mtune= isn't used, alt_patt will be used if
1164 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1167 When -march= or .arch is used, we can't use anything beyond
1168 cpu_arch_isa_flags. */
1170 if (flag_code
== CODE_16BIT
)
1174 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1176 /* Adjust jump offset. */
1177 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1180 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1181 f16_patt
[count
- 1], count
);
1185 const char *const *patt
= NULL
;
1187 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1189 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1190 switch (cpu_arch_tune
)
1192 case PROCESSOR_UNKNOWN
:
1193 /* We use cpu_arch_isa_flags to check if we SHOULD
1194 optimize with nops. */
1195 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1200 case PROCESSOR_PENTIUM4
:
1201 case PROCESSOR_NOCONA
:
1202 case PROCESSOR_CORE
:
1203 case PROCESSOR_CORE2
:
1204 case PROCESSOR_COREI7
:
1205 case PROCESSOR_L1OM
:
1206 case PROCESSOR_K1OM
:
1207 case PROCESSOR_GENERIC64
:
1209 case PROCESSOR_ATHLON
:
1211 case PROCESSOR_AMDFAM10
:
1213 case PROCESSOR_ZNVER
:
1217 case PROCESSOR_I386
:
1218 case PROCESSOR_I486
:
1219 case PROCESSOR_PENTIUM
:
1220 case PROCESSOR_PENTIUMPRO
:
1221 case PROCESSOR_IAMCU
:
1222 case PROCESSOR_GENERIC32
:
1229 switch (fragP
->tc_frag_data
.tune
)
1231 case PROCESSOR_UNKNOWN
:
1232 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1233 PROCESSOR_UNKNOWN. */
1237 case PROCESSOR_I386
:
1238 case PROCESSOR_I486
:
1239 case PROCESSOR_PENTIUM
:
1240 case PROCESSOR_IAMCU
:
1242 case PROCESSOR_ATHLON
:
1244 case PROCESSOR_AMDFAM10
:
1246 case PROCESSOR_ZNVER
:
1248 case PROCESSOR_GENERIC32
:
1249 /* We use cpu_arch_isa_flags to check if we CAN optimize
1251 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1256 case PROCESSOR_PENTIUMPRO
:
1257 case PROCESSOR_PENTIUM4
:
1258 case PROCESSOR_NOCONA
:
1259 case PROCESSOR_CORE
:
1260 case PROCESSOR_CORE2
:
1261 case PROCESSOR_COREI7
:
1262 case PROCESSOR_L1OM
:
1263 case PROCESSOR_K1OM
:
1264 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1269 case PROCESSOR_GENERIC64
:
1275 if (patt
== f32_patt
)
1277 /* If the padding is less than 15 bytes, we use the normal
1278 ones. Otherwise, we use a jump instruction and adjust
1282 /* For 64bit, the limit is 3 bytes. */
1283 if (flag_code
== CODE_64BIT
1284 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1289 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1290 patt
[count
- 1], count
);
1293 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1295 /* Adjust jump offset. */
1296 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1301 /* Maximum length of an instruction is 10 byte. If the
1302 padding is greater than 10 bytes and we don't use jump,
1303 we have to break it into smaller pieces. */
1304 int padding
= count
;
1305 while (padding
> 10)
1308 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1313 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1314 patt
[padding
- 1], padding
);
1317 fragP
->fr_var
= count
;
1321 operand_type_all_zero (const union i386_operand_type
*x
)
1323 switch (ARRAY_SIZE(x
->array
))
1332 return !x
->array
[0];
1339 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1341 switch (ARRAY_SIZE(x
->array
))
1356 operand_type_equal (const union i386_operand_type
*x
,
1357 const union i386_operand_type
*y
)
1359 switch (ARRAY_SIZE(x
->array
))
1362 if (x
->array
[2] != y
->array
[2])
1365 if (x
->array
[1] != y
->array
[1])
1368 return x
->array
[0] == y
->array
[0];
1376 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1378 switch (ARRAY_SIZE(x
->array
))
1387 return !x
->array
[0];
1394 cpu_flags_equal (const union i386_cpu_flags
*x
,
1395 const union i386_cpu_flags
*y
)
1397 switch (ARRAY_SIZE(x
->array
))
1400 if (x
->array
[2] != y
->array
[2])
1403 if (x
->array
[1] != y
->array
[1])
1406 return x
->array
[0] == y
->array
[0];
1414 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1416 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1417 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1420 static INLINE i386_cpu_flags
1421 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1423 switch (ARRAY_SIZE (x
.array
))
1426 x
.array
[2] &= y
.array
[2];
1428 x
.array
[1] &= y
.array
[1];
1430 x
.array
[0] &= y
.array
[0];
1438 static INLINE i386_cpu_flags
1439 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1441 switch (ARRAY_SIZE (x
.array
))
1444 x
.array
[2] |= y
.array
[2];
1446 x
.array
[1] |= y
.array
[1];
1448 x
.array
[0] |= y
.array
[0];
1456 static INLINE i386_cpu_flags
1457 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1459 switch (ARRAY_SIZE (x
.array
))
1462 x
.array
[2] &= ~y
.array
[2];
1464 x
.array
[1] &= ~y
.array
[1];
1466 x
.array
[0] &= ~y
.array
[0];
1475 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1477 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1479 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1480 i386_cpu_flags compat_flags
;
1481 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1482 return cpu_flags_all_zero (&compat_flags
);
1488 #define CPU_FLAGS_ARCH_MATCH 0x1
1489 #define CPU_FLAGS_64BIT_MATCH 0x2
1490 #define CPU_FLAGS_AES_MATCH 0x4
1491 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1492 #define CPU_FLAGS_AVX_MATCH 0x10
1494 #define CPU_FLAGS_32BIT_MATCH \
1495 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1496 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1497 #define CPU_FLAGS_PERFECT_MATCH \
1498 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1500 /* Return CPU flags match bits. */
1503 cpu_flags_match (const insn_template
*t
)
1505 i386_cpu_flags x
= t
->cpu_flags
;
1506 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1508 x
.bitfield
.cpu64
= 0;
1509 x
.bitfield
.cpuno64
= 0;
1511 if (cpu_flags_all_zero (&x
))
1513 /* This instruction is available on all archs. */
1514 match
|= CPU_FLAGS_32BIT_MATCH
;
1518 /* This instruction is available only on some archs. */
1519 i386_cpu_flags cpu
= cpu_arch_flags
;
1521 cpu
.bitfield
.cpu64
= 0;
1522 cpu
.bitfield
.cpuno64
= 0;
1523 cpu
= cpu_flags_and (x
, cpu
);
1524 if (!cpu_flags_all_zero (&cpu
))
1526 if (x
.bitfield
.cpuavx
)
1528 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1529 if (cpu
.bitfield
.cpuavx
)
1531 /* Check SSE2AVX. */
1532 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1534 match
|= (CPU_FLAGS_ARCH_MATCH
1535 | CPU_FLAGS_AVX_MATCH
);
1537 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1538 match
|= CPU_FLAGS_AES_MATCH
;
1540 if (!x
.bitfield
.cpupclmul
1541 || cpu
.bitfield
.cpupclmul
)
1542 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1546 match
|= CPU_FLAGS_ARCH_MATCH
;
1549 match
|= CPU_FLAGS_32BIT_MATCH
;
1555 static INLINE i386_operand_type
1556 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1558 switch (ARRAY_SIZE (x
.array
))
1561 x
.array
[2] &= y
.array
[2];
1563 x
.array
[1] &= y
.array
[1];
1565 x
.array
[0] &= y
.array
[0];
1573 static INLINE i386_operand_type
1574 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1576 switch (ARRAY_SIZE (x
.array
))
1579 x
.array
[2] |= y
.array
[2];
1581 x
.array
[1] |= y
.array
[1];
1583 x
.array
[0] |= y
.array
[0];
1591 static INLINE i386_operand_type
1592 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1594 switch (ARRAY_SIZE (x
.array
))
1597 x
.array
[2] ^= y
.array
[2];
1599 x
.array
[1] ^= y
.array
[1];
1601 x
.array
[0] ^= y
.array
[0];
1609 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1610 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1611 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1612 static const i386_operand_type inoutportreg
1613 = OPERAND_TYPE_INOUTPORTREG
;
1614 static const i386_operand_type reg16_inoutportreg
1615 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1616 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1617 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1618 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1619 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1620 static const i386_operand_type anydisp
1621 = OPERAND_TYPE_ANYDISP
;
1622 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1623 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1624 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1625 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1626 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1627 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1628 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1629 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1630 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1631 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1632 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1633 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1634 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1635 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1646 operand_type_check (i386_operand_type t
, enum operand_type c
)
1651 return (t
.bitfield
.reg8
1654 || t
.bitfield
.reg64
);
1657 return (t
.bitfield
.imm8
1661 || t
.bitfield
.imm32s
1662 || t
.bitfield
.imm64
);
1665 return (t
.bitfield
.disp8
1666 || t
.bitfield
.disp16
1667 || t
.bitfield
.disp32
1668 || t
.bitfield
.disp32s
1669 || t
.bitfield
.disp64
);
1672 return (t
.bitfield
.disp8
1673 || t
.bitfield
.disp16
1674 || t
.bitfield
.disp32
1675 || t
.bitfield
.disp32s
1676 || t
.bitfield
.disp64
1677 || t
.bitfield
.baseindex
);
1686 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1687 operand J for instruction template T. */
1690 match_reg_size (const insn_template
*t
, unsigned int j
)
1692 return !((i
.types
[j
].bitfield
.byte
1693 && !t
->operand_types
[j
].bitfield
.byte
)
1694 || (i
.types
[j
].bitfield
.word
1695 && !t
->operand_types
[j
].bitfield
.word
)
1696 || (i
.types
[j
].bitfield
.dword
1697 && !t
->operand_types
[j
].bitfield
.dword
)
1698 || (i
.types
[j
].bitfield
.qword
1699 && !t
->operand_types
[j
].bitfield
.qword
));
1702 /* Return 1 if there is no conflict in any size on operand J for
1703 instruction template T. */
1706 match_mem_size (const insn_template
*t
, unsigned int j
)
1708 return (match_reg_size (t
, j
)
1709 && !((i
.types
[j
].bitfield
.unspecified
1711 && !t
->operand_types
[j
].bitfield
.unspecified
)
1712 || (i
.types
[j
].bitfield
.fword
1713 && !t
->operand_types
[j
].bitfield
.fword
)
1714 || (i
.types
[j
].bitfield
.tbyte
1715 && !t
->operand_types
[j
].bitfield
.tbyte
)
1716 || (i
.types
[j
].bitfield
.xmmword
1717 && !t
->operand_types
[j
].bitfield
.xmmword
)
1718 || (i
.types
[j
].bitfield
.ymmword
1719 && !t
->operand_types
[j
].bitfield
.ymmword
)
1720 || (i
.types
[j
].bitfield
.zmmword
1721 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1724 /* Return 1 if there is no size conflict on any operands for
1725 instruction template T. */
1728 operand_size_match (const insn_template
*t
)
1733 /* Don't check jump instructions. */
1734 if (t
->opcode_modifier
.jump
1735 || t
->opcode_modifier
.jumpbyte
1736 || t
->opcode_modifier
.jumpdword
1737 || t
->opcode_modifier
.jumpintersegment
)
1740 /* Check memory and accumulator operand size. */
1741 for (j
= 0; j
< i
.operands
; j
++)
1743 if (t
->operand_types
[j
].bitfield
.anysize
)
1746 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1752 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1761 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1764 i
.error
= operand_size_mismatch
;
1768 /* Check reverse. */
1769 gas_assert (i
.operands
== 2);
1772 for (j
= 0; j
< 2; j
++)
1774 if (t
->operand_types
[j
].bitfield
.acc
1775 && !match_reg_size (t
, j
? 0 : 1))
1778 if (i
.types
[j
].bitfield
.mem
1779 && !match_mem_size (t
, j
? 0 : 1))
1787 operand_type_match (i386_operand_type overlap
,
1788 i386_operand_type given
)
1790 i386_operand_type temp
= overlap
;
1792 temp
.bitfield
.jumpabsolute
= 0;
1793 temp
.bitfield
.unspecified
= 0;
1794 temp
.bitfield
.byte
= 0;
1795 temp
.bitfield
.word
= 0;
1796 temp
.bitfield
.dword
= 0;
1797 temp
.bitfield
.fword
= 0;
1798 temp
.bitfield
.qword
= 0;
1799 temp
.bitfield
.tbyte
= 0;
1800 temp
.bitfield
.xmmword
= 0;
1801 temp
.bitfield
.ymmword
= 0;
1802 temp
.bitfield
.zmmword
= 0;
1803 if (operand_type_all_zero (&temp
))
1806 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1807 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1811 i
.error
= operand_type_mismatch
;
1815 /* If given types g0 and g1 are registers they must be of the same type
1816 unless the expected operand type register overlap is null.
1817 Note that Acc in a template matches every size of reg. */
1820 operand_type_register_match (i386_operand_type m0
,
1821 i386_operand_type g0
,
1822 i386_operand_type t0
,
1823 i386_operand_type m1
,
1824 i386_operand_type g1
,
1825 i386_operand_type t1
)
1827 if (!operand_type_check (g0
, reg
))
1830 if (!operand_type_check (g1
, reg
))
1833 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1834 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1835 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1836 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1839 if (m0
.bitfield
.acc
)
1841 t0
.bitfield
.reg8
= 1;
1842 t0
.bitfield
.reg16
= 1;
1843 t0
.bitfield
.reg32
= 1;
1844 t0
.bitfield
.reg64
= 1;
1847 if (m1
.bitfield
.acc
)
1849 t1
.bitfield
.reg8
= 1;
1850 t1
.bitfield
.reg16
= 1;
1851 t1
.bitfield
.reg32
= 1;
1852 t1
.bitfield
.reg64
= 1;
1855 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1856 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1857 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1858 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1861 i
.error
= register_type_mismatch
;
1866 static INLINE
unsigned int
1867 register_number (const reg_entry
*r
)
1869 unsigned int nr
= r
->reg_num
;
1871 if (r
->reg_flags
& RegRex
)
1877 static INLINE
unsigned int
1878 mode_from_disp_size (i386_operand_type t
)
1880 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1882 else if (t
.bitfield
.disp16
1883 || t
.bitfield
.disp32
1884 || t
.bitfield
.disp32s
)
1891 fits_in_signed_byte (addressT num
)
1893 return num
+ 0x80 <= 0xff;
1897 fits_in_unsigned_byte (addressT num
)
1903 fits_in_unsigned_word (addressT num
)
1905 return num
<= 0xffff;
1909 fits_in_signed_word (addressT num
)
1911 return num
+ 0x8000 <= 0xffff;
1915 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1920 return num
+ 0x80000000 <= 0xffffffff;
1922 } /* fits_in_signed_long() */
1925 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1930 return num
<= 0xffffffff;
1932 } /* fits_in_unsigned_long() */
1935 fits_in_vec_disp8 (offsetT num
)
1937 int shift
= i
.memshift
;
1943 mask
= (1 << shift
) - 1;
1945 /* Return 0 if NUM isn't properly aligned. */
1949 /* Check if NUM will fit in 8bit after shift. */
1950 return fits_in_signed_byte (num
>> shift
);
1954 fits_in_imm4 (offsetT num
)
1956 return (num
& 0xf) == num
;
1959 static i386_operand_type
1960 smallest_imm_type (offsetT num
)
1962 i386_operand_type t
;
1964 operand_type_set (&t
, 0);
1965 t
.bitfield
.imm64
= 1;
1967 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1969 /* This code is disabled on the 486 because all the Imm1 forms
1970 in the opcode table are slower on the i486. They're the
1971 versions with the implicitly specified single-position
1972 displacement, which has another syntax if you really want to
1974 t
.bitfield
.imm1
= 1;
1975 t
.bitfield
.imm8
= 1;
1976 t
.bitfield
.imm8s
= 1;
1977 t
.bitfield
.imm16
= 1;
1978 t
.bitfield
.imm32
= 1;
1979 t
.bitfield
.imm32s
= 1;
1981 else if (fits_in_signed_byte (num
))
1983 t
.bitfield
.imm8
= 1;
1984 t
.bitfield
.imm8s
= 1;
1985 t
.bitfield
.imm16
= 1;
1986 t
.bitfield
.imm32
= 1;
1987 t
.bitfield
.imm32s
= 1;
1989 else if (fits_in_unsigned_byte (num
))
1991 t
.bitfield
.imm8
= 1;
1992 t
.bitfield
.imm16
= 1;
1993 t
.bitfield
.imm32
= 1;
1994 t
.bitfield
.imm32s
= 1;
1996 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1998 t
.bitfield
.imm16
= 1;
1999 t
.bitfield
.imm32
= 1;
2000 t
.bitfield
.imm32s
= 1;
2002 else if (fits_in_signed_long (num
))
2004 t
.bitfield
.imm32
= 1;
2005 t
.bitfield
.imm32s
= 1;
2007 else if (fits_in_unsigned_long (num
))
2008 t
.bitfield
.imm32
= 1;
2014 offset_in_range (offsetT val
, int size
)
2020 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2021 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2022 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2024 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2030 /* If BFD64, sign extend val for 32bit address mode. */
2031 if (flag_code
!= CODE_64BIT
2032 || i
.prefix
[ADDR_PREFIX
])
2033 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2034 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2037 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2039 char buf1
[40], buf2
[40];
2041 sprint_value (buf1
, val
);
2042 sprint_value (buf2
, val
& mask
);
2043 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2057 a. PREFIX_EXIST if attempting to add a prefix where one from the
2058 same class already exists.
2059 b. PREFIX_LOCK if lock prefix is added.
2060 c. PREFIX_REP if rep/repne prefix is added.
2061 d. PREFIX_OTHER if other prefix is added.
2064 static enum PREFIX_GROUP
2065 add_prefix (unsigned int prefix
)
2067 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2070 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2071 && flag_code
== CODE_64BIT
)
2073 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2074 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2075 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2086 case CS_PREFIX_OPCODE
:
2087 case DS_PREFIX_OPCODE
:
2088 case ES_PREFIX_OPCODE
:
2089 case FS_PREFIX_OPCODE
:
2090 case GS_PREFIX_OPCODE
:
2091 case SS_PREFIX_OPCODE
:
2095 case REPNE_PREFIX_OPCODE
:
2096 case REPE_PREFIX_OPCODE
:
2101 case LOCK_PREFIX_OPCODE
:
2110 case ADDR_PREFIX_OPCODE
:
2114 case DATA_PREFIX_OPCODE
:
2118 if (i
.prefix
[q
] != 0)
2126 i
.prefix
[q
] |= prefix
;
2129 as_bad (_("same type of prefix used twice"));
2135 update_code_flag (int value
, int check
)
2137 PRINTF_LIKE ((*as_error
));
2139 flag_code
= (enum flag_code
) value
;
2140 if (flag_code
== CODE_64BIT
)
2142 cpu_arch_flags
.bitfield
.cpu64
= 1;
2143 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2147 cpu_arch_flags
.bitfield
.cpu64
= 0;
2148 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2150 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2153 as_error
= as_fatal
;
2156 (*as_error
) (_("64bit mode not supported on `%s'."),
2157 cpu_arch_name
? cpu_arch_name
: default_arch
);
2159 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2162 as_error
= as_fatal
;
2165 (*as_error
) (_("32bit mode not supported on `%s'."),
2166 cpu_arch_name
? cpu_arch_name
: default_arch
);
2168 stackop_size
= '\0';
2172 set_code_flag (int value
)
2174 update_code_flag (value
, 0);
2178 set_16bit_gcc_code_flag (int new_code_flag
)
2180 flag_code
= (enum flag_code
) new_code_flag
;
2181 if (flag_code
!= CODE_16BIT
)
2183 cpu_arch_flags
.bitfield
.cpu64
= 0;
2184 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2185 stackop_size
= LONG_MNEM_SUFFIX
;
2189 set_intel_syntax (int syntax_flag
)
2191 /* Find out if register prefixing is specified. */
2192 int ask_naked_reg
= 0;
2195 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2198 int e
= get_symbol_name (&string
);
2200 if (strcmp (string
, "prefix") == 0)
2202 else if (strcmp (string
, "noprefix") == 0)
2205 as_bad (_("bad argument to syntax directive."));
2206 (void) restore_line_pointer (e
);
2208 demand_empty_rest_of_line ();
2210 intel_syntax
= syntax_flag
;
2212 if (ask_naked_reg
== 0)
2213 allow_naked_reg
= (intel_syntax
2214 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2216 allow_naked_reg
= (ask_naked_reg
< 0);
2218 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2220 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2221 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2222 register_prefix
= allow_naked_reg
? "" : "%";
2226 set_intel_mnemonic (int mnemonic_flag
)
2228 intel_mnemonic
= mnemonic_flag
;
2232 set_allow_index_reg (int flag
)
2234 allow_index_reg
= flag
;
2238 set_check (int what
)
2240 enum check_kind
*kind
;
2245 kind
= &operand_check
;
2256 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2259 int e
= get_symbol_name (&string
);
2261 if (strcmp (string
, "none") == 0)
2263 else if (strcmp (string
, "warning") == 0)
2264 *kind
= check_warning
;
2265 else if (strcmp (string
, "error") == 0)
2266 *kind
= check_error
;
2268 as_bad (_("bad argument to %s_check directive."), str
);
2269 (void) restore_line_pointer (e
);
2272 as_bad (_("missing argument for %s_check directive"), str
);
2274 demand_empty_rest_of_line ();
2278 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2279 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2281 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2282 static const char *arch
;
2284 /* Intel LIOM is only supported on ELF. */
2290 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2291 use default_arch. */
2292 arch
= cpu_arch_name
;
2294 arch
= default_arch
;
2297 /* If we are targeting Intel MCU, we must enable it. */
2298 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2299 || new_flag
.bitfield
.cpuiamcu
)
2302 /* If we are targeting Intel L1OM, we must enable it. */
2303 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2304 || new_flag
.bitfield
.cpul1om
)
2307 /* If we are targeting Intel K1OM, we must enable it. */
2308 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2309 || new_flag
.bitfield
.cpuk1om
)
2312 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2317 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2321 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2324 int e
= get_symbol_name (&string
);
2326 i386_cpu_flags flags
;
2328 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2330 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2332 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2336 cpu_arch_name
= cpu_arch
[j
].name
;
2337 cpu_sub_arch_name
= NULL
;
2338 cpu_arch_flags
= cpu_arch
[j
].flags
;
2339 if (flag_code
== CODE_64BIT
)
2341 cpu_arch_flags
.bitfield
.cpu64
= 1;
2342 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2346 cpu_arch_flags
.bitfield
.cpu64
= 0;
2347 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2349 cpu_arch_isa
= cpu_arch
[j
].type
;
2350 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2351 if (!cpu_arch_tune_set
)
2353 cpu_arch_tune
= cpu_arch_isa
;
2354 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2359 if (!cpu_arch
[j
].negated
)
2360 flags
= cpu_flags_or (cpu_arch_flags
,
2363 flags
= cpu_flags_and_not (cpu_arch_flags
,
2366 if (!valid_iamcu_cpu_flags (&flags
))
2367 as_fatal (_("`%s' isn't valid for Intel MCU"),
2369 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2371 if (cpu_sub_arch_name
)
2373 char *name
= cpu_sub_arch_name
;
2374 cpu_sub_arch_name
= concat (name
,
2376 (const char *) NULL
);
2380 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2381 cpu_arch_flags
= flags
;
2382 cpu_arch_isa_flags
= flags
;
2384 (void) restore_line_pointer (e
);
2385 demand_empty_rest_of_line ();
2389 if (j
>= ARRAY_SIZE (cpu_arch
))
2390 as_bad (_("no such architecture: `%s'"), string
);
2392 *input_line_pointer
= e
;
2395 as_bad (_("missing cpu architecture"));
2397 no_cond_jump_promotion
= 0;
2398 if (*input_line_pointer
== ','
2399 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2404 ++input_line_pointer
;
2405 e
= get_symbol_name (&string
);
2407 if (strcmp (string
, "nojumps") == 0)
2408 no_cond_jump_promotion
= 1;
2409 else if (strcmp (string
, "jumps") == 0)
2412 as_bad (_("no such architecture modifier: `%s'"), string
);
2414 (void) restore_line_pointer (e
);
2417 demand_empty_rest_of_line ();
2420 enum bfd_architecture
2423 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2425 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2426 || flag_code
!= CODE_64BIT
)
2427 as_fatal (_("Intel L1OM is 64bit ELF only"));
2428 return bfd_arch_l1om
;
2430 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2432 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2433 || flag_code
!= CODE_64BIT
)
2434 as_fatal (_("Intel K1OM is 64bit ELF only"));
2435 return bfd_arch_k1om
;
2437 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2439 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2440 || flag_code
== CODE_64BIT
)
2441 as_fatal (_("Intel MCU is 32bit ELF only"));
2442 return bfd_arch_iamcu
;
2445 return bfd_arch_i386
;
2451 if (!strncmp (default_arch
, "x86_64", 6))
2453 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2455 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2456 || default_arch
[6] != '\0')
2457 as_fatal (_("Intel L1OM is 64bit ELF only"));
2458 return bfd_mach_l1om
;
2460 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2462 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2463 || default_arch
[6] != '\0')
2464 as_fatal (_("Intel K1OM is 64bit ELF only"));
2465 return bfd_mach_k1om
;
2467 else if (default_arch
[6] == '\0')
2468 return bfd_mach_x86_64
;
2470 return bfd_mach_x64_32
;
2472 else if (!strcmp (default_arch
, "i386")
2473 || !strcmp (default_arch
, "iamcu"))
2475 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2477 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2478 as_fatal (_("Intel MCU is 32bit ELF only"));
2479 return bfd_mach_i386_iamcu
;
2482 return bfd_mach_i386_i386
;
2485 as_fatal (_("unknown architecture"));
2491 const char *hash_err
;
2493 /* Initialize op_hash hash table. */
2494 op_hash
= hash_new ();
2497 const insn_template
*optab
;
2498 templates
*core_optab
;
2500 /* Setup for loop. */
2502 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2503 core_optab
->start
= optab
;
2508 if (optab
->name
== NULL
2509 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2511 /* different name --> ship out current template list;
2512 add to hash table; & begin anew. */
2513 core_optab
->end
= optab
;
2514 hash_err
= hash_insert (op_hash
,
2516 (void *) core_optab
);
2519 as_fatal (_("can't hash %s: %s"),
2523 if (optab
->name
== NULL
)
2525 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2526 core_optab
->start
= optab
;
2531 /* Initialize reg_hash hash table. */
2532 reg_hash
= hash_new ();
2534 const reg_entry
*regtab
;
2535 unsigned int regtab_size
= i386_regtab_size
;
2537 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2539 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2541 as_fatal (_("can't hash %s: %s"),
2547 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2552 for (c
= 0; c
< 256; c
++)
2557 mnemonic_chars
[c
] = c
;
2558 register_chars
[c
] = c
;
2559 operand_chars
[c
] = c
;
2561 else if (ISLOWER (c
))
2563 mnemonic_chars
[c
] = c
;
2564 register_chars
[c
] = c
;
2565 operand_chars
[c
] = c
;
2567 else if (ISUPPER (c
))
2569 mnemonic_chars
[c
] = TOLOWER (c
);
2570 register_chars
[c
] = mnemonic_chars
[c
];
2571 operand_chars
[c
] = c
;
2573 else if (c
== '{' || c
== '}')
2574 operand_chars
[c
] = c
;
2576 if (ISALPHA (c
) || ISDIGIT (c
))
2577 identifier_chars
[c
] = c
;
2580 identifier_chars
[c
] = c
;
2581 operand_chars
[c
] = c
;
2586 identifier_chars
['@'] = '@';
2589 identifier_chars
['?'] = '?';
2590 operand_chars
['?'] = '?';
2592 digit_chars
['-'] = '-';
2593 mnemonic_chars
['_'] = '_';
2594 mnemonic_chars
['-'] = '-';
2595 mnemonic_chars
['.'] = '.';
2596 identifier_chars
['_'] = '_';
2597 identifier_chars
['.'] = '.';
2599 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2600 operand_chars
[(unsigned char) *p
] = *p
;
2603 if (flag_code
== CODE_64BIT
)
2605 #if defined (OBJ_COFF) && defined (TE_PE)
2606 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2609 x86_dwarf2_return_column
= 16;
2611 x86_cie_data_alignment
= -8;
2615 x86_dwarf2_return_column
= 8;
2616 x86_cie_data_alignment
= -4;
2621 i386_print_statistics (FILE *file
)
2623 hash_print_statistics (file
, "i386 opcode", op_hash
);
2624 hash_print_statistics (file
, "i386 register", reg_hash
);
2629 /* Debugging routines for md_assemble. */
2630 static void pte (insn_template
*);
2631 static void pt (i386_operand_type
);
2632 static void pe (expressionS
*);
2633 static void ps (symbolS
*);
2636 pi (char *line
, i386_insn
*x
)
2640 fprintf (stdout
, "%s: template ", line
);
2642 fprintf (stdout
, " address: base %s index %s scale %x\n",
2643 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2644 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2645 x
->log2_scale_factor
);
2646 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2647 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2648 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2649 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2650 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2651 (x
->rex
& REX_W
) != 0,
2652 (x
->rex
& REX_R
) != 0,
2653 (x
->rex
& REX_X
) != 0,
2654 (x
->rex
& REX_B
) != 0);
2655 for (j
= 0; j
< x
->operands
; j
++)
2657 fprintf (stdout
, " #%d: ", j
+ 1);
2659 fprintf (stdout
, "\n");
2660 if (x
->types
[j
].bitfield
.reg8
2661 || x
->types
[j
].bitfield
.reg16
2662 || x
->types
[j
].bitfield
.reg32
2663 || x
->types
[j
].bitfield
.reg64
2664 || x
->types
[j
].bitfield
.regmmx
2665 || x
->types
[j
].bitfield
.regxmm
2666 || x
->types
[j
].bitfield
.regymm
2667 || x
->types
[j
].bitfield
.regzmm
2668 || x
->types
[j
].bitfield
.sreg2
2669 || x
->types
[j
].bitfield
.sreg3
2670 || x
->types
[j
].bitfield
.control
2671 || x
->types
[j
].bitfield
.debug
2672 || x
->types
[j
].bitfield
.test
)
2673 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2674 if (operand_type_check (x
->types
[j
], imm
))
2676 if (operand_type_check (x
->types
[j
], disp
))
2677 pe (x
->op
[j
].disps
);
2682 pte (insn_template
*t
)
2685 fprintf (stdout
, " %d operands ", t
->operands
);
2686 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2687 if (t
->extension_opcode
!= None
)
2688 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2689 if (t
->opcode_modifier
.d
)
2690 fprintf (stdout
, "D");
2691 if (t
->opcode_modifier
.w
)
2692 fprintf (stdout
, "W");
2693 fprintf (stdout
, "\n");
2694 for (j
= 0; j
< t
->operands
; j
++)
2696 fprintf (stdout
, " #%d type ", j
+ 1);
2697 pt (t
->operand_types
[j
]);
2698 fprintf (stdout
, "\n");
2705 fprintf (stdout
, " operation %d\n", e
->X_op
);
2706 fprintf (stdout
, " add_number %ld (%lx)\n",
2707 (long) e
->X_add_number
, (long) e
->X_add_number
);
2708 if (e
->X_add_symbol
)
2710 fprintf (stdout
, " add_symbol ");
2711 ps (e
->X_add_symbol
);
2712 fprintf (stdout
, "\n");
2716 fprintf (stdout
, " op_symbol ");
2717 ps (e
->X_op_symbol
);
2718 fprintf (stdout
, "\n");
2725 fprintf (stdout
, "%s type %s%s",
2727 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2728 segment_name (S_GET_SEGMENT (s
)));
2731 static struct type_name
2733 i386_operand_type mask
;
2736 const type_names
[] =
2738 { OPERAND_TYPE_REG8
, "r8" },
2739 { OPERAND_TYPE_REG16
, "r16" },
2740 { OPERAND_TYPE_REG32
, "r32" },
2741 { OPERAND_TYPE_REG64
, "r64" },
2742 { OPERAND_TYPE_IMM8
, "i8" },
2743 { OPERAND_TYPE_IMM8
, "i8s" },
2744 { OPERAND_TYPE_IMM16
, "i16" },
2745 { OPERAND_TYPE_IMM32
, "i32" },
2746 { OPERAND_TYPE_IMM32S
, "i32s" },
2747 { OPERAND_TYPE_IMM64
, "i64" },
2748 { OPERAND_TYPE_IMM1
, "i1" },
2749 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2750 { OPERAND_TYPE_DISP8
, "d8" },
2751 { OPERAND_TYPE_DISP16
, "d16" },
2752 { OPERAND_TYPE_DISP32
, "d32" },
2753 { OPERAND_TYPE_DISP32S
, "d32s" },
2754 { OPERAND_TYPE_DISP64
, "d64" },
2755 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2756 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2757 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2758 { OPERAND_TYPE_CONTROL
, "control reg" },
2759 { OPERAND_TYPE_TEST
, "test reg" },
2760 { OPERAND_TYPE_DEBUG
, "debug reg" },
2761 { OPERAND_TYPE_FLOATREG
, "FReg" },
2762 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2763 { OPERAND_TYPE_SREG2
, "SReg2" },
2764 { OPERAND_TYPE_SREG3
, "SReg3" },
2765 { OPERAND_TYPE_ACC
, "Acc" },
2766 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2767 { OPERAND_TYPE_REGMMX
, "rMMX" },
2768 { OPERAND_TYPE_REGXMM
, "rXMM" },
2769 { OPERAND_TYPE_REGYMM
, "rYMM" },
2770 { OPERAND_TYPE_REGZMM
, "rZMM" },
2771 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2772 { OPERAND_TYPE_ESSEG
, "es" },
2776 pt (i386_operand_type t
)
2779 i386_operand_type a
;
2781 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2783 a
= operand_type_and (t
, type_names
[j
].mask
);
2784 if (!operand_type_all_zero (&a
))
2785 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2790 #endif /* DEBUG386 */
2792 static bfd_reloc_code_real_type
2793 reloc (unsigned int size
,
2796 bfd_reloc_code_real_type other
)
2798 if (other
!= NO_RELOC
)
2800 reloc_howto_type
*rel
;
2805 case BFD_RELOC_X86_64_GOT32
:
2806 return BFD_RELOC_X86_64_GOT64
;
2808 case BFD_RELOC_X86_64_GOTPLT64
:
2809 return BFD_RELOC_X86_64_GOTPLT64
;
2811 case BFD_RELOC_X86_64_PLTOFF64
:
2812 return BFD_RELOC_X86_64_PLTOFF64
;
2814 case BFD_RELOC_X86_64_GOTPC32
:
2815 other
= BFD_RELOC_X86_64_GOTPC64
;
2817 case BFD_RELOC_X86_64_GOTPCREL
:
2818 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2820 case BFD_RELOC_X86_64_TPOFF32
:
2821 other
= BFD_RELOC_X86_64_TPOFF64
;
2823 case BFD_RELOC_X86_64_DTPOFF32
:
2824 other
= BFD_RELOC_X86_64_DTPOFF64
;
2830 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2831 if (other
== BFD_RELOC_SIZE32
)
2834 other
= BFD_RELOC_SIZE64
;
2837 as_bad (_("there are no pc-relative size relocations"));
2843 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2844 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2847 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2849 as_bad (_("unknown relocation (%u)"), other
);
2850 else if (size
!= bfd_get_reloc_size (rel
))
2851 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2852 bfd_get_reloc_size (rel
),
2854 else if (pcrel
&& !rel
->pc_relative
)
2855 as_bad (_("non-pc-relative relocation for pc-relative field"));
2856 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2858 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2860 as_bad (_("relocated field and relocation type differ in signedness"));
2869 as_bad (_("there are no unsigned pc-relative relocations"));
2872 case 1: return BFD_RELOC_8_PCREL
;
2873 case 2: return BFD_RELOC_16_PCREL
;
2874 case 4: return BFD_RELOC_32_PCREL
;
2875 case 8: return BFD_RELOC_64_PCREL
;
2877 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2884 case 4: return BFD_RELOC_X86_64_32S
;
2889 case 1: return BFD_RELOC_8
;
2890 case 2: return BFD_RELOC_16
;
2891 case 4: return BFD_RELOC_32
;
2892 case 8: return BFD_RELOC_64
;
2894 as_bad (_("cannot do %s %u byte relocation"),
2895 sign
> 0 ? "signed" : "unsigned", size
);
2901 /* Here we decide which fixups can be adjusted to make them relative to
2902 the beginning of the section instead of the symbol. Basically we need
2903 to make sure that the dynamic relocations are done correctly, so in
2904 some cases we force the original symbol to be used. */
2907 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2909 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2913 /* Don't adjust pc-relative references to merge sections in 64-bit
2915 if (use_rela_relocations
2916 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2920 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2921 and changed later by validate_fix. */
2922 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2923 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2926 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2927 for size relocations. */
2928 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2929 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2930 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2931 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2932 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2933 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
2934 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2935 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2936 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2937 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2938 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2939 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2940 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2941 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2942 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2943 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2944 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2945 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2946 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2947 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
2948 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
2949 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2950 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2951 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2952 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2953 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2954 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2955 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2956 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2957 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2958 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2959 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2960 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2967 intel_float_operand (const char *mnemonic
)
2969 /* Note that the value returned is meaningful only for opcodes with (memory)
2970 operands, hence the code here is free to improperly handle opcodes that
2971 have no operands (for better performance and smaller code). */
2973 if (mnemonic
[0] != 'f')
2974 return 0; /* non-math */
2976 switch (mnemonic
[1])
2978 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2979 the fs segment override prefix not currently handled because no
2980 call path can make opcodes without operands get here */
2982 return 2 /* integer op */;
2984 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2985 return 3; /* fldcw/fldenv */
2988 if (mnemonic
[2] != 'o' /* fnop */)
2989 return 3; /* non-waiting control op */
2992 if (mnemonic
[2] == 's')
2993 return 3; /* frstor/frstpm */
2996 if (mnemonic
[2] == 'a')
2997 return 3; /* fsave */
2998 if (mnemonic
[2] == 't')
3000 switch (mnemonic
[3])
3002 case 'c': /* fstcw */
3003 case 'd': /* fstdw */
3004 case 'e': /* fstenv */
3005 case 's': /* fsts[gw] */
3011 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3012 return 0; /* fxsave/fxrstor are not really math ops */
3019 /* Build the VEX prefix. */
3022 build_vex_prefix (const insn_template
*t
)
3024 unsigned int register_specifier
;
3025 unsigned int implied_prefix
;
3026 unsigned int vector_length
;
3028 /* Check register specifier. */
3029 if (i
.vex
.register_specifier
)
3031 register_specifier
=
3032 ~register_number (i
.vex
.register_specifier
) & 0xf;
3033 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3036 register_specifier
= 0xf;
3038 /* Use 2-byte VEX prefix by swappping destination and source
3041 && i
.operands
== i
.reg_operands
3042 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3043 && i
.tm
.opcode_modifier
.s
3046 unsigned int xchg
= i
.operands
- 1;
3047 union i386_op temp_op
;
3048 i386_operand_type temp_type
;
3050 temp_type
= i
.types
[xchg
];
3051 i
.types
[xchg
] = i
.types
[0];
3052 i
.types
[0] = temp_type
;
3053 temp_op
= i
.op
[xchg
];
3054 i
.op
[xchg
] = i
.op
[0];
3057 gas_assert (i
.rm
.mode
== 3);
3061 i
.rm
.regmem
= i
.rm
.reg
;
3064 /* Use the next insn. */
3068 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3069 vector_length
= avxscalar
;
3071 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3073 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3078 case DATA_PREFIX_OPCODE
:
3081 case REPE_PREFIX_OPCODE
:
3084 case REPNE_PREFIX_OPCODE
:
3091 /* Use 2-byte VEX prefix if possible. */
3092 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3093 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3094 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3096 /* 2-byte VEX prefix. */
3100 i
.vex
.bytes
[0] = 0xc5;
3102 /* Check the REX.R bit. */
3103 r
= (i
.rex
& REX_R
) ? 0 : 1;
3104 i
.vex
.bytes
[1] = (r
<< 7
3105 | register_specifier
<< 3
3106 | vector_length
<< 2
3111 /* 3-byte VEX prefix. */
3116 switch (i
.tm
.opcode_modifier
.vexopcode
)
3120 i
.vex
.bytes
[0] = 0xc4;
3124 i
.vex
.bytes
[0] = 0xc4;
3128 i
.vex
.bytes
[0] = 0xc4;
3132 i
.vex
.bytes
[0] = 0x8f;
3136 i
.vex
.bytes
[0] = 0x8f;
3140 i
.vex
.bytes
[0] = 0x8f;
3146 /* The high 3 bits of the second VEX byte are 1's compliment
3147 of RXB bits from REX. */
3148 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3150 /* Check the REX.W bit. */
3151 w
= (i
.rex
& REX_W
) ? 1 : 0;
3152 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3155 i
.vex
.bytes
[2] = (w
<< 7
3156 | register_specifier
<< 3
3157 | vector_length
<< 2
3162 /* Build the EVEX prefix. */
3165 build_evex_prefix (void)
3167 unsigned int register_specifier
;
3168 unsigned int implied_prefix
;
3170 rex_byte vrex_used
= 0;
3172 /* Check register specifier. */
3173 if (i
.vex
.register_specifier
)
3175 gas_assert ((i
.vrex
& REX_X
) == 0);
3177 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3178 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3179 register_specifier
+= 8;
3180 /* The upper 16 registers are encoded in the fourth byte of the
3182 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3183 i
.vex
.bytes
[3] = 0x8;
3184 register_specifier
= ~register_specifier
& 0xf;
3188 register_specifier
= 0xf;
3190 /* Encode upper 16 vector index register in the fourth byte of
3192 if (!(i
.vrex
& REX_X
))
3193 i
.vex
.bytes
[3] = 0x8;
3198 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3203 case DATA_PREFIX_OPCODE
:
3206 case REPE_PREFIX_OPCODE
:
3209 case REPNE_PREFIX_OPCODE
:
3216 /* 4 byte EVEX prefix. */
3218 i
.vex
.bytes
[0] = 0x62;
3221 switch (i
.tm
.opcode_modifier
.vexopcode
)
3237 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3239 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3241 /* The fifth bit of the second EVEX byte is 1's compliment of the
3242 REX_R bit in VREX. */
3243 if (!(i
.vrex
& REX_R
))
3244 i
.vex
.bytes
[1] |= 0x10;
3248 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3250 /* When all operands are registers, the REX_X bit in REX is not
3251 used. We reuse it to encode the upper 16 registers, which is
3252 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3253 as 1's compliment. */
3254 if ((i
.vrex
& REX_B
))
3257 i
.vex
.bytes
[1] &= ~0x40;
3261 /* EVEX instructions shouldn't need the REX prefix. */
3262 i
.vrex
&= ~vrex_used
;
3263 gas_assert (i
.vrex
== 0);
3265 /* Check the REX.W bit. */
3266 w
= (i
.rex
& REX_W
) ? 1 : 0;
3267 if (i
.tm
.opcode_modifier
.vexw
)
3269 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3272 /* If w is not set it means we are dealing with WIG instruction. */
3275 if (evexwig
== evexw1
)
3279 /* Encode the U bit. */
3280 implied_prefix
|= 0x4;
3282 /* The third byte of the EVEX prefix. */
3283 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3285 /* The fourth byte of the EVEX prefix. */
3286 /* The zeroing-masking bit. */
3287 if (i
.mask
&& i
.mask
->zeroing
)
3288 i
.vex
.bytes
[3] |= 0x80;
3290 /* Don't always set the broadcast bit if there is no RC. */
3293 /* Encode the vector length. */
3294 unsigned int vec_length
;
3296 switch (i
.tm
.opcode_modifier
.evex
)
3298 case EVEXLIG
: /* LL' is ignored */
3299 vec_length
= evexlig
<< 5;
3302 vec_length
= 0 << 5;
3305 vec_length
= 1 << 5;
3308 vec_length
= 2 << 5;
3314 i
.vex
.bytes
[3] |= vec_length
;
3315 /* Encode the broadcast bit. */
3317 i
.vex
.bytes
[3] |= 0x10;
3321 if (i
.rounding
->type
!= saeonly
)
3322 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3324 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3327 if (i
.mask
&& i
.mask
->mask
)
3328 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3332 process_immext (void)
3336 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3339 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3340 with an opcode suffix which is coded in the same place as an
3341 8-bit immediate field would be.
3342 Here we check those operands and remove them afterwards. */
3345 for (x
= 0; x
< i
.operands
; x
++)
3346 if (register_number (i
.op
[x
].regs
) != x
)
3347 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3348 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3354 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3356 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3357 suffix which is coded in the same place as an 8-bit immediate
3359 Here we check those operands and remove them afterwards. */
3362 if (i
.operands
!= 3)
3365 for (x
= 0; x
< 2; x
++)
3366 if (register_number (i
.op
[x
].regs
) != x
)
3367 goto bad_register_operand
;
3369 /* Check for third operand for mwaitx/monitorx insn. */
3370 if (register_number (i
.op
[x
].regs
)
3371 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3373 bad_register_operand
:
3374 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3375 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3382 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3383 which is coded in the same place as an 8-bit immediate field
3384 would be. Here we fake an 8-bit immediate operand from the
3385 opcode suffix stored in tm.extension_opcode.
3387 AVX instructions also use this encoding, for some of
3388 3 argument instructions. */
3390 gas_assert (i
.imm_operands
<= 1
3392 || ((i
.tm
.opcode_modifier
.vex
3393 || i
.tm
.opcode_modifier
.evex
)
3394 && i
.operands
<= 4)));
3396 exp
= &im_expressions
[i
.imm_operands
++];
3397 i
.op
[i
.operands
].imms
= exp
;
3398 i
.types
[i
.operands
] = imm8
;
3400 exp
->X_op
= O_constant
;
3401 exp
->X_add_number
= i
.tm
.extension_opcode
;
3402 i
.tm
.extension_opcode
= None
;
3409 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3414 as_bad (_("invalid instruction `%s' after `%s'"),
3415 i
.tm
.name
, i
.hle_prefix
);
3418 if (i
.prefix
[LOCK_PREFIX
])
3420 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3424 case HLEPrefixRelease
:
3425 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3427 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3431 if (i
.mem_operands
== 0
3432 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3434 as_bad (_("memory destination needed for instruction `%s'"
3435 " after `xrelease'"), i
.tm
.name
);
3442 /* This is the guts of the machine-dependent assembler. LINE points to a
3443 machine dependent instruction. This function is supposed to emit
3444 the frags/bytes it assembles to. */
3447 md_assemble (char *line
)
3450 char mnemonic
[MAX_MNEM_SIZE
];
3451 const insn_template
*t
;
3453 /* Initialize globals. */
3454 memset (&i
, '\0', sizeof (i
));
3455 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3456 i
.reloc
[j
] = NO_RELOC
;
3457 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3458 memset (im_expressions
, '\0', sizeof (im_expressions
));
3459 save_stack_p
= save_stack
;
3461 /* First parse an instruction mnemonic & call i386_operand for the operands.
3462 We assume that the scrubber has arranged it so that line[0] is the valid
3463 start of a (possibly prefixed) mnemonic. */
3465 line
= parse_insn (line
, mnemonic
);
3469 line
= parse_operands (line
, mnemonic
);
3474 /* Now we've parsed the mnemonic into a set of templates, and have the
3475 operands at hand. */
3477 /* All intel opcodes have reversed operands except for "bound" and
3478 "enter". We also don't reverse intersegment "jmp" and "call"
3479 instructions with 2 immediate operands so that the immediate segment
3480 precedes the offset, as it does when in AT&T mode. */
3483 && (strcmp (mnemonic
, "bound") != 0)
3484 && (strcmp (mnemonic
, "invlpga") != 0)
3485 && !(operand_type_check (i
.types
[0], imm
)
3486 && operand_type_check (i
.types
[1], imm
)))
3489 /* The order of the immediates should be reversed
3490 for 2 immediates extrq and insertq instructions */
3491 if (i
.imm_operands
== 2
3492 && (strcmp (mnemonic
, "extrq") == 0
3493 || strcmp (mnemonic
, "insertq") == 0))
3494 swap_2_operands (0, 1);
3499 /* Don't optimize displacement for movabs since it only takes 64bit
3502 && i
.disp_encoding
!= disp_encoding_32bit
3503 && (flag_code
!= CODE_64BIT
3504 || strcmp (mnemonic
, "movabs") != 0))
3507 /* Next, we find a template that matches the given insn,
3508 making sure the overlap of the given operands types is consistent
3509 with the template operand types. */
3511 if (!(t
= match_template ()))
3514 if (sse_check
!= check_none
3515 && !i
.tm
.opcode_modifier
.noavx
3516 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3517 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3518 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3519 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3520 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3521 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3523 (sse_check
== check_warning
3525 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3528 /* Zap movzx and movsx suffix. The suffix has been set from
3529 "word ptr" or "byte ptr" on the source operand in Intel syntax
3530 or extracted from mnemonic in AT&T syntax. But we'll use
3531 the destination register to choose the suffix for encoding. */
3532 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3534 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3535 there is no suffix, the default will be byte extension. */
3536 if (i
.reg_operands
!= 2
3539 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3544 if (i
.tm
.opcode_modifier
.fwait
)
3545 if (!add_prefix (FWAIT_OPCODE
))
3548 /* Check if REP prefix is OK. */
3549 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3551 as_bad (_("invalid instruction `%s' after `%s'"),
3552 i
.tm
.name
, i
.rep_prefix
);
3556 /* Check for lock without a lockable instruction. Destination operand
3557 must be memory unless it is xchg (0x86). */
3558 if (i
.prefix
[LOCK_PREFIX
]
3559 && (!i
.tm
.opcode_modifier
.islockable
3560 || i
.mem_operands
== 0
3561 || (i
.tm
.base_opcode
!= 0x86
3562 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3564 as_bad (_("expecting lockable instruction after `lock'"));
3568 /* Check if HLE prefix is OK. */
3569 if (i
.hle_prefix
&& !check_hle ())
3572 /* Check BND prefix. */
3573 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3574 as_bad (_("expecting valid branch instruction after `bnd'"));
3576 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3577 && flag_code
== CODE_64BIT
3578 && i
.prefix
[ADDR_PREFIX
])
3579 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3581 /* Insert BND prefix. */
3583 && i
.tm
.opcode_modifier
.bndprefixok
3584 && !i
.prefix
[BND_PREFIX
])
3585 add_prefix (BND_PREFIX_OPCODE
);
3587 /* Check string instruction segment overrides. */
3588 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3590 if (!check_string ())
3592 i
.disp_operands
= 0;
3595 if (!process_suffix ())
3598 /* Update operand types. */
3599 for (j
= 0; j
< i
.operands
; j
++)
3600 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3602 /* Make still unresolved immediate matches conform to size of immediate
3603 given in i.suffix. */
3604 if (!finalize_imm ())
3607 if (i
.types
[0].bitfield
.imm1
)
3608 i
.imm_operands
= 0; /* kludge for shift insns. */
3610 /* We only need to check those implicit registers for instructions
3611 with 3 operands or less. */
3612 if (i
.operands
<= 3)
3613 for (j
= 0; j
< i
.operands
; j
++)
3614 if (i
.types
[j
].bitfield
.inoutportreg
3615 || i
.types
[j
].bitfield
.shiftcount
3616 || i
.types
[j
].bitfield
.acc
3617 || i
.types
[j
].bitfield
.floatacc
)
3620 /* ImmExt should be processed after SSE2AVX. */
3621 if (!i
.tm
.opcode_modifier
.sse2avx
3622 && i
.tm
.opcode_modifier
.immext
)
3625 /* For insns with operands there are more diddles to do to the opcode. */
3628 if (!process_operands ())
3631 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3633 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3634 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3637 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3639 if (flag_code
== CODE_16BIT
)
3641 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3646 if (i
.tm
.opcode_modifier
.vex
)
3647 build_vex_prefix (t
);
3649 build_evex_prefix ();
3652 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3653 instructions may define INT_OPCODE as well, so avoid this corner
3654 case for those instructions that use MODRM. */
3655 if (i
.tm
.base_opcode
== INT_OPCODE
3656 && !i
.tm
.opcode_modifier
.modrm
3657 && i
.op
[0].imms
->X_add_number
== 3)
3659 i
.tm
.base_opcode
= INT3_OPCODE
;
3663 if ((i
.tm
.opcode_modifier
.jump
3664 || i
.tm
.opcode_modifier
.jumpbyte
3665 || i
.tm
.opcode_modifier
.jumpdword
)
3666 && i
.op
[0].disps
->X_op
== O_constant
)
3668 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3669 the absolute address given by the constant. Since ix86 jumps and
3670 calls are pc relative, we need to generate a reloc. */
3671 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3672 i
.op
[0].disps
->X_op
= O_symbol
;
3675 if (i
.tm
.opcode_modifier
.rex64
)
3678 /* For 8 bit registers we need an empty rex prefix. Also if the
3679 instruction already has a prefix, we need to convert old
3680 registers to new ones. */
3682 if ((i
.types
[0].bitfield
.reg8
3683 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3684 || (i
.types
[1].bitfield
.reg8
3685 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3686 || ((i
.types
[0].bitfield
.reg8
3687 || i
.types
[1].bitfield
.reg8
)
3692 i
.rex
|= REX_OPCODE
;
3693 for (x
= 0; x
< 2; x
++)
3695 /* Look for 8 bit operand that uses old registers. */
3696 if (i
.types
[x
].bitfield
.reg8
3697 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3699 /* In case it is "hi" register, give up. */
3700 if (i
.op
[x
].regs
->reg_num
> 3)
3701 as_bad (_("can't encode register '%s%s' in an "
3702 "instruction requiring REX prefix."),
3703 register_prefix
, i
.op
[x
].regs
->reg_name
);
3705 /* Otherwise it is equivalent to the extended register.
3706 Since the encoding doesn't change this is merely
3707 cosmetic cleanup for debug output. */
3709 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3715 add_prefix (REX_OPCODE
| i
.rex
);
3717 /* We are ready to output the insn. */
3722 parse_insn (char *line
, char *mnemonic
)
3725 char *token_start
= l
;
3728 const insn_template
*t
;
3734 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3739 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3741 as_bad (_("no such instruction: `%s'"), token_start
);
3746 if (!is_space_char (*l
)
3747 && *l
!= END_OF_INSN
3749 || (*l
!= PREFIX_SEPARATOR
3752 as_bad (_("invalid character %s in mnemonic"),
3753 output_invalid (*l
));
3756 if (token_start
== l
)
3758 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3759 as_bad (_("expecting prefix; got nothing"));
3761 as_bad (_("expecting mnemonic; got nothing"));
3765 /* Look up instruction (or prefix) via hash table. */
3766 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3768 if (*l
!= END_OF_INSN
3769 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3770 && current_templates
3771 && current_templates
->start
->opcode_modifier
.isprefix
)
3773 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3775 as_bad ((flag_code
!= CODE_64BIT
3776 ? _("`%s' is only supported in 64-bit mode")
3777 : _("`%s' is not supported in 64-bit mode")),
3778 current_templates
->start
->name
);
3781 /* If we are in 16-bit mode, do not allow addr16 or data16.
3782 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3783 if ((current_templates
->start
->opcode_modifier
.size16
3784 || current_templates
->start
->opcode_modifier
.size32
)
3785 && flag_code
!= CODE_64BIT
3786 && (current_templates
->start
->opcode_modifier
.size32
3787 ^ (flag_code
== CODE_16BIT
)))
3789 as_bad (_("redundant %s prefix"),
3790 current_templates
->start
->name
);
3793 /* Add prefix, checking for repeated prefixes. */
3794 switch (add_prefix (current_templates
->start
->base_opcode
))
3799 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3800 i
.hle_prefix
= current_templates
->start
->name
;
3801 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3802 i
.bnd_prefix
= current_templates
->start
->name
;
3804 i
.rep_prefix
= current_templates
->start
->name
;
3809 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3816 if (!current_templates
)
3818 /* Check if we should swap operand or force 32bit displacement in
3820 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3822 else if (mnem_p
- 3 == dot_p
3825 i
.disp_encoding
= disp_encoding_8bit
;
3826 else if (mnem_p
- 4 == dot_p
3830 i
.disp_encoding
= disp_encoding_32bit
;
3835 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3838 if (!current_templates
)
3841 /* See if we can get a match by trimming off a suffix. */
3844 case WORD_MNEM_SUFFIX
:
3845 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3846 i
.suffix
= SHORT_MNEM_SUFFIX
;
3848 case BYTE_MNEM_SUFFIX
:
3849 case QWORD_MNEM_SUFFIX
:
3850 i
.suffix
= mnem_p
[-1];
3852 current_templates
= (const templates
*) hash_find (op_hash
,
3855 case SHORT_MNEM_SUFFIX
:
3856 case LONG_MNEM_SUFFIX
:
3859 i
.suffix
= mnem_p
[-1];
3861 current_templates
= (const templates
*) hash_find (op_hash
,
3870 if (intel_float_operand (mnemonic
) == 1)
3871 i
.suffix
= SHORT_MNEM_SUFFIX
;
3873 i
.suffix
= LONG_MNEM_SUFFIX
;
3875 current_templates
= (const templates
*) hash_find (op_hash
,
3880 if (!current_templates
)
3882 as_bad (_("no such instruction: `%s'"), token_start
);
3887 if (current_templates
->start
->opcode_modifier
.jump
3888 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3890 /* Check for a branch hint. We allow ",pt" and ",pn" for
3891 predict taken and predict not taken respectively.
3892 I'm not sure that branch hints actually do anything on loop
3893 and jcxz insns (JumpByte) for current Pentium4 chips. They
3894 may work in the future and it doesn't hurt to accept them
3896 if (l
[0] == ',' && l
[1] == 'p')
3900 if (!add_prefix (DS_PREFIX_OPCODE
))
3904 else if (l
[2] == 'n')
3906 if (!add_prefix (CS_PREFIX_OPCODE
))
3912 /* Any other comma loses. */
3915 as_bad (_("invalid character %s in mnemonic"),
3916 output_invalid (*l
));
3920 /* Check if instruction is supported on specified architecture. */
3922 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3924 supported
|= cpu_flags_match (t
);
3925 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3929 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3931 as_bad (flag_code
== CODE_64BIT
3932 ? _("`%s' is not supported in 64-bit mode")
3933 : _("`%s' is only supported in 64-bit mode"),
3934 current_templates
->start
->name
);
3937 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3939 as_bad (_("`%s' is not supported on `%s%s'"),
3940 current_templates
->start
->name
,
3941 cpu_arch_name
? cpu_arch_name
: default_arch
,
3942 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3947 if (!cpu_arch_flags
.bitfield
.cpui386
3948 && (flag_code
!= CODE_16BIT
))
3950 as_warn (_("use .code16 to ensure correct addressing mode"));
3957 parse_operands (char *l
, const char *mnemonic
)
3961 /* 1 if operand is pending after ','. */
3962 unsigned int expecting_operand
= 0;
3964 /* Non-zero if operand parens not balanced. */
3965 unsigned int paren_not_balanced
;
3967 while (*l
!= END_OF_INSN
)
3969 /* Skip optional white space before operand. */
3970 if (is_space_char (*l
))
3972 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
3974 as_bad (_("invalid character %s before operand %d"),
3975 output_invalid (*l
),
3979 token_start
= l
; /* After white space. */
3980 paren_not_balanced
= 0;
3981 while (paren_not_balanced
|| *l
!= ',')
3983 if (*l
== END_OF_INSN
)
3985 if (paren_not_balanced
)
3988 as_bad (_("unbalanced parenthesis in operand %d."),
3991 as_bad (_("unbalanced brackets in operand %d."),
3996 break; /* we are done */
3998 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4000 as_bad (_("invalid character %s in operand %d"),
4001 output_invalid (*l
),
4008 ++paren_not_balanced
;
4010 --paren_not_balanced
;
4015 ++paren_not_balanced
;
4017 --paren_not_balanced
;
4021 if (l
!= token_start
)
4022 { /* Yes, we've read in another operand. */
4023 unsigned int operand_ok
;
4024 this_operand
= i
.operands
++;
4025 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4026 if (i
.operands
> MAX_OPERANDS
)
4028 as_bad (_("spurious operands; (%d operands/instruction max)"),
4032 /* Now parse operand adding info to 'i' as we go along. */
4033 END_STRING_AND_SAVE (l
);
4037 i386_intel_operand (token_start
,
4038 intel_float_operand (mnemonic
));
4040 operand_ok
= i386_att_operand (token_start
);
4042 RESTORE_END_STRING (l
);
4048 if (expecting_operand
)
4050 expecting_operand_after_comma
:
4051 as_bad (_("expecting operand after ','; got nothing"));
4056 as_bad (_("expecting operand before ','; got nothing"));
4061 /* Now *l must be either ',' or END_OF_INSN. */
4064 if (*++l
== END_OF_INSN
)
4066 /* Just skip it, if it's \n complain. */
4067 goto expecting_operand_after_comma
;
4069 expecting_operand
= 1;
4076 swap_2_operands (int xchg1
, int xchg2
)
4078 union i386_op temp_op
;
4079 i386_operand_type temp_type
;
4080 enum bfd_reloc_code_real temp_reloc
;
4082 temp_type
= i
.types
[xchg2
];
4083 i
.types
[xchg2
] = i
.types
[xchg1
];
4084 i
.types
[xchg1
] = temp_type
;
4085 temp_op
= i
.op
[xchg2
];
4086 i
.op
[xchg2
] = i
.op
[xchg1
];
4087 i
.op
[xchg1
] = temp_op
;
4088 temp_reloc
= i
.reloc
[xchg2
];
4089 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4090 i
.reloc
[xchg1
] = temp_reloc
;
4094 if (i
.mask
->operand
== xchg1
)
4095 i
.mask
->operand
= xchg2
;
4096 else if (i
.mask
->operand
== xchg2
)
4097 i
.mask
->operand
= xchg1
;
4101 if (i
.broadcast
->operand
== xchg1
)
4102 i
.broadcast
->operand
= xchg2
;
4103 else if (i
.broadcast
->operand
== xchg2
)
4104 i
.broadcast
->operand
= xchg1
;
4108 if (i
.rounding
->operand
== xchg1
)
4109 i
.rounding
->operand
= xchg2
;
4110 else if (i
.rounding
->operand
== xchg2
)
4111 i
.rounding
->operand
= xchg1
;
4116 swap_operands (void)
4122 swap_2_operands (1, i
.operands
- 2);
4125 swap_2_operands (0, i
.operands
- 1);
4131 if (i
.mem_operands
== 2)
4133 const seg_entry
*temp_seg
;
4134 temp_seg
= i
.seg
[0];
4135 i
.seg
[0] = i
.seg
[1];
4136 i
.seg
[1] = temp_seg
;
4140 /* Try to ensure constant immediates are represented in the smallest
4145 char guess_suffix
= 0;
4149 guess_suffix
= i
.suffix
;
4150 else if (i
.reg_operands
)
4152 /* Figure out a suffix from the last register operand specified.
4153 We can't do this properly yet, ie. excluding InOutPortReg,
4154 but the following works for instructions with immediates.
4155 In any case, we can't set i.suffix yet. */
4156 for (op
= i
.operands
; --op
>= 0;)
4157 if (i
.types
[op
].bitfield
.reg8
)
4159 guess_suffix
= BYTE_MNEM_SUFFIX
;
4162 else if (i
.types
[op
].bitfield
.reg16
)
4164 guess_suffix
= WORD_MNEM_SUFFIX
;
4167 else if (i
.types
[op
].bitfield
.reg32
)
4169 guess_suffix
= LONG_MNEM_SUFFIX
;
4172 else if (i
.types
[op
].bitfield
.reg64
)
4174 guess_suffix
= QWORD_MNEM_SUFFIX
;
4178 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4179 guess_suffix
= WORD_MNEM_SUFFIX
;
4181 for (op
= i
.operands
; --op
>= 0;)
4182 if (operand_type_check (i
.types
[op
], imm
))
4184 switch (i
.op
[op
].imms
->X_op
)
4187 /* If a suffix is given, this operand may be shortened. */
4188 switch (guess_suffix
)
4190 case LONG_MNEM_SUFFIX
:
4191 i
.types
[op
].bitfield
.imm32
= 1;
4192 i
.types
[op
].bitfield
.imm64
= 1;
4194 case WORD_MNEM_SUFFIX
:
4195 i
.types
[op
].bitfield
.imm16
= 1;
4196 i
.types
[op
].bitfield
.imm32
= 1;
4197 i
.types
[op
].bitfield
.imm32s
= 1;
4198 i
.types
[op
].bitfield
.imm64
= 1;
4200 case BYTE_MNEM_SUFFIX
:
4201 i
.types
[op
].bitfield
.imm8
= 1;
4202 i
.types
[op
].bitfield
.imm8s
= 1;
4203 i
.types
[op
].bitfield
.imm16
= 1;
4204 i
.types
[op
].bitfield
.imm32
= 1;
4205 i
.types
[op
].bitfield
.imm32s
= 1;
4206 i
.types
[op
].bitfield
.imm64
= 1;
4210 /* If this operand is at most 16 bits, convert it
4211 to a signed 16 bit number before trying to see
4212 whether it will fit in an even smaller size.
4213 This allows a 16-bit operand such as $0xffe0 to
4214 be recognised as within Imm8S range. */
4215 if ((i
.types
[op
].bitfield
.imm16
)
4216 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4218 i
.op
[op
].imms
->X_add_number
=
4219 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4221 if ((i
.types
[op
].bitfield
.imm32
)
4222 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4225 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4226 ^ ((offsetT
) 1 << 31))
4227 - ((offsetT
) 1 << 31));
4230 = operand_type_or (i
.types
[op
],
4231 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4233 /* We must avoid matching of Imm32 templates when 64bit
4234 only immediate is available. */
4235 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4236 i
.types
[op
].bitfield
.imm32
= 0;
4243 /* Symbols and expressions. */
4245 /* Convert symbolic operand to proper sizes for matching, but don't
4246 prevent matching a set of insns that only supports sizes other
4247 than those matching the insn suffix. */
4249 i386_operand_type mask
, allowed
;
4250 const insn_template
*t
;
4252 operand_type_set (&mask
, 0);
4253 operand_type_set (&allowed
, 0);
4255 for (t
= current_templates
->start
;
4256 t
< current_templates
->end
;
4258 allowed
= operand_type_or (allowed
,
4259 t
->operand_types
[op
]);
4260 switch (guess_suffix
)
4262 case QWORD_MNEM_SUFFIX
:
4263 mask
.bitfield
.imm64
= 1;
4264 mask
.bitfield
.imm32s
= 1;
4266 case LONG_MNEM_SUFFIX
:
4267 mask
.bitfield
.imm32
= 1;
4269 case WORD_MNEM_SUFFIX
:
4270 mask
.bitfield
.imm16
= 1;
4272 case BYTE_MNEM_SUFFIX
:
4273 mask
.bitfield
.imm8
= 1;
4278 allowed
= operand_type_and (mask
, allowed
);
4279 if (!operand_type_all_zero (&allowed
))
4280 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4287 /* Try to use the smallest displacement type too. */
4289 optimize_disp (void)
4293 for (op
= i
.operands
; --op
>= 0;)
4294 if (operand_type_check (i
.types
[op
], disp
))
4296 if (i
.op
[op
].disps
->X_op
== O_constant
)
4298 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4300 if (i
.types
[op
].bitfield
.disp16
4301 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4303 /* If this operand is at most 16 bits, convert
4304 to a signed 16 bit number and don't use 64bit
4306 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4307 i
.types
[op
].bitfield
.disp64
= 0;
4309 if (i
.types
[op
].bitfield
.disp32
4310 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4312 /* If this operand is at most 32 bits, convert
4313 to a signed 32 bit number and don't use 64bit
4315 op_disp
&= (((offsetT
) 2 << 31) - 1);
4316 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4317 i
.types
[op
].bitfield
.disp64
= 0;
4319 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4321 i
.types
[op
].bitfield
.disp8
= 0;
4322 i
.types
[op
].bitfield
.disp16
= 0;
4323 i
.types
[op
].bitfield
.disp32
= 0;
4324 i
.types
[op
].bitfield
.disp32s
= 0;
4325 i
.types
[op
].bitfield
.disp64
= 0;
4329 else if (flag_code
== CODE_64BIT
)
4331 if (fits_in_signed_long (op_disp
))
4333 i
.types
[op
].bitfield
.disp64
= 0;
4334 i
.types
[op
].bitfield
.disp32s
= 1;
4336 if (i
.prefix
[ADDR_PREFIX
]
4337 && fits_in_unsigned_long (op_disp
))
4338 i
.types
[op
].bitfield
.disp32
= 1;
4340 if ((i
.types
[op
].bitfield
.disp32
4341 || i
.types
[op
].bitfield
.disp32s
4342 || i
.types
[op
].bitfield
.disp16
)
4343 && fits_in_signed_byte (op_disp
))
4344 i
.types
[op
].bitfield
.disp8
= 1;
4346 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4347 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4349 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4350 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4351 i
.types
[op
].bitfield
.disp8
= 0;
4352 i
.types
[op
].bitfield
.disp16
= 0;
4353 i
.types
[op
].bitfield
.disp32
= 0;
4354 i
.types
[op
].bitfield
.disp32s
= 0;
4355 i
.types
[op
].bitfield
.disp64
= 0;
4358 /* We only support 64bit displacement on constants. */
4359 i
.types
[op
].bitfield
.disp64
= 0;
4363 /* Check if operands are valid for the instruction. */
4366 check_VecOperands (const insn_template
*t
)
4370 /* Without VSIB byte, we can't have a vector register for index. */
4371 if (!t
->opcode_modifier
.vecsib
4373 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4374 || i
.index_reg
->reg_type
.bitfield
.regymm
4375 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4377 i
.error
= unsupported_vector_index_register
;
4381 /* Check if default mask is allowed. */
4382 if (t
->opcode_modifier
.nodefmask
4383 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4385 i
.error
= no_default_mask
;
4389 /* For VSIB byte, we need a vector register for index, and all vector
4390 registers must be distinct. */
4391 if (t
->opcode_modifier
.vecsib
)
4394 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4395 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4396 || (t
->opcode_modifier
.vecsib
== VecSIB256
4397 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4398 || (t
->opcode_modifier
.vecsib
== VecSIB512
4399 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4401 i
.error
= invalid_vsib_address
;
4405 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4406 if (i
.reg_operands
== 2 && !i
.mask
)
4408 gas_assert (i
.types
[0].bitfield
.regxmm
4409 || i
.types
[0].bitfield
.regymm
);
4410 gas_assert (i
.types
[2].bitfield
.regxmm
4411 || i
.types
[2].bitfield
.regymm
);
4412 if (operand_check
== check_none
)
4414 if (register_number (i
.op
[0].regs
)
4415 != register_number (i
.index_reg
)
4416 && register_number (i
.op
[2].regs
)
4417 != register_number (i
.index_reg
)
4418 && register_number (i
.op
[0].regs
)
4419 != register_number (i
.op
[2].regs
))
4421 if (operand_check
== check_error
)
4423 i
.error
= invalid_vector_register_set
;
4426 as_warn (_("mask, index, and destination registers should be distinct"));
4428 else if (i
.reg_operands
== 1 && i
.mask
)
4430 if ((i
.types
[1].bitfield
.regymm
4431 || i
.types
[1].bitfield
.regzmm
)
4432 && (register_number (i
.op
[1].regs
)
4433 == register_number (i
.index_reg
)))
4435 if (operand_check
== check_error
)
4437 i
.error
= invalid_vector_register_set
;
4440 if (operand_check
!= check_none
)
4441 as_warn (_("index and destination registers should be distinct"));
4446 /* Check if broadcast is supported by the instruction and is applied
4447 to the memory operand. */
4450 int broadcasted_opnd_size
;
4452 /* Check if specified broadcast is supported in this instruction,
4453 and it's applied to memory operand of DWORD or QWORD type,
4454 depending on VecESize. */
4455 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4456 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4457 || (t
->opcode_modifier
.vecesize
== 0
4458 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4459 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4460 || (t
->opcode_modifier
.vecesize
== 1
4461 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4462 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4465 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4466 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4467 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4468 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4469 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4470 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4471 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4472 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4473 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4477 if ((broadcasted_opnd_size
== 256
4478 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4479 || (broadcasted_opnd_size
== 512
4480 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4483 i
.error
= unsupported_broadcast
;
4487 /* If broadcast is supported in this instruction, we need to check if
4488 operand of one-element size isn't specified without broadcast. */
4489 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4491 /* Find memory operand. */
4492 for (op
= 0; op
< i
.operands
; op
++)
4493 if (operand_type_check (i
.types
[op
], anymem
))
4495 gas_assert (op
< i
.operands
);
4496 /* Check size of the memory operand. */
4497 if ((t
->opcode_modifier
.vecesize
== 0
4498 && i
.types
[op
].bitfield
.dword
)
4499 || (t
->opcode_modifier
.vecesize
== 1
4500 && i
.types
[op
].bitfield
.qword
))
4502 i
.error
= broadcast_needed
;
4507 /* Check if requested masking is supported. */
4509 && (!t
->opcode_modifier
.masking
4511 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4513 i
.error
= unsupported_masking
;
4517 /* Check if masking is applied to dest operand. */
4518 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4520 i
.error
= mask_not_on_destination
;
4527 if ((i
.rounding
->type
!= saeonly
4528 && !t
->opcode_modifier
.staticrounding
)
4529 || (i
.rounding
->type
== saeonly
4530 && (t
->opcode_modifier
.staticrounding
4531 || !t
->opcode_modifier
.sae
)))
4533 i
.error
= unsupported_rc_sae
;
4536 /* If the instruction has several immediate operands and one of
4537 them is rounding, the rounding operand should be the last
4538 immediate operand. */
4539 if (i
.imm_operands
> 1
4540 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4542 i
.error
= rc_sae_operand_not_last_imm
;
4547 /* Check vector Disp8 operand. */
4548 if (t
->opcode_modifier
.disp8memshift
)
4551 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4553 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4555 for (op
= 0; op
< i
.operands
; op
++)
4556 if (operand_type_check (i
.types
[op
], disp
)
4557 && i
.op
[op
].disps
->X_op
== O_constant
)
4559 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4560 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4561 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4564 i
.types
[op
].bitfield
.vec_disp8
= 1;
4567 /* Vector insn can only have Vec_Disp8/Disp32 in
4568 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4570 i
.types
[op
].bitfield
.disp8
= 0;
4571 if (flag_code
!= CODE_16BIT
)
4572 i
.types
[op
].bitfield
.disp16
= 0;
4575 else if (flag_code
!= CODE_16BIT
)
4577 /* One form of this instruction supports vector Disp8.
4578 Try vector Disp8 if we need to use Disp32. */
4579 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4581 i
.error
= try_vector_disp8
;
4593 /* Check if operands are valid for the instruction. Update VEX
4597 VEX_check_operands (const insn_template
*t
)
4599 /* VREX is only valid with EVEX prefix. */
4600 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4602 i
.error
= invalid_register_operand
;
4606 if (!t
->opcode_modifier
.vex
)
4609 /* Only check VEX_Imm4, which must be the first operand. */
4610 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4612 if (i
.op
[0].imms
->X_op
!= O_constant
4613 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4619 /* Turn off Imm8 so that update_imm won't complain. */
4620 i
.types
[0] = vec_imm4
;
4626 static const insn_template
*
4627 match_template (void)
4629 /* Points to template once we've found it. */
4630 const insn_template
*t
;
4631 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4632 i386_operand_type overlap4
;
4633 unsigned int found_reverse_match
;
4634 i386_opcode_modifier suffix_check
;
4635 i386_operand_type operand_types
[MAX_OPERANDS
];
4636 int addr_prefix_disp
;
4638 unsigned int found_cpu_match
;
4639 unsigned int check_register
;
4640 enum i386_error specific_error
= 0;
4642 #if MAX_OPERANDS != 5
4643 # error "MAX_OPERANDS must be 5."
4646 found_reverse_match
= 0;
4647 addr_prefix_disp
= -1;
4649 memset (&suffix_check
, 0, sizeof (suffix_check
));
4650 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4651 suffix_check
.no_bsuf
= 1;
4652 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4653 suffix_check
.no_wsuf
= 1;
4654 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4655 suffix_check
.no_ssuf
= 1;
4656 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4657 suffix_check
.no_lsuf
= 1;
4658 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4659 suffix_check
.no_qsuf
= 1;
4660 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4661 suffix_check
.no_ldsuf
= 1;
4663 /* Must have right number of operands. */
4664 i
.error
= number_of_operands_mismatch
;
4666 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4668 addr_prefix_disp
= -1;
4670 if (i
.operands
!= t
->operands
)
4673 /* Check processor support. */
4674 i
.error
= unsupported
;
4675 found_cpu_match
= (cpu_flags_match (t
)
4676 == CPU_FLAGS_PERFECT_MATCH
);
4677 if (!found_cpu_match
)
4680 /* Check old gcc support. */
4681 i
.error
= old_gcc_only
;
4682 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4685 /* Check AT&T mnemonic. */
4686 i
.error
= unsupported_with_intel_mnemonic
;
4687 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4690 /* Check AT&T/Intel syntax. */
4691 i
.error
= unsupported_syntax
;
4692 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4693 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4696 /* Check the suffix, except for some instructions in intel mode. */
4697 i
.error
= invalid_instruction_suffix
;
4698 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4699 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4700 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4701 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4702 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4703 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4704 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4707 if (!operand_size_match (t
))
4710 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4711 operand_types
[j
] = t
->operand_types
[j
];
4713 /* In general, don't allow 64-bit operands in 32-bit mode. */
4714 if (i
.suffix
== QWORD_MNEM_SUFFIX
4715 && flag_code
!= CODE_64BIT
4717 ? (!t
->opcode_modifier
.ignoresize
4718 && !intel_float_operand (t
->name
))
4719 : intel_float_operand (t
->name
) != 2)
4720 && ((!operand_types
[0].bitfield
.regmmx
4721 && !operand_types
[0].bitfield
.regxmm
4722 && !operand_types
[0].bitfield
.regymm
4723 && !operand_types
[0].bitfield
.regzmm
)
4724 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4725 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4726 && operand_types
[t
->operands
> 1].bitfield
.regymm
4727 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4728 && (t
->base_opcode
!= 0x0fc7
4729 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4732 /* In general, don't allow 32-bit operands on pre-386. */
4733 else if (i
.suffix
== LONG_MNEM_SUFFIX
4734 && !cpu_arch_flags
.bitfield
.cpui386
4736 ? (!t
->opcode_modifier
.ignoresize
4737 && !intel_float_operand (t
->name
))
4738 : intel_float_operand (t
->name
) != 2)
4739 && ((!operand_types
[0].bitfield
.regmmx
4740 && !operand_types
[0].bitfield
.regxmm
)
4741 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4742 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4745 /* Do not verify operands when there are none. */
4749 /* We've found a match; break out of loop. */
4753 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4754 into Disp32/Disp16/Disp32 operand. */
4755 if (i
.prefix
[ADDR_PREFIX
] != 0)
4757 /* There should be only one Disp operand. */
4761 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4763 if (operand_types
[j
].bitfield
.disp16
)
4765 addr_prefix_disp
= j
;
4766 operand_types
[j
].bitfield
.disp32
= 1;
4767 operand_types
[j
].bitfield
.disp16
= 0;
4773 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4775 if (operand_types
[j
].bitfield
.disp32
)
4777 addr_prefix_disp
= j
;
4778 operand_types
[j
].bitfield
.disp32
= 0;
4779 operand_types
[j
].bitfield
.disp16
= 1;
4785 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4787 if (operand_types
[j
].bitfield
.disp64
)
4789 addr_prefix_disp
= j
;
4790 operand_types
[j
].bitfield
.disp64
= 0;
4791 operand_types
[j
].bitfield
.disp32
= 1;
4799 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4800 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4803 /* We check register size if needed. */
4804 check_register
= t
->opcode_modifier
.checkregsize
;
4805 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4806 switch (t
->operands
)
4809 if (!operand_type_match (overlap0
, i
.types
[0]))
4813 /* xchg %eax, %eax is a special case. It is an aliase for nop
4814 only in 32bit mode and we can use opcode 0x90. In 64bit
4815 mode, we can't use 0x90 for xchg %eax, %eax since it should
4816 zero-extend %eax to %rax. */
4817 if (flag_code
== CODE_64BIT
4818 && t
->base_opcode
== 0x90
4819 && operand_type_equal (&i
.types
[0], &acc32
)
4820 && operand_type_equal (&i
.types
[1], &acc32
))
4824 /* If we swap operand in encoding, we either match
4825 the next one or reverse direction of operands. */
4826 if (t
->opcode_modifier
.s
)
4828 else if (t
->opcode_modifier
.d
)
4833 /* If we swap operand in encoding, we match the next one. */
4834 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4838 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4839 if (!operand_type_match (overlap0
, i
.types
[0])
4840 || !operand_type_match (overlap1
, i
.types
[1])
4842 && !operand_type_register_match (overlap0
, i
.types
[0],
4844 overlap1
, i
.types
[1],
4847 /* Check if other direction is valid ... */
4848 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4852 /* Try reversing direction of operands. */
4853 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4854 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4855 if (!operand_type_match (overlap0
, i
.types
[0])
4856 || !operand_type_match (overlap1
, i
.types
[1])
4858 && !operand_type_register_match (overlap0
,
4865 /* Does not match either direction. */
4868 /* found_reverse_match holds which of D or FloatDR
4870 if (t
->opcode_modifier
.d
)
4871 found_reverse_match
= Opcode_D
;
4872 else if (t
->opcode_modifier
.floatd
)
4873 found_reverse_match
= Opcode_FloatD
;
4875 found_reverse_match
= 0;
4876 if (t
->opcode_modifier
.floatr
)
4877 found_reverse_match
|= Opcode_FloatR
;
4881 /* Found a forward 2 operand match here. */
4882 switch (t
->operands
)
4885 overlap4
= operand_type_and (i
.types
[4],
4888 overlap3
= operand_type_and (i
.types
[3],
4891 overlap2
= operand_type_and (i
.types
[2],
4896 switch (t
->operands
)
4899 if (!operand_type_match (overlap4
, i
.types
[4])
4900 || !operand_type_register_match (overlap3
,
4908 if (!operand_type_match (overlap3
, i
.types
[3])
4910 && !operand_type_register_match (overlap2
,
4918 /* Here we make use of the fact that there are no
4919 reverse match 3 operand instructions, and all 3
4920 operand instructions only need to be checked for
4921 register consistency between operands 2 and 3. */
4922 if (!operand_type_match (overlap2
, i
.types
[2])
4924 && !operand_type_register_match (overlap1
,
4934 /* Found either forward/reverse 2, 3 or 4 operand match here:
4935 slip through to break. */
4937 if (!found_cpu_match
)
4939 found_reverse_match
= 0;
4943 /* Check if vector and VEX operands are valid. */
4944 if (check_VecOperands (t
) || VEX_check_operands (t
))
4946 specific_error
= i
.error
;
4950 /* We've found a match; break out of loop. */
4954 if (t
== current_templates
->end
)
4956 /* We found no match. */
4957 const char *err_msg
;
4958 switch (specific_error
? specific_error
: i
.error
)
4962 case operand_size_mismatch
:
4963 err_msg
= _("operand size mismatch");
4965 case operand_type_mismatch
:
4966 err_msg
= _("operand type mismatch");
4968 case register_type_mismatch
:
4969 err_msg
= _("register type mismatch");
4971 case number_of_operands_mismatch
:
4972 err_msg
= _("number of operands mismatch");
4974 case invalid_instruction_suffix
:
4975 err_msg
= _("invalid instruction suffix");
4978 err_msg
= _("constant doesn't fit in 4 bits");
4981 err_msg
= _("only supported with old gcc");
4983 case unsupported_with_intel_mnemonic
:
4984 err_msg
= _("unsupported with Intel mnemonic");
4986 case unsupported_syntax
:
4987 err_msg
= _("unsupported syntax");
4990 as_bad (_("unsupported instruction `%s'"),
4991 current_templates
->start
->name
);
4993 case invalid_vsib_address
:
4994 err_msg
= _("invalid VSIB address");
4996 case invalid_vector_register_set
:
4997 err_msg
= _("mask, index, and destination registers must be distinct");
4999 case unsupported_vector_index_register
:
5000 err_msg
= _("unsupported vector index register");
5002 case unsupported_broadcast
:
5003 err_msg
= _("unsupported broadcast");
5005 case broadcast_not_on_src_operand
:
5006 err_msg
= _("broadcast not on source memory operand");
5008 case broadcast_needed
:
5009 err_msg
= _("broadcast is needed for operand of such type");
5011 case unsupported_masking
:
5012 err_msg
= _("unsupported masking");
5014 case mask_not_on_destination
:
5015 err_msg
= _("mask not on destination operand");
5017 case no_default_mask
:
5018 err_msg
= _("default mask isn't allowed");
5020 case unsupported_rc_sae
:
5021 err_msg
= _("unsupported static rounding/sae");
5023 case rc_sae_operand_not_last_imm
:
5025 err_msg
= _("RC/SAE operand must precede immediate operands");
5027 err_msg
= _("RC/SAE operand must follow immediate operands");
5029 case invalid_register_operand
:
5030 err_msg
= _("invalid register operand");
5033 as_bad (_("%s for `%s'"), err_msg
,
5034 current_templates
->start
->name
);
5038 if (!quiet_warnings
)
5041 && (i
.types
[0].bitfield
.jumpabsolute
5042 != operand_types
[0].bitfield
.jumpabsolute
))
5044 as_warn (_("indirect %s without `*'"), t
->name
);
5047 if (t
->opcode_modifier
.isprefix
5048 && t
->opcode_modifier
.ignoresize
)
5050 /* Warn them that a data or address size prefix doesn't
5051 affect assembly of the next line of code. */
5052 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5056 /* Copy the template we found. */
5059 if (addr_prefix_disp
!= -1)
5060 i
.tm
.operand_types
[addr_prefix_disp
]
5061 = operand_types
[addr_prefix_disp
];
5063 if (found_reverse_match
)
5065 /* If we found a reverse match we must alter the opcode
5066 direction bit. found_reverse_match holds bits to change
5067 (different for int & float insns). */
5069 i
.tm
.base_opcode
^= found_reverse_match
;
5071 i
.tm
.operand_types
[0] = operand_types
[1];
5072 i
.tm
.operand_types
[1] = operand_types
[0];
5081 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5082 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5084 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5086 as_bad (_("`%s' operand %d must use `%ses' segment"),
5092 /* There's only ever one segment override allowed per instruction.
5093 This instruction possibly has a legal segment override on the
5094 second operand, so copy the segment to where non-string
5095 instructions store it, allowing common code. */
5096 i
.seg
[0] = i
.seg
[1];
5098 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5100 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5102 as_bad (_("`%s' operand %d must use `%ses' segment"),
5113 process_suffix (void)
5115 /* If matched instruction specifies an explicit instruction mnemonic
5117 if (i
.tm
.opcode_modifier
.size16
)
5118 i
.suffix
= WORD_MNEM_SUFFIX
;
5119 else if (i
.tm
.opcode_modifier
.size32
)
5120 i
.suffix
= LONG_MNEM_SUFFIX
;
5121 else if (i
.tm
.opcode_modifier
.size64
)
5122 i
.suffix
= QWORD_MNEM_SUFFIX
;
5123 else if (i
.reg_operands
)
5125 /* If there's no instruction mnemonic suffix we try to invent one
5126 based on register operands. */
5129 /* We take i.suffix from the last register operand specified,
5130 Destination register type is more significant than source
5131 register type. crc32 in SSE4.2 prefers source register
5133 if (i
.tm
.base_opcode
== 0xf20f38f1)
5135 if (i
.types
[0].bitfield
.reg16
)
5136 i
.suffix
= WORD_MNEM_SUFFIX
;
5137 else if (i
.types
[0].bitfield
.reg32
)
5138 i
.suffix
= LONG_MNEM_SUFFIX
;
5139 else if (i
.types
[0].bitfield
.reg64
)
5140 i
.suffix
= QWORD_MNEM_SUFFIX
;
5142 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5144 if (i
.types
[0].bitfield
.reg8
)
5145 i
.suffix
= BYTE_MNEM_SUFFIX
;
5152 if (i
.tm
.base_opcode
== 0xf20f38f1
5153 || i
.tm
.base_opcode
== 0xf20f38f0)
5155 /* We have to know the operand size for crc32. */
5156 as_bad (_("ambiguous memory operand size for `%s`"),
5161 for (op
= i
.operands
; --op
>= 0;)
5162 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5164 if (i
.types
[op
].bitfield
.reg8
)
5166 i
.suffix
= BYTE_MNEM_SUFFIX
;
5169 else if (i
.types
[op
].bitfield
.reg16
)
5171 i
.suffix
= WORD_MNEM_SUFFIX
;
5174 else if (i
.types
[op
].bitfield
.reg32
)
5176 i
.suffix
= LONG_MNEM_SUFFIX
;
5179 else if (i
.types
[op
].bitfield
.reg64
)
5181 i
.suffix
= QWORD_MNEM_SUFFIX
;
5187 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5190 && i
.tm
.opcode_modifier
.ignoresize
5191 && i
.tm
.opcode_modifier
.no_bsuf
)
5193 else if (!check_byte_reg ())
5196 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5199 && i
.tm
.opcode_modifier
.ignoresize
5200 && i
.tm
.opcode_modifier
.no_lsuf
)
5202 else if (!check_long_reg ())
5205 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5208 && i
.tm
.opcode_modifier
.ignoresize
5209 && i
.tm
.opcode_modifier
.no_qsuf
)
5211 else if (!check_qword_reg ())
5214 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5217 && i
.tm
.opcode_modifier
.ignoresize
5218 && i
.tm
.opcode_modifier
.no_wsuf
)
5220 else if (!check_word_reg ())
5223 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5224 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5225 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5227 /* Skip if the instruction has x/y/z suffix. match_template
5228 should check if it is a valid suffix. */
5230 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5231 /* Do nothing if the instruction is going to ignore the prefix. */
5236 else if (i
.tm
.opcode_modifier
.defaultsize
5238 /* exclude fldenv/frstor/fsave/fstenv */
5239 && i
.tm
.opcode_modifier
.no_ssuf
)
5241 i
.suffix
= stackop_size
;
5243 else if (intel_syntax
5245 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5246 || i
.tm
.opcode_modifier
.jumpbyte
5247 || i
.tm
.opcode_modifier
.jumpintersegment
5248 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5249 && i
.tm
.extension_opcode
<= 3)))
5254 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5256 i
.suffix
= QWORD_MNEM_SUFFIX
;
5260 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5261 i
.suffix
= LONG_MNEM_SUFFIX
;
5264 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5265 i
.suffix
= WORD_MNEM_SUFFIX
;
5274 if (i
.tm
.opcode_modifier
.w
)
5276 as_bad (_("no instruction mnemonic suffix given and "
5277 "no register operands; can't size instruction"));
5283 unsigned int suffixes
;
5285 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5286 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5288 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5290 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5292 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5294 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5297 /* There are more than suffix matches. */
5298 if (i
.tm
.opcode_modifier
.w
5299 || ((suffixes
& (suffixes
- 1))
5300 && !i
.tm
.opcode_modifier
.defaultsize
5301 && !i
.tm
.opcode_modifier
.ignoresize
))
5303 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5309 /* Change the opcode based on the operand size given by i.suffix;
5310 We don't need to change things for byte insns. */
5313 && i
.suffix
!= BYTE_MNEM_SUFFIX
5314 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5315 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5316 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5318 /* It's not a byte, select word/dword operation. */
5319 if (i
.tm
.opcode_modifier
.w
)
5321 if (i
.tm
.opcode_modifier
.shortform
)
5322 i
.tm
.base_opcode
|= 8;
5324 i
.tm
.base_opcode
|= 1;
5327 /* Now select between word & dword operations via the operand
5328 size prefix, except for instructions that will ignore this
5330 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5332 /* The address size override prefix changes the size of the
5334 if ((flag_code
== CODE_32BIT
5335 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5336 || (flag_code
!= CODE_32BIT
5337 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5338 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5341 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5342 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5343 && !i
.tm
.opcode_modifier
.ignoresize
5344 && !i
.tm
.opcode_modifier
.floatmf
5345 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5346 || (flag_code
== CODE_64BIT
5347 && i
.tm
.opcode_modifier
.jumpbyte
)))
5349 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5351 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5352 prefix
= ADDR_PREFIX_OPCODE
;
5354 if (!add_prefix (prefix
))
5358 /* Set mode64 for an operand. */
5359 if (i
.suffix
== QWORD_MNEM_SUFFIX
5360 && flag_code
== CODE_64BIT
5361 && !i
.tm
.opcode_modifier
.norex64
)
5363 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5364 need rex64. cmpxchg8b is also a special case. */
5365 if (! (i
.operands
== 2
5366 && i
.tm
.base_opcode
== 0x90
5367 && i
.tm
.extension_opcode
== None
5368 && operand_type_equal (&i
.types
[0], &acc64
)
5369 && operand_type_equal (&i
.types
[1], &acc64
))
5370 && ! (i
.operands
== 1
5371 && i
.tm
.base_opcode
== 0xfc7
5372 && i
.tm
.extension_opcode
== 1
5373 && !operand_type_check (i
.types
[0], reg
)
5374 && operand_type_check (i
.types
[0], anymem
)))
5378 /* Size floating point instruction. */
5379 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5380 if (i
.tm
.opcode_modifier
.floatmf
)
5381 i
.tm
.base_opcode
^= 4;
5388 check_byte_reg (void)
5392 for (op
= i
.operands
; --op
>= 0;)
5394 /* If this is an eight bit register, it's OK. If it's the 16 or
5395 32 bit version of an eight bit register, we will just use the
5396 low portion, and that's OK too. */
5397 if (i
.types
[op
].bitfield
.reg8
)
5400 /* I/O port address operands are OK too. */
5401 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5404 /* crc32 doesn't generate this warning. */
5405 if (i
.tm
.base_opcode
== 0xf20f38f0)
5408 if ((i
.types
[op
].bitfield
.reg16
5409 || i
.types
[op
].bitfield
.reg32
5410 || i
.types
[op
].bitfield
.reg64
)
5411 && i
.op
[op
].regs
->reg_num
< 4
5412 /* Prohibit these changes in 64bit mode, since the lowering
5413 would be more complicated. */
5414 && flag_code
!= CODE_64BIT
)
5416 #if REGISTER_WARNINGS
5417 if (!quiet_warnings
)
5418 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5420 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5421 ? REGNAM_AL
- REGNAM_AX
5422 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5424 i
.op
[op
].regs
->reg_name
,
5429 /* Any other register is bad. */
5430 if (i
.types
[op
].bitfield
.reg16
5431 || i
.types
[op
].bitfield
.reg32
5432 || i
.types
[op
].bitfield
.reg64
5433 || i
.types
[op
].bitfield
.regmmx
5434 || i
.types
[op
].bitfield
.regxmm
5435 || i
.types
[op
].bitfield
.regymm
5436 || i
.types
[op
].bitfield
.regzmm
5437 || i
.types
[op
].bitfield
.sreg2
5438 || i
.types
[op
].bitfield
.sreg3
5439 || i
.types
[op
].bitfield
.control
5440 || i
.types
[op
].bitfield
.debug
5441 || i
.types
[op
].bitfield
.test
5442 || i
.types
[op
].bitfield
.floatreg
5443 || i
.types
[op
].bitfield
.floatacc
)
5445 as_bad (_("`%s%s' not allowed with `%s%c'"),
5447 i
.op
[op
].regs
->reg_name
,
5457 check_long_reg (void)
5461 for (op
= i
.operands
; --op
>= 0;)
5462 /* Reject eight bit registers, except where the template requires
5463 them. (eg. movzb) */
5464 if (i
.types
[op
].bitfield
.reg8
5465 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5466 || i
.tm
.operand_types
[op
].bitfield
.reg32
5467 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5469 as_bad (_("`%s%s' not allowed with `%s%c'"),
5471 i
.op
[op
].regs
->reg_name
,
5476 /* Warn if the e prefix on a general reg is missing. */
5477 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5478 && i
.types
[op
].bitfield
.reg16
5479 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5480 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5482 /* Prohibit these changes in the 64bit mode, since the
5483 lowering is more complicated. */
5484 if (flag_code
== CODE_64BIT
)
5486 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5487 register_prefix
, i
.op
[op
].regs
->reg_name
,
5491 #if REGISTER_WARNINGS
5492 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5494 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5495 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5498 /* Warn if the r prefix on a general reg is present. */
5499 else if (i
.types
[op
].bitfield
.reg64
5500 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5501 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5504 && i
.tm
.opcode_modifier
.toqword
5505 && !i
.types
[0].bitfield
.regxmm
)
5507 /* Convert to QWORD. We want REX byte. */
5508 i
.suffix
= QWORD_MNEM_SUFFIX
;
5512 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5513 register_prefix
, i
.op
[op
].regs
->reg_name
,
5522 check_qword_reg (void)
5526 for (op
= i
.operands
; --op
>= 0; )
5527 /* Reject eight bit registers, except where the template requires
5528 them. (eg. movzb) */
5529 if (i
.types
[op
].bitfield
.reg8
5530 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5531 || i
.tm
.operand_types
[op
].bitfield
.reg32
5532 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5534 as_bad (_("`%s%s' not allowed with `%s%c'"),
5536 i
.op
[op
].regs
->reg_name
,
5541 /* Warn if the r prefix on a general reg is missing. */
5542 else if ((i
.types
[op
].bitfield
.reg16
5543 || i
.types
[op
].bitfield
.reg32
)
5544 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5545 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5547 /* Prohibit these changes in the 64bit mode, since the
5548 lowering is more complicated. */
5550 && i
.tm
.opcode_modifier
.todword
5551 && !i
.types
[0].bitfield
.regxmm
)
5553 /* Convert to DWORD. We don't want REX byte. */
5554 i
.suffix
= LONG_MNEM_SUFFIX
;
5558 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5559 register_prefix
, i
.op
[op
].regs
->reg_name
,
5568 check_word_reg (void)
5571 for (op
= i
.operands
; --op
>= 0;)
5572 /* Reject eight bit registers, except where the template requires
5573 them. (eg. movzb) */
5574 if (i
.types
[op
].bitfield
.reg8
5575 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5576 || i
.tm
.operand_types
[op
].bitfield
.reg32
5577 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5579 as_bad (_("`%s%s' not allowed with `%s%c'"),
5581 i
.op
[op
].regs
->reg_name
,
5586 /* Warn if the e or r prefix on a general reg is present. */
5587 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5588 && (i
.types
[op
].bitfield
.reg32
5589 || i
.types
[op
].bitfield
.reg64
)
5590 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5591 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5593 /* Prohibit these changes in the 64bit mode, since the
5594 lowering is more complicated. */
5595 if (flag_code
== CODE_64BIT
)
5597 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5598 register_prefix
, i
.op
[op
].regs
->reg_name
,
5602 #if REGISTER_WARNINGS
5603 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5605 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5606 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5613 update_imm (unsigned int j
)
5615 i386_operand_type overlap
= i
.types
[j
];
5616 if ((overlap
.bitfield
.imm8
5617 || overlap
.bitfield
.imm8s
5618 || overlap
.bitfield
.imm16
5619 || overlap
.bitfield
.imm32
5620 || overlap
.bitfield
.imm32s
5621 || overlap
.bitfield
.imm64
)
5622 && !operand_type_equal (&overlap
, &imm8
)
5623 && !operand_type_equal (&overlap
, &imm8s
)
5624 && !operand_type_equal (&overlap
, &imm16
)
5625 && !operand_type_equal (&overlap
, &imm32
)
5626 && !operand_type_equal (&overlap
, &imm32s
)
5627 && !operand_type_equal (&overlap
, &imm64
))
5631 i386_operand_type temp
;
5633 operand_type_set (&temp
, 0);
5634 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5636 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5637 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5639 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5640 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5641 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5643 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5644 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5647 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5650 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5651 || operand_type_equal (&overlap
, &imm16_32
)
5652 || operand_type_equal (&overlap
, &imm16_32s
))
5654 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5659 if (!operand_type_equal (&overlap
, &imm8
)
5660 && !operand_type_equal (&overlap
, &imm8s
)
5661 && !operand_type_equal (&overlap
, &imm16
)
5662 && !operand_type_equal (&overlap
, &imm32
)
5663 && !operand_type_equal (&overlap
, &imm32s
)
5664 && !operand_type_equal (&overlap
, &imm64
))
5666 as_bad (_("no instruction mnemonic suffix given; "
5667 "can't determine immediate size"));
5671 i
.types
[j
] = overlap
;
5681 /* Update the first 2 immediate operands. */
5682 n
= i
.operands
> 2 ? 2 : i
.operands
;
5685 for (j
= 0; j
< n
; j
++)
5686 if (update_imm (j
) == 0)
5689 /* The 3rd operand can't be immediate operand. */
5690 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5697 bad_implicit_operand (int xmm
)
5699 const char *ireg
= xmm
? "xmm0" : "ymm0";
5702 as_bad (_("the last operand of `%s' must be `%s%s'"),
5703 i
.tm
.name
, register_prefix
, ireg
);
5705 as_bad (_("the first operand of `%s' must be `%s%s'"),
5706 i
.tm
.name
, register_prefix
, ireg
);
5711 process_operands (void)
5713 /* Default segment register this instruction will use for memory
5714 accesses. 0 means unknown. This is only for optimizing out
5715 unnecessary segment overrides. */
5716 const seg_entry
*default_seg
= 0;
5718 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5720 unsigned int dupl
= i
.operands
;
5721 unsigned int dest
= dupl
- 1;
5724 /* The destination must be an xmm register. */
5725 gas_assert (i
.reg_operands
5726 && MAX_OPERANDS
> dupl
5727 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5729 if (i
.tm
.opcode_modifier
.firstxmm0
)
5731 /* The first operand is implicit and must be xmm0. */
5732 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5733 if (register_number (i
.op
[0].regs
) != 0)
5734 return bad_implicit_operand (1);
5736 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5738 /* Keep xmm0 for instructions with VEX prefix and 3
5744 /* We remove the first xmm0 and keep the number of
5745 operands unchanged, which in fact duplicates the
5747 for (j
= 1; j
< i
.operands
; j
++)
5749 i
.op
[j
- 1] = i
.op
[j
];
5750 i
.types
[j
- 1] = i
.types
[j
];
5751 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5755 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5757 gas_assert ((MAX_OPERANDS
- 1) > dupl
5758 && (i
.tm
.opcode_modifier
.vexsources
5761 /* Add the implicit xmm0 for instructions with VEX prefix
5763 for (j
= i
.operands
; j
> 0; j
--)
5765 i
.op
[j
] = i
.op
[j
- 1];
5766 i
.types
[j
] = i
.types
[j
- 1];
5767 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5770 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5771 i
.types
[0] = regxmm
;
5772 i
.tm
.operand_types
[0] = regxmm
;
5775 i
.reg_operands
+= 2;
5780 i
.op
[dupl
] = i
.op
[dest
];
5781 i
.types
[dupl
] = i
.types
[dest
];
5782 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5791 i
.op
[dupl
] = i
.op
[dest
];
5792 i
.types
[dupl
] = i
.types
[dest
];
5793 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5796 if (i
.tm
.opcode_modifier
.immext
)
5799 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5803 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5804 gas_assert (i
.reg_operands
5805 && (operand_type_equal (&i
.types
[0], ®xmm
)
5806 || operand_type_equal (&i
.types
[0], ®ymm
)
5807 || operand_type_equal (&i
.types
[0], ®zmm
)));
5808 if (register_number (i
.op
[0].regs
) != 0)
5809 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5811 for (j
= 1; j
< i
.operands
; j
++)
5813 i
.op
[j
- 1] = i
.op
[j
];
5814 i
.types
[j
- 1] = i
.types
[j
];
5816 /* We need to adjust fields in i.tm since they are used by
5817 build_modrm_byte. */
5818 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5825 else if (i
.tm
.opcode_modifier
.regkludge
)
5827 /* The imul $imm, %reg instruction is converted into
5828 imul $imm, %reg, %reg, and the clr %reg instruction
5829 is converted into xor %reg, %reg. */
5831 unsigned int first_reg_op
;
5833 if (operand_type_check (i
.types
[0], reg
))
5837 /* Pretend we saw the extra register operand. */
5838 gas_assert (i
.reg_operands
== 1
5839 && i
.op
[first_reg_op
+ 1].regs
== 0);
5840 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5841 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5846 if (i
.tm
.opcode_modifier
.shortform
)
5848 if (i
.types
[0].bitfield
.sreg2
5849 || i
.types
[0].bitfield
.sreg3
)
5851 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5852 && i
.op
[0].regs
->reg_num
== 1)
5854 as_bad (_("you can't `pop %scs'"), register_prefix
);
5857 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5858 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5863 /* The register or float register operand is in operand
5867 if (i
.types
[0].bitfield
.floatreg
5868 || operand_type_check (i
.types
[0], reg
))
5872 /* Register goes in low 3 bits of opcode. */
5873 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5874 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5876 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5878 /* Warn about some common errors, but press on regardless.
5879 The first case can be generated by gcc (<= 2.8.1). */
5880 if (i
.operands
== 2)
5882 /* Reversed arguments on faddp, fsubp, etc. */
5883 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5884 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5885 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5889 /* Extraneous `l' suffix on fp insn. */
5890 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5891 register_prefix
, i
.op
[0].regs
->reg_name
);
5896 else if (i
.tm
.opcode_modifier
.modrm
)
5898 /* The opcode is completed (modulo i.tm.extension_opcode which
5899 must be put into the modrm byte). Now, we make the modrm and
5900 index base bytes based on all the info we've collected. */
5902 default_seg
= build_modrm_byte ();
5904 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5908 else if (i
.tm
.opcode_modifier
.isstring
)
5910 /* For the string instructions that allow a segment override
5911 on one of their operands, the default segment is ds. */
5915 if (i
.tm
.base_opcode
== 0x8d /* lea */
5918 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5920 /* If a segment was explicitly specified, and the specified segment
5921 is not the default, use an opcode prefix to select it. If we
5922 never figured out what the default segment is, then default_seg
5923 will be zero at this point, and the specified segment prefix will
5925 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5927 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5933 static const seg_entry
*
5934 build_modrm_byte (void)
5936 const seg_entry
*default_seg
= 0;
5937 unsigned int source
, dest
;
5940 /* The first operand of instructions with VEX prefix and 3 sources
5941 must be VEX_Imm4. */
5942 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5945 unsigned int nds
, reg_slot
;
5948 if (i
.tm
.opcode_modifier
.veximmext
5949 && i
.tm
.opcode_modifier
.immext
)
5951 dest
= i
.operands
- 2;
5952 gas_assert (dest
== 3);
5955 dest
= i
.operands
- 1;
5958 /* There are 2 kinds of instructions:
5959 1. 5 operands: 4 register operands or 3 register operands
5960 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5961 VexW0 or VexW1. The destination must be either XMM, YMM or
5963 2. 4 operands: 4 register operands or 3 register operands
5964 plus 1 memory operand, VexXDS, and VexImmExt */
5965 gas_assert ((i
.reg_operands
== 4
5966 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5967 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5968 && (i
.tm
.opcode_modifier
.veximmext
5969 || (i
.imm_operands
== 1
5970 && i
.types
[0].bitfield
.vec_imm4
5971 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5972 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5973 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5974 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5975 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5977 if (i
.imm_operands
== 0)
5979 /* When there is no immediate operand, generate an 8bit
5980 immediate operand to encode the first operand. */
5981 exp
= &im_expressions
[i
.imm_operands
++];
5982 i
.op
[i
.operands
].imms
= exp
;
5983 i
.types
[i
.operands
] = imm8
;
5985 /* If VexW1 is set, the first operand is the source and
5986 the second operand is encoded in the immediate operand. */
5987 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5998 /* FMA swaps REG and NDS. */
5999 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6007 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6009 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6011 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6013 exp
->X_op
= O_constant
;
6014 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6015 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6019 unsigned int imm_slot
;
6021 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6023 /* If VexW0 is set, the third operand is the source and
6024 the second operand is encoded in the immediate
6031 /* VexW1 is set, the second operand is the source and
6032 the third operand is encoded in the immediate
6038 if (i
.tm
.opcode_modifier
.immext
)
6040 /* When ImmExt is set, the immdiate byte is the last
6042 imm_slot
= i
.operands
- 1;
6050 /* Turn on Imm8 so that output_imm will generate it. */
6051 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6054 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6056 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6058 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6060 i
.op
[imm_slot
].imms
->X_add_number
6061 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6062 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6065 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6066 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6068 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6070 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6075 /* i.reg_operands MUST be the number of real register operands;
6076 implicit registers do not count. If there are 3 register
6077 operands, it must be a instruction with VexNDS. For a
6078 instruction with VexNDD, the destination register is encoded
6079 in VEX prefix. If there are 4 register operands, it must be
6080 a instruction with VEX prefix and 3 sources. */
6081 if (i
.mem_operands
== 0
6082 && ((i
.reg_operands
== 2
6083 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6084 || (i
.reg_operands
== 3
6085 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6086 || (i
.reg_operands
== 4 && vex_3_sources
)))
6094 /* When there are 3 operands, one of them may be immediate,
6095 which may be the first or the last operand. Otherwise,
6096 the first operand must be shift count register (cl) or it
6097 is an instruction with VexNDS. */
6098 gas_assert (i
.imm_operands
== 1
6099 || (i
.imm_operands
== 0
6100 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6101 || i
.types
[0].bitfield
.shiftcount
)));
6102 if (operand_type_check (i
.types
[0], imm
)
6103 || i
.types
[0].bitfield
.shiftcount
)
6109 /* When there are 4 operands, the first two must be 8bit
6110 immediate operands. The source operand will be the 3rd
6113 For instructions with VexNDS, if the first operand
6114 an imm8, the source operand is the 2nd one. If the last
6115 operand is imm8, the source operand is the first one. */
6116 gas_assert ((i
.imm_operands
== 2
6117 && i
.types
[0].bitfield
.imm8
6118 && i
.types
[1].bitfield
.imm8
)
6119 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6120 && i
.imm_operands
== 1
6121 && (i
.types
[0].bitfield
.imm8
6122 || i
.types
[i
.operands
- 1].bitfield
.imm8
6124 if (i
.imm_operands
== 2)
6128 if (i
.types
[0].bitfield
.imm8
)
6135 if (i
.tm
.opcode_modifier
.evex
)
6137 /* For EVEX instructions, when there are 5 operands, the
6138 first one must be immediate operand. If the second one
6139 is immediate operand, the source operand is the 3th
6140 one. If the last one is immediate operand, the source
6141 operand is the 2nd one. */
6142 gas_assert (i
.imm_operands
== 2
6143 && i
.tm
.opcode_modifier
.sae
6144 && operand_type_check (i
.types
[0], imm
));
6145 if (operand_type_check (i
.types
[1], imm
))
6147 else if (operand_type_check (i
.types
[4], imm
))
6161 /* RC/SAE operand could be between DEST and SRC. That happens
6162 when one operand is GPR and the other one is XMM/YMM/ZMM
6164 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6167 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6169 /* For instructions with VexNDS, the register-only source
6170 operand must be 32/64bit integer, XMM, YMM or ZMM
6171 register. It is encoded in VEX prefix. We need to
6172 clear RegMem bit before calling operand_type_equal. */
6174 i386_operand_type op
;
6177 /* Check register-only source operand when two source
6178 operands are swapped. */
6179 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6180 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6188 op
= i
.tm
.operand_types
[vvvv
];
6189 op
.bitfield
.regmem
= 0;
6190 if ((dest
+ 1) >= i
.operands
6191 || (!op
.bitfield
.reg32
6192 && op
.bitfield
.reg64
6193 && !operand_type_equal (&op
, ®xmm
)
6194 && !operand_type_equal (&op
, ®ymm
)
6195 && !operand_type_equal (&op
, ®zmm
)
6196 && !operand_type_equal (&op
, ®mask
)))
6198 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6204 /* One of the register operands will be encoded in the i.tm.reg
6205 field, the other in the combined i.tm.mode and i.tm.regmem
6206 fields. If no form of this instruction supports a memory
6207 destination operand, then we assume the source operand may
6208 sometimes be a memory operand and so we need to store the
6209 destination in the i.rm.reg field. */
6210 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6211 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6213 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6214 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6215 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6217 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6219 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6221 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6226 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6227 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6228 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6230 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6232 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6234 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6237 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6239 if (!i
.types
[0].bitfield
.control
6240 && !i
.types
[1].bitfield
.control
)
6242 i
.rex
&= ~(REX_R
| REX_B
);
6243 add_prefix (LOCK_PREFIX_OPCODE
);
6247 { /* If it's not 2 reg operands... */
6252 unsigned int fake_zero_displacement
= 0;
6255 for (op
= 0; op
< i
.operands
; op
++)
6256 if (operand_type_check (i
.types
[op
], anymem
))
6258 gas_assert (op
< i
.operands
);
6260 if (i
.tm
.opcode_modifier
.vecsib
)
6262 if (i
.index_reg
->reg_num
== RegEiz
6263 || i
.index_reg
->reg_num
== RegRiz
)
6266 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6269 i
.sib
.base
= NO_BASE_REGISTER
;
6270 i
.sib
.scale
= i
.log2_scale_factor
;
6271 /* No Vec_Disp8 if there is no base. */
6272 i
.types
[op
].bitfield
.vec_disp8
= 0;
6273 i
.types
[op
].bitfield
.disp8
= 0;
6274 i
.types
[op
].bitfield
.disp16
= 0;
6275 i
.types
[op
].bitfield
.disp64
= 0;
6276 if (flag_code
!= CODE_64BIT
)
6278 /* Must be 32 bit */
6279 i
.types
[op
].bitfield
.disp32
= 1;
6280 i
.types
[op
].bitfield
.disp32s
= 0;
6284 i
.types
[op
].bitfield
.disp32
= 0;
6285 i
.types
[op
].bitfield
.disp32s
= 1;
6288 i
.sib
.index
= i
.index_reg
->reg_num
;
6289 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6291 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6297 if (i
.base_reg
== 0)
6300 if (!i
.disp_operands
)
6302 fake_zero_displacement
= 1;
6303 /* Instructions with VSIB byte need 32bit displacement
6304 if there is no base register. */
6305 if (i
.tm
.opcode_modifier
.vecsib
)
6306 i
.types
[op
].bitfield
.disp32
= 1;
6308 if (i
.index_reg
== 0)
6310 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6311 /* Operand is just <disp> */
6312 if (flag_code
== CODE_64BIT
)
6314 /* 64bit mode overwrites the 32bit absolute
6315 addressing by RIP relative addressing and
6316 absolute addressing is encoded by one of the
6317 redundant SIB forms. */
6318 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6319 i
.sib
.base
= NO_BASE_REGISTER
;
6320 i
.sib
.index
= NO_INDEX_REGISTER
;
6321 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6322 ? disp32s
: disp32
);
6324 else if ((flag_code
== CODE_16BIT
)
6325 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6327 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6328 i
.types
[op
] = disp16
;
6332 i
.rm
.regmem
= NO_BASE_REGISTER
;
6333 i
.types
[op
] = disp32
;
6336 else if (!i
.tm
.opcode_modifier
.vecsib
)
6338 /* !i.base_reg && i.index_reg */
6339 if (i
.index_reg
->reg_num
== RegEiz
6340 || i
.index_reg
->reg_num
== RegRiz
)
6341 i
.sib
.index
= NO_INDEX_REGISTER
;
6343 i
.sib
.index
= i
.index_reg
->reg_num
;
6344 i
.sib
.base
= NO_BASE_REGISTER
;
6345 i
.sib
.scale
= i
.log2_scale_factor
;
6346 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6347 /* No Vec_Disp8 if there is no base. */
6348 i
.types
[op
].bitfield
.vec_disp8
= 0;
6349 i
.types
[op
].bitfield
.disp8
= 0;
6350 i
.types
[op
].bitfield
.disp16
= 0;
6351 i
.types
[op
].bitfield
.disp64
= 0;
6352 if (flag_code
!= CODE_64BIT
)
6354 /* Must be 32 bit */
6355 i
.types
[op
].bitfield
.disp32
= 1;
6356 i
.types
[op
].bitfield
.disp32s
= 0;
6360 i
.types
[op
].bitfield
.disp32
= 0;
6361 i
.types
[op
].bitfield
.disp32s
= 1;
6363 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6367 /* RIP addressing for 64bit mode. */
6368 else if (i
.base_reg
->reg_num
== RegRip
||
6369 i
.base_reg
->reg_num
== RegEip
)
6371 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6372 i
.rm
.regmem
= NO_BASE_REGISTER
;
6373 i
.types
[op
].bitfield
.disp8
= 0;
6374 i
.types
[op
].bitfield
.disp16
= 0;
6375 i
.types
[op
].bitfield
.disp32
= 0;
6376 i
.types
[op
].bitfield
.disp32s
= 1;
6377 i
.types
[op
].bitfield
.disp64
= 0;
6378 i
.types
[op
].bitfield
.vec_disp8
= 0;
6379 i
.flags
[op
] |= Operand_PCrel
;
6380 if (! i
.disp_operands
)
6381 fake_zero_displacement
= 1;
6383 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6385 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6386 switch (i
.base_reg
->reg_num
)
6389 if (i
.index_reg
== 0)
6391 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6392 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6396 if (i
.index_reg
== 0)
6399 if (operand_type_check (i
.types
[op
], disp
) == 0)
6401 /* fake (%bp) into 0(%bp) */
6402 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6403 i
.types
[op
].bitfield
.vec_disp8
= 1;
6405 i
.types
[op
].bitfield
.disp8
= 1;
6406 fake_zero_displacement
= 1;
6409 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6410 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6412 default: /* (%si) -> 4 or (%di) -> 5 */
6413 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6415 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6417 else /* i.base_reg and 32/64 bit mode */
6419 if (flag_code
== CODE_64BIT
6420 && operand_type_check (i
.types
[op
], disp
))
6422 i386_operand_type temp
;
6423 operand_type_set (&temp
, 0);
6424 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6425 temp
.bitfield
.vec_disp8
6426 = i
.types
[op
].bitfield
.vec_disp8
;
6428 if (i
.prefix
[ADDR_PREFIX
] == 0)
6429 i
.types
[op
].bitfield
.disp32s
= 1;
6431 i
.types
[op
].bitfield
.disp32
= 1;
6434 if (!i
.tm
.opcode_modifier
.vecsib
)
6435 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6436 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6438 i
.sib
.base
= i
.base_reg
->reg_num
;
6439 /* x86-64 ignores REX prefix bit here to avoid decoder
6441 if (!(i
.base_reg
->reg_flags
& RegRex
)
6442 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6443 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6445 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6447 fake_zero_displacement
= 1;
6448 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6449 i
.types
[op
].bitfield
.vec_disp8
= 1;
6451 i
.types
[op
].bitfield
.disp8
= 1;
6453 i
.sib
.scale
= i
.log2_scale_factor
;
6454 if (i
.index_reg
== 0)
6456 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6457 /* <disp>(%esp) becomes two byte modrm with no index
6458 register. We've already stored the code for esp
6459 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6460 Any base register besides %esp will not use the
6461 extra modrm byte. */
6462 i
.sib
.index
= NO_INDEX_REGISTER
;
6464 else if (!i
.tm
.opcode_modifier
.vecsib
)
6466 if (i
.index_reg
->reg_num
== RegEiz
6467 || i
.index_reg
->reg_num
== RegRiz
)
6468 i
.sib
.index
= NO_INDEX_REGISTER
;
6470 i
.sib
.index
= i
.index_reg
->reg_num
;
6471 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6472 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6477 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6478 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6482 if (!fake_zero_displacement
6486 fake_zero_displacement
= 1;
6487 if (i
.disp_encoding
== disp_encoding_8bit
)
6488 i
.types
[op
].bitfield
.disp8
= 1;
6490 i
.types
[op
].bitfield
.disp32
= 1;
6492 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6496 if (fake_zero_displacement
)
6498 /* Fakes a zero displacement assuming that i.types[op]
6499 holds the correct displacement size. */
6502 gas_assert (i
.op
[op
].disps
== 0);
6503 exp
= &disp_expressions
[i
.disp_operands
++];
6504 i
.op
[op
].disps
= exp
;
6505 exp
->X_op
= O_constant
;
6506 exp
->X_add_number
= 0;
6507 exp
->X_add_symbol
= (symbolS
*) 0;
6508 exp
->X_op_symbol
= (symbolS
*) 0;
6516 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6518 if (operand_type_check (i
.types
[0], imm
))
6519 i
.vex
.register_specifier
= NULL
;
6522 /* VEX.vvvv encodes one of the sources when the first
6523 operand is not an immediate. */
6524 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6525 i
.vex
.register_specifier
= i
.op
[0].regs
;
6527 i
.vex
.register_specifier
= i
.op
[1].regs
;
6530 /* Destination is a XMM register encoded in the ModRM.reg
6532 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6533 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6536 /* ModRM.rm and VEX.B encodes the other source. */
6537 if (!i
.mem_operands
)
6541 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6542 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6544 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6546 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6550 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6552 i
.vex
.register_specifier
= i
.op
[2].regs
;
6553 if (!i
.mem_operands
)
6556 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6557 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6561 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6562 (if any) based on i.tm.extension_opcode. Again, we must be
6563 careful to make sure that segment/control/debug/test/MMX
6564 registers are coded into the i.rm.reg field. */
6565 else if (i
.reg_operands
)
6568 unsigned int vex_reg
= ~0;
6570 for (op
= 0; op
< i
.operands
; op
++)
6571 if (i
.types
[op
].bitfield
.reg8
6572 || i
.types
[op
].bitfield
.reg16
6573 || i
.types
[op
].bitfield
.reg32
6574 || i
.types
[op
].bitfield
.reg64
6575 || i
.types
[op
].bitfield
.regmmx
6576 || i
.types
[op
].bitfield
.regxmm
6577 || i
.types
[op
].bitfield
.regymm
6578 || i
.types
[op
].bitfield
.regbnd
6579 || i
.types
[op
].bitfield
.regzmm
6580 || i
.types
[op
].bitfield
.regmask
6581 || i
.types
[op
].bitfield
.sreg2
6582 || i
.types
[op
].bitfield
.sreg3
6583 || i
.types
[op
].bitfield
.control
6584 || i
.types
[op
].bitfield
.debug
6585 || i
.types
[op
].bitfield
.test
)
6590 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6592 /* For instructions with VexNDS, the register-only
6593 source operand is encoded in VEX prefix. */
6594 gas_assert (mem
!= (unsigned int) ~0);
6599 gas_assert (op
< i
.operands
);
6603 /* Check register-only source operand when two source
6604 operands are swapped. */
6605 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6606 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6610 gas_assert (mem
== (vex_reg
+ 1)
6611 && op
< i
.operands
);
6616 gas_assert (vex_reg
< i
.operands
);
6620 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6622 /* For instructions with VexNDD, the register destination
6623 is encoded in VEX prefix. */
6624 if (i
.mem_operands
== 0)
6626 /* There is no memory operand. */
6627 gas_assert ((op
+ 2) == i
.operands
);
6632 /* There are only 2 operands. */
6633 gas_assert (op
< 2 && i
.operands
== 2);
6638 gas_assert (op
< i
.operands
);
6640 if (vex_reg
!= (unsigned int) ~0)
6642 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6644 if (type
->bitfield
.reg32
!= 1
6645 && type
->bitfield
.reg64
!= 1
6646 && !operand_type_equal (type
, ®xmm
)
6647 && !operand_type_equal (type
, ®ymm
)
6648 && !operand_type_equal (type
, ®zmm
)
6649 && !operand_type_equal (type
, ®mask
))
6652 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6655 /* Don't set OP operand twice. */
6658 /* If there is an extension opcode to put here, the
6659 register number must be put into the regmem field. */
6660 if (i
.tm
.extension_opcode
!= None
)
6662 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6663 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6665 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6670 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6671 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6673 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6678 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6679 must set it to 3 to indicate this is a register operand
6680 in the regmem field. */
6681 if (!i
.mem_operands
)
6685 /* Fill in i.rm.reg field with extension opcode (if any). */
6686 if (i
.tm
.extension_opcode
!= None
)
6687 i
.rm
.reg
= i
.tm
.extension_opcode
;
6693 output_branch (void)
6699 relax_substateT subtype
;
6703 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6704 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6707 if (i
.prefix
[DATA_PREFIX
] != 0)
6713 /* Pentium4 branch hints. */
6714 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6715 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6720 if (i
.prefix
[REX_PREFIX
] != 0)
6726 /* BND prefixed jump. */
6727 if (i
.prefix
[BND_PREFIX
] != 0)
6729 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6733 if (i
.prefixes
!= 0 && !intel_syntax
)
6734 as_warn (_("skipping prefixes on this instruction"));
6736 /* It's always a symbol; End frag & setup for relax.
6737 Make sure there is enough room in this frag for the largest
6738 instruction we may generate in md_convert_frag. This is 2
6739 bytes for the opcode and room for the prefix and largest
6741 frag_grow (prefix
+ 2 + 4);
6742 /* Prefix and 1 opcode byte go in fr_fix. */
6743 p
= frag_more (prefix
+ 1);
6744 if (i
.prefix
[DATA_PREFIX
] != 0)
6745 *p
++ = DATA_PREFIX_OPCODE
;
6746 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6747 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6748 *p
++ = i
.prefix
[SEG_PREFIX
];
6749 if (i
.prefix
[REX_PREFIX
] != 0)
6750 *p
++ = i
.prefix
[REX_PREFIX
];
6751 *p
= i
.tm
.base_opcode
;
6753 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6754 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6755 else if (cpu_arch_flags
.bitfield
.cpui386
)
6756 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6758 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6761 sym
= i
.op
[0].disps
->X_add_symbol
;
6762 off
= i
.op
[0].disps
->X_add_number
;
6764 if (i
.op
[0].disps
->X_op
!= O_constant
6765 && i
.op
[0].disps
->X_op
!= O_symbol
)
6767 /* Handle complex expressions. */
6768 sym
= make_expr_symbol (i
.op
[0].disps
);
6772 /* 1 possible extra opcode + 4 byte displacement go in var part.
6773 Pass reloc in fr_var. */
6774 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6784 if (i
.tm
.opcode_modifier
.jumpbyte
)
6786 /* This is a loop or jecxz type instruction. */
6788 if (i
.prefix
[ADDR_PREFIX
] != 0)
6790 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6793 /* Pentium4 branch hints. */
6794 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6795 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6797 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6806 if (flag_code
== CODE_16BIT
)
6809 if (i
.prefix
[DATA_PREFIX
] != 0)
6811 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6821 if (i
.prefix
[REX_PREFIX
] != 0)
6823 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6827 /* BND prefixed jump. */
6828 if (i
.prefix
[BND_PREFIX
] != 0)
6830 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6834 if (i
.prefixes
!= 0 && !intel_syntax
)
6835 as_warn (_("skipping prefixes on this instruction"));
6837 p
= frag_more (i
.tm
.opcode_length
+ size
);
6838 switch (i
.tm
.opcode_length
)
6841 *p
++ = i
.tm
.base_opcode
>> 8;
6843 *p
++ = i
.tm
.base_opcode
;
6849 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6850 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6852 /* All jumps handled here are signed, but don't use a signed limit
6853 check for 32 and 16 bit jumps as we want to allow wrap around at
6854 4G and 64k respectively. */
6856 fixP
->fx_signed
= 1;
6860 output_interseg_jump (void)
6868 if (flag_code
== CODE_16BIT
)
6872 if (i
.prefix
[DATA_PREFIX
] != 0)
6878 if (i
.prefix
[REX_PREFIX
] != 0)
6888 if (i
.prefixes
!= 0 && !intel_syntax
)
6889 as_warn (_("skipping prefixes on this instruction"));
6891 /* 1 opcode; 2 segment; offset */
6892 p
= frag_more (prefix
+ 1 + 2 + size
);
6894 if (i
.prefix
[DATA_PREFIX
] != 0)
6895 *p
++ = DATA_PREFIX_OPCODE
;
6897 if (i
.prefix
[REX_PREFIX
] != 0)
6898 *p
++ = i
.prefix
[REX_PREFIX
];
6900 *p
++ = i
.tm
.base_opcode
;
6901 if (i
.op
[1].imms
->X_op
== O_constant
)
6903 offsetT n
= i
.op
[1].imms
->X_add_number
;
6906 && !fits_in_unsigned_word (n
)
6907 && !fits_in_signed_word (n
))
6909 as_bad (_("16-bit jump out of range"));
6912 md_number_to_chars (p
, n
, size
);
6915 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6916 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6917 if (i
.op
[0].imms
->X_op
!= O_constant
)
6918 as_bad (_("can't handle non absolute segment in `%s'"),
6920 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6926 fragS
*insn_start_frag
;
6927 offsetT insn_start_off
;
6929 /* Tie dwarf2 debug info to the address at the start of the insn.
6930 We can't do this after the insn has been output as the current
6931 frag may have been closed off. eg. by frag_var. */
6932 dwarf2_emit_insn (0);
6934 insn_start_frag
= frag_now
;
6935 insn_start_off
= frag_now_fix ();
6938 if (i
.tm
.opcode_modifier
.jump
)
6940 else if (i
.tm
.opcode_modifier
.jumpbyte
6941 || i
.tm
.opcode_modifier
.jumpdword
)
6943 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6944 output_interseg_jump ();
6947 /* Output normal instructions here. */
6951 unsigned int prefix
;
6953 /* Some processors fail on LOCK prefix. This options makes
6954 assembler ignore LOCK prefix and serves as a workaround. */
6955 if (omit_lock_prefix
)
6957 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6959 i
.prefix
[LOCK_PREFIX
] = 0;
6962 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6963 don't need the explicit prefix. */
6964 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6966 switch (i
.tm
.opcode_length
)
6969 if (i
.tm
.base_opcode
& 0xff000000)
6971 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6976 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6978 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6979 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6982 if (prefix
!= REPE_PREFIX_OPCODE
6983 || (i
.prefix
[REP_PREFIX
]
6984 != REPE_PREFIX_OPCODE
))
6985 add_prefix (prefix
);
6988 add_prefix (prefix
);
6997 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6998 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6999 R_X86_64_GOTTPOFF relocation so that linker can safely
7000 perform IE->LE optimization. */
7001 if (x86_elf_abi
== X86_64_X32_ABI
7003 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7004 && i
.prefix
[REX_PREFIX
] == 0)
7005 add_prefix (REX_OPCODE
);
7008 /* The prefix bytes. */
7009 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7011 FRAG_APPEND_1_CHAR (*q
);
7015 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7020 /* REX byte is encoded in VEX prefix. */
7024 FRAG_APPEND_1_CHAR (*q
);
7027 /* There should be no other prefixes for instructions
7032 /* For EVEX instructions i.vrex should become 0 after
7033 build_evex_prefix. For VEX instructions upper 16 registers
7034 aren't available, so VREX should be 0. */
7037 /* Now the VEX prefix. */
7038 p
= frag_more (i
.vex
.length
);
7039 for (j
= 0; j
< i
.vex
.length
; j
++)
7040 p
[j
] = i
.vex
.bytes
[j
];
7043 /* Now the opcode; be careful about word order here! */
7044 if (i
.tm
.opcode_length
== 1)
7046 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7050 switch (i
.tm
.opcode_length
)
7054 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7055 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7059 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7069 /* Put out high byte first: can't use md_number_to_chars! */
7070 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7071 *p
= i
.tm
.base_opcode
& 0xff;
7074 /* Now the modrm byte and sib byte (if present). */
7075 if (i
.tm
.opcode_modifier
.modrm
)
7077 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7080 /* If i.rm.regmem == ESP (4)
7081 && i.rm.mode != (Register mode)
7083 ==> need second modrm byte. */
7084 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7086 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7087 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7089 | i
.sib
.scale
<< 6));
7092 if (i
.disp_operands
)
7093 output_disp (insn_start_frag
, insn_start_off
);
7096 output_imm (insn_start_frag
, insn_start_off
);
7102 pi ("" /*line*/, &i
);
7104 #endif /* DEBUG386 */
7107 /* Return the size of the displacement operand N. */
7110 disp_size (unsigned int n
)
7114 /* Vec_Disp8 has to be 8bit. */
7115 if (i
.types
[n
].bitfield
.vec_disp8
)
7117 else if (i
.types
[n
].bitfield
.disp64
)
7119 else if (i
.types
[n
].bitfield
.disp8
)
7121 else if (i
.types
[n
].bitfield
.disp16
)
7126 /* Return the size of the immediate operand N. */
7129 imm_size (unsigned int n
)
7132 if (i
.types
[n
].bitfield
.imm64
)
7134 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7136 else if (i
.types
[n
].bitfield
.imm16
)
7142 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7147 for (n
= 0; n
< i
.operands
; n
++)
7149 if (i
.types
[n
].bitfield
.vec_disp8
7150 || operand_type_check (i
.types
[n
], disp
))
7152 if (i
.op
[n
].disps
->X_op
== O_constant
)
7154 int size
= disp_size (n
);
7155 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7157 if (i
.types
[n
].bitfield
.vec_disp8
)
7159 val
= offset_in_range (val
, size
);
7160 p
= frag_more (size
);
7161 md_number_to_chars (p
, val
, size
);
7165 enum bfd_reloc_code_real reloc_type
;
7166 int size
= disp_size (n
);
7167 int sign
= i
.types
[n
].bitfield
.disp32s
;
7168 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7171 /* We can't have 8 bit displacement here. */
7172 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7174 /* The PC relative address is computed relative
7175 to the instruction boundary, so in case immediate
7176 fields follows, we need to adjust the value. */
7177 if (pcrel
&& i
.imm_operands
)
7182 for (n1
= 0; n1
< i
.operands
; n1
++)
7183 if (operand_type_check (i
.types
[n1
], imm
))
7185 /* Only one immediate is allowed for PC
7186 relative address. */
7187 gas_assert (sz
== 0);
7189 i
.op
[n
].disps
->X_add_number
-= sz
;
7191 /* We should find the immediate. */
7192 gas_assert (sz
!= 0);
7195 p
= frag_more (size
);
7196 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7198 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7199 && (((reloc_type
== BFD_RELOC_32
7200 || reloc_type
== BFD_RELOC_X86_64_32S
7201 || (reloc_type
== BFD_RELOC_64
7203 && (i
.op
[n
].disps
->X_op
== O_symbol
7204 || (i
.op
[n
].disps
->X_op
== O_add
7205 && ((symbol_get_value_expression
7206 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7208 || reloc_type
== BFD_RELOC_32_PCREL
))
7212 if (insn_start_frag
== frag_now
)
7213 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7218 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7219 for (fr
= insn_start_frag
->fr_next
;
7220 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7222 add
+= p
- frag_now
->fr_literal
;
7227 reloc_type
= BFD_RELOC_386_GOTPC
;
7228 i
.op
[n
].imms
->X_add_number
+= add
;
7230 else if (reloc_type
== BFD_RELOC_64
)
7231 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7233 /* Don't do the adjustment for x86-64, as there
7234 the pcrel addressing is relative to the _next_
7235 insn, and that is taken care of in other code. */
7236 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7238 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7239 size
, i
.op
[n
].disps
, pcrel
,
7241 /* Check for "call/jmp *mem", "mov mem, %reg",
7242 "test %reg, mem" and "binop mem, %reg" where binop
7243 is one of adc, add, and, cmp, or, sbb, sub, xor
7246 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7247 && ((i
.operands
== 1
7248 && i
.tm
.base_opcode
== 0xff
7249 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7251 && (i
.tm
.base_opcode
== 0x8b
7252 || i
.tm
.base_opcode
== 0x85
7253 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7257 fixP
->fx_tcbit
= i
.rex
!= 0;
7259 && (i
.base_reg
->reg_num
== RegRip
7260 || i
.base_reg
->reg_num
== RegEip
))
7261 fixP
->fx_tcbit2
= 1;
7264 fixP
->fx_tcbit2
= 1;
7272 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7277 for (n
= 0; n
< i
.operands
; n
++)
7279 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7280 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7283 if (operand_type_check (i
.types
[n
], imm
))
7285 if (i
.op
[n
].imms
->X_op
== O_constant
)
7287 int size
= imm_size (n
);
7290 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7292 p
= frag_more (size
);
7293 md_number_to_chars (p
, val
, size
);
7297 /* Not absolute_section.
7298 Need a 32-bit fixup (don't support 8bit
7299 non-absolute imms). Try to support other
7301 enum bfd_reloc_code_real reloc_type
;
7302 int size
= imm_size (n
);
7305 if (i
.types
[n
].bitfield
.imm32s
7306 && (i
.suffix
== QWORD_MNEM_SUFFIX
7307 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7312 p
= frag_more (size
);
7313 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7315 /* This is tough to explain. We end up with this one if we
7316 * have operands that look like
7317 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7318 * obtain the absolute address of the GOT, and it is strongly
7319 * preferable from a performance point of view to avoid using
7320 * a runtime relocation for this. The actual sequence of
7321 * instructions often look something like:
7326 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7328 * The call and pop essentially return the absolute address
7329 * of the label .L66 and store it in %ebx. The linker itself
7330 * will ultimately change the first operand of the addl so
7331 * that %ebx points to the GOT, but to keep things simple, the
7332 * .o file must have this operand set so that it generates not
7333 * the absolute address of .L66, but the absolute address of
7334 * itself. This allows the linker itself simply treat a GOTPC
7335 * relocation as asking for a pcrel offset to the GOT to be
7336 * added in, and the addend of the relocation is stored in the
7337 * operand field for the instruction itself.
7339 * Our job here is to fix the operand so that it would add
7340 * the correct offset so that %ebx would point to itself. The
7341 * thing that is tricky is that .-.L66 will point to the
7342 * beginning of the instruction, so we need to further modify
7343 * the operand so that it will point to itself. There are
7344 * other cases where you have something like:
7346 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7348 * and here no correction would be required. Internally in
7349 * the assembler we treat operands of this form as not being
7350 * pcrel since the '.' is explicitly mentioned, and I wonder
7351 * whether it would simplify matters to do it this way. Who
7352 * knows. In earlier versions of the PIC patches, the
7353 * pcrel_adjust field was used to store the correction, but
7354 * since the expression is not pcrel, I felt it would be
7355 * confusing to do it this way. */
7357 if ((reloc_type
== BFD_RELOC_32
7358 || reloc_type
== BFD_RELOC_X86_64_32S
7359 || reloc_type
== BFD_RELOC_64
)
7361 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7362 && (i
.op
[n
].imms
->X_op
== O_symbol
7363 || (i
.op
[n
].imms
->X_op
== O_add
7364 && ((symbol_get_value_expression
7365 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7370 if (insn_start_frag
== frag_now
)
7371 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7376 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7377 for (fr
= insn_start_frag
->fr_next
;
7378 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7380 add
+= p
- frag_now
->fr_literal
;
7384 reloc_type
= BFD_RELOC_386_GOTPC
;
7386 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7388 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7389 i
.op
[n
].imms
->X_add_number
+= add
;
7391 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7392 i
.op
[n
].imms
, 0, reloc_type
);
7398 /* x86_cons_fix_new is called via the expression parsing code when a
7399 reloc is needed. We use this hook to get the correct .got reloc. */
7400 static int cons_sign
= -1;
7403 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7404 expressionS
*exp
, bfd_reloc_code_real_type r
)
7406 r
= reloc (len
, 0, cons_sign
, r
);
7409 if (exp
->X_op
== O_secrel
)
7411 exp
->X_op
= O_symbol
;
7412 r
= BFD_RELOC_32_SECREL
;
7416 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7419 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7420 purpose of the `.dc.a' internal pseudo-op. */
7423 x86_address_bytes (void)
7425 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7427 return stdoutput
->arch_info
->bits_per_address
/ 8;
7430 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7432 # define lex_got(reloc, adjust, types) NULL
7434 /* Parse operands of the form
7435 <symbol>@GOTOFF+<nnn>
7436 and similar .plt or .got references.
7438 If we find one, set up the correct relocation in RELOC and copy the
7439 input string, minus the `@GOTOFF' into a malloc'd buffer for
7440 parsing by the calling routine. Return this buffer, and if ADJUST
7441 is non-null set it to the length of the string we removed from the
7442 input line. Otherwise return NULL. */
7444 lex_got (enum bfd_reloc_code_real
*rel
,
7446 i386_operand_type
*types
)
7448 /* Some of the relocations depend on the size of what field is to
7449 be relocated. But in our callers i386_immediate and i386_displacement
7450 we don't yet know the operand size (this will be set by insn
7451 matching). Hence we record the word32 relocation here,
7452 and adjust the reloc according to the real size in reloc(). */
7453 static const struct {
7456 const enum bfd_reloc_code_real rel
[2];
7457 const i386_operand_type types64
;
7459 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7460 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7462 OPERAND_TYPE_IMM32_64
},
7464 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7465 BFD_RELOC_X86_64_PLTOFF64
},
7466 OPERAND_TYPE_IMM64
},
7467 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7468 BFD_RELOC_X86_64_PLT32
},
7469 OPERAND_TYPE_IMM32_32S_DISP32
},
7470 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7471 BFD_RELOC_X86_64_GOTPLT64
},
7472 OPERAND_TYPE_IMM64_DISP64
},
7473 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7474 BFD_RELOC_X86_64_GOTOFF64
},
7475 OPERAND_TYPE_IMM64_DISP64
},
7476 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7477 BFD_RELOC_X86_64_GOTPCREL
},
7478 OPERAND_TYPE_IMM32_32S_DISP32
},
7479 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7480 BFD_RELOC_X86_64_TLSGD
},
7481 OPERAND_TYPE_IMM32_32S_DISP32
},
7482 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7483 _dummy_first_bfd_reloc_code_real
},
7484 OPERAND_TYPE_NONE
},
7485 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7486 BFD_RELOC_X86_64_TLSLD
},
7487 OPERAND_TYPE_IMM32_32S_DISP32
},
7488 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7489 BFD_RELOC_X86_64_GOTTPOFF
},
7490 OPERAND_TYPE_IMM32_32S_DISP32
},
7491 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7492 BFD_RELOC_X86_64_TPOFF32
},
7493 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7494 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7495 _dummy_first_bfd_reloc_code_real
},
7496 OPERAND_TYPE_NONE
},
7497 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7498 BFD_RELOC_X86_64_DTPOFF32
},
7499 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7500 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7501 _dummy_first_bfd_reloc_code_real
},
7502 OPERAND_TYPE_NONE
},
7503 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7504 _dummy_first_bfd_reloc_code_real
},
7505 OPERAND_TYPE_NONE
},
7506 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7507 BFD_RELOC_X86_64_GOT32
},
7508 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7509 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7510 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7511 OPERAND_TYPE_IMM32_32S_DISP32
},
7512 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7513 BFD_RELOC_X86_64_TLSDESC_CALL
},
7514 OPERAND_TYPE_IMM32_32S_DISP32
},
7519 #if defined (OBJ_MAYBE_ELF)
7524 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7525 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7528 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7530 int len
= gotrel
[j
].len
;
7531 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7533 if (gotrel
[j
].rel
[object_64bit
] != 0)
7536 char *tmpbuf
, *past_reloc
;
7538 *rel
= gotrel
[j
].rel
[object_64bit
];
7542 if (flag_code
!= CODE_64BIT
)
7544 types
->bitfield
.imm32
= 1;
7545 types
->bitfield
.disp32
= 1;
7548 *types
= gotrel
[j
].types64
;
7551 if (j
!= 0 && GOT_symbol
== NULL
)
7552 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7554 /* The length of the first part of our input line. */
7555 first
= cp
- input_line_pointer
;
7557 /* The second part goes from after the reloc token until
7558 (and including) an end_of_line char or comma. */
7559 past_reloc
= cp
+ 1 + len
;
7561 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7563 second
= cp
+ 1 - past_reloc
;
7565 /* Allocate and copy string. The trailing NUL shouldn't
7566 be necessary, but be safe. */
7567 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7568 memcpy (tmpbuf
, input_line_pointer
, first
);
7569 if (second
!= 0 && *past_reloc
!= ' ')
7570 /* Replace the relocation token with ' ', so that
7571 errors like foo@GOTOFF1 will be detected. */
7572 tmpbuf
[first
++] = ' ';
7574 /* Increment length by 1 if the relocation token is
7579 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7580 tmpbuf
[first
+ second
] = '\0';
7584 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7585 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7590 /* Might be a symbol version string. Don't as_bad here. */
7599 /* Parse operands of the form
7600 <symbol>@SECREL32+<nnn>
7602 If we find one, set up the correct relocation in RELOC and copy the
7603 input string, minus the `@SECREL32' into a malloc'd buffer for
7604 parsing by the calling routine. Return this buffer, and if ADJUST
7605 is non-null set it to the length of the string we removed from the
7606 input line. Otherwise return NULL.
7608 This function is copied from the ELF version above adjusted for PE targets. */
7611 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7612 int *adjust ATTRIBUTE_UNUSED
,
7613 i386_operand_type
*types
)
7619 const enum bfd_reloc_code_real rel
[2];
7620 const i386_operand_type types64
;
7624 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7625 BFD_RELOC_32_SECREL
},
7626 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7632 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7633 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7636 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7638 int len
= gotrel
[j
].len
;
7640 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7642 if (gotrel
[j
].rel
[object_64bit
] != 0)
7645 char *tmpbuf
, *past_reloc
;
7647 *rel
= gotrel
[j
].rel
[object_64bit
];
7653 if (flag_code
!= CODE_64BIT
)
7655 types
->bitfield
.imm32
= 1;
7656 types
->bitfield
.disp32
= 1;
7659 *types
= gotrel
[j
].types64
;
7662 /* The length of the first part of our input line. */
7663 first
= cp
- input_line_pointer
;
7665 /* The second part goes from after the reloc token until
7666 (and including) an end_of_line char or comma. */
7667 past_reloc
= cp
+ 1 + len
;
7669 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7671 second
= cp
+ 1 - past_reloc
;
7673 /* Allocate and copy string. The trailing NUL shouldn't
7674 be necessary, but be safe. */
7675 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7676 memcpy (tmpbuf
, input_line_pointer
, first
);
7677 if (second
!= 0 && *past_reloc
!= ' ')
7678 /* Replace the relocation token with ' ', so that
7679 errors like foo@SECLREL321 will be detected. */
7680 tmpbuf
[first
++] = ' ';
7681 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7682 tmpbuf
[first
+ second
] = '\0';
7686 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7687 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7692 /* Might be a symbol version string. Don't as_bad here. */
7698 bfd_reloc_code_real_type
7699 x86_cons (expressionS
*exp
, int size
)
7701 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7703 intel_syntax
= -intel_syntax
;
7706 if (size
== 4 || (object_64bit
&& size
== 8))
7708 /* Handle @GOTOFF and the like in an expression. */
7710 char *gotfree_input_line
;
7713 save
= input_line_pointer
;
7714 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7715 if (gotfree_input_line
)
7716 input_line_pointer
= gotfree_input_line
;
7720 if (gotfree_input_line
)
7722 /* expression () has merrily parsed up to the end of line,
7723 or a comma - in the wrong buffer. Transfer how far
7724 input_line_pointer has moved to the right buffer. */
7725 input_line_pointer
= (save
7726 + (input_line_pointer
- gotfree_input_line
)
7728 free (gotfree_input_line
);
7729 if (exp
->X_op
== O_constant
7730 || exp
->X_op
== O_absent
7731 || exp
->X_op
== O_illegal
7732 || exp
->X_op
== O_register
7733 || exp
->X_op
== O_big
)
7735 char c
= *input_line_pointer
;
7736 *input_line_pointer
= 0;
7737 as_bad (_("missing or invalid expression `%s'"), save
);
7738 *input_line_pointer
= c
;
7745 intel_syntax
= -intel_syntax
;
7748 i386_intel_simplify (exp
);
7754 signed_cons (int size
)
7756 if (flag_code
== CODE_64BIT
)
7764 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7771 if (exp
.X_op
== O_symbol
)
7772 exp
.X_op
= O_secrel
;
7774 emit_expr (&exp
, 4);
7776 while (*input_line_pointer
++ == ',');
7778 input_line_pointer
--;
7779 demand_empty_rest_of_line ();
7783 /* Handle Vector operations. */
7786 check_VecOperations (char *op_string
, char *op_end
)
7788 const reg_entry
*mask
;
7793 && (op_end
== NULL
|| op_string
< op_end
))
7796 if (*op_string
== '{')
7800 /* Check broadcasts. */
7801 if (strncmp (op_string
, "1to", 3) == 0)
7806 goto duplicated_vec_op
;
7809 if (*op_string
== '8')
7810 bcst_type
= BROADCAST_1TO8
;
7811 else if (*op_string
== '4')
7812 bcst_type
= BROADCAST_1TO4
;
7813 else if (*op_string
== '2')
7814 bcst_type
= BROADCAST_1TO2
;
7815 else if (*op_string
== '1'
7816 && *(op_string
+1) == '6')
7818 bcst_type
= BROADCAST_1TO16
;
7823 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7828 broadcast_op
.type
= bcst_type
;
7829 broadcast_op
.operand
= this_operand
;
7830 i
.broadcast
= &broadcast_op
;
7832 /* Check masking operation. */
7833 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7835 /* k0 can't be used for write mask. */
7836 if (mask
->reg_num
== 0)
7838 as_bad (_("`%s' can't be used for write mask"),
7845 mask_op
.mask
= mask
;
7846 mask_op
.zeroing
= 0;
7847 mask_op
.operand
= this_operand
;
7853 goto duplicated_vec_op
;
7855 i
.mask
->mask
= mask
;
7857 /* Only "{z}" is allowed here. No need to check
7858 zeroing mask explicitly. */
7859 if (i
.mask
->operand
!= this_operand
)
7861 as_bad (_("invalid write mask `%s'"), saved
);
7868 /* Check zeroing-flag for masking operation. */
7869 else if (*op_string
== 'z')
7873 mask_op
.mask
= NULL
;
7874 mask_op
.zeroing
= 1;
7875 mask_op
.operand
= this_operand
;
7880 if (i
.mask
->zeroing
)
7883 as_bad (_("duplicated `%s'"), saved
);
7887 i
.mask
->zeroing
= 1;
7889 /* Only "{%k}" is allowed here. No need to check mask
7890 register explicitly. */
7891 if (i
.mask
->operand
!= this_operand
)
7893 as_bad (_("invalid zeroing-masking `%s'"),
7902 goto unknown_vec_op
;
7904 if (*op_string
!= '}')
7906 as_bad (_("missing `}' in `%s'"), saved
);
7913 /* We don't know this one. */
7914 as_bad (_("unknown vector operation: `%s'"), saved
);
7922 i386_immediate (char *imm_start
)
7924 char *save_input_line_pointer
;
7925 char *gotfree_input_line
;
7928 i386_operand_type types
;
7930 operand_type_set (&types
, ~0);
7932 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7934 as_bad (_("at most %d immediate operands are allowed"),
7935 MAX_IMMEDIATE_OPERANDS
);
7939 exp
= &im_expressions
[i
.imm_operands
++];
7940 i
.op
[this_operand
].imms
= exp
;
7942 if (is_space_char (*imm_start
))
7945 save_input_line_pointer
= input_line_pointer
;
7946 input_line_pointer
= imm_start
;
7948 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7949 if (gotfree_input_line
)
7950 input_line_pointer
= gotfree_input_line
;
7952 exp_seg
= expression (exp
);
7956 /* Handle vector operations. */
7957 if (*input_line_pointer
== '{')
7959 input_line_pointer
= check_VecOperations (input_line_pointer
,
7961 if (input_line_pointer
== NULL
)
7965 if (*input_line_pointer
)
7966 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7968 input_line_pointer
= save_input_line_pointer
;
7969 if (gotfree_input_line
)
7971 free (gotfree_input_line
);
7973 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7974 exp
->X_op
= O_illegal
;
7977 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7981 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7982 i386_operand_type types
, const char *imm_start
)
7984 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7987 as_bad (_("missing or invalid immediate expression `%s'"),
7991 else if (exp
->X_op
== O_constant
)
7993 /* Size it properly later. */
7994 i
.types
[this_operand
].bitfield
.imm64
= 1;
7995 /* If not 64bit, sign extend val. */
7996 if (flag_code
!= CODE_64BIT
7997 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7999 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8001 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8002 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8003 && exp_seg
!= absolute_section
8004 && exp_seg
!= text_section
8005 && exp_seg
!= data_section
8006 && exp_seg
!= bss_section
8007 && exp_seg
!= undefined_section
8008 && !bfd_is_com_section (exp_seg
))
8010 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8014 else if (!intel_syntax
&& exp_seg
== reg_section
)
8017 as_bad (_("illegal immediate register operand %s"), imm_start
);
8022 /* This is an address. The size of the address will be
8023 determined later, depending on destination register,
8024 suffix, or the default for the section. */
8025 i
.types
[this_operand
].bitfield
.imm8
= 1;
8026 i
.types
[this_operand
].bitfield
.imm16
= 1;
8027 i
.types
[this_operand
].bitfield
.imm32
= 1;
8028 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8029 i
.types
[this_operand
].bitfield
.imm64
= 1;
8030 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8038 i386_scale (char *scale
)
8041 char *save
= input_line_pointer
;
8043 input_line_pointer
= scale
;
8044 val
= get_absolute_expression ();
8049 i
.log2_scale_factor
= 0;
8052 i
.log2_scale_factor
= 1;
8055 i
.log2_scale_factor
= 2;
8058 i
.log2_scale_factor
= 3;
8062 char sep
= *input_line_pointer
;
8064 *input_line_pointer
= '\0';
8065 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8067 *input_line_pointer
= sep
;
8068 input_line_pointer
= save
;
8072 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8074 as_warn (_("scale factor of %d without an index register"),
8075 1 << i
.log2_scale_factor
);
8076 i
.log2_scale_factor
= 0;
8078 scale
= input_line_pointer
;
8079 input_line_pointer
= save
;
8084 i386_displacement (char *disp_start
, char *disp_end
)
8088 char *save_input_line_pointer
;
8089 char *gotfree_input_line
;
8091 i386_operand_type bigdisp
, types
= anydisp
;
8094 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8096 as_bad (_("at most %d displacement operands are allowed"),
8097 MAX_MEMORY_OPERANDS
);
8101 operand_type_set (&bigdisp
, 0);
8102 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8103 || (!current_templates
->start
->opcode_modifier
.jump
8104 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8106 bigdisp
.bitfield
.disp32
= 1;
8107 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8108 if (flag_code
== CODE_64BIT
)
8112 bigdisp
.bitfield
.disp32s
= 1;
8113 bigdisp
.bitfield
.disp64
= 1;
8116 else if ((flag_code
== CODE_16BIT
) ^ override
)
8118 bigdisp
.bitfield
.disp32
= 0;
8119 bigdisp
.bitfield
.disp16
= 1;
8124 /* For PC-relative branches, the width of the displacement
8125 is dependent upon data size, not address size. */
8126 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8127 if (flag_code
== CODE_64BIT
)
8129 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8130 bigdisp
.bitfield
.disp16
= 1;
8133 bigdisp
.bitfield
.disp32
= 1;
8134 bigdisp
.bitfield
.disp32s
= 1;
8140 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8142 : LONG_MNEM_SUFFIX
));
8143 bigdisp
.bitfield
.disp32
= 1;
8144 if ((flag_code
== CODE_16BIT
) ^ override
)
8146 bigdisp
.bitfield
.disp32
= 0;
8147 bigdisp
.bitfield
.disp16
= 1;
8151 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8154 exp
= &disp_expressions
[i
.disp_operands
];
8155 i
.op
[this_operand
].disps
= exp
;
8157 save_input_line_pointer
= input_line_pointer
;
8158 input_line_pointer
= disp_start
;
8159 END_STRING_AND_SAVE (disp_end
);
8161 #ifndef GCC_ASM_O_HACK
8162 #define GCC_ASM_O_HACK 0
8165 END_STRING_AND_SAVE (disp_end
+ 1);
8166 if (i
.types
[this_operand
].bitfield
.baseIndex
8167 && displacement_string_end
[-1] == '+')
8169 /* This hack is to avoid a warning when using the "o"
8170 constraint within gcc asm statements.
8173 #define _set_tssldt_desc(n,addr,limit,type) \
8174 __asm__ __volatile__ ( \
8176 "movw %w1,2+%0\n\t" \
8178 "movb %b1,4+%0\n\t" \
8179 "movb %4,5+%0\n\t" \
8180 "movb $0,6+%0\n\t" \
8181 "movb %h1,7+%0\n\t" \
8183 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8185 This works great except that the output assembler ends
8186 up looking a bit weird if it turns out that there is
8187 no offset. You end up producing code that looks like:
8200 So here we provide the missing zero. */
8202 *displacement_string_end
= '0';
8205 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8206 if (gotfree_input_line
)
8207 input_line_pointer
= gotfree_input_line
;
8209 exp_seg
= expression (exp
);
8212 if (*input_line_pointer
)
8213 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8215 RESTORE_END_STRING (disp_end
+ 1);
8217 input_line_pointer
= save_input_line_pointer
;
8218 if (gotfree_input_line
)
8220 free (gotfree_input_line
);
8222 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8223 exp
->X_op
= O_illegal
;
8226 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8228 RESTORE_END_STRING (disp_end
);
8234 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8235 i386_operand_type types
, const char *disp_start
)
8237 i386_operand_type bigdisp
;
8240 /* We do this to make sure that the section symbol is in
8241 the symbol table. We will ultimately change the relocation
8242 to be relative to the beginning of the section. */
8243 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8244 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8245 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8247 if (exp
->X_op
!= O_symbol
)
8250 if (S_IS_LOCAL (exp
->X_add_symbol
)
8251 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8252 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8253 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8254 exp
->X_op
= O_subtract
;
8255 exp
->X_op_symbol
= GOT_symbol
;
8256 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8257 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8258 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8259 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8261 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8264 else if (exp
->X_op
== O_absent
8265 || exp
->X_op
== O_illegal
8266 || exp
->X_op
== O_big
)
8269 as_bad (_("missing or invalid displacement expression `%s'"),
8274 else if (flag_code
== CODE_64BIT
8275 && !i
.prefix
[ADDR_PREFIX
]
8276 && exp
->X_op
== O_constant
)
8278 /* Since displacement is signed extended to 64bit, don't allow
8279 disp32 and turn off disp32s if they are out of range. */
8280 i
.types
[this_operand
].bitfield
.disp32
= 0;
8281 if (!fits_in_signed_long (exp
->X_add_number
))
8283 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8284 if (i
.types
[this_operand
].bitfield
.baseindex
)
8286 as_bad (_("0x%lx out range of signed 32bit displacement"),
8287 (long) exp
->X_add_number
);
8293 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8294 else if (exp
->X_op
!= O_constant
8295 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8296 && exp_seg
!= absolute_section
8297 && exp_seg
!= text_section
8298 && exp_seg
!= data_section
8299 && exp_seg
!= bss_section
8300 && exp_seg
!= undefined_section
8301 && !bfd_is_com_section (exp_seg
))
8303 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8308 /* Check if this is a displacement only operand. */
8309 bigdisp
= i
.types
[this_operand
];
8310 bigdisp
.bitfield
.disp8
= 0;
8311 bigdisp
.bitfield
.disp16
= 0;
8312 bigdisp
.bitfield
.disp32
= 0;
8313 bigdisp
.bitfield
.disp32s
= 0;
8314 bigdisp
.bitfield
.disp64
= 0;
8315 if (operand_type_all_zero (&bigdisp
))
8316 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8322 /* Make sure the memory operand we've been dealt is valid.
8323 Return 1 on success, 0 on a failure. */
8326 i386_index_check (const char *operand_string
)
8328 const char *kind
= "base/index";
8329 enum flag_code addr_mode
;
8331 if (i
.prefix
[ADDR_PREFIX
])
8332 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8335 addr_mode
= flag_code
;
8337 #if INFER_ADDR_PREFIX
8338 if (i
.mem_operands
== 0)
8340 /* Infer address prefix from the first memory operand. */
8341 const reg_entry
*addr_reg
= i
.base_reg
;
8343 if (addr_reg
== NULL
)
8344 addr_reg
= i
.index_reg
;
8348 if (addr_reg
->reg_num
== RegEip
8349 || addr_reg
->reg_num
== RegEiz
8350 || addr_reg
->reg_type
.bitfield
.reg32
)
8351 addr_mode
= CODE_32BIT
;
8352 else if (flag_code
!= CODE_64BIT
8353 && addr_reg
->reg_type
.bitfield
.reg16
)
8354 addr_mode
= CODE_16BIT
;
8356 if (addr_mode
!= flag_code
)
8358 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8360 /* Change the size of any displacement too. At most one
8361 of Disp16 or Disp32 is set.
8362 FIXME. There doesn't seem to be any real need for
8363 separate Disp16 and Disp32 flags. The same goes for
8364 Imm16 and Imm32. Removing them would probably clean
8365 up the code quite a lot. */
8366 if (flag_code
!= CODE_64BIT
8367 && (i
.types
[this_operand
].bitfield
.disp16
8368 || i
.types
[this_operand
].bitfield
.disp32
))
8369 i
.types
[this_operand
]
8370 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8377 if (current_templates
->start
->opcode_modifier
.isstring
8378 && !current_templates
->start
->opcode_modifier
.immext
8379 && (current_templates
->end
[-1].opcode_modifier
.isstring
8382 /* Memory operands of string insns are special in that they only allow
8383 a single register (rDI, rSI, or rBX) as their memory address. */
8384 const reg_entry
*expected_reg
;
8385 static const char *di_si
[][2] =
8391 static const char *bx
[] = { "ebx", "bx", "rbx" };
8393 kind
= "string address";
8395 if (current_templates
->start
->opcode_modifier
.w
)
8397 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8399 if (!type
.bitfield
.baseindex
8400 || ((!i
.mem_operands
!= !intel_syntax
)
8401 && current_templates
->end
[-1].operand_types
[1]
8402 .bitfield
.baseindex
))
8403 type
= current_templates
->end
[-1].operand_types
[1];
8404 expected_reg
= hash_find (reg_hash
,
8405 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8409 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8411 if (i
.base_reg
!= expected_reg
8413 || operand_type_check (i
.types
[this_operand
], disp
))
8415 /* The second memory operand must have the same size as
8419 && !((addr_mode
== CODE_64BIT
8420 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8421 || (addr_mode
== CODE_32BIT
8422 ? i
.base_reg
->reg_type
.bitfield
.reg32
8423 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8426 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8428 intel_syntax
? '[' : '(',
8430 expected_reg
->reg_name
,
8431 intel_syntax
? ']' : ')');
8438 as_bad (_("`%s' is not a valid %s expression"),
8439 operand_string
, kind
);
8444 if (addr_mode
!= CODE_16BIT
)
8446 /* 32-bit/64-bit checks. */
8448 && (addr_mode
== CODE_64BIT
8449 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8450 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8452 || (i
.base_reg
->reg_num
8453 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8455 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8456 && !i
.index_reg
->reg_type
.bitfield
.regymm
8457 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8458 && ((addr_mode
== CODE_64BIT
8459 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8460 || i
.index_reg
->reg_num
== RegRiz
)
8461 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8462 || i
.index_reg
->reg_num
== RegEiz
))
8463 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8468 /* 16-bit checks. */
8470 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8471 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8473 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8474 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8476 && i
.base_reg
->reg_num
< 6
8477 && i
.index_reg
->reg_num
>= 6
8478 && i
.log2_scale_factor
== 0))))
8485 /* Handle vector immediates. */
8488 RC_SAE_immediate (const char *imm_start
)
8490 unsigned int match_found
, j
;
8491 const char *pstr
= imm_start
;
8499 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8501 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8505 rc_op
.type
= RC_NamesTable
[j
].type
;
8506 rc_op
.operand
= this_operand
;
8507 i
.rounding
= &rc_op
;
8511 as_bad (_("duplicated `%s'"), imm_start
);
8514 pstr
+= RC_NamesTable
[j
].len
;
8524 as_bad (_("Missing '}': '%s'"), imm_start
);
8527 /* RC/SAE immediate string should contain nothing more. */;
8530 as_bad (_("Junk after '}': '%s'"), imm_start
);
8534 exp
= &im_expressions
[i
.imm_operands
++];
8535 i
.op
[this_operand
].imms
= exp
;
8537 exp
->X_op
= O_constant
;
8538 exp
->X_add_number
= 0;
8539 exp
->X_add_symbol
= (symbolS
*) 0;
8540 exp
->X_op_symbol
= (symbolS
*) 0;
8542 i
.types
[this_operand
].bitfield
.imm8
= 1;
8546 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8550 i386_att_operand (char *operand_string
)
8554 char *op_string
= operand_string
;
8556 if (is_space_char (*op_string
))
8559 /* We check for an absolute prefix (differentiating,
8560 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8561 if (*op_string
== ABSOLUTE_PREFIX
)
8564 if (is_space_char (*op_string
))
8566 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8569 /* Check if operand is a register. */
8570 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8572 i386_operand_type temp
;
8574 /* Check for a segment override by searching for ':' after a
8575 segment register. */
8577 if (is_space_char (*op_string
))
8579 if (*op_string
== ':'
8580 && (r
->reg_type
.bitfield
.sreg2
8581 || r
->reg_type
.bitfield
.sreg3
))
8586 i
.seg
[i
.mem_operands
] = &es
;
8589 i
.seg
[i
.mem_operands
] = &cs
;
8592 i
.seg
[i
.mem_operands
] = &ss
;
8595 i
.seg
[i
.mem_operands
] = &ds
;
8598 i
.seg
[i
.mem_operands
] = &fs
;
8601 i
.seg
[i
.mem_operands
] = &gs
;
8605 /* Skip the ':' and whitespace. */
8607 if (is_space_char (*op_string
))
8610 if (!is_digit_char (*op_string
)
8611 && !is_identifier_char (*op_string
)
8612 && *op_string
!= '('
8613 && *op_string
!= ABSOLUTE_PREFIX
)
8615 as_bad (_("bad memory operand `%s'"), op_string
);
8618 /* Handle case of %es:*foo. */
8619 if (*op_string
== ABSOLUTE_PREFIX
)
8622 if (is_space_char (*op_string
))
8624 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8626 goto do_memory_reference
;
8629 /* Handle vector operations. */
8630 if (*op_string
== '{')
8632 op_string
= check_VecOperations (op_string
, NULL
);
8633 if (op_string
== NULL
)
8639 as_bad (_("junk `%s' after register"), op_string
);
8643 temp
.bitfield
.baseindex
= 0;
8644 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8646 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8647 i
.op
[this_operand
].regs
= r
;
8650 else if (*op_string
== REGISTER_PREFIX
)
8652 as_bad (_("bad register name `%s'"), op_string
);
8655 else if (*op_string
== IMMEDIATE_PREFIX
)
8658 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8660 as_bad (_("immediate operand illegal with absolute jump"));
8663 if (!i386_immediate (op_string
))
8666 else if (RC_SAE_immediate (operand_string
))
8668 /* If it is a RC or SAE immediate, do nothing. */
8671 else if (is_digit_char (*op_string
)
8672 || is_identifier_char (*op_string
)
8673 || *op_string
== '"'
8674 || *op_string
== '(')
8676 /* This is a memory reference of some sort. */
8679 /* Start and end of displacement string expression (if found). */
8680 char *displacement_string_start
;
8681 char *displacement_string_end
;
8684 do_memory_reference
:
8685 if ((i
.mem_operands
== 1
8686 && !current_templates
->start
->opcode_modifier
.isstring
)
8687 || i
.mem_operands
== 2)
8689 as_bad (_("too many memory references for `%s'"),
8690 current_templates
->start
->name
);
8694 /* Check for base index form. We detect the base index form by
8695 looking for an ')' at the end of the operand, searching
8696 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8698 base_string
= op_string
+ strlen (op_string
);
8700 /* Handle vector operations. */
8701 vop_start
= strchr (op_string
, '{');
8702 if (vop_start
&& vop_start
< base_string
)
8704 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8706 base_string
= vop_start
;
8710 if (is_space_char (*base_string
))
8713 /* If we only have a displacement, set-up for it to be parsed later. */
8714 displacement_string_start
= op_string
;
8715 displacement_string_end
= base_string
+ 1;
8717 if (*base_string
== ')')
8720 unsigned int parens_balanced
= 1;
8721 /* We've already checked that the number of left & right ()'s are
8722 equal, so this loop will not be infinite. */
8726 if (*base_string
== ')')
8728 if (*base_string
== '(')
8731 while (parens_balanced
);
8733 temp_string
= base_string
;
8735 /* Skip past '(' and whitespace. */
8737 if (is_space_char (*base_string
))
8740 if (*base_string
== ','
8741 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8744 displacement_string_end
= temp_string
;
8746 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8750 base_string
= end_op
;
8751 if (is_space_char (*base_string
))
8755 /* There may be an index reg or scale factor here. */
8756 if (*base_string
== ',')
8759 if (is_space_char (*base_string
))
8762 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8765 base_string
= end_op
;
8766 if (is_space_char (*base_string
))
8768 if (*base_string
== ',')
8771 if (is_space_char (*base_string
))
8774 else if (*base_string
!= ')')
8776 as_bad (_("expecting `,' or `)' "
8777 "after index register in `%s'"),
8782 else if (*base_string
== REGISTER_PREFIX
)
8784 end_op
= strchr (base_string
, ',');
8787 as_bad (_("bad register name `%s'"), base_string
);
8791 /* Check for scale factor. */
8792 if (*base_string
!= ')')
8794 char *end_scale
= i386_scale (base_string
);
8799 base_string
= end_scale
;
8800 if (is_space_char (*base_string
))
8802 if (*base_string
!= ')')
8804 as_bad (_("expecting `)' "
8805 "after scale factor in `%s'"),
8810 else if (!i
.index_reg
)
8812 as_bad (_("expecting index register or scale factor "
8813 "after `,'; got '%c'"),
8818 else if (*base_string
!= ')')
8820 as_bad (_("expecting `,' or `)' "
8821 "after base register in `%s'"),
8826 else if (*base_string
== REGISTER_PREFIX
)
8828 end_op
= strchr (base_string
, ',');
8831 as_bad (_("bad register name `%s'"), base_string
);
8836 /* If there's an expression beginning the operand, parse it,
8837 assuming displacement_string_start and
8838 displacement_string_end are meaningful. */
8839 if (displacement_string_start
!= displacement_string_end
)
8841 if (!i386_displacement (displacement_string_start
,
8842 displacement_string_end
))
8846 /* Special case for (%dx) while doing input/output op. */
8848 && operand_type_equal (&i
.base_reg
->reg_type
,
8849 ®16_inoutportreg
)
8851 && i
.log2_scale_factor
== 0
8852 && i
.seg
[i
.mem_operands
] == 0
8853 && !operand_type_check (i
.types
[this_operand
], disp
))
8855 i
.types
[this_operand
] = inoutportreg
;
8859 if (i386_index_check (operand_string
) == 0)
8861 i
.types
[this_operand
].bitfield
.mem
= 1;
8866 /* It's not a memory operand; argh! */
8867 as_bad (_("invalid char %s beginning operand %d `%s'"),
8868 output_invalid (*op_string
),
8873 return 1; /* Normal return. */
8876 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8877 that an rs_machine_dependent frag may reach. */
8880 i386_frag_max_var (fragS
*frag
)
8882 /* The only relaxable frags are for jumps.
8883 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8884 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8885 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8888 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8890 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
8892 /* STT_GNU_IFUNC symbol must go through PLT. */
8893 if ((symbol_get_bfdsym (fr_symbol
)->flags
8894 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8897 if (!S_IS_EXTERNAL (fr_symbol
))
8898 /* Symbol may be weak or local. */
8899 return !S_IS_WEAK (fr_symbol
);
8901 /* Global symbols with non-default visibility can't be preempted. */
8902 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
8905 if (fr_var
!= NO_RELOC
)
8906 switch ((enum bfd_reloc_code_real
) fr_var
)
8908 case BFD_RELOC_386_PLT32
:
8909 case BFD_RELOC_X86_64_PLT32
:
8910 /* Symbol with PLT relocatin may be preempted. */
8916 /* Global symbols with default visibility in a shared library may be
8917 preempted by another definition. */
8922 /* md_estimate_size_before_relax()
8924 Called just before relax() for rs_machine_dependent frags. The x86
8925 assembler uses these frags to handle variable size jump
8928 Any symbol that is now undefined will not become defined.
8929 Return the correct fr_subtype in the frag.
8930 Return the initial "guess for variable size of frag" to caller.
8931 The guess is actually the growth beyond the fixed part. Whatever
8932 we do to grow the fixed or variable part contributes to our
8936 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8938 /* We've already got fragP->fr_subtype right; all we have to do is
8939 check for un-relaxable symbols. On an ELF system, we can't relax
8940 an externally visible symbol, because it may be overridden by a
8942 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8943 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8945 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
8948 #if defined (OBJ_COFF) && defined (TE_PE)
8949 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8950 && S_IS_WEAK (fragP
->fr_symbol
))
8954 /* Symbol is undefined in this segment, or we need to keep a
8955 reloc so that weak symbols can be overridden. */
8956 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8957 enum bfd_reloc_code_real reloc_type
;
8958 unsigned char *opcode
;
8961 if (fragP
->fr_var
!= NO_RELOC
)
8962 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8964 reloc_type
= BFD_RELOC_16_PCREL
;
8966 reloc_type
= BFD_RELOC_32_PCREL
;
8968 old_fr_fix
= fragP
->fr_fix
;
8969 opcode
= (unsigned char *) fragP
->fr_opcode
;
8971 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8974 /* Make jmp (0xeb) a (d)word displacement jump. */
8976 fragP
->fr_fix
+= size
;
8977 fix_new (fragP
, old_fr_fix
, size
,
8979 fragP
->fr_offset
, 1,
8985 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8987 /* Negate the condition, and branch past an
8988 unconditional jump. */
8991 /* Insert an unconditional jump. */
8993 /* We added two extra opcode bytes, and have a two byte
8995 fragP
->fr_fix
+= 2 + 2;
8996 fix_new (fragP
, old_fr_fix
+ 2, 2,
8998 fragP
->fr_offset
, 1,
9005 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9010 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9012 fragP
->fr_offset
, 1,
9014 fixP
->fx_signed
= 1;
9018 /* This changes the byte-displacement jump 0x7N
9019 to the (d)word-displacement jump 0x0f,0x8N. */
9020 opcode
[1] = opcode
[0] + 0x10;
9021 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9022 /* We've added an opcode byte. */
9023 fragP
->fr_fix
+= 1 + size
;
9024 fix_new (fragP
, old_fr_fix
+ 1, size
,
9026 fragP
->fr_offset
, 1,
9031 BAD_CASE (fragP
->fr_subtype
);
9035 return fragP
->fr_fix
- old_fr_fix
;
9038 /* Guess size depending on current relax state. Initially the relax
9039 state will correspond to a short jump and we return 1, because
9040 the variable part of the frag (the branch offset) is one byte
9041 long. However, we can relax a section more than once and in that
9042 case we must either set fr_subtype back to the unrelaxed state,
9043 or return the value for the appropriate branch. */
9044 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9047 /* Called after relax() is finished.
9049 In: Address of frag.
9050 fr_type == rs_machine_dependent.
9051 fr_subtype is what the address relaxed to.
9053 Out: Any fixSs and constants are set up.
9054 Caller will turn frag into a ".space 0". */
9057 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9060 unsigned char *opcode
;
9061 unsigned char *where_to_put_displacement
= NULL
;
9062 offsetT target_address
;
9063 offsetT opcode_address
;
9064 unsigned int extension
= 0;
9065 offsetT displacement_from_opcode_start
;
9067 opcode
= (unsigned char *) fragP
->fr_opcode
;
9069 /* Address we want to reach in file space. */
9070 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9072 /* Address opcode resides at in file space. */
9073 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9075 /* Displacement from opcode start to fill into instruction. */
9076 displacement_from_opcode_start
= target_address
- opcode_address
;
9078 if ((fragP
->fr_subtype
& BIG
) == 0)
9080 /* Don't have to change opcode. */
9081 extension
= 1; /* 1 opcode + 1 displacement */
9082 where_to_put_displacement
= &opcode
[1];
9086 if (no_cond_jump_promotion
9087 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9088 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9089 _("long jump required"));
9091 switch (fragP
->fr_subtype
)
9093 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9094 extension
= 4; /* 1 opcode + 4 displacement */
9096 where_to_put_displacement
= &opcode
[1];
9099 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9100 extension
= 2; /* 1 opcode + 2 displacement */
9102 where_to_put_displacement
= &opcode
[1];
9105 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9106 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9107 extension
= 5; /* 2 opcode + 4 displacement */
9108 opcode
[1] = opcode
[0] + 0x10;
9109 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9110 where_to_put_displacement
= &opcode
[2];
9113 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9114 extension
= 3; /* 2 opcode + 2 displacement */
9115 opcode
[1] = opcode
[0] + 0x10;
9116 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9117 where_to_put_displacement
= &opcode
[2];
9120 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9125 where_to_put_displacement
= &opcode
[3];
9129 BAD_CASE (fragP
->fr_subtype
);
9134 /* If size if less then four we are sure that the operand fits,
9135 but if it's 4, then it could be that the displacement is larger
9137 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9139 && ((addressT
) (displacement_from_opcode_start
- extension
9140 + ((addressT
) 1 << 31))
9141 > (((addressT
) 2 << 31) - 1)))
9143 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9144 _("jump target out of range"));
9145 /* Make us emit 0. */
9146 displacement_from_opcode_start
= extension
;
9148 /* Now put displacement after opcode. */
9149 md_number_to_chars ((char *) where_to_put_displacement
,
9150 (valueT
) (displacement_from_opcode_start
- extension
),
9151 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9152 fragP
->fr_fix
+= extension
;
9155 /* Apply a fixup (fixP) to segment data, once it has been determined
9156 by our caller that we have all the info we need to fix it up.
9158 Parameter valP is the pointer to the value of the bits.
9160 On the 386, immediates, displacements, and data pointers are all in
9161 the same (little-endian) format, so we don't need to care about which
9165 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9167 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9168 valueT value
= *valP
;
9170 #if !defined (TE_Mach)
9173 switch (fixP
->fx_r_type
)
9179 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9182 case BFD_RELOC_X86_64_32S
:
9183 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9186 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9189 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9194 if (fixP
->fx_addsy
!= NULL
9195 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9196 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9197 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9198 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9199 && !use_rela_relocations
)
9201 /* This is a hack. There should be a better way to handle this.
9202 This covers for the fact that bfd_install_relocation will
9203 subtract the current location (for partial_inplace, PC relative
9204 relocations); see more below. */
9208 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9211 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9213 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9216 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9219 || (symbol_section_p (fixP
->fx_addsy
)
9220 && sym_seg
!= absolute_section
))
9221 && !generic_force_reloc (fixP
))
9223 /* Yes, we add the values in twice. This is because
9224 bfd_install_relocation subtracts them out again. I think
9225 bfd_install_relocation is broken, but I don't dare change
9227 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9231 #if defined (OBJ_COFF) && defined (TE_PE)
9232 /* For some reason, the PE format does not store a
9233 section address offset for a PC relative symbol. */
9234 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9235 || S_IS_WEAK (fixP
->fx_addsy
))
9236 value
+= md_pcrel_from (fixP
);
9239 #if defined (OBJ_COFF) && defined (TE_PE)
9240 if (fixP
->fx_addsy
!= NULL
9241 && S_IS_WEAK (fixP
->fx_addsy
)
9242 /* PR 16858: Do not modify weak function references. */
9243 && ! fixP
->fx_pcrel
)
9245 #if !defined (TE_PEP)
9246 /* For x86 PE weak function symbols are neither PC-relative
9247 nor do they set S_IS_FUNCTION. So the only reliable way
9248 to detect them is to check the flags of their containing
9250 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9251 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9255 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9259 /* Fix a few things - the dynamic linker expects certain values here,
9260 and we must not disappoint it. */
9261 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9262 if (IS_ELF
&& fixP
->fx_addsy
)
9263 switch (fixP
->fx_r_type
)
9265 case BFD_RELOC_386_PLT32
:
9266 case BFD_RELOC_X86_64_PLT32
:
9267 /* Make the jump instruction point to the address of the operand. At
9268 runtime we merely add the offset to the actual PLT entry. */
9272 case BFD_RELOC_386_TLS_GD
:
9273 case BFD_RELOC_386_TLS_LDM
:
9274 case BFD_RELOC_386_TLS_IE_32
:
9275 case BFD_RELOC_386_TLS_IE
:
9276 case BFD_RELOC_386_TLS_GOTIE
:
9277 case BFD_RELOC_386_TLS_GOTDESC
:
9278 case BFD_RELOC_X86_64_TLSGD
:
9279 case BFD_RELOC_X86_64_TLSLD
:
9280 case BFD_RELOC_X86_64_GOTTPOFF
:
9281 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9282 value
= 0; /* Fully resolved at runtime. No addend. */
9284 case BFD_RELOC_386_TLS_LE
:
9285 case BFD_RELOC_386_TLS_LDO_32
:
9286 case BFD_RELOC_386_TLS_LE_32
:
9287 case BFD_RELOC_X86_64_DTPOFF32
:
9288 case BFD_RELOC_X86_64_DTPOFF64
:
9289 case BFD_RELOC_X86_64_TPOFF32
:
9290 case BFD_RELOC_X86_64_TPOFF64
:
9291 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9294 case BFD_RELOC_386_TLS_DESC_CALL
:
9295 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9296 value
= 0; /* Fully resolved at runtime. No addend. */
9297 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9301 case BFD_RELOC_386_GOT32
:
9302 case BFD_RELOC_X86_64_GOT32
:
9303 value
= 0; /* Fully resolved at runtime. No addend. */
9306 case BFD_RELOC_VTABLE_INHERIT
:
9307 case BFD_RELOC_VTABLE_ENTRY
:
9314 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9316 #endif /* !defined (TE_Mach) */
9318 /* Are we finished with this relocation now? */
9319 if (fixP
->fx_addsy
== NULL
)
9321 #if defined (OBJ_COFF) && defined (TE_PE)
9322 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9325 /* Remember value for tc_gen_reloc. */
9326 fixP
->fx_addnumber
= value
;
9327 /* Clear out the frag for now. */
9331 else if (use_rela_relocations
)
9333 fixP
->fx_no_overflow
= 1;
9334 /* Remember value for tc_gen_reloc. */
9335 fixP
->fx_addnumber
= value
;
9339 md_number_to_chars (p
, value
, fixP
->fx_size
);
9343 md_atof (int type
, char *litP
, int *sizeP
)
9345 /* This outputs the LITTLENUMs in REVERSE order;
9346 in accord with the bigendian 386. */
9347 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9350 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9353 output_invalid (int c
)
9356 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9359 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9360 "(0x%x)", (unsigned char) c
);
9361 return output_invalid_buf
;
9364 /* REG_STRING starts *before* REGISTER_PREFIX. */
9366 static const reg_entry
*
9367 parse_real_register (char *reg_string
, char **end_op
)
9369 char *s
= reg_string
;
9371 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9374 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9375 if (*s
== REGISTER_PREFIX
)
9378 if (is_space_char (*s
))
9382 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9384 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9385 return (const reg_entry
*) NULL
;
9389 /* For naked regs, make sure that we are not dealing with an identifier.
9390 This prevents confusing an identifier like `eax_var' with register
9392 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9393 return (const reg_entry
*) NULL
;
9397 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9399 /* Handle floating point regs, allowing spaces in the (i) part. */
9400 if (r
== i386_regtab
/* %st is first entry of table */)
9402 if (is_space_char (*s
))
9407 if (is_space_char (*s
))
9409 if (*s
>= '0' && *s
<= '7')
9413 if (is_space_char (*s
))
9418 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9423 /* We have "%st(" then garbage. */
9424 return (const reg_entry
*) NULL
;
9428 if (r
== NULL
|| allow_pseudo_reg
)
9431 if (operand_type_all_zero (&r
->reg_type
))
9432 return (const reg_entry
*) NULL
;
9434 if ((r
->reg_type
.bitfield
.reg32
9435 || r
->reg_type
.bitfield
.sreg3
9436 || r
->reg_type
.bitfield
.control
9437 || r
->reg_type
.bitfield
.debug
9438 || r
->reg_type
.bitfield
.test
)
9439 && !cpu_arch_flags
.bitfield
.cpui386
)
9440 return (const reg_entry
*) NULL
;
9442 if (r
->reg_type
.bitfield
.floatreg
9443 && !cpu_arch_flags
.bitfield
.cpu8087
9444 && !cpu_arch_flags
.bitfield
.cpu287
9445 && !cpu_arch_flags
.bitfield
.cpu387
)
9446 return (const reg_entry
*) NULL
;
9448 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9449 return (const reg_entry
*) NULL
;
9451 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9452 return (const reg_entry
*) NULL
;
9454 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9455 return (const reg_entry
*) NULL
;
9457 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9458 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9459 return (const reg_entry
*) NULL
;
9461 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9462 if (!allow_index_reg
9463 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9464 return (const reg_entry
*) NULL
;
9466 /* Upper 16 vector register is only available with VREX in 64bit
9468 if ((r
->reg_flags
& RegVRex
))
9470 if (!cpu_arch_flags
.bitfield
.cpuvrex
9471 || flag_code
!= CODE_64BIT
)
9472 return (const reg_entry
*) NULL
;
9477 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9478 || r
->reg_type
.bitfield
.reg64
)
9479 && (!cpu_arch_flags
.bitfield
.cpulm
9480 || !operand_type_equal (&r
->reg_type
, &control
))
9481 && flag_code
!= CODE_64BIT
)
9482 return (const reg_entry
*) NULL
;
9484 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9485 return (const reg_entry
*) NULL
;
9490 /* REG_STRING starts *before* REGISTER_PREFIX. */
9492 static const reg_entry
*
9493 parse_register (char *reg_string
, char **end_op
)
9497 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9498 r
= parse_real_register (reg_string
, end_op
);
9503 char *save
= input_line_pointer
;
9507 input_line_pointer
= reg_string
;
9508 c
= get_symbol_name (®_string
);
9509 symbolP
= symbol_find (reg_string
);
9510 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9512 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9514 know (e
->X_op
== O_register
);
9515 know (e
->X_add_number
>= 0
9516 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9517 r
= i386_regtab
+ e
->X_add_number
;
9518 if ((r
->reg_flags
& RegVRex
))
9520 *end_op
= input_line_pointer
;
9522 *input_line_pointer
= c
;
9523 input_line_pointer
= save
;
9529 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9532 char *end
= input_line_pointer
;
9535 r
= parse_register (name
, &input_line_pointer
);
9536 if (r
&& end
<= input_line_pointer
)
9538 *nextcharP
= *input_line_pointer
;
9539 *input_line_pointer
= 0;
9540 e
->X_op
= O_register
;
9541 e
->X_add_number
= r
- i386_regtab
;
9544 input_line_pointer
= end
;
9546 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9550 md_operand (expressionS
*e
)
9555 switch (*input_line_pointer
)
9557 case REGISTER_PREFIX
:
9558 r
= parse_real_register (input_line_pointer
, &end
);
9561 e
->X_op
= O_register
;
9562 e
->X_add_number
= r
- i386_regtab
;
9563 input_line_pointer
= end
;
9568 gas_assert (intel_syntax
);
9569 end
= input_line_pointer
++;
9571 if (*input_line_pointer
== ']')
9573 ++input_line_pointer
;
9574 e
->X_op_symbol
= make_expr_symbol (e
);
9575 e
->X_add_symbol
= NULL
;
9576 e
->X_add_number
= 0;
9582 input_line_pointer
= end
;
9589 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9590 const char *md_shortopts
= "kVQ:sqn";
9592 const char *md_shortopts
= "qn";
9595 #define OPTION_32 (OPTION_MD_BASE + 0)
9596 #define OPTION_64 (OPTION_MD_BASE + 1)
9597 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9598 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9599 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9600 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9601 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9602 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9603 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9604 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9605 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9606 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9607 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9608 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9609 #define OPTION_X32 (OPTION_MD_BASE + 14)
9610 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9611 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9612 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9613 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9614 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9615 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9616 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9617 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9618 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9620 struct option md_longopts
[] =
9622 {"32", no_argument
, NULL
, OPTION_32
},
9623 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9624 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9625 {"64", no_argument
, NULL
, OPTION_64
},
9627 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9628 {"x32", no_argument
, NULL
, OPTION_X32
},
9629 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9631 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9632 {"march", required_argument
, NULL
, OPTION_MARCH
},
9633 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9634 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9635 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9636 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9637 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9638 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9639 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9640 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9641 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9642 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9643 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9644 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9645 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9646 # if defined (TE_PE) || defined (TE_PEP)
9647 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9649 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9650 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9651 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9652 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9653 {NULL
, no_argument
, NULL
, 0}
9655 size_t md_longopts_size
= sizeof (md_longopts
);
9658 md_parse_option (int c
, char *arg
)
9666 optimize_align_code
= 0;
9673 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9674 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9675 should be emitted or not. FIXME: Not implemented. */
9679 /* -V: SVR4 argument to print version ID. */
9681 print_version_id ();
9684 /* -k: Ignore for FreeBSD compatibility. */
9689 /* -s: On i386 Solaris, this tells the native assembler to use
9690 .stab instead of .stab.excl. We always use .stab anyhow. */
9693 case OPTION_MSHARED
:
9697 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9698 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9701 const char **list
, **l
;
9703 list
= bfd_target_list ();
9704 for (l
= list
; *l
!= NULL
; l
++)
9705 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9706 || strcmp (*l
, "coff-x86-64") == 0
9707 || strcmp (*l
, "pe-x86-64") == 0
9708 || strcmp (*l
, "pei-x86-64") == 0
9709 || strcmp (*l
, "mach-o-x86-64") == 0)
9711 default_arch
= "x86_64";
9715 as_fatal (_("no compiled in support for x86_64"));
9721 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9725 const char **list
, **l
;
9727 list
= bfd_target_list ();
9728 for (l
= list
; *l
!= NULL
; l
++)
9729 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9731 default_arch
= "x86_64:32";
9735 as_fatal (_("no compiled in support for 32bit x86_64"));
9739 as_fatal (_("32bit x86_64 is only supported for ELF"));
9744 default_arch
= "i386";
9748 #ifdef SVR4_COMMENT_CHARS
9753 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9755 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9759 i386_comment_chars
= n
;
9765 arch
= xstrdup (arg
);
9769 as_fatal (_("invalid -march= option: `%s'"), arg
);
9770 next
= strchr (arch
, '+');
9773 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9775 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9778 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9781 cpu_arch_name
= cpu_arch
[j
].name
;
9782 cpu_sub_arch_name
= NULL
;
9783 cpu_arch_flags
= cpu_arch
[j
].flags
;
9784 cpu_arch_isa
= cpu_arch
[j
].type
;
9785 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9786 if (!cpu_arch_tune_set
)
9788 cpu_arch_tune
= cpu_arch_isa
;
9789 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9793 else if (*cpu_arch
[j
].name
== '.'
9794 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9796 /* ISA entension. */
9797 i386_cpu_flags flags
;
9799 if (!cpu_arch
[j
].negated
)
9800 flags
= cpu_flags_or (cpu_arch_flags
,
9803 flags
= cpu_flags_and_not (cpu_arch_flags
,
9806 if (!valid_iamcu_cpu_flags (&flags
))
9807 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9808 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9810 if (cpu_sub_arch_name
)
9812 char *name
= cpu_sub_arch_name
;
9813 cpu_sub_arch_name
= concat (name
,
9815 (const char *) NULL
);
9819 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9820 cpu_arch_flags
= flags
;
9821 cpu_arch_isa_flags
= flags
;
9827 if (j
>= ARRAY_SIZE (cpu_arch
))
9828 as_fatal (_("invalid -march= option: `%s'"), arg
);
9832 while (next
!= NULL
);
9837 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9838 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9840 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9842 cpu_arch_tune_set
= 1;
9843 cpu_arch_tune
= cpu_arch
[j
].type
;
9844 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9848 if (j
>= ARRAY_SIZE (cpu_arch
))
9849 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9852 case OPTION_MMNEMONIC
:
9853 if (strcasecmp (arg
, "att") == 0)
9855 else if (strcasecmp (arg
, "intel") == 0)
9858 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9861 case OPTION_MSYNTAX
:
9862 if (strcasecmp (arg
, "att") == 0)
9864 else if (strcasecmp (arg
, "intel") == 0)
9867 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9870 case OPTION_MINDEX_REG
:
9871 allow_index_reg
= 1;
9874 case OPTION_MNAKED_REG
:
9875 allow_naked_reg
= 1;
9878 case OPTION_MOLD_GCC
:
9882 case OPTION_MSSE2AVX
:
9886 case OPTION_MSSE_CHECK
:
9887 if (strcasecmp (arg
, "error") == 0)
9888 sse_check
= check_error
;
9889 else if (strcasecmp (arg
, "warning") == 0)
9890 sse_check
= check_warning
;
9891 else if (strcasecmp (arg
, "none") == 0)
9892 sse_check
= check_none
;
9894 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9897 case OPTION_MOPERAND_CHECK
:
9898 if (strcasecmp (arg
, "error") == 0)
9899 operand_check
= check_error
;
9900 else if (strcasecmp (arg
, "warning") == 0)
9901 operand_check
= check_warning
;
9902 else if (strcasecmp (arg
, "none") == 0)
9903 operand_check
= check_none
;
9905 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9908 case OPTION_MAVXSCALAR
:
9909 if (strcasecmp (arg
, "128") == 0)
9911 else if (strcasecmp (arg
, "256") == 0)
9914 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9917 case OPTION_MADD_BND_PREFIX
:
9921 case OPTION_MEVEXLIG
:
9922 if (strcmp (arg
, "128") == 0)
9924 else if (strcmp (arg
, "256") == 0)
9926 else if (strcmp (arg
, "512") == 0)
9929 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9932 case OPTION_MEVEXRCIG
:
9933 if (strcmp (arg
, "rne") == 0)
9935 else if (strcmp (arg
, "rd") == 0)
9937 else if (strcmp (arg
, "ru") == 0)
9939 else if (strcmp (arg
, "rz") == 0)
9942 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9945 case OPTION_MEVEXWIG
:
9946 if (strcmp (arg
, "0") == 0)
9948 else if (strcmp (arg
, "1") == 0)
9951 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9954 # if defined (TE_PE) || defined (TE_PEP)
9955 case OPTION_MBIG_OBJ
:
9960 case OPTION_OMIT_LOCK_PREFIX
:
9961 if (strcasecmp (arg
, "yes") == 0)
9962 omit_lock_prefix
= 1;
9963 else if (strcasecmp (arg
, "no") == 0)
9964 omit_lock_prefix
= 0;
9966 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9970 cpu_arch_flags
.bitfield
.cpuamd64
= 1;
9971 cpu_arch_flags
.bitfield
.cpuintel64
= 0;
9972 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 1;
9973 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 0;
9976 case OPTION_MINTEL64
:
9977 cpu_arch_flags
.bitfield
.cpuamd64
= 0;
9978 cpu_arch_flags
.bitfield
.cpuintel64
= 1;
9979 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 0;
9980 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 1;
9989 #define MESSAGE_TEMPLATE \
9993 show_arch (FILE *stream
, int ext
, int check
)
9995 static char message
[] = MESSAGE_TEMPLATE
;
9996 char *start
= message
+ 27;
9998 int size
= sizeof (MESSAGE_TEMPLATE
);
10005 left
= size
- (start
- message
);
10006 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10008 /* Should it be skipped? */
10009 if (cpu_arch
[j
].skip
)
10012 name
= cpu_arch
[j
].name
;
10013 len
= cpu_arch
[j
].len
;
10016 /* It is an extension. Skip if we aren't asked to show it. */
10027 /* It is an processor. Skip if we show only extension. */
10030 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10032 /* It is an impossible processor - skip. */
10036 /* Reserve 2 spaces for ", " or ",\0" */
10039 /* Check if there is any room. */
10047 p
= mempcpy (p
, name
, len
);
10051 /* Output the current message now and start a new one. */
10054 fprintf (stream
, "%s\n", message
);
10056 left
= size
- (start
- message
) - len
- 2;
10058 gas_assert (left
>= 0);
10060 p
= mempcpy (p
, name
, len
);
10065 fprintf (stream
, "%s\n", message
);
10069 md_show_usage (FILE *stream
)
10071 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10072 fprintf (stream
, _("\
10074 -V print assembler version number\n\
10077 fprintf (stream
, _("\
10078 -n Do not optimize code alignment\n\
10079 -q quieten some warnings\n"));
10080 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10081 fprintf (stream
, _("\
10084 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10085 || defined (TE_PE) || defined (TE_PEP))
10086 fprintf (stream
, _("\
10087 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10089 #ifdef SVR4_COMMENT_CHARS
10090 fprintf (stream
, _("\
10091 --divide do not treat `/' as a comment character\n"));
10093 fprintf (stream
, _("\
10094 --divide ignored\n"));
10096 fprintf (stream
, _("\
10097 -march=CPU[,+EXTENSION...]\n\
10098 generate code for CPU and EXTENSION, CPU is one of:\n"));
10099 show_arch (stream
, 0, 1);
10100 fprintf (stream
, _("\
10101 EXTENSION is combination of:\n"));
10102 show_arch (stream
, 1, 0);
10103 fprintf (stream
, _("\
10104 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10105 show_arch (stream
, 0, 0);
10106 fprintf (stream
, _("\
10107 -msse2avx encode SSE instructions with VEX prefix\n"));
10108 fprintf (stream
, _("\
10109 -msse-check=[none|error|warning]\n\
10110 check SSE instructions\n"));
10111 fprintf (stream
, _("\
10112 -moperand-check=[none|error|warning]\n\
10113 check operand combinations for validity\n"));
10114 fprintf (stream
, _("\
10115 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10117 fprintf (stream
, _("\
10118 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10120 fprintf (stream
, _("\
10121 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10122 for EVEX.W bit ignored instructions\n"));
10123 fprintf (stream
, _("\
10124 -mevexrcig=[rne|rd|ru|rz]\n\
10125 encode EVEX instructions with specific EVEX.RC value\n\
10126 for SAE-only ignored instructions\n"));
10127 fprintf (stream
, _("\
10128 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10129 fprintf (stream
, _("\
10130 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10131 fprintf (stream
, _("\
10132 -mindex-reg support pseudo index registers\n"));
10133 fprintf (stream
, _("\
10134 -mnaked-reg don't require `%%' prefix for registers\n"));
10135 fprintf (stream
, _("\
10136 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10137 fprintf (stream
, _("\
10138 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10139 fprintf (stream
, _("\
10140 -mshared disable branch optimization for shared code\n"));
10141 # if defined (TE_PE) || defined (TE_PEP)
10142 fprintf (stream
, _("\
10143 -mbig-obj generate big object files\n"));
10145 fprintf (stream
, _("\
10146 -momit-lock-prefix=[no|yes]\n\
10147 strip all lock prefixes\n"));
10148 fprintf (stream
, _("\
10149 -mamd64 accept only AMD64 ISA\n"));
10150 fprintf (stream
, _("\
10151 -mintel64 accept only Intel64 ISA\n"));
10154 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10155 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10156 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10158 /* Pick the target format to use. */
10161 i386_target_format (void)
10163 if (!strncmp (default_arch
, "x86_64", 6))
10165 update_code_flag (CODE_64BIT
, 1);
10166 if (default_arch
[6] == '\0')
10167 x86_elf_abi
= X86_64_ABI
;
10169 x86_elf_abi
= X86_64_X32_ABI
;
10171 else if (!strcmp (default_arch
, "i386"))
10172 update_code_flag (CODE_32BIT
, 1);
10173 else if (!strcmp (default_arch
, "iamcu"))
10175 update_code_flag (CODE_32BIT
, 1);
10176 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10178 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10179 cpu_arch_name
= "iamcu";
10180 cpu_sub_arch_name
= NULL
;
10181 cpu_arch_flags
= iamcu_flags
;
10182 cpu_arch_isa
= PROCESSOR_IAMCU
;
10183 cpu_arch_isa_flags
= iamcu_flags
;
10184 if (!cpu_arch_tune_set
)
10186 cpu_arch_tune
= cpu_arch_isa
;
10187 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10191 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10195 as_fatal (_("unknown architecture"));
10197 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10198 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10199 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10200 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10202 switch (OUTPUT_FLAVOR
)
10204 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10205 case bfd_target_aout_flavour
:
10206 return AOUT_TARGET_FORMAT
;
10208 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10209 # if defined (TE_PE) || defined (TE_PEP)
10210 case bfd_target_coff_flavour
:
10211 if (flag_code
== CODE_64BIT
)
10212 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10215 # elif defined (TE_GO32)
10216 case bfd_target_coff_flavour
:
10217 return "coff-go32";
10219 case bfd_target_coff_flavour
:
10220 return "coff-i386";
10223 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10224 case bfd_target_elf_flavour
:
10226 const char *format
;
10228 switch (x86_elf_abi
)
10231 format
= ELF_TARGET_FORMAT
;
10234 use_rela_relocations
= 1;
10236 format
= ELF_TARGET_FORMAT64
;
10238 case X86_64_X32_ABI
:
10239 use_rela_relocations
= 1;
10241 disallow_64bit_reloc
= 1;
10242 format
= ELF_TARGET_FORMAT32
;
10245 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10247 if (x86_elf_abi
!= X86_64_ABI
)
10248 as_fatal (_("Intel L1OM is 64bit only"));
10249 return ELF_TARGET_L1OM_FORMAT
;
10251 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10253 if (x86_elf_abi
!= X86_64_ABI
)
10254 as_fatal (_("Intel K1OM is 64bit only"));
10255 return ELF_TARGET_K1OM_FORMAT
;
10257 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10259 if (x86_elf_abi
!= I386_ABI
)
10260 as_fatal (_("Intel MCU is 32bit only"));
10261 return ELF_TARGET_IAMCU_FORMAT
;
10267 #if defined (OBJ_MACH_O)
10268 case bfd_target_mach_o_flavour
:
10269 if (flag_code
== CODE_64BIT
)
10271 use_rela_relocations
= 1;
10273 return "mach-o-x86-64";
10276 return "mach-o-i386";
10284 #endif /* OBJ_MAYBE_ more than one */
10287 md_undefined_symbol (char *name
)
10289 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10290 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10291 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10292 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10296 if (symbol_find (name
))
10297 as_bad (_("GOT already in symbol table"));
10298 GOT_symbol
= symbol_new (name
, undefined_section
,
10299 (valueT
) 0, &zero_address_frag
);
10306 /* Round up a section size to the appropriate boundary. */
10309 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10311 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10312 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10314 /* For a.out, force the section size to be aligned. If we don't do
10315 this, BFD will align it for us, but it will not write out the
10316 final bytes of the section. This may be a bug in BFD, but it is
10317 easier to fix it here since that is how the other a.out targets
10321 align
= bfd_get_section_alignment (stdoutput
, segment
);
10322 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10329 /* On the i386, PC-relative offsets are relative to the start of the
10330 next instruction. That is, the address of the offset, plus its
10331 size, since the offset is always the last part of the insn. */
10334 md_pcrel_from (fixS
*fixP
)
10336 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10342 s_bss (int ignore ATTRIBUTE_UNUSED
)
10346 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10348 obj_elf_section_change_hook ();
10350 temp
= get_absolute_expression ();
10351 subseg_set (bss_section
, (subsegT
) temp
);
10352 demand_empty_rest_of_line ();
10358 i386_validate_fix (fixS
*fixp
)
10360 if (fixp
->fx_subsy
)
10362 if (fixp
->fx_subsy
== GOT_symbol
)
10364 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10368 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10369 if (fixp
->fx_tcbit2
)
10370 fixp
->fx_r_type
= (fixp
->fx_tcbit
10371 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10372 : BFD_RELOC_X86_64_GOTPCRELX
);
10375 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10380 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10382 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10384 fixp
->fx_subsy
= 0;
10387 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10388 else if (!object_64bit
)
10390 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10391 && fixp
->fx_tcbit2
)
10392 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10398 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10401 bfd_reloc_code_real_type code
;
10403 switch (fixp
->fx_r_type
)
10405 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10406 case BFD_RELOC_SIZE32
:
10407 case BFD_RELOC_SIZE64
:
10408 if (S_IS_DEFINED (fixp
->fx_addsy
)
10409 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10411 /* Resolve size relocation against local symbol to size of
10412 the symbol plus addend. */
10413 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10414 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10415 && !fits_in_unsigned_long (value
))
10416 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10417 _("symbol size computation overflow"));
10418 fixp
->fx_addsy
= NULL
;
10419 fixp
->fx_subsy
= NULL
;
10420 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10425 case BFD_RELOC_X86_64_PLT32
:
10426 case BFD_RELOC_X86_64_GOT32
:
10427 case BFD_RELOC_X86_64_GOTPCREL
:
10428 case BFD_RELOC_X86_64_GOTPCRELX
:
10429 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10430 case BFD_RELOC_386_PLT32
:
10431 case BFD_RELOC_386_GOT32
:
10432 case BFD_RELOC_386_GOT32X
:
10433 case BFD_RELOC_386_GOTOFF
:
10434 case BFD_RELOC_386_GOTPC
:
10435 case BFD_RELOC_386_TLS_GD
:
10436 case BFD_RELOC_386_TLS_LDM
:
10437 case BFD_RELOC_386_TLS_LDO_32
:
10438 case BFD_RELOC_386_TLS_IE_32
:
10439 case BFD_RELOC_386_TLS_IE
:
10440 case BFD_RELOC_386_TLS_GOTIE
:
10441 case BFD_RELOC_386_TLS_LE_32
:
10442 case BFD_RELOC_386_TLS_LE
:
10443 case BFD_RELOC_386_TLS_GOTDESC
:
10444 case BFD_RELOC_386_TLS_DESC_CALL
:
10445 case BFD_RELOC_X86_64_TLSGD
:
10446 case BFD_RELOC_X86_64_TLSLD
:
10447 case BFD_RELOC_X86_64_DTPOFF32
:
10448 case BFD_RELOC_X86_64_DTPOFF64
:
10449 case BFD_RELOC_X86_64_GOTTPOFF
:
10450 case BFD_RELOC_X86_64_TPOFF32
:
10451 case BFD_RELOC_X86_64_TPOFF64
:
10452 case BFD_RELOC_X86_64_GOTOFF64
:
10453 case BFD_RELOC_X86_64_GOTPC32
:
10454 case BFD_RELOC_X86_64_GOT64
:
10455 case BFD_RELOC_X86_64_GOTPCREL64
:
10456 case BFD_RELOC_X86_64_GOTPC64
:
10457 case BFD_RELOC_X86_64_GOTPLT64
:
10458 case BFD_RELOC_X86_64_PLTOFF64
:
10459 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10460 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10461 case BFD_RELOC_RVA
:
10462 case BFD_RELOC_VTABLE_ENTRY
:
10463 case BFD_RELOC_VTABLE_INHERIT
:
10465 case BFD_RELOC_32_SECREL
:
10467 code
= fixp
->fx_r_type
;
10469 case BFD_RELOC_X86_64_32S
:
10470 if (!fixp
->fx_pcrel
)
10472 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10473 code
= fixp
->fx_r_type
;
10477 if (fixp
->fx_pcrel
)
10479 switch (fixp
->fx_size
)
10482 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10483 _("can not do %d byte pc-relative relocation"),
10485 code
= BFD_RELOC_32_PCREL
;
10487 case 1: code
= BFD_RELOC_8_PCREL
; break;
10488 case 2: code
= BFD_RELOC_16_PCREL
; break;
10489 case 4: code
= BFD_RELOC_32_PCREL
; break;
10491 case 8: code
= BFD_RELOC_64_PCREL
; break;
10497 switch (fixp
->fx_size
)
10500 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10501 _("can not do %d byte relocation"),
10503 code
= BFD_RELOC_32
;
10505 case 1: code
= BFD_RELOC_8
; break;
10506 case 2: code
= BFD_RELOC_16
; break;
10507 case 4: code
= BFD_RELOC_32
; break;
10509 case 8: code
= BFD_RELOC_64
; break;
10516 if ((code
== BFD_RELOC_32
10517 || code
== BFD_RELOC_32_PCREL
10518 || code
== BFD_RELOC_X86_64_32S
)
10520 && fixp
->fx_addsy
== GOT_symbol
)
10523 code
= BFD_RELOC_386_GOTPC
;
10525 code
= BFD_RELOC_X86_64_GOTPC32
;
10527 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10529 && fixp
->fx_addsy
== GOT_symbol
)
10531 code
= BFD_RELOC_X86_64_GOTPC64
;
10534 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10535 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10536 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10538 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10540 if (!use_rela_relocations
)
10542 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10543 vtable entry to be used in the relocation's section offset. */
10544 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10545 rel
->address
= fixp
->fx_offset
;
10546 #if defined (OBJ_COFF) && defined (TE_PE)
10547 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10548 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10553 /* Use the rela in 64bit mode. */
10556 if (disallow_64bit_reloc
)
10559 case BFD_RELOC_X86_64_DTPOFF64
:
10560 case BFD_RELOC_X86_64_TPOFF64
:
10561 case BFD_RELOC_64_PCREL
:
10562 case BFD_RELOC_X86_64_GOTOFF64
:
10563 case BFD_RELOC_X86_64_GOT64
:
10564 case BFD_RELOC_X86_64_GOTPCREL64
:
10565 case BFD_RELOC_X86_64_GOTPC64
:
10566 case BFD_RELOC_X86_64_GOTPLT64
:
10567 case BFD_RELOC_X86_64_PLTOFF64
:
10568 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10569 _("cannot represent relocation type %s in x32 mode"),
10570 bfd_get_reloc_code_name (code
));
10576 if (!fixp
->fx_pcrel
)
10577 rel
->addend
= fixp
->fx_offset
;
10581 case BFD_RELOC_X86_64_PLT32
:
10582 case BFD_RELOC_X86_64_GOT32
:
10583 case BFD_RELOC_X86_64_GOTPCREL
:
10584 case BFD_RELOC_X86_64_GOTPCRELX
:
10585 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10586 case BFD_RELOC_X86_64_TLSGD
:
10587 case BFD_RELOC_X86_64_TLSLD
:
10588 case BFD_RELOC_X86_64_GOTTPOFF
:
10589 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10590 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10591 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10594 rel
->addend
= (section
->vma
10596 + fixp
->fx_addnumber
10597 + md_pcrel_from (fixp
));
10602 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10603 if (rel
->howto
== NULL
)
10605 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10606 _("cannot represent relocation type %s"),
10607 bfd_get_reloc_code_name (code
));
10608 /* Set howto to a garbage value so that we can keep going. */
10609 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10610 gas_assert (rel
->howto
!= NULL
);
10616 #include "tc-i386-intel.c"
10619 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10621 int saved_naked_reg
;
10622 char saved_register_dot
;
10624 saved_naked_reg
= allow_naked_reg
;
10625 allow_naked_reg
= 1;
10626 saved_register_dot
= register_chars
['.'];
10627 register_chars
['.'] = '.';
10628 allow_pseudo_reg
= 1;
10629 expression_and_evaluate (exp
);
10630 allow_pseudo_reg
= 0;
10631 register_chars
['.'] = saved_register_dot
;
10632 allow_naked_reg
= saved_naked_reg
;
10634 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10636 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10638 exp
->X_op
= O_constant
;
10639 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10640 .dw2_regnum
[flag_code
>> 1];
10643 exp
->X_op
= O_illegal
;
10648 tc_x86_frame_initial_instructions (void)
10650 static unsigned int sp_regno
[2];
10652 if (!sp_regno
[flag_code
>> 1])
10654 char *saved_input
= input_line_pointer
;
10655 char sp
[][4] = {"esp", "rsp"};
10658 input_line_pointer
= sp
[flag_code
>> 1];
10659 tc_x86_parse_to_dw2regnum (&exp
);
10660 gas_assert (exp
.X_op
== O_constant
);
10661 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10662 input_line_pointer
= saved_input
;
10665 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10666 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10670 x86_dwarf2_addr_size (void)
10672 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10673 if (x86_elf_abi
== X86_64_X32_ABI
)
10676 return bfd_arch_bits_per_address (stdoutput
) / 8;
10680 i386_elf_section_type (const char *str
, size_t len
)
10682 if (flag_code
== CODE_64BIT
10683 && len
== sizeof ("unwind") - 1
10684 && strncmp (str
, "unwind", 6) == 0)
10685 return SHT_X86_64_UNWIND
;
10692 i386_solaris_fix_up_eh_frame (segT sec
)
10694 if (flag_code
== CODE_64BIT
)
10695 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10701 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10705 exp
.X_op
= O_secrel
;
10706 exp
.X_add_symbol
= symbol
;
10707 exp
.X_add_number
= 0;
10708 emit_expr (&exp
, size
);
10712 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10713 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10716 x86_64_section_letter (int letter
, char **ptr_msg
)
10718 if (flag_code
== CODE_64BIT
)
10721 return SHF_X86_64_LARGE
;
10723 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10726 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10731 x86_64_section_word (char *str
, size_t len
)
10733 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10734 return SHF_X86_64_LARGE
;
10740 handle_large_common (int small ATTRIBUTE_UNUSED
)
10742 if (flag_code
!= CODE_64BIT
)
10744 s_comm_internal (0, elf_common_parse
);
10745 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10749 static segT lbss_section
;
10750 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10751 asection
*saved_bss_section
= bss_section
;
10753 if (lbss_section
== NULL
)
10755 flagword applicable
;
10756 segT seg
= now_seg
;
10757 subsegT subseg
= now_subseg
;
10759 /* The .lbss section is for local .largecomm symbols. */
10760 lbss_section
= subseg_new (".lbss", 0);
10761 applicable
= bfd_applicable_section_flags (stdoutput
);
10762 bfd_set_section_flags (stdoutput
, lbss_section
,
10763 applicable
& SEC_ALLOC
);
10764 seg_info (lbss_section
)->bss
= 1;
10766 subseg_set (seg
, subseg
);
10769 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10770 bss_section
= lbss_section
;
10772 s_comm_internal (0, elf_common_parse
);
10774 elf_com_section_ptr
= saved_com_section_ptr
;
10775 bss_section
= saved_bss_section
;
10778 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */